1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 31 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 32 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 33 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 34 35 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 36 { 37 struct ixgbe_mac_info *mac = &hw->mac; 38 struct ixgbe_phy_info *phy = &hw->phy; 39 struct ixgbe_link_info *link = &hw->link; 40 41 /* Start with X540 invariants, since so simular */ 42 ixgbe_get_invariants_X540(hw); 43 44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 45 phy->ops.set_phy_power = NULL; 46 47 link->addr = IXGBE_CS4227; 48 49 return 0; 50 } 51 52 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 53 { 54 struct ixgbe_phy_info *phy = &hw->phy; 55 56 /* Start with X540 invariants, since so similar */ 57 ixgbe_get_invariants_X540(hw); 58 59 phy->ops.set_phy_power = NULL; 60 61 return 0; 62 } 63 64 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 65 { 66 struct ixgbe_mac_info *mac = &hw->mac; 67 struct ixgbe_phy_info *phy = &hw->phy; 68 69 /* Start with X540 invariants, since so simular */ 70 ixgbe_get_invariants_X540(hw); 71 72 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 73 phy->ops.set_phy_power = NULL; 74 75 return 0; 76 } 77 78 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 79 { 80 struct ixgbe_phy_info *phy = &hw->phy; 81 82 /* Start with X540 invariants, since so similar */ 83 ixgbe_get_invariants_X540(hw); 84 85 phy->ops.set_phy_power = NULL; 86 87 return 0; 88 } 89 90 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 91 * @hw: pointer to hardware structure 92 **/ 93 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 94 { 95 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 96 97 if (hw->bus.lan_id) { 98 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 99 esdp |= IXGBE_ESDP_SDP1_DIR; 100 } 101 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 103 IXGBE_WRITE_FLUSH(hw); 104 } 105 106 /** 107 * ixgbe_read_cs4227 - Read CS4227 register 108 * @hw: pointer to hardware structure 109 * @reg: register number to write 110 * @value: pointer to receive value read 111 * 112 * Returns status code 113 */ 114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 115 { 116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 117 } 118 119 /** 120 * ixgbe_write_cs4227 - Write CS4227 register 121 * @hw: pointer to hardware structure 122 * @reg: register number to write 123 * @value: value to write to register 124 * 125 * Returns status code 126 */ 127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 128 { 129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 130 } 131 132 /** 133 * ixgbe_read_pe - Read register from port expander 134 * @hw: pointer to hardware structure 135 * @reg: register number to read 136 * @value: pointer to receive read value 137 * 138 * Returns status code 139 */ 140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 141 { 142 s32 status; 143 144 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 145 if (status) 146 hw_err(hw, "port expander access failed with %d\n", status); 147 return status; 148 } 149 150 /** 151 * ixgbe_write_pe - Write register to port expander 152 * @hw: pointer to hardware structure 153 * @reg: register number to write 154 * @value: value to write 155 * 156 * Returns status code 157 */ 158 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 159 { 160 s32 status; 161 162 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 163 value); 164 if (status) 165 hw_err(hw, "port expander access failed with %d\n", status); 166 return status; 167 } 168 169 /** 170 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 171 * @hw: pointer to hardware structure 172 * 173 * This function assumes that the caller has acquired the proper semaphore. 174 * Returns error code 175 */ 176 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 177 { 178 s32 status; 179 u32 retry; 180 u16 value; 181 u8 reg; 182 183 /* Trigger hard reset. */ 184 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 185 if (status) 186 return status; 187 reg |= IXGBE_PE_BIT1; 188 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 189 if (status) 190 return status; 191 192 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 193 if (status) 194 return status; 195 reg &= ~IXGBE_PE_BIT1; 196 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 197 if (status) 198 return status; 199 200 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 201 if (status) 202 return status; 203 reg &= ~IXGBE_PE_BIT1; 204 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 205 if (status) 206 return status; 207 208 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 209 210 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 211 if (status) 212 return status; 213 reg |= IXGBE_PE_BIT1; 214 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 215 if (status) 216 return status; 217 218 /* Wait for the reset to complete. */ 219 msleep(IXGBE_CS4227_RESET_DELAY); 220 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 222 &value); 223 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 224 break; 225 msleep(IXGBE_CS4227_CHECK_DELAY); 226 } 227 if (retry == IXGBE_CS4227_RETRIES) { 228 hw_err(hw, "CS4227 reset did not complete\n"); 229 return IXGBE_ERR_PHY; 230 } 231 232 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 233 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 234 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 235 return IXGBE_ERR_PHY; 236 } 237 238 return 0; 239 } 240 241 /** 242 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 243 * @hw: pointer to hardware structure 244 */ 245 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 246 { 247 u32 swfw_mask = hw->phy.phy_semaphore_mask; 248 s32 status; 249 u16 value; 250 u8 retry; 251 252 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 253 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 254 if (status) { 255 hw_err(hw, "semaphore failed with %d\n", status); 256 msleep(IXGBE_CS4227_CHECK_DELAY); 257 continue; 258 } 259 260 /* Get status of reset flow. */ 261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 262 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 263 goto out; 264 265 if (status || value != IXGBE_CS4227_RESET_PENDING) 266 break; 267 268 /* Reset is pending. Wait and check again. */ 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 msleep(IXGBE_CS4227_CHECK_DELAY); 271 } 272 /* If still pending, assume other instance failed. */ 273 if (retry == IXGBE_CS4227_RETRIES) { 274 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 275 if (status) { 276 hw_err(hw, "semaphore failed with %d\n", status); 277 return; 278 } 279 } 280 281 /* Reset the CS4227. */ 282 status = ixgbe_reset_cs4227(hw); 283 if (status) { 284 hw_err(hw, "CS4227 reset failed: %d", status); 285 goto out; 286 } 287 288 /* Reset takes so long, temporarily release semaphore in case the 289 * other driver instance is waiting for the reset indication. 290 */ 291 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 292 IXGBE_CS4227_RESET_PENDING); 293 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 294 usleep_range(10000, 12000); 295 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 296 if (status) { 297 hw_err(hw, "semaphore failed with %d", status); 298 return; 299 } 300 301 /* Record completion for next time. */ 302 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 303 IXGBE_CS4227_RESET_COMPLETE); 304 305 out: 306 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 307 msleep(hw->eeprom.semaphore_delay); 308 } 309 310 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 311 * @hw: pointer to hardware structure 312 * 313 * Returns error code 314 */ 315 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 316 { 317 switch (hw->device_id) { 318 case IXGBE_DEV_ID_X550EM_A_SFP: 319 if (hw->bus.lan_id) 320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 321 else 322 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 323 return ixgbe_identify_module_generic(hw); 324 case IXGBE_DEV_ID_X550EM_X_SFP: 325 /* set up for CS4227 usage */ 326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 327 ixgbe_setup_mux_ctl(hw); 328 ixgbe_check_cs4227(hw); 329 /* Fallthrough */ 330 case IXGBE_DEV_ID_X550EM_A_SFP_N: 331 return ixgbe_identify_module_generic(hw); 332 case IXGBE_DEV_ID_X550EM_X_KX4: 333 hw->phy.type = ixgbe_phy_x550em_kx4; 334 break; 335 case IXGBE_DEV_ID_X550EM_X_XFI: 336 hw->phy.type = ixgbe_phy_x550em_xfi; 337 break; 338 case IXGBE_DEV_ID_X550EM_X_KR: 339 case IXGBE_DEV_ID_X550EM_A_KR: 340 case IXGBE_DEV_ID_X550EM_A_KR_L: 341 hw->phy.type = ixgbe_phy_x550em_kr; 342 break; 343 case IXGBE_DEV_ID_X550EM_A_10G_T: 344 if (hw->bus.lan_id) 345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 346 else 347 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 348 /* Fallthrough */ 349 case IXGBE_DEV_ID_X550EM_X_10G_T: 350 return ixgbe_identify_phy_generic(hw); 351 case IXGBE_DEV_ID_X550EM_X_1G_T: 352 hw->phy.type = ixgbe_phy_ext_1g_t; 353 break; 354 case IXGBE_DEV_ID_X550EM_A_1G_T: 355 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 356 hw->phy.type = ixgbe_phy_fw; 357 hw->phy.ops.read_reg = NULL; 358 hw->phy.ops.write_reg = NULL; 359 if (hw->bus.lan_id) 360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 361 else 362 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 363 break; 364 default: 365 break; 366 } 367 return 0; 368 } 369 370 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 371 u32 device_type, u16 *phy_data) 372 { 373 return IXGBE_NOT_IMPLEMENTED; 374 } 375 376 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 377 u32 device_type, u16 phy_data) 378 { 379 return IXGBE_NOT_IMPLEMENTED; 380 } 381 382 /** 383 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 384 * @hw: pointer to the hardware structure 385 * @addr: I2C bus address to read from 386 * @reg: I2C device register to read from 387 * @val: pointer to location to receive read value 388 * 389 * Returns an error code on error. 390 **/ 391 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 392 u16 reg, u16 *val) 393 { 394 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 395 } 396 397 /** 398 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 399 * @hw: pointer to the hardware structure 400 * @addr: I2C bus address to read from 401 * @reg: I2C device register to read from 402 * @val: pointer to location to receive read value 403 * 404 * Returns an error code on error. 405 **/ 406 static s32 407 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 408 u16 reg, u16 *val) 409 { 410 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 411 } 412 413 /** 414 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 415 * @hw: pointer to the hardware structure 416 * @addr: I2C bus address to write to 417 * @reg: I2C device register to write to 418 * @val: value to write 419 * 420 * Returns an error code on error. 421 **/ 422 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 423 u8 addr, u16 reg, u16 val) 424 { 425 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 426 } 427 428 /** 429 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 430 * @hw: pointer to the hardware structure 431 * @addr: I2C bus address to write to 432 * @reg: I2C device register to write to 433 * @val: value to write 434 * 435 * Returns an error code on error. 436 **/ 437 static s32 438 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 439 u8 addr, u16 reg, u16 val) 440 { 441 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 442 } 443 444 /** 445 * ixgbe_fw_phy_activity - Perform an activity on a PHY 446 * @hw: pointer to hardware structure 447 * @activity: activity to perform 448 * @data: Pointer to 4 32-bit words of data 449 */ 450 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 451 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 452 { 453 union { 454 struct ixgbe_hic_phy_activity_req cmd; 455 struct ixgbe_hic_phy_activity_resp rsp; 456 } hic; 457 u16 retries = FW_PHY_ACT_RETRIES; 458 s32 rc; 459 u32 i; 460 461 do { 462 memset(&hic, 0, sizeof(hic)); 463 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 464 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 465 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 466 hic.cmd.port_number = hw->bus.lan_id; 467 hic.cmd.activity_id = cpu_to_le16(activity); 468 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 469 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 470 471 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 472 IXGBE_HI_COMMAND_TIMEOUT, 473 true); 474 if (rc) 475 return rc; 476 if (hic.rsp.hdr.cmd_or_resp.ret_status == 477 FW_CEM_RESP_STATUS_SUCCESS) { 478 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 479 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 480 return 0; 481 } 482 usleep_range(20, 30); 483 --retries; 484 } while (retries > 0); 485 486 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 487 } 488 489 static const struct { 490 u16 fw_speed; 491 ixgbe_link_speed phy_speed; 492 } ixgbe_fw_map[] = { 493 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 494 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 495 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 496 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 497 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 498 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 499 }; 500 501 /** 502 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 503 * @hw: pointer to hardware structure 504 * 505 * Returns error code 506 */ 507 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 508 { 509 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 510 u16 phy_speeds; 511 u16 phy_id_lo; 512 s32 rc; 513 u16 i; 514 515 if (hw->phy.id) 516 return 0; 517 518 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 519 if (rc) 520 return rc; 521 522 hw->phy.speeds_supported = 0; 523 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 524 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 525 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 526 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 527 } 528 529 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 530 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 531 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 532 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 533 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 534 return IXGBE_ERR_PHY_ADDR_INVALID; 535 536 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 537 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 538 IXGBE_LINK_SPEED_1GB_FULL; 539 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 540 return 0; 541 } 542 543 /** 544 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 545 * @hw: pointer to hardware structure 546 * 547 * Returns error code 548 */ 549 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 550 { 551 if (hw->bus.lan_id) 552 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 553 else 554 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 555 556 hw->phy.type = ixgbe_phy_fw; 557 hw->phy.ops.read_reg = NULL; 558 hw->phy.ops.write_reg = NULL; 559 return ixgbe_get_phy_id_fw(hw); 560 } 561 562 /** 563 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 564 * @hw: pointer to hardware structure 565 * 566 * Returns error code 567 */ 568 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 569 { 570 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 571 572 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 573 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 574 } 575 576 /** 577 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 578 * @hw: pointer to hardware structure 579 */ 580 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 581 { 582 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 583 s32 rc; 584 u16 i; 585 586 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 587 return 0; 588 589 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 590 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 591 return IXGBE_ERR_INVALID_LINK_SETTINGS; 592 } 593 594 switch (hw->fc.requested_mode) { 595 case ixgbe_fc_full: 596 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 597 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 598 break; 599 case ixgbe_fc_rx_pause: 600 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 601 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 602 break; 603 case ixgbe_fc_tx_pause: 604 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 605 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 606 break; 607 default: 608 break; 609 } 610 611 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 612 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 613 setup[0] |= ixgbe_fw_map[i].fw_speed; 614 } 615 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 616 617 if (hw->phy.eee_speeds_advertised) 618 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 619 620 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 621 if (rc) 622 return rc; 623 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 624 return IXGBE_ERR_OVERTEMP; 625 return 0; 626 } 627 628 /** 629 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 630 * @hw: pointer to hardware structure 631 * 632 * Called at init time to set up flow control. 633 */ 634 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 635 { 636 if (hw->fc.requested_mode == ixgbe_fc_default) 637 hw->fc.requested_mode = ixgbe_fc_full; 638 639 return ixgbe_setup_fw_link(hw); 640 } 641 642 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 643 * @hw: pointer to hardware structure 644 * 645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 646 * ixgbe_hw struct in order to set up EEPROM access. 647 **/ 648 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 649 { 650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 651 u32 eec; 652 u16 eeprom_size; 653 654 if (eeprom->type == ixgbe_eeprom_uninitialized) { 655 eeprom->semaphore_delay = 10; 656 eeprom->type = ixgbe_flash; 657 658 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 659 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 660 IXGBE_EEC_SIZE_SHIFT); 661 eeprom->word_size = BIT(eeprom_size + 662 IXGBE_EEPROM_WORD_SIZE_SHIFT); 663 664 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 665 eeprom->type, eeprom->word_size); 666 } 667 668 return 0; 669 } 670 671 /** 672 * ixgbe_iosf_wait - Wait for IOSF command completion 673 * @hw: pointer to hardware structure 674 * @ctrl: pointer to location to receive final IOSF control value 675 * 676 * Return: failing status on timeout 677 * 678 * Note: ctrl can be NULL if the IOSF control register value is not needed 679 */ 680 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 681 { 682 u32 i, command; 683 684 /* Check every 10 usec to see if the address cycle completed. 685 * The SB IOSF BUSY bit will clear when the operation is 686 * complete. 687 */ 688 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 689 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 690 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 691 break; 692 udelay(10); 693 } 694 if (ctrl) 695 *ctrl = command; 696 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 697 hw_dbg(hw, "IOSF wait timed out\n"); 698 return IXGBE_ERR_PHY; 699 } 700 701 return 0; 702 } 703 704 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 705 * IOSF device 706 * @hw: pointer to hardware structure 707 * @reg_addr: 32 bit PHY register to write 708 * @device_type: 3 bit device type 709 * @phy_data: Pointer to read data from the register 710 **/ 711 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 712 u32 device_type, u32 *data) 713 { 714 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 715 u32 command, error; 716 s32 ret; 717 718 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 719 if (ret) 720 return ret; 721 722 ret = ixgbe_iosf_wait(hw, NULL); 723 if (ret) 724 goto out; 725 726 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 727 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 728 729 /* Write IOSF control register */ 730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 731 732 ret = ixgbe_iosf_wait(hw, &command); 733 734 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 735 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 736 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 737 hw_dbg(hw, "Failed to read, error %x\n", error); 738 return IXGBE_ERR_PHY; 739 } 740 741 if (!ret) 742 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 743 744 out: 745 hw->mac.ops.release_swfw_sync(hw, gssr); 746 return ret; 747 } 748 749 /** 750 * ixgbe_get_phy_token - Get the token for shared PHY access 751 * @hw: Pointer to hardware structure 752 */ 753 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 754 { 755 struct ixgbe_hic_phy_token_req token_cmd; 756 s32 status; 757 758 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 759 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 760 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 761 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 762 token_cmd.port_number = hw->bus.lan_id; 763 token_cmd.command_type = FW_PHY_TOKEN_REQ; 764 token_cmd.pad = 0; 765 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 766 IXGBE_HI_COMMAND_TIMEOUT, 767 true); 768 if (status) 769 return status; 770 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 771 return 0; 772 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 773 return IXGBE_ERR_FW_RESP_INVALID; 774 775 return IXGBE_ERR_TOKEN_RETRY; 776 } 777 778 /** 779 * ixgbe_put_phy_token - Put the token for shared PHY access 780 * @hw: Pointer to hardware structure 781 */ 782 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 783 { 784 struct ixgbe_hic_phy_token_req token_cmd; 785 s32 status; 786 787 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 788 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 789 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 790 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 791 token_cmd.port_number = hw->bus.lan_id; 792 token_cmd.command_type = FW_PHY_TOKEN_REL; 793 token_cmd.pad = 0; 794 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 795 IXGBE_HI_COMMAND_TIMEOUT, 796 true); 797 if (status) 798 return status; 799 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 800 return 0; 801 return IXGBE_ERR_FW_RESP_INVALID; 802 } 803 804 /** 805 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 806 * @hw: pointer to hardware structure 807 * @reg_addr: 32 bit PHY register to write 808 * @device_type: 3 bit device type 809 * @data: Data to write to the register 810 **/ 811 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 812 __always_unused u32 device_type, 813 u32 data) 814 { 815 struct ixgbe_hic_internal_phy_req write_cmd; 816 817 memset(&write_cmd, 0, sizeof(write_cmd)); 818 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 819 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 820 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 821 write_cmd.port_number = hw->bus.lan_id; 822 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 823 write_cmd.address = cpu_to_be16(reg_addr); 824 write_cmd.write_data = cpu_to_be32(data); 825 826 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 827 IXGBE_HI_COMMAND_TIMEOUT, false); 828 } 829 830 /** 831 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 832 * @hw: pointer to hardware structure 833 * @reg_addr: 32 bit PHY register to write 834 * @device_type: 3 bit device type 835 * @data: Pointer to read data from the register 836 **/ 837 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 838 __always_unused u32 device_type, 839 u32 *data) 840 { 841 union { 842 struct ixgbe_hic_internal_phy_req cmd; 843 struct ixgbe_hic_internal_phy_resp rsp; 844 } hic; 845 s32 status; 846 847 memset(&hic, 0, sizeof(hic)); 848 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 849 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 850 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 851 hic.cmd.port_number = hw->bus.lan_id; 852 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 853 hic.cmd.address = cpu_to_be16(reg_addr); 854 855 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 856 IXGBE_HI_COMMAND_TIMEOUT, true); 857 858 /* Extract the register value from the response. */ 859 *data = be32_to_cpu(hic.rsp.read_data); 860 861 return status; 862 } 863 864 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 865 * @hw: pointer to hardware structure 866 * @offset: offset of word in the EEPROM to read 867 * @words: number of words 868 * @data: word(s) read from the EEPROM 869 * 870 * Reads a 16 bit word(s) from the EEPROM using the hostif. 871 **/ 872 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 873 u16 offset, u16 words, u16 *data) 874 { 875 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 876 struct ixgbe_hic_read_shadow_ram buffer; 877 u32 current_word = 0; 878 u16 words_to_read; 879 s32 status; 880 u32 i; 881 882 /* Take semaphore for the entire operation. */ 883 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 884 if (status) { 885 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 886 return status; 887 } 888 889 while (words) { 890 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 891 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 892 else 893 words_to_read = words; 894 895 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 896 buffer.hdr.req.buf_lenh = 0; 897 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 898 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 899 900 /* convert offset from words to bytes */ 901 buffer.address = cpu_to_be32((offset + current_word) * 2); 902 buffer.length = cpu_to_be16(words_to_read * 2); 903 buffer.pad2 = 0; 904 buffer.pad3 = 0; 905 906 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 907 IXGBE_HI_COMMAND_TIMEOUT); 908 if (status) { 909 hw_dbg(hw, "Host interface command failed\n"); 910 goto out; 911 } 912 913 for (i = 0; i < words_to_read; i++) { 914 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 915 2 * i; 916 u32 value = IXGBE_READ_REG(hw, reg); 917 918 data[current_word] = (u16)(value & 0xffff); 919 current_word++; 920 i++; 921 if (i < words_to_read) { 922 value >>= 16; 923 data[current_word] = (u16)(value & 0xffff); 924 current_word++; 925 } 926 } 927 words -= words_to_read; 928 } 929 930 out: 931 hw->mac.ops.release_swfw_sync(hw, mask); 932 return status; 933 } 934 935 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 936 * @hw: pointer to hardware structure 937 * @ptr: pointer offset in eeprom 938 * @size: size of section pointed by ptr, if 0 first word will be used as size 939 * @csum: address of checksum to update 940 * 941 * Returns error status for any failure 942 **/ 943 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 944 u16 size, u16 *csum, u16 *buffer, 945 u32 buffer_size) 946 { 947 u16 buf[256]; 948 s32 status; 949 u16 length, bufsz, i, start; 950 u16 *local_buffer; 951 952 bufsz = ARRAY_SIZE(buf); 953 954 /* Read a chunk at the pointer location */ 955 if (!buffer) { 956 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 957 if (status) { 958 hw_dbg(hw, "Failed to read EEPROM image\n"); 959 return status; 960 } 961 local_buffer = buf; 962 } else { 963 if (buffer_size < ptr) 964 return IXGBE_ERR_PARAM; 965 local_buffer = &buffer[ptr]; 966 } 967 968 if (size) { 969 start = 0; 970 length = size; 971 } else { 972 start = 1; 973 length = local_buffer[0]; 974 975 /* Skip pointer section if length is invalid. */ 976 if (length == 0xFFFF || length == 0 || 977 (ptr + length) >= hw->eeprom.word_size) 978 return 0; 979 } 980 981 if (buffer && ((u32)start + (u32)length > buffer_size)) 982 return IXGBE_ERR_PARAM; 983 984 for (i = start; length; i++, length--) { 985 if (i == bufsz && !buffer) { 986 ptr += bufsz; 987 i = 0; 988 if (length < bufsz) 989 bufsz = length; 990 991 /* Read a chunk at the pointer location */ 992 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 993 bufsz, buf); 994 if (status) { 995 hw_dbg(hw, "Failed to read EEPROM image\n"); 996 return status; 997 } 998 } 999 *csum += local_buffer[i]; 1000 } 1001 return 0; 1002 } 1003 1004 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 1005 * @hw: pointer to hardware structure 1006 * @buffer: pointer to buffer containing calculated checksum 1007 * @buffer_size: size of buffer 1008 * 1009 * Returns a negative error code on error, or the 16-bit checksum 1010 **/ 1011 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 1012 u32 buffer_size) 1013 { 1014 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 1015 u16 *local_buffer; 1016 s32 status; 1017 u16 checksum = 0; 1018 u16 pointer, i, size; 1019 1020 hw->eeprom.ops.init_params(hw); 1021 1022 if (!buffer) { 1023 /* Read pointer area */ 1024 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1025 IXGBE_EEPROM_LAST_WORD + 1, 1026 eeprom_ptrs); 1027 if (status) { 1028 hw_dbg(hw, "Failed to read EEPROM image\n"); 1029 return status; 1030 } 1031 local_buffer = eeprom_ptrs; 1032 } else { 1033 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1034 return IXGBE_ERR_PARAM; 1035 local_buffer = buffer; 1036 } 1037 1038 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1039 * checksum word itself 1040 */ 1041 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1042 if (i != IXGBE_EEPROM_CHECKSUM) 1043 checksum += local_buffer[i]; 1044 1045 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1046 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1047 */ 1048 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1049 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1050 continue; 1051 1052 pointer = local_buffer[i]; 1053 1054 /* Skip pointer section if the pointer is invalid. */ 1055 if (pointer == 0xFFFF || pointer == 0 || 1056 pointer >= hw->eeprom.word_size) 1057 continue; 1058 1059 switch (i) { 1060 case IXGBE_PCIE_GENERAL_PTR: 1061 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1062 break; 1063 case IXGBE_PCIE_CONFIG0_PTR: 1064 case IXGBE_PCIE_CONFIG1_PTR: 1065 size = IXGBE_PCIE_CONFIG_SIZE; 1066 break; 1067 default: 1068 size = 0; 1069 break; 1070 } 1071 1072 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1073 buffer, buffer_size); 1074 if (status) 1075 return status; 1076 } 1077 1078 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1079 1080 return (s32)checksum; 1081 } 1082 1083 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1084 * @hw: pointer to hardware structure 1085 * 1086 * Returns a negative error code on error, or the 16-bit checksum 1087 **/ 1088 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1089 { 1090 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1091 } 1092 1093 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1094 * @hw: pointer to hardware structure 1095 * @offset: offset of word in the EEPROM to read 1096 * @data: word read from the EEPROM 1097 * 1098 * Reads a 16 bit word from the EEPROM using the hostif. 1099 **/ 1100 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1101 { 1102 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1103 struct ixgbe_hic_read_shadow_ram buffer; 1104 s32 status; 1105 1106 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1107 buffer.hdr.req.buf_lenh = 0; 1108 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1109 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1110 1111 /* convert offset from words to bytes */ 1112 buffer.address = cpu_to_be32(offset * 2); 1113 /* one word */ 1114 buffer.length = cpu_to_be16(sizeof(u16)); 1115 1116 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1117 if (status) 1118 return status; 1119 1120 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1121 IXGBE_HI_COMMAND_TIMEOUT); 1122 if (!status) { 1123 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1124 FW_NVM_DATA_OFFSET); 1125 } 1126 1127 hw->mac.ops.release_swfw_sync(hw, mask); 1128 return status; 1129 } 1130 1131 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1132 * @hw: pointer to hardware structure 1133 * @checksum_val: calculated checksum 1134 * 1135 * Performs checksum calculation and validates the EEPROM checksum. If the 1136 * caller does not need checksum_val, the value can be NULL. 1137 **/ 1138 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1139 u16 *checksum_val) 1140 { 1141 s32 status; 1142 u16 checksum; 1143 u16 read_checksum = 0; 1144 1145 /* Read the first word from the EEPROM. If this times out or fails, do 1146 * not continue or we could be in for a very long wait while every 1147 * EEPROM read fails 1148 */ 1149 status = hw->eeprom.ops.read(hw, 0, &checksum); 1150 if (status) { 1151 hw_dbg(hw, "EEPROM read failed\n"); 1152 return status; 1153 } 1154 1155 status = hw->eeprom.ops.calc_checksum(hw); 1156 if (status < 0) 1157 return status; 1158 1159 checksum = (u16)(status & 0xffff); 1160 1161 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1162 &read_checksum); 1163 if (status) 1164 return status; 1165 1166 /* Verify read checksum from EEPROM is the same as 1167 * calculated checksum 1168 */ 1169 if (read_checksum != checksum) { 1170 status = IXGBE_ERR_EEPROM_CHECKSUM; 1171 hw_dbg(hw, "Invalid EEPROM checksum"); 1172 } 1173 1174 /* If the user cares, return the calculated checksum */ 1175 if (checksum_val) 1176 *checksum_val = checksum; 1177 1178 return status; 1179 } 1180 1181 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1182 * @hw: pointer to hardware structure 1183 * @offset: offset of word in the EEPROM to write 1184 * @data: word write to the EEPROM 1185 * 1186 * Write a 16 bit word to the EEPROM using the hostif. 1187 **/ 1188 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1189 u16 data) 1190 { 1191 s32 status; 1192 struct ixgbe_hic_write_shadow_ram buffer; 1193 1194 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1195 buffer.hdr.req.buf_lenh = 0; 1196 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1197 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1198 1199 /* one word */ 1200 buffer.length = cpu_to_be16(sizeof(u16)); 1201 buffer.data = data; 1202 buffer.address = cpu_to_be32(offset * 2); 1203 1204 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1205 IXGBE_HI_COMMAND_TIMEOUT, false); 1206 return status; 1207 } 1208 1209 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1210 * @hw: pointer to hardware structure 1211 * @offset: offset of word in the EEPROM to write 1212 * @data: word write to the EEPROM 1213 * 1214 * Write a 16 bit word to the EEPROM using the hostif. 1215 **/ 1216 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1217 { 1218 s32 status = 0; 1219 1220 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1221 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1222 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1223 } else { 1224 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1225 status = IXGBE_ERR_SWFW_SYNC; 1226 } 1227 1228 return status; 1229 } 1230 1231 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1232 * @hw: pointer to hardware structure 1233 * 1234 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1235 **/ 1236 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1237 { 1238 s32 status = 0; 1239 union ixgbe_hic_hdr2 buffer; 1240 1241 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1242 buffer.req.buf_lenh = 0; 1243 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1244 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1245 1246 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1247 IXGBE_HI_COMMAND_TIMEOUT, false); 1248 return status; 1249 } 1250 1251 /** 1252 * ixgbe_get_bus_info_X550em - Set PCI bus info 1253 * @hw: pointer to hardware structure 1254 * 1255 * Sets bus link width and speed to unknown because X550em is 1256 * not a PCI device. 1257 **/ 1258 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1259 { 1260 hw->bus.type = ixgbe_bus_type_internal; 1261 hw->bus.width = ixgbe_bus_width_unknown; 1262 hw->bus.speed = ixgbe_bus_speed_unknown; 1263 1264 hw->mac.ops.set_lan_id(hw); 1265 1266 return 0; 1267 } 1268 1269 /** ixgbe_disable_rx_x550 - Disable RX unit 1270 * 1271 * Enables the Rx DMA unit for x550 1272 **/ 1273 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1274 { 1275 u32 rxctrl, pfdtxgswc; 1276 s32 status; 1277 struct ixgbe_hic_disable_rxen fw_cmd; 1278 1279 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1280 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1281 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1282 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1283 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1284 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1285 hw->mac.set_lben = true; 1286 } else { 1287 hw->mac.set_lben = false; 1288 } 1289 1290 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1291 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1292 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1293 fw_cmd.port_number = hw->bus.lan_id; 1294 1295 status = ixgbe_host_interface_command(hw, &fw_cmd, 1296 sizeof(struct ixgbe_hic_disable_rxen), 1297 IXGBE_HI_COMMAND_TIMEOUT, true); 1298 1299 /* If we fail - disable RX using register write */ 1300 if (status) { 1301 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1302 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1303 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1304 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1305 } 1306 } 1307 } 1308 } 1309 1310 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1311 * @hw: pointer to hardware structure 1312 * 1313 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1314 * checksum and updates the EEPROM and instructs the hardware to update 1315 * the flash. 1316 **/ 1317 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1318 { 1319 s32 status; 1320 u16 checksum = 0; 1321 1322 /* Read the first word from the EEPROM. If this times out or fails, do 1323 * not continue or we could be in for a very long wait while every 1324 * EEPROM read fails 1325 */ 1326 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1327 if (status) { 1328 hw_dbg(hw, "EEPROM read failed\n"); 1329 return status; 1330 } 1331 1332 status = ixgbe_calc_eeprom_checksum_X550(hw); 1333 if (status < 0) 1334 return status; 1335 1336 checksum = (u16)(status & 0xffff); 1337 1338 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1339 checksum); 1340 if (status) 1341 return status; 1342 1343 status = ixgbe_update_flash_X550(hw); 1344 1345 return status; 1346 } 1347 1348 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1349 * @hw: pointer to hardware structure 1350 * @offset: offset of word in the EEPROM to write 1351 * @words: number of words 1352 * @data: word(s) write to the EEPROM 1353 * 1354 * 1355 * Write a 16 bit word(s) to the EEPROM using the hostif. 1356 **/ 1357 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1358 u16 offset, u16 words, 1359 u16 *data) 1360 { 1361 s32 status = 0; 1362 u32 i = 0; 1363 1364 /* Take semaphore for the entire operation. */ 1365 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1366 if (status) { 1367 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1368 return status; 1369 } 1370 1371 for (i = 0; i < words; i++) { 1372 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1373 data[i]); 1374 if (status) { 1375 hw_dbg(hw, "Eeprom buffered write failed\n"); 1376 break; 1377 } 1378 } 1379 1380 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1381 1382 return status; 1383 } 1384 1385 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1386 * IOSF device 1387 * 1388 * @hw: pointer to hardware structure 1389 * @reg_addr: 32 bit PHY register to write 1390 * @device_type: 3 bit device type 1391 * @data: Data to write to the register 1392 **/ 1393 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1394 u32 device_type, u32 data) 1395 { 1396 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1397 u32 command, error; 1398 s32 ret; 1399 1400 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1401 if (ret) 1402 return ret; 1403 1404 ret = ixgbe_iosf_wait(hw, NULL); 1405 if (ret) 1406 goto out; 1407 1408 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1409 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1410 1411 /* Write IOSF control register */ 1412 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1413 1414 /* Write IOSF data register */ 1415 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1416 1417 ret = ixgbe_iosf_wait(hw, &command); 1418 1419 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1420 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1421 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1422 hw_dbg(hw, "Failed to write, error %x\n", error); 1423 return IXGBE_ERR_PHY; 1424 } 1425 1426 out: 1427 hw->mac.ops.release_swfw_sync(hw, gssr); 1428 return ret; 1429 } 1430 1431 /** 1432 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1433 * @hw: pointer to hardware structure 1434 * 1435 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1436 **/ 1437 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1438 { 1439 s32 status; 1440 u32 reg_val; 1441 1442 /* Disable training protocol FSM. */ 1443 status = ixgbe_read_iosf_sb_reg_x550(hw, 1444 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1445 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1446 if (status) 1447 return status; 1448 1449 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1450 status = ixgbe_write_iosf_sb_reg_x550(hw, 1451 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1452 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1453 if (status) 1454 return status; 1455 1456 /* Disable Flex from training TXFFE. */ 1457 status = ixgbe_read_iosf_sb_reg_x550(hw, 1458 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1459 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1460 if (status) 1461 return status; 1462 1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1464 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1465 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1466 status = ixgbe_write_iosf_sb_reg_x550(hw, 1467 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1468 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1469 if (status) 1470 return status; 1471 1472 status = ixgbe_read_iosf_sb_reg_x550(hw, 1473 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1474 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1475 if (status) 1476 return status; 1477 1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1479 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1480 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1481 status = ixgbe_write_iosf_sb_reg_x550(hw, 1482 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1483 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1484 if (status) 1485 return status; 1486 1487 /* Enable override for coefficients. */ 1488 status = ixgbe_read_iosf_sb_reg_x550(hw, 1489 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1490 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1491 if (status) 1492 return status; 1493 1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1496 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1497 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1498 status = ixgbe_write_iosf_sb_reg_x550(hw, 1499 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1500 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1501 return status; 1502 } 1503 1504 /** 1505 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1506 * internal PHY 1507 * @hw: pointer to hardware structure 1508 **/ 1509 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1510 { 1511 s32 status; 1512 u32 link_ctrl; 1513 1514 /* Restart auto-negotiation. */ 1515 status = hw->mac.ops.read_iosf_sb_reg(hw, 1516 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1517 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1518 1519 if (status) { 1520 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1521 return status; 1522 } 1523 1524 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1525 status = hw->mac.ops.write_iosf_sb_reg(hw, 1526 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1527 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1528 1529 if (hw->mac.type == ixgbe_mac_x550em_a) { 1530 u32 flx_mask_st20; 1531 1532 /* Indicate to FW that AN restart has been asserted */ 1533 status = hw->mac.ops.read_iosf_sb_reg(hw, 1534 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1535 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1536 1537 if (status) { 1538 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1539 return status; 1540 } 1541 1542 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1543 status = hw->mac.ops.write_iosf_sb_reg(hw, 1544 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1545 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1546 } 1547 1548 return status; 1549 } 1550 1551 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1552 * @hw: pointer to hardware structure 1553 * @speed: the link speed to force 1554 * 1555 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1556 * internal and external PHY at a specific speed, without autonegotiation. 1557 **/ 1558 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1559 { 1560 struct ixgbe_mac_info *mac = &hw->mac; 1561 s32 status; 1562 u32 reg_val; 1563 1564 /* iXFI is only supported with X552 */ 1565 if (mac->type != ixgbe_mac_X550EM_x) 1566 return IXGBE_ERR_LINK_SETUP; 1567 1568 /* Disable AN and force speed to 10G Serial. */ 1569 status = ixgbe_read_iosf_sb_reg_x550(hw, 1570 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1571 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1572 if (status) 1573 return status; 1574 1575 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1576 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1577 1578 /* Select forced link speed for internal PHY. */ 1579 switch (*speed) { 1580 case IXGBE_LINK_SPEED_10GB_FULL: 1581 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1582 break; 1583 case IXGBE_LINK_SPEED_1GB_FULL: 1584 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1585 break; 1586 default: 1587 /* Other link speeds are not supported by internal KR PHY. */ 1588 return IXGBE_ERR_LINK_SETUP; 1589 } 1590 1591 status = ixgbe_write_iosf_sb_reg_x550(hw, 1592 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1593 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1594 if (status) 1595 return status; 1596 1597 /* Additional configuration needed for x550em_x */ 1598 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1599 status = ixgbe_setup_ixfi_x550em_x(hw); 1600 if (status) 1601 return status; 1602 } 1603 1604 /* Toggle port SW reset by AN reset. */ 1605 status = ixgbe_restart_an_internal_phy_x550em(hw); 1606 1607 return status; 1608 } 1609 1610 /** 1611 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1612 * @hw: pointer to hardware structure 1613 * @linear: true if SFP module is linear 1614 */ 1615 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1616 { 1617 switch (hw->phy.sfp_type) { 1618 case ixgbe_sfp_type_not_present: 1619 return IXGBE_ERR_SFP_NOT_PRESENT; 1620 case ixgbe_sfp_type_da_cu_core0: 1621 case ixgbe_sfp_type_da_cu_core1: 1622 *linear = true; 1623 break; 1624 case ixgbe_sfp_type_srlr_core0: 1625 case ixgbe_sfp_type_srlr_core1: 1626 case ixgbe_sfp_type_da_act_lmt_core0: 1627 case ixgbe_sfp_type_da_act_lmt_core1: 1628 case ixgbe_sfp_type_1g_sx_core0: 1629 case ixgbe_sfp_type_1g_sx_core1: 1630 case ixgbe_sfp_type_1g_lx_core0: 1631 case ixgbe_sfp_type_1g_lx_core1: 1632 *linear = false; 1633 break; 1634 case ixgbe_sfp_type_unknown: 1635 case ixgbe_sfp_type_1g_cu_core0: 1636 case ixgbe_sfp_type_1g_cu_core1: 1637 default: 1638 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1639 } 1640 1641 return 0; 1642 } 1643 1644 /** 1645 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1646 * @hw: pointer to hardware structure 1647 * @speed: the link speed to force 1648 * @autoneg_wait_to_complete: unused 1649 * 1650 * Configures the extern PHY and the integrated KR PHY for SFP support. 1651 */ 1652 static s32 1653 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1654 ixgbe_link_speed speed, 1655 __always_unused bool autoneg_wait_to_complete) 1656 { 1657 s32 status; 1658 u16 reg_slice, reg_val; 1659 bool setup_linear = false; 1660 1661 /* Check if SFP module is supported and linear */ 1662 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1663 1664 /* If no SFP module present, then return success. Return success since 1665 * there is no reason to configure CS4227 and SFP not present error is 1666 * not accepted in the setup MAC link flow. 1667 */ 1668 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 1669 return 0; 1670 1671 if (status) 1672 return status; 1673 1674 /* Configure internal PHY for KR/KX. */ 1675 ixgbe_setup_kr_speed_x550em(hw, speed); 1676 1677 /* Configure CS4227 LINE side to proper mode. */ 1678 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1679 if (setup_linear) 1680 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1681 else 1682 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1683 1684 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1685 reg_val); 1686 1687 return status; 1688 } 1689 1690 /** 1691 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1692 * @hw: pointer to hardware structure 1693 * @speed: the link speed to force 1694 * 1695 * Configures the integrated PHY for native SFI mode. Used to connect the 1696 * internal PHY directly to an SFP cage, without autonegotiation. 1697 **/ 1698 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1699 { 1700 struct ixgbe_mac_info *mac = &hw->mac; 1701 s32 status; 1702 u32 reg_val; 1703 1704 /* Disable all AN and force speed to 10G Serial. */ 1705 status = mac->ops.read_iosf_sb_reg(hw, 1706 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1707 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1708 if (status) 1709 return status; 1710 1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1712 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1713 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1714 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1715 1716 /* Select forced link speed for internal PHY. */ 1717 switch (*speed) { 1718 case IXGBE_LINK_SPEED_10GB_FULL: 1719 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1720 break; 1721 case IXGBE_LINK_SPEED_1GB_FULL: 1722 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1723 break; 1724 default: 1725 /* Other link speeds are not supported by internal PHY. */ 1726 return IXGBE_ERR_LINK_SETUP; 1727 } 1728 1729 status = mac->ops.write_iosf_sb_reg(hw, 1730 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1731 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1732 1733 /* Toggle port SW reset by AN reset. */ 1734 status = ixgbe_restart_an_internal_phy_x550em(hw); 1735 1736 return status; 1737 } 1738 1739 /** 1740 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1741 * @hw: pointer to hardware structure 1742 * @speed: link speed 1743 * @autoneg_wait_to_complete: unused 1744 * 1745 * Configure the the integrated PHY for native SFP support. 1746 */ 1747 static s32 1748 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1749 __always_unused bool autoneg_wait_to_complete) 1750 { 1751 bool setup_linear = false; 1752 u32 reg_phy_int; 1753 s32 ret_val; 1754 1755 /* Check if SFP module is supported and linear */ 1756 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1757 1758 /* If no SFP module present, then return success. Return success since 1759 * SFP not present error is not excepted in the setup MAC link flow. 1760 */ 1761 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1762 return 0; 1763 1764 if (ret_val) 1765 return ret_val; 1766 1767 /* Configure internal PHY for native SFI based on module type */ 1768 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1769 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1770 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1771 if (ret_val) 1772 return ret_val; 1773 1774 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1775 if (!setup_linear) 1776 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1777 1778 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1779 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1780 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1781 if (ret_val) 1782 return ret_val; 1783 1784 /* Setup SFI internal link. */ 1785 return ixgbe_setup_sfi_x550a(hw, &speed); 1786 } 1787 1788 /** 1789 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1790 * @hw: pointer to hardware structure 1791 * @speed: link speed 1792 * @autoneg_wait_to_complete: unused 1793 * 1794 * Configure the the integrated PHY for SFP support. 1795 */ 1796 static s32 1797 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1798 __always_unused bool autoneg_wait_to_complete) 1799 { 1800 u32 reg_slice, slice_offset; 1801 bool setup_linear = false; 1802 u16 reg_phy_ext; 1803 s32 ret_val; 1804 1805 /* Check if SFP module is supported and linear */ 1806 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1807 1808 /* If no SFP module present, then return success. Return success since 1809 * SFP not present error is not excepted in the setup MAC link flow. 1810 */ 1811 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1812 return 0; 1813 1814 if (ret_val) 1815 return ret_val; 1816 1817 /* Configure internal PHY for KR/KX. */ 1818 ixgbe_setup_kr_speed_x550em(hw, speed); 1819 1820 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1821 return IXGBE_ERR_PHY_ADDR_INVALID; 1822 1823 /* Get external PHY SKU id */ 1824 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 1825 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1826 if (ret_val) 1827 return ret_val; 1828 1829 /* When configuring quad port CS4223, the MAC instance is part 1830 * of the slice offset. 1831 */ 1832 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 1833 slice_offset = (hw->bus.lan_id + 1834 (hw->bus.instance_id << 1)) << 12; 1835 else 1836 slice_offset = hw->bus.lan_id << 12; 1837 1838 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1839 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1840 1841 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 1842 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1843 if (ret_val) 1844 return ret_val; 1845 1846 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1847 (IXGBE_CS4227_EDC_MODE_SR << 1)); 1848 1849 if (setup_linear) 1850 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1851 else 1852 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1853 1854 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 1855 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 1856 if (ret_val) 1857 return ret_val; 1858 1859 /* Flush previous write with a read */ 1860 return hw->phy.ops.read_reg(hw, reg_slice, 1861 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1862 } 1863 1864 /** 1865 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1866 * @hw: pointer to hardware structure 1867 * @speed: new link speed 1868 * @autoneg_wait: true when waiting for completion is needed 1869 * 1870 * Setup internal/external PHY link speed based on link speed, then set 1871 * external PHY auto advertised link speed. 1872 * 1873 * Returns error status for any failure 1874 **/ 1875 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1876 ixgbe_link_speed speed, 1877 bool autoneg_wait) 1878 { 1879 s32 status; 1880 ixgbe_link_speed force_speed; 1881 1882 /* Setup internal/external PHY link speed to iXFI (10G), unless 1883 * only 1G is auto advertised then setup KX link. 1884 */ 1885 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1886 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1887 else 1888 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1889 1890 /* If X552 and internal link mode is XFI, then setup XFI internal link. 1891 */ 1892 if (hw->mac.type == ixgbe_mac_X550EM_x && 1893 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1894 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1895 1896 if (status) 1897 return status; 1898 } 1899 1900 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1901 } 1902 1903 /** ixgbe_check_link_t_X550em - Determine link and speed status 1904 * @hw: pointer to hardware structure 1905 * @speed: pointer to link speed 1906 * @link_up: true when link is up 1907 * @link_up_wait_to_complete: bool used to wait for link up or not 1908 * 1909 * Check that both the MAC and X557 external PHY have link. 1910 **/ 1911 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1912 ixgbe_link_speed *speed, 1913 bool *link_up, 1914 bool link_up_wait_to_complete) 1915 { 1916 u32 status; 1917 u16 i, autoneg_status; 1918 1919 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1920 return IXGBE_ERR_CONFIG; 1921 1922 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1923 link_up_wait_to_complete); 1924 1925 /* If check link fails or MAC link is not up, then return */ 1926 if (status || !(*link_up)) 1927 return status; 1928 1929 /* MAC link is up, so check external PHY link. 1930 * Link status is latching low, and can only be used to detect link 1931 * drop, and not the current status of the link without performing 1932 * back-to-back reads. 1933 */ 1934 for (i = 0; i < 2; i++) { 1935 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1936 &autoneg_status); 1937 1938 if (status) 1939 return status; 1940 } 1941 1942 /* If external PHY link is not up, then indicate link not up */ 1943 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1944 *link_up = false; 1945 1946 return 0; 1947 } 1948 1949 /** 1950 * ixgbe_setup_sgmii - Set up link for sgmii 1951 * @hw: pointer to hardware structure 1952 * @speed: unused 1953 * @autoneg_wait_to_complete: unused 1954 */ 1955 static s32 1956 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1957 __always_unused bool autoneg_wait_to_complete) 1958 { 1959 struct ixgbe_mac_info *mac = &hw->mac; 1960 u32 lval, sval, flx_val; 1961 s32 rc; 1962 1963 rc = mac->ops.read_iosf_sb_reg(hw, 1964 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1965 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1966 if (rc) 1967 return rc; 1968 1969 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1970 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1971 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1972 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1973 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1974 rc = mac->ops.write_iosf_sb_reg(hw, 1975 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1976 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1977 if (rc) 1978 return rc; 1979 1980 rc = mac->ops.read_iosf_sb_reg(hw, 1981 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1982 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1983 if (rc) 1984 return rc; 1985 1986 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1987 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1988 rc = mac->ops.write_iosf_sb_reg(hw, 1989 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1990 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1991 if (rc) 1992 return rc; 1993 1994 rc = mac->ops.read_iosf_sb_reg(hw, 1995 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1996 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1997 if (rc) 1998 return rc; 1999 2000 rc = mac->ops.read_iosf_sb_reg(hw, 2001 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2002 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2003 if (rc) 2004 return rc; 2005 2006 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2007 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2008 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2009 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2010 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2011 2012 rc = mac->ops.write_iosf_sb_reg(hw, 2013 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2014 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2015 if (rc) 2016 return rc; 2017 2018 rc = ixgbe_restart_an_internal_phy_x550em(hw); 2019 return rc; 2020 } 2021 2022 /** 2023 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 2024 * @hw: pointer to hardware structure 2025 * @speed: the link speed to force 2026 * @autoneg_wait: true when waiting for completion is needed 2027 */ 2028 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 2029 bool autoneg_wait) 2030 { 2031 struct ixgbe_mac_info *mac = &hw->mac; 2032 u32 lval, sval, flx_val; 2033 s32 rc; 2034 2035 rc = mac->ops.read_iosf_sb_reg(hw, 2036 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2037 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2038 if (rc) 2039 return rc; 2040 2041 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2042 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2043 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2044 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2045 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2046 rc = mac->ops.write_iosf_sb_reg(hw, 2047 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2048 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2049 if (rc) 2050 return rc; 2051 2052 rc = mac->ops.read_iosf_sb_reg(hw, 2053 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2054 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2055 if (rc) 2056 return rc; 2057 2058 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2059 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2060 rc = mac->ops.write_iosf_sb_reg(hw, 2061 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2062 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2063 if (rc) 2064 return rc; 2065 2066 rc = mac->ops.write_iosf_sb_reg(hw, 2067 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2068 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2069 if (rc) 2070 return rc; 2071 2072 rc = mac->ops.read_iosf_sb_reg(hw, 2073 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2074 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2075 if (rc) 2076 return rc; 2077 2078 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2079 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2080 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2081 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2082 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2083 2084 rc = mac->ops.write_iosf_sb_reg(hw, 2085 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2086 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2087 if (rc) 2088 return rc; 2089 2090 ixgbe_restart_an_internal_phy_x550em(hw); 2091 2092 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2093 } 2094 2095 /** 2096 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2097 * @hw: pointer to hardware structure 2098 * 2099 * Enable flow control according to IEEE clause 37. 2100 */ 2101 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2102 { 2103 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2104 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2105 ixgbe_link_speed speed; 2106 bool link_up; 2107 2108 /* AN should have completed when the cable was plugged in. 2109 * Look for reasons to bail out. Bail out if: 2110 * - FC autoneg is disabled, or if 2111 * - link is not up. 2112 */ 2113 if (hw->fc.disable_fc_autoneg) 2114 goto out; 2115 2116 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2117 if (!link_up) 2118 goto out; 2119 2120 /* Check if auto-negotiation has completed */ 2121 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2122 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2123 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2124 goto out; 2125 } 2126 2127 /* Negotiate the flow control */ 2128 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2129 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2130 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2131 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2132 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2133 2134 out: 2135 if (!status) { 2136 hw->fc.fc_was_autonegged = true; 2137 } else { 2138 hw->fc.fc_was_autonegged = false; 2139 hw->fc.current_mode = hw->fc.requested_mode; 2140 } 2141 } 2142 2143 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2144 * @hw: pointer to hardware structure 2145 **/ 2146 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2147 { 2148 struct ixgbe_mac_info *mac = &hw->mac; 2149 2150 switch (mac->ops.get_media_type(hw)) { 2151 case ixgbe_media_type_fiber: 2152 mac->ops.setup_fc = NULL; 2153 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2154 break; 2155 case ixgbe_media_type_copper: 2156 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2157 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2158 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2159 break; 2160 } 2161 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2162 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2163 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2164 mac->ops.check_link = ixgbe_check_mac_link_generic; 2165 break; 2166 case ixgbe_media_type_backplane: 2167 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2168 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2169 break; 2170 default: 2171 break; 2172 } 2173 } 2174 2175 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2176 * @hw: pointer to hardware structure 2177 **/ 2178 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2179 { 2180 struct ixgbe_mac_info *mac = &hw->mac; 2181 2182 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2183 2184 switch (mac->ops.get_media_type(hw)) { 2185 case ixgbe_media_type_fiber: 2186 /* CS4227 does not support autoneg, so disable the laser control 2187 * functions for SFP+ fiber 2188 */ 2189 mac->ops.disable_tx_laser = NULL; 2190 mac->ops.enable_tx_laser = NULL; 2191 mac->ops.flap_tx_laser = NULL; 2192 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2193 switch (hw->device_id) { 2194 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2195 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2196 break; 2197 case IXGBE_DEV_ID_X550EM_A_SFP: 2198 mac->ops.setup_mac_link = 2199 ixgbe_setup_mac_link_sfp_x550a; 2200 break; 2201 default: 2202 mac->ops.setup_mac_link = 2203 ixgbe_setup_mac_link_sfp_x550em; 2204 break; 2205 } 2206 mac->ops.set_rate_select_speed = 2207 ixgbe_set_soft_rate_select_speed; 2208 break; 2209 case ixgbe_media_type_copper: 2210 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2211 break; 2212 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2213 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2214 mac->ops.check_link = ixgbe_check_link_t_X550em; 2215 break; 2216 case ixgbe_media_type_backplane: 2217 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2218 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2219 mac->ops.setup_link = ixgbe_setup_sgmii; 2220 break; 2221 default: 2222 break; 2223 } 2224 2225 /* Additional modification for X550em_a devices */ 2226 if (hw->mac.type == ixgbe_mac_x550em_a) 2227 ixgbe_init_mac_link_ops_X550em_a(hw); 2228 } 2229 2230 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2231 * @hw: pointer to hardware structure 2232 */ 2233 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2234 { 2235 s32 status; 2236 bool linear; 2237 2238 /* Check if SFP module is supported */ 2239 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2240 if (status) 2241 return status; 2242 2243 ixgbe_init_mac_link_ops_X550em(hw); 2244 hw->phy.ops.reset = NULL; 2245 2246 return 0; 2247 } 2248 2249 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2250 * @hw: pointer to hardware structure 2251 * @speed: pointer to link speed 2252 * @autoneg: true when autoneg or autotry is enabled 2253 **/ 2254 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2255 ixgbe_link_speed *speed, 2256 bool *autoneg) 2257 { 2258 if (hw->phy.type == ixgbe_phy_fw) { 2259 *autoneg = true; 2260 *speed = hw->phy.speeds_supported; 2261 return 0; 2262 } 2263 2264 /* SFP */ 2265 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2266 /* CS4227 SFP must not enable auto-negotiation */ 2267 *autoneg = false; 2268 2269 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2270 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 2271 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2272 return 0; 2273 } 2274 2275 /* Link capabilities are based on SFP */ 2276 if (hw->phy.multispeed_fiber) 2277 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2278 IXGBE_LINK_SPEED_1GB_FULL; 2279 else 2280 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2281 } else { 2282 switch (hw->phy.type) { 2283 case ixgbe_phy_x550em_kx4: 2284 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2285 IXGBE_LINK_SPEED_2_5GB_FULL | 2286 IXGBE_LINK_SPEED_10GB_FULL; 2287 break; 2288 case ixgbe_phy_x550em_xfi: 2289 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2290 IXGBE_LINK_SPEED_10GB_FULL; 2291 break; 2292 case ixgbe_phy_ext_1g_t: 2293 case ixgbe_phy_sgmii: 2294 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2295 break; 2296 case ixgbe_phy_x550em_kr: 2297 if (hw->mac.type == ixgbe_mac_x550em_a) { 2298 /* check different backplane modes */ 2299 if (hw->phy.nw_mng_if_sel & 2300 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2301 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2302 break; 2303 } else if (hw->device_id == 2304 IXGBE_DEV_ID_X550EM_A_KR_L) { 2305 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2306 break; 2307 } 2308 } 2309 /* fall through */ 2310 default: 2311 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2312 IXGBE_LINK_SPEED_1GB_FULL; 2313 break; 2314 } 2315 *autoneg = true; 2316 } 2317 return 0; 2318 } 2319 2320 /** 2321 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2322 * @hw: pointer to hardware structure 2323 * @lsc: pointer to boolean flag which indicates whether external Base T 2324 * PHY interrupt is lsc 2325 * 2326 * Determime if external Base T PHY interrupt cause is high temperature 2327 * failure alarm or link status change. 2328 * 2329 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2330 * failure alarm, else return PHY access status. 2331 **/ 2332 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2333 { 2334 u32 status; 2335 u16 reg; 2336 2337 *lsc = false; 2338 2339 /* Vendor alarm triggered */ 2340 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2341 MDIO_MMD_VEND1, 2342 ®); 2343 2344 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2345 return status; 2346 2347 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2348 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2349 MDIO_MMD_VEND1, 2350 ®); 2351 2352 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2353 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2354 return status; 2355 2356 /* Global alarm triggered */ 2357 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2358 MDIO_MMD_VEND1, 2359 ®); 2360 2361 if (status) 2362 return status; 2363 2364 /* If high temperature failure, then return over temp error and exit */ 2365 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2366 /* power down the PHY in case the PHY FW didn't already */ 2367 ixgbe_set_copper_phy_power(hw, false); 2368 return IXGBE_ERR_OVERTEMP; 2369 } 2370 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2371 /* device fault alarm triggered */ 2372 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2373 MDIO_MMD_VEND1, 2374 ®); 2375 if (status) 2376 return status; 2377 2378 /* if device fault was due to high temp alarm handle and exit */ 2379 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2380 /* power down the PHY in case the PHY FW didn't */ 2381 ixgbe_set_copper_phy_power(hw, false); 2382 return IXGBE_ERR_OVERTEMP; 2383 } 2384 } 2385 2386 /* Vendor alarm 2 triggered */ 2387 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2388 MDIO_MMD_AN, ®); 2389 2390 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2391 return status; 2392 2393 /* link connect/disconnect event occurred */ 2394 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2395 MDIO_MMD_AN, ®); 2396 2397 if (status) 2398 return status; 2399 2400 /* Indicate LSC */ 2401 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2402 *lsc = true; 2403 2404 return 0; 2405 } 2406 2407 /** 2408 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2409 * @hw: pointer to hardware structure 2410 * 2411 * Enable link status change and temperature failure alarm for the external 2412 * Base T PHY 2413 * 2414 * Returns PHY access status 2415 **/ 2416 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2417 { 2418 u32 status; 2419 u16 reg; 2420 bool lsc; 2421 2422 /* Clear interrupt flags */ 2423 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2424 2425 /* Enable link status change alarm */ 2426 2427 /* Enable the LASI interrupts on X552 devices to receive notifications 2428 * of the link configurations of the external PHY and correspondingly 2429 * support the configuration of the internal iXFI link, since iXFI does 2430 * not support auto-negotiation. This is not required for X553 devices 2431 * having KR support, which performs auto-negotiations and which is used 2432 * as the internal link to the external PHY. Hence adding a check here 2433 * to avoid enabling LASI interrupts for X553 devices. 2434 */ 2435 if (hw->mac.type != ixgbe_mac_x550em_a) { 2436 status = hw->phy.ops.read_reg(hw, 2437 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2438 MDIO_MMD_AN, ®); 2439 if (status) 2440 return status; 2441 2442 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2443 2444 status = hw->phy.ops.write_reg(hw, 2445 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2446 MDIO_MMD_AN, reg); 2447 if (status) 2448 return status; 2449 } 2450 2451 /* Enable high temperature failure and global fault alarms */ 2452 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2453 MDIO_MMD_VEND1, 2454 ®); 2455 if (status) 2456 return status; 2457 2458 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2459 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2460 2461 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2462 MDIO_MMD_VEND1, 2463 reg); 2464 if (status) 2465 return status; 2466 2467 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2468 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2469 MDIO_MMD_VEND1, 2470 ®); 2471 if (status) 2472 return status; 2473 2474 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2475 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2476 2477 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2478 MDIO_MMD_VEND1, 2479 reg); 2480 if (status) 2481 return status; 2482 2483 /* Enable chip-wide vendor alarm */ 2484 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2485 MDIO_MMD_VEND1, 2486 ®); 2487 if (status) 2488 return status; 2489 2490 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2491 2492 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2493 MDIO_MMD_VEND1, 2494 reg); 2495 2496 return status; 2497 } 2498 2499 /** 2500 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2501 * @hw: pointer to hardware structure 2502 * 2503 * Handle external Base T PHY interrupt. If high temperature 2504 * failure alarm then return error, else if link status change 2505 * then setup internal/external PHY link 2506 * 2507 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2508 * failure alarm, else return PHY access status. 2509 **/ 2510 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2511 { 2512 struct ixgbe_phy_info *phy = &hw->phy; 2513 bool lsc; 2514 u32 status; 2515 2516 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2517 if (status) 2518 return status; 2519 2520 if (lsc && phy->ops.setup_internal_link) 2521 return phy->ops.setup_internal_link(hw); 2522 2523 return 0; 2524 } 2525 2526 /** 2527 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2528 * @hw: pointer to hardware structure 2529 * @speed: link speed 2530 * 2531 * Configures the integrated KR PHY. 2532 **/ 2533 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2534 ixgbe_link_speed speed) 2535 { 2536 s32 status; 2537 u32 reg_val; 2538 2539 status = hw->mac.ops.read_iosf_sb_reg(hw, 2540 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2541 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2542 if (status) 2543 return status; 2544 2545 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2546 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2547 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2548 2549 /* Advertise 10G support. */ 2550 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2551 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2552 2553 /* Advertise 1G support. */ 2554 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2555 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2556 2557 status = hw->mac.ops.write_iosf_sb_reg(hw, 2558 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2559 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2560 2561 if (hw->mac.type == ixgbe_mac_x550em_a) { 2562 /* Set lane mode to KR auto negotiation */ 2563 status = hw->mac.ops.read_iosf_sb_reg(hw, 2564 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2565 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2566 2567 if (status) 2568 return status; 2569 2570 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2571 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2572 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2573 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2574 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2575 2576 status = hw->mac.ops.write_iosf_sb_reg(hw, 2577 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2578 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2579 } 2580 2581 return ixgbe_restart_an_internal_phy_x550em(hw); 2582 } 2583 2584 /** 2585 * ixgbe_setup_kr_x550em - Configure the KR PHY 2586 * @hw: pointer to hardware structure 2587 **/ 2588 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2589 { 2590 /* leave link alone for 2.5G */ 2591 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2592 return 0; 2593 2594 if (ixgbe_check_reset_blocked(hw)) 2595 return 0; 2596 2597 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2598 } 2599 2600 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2601 * @hw: address of hardware structure 2602 * @link_up: address of boolean to indicate link status 2603 * 2604 * Returns error code if unable to get link status. 2605 **/ 2606 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2607 { 2608 u32 ret; 2609 u16 autoneg_status; 2610 2611 *link_up = false; 2612 2613 /* read this twice back to back to indicate current status */ 2614 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2615 &autoneg_status); 2616 if (ret) 2617 return ret; 2618 2619 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2620 &autoneg_status); 2621 if (ret) 2622 return ret; 2623 2624 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2625 2626 return 0; 2627 } 2628 2629 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2630 * @hw: point to hardware structure 2631 * 2632 * Configures the link between the integrated KR PHY and the external X557 PHY 2633 * The driver will call this function when it gets a link status change 2634 * interrupt from the X557 PHY. This function configures the link speed 2635 * between the PHYs to match the link speed of the BASE-T link. 2636 * 2637 * A return of a non-zero value indicates an error, and the base driver should 2638 * not report link up. 2639 **/ 2640 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2641 { 2642 ixgbe_link_speed force_speed; 2643 bool link_up; 2644 u32 status; 2645 u16 speed; 2646 2647 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2648 return IXGBE_ERR_CONFIG; 2649 2650 if (!(hw->mac.type == ixgbe_mac_X550EM_x && 2651 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) { 2652 speed = IXGBE_LINK_SPEED_10GB_FULL | 2653 IXGBE_LINK_SPEED_1GB_FULL; 2654 return ixgbe_setup_kr_speed_x550em(hw, speed); 2655 } 2656 2657 /* If link is not up, then there is no setup necessary so return */ 2658 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2659 if (status) 2660 return status; 2661 2662 if (!link_up) 2663 return 0; 2664 2665 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2666 MDIO_MMD_AN, 2667 &speed); 2668 if (status) 2669 return status; 2670 2671 /* If link is not still up, then no setup is necessary so return */ 2672 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2673 if (status) 2674 return status; 2675 2676 if (!link_up) 2677 return 0; 2678 2679 /* clear everything but the speed and duplex bits */ 2680 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2681 2682 switch (speed) { 2683 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2684 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2685 break; 2686 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2687 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2688 break; 2689 default: 2690 /* Internal PHY does not support anything else */ 2691 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2692 } 2693 2694 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2695 } 2696 2697 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2698 * @hw: pointer to hardware structure 2699 **/ 2700 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2701 { 2702 s32 status; 2703 2704 status = ixgbe_reset_phy_generic(hw); 2705 2706 if (status) 2707 return status; 2708 2709 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2710 return ixgbe_enable_lasi_ext_t_x550em(hw); 2711 } 2712 2713 /** 2714 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2715 * @hw: pointer to hardware structure 2716 * @led_idx: led number to turn on 2717 **/ 2718 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2719 { 2720 u16 phy_data; 2721 2722 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2723 return IXGBE_ERR_PARAM; 2724 2725 /* To turn on the LED, set mode to ON. */ 2726 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2727 MDIO_MMD_VEND1, &phy_data); 2728 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2729 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2730 MDIO_MMD_VEND1, phy_data); 2731 2732 return 0; 2733 } 2734 2735 /** 2736 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2737 * @hw: pointer to hardware structure 2738 * @led_idx: led number to turn off 2739 **/ 2740 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2741 { 2742 u16 phy_data; 2743 2744 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2745 return IXGBE_ERR_PARAM; 2746 2747 /* To turn on the LED, set mode to ON. */ 2748 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2749 MDIO_MMD_VEND1, &phy_data); 2750 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2751 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2752 MDIO_MMD_VEND1, phy_data); 2753 2754 return 0; 2755 } 2756 2757 /** 2758 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2759 * @hw: pointer to the HW structure 2760 * @maj: driver version major number 2761 * @min: driver version minor number 2762 * @build: driver version build number 2763 * @sub: driver version sub build number 2764 * @len: length of driver_ver string 2765 * @driver_ver: driver string 2766 * 2767 * Sends driver version number to firmware through the manageability 2768 * block. On success return 0 2769 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 2770 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 2771 **/ 2772 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2773 u8 build, u8 sub, u16 len, 2774 const char *driver_ver) 2775 { 2776 struct ixgbe_hic_drv_info2 fw_cmd; 2777 s32 ret_val; 2778 int i; 2779 2780 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2781 return IXGBE_ERR_INVALID_ARGUMENT; 2782 2783 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2784 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2785 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2786 fw_cmd.port_num = (u8)hw->bus.func; 2787 fw_cmd.ver_maj = maj; 2788 fw_cmd.ver_min = min; 2789 fw_cmd.ver_build = build; 2790 fw_cmd.ver_sub = sub; 2791 fw_cmd.hdr.checksum = 0; 2792 memcpy(fw_cmd.driver_string, driver_ver, len); 2793 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2794 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2795 2796 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2797 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2798 sizeof(fw_cmd), 2799 IXGBE_HI_COMMAND_TIMEOUT, 2800 true); 2801 if (ret_val) 2802 continue; 2803 2804 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2805 FW_CEM_RESP_STATUS_SUCCESS) 2806 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 2807 return 0; 2808 } 2809 2810 return ret_val; 2811 } 2812 2813 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2814 * @hw: pointer to hardware structure 2815 * @lcd_speed: pointer to lowest common link speed 2816 * 2817 * Determine lowest common link speed with link partner. 2818 **/ 2819 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2820 ixgbe_link_speed *lcd_speed) 2821 { 2822 u16 an_lp_status; 2823 s32 status; 2824 u16 word = hw->eeprom.ctrl_word_3; 2825 2826 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2827 2828 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2829 MDIO_MMD_AN, 2830 &an_lp_status); 2831 if (status) 2832 return status; 2833 2834 /* If link partner advertised 1G, return 1G */ 2835 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2836 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2837 return status; 2838 } 2839 2840 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2841 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2842 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2843 return status; 2844 2845 /* Link partner not capable of lower speeds, return 10G */ 2846 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2847 return status; 2848 } 2849 2850 /** 2851 * ixgbe_setup_fc_x550em - Set up flow control 2852 * @hw: pointer to hardware structure 2853 */ 2854 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2855 { 2856 bool pause, asm_dir; 2857 u32 reg_val; 2858 s32 rc = 0; 2859 2860 /* Validate the requested mode */ 2861 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2862 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2863 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2864 } 2865 2866 /* 10gig parts do not have a word in the EEPROM to determine the 2867 * default flow control setting, so we explicitly set it to full. 2868 */ 2869 if (hw->fc.requested_mode == ixgbe_fc_default) 2870 hw->fc.requested_mode = ixgbe_fc_full; 2871 2872 /* Determine PAUSE and ASM_DIR bits. */ 2873 switch (hw->fc.requested_mode) { 2874 case ixgbe_fc_none: 2875 pause = false; 2876 asm_dir = false; 2877 break; 2878 case ixgbe_fc_tx_pause: 2879 pause = false; 2880 asm_dir = true; 2881 break; 2882 case ixgbe_fc_rx_pause: 2883 /* Rx Flow control is enabled and Tx Flow control is 2884 * disabled by software override. Since there really 2885 * isn't a way to advertise that we are capable of RX 2886 * Pause ONLY, we will advertise that we support both 2887 * symmetric and asymmetric Rx PAUSE, as such we fall 2888 * through to the fc_full statement. Later, we will 2889 * disable the adapter's ability to send PAUSE frames. 2890 */ 2891 /* Fallthrough */ 2892 case ixgbe_fc_full: 2893 pause = true; 2894 asm_dir = true; 2895 break; 2896 default: 2897 hw_err(hw, "Flow control param set incorrectly\n"); 2898 return IXGBE_ERR_CONFIG; 2899 } 2900 2901 switch (hw->device_id) { 2902 case IXGBE_DEV_ID_X550EM_X_KR: 2903 case IXGBE_DEV_ID_X550EM_A_KR: 2904 case IXGBE_DEV_ID_X550EM_A_KR_L: 2905 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2906 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2907 IXGBE_SB_IOSF_TARGET_KR_PHY, 2908 ®_val); 2909 if (rc) 2910 return rc; 2911 2912 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2913 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2914 if (pause) 2915 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2916 if (asm_dir) 2917 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2918 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2919 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2920 IXGBE_SB_IOSF_TARGET_KR_PHY, 2921 reg_val); 2922 2923 /* This device does not fully support AN. */ 2924 hw->fc.disable_fc_autoneg = true; 2925 break; 2926 case IXGBE_DEV_ID_X550EM_X_XFI: 2927 hw->fc.disable_fc_autoneg = true; 2928 break; 2929 default: 2930 break; 2931 } 2932 return rc; 2933 } 2934 2935 /** 2936 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2937 * @hw: pointer to hardware structure 2938 **/ 2939 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2940 { 2941 u32 link_s1, lp_an_page_low, an_cntl_1; 2942 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2943 ixgbe_link_speed speed; 2944 bool link_up; 2945 2946 /* AN should have completed when the cable was plugged in. 2947 * Look for reasons to bail out. Bail out if: 2948 * - FC autoneg is disabled, or if 2949 * - link is not up. 2950 */ 2951 if (hw->fc.disable_fc_autoneg) { 2952 hw_err(hw, "Flow control autoneg is disabled"); 2953 goto out; 2954 } 2955 2956 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2957 if (!link_up) { 2958 hw_err(hw, "The link is down"); 2959 goto out; 2960 } 2961 2962 /* Check at auto-negotiation has completed */ 2963 status = hw->mac.ops.read_iosf_sb_reg(hw, 2964 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2966 2967 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2968 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2969 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2970 goto out; 2971 } 2972 2973 /* Read the 10g AN autoc and LP ability registers and resolve 2974 * local flow control settings accordingly 2975 */ 2976 status = hw->mac.ops.read_iosf_sb_reg(hw, 2977 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2978 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2979 2980 if (status) { 2981 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2982 goto out; 2983 } 2984 2985 status = hw->mac.ops.read_iosf_sb_reg(hw, 2986 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2987 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2988 2989 if (status) { 2990 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2991 goto out; 2992 } 2993 2994 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2995 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2996 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2997 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2998 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2999 3000 out: 3001 if (!status) { 3002 hw->fc.fc_was_autonegged = true; 3003 } else { 3004 hw->fc.fc_was_autonegged = false; 3005 hw->fc.current_mode = hw->fc.requested_mode; 3006 } 3007 } 3008 3009 /** 3010 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 3011 * @hw: pointer to hardware structure 3012 **/ 3013 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 3014 { 3015 hw->fc.fc_was_autonegged = false; 3016 hw->fc.current_mode = hw->fc.requested_mode; 3017 } 3018 3019 /** ixgbe_enter_lplu_x550em - Transition to low power states 3020 * @hw: pointer to hardware structure 3021 * 3022 * Configures Low Power Link Up on transition to low power states 3023 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 3024 * the X557 PHY immediately prior to entering LPLU. 3025 **/ 3026 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3027 { 3028 u16 an_10g_cntl_reg, autoneg_reg, speed; 3029 s32 status; 3030 ixgbe_link_speed lcd_speed; 3031 u32 save_autoneg; 3032 bool link_up; 3033 3034 /* If blocked by MNG FW, then don't restart AN */ 3035 if (ixgbe_check_reset_blocked(hw)) 3036 return 0; 3037 3038 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3039 if (status) 3040 return status; 3041 3042 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 3043 &hw->eeprom.ctrl_word_3); 3044 if (status) 3045 return status; 3046 3047 /* If link is down, LPLU disabled in NVM, WoL disabled, or 3048 * manageability disabled, then force link down by entering 3049 * low power mode. 3050 */ 3051 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3052 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3053 return ixgbe_set_copper_phy_power(hw, false); 3054 3055 /* Determine LCD */ 3056 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3057 if (status) 3058 return status; 3059 3060 /* If no valid LCD link speed, then force link down and exit. */ 3061 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3062 return ixgbe_set_copper_phy_power(hw, false); 3063 3064 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3065 MDIO_MMD_AN, 3066 &speed); 3067 if (status) 3068 return status; 3069 3070 /* If no link now, speed is invalid so take link down */ 3071 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3072 if (status) 3073 return ixgbe_set_copper_phy_power(hw, false); 3074 3075 /* clear everything but the speed bits */ 3076 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3077 3078 /* If current speed is already LCD, then exit. */ 3079 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3080 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3081 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3082 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3083 return status; 3084 3085 /* Clear AN completed indication */ 3086 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3087 MDIO_MMD_AN, 3088 &autoneg_reg); 3089 if (status) 3090 return status; 3091 3092 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3093 MDIO_MMD_AN, 3094 &an_10g_cntl_reg); 3095 if (status) 3096 return status; 3097 3098 status = hw->phy.ops.read_reg(hw, 3099 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3100 MDIO_MMD_AN, 3101 &autoneg_reg); 3102 if (status) 3103 return status; 3104 3105 save_autoneg = hw->phy.autoneg_advertised; 3106 3107 /* Setup link at least common link speed */ 3108 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3109 3110 /* restore autoneg from before setting lplu speed */ 3111 hw->phy.autoneg_advertised = save_autoneg; 3112 3113 return status; 3114 } 3115 3116 /** 3117 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3118 * @hw: pointer to hardware structure 3119 */ 3120 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3121 { 3122 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3123 s32 rc; 3124 3125 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3126 return 0; 3127 3128 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3129 if (rc) 3130 return rc; 3131 memset(store, 0, sizeof(store)); 3132 3133 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3134 if (rc) 3135 return rc; 3136 3137 return ixgbe_setup_fw_link(hw); 3138 } 3139 3140 /** 3141 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3142 * @hw: pointer to hardware structure 3143 */ 3144 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3145 { 3146 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3147 s32 rc; 3148 3149 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3150 if (rc) 3151 return rc; 3152 3153 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3154 ixgbe_shutdown_fw_phy(hw); 3155 return IXGBE_ERR_OVERTEMP; 3156 } 3157 return 0; 3158 } 3159 3160 /** 3161 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3162 * @hw: pointer to hardware structure 3163 * 3164 * Read NW_MNG_IF_SEL register and save field values. 3165 */ 3166 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3167 { 3168 /* Save NW management interface connected on board. This is used 3169 * to determine internal PHY mode. 3170 */ 3171 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3172 3173 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3174 * PHY address. This register field was has only been used for X552. 3175 */ 3176 if (hw->mac.type == ixgbe_mac_x550em_a && 3177 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3178 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 3179 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 3180 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 3181 } 3182 } 3183 3184 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3185 * @hw: pointer to hardware structure 3186 * 3187 * Initialize any function pointers that were not able to be 3188 * set during init_shared_code because the PHY/SFP type was 3189 * not known. Perform the SFP init if necessary. 3190 **/ 3191 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3192 { 3193 struct ixgbe_phy_info *phy = &hw->phy; 3194 s32 ret_val; 3195 3196 hw->mac.ops.set_lan_id(hw); 3197 3198 ixgbe_read_mng_if_sel_x550em(hw); 3199 3200 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3201 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3202 ixgbe_setup_mux_ctl(hw); 3203 } 3204 3205 /* Identify the PHY or SFP module */ 3206 ret_val = phy->ops.identify(hw); 3207 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 3208 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 3209 return ret_val; 3210 3211 /* Setup function pointers based on detected hardware */ 3212 ixgbe_init_mac_link_ops_X550em(hw); 3213 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3214 phy->ops.reset = NULL; 3215 3216 /* Set functions pointers based on phy type */ 3217 switch (hw->phy.type) { 3218 case ixgbe_phy_x550em_kx4: 3219 phy->ops.setup_link = NULL; 3220 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3221 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3222 break; 3223 case ixgbe_phy_x550em_kr: 3224 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3225 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3226 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3227 break; 3228 case ixgbe_phy_x550em_xfi: 3229 /* link is managed by HW */ 3230 phy->ops.setup_link = NULL; 3231 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3232 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3233 break; 3234 case ixgbe_phy_x550em_ext_t: 3235 /* Save NW management interface connected on board. This is used 3236 * to determine internal PHY mode 3237 */ 3238 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3239 3240 /* If internal link mode is XFI, then setup iXFI internal link, 3241 * else setup KR now. 3242 */ 3243 phy->ops.setup_internal_link = 3244 ixgbe_setup_internal_phy_t_x550em; 3245 3246 /* setup SW LPLU only for first revision */ 3247 if (hw->mac.type == ixgbe_mac_X550EM_x && 3248 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3249 IXGBE_FUSES0_REV_MASK)) 3250 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3251 3252 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3253 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3254 break; 3255 case ixgbe_phy_sgmii: 3256 phy->ops.setup_link = NULL; 3257 break; 3258 case ixgbe_phy_fw: 3259 phy->ops.setup_link = ixgbe_setup_fw_link; 3260 phy->ops.reset = ixgbe_reset_phy_fw; 3261 break; 3262 case ixgbe_phy_ext_1g_t: 3263 phy->ops.setup_link = NULL; 3264 phy->ops.read_reg = NULL; 3265 phy->ops.write_reg = NULL; 3266 phy->ops.reset = NULL; 3267 break; 3268 default: 3269 break; 3270 } 3271 3272 return ret_val; 3273 } 3274 3275 /** ixgbe_get_media_type_X550em - Get media type 3276 * @hw: pointer to hardware structure 3277 * 3278 * Returns the media type (fiber, copper, backplane) 3279 * 3280 */ 3281 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3282 { 3283 enum ixgbe_media_type media_type; 3284 3285 /* Detect if there is a copper PHY attached. */ 3286 switch (hw->device_id) { 3287 case IXGBE_DEV_ID_X550EM_A_SGMII: 3288 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3289 hw->phy.type = ixgbe_phy_sgmii; 3290 /* Fallthrough */ 3291 case IXGBE_DEV_ID_X550EM_X_KR: 3292 case IXGBE_DEV_ID_X550EM_X_KX4: 3293 case IXGBE_DEV_ID_X550EM_X_XFI: 3294 case IXGBE_DEV_ID_X550EM_A_KR: 3295 case IXGBE_DEV_ID_X550EM_A_KR_L: 3296 media_type = ixgbe_media_type_backplane; 3297 break; 3298 case IXGBE_DEV_ID_X550EM_X_SFP: 3299 case IXGBE_DEV_ID_X550EM_A_SFP: 3300 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3301 media_type = ixgbe_media_type_fiber; 3302 break; 3303 case IXGBE_DEV_ID_X550EM_X_1G_T: 3304 case IXGBE_DEV_ID_X550EM_X_10G_T: 3305 case IXGBE_DEV_ID_X550EM_A_10G_T: 3306 case IXGBE_DEV_ID_X550EM_A_1G_T: 3307 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3308 media_type = ixgbe_media_type_copper; 3309 break; 3310 default: 3311 media_type = ixgbe_media_type_unknown; 3312 break; 3313 } 3314 return media_type; 3315 } 3316 3317 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3318 ** @hw: pointer to hardware structure 3319 **/ 3320 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3321 { 3322 s32 status; 3323 u16 reg; 3324 3325 status = hw->phy.ops.read_reg(hw, 3326 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3327 MDIO_MMD_PMAPMD, 3328 ®); 3329 if (status) 3330 return status; 3331 3332 /* If PHY FW reset completed bit is set then this is the first 3333 * SW instance after a power on so the PHY FW must be un-stalled. 3334 */ 3335 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3336 status = hw->phy.ops.read_reg(hw, 3337 IXGBE_MDIO_GLOBAL_RES_PR_10, 3338 MDIO_MMD_VEND1, 3339 ®); 3340 if (status) 3341 return status; 3342 3343 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3344 3345 status = hw->phy.ops.write_reg(hw, 3346 IXGBE_MDIO_GLOBAL_RES_PR_10, 3347 MDIO_MMD_VEND1, 3348 reg); 3349 if (status) 3350 return status; 3351 } 3352 3353 return status; 3354 } 3355 3356 /** 3357 * ixgbe_set_mdio_speed - Set MDIO clock speed 3358 * @hw: pointer to hardware structure 3359 */ 3360 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3361 { 3362 u32 hlreg0; 3363 3364 switch (hw->device_id) { 3365 case IXGBE_DEV_ID_X550EM_X_10G_T: 3366 case IXGBE_DEV_ID_X550EM_A_SGMII: 3367 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3368 case IXGBE_DEV_ID_X550EM_A_10G_T: 3369 case IXGBE_DEV_ID_X550EM_A_SFP: 3370 /* Config MDIO clock speed before the first MDIO PHY access */ 3371 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3372 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3373 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3374 break; 3375 case IXGBE_DEV_ID_X550EM_A_1G_T: 3376 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3377 /* Select fast MDIO clock speed for these devices */ 3378 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3379 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3380 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3381 break; 3382 default: 3383 break; 3384 } 3385 } 3386 3387 /** ixgbe_reset_hw_X550em - Perform hardware reset 3388 ** @hw: pointer to hardware structure 3389 ** 3390 ** Resets the hardware by resetting the transmit and receive units, masks 3391 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3392 ** reset. 3393 **/ 3394 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3395 { 3396 ixgbe_link_speed link_speed; 3397 s32 status; 3398 u32 ctrl = 0; 3399 u32 i; 3400 bool link_up = false; 3401 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3402 3403 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3404 status = hw->mac.ops.stop_adapter(hw); 3405 if (status) 3406 return status; 3407 3408 /* flush pending Tx transactions */ 3409 ixgbe_clear_tx_pending(hw); 3410 3411 /* PHY ops must be identified and initialized prior to reset */ 3412 status = hw->phy.ops.init(hw); 3413 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || 3414 status == IXGBE_ERR_PHY_ADDR_INVALID) 3415 return status; 3416 3417 /* start the external PHY */ 3418 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3419 status = ixgbe_init_ext_t_x550em(hw); 3420 if (status) 3421 return status; 3422 } 3423 3424 /* Setup SFP module if there is one present. */ 3425 if (hw->phy.sfp_setup_needed) { 3426 status = hw->mac.ops.setup_sfp(hw); 3427 hw->phy.sfp_setup_needed = false; 3428 } 3429 3430 /* Reset PHY */ 3431 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3432 hw->phy.ops.reset(hw); 3433 3434 mac_reset_top: 3435 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3436 * If link reset is used when link is up, it might reset the PHY when 3437 * mng is using it. If link is down or the flag to force full link 3438 * reset is set, then perform link reset. 3439 */ 3440 ctrl = IXGBE_CTRL_LNK_RST; 3441 3442 if (!hw->force_full_reset) { 3443 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3444 if (link_up) 3445 ctrl = IXGBE_CTRL_RST; 3446 } 3447 3448 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3449 if (status) { 3450 hw_dbg(hw, "semaphore failed with %d", status); 3451 return IXGBE_ERR_SWFW_SYNC; 3452 } 3453 3454 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3455 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3456 IXGBE_WRITE_FLUSH(hw); 3457 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3458 usleep_range(1000, 1200); 3459 3460 /* Poll for reset bit to self-clear meaning reset is complete */ 3461 for (i = 0; i < 10; i++) { 3462 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3463 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3464 break; 3465 udelay(1); 3466 } 3467 3468 if (ctrl & IXGBE_CTRL_RST_MASK) { 3469 status = IXGBE_ERR_RESET_FAILED; 3470 hw_dbg(hw, "Reset polling failed to complete.\n"); 3471 } 3472 3473 msleep(50); 3474 3475 /* Double resets are required for recovery from certain error 3476 * clear the multicast table. Also reset num_rar_entries to 128, 3477 * since we modify this value when programming the SAN MAC address. 3478 */ 3479 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3480 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3481 goto mac_reset_top; 3482 } 3483 3484 /* Store the permanent mac address */ 3485 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3486 3487 /* Store MAC address from RAR0, clear receive address registers, and 3488 * clear the multicast table. Also reset num_rar_entries to 128, 3489 * since we modify this value when programming the SAN MAC address. 3490 */ 3491 hw->mac.num_rar_entries = 128; 3492 hw->mac.ops.init_rx_addrs(hw); 3493 3494 ixgbe_set_mdio_speed(hw); 3495 3496 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3497 ixgbe_setup_mux_ctl(hw); 3498 3499 return status; 3500 } 3501 3502 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3503 * anti-spoofing 3504 * @hw: pointer to hardware structure 3505 * @enable: enable or disable switch for Ethertype anti-spoofing 3506 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3507 **/ 3508 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3509 bool enable, int vf) 3510 { 3511 int vf_target_reg = vf >> 3; 3512 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3513 u32 pfvfspoof; 3514 3515 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3516 if (enable) 3517 pfvfspoof |= BIT(vf_target_shift); 3518 else 3519 pfvfspoof &= ~BIT(vf_target_shift); 3520 3521 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3522 } 3523 3524 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3525 * @hw: pointer to hardware structure 3526 * @enable: enable or disable source address pruning 3527 * @pool: Rx pool to set source address pruning for 3528 **/ 3529 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3530 bool enable, 3531 unsigned int pool) 3532 { 3533 u64 pfflp; 3534 3535 /* max rx pool is 63 */ 3536 if (pool > 63) 3537 return; 3538 3539 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3540 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3541 3542 if (enable) 3543 pfflp |= (1ULL << pool); 3544 else 3545 pfflp &= ~(1ULL << pool); 3546 3547 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3548 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3549 } 3550 3551 /** 3552 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3553 * @hw: pointer to hardware structure 3554 * 3555 * Called at init time to set up flow control. 3556 **/ 3557 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3558 { 3559 s32 status = 0; 3560 u32 an_cntl = 0; 3561 3562 /* Validate the requested mode */ 3563 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3564 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3565 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3566 } 3567 3568 if (hw->fc.requested_mode == ixgbe_fc_default) 3569 hw->fc.requested_mode = ixgbe_fc_full; 3570 3571 /* Set up the 1G and 10G flow control advertisement registers so the 3572 * HW will be able to do FC autoneg once the cable is plugged in. If 3573 * we link at 10G, the 1G advertisement is harmless and vice versa. 3574 */ 3575 status = hw->mac.ops.read_iosf_sb_reg(hw, 3576 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3577 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3578 3579 if (status) { 3580 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3581 return status; 3582 } 3583 3584 /* The possible values of fc.requested_mode are: 3585 * 0: Flow control is completely disabled 3586 * 1: Rx flow control is enabled (we can receive pause frames, 3587 * but not send pause frames). 3588 * 2: Tx flow control is enabled (we can send pause frames but 3589 * we do not support receiving pause frames). 3590 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3591 * other: Invalid. 3592 */ 3593 switch (hw->fc.requested_mode) { 3594 case ixgbe_fc_none: 3595 /* Flow control completely disabled by software override. */ 3596 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3597 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3598 break; 3599 case ixgbe_fc_tx_pause: 3600 /* Tx Flow control is enabled, and Rx Flow control is 3601 * disabled by software override. 3602 */ 3603 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3604 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3605 break; 3606 case ixgbe_fc_rx_pause: 3607 /* Rx Flow control is enabled and Tx Flow control is 3608 * disabled by software override. Since there really 3609 * isn't a way to advertise that we are capable of RX 3610 * Pause ONLY, we will advertise that we support both 3611 * symmetric and asymmetric Rx PAUSE, as such we fall 3612 * through to the fc_full statement. Later, we will 3613 * disable the adapter's ability to send PAUSE frames. 3614 */ 3615 case ixgbe_fc_full: 3616 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3617 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3618 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3619 break; 3620 default: 3621 hw_err(hw, "Flow control param set incorrectly\n"); 3622 return IXGBE_ERR_CONFIG; 3623 } 3624 3625 status = hw->mac.ops.write_iosf_sb_reg(hw, 3626 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3627 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3628 3629 /* Restart auto-negotiation. */ 3630 status = ixgbe_restart_an_internal_phy_x550em(hw); 3631 3632 return status; 3633 } 3634 3635 /** 3636 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3637 * @hw: pointer to hardware structure 3638 * @state: set mux if 1, clear if 0 3639 */ 3640 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3641 { 3642 u32 esdp; 3643 3644 if (!hw->bus.lan_id) 3645 return; 3646 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3647 if (state) 3648 esdp |= IXGBE_ESDP_SDP1; 3649 else 3650 esdp &= ~IXGBE_ESDP_SDP1; 3651 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3652 IXGBE_WRITE_FLUSH(hw); 3653 } 3654 3655 /** 3656 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3657 * @hw: pointer to hardware structure 3658 * @mask: Mask to specify which semaphore to acquire 3659 * 3660 * Acquires the SWFW semaphore and sets the I2C MUX 3661 */ 3662 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3663 { 3664 s32 status; 3665 3666 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3667 if (status) 3668 return status; 3669 3670 if (mask & IXGBE_GSSR_I2C_MASK) 3671 ixgbe_set_mux(hw, 1); 3672 3673 return 0; 3674 } 3675 3676 /** 3677 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3678 * @hw: pointer to hardware structure 3679 * @mask: Mask to specify which semaphore to release 3680 * 3681 * Releases the SWFW semaphore and sets the I2C MUX 3682 */ 3683 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3684 { 3685 if (mask & IXGBE_GSSR_I2C_MASK) 3686 ixgbe_set_mux(hw, 0); 3687 3688 ixgbe_release_swfw_sync_X540(hw, mask); 3689 } 3690 3691 /** 3692 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3693 * @hw: pointer to hardware structure 3694 * @mask: Mask to specify which semaphore to acquire 3695 * 3696 * Acquires the SWFW semaphore and get the shared PHY token as needed 3697 */ 3698 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3699 { 3700 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3701 int retries = FW_PHY_TOKEN_RETRIES; 3702 s32 status; 3703 3704 while (--retries) { 3705 status = 0; 3706 if (hmask) 3707 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3708 if (status) 3709 return status; 3710 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3711 return 0; 3712 3713 status = ixgbe_get_phy_token(hw); 3714 if (!status) 3715 return 0; 3716 if (hmask) 3717 ixgbe_release_swfw_sync_X540(hw, hmask); 3718 if (status != IXGBE_ERR_TOKEN_RETRY) 3719 return status; 3720 msleep(FW_PHY_TOKEN_DELAY); 3721 } 3722 3723 return status; 3724 } 3725 3726 /** 3727 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3728 * @hw: pointer to hardware structure 3729 * @mask: Mask to specify which semaphore to release 3730 * 3731 * Release the SWFW semaphore and puts the shared PHY token as needed 3732 */ 3733 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3734 { 3735 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3736 3737 if (mask & IXGBE_GSSR_TOKEN_SM) 3738 ixgbe_put_phy_token(hw); 3739 3740 if (hmask) 3741 ixgbe_release_swfw_sync_X540(hw, hmask); 3742 } 3743 3744 /** 3745 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3746 * @hw: pointer to hardware structure 3747 * @reg_addr: 32 bit address of PHY register to read 3748 * @device_type: 5 bit device type 3749 * @phy_data: Pointer to read data from PHY register 3750 * 3751 * Reads a value from a specified PHY register using the SWFW lock and PHY 3752 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3753 * instances. 3754 */ 3755 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3756 u32 device_type, u16 *phy_data) 3757 { 3758 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3759 s32 status; 3760 3761 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3762 return IXGBE_ERR_SWFW_SYNC; 3763 3764 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3765 3766 hw->mac.ops.release_swfw_sync(hw, mask); 3767 3768 return status; 3769 } 3770 3771 /** 3772 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3773 * @hw: pointer to hardware structure 3774 * @reg_addr: 32 bit PHY register to write 3775 * @device_type: 5 bit device type 3776 * @phy_data: Data to write to the PHY register 3777 * 3778 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3779 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3780 */ 3781 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3782 u32 device_type, u16 phy_data) 3783 { 3784 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3785 s32 status; 3786 3787 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3788 return IXGBE_ERR_SWFW_SYNC; 3789 3790 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3791 hw->mac.ops.release_swfw_sync(hw, mask); 3792 3793 return status; 3794 } 3795 3796 #define X550_COMMON_MAC \ 3797 .init_hw = &ixgbe_init_hw_generic, \ 3798 .start_hw = &ixgbe_start_hw_X540, \ 3799 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3800 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3801 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3802 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3803 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3804 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3805 .read_analog_reg8 = NULL, \ 3806 .write_analog_reg8 = NULL, \ 3807 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3808 .check_link = &ixgbe_check_mac_link_generic, \ 3809 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3810 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3811 .set_rar = &ixgbe_set_rar_generic, \ 3812 .clear_rar = &ixgbe_clear_rar_generic, \ 3813 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3814 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3815 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3816 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3817 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3818 .enable_mc = &ixgbe_enable_mc_generic, \ 3819 .disable_mc = &ixgbe_disable_mc_generic, \ 3820 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3821 .set_vfta = &ixgbe_set_vfta_generic, \ 3822 .fc_enable = &ixgbe_fc_enable_generic, \ 3823 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3824 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3825 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3826 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3827 .set_source_address_pruning = \ 3828 &ixgbe_set_source_address_pruning_X550, \ 3829 .set_ethertype_anti_spoofing = \ 3830 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3831 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3832 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3833 .get_thermal_sensor_data = NULL, \ 3834 .init_thermal_sensor_thresh = NULL, \ 3835 .enable_rx = &ixgbe_enable_rx_generic, \ 3836 .disable_rx = &ixgbe_disable_rx_x550, \ 3837 3838 static const struct ixgbe_mac_operations mac_ops_X550 = { 3839 X550_COMMON_MAC 3840 .led_on = ixgbe_led_on_generic, 3841 .led_off = ixgbe_led_off_generic, 3842 .init_led_link_act = ixgbe_init_led_link_act_generic, 3843 .reset_hw = &ixgbe_reset_hw_X540, 3844 .get_media_type = &ixgbe_get_media_type_X540, 3845 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3846 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3847 .setup_link = &ixgbe_setup_mac_link_X540, 3848 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3849 .get_bus_info = &ixgbe_get_bus_info_generic, 3850 .setup_sfp = NULL, 3851 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3852 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3853 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3854 .prot_autoc_read = prot_autoc_read_generic, 3855 .prot_autoc_write = prot_autoc_write_generic, 3856 .setup_fc = ixgbe_setup_fc_generic, 3857 .fc_autoneg = ixgbe_fc_autoneg, 3858 }; 3859 3860 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3861 X550_COMMON_MAC 3862 .led_on = ixgbe_led_on_t_x550em, 3863 .led_off = ixgbe_led_off_t_x550em, 3864 .init_led_link_act = ixgbe_init_led_link_act_generic, 3865 .reset_hw = &ixgbe_reset_hw_X550em, 3866 .get_media_type = &ixgbe_get_media_type_X550em, 3867 .get_san_mac_addr = NULL, 3868 .get_wwn_prefix = NULL, 3869 .setup_link = &ixgbe_setup_mac_link_X540, 3870 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3871 .get_bus_info = &ixgbe_get_bus_info_X550em, 3872 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3873 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3874 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3875 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3876 .setup_fc = NULL, /* defined later */ 3877 .fc_autoneg = ixgbe_fc_autoneg, 3878 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3879 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3880 }; 3881 3882 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = { 3883 X550_COMMON_MAC 3884 .led_on = NULL, 3885 .led_off = NULL, 3886 .init_led_link_act = NULL, 3887 .reset_hw = &ixgbe_reset_hw_X550em, 3888 .get_media_type = &ixgbe_get_media_type_X550em, 3889 .get_san_mac_addr = NULL, 3890 .get_wwn_prefix = NULL, 3891 .setup_link = &ixgbe_setup_mac_link_X540, 3892 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3893 .get_bus_info = &ixgbe_get_bus_info_X550em, 3894 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3895 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3896 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3897 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3898 .setup_fc = NULL, 3899 .fc_autoneg = ixgbe_fc_autoneg, 3900 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3901 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3902 }; 3903 3904 static const struct ixgbe_mac_operations mac_ops_x550em_a = { 3905 X550_COMMON_MAC 3906 .led_on = ixgbe_led_on_t_x550em, 3907 .led_off = ixgbe_led_off_t_x550em, 3908 .init_led_link_act = ixgbe_init_led_link_act_generic, 3909 .reset_hw = ixgbe_reset_hw_X550em, 3910 .get_media_type = ixgbe_get_media_type_X550em, 3911 .get_san_mac_addr = NULL, 3912 .get_wwn_prefix = NULL, 3913 .setup_link = &ixgbe_setup_mac_link_X540, 3914 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3915 .get_bus_info = ixgbe_get_bus_info_X550em, 3916 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3917 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3918 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3919 .setup_fc = ixgbe_setup_fc_x550em, 3920 .fc_autoneg = ixgbe_fc_autoneg, 3921 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3922 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3923 }; 3924 3925 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3926 X550_COMMON_MAC 3927 .led_on = ixgbe_led_on_generic, 3928 .led_off = ixgbe_led_off_generic, 3929 .init_led_link_act = ixgbe_init_led_link_act_generic, 3930 .reset_hw = ixgbe_reset_hw_X550em, 3931 .get_media_type = ixgbe_get_media_type_X550em, 3932 .get_san_mac_addr = NULL, 3933 .get_wwn_prefix = NULL, 3934 .setup_link = NULL, /* defined later */ 3935 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3936 .get_bus_info = ixgbe_get_bus_info_X550em, 3937 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3938 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3939 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3940 .setup_fc = ixgbe_setup_fc_x550em, 3941 .fc_autoneg = ixgbe_fc_autoneg, 3942 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3943 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3944 }; 3945 3946 #define X550_COMMON_EEP \ 3947 .read = &ixgbe_read_ee_hostif_X550, \ 3948 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3949 .write = &ixgbe_write_ee_hostif_X550, \ 3950 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3951 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3952 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3953 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3954 3955 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3956 X550_COMMON_EEP 3957 .init_params = &ixgbe_init_eeprom_params_X550, 3958 }; 3959 3960 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3961 X550_COMMON_EEP 3962 .init_params = &ixgbe_init_eeprom_params_X540, 3963 }; 3964 3965 #define X550_COMMON_PHY \ 3966 .identify_sfp = &ixgbe_identify_module_generic, \ 3967 .reset = NULL, \ 3968 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3969 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3970 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3971 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3972 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3973 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3974 .setup_link = &ixgbe_setup_phy_link_generic, \ 3975 .set_phy_power = NULL, 3976 3977 static const struct ixgbe_phy_operations phy_ops_X550 = { 3978 X550_COMMON_PHY 3979 .check_overtemp = &ixgbe_tn_check_overtemp, 3980 .init = NULL, 3981 .identify = &ixgbe_identify_phy_generic, 3982 .read_reg = &ixgbe_read_phy_reg_generic, 3983 .write_reg = &ixgbe_write_phy_reg_generic, 3984 }; 3985 3986 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3987 X550_COMMON_PHY 3988 .check_overtemp = &ixgbe_tn_check_overtemp, 3989 .init = &ixgbe_init_phy_ops_X550em, 3990 .identify = &ixgbe_identify_phy_x550em, 3991 .read_reg = &ixgbe_read_phy_reg_generic, 3992 .write_reg = &ixgbe_write_phy_reg_generic, 3993 }; 3994 3995 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 3996 X550_COMMON_PHY 3997 .check_overtemp = NULL, 3998 .init = ixgbe_init_phy_ops_X550em, 3999 .identify = ixgbe_identify_phy_x550em, 4000 .read_reg = NULL, 4001 .write_reg = NULL, 4002 .read_reg_mdi = NULL, 4003 .write_reg_mdi = NULL, 4004 }; 4005 4006 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 4007 X550_COMMON_PHY 4008 .check_overtemp = &ixgbe_tn_check_overtemp, 4009 .init = &ixgbe_init_phy_ops_X550em, 4010 .identify = &ixgbe_identify_phy_x550em, 4011 .read_reg = &ixgbe_read_phy_reg_x550a, 4012 .write_reg = &ixgbe_write_phy_reg_x550a, 4013 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 4014 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 4015 }; 4016 4017 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 4018 X550_COMMON_PHY 4019 .check_overtemp = ixgbe_check_overtemp_fw, 4020 .init = ixgbe_init_phy_ops_X550em, 4021 .identify = ixgbe_identify_phy_fw, 4022 .read_reg = NULL, 4023 .write_reg = NULL, 4024 .read_reg_mdi = NULL, 4025 .write_reg_mdi = NULL, 4026 }; 4027 4028 static const struct ixgbe_link_operations link_ops_x550em_x = { 4029 .read_link = &ixgbe_read_i2c_combined_generic, 4030 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 4031 .write_link = &ixgbe_write_i2c_combined_generic, 4032 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 4033 }; 4034 4035 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 4036 IXGBE_MVALS_INIT(X550) 4037 }; 4038 4039 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 4040 IXGBE_MVALS_INIT(X550EM_x) 4041 }; 4042 4043 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 4044 IXGBE_MVALS_INIT(X550EM_a) 4045 }; 4046 4047 const struct ixgbe_info ixgbe_X550_info = { 4048 .mac = ixgbe_mac_X550, 4049 .get_invariants = &ixgbe_get_invariants_X540, 4050 .mac_ops = &mac_ops_X550, 4051 .eeprom_ops = &eeprom_ops_X550, 4052 .phy_ops = &phy_ops_X550, 4053 .mbx_ops = &mbx_ops_generic, 4054 .mvals = ixgbe_mvals_X550, 4055 }; 4056 4057 const struct ixgbe_info ixgbe_X550EM_x_info = { 4058 .mac = ixgbe_mac_X550EM_x, 4059 .get_invariants = &ixgbe_get_invariants_X550_x, 4060 .mac_ops = &mac_ops_X550EM_x, 4061 .eeprom_ops = &eeprom_ops_X550EM_x, 4062 .phy_ops = &phy_ops_X550EM_x, 4063 .mbx_ops = &mbx_ops_generic, 4064 .mvals = ixgbe_mvals_X550EM_x, 4065 .link_ops = &link_ops_x550em_x, 4066 }; 4067 4068 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 4069 .mac = ixgbe_mac_X550EM_x, 4070 .get_invariants = ixgbe_get_invariants_X550_x_fw, 4071 .mac_ops = &mac_ops_X550EM_x_fw, 4072 .eeprom_ops = &eeprom_ops_X550EM_x, 4073 .phy_ops = &phy_ops_x550em_x_fw, 4074 .mbx_ops = &mbx_ops_generic, 4075 .mvals = ixgbe_mvals_X550EM_x, 4076 }; 4077 4078 const struct ixgbe_info ixgbe_x550em_a_info = { 4079 .mac = ixgbe_mac_x550em_a, 4080 .get_invariants = &ixgbe_get_invariants_X550_a, 4081 .mac_ops = &mac_ops_x550em_a, 4082 .eeprom_ops = &eeprom_ops_X550EM_x, 4083 .phy_ops = &phy_ops_x550em_a, 4084 .mbx_ops = &mbx_ops_generic, 4085 .mvals = ixgbe_mvals_x550em_a, 4086 }; 4087 4088 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4089 .mac = ixgbe_mac_x550em_a, 4090 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4091 .mac_ops = &mac_ops_x550em_a_fw, 4092 .eeprom_ops = &eeprom_ops_X550EM_x, 4093 .phy_ops = &phy_ops_x550em_a_fw, 4094 .mbx_ops = &mbx_ops_generic, 4095 .mvals = ixgbe_mvals_x550em_a, 4096 }; 4097