1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 31 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 32 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 33 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 34 35 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 36 { 37 struct ixgbe_mac_info *mac = &hw->mac; 38 struct ixgbe_phy_info *phy = &hw->phy; 39 struct ixgbe_link_info *link = &hw->link; 40 41 /* Start with X540 invariants, since so simular */ 42 ixgbe_get_invariants_X540(hw); 43 44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 45 phy->ops.set_phy_power = NULL; 46 47 link->addr = IXGBE_CS4227; 48 49 return 0; 50 } 51 52 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 53 { 54 struct ixgbe_phy_info *phy = &hw->phy; 55 56 /* Start with X540 invariants, since so similar */ 57 ixgbe_get_invariants_X540(hw); 58 59 phy->ops.set_phy_power = NULL; 60 61 return 0; 62 } 63 64 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 65 { 66 struct ixgbe_mac_info *mac = &hw->mac; 67 struct ixgbe_phy_info *phy = &hw->phy; 68 69 /* Start with X540 invariants, since so simular */ 70 ixgbe_get_invariants_X540(hw); 71 72 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 73 phy->ops.set_phy_power = NULL; 74 75 return 0; 76 } 77 78 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 79 { 80 struct ixgbe_phy_info *phy = &hw->phy; 81 82 /* Start with X540 invariants, since so similar */ 83 ixgbe_get_invariants_X540(hw); 84 85 phy->ops.set_phy_power = NULL; 86 87 return 0; 88 } 89 90 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 91 * @hw: pointer to hardware structure 92 **/ 93 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 94 { 95 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 96 97 if (hw->bus.lan_id) { 98 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 99 esdp |= IXGBE_ESDP_SDP1_DIR; 100 } 101 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 103 IXGBE_WRITE_FLUSH(hw); 104 } 105 106 /** 107 * ixgbe_read_cs4227 - Read CS4227 register 108 * @hw: pointer to hardware structure 109 * @reg: register number to write 110 * @value: pointer to receive value read 111 * 112 * Returns status code 113 */ 114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 115 { 116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 117 } 118 119 /** 120 * ixgbe_write_cs4227 - Write CS4227 register 121 * @hw: pointer to hardware structure 122 * @reg: register number to write 123 * @value: value to write to register 124 * 125 * Returns status code 126 */ 127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 128 { 129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 130 } 131 132 /** 133 * ixgbe_read_pe - Read register from port expander 134 * @hw: pointer to hardware structure 135 * @reg: register number to read 136 * @value: pointer to receive read value 137 * 138 * Returns status code 139 */ 140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 141 { 142 s32 status; 143 144 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 145 if (status) 146 hw_err(hw, "port expander access failed with %d\n", status); 147 return status; 148 } 149 150 /** 151 * ixgbe_write_pe - Write register to port expander 152 * @hw: pointer to hardware structure 153 * @reg: register number to write 154 * @value: value to write 155 * 156 * Returns status code 157 */ 158 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 159 { 160 s32 status; 161 162 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 163 value); 164 if (status) 165 hw_err(hw, "port expander access failed with %d\n", status); 166 return status; 167 } 168 169 /** 170 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 171 * @hw: pointer to hardware structure 172 * 173 * This function assumes that the caller has acquired the proper semaphore. 174 * Returns error code 175 */ 176 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 177 { 178 s32 status; 179 u32 retry; 180 u16 value; 181 u8 reg; 182 183 /* Trigger hard reset. */ 184 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 185 if (status) 186 return status; 187 reg |= IXGBE_PE_BIT1; 188 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 189 if (status) 190 return status; 191 192 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 193 if (status) 194 return status; 195 reg &= ~IXGBE_PE_BIT1; 196 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 197 if (status) 198 return status; 199 200 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 201 if (status) 202 return status; 203 reg &= ~IXGBE_PE_BIT1; 204 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 205 if (status) 206 return status; 207 208 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 209 210 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 211 if (status) 212 return status; 213 reg |= IXGBE_PE_BIT1; 214 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 215 if (status) 216 return status; 217 218 /* Wait for the reset to complete. */ 219 msleep(IXGBE_CS4227_RESET_DELAY); 220 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 222 &value); 223 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 224 break; 225 msleep(IXGBE_CS4227_CHECK_DELAY); 226 } 227 if (retry == IXGBE_CS4227_RETRIES) { 228 hw_err(hw, "CS4227 reset did not complete\n"); 229 return IXGBE_ERR_PHY; 230 } 231 232 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 233 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 234 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 235 return IXGBE_ERR_PHY; 236 } 237 238 return 0; 239 } 240 241 /** 242 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 243 * @hw: pointer to hardware structure 244 */ 245 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 246 { 247 u32 swfw_mask = hw->phy.phy_semaphore_mask; 248 s32 status; 249 u16 value; 250 u8 retry; 251 252 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 253 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 254 if (status) { 255 hw_err(hw, "semaphore failed with %d\n", status); 256 msleep(IXGBE_CS4227_CHECK_DELAY); 257 continue; 258 } 259 260 /* Get status of reset flow. */ 261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 262 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 263 goto out; 264 265 if (status || value != IXGBE_CS4227_RESET_PENDING) 266 break; 267 268 /* Reset is pending. Wait and check again. */ 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 msleep(IXGBE_CS4227_CHECK_DELAY); 271 } 272 /* If still pending, assume other instance failed. */ 273 if (retry == IXGBE_CS4227_RETRIES) { 274 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 275 if (status) { 276 hw_err(hw, "semaphore failed with %d\n", status); 277 return; 278 } 279 } 280 281 /* Reset the CS4227. */ 282 status = ixgbe_reset_cs4227(hw); 283 if (status) { 284 hw_err(hw, "CS4227 reset failed: %d", status); 285 goto out; 286 } 287 288 /* Reset takes so long, temporarily release semaphore in case the 289 * other driver instance is waiting for the reset indication. 290 */ 291 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 292 IXGBE_CS4227_RESET_PENDING); 293 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 294 usleep_range(10000, 12000); 295 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 296 if (status) { 297 hw_err(hw, "semaphore failed with %d", status); 298 return; 299 } 300 301 /* Record completion for next time. */ 302 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 303 IXGBE_CS4227_RESET_COMPLETE); 304 305 out: 306 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 307 msleep(hw->eeprom.semaphore_delay); 308 } 309 310 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 311 * @hw: pointer to hardware structure 312 * 313 * Returns error code 314 */ 315 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 316 { 317 switch (hw->device_id) { 318 case IXGBE_DEV_ID_X550EM_A_SFP: 319 if (hw->bus.lan_id) 320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 321 else 322 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 323 return ixgbe_identify_module_generic(hw); 324 case IXGBE_DEV_ID_X550EM_X_SFP: 325 /* set up for CS4227 usage */ 326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 327 ixgbe_setup_mux_ctl(hw); 328 ixgbe_check_cs4227(hw); 329 /* Fallthrough */ 330 case IXGBE_DEV_ID_X550EM_A_SFP_N: 331 return ixgbe_identify_module_generic(hw); 332 case IXGBE_DEV_ID_X550EM_X_KX4: 333 hw->phy.type = ixgbe_phy_x550em_kx4; 334 break; 335 case IXGBE_DEV_ID_X550EM_X_XFI: 336 hw->phy.type = ixgbe_phy_x550em_xfi; 337 break; 338 case IXGBE_DEV_ID_X550EM_X_KR: 339 case IXGBE_DEV_ID_X550EM_A_KR: 340 case IXGBE_DEV_ID_X550EM_A_KR_L: 341 hw->phy.type = ixgbe_phy_x550em_kr; 342 break; 343 case IXGBE_DEV_ID_X550EM_A_10G_T: 344 if (hw->bus.lan_id) 345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 346 else 347 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 348 /* Fallthrough */ 349 case IXGBE_DEV_ID_X550EM_X_10G_T: 350 return ixgbe_identify_phy_generic(hw); 351 case IXGBE_DEV_ID_X550EM_X_1G_T: 352 hw->phy.type = ixgbe_phy_ext_1g_t; 353 break; 354 case IXGBE_DEV_ID_X550EM_A_1G_T: 355 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 356 hw->phy.type = ixgbe_phy_fw; 357 hw->phy.ops.read_reg = NULL; 358 hw->phy.ops.write_reg = NULL; 359 if (hw->bus.lan_id) 360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 361 else 362 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 363 break; 364 default: 365 break; 366 } 367 return 0; 368 } 369 370 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 371 u32 device_type, u16 *phy_data) 372 { 373 return IXGBE_NOT_IMPLEMENTED; 374 } 375 376 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 377 u32 device_type, u16 phy_data) 378 { 379 return IXGBE_NOT_IMPLEMENTED; 380 } 381 382 /** 383 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 384 * @hw: pointer to the hardware structure 385 * @addr: I2C bus address to read from 386 * @reg: I2C device register to read from 387 * @val: pointer to location to receive read value 388 * 389 * Returns an error code on error. 390 **/ 391 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 392 u16 reg, u16 *val) 393 { 394 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 395 } 396 397 /** 398 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 399 * @hw: pointer to the hardware structure 400 * @addr: I2C bus address to read from 401 * @reg: I2C device register to read from 402 * @val: pointer to location to receive read value 403 * 404 * Returns an error code on error. 405 **/ 406 static s32 407 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 408 u16 reg, u16 *val) 409 { 410 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 411 } 412 413 /** 414 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 415 * @hw: pointer to the hardware structure 416 * @addr: I2C bus address to write to 417 * @reg: I2C device register to write to 418 * @val: value to write 419 * 420 * Returns an error code on error. 421 **/ 422 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 423 u8 addr, u16 reg, u16 val) 424 { 425 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 426 } 427 428 /** 429 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 430 * @hw: pointer to the hardware structure 431 * @addr: I2C bus address to write to 432 * @reg: I2C device register to write to 433 * @val: value to write 434 * 435 * Returns an error code on error. 436 **/ 437 static s32 438 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 439 u8 addr, u16 reg, u16 val) 440 { 441 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 442 } 443 444 /** 445 * ixgbe_fw_phy_activity - Perform an activity on a PHY 446 * @hw: pointer to hardware structure 447 * @activity: activity to perform 448 * @data: Pointer to 4 32-bit words of data 449 */ 450 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 451 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 452 { 453 union { 454 struct ixgbe_hic_phy_activity_req cmd; 455 struct ixgbe_hic_phy_activity_resp rsp; 456 } hic; 457 u16 retries = FW_PHY_ACT_RETRIES; 458 s32 rc; 459 u32 i; 460 461 do { 462 memset(&hic, 0, sizeof(hic)); 463 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 464 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 465 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 466 hic.cmd.port_number = hw->bus.lan_id; 467 hic.cmd.activity_id = cpu_to_le16(activity); 468 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 469 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 470 471 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 472 IXGBE_HI_COMMAND_TIMEOUT, 473 true); 474 if (rc) 475 return rc; 476 if (hic.rsp.hdr.cmd_or_resp.ret_status == 477 FW_CEM_RESP_STATUS_SUCCESS) { 478 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 479 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 480 return 0; 481 } 482 usleep_range(20, 30); 483 --retries; 484 } while (retries > 0); 485 486 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 487 } 488 489 static const struct { 490 u16 fw_speed; 491 ixgbe_link_speed phy_speed; 492 } ixgbe_fw_map[] = { 493 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 494 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 495 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 496 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 497 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 498 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 499 }; 500 501 /** 502 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 503 * @hw: pointer to hardware structure 504 * 505 * Returns error code 506 */ 507 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 508 { 509 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 510 u16 phy_speeds; 511 u16 phy_id_lo; 512 s32 rc; 513 u16 i; 514 515 if (hw->phy.id) 516 return 0; 517 518 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 519 if (rc) 520 return rc; 521 522 hw->phy.speeds_supported = 0; 523 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 524 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 525 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 526 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 527 } 528 529 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 530 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 531 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 532 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 533 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 534 return IXGBE_ERR_PHY_ADDR_INVALID; 535 536 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 537 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 538 IXGBE_LINK_SPEED_1GB_FULL; 539 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 540 return 0; 541 } 542 543 /** 544 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 545 * @hw: pointer to hardware structure 546 * 547 * Returns error code 548 */ 549 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 550 { 551 if (hw->bus.lan_id) 552 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 553 else 554 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 555 556 hw->phy.type = ixgbe_phy_fw; 557 hw->phy.ops.read_reg = NULL; 558 hw->phy.ops.write_reg = NULL; 559 return ixgbe_get_phy_id_fw(hw); 560 } 561 562 /** 563 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 564 * @hw: pointer to hardware structure 565 * 566 * Returns error code 567 */ 568 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 569 { 570 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 571 572 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 573 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 574 } 575 576 /** 577 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 578 * @hw: pointer to hardware structure 579 */ 580 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 581 { 582 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 583 s32 rc; 584 u16 i; 585 586 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 587 return 0; 588 589 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 590 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 591 return IXGBE_ERR_INVALID_LINK_SETTINGS; 592 } 593 594 switch (hw->fc.requested_mode) { 595 case ixgbe_fc_full: 596 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 597 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 598 break; 599 case ixgbe_fc_rx_pause: 600 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 601 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 602 break; 603 case ixgbe_fc_tx_pause: 604 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 605 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 606 break; 607 default: 608 break; 609 } 610 611 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 612 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 613 setup[0] |= ixgbe_fw_map[i].fw_speed; 614 } 615 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 616 617 if (hw->phy.eee_speeds_advertised) 618 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 619 620 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 621 if (rc) 622 return rc; 623 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 624 return IXGBE_ERR_OVERTEMP; 625 return 0; 626 } 627 628 /** 629 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 630 * @hw: pointer to hardware structure 631 * 632 * Called at init time to set up flow control. 633 */ 634 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 635 { 636 if (hw->fc.requested_mode == ixgbe_fc_default) 637 hw->fc.requested_mode = ixgbe_fc_full; 638 639 return ixgbe_setup_fw_link(hw); 640 } 641 642 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 643 * @hw: pointer to hardware structure 644 * 645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 646 * ixgbe_hw struct in order to set up EEPROM access. 647 **/ 648 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 649 { 650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 651 u32 eec; 652 u16 eeprom_size; 653 654 if (eeprom->type == ixgbe_eeprom_uninitialized) { 655 eeprom->semaphore_delay = 10; 656 eeprom->type = ixgbe_flash; 657 658 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 659 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 660 IXGBE_EEC_SIZE_SHIFT); 661 eeprom->word_size = BIT(eeprom_size + 662 IXGBE_EEPROM_WORD_SIZE_SHIFT); 663 664 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 665 eeprom->type, eeprom->word_size); 666 } 667 668 return 0; 669 } 670 671 /** 672 * ixgbe_iosf_wait - Wait for IOSF command completion 673 * @hw: pointer to hardware structure 674 * @ctrl: pointer to location to receive final IOSF control value 675 * 676 * Return: failing status on timeout 677 * 678 * Note: ctrl can be NULL if the IOSF control register value is not needed 679 */ 680 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 681 { 682 u32 i, command; 683 684 /* Check every 10 usec to see if the address cycle completed. 685 * The SB IOSF BUSY bit will clear when the operation is 686 * complete. 687 */ 688 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 689 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 690 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 691 break; 692 udelay(10); 693 } 694 if (ctrl) 695 *ctrl = command; 696 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 697 hw_dbg(hw, "IOSF wait timed out\n"); 698 return IXGBE_ERR_PHY; 699 } 700 701 return 0; 702 } 703 704 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 705 * IOSF device 706 * @hw: pointer to hardware structure 707 * @reg_addr: 32 bit PHY register to write 708 * @device_type: 3 bit device type 709 * @phy_data: Pointer to read data from the register 710 **/ 711 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 712 u32 device_type, u32 *data) 713 { 714 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 715 u32 command, error; 716 s32 ret; 717 718 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 719 if (ret) 720 return ret; 721 722 ret = ixgbe_iosf_wait(hw, NULL); 723 if (ret) 724 goto out; 725 726 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 727 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 728 729 /* Write IOSF control register */ 730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 731 732 ret = ixgbe_iosf_wait(hw, &command); 733 734 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 735 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 736 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 737 hw_dbg(hw, "Failed to read, error %x\n", error); 738 return IXGBE_ERR_PHY; 739 } 740 741 if (!ret) 742 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 743 744 out: 745 hw->mac.ops.release_swfw_sync(hw, gssr); 746 return ret; 747 } 748 749 /** 750 * ixgbe_get_phy_token - Get the token for shared PHY access 751 * @hw: Pointer to hardware structure 752 */ 753 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 754 { 755 struct ixgbe_hic_phy_token_req token_cmd; 756 s32 status; 757 758 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 759 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 760 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 761 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 762 token_cmd.port_number = hw->bus.lan_id; 763 token_cmd.command_type = FW_PHY_TOKEN_REQ; 764 token_cmd.pad = 0; 765 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 766 IXGBE_HI_COMMAND_TIMEOUT, 767 true); 768 if (status) 769 return status; 770 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 771 return 0; 772 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 773 return IXGBE_ERR_FW_RESP_INVALID; 774 775 return IXGBE_ERR_TOKEN_RETRY; 776 } 777 778 /** 779 * ixgbe_put_phy_token - Put the token for shared PHY access 780 * @hw: Pointer to hardware structure 781 */ 782 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 783 { 784 struct ixgbe_hic_phy_token_req token_cmd; 785 s32 status; 786 787 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 788 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 789 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 790 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 791 token_cmd.port_number = hw->bus.lan_id; 792 token_cmd.command_type = FW_PHY_TOKEN_REL; 793 token_cmd.pad = 0; 794 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 795 IXGBE_HI_COMMAND_TIMEOUT, 796 true); 797 if (status) 798 return status; 799 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 800 return 0; 801 return IXGBE_ERR_FW_RESP_INVALID; 802 } 803 804 /** 805 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 806 * @hw: pointer to hardware structure 807 * @reg_addr: 32 bit PHY register to write 808 * @device_type: 3 bit device type 809 * @data: Data to write to the register 810 **/ 811 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 812 __always_unused u32 device_type, 813 u32 data) 814 { 815 struct ixgbe_hic_internal_phy_req write_cmd; 816 817 memset(&write_cmd, 0, sizeof(write_cmd)); 818 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 819 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 820 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 821 write_cmd.port_number = hw->bus.lan_id; 822 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 823 write_cmd.address = cpu_to_be16(reg_addr); 824 write_cmd.write_data = cpu_to_be32(data); 825 826 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 827 IXGBE_HI_COMMAND_TIMEOUT, false); 828 } 829 830 /** 831 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 832 * @hw: pointer to hardware structure 833 * @reg_addr: 32 bit PHY register to write 834 * @device_type: 3 bit device type 835 * @data: Pointer to read data from the register 836 **/ 837 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 838 __always_unused u32 device_type, 839 u32 *data) 840 { 841 union { 842 struct ixgbe_hic_internal_phy_req cmd; 843 struct ixgbe_hic_internal_phy_resp rsp; 844 } hic; 845 s32 status; 846 847 memset(&hic, 0, sizeof(hic)); 848 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 849 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 850 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 851 hic.cmd.port_number = hw->bus.lan_id; 852 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 853 hic.cmd.address = cpu_to_be16(reg_addr); 854 855 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 856 IXGBE_HI_COMMAND_TIMEOUT, true); 857 858 /* Extract the register value from the response. */ 859 *data = be32_to_cpu(hic.rsp.read_data); 860 861 return status; 862 } 863 864 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 865 * @hw: pointer to hardware structure 866 * @offset: offset of word in the EEPROM to read 867 * @words: number of words 868 * @data: word(s) read from the EEPROM 869 * 870 * Reads a 16 bit word(s) from the EEPROM using the hostif. 871 **/ 872 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 873 u16 offset, u16 words, u16 *data) 874 { 875 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 876 struct ixgbe_hic_read_shadow_ram buffer; 877 u32 current_word = 0; 878 u16 words_to_read; 879 s32 status; 880 u32 i; 881 882 /* Take semaphore for the entire operation. */ 883 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 884 if (status) { 885 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 886 return status; 887 } 888 889 while (words) { 890 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 891 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 892 else 893 words_to_read = words; 894 895 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 896 buffer.hdr.req.buf_lenh = 0; 897 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 898 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 899 900 /* convert offset from words to bytes */ 901 buffer.address = cpu_to_be32((offset + current_word) * 2); 902 buffer.length = cpu_to_be16(words_to_read * 2); 903 904 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 905 IXGBE_HI_COMMAND_TIMEOUT); 906 if (status) { 907 hw_dbg(hw, "Host interface command failed\n"); 908 goto out; 909 } 910 911 for (i = 0; i < words_to_read; i++) { 912 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 913 2 * i; 914 u32 value = IXGBE_READ_REG(hw, reg); 915 916 data[current_word] = (u16)(value & 0xffff); 917 current_word++; 918 i++; 919 if (i < words_to_read) { 920 value >>= 16; 921 data[current_word] = (u16)(value & 0xffff); 922 current_word++; 923 } 924 } 925 words -= words_to_read; 926 } 927 928 out: 929 hw->mac.ops.release_swfw_sync(hw, mask); 930 return status; 931 } 932 933 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 934 * @hw: pointer to hardware structure 935 * @ptr: pointer offset in eeprom 936 * @size: size of section pointed by ptr, if 0 first word will be used as size 937 * @csum: address of checksum to update 938 * 939 * Returns error status for any failure 940 **/ 941 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 942 u16 size, u16 *csum, u16 *buffer, 943 u32 buffer_size) 944 { 945 u16 buf[256]; 946 s32 status; 947 u16 length, bufsz, i, start; 948 u16 *local_buffer; 949 950 bufsz = sizeof(buf) / sizeof(buf[0]); 951 952 /* Read a chunk at the pointer location */ 953 if (!buffer) { 954 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 955 if (status) { 956 hw_dbg(hw, "Failed to read EEPROM image\n"); 957 return status; 958 } 959 local_buffer = buf; 960 } else { 961 if (buffer_size < ptr) 962 return IXGBE_ERR_PARAM; 963 local_buffer = &buffer[ptr]; 964 } 965 966 if (size) { 967 start = 0; 968 length = size; 969 } else { 970 start = 1; 971 length = local_buffer[0]; 972 973 /* Skip pointer section if length is invalid. */ 974 if (length == 0xFFFF || length == 0 || 975 (ptr + length) >= hw->eeprom.word_size) 976 return 0; 977 } 978 979 if (buffer && ((u32)start + (u32)length > buffer_size)) 980 return IXGBE_ERR_PARAM; 981 982 for (i = start; length; i++, length--) { 983 if (i == bufsz && !buffer) { 984 ptr += bufsz; 985 i = 0; 986 if (length < bufsz) 987 bufsz = length; 988 989 /* Read a chunk at the pointer location */ 990 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 991 bufsz, buf); 992 if (status) { 993 hw_dbg(hw, "Failed to read EEPROM image\n"); 994 return status; 995 } 996 } 997 *csum += local_buffer[i]; 998 } 999 return 0; 1000 } 1001 1002 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 1003 * @hw: pointer to hardware structure 1004 * @buffer: pointer to buffer containing calculated checksum 1005 * @buffer_size: size of buffer 1006 * 1007 * Returns a negative error code on error, or the 16-bit checksum 1008 **/ 1009 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 1010 u32 buffer_size) 1011 { 1012 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 1013 u16 *local_buffer; 1014 s32 status; 1015 u16 checksum = 0; 1016 u16 pointer, i, size; 1017 1018 hw->eeprom.ops.init_params(hw); 1019 1020 if (!buffer) { 1021 /* Read pointer area */ 1022 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1023 IXGBE_EEPROM_LAST_WORD + 1, 1024 eeprom_ptrs); 1025 if (status) { 1026 hw_dbg(hw, "Failed to read EEPROM image\n"); 1027 return status; 1028 } 1029 local_buffer = eeprom_ptrs; 1030 } else { 1031 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1032 return IXGBE_ERR_PARAM; 1033 local_buffer = buffer; 1034 } 1035 1036 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1037 * checksum word itself 1038 */ 1039 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1040 if (i != IXGBE_EEPROM_CHECKSUM) 1041 checksum += local_buffer[i]; 1042 1043 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1044 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1045 */ 1046 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1047 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1048 continue; 1049 1050 pointer = local_buffer[i]; 1051 1052 /* Skip pointer section if the pointer is invalid. */ 1053 if (pointer == 0xFFFF || pointer == 0 || 1054 pointer >= hw->eeprom.word_size) 1055 continue; 1056 1057 switch (i) { 1058 case IXGBE_PCIE_GENERAL_PTR: 1059 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1060 break; 1061 case IXGBE_PCIE_CONFIG0_PTR: 1062 case IXGBE_PCIE_CONFIG1_PTR: 1063 size = IXGBE_PCIE_CONFIG_SIZE; 1064 break; 1065 default: 1066 size = 0; 1067 break; 1068 } 1069 1070 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1071 buffer, buffer_size); 1072 if (status) 1073 return status; 1074 } 1075 1076 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1077 1078 return (s32)checksum; 1079 } 1080 1081 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1082 * @hw: pointer to hardware structure 1083 * 1084 * Returns a negative error code on error, or the 16-bit checksum 1085 **/ 1086 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1087 { 1088 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1089 } 1090 1091 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1092 * @hw: pointer to hardware structure 1093 * @offset: offset of word in the EEPROM to read 1094 * @data: word read from the EEPROM 1095 * 1096 * Reads a 16 bit word from the EEPROM using the hostif. 1097 **/ 1098 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1099 { 1100 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1101 struct ixgbe_hic_read_shadow_ram buffer; 1102 s32 status; 1103 1104 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1105 buffer.hdr.req.buf_lenh = 0; 1106 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1107 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1108 1109 /* convert offset from words to bytes */ 1110 buffer.address = cpu_to_be32(offset * 2); 1111 /* one word */ 1112 buffer.length = cpu_to_be16(sizeof(u16)); 1113 1114 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1115 if (status) 1116 return status; 1117 1118 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1119 IXGBE_HI_COMMAND_TIMEOUT); 1120 if (!status) { 1121 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1122 FW_NVM_DATA_OFFSET); 1123 } 1124 1125 hw->mac.ops.release_swfw_sync(hw, mask); 1126 return status; 1127 } 1128 1129 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1130 * @hw: pointer to hardware structure 1131 * @checksum_val: calculated checksum 1132 * 1133 * Performs checksum calculation and validates the EEPROM checksum. If the 1134 * caller does not need checksum_val, the value can be NULL. 1135 **/ 1136 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1137 u16 *checksum_val) 1138 { 1139 s32 status; 1140 u16 checksum; 1141 u16 read_checksum = 0; 1142 1143 /* Read the first word from the EEPROM. If this times out or fails, do 1144 * not continue or we could be in for a very long wait while every 1145 * EEPROM read fails 1146 */ 1147 status = hw->eeprom.ops.read(hw, 0, &checksum); 1148 if (status) { 1149 hw_dbg(hw, "EEPROM read failed\n"); 1150 return status; 1151 } 1152 1153 status = hw->eeprom.ops.calc_checksum(hw); 1154 if (status < 0) 1155 return status; 1156 1157 checksum = (u16)(status & 0xffff); 1158 1159 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1160 &read_checksum); 1161 if (status) 1162 return status; 1163 1164 /* Verify read checksum from EEPROM is the same as 1165 * calculated checksum 1166 */ 1167 if (read_checksum != checksum) { 1168 status = IXGBE_ERR_EEPROM_CHECKSUM; 1169 hw_dbg(hw, "Invalid EEPROM checksum"); 1170 } 1171 1172 /* If the user cares, return the calculated checksum */ 1173 if (checksum_val) 1174 *checksum_val = checksum; 1175 1176 return status; 1177 } 1178 1179 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1180 * @hw: pointer to hardware structure 1181 * @offset: offset of word in the EEPROM to write 1182 * @data: word write to the EEPROM 1183 * 1184 * Write a 16 bit word to the EEPROM using the hostif. 1185 **/ 1186 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1187 u16 data) 1188 { 1189 s32 status; 1190 struct ixgbe_hic_write_shadow_ram buffer; 1191 1192 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1193 buffer.hdr.req.buf_lenh = 0; 1194 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1195 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1196 1197 /* one word */ 1198 buffer.length = cpu_to_be16(sizeof(u16)); 1199 buffer.data = data; 1200 buffer.address = cpu_to_be32(offset * 2); 1201 1202 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1203 IXGBE_HI_COMMAND_TIMEOUT, false); 1204 return status; 1205 } 1206 1207 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1208 * @hw: pointer to hardware structure 1209 * @offset: offset of word in the EEPROM to write 1210 * @data: word write to the EEPROM 1211 * 1212 * Write a 16 bit word to the EEPROM using the hostif. 1213 **/ 1214 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1215 { 1216 s32 status = 0; 1217 1218 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1219 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1220 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1221 } else { 1222 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1223 status = IXGBE_ERR_SWFW_SYNC; 1224 } 1225 1226 return status; 1227 } 1228 1229 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1230 * @hw: pointer to hardware structure 1231 * 1232 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1233 **/ 1234 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1235 { 1236 s32 status = 0; 1237 union ixgbe_hic_hdr2 buffer; 1238 1239 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1240 buffer.req.buf_lenh = 0; 1241 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1242 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1243 1244 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1245 IXGBE_HI_COMMAND_TIMEOUT, false); 1246 return status; 1247 } 1248 1249 /** 1250 * ixgbe_get_bus_info_X550em - Set PCI bus info 1251 * @hw: pointer to hardware structure 1252 * 1253 * Sets bus link width and speed to unknown because X550em is 1254 * not a PCI device. 1255 **/ 1256 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1257 { 1258 hw->bus.type = ixgbe_bus_type_internal; 1259 hw->bus.width = ixgbe_bus_width_unknown; 1260 hw->bus.speed = ixgbe_bus_speed_unknown; 1261 1262 hw->mac.ops.set_lan_id(hw); 1263 1264 return 0; 1265 } 1266 1267 /** ixgbe_disable_rx_x550 - Disable RX unit 1268 * 1269 * Enables the Rx DMA unit for x550 1270 **/ 1271 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1272 { 1273 u32 rxctrl, pfdtxgswc; 1274 s32 status; 1275 struct ixgbe_hic_disable_rxen fw_cmd; 1276 1277 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1278 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1279 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1280 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1281 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1282 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1283 hw->mac.set_lben = true; 1284 } else { 1285 hw->mac.set_lben = false; 1286 } 1287 1288 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1289 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1290 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1291 fw_cmd.port_number = hw->bus.lan_id; 1292 1293 status = ixgbe_host_interface_command(hw, &fw_cmd, 1294 sizeof(struct ixgbe_hic_disable_rxen), 1295 IXGBE_HI_COMMAND_TIMEOUT, true); 1296 1297 /* If we fail - disable RX using register write */ 1298 if (status) { 1299 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1300 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1301 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1303 } 1304 } 1305 } 1306 } 1307 1308 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1309 * @hw: pointer to hardware structure 1310 * 1311 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1312 * checksum and updates the EEPROM and instructs the hardware to update 1313 * the flash. 1314 **/ 1315 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1316 { 1317 s32 status; 1318 u16 checksum = 0; 1319 1320 /* Read the first word from the EEPROM. If this times out or fails, do 1321 * not continue or we could be in for a very long wait while every 1322 * EEPROM read fails 1323 */ 1324 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1325 if (status) { 1326 hw_dbg(hw, "EEPROM read failed\n"); 1327 return status; 1328 } 1329 1330 status = ixgbe_calc_eeprom_checksum_X550(hw); 1331 if (status < 0) 1332 return status; 1333 1334 checksum = (u16)(status & 0xffff); 1335 1336 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1337 checksum); 1338 if (status) 1339 return status; 1340 1341 status = ixgbe_update_flash_X550(hw); 1342 1343 return status; 1344 } 1345 1346 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1347 * @hw: pointer to hardware structure 1348 * @offset: offset of word in the EEPROM to write 1349 * @words: number of words 1350 * @data: word(s) write to the EEPROM 1351 * 1352 * 1353 * Write a 16 bit word(s) to the EEPROM using the hostif. 1354 **/ 1355 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1356 u16 offset, u16 words, 1357 u16 *data) 1358 { 1359 s32 status = 0; 1360 u32 i = 0; 1361 1362 /* Take semaphore for the entire operation. */ 1363 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1364 if (status) { 1365 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1366 return status; 1367 } 1368 1369 for (i = 0; i < words; i++) { 1370 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1371 data[i]); 1372 if (status) { 1373 hw_dbg(hw, "Eeprom buffered write failed\n"); 1374 break; 1375 } 1376 } 1377 1378 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1379 1380 return status; 1381 } 1382 1383 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1384 * IOSF device 1385 * 1386 * @hw: pointer to hardware structure 1387 * @reg_addr: 32 bit PHY register to write 1388 * @device_type: 3 bit device type 1389 * @data: Data to write to the register 1390 **/ 1391 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1392 u32 device_type, u32 data) 1393 { 1394 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1395 u32 command, error; 1396 s32 ret; 1397 1398 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1399 if (ret) 1400 return ret; 1401 1402 ret = ixgbe_iosf_wait(hw, NULL); 1403 if (ret) 1404 goto out; 1405 1406 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1407 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1408 1409 /* Write IOSF control register */ 1410 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1411 1412 /* Write IOSF data register */ 1413 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1414 1415 ret = ixgbe_iosf_wait(hw, &command); 1416 1417 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1418 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1419 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1420 hw_dbg(hw, "Failed to write, error %x\n", error); 1421 return IXGBE_ERR_PHY; 1422 } 1423 1424 out: 1425 hw->mac.ops.release_swfw_sync(hw, gssr); 1426 return ret; 1427 } 1428 1429 /** 1430 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1431 * @hw: pointer to hardware structure 1432 * 1433 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1434 **/ 1435 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1436 { 1437 s32 status; 1438 u32 reg_val; 1439 1440 /* Disable training protocol FSM. */ 1441 status = ixgbe_read_iosf_sb_reg_x550(hw, 1442 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1443 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1444 if (status) 1445 return status; 1446 1447 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1448 status = ixgbe_write_iosf_sb_reg_x550(hw, 1449 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1450 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1451 if (status) 1452 return status; 1453 1454 /* Disable Flex from training TXFFE. */ 1455 status = ixgbe_read_iosf_sb_reg_x550(hw, 1456 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1457 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1458 if (status) 1459 return status; 1460 1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1462 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1464 status = ixgbe_write_iosf_sb_reg_x550(hw, 1465 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1466 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1467 if (status) 1468 return status; 1469 1470 status = ixgbe_read_iosf_sb_reg_x550(hw, 1471 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1472 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1473 if (status) 1474 return status; 1475 1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1477 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1479 status = ixgbe_write_iosf_sb_reg_x550(hw, 1480 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1481 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1482 if (status) 1483 return status; 1484 1485 /* Enable override for coefficients. */ 1486 status = ixgbe_read_iosf_sb_reg_x550(hw, 1487 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1488 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1489 if (status) 1490 return status; 1491 1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1496 status = ixgbe_write_iosf_sb_reg_x550(hw, 1497 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1498 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1499 return status; 1500 } 1501 1502 /** 1503 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1504 * internal PHY 1505 * @hw: pointer to hardware structure 1506 **/ 1507 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1508 { 1509 s32 status; 1510 u32 link_ctrl; 1511 1512 /* Restart auto-negotiation. */ 1513 status = hw->mac.ops.read_iosf_sb_reg(hw, 1514 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1515 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1516 1517 if (status) { 1518 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1519 return status; 1520 } 1521 1522 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1523 status = hw->mac.ops.write_iosf_sb_reg(hw, 1524 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1525 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1526 1527 if (hw->mac.type == ixgbe_mac_x550em_a) { 1528 u32 flx_mask_st20; 1529 1530 /* Indicate to FW that AN restart has been asserted */ 1531 status = hw->mac.ops.read_iosf_sb_reg(hw, 1532 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1533 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1534 1535 if (status) { 1536 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1537 return status; 1538 } 1539 1540 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1541 status = hw->mac.ops.write_iosf_sb_reg(hw, 1542 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1543 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1544 } 1545 1546 return status; 1547 } 1548 1549 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1550 * @hw: pointer to hardware structure 1551 * @speed: the link speed to force 1552 * 1553 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1554 * internal and external PHY at a specific speed, without autonegotiation. 1555 **/ 1556 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1557 { 1558 s32 status; 1559 u32 reg_val; 1560 1561 /* Disable AN and force speed to 10G Serial. */ 1562 status = ixgbe_read_iosf_sb_reg_x550(hw, 1563 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1564 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1565 if (status) 1566 return status; 1567 1568 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1569 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1570 1571 /* Select forced link speed for internal PHY. */ 1572 switch (*speed) { 1573 case IXGBE_LINK_SPEED_10GB_FULL: 1574 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1575 break; 1576 case IXGBE_LINK_SPEED_1GB_FULL: 1577 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1578 break; 1579 default: 1580 /* Other link speeds are not supported by internal KR PHY. */ 1581 return IXGBE_ERR_LINK_SETUP; 1582 } 1583 1584 status = ixgbe_write_iosf_sb_reg_x550(hw, 1585 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1586 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1587 if (status) 1588 return status; 1589 1590 /* Additional configuration needed for x550em_x */ 1591 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1592 status = ixgbe_setup_ixfi_x550em_x(hw); 1593 if (status) 1594 return status; 1595 } 1596 1597 /* Toggle port SW reset by AN reset. */ 1598 status = ixgbe_restart_an_internal_phy_x550em(hw); 1599 1600 return status; 1601 } 1602 1603 /** 1604 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1605 * @hw: pointer to hardware structure 1606 * @linear: true if SFP module is linear 1607 */ 1608 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1609 { 1610 switch (hw->phy.sfp_type) { 1611 case ixgbe_sfp_type_not_present: 1612 return IXGBE_ERR_SFP_NOT_PRESENT; 1613 case ixgbe_sfp_type_da_cu_core0: 1614 case ixgbe_sfp_type_da_cu_core1: 1615 *linear = true; 1616 break; 1617 case ixgbe_sfp_type_srlr_core0: 1618 case ixgbe_sfp_type_srlr_core1: 1619 case ixgbe_sfp_type_da_act_lmt_core0: 1620 case ixgbe_sfp_type_da_act_lmt_core1: 1621 case ixgbe_sfp_type_1g_sx_core0: 1622 case ixgbe_sfp_type_1g_sx_core1: 1623 case ixgbe_sfp_type_1g_lx_core0: 1624 case ixgbe_sfp_type_1g_lx_core1: 1625 *linear = false; 1626 break; 1627 case ixgbe_sfp_type_unknown: 1628 case ixgbe_sfp_type_1g_cu_core0: 1629 case ixgbe_sfp_type_1g_cu_core1: 1630 default: 1631 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1632 } 1633 1634 return 0; 1635 } 1636 1637 /** 1638 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1639 * @hw: pointer to hardware structure 1640 * 1641 * Configures the extern PHY and the integrated KR PHY for SFP support. 1642 */ 1643 static s32 1644 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1645 ixgbe_link_speed speed, 1646 __always_unused bool autoneg_wait_to_complete) 1647 { 1648 s32 status; 1649 u16 reg_slice, reg_val; 1650 bool setup_linear = false; 1651 1652 /* Check if SFP module is supported and linear */ 1653 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1654 1655 /* If no SFP module present, then return success. Return success since 1656 * there is no reason to configure CS4227 and SFP not present error is 1657 * not accepted in the setup MAC link flow. 1658 */ 1659 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 1660 return 0; 1661 1662 if (status) 1663 return status; 1664 1665 /* Configure internal PHY for KR/KX. */ 1666 ixgbe_setup_kr_speed_x550em(hw, speed); 1667 1668 /* Configure CS4227 LINE side to proper mode. */ 1669 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1670 if (setup_linear) 1671 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1672 else 1673 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1674 1675 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1676 reg_val); 1677 1678 return status; 1679 } 1680 1681 /** 1682 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1683 * @hw: pointer to hardware structure 1684 * @speed: the link speed to force 1685 * 1686 * Configures the integrated PHY for native SFI mode. Used to connect the 1687 * internal PHY directly to an SFP cage, without autonegotiation. 1688 **/ 1689 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1690 { 1691 struct ixgbe_mac_info *mac = &hw->mac; 1692 s32 status; 1693 u32 reg_val; 1694 1695 /* Disable all AN and force speed to 10G Serial. */ 1696 status = mac->ops.read_iosf_sb_reg(hw, 1697 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1698 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1699 if (status) 1700 return status; 1701 1702 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1703 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1704 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1705 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1706 1707 /* Select forced link speed for internal PHY. */ 1708 switch (*speed) { 1709 case IXGBE_LINK_SPEED_10GB_FULL: 1710 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1711 break; 1712 case IXGBE_LINK_SPEED_1GB_FULL: 1713 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1714 break; 1715 default: 1716 /* Other link speeds are not supported by internal PHY. */ 1717 return IXGBE_ERR_LINK_SETUP; 1718 } 1719 1720 status = mac->ops.write_iosf_sb_reg(hw, 1721 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1722 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1723 1724 /* Toggle port SW reset by AN reset. */ 1725 status = ixgbe_restart_an_internal_phy_x550em(hw); 1726 1727 return status; 1728 } 1729 1730 /** 1731 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1732 * @hw: pointer to hardware structure 1733 * 1734 * Configure the the integrated PHY for native SFP support. 1735 */ 1736 static s32 1737 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1738 __always_unused bool autoneg_wait_to_complete) 1739 { 1740 bool setup_linear = false; 1741 u32 reg_phy_int; 1742 s32 ret_val; 1743 1744 /* Check if SFP module is supported and linear */ 1745 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1746 1747 /* If no SFP module present, then return success. Return success since 1748 * SFP not present error is not excepted in the setup MAC link flow. 1749 */ 1750 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1751 return 0; 1752 1753 if (ret_val) 1754 return ret_val; 1755 1756 /* Configure internal PHY for native SFI based on module type */ 1757 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1758 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1759 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1760 if (ret_val) 1761 return ret_val; 1762 1763 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1764 if (!setup_linear) 1765 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1766 1767 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1768 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1769 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1770 if (ret_val) 1771 return ret_val; 1772 1773 /* Setup SFI internal link. */ 1774 return ixgbe_setup_sfi_x550a(hw, &speed); 1775 } 1776 1777 /** 1778 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1779 * @hw: pointer to hardware structure 1780 * 1781 * Configure the the integrated PHY for SFP support. 1782 */ 1783 static s32 1784 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1785 __always_unused bool autoneg_wait_to_complete) 1786 { 1787 u32 reg_slice, slice_offset; 1788 bool setup_linear = false; 1789 u16 reg_phy_ext; 1790 s32 ret_val; 1791 1792 /* Check if SFP module is supported and linear */ 1793 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1794 1795 /* If no SFP module present, then return success. Return success since 1796 * SFP not present error is not excepted in the setup MAC link flow. 1797 */ 1798 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1799 return 0; 1800 1801 if (ret_val) 1802 return ret_val; 1803 1804 /* Configure internal PHY for KR/KX. */ 1805 ixgbe_setup_kr_speed_x550em(hw, speed); 1806 1807 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1808 return IXGBE_ERR_PHY_ADDR_INVALID; 1809 1810 /* Get external PHY SKU id */ 1811 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 1812 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1813 if (ret_val) 1814 return ret_val; 1815 1816 /* When configuring quad port CS4223, the MAC instance is part 1817 * of the slice offset. 1818 */ 1819 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 1820 slice_offset = (hw->bus.lan_id + 1821 (hw->bus.instance_id << 1)) << 12; 1822 else 1823 slice_offset = hw->bus.lan_id << 12; 1824 1825 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1826 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1827 1828 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 1829 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1830 if (ret_val) 1831 return ret_val; 1832 1833 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1834 (IXGBE_CS4227_EDC_MODE_SR << 1)); 1835 1836 if (setup_linear) 1837 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1838 else 1839 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1840 1841 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 1842 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 1843 if (ret_val) 1844 return ret_val; 1845 1846 /* Flush previous write with a read */ 1847 return hw->phy.ops.read_reg(hw, reg_slice, 1848 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1849 } 1850 1851 /** 1852 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1853 * @hw: pointer to hardware structure 1854 * @speed: new link speed 1855 * @autoneg_wait_to_complete: true when waiting for completion is needed 1856 * 1857 * Setup internal/external PHY link speed based on link speed, then set 1858 * external PHY auto advertised link speed. 1859 * 1860 * Returns error status for any failure 1861 **/ 1862 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1863 ixgbe_link_speed speed, 1864 bool autoneg_wait) 1865 { 1866 s32 status; 1867 ixgbe_link_speed force_speed; 1868 1869 /* Setup internal/external PHY link speed to iXFI (10G), unless 1870 * only 1G is auto advertised then setup KX link. 1871 */ 1872 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1873 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1874 else 1875 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1876 1877 /* If internal link mode is XFI, then setup XFI internal link. */ 1878 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1879 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1880 1881 if (status) 1882 return status; 1883 } 1884 1885 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1886 } 1887 1888 /** ixgbe_check_link_t_X550em - Determine link and speed status 1889 * @hw: pointer to hardware structure 1890 * @speed: pointer to link speed 1891 * @link_up: true when link is up 1892 * @link_up_wait_to_complete: bool used to wait for link up or not 1893 * 1894 * Check that both the MAC and X557 external PHY have link. 1895 **/ 1896 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1897 ixgbe_link_speed *speed, 1898 bool *link_up, 1899 bool link_up_wait_to_complete) 1900 { 1901 u32 status; 1902 u16 i, autoneg_status; 1903 1904 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1905 return IXGBE_ERR_CONFIG; 1906 1907 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1908 link_up_wait_to_complete); 1909 1910 /* If check link fails or MAC link is not up, then return */ 1911 if (status || !(*link_up)) 1912 return status; 1913 1914 /* MAC link is up, so check external PHY link. 1915 * Link status is latching low, and can only be used to detect link 1916 * drop, and not the current status of the link without performing 1917 * back-to-back reads. 1918 */ 1919 for (i = 0; i < 2; i++) { 1920 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1921 &autoneg_status); 1922 1923 if (status) 1924 return status; 1925 } 1926 1927 /* If external PHY link is not up, then indicate link not up */ 1928 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1929 *link_up = false; 1930 1931 return 0; 1932 } 1933 1934 /** 1935 * ixgbe_setup_sgmii - Set up link for sgmii 1936 * @hw: pointer to hardware structure 1937 */ 1938 static s32 1939 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1940 __always_unused bool autoneg_wait_to_complete) 1941 { 1942 struct ixgbe_mac_info *mac = &hw->mac; 1943 u32 lval, sval, flx_val; 1944 s32 rc; 1945 1946 rc = mac->ops.read_iosf_sb_reg(hw, 1947 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1948 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1949 if (rc) 1950 return rc; 1951 1952 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1953 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1954 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1955 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1956 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1957 rc = mac->ops.write_iosf_sb_reg(hw, 1958 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1959 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1960 if (rc) 1961 return rc; 1962 1963 rc = mac->ops.read_iosf_sb_reg(hw, 1964 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1965 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1966 if (rc) 1967 return rc; 1968 1969 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1970 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1971 rc = mac->ops.write_iosf_sb_reg(hw, 1972 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1973 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1974 if (rc) 1975 return rc; 1976 1977 rc = mac->ops.read_iosf_sb_reg(hw, 1978 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1979 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1980 if (rc) 1981 return rc; 1982 1983 rc = mac->ops.read_iosf_sb_reg(hw, 1984 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1985 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1986 if (rc) 1987 return rc; 1988 1989 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1990 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1991 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1992 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1993 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1994 1995 rc = mac->ops.write_iosf_sb_reg(hw, 1996 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1997 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1998 if (rc) 1999 return rc; 2000 2001 rc = ixgbe_restart_an_internal_phy_x550em(hw); 2002 return rc; 2003 } 2004 2005 /** 2006 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 2007 * @hw: pointer to hardware structure 2008 */ 2009 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 2010 bool autoneg_wait) 2011 { 2012 struct ixgbe_mac_info *mac = &hw->mac; 2013 u32 lval, sval, flx_val; 2014 s32 rc; 2015 2016 rc = mac->ops.read_iosf_sb_reg(hw, 2017 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2018 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2019 if (rc) 2020 return rc; 2021 2022 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2023 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2024 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2025 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2026 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2027 rc = mac->ops.write_iosf_sb_reg(hw, 2028 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2029 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2030 if (rc) 2031 return rc; 2032 2033 rc = mac->ops.read_iosf_sb_reg(hw, 2034 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2035 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2036 if (rc) 2037 return rc; 2038 2039 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2040 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2041 rc = mac->ops.write_iosf_sb_reg(hw, 2042 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2043 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2044 if (rc) 2045 return rc; 2046 2047 rc = mac->ops.write_iosf_sb_reg(hw, 2048 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2049 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2050 if (rc) 2051 return rc; 2052 2053 rc = mac->ops.read_iosf_sb_reg(hw, 2054 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2055 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2056 if (rc) 2057 return rc; 2058 2059 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2060 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2061 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2062 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2063 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2064 2065 rc = mac->ops.write_iosf_sb_reg(hw, 2066 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2067 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2068 if (rc) 2069 return rc; 2070 2071 ixgbe_restart_an_internal_phy_x550em(hw); 2072 2073 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2074 } 2075 2076 /** 2077 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2078 * @hw: pointer to hardware structure 2079 * 2080 * Enable flow control according to IEEE clause 37. 2081 */ 2082 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2083 { 2084 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2085 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2086 ixgbe_link_speed speed; 2087 bool link_up; 2088 2089 /* AN should have completed when the cable was plugged in. 2090 * Look for reasons to bail out. Bail out if: 2091 * - FC autoneg is disabled, or if 2092 * - link is not up. 2093 */ 2094 if (hw->fc.disable_fc_autoneg) 2095 goto out; 2096 2097 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2098 if (!link_up) 2099 goto out; 2100 2101 /* Check if auto-negotiation has completed */ 2102 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2103 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2104 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2105 goto out; 2106 } 2107 2108 /* Negotiate the flow control */ 2109 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2110 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2111 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2112 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2113 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2114 2115 out: 2116 if (!status) { 2117 hw->fc.fc_was_autonegged = true; 2118 } else { 2119 hw->fc.fc_was_autonegged = false; 2120 hw->fc.current_mode = hw->fc.requested_mode; 2121 } 2122 } 2123 2124 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2125 * @hw: pointer to hardware structure 2126 **/ 2127 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2128 { 2129 struct ixgbe_mac_info *mac = &hw->mac; 2130 2131 switch (mac->ops.get_media_type(hw)) { 2132 case ixgbe_media_type_fiber: 2133 mac->ops.setup_fc = NULL; 2134 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2135 break; 2136 case ixgbe_media_type_copper: 2137 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2138 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2139 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2140 break; 2141 } 2142 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2143 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2144 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2145 mac->ops.check_link = ixgbe_check_mac_link_generic; 2146 break; 2147 case ixgbe_media_type_backplane: 2148 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2149 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2150 break; 2151 default: 2152 break; 2153 } 2154 } 2155 2156 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2157 * @hw: pointer to hardware structure 2158 **/ 2159 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2160 { 2161 struct ixgbe_mac_info *mac = &hw->mac; 2162 2163 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2164 2165 switch (mac->ops.get_media_type(hw)) { 2166 case ixgbe_media_type_fiber: 2167 /* CS4227 does not support autoneg, so disable the laser control 2168 * functions for SFP+ fiber 2169 */ 2170 mac->ops.disable_tx_laser = NULL; 2171 mac->ops.enable_tx_laser = NULL; 2172 mac->ops.flap_tx_laser = NULL; 2173 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2174 switch (hw->device_id) { 2175 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2176 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2177 break; 2178 case IXGBE_DEV_ID_X550EM_A_SFP: 2179 mac->ops.setup_mac_link = 2180 ixgbe_setup_mac_link_sfp_x550a; 2181 break; 2182 default: 2183 mac->ops.setup_mac_link = 2184 ixgbe_setup_mac_link_sfp_x550em; 2185 break; 2186 } 2187 mac->ops.set_rate_select_speed = 2188 ixgbe_set_soft_rate_select_speed; 2189 break; 2190 case ixgbe_media_type_copper: 2191 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2192 break; 2193 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2194 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2195 mac->ops.check_link = ixgbe_check_link_t_X550em; 2196 break; 2197 case ixgbe_media_type_backplane: 2198 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2199 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2200 mac->ops.setup_link = ixgbe_setup_sgmii; 2201 break; 2202 default: 2203 break; 2204 } 2205 2206 /* Additional modification for X550em_a devices */ 2207 if (hw->mac.type == ixgbe_mac_x550em_a) 2208 ixgbe_init_mac_link_ops_X550em_a(hw); 2209 } 2210 2211 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2212 * @hw: pointer to hardware structure 2213 */ 2214 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2215 { 2216 s32 status; 2217 bool linear; 2218 2219 /* Check if SFP module is supported */ 2220 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2221 if (status) 2222 return status; 2223 2224 ixgbe_init_mac_link_ops_X550em(hw); 2225 hw->phy.ops.reset = NULL; 2226 2227 return 0; 2228 } 2229 2230 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2231 * @hw: pointer to hardware structure 2232 * @speed: pointer to link speed 2233 * @autoneg: true when autoneg or autotry is enabled 2234 **/ 2235 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2236 ixgbe_link_speed *speed, 2237 bool *autoneg) 2238 { 2239 if (hw->phy.type == ixgbe_phy_fw) { 2240 *autoneg = true; 2241 *speed = hw->phy.speeds_supported; 2242 return 0; 2243 } 2244 2245 /* SFP */ 2246 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2247 /* CS4227 SFP must not enable auto-negotiation */ 2248 *autoneg = false; 2249 2250 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2251 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 2252 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2253 return 0; 2254 } 2255 2256 /* Link capabilities are based on SFP */ 2257 if (hw->phy.multispeed_fiber) 2258 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2259 IXGBE_LINK_SPEED_1GB_FULL; 2260 else 2261 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2262 } else { 2263 switch (hw->phy.type) { 2264 case ixgbe_phy_x550em_kx4: 2265 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2266 IXGBE_LINK_SPEED_2_5GB_FULL | 2267 IXGBE_LINK_SPEED_10GB_FULL; 2268 break; 2269 case ixgbe_phy_x550em_xfi: 2270 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2271 IXGBE_LINK_SPEED_10GB_FULL; 2272 break; 2273 case ixgbe_phy_ext_1g_t: 2274 case ixgbe_phy_sgmii: 2275 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2276 break; 2277 case ixgbe_phy_x550em_kr: 2278 if (hw->mac.type == ixgbe_mac_x550em_a) { 2279 /* check different backplane modes */ 2280 if (hw->phy.nw_mng_if_sel & 2281 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2282 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2283 break; 2284 } else if (hw->device_id == 2285 IXGBE_DEV_ID_X550EM_A_KR_L) { 2286 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2287 break; 2288 } 2289 } 2290 /* fall through */ 2291 default: 2292 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2293 IXGBE_LINK_SPEED_1GB_FULL; 2294 break; 2295 } 2296 *autoneg = true; 2297 } 2298 return 0; 2299 } 2300 2301 /** 2302 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2303 * @hw: pointer to hardware structure 2304 * @lsc: pointer to boolean flag which indicates whether external Base T 2305 * PHY interrupt is lsc 2306 * 2307 * Determime if external Base T PHY interrupt cause is high temperature 2308 * failure alarm or link status change. 2309 * 2310 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2311 * failure alarm, else return PHY access status. 2312 **/ 2313 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2314 { 2315 u32 status; 2316 u16 reg; 2317 2318 *lsc = false; 2319 2320 /* Vendor alarm triggered */ 2321 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2322 MDIO_MMD_VEND1, 2323 ®); 2324 2325 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2326 return status; 2327 2328 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2329 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2330 MDIO_MMD_VEND1, 2331 ®); 2332 2333 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2334 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2335 return status; 2336 2337 /* Global alarm triggered */ 2338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2339 MDIO_MMD_VEND1, 2340 ®); 2341 2342 if (status) 2343 return status; 2344 2345 /* If high temperature failure, then return over temp error and exit */ 2346 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2347 /* power down the PHY in case the PHY FW didn't already */ 2348 ixgbe_set_copper_phy_power(hw, false); 2349 return IXGBE_ERR_OVERTEMP; 2350 } 2351 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2352 /* device fault alarm triggered */ 2353 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2354 MDIO_MMD_VEND1, 2355 ®); 2356 if (status) 2357 return status; 2358 2359 /* if device fault was due to high temp alarm handle and exit */ 2360 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2361 /* power down the PHY in case the PHY FW didn't */ 2362 ixgbe_set_copper_phy_power(hw, false); 2363 return IXGBE_ERR_OVERTEMP; 2364 } 2365 } 2366 2367 /* Vendor alarm 2 triggered */ 2368 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2369 MDIO_MMD_AN, ®); 2370 2371 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2372 return status; 2373 2374 /* link connect/disconnect event occurred */ 2375 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2376 MDIO_MMD_AN, ®); 2377 2378 if (status) 2379 return status; 2380 2381 /* Indicate LSC */ 2382 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2383 *lsc = true; 2384 2385 return 0; 2386 } 2387 2388 /** 2389 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2390 * @hw: pointer to hardware structure 2391 * 2392 * Enable link status change and temperature failure alarm for the external 2393 * Base T PHY 2394 * 2395 * Returns PHY access status 2396 **/ 2397 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2398 { 2399 u32 status; 2400 u16 reg; 2401 bool lsc; 2402 2403 /* Clear interrupt flags */ 2404 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2405 2406 /* Enable link status change alarm */ 2407 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2408 MDIO_MMD_AN, ®); 2409 if (status) 2410 return status; 2411 2412 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2413 2414 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2415 MDIO_MMD_AN, reg); 2416 if (status) 2417 return status; 2418 2419 /* Enable high temperature failure and global fault alarms */ 2420 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2421 MDIO_MMD_VEND1, 2422 ®); 2423 if (status) 2424 return status; 2425 2426 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2427 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2428 2429 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2430 MDIO_MMD_VEND1, 2431 reg); 2432 if (status) 2433 return status; 2434 2435 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2436 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2437 MDIO_MMD_VEND1, 2438 ®); 2439 if (status) 2440 return status; 2441 2442 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2443 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2444 2445 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2446 MDIO_MMD_VEND1, 2447 reg); 2448 if (status) 2449 return status; 2450 2451 /* Enable chip-wide vendor alarm */ 2452 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2453 MDIO_MMD_VEND1, 2454 ®); 2455 if (status) 2456 return status; 2457 2458 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2459 2460 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2461 MDIO_MMD_VEND1, 2462 reg); 2463 2464 return status; 2465 } 2466 2467 /** 2468 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2469 * @hw: pointer to hardware structure 2470 * 2471 * Handle external Base T PHY interrupt. If high temperature 2472 * failure alarm then return error, else if link status change 2473 * then setup internal/external PHY link 2474 * 2475 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2476 * failure alarm, else return PHY access status. 2477 **/ 2478 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2479 { 2480 struct ixgbe_phy_info *phy = &hw->phy; 2481 bool lsc; 2482 u32 status; 2483 2484 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2485 if (status) 2486 return status; 2487 2488 if (lsc && phy->ops.setup_internal_link) 2489 return phy->ops.setup_internal_link(hw); 2490 2491 return 0; 2492 } 2493 2494 /** 2495 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2496 * @hw: pointer to hardware structure 2497 * @speed: link speed 2498 * 2499 * Configures the integrated KR PHY. 2500 **/ 2501 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2502 ixgbe_link_speed speed) 2503 { 2504 s32 status; 2505 u32 reg_val; 2506 2507 status = hw->mac.ops.read_iosf_sb_reg(hw, 2508 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2509 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2510 if (status) 2511 return status; 2512 2513 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2514 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2515 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2516 2517 /* Advertise 10G support. */ 2518 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2519 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2520 2521 /* Advertise 1G support. */ 2522 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2523 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2524 2525 status = hw->mac.ops.write_iosf_sb_reg(hw, 2526 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2527 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2528 2529 if (hw->mac.type == ixgbe_mac_x550em_a) { 2530 /* Set lane mode to KR auto negotiation */ 2531 status = hw->mac.ops.read_iosf_sb_reg(hw, 2532 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2533 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2534 2535 if (status) 2536 return status; 2537 2538 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2539 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2540 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2541 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2542 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2543 2544 status = hw->mac.ops.write_iosf_sb_reg(hw, 2545 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2546 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2547 } 2548 2549 return ixgbe_restart_an_internal_phy_x550em(hw); 2550 } 2551 2552 /** 2553 * ixgbe_setup_kr_x550em - Configure the KR PHY 2554 * @hw: pointer to hardware structure 2555 **/ 2556 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2557 { 2558 /* leave link alone for 2.5G */ 2559 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2560 return 0; 2561 2562 if (ixgbe_check_reset_blocked(hw)) 2563 return 0; 2564 2565 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2566 } 2567 2568 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2569 * @hw: address of hardware structure 2570 * @link_up: address of boolean to indicate link status 2571 * 2572 * Returns error code if unable to get link status. 2573 **/ 2574 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2575 { 2576 u32 ret; 2577 u16 autoneg_status; 2578 2579 *link_up = false; 2580 2581 /* read this twice back to back to indicate current status */ 2582 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2583 &autoneg_status); 2584 if (ret) 2585 return ret; 2586 2587 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2588 &autoneg_status); 2589 if (ret) 2590 return ret; 2591 2592 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2593 2594 return 0; 2595 } 2596 2597 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2598 * @hw: point to hardware structure 2599 * 2600 * Configures the link between the integrated KR PHY and the external X557 PHY 2601 * The driver will call this function when it gets a link status change 2602 * interrupt from the X557 PHY. This function configures the link speed 2603 * between the PHYs to match the link speed of the BASE-T link. 2604 * 2605 * A return of a non-zero value indicates an error, and the base driver should 2606 * not report link up. 2607 **/ 2608 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2609 { 2610 ixgbe_link_speed force_speed; 2611 bool link_up; 2612 u32 status; 2613 u16 speed; 2614 2615 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2616 return IXGBE_ERR_CONFIG; 2617 2618 if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 2619 speed = IXGBE_LINK_SPEED_10GB_FULL | 2620 IXGBE_LINK_SPEED_1GB_FULL; 2621 return ixgbe_setup_kr_speed_x550em(hw, speed); 2622 } 2623 2624 /* If link is not up, then there is no setup necessary so return */ 2625 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2626 if (status) 2627 return status; 2628 2629 if (!link_up) 2630 return 0; 2631 2632 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2633 MDIO_MMD_AN, 2634 &speed); 2635 if (status) 2636 return status; 2637 2638 /* If link is not still up, then no setup is necessary so return */ 2639 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2640 if (status) 2641 return status; 2642 2643 if (!link_up) 2644 return 0; 2645 2646 /* clear everything but the speed and duplex bits */ 2647 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2648 2649 switch (speed) { 2650 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2651 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2652 break; 2653 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2654 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2655 break; 2656 default: 2657 /* Internal PHY does not support anything else */ 2658 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2659 } 2660 2661 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2662 } 2663 2664 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2665 * @hw: pointer to hardware structure 2666 **/ 2667 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2668 { 2669 s32 status; 2670 2671 status = ixgbe_reset_phy_generic(hw); 2672 2673 if (status) 2674 return status; 2675 2676 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2677 return ixgbe_enable_lasi_ext_t_x550em(hw); 2678 } 2679 2680 /** 2681 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2682 * @hw: pointer to hardware structure 2683 * @led_idx: led number to turn on 2684 **/ 2685 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2686 { 2687 u16 phy_data; 2688 2689 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2690 return IXGBE_ERR_PARAM; 2691 2692 /* To turn on the LED, set mode to ON. */ 2693 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2694 MDIO_MMD_VEND1, &phy_data); 2695 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2696 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2697 MDIO_MMD_VEND1, phy_data); 2698 2699 return 0; 2700 } 2701 2702 /** 2703 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2704 * @hw: pointer to hardware structure 2705 * @led_idx: led number to turn off 2706 **/ 2707 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2708 { 2709 u16 phy_data; 2710 2711 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2712 return IXGBE_ERR_PARAM; 2713 2714 /* To turn on the LED, set mode to ON. */ 2715 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2716 MDIO_MMD_VEND1, &phy_data); 2717 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2718 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2719 MDIO_MMD_VEND1, phy_data); 2720 2721 return 0; 2722 } 2723 2724 /** 2725 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2726 * @hw: pointer to the HW structure 2727 * @maj: driver version major number 2728 * @min: driver version minor number 2729 * @build: driver version build number 2730 * @sub: driver version sub build number 2731 * @len: length of driver_ver string 2732 * @driver_ver: driver string 2733 * 2734 * Sends driver version number to firmware through the manageability 2735 * block. On success return 0 2736 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 2737 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 2738 **/ 2739 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2740 u8 build, u8 sub, u16 len, 2741 const char *driver_ver) 2742 { 2743 struct ixgbe_hic_drv_info2 fw_cmd; 2744 s32 ret_val; 2745 int i; 2746 2747 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2748 return IXGBE_ERR_INVALID_ARGUMENT; 2749 2750 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2751 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2752 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2753 fw_cmd.port_num = (u8)hw->bus.func; 2754 fw_cmd.ver_maj = maj; 2755 fw_cmd.ver_min = min; 2756 fw_cmd.ver_build = build; 2757 fw_cmd.ver_sub = sub; 2758 fw_cmd.hdr.checksum = 0; 2759 memcpy(fw_cmd.driver_string, driver_ver, len); 2760 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2761 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2762 2763 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2764 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2765 sizeof(fw_cmd), 2766 IXGBE_HI_COMMAND_TIMEOUT, 2767 true); 2768 if (ret_val) 2769 continue; 2770 2771 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2772 FW_CEM_RESP_STATUS_SUCCESS) 2773 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 2774 return 0; 2775 } 2776 2777 return ret_val; 2778 } 2779 2780 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2781 * @hw: pointer to hardware structure 2782 * @lcd_speed: pointer to lowest common link speed 2783 * 2784 * Determine lowest common link speed with link partner. 2785 **/ 2786 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2787 ixgbe_link_speed *lcd_speed) 2788 { 2789 u16 an_lp_status; 2790 s32 status; 2791 u16 word = hw->eeprom.ctrl_word_3; 2792 2793 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2794 2795 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2796 MDIO_MMD_AN, 2797 &an_lp_status); 2798 if (status) 2799 return status; 2800 2801 /* If link partner advertised 1G, return 1G */ 2802 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2803 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2804 return status; 2805 } 2806 2807 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2808 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2809 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2810 return status; 2811 2812 /* Link partner not capable of lower speeds, return 10G */ 2813 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2814 return status; 2815 } 2816 2817 /** 2818 * ixgbe_setup_fc_x550em - Set up flow control 2819 * @hw: pointer to hardware structure 2820 */ 2821 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2822 { 2823 bool pause, asm_dir; 2824 u32 reg_val; 2825 s32 rc; 2826 2827 /* Validate the requested mode */ 2828 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2829 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2830 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2831 } 2832 2833 /* 10gig parts do not have a word in the EEPROM to determine the 2834 * default flow control setting, so we explicitly set it to full. 2835 */ 2836 if (hw->fc.requested_mode == ixgbe_fc_default) 2837 hw->fc.requested_mode = ixgbe_fc_full; 2838 2839 /* Determine PAUSE and ASM_DIR bits. */ 2840 switch (hw->fc.requested_mode) { 2841 case ixgbe_fc_none: 2842 pause = false; 2843 asm_dir = false; 2844 break; 2845 case ixgbe_fc_tx_pause: 2846 pause = false; 2847 asm_dir = true; 2848 break; 2849 case ixgbe_fc_rx_pause: 2850 /* Rx Flow control is enabled and Tx Flow control is 2851 * disabled by software override. Since there really 2852 * isn't a way to advertise that we are capable of RX 2853 * Pause ONLY, we will advertise that we support both 2854 * symmetric and asymmetric Rx PAUSE, as such we fall 2855 * through to the fc_full statement. Later, we will 2856 * disable the adapter's ability to send PAUSE frames. 2857 */ 2858 /* Fallthrough */ 2859 case ixgbe_fc_full: 2860 pause = true; 2861 asm_dir = true; 2862 break; 2863 default: 2864 hw_err(hw, "Flow control param set incorrectly\n"); 2865 return IXGBE_ERR_CONFIG; 2866 } 2867 2868 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR && 2869 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR && 2870 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L) 2871 return 0; 2872 2873 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2874 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2875 IXGBE_SB_IOSF_TARGET_KR_PHY, 2876 ®_val); 2877 if (rc) 2878 return rc; 2879 2880 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2881 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2882 if (pause) 2883 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2884 if (asm_dir) 2885 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2886 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2887 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2888 IXGBE_SB_IOSF_TARGET_KR_PHY, 2889 reg_val); 2890 2891 /* This device does not fully support AN. */ 2892 hw->fc.disable_fc_autoneg = true; 2893 2894 return rc; 2895 } 2896 2897 /** 2898 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2899 * @hw: pointer to hardware structure 2900 **/ 2901 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2902 { 2903 u32 link_s1, lp_an_page_low, an_cntl_1; 2904 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2905 ixgbe_link_speed speed; 2906 bool link_up; 2907 2908 /* AN should have completed when the cable was plugged in. 2909 * Look for reasons to bail out. Bail out if: 2910 * - FC autoneg is disabled, or if 2911 * - link is not up. 2912 */ 2913 if (hw->fc.disable_fc_autoneg) { 2914 hw_err(hw, "Flow control autoneg is disabled"); 2915 goto out; 2916 } 2917 2918 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2919 if (!link_up) { 2920 hw_err(hw, "The link is down"); 2921 goto out; 2922 } 2923 2924 /* Check at auto-negotiation has completed */ 2925 status = hw->mac.ops.read_iosf_sb_reg(hw, 2926 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2927 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2928 2929 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2930 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2931 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2932 goto out; 2933 } 2934 2935 /* Read the 10g AN autoc and LP ability registers and resolve 2936 * local flow control settings accordingly 2937 */ 2938 status = hw->mac.ops.read_iosf_sb_reg(hw, 2939 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2940 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2941 2942 if (status) { 2943 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2944 goto out; 2945 } 2946 2947 status = hw->mac.ops.read_iosf_sb_reg(hw, 2948 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2949 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2950 2951 if (status) { 2952 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2953 goto out; 2954 } 2955 2956 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2957 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2958 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2959 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2960 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2961 2962 out: 2963 if (!status) { 2964 hw->fc.fc_was_autonegged = true; 2965 } else { 2966 hw->fc.fc_was_autonegged = false; 2967 hw->fc.current_mode = hw->fc.requested_mode; 2968 } 2969 } 2970 2971 /** 2972 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 2973 * @hw: pointer to hardware structure 2974 **/ 2975 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 2976 { 2977 hw->fc.fc_was_autonegged = false; 2978 hw->fc.current_mode = hw->fc.requested_mode; 2979 } 2980 2981 /** ixgbe_enter_lplu_x550em - Transition to low power states 2982 * @hw: pointer to hardware structure 2983 * 2984 * Configures Low Power Link Up on transition to low power states 2985 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 2986 * the X557 PHY immediately prior to entering LPLU. 2987 **/ 2988 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2989 { 2990 u16 an_10g_cntl_reg, autoneg_reg, speed; 2991 s32 status; 2992 ixgbe_link_speed lcd_speed; 2993 u32 save_autoneg; 2994 bool link_up; 2995 2996 /* If blocked by MNG FW, then don't restart AN */ 2997 if (ixgbe_check_reset_blocked(hw)) 2998 return 0; 2999 3000 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3001 if (status) 3002 return status; 3003 3004 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 3005 &hw->eeprom.ctrl_word_3); 3006 if (status) 3007 return status; 3008 3009 /* If link is down, LPLU disabled in NVM, WoL disabled, or 3010 * manageability disabled, then force link down by entering 3011 * low power mode. 3012 */ 3013 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3014 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3015 return ixgbe_set_copper_phy_power(hw, false); 3016 3017 /* Determine LCD */ 3018 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3019 if (status) 3020 return status; 3021 3022 /* If no valid LCD link speed, then force link down and exit. */ 3023 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3024 return ixgbe_set_copper_phy_power(hw, false); 3025 3026 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3027 MDIO_MMD_AN, 3028 &speed); 3029 if (status) 3030 return status; 3031 3032 /* If no link now, speed is invalid so take link down */ 3033 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3034 if (status) 3035 return ixgbe_set_copper_phy_power(hw, false); 3036 3037 /* clear everything but the speed bits */ 3038 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3039 3040 /* If current speed is already LCD, then exit. */ 3041 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3042 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3043 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3044 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3045 return status; 3046 3047 /* Clear AN completed indication */ 3048 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3049 MDIO_MMD_AN, 3050 &autoneg_reg); 3051 if (status) 3052 return status; 3053 3054 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3055 MDIO_MMD_AN, 3056 &an_10g_cntl_reg); 3057 if (status) 3058 return status; 3059 3060 status = hw->phy.ops.read_reg(hw, 3061 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3062 MDIO_MMD_AN, 3063 &autoneg_reg); 3064 if (status) 3065 return status; 3066 3067 save_autoneg = hw->phy.autoneg_advertised; 3068 3069 /* Setup link at least common link speed */ 3070 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3071 3072 /* restore autoneg from before setting lplu speed */ 3073 hw->phy.autoneg_advertised = save_autoneg; 3074 3075 return status; 3076 } 3077 3078 /** 3079 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3080 * @hw: pointer to hardware structure 3081 */ 3082 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3083 { 3084 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3085 s32 rc; 3086 3087 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3088 return 0; 3089 3090 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3091 if (rc) 3092 return rc; 3093 memset(store, 0, sizeof(store)); 3094 3095 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3096 if (rc) 3097 return rc; 3098 3099 return ixgbe_setup_fw_link(hw); 3100 } 3101 3102 /** 3103 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3104 * @hw: pointer to hardware structure 3105 */ 3106 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3107 { 3108 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3109 s32 rc; 3110 3111 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3112 if (rc) 3113 return rc; 3114 3115 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3116 ixgbe_shutdown_fw_phy(hw); 3117 return IXGBE_ERR_OVERTEMP; 3118 } 3119 return 0; 3120 } 3121 3122 /** 3123 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3124 * @hw: pointer to hardware structure 3125 * 3126 * Read NW_MNG_IF_SEL register and save field values. 3127 */ 3128 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3129 { 3130 /* Save NW management interface connected on board. This is used 3131 * to determine internal PHY mode. 3132 */ 3133 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3134 3135 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3136 * PHY address. This register field was has only been used for X552. 3137 */ 3138 if (hw->mac.type == ixgbe_mac_x550em_a && 3139 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3140 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 3141 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 3142 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 3143 } 3144 } 3145 3146 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3147 * @hw: pointer to hardware structure 3148 * 3149 * Initialize any function pointers that were not able to be 3150 * set during init_shared_code because the PHY/SFP type was 3151 * not known. Perform the SFP init if necessary. 3152 **/ 3153 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3154 { 3155 struct ixgbe_phy_info *phy = &hw->phy; 3156 s32 ret_val; 3157 3158 hw->mac.ops.set_lan_id(hw); 3159 3160 ixgbe_read_mng_if_sel_x550em(hw); 3161 3162 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3163 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3164 ixgbe_setup_mux_ctl(hw); 3165 } 3166 3167 /* Identify the PHY or SFP module */ 3168 ret_val = phy->ops.identify(hw); 3169 3170 /* Setup function pointers based on detected hardware */ 3171 ixgbe_init_mac_link_ops_X550em(hw); 3172 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3173 phy->ops.reset = NULL; 3174 3175 /* Set functions pointers based on phy type */ 3176 switch (hw->phy.type) { 3177 case ixgbe_phy_x550em_kx4: 3178 phy->ops.setup_link = NULL; 3179 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3180 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3181 break; 3182 case ixgbe_phy_x550em_kr: 3183 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3184 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3185 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3186 break; 3187 case ixgbe_phy_x550em_xfi: 3188 /* link is managed by HW */ 3189 phy->ops.setup_link = NULL; 3190 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3191 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3192 break; 3193 case ixgbe_phy_x550em_ext_t: 3194 /* Save NW management interface connected on board. This is used 3195 * to determine internal PHY mode 3196 */ 3197 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3198 3199 /* If internal link mode is XFI, then setup iXFI internal link, 3200 * else setup KR now. 3201 */ 3202 phy->ops.setup_internal_link = 3203 ixgbe_setup_internal_phy_t_x550em; 3204 3205 /* setup SW LPLU only for first revision */ 3206 if (hw->mac.type == ixgbe_mac_X550EM_x && 3207 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3208 IXGBE_FUSES0_REV_MASK)) 3209 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3210 3211 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3212 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3213 break; 3214 case ixgbe_phy_sgmii: 3215 phy->ops.setup_link = NULL; 3216 break; 3217 case ixgbe_phy_fw: 3218 phy->ops.setup_link = ixgbe_setup_fw_link; 3219 phy->ops.reset = ixgbe_reset_phy_fw; 3220 break; 3221 case ixgbe_phy_ext_1g_t: 3222 phy->ops.setup_link = NULL; 3223 phy->ops.read_reg = NULL; 3224 phy->ops.write_reg = NULL; 3225 phy->ops.reset = NULL; 3226 break; 3227 default: 3228 break; 3229 } 3230 3231 return ret_val; 3232 } 3233 3234 /** ixgbe_get_media_type_X550em - Get media type 3235 * @hw: pointer to hardware structure 3236 * 3237 * Returns the media type (fiber, copper, backplane) 3238 * 3239 */ 3240 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3241 { 3242 enum ixgbe_media_type media_type; 3243 3244 /* Detect if there is a copper PHY attached. */ 3245 switch (hw->device_id) { 3246 case IXGBE_DEV_ID_X550EM_A_SGMII: 3247 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3248 hw->phy.type = ixgbe_phy_sgmii; 3249 /* Fallthrough */ 3250 case IXGBE_DEV_ID_X550EM_X_KR: 3251 case IXGBE_DEV_ID_X550EM_X_KX4: 3252 case IXGBE_DEV_ID_X550EM_X_XFI: 3253 case IXGBE_DEV_ID_X550EM_A_KR: 3254 case IXGBE_DEV_ID_X550EM_A_KR_L: 3255 media_type = ixgbe_media_type_backplane; 3256 break; 3257 case IXGBE_DEV_ID_X550EM_X_SFP: 3258 case IXGBE_DEV_ID_X550EM_A_SFP: 3259 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3260 media_type = ixgbe_media_type_fiber; 3261 break; 3262 case IXGBE_DEV_ID_X550EM_X_1G_T: 3263 case IXGBE_DEV_ID_X550EM_X_10G_T: 3264 case IXGBE_DEV_ID_X550EM_A_10G_T: 3265 case IXGBE_DEV_ID_X550EM_A_1G_T: 3266 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3267 media_type = ixgbe_media_type_copper; 3268 break; 3269 default: 3270 media_type = ixgbe_media_type_unknown; 3271 break; 3272 } 3273 return media_type; 3274 } 3275 3276 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3277 ** @hw: pointer to hardware structure 3278 **/ 3279 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3280 { 3281 s32 status; 3282 u16 reg; 3283 3284 status = hw->phy.ops.read_reg(hw, 3285 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3286 MDIO_MMD_PMAPMD, 3287 ®); 3288 if (status) 3289 return status; 3290 3291 /* If PHY FW reset completed bit is set then this is the first 3292 * SW instance after a power on so the PHY FW must be un-stalled. 3293 */ 3294 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3295 status = hw->phy.ops.read_reg(hw, 3296 IXGBE_MDIO_GLOBAL_RES_PR_10, 3297 MDIO_MMD_VEND1, 3298 ®); 3299 if (status) 3300 return status; 3301 3302 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3303 3304 status = hw->phy.ops.write_reg(hw, 3305 IXGBE_MDIO_GLOBAL_RES_PR_10, 3306 MDIO_MMD_VEND1, 3307 reg); 3308 if (status) 3309 return status; 3310 } 3311 3312 return status; 3313 } 3314 3315 /** 3316 * ixgbe_set_mdio_speed - Set MDIO clock speed 3317 * @hw: pointer to hardware structure 3318 */ 3319 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3320 { 3321 u32 hlreg0; 3322 3323 switch (hw->device_id) { 3324 case IXGBE_DEV_ID_X550EM_X_10G_T: 3325 case IXGBE_DEV_ID_X550EM_A_SGMII: 3326 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3327 case IXGBE_DEV_ID_X550EM_A_10G_T: 3328 case IXGBE_DEV_ID_X550EM_A_SFP: 3329 /* Config MDIO clock speed before the first MDIO PHY access */ 3330 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3331 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3332 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3333 break; 3334 case IXGBE_DEV_ID_X550EM_A_1G_T: 3335 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3336 /* Select fast MDIO clock speed for these devices */ 3337 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3338 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3339 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3340 break; 3341 default: 3342 break; 3343 } 3344 } 3345 3346 /** ixgbe_reset_hw_X550em - Perform hardware reset 3347 ** @hw: pointer to hardware structure 3348 ** 3349 ** Resets the hardware by resetting the transmit and receive units, masks 3350 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3351 ** reset. 3352 **/ 3353 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3354 { 3355 ixgbe_link_speed link_speed; 3356 s32 status; 3357 u32 ctrl = 0; 3358 u32 i; 3359 bool link_up = false; 3360 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3361 3362 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3363 status = hw->mac.ops.stop_adapter(hw); 3364 if (status) 3365 return status; 3366 3367 /* flush pending Tx transactions */ 3368 ixgbe_clear_tx_pending(hw); 3369 3370 /* PHY ops must be identified and initialized prior to reset */ 3371 3372 /* Identify PHY and related function pointers */ 3373 status = hw->phy.ops.init(hw); 3374 3375 /* start the external PHY */ 3376 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3377 status = ixgbe_init_ext_t_x550em(hw); 3378 if (status) 3379 return status; 3380 } 3381 3382 /* Setup SFP module if there is one present. */ 3383 if (hw->phy.sfp_setup_needed) { 3384 status = hw->mac.ops.setup_sfp(hw); 3385 hw->phy.sfp_setup_needed = false; 3386 } 3387 3388 /* Reset PHY */ 3389 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3390 hw->phy.ops.reset(hw); 3391 3392 mac_reset_top: 3393 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3394 * If link reset is used when link is up, it might reset the PHY when 3395 * mng is using it. If link is down or the flag to force full link 3396 * reset is set, then perform link reset. 3397 */ 3398 ctrl = IXGBE_CTRL_LNK_RST; 3399 3400 if (!hw->force_full_reset) { 3401 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3402 if (link_up) 3403 ctrl = IXGBE_CTRL_RST; 3404 } 3405 3406 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3407 if (status) { 3408 hw_dbg(hw, "semaphore failed with %d", status); 3409 return IXGBE_ERR_SWFW_SYNC; 3410 } 3411 3412 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3413 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3414 IXGBE_WRITE_FLUSH(hw); 3415 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3416 usleep_range(1000, 1200); 3417 3418 /* Poll for reset bit to self-clear meaning reset is complete */ 3419 for (i = 0; i < 10; i++) { 3420 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3421 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3422 break; 3423 udelay(1); 3424 } 3425 3426 if (ctrl & IXGBE_CTRL_RST_MASK) { 3427 status = IXGBE_ERR_RESET_FAILED; 3428 hw_dbg(hw, "Reset polling failed to complete.\n"); 3429 } 3430 3431 msleep(50); 3432 3433 /* Double resets are required for recovery from certain error 3434 * clear the multicast table. Also reset num_rar_entries to 128, 3435 * since we modify this value when programming the SAN MAC address. 3436 */ 3437 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3438 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3439 goto mac_reset_top; 3440 } 3441 3442 /* Store the permanent mac address */ 3443 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3444 3445 /* Store MAC address from RAR0, clear receive address registers, and 3446 * clear the multicast table. Also reset num_rar_entries to 128, 3447 * since we modify this value when programming the SAN MAC address. 3448 */ 3449 hw->mac.num_rar_entries = 128; 3450 hw->mac.ops.init_rx_addrs(hw); 3451 3452 ixgbe_set_mdio_speed(hw); 3453 3454 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3455 ixgbe_setup_mux_ctl(hw); 3456 3457 return status; 3458 } 3459 3460 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3461 * anti-spoofing 3462 * @hw: pointer to hardware structure 3463 * @enable: enable or disable switch for Ethertype anti-spoofing 3464 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3465 **/ 3466 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3467 bool enable, int vf) 3468 { 3469 int vf_target_reg = vf >> 3; 3470 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3471 u32 pfvfspoof; 3472 3473 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3474 if (enable) 3475 pfvfspoof |= BIT(vf_target_shift); 3476 else 3477 pfvfspoof &= ~BIT(vf_target_shift); 3478 3479 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3480 } 3481 3482 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3483 * @hw: pointer to hardware structure 3484 * @enable: enable or disable source address pruning 3485 * @pool: Rx pool to set source address pruning for 3486 **/ 3487 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3488 bool enable, 3489 unsigned int pool) 3490 { 3491 u64 pfflp; 3492 3493 /* max rx pool is 63 */ 3494 if (pool > 63) 3495 return; 3496 3497 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3498 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3499 3500 if (enable) 3501 pfflp |= (1ULL << pool); 3502 else 3503 pfflp &= ~(1ULL << pool); 3504 3505 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3506 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3507 } 3508 3509 /** 3510 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3511 * @hw: pointer to hardware structure 3512 * 3513 * Called at init time to set up flow control. 3514 **/ 3515 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3516 { 3517 s32 status = 0; 3518 u32 an_cntl = 0; 3519 3520 /* Validate the requested mode */ 3521 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3522 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3523 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3524 } 3525 3526 if (hw->fc.requested_mode == ixgbe_fc_default) 3527 hw->fc.requested_mode = ixgbe_fc_full; 3528 3529 /* Set up the 1G and 10G flow control advertisement registers so the 3530 * HW will be able to do FC autoneg once the cable is plugged in. If 3531 * we link at 10G, the 1G advertisement is harmless and vice versa. 3532 */ 3533 status = hw->mac.ops.read_iosf_sb_reg(hw, 3534 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3535 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3536 3537 if (status) { 3538 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3539 return status; 3540 } 3541 3542 /* The possible values of fc.requested_mode are: 3543 * 0: Flow control is completely disabled 3544 * 1: Rx flow control is enabled (we can receive pause frames, 3545 * but not send pause frames). 3546 * 2: Tx flow control is enabled (we can send pause frames but 3547 * we do not support receiving pause frames). 3548 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3549 * other: Invalid. 3550 */ 3551 switch (hw->fc.requested_mode) { 3552 case ixgbe_fc_none: 3553 /* Flow control completely disabled by software override. */ 3554 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3555 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3556 break; 3557 case ixgbe_fc_tx_pause: 3558 /* Tx Flow control is enabled, and Rx Flow control is 3559 * disabled by software override. 3560 */ 3561 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3562 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3563 break; 3564 case ixgbe_fc_rx_pause: 3565 /* Rx Flow control is enabled and Tx Flow control is 3566 * disabled by software override. Since there really 3567 * isn't a way to advertise that we are capable of RX 3568 * Pause ONLY, we will advertise that we support both 3569 * symmetric and asymmetric Rx PAUSE, as such we fall 3570 * through to the fc_full statement. Later, we will 3571 * disable the adapter's ability to send PAUSE frames. 3572 */ 3573 case ixgbe_fc_full: 3574 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3575 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3576 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3577 break; 3578 default: 3579 hw_err(hw, "Flow control param set incorrectly\n"); 3580 return IXGBE_ERR_CONFIG; 3581 } 3582 3583 status = hw->mac.ops.write_iosf_sb_reg(hw, 3584 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3585 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3586 3587 /* Restart auto-negotiation. */ 3588 status = ixgbe_restart_an_internal_phy_x550em(hw); 3589 3590 return status; 3591 } 3592 3593 /** 3594 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3595 * @hw: pointer to hardware structure 3596 * @state: set mux if 1, clear if 0 3597 */ 3598 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3599 { 3600 u32 esdp; 3601 3602 if (!hw->bus.lan_id) 3603 return; 3604 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3605 if (state) 3606 esdp |= IXGBE_ESDP_SDP1; 3607 else 3608 esdp &= ~IXGBE_ESDP_SDP1; 3609 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3610 IXGBE_WRITE_FLUSH(hw); 3611 } 3612 3613 /** 3614 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3615 * @hw: pointer to hardware structure 3616 * @mask: Mask to specify which semaphore to acquire 3617 * 3618 * Acquires the SWFW semaphore and sets the I2C MUX 3619 */ 3620 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3621 { 3622 s32 status; 3623 3624 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3625 if (status) 3626 return status; 3627 3628 if (mask & IXGBE_GSSR_I2C_MASK) 3629 ixgbe_set_mux(hw, 1); 3630 3631 return 0; 3632 } 3633 3634 /** 3635 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3636 * @hw: pointer to hardware structure 3637 * @mask: Mask to specify which semaphore to release 3638 * 3639 * Releases the SWFW semaphore and sets the I2C MUX 3640 */ 3641 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3642 { 3643 if (mask & IXGBE_GSSR_I2C_MASK) 3644 ixgbe_set_mux(hw, 0); 3645 3646 ixgbe_release_swfw_sync_X540(hw, mask); 3647 } 3648 3649 /** 3650 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3651 * @hw: pointer to hardware structure 3652 * @mask: Mask to specify which semaphore to acquire 3653 * 3654 * Acquires the SWFW semaphore and get the shared PHY token as needed 3655 */ 3656 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3657 { 3658 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3659 int retries = FW_PHY_TOKEN_RETRIES; 3660 s32 status; 3661 3662 while (--retries) { 3663 status = 0; 3664 if (hmask) 3665 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3666 if (status) 3667 return status; 3668 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3669 return 0; 3670 3671 status = ixgbe_get_phy_token(hw); 3672 if (!status) 3673 return 0; 3674 if (hmask) 3675 ixgbe_release_swfw_sync_X540(hw, hmask); 3676 if (status != IXGBE_ERR_TOKEN_RETRY) 3677 return status; 3678 msleep(FW_PHY_TOKEN_DELAY); 3679 } 3680 3681 return status; 3682 } 3683 3684 /** 3685 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3686 * @hw: pointer to hardware structure 3687 * @mask: Mask to specify which semaphore to release 3688 * 3689 * Release the SWFW semaphore and puts the shared PHY token as needed 3690 */ 3691 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3692 { 3693 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3694 3695 if (mask & IXGBE_GSSR_TOKEN_SM) 3696 ixgbe_put_phy_token(hw); 3697 3698 if (hmask) 3699 ixgbe_release_swfw_sync_X540(hw, hmask); 3700 } 3701 3702 /** 3703 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3704 * @hw: pointer to hardware structure 3705 * @reg_addr: 32 bit address of PHY register to read 3706 * @phy_data: Pointer to read data from PHY register 3707 * 3708 * Reads a value from a specified PHY register using the SWFW lock and PHY 3709 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3710 * instances. 3711 */ 3712 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3713 u32 device_type, u16 *phy_data) 3714 { 3715 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3716 s32 status; 3717 3718 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3719 return IXGBE_ERR_SWFW_SYNC; 3720 3721 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3722 3723 hw->mac.ops.release_swfw_sync(hw, mask); 3724 3725 return status; 3726 } 3727 3728 /** 3729 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3730 * @hw: pointer to hardware structure 3731 * @reg_addr: 32 bit PHY register to write 3732 * @device_type: 5 bit device type 3733 * @phy_data: Data to write to the PHY register 3734 * 3735 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3736 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3737 */ 3738 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3739 u32 device_type, u16 phy_data) 3740 { 3741 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3742 s32 status; 3743 3744 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3745 return IXGBE_ERR_SWFW_SYNC; 3746 3747 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3748 hw->mac.ops.release_swfw_sync(hw, mask); 3749 3750 return status; 3751 } 3752 3753 #define X550_COMMON_MAC \ 3754 .init_hw = &ixgbe_init_hw_generic, \ 3755 .start_hw = &ixgbe_start_hw_X540, \ 3756 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3757 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3758 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3759 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3760 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3761 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3762 .read_analog_reg8 = NULL, \ 3763 .write_analog_reg8 = NULL, \ 3764 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3765 .check_link = &ixgbe_check_mac_link_generic, \ 3766 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3767 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3768 .set_rar = &ixgbe_set_rar_generic, \ 3769 .clear_rar = &ixgbe_clear_rar_generic, \ 3770 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3771 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3772 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3773 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3774 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3775 .enable_mc = &ixgbe_enable_mc_generic, \ 3776 .disable_mc = &ixgbe_disable_mc_generic, \ 3777 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3778 .set_vfta = &ixgbe_set_vfta_generic, \ 3779 .fc_enable = &ixgbe_fc_enable_generic, \ 3780 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3781 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3782 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3783 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3784 .set_source_address_pruning = \ 3785 &ixgbe_set_source_address_pruning_X550, \ 3786 .set_ethertype_anti_spoofing = \ 3787 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3788 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3789 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3790 .get_thermal_sensor_data = NULL, \ 3791 .init_thermal_sensor_thresh = NULL, \ 3792 .enable_rx = &ixgbe_enable_rx_generic, \ 3793 .disable_rx = &ixgbe_disable_rx_x550, \ 3794 3795 static const struct ixgbe_mac_operations mac_ops_X550 = { 3796 X550_COMMON_MAC 3797 .led_on = ixgbe_led_on_generic, 3798 .led_off = ixgbe_led_off_generic, 3799 .init_led_link_act = ixgbe_init_led_link_act_generic, 3800 .reset_hw = &ixgbe_reset_hw_X540, 3801 .get_media_type = &ixgbe_get_media_type_X540, 3802 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3803 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3804 .setup_link = &ixgbe_setup_mac_link_X540, 3805 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3806 .get_bus_info = &ixgbe_get_bus_info_generic, 3807 .setup_sfp = NULL, 3808 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3809 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3810 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3811 .prot_autoc_read = prot_autoc_read_generic, 3812 .prot_autoc_write = prot_autoc_write_generic, 3813 .setup_fc = ixgbe_setup_fc_generic, 3814 .fc_autoneg = ixgbe_fc_autoneg, 3815 }; 3816 3817 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3818 X550_COMMON_MAC 3819 .led_on = ixgbe_led_on_t_x550em, 3820 .led_off = ixgbe_led_off_t_x550em, 3821 .init_led_link_act = ixgbe_init_led_link_act_generic, 3822 .reset_hw = &ixgbe_reset_hw_X550em, 3823 .get_media_type = &ixgbe_get_media_type_X550em, 3824 .get_san_mac_addr = NULL, 3825 .get_wwn_prefix = NULL, 3826 .setup_link = &ixgbe_setup_mac_link_X540, 3827 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3828 .get_bus_info = &ixgbe_get_bus_info_X550em, 3829 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3830 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3831 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3832 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3833 .setup_fc = NULL, /* defined later */ 3834 .fc_autoneg = ixgbe_fc_autoneg, 3835 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3836 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3837 }; 3838 3839 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = { 3840 X550_COMMON_MAC 3841 .led_on = NULL, 3842 .led_off = NULL, 3843 .init_led_link_act = NULL, 3844 .reset_hw = &ixgbe_reset_hw_X550em, 3845 .get_media_type = &ixgbe_get_media_type_X550em, 3846 .get_san_mac_addr = NULL, 3847 .get_wwn_prefix = NULL, 3848 .setup_link = &ixgbe_setup_mac_link_X540, 3849 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3850 .get_bus_info = &ixgbe_get_bus_info_X550em, 3851 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3852 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3853 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3854 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3855 .setup_fc = NULL, 3856 .fc_autoneg = ixgbe_fc_autoneg, 3857 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3858 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3859 }; 3860 3861 static struct ixgbe_mac_operations mac_ops_x550em_a = { 3862 X550_COMMON_MAC 3863 .led_on = ixgbe_led_on_t_x550em, 3864 .led_off = ixgbe_led_off_t_x550em, 3865 .init_led_link_act = ixgbe_init_led_link_act_generic, 3866 .reset_hw = ixgbe_reset_hw_X550em, 3867 .get_media_type = ixgbe_get_media_type_X550em, 3868 .get_san_mac_addr = NULL, 3869 .get_wwn_prefix = NULL, 3870 .setup_link = &ixgbe_setup_mac_link_X540, 3871 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3872 .get_bus_info = ixgbe_get_bus_info_X550em, 3873 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3874 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3875 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3876 .setup_fc = ixgbe_setup_fc_x550em, 3877 .fc_autoneg = ixgbe_fc_autoneg, 3878 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3879 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3880 }; 3881 3882 static struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3883 X550_COMMON_MAC 3884 .led_on = ixgbe_led_on_generic, 3885 .led_off = ixgbe_led_off_generic, 3886 .init_led_link_act = ixgbe_init_led_link_act_generic, 3887 .reset_hw = ixgbe_reset_hw_X550em, 3888 .get_media_type = ixgbe_get_media_type_X550em, 3889 .get_san_mac_addr = NULL, 3890 .get_wwn_prefix = NULL, 3891 .setup_link = NULL, /* defined later */ 3892 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3893 .get_bus_info = ixgbe_get_bus_info_X550em, 3894 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3895 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3896 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3897 .setup_fc = ixgbe_setup_fc_x550em, 3898 .fc_autoneg = ixgbe_fc_autoneg, 3899 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3900 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3901 }; 3902 3903 #define X550_COMMON_EEP \ 3904 .read = &ixgbe_read_ee_hostif_X550, \ 3905 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3906 .write = &ixgbe_write_ee_hostif_X550, \ 3907 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3908 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3909 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3910 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3911 3912 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3913 X550_COMMON_EEP 3914 .init_params = &ixgbe_init_eeprom_params_X550, 3915 }; 3916 3917 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3918 X550_COMMON_EEP 3919 .init_params = &ixgbe_init_eeprom_params_X540, 3920 }; 3921 3922 #define X550_COMMON_PHY \ 3923 .identify_sfp = &ixgbe_identify_module_generic, \ 3924 .reset = NULL, \ 3925 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3926 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3927 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3928 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3929 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3930 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3931 .setup_link = &ixgbe_setup_phy_link_generic, \ 3932 .set_phy_power = NULL, 3933 3934 static const struct ixgbe_phy_operations phy_ops_X550 = { 3935 X550_COMMON_PHY 3936 .check_overtemp = &ixgbe_tn_check_overtemp, 3937 .init = NULL, 3938 .identify = &ixgbe_identify_phy_generic, 3939 .read_reg = &ixgbe_read_phy_reg_generic, 3940 .write_reg = &ixgbe_write_phy_reg_generic, 3941 }; 3942 3943 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3944 X550_COMMON_PHY 3945 .check_overtemp = &ixgbe_tn_check_overtemp, 3946 .init = &ixgbe_init_phy_ops_X550em, 3947 .identify = &ixgbe_identify_phy_x550em, 3948 .read_reg = &ixgbe_read_phy_reg_generic, 3949 .write_reg = &ixgbe_write_phy_reg_generic, 3950 }; 3951 3952 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 3953 X550_COMMON_PHY 3954 .check_overtemp = NULL, 3955 .init = ixgbe_init_phy_ops_X550em, 3956 .identify = ixgbe_identify_phy_x550em, 3957 .read_reg = NULL, 3958 .write_reg = NULL, 3959 .read_reg_mdi = NULL, 3960 .write_reg_mdi = NULL, 3961 }; 3962 3963 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 3964 X550_COMMON_PHY 3965 .check_overtemp = &ixgbe_tn_check_overtemp, 3966 .init = &ixgbe_init_phy_ops_X550em, 3967 .identify = &ixgbe_identify_phy_x550em, 3968 .read_reg = &ixgbe_read_phy_reg_x550a, 3969 .write_reg = &ixgbe_write_phy_reg_x550a, 3970 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 3971 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 3972 }; 3973 3974 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 3975 X550_COMMON_PHY 3976 .check_overtemp = ixgbe_check_overtemp_fw, 3977 .init = ixgbe_init_phy_ops_X550em, 3978 .identify = ixgbe_identify_phy_fw, 3979 .read_reg = NULL, 3980 .write_reg = NULL, 3981 .read_reg_mdi = NULL, 3982 .write_reg_mdi = NULL, 3983 }; 3984 3985 static const struct ixgbe_link_operations link_ops_x550em_x = { 3986 .read_link = &ixgbe_read_i2c_combined_generic, 3987 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 3988 .write_link = &ixgbe_write_i2c_combined_generic, 3989 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 3990 }; 3991 3992 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 3993 IXGBE_MVALS_INIT(X550) 3994 }; 3995 3996 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 3997 IXGBE_MVALS_INIT(X550EM_x) 3998 }; 3999 4000 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 4001 IXGBE_MVALS_INIT(X550EM_a) 4002 }; 4003 4004 const struct ixgbe_info ixgbe_X550_info = { 4005 .mac = ixgbe_mac_X550, 4006 .get_invariants = &ixgbe_get_invariants_X540, 4007 .mac_ops = &mac_ops_X550, 4008 .eeprom_ops = &eeprom_ops_X550, 4009 .phy_ops = &phy_ops_X550, 4010 .mbx_ops = &mbx_ops_generic, 4011 .mvals = ixgbe_mvals_X550, 4012 }; 4013 4014 const struct ixgbe_info ixgbe_X550EM_x_info = { 4015 .mac = ixgbe_mac_X550EM_x, 4016 .get_invariants = &ixgbe_get_invariants_X550_x, 4017 .mac_ops = &mac_ops_X550EM_x, 4018 .eeprom_ops = &eeprom_ops_X550EM_x, 4019 .phy_ops = &phy_ops_X550EM_x, 4020 .mbx_ops = &mbx_ops_generic, 4021 .mvals = ixgbe_mvals_X550EM_x, 4022 .link_ops = &link_ops_x550em_x, 4023 }; 4024 4025 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 4026 .mac = ixgbe_mac_X550EM_x, 4027 .get_invariants = ixgbe_get_invariants_X550_x_fw, 4028 .mac_ops = &mac_ops_X550EM_x_fw, 4029 .eeprom_ops = &eeprom_ops_X550EM_x, 4030 .phy_ops = &phy_ops_x550em_x_fw, 4031 .mbx_ops = &mbx_ops_generic, 4032 .mvals = ixgbe_mvals_X550EM_x, 4033 }; 4034 4035 const struct ixgbe_info ixgbe_x550em_a_info = { 4036 .mac = ixgbe_mac_x550em_a, 4037 .get_invariants = &ixgbe_get_invariants_X550_a, 4038 .mac_ops = &mac_ops_x550em_a, 4039 .eeprom_ops = &eeprom_ops_X550EM_x, 4040 .phy_ops = &phy_ops_x550em_a, 4041 .mbx_ops = &mbx_ops_generic, 4042 .mvals = ixgbe_mvals_x550em_a, 4043 }; 4044 4045 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4046 .mac = ixgbe_mac_x550em_a, 4047 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4048 .mac_ops = &mac_ops_x550em_a_fw, 4049 .eeprom_ops = &eeprom_ops_X550EM_x, 4050 .phy_ops = &phy_ops_x550em_a_fw, 4051 .mbx_ops = &mbx_ops_generic, 4052 .mvals = ixgbe_mvals_x550em_a, 4053 }; 4054