1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 31 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 32 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 33 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 34 35 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 36 { 37 struct ixgbe_mac_info *mac = &hw->mac; 38 struct ixgbe_phy_info *phy = &hw->phy; 39 struct ixgbe_link_info *link = &hw->link; 40 41 /* Start with X540 invariants, since so simular */ 42 ixgbe_get_invariants_X540(hw); 43 44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 45 phy->ops.set_phy_power = NULL; 46 47 link->addr = IXGBE_CS4227; 48 49 return 0; 50 } 51 52 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 53 { 54 struct ixgbe_phy_info *phy = &hw->phy; 55 56 /* Start with X540 invariants, since so similar */ 57 ixgbe_get_invariants_X540(hw); 58 59 phy->ops.set_phy_power = NULL; 60 61 return 0; 62 } 63 64 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 65 { 66 struct ixgbe_mac_info *mac = &hw->mac; 67 struct ixgbe_phy_info *phy = &hw->phy; 68 69 /* Start with X540 invariants, since so simular */ 70 ixgbe_get_invariants_X540(hw); 71 72 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 73 phy->ops.set_phy_power = NULL; 74 75 return 0; 76 } 77 78 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 79 { 80 struct ixgbe_phy_info *phy = &hw->phy; 81 82 /* Start with X540 invariants, since so similar */ 83 ixgbe_get_invariants_X540(hw); 84 85 phy->ops.set_phy_power = NULL; 86 87 return 0; 88 } 89 90 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 91 * @hw: pointer to hardware structure 92 **/ 93 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 94 { 95 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 96 97 if (hw->bus.lan_id) { 98 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 99 esdp |= IXGBE_ESDP_SDP1_DIR; 100 } 101 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 103 IXGBE_WRITE_FLUSH(hw); 104 } 105 106 /** 107 * ixgbe_read_cs4227 - Read CS4227 register 108 * @hw: pointer to hardware structure 109 * @reg: register number to write 110 * @value: pointer to receive value read 111 * 112 * Returns status code 113 */ 114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 115 { 116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 117 } 118 119 /** 120 * ixgbe_write_cs4227 - Write CS4227 register 121 * @hw: pointer to hardware structure 122 * @reg: register number to write 123 * @value: value to write to register 124 * 125 * Returns status code 126 */ 127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 128 { 129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 130 } 131 132 /** 133 * ixgbe_read_pe - Read register from port expander 134 * @hw: pointer to hardware structure 135 * @reg: register number to read 136 * @value: pointer to receive read value 137 * 138 * Returns status code 139 */ 140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 141 { 142 s32 status; 143 144 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 145 if (status) 146 hw_err(hw, "port expander access failed with %d\n", status); 147 return status; 148 } 149 150 /** 151 * ixgbe_write_pe - Write register to port expander 152 * @hw: pointer to hardware structure 153 * @reg: register number to write 154 * @value: value to write 155 * 156 * Returns status code 157 */ 158 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 159 { 160 s32 status; 161 162 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 163 value); 164 if (status) 165 hw_err(hw, "port expander access failed with %d\n", status); 166 return status; 167 } 168 169 /** 170 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 171 * @hw: pointer to hardware structure 172 * 173 * This function assumes that the caller has acquired the proper semaphore. 174 * Returns error code 175 */ 176 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 177 { 178 s32 status; 179 u32 retry; 180 u16 value; 181 u8 reg; 182 183 /* Trigger hard reset. */ 184 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 185 if (status) 186 return status; 187 reg |= IXGBE_PE_BIT1; 188 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 189 if (status) 190 return status; 191 192 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 193 if (status) 194 return status; 195 reg &= ~IXGBE_PE_BIT1; 196 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 197 if (status) 198 return status; 199 200 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 201 if (status) 202 return status; 203 reg &= ~IXGBE_PE_BIT1; 204 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 205 if (status) 206 return status; 207 208 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 209 210 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 211 if (status) 212 return status; 213 reg |= IXGBE_PE_BIT1; 214 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 215 if (status) 216 return status; 217 218 /* Wait for the reset to complete. */ 219 msleep(IXGBE_CS4227_RESET_DELAY); 220 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 222 &value); 223 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 224 break; 225 msleep(IXGBE_CS4227_CHECK_DELAY); 226 } 227 if (retry == IXGBE_CS4227_RETRIES) { 228 hw_err(hw, "CS4227 reset did not complete\n"); 229 return IXGBE_ERR_PHY; 230 } 231 232 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 233 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 234 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 235 return IXGBE_ERR_PHY; 236 } 237 238 return 0; 239 } 240 241 /** 242 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 243 * @hw: pointer to hardware structure 244 */ 245 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 246 { 247 u32 swfw_mask = hw->phy.phy_semaphore_mask; 248 s32 status; 249 u16 value; 250 u8 retry; 251 252 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 253 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 254 if (status) { 255 hw_err(hw, "semaphore failed with %d\n", status); 256 msleep(IXGBE_CS4227_CHECK_DELAY); 257 continue; 258 } 259 260 /* Get status of reset flow. */ 261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 262 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 263 goto out; 264 265 if (status || value != IXGBE_CS4227_RESET_PENDING) 266 break; 267 268 /* Reset is pending. Wait and check again. */ 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 msleep(IXGBE_CS4227_CHECK_DELAY); 271 } 272 /* If still pending, assume other instance failed. */ 273 if (retry == IXGBE_CS4227_RETRIES) { 274 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 275 if (status) { 276 hw_err(hw, "semaphore failed with %d\n", status); 277 return; 278 } 279 } 280 281 /* Reset the CS4227. */ 282 status = ixgbe_reset_cs4227(hw); 283 if (status) { 284 hw_err(hw, "CS4227 reset failed: %d", status); 285 goto out; 286 } 287 288 /* Reset takes so long, temporarily release semaphore in case the 289 * other driver instance is waiting for the reset indication. 290 */ 291 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 292 IXGBE_CS4227_RESET_PENDING); 293 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 294 usleep_range(10000, 12000); 295 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 296 if (status) { 297 hw_err(hw, "semaphore failed with %d", status); 298 return; 299 } 300 301 /* Record completion for next time. */ 302 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 303 IXGBE_CS4227_RESET_COMPLETE); 304 305 out: 306 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 307 msleep(hw->eeprom.semaphore_delay); 308 } 309 310 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 311 * @hw: pointer to hardware structure 312 * 313 * Returns error code 314 */ 315 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 316 { 317 switch (hw->device_id) { 318 case IXGBE_DEV_ID_X550EM_A_SFP: 319 if (hw->bus.lan_id) 320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 321 else 322 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 323 return ixgbe_identify_module_generic(hw); 324 case IXGBE_DEV_ID_X550EM_X_SFP: 325 /* set up for CS4227 usage */ 326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 327 ixgbe_setup_mux_ctl(hw); 328 ixgbe_check_cs4227(hw); 329 /* Fallthrough */ 330 case IXGBE_DEV_ID_X550EM_A_SFP_N: 331 return ixgbe_identify_module_generic(hw); 332 case IXGBE_DEV_ID_X550EM_X_KX4: 333 hw->phy.type = ixgbe_phy_x550em_kx4; 334 break; 335 case IXGBE_DEV_ID_X550EM_X_XFI: 336 hw->phy.type = ixgbe_phy_x550em_xfi; 337 break; 338 case IXGBE_DEV_ID_X550EM_X_KR: 339 case IXGBE_DEV_ID_X550EM_A_KR: 340 case IXGBE_DEV_ID_X550EM_A_KR_L: 341 hw->phy.type = ixgbe_phy_x550em_kr; 342 break; 343 case IXGBE_DEV_ID_X550EM_A_10G_T: 344 if (hw->bus.lan_id) 345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 346 else 347 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 348 /* Fallthrough */ 349 case IXGBE_DEV_ID_X550EM_X_10G_T: 350 return ixgbe_identify_phy_generic(hw); 351 case IXGBE_DEV_ID_X550EM_X_1G_T: 352 hw->phy.type = ixgbe_phy_ext_1g_t; 353 break; 354 case IXGBE_DEV_ID_X550EM_A_1G_T: 355 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 356 hw->phy.type = ixgbe_phy_fw; 357 hw->phy.ops.read_reg = NULL; 358 hw->phy.ops.write_reg = NULL; 359 if (hw->bus.lan_id) 360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 361 else 362 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 363 break; 364 default: 365 break; 366 } 367 return 0; 368 } 369 370 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 371 u32 device_type, u16 *phy_data) 372 { 373 return IXGBE_NOT_IMPLEMENTED; 374 } 375 376 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 377 u32 device_type, u16 phy_data) 378 { 379 return IXGBE_NOT_IMPLEMENTED; 380 } 381 382 /** 383 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 384 * @hw: pointer to the hardware structure 385 * @addr: I2C bus address to read from 386 * @reg: I2C device register to read from 387 * @val: pointer to location to receive read value 388 * 389 * Returns an error code on error. 390 **/ 391 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 392 u16 reg, u16 *val) 393 { 394 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 395 } 396 397 /** 398 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 399 * @hw: pointer to the hardware structure 400 * @addr: I2C bus address to read from 401 * @reg: I2C device register to read from 402 * @val: pointer to location to receive read value 403 * 404 * Returns an error code on error. 405 **/ 406 static s32 407 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 408 u16 reg, u16 *val) 409 { 410 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 411 } 412 413 /** 414 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 415 * @hw: pointer to the hardware structure 416 * @addr: I2C bus address to write to 417 * @reg: I2C device register to write to 418 * @val: value to write 419 * 420 * Returns an error code on error. 421 **/ 422 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 423 u8 addr, u16 reg, u16 val) 424 { 425 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 426 } 427 428 /** 429 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 430 * @hw: pointer to the hardware structure 431 * @addr: I2C bus address to write to 432 * @reg: I2C device register to write to 433 * @val: value to write 434 * 435 * Returns an error code on error. 436 **/ 437 static s32 438 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 439 u8 addr, u16 reg, u16 val) 440 { 441 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 442 } 443 444 /** 445 * ixgbe_fw_phy_activity - Perform an activity on a PHY 446 * @hw: pointer to hardware structure 447 * @activity: activity to perform 448 * @data: Pointer to 4 32-bit words of data 449 */ 450 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 451 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 452 { 453 union { 454 struct ixgbe_hic_phy_activity_req cmd; 455 struct ixgbe_hic_phy_activity_resp rsp; 456 } hic; 457 u16 retries = FW_PHY_ACT_RETRIES; 458 s32 rc; 459 u32 i; 460 461 do { 462 memset(&hic, 0, sizeof(hic)); 463 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 464 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 465 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 466 hic.cmd.port_number = hw->bus.lan_id; 467 hic.cmd.activity_id = cpu_to_le16(activity); 468 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 469 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 470 471 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 472 IXGBE_HI_COMMAND_TIMEOUT, 473 true); 474 if (rc) 475 return rc; 476 if (hic.rsp.hdr.cmd_or_resp.ret_status == 477 FW_CEM_RESP_STATUS_SUCCESS) { 478 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 479 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 480 return 0; 481 } 482 usleep_range(20, 30); 483 --retries; 484 } while (retries > 0); 485 486 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 487 } 488 489 static const struct { 490 u16 fw_speed; 491 ixgbe_link_speed phy_speed; 492 } ixgbe_fw_map[] = { 493 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 494 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 495 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 496 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 497 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 498 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 499 }; 500 501 /** 502 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 503 * @hw: pointer to hardware structure 504 * 505 * Returns error code 506 */ 507 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 508 { 509 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 510 u16 phy_speeds; 511 u16 phy_id_lo; 512 s32 rc; 513 u16 i; 514 515 if (hw->phy.id) 516 return 0; 517 518 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 519 if (rc) 520 return rc; 521 522 hw->phy.speeds_supported = 0; 523 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 524 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 525 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 526 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 527 } 528 529 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 530 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 531 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 532 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 533 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 534 return IXGBE_ERR_PHY_ADDR_INVALID; 535 536 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 537 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 538 IXGBE_LINK_SPEED_1GB_FULL; 539 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 540 return 0; 541 } 542 543 /** 544 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 545 * @hw: pointer to hardware structure 546 * 547 * Returns error code 548 */ 549 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 550 { 551 if (hw->bus.lan_id) 552 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 553 else 554 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 555 556 hw->phy.type = ixgbe_phy_fw; 557 hw->phy.ops.read_reg = NULL; 558 hw->phy.ops.write_reg = NULL; 559 return ixgbe_get_phy_id_fw(hw); 560 } 561 562 /** 563 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 564 * @hw: pointer to hardware structure 565 * 566 * Returns error code 567 */ 568 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 569 { 570 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 571 572 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 573 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 574 } 575 576 /** 577 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 578 * @hw: pointer to hardware structure 579 */ 580 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 581 { 582 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 583 s32 rc; 584 u16 i; 585 586 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 587 return 0; 588 589 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 590 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 591 return IXGBE_ERR_INVALID_LINK_SETTINGS; 592 } 593 594 switch (hw->fc.requested_mode) { 595 case ixgbe_fc_full: 596 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 597 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 598 break; 599 case ixgbe_fc_rx_pause: 600 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 601 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 602 break; 603 case ixgbe_fc_tx_pause: 604 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 605 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 606 break; 607 default: 608 break; 609 } 610 611 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 612 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 613 setup[0] |= ixgbe_fw_map[i].fw_speed; 614 } 615 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 616 617 if (hw->phy.eee_speeds_advertised) 618 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 619 620 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 621 if (rc) 622 return rc; 623 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 624 return IXGBE_ERR_OVERTEMP; 625 return 0; 626 } 627 628 /** 629 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 630 * @hw: pointer to hardware structure 631 * 632 * Called at init time to set up flow control. 633 */ 634 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 635 { 636 if (hw->fc.requested_mode == ixgbe_fc_default) 637 hw->fc.requested_mode = ixgbe_fc_full; 638 639 return ixgbe_setup_fw_link(hw); 640 } 641 642 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 643 * @hw: pointer to hardware structure 644 * 645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 646 * ixgbe_hw struct in order to set up EEPROM access. 647 **/ 648 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 649 { 650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 651 u32 eec; 652 u16 eeprom_size; 653 654 if (eeprom->type == ixgbe_eeprom_uninitialized) { 655 eeprom->semaphore_delay = 10; 656 eeprom->type = ixgbe_flash; 657 658 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 659 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 660 IXGBE_EEC_SIZE_SHIFT); 661 eeprom->word_size = BIT(eeprom_size + 662 IXGBE_EEPROM_WORD_SIZE_SHIFT); 663 664 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 665 eeprom->type, eeprom->word_size); 666 } 667 668 return 0; 669 } 670 671 /** 672 * ixgbe_iosf_wait - Wait for IOSF command completion 673 * @hw: pointer to hardware structure 674 * @ctrl: pointer to location to receive final IOSF control value 675 * 676 * Return: failing status on timeout 677 * 678 * Note: ctrl can be NULL if the IOSF control register value is not needed 679 */ 680 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 681 { 682 u32 i, command; 683 684 /* Check every 10 usec to see if the address cycle completed. 685 * The SB IOSF BUSY bit will clear when the operation is 686 * complete. 687 */ 688 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 689 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 690 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 691 break; 692 udelay(10); 693 } 694 if (ctrl) 695 *ctrl = command; 696 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 697 hw_dbg(hw, "IOSF wait timed out\n"); 698 return IXGBE_ERR_PHY; 699 } 700 701 return 0; 702 } 703 704 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 705 * IOSF device 706 * @hw: pointer to hardware structure 707 * @reg_addr: 32 bit PHY register to write 708 * @device_type: 3 bit device type 709 * @phy_data: Pointer to read data from the register 710 **/ 711 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 712 u32 device_type, u32 *data) 713 { 714 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 715 u32 command, error; 716 s32 ret; 717 718 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 719 if (ret) 720 return ret; 721 722 ret = ixgbe_iosf_wait(hw, NULL); 723 if (ret) 724 goto out; 725 726 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 727 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 728 729 /* Write IOSF control register */ 730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 731 732 ret = ixgbe_iosf_wait(hw, &command); 733 734 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 735 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 736 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 737 hw_dbg(hw, "Failed to read, error %x\n", error); 738 return IXGBE_ERR_PHY; 739 } 740 741 if (!ret) 742 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 743 744 out: 745 hw->mac.ops.release_swfw_sync(hw, gssr); 746 return ret; 747 } 748 749 /** 750 * ixgbe_get_phy_token - Get the token for shared PHY access 751 * @hw: Pointer to hardware structure 752 */ 753 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 754 { 755 struct ixgbe_hic_phy_token_req token_cmd; 756 s32 status; 757 758 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 759 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 760 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 761 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 762 token_cmd.port_number = hw->bus.lan_id; 763 token_cmd.command_type = FW_PHY_TOKEN_REQ; 764 token_cmd.pad = 0; 765 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 766 IXGBE_HI_COMMAND_TIMEOUT, 767 true); 768 if (status) 769 return status; 770 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 771 return 0; 772 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 773 return IXGBE_ERR_FW_RESP_INVALID; 774 775 return IXGBE_ERR_TOKEN_RETRY; 776 } 777 778 /** 779 * ixgbe_put_phy_token - Put the token for shared PHY access 780 * @hw: Pointer to hardware structure 781 */ 782 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 783 { 784 struct ixgbe_hic_phy_token_req token_cmd; 785 s32 status; 786 787 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 788 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 789 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 790 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 791 token_cmd.port_number = hw->bus.lan_id; 792 token_cmd.command_type = FW_PHY_TOKEN_REL; 793 token_cmd.pad = 0; 794 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 795 IXGBE_HI_COMMAND_TIMEOUT, 796 true); 797 if (status) 798 return status; 799 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 800 return 0; 801 return IXGBE_ERR_FW_RESP_INVALID; 802 } 803 804 /** 805 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 806 * @hw: pointer to hardware structure 807 * @reg_addr: 32 bit PHY register to write 808 * @device_type: 3 bit device type 809 * @data: Data to write to the register 810 **/ 811 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 812 __always_unused u32 device_type, 813 u32 data) 814 { 815 struct ixgbe_hic_internal_phy_req write_cmd; 816 817 memset(&write_cmd, 0, sizeof(write_cmd)); 818 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 819 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 820 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 821 write_cmd.port_number = hw->bus.lan_id; 822 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 823 write_cmd.address = cpu_to_be16(reg_addr); 824 write_cmd.write_data = cpu_to_be32(data); 825 826 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 827 IXGBE_HI_COMMAND_TIMEOUT, false); 828 } 829 830 /** 831 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 832 * @hw: pointer to hardware structure 833 * @reg_addr: 32 bit PHY register to write 834 * @device_type: 3 bit device type 835 * @data: Pointer to read data from the register 836 **/ 837 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 838 __always_unused u32 device_type, 839 u32 *data) 840 { 841 union { 842 struct ixgbe_hic_internal_phy_req cmd; 843 struct ixgbe_hic_internal_phy_resp rsp; 844 } hic; 845 s32 status; 846 847 memset(&hic, 0, sizeof(hic)); 848 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 849 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 850 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 851 hic.cmd.port_number = hw->bus.lan_id; 852 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 853 hic.cmd.address = cpu_to_be16(reg_addr); 854 855 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 856 IXGBE_HI_COMMAND_TIMEOUT, true); 857 858 /* Extract the register value from the response. */ 859 *data = be32_to_cpu(hic.rsp.read_data); 860 861 return status; 862 } 863 864 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 865 * @hw: pointer to hardware structure 866 * @offset: offset of word in the EEPROM to read 867 * @words: number of words 868 * @data: word(s) read from the EEPROM 869 * 870 * Reads a 16 bit word(s) from the EEPROM using the hostif. 871 **/ 872 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 873 u16 offset, u16 words, u16 *data) 874 { 875 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 876 struct ixgbe_hic_read_shadow_ram buffer; 877 u32 current_word = 0; 878 u16 words_to_read; 879 s32 status; 880 u32 i; 881 882 /* Take semaphore for the entire operation. */ 883 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 884 if (status) { 885 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 886 return status; 887 } 888 889 while (words) { 890 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 891 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 892 else 893 words_to_read = words; 894 895 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 896 buffer.hdr.req.buf_lenh = 0; 897 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 898 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 899 900 /* convert offset from words to bytes */ 901 buffer.address = cpu_to_be32((offset + current_word) * 2); 902 buffer.length = cpu_to_be16(words_to_read * 2); 903 buffer.pad2 = 0; 904 buffer.pad3 = 0; 905 906 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 907 IXGBE_HI_COMMAND_TIMEOUT); 908 if (status) { 909 hw_dbg(hw, "Host interface command failed\n"); 910 goto out; 911 } 912 913 for (i = 0; i < words_to_read; i++) { 914 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 915 2 * i; 916 u32 value = IXGBE_READ_REG(hw, reg); 917 918 data[current_word] = (u16)(value & 0xffff); 919 current_word++; 920 i++; 921 if (i < words_to_read) { 922 value >>= 16; 923 data[current_word] = (u16)(value & 0xffff); 924 current_word++; 925 } 926 } 927 words -= words_to_read; 928 } 929 930 out: 931 hw->mac.ops.release_swfw_sync(hw, mask); 932 return status; 933 } 934 935 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 936 * @hw: pointer to hardware structure 937 * @ptr: pointer offset in eeprom 938 * @size: size of section pointed by ptr, if 0 first word will be used as size 939 * @csum: address of checksum to update 940 * 941 * Returns error status for any failure 942 **/ 943 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 944 u16 size, u16 *csum, u16 *buffer, 945 u32 buffer_size) 946 { 947 u16 buf[256]; 948 s32 status; 949 u16 length, bufsz, i, start; 950 u16 *local_buffer; 951 952 bufsz = sizeof(buf) / sizeof(buf[0]); 953 954 /* Read a chunk at the pointer location */ 955 if (!buffer) { 956 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 957 if (status) { 958 hw_dbg(hw, "Failed to read EEPROM image\n"); 959 return status; 960 } 961 local_buffer = buf; 962 } else { 963 if (buffer_size < ptr) 964 return IXGBE_ERR_PARAM; 965 local_buffer = &buffer[ptr]; 966 } 967 968 if (size) { 969 start = 0; 970 length = size; 971 } else { 972 start = 1; 973 length = local_buffer[0]; 974 975 /* Skip pointer section if length is invalid. */ 976 if (length == 0xFFFF || length == 0 || 977 (ptr + length) >= hw->eeprom.word_size) 978 return 0; 979 } 980 981 if (buffer && ((u32)start + (u32)length > buffer_size)) 982 return IXGBE_ERR_PARAM; 983 984 for (i = start; length; i++, length--) { 985 if (i == bufsz && !buffer) { 986 ptr += bufsz; 987 i = 0; 988 if (length < bufsz) 989 bufsz = length; 990 991 /* Read a chunk at the pointer location */ 992 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 993 bufsz, buf); 994 if (status) { 995 hw_dbg(hw, "Failed to read EEPROM image\n"); 996 return status; 997 } 998 } 999 *csum += local_buffer[i]; 1000 } 1001 return 0; 1002 } 1003 1004 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 1005 * @hw: pointer to hardware structure 1006 * @buffer: pointer to buffer containing calculated checksum 1007 * @buffer_size: size of buffer 1008 * 1009 * Returns a negative error code on error, or the 16-bit checksum 1010 **/ 1011 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 1012 u32 buffer_size) 1013 { 1014 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 1015 u16 *local_buffer; 1016 s32 status; 1017 u16 checksum = 0; 1018 u16 pointer, i, size; 1019 1020 hw->eeprom.ops.init_params(hw); 1021 1022 if (!buffer) { 1023 /* Read pointer area */ 1024 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1025 IXGBE_EEPROM_LAST_WORD + 1, 1026 eeprom_ptrs); 1027 if (status) { 1028 hw_dbg(hw, "Failed to read EEPROM image\n"); 1029 return status; 1030 } 1031 local_buffer = eeprom_ptrs; 1032 } else { 1033 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1034 return IXGBE_ERR_PARAM; 1035 local_buffer = buffer; 1036 } 1037 1038 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1039 * checksum word itself 1040 */ 1041 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1042 if (i != IXGBE_EEPROM_CHECKSUM) 1043 checksum += local_buffer[i]; 1044 1045 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1046 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1047 */ 1048 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1049 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1050 continue; 1051 1052 pointer = local_buffer[i]; 1053 1054 /* Skip pointer section if the pointer is invalid. */ 1055 if (pointer == 0xFFFF || pointer == 0 || 1056 pointer >= hw->eeprom.word_size) 1057 continue; 1058 1059 switch (i) { 1060 case IXGBE_PCIE_GENERAL_PTR: 1061 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1062 break; 1063 case IXGBE_PCIE_CONFIG0_PTR: 1064 case IXGBE_PCIE_CONFIG1_PTR: 1065 size = IXGBE_PCIE_CONFIG_SIZE; 1066 break; 1067 default: 1068 size = 0; 1069 break; 1070 } 1071 1072 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1073 buffer, buffer_size); 1074 if (status) 1075 return status; 1076 } 1077 1078 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1079 1080 return (s32)checksum; 1081 } 1082 1083 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1084 * @hw: pointer to hardware structure 1085 * 1086 * Returns a negative error code on error, or the 16-bit checksum 1087 **/ 1088 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1089 { 1090 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1091 } 1092 1093 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1094 * @hw: pointer to hardware structure 1095 * @offset: offset of word in the EEPROM to read 1096 * @data: word read from the EEPROM 1097 * 1098 * Reads a 16 bit word from the EEPROM using the hostif. 1099 **/ 1100 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1101 { 1102 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1103 struct ixgbe_hic_read_shadow_ram buffer; 1104 s32 status; 1105 1106 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1107 buffer.hdr.req.buf_lenh = 0; 1108 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1109 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1110 1111 /* convert offset from words to bytes */ 1112 buffer.address = cpu_to_be32(offset * 2); 1113 /* one word */ 1114 buffer.length = cpu_to_be16(sizeof(u16)); 1115 1116 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1117 if (status) 1118 return status; 1119 1120 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1121 IXGBE_HI_COMMAND_TIMEOUT); 1122 if (!status) { 1123 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1124 FW_NVM_DATA_OFFSET); 1125 } 1126 1127 hw->mac.ops.release_swfw_sync(hw, mask); 1128 return status; 1129 } 1130 1131 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1132 * @hw: pointer to hardware structure 1133 * @checksum_val: calculated checksum 1134 * 1135 * Performs checksum calculation and validates the EEPROM checksum. If the 1136 * caller does not need checksum_val, the value can be NULL. 1137 **/ 1138 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1139 u16 *checksum_val) 1140 { 1141 s32 status; 1142 u16 checksum; 1143 u16 read_checksum = 0; 1144 1145 /* Read the first word from the EEPROM. If this times out or fails, do 1146 * not continue or we could be in for a very long wait while every 1147 * EEPROM read fails 1148 */ 1149 status = hw->eeprom.ops.read(hw, 0, &checksum); 1150 if (status) { 1151 hw_dbg(hw, "EEPROM read failed\n"); 1152 return status; 1153 } 1154 1155 status = hw->eeprom.ops.calc_checksum(hw); 1156 if (status < 0) 1157 return status; 1158 1159 checksum = (u16)(status & 0xffff); 1160 1161 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1162 &read_checksum); 1163 if (status) 1164 return status; 1165 1166 /* Verify read checksum from EEPROM is the same as 1167 * calculated checksum 1168 */ 1169 if (read_checksum != checksum) { 1170 status = IXGBE_ERR_EEPROM_CHECKSUM; 1171 hw_dbg(hw, "Invalid EEPROM checksum"); 1172 } 1173 1174 /* If the user cares, return the calculated checksum */ 1175 if (checksum_val) 1176 *checksum_val = checksum; 1177 1178 return status; 1179 } 1180 1181 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1182 * @hw: pointer to hardware structure 1183 * @offset: offset of word in the EEPROM to write 1184 * @data: word write to the EEPROM 1185 * 1186 * Write a 16 bit word to the EEPROM using the hostif. 1187 **/ 1188 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1189 u16 data) 1190 { 1191 s32 status; 1192 struct ixgbe_hic_write_shadow_ram buffer; 1193 1194 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1195 buffer.hdr.req.buf_lenh = 0; 1196 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1197 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1198 1199 /* one word */ 1200 buffer.length = cpu_to_be16(sizeof(u16)); 1201 buffer.data = data; 1202 buffer.address = cpu_to_be32(offset * 2); 1203 1204 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1205 IXGBE_HI_COMMAND_TIMEOUT, false); 1206 return status; 1207 } 1208 1209 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1210 * @hw: pointer to hardware structure 1211 * @offset: offset of word in the EEPROM to write 1212 * @data: word write to the EEPROM 1213 * 1214 * Write a 16 bit word to the EEPROM using the hostif. 1215 **/ 1216 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1217 { 1218 s32 status = 0; 1219 1220 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1221 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1222 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1223 } else { 1224 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1225 status = IXGBE_ERR_SWFW_SYNC; 1226 } 1227 1228 return status; 1229 } 1230 1231 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1232 * @hw: pointer to hardware structure 1233 * 1234 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1235 **/ 1236 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1237 { 1238 s32 status = 0; 1239 union ixgbe_hic_hdr2 buffer; 1240 1241 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1242 buffer.req.buf_lenh = 0; 1243 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1244 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1245 1246 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1247 IXGBE_HI_COMMAND_TIMEOUT, false); 1248 return status; 1249 } 1250 1251 /** 1252 * ixgbe_get_bus_info_X550em - Set PCI bus info 1253 * @hw: pointer to hardware structure 1254 * 1255 * Sets bus link width and speed to unknown because X550em is 1256 * not a PCI device. 1257 **/ 1258 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1259 { 1260 hw->bus.type = ixgbe_bus_type_internal; 1261 hw->bus.width = ixgbe_bus_width_unknown; 1262 hw->bus.speed = ixgbe_bus_speed_unknown; 1263 1264 hw->mac.ops.set_lan_id(hw); 1265 1266 return 0; 1267 } 1268 1269 /** ixgbe_disable_rx_x550 - Disable RX unit 1270 * 1271 * Enables the Rx DMA unit for x550 1272 **/ 1273 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1274 { 1275 u32 rxctrl, pfdtxgswc; 1276 s32 status; 1277 struct ixgbe_hic_disable_rxen fw_cmd; 1278 1279 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1280 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1281 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1282 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1283 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1284 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1285 hw->mac.set_lben = true; 1286 } else { 1287 hw->mac.set_lben = false; 1288 } 1289 1290 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1291 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1292 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1293 fw_cmd.port_number = hw->bus.lan_id; 1294 1295 status = ixgbe_host_interface_command(hw, &fw_cmd, 1296 sizeof(struct ixgbe_hic_disable_rxen), 1297 IXGBE_HI_COMMAND_TIMEOUT, true); 1298 1299 /* If we fail - disable RX using register write */ 1300 if (status) { 1301 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1302 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1303 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1304 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1305 } 1306 } 1307 } 1308 } 1309 1310 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1311 * @hw: pointer to hardware structure 1312 * 1313 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1314 * checksum and updates the EEPROM and instructs the hardware to update 1315 * the flash. 1316 **/ 1317 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1318 { 1319 s32 status; 1320 u16 checksum = 0; 1321 1322 /* Read the first word from the EEPROM. If this times out or fails, do 1323 * not continue or we could be in for a very long wait while every 1324 * EEPROM read fails 1325 */ 1326 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1327 if (status) { 1328 hw_dbg(hw, "EEPROM read failed\n"); 1329 return status; 1330 } 1331 1332 status = ixgbe_calc_eeprom_checksum_X550(hw); 1333 if (status < 0) 1334 return status; 1335 1336 checksum = (u16)(status & 0xffff); 1337 1338 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1339 checksum); 1340 if (status) 1341 return status; 1342 1343 status = ixgbe_update_flash_X550(hw); 1344 1345 return status; 1346 } 1347 1348 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1349 * @hw: pointer to hardware structure 1350 * @offset: offset of word in the EEPROM to write 1351 * @words: number of words 1352 * @data: word(s) write to the EEPROM 1353 * 1354 * 1355 * Write a 16 bit word(s) to the EEPROM using the hostif. 1356 **/ 1357 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1358 u16 offset, u16 words, 1359 u16 *data) 1360 { 1361 s32 status = 0; 1362 u32 i = 0; 1363 1364 /* Take semaphore for the entire operation. */ 1365 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1366 if (status) { 1367 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1368 return status; 1369 } 1370 1371 for (i = 0; i < words; i++) { 1372 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1373 data[i]); 1374 if (status) { 1375 hw_dbg(hw, "Eeprom buffered write failed\n"); 1376 break; 1377 } 1378 } 1379 1380 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1381 1382 return status; 1383 } 1384 1385 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1386 * IOSF device 1387 * 1388 * @hw: pointer to hardware structure 1389 * @reg_addr: 32 bit PHY register to write 1390 * @device_type: 3 bit device type 1391 * @data: Data to write to the register 1392 **/ 1393 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1394 u32 device_type, u32 data) 1395 { 1396 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1397 u32 command, error; 1398 s32 ret; 1399 1400 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1401 if (ret) 1402 return ret; 1403 1404 ret = ixgbe_iosf_wait(hw, NULL); 1405 if (ret) 1406 goto out; 1407 1408 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1409 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1410 1411 /* Write IOSF control register */ 1412 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1413 1414 /* Write IOSF data register */ 1415 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1416 1417 ret = ixgbe_iosf_wait(hw, &command); 1418 1419 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1420 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1421 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1422 hw_dbg(hw, "Failed to write, error %x\n", error); 1423 return IXGBE_ERR_PHY; 1424 } 1425 1426 out: 1427 hw->mac.ops.release_swfw_sync(hw, gssr); 1428 return ret; 1429 } 1430 1431 /** 1432 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1433 * @hw: pointer to hardware structure 1434 * 1435 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1436 **/ 1437 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1438 { 1439 s32 status; 1440 u32 reg_val; 1441 1442 /* Disable training protocol FSM. */ 1443 status = ixgbe_read_iosf_sb_reg_x550(hw, 1444 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1445 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1446 if (status) 1447 return status; 1448 1449 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1450 status = ixgbe_write_iosf_sb_reg_x550(hw, 1451 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1452 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1453 if (status) 1454 return status; 1455 1456 /* Disable Flex from training TXFFE. */ 1457 status = ixgbe_read_iosf_sb_reg_x550(hw, 1458 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1459 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1460 if (status) 1461 return status; 1462 1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1464 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1465 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1466 status = ixgbe_write_iosf_sb_reg_x550(hw, 1467 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1468 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1469 if (status) 1470 return status; 1471 1472 status = ixgbe_read_iosf_sb_reg_x550(hw, 1473 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1474 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1475 if (status) 1476 return status; 1477 1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1479 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1480 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1481 status = ixgbe_write_iosf_sb_reg_x550(hw, 1482 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1483 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1484 if (status) 1485 return status; 1486 1487 /* Enable override for coefficients. */ 1488 status = ixgbe_read_iosf_sb_reg_x550(hw, 1489 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1490 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1491 if (status) 1492 return status; 1493 1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1496 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1497 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1498 status = ixgbe_write_iosf_sb_reg_x550(hw, 1499 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1500 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1501 return status; 1502 } 1503 1504 /** 1505 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1506 * internal PHY 1507 * @hw: pointer to hardware structure 1508 **/ 1509 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1510 { 1511 s32 status; 1512 u32 link_ctrl; 1513 1514 /* Restart auto-negotiation. */ 1515 status = hw->mac.ops.read_iosf_sb_reg(hw, 1516 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1517 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1518 1519 if (status) { 1520 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1521 return status; 1522 } 1523 1524 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1525 status = hw->mac.ops.write_iosf_sb_reg(hw, 1526 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1527 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1528 1529 if (hw->mac.type == ixgbe_mac_x550em_a) { 1530 u32 flx_mask_st20; 1531 1532 /* Indicate to FW that AN restart has been asserted */ 1533 status = hw->mac.ops.read_iosf_sb_reg(hw, 1534 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1535 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1536 1537 if (status) { 1538 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1539 return status; 1540 } 1541 1542 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1543 status = hw->mac.ops.write_iosf_sb_reg(hw, 1544 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1545 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1546 } 1547 1548 return status; 1549 } 1550 1551 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1552 * @hw: pointer to hardware structure 1553 * @speed: the link speed to force 1554 * 1555 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1556 * internal and external PHY at a specific speed, without autonegotiation. 1557 **/ 1558 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1559 { 1560 struct ixgbe_mac_info *mac = &hw->mac; 1561 s32 status; 1562 u32 reg_val; 1563 1564 /* iXFI is only supported with X552 */ 1565 if (mac->type != ixgbe_mac_X550EM_x) 1566 return IXGBE_ERR_LINK_SETUP; 1567 1568 /* Disable AN and force speed to 10G Serial. */ 1569 status = ixgbe_read_iosf_sb_reg_x550(hw, 1570 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1571 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1572 if (status) 1573 return status; 1574 1575 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1576 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1577 1578 /* Select forced link speed for internal PHY. */ 1579 switch (*speed) { 1580 case IXGBE_LINK_SPEED_10GB_FULL: 1581 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1582 break; 1583 case IXGBE_LINK_SPEED_1GB_FULL: 1584 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1585 break; 1586 default: 1587 /* Other link speeds are not supported by internal KR PHY. */ 1588 return IXGBE_ERR_LINK_SETUP; 1589 } 1590 1591 status = ixgbe_write_iosf_sb_reg_x550(hw, 1592 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1593 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1594 if (status) 1595 return status; 1596 1597 /* Additional configuration needed for x550em_x */ 1598 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1599 status = ixgbe_setup_ixfi_x550em_x(hw); 1600 if (status) 1601 return status; 1602 } 1603 1604 /* Toggle port SW reset by AN reset. */ 1605 status = ixgbe_restart_an_internal_phy_x550em(hw); 1606 1607 return status; 1608 } 1609 1610 /** 1611 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1612 * @hw: pointer to hardware structure 1613 * @linear: true if SFP module is linear 1614 */ 1615 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1616 { 1617 switch (hw->phy.sfp_type) { 1618 case ixgbe_sfp_type_not_present: 1619 return IXGBE_ERR_SFP_NOT_PRESENT; 1620 case ixgbe_sfp_type_da_cu_core0: 1621 case ixgbe_sfp_type_da_cu_core1: 1622 *linear = true; 1623 break; 1624 case ixgbe_sfp_type_srlr_core0: 1625 case ixgbe_sfp_type_srlr_core1: 1626 case ixgbe_sfp_type_da_act_lmt_core0: 1627 case ixgbe_sfp_type_da_act_lmt_core1: 1628 case ixgbe_sfp_type_1g_sx_core0: 1629 case ixgbe_sfp_type_1g_sx_core1: 1630 case ixgbe_sfp_type_1g_lx_core0: 1631 case ixgbe_sfp_type_1g_lx_core1: 1632 *linear = false; 1633 break; 1634 case ixgbe_sfp_type_unknown: 1635 case ixgbe_sfp_type_1g_cu_core0: 1636 case ixgbe_sfp_type_1g_cu_core1: 1637 default: 1638 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1639 } 1640 1641 return 0; 1642 } 1643 1644 /** 1645 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1646 * @hw: pointer to hardware structure 1647 * 1648 * Configures the extern PHY and the integrated KR PHY for SFP support. 1649 */ 1650 static s32 1651 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1652 ixgbe_link_speed speed, 1653 __always_unused bool autoneg_wait_to_complete) 1654 { 1655 s32 status; 1656 u16 reg_slice, reg_val; 1657 bool setup_linear = false; 1658 1659 /* Check if SFP module is supported and linear */ 1660 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1661 1662 /* If no SFP module present, then return success. Return success since 1663 * there is no reason to configure CS4227 and SFP not present error is 1664 * not accepted in the setup MAC link flow. 1665 */ 1666 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 1667 return 0; 1668 1669 if (status) 1670 return status; 1671 1672 /* Configure internal PHY for KR/KX. */ 1673 ixgbe_setup_kr_speed_x550em(hw, speed); 1674 1675 /* Configure CS4227 LINE side to proper mode. */ 1676 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1677 if (setup_linear) 1678 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1679 else 1680 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1681 1682 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1683 reg_val); 1684 1685 return status; 1686 } 1687 1688 /** 1689 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1690 * @hw: pointer to hardware structure 1691 * @speed: the link speed to force 1692 * 1693 * Configures the integrated PHY for native SFI mode. Used to connect the 1694 * internal PHY directly to an SFP cage, without autonegotiation. 1695 **/ 1696 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1697 { 1698 struct ixgbe_mac_info *mac = &hw->mac; 1699 s32 status; 1700 u32 reg_val; 1701 1702 /* Disable all AN and force speed to 10G Serial. */ 1703 status = mac->ops.read_iosf_sb_reg(hw, 1704 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1705 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1706 if (status) 1707 return status; 1708 1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1712 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1713 1714 /* Select forced link speed for internal PHY. */ 1715 switch (*speed) { 1716 case IXGBE_LINK_SPEED_10GB_FULL: 1717 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1718 break; 1719 case IXGBE_LINK_SPEED_1GB_FULL: 1720 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1721 break; 1722 default: 1723 /* Other link speeds are not supported by internal PHY. */ 1724 return IXGBE_ERR_LINK_SETUP; 1725 } 1726 1727 status = mac->ops.write_iosf_sb_reg(hw, 1728 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1729 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1730 1731 /* Toggle port SW reset by AN reset. */ 1732 status = ixgbe_restart_an_internal_phy_x550em(hw); 1733 1734 return status; 1735 } 1736 1737 /** 1738 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1739 * @hw: pointer to hardware structure 1740 * 1741 * Configure the the integrated PHY for native SFP support. 1742 */ 1743 static s32 1744 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1745 __always_unused bool autoneg_wait_to_complete) 1746 { 1747 bool setup_linear = false; 1748 u32 reg_phy_int; 1749 s32 ret_val; 1750 1751 /* Check if SFP module is supported and linear */ 1752 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1753 1754 /* If no SFP module present, then return success. Return success since 1755 * SFP not present error is not excepted in the setup MAC link flow. 1756 */ 1757 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1758 return 0; 1759 1760 if (ret_val) 1761 return ret_val; 1762 1763 /* Configure internal PHY for native SFI based on module type */ 1764 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1765 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1766 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1767 if (ret_val) 1768 return ret_val; 1769 1770 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1771 if (!setup_linear) 1772 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1773 1774 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1775 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1776 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1777 if (ret_val) 1778 return ret_val; 1779 1780 /* Setup SFI internal link. */ 1781 return ixgbe_setup_sfi_x550a(hw, &speed); 1782 } 1783 1784 /** 1785 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1786 * @hw: pointer to hardware structure 1787 * 1788 * Configure the the integrated PHY for SFP support. 1789 */ 1790 static s32 1791 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1792 __always_unused bool autoneg_wait_to_complete) 1793 { 1794 u32 reg_slice, slice_offset; 1795 bool setup_linear = false; 1796 u16 reg_phy_ext; 1797 s32 ret_val; 1798 1799 /* Check if SFP module is supported and linear */ 1800 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1801 1802 /* If no SFP module present, then return success. Return success since 1803 * SFP not present error is not excepted in the setup MAC link flow. 1804 */ 1805 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1806 return 0; 1807 1808 if (ret_val) 1809 return ret_val; 1810 1811 /* Configure internal PHY for KR/KX. */ 1812 ixgbe_setup_kr_speed_x550em(hw, speed); 1813 1814 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1815 return IXGBE_ERR_PHY_ADDR_INVALID; 1816 1817 /* Get external PHY SKU id */ 1818 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 1819 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1820 if (ret_val) 1821 return ret_val; 1822 1823 /* When configuring quad port CS4223, the MAC instance is part 1824 * of the slice offset. 1825 */ 1826 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 1827 slice_offset = (hw->bus.lan_id + 1828 (hw->bus.instance_id << 1)) << 12; 1829 else 1830 slice_offset = hw->bus.lan_id << 12; 1831 1832 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1833 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1834 1835 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 1836 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1837 if (ret_val) 1838 return ret_val; 1839 1840 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1841 (IXGBE_CS4227_EDC_MODE_SR << 1)); 1842 1843 if (setup_linear) 1844 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1845 else 1846 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1847 1848 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 1849 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 1850 if (ret_val) 1851 return ret_val; 1852 1853 /* Flush previous write with a read */ 1854 return hw->phy.ops.read_reg(hw, reg_slice, 1855 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1856 } 1857 1858 /** 1859 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1860 * @hw: pointer to hardware structure 1861 * @speed: new link speed 1862 * @autoneg_wait_to_complete: true when waiting for completion is needed 1863 * 1864 * Setup internal/external PHY link speed based on link speed, then set 1865 * external PHY auto advertised link speed. 1866 * 1867 * Returns error status for any failure 1868 **/ 1869 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1870 ixgbe_link_speed speed, 1871 bool autoneg_wait) 1872 { 1873 s32 status; 1874 ixgbe_link_speed force_speed; 1875 1876 /* Setup internal/external PHY link speed to iXFI (10G), unless 1877 * only 1G is auto advertised then setup KX link. 1878 */ 1879 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1880 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1881 else 1882 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1883 1884 /* If X552 and internal link mode is XFI, then setup XFI internal link. 1885 */ 1886 if (hw->mac.type == ixgbe_mac_X550EM_x && 1887 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1888 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1889 1890 if (status) 1891 return status; 1892 } 1893 1894 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1895 } 1896 1897 /** ixgbe_check_link_t_X550em - Determine link and speed status 1898 * @hw: pointer to hardware structure 1899 * @speed: pointer to link speed 1900 * @link_up: true when link is up 1901 * @link_up_wait_to_complete: bool used to wait for link up or not 1902 * 1903 * Check that both the MAC and X557 external PHY have link. 1904 **/ 1905 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1906 ixgbe_link_speed *speed, 1907 bool *link_up, 1908 bool link_up_wait_to_complete) 1909 { 1910 u32 status; 1911 u16 i, autoneg_status; 1912 1913 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1914 return IXGBE_ERR_CONFIG; 1915 1916 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1917 link_up_wait_to_complete); 1918 1919 /* If check link fails or MAC link is not up, then return */ 1920 if (status || !(*link_up)) 1921 return status; 1922 1923 /* MAC link is up, so check external PHY link. 1924 * Link status is latching low, and can only be used to detect link 1925 * drop, and not the current status of the link without performing 1926 * back-to-back reads. 1927 */ 1928 for (i = 0; i < 2; i++) { 1929 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1930 &autoneg_status); 1931 1932 if (status) 1933 return status; 1934 } 1935 1936 /* If external PHY link is not up, then indicate link not up */ 1937 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1938 *link_up = false; 1939 1940 return 0; 1941 } 1942 1943 /** 1944 * ixgbe_setup_sgmii - Set up link for sgmii 1945 * @hw: pointer to hardware structure 1946 */ 1947 static s32 1948 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1949 __always_unused bool autoneg_wait_to_complete) 1950 { 1951 struct ixgbe_mac_info *mac = &hw->mac; 1952 u32 lval, sval, flx_val; 1953 s32 rc; 1954 1955 rc = mac->ops.read_iosf_sb_reg(hw, 1956 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1957 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1958 if (rc) 1959 return rc; 1960 1961 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1962 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1963 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1964 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1965 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1966 rc = mac->ops.write_iosf_sb_reg(hw, 1967 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1968 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1969 if (rc) 1970 return rc; 1971 1972 rc = mac->ops.read_iosf_sb_reg(hw, 1973 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1974 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1975 if (rc) 1976 return rc; 1977 1978 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1979 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1980 rc = mac->ops.write_iosf_sb_reg(hw, 1981 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1982 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1983 if (rc) 1984 return rc; 1985 1986 rc = mac->ops.read_iosf_sb_reg(hw, 1987 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1988 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1989 if (rc) 1990 return rc; 1991 1992 rc = mac->ops.read_iosf_sb_reg(hw, 1993 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1994 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1995 if (rc) 1996 return rc; 1997 1998 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1999 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2000 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2001 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2002 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2003 2004 rc = mac->ops.write_iosf_sb_reg(hw, 2005 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2006 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2007 if (rc) 2008 return rc; 2009 2010 rc = ixgbe_restart_an_internal_phy_x550em(hw); 2011 return rc; 2012 } 2013 2014 /** 2015 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 2016 * @hw: pointer to hardware structure 2017 */ 2018 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 2019 bool autoneg_wait) 2020 { 2021 struct ixgbe_mac_info *mac = &hw->mac; 2022 u32 lval, sval, flx_val; 2023 s32 rc; 2024 2025 rc = mac->ops.read_iosf_sb_reg(hw, 2026 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2027 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2028 if (rc) 2029 return rc; 2030 2031 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2032 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2033 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2034 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2035 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2036 rc = mac->ops.write_iosf_sb_reg(hw, 2037 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2038 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2039 if (rc) 2040 return rc; 2041 2042 rc = mac->ops.read_iosf_sb_reg(hw, 2043 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2044 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2045 if (rc) 2046 return rc; 2047 2048 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2049 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2050 rc = mac->ops.write_iosf_sb_reg(hw, 2051 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2052 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2053 if (rc) 2054 return rc; 2055 2056 rc = mac->ops.write_iosf_sb_reg(hw, 2057 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2058 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2059 if (rc) 2060 return rc; 2061 2062 rc = mac->ops.read_iosf_sb_reg(hw, 2063 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2064 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2065 if (rc) 2066 return rc; 2067 2068 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2069 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2070 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2071 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2072 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2073 2074 rc = mac->ops.write_iosf_sb_reg(hw, 2075 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2076 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2077 if (rc) 2078 return rc; 2079 2080 ixgbe_restart_an_internal_phy_x550em(hw); 2081 2082 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2083 } 2084 2085 /** 2086 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2087 * @hw: pointer to hardware structure 2088 * 2089 * Enable flow control according to IEEE clause 37. 2090 */ 2091 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2092 { 2093 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2094 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2095 ixgbe_link_speed speed; 2096 bool link_up; 2097 2098 /* AN should have completed when the cable was plugged in. 2099 * Look for reasons to bail out. Bail out if: 2100 * - FC autoneg is disabled, or if 2101 * - link is not up. 2102 */ 2103 if (hw->fc.disable_fc_autoneg) 2104 goto out; 2105 2106 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2107 if (!link_up) 2108 goto out; 2109 2110 /* Check if auto-negotiation has completed */ 2111 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2112 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2113 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2114 goto out; 2115 } 2116 2117 /* Negotiate the flow control */ 2118 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2119 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2120 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2121 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2122 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2123 2124 out: 2125 if (!status) { 2126 hw->fc.fc_was_autonegged = true; 2127 } else { 2128 hw->fc.fc_was_autonegged = false; 2129 hw->fc.current_mode = hw->fc.requested_mode; 2130 } 2131 } 2132 2133 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2134 * @hw: pointer to hardware structure 2135 **/ 2136 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2137 { 2138 struct ixgbe_mac_info *mac = &hw->mac; 2139 2140 switch (mac->ops.get_media_type(hw)) { 2141 case ixgbe_media_type_fiber: 2142 mac->ops.setup_fc = NULL; 2143 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2144 break; 2145 case ixgbe_media_type_copper: 2146 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2147 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2148 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2149 break; 2150 } 2151 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2152 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2153 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2154 mac->ops.check_link = ixgbe_check_mac_link_generic; 2155 break; 2156 case ixgbe_media_type_backplane: 2157 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2158 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2159 break; 2160 default: 2161 break; 2162 } 2163 } 2164 2165 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2166 * @hw: pointer to hardware structure 2167 **/ 2168 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2169 { 2170 struct ixgbe_mac_info *mac = &hw->mac; 2171 2172 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2173 2174 switch (mac->ops.get_media_type(hw)) { 2175 case ixgbe_media_type_fiber: 2176 /* CS4227 does not support autoneg, so disable the laser control 2177 * functions for SFP+ fiber 2178 */ 2179 mac->ops.disable_tx_laser = NULL; 2180 mac->ops.enable_tx_laser = NULL; 2181 mac->ops.flap_tx_laser = NULL; 2182 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2183 switch (hw->device_id) { 2184 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2185 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2186 break; 2187 case IXGBE_DEV_ID_X550EM_A_SFP: 2188 mac->ops.setup_mac_link = 2189 ixgbe_setup_mac_link_sfp_x550a; 2190 break; 2191 default: 2192 mac->ops.setup_mac_link = 2193 ixgbe_setup_mac_link_sfp_x550em; 2194 break; 2195 } 2196 mac->ops.set_rate_select_speed = 2197 ixgbe_set_soft_rate_select_speed; 2198 break; 2199 case ixgbe_media_type_copper: 2200 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2201 break; 2202 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2203 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2204 mac->ops.check_link = ixgbe_check_link_t_X550em; 2205 break; 2206 case ixgbe_media_type_backplane: 2207 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2208 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2209 mac->ops.setup_link = ixgbe_setup_sgmii; 2210 break; 2211 default: 2212 break; 2213 } 2214 2215 /* Additional modification for X550em_a devices */ 2216 if (hw->mac.type == ixgbe_mac_x550em_a) 2217 ixgbe_init_mac_link_ops_X550em_a(hw); 2218 } 2219 2220 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2221 * @hw: pointer to hardware structure 2222 */ 2223 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2224 { 2225 s32 status; 2226 bool linear; 2227 2228 /* Check if SFP module is supported */ 2229 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2230 if (status) 2231 return status; 2232 2233 ixgbe_init_mac_link_ops_X550em(hw); 2234 hw->phy.ops.reset = NULL; 2235 2236 return 0; 2237 } 2238 2239 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2240 * @hw: pointer to hardware structure 2241 * @speed: pointer to link speed 2242 * @autoneg: true when autoneg or autotry is enabled 2243 **/ 2244 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2245 ixgbe_link_speed *speed, 2246 bool *autoneg) 2247 { 2248 if (hw->phy.type == ixgbe_phy_fw) { 2249 *autoneg = true; 2250 *speed = hw->phy.speeds_supported; 2251 return 0; 2252 } 2253 2254 /* SFP */ 2255 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2256 /* CS4227 SFP must not enable auto-negotiation */ 2257 *autoneg = false; 2258 2259 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2260 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 2261 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2262 return 0; 2263 } 2264 2265 /* Link capabilities are based on SFP */ 2266 if (hw->phy.multispeed_fiber) 2267 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2268 IXGBE_LINK_SPEED_1GB_FULL; 2269 else 2270 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2271 } else { 2272 switch (hw->phy.type) { 2273 case ixgbe_phy_x550em_kx4: 2274 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2275 IXGBE_LINK_SPEED_2_5GB_FULL | 2276 IXGBE_LINK_SPEED_10GB_FULL; 2277 break; 2278 case ixgbe_phy_x550em_xfi: 2279 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2280 IXGBE_LINK_SPEED_10GB_FULL; 2281 break; 2282 case ixgbe_phy_ext_1g_t: 2283 case ixgbe_phy_sgmii: 2284 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2285 break; 2286 case ixgbe_phy_x550em_kr: 2287 if (hw->mac.type == ixgbe_mac_x550em_a) { 2288 /* check different backplane modes */ 2289 if (hw->phy.nw_mng_if_sel & 2290 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2291 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2292 break; 2293 } else if (hw->device_id == 2294 IXGBE_DEV_ID_X550EM_A_KR_L) { 2295 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2296 break; 2297 } 2298 } 2299 /* fall through */ 2300 default: 2301 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2302 IXGBE_LINK_SPEED_1GB_FULL; 2303 break; 2304 } 2305 *autoneg = true; 2306 } 2307 return 0; 2308 } 2309 2310 /** 2311 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2312 * @hw: pointer to hardware structure 2313 * @lsc: pointer to boolean flag which indicates whether external Base T 2314 * PHY interrupt is lsc 2315 * 2316 * Determime if external Base T PHY interrupt cause is high temperature 2317 * failure alarm or link status change. 2318 * 2319 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2320 * failure alarm, else return PHY access status. 2321 **/ 2322 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2323 { 2324 u32 status; 2325 u16 reg; 2326 2327 *lsc = false; 2328 2329 /* Vendor alarm triggered */ 2330 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2331 MDIO_MMD_VEND1, 2332 ®); 2333 2334 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2335 return status; 2336 2337 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2339 MDIO_MMD_VEND1, 2340 ®); 2341 2342 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2343 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2344 return status; 2345 2346 /* Global alarm triggered */ 2347 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2348 MDIO_MMD_VEND1, 2349 ®); 2350 2351 if (status) 2352 return status; 2353 2354 /* If high temperature failure, then return over temp error and exit */ 2355 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2356 /* power down the PHY in case the PHY FW didn't already */ 2357 ixgbe_set_copper_phy_power(hw, false); 2358 return IXGBE_ERR_OVERTEMP; 2359 } 2360 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2361 /* device fault alarm triggered */ 2362 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2363 MDIO_MMD_VEND1, 2364 ®); 2365 if (status) 2366 return status; 2367 2368 /* if device fault was due to high temp alarm handle and exit */ 2369 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2370 /* power down the PHY in case the PHY FW didn't */ 2371 ixgbe_set_copper_phy_power(hw, false); 2372 return IXGBE_ERR_OVERTEMP; 2373 } 2374 } 2375 2376 /* Vendor alarm 2 triggered */ 2377 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2378 MDIO_MMD_AN, ®); 2379 2380 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2381 return status; 2382 2383 /* link connect/disconnect event occurred */ 2384 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2385 MDIO_MMD_AN, ®); 2386 2387 if (status) 2388 return status; 2389 2390 /* Indicate LSC */ 2391 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2392 *lsc = true; 2393 2394 return 0; 2395 } 2396 2397 /** 2398 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2399 * @hw: pointer to hardware structure 2400 * 2401 * Enable link status change and temperature failure alarm for the external 2402 * Base T PHY 2403 * 2404 * Returns PHY access status 2405 **/ 2406 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2407 { 2408 u32 status; 2409 u16 reg; 2410 bool lsc; 2411 2412 /* Clear interrupt flags */ 2413 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2414 2415 /* Enable link status change alarm */ 2416 2417 /* Enable the LASI interrupts on X552 devices to receive notifications 2418 * of the link configurations of the external PHY and correspondingly 2419 * support the configuration of the internal iXFI link, since iXFI does 2420 * not support auto-negotiation. This is not required for X553 devices 2421 * having KR support, which performs auto-negotiations and which is used 2422 * as the internal link to the external PHY. Hence adding a check here 2423 * to avoid enabling LASI interrupts for X553 devices. 2424 */ 2425 if (hw->mac.type != ixgbe_mac_x550em_a) { 2426 status = hw->phy.ops.read_reg(hw, 2427 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2428 MDIO_MMD_AN, ®); 2429 if (status) 2430 return status; 2431 2432 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2433 2434 status = hw->phy.ops.write_reg(hw, 2435 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2436 MDIO_MMD_AN, reg); 2437 if (status) 2438 return status; 2439 } 2440 2441 /* Enable high temperature failure and global fault alarms */ 2442 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2443 MDIO_MMD_VEND1, 2444 ®); 2445 if (status) 2446 return status; 2447 2448 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2449 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2450 2451 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2452 MDIO_MMD_VEND1, 2453 reg); 2454 if (status) 2455 return status; 2456 2457 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2458 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2459 MDIO_MMD_VEND1, 2460 ®); 2461 if (status) 2462 return status; 2463 2464 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2465 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2466 2467 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2468 MDIO_MMD_VEND1, 2469 reg); 2470 if (status) 2471 return status; 2472 2473 /* Enable chip-wide vendor alarm */ 2474 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2475 MDIO_MMD_VEND1, 2476 ®); 2477 if (status) 2478 return status; 2479 2480 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2481 2482 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2483 MDIO_MMD_VEND1, 2484 reg); 2485 2486 return status; 2487 } 2488 2489 /** 2490 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2491 * @hw: pointer to hardware structure 2492 * 2493 * Handle external Base T PHY interrupt. If high temperature 2494 * failure alarm then return error, else if link status change 2495 * then setup internal/external PHY link 2496 * 2497 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2498 * failure alarm, else return PHY access status. 2499 **/ 2500 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2501 { 2502 struct ixgbe_phy_info *phy = &hw->phy; 2503 bool lsc; 2504 u32 status; 2505 2506 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2507 if (status) 2508 return status; 2509 2510 if (lsc && phy->ops.setup_internal_link) 2511 return phy->ops.setup_internal_link(hw); 2512 2513 return 0; 2514 } 2515 2516 /** 2517 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2518 * @hw: pointer to hardware structure 2519 * @speed: link speed 2520 * 2521 * Configures the integrated KR PHY. 2522 **/ 2523 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2524 ixgbe_link_speed speed) 2525 { 2526 s32 status; 2527 u32 reg_val; 2528 2529 status = hw->mac.ops.read_iosf_sb_reg(hw, 2530 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2531 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2532 if (status) 2533 return status; 2534 2535 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2536 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2537 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2538 2539 /* Advertise 10G support. */ 2540 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2541 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2542 2543 /* Advertise 1G support. */ 2544 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2545 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2546 2547 status = hw->mac.ops.write_iosf_sb_reg(hw, 2548 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2549 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2550 2551 if (hw->mac.type == ixgbe_mac_x550em_a) { 2552 /* Set lane mode to KR auto negotiation */ 2553 status = hw->mac.ops.read_iosf_sb_reg(hw, 2554 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2555 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2556 2557 if (status) 2558 return status; 2559 2560 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2561 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2562 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2563 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2564 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2565 2566 status = hw->mac.ops.write_iosf_sb_reg(hw, 2567 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2568 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2569 } 2570 2571 return ixgbe_restart_an_internal_phy_x550em(hw); 2572 } 2573 2574 /** 2575 * ixgbe_setup_kr_x550em - Configure the KR PHY 2576 * @hw: pointer to hardware structure 2577 **/ 2578 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2579 { 2580 /* leave link alone for 2.5G */ 2581 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2582 return 0; 2583 2584 if (ixgbe_check_reset_blocked(hw)) 2585 return 0; 2586 2587 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2588 } 2589 2590 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2591 * @hw: address of hardware structure 2592 * @link_up: address of boolean to indicate link status 2593 * 2594 * Returns error code if unable to get link status. 2595 **/ 2596 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2597 { 2598 u32 ret; 2599 u16 autoneg_status; 2600 2601 *link_up = false; 2602 2603 /* read this twice back to back to indicate current status */ 2604 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2605 &autoneg_status); 2606 if (ret) 2607 return ret; 2608 2609 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2610 &autoneg_status); 2611 if (ret) 2612 return ret; 2613 2614 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2615 2616 return 0; 2617 } 2618 2619 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2620 * @hw: point to hardware structure 2621 * 2622 * Configures the link between the integrated KR PHY and the external X557 PHY 2623 * The driver will call this function when it gets a link status change 2624 * interrupt from the X557 PHY. This function configures the link speed 2625 * between the PHYs to match the link speed of the BASE-T link. 2626 * 2627 * A return of a non-zero value indicates an error, and the base driver should 2628 * not report link up. 2629 **/ 2630 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2631 { 2632 ixgbe_link_speed force_speed; 2633 bool link_up; 2634 u32 status; 2635 u16 speed; 2636 2637 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2638 return IXGBE_ERR_CONFIG; 2639 2640 if (!(hw->mac.type == ixgbe_mac_X550EM_x && 2641 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) { 2642 speed = IXGBE_LINK_SPEED_10GB_FULL | 2643 IXGBE_LINK_SPEED_1GB_FULL; 2644 return ixgbe_setup_kr_speed_x550em(hw, speed); 2645 } 2646 2647 /* If link is not up, then there is no setup necessary so return */ 2648 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2649 if (status) 2650 return status; 2651 2652 if (!link_up) 2653 return 0; 2654 2655 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2656 MDIO_MMD_AN, 2657 &speed); 2658 if (status) 2659 return status; 2660 2661 /* If link is not still up, then no setup is necessary so return */ 2662 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2663 if (status) 2664 return status; 2665 2666 if (!link_up) 2667 return 0; 2668 2669 /* clear everything but the speed and duplex bits */ 2670 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2671 2672 switch (speed) { 2673 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2674 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2675 break; 2676 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2677 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2678 break; 2679 default: 2680 /* Internal PHY does not support anything else */ 2681 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2682 } 2683 2684 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2685 } 2686 2687 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2688 * @hw: pointer to hardware structure 2689 **/ 2690 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2691 { 2692 s32 status; 2693 2694 status = ixgbe_reset_phy_generic(hw); 2695 2696 if (status) 2697 return status; 2698 2699 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2700 return ixgbe_enable_lasi_ext_t_x550em(hw); 2701 } 2702 2703 /** 2704 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2705 * @hw: pointer to hardware structure 2706 * @led_idx: led number to turn on 2707 **/ 2708 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2709 { 2710 u16 phy_data; 2711 2712 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2713 return IXGBE_ERR_PARAM; 2714 2715 /* To turn on the LED, set mode to ON. */ 2716 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2717 MDIO_MMD_VEND1, &phy_data); 2718 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2719 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2720 MDIO_MMD_VEND1, phy_data); 2721 2722 return 0; 2723 } 2724 2725 /** 2726 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2727 * @hw: pointer to hardware structure 2728 * @led_idx: led number to turn off 2729 **/ 2730 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2731 { 2732 u16 phy_data; 2733 2734 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2735 return IXGBE_ERR_PARAM; 2736 2737 /* To turn on the LED, set mode to ON. */ 2738 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2739 MDIO_MMD_VEND1, &phy_data); 2740 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2741 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2742 MDIO_MMD_VEND1, phy_data); 2743 2744 return 0; 2745 } 2746 2747 /** 2748 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2749 * @hw: pointer to the HW structure 2750 * @maj: driver version major number 2751 * @min: driver version minor number 2752 * @build: driver version build number 2753 * @sub: driver version sub build number 2754 * @len: length of driver_ver string 2755 * @driver_ver: driver string 2756 * 2757 * Sends driver version number to firmware through the manageability 2758 * block. On success return 0 2759 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 2760 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 2761 **/ 2762 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2763 u8 build, u8 sub, u16 len, 2764 const char *driver_ver) 2765 { 2766 struct ixgbe_hic_drv_info2 fw_cmd; 2767 s32 ret_val; 2768 int i; 2769 2770 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2771 return IXGBE_ERR_INVALID_ARGUMENT; 2772 2773 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2774 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2775 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2776 fw_cmd.port_num = (u8)hw->bus.func; 2777 fw_cmd.ver_maj = maj; 2778 fw_cmd.ver_min = min; 2779 fw_cmd.ver_build = build; 2780 fw_cmd.ver_sub = sub; 2781 fw_cmd.hdr.checksum = 0; 2782 memcpy(fw_cmd.driver_string, driver_ver, len); 2783 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2784 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2785 2786 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2787 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2788 sizeof(fw_cmd), 2789 IXGBE_HI_COMMAND_TIMEOUT, 2790 true); 2791 if (ret_val) 2792 continue; 2793 2794 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2795 FW_CEM_RESP_STATUS_SUCCESS) 2796 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 2797 return 0; 2798 } 2799 2800 return ret_val; 2801 } 2802 2803 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2804 * @hw: pointer to hardware structure 2805 * @lcd_speed: pointer to lowest common link speed 2806 * 2807 * Determine lowest common link speed with link partner. 2808 **/ 2809 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2810 ixgbe_link_speed *lcd_speed) 2811 { 2812 u16 an_lp_status; 2813 s32 status; 2814 u16 word = hw->eeprom.ctrl_word_3; 2815 2816 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2817 2818 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2819 MDIO_MMD_AN, 2820 &an_lp_status); 2821 if (status) 2822 return status; 2823 2824 /* If link partner advertised 1G, return 1G */ 2825 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2826 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2827 return status; 2828 } 2829 2830 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2831 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2832 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2833 return status; 2834 2835 /* Link partner not capable of lower speeds, return 10G */ 2836 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2837 return status; 2838 } 2839 2840 /** 2841 * ixgbe_setup_fc_x550em - Set up flow control 2842 * @hw: pointer to hardware structure 2843 */ 2844 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2845 { 2846 bool pause, asm_dir; 2847 u32 reg_val; 2848 s32 rc = 0; 2849 2850 /* Validate the requested mode */ 2851 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2852 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2853 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2854 } 2855 2856 /* 10gig parts do not have a word in the EEPROM to determine the 2857 * default flow control setting, so we explicitly set it to full. 2858 */ 2859 if (hw->fc.requested_mode == ixgbe_fc_default) 2860 hw->fc.requested_mode = ixgbe_fc_full; 2861 2862 /* Determine PAUSE and ASM_DIR bits. */ 2863 switch (hw->fc.requested_mode) { 2864 case ixgbe_fc_none: 2865 pause = false; 2866 asm_dir = false; 2867 break; 2868 case ixgbe_fc_tx_pause: 2869 pause = false; 2870 asm_dir = true; 2871 break; 2872 case ixgbe_fc_rx_pause: 2873 /* Rx Flow control is enabled and Tx Flow control is 2874 * disabled by software override. Since there really 2875 * isn't a way to advertise that we are capable of RX 2876 * Pause ONLY, we will advertise that we support both 2877 * symmetric and asymmetric Rx PAUSE, as such we fall 2878 * through to the fc_full statement. Later, we will 2879 * disable the adapter's ability to send PAUSE frames. 2880 */ 2881 /* Fallthrough */ 2882 case ixgbe_fc_full: 2883 pause = true; 2884 asm_dir = true; 2885 break; 2886 default: 2887 hw_err(hw, "Flow control param set incorrectly\n"); 2888 return IXGBE_ERR_CONFIG; 2889 } 2890 2891 switch (hw->device_id) { 2892 case IXGBE_DEV_ID_X550EM_X_KR: 2893 case IXGBE_DEV_ID_X550EM_A_KR: 2894 case IXGBE_DEV_ID_X550EM_A_KR_L: 2895 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2896 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2897 IXGBE_SB_IOSF_TARGET_KR_PHY, 2898 ®_val); 2899 if (rc) 2900 return rc; 2901 2902 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2903 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2904 if (pause) 2905 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2906 if (asm_dir) 2907 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2908 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2909 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2910 IXGBE_SB_IOSF_TARGET_KR_PHY, 2911 reg_val); 2912 2913 /* This device does not fully support AN. */ 2914 hw->fc.disable_fc_autoneg = true; 2915 break; 2916 case IXGBE_DEV_ID_X550EM_X_XFI: 2917 hw->fc.disable_fc_autoneg = true; 2918 break; 2919 default: 2920 break; 2921 } 2922 return rc; 2923 } 2924 2925 /** 2926 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2927 * @hw: pointer to hardware structure 2928 **/ 2929 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2930 { 2931 u32 link_s1, lp_an_page_low, an_cntl_1; 2932 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2933 ixgbe_link_speed speed; 2934 bool link_up; 2935 2936 /* AN should have completed when the cable was plugged in. 2937 * Look for reasons to bail out. Bail out if: 2938 * - FC autoneg is disabled, or if 2939 * - link is not up. 2940 */ 2941 if (hw->fc.disable_fc_autoneg) { 2942 hw_err(hw, "Flow control autoneg is disabled"); 2943 goto out; 2944 } 2945 2946 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2947 if (!link_up) { 2948 hw_err(hw, "The link is down"); 2949 goto out; 2950 } 2951 2952 /* Check at auto-negotiation has completed */ 2953 status = hw->mac.ops.read_iosf_sb_reg(hw, 2954 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2955 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2956 2957 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2958 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2959 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2960 goto out; 2961 } 2962 2963 /* Read the 10g AN autoc and LP ability registers and resolve 2964 * local flow control settings accordingly 2965 */ 2966 status = hw->mac.ops.read_iosf_sb_reg(hw, 2967 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2968 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2969 2970 if (status) { 2971 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2972 goto out; 2973 } 2974 2975 status = hw->mac.ops.read_iosf_sb_reg(hw, 2976 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2977 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2978 2979 if (status) { 2980 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2981 goto out; 2982 } 2983 2984 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2985 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2986 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2987 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2988 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2989 2990 out: 2991 if (!status) { 2992 hw->fc.fc_was_autonegged = true; 2993 } else { 2994 hw->fc.fc_was_autonegged = false; 2995 hw->fc.current_mode = hw->fc.requested_mode; 2996 } 2997 } 2998 2999 /** 3000 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 3001 * @hw: pointer to hardware structure 3002 **/ 3003 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 3004 { 3005 hw->fc.fc_was_autonegged = false; 3006 hw->fc.current_mode = hw->fc.requested_mode; 3007 } 3008 3009 /** ixgbe_enter_lplu_x550em - Transition to low power states 3010 * @hw: pointer to hardware structure 3011 * 3012 * Configures Low Power Link Up on transition to low power states 3013 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 3014 * the X557 PHY immediately prior to entering LPLU. 3015 **/ 3016 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3017 { 3018 u16 an_10g_cntl_reg, autoneg_reg, speed; 3019 s32 status; 3020 ixgbe_link_speed lcd_speed; 3021 u32 save_autoneg; 3022 bool link_up; 3023 3024 /* If blocked by MNG FW, then don't restart AN */ 3025 if (ixgbe_check_reset_blocked(hw)) 3026 return 0; 3027 3028 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3029 if (status) 3030 return status; 3031 3032 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 3033 &hw->eeprom.ctrl_word_3); 3034 if (status) 3035 return status; 3036 3037 /* If link is down, LPLU disabled in NVM, WoL disabled, or 3038 * manageability disabled, then force link down by entering 3039 * low power mode. 3040 */ 3041 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3042 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3043 return ixgbe_set_copper_phy_power(hw, false); 3044 3045 /* Determine LCD */ 3046 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3047 if (status) 3048 return status; 3049 3050 /* If no valid LCD link speed, then force link down and exit. */ 3051 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3052 return ixgbe_set_copper_phy_power(hw, false); 3053 3054 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3055 MDIO_MMD_AN, 3056 &speed); 3057 if (status) 3058 return status; 3059 3060 /* If no link now, speed is invalid so take link down */ 3061 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3062 if (status) 3063 return ixgbe_set_copper_phy_power(hw, false); 3064 3065 /* clear everything but the speed bits */ 3066 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3067 3068 /* If current speed is already LCD, then exit. */ 3069 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3070 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3071 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3072 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3073 return status; 3074 3075 /* Clear AN completed indication */ 3076 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3077 MDIO_MMD_AN, 3078 &autoneg_reg); 3079 if (status) 3080 return status; 3081 3082 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3083 MDIO_MMD_AN, 3084 &an_10g_cntl_reg); 3085 if (status) 3086 return status; 3087 3088 status = hw->phy.ops.read_reg(hw, 3089 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3090 MDIO_MMD_AN, 3091 &autoneg_reg); 3092 if (status) 3093 return status; 3094 3095 save_autoneg = hw->phy.autoneg_advertised; 3096 3097 /* Setup link at least common link speed */ 3098 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3099 3100 /* restore autoneg from before setting lplu speed */ 3101 hw->phy.autoneg_advertised = save_autoneg; 3102 3103 return status; 3104 } 3105 3106 /** 3107 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3108 * @hw: pointer to hardware structure 3109 */ 3110 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3111 { 3112 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3113 s32 rc; 3114 3115 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3116 return 0; 3117 3118 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3119 if (rc) 3120 return rc; 3121 memset(store, 0, sizeof(store)); 3122 3123 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3124 if (rc) 3125 return rc; 3126 3127 return ixgbe_setup_fw_link(hw); 3128 } 3129 3130 /** 3131 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3132 * @hw: pointer to hardware structure 3133 */ 3134 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3135 { 3136 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3137 s32 rc; 3138 3139 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3140 if (rc) 3141 return rc; 3142 3143 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3144 ixgbe_shutdown_fw_phy(hw); 3145 return IXGBE_ERR_OVERTEMP; 3146 } 3147 return 0; 3148 } 3149 3150 /** 3151 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3152 * @hw: pointer to hardware structure 3153 * 3154 * Read NW_MNG_IF_SEL register and save field values. 3155 */ 3156 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3157 { 3158 /* Save NW management interface connected on board. This is used 3159 * to determine internal PHY mode. 3160 */ 3161 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3162 3163 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3164 * PHY address. This register field was has only been used for X552. 3165 */ 3166 if (hw->mac.type == ixgbe_mac_x550em_a && 3167 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3168 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 3169 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 3170 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 3171 } 3172 } 3173 3174 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3175 * @hw: pointer to hardware structure 3176 * 3177 * Initialize any function pointers that were not able to be 3178 * set during init_shared_code because the PHY/SFP type was 3179 * not known. Perform the SFP init if necessary. 3180 **/ 3181 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3182 { 3183 struct ixgbe_phy_info *phy = &hw->phy; 3184 s32 ret_val; 3185 3186 hw->mac.ops.set_lan_id(hw); 3187 3188 ixgbe_read_mng_if_sel_x550em(hw); 3189 3190 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3191 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3192 ixgbe_setup_mux_ctl(hw); 3193 } 3194 3195 /* Identify the PHY or SFP module */ 3196 ret_val = phy->ops.identify(hw); 3197 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 3198 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 3199 return ret_val; 3200 3201 /* Setup function pointers based on detected hardware */ 3202 ixgbe_init_mac_link_ops_X550em(hw); 3203 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3204 phy->ops.reset = NULL; 3205 3206 /* Set functions pointers based on phy type */ 3207 switch (hw->phy.type) { 3208 case ixgbe_phy_x550em_kx4: 3209 phy->ops.setup_link = NULL; 3210 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3211 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3212 break; 3213 case ixgbe_phy_x550em_kr: 3214 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3215 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3216 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3217 break; 3218 case ixgbe_phy_x550em_xfi: 3219 /* link is managed by HW */ 3220 phy->ops.setup_link = NULL; 3221 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3222 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3223 break; 3224 case ixgbe_phy_x550em_ext_t: 3225 /* Save NW management interface connected on board. This is used 3226 * to determine internal PHY mode 3227 */ 3228 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3229 3230 /* If internal link mode is XFI, then setup iXFI internal link, 3231 * else setup KR now. 3232 */ 3233 phy->ops.setup_internal_link = 3234 ixgbe_setup_internal_phy_t_x550em; 3235 3236 /* setup SW LPLU only for first revision */ 3237 if (hw->mac.type == ixgbe_mac_X550EM_x && 3238 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3239 IXGBE_FUSES0_REV_MASK)) 3240 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3241 3242 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3243 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3244 break; 3245 case ixgbe_phy_sgmii: 3246 phy->ops.setup_link = NULL; 3247 break; 3248 case ixgbe_phy_fw: 3249 phy->ops.setup_link = ixgbe_setup_fw_link; 3250 phy->ops.reset = ixgbe_reset_phy_fw; 3251 break; 3252 case ixgbe_phy_ext_1g_t: 3253 phy->ops.setup_link = NULL; 3254 phy->ops.read_reg = NULL; 3255 phy->ops.write_reg = NULL; 3256 phy->ops.reset = NULL; 3257 break; 3258 default: 3259 break; 3260 } 3261 3262 return ret_val; 3263 } 3264 3265 /** ixgbe_get_media_type_X550em - Get media type 3266 * @hw: pointer to hardware structure 3267 * 3268 * Returns the media type (fiber, copper, backplane) 3269 * 3270 */ 3271 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3272 { 3273 enum ixgbe_media_type media_type; 3274 3275 /* Detect if there is a copper PHY attached. */ 3276 switch (hw->device_id) { 3277 case IXGBE_DEV_ID_X550EM_A_SGMII: 3278 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3279 hw->phy.type = ixgbe_phy_sgmii; 3280 /* Fallthrough */ 3281 case IXGBE_DEV_ID_X550EM_X_KR: 3282 case IXGBE_DEV_ID_X550EM_X_KX4: 3283 case IXGBE_DEV_ID_X550EM_X_XFI: 3284 case IXGBE_DEV_ID_X550EM_A_KR: 3285 case IXGBE_DEV_ID_X550EM_A_KR_L: 3286 media_type = ixgbe_media_type_backplane; 3287 break; 3288 case IXGBE_DEV_ID_X550EM_X_SFP: 3289 case IXGBE_DEV_ID_X550EM_A_SFP: 3290 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3291 media_type = ixgbe_media_type_fiber; 3292 break; 3293 case IXGBE_DEV_ID_X550EM_X_1G_T: 3294 case IXGBE_DEV_ID_X550EM_X_10G_T: 3295 case IXGBE_DEV_ID_X550EM_A_10G_T: 3296 case IXGBE_DEV_ID_X550EM_A_1G_T: 3297 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3298 media_type = ixgbe_media_type_copper; 3299 break; 3300 default: 3301 media_type = ixgbe_media_type_unknown; 3302 break; 3303 } 3304 return media_type; 3305 } 3306 3307 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3308 ** @hw: pointer to hardware structure 3309 **/ 3310 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3311 { 3312 s32 status; 3313 u16 reg; 3314 3315 status = hw->phy.ops.read_reg(hw, 3316 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3317 MDIO_MMD_PMAPMD, 3318 ®); 3319 if (status) 3320 return status; 3321 3322 /* If PHY FW reset completed bit is set then this is the first 3323 * SW instance after a power on so the PHY FW must be un-stalled. 3324 */ 3325 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3326 status = hw->phy.ops.read_reg(hw, 3327 IXGBE_MDIO_GLOBAL_RES_PR_10, 3328 MDIO_MMD_VEND1, 3329 ®); 3330 if (status) 3331 return status; 3332 3333 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3334 3335 status = hw->phy.ops.write_reg(hw, 3336 IXGBE_MDIO_GLOBAL_RES_PR_10, 3337 MDIO_MMD_VEND1, 3338 reg); 3339 if (status) 3340 return status; 3341 } 3342 3343 return status; 3344 } 3345 3346 /** 3347 * ixgbe_set_mdio_speed - Set MDIO clock speed 3348 * @hw: pointer to hardware structure 3349 */ 3350 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3351 { 3352 u32 hlreg0; 3353 3354 switch (hw->device_id) { 3355 case IXGBE_DEV_ID_X550EM_X_10G_T: 3356 case IXGBE_DEV_ID_X550EM_A_SGMII: 3357 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3358 case IXGBE_DEV_ID_X550EM_A_10G_T: 3359 case IXGBE_DEV_ID_X550EM_A_SFP: 3360 /* Config MDIO clock speed before the first MDIO PHY access */ 3361 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3362 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3363 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3364 break; 3365 case IXGBE_DEV_ID_X550EM_A_1G_T: 3366 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3367 /* Select fast MDIO clock speed for these devices */ 3368 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3369 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3370 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3371 break; 3372 default: 3373 break; 3374 } 3375 } 3376 3377 /** ixgbe_reset_hw_X550em - Perform hardware reset 3378 ** @hw: pointer to hardware structure 3379 ** 3380 ** Resets the hardware by resetting the transmit and receive units, masks 3381 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3382 ** reset. 3383 **/ 3384 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3385 { 3386 ixgbe_link_speed link_speed; 3387 s32 status; 3388 u32 ctrl = 0; 3389 u32 i; 3390 bool link_up = false; 3391 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3392 3393 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3394 status = hw->mac.ops.stop_adapter(hw); 3395 if (status) 3396 return status; 3397 3398 /* flush pending Tx transactions */ 3399 ixgbe_clear_tx_pending(hw); 3400 3401 /* PHY ops must be identified and initialized prior to reset */ 3402 status = hw->phy.ops.init(hw); 3403 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || 3404 status == IXGBE_ERR_PHY_ADDR_INVALID) 3405 return status; 3406 3407 /* start the external PHY */ 3408 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3409 status = ixgbe_init_ext_t_x550em(hw); 3410 if (status) 3411 return status; 3412 } 3413 3414 /* Setup SFP module if there is one present. */ 3415 if (hw->phy.sfp_setup_needed) { 3416 status = hw->mac.ops.setup_sfp(hw); 3417 hw->phy.sfp_setup_needed = false; 3418 } 3419 3420 /* Reset PHY */ 3421 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3422 hw->phy.ops.reset(hw); 3423 3424 mac_reset_top: 3425 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3426 * If link reset is used when link is up, it might reset the PHY when 3427 * mng is using it. If link is down or the flag to force full link 3428 * reset is set, then perform link reset. 3429 */ 3430 ctrl = IXGBE_CTRL_LNK_RST; 3431 3432 if (!hw->force_full_reset) { 3433 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3434 if (link_up) 3435 ctrl = IXGBE_CTRL_RST; 3436 } 3437 3438 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3439 if (status) { 3440 hw_dbg(hw, "semaphore failed with %d", status); 3441 return IXGBE_ERR_SWFW_SYNC; 3442 } 3443 3444 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3445 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3446 IXGBE_WRITE_FLUSH(hw); 3447 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3448 usleep_range(1000, 1200); 3449 3450 /* Poll for reset bit to self-clear meaning reset is complete */ 3451 for (i = 0; i < 10; i++) { 3452 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3453 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3454 break; 3455 udelay(1); 3456 } 3457 3458 if (ctrl & IXGBE_CTRL_RST_MASK) { 3459 status = IXGBE_ERR_RESET_FAILED; 3460 hw_dbg(hw, "Reset polling failed to complete.\n"); 3461 } 3462 3463 msleep(50); 3464 3465 /* Double resets are required for recovery from certain error 3466 * clear the multicast table. Also reset num_rar_entries to 128, 3467 * since we modify this value when programming the SAN MAC address. 3468 */ 3469 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3470 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3471 goto mac_reset_top; 3472 } 3473 3474 /* Store the permanent mac address */ 3475 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3476 3477 /* Store MAC address from RAR0, clear receive address registers, and 3478 * clear the multicast table. Also reset num_rar_entries to 128, 3479 * since we modify this value when programming the SAN MAC address. 3480 */ 3481 hw->mac.num_rar_entries = 128; 3482 hw->mac.ops.init_rx_addrs(hw); 3483 3484 ixgbe_set_mdio_speed(hw); 3485 3486 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3487 ixgbe_setup_mux_ctl(hw); 3488 3489 return status; 3490 } 3491 3492 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3493 * anti-spoofing 3494 * @hw: pointer to hardware structure 3495 * @enable: enable or disable switch for Ethertype anti-spoofing 3496 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3497 **/ 3498 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3499 bool enable, int vf) 3500 { 3501 int vf_target_reg = vf >> 3; 3502 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3503 u32 pfvfspoof; 3504 3505 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3506 if (enable) 3507 pfvfspoof |= BIT(vf_target_shift); 3508 else 3509 pfvfspoof &= ~BIT(vf_target_shift); 3510 3511 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3512 } 3513 3514 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3515 * @hw: pointer to hardware structure 3516 * @enable: enable or disable source address pruning 3517 * @pool: Rx pool to set source address pruning for 3518 **/ 3519 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3520 bool enable, 3521 unsigned int pool) 3522 { 3523 u64 pfflp; 3524 3525 /* max rx pool is 63 */ 3526 if (pool > 63) 3527 return; 3528 3529 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3530 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3531 3532 if (enable) 3533 pfflp |= (1ULL << pool); 3534 else 3535 pfflp &= ~(1ULL << pool); 3536 3537 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3538 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3539 } 3540 3541 /** 3542 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3543 * @hw: pointer to hardware structure 3544 * 3545 * Called at init time to set up flow control. 3546 **/ 3547 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3548 { 3549 s32 status = 0; 3550 u32 an_cntl = 0; 3551 3552 /* Validate the requested mode */ 3553 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3554 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3555 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3556 } 3557 3558 if (hw->fc.requested_mode == ixgbe_fc_default) 3559 hw->fc.requested_mode = ixgbe_fc_full; 3560 3561 /* Set up the 1G and 10G flow control advertisement registers so the 3562 * HW will be able to do FC autoneg once the cable is plugged in. If 3563 * we link at 10G, the 1G advertisement is harmless and vice versa. 3564 */ 3565 status = hw->mac.ops.read_iosf_sb_reg(hw, 3566 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3567 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3568 3569 if (status) { 3570 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3571 return status; 3572 } 3573 3574 /* The possible values of fc.requested_mode are: 3575 * 0: Flow control is completely disabled 3576 * 1: Rx flow control is enabled (we can receive pause frames, 3577 * but not send pause frames). 3578 * 2: Tx flow control is enabled (we can send pause frames but 3579 * we do not support receiving pause frames). 3580 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3581 * other: Invalid. 3582 */ 3583 switch (hw->fc.requested_mode) { 3584 case ixgbe_fc_none: 3585 /* Flow control completely disabled by software override. */ 3586 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3587 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3588 break; 3589 case ixgbe_fc_tx_pause: 3590 /* Tx Flow control is enabled, and Rx Flow control is 3591 * disabled by software override. 3592 */ 3593 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3594 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3595 break; 3596 case ixgbe_fc_rx_pause: 3597 /* Rx Flow control is enabled and Tx Flow control is 3598 * disabled by software override. Since there really 3599 * isn't a way to advertise that we are capable of RX 3600 * Pause ONLY, we will advertise that we support both 3601 * symmetric and asymmetric Rx PAUSE, as such we fall 3602 * through to the fc_full statement. Later, we will 3603 * disable the adapter's ability to send PAUSE frames. 3604 */ 3605 case ixgbe_fc_full: 3606 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3607 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3608 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3609 break; 3610 default: 3611 hw_err(hw, "Flow control param set incorrectly\n"); 3612 return IXGBE_ERR_CONFIG; 3613 } 3614 3615 status = hw->mac.ops.write_iosf_sb_reg(hw, 3616 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3617 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3618 3619 /* Restart auto-negotiation. */ 3620 status = ixgbe_restart_an_internal_phy_x550em(hw); 3621 3622 return status; 3623 } 3624 3625 /** 3626 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3627 * @hw: pointer to hardware structure 3628 * @state: set mux if 1, clear if 0 3629 */ 3630 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3631 { 3632 u32 esdp; 3633 3634 if (!hw->bus.lan_id) 3635 return; 3636 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3637 if (state) 3638 esdp |= IXGBE_ESDP_SDP1; 3639 else 3640 esdp &= ~IXGBE_ESDP_SDP1; 3641 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3642 IXGBE_WRITE_FLUSH(hw); 3643 } 3644 3645 /** 3646 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3647 * @hw: pointer to hardware structure 3648 * @mask: Mask to specify which semaphore to acquire 3649 * 3650 * Acquires the SWFW semaphore and sets the I2C MUX 3651 */ 3652 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3653 { 3654 s32 status; 3655 3656 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3657 if (status) 3658 return status; 3659 3660 if (mask & IXGBE_GSSR_I2C_MASK) 3661 ixgbe_set_mux(hw, 1); 3662 3663 return 0; 3664 } 3665 3666 /** 3667 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3668 * @hw: pointer to hardware structure 3669 * @mask: Mask to specify which semaphore to release 3670 * 3671 * Releases the SWFW semaphore and sets the I2C MUX 3672 */ 3673 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3674 { 3675 if (mask & IXGBE_GSSR_I2C_MASK) 3676 ixgbe_set_mux(hw, 0); 3677 3678 ixgbe_release_swfw_sync_X540(hw, mask); 3679 } 3680 3681 /** 3682 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3683 * @hw: pointer to hardware structure 3684 * @mask: Mask to specify which semaphore to acquire 3685 * 3686 * Acquires the SWFW semaphore and get the shared PHY token as needed 3687 */ 3688 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3689 { 3690 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3691 int retries = FW_PHY_TOKEN_RETRIES; 3692 s32 status; 3693 3694 while (--retries) { 3695 status = 0; 3696 if (hmask) 3697 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3698 if (status) 3699 return status; 3700 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3701 return 0; 3702 3703 status = ixgbe_get_phy_token(hw); 3704 if (!status) 3705 return 0; 3706 if (hmask) 3707 ixgbe_release_swfw_sync_X540(hw, hmask); 3708 if (status != IXGBE_ERR_TOKEN_RETRY) 3709 return status; 3710 msleep(FW_PHY_TOKEN_DELAY); 3711 } 3712 3713 return status; 3714 } 3715 3716 /** 3717 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3718 * @hw: pointer to hardware structure 3719 * @mask: Mask to specify which semaphore to release 3720 * 3721 * Release the SWFW semaphore and puts the shared PHY token as needed 3722 */ 3723 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3724 { 3725 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3726 3727 if (mask & IXGBE_GSSR_TOKEN_SM) 3728 ixgbe_put_phy_token(hw); 3729 3730 if (hmask) 3731 ixgbe_release_swfw_sync_X540(hw, hmask); 3732 } 3733 3734 /** 3735 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3736 * @hw: pointer to hardware structure 3737 * @reg_addr: 32 bit address of PHY register to read 3738 * @phy_data: Pointer to read data from PHY register 3739 * 3740 * Reads a value from a specified PHY register using the SWFW lock and PHY 3741 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3742 * instances. 3743 */ 3744 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3745 u32 device_type, u16 *phy_data) 3746 { 3747 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3748 s32 status; 3749 3750 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3751 return IXGBE_ERR_SWFW_SYNC; 3752 3753 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3754 3755 hw->mac.ops.release_swfw_sync(hw, mask); 3756 3757 return status; 3758 } 3759 3760 /** 3761 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3762 * @hw: pointer to hardware structure 3763 * @reg_addr: 32 bit PHY register to write 3764 * @device_type: 5 bit device type 3765 * @phy_data: Data to write to the PHY register 3766 * 3767 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3768 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3769 */ 3770 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3771 u32 device_type, u16 phy_data) 3772 { 3773 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3774 s32 status; 3775 3776 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3777 return IXGBE_ERR_SWFW_SYNC; 3778 3779 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3780 hw->mac.ops.release_swfw_sync(hw, mask); 3781 3782 return status; 3783 } 3784 3785 #define X550_COMMON_MAC \ 3786 .init_hw = &ixgbe_init_hw_generic, \ 3787 .start_hw = &ixgbe_start_hw_X540, \ 3788 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3789 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3790 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3791 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3792 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3793 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3794 .read_analog_reg8 = NULL, \ 3795 .write_analog_reg8 = NULL, \ 3796 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3797 .check_link = &ixgbe_check_mac_link_generic, \ 3798 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3799 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3800 .set_rar = &ixgbe_set_rar_generic, \ 3801 .clear_rar = &ixgbe_clear_rar_generic, \ 3802 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3803 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3804 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3805 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3806 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3807 .enable_mc = &ixgbe_enable_mc_generic, \ 3808 .disable_mc = &ixgbe_disable_mc_generic, \ 3809 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3810 .set_vfta = &ixgbe_set_vfta_generic, \ 3811 .fc_enable = &ixgbe_fc_enable_generic, \ 3812 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3813 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3814 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3815 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3816 .set_source_address_pruning = \ 3817 &ixgbe_set_source_address_pruning_X550, \ 3818 .set_ethertype_anti_spoofing = \ 3819 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3820 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3821 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3822 .get_thermal_sensor_data = NULL, \ 3823 .init_thermal_sensor_thresh = NULL, \ 3824 .enable_rx = &ixgbe_enable_rx_generic, \ 3825 .disable_rx = &ixgbe_disable_rx_x550, \ 3826 3827 static const struct ixgbe_mac_operations mac_ops_X550 = { 3828 X550_COMMON_MAC 3829 .led_on = ixgbe_led_on_generic, 3830 .led_off = ixgbe_led_off_generic, 3831 .init_led_link_act = ixgbe_init_led_link_act_generic, 3832 .reset_hw = &ixgbe_reset_hw_X540, 3833 .get_media_type = &ixgbe_get_media_type_X540, 3834 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3835 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3836 .setup_link = &ixgbe_setup_mac_link_X540, 3837 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3838 .get_bus_info = &ixgbe_get_bus_info_generic, 3839 .setup_sfp = NULL, 3840 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3841 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3842 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3843 .prot_autoc_read = prot_autoc_read_generic, 3844 .prot_autoc_write = prot_autoc_write_generic, 3845 .setup_fc = ixgbe_setup_fc_generic, 3846 .fc_autoneg = ixgbe_fc_autoneg, 3847 }; 3848 3849 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3850 X550_COMMON_MAC 3851 .led_on = ixgbe_led_on_t_x550em, 3852 .led_off = ixgbe_led_off_t_x550em, 3853 .init_led_link_act = ixgbe_init_led_link_act_generic, 3854 .reset_hw = &ixgbe_reset_hw_X550em, 3855 .get_media_type = &ixgbe_get_media_type_X550em, 3856 .get_san_mac_addr = NULL, 3857 .get_wwn_prefix = NULL, 3858 .setup_link = &ixgbe_setup_mac_link_X540, 3859 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3860 .get_bus_info = &ixgbe_get_bus_info_X550em, 3861 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3862 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3863 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3864 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3865 .setup_fc = NULL, /* defined later */ 3866 .fc_autoneg = ixgbe_fc_autoneg, 3867 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3868 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3869 }; 3870 3871 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = { 3872 X550_COMMON_MAC 3873 .led_on = NULL, 3874 .led_off = NULL, 3875 .init_led_link_act = NULL, 3876 .reset_hw = &ixgbe_reset_hw_X550em, 3877 .get_media_type = &ixgbe_get_media_type_X550em, 3878 .get_san_mac_addr = NULL, 3879 .get_wwn_prefix = NULL, 3880 .setup_link = &ixgbe_setup_mac_link_X540, 3881 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3882 .get_bus_info = &ixgbe_get_bus_info_X550em, 3883 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3884 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3885 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3886 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3887 .setup_fc = NULL, 3888 .fc_autoneg = ixgbe_fc_autoneg, 3889 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3890 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3891 }; 3892 3893 static const struct ixgbe_mac_operations mac_ops_x550em_a = { 3894 X550_COMMON_MAC 3895 .led_on = ixgbe_led_on_t_x550em, 3896 .led_off = ixgbe_led_off_t_x550em, 3897 .init_led_link_act = ixgbe_init_led_link_act_generic, 3898 .reset_hw = ixgbe_reset_hw_X550em, 3899 .get_media_type = ixgbe_get_media_type_X550em, 3900 .get_san_mac_addr = NULL, 3901 .get_wwn_prefix = NULL, 3902 .setup_link = &ixgbe_setup_mac_link_X540, 3903 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3904 .get_bus_info = ixgbe_get_bus_info_X550em, 3905 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3906 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3907 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3908 .setup_fc = ixgbe_setup_fc_x550em, 3909 .fc_autoneg = ixgbe_fc_autoneg, 3910 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3911 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3912 }; 3913 3914 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3915 X550_COMMON_MAC 3916 .led_on = ixgbe_led_on_generic, 3917 .led_off = ixgbe_led_off_generic, 3918 .init_led_link_act = ixgbe_init_led_link_act_generic, 3919 .reset_hw = ixgbe_reset_hw_X550em, 3920 .get_media_type = ixgbe_get_media_type_X550em, 3921 .get_san_mac_addr = NULL, 3922 .get_wwn_prefix = NULL, 3923 .setup_link = NULL, /* defined later */ 3924 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3925 .get_bus_info = ixgbe_get_bus_info_X550em, 3926 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3927 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3928 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3929 .setup_fc = ixgbe_setup_fc_x550em, 3930 .fc_autoneg = ixgbe_fc_autoneg, 3931 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3932 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3933 }; 3934 3935 #define X550_COMMON_EEP \ 3936 .read = &ixgbe_read_ee_hostif_X550, \ 3937 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3938 .write = &ixgbe_write_ee_hostif_X550, \ 3939 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3940 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3941 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3942 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3943 3944 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3945 X550_COMMON_EEP 3946 .init_params = &ixgbe_init_eeprom_params_X550, 3947 }; 3948 3949 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3950 X550_COMMON_EEP 3951 .init_params = &ixgbe_init_eeprom_params_X540, 3952 }; 3953 3954 #define X550_COMMON_PHY \ 3955 .identify_sfp = &ixgbe_identify_module_generic, \ 3956 .reset = NULL, \ 3957 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3958 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3959 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3960 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3961 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3962 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3963 .setup_link = &ixgbe_setup_phy_link_generic, \ 3964 .set_phy_power = NULL, 3965 3966 static const struct ixgbe_phy_operations phy_ops_X550 = { 3967 X550_COMMON_PHY 3968 .check_overtemp = &ixgbe_tn_check_overtemp, 3969 .init = NULL, 3970 .identify = &ixgbe_identify_phy_generic, 3971 .read_reg = &ixgbe_read_phy_reg_generic, 3972 .write_reg = &ixgbe_write_phy_reg_generic, 3973 }; 3974 3975 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3976 X550_COMMON_PHY 3977 .check_overtemp = &ixgbe_tn_check_overtemp, 3978 .init = &ixgbe_init_phy_ops_X550em, 3979 .identify = &ixgbe_identify_phy_x550em, 3980 .read_reg = &ixgbe_read_phy_reg_generic, 3981 .write_reg = &ixgbe_write_phy_reg_generic, 3982 }; 3983 3984 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 3985 X550_COMMON_PHY 3986 .check_overtemp = NULL, 3987 .init = ixgbe_init_phy_ops_X550em, 3988 .identify = ixgbe_identify_phy_x550em, 3989 .read_reg = NULL, 3990 .write_reg = NULL, 3991 .read_reg_mdi = NULL, 3992 .write_reg_mdi = NULL, 3993 }; 3994 3995 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 3996 X550_COMMON_PHY 3997 .check_overtemp = &ixgbe_tn_check_overtemp, 3998 .init = &ixgbe_init_phy_ops_X550em, 3999 .identify = &ixgbe_identify_phy_x550em, 4000 .read_reg = &ixgbe_read_phy_reg_x550a, 4001 .write_reg = &ixgbe_write_phy_reg_x550a, 4002 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 4003 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 4004 }; 4005 4006 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 4007 X550_COMMON_PHY 4008 .check_overtemp = ixgbe_check_overtemp_fw, 4009 .init = ixgbe_init_phy_ops_X550em, 4010 .identify = ixgbe_identify_phy_fw, 4011 .read_reg = NULL, 4012 .write_reg = NULL, 4013 .read_reg_mdi = NULL, 4014 .write_reg_mdi = NULL, 4015 }; 4016 4017 static const struct ixgbe_link_operations link_ops_x550em_x = { 4018 .read_link = &ixgbe_read_i2c_combined_generic, 4019 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 4020 .write_link = &ixgbe_write_i2c_combined_generic, 4021 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 4022 }; 4023 4024 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 4025 IXGBE_MVALS_INIT(X550) 4026 }; 4027 4028 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 4029 IXGBE_MVALS_INIT(X550EM_x) 4030 }; 4031 4032 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 4033 IXGBE_MVALS_INIT(X550EM_a) 4034 }; 4035 4036 const struct ixgbe_info ixgbe_X550_info = { 4037 .mac = ixgbe_mac_X550, 4038 .get_invariants = &ixgbe_get_invariants_X540, 4039 .mac_ops = &mac_ops_X550, 4040 .eeprom_ops = &eeprom_ops_X550, 4041 .phy_ops = &phy_ops_X550, 4042 .mbx_ops = &mbx_ops_generic, 4043 .mvals = ixgbe_mvals_X550, 4044 }; 4045 4046 const struct ixgbe_info ixgbe_X550EM_x_info = { 4047 .mac = ixgbe_mac_X550EM_x, 4048 .get_invariants = &ixgbe_get_invariants_X550_x, 4049 .mac_ops = &mac_ops_X550EM_x, 4050 .eeprom_ops = &eeprom_ops_X550EM_x, 4051 .phy_ops = &phy_ops_X550EM_x, 4052 .mbx_ops = &mbx_ops_generic, 4053 .mvals = ixgbe_mvals_X550EM_x, 4054 .link_ops = &link_ops_x550em_x, 4055 }; 4056 4057 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 4058 .mac = ixgbe_mac_X550EM_x, 4059 .get_invariants = ixgbe_get_invariants_X550_x_fw, 4060 .mac_ops = &mac_ops_X550EM_x_fw, 4061 .eeprom_ops = &eeprom_ops_X550EM_x, 4062 .phy_ops = &phy_ops_x550em_x_fw, 4063 .mbx_ops = &mbx_ops_generic, 4064 .mvals = ixgbe_mvals_X550EM_x, 4065 }; 4066 4067 const struct ixgbe_info ixgbe_x550em_a_info = { 4068 .mac = ixgbe_mac_x550em_a, 4069 .get_invariants = &ixgbe_get_invariants_X550_a, 4070 .mac_ops = &mac_ops_x550em_a, 4071 .eeprom_ops = &eeprom_ops_X550EM_x, 4072 .phy_ops = &phy_ops_x550em_a, 4073 .mbx_ops = &mbx_ops_generic, 4074 .mvals = ixgbe_mvals_x550em_a, 4075 }; 4076 4077 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4078 .mac = ixgbe_mac_x550em_a, 4079 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4080 .mac_ops = &mac_ops_x550em_a_fw, 4081 .eeprom_ops = &eeprom_ops_X550EM_x, 4082 .phy_ops = &phy_ops_x550em_a_fw, 4083 .mbx_ops = &mbx_ops_generic, 4084 .mvals = ixgbe_mvals_x550em_a, 4085 }; 4086