1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe.h" 33 #include "ixgbe_phy.h" 34 35 #define IXGBE_X540_MAX_TX_QUEUES 128 36 #define IXGBE_X540_MAX_RX_QUEUES 128 37 #define IXGBE_X540_RAR_ENTRIES 128 38 #define IXGBE_X540_MC_TBL_SIZE 128 39 #define IXGBE_X540_VFT_TBL_SIZE 128 40 #define IXGBE_X540_RX_PB_SIZE 384 41 42 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 43 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 44 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); 45 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); 46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 48 49 static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 50 { 51 return ixgbe_media_type_copper; 52 } 53 54 static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) 55 { 56 struct ixgbe_mac_info *mac = &hw->mac; 57 58 /* Call PHY identify routine to get the phy type */ 59 ixgbe_identify_phy_generic(hw); 60 61 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 62 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 63 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 64 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 65 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 66 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 67 68 return 0; 69 } 70 71 /** 72 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires 73 * @hw: pointer to hardware structure 74 * @speed: new link speed 75 * @autoneg_wait_to_complete: true when waiting for completion is needed 76 **/ 77 static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 78 ixgbe_link_speed speed, 79 bool autoneg_wait_to_complete) 80 { 81 return hw->phy.ops.setup_link_speed(hw, speed, 82 autoneg_wait_to_complete); 83 } 84 85 /** 86 * ixgbe_reset_hw_X540 - Perform hardware reset 87 * @hw: pointer to hardware structure 88 * 89 * Resets the hardware by resetting the transmit and receive units, masks 90 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 91 * reset. 92 **/ 93 static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 94 { 95 s32 status; 96 u32 ctrl, i; 97 98 /* Call adapter stop to disable tx/rx and clear interrupts */ 99 status = hw->mac.ops.stop_adapter(hw); 100 if (status != 0) 101 goto reset_hw_out; 102 103 /* flush pending Tx transactions */ 104 ixgbe_clear_tx_pending(hw); 105 106 mac_reset_top: 107 ctrl = IXGBE_CTRL_RST; 108 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 109 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 110 IXGBE_WRITE_FLUSH(hw); 111 112 /* Poll for reset bit to self-clear indicating reset is complete */ 113 for (i = 0; i < 10; i++) { 114 udelay(1); 115 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 116 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 117 break; 118 } 119 120 if (ctrl & IXGBE_CTRL_RST_MASK) { 121 status = IXGBE_ERR_RESET_FAILED; 122 hw_dbg(hw, "Reset polling failed to complete.\n"); 123 } 124 msleep(100); 125 126 /* 127 * Double resets are required for recovery from certain error 128 * conditions. Between resets, it is necessary to stall to allow time 129 * for any pending HW events to complete. 130 */ 131 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 132 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 133 goto mac_reset_top; 134 } 135 136 /* Set the Rx packet buffer size. */ 137 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 138 139 /* Store the permanent mac address */ 140 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 141 142 /* 143 * Store MAC address from RAR0, clear receive address registers, and 144 * clear the multicast table. Also reset num_rar_entries to 128, 145 * since we modify this value when programming the SAN MAC address. 146 */ 147 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; 148 hw->mac.ops.init_rx_addrs(hw); 149 150 /* Store the permanent SAN mac address */ 151 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 152 153 /* Add the SAN MAC address to the RAR only if it's a valid address */ 154 if (is_valid_ether_addr(hw->mac.san_addr)) { 155 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 156 hw->mac.san_addr, 0, IXGBE_RAH_AV); 157 158 /* Save the SAN MAC RAR index */ 159 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 160 161 /* Reserve the last RAR for the SAN MAC address */ 162 hw->mac.num_rar_entries--; 163 } 164 165 /* Store the alternative WWNN/WWPN prefix */ 166 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 167 &hw->mac.wwpn_prefix); 168 169 reset_hw_out: 170 return status; 171 } 172 173 /** 174 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 175 * @hw: pointer to hardware structure 176 * 177 * Starts the hardware using the generic start_hw function 178 * and the generation start_hw function. 179 * Then performs revision-specific operations, if any. 180 **/ 181 static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 182 { 183 s32 ret_val = 0; 184 185 ret_val = ixgbe_start_hw_generic(hw); 186 if (ret_val != 0) 187 goto out; 188 189 ret_val = ixgbe_start_hw_gen2(hw); 190 hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE; 191 out: 192 return ret_val; 193 } 194 195 /** 196 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 197 * @hw: pointer to hardware structure 198 * 199 * Determines physical layer capabilities of the current configuration. 200 **/ 201 static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 202 { 203 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 204 u16 ext_ability = 0; 205 206 hw->phy.ops.identify(hw); 207 208 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 209 &ext_ability); 210 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 211 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 212 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 213 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 214 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 215 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 216 217 return physical_layer; 218 } 219 220 /** 221 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 222 * @hw: pointer to hardware structure 223 * 224 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 225 * ixgbe_hw struct in order to set up EEPROM access. 226 **/ 227 static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 228 { 229 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 230 u32 eec; 231 u16 eeprom_size; 232 233 if (eeprom->type == ixgbe_eeprom_uninitialized) { 234 eeprom->semaphore_delay = 10; 235 eeprom->type = ixgbe_flash; 236 237 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 238 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 239 IXGBE_EEC_SIZE_SHIFT); 240 eeprom->word_size = 1 << (eeprom_size + 241 IXGBE_EEPROM_WORD_SIZE_SHIFT); 242 243 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 244 eeprom->type, eeprom->word_size); 245 } 246 247 return 0; 248 } 249 250 /** 251 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 252 * @hw: pointer to hardware structure 253 * @offset: offset of word in the EEPROM to read 254 * @data: word read from the EEPROM 255 * 256 * Reads a 16 bit word from the EEPROM using the EERD register. 257 **/ 258 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 259 { 260 s32 status = 0; 261 262 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 263 0) 264 status = ixgbe_read_eerd_generic(hw, offset, data); 265 else 266 status = IXGBE_ERR_SWFW_SYNC; 267 268 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 269 return status; 270 } 271 272 /** 273 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD 274 * @hw: pointer to hardware structure 275 * @offset: offset of word in the EEPROM to read 276 * @words: number of words 277 * @data: word(s) read from the EEPROM 278 * 279 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 280 **/ 281 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 282 u16 offset, u16 words, u16 *data) 283 { 284 s32 status = 0; 285 286 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 287 0) 288 status = ixgbe_read_eerd_buffer_generic(hw, offset, 289 words, data); 290 else 291 status = IXGBE_ERR_SWFW_SYNC; 292 293 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 294 return status; 295 } 296 297 /** 298 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 299 * @hw: pointer to hardware structure 300 * @offset: offset of word in the EEPROM to write 301 * @data: word write to the EEPROM 302 * 303 * Write a 16 bit word to the EEPROM using the EEWR register. 304 **/ 305 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 306 { 307 s32 status = 0; 308 309 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) 310 status = ixgbe_write_eewr_generic(hw, offset, data); 311 else 312 status = IXGBE_ERR_SWFW_SYNC; 313 314 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 315 return status; 316 } 317 318 /** 319 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 320 * @hw: pointer to hardware structure 321 * @offset: offset of word in the EEPROM to write 322 * @words: number of words 323 * @data: word(s) write to the EEPROM 324 * 325 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 326 **/ 327 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 328 u16 offset, u16 words, u16 *data) 329 { 330 s32 status = 0; 331 332 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 333 0) 334 status = ixgbe_write_eewr_buffer_generic(hw, offset, 335 words, data); 336 else 337 status = IXGBE_ERR_SWFW_SYNC; 338 339 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 340 return status; 341 } 342 343 /** 344 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 345 * 346 * This function does not use synchronization for EERD and EEWR. It can 347 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 348 * 349 * @hw: pointer to hardware structure 350 **/ 351 static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 352 { 353 u16 i; 354 u16 j; 355 u16 checksum = 0; 356 u16 length = 0; 357 u16 pointer = 0; 358 u16 word = 0; 359 360 /* 361 * Do not use hw->eeprom.ops.read because we do not want to take 362 * the synchronization semaphores here. Instead use 363 * ixgbe_read_eerd_generic 364 */ 365 366 /* Include 0x0-0x3F in the checksum */ 367 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 368 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) { 369 hw_dbg(hw, "EEPROM read failed\n"); 370 break; 371 } 372 checksum += word; 373 } 374 375 /* 376 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 377 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 378 */ 379 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 380 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 381 continue; 382 383 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) { 384 hw_dbg(hw, "EEPROM read failed\n"); 385 break; 386 } 387 388 /* Skip pointer section if the pointer is invalid. */ 389 if (pointer == 0xFFFF || pointer == 0 || 390 pointer >= hw->eeprom.word_size) 391 continue; 392 393 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) { 394 hw_dbg(hw, "EEPROM read failed\n"); 395 break; 396 } 397 398 /* Skip pointer section if length is invalid. */ 399 if (length == 0xFFFF || length == 0 || 400 (pointer + length) >= hw->eeprom.word_size) 401 continue; 402 403 for (j = pointer+1; j <= pointer+length; j++) { 404 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) { 405 hw_dbg(hw, "EEPROM read failed\n"); 406 break; 407 } 408 checksum += word; 409 } 410 } 411 412 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 413 414 return checksum; 415 } 416 417 /** 418 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 419 * @hw: pointer to hardware structure 420 * @checksum_val: calculated checksum 421 * 422 * Performs checksum calculation and validates the EEPROM checksum. If the 423 * caller does not need checksum_val, the value can be NULL. 424 **/ 425 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 426 u16 *checksum_val) 427 { 428 s32 status; 429 u16 checksum; 430 u16 read_checksum = 0; 431 432 /* 433 * Read the first word from the EEPROM. If this times out or fails, do 434 * not continue or we could be in for a very long wait while every 435 * EEPROM read fails 436 */ 437 status = hw->eeprom.ops.read(hw, 0, &checksum); 438 439 if (status != 0) { 440 hw_dbg(hw, "EEPROM read failed\n"); 441 goto out; 442 } 443 444 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 445 checksum = hw->eeprom.ops.calc_checksum(hw); 446 447 /* 448 * Do not use hw->eeprom.ops.read because we do not want to take 449 * the synchronization semaphores twice here. 450 */ 451 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 452 &read_checksum); 453 454 /* 455 * Verify read checksum from EEPROM is the same as 456 * calculated checksum 457 */ 458 if (read_checksum != checksum) 459 status = IXGBE_ERR_EEPROM_CHECKSUM; 460 461 /* If the user cares, return the calculated checksum */ 462 if (checksum_val) 463 *checksum_val = checksum; 464 } else { 465 status = IXGBE_ERR_SWFW_SYNC; 466 } 467 468 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 469 out: 470 return status; 471 } 472 473 /** 474 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 475 * @hw: pointer to hardware structure 476 * 477 * After writing EEPROM to shadow RAM using EEWR register, software calculates 478 * checksum and updates the EEPROM and instructs the hardware to update 479 * the flash. 480 **/ 481 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 482 { 483 s32 status; 484 u16 checksum; 485 486 /* 487 * Read the first word from the EEPROM. If this times out or fails, do 488 * not continue or we could be in for a very long wait while every 489 * EEPROM read fails 490 */ 491 status = hw->eeprom.ops.read(hw, 0, &checksum); 492 493 if (status != 0) 494 hw_dbg(hw, "EEPROM read failed\n"); 495 496 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 497 checksum = hw->eeprom.ops.calc_checksum(hw); 498 499 /* 500 * Do not use hw->eeprom.ops.write because we do not want to 501 * take the synchronization semaphores twice here. 502 */ 503 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 504 checksum); 505 506 if (status == 0) 507 status = ixgbe_update_flash_X540(hw); 508 else 509 status = IXGBE_ERR_SWFW_SYNC; 510 } 511 512 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 513 514 return status; 515 } 516 517 /** 518 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 519 * @hw: pointer to hardware structure 520 * 521 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 522 * EEPROM from shadow RAM to the flash device. 523 **/ 524 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 525 { 526 u32 flup; 527 s32 status = IXGBE_ERR_EEPROM; 528 529 status = ixgbe_poll_flash_update_done_X540(hw); 530 if (status == IXGBE_ERR_EEPROM) { 531 hw_dbg(hw, "Flash update time out\n"); 532 goto out; 533 } 534 535 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 536 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 537 538 status = ixgbe_poll_flash_update_done_X540(hw); 539 if (status == 0) 540 hw_dbg(hw, "Flash update complete\n"); 541 else 542 hw_dbg(hw, "Flash update time out\n"); 543 544 if (hw->revision_id == 0) { 545 flup = IXGBE_READ_REG(hw, IXGBE_EEC); 546 547 if (flup & IXGBE_EEC_SEC1VAL) { 548 flup |= IXGBE_EEC_FLUP; 549 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 550 } 551 552 status = ixgbe_poll_flash_update_done_X540(hw); 553 if (status == 0) 554 hw_dbg(hw, "Flash update complete\n"); 555 else 556 hw_dbg(hw, "Flash update time out\n"); 557 } 558 out: 559 return status; 560 } 561 562 /** 563 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 564 * @hw: pointer to hardware structure 565 * 566 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 567 * flash update is done. 568 **/ 569 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 570 { 571 u32 i; 572 u32 reg; 573 s32 status = IXGBE_ERR_EEPROM; 574 575 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 576 reg = IXGBE_READ_REG(hw, IXGBE_EEC); 577 if (reg & IXGBE_EEC_FLUDONE) { 578 status = 0; 579 break; 580 } 581 udelay(5); 582 } 583 return status; 584 } 585 586 /** 587 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 588 * @hw: pointer to hardware structure 589 * @mask: Mask to specify which semaphore to acquire 590 * 591 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 592 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 593 **/ 594 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 595 { 596 u32 swfw_sync; 597 u32 swmask = mask; 598 u32 fwmask = mask << 5; 599 u32 hwmask = 0; 600 u32 timeout = 200; 601 u32 i; 602 603 if (swmask == IXGBE_GSSR_EEP_SM) 604 hwmask = IXGBE_GSSR_FLASH_SM; 605 606 for (i = 0; i < timeout; i++) { 607 /* 608 * SW NVM semaphore bit is used for access to all 609 * SW_FW_SYNC bits (not just NVM) 610 */ 611 if (ixgbe_get_swfw_sync_semaphore(hw)) 612 return IXGBE_ERR_SWFW_SYNC; 613 614 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 615 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 616 swfw_sync |= swmask; 617 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 618 ixgbe_release_swfw_sync_semaphore(hw); 619 break; 620 } else { 621 /* 622 * Firmware currently using resource (fwmask), 623 * hardware currently using resource (hwmask), 624 * or other software thread currently using 625 * resource (swmask) 626 */ 627 ixgbe_release_swfw_sync_semaphore(hw); 628 usleep_range(5000, 10000); 629 } 630 } 631 632 /* 633 * If the resource is not released by the FW/HW the SW can assume that 634 * the FW/HW malfunctions. In that case the SW should sets the 635 * SW bit(s) of the requested resource(s) while ignoring the 636 * corresponding FW/HW bits in the SW_FW_SYNC register. 637 */ 638 if (i >= timeout) { 639 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 640 if (swfw_sync & (fwmask | hwmask)) { 641 if (ixgbe_get_swfw_sync_semaphore(hw)) 642 return IXGBE_ERR_SWFW_SYNC; 643 644 swfw_sync |= swmask; 645 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 646 ixgbe_release_swfw_sync_semaphore(hw); 647 } 648 } 649 650 usleep_range(5000, 10000); 651 return 0; 652 } 653 654 /** 655 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 656 * @hw: pointer to hardware structure 657 * @mask: Mask to specify which semaphore to release 658 * 659 * Releases the SWFW semaphore through the SW_FW_SYNC register 660 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 661 **/ 662 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 663 { 664 u32 swfw_sync; 665 u32 swmask = mask; 666 667 ixgbe_get_swfw_sync_semaphore(hw); 668 669 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 670 swfw_sync &= ~swmask; 671 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 672 673 ixgbe_release_swfw_sync_semaphore(hw); 674 usleep_range(5000, 10000); 675 } 676 677 /** 678 * ixgbe_get_nvm_semaphore - Get hardware semaphore 679 * @hw: pointer to hardware structure 680 * 681 * Sets the hardware semaphores so SW/FW can gain control of shared resources 682 **/ 683 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 684 { 685 s32 status = IXGBE_ERR_EEPROM; 686 u32 timeout = 2000; 687 u32 i; 688 u32 swsm; 689 690 /* Get SMBI software semaphore between device drivers first */ 691 for (i = 0; i < timeout; i++) { 692 /* 693 * If the SMBI bit is 0 when we read it, then the bit will be 694 * set and we have the semaphore 695 */ 696 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 697 if (!(swsm & IXGBE_SWSM_SMBI)) { 698 status = 0; 699 break; 700 } 701 udelay(50); 702 } 703 704 /* Now get the semaphore between SW/FW through the REGSMP bit */ 705 if (status) { 706 for (i = 0; i < timeout; i++) { 707 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 708 if (!(swsm & IXGBE_SWFW_REGSMP)) 709 break; 710 711 udelay(50); 712 } 713 } else { 714 hw_dbg(hw, "Software semaphore SMBI between device drivers " 715 "not granted.\n"); 716 } 717 718 return status; 719 } 720 721 /** 722 * ixgbe_release_nvm_semaphore - Release hardware semaphore 723 * @hw: pointer to hardware structure 724 * 725 * This function clears hardware semaphore bits. 726 **/ 727 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 728 { 729 u32 swsm; 730 731 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 732 733 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 734 swsm &= ~IXGBE_SWSM_SMBI; 735 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 736 737 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 738 swsm &= ~IXGBE_SWFW_REGSMP; 739 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 740 741 IXGBE_WRITE_FLUSH(hw); 742 } 743 744 /** 745 * ixgbe_blink_led_start_X540 - Blink LED based on index. 746 * @hw: pointer to hardware structure 747 * @index: led number to blink 748 * 749 * Devices that implement the version 2 interface: 750 * X540 751 **/ 752 static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 753 { 754 u32 macc_reg; 755 u32 ledctl_reg; 756 ixgbe_link_speed speed; 757 bool link_up; 758 759 /* 760 * Link should be up in order for the blink bit in the LED control 761 * register to work. Force link and speed in the MAC if link is down. 762 * This will be reversed when we stop the blinking. 763 */ 764 hw->mac.ops.check_link(hw, &speed, &link_up, false); 765 if (!link_up) { 766 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 767 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 768 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 769 } 770 /* Set the LED to LINK_UP + BLINK. */ 771 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 772 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 773 ledctl_reg |= IXGBE_LED_BLINK(index); 774 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 775 IXGBE_WRITE_FLUSH(hw); 776 777 return 0; 778 } 779 780 /** 781 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 782 * @hw: pointer to hardware structure 783 * @index: led number to stop blinking 784 * 785 * Devices that implement the version 2 interface: 786 * X540 787 **/ 788 static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 789 { 790 u32 macc_reg; 791 u32 ledctl_reg; 792 793 /* Restore the LED to its default value. */ 794 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 795 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 796 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 797 ledctl_reg &= ~IXGBE_LED_BLINK(index); 798 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 799 800 /* Unforce link and speed in the MAC. */ 801 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 802 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 803 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 804 IXGBE_WRITE_FLUSH(hw); 805 806 return 0; 807 } 808 static struct ixgbe_mac_operations mac_ops_X540 = { 809 .init_hw = &ixgbe_init_hw_generic, 810 .reset_hw = &ixgbe_reset_hw_X540, 811 .start_hw = &ixgbe_start_hw_X540, 812 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 813 .get_media_type = &ixgbe_get_media_type_X540, 814 .get_supported_physical_layer = 815 &ixgbe_get_supported_physical_layer_X540, 816 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 817 .get_mac_addr = &ixgbe_get_mac_addr_generic, 818 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 819 .get_device_caps = &ixgbe_get_device_caps_generic, 820 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 821 .stop_adapter = &ixgbe_stop_adapter_generic, 822 .get_bus_info = &ixgbe_get_bus_info_generic, 823 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 824 .read_analog_reg8 = NULL, 825 .write_analog_reg8 = NULL, 826 .setup_link = &ixgbe_setup_mac_link_X540, 827 .set_rxpba = &ixgbe_set_rxpba_generic, 828 .check_link = &ixgbe_check_mac_link_generic, 829 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 830 .led_on = &ixgbe_led_on_generic, 831 .led_off = &ixgbe_led_off_generic, 832 .blink_led_start = &ixgbe_blink_led_start_X540, 833 .blink_led_stop = &ixgbe_blink_led_stop_X540, 834 .set_rar = &ixgbe_set_rar_generic, 835 .clear_rar = &ixgbe_clear_rar_generic, 836 .set_vmdq = &ixgbe_set_vmdq_generic, 837 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 838 .clear_vmdq = &ixgbe_clear_vmdq_generic, 839 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 840 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 841 .enable_mc = &ixgbe_enable_mc_generic, 842 .disable_mc = &ixgbe_disable_mc_generic, 843 .clear_vfta = &ixgbe_clear_vfta_generic, 844 .set_vfta = &ixgbe_set_vfta_generic, 845 .fc_enable = &ixgbe_fc_enable_generic, 846 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 847 .init_uta_tables = &ixgbe_init_uta_tables_generic, 848 .setup_sfp = NULL, 849 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 850 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 851 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 852 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 853 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 854 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 855 .get_thermal_sensor_data = NULL, 856 .init_thermal_sensor_thresh = NULL, 857 .mng_fw_enabled = NULL, 858 }; 859 860 static struct ixgbe_eeprom_operations eeprom_ops_X540 = { 861 .init_params = &ixgbe_init_eeprom_params_X540, 862 .read = &ixgbe_read_eerd_X540, 863 .read_buffer = &ixgbe_read_eerd_buffer_X540, 864 .write = &ixgbe_write_eewr_X540, 865 .write_buffer = &ixgbe_write_eewr_buffer_X540, 866 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, 867 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, 868 .update_checksum = &ixgbe_update_eeprom_checksum_X540, 869 }; 870 871 static struct ixgbe_phy_operations phy_ops_X540 = { 872 .identify = &ixgbe_identify_phy_generic, 873 .identify_sfp = &ixgbe_identify_sfp_module_generic, 874 .init = NULL, 875 .reset = NULL, 876 .read_reg = &ixgbe_read_phy_reg_generic, 877 .write_reg = &ixgbe_write_phy_reg_generic, 878 .setup_link = &ixgbe_setup_phy_link_generic, 879 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 880 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 881 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 882 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 883 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 884 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 885 .check_overtemp = &ixgbe_tn_check_overtemp, 886 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, 887 }; 888 889 struct ixgbe_info ixgbe_X540_info = { 890 .mac = ixgbe_mac_X540, 891 .get_invariants = &ixgbe_get_invariants_X540, 892 .mac_ops = &mac_ops_X540, 893 .eeprom_ops = &eeprom_ops_X540, 894 .phy_ops = &phy_ops_X540, 895 .mbx_ops = &mbx_ops_generic, 896 }; 897