1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 #include "ixgbe_x540.h" 36 37 #define IXGBE_X540_MAX_TX_QUEUES 128 38 #define IXGBE_X540_MAX_RX_QUEUES 128 39 #define IXGBE_X540_RAR_ENTRIES 128 40 #define IXGBE_X540_MC_TBL_SIZE 128 41 #define IXGBE_X540_VFT_TBL_SIZE 128 42 #define IXGBE_X540_RX_PB_SIZE 384 43 44 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 45 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 48 49 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 50 { 51 return ixgbe_media_type_copper; 52 } 53 54 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) 55 { 56 struct ixgbe_mac_info *mac = &hw->mac; 57 58 /* Call PHY identify routine to get the phy type */ 59 ixgbe_identify_phy_generic(hw); 60 61 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 62 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 63 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 64 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 65 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 66 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 67 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 68 69 return 0; 70 } 71 72 /** 73 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires 74 * @hw: pointer to hardware structure 75 * @speed: new link speed 76 * @autoneg_wait_to_complete: true when waiting for completion is needed 77 **/ 78 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, 79 bool autoneg_wait_to_complete) 80 { 81 return hw->phy.ops.setup_link_speed(hw, speed, 82 autoneg_wait_to_complete); 83 } 84 85 /** 86 * ixgbe_reset_hw_X540 - Perform hardware reset 87 * @hw: pointer to hardware structure 88 * 89 * Resets the hardware by resetting the transmit and receive units, masks 90 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 91 * reset. 92 **/ 93 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 94 { 95 s32 status; 96 u32 ctrl, i; 97 98 /* Call adapter stop to disable tx/rx and clear interrupts */ 99 status = hw->mac.ops.stop_adapter(hw); 100 if (status) 101 return status; 102 103 /* flush pending Tx transactions */ 104 ixgbe_clear_tx_pending(hw); 105 106 mac_reset_top: 107 ctrl = IXGBE_CTRL_RST; 108 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 109 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 110 IXGBE_WRITE_FLUSH(hw); 111 112 /* Poll for reset bit to self-clear indicating reset is complete */ 113 for (i = 0; i < 10; i++) { 114 udelay(1); 115 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 116 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 117 break; 118 } 119 120 if (ctrl & IXGBE_CTRL_RST_MASK) { 121 status = IXGBE_ERR_RESET_FAILED; 122 hw_dbg(hw, "Reset polling failed to complete.\n"); 123 } 124 msleep(100); 125 126 /* 127 * Double resets are required for recovery from certain error 128 * conditions. Between resets, it is necessary to stall to allow time 129 * for any pending HW events to complete. 130 */ 131 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 132 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 133 goto mac_reset_top; 134 } 135 136 /* Set the Rx packet buffer size. */ 137 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 138 139 /* Store the permanent mac address */ 140 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 141 142 /* 143 * Store MAC address from RAR0, clear receive address registers, and 144 * clear the multicast table. Also reset num_rar_entries to 128, 145 * since we modify this value when programming the SAN MAC address. 146 */ 147 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; 148 hw->mac.ops.init_rx_addrs(hw); 149 150 /* Store the permanent SAN mac address */ 151 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 152 153 /* Add the SAN MAC address to the RAR only if it's a valid address */ 154 if (is_valid_ether_addr(hw->mac.san_addr)) { 155 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 156 hw->mac.san_addr, 0, IXGBE_RAH_AV); 157 158 /* Save the SAN MAC RAR index */ 159 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 160 161 /* Reserve the last RAR for the SAN MAC address */ 162 hw->mac.num_rar_entries--; 163 } 164 165 /* Store the alternative WWNN/WWPN prefix */ 166 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 167 &hw->mac.wwpn_prefix); 168 169 return status; 170 } 171 172 /** 173 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 174 * @hw: pointer to hardware structure 175 * 176 * Starts the hardware using the generic start_hw function 177 * and the generation start_hw function. 178 * Then performs revision-specific operations, if any. 179 **/ 180 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 181 { 182 s32 ret_val; 183 184 ret_val = ixgbe_start_hw_generic(hw); 185 if (ret_val) 186 return ret_val; 187 188 return ixgbe_start_hw_gen2(hw); 189 } 190 191 /** 192 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 193 * @hw: pointer to hardware structure 194 * 195 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 196 * ixgbe_hw struct in order to set up EEPROM access. 197 **/ 198 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 199 { 200 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 201 u32 eec; 202 u16 eeprom_size; 203 204 if (eeprom->type == ixgbe_eeprom_uninitialized) { 205 eeprom->semaphore_delay = 10; 206 eeprom->type = ixgbe_flash; 207 208 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 209 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 210 IXGBE_EEC_SIZE_SHIFT); 211 eeprom->word_size = 1 << (eeprom_size + 212 IXGBE_EEPROM_WORD_SIZE_SHIFT); 213 214 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 215 eeprom->type, eeprom->word_size); 216 } 217 218 return 0; 219 } 220 221 /** 222 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 223 * @hw: pointer to hardware structure 224 * @offset: offset of word in the EEPROM to read 225 * @data: word read from the EEPROM 226 * 227 * Reads a 16 bit word from the EEPROM using the EERD register. 228 **/ 229 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 230 { 231 s32 status; 232 233 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 234 return IXGBE_ERR_SWFW_SYNC; 235 236 status = ixgbe_read_eerd_generic(hw, offset, data); 237 238 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 239 return status; 240 } 241 242 /** 243 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD 244 * @hw: pointer to hardware structure 245 * @offset: offset of word in the EEPROM to read 246 * @words: number of words 247 * @data: word(s) read from the EEPROM 248 * 249 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 250 **/ 251 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 252 u16 offset, u16 words, u16 *data) 253 { 254 s32 status; 255 256 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 257 return IXGBE_ERR_SWFW_SYNC; 258 259 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data); 260 261 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 262 return status; 263 } 264 265 /** 266 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 267 * @hw: pointer to hardware structure 268 * @offset: offset of word in the EEPROM to write 269 * @data: word write to the EEPROM 270 * 271 * Write a 16 bit word to the EEPROM using the EEWR register. 272 **/ 273 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 274 { 275 s32 status; 276 277 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 278 return IXGBE_ERR_SWFW_SYNC; 279 280 status = ixgbe_write_eewr_generic(hw, offset, data); 281 282 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 283 return status; 284 } 285 286 /** 287 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 288 * @hw: pointer to hardware structure 289 * @offset: offset of word in the EEPROM to write 290 * @words: number of words 291 * @data: word(s) write to the EEPROM 292 * 293 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 294 **/ 295 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 296 u16 offset, u16 words, u16 *data) 297 { 298 s32 status; 299 300 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 301 return IXGBE_ERR_SWFW_SYNC; 302 303 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data); 304 305 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 306 return status; 307 } 308 309 /** 310 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 311 * 312 * This function does not use synchronization for EERD and EEWR. It can 313 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 314 * 315 * @hw: pointer to hardware structure 316 **/ 317 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 318 { 319 u16 i; 320 u16 j; 321 u16 checksum = 0; 322 u16 length = 0; 323 u16 pointer = 0; 324 u16 word = 0; 325 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM; 326 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 327 328 /* 329 * Do not use hw->eeprom.ops.read because we do not want to take 330 * the synchronization semaphores here. Instead use 331 * ixgbe_read_eerd_generic 332 */ 333 334 /* Include 0x0-0x3F in the checksum */ 335 for (i = 0; i < checksum_last_word; i++) { 336 if (ixgbe_read_eerd_generic(hw, i, &word)) { 337 hw_dbg(hw, "EEPROM read failed\n"); 338 return IXGBE_ERR_EEPROM; 339 } 340 checksum += word; 341 } 342 343 /* 344 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 345 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 346 */ 347 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 348 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 349 continue; 350 351 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 352 hw_dbg(hw, "EEPROM read failed\n"); 353 break; 354 } 355 356 /* Skip pointer section if the pointer is invalid. */ 357 if (pointer == 0xFFFF || pointer == 0 || 358 pointer >= hw->eeprom.word_size) 359 continue; 360 361 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 362 hw_dbg(hw, "EEPROM read failed\n"); 363 return IXGBE_ERR_EEPROM; 364 break; 365 } 366 367 /* Skip pointer section if length is invalid. */ 368 if (length == 0xFFFF || length == 0 || 369 (pointer + length) >= hw->eeprom.word_size) 370 continue; 371 372 for (j = pointer + 1; j <= pointer + length; j++) { 373 if (ixgbe_read_eerd_generic(hw, j, &word)) { 374 hw_dbg(hw, "EEPROM read failed\n"); 375 return IXGBE_ERR_EEPROM; 376 } 377 checksum += word; 378 } 379 } 380 381 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 382 383 return (s32)checksum; 384 } 385 386 /** 387 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 388 * @hw: pointer to hardware structure 389 * @checksum_val: calculated checksum 390 * 391 * Performs checksum calculation and validates the EEPROM checksum. If the 392 * caller does not need checksum_val, the value can be NULL. 393 **/ 394 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 395 u16 *checksum_val) 396 { 397 s32 status; 398 u16 checksum; 399 u16 read_checksum = 0; 400 401 /* Read the first word from the EEPROM. If this times out or fails, do 402 * not continue or we could be in for a very long wait while every 403 * EEPROM read fails 404 */ 405 status = hw->eeprom.ops.read(hw, 0, &checksum); 406 if (status) { 407 hw_dbg(hw, "EEPROM read failed\n"); 408 return status; 409 } 410 411 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 412 return IXGBE_ERR_SWFW_SYNC; 413 414 status = hw->eeprom.ops.calc_checksum(hw); 415 if (status < 0) 416 goto out; 417 418 checksum = (u16)(status & 0xffff); 419 420 /* Do not use hw->eeprom.ops.read because we do not want to take 421 * the synchronization semaphores twice here. 422 */ 423 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 424 &read_checksum); 425 if (status) 426 goto out; 427 428 /* Verify read checksum from EEPROM is the same as 429 * calculated checksum 430 */ 431 if (read_checksum != checksum) { 432 hw_dbg(hw, "Invalid EEPROM checksum"); 433 status = IXGBE_ERR_EEPROM_CHECKSUM; 434 } 435 436 /* If the user cares, return the calculated checksum */ 437 if (checksum_val) 438 *checksum_val = checksum; 439 440 out: 441 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 442 443 return status; 444 } 445 446 /** 447 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 448 * @hw: pointer to hardware structure 449 * 450 * After writing EEPROM to shadow RAM using EEWR register, software calculates 451 * checksum and updates the EEPROM and instructs the hardware to update 452 * the flash. 453 **/ 454 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 455 { 456 s32 status; 457 u16 checksum; 458 459 /* Read the first word from the EEPROM. If this times out or fails, do 460 * not continue or we could be in for a very long wait while every 461 * EEPROM read fails 462 */ 463 status = hw->eeprom.ops.read(hw, 0, &checksum); 464 if (status) { 465 hw_dbg(hw, "EEPROM read failed\n"); 466 return status; 467 } 468 469 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 470 return IXGBE_ERR_SWFW_SYNC; 471 472 status = hw->eeprom.ops.calc_checksum(hw); 473 if (status < 0) 474 goto out; 475 476 checksum = (u16)(status & 0xffff); 477 478 /* Do not use hw->eeprom.ops.write because we do not want to 479 * take the synchronization semaphores twice here. 480 */ 481 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 482 if (status) 483 goto out; 484 485 status = ixgbe_update_flash_X540(hw); 486 487 out: 488 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 489 return status; 490 } 491 492 /** 493 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 494 * @hw: pointer to hardware structure 495 * 496 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 497 * EEPROM from shadow RAM to the flash device. 498 **/ 499 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 500 { 501 u32 flup; 502 s32 status; 503 504 status = ixgbe_poll_flash_update_done_X540(hw); 505 if (status == IXGBE_ERR_EEPROM) { 506 hw_dbg(hw, "Flash update time out\n"); 507 return status; 508 } 509 510 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 511 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 512 513 status = ixgbe_poll_flash_update_done_X540(hw); 514 if (status == 0) 515 hw_dbg(hw, "Flash update complete\n"); 516 else 517 hw_dbg(hw, "Flash update time out\n"); 518 519 if (hw->revision_id == 0) { 520 flup = IXGBE_READ_REG(hw, IXGBE_EEC); 521 522 if (flup & IXGBE_EEC_SEC1VAL) { 523 flup |= IXGBE_EEC_FLUP; 524 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 525 } 526 527 status = ixgbe_poll_flash_update_done_X540(hw); 528 if (status == 0) 529 hw_dbg(hw, "Flash update complete\n"); 530 else 531 hw_dbg(hw, "Flash update time out\n"); 532 } 533 534 return status; 535 } 536 537 /** 538 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 539 * @hw: pointer to hardware structure 540 * 541 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 542 * flash update is done. 543 **/ 544 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 545 { 546 u32 i; 547 u32 reg; 548 549 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 550 reg = IXGBE_READ_REG(hw, IXGBE_EEC); 551 if (reg & IXGBE_EEC_FLUDONE) 552 return 0; 553 udelay(5); 554 } 555 return IXGBE_ERR_EEPROM; 556 } 557 558 /** 559 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 560 * @hw: pointer to hardware structure 561 * @mask: Mask to specify which semaphore to acquire 562 * 563 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 564 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 565 **/ 566 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 567 { 568 u32 swfw_sync; 569 u32 swmask = mask; 570 u32 fwmask = mask << 5; 571 u32 hwmask = 0; 572 u32 timeout = 200; 573 u32 i; 574 575 if (swmask == IXGBE_GSSR_EEP_SM) 576 hwmask = IXGBE_GSSR_FLASH_SM; 577 578 for (i = 0; i < timeout; i++) { 579 /* 580 * SW NVM semaphore bit is used for access to all 581 * SW_FW_SYNC bits (not just NVM) 582 */ 583 if (ixgbe_get_swfw_sync_semaphore(hw)) 584 return IXGBE_ERR_SWFW_SYNC; 585 586 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 587 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 588 swfw_sync |= swmask; 589 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 590 ixgbe_release_swfw_sync_semaphore(hw); 591 break; 592 } else { 593 /* 594 * Firmware currently using resource (fwmask), 595 * hardware currently using resource (hwmask), 596 * or other software thread currently using 597 * resource (swmask) 598 */ 599 ixgbe_release_swfw_sync_semaphore(hw); 600 usleep_range(5000, 10000); 601 } 602 } 603 604 /* 605 * If the resource is not released by the FW/HW the SW can assume that 606 * the FW/HW malfunctions. In that case the SW should sets the 607 * SW bit(s) of the requested resource(s) while ignoring the 608 * corresponding FW/HW bits in the SW_FW_SYNC register. 609 */ 610 if (i >= timeout) { 611 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 612 if (swfw_sync & (fwmask | hwmask)) { 613 if (ixgbe_get_swfw_sync_semaphore(hw)) 614 return IXGBE_ERR_SWFW_SYNC; 615 616 swfw_sync |= swmask; 617 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 618 ixgbe_release_swfw_sync_semaphore(hw); 619 } 620 } 621 622 usleep_range(5000, 10000); 623 return 0; 624 } 625 626 /** 627 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 628 * @hw: pointer to hardware structure 629 * @mask: Mask to specify which semaphore to release 630 * 631 * Releases the SWFW semaphore through the SW_FW_SYNC register 632 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 633 **/ 634 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 635 { 636 u32 swfw_sync; 637 u32 swmask = mask; 638 639 ixgbe_get_swfw_sync_semaphore(hw); 640 641 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 642 swfw_sync &= ~swmask; 643 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 644 645 ixgbe_release_swfw_sync_semaphore(hw); 646 usleep_range(5000, 10000); 647 } 648 649 /** 650 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 651 * @hw: pointer to hardware structure 652 * 653 * Sets the hardware semaphores so SW/FW can gain control of shared resources 654 */ 655 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 656 { 657 u32 timeout = 2000; 658 u32 i; 659 u32 swsm; 660 661 /* Get SMBI software semaphore between device drivers first */ 662 for (i = 0; i < timeout; i++) { 663 /* If the SMBI bit is 0 when we read it, then the bit will be 664 * set and we have the semaphore 665 */ 666 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 667 if (!(swsm & IXGBE_SWSM_SMBI)) 668 break; 669 usleep_range(50, 100); 670 } 671 672 if (i == timeout) { 673 hw_dbg(hw, 674 "Software semaphore SMBI between device drivers not granted.\n"); 675 return IXGBE_ERR_EEPROM; 676 } 677 678 /* Now get the semaphore between SW/FW through the REGSMP bit */ 679 for (i = 0; i < timeout; i++) { 680 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 681 if (!(swsm & IXGBE_SWFW_REGSMP)) 682 return 0; 683 684 usleep_range(50, 100); 685 } 686 687 return IXGBE_ERR_EEPROM; 688 } 689 690 /** 691 * ixgbe_release_nvm_semaphore - Release hardware semaphore 692 * @hw: pointer to hardware structure 693 * 694 * This function clears hardware semaphore bits. 695 **/ 696 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 697 { 698 u32 swsm; 699 700 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 701 702 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 703 swsm &= ~IXGBE_SWSM_SMBI; 704 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 705 706 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 707 swsm &= ~IXGBE_SWFW_REGSMP; 708 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 709 710 IXGBE_WRITE_FLUSH(hw); 711 } 712 713 /** 714 * ixgbe_blink_led_start_X540 - Blink LED based on index. 715 * @hw: pointer to hardware structure 716 * @index: led number to blink 717 * 718 * Devices that implement the version 2 interface: 719 * X540 720 **/ 721 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 722 { 723 u32 macc_reg; 724 u32 ledctl_reg; 725 ixgbe_link_speed speed; 726 bool link_up; 727 728 /* 729 * Link should be up in order for the blink bit in the LED control 730 * register to work. Force link and speed in the MAC if link is down. 731 * This will be reversed when we stop the blinking. 732 */ 733 hw->mac.ops.check_link(hw, &speed, &link_up, false); 734 if (!link_up) { 735 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 736 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 737 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 738 } 739 /* Set the LED to LINK_UP + BLINK. */ 740 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 741 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 742 ledctl_reg |= IXGBE_LED_BLINK(index); 743 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 744 IXGBE_WRITE_FLUSH(hw); 745 746 return 0; 747 } 748 749 /** 750 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 751 * @hw: pointer to hardware structure 752 * @index: led number to stop blinking 753 * 754 * Devices that implement the version 2 interface: 755 * X540 756 **/ 757 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 758 { 759 u32 macc_reg; 760 u32 ledctl_reg; 761 762 /* Restore the LED to its default value. */ 763 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 764 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 765 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 766 ledctl_reg &= ~IXGBE_LED_BLINK(index); 767 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 768 769 /* Unforce link and speed in the MAC. */ 770 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 771 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 772 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 773 IXGBE_WRITE_FLUSH(hw); 774 775 return 0; 776 } 777 static struct ixgbe_mac_operations mac_ops_X540 = { 778 .init_hw = &ixgbe_init_hw_generic, 779 .reset_hw = &ixgbe_reset_hw_X540, 780 .start_hw = &ixgbe_start_hw_X540, 781 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 782 .get_media_type = &ixgbe_get_media_type_X540, 783 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 784 .get_mac_addr = &ixgbe_get_mac_addr_generic, 785 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 786 .get_device_caps = &ixgbe_get_device_caps_generic, 787 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 788 .stop_adapter = &ixgbe_stop_adapter_generic, 789 .get_bus_info = &ixgbe_get_bus_info_generic, 790 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 791 .read_analog_reg8 = NULL, 792 .write_analog_reg8 = NULL, 793 .setup_link = &ixgbe_setup_mac_link_X540, 794 .set_rxpba = &ixgbe_set_rxpba_generic, 795 .check_link = &ixgbe_check_mac_link_generic, 796 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 797 .led_on = &ixgbe_led_on_generic, 798 .led_off = &ixgbe_led_off_generic, 799 .blink_led_start = &ixgbe_blink_led_start_X540, 800 .blink_led_stop = &ixgbe_blink_led_stop_X540, 801 .set_rar = &ixgbe_set_rar_generic, 802 .clear_rar = &ixgbe_clear_rar_generic, 803 .set_vmdq = &ixgbe_set_vmdq_generic, 804 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 805 .clear_vmdq = &ixgbe_clear_vmdq_generic, 806 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 807 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 808 .enable_mc = &ixgbe_enable_mc_generic, 809 .disable_mc = &ixgbe_disable_mc_generic, 810 .clear_vfta = &ixgbe_clear_vfta_generic, 811 .set_vfta = &ixgbe_set_vfta_generic, 812 .fc_enable = &ixgbe_fc_enable_generic, 813 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 814 .init_uta_tables = &ixgbe_init_uta_tables_generic, 815 .setup_sfp = NULL, 816 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 817 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 818 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 819 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 820 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 821 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 822 .get_thermal_sensor_data = NULL, 823 .init_thermal_sensor_thresh = NULL, 824 .prot_autoc_read = &prot_autoc_read_generic, 825 .prot_autoc_write = &prot_autoc_write_generic, 826 }; 827 828 static struct ixgbe_eeprom_operations eeprom_ops_X540 = { 829 .init_params = &ixgbe_init_eeprom_params_X540, 830 .read = &ixgbe_read_eerd_X540, 831 .read_buffer = &ixgbe_read_eerd_buffer_X540, 832 .write = &ixgbe_write_eewr_X540, 833 .write_buffer = &ixgbe_write_eewr_buffer_X540, 834 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, 835 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, 836 .update_checksum = &ixgbe_update_eeprom_checksum_X540, 837 }; 838 839 static struct ixgbe_phy_operations phy_ops_X540 = { 840 .identify = &ixgbe_identify_phy_generic, 841 .identify_sfp = &ixgbe_identify_sfp_module_generic, 842 .init = NULL, 843 .reset = NULL, 844 .read_reg = &ixgbe_read_phy_reg_generic, 845 .write_reg = &ixgbe_write_phy_reg_generic, 846 .setup_link = &ixgbe_setup_phy_link_generic, 847 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 848 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 849 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 850 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 851 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 852 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 853 .check_overtemp = &ixgbe_tn_check_overtemp, 854 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, 855 }; 856 857 struct ixgbe_info ixgbe_X540_info = { 858 .mac = ixgbe_mac_X540, 859 .get_invariants = &ixgbe_get_invariants_X540, 860 .mac_ops = &mac_ops_X540, 861 .eeprom_ops = &eeprom_ops_X540, 862 .phy_ops = &phy_ops_X540, 863 .mbx_ops = &mbx_ops_generic, 864 }; 865