1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 36 #define IXGBE_X540_MAX_TX_QUEUES 128 37 #define IXGBE_X540_MAX_RX_QUEUES 128 38 #define IXGBE_X540_RAR_ENTRIES 128 39 #define IXGBE_X540_MC_TBL_SIZE 128 40 #define IXGBE_X540_VFT_TBL_SIZE 128 41 #define IXGBE_X540_RX_PB_SIZE 384 42 43 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 44 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 45 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); 46 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); 47 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 48 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 49 50 static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 51 { 52 return ixgbe_media_type_copper; 53 } 54 55 static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) 56 { 57 struct ixgbe_mac_info *mac = &hw->mac; 58 59 /* Call PHY identify routine to get the phy type */ 60 ixgbe_identify_phy_generic(hw); 61 62 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 63 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 64 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 65 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 66 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 67 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 68 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 69 70 return 0; 71 } 72 73 /** 74 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires 75 * @hw: pointer to hardware structure 76 * @speed: new link speed 77 * @autoneg_wait_to_complete: true when waiting for completion is needed 78 **/ 79 static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 80 ixgbe_link_speed speed, 81 bool autoneg_wait_to_complete) 82 { 83 return hw->phy.ops.setup_link_speed(hw, speed, 84 autoneg_wait_to_complete); 85 } 86 87 /** 88 * ixgbe_reset_hw_X540 - Perform hardware reset 89 * @hw: pointer to hardware structure 90 * 91 * Resets the hardware by resetting the transmit and receive units, masks 92 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 93 * reset. 94 **/ 95 static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 96 { 97 s32 status; 98 u32 ctrl, i; 99 100 /* Call adapter stop to disable tx/rx and clear interrupts */ 101 status = hw->mac.ops.stop_adapter(hw); 102 if (status != 0) 103 goto reset_hw_out; 104 105 /* flush pending Tx transactions */ 106 ixgbe_clear_tx_pending(hw); 107 108 mac_reset_top: 109 ctrl = IXGBE_CTRL_RST; 110 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 111 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 112 IXGBE_WRITE_FLUSH(hw); 113 114 /* Poll for reset bit to self-clear indicating reset is complete */ 115 for (i = 0; i < 10; i++) { 116 udelay(1); 117 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 118 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 119 break; 120 } 121 122 if (ctrl & IXGBE_CTRL_RST_MASK) { 123 status = IXGBE_ERR_RESET_FAILED; 124 hw_dbg(hw, "Reset polling failed to complete.\n"); 125 } 126 msleep(100); 127 128 /* 129 * Double resets are required for recovery from certain error 130 * conditions. Between resets, it is necessary to stall to allow time 131 * for any pending HW events to complete. 132 */ 133 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 134 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 135 goto mac_reset_top; 136 } 137 138 /* Set the Rx packet buffer size. */ 139 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 140 141 /* Store the permanent mac address */ 142 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 143 144 /* 145 * Store MAC address from RAR0, clear receive address registers, and 146 * clear the multicast table. Also reset num_rar_entries to 128, 147 * since we modify this value when programming the SAN MAC address. 148 */ 149 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; 150 hw->mac.ops.init_rx_addrs(hw); 151 152 /* Store the permanent SAN mac address */ 153 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 154 155 /* Add the SAN MAC address to the RAR only if it's a valid address */ 156 if (is_valid_ether_addr(hw->mac.san_addr)) { 157 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 158 hw->mac.san_addr, 0, IXGBE_RAH_AV); 159 160 /* Save the SAN MAC RAR index */ 161 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 162 163 /* Reserve the last RAR for the SAN MAC address */ 164 hw->mac.num_rar_entries--; 165 } 166 167 /* Store the alternative WWNN/WWPN prefix */ 168 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 169 &hw->mac.wwpn_prefix); 170 171 reset_hw_out: 172 return status; 173 } 174 175 /** 176 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 177 * @hw: pointer to hardware structure 178 * 179 * Starts the hardware using the generic start_hw function 180 * and the generation start_hw function. 181 * Then performs revision-specific operations, if any. 182 **/ 183 static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 184 { 185 s32 ret_val = 0; 186 187 ret_val = ixgbe_start_hw_generic(hw); 188 if (ret_val != 0) 189 goto out; 190 191 ret_val = ixgbe_start_hw_gen2(hw); 192 out: 193 return ret_val; 194 } 195 196 /** 197 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 198 * @hw: pointer to hardware structure 199 * 200 * Determines physical layer capabilities of the current configuration. 201 **/ 202 static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 203 { 204 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 205 u16 ext_ability = 0; 206 207 hw->phy.ops.identify(hw); 208 209 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, 210 &ext_ability); 211 if (ext_ability & MDIO_PMA_EXTABLE_10GBT) 212 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 213 if (ext_ability & MDIO_PMA_EXTABLE_1000BT) 214 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 215 if (ext_ability & MDIO_PMA_EXTABLE_100BTX) 216 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 217 218 return physical_layer; 219 } 220 221 /** 222 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 223 * @hw: pointer to hardware structure 224 * 225 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 226 * ixgbe_hw struct in order to set up EEPROM access. 227 **/ 228 static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 229 { 230 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 231 u32 eec; 232 u16 eeprom_size; 233 234 if (eeprom->type == ixgbe_eeprom_uninitialized) { 235 eeprom->semaphore_delay = 10; 236 eeprom->type = ixgbe_flash; 237 238 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 239 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 240 IXGBE_EEC_SIZE_SHIFT); 241 eeprom->word_size = 1 << (eeprom_size + 242 IXGBE_EEPROM_WORD_SIZE_SHIFT); 243 244 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 245 eeprom->type, eeprom->word_size); 246 } 247 248 return 0; 249 } 250 251 /** 252 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 253 * @hw: pointer to hardware structure 254 * @offset: offset of word in the EEPROM to read 255 * @data: word read from the EEPROM 256 * 257 * Reads a 16 bit word from the EEPROM using the EERD register. 258 **/ 259 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 260 { 261 s32 status = 0; 262 263 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 264 0) 265 status = ixgbe_read_eerd_generic(hw, offset, data); 266 else 267 status = IXGBE_ERR_SWFW_SYNC; 268 269 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 270 return status; 271 } 272 273 /** 274 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD 275 * @hw: pointer to hardware structure 276 * @offset: offset of word in the EEPROM to read 277 * @words: number of words 278 * @data: word(s) read from the EEPROM 279 * 280 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 281 **/ 282 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 283 u16 offset, u16 words, u16 *data) 284 { 285 s32 status = 0; 286 287 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 288 0) 289 status = ixgbe_read_eerd_buffer_generic(hw, offset, 290 words, data); 291 else 292 status = IXGBE_ERR_SWFW_SYNC; 293 294 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 295 return status; 296 } 297 298 /** 299 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 300 * @hw: pointer to hardware structure 301 * @offset: offset of word in the EEPROM to write 302 * @data: word write to the EEPROM 303 * 304 * Write a 16 bit word to the EEPROM using the EEWR register. 305 **/ 306 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 307 { 308 s32 status = 0; 309 310 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) 311 status = ixgbe_write_eewr_generic(hw, offset, data); 312 else 313 status = IXGBE_ERR_SWFW_SYNC; 314 315 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 316 return status; 317 } 318 319 /** 320 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 321 * @hw: pointer to hardware structure 322 * @offset: offset of word in the EEPROM to write 323 * @words: number of words 324 * @data: word(s) write to the EEPROM 325 * 326 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 327 **/ 328 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 329 u16 offset, u16 words, u16 *data) 330 { 331 s32 status = 0; 332 333 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 334 0) 335 status = ixgbe_write_eewr_buffer_generic(hw, offset, 336 words, data); 337 else 338 status = IXGBE_ERR_SWFW_SYNC; 339 340 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 341 return status; 342 } 343 344 /** 345 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 346 * 347 * This function does not use synchronization for EERD and EEWR. It can 348 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 349 * 350 * @hw: pointer to hardware structure 351 **/ 352 static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 353 { 354 u16 i; 355 u16 j; 356 u16 checksum = 0; 357 u16 length = 0; 358 u16 pointer = 0; 359 u16 word = 0; 360 361 /* 362 * Do not use hw->eeprom.ops.read because we do not want to take 363 * the synchronization semaphores here. Instead use 364 * ixgbe_read_eerd_generic 365 */ 366 367 /* Include 0x0-0x3F in the checksum */ 368 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 369 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) { 370 hw_dbg(hw, "EEPROM read failed\n"); 371 break; 372 } 373 checksum += word; 374 } 375 376 /* 377 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 378 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 379 */ 380 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 381 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 382 continue; 383 384 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) { 385 hw_dbg(hw, "EEPROM read failed\n"); 386 break; 387 } 388 389 /* Skip pointer section if the pointer is invalid. */ 390 if (pointer == 0xFFFF || pointer == 0 || 391 pointer >= hw->eeprom.word_size) 392 continue; 393 394 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) { 395 hw_dbg(hw, "EEPROM read failed\n"); 396 break; 397 } 398 399 /* Skip pointer section if length is invalid. */ 400 if (length == 0xFFFF || length == 0 || 401 (pointer + length) >= hw->eeprom.word_size) 402 continue; 403 404 for (j = pointer+1; j <= pointer+length; j++) { 405 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) { 406 hw_dbg(hw, "EEPROM read failed\n"); 407 break; 408 } 409 checksum += word; 410 } 411 } 412 413 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 414 415 return checksum; 416 } 417 418 /** 419 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 420 * @hw: pointer to hardware structure 421 * @checksum_val: calculated checksum 422 * 423 * Performs checksum calculation and validates the EEPROM checksum. If the 424 * caller does not need checksum_val, the value can be NULL. 425 **/ 426 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 427 u16 *checksum_val) 428 { 429 s32 status; 430 u16 checksum; 431 u16 read_checksum = 0; 432 433 /* 434 * Read the first word from the EEPROM. If this times out or fails, do 435 * not continue or we could be in for a very long wait while every 436 * EEPROM read fails 437 */ 438 status = hw->eeprom.ops.read(hw, 0, &checksum); 439 440 if (status != 0) { 441 hw_dbg(hw, "EEPROM read failed\n"); 442 goto out; 443 } 444 445 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 446 checksum = hw->eeprom.ops.calc_checksum(hw); 447 448 /* 449 * Do not use hw->eeprom.ops.read because we do not want to take 450 * the synchronization semaphores twice here. 451 */ 452 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 453 &read_checksum); 454 455 /* 456 * Verify read checksum from EEPROM is the same as 457 * calculated checksum 458 */ 459 if (read_checksum != checksum) 460 status = IXGBE_ERR_EEPROM_CHECKSUM; 461 462 /* If the user cares, return the calculated checksum */ 463 if (checksum_val) 464 *checksum_val = checksum; 465 } else { 466 status = IXGBE_ERR_SWFW_SYNC; 467 } 468 469 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 470 out: 471 return status; 472 } 473 474 /** 475 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 476 * @hw: pointer to hardware structure 477 * 478 * After writing EEPROM to shadow RAM using EEWR register, software calculates 479 * checksum and updates the EEPROM and instructs the hardware to update 480 * the flash. 481 **/ 482 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 483 { 484 s32 status; 485 u16 checksum; 486 487 /* 488 * Read the first word from the EEPROM. If this times out or fails, do 489 * not continue or we could be in for a very long wait while every 490 * EEPROM read fails 491 */ 492 status = hw->eeprom.ops.read(hw, 0, &checksum); 493 494 if (status != 0) 495 hw_dbg(hw, "EEPROM read failed\n"); 496 497 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 498 checksum = hw->eeprom.ops.calc_checksum(hw); 499 500 /* 501 * Do not use hw->eeprom.ops.write because we do not want to 502 * take the synchronization semaphores twice here. 503 */ 504 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 505 checksum); 506 507 if (status == 0) 508 status = ixgbe_update_flash_X540(hw); 509 else 510 status = IXGBE_ERR_SWFW_SYNC; 511 } 512 513 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 514 515 return status; 516 } 517 518 /** 519 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 520 * @hw: pointer to hardware structure 521 * 522 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 523 * EEPROM from shadow RAM to the flash device. 524 **/ 525 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 526 { 527 u32 flup; 528 s32 status = IXGBE_ERR_EEPROM; 529 530 status = ixgbe_poll_flash_update_done_X540(hw); 531 if (status == IXGBE_ERR_EEPROM) { 532 hw_dbg(hw, "Flash update time out\n"); 533 goto out; 534 } 535 536 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 537 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 538 539 status = ixgbe_poll_flash_update_done_X540(hw); 540 if (status == 0) 541 hw_dbg(hw, "Flash update complete\n"); 542 else 543 hw_dbg(hw, "Flash update time out\n"); 544 545 if (hw->revision_id == 0) { 546 flup = IXGBE_READ_REG(hw, IXGBE_EEC); 547 548 if (flup & IXGBE_EEC_SEC1VAL) { 549 flup |= IXGBE_EEC_FLUP; 550 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 551 } 552 553 status = ixgbe_poll_flash_update_done_X540(hw); 554 if (status == 0) 555 hw_dbg(hw, "Flash update complete\n"); 556 else 557 hw_dbg(hw, "Flash update time out\n"); 558 } 559 out: 560 return status; 561 } 562 563 /** 564 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 565 * @hw: pointer to hardware structure 566 * 567 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 568 * flash update is done. 569 **/ 570 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 571 { 572 u32 i; 573 u32 reg; 574 s32 status = IXGBE_ERR_EEPROM; 575 576 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 577 reg = IXGBE_READ_REG(hw, IXGBE_EEC); 578 if (reg & IXGBE_EEC_FLUDONE) { 579 status = 0; 580 break; 581 } 582 udelay(5); 583 } 584 return status; 585 } 586 587 /** 588 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 589 * @hw: pointer to hardware structure 590 * @mask: Mask to specify which semaphore to acquire 591 * 592 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 593 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 594 **/ 595 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 596 { 597 u32 swfw_sync; 598 u32 swmask = mask; 599 u32 fwmask = mask << 5; 600 u32 hwmask = 0; 601 u32 timeout = 200; 602 u32 i; 603 604 if (swmask == IXGBE_GSSR_EEP_SM) 605 hwmask = IXGBE_GSSR_FLASH_SM; 606 607 for (i = 0; i < timeout; i++) { 608 /* 609 * SW NVM semaphore bit is used for access to all 610 * SW_FW_SYNC bits (not just NVM) 611 */ 612 if (ixgbe_get_swfw_sync_semaphore(hw)) 613 return IXGBE_ERR_SWFW_SYNC; 614 615 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 616 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 617 swfw_sync |= swmask; 618 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 619 ixgbe_release_swfw_sync_semaphore(hw); 620 break; 621 } else { 622 /* 623 * Firmware currently using resource (fwmask), 624 * hardware currently using resource (hwmask), 625 * or other software thread currently using 626 * resource (swmask) 627 */ 628 ixgbe_release_swfw_sync_semaphore(hw); 629 usleep_range(5000, 10000); 630 } 631 } 632 633 /* 634 * If the resource is not released by the FW/HW the SW can assume that 635 * the FW/HW malfunctions. In that case the SW should sets the 636 * SW bit(s) of the requested resource(s) while ignoring the 637 * corresponding FW/HW bits in the SW_FW_SYNC register. 638 */ 639 if (i >= timeout) { 640 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 641 if (swfw_sync & (fwmask | hwmask)) { 642 if (ixgbe_get_swfw_sync_semaphore(hw)) 643 return IXGBE_ERR_SWFW_SYNC; 644 645 swfw_sync |= swmask; 646 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 647 ixgbe_release_swfw_sync_semaphore(hw); 648 } 649 } 650 651 usleep_range(5000, 10000); 652 return 0; 653 } 654 655 /** 656 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 657 * @hw: pointer to hardware structure 658 * @mask: Mask to specify which semaphore to release 659 * 660 * Releases the SWFW semaphore through the SW_FW_SYNC register 661 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 662 **/ 663 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 664 { 665 u32 swfw_sync; 666 u32 swmask = mask; 667 668 ixgbe_get_swfw_sync_semaphore(hw); 669 670 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 671 swfw_sync &= ~swmask; 672 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 673 674 ixgbe_release_swfw_sync_semaphore(hw); 675 usleep_range(5000, 10000); 676 } 677 678 /** 679 * ixgbe_get_nvm_semaphore - Get hardware semaphore 680 * @hw: pointer to hardware structure 681 * 682 * Sets the hardware semaphores so SW/FW can gain control of shared resources 683 **/ 684 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 685 { 686 s32 status = IXGBE_ERR_EEPROM; 687 u32 timeout = 2000; 688 u32 i; 689 u32 swsm; 690 691 /* Get SMBI software semaphore between device drivers first */ 692 for (i = 0; i < timeout; i++) { 693 /* 694 * If the SMBI bit is 0 when we read it, then the bit will be 695 * set and we have the semaphore 696 */ 697 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 698 if (!(swsm & IXGBE_SWSM_SMBI)) { 699 status = 0; 700 break; 701 } 702 udelay(50); 703 } 704 705 /* Now get the semaphore between SW/FW through the REGSMP bit */ 706 if (status) { 707 for (i = 0; i < timeout; i++) { 708 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 709 if (!(swsm & IXGBE_SWFW_REGSMP)) 710 break; 711 712 udelay(50); 713 } 714 } else { 715 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); 716 } 717 718 return status; 719 } 720 721 /** 722 * ixgbe_release_nvm_semaphore - Release hardware semaphore 723 * @hw: pointer to hardware structure 724 * 725 * This function clears hardware semaphore bits. 726 **/ 727 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 728 { 729 u32 swsm; 730 731 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 732 733 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 734 swsm &= ~IXGBE_SWSM_SMBI; 735 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 736 737 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 738 swsm &= ~IXGBE_SWFW_REGSMP; 739 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 740 741 IXGBE_WRITE_FLUSH(hw); 742 } 743 744 /** 745 * ixgbe_blink_led_start_X540 - Blink LED based on index. 746 * @hw: pointer to hardware structure 747 * @index: led number to blink 748 * 749 * Devices that implement the version 2 interface: 750 * X540 751 **/ 752 static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 753 { 754 u32 macc_reg; 755 u32 ledctl_reg; 756 ixgbe_link_speed speed; 757 bool link_up; 758 759 /* 760 * Link should be up in order for the blink bit in the LED control 761 * register to work. Force link and speed in the MAC if link is down. 762 * This will be reversed when we stop the blinking. 763 */ 764 hw->mac.ops.check_link(hw, &speed, &link_up, false); 765 if (!link_up) { 766 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 767 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 768 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 769 } 770 /* Set the LED to LINK_UP + BLINK. */ 771 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 772 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 773 ledctl_reg |= IXGBE_LED_BLINK(index); 774 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 775 IXGBE_WRITE_FLUSH(hw); 776 777 return 0; 778 } 779 780 /** 781 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 782 * @hw: pointer to hardware structure 783 * @index: led number to stop blinking 784 * 785 * Devices that implement the version 2 interface: 786 * X540 787 **/ 788 static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 789 { 790 u32 macc_reg; 791 u32 ledctl_reg; 792 793 /* Restore the LED to its default value. */ 794 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 795 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 796 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 797 ledctl_reg &= ~IXGBE_LED_BLINK(index); 798 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 799 800 /* Unforce link and speed in the MAC. */ 801 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 802 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 803 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 804 IXGBE_WRITE_FLUSH(hw); 805 806 return 0; 807 } 808 static struct ixgbe_mac_operations mac_ops_X540 = { 809 .init_hw = &ixgbe_init_hw_generic, 810 .reset_hw = &ixgbe_reset_hw_X540, 811 .start_hw = &ixgbe_start_hw_X540, 812 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 813 .get_media_type = &ixgbe_get_media_type_X540, 814 .get_supported_physical_layer = 815 &ixgbe_get_supported_physical_layer_X540, 816 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 817 .get_mac_addr = &ixgbe_get_mac_addr_generic, 818 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 819 .get_device_caps = &ixgbe_get_device_caps_generic, 820 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 821 .stop_adapter = &ixgbe_stop_adapter_generic, 822 .get_bus_info = &ixgbe_get_bus_info_generic, 823 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 824 .read_analog_reg8 = NULL, 825 .write_analog_reg8 = NULL, 826 .setup_link = &ixgbe_setup_mac_link_X540, 827 .set_rxpba = &ixgbe_set_rxpba_generic, 828 .check_link = &ixgbe_check_mac_link_generic, 829 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 830 .led_on = &ixgbe_led_on_generic, 831 .led_off = &ixgbe_led_off_generic, 832 .blink_led_start = &ixgbe_blink_led_start_X540, 833 .blink_led_stop = &ixgbe_blink_led_stop_X540, 834 .set_rar = &ixgbe_set_rar_generic, 835 .clear_rar = &ixgbe_clear_rar_generic, 836 .set_vmdq = &ixgbe_set_vmdq_generic, 837 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 838 .clear_vmdq = &ixgbe_clear_vmdq_generic, 839 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 840 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 841 .enable_mc = &ixgbe_enable_mc_generic, 842 .disable_mc = &ixgbe_disable_mc_generic, 843 .clear_vfta = &ixgbe_clear_vfta_generic, 844 .set_vfta = &ixgbe_set_vfta_generic, 845 .fc_enable = &ixgbe_fc_enable_generic, 846 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 847 .init_uta_tables = &ixgbe_init_uta_tables_generic, 848 .setup_sfp = NULL, 849 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 850 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 851 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 852 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 853 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 854 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 855 .get_thermal_sensor_data = NULL, 856 .init_thermal_sensor_thresh = NULL, 857 .prot_autoc_read = &prot_autoc_read_generic, 858 .prot_autoc_write = &prot_autoc_write_generic, 859 }; 860 861 static struct ixgbe_eeprom_operations eeprom_ops_X540 = { 862 .init_params = &ixgbe_init_eeprom_params_X540, 863 .read = &ixgbe_read_eerd_X540, 864 .read_buffer = &ixgbe_read_eerd_buffer_X540, 865 .write = &ixgbe_write_eewr_X540, 866 .write_buffer = &ixgbe_write_eewr_buffer_X540, 867 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, 868 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, 869 .update_checksum = &ixgbe_update_eeprom_checksum_X540, 870 }; 871 872 static struct ixgbe_phy_operations phy_ops_X540 = { 873 .identify = &ixgbe_identify_phy_generic, 874 .identify_sfp = &ixgbe_identify_sfp_module_generic, 875 .init = NULL, 876 .reset = NULL, 877 .read_reg = &ixgbe_read_phy_reg_generic, 878 .write_reg = &ixgbe_write_phy_reg_generic, 879 .setup_link = &ixgbe_setup_phy_link_generic, 880 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 881 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 882 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 883 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 884 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 885 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 886 .check_overtemp = &ixgbe_tn_check_overtemp, 887 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, 888 }; 889 890 struct ixgbe_info ixgbe_X540_info = { 891 .mac = ixgbe_mac_X540, 892 .get_invariants = &ixgbe_get_invariants_X540, 893 .mac_ops = &mac_ops_X540, 894 .eeprom_ops = &eeprom_ops_X540, 895 .phy_ops = &phy_ops_X540, 896 .mbx_ops = &mbx_ops_generic, 897 }; 898