1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/pci.h> 5 #include <linux/delay.h> 6 #include <linux/sched.h> 7 8 #include "ixgbe.h" 9 #include "ixgbe_phy.h" 10 #include "ixgbe_x540.h" 11 12 #define IXGBE_X540_MAX_TX_QUEUES 128 13 #define IXGBE_X540_MAX_RX_QUEUES 128 14 #define IXGBE_X540_RAR_ENTRIES 128 15 #define IXGBE_X540_MC_TBL_SIZE 128 16 #define IXGBE_X540_VFT_TBL_SIZE 128 17 #define IXGBE_X540_RX_PB_SIZE 384 18 19 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 20 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 21 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 22 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 23 24 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 25 { 26 return ixgbe_media_type_copper; 27 } 28 29 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) 30 { 31 struct ixgbe_mac_info *mac = &hw->mac; 32 struct ixgbe_phy_info *phy = &hw->phy; 33 34 /* set_phy_power was set by default to NULL */ 35 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 36 37 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 38 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 39 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 40 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 41 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 42 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 43 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 44 45 return 0; 46 } 47 48 /** 49 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires 50 * @hw: pointer to hardware structure 51 * @speed: new link speed 52 * @autoneg_wait_to_complete: true when waiting for completion is needed 53 **/ 54 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed, 55 bool autoneg_wait_to_complete) 56 { 57 return hw->phy.ops.setup_link_speed(hw, speed, 58 autoneg_wait_to_complete); 59 } 60 61 /** 62 * ixgbe_reset_hw_X540 - Perform hardware reset 63 * @hw: pointer to hardware structure 64 * 65 * Resets the hardware by resetting the transmit and receive units, masks 66 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 67 * reset. 68 **/ 69 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 70 { 71 s32 status; 72 u32 ctrl, i; 73 u32 swfw_mask = hw->phy.phy_semaphore_mask; 74 75 /* Call adapter stop to disable tx/rx and clear interrupts */ 76 status = hw->mac.ops.stop_adapter(hw); 77 if (status) 78 return status; 79 80 /* flush pending Tx transactions */ 81 ixgbe_clear_tx_pending(hw); 82 83 mac_reset_top: 84 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 85 if (status) { 86 hw_dbg(hw, "semaphore failed with %d", status); 87 return IXGBE_ERR_SWFW_SYNC; 88 } 89 90 ctrl = IXGBE_CTRL_RST; 91 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 92 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 93 IXGBE_WRITE_FLUSH(hw); 94 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 95 usleep_range(1000, 1200); 96 97 /* Poll for reset bit to self-clear indicating reset is complete */ 98 for (i = 0; i < 10; i++) { 99 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 100 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 101 break; 102 udelay(1); 103 } 104 105 if (ctrl & IXGBE_CTRL_RST_MASK) { 106 status = IXGBE_ERR_RESET_FAILED; 107 hw_dbg(hw, "Reset polling failed to complete.\n"); 108 } 109 msleep(100); 110 111 /* 112 * Double resets are required for recovery from certain error 113 * conditions. Between resets, it is necessary to stall to allow time 114 * for any pending HW events to complete. 115 */ 116 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 117 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 118 goto mac_reset_top; 119 } 120 121 /* Set the Rx packet buffer size. */ 122 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 123 124 /* Store the permanent mac address */ 125 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 126 127 /* 128 * Store MAC address from RAR0, clear receive address registers, and 129 * clear the multicast table. Also reset num_rar_entries to 128, 130 * since we modify this value when programming the SAN MAC address. 131 */ 132 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; 133 hw->mac.ops.init_rx_addrs(hw); 134 135 /* Store the permanent SAN mac address */ 136 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 137 138 /* Add the SAN MAC address to the RAR only if it's a valid address */ 139 if (is_valid_ether_addr(hw->mac.san_addr)) { 140 /* Save the SAN MAC RAR index */ 141 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 142 143 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 144 hw->mac.san_addr, 0, IXGBE_RAH_AV); 145 146 /* clear VMDq pool/queue selection for this RAR */ 147 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 148 IXGBE_CLEAR_VMDQ_ALL); 149 150 /* Reserve the last RAR for the SAN MAC address */ 151 hw->mac.num_rar_entries--; 152 } 153 154 /* Store the alternative WWNN/WWPN prefix */ 155 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 156 &hw->mac.wwpn_prefix); 157 158 return status; 159 } 160 161 /** 162 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 163 * @hw: pointer to hardware structure 164 * 165 * Starts the hardware using the generic start_hw function 166 * and the generation start_hw function. 167 * Then performs revision-specific operations, if any. 168 **/ 169 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 170 { 171 s32 ret_val; 172 173 ret_val = ixgbe_start_hw_generic(hw); 174 if (ret_val) 175 return ret_val; 176 177 return ixgbe_start_hw_gen2(hw); 178 } 179 180 /** 181 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 182 * @hw: pointer to hardware structure 183 * 184 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 185 * ixgbe_hw struct in order to set up EEPROM access. 186 **/ 187 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 188 { 189 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 190 u32 eec; 191 u16 eeprom_size; 192 193 if (eeprom->type == ixgbe_eeprom_uninitialized) { 194 eeprom->semaphore_delay = 10; 195 eeprom->type = ixgbe_flash; 196 197 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 198 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 199 IXGBE_EEC_SIZE_SHIFT); 200 eeprom->word_size = BIT(eeprom_size + 201 IXGBE_EEPROM_WORD_SIZE_SHIFT); 202 203 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 204 eeprom->type, eeprom->word_size); 205 } 206 207 return 0; 208 } 209 210 /** 211 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 212 * @hw: pointer to hardware structure 213 * @offset: offset of word in the EEPROM to read 214 * @data: word read from the EEPROM 215 * 216 * Reads a 16 bit word from the EEPROM using the EERD register. 217 **/ 218 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 219 { 220 s32 status; 221 222 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 223 return IXGBE_ERR_SWFW_SYNC; 224 225 status = ixgbe_read_eerd_generic(hw, offset, data); 226 227 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 228 return status; 229 } 230 231 /** 232 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD 233 * @hw: pointer to hardware structure 234 * @offset: offset of word in the EEPROM to read 235 * @words: number of words 236 * @data: word(s) read from the EEPROM 237 * 238 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 239 **/ 240 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 241 u16 offset, u16 words, u16 *data) 242 { 243 s32 status; 244 245 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 246 return IXGBE_ERR_SWFW_SYNC; 247 248 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data); 249 250 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 251 return status; 252 } 253 254 /** 255 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 256 * @hw: pointer to hardware structure 257 * @offset: offset of word in the EEPROM to write 258 * @data: word write to the EEPROM 259 * 260 * Write a 16 bit word to the EEPROM using the EEWR register. 261 **/ 262 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 263 { 264 s32 status; 265 266 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 267 return IXGBE_ERR_SWFW_SYNC; 268 269 status = ixgbe_write_eewr_generic(hw, offset, data); 270 271 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 272 return status; 273 } 274 275 /** 276 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 277 * @hw: pointer to hardware structure 278 * @offset: offset of word in the EEPROM to write 279 * @words: number of words 280 * @data: word(s) write to the EEPROM 281 * 282 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 283 **/ 284 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 285 u16 offset, u16 words, u16 *data) 286 { 287 s32 status; 288 289 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 290 return IXGBE_ERR_SWFW_SYNC; 291 292 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data); 293 294 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 295 return status; 296 } 297 298 /** 299 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 300 * 301 * This function does not use synchronization for EERD and EEWR. It can 302 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 303 * 304 * @hw: pointer to hardware structure 305 **/ 306 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 307 { 308 u16 i; 309 u16 j; 310 u16 checksum = 0; 311 u16 length = 0; 312 u16 pointer = 0; 313 u16 word = 0; 314 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM; 315 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 316 317 /* 318 * Do not use hw->eeprom.ops.read because we do not want to take 319 * the synchronization semaphores here. Instead use 320 * ixgbe_read_eerd_generic 321 */ 322 323 /* Include 0x0-0x3F in the checksum */ 324 for (i = 0; i < checksum_last_word; i++) { 325 if (ixgbe_read_eerd_generic(hw, i, &word)) { 326 hw_dbg(hw, "EEPROM read failed\n"); 327 return IXGBE_ERR_EEPROM; 328 } 329 checksum += word; 330 } 331 332 /* 333 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 334 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 335 */ 336 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 337 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 338 continue; 339 340 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 341 hw_dbg(hw, "EEPROM read failed\n"); 342 break; 343 } 344 345 /* Skip pointer section if the pointer is invalid. */ 346 if (pointer == 0xFFFF || pointer == 0 || 347 pointer >= hw->eeprom.word_size) 348 continue; 349 350 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 351 hw_dbg(hw, "EEPROM read failed\n"); 352 return IXGBE_ERR_EEPROM; 353 break; 354 } 355 356 /* Skip pointer section if length is invalid. */ 357 if (length == 0xFFFF || length == 0 || 358 (pointer + length) >= hw->eeprom.word_size) 359 continue; 360 361 for (j = pointer + 1; j <= pointer + length; j++) { 362 if (ixgbe_read_eerd_generic(hw, j, &word)) { 363 hw_dbg(hw, "EEPROM read failed\n"); 364 return IXGBE_ERR_EEPROM; 365 } 366 checksum += word; 367 } 368 } 369 370 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 371 372 return (s32)checksum; 373 } 374 375 /** 376 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 377 * @hw: pointer to hardware structure 378 * @checksum_val: calculated checksum 379 * 380 * Performs checksum calculation and validates the EEPROM checksum. If the 381 * caller does not need checksum_val, the value can be NULL. 382 **/ 383 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 384 u16 *checksum_val) 385 { 386 s32 status; 387 u16 checksum; 388 u16 read_checksum = 0; 389 390 /* Read the first word from the EEPROM. If this times out or fails, do 391 * not continue or we could be in for a very long wait while every 392 * EEPROM read fails 393 */ 394 status = hw->eeprom.ops.read(hw, 0, &checksum); 395 if (status) { 396 hw_dbg(hw, "EEPROM read failed\n"); 397 return status; 398 } 399 400 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 401 return IXGBE_ERR_SWFW_SYNC; 402 403 status = hw->eeprom.ops.calc_checksum(hw); 404 if (status < 0) 405 goto out; 406 407 checksum = (u16)(status & 0xffff); 408 409 /* Do not use hw->eeprom.ops.read because we do not want to take 410 * the synchronization semaphores twice here. 411 */ 412 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 413 &read_checksum); 414 if (status) 415 goto out; 416 417 /* Verify read checksum from EEPROM is the same as 418 * calculated checksum 419 */ 420 if (read_checksum != checksum) { 421 hw_dbg(hw, "Invalid EEPROM checksum"); 422 status = IXGBE_ERR_EEPROM_CHECKSUM; 423 } 424 425 /* If the user cares, return the calculated checksum */ 426 if (checksum_val) 427 *checksum_val = checksum; 428 429 out: 430 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 431 432 return status; 433 } 434 435 /** 436 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 437 * @hw: pointer to hardware structure 438 * 439 * After writing EEPROM to shadow RAM using EEWR register, software calculates 440 * checksum and updates the EEPROM and instructs the hardware to update 441 * the flash. 442 **/ 443 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 444 { 445 s32 status; 446 u16 checksum; 447 448 /* Read the first word from the EEPROM. If this times out or fails, do 449 * not continue or we could be in for a very long wait while every 450 * EEPROM read fails 451 */ 452 status = hw->eeprom.ops.read(hw, 0, &checksum); 453 if (status) { 454 hw_dbg(hw, "EEPROM read failed\n"); 455 return status; 456 } 457 458 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 459 return IXGBE_ERR_SWFW_SYNC; 460 461 status = hw->eeprom.ops.calc_checksum(hw); 462 if (status < 0) 463 goto out; 464 465 checksum = (u16)(status & 0xffff); 466 467 /* Do not use hw->eeprom.ops.write because we do not want to 468 * take the synchronization semaphores twice here. 469 */ 470 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 471 if (status) 472 goto out; 473 474 status = ixgbe_update_flash_X540(hw); 475 476 out: 477 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 478 return status; 479 } 480 481 /** 482 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 483 * @hw: pointer to hardware structure 484 * 485 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 486 * EEPROM from shadow RAM to the flash device. 487 **/ 488 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 489 { 490 u32 flup; 491 s32 status; 492 493 status = ixgbe_poll_flash_update_done_X540(hw); 494 if (status == IXGBE_ERR_EEPROM) { 495 hw_dbg(hw, "Flash update time out\n"); 496 return status; 497 } 498 499 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP; 500 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup); 501 502 status = ixgbe_poll_flash_update_done_X540(hw); 503 if (status == 0) 504 hw_dbg(hw, "Flash update complete\n"); 505 else 506 hw_dbg(hw, "Flash update time out\n"); 507 508 if (hw->revision_id == 0) { 509 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 510 511 if (flup & IXGBE_EEC_SEC1VAL) { 512 flup |= IXGBE_EEC_FLUP; 513 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup); 514 } 515 516 status = ixgbe_poll_flash_update_done_X540(hw); 517 if (status == 0) 518 hw_dbg(hw, "Flash update complete\n"); 519 else 520 hw_dbg(hw, "Flash update time out\n"); 521 } 522 523 return status; 524 } 525 526 /** 527 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 528 * @hw: pointer to hardware structure 529 * 530 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 531 * flash update is done. 532 **/ 533 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 534 { 535 u32 i; 536 u32 reg; 537 538 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 539 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 540 if (reg & IXGBE_EEC_FLUDONE) 541 return 0; 542 udelay(5); 543 } 544 return IXGBE_ERR_EEPROM; 545 } 546 547 /** 548 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 549 * @hw: pointer to hardware structure 550 * @mask: Mask to specify which semaphore to acquire 551 * 552 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 553 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 554 **/ 555 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 556 { 557 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 558 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 559 u32 fwmask = swmask << 5; 560 u32 timeout = 200; 561 u32 hwmask = 0; 562 u32 swfw_sync; 563 u32 i; 564 565 if (swmask & IXGBE_GSSR_EEP_SM) 566 hwmask = IXGBE_GSSR_FLASH_SM; 567 568 /* SW only mask does not have FW bit pair */ 569 if (mask & IXGBE_GSSR_SW_MNG_SM) 570 swmask |= IXGBE_GSSR_SW_MNG_SM; 571 572 swmask |= swi2c_mask; 573 fwmask |= swi2c_mask << 2; 574 for (i = 0; i < timeout; i++) { 575 /* SW NVM semaphore bit is used for access to all 576 * SW_FW_SYNC bits (not just NVM) 577 */ 578 if (ixgbe_get_swfw_sync_semaphore(hw)) 579 return IXGBE_ERR_SWFW_SYNC; 580 581 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); 582 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 583 swfw_sync |= swmask; 584 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); 585 ixgbe_release_swfw_sync_semaphore(hw); 586 usleep_range(5000, 6000); 587 return 0; 588 } 589 /* Firmware currently using resource (fwmask), hardware 590 * currently using resource (hwmask), or other software 591 * thread currently using resource (swmask) 592 */ 593 ixgbe_release_swfw_sync_semaphore(hw); 594 usleep_range(5000, 10000); 595 } 596 597 /* If the resource is not released by the FW/HW the SW can assume that 598 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 599 * of the requested resource(s) while ignoring the corresponding FW/HW 600 * bits in the SW_FW_SYNC register. 601 */ 602 if (ixgbe_get_swfw_sync_semaphore(hw)) 603 return IXGBE_ERR_SWFW_SYNC; 604 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); 605 if (swfw_sync & (fwmask | hwmask)) { 606 swfw_sync |= swmask; 607 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); 608 ixgbe_release_swfw_sync_semaphore(hw); 609 usleep_range(5000, 6000); 610 return 0; 611 } 612 /* If the resource is not released by other SW the SW can assume that 613 * the other SW malfunctions. In that case the SW should clear all SW 614 * flags that it does not own and then repeat the whole process once 615 * again. 616 */ 617 if (swfw_sync & swmask) { 618 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 619 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 620 IXGBE_GSSR_SW_MNG_SM; 621 622 if (swi2c_mask) 623 rmask |= IXGBE_GSSR_I2C_MASK; 624 ixgbe_release_swfw_sync_X540(hw, rmask); 625 ixgbe_release_swfw_sync_semaphore(hw); 626 return IXGBE_ERR_SWFW_SYNC; 627 } 628 ixgbe_release_swfw_sync_semaphore(hw); 629 630 return IXGBE_ERR_SWFW_SYNC; 631 } 632 633 /** 634 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 635 * @hw: pointer to hardware structure 636 * @mask: Mask to specify which semaphore to release 637 * 638 * Releases the SWFW semaphore through the SW_FW_SYNC register 639 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 640 **/ 641 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 642 { 643 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 644 u32 swfw_sync; 645 646 if (mask & IXGBE_GSSR_I2C_MASK) 647 swmask |= mask & IXGBE_GSSR_I2C_MASK; 648 ixgbe_get_swfw_sync_semaphore(hw); 649 650 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); 651 swfw_sync &= ~swmask; 652 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync); 653 654 ixgbe_release_swfw_sync_semaphore(hw); 655 usleep_range(5000, 6000); 656 } 657 658 /** 659 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 660 * @hw: pointer to hardware structure 661 * 662 * Sets the hardware semaphores so SW/FW can gain control of shared resources 663 */ 664 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 665 { 666 u32 timeout = 2000; 667 u32 i; 668 u32 swsm; 669 670 /* Get SMBI software semaphore between device drivers first */ 671 for (i = 0; i < timeout; i++) { 672 /* If the SMBI bit is 0 when we read it, then the bit will be 673 * set and we have the semaphore 674 */ 675 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 676 if (!(swsm & IXGBE_SWSM_SMBI)) 677 break; 678 usleep_range(50, 100); 679 } 680 681 if (i == timeout) { 682 hw_dbg(hw, 683 "Software semaphore SMBI between device drivers not granted.\n"); 684 return IXGBE_ERR_EEPROM; 685 } 686 687 /* Now get the semaphore between SW/FW through the REGSMP bit */ 688 for (i = 0; i < timeout; i++) { 689 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); 690 if (!(swsm & IXGBE_SWFW_REGSMP)) 691 return 0; 692 693 usleep_range(50, 100); 694 } 695 696 /* Release semaphores and return error if SW NVM semaphore 697 * was not granted because we do not have access to the EEPROM 698 */ 699 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n"); 700 ixgbe_release_swfw_sync_semaphore(hw); 701 return IXGBE_ERR_EEPROM; 702 } 703 704 /** 705 * ixgbe_release_nvm_semaphore - Release hardware semaphore 706 * @hw: pointer to hardware structure 707 * 708 * This function clears hardware semaphore bits. 709 **/ 710 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 711 { 712 u32 swsm; 713 714 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 715 716 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw)); 717 swsm &= ~IXGBE_SWFW_REGSMP; 718 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm); 719 720 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); 721 swsm &= ~IXGBE_SWSM_SMBI; 722 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); 723 724 IXGBE_WRITE_FLUSH(hw); 725 } 726 727 /** 728 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore 729 * @hw: pointer to hardware structure 730 * 731 * This function reset hardware semaphore bits for a semaphore that may 732 * have be left locked due to a catastrophic failure. 733 **/ 734 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) 735 { 736 u32 rmask; 737 738 /* First try to grab the semaphore but we don't need to bother 739 * looking to see whether we got the lock or not since we do 740 * the same thing regardless of whether we got the lock or not. 741 * We got the lock - we release it. 742 * We timeout trying to get the lock - we force its release. 743 */ 744 ixgbe_get_swfw_sync_semaphore(hw); 745 ixgbe_release_swfw_sync_semaphore(hw); 746 747 /* Acquire and release all software resources. */ 748 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 749 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 750 IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_I2C_MASK; 751 752 ixgbe_acquire_swfw_sync_X540(hw, rmask); 753 ixgbe_release_swfw_sync_X540(hw, rmask); 754 } 755 756 /** 757 * ixgbe_blink_led_start_X540 - Blink LED based on index. 758 * @hw: pointer to hardware structure 759 * @index: led number to blink 760 * 761 * Devices that implement the version 2 interface: 762 * X540 763 **/ 764 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 765 { 766 u32 macc_reg; 767 u32 ledctl_reg; 768 ixgbe_link_speed speed; 769 bool link_up; 770 771 if (index > 3) 772 return IXGBE_ERR_PARAM; 773 774 /* Link should be up in order for the blink bit in the LED control 775 * register to work. Force link and speed in the MAC if link is down. 776 * This will be reversed when we stop the blinking. 777 */ 778 hw->mac.ops.check_link(hw, &speed, &link_up, false); 779 if (!link_up) { 780 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 781 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 782 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 783 } 784 /* Set the LED to LINK_UP + BLINK. */ 785 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 786 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 787 ledctl_reg |= IXGBE_LED_BLINK(index); 788 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 789 IXGBE_WRITE_FLUSH(hw); 790 791 return 0; 792 } 793 794 /** 795 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 796 * @hw: pointer to hardware structure 797 * @index: led number to stop blinking 798 * 799 * Devices that implement the version 2 interface: 800 * X540 801 **/ 802 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 803 { 804 u32 macc_reg; 805 u32 ledctl_reg; 806 807 if (index > 3) 808 return IXGBE_ERR_PARAM; 809 810 /* Restore the LED to its default value. */ 811 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 812 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 813 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 814 ledctl_reg &= ~IXGBE_LED_BLINK(index); 815 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 816 817 /* Unforce link and speed in the MAC. */ 818 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 819 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 820 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 821 IXGBE_WRITE_FLUSH(hw); 822 823 return 0; 824 } 825 static const struct ixgbe_mac_operations mac_ops_X540 = { 826 .init_hw = &ixgbe_init_hw_generic, 827 .reset_hw = &ixgbe_reset_hw_X540, 828 .start_hw = &ixgbe_start_hw_X540, 829 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 830 .get_media_type = &ixgbe_get_media_type_X540, 831 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, 832 .get_mac_addr = &ixgbe_get_mac_addr_generic, 833 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 834 .get_device_caps = &ixgbe_get_device_caps_generic, 835 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 836 .stop_adapter = &ixgbe_stop_adapter_generic, 837 .get_bus_info = &ixgbe_get_bus_info_generic, 838 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 839 .read_analog_reg8 = NULL, 840 .write_analog_reg8 = NULL, 841 .setup_link = &ixgbe_setup_mac_link_X540, 842 .set_rxpba = &ixgbe_set_rxpba_generic, 843 .check_link = &ixgbe_check_mac_link_generic, 844 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 845 .led_on = &ixgbe_led_on_generic, 846 .led_off = &ixgbe_led_off_generic, 847 .init_led_link_act = ixgbe_init_led_link_act_generic, 848 .blink_led_start = &ixgbe_blink_led_start_X540, 849 .blink_led_stop = &ixgbe_blink_led_stop_X540, 850 .set_rar = &ixgbe_set_rar_generic, 851 .clear_rar = &ixgbe_clear_rar_generic, 852 .set_vmdq = &ixgbe_set_vmdq_generic, 853 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, 854 .clear_vmdq = &ixgbe_clear_vmdq_generic, 855 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, 856 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, 857 .enable_mc = &ixgbe_enable_mc_generic, 858 .disable_mc = &ixgbe_disable_mc_generic, 859 .clear_vfta = &ixgbe_clear_vfta_generic, 860 .set_vfta = &ixgbe_set_vfta_generic, 861 .fc_enable = &ixgbe_fc_enable_generic, 862 .setup_fc = ixgbe_setup_fc_generic, 863 .fc_autoneg = ixgbe_fc_autoneg, 864 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, 865 .init_uta_tables = &ixgbe_init_uta_tables_generic, 866 .setup_sfp = NULL, 867 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, 868 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, 869 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 870 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 871 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 872 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, 873 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, 874 .get_thermal_sensor_data = NULL, 875 .init_thermal_sensor_thresh = NULL, 876 .prot_autoc_read = &prot_autoc_read_generic, 877 .prot_autoc_write = &prot_autoc_write_generic, 878 .enable_rx = &ixgbe_enable_rx_generic, 879 .disable_rx = &ixgbe_disable_rx_generic, 880 }; 881 882 static const struct ixgbe_eeprom_operations eeprom_ops_X540 = { 883 .init_params = &ixgbe_init_eeprom_params_X540, 884 .read = &ixgbe_read_eerd_X540, 885 .read_buffer = &ixgbe_read_eerd_buffer_X540, 886 .write = &ixgbe_write_eewr_X540, 887 .write_buffer = &ixgbe_write_eewr_buffer_X540, 888 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, 889 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, 890 .update_checksum = &ixgbe_update_eeprom_checksum_X540, 891 }; 892 893 static const struct ixgbe_phy_operations phy_ops_X540 = { 894 .identify = &ixgbe_identify_phy_generic, 895 .identify_sfp = &ixgbe_identify_sfp_module_generic, 896 .init = NULL, 897 .reset = NULL, 898 .read_reg = &ixgbe_read_phy_reg_generic, 899 .write_reg = &ixgbe_write_phy_reg_generic, 900 .setup_link = &ixgbe_setup_phy_link_generic, 901 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 902 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, 903 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, 904 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, 905 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, 906 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, 907 .check_overtemp = &ixgbe_tn_check_overtemp, 908 .set_phy_power = &ixgbe_set_copper_phy_power, 909 }; 910 911 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 912 IXGBE_MVALS_INIT(X540) 913 }; 914 915 const struct ixgbe_info ixgbe_X540_info = { 916 .mac = ixgbe_mac_X540, 917 .get_invariants = &ixgbe_get_invariants_X540, 918 .mac_ops = &mac_ops_X540, 919 .eeprom_ops = &eeprom_ops_X540, 920 .phy_ops = &phy_ops_X540, 921 .mbx_ops = &mbx_ops_generic, 922 .mvals = ixgbe_mvals_X540, 923 }; 924