1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 #include "ixgbe.h" 28 #include <linux/export.h> 29 30 /* 31 * The 82599 and the X540 do not have true 64bit nanosecond scale 32 * counter registers. Instead, SYSTIME is defined by a fixed point 33 * system which allows the user to define the scale counter increment 34 * value at every level change of the oscillator driving the SYSTIME 35 * value. For both devices the TIMINCA:IV field defines this 36 * increment. On the X540 device, 31 bits are provided. However on the 37 * 82599 only provides 24 bits. The time unit is determined by the 38 * clock frequency of the oscillator in combination with the TIMINCA 39 * register. When these devices link at 10Gb the oscillator has a 40 * period of 6.4ns. In order to convert the scale counter into 41 * nanoseconds the cyclecounter and timecounter structures are 42 * used. The SYSTIME registers need to be converted to ns values by use 43 * of only a right shift (division by power of 2). The following math 44 * determines the largest incvalue that will fit into the available 45 * bits in the TIMINCA register. 46 * 47 * PeriodWidth: Number of bits to store the clock period 48 * MaxWidth: The maximum width value of the TIMINCA register 49 * Period: The clock period for the oscillator 50 * round(): discard the fractional portion of the calculation 51 * 52 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ] 53 * 54 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns 55 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns 56 * 57 * The period also changes based on the link speed: 58 * At 10Gb link or no link, the period remains the same. 59 * At 1Gb link, the period is multiplied by 10. (64ns) 60 * At 100Mb link, the period is multiplied by 100. (640ns) 61 * 62 * The calculated value allows us to right shift the SYSTIME register 63 * value in order to quickly convert it into a nanosecond clock, 64 * while allowing for the maximum possible adjustment value. 65 * 66 * These diagrams are only for the 10Gb link period 67 * 68 * SYSTIMEH SYSTIMEL 69 * +--------------+ +--------------+ 70 * X540 | 32 | | 1 | 3 | 28 | 71 * *--------------+ +--------------+ 72 * \________ 36 bits ______/ fract 73 * 74 * +--------------+ +--------------+ 75 * 82599 | 32 | | 8 | 3 | 21 | 76 * *--------------+ +--------------+ 77 * \________ 43 bits ______/ fract 78 * 79 * The 36 bit X540 SYSTIME overflows every 80 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds 81 * 82 * The 43 bit 82599 SYSTIME overflows every 83 * 2^43 * 10^-9 / 3600 = 2.4 hours 84 */ 85 #define IXGBE_INCVAL_10GB 0x66666666 86 #define IXGBE_INCVAL_1GB 0x40000000 87 #define IXGBE_INCVAL_100 0x50000000 88 89 #define IXGBE_INCVAL_SHIFT_10GB 28 90 #define IXGBE_INCVAL_SHIFT_1GB 24 91 #define IXGBE_INCVAL_SHIFT_100 21 92 93 #define IXGBE_INCVAL_SHIFT_82599 7 94 #define IXGBE_INCPER_SHIFT_82599 24 95 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL 96 97 #define IXGBE_OVERFLOW_PERIOD (HZ * 30) 98 99 #ifndef NSECS_PER_SEC 100 #define NSECS_PER_SEC 1000000000ULL 101 #endif 102 103 /** 104 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter) 105 * @cc - the cyclecounter structure 106 * 107 * this function reads the cyclecounter registers and is called by the 108 * cyclecounter structure used to construct a ns counter from the 109 * arbitrary fixed point registers 110 */ 111 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc) 112 { 113 struct ixgbe_adapter *adapter = 114 container_of(cc, struct ixgbe_adapter, cc); 115 struct ixgbe_hw *hw = &adapter->hw; 116 u64 stamp = 0; 117 118 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 119 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; 120 121 return stamp; 122 } 123 124 /** 125 * ixgbe_ptp_adjfreq 126 * @ptp - the ptp clock structure 127 * @ppb - parts per billion adjustment from base 128 * 129 * adjust the frequency of the ptp cycle counter by the 130 * indicated ppb from the base frequency. 131 */ 132 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 133 { 134 struct ixgbe_adapter *adapter = 135 container_of(ptp, struct ixgbe_adapter, ptp_caps); 136 struct ixgbe_hw *hw = &adapter->hw; 137 u64 freq; 138 u32 diff, incval; 139 int neg_adj = 0; 140 141 if (ppb < 0) { 142 neg_adj = 1; 143 ppb = -ppb; 144 } 145 146 smp_mb(); 147 incval = ACCESS_ONCE(adapter->base_incval); 148 149 freq = incval; 150 freq *= ppb; 151 diff = div_u64(freq, 1000000000ULL); 152 153 incval = neg_adj ? (incval - diff) : (incval + diff); 154 155 switch (hw->mac.type) { 156 case ixgbe_mac_X540: 157 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 158 break; 159 case ixgbe_mac_82599EB: 160 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 161 (1 << IXGBE_INCPER_SHIFT_82599) | 162 incval); 163 break; 164 default: 165 break; 166 } 167 168 return 0; 169 } 170 171 /** 172 * ixgbe_ptp_adjtime 173 * @ptp - the ptp clock structure 174 * @delta - offset to adjust the cycle counter by 175 * 176 * adjust the timer by resetting the timecounter structure. 177 */ 178 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 179 { 180 struct ixgbe_adapter *adapter = 181 container_of(ptp, struct ixgbe_adapter, ptp_caps); 182 unsigned long flags; 183 u64 now; 184 185 spin_lock_irqsave(&adapter->tmreg_lock, flags); 186 187 now = timecounter_read(&adapter->tc); 188 now += delta; 189 190 /* reset the timecounter */ 191 timecounter_init(&adapter->tc, 192 &adapter->cc, 193 now); 194 195 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 196 return 0; 197 } 198 199 /** 200 * ixgbe_ptp_gettime 201 * @ptp - the ptp clock structure 202 * @ts - timespec structure to hold the current time value 203 * 204 * read the timecounter and return the correct value on ns, 205 * after converting it into a struct timespec. 206 */ 207 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 208 { 209 struct ixgbe_adapter *adapter = 210 container_of(ptp, struct ixgbe_adapter, ptp_caps); 211 u64 ns; 212 u32 remainder; 213 unsigned long flags; 214 215 spin_lock_irqsave(&adapter->tmreg_lock, flags); 216 ns = timecounter_read(&adapter->tc); 217 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 218 219 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder); 220 ts->tv_nsec = remainder; 221 222 return 0; 223 } 224 225 /** 226 * ixgbe_ptp_settime 227 * @ptp - the ptp clock structure 228 * @ts - the timespec containing the new time for the cycle counter 229 * 230 * reset the timecounter to use a new base value instead of the kernel 231 * wall timer value. 232 */ 233 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp, 234 const struct timespec *ts) 235 { 236 struct ixgbe_adapter *adapter = 237 container_of(ptp, struct ixgbe_adapter, ptp_caps); 238 u64 ns; 239 unsigned long flags; 240 241 ns = ts->tv_sec * 1000000000ULL; 242 ns += ts->tv_nsec; 243 244 /* reset the timecounter */ 245 spin_lock_irqsave(&adapter->tmreg_lock, flags); 246 timecounter_init(&adapter->tc, &adapter->cc, ns); 247 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 248 249 return 0; 250 } 251 252 /** 253 * ixgbe_ptp_enable 254 * @ptp - the ptp clock structure 255 * @rq - the requested feature to change 256 * @on - whether to enable or disable the feature 257 * 258 * enable (or disable) ancillary features of the phc subsystem. 259 * our driver only supports the PPS feature on the X540 260 */ 261 static int ixgbe_ptp_enable(struct ptp_clock_info *ptp, 262 struct ptp_clock_request *rq, int on) 263 { 264 struct ixgbe_adapter *adapter = 265 container_of(ptp, struct ixgbe_adapter, ptp_caps); 266 267 /** 268 * When PPS is enabled, unmask the interrupt for the ClockOut 269 * feature, so that the interrupt handler can send the PPS 270 * event when the clock SDP triggers. Clear mask when PPS is 271 * disabled 272 */ 273 if (rq->type == PTP_CLK_REQ_PPS) { 274 switch (adapter->hw.mac.type) { 275 case ixgbe_mac_X540: 276 if (on) 277 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED; 278 else 279 adapter->flags2 &= 280 ~IXGBE_FLAG2_PTP_PPS_ENABLED; 281 return 0; 282 default: 283 break; 284 } 285 } 286 287 return -ENOTSUPP; 288 } 289 290 /** 291 * ixgbe_ptp_check_pps_event 292 * @adapter - the private adapter structure 293 * @eicr - the interrupt cause register value 294 * 295 * This function is called by the interrupt routine when checking for 296 * interrupts. It will check and handle a pps event. 297 */ 298 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr) 299 { 300 struct ixgbe_hw *hw = &adapter->hw; 301 struct ptp_clock_event event; 302 303 event.type = PTP_CLOCK_PPS; 304 305 /* Make sure ptp clock is valid, and PPS event enabled */ 306 if (!adapter->ptp_clock || 307 !(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED)) 308 return; 309 310 switch (hw->mac.type) { 311 case ixgbe_mac_X540: 312 if (eicr & IXGBE_EICR_TIMESYNC) 313 ptp_clock_event(adapter->ptp_clock, &event); 314 break; 315 default: 316 break; 317 } 318 } 319 320 /** 321 * ixgbe_ptp_enable_sdp 322 * @hw - the hardware private structure 323 * @shift - the clock shift for calculating nanoseconds 324 * 325 * this function enables the clock out feature on the sdp0 for the 326 * X540 device. It will create a 1second periodic output that can be 327 * used as the PPS (via an interrupt). 328 * 329 * It calculates when the systime will be on an exact second, and then 330 * aligns the start of the PPS signal to that value. The shift is 331 * necessary because it can change based on the link speed. 332 */ 333 static void ixgbe_ptp_enable_sdp(struct ixgbe_hw *hw, int shift) 334 { 335 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh; 336 u64 clock_edge = 0; 337 u32 rem; 338 339 switch (hw->mac.type) { 340 case ixgbe_mac_X540: 341 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 342 343 /* 344 * enable the SDP0 pin as output, and connected to the native 345 * function for Timesync (ClockOut) 346 */ 347 esdp |= (IXGBE_ESDP_SDP0_DIR | 348 IXGBE_ESDP_SDP0_NATIVE); 349 350 /* 351 * enable the Clock Out feature on SDP0, and allow interrupts 352 * to occur when the pin changes 353 */ 354 tsauxc = (IXGBE_TSAUXC_EN_CLK | 355 IXGBE_TSAUXC_SYNCLK | 356 IXGBE_TSAUXC_SDP0_INT); 357 358 /* clock period (or pulse length) */ 359 clktiml = (u32)(NSECS_PER_SEC << shift); 360 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32); 361 362 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 363 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; 364 365 /* 366 * account for the fact that we can't do u64 division 367 * with remainder, by converting the clock values into 368 * nanoseconds first 369 */ 370 clock_edge >>= shift; 371 div_u64_rem(clock_edge, NSECS_PER_SEC, &rem); 372 clock_edge += (NSECS_PER_SEC - rem); 373 clock_edge <<= shift; 374 375 /* specify the initial clock start time */ 376 trgttiml = (u32)clock_edge; 377 trgttimh = (u32)(clock_edge >> 32); 378 379 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml); 380 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh); 381 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml); 382 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh); 383 384 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 385 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 386 387 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_TIMESYNC); 388 break; 389 default: 390 break; 391 } 392 } 393 394 /** 395 * ixgbe_ptp_disable_sdp 396 * @hw - the private hardware structure 397 * 398 * this function disables the auxiliary SDP clock out feature 399 */ 400 static void ixgbe_ptp_disable_sdp(struct ixgbe_hw *hw) 401 { 402 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_TIMESYNC); 403 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0); 404 } 405 406 /** 407 * ixgbe_ptp_overflow_check - delayed work to detect SYSTIME overflow 408 * @work: structure containing information about this work task 409 * 410 * this work function is scheduled to continue reading the timecounter 411 * in order to prevent missing when the system time registers wrap 412 * around. This needs to be run approximately twice a minute when no 413 * PTP activity is occurring. 414 */ 415 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter) 416 { 417 unsigned long elapsed_jiffies = adapter->last_overflow_check - jiffies; 418 struct timespec ts; 419 420 if ((adapter->flags2 & IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED) && 421 (elapsed_jiffies >= IXGBE_OVERFLOW_PERIOD)) { 422 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts); 423 adapter->last_overflow_check = jiffies; 424 } 425 } 426 427 /** 428 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp 429 * @q_vector: structure containing interrupt and ring information 430 * @skb: particular skb to send timestamp with 431 * 432 * if the timestamp is valid, we convert it into the timecounter ns 433 * value, then store that result into the shhwtstamps structure which 434 * is passed up the network stack 435 */ 436 void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector, 437 struct sk_buff *skb) 438 { 439 struct ixgbe_adapter *adapter; 440 struct ixgbe_hw *hw; 441 struct skb_shared_hwtstamps shhwtstamps; 442 u64 regval = 0, ns; 443 u32 tsynctxctl; 444 unsigned long flags; 445 446 /* we cannot process timestamps on a ring without a q_vector */ 447 if (!q_vector || !q_vector->adapter) 448 return; 449 450 adapter = q_vector->adapter; 451 hw = &adapter->hw; 452 453 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 454 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 455 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32; 456 457 /* 458 * if TX timestamp is not valid, exit after clearing the 459 * timestamp registers 460 */ 461 if (!(tsynctxctl & IXGBE_TSYNCTXCTL_VALID)) 462 return; 463 464 spin_lock_irqsave(&adapter->tmreg_lock, flags); 465 ns = timecounter_cyc2time(&adapter->tc, regval); 466 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 467 468 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 469 shhwtstamps.hwtstamp = ns_to_ktime(ns); 470 skb_tstamp_tx(skb, &shhwtstamps); 471 } 472 473 /** 474 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp 475 * @q_vector: structure containing interrupt and ring information 476 * @skb: particular skb to send timestamp with 477 * 478 * if the timestamp is valid, we convert it into the timecounter ns 479 * value, then store that result into the shhwtstamps structure which 480 * is passed up the network stack 481 */ 482 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector, 483 struct sk_buff *skb) 484 { 485 struct ixgbe_adapter *adapter; 486 struct ixgbe_hw *hw; 487 struct skb_shared_hwtstamps *shhwtstamps; 488 u64 regval = 0, ns; 489 u32 tsyncrxctl; 490 unsigned long flags; 491 492 /* we cannot process timestamps on a ring without a q_vector */ 493 if (!q_vector || !q_vector->adapter) 494 return; 495 496 adapter = q_vector->adapter; 497 hw = &adapter->hw; 498 499 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 500 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 501 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32; 502 503 /* 504 * If this bit is set, then the RX registers contain the time stamp. No 505 * other packet will be time stamped until we read these registers, so 506 * read the registers to make them available again. Because only one 507 * packet can be time stamped at a time, we know that the register 508 * values must belong to this one here and therefore we don't need to 509 * compare any of the additional attributes stored for it. 510 * 511 * If nothing went wrong, then it should have a skb_shared_tx that we 512 * can turn into a skb_shared_hwtstamps. 513 */ 514 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) 515 return; 516 517 spin_lock_irqsave(&adapter->tmreg_lock, flags); 518 ns = timecounter_cyc2time(&adapter->tc, regval); 519 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 520 521 shhwtstamps = skb_hwtstamps(skb); 522 shhwtstamps->hwtstamp = ns_to_ktime(ns); 523 } 524 525 /** 526 * ixgbe_ptp_hwtstamp_ioctl - control hardware time stamping 527 * @adapter: pointer to adapter struct 528 * @ifreq: ioctl data 529 * @cmd: particular ioctl requested 530 * 531 * Outgoing time stamping can be enabled and disabled. Play nice and 532 * disable it when requested, although it shouldn't case any overhead 533 * when no packet needs it. At most one packet in the queue may be 534 * marked for time stamping, otherwise it would be impossible to tell 535 * for sure to which packet the hardware time stamp belongs. 536 * 537 * Incoming time stamping has to be configured via the hardware 538 * filters. Not all combinations are supported, in particular event 539 * type has to be specified. Matching the kind of event packet is 540 * not supported, with the exception of "all V2 events regardless of 541 * level 2 or 4". 542 */ 543 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, 544 struct ifreq *ifr, int cmd) 545 { 546 struct ixgbe_hw *hw = &adapter->hw; 547 struct hwtstamp_config config; 548 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; 549 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; 550 u32 tsync_rx_mtrl = 0; 551 bool is_l4 = false; 552 bool is_l2 = false; 553 u32 regval; 554 555 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 556 return -EFAULT; 557 558 /* reserved for future extensions */ 559 if (config.flags) 560 return -EINVAL; 561 562 switch (config.tx_type) { 563 case HWTSTAMP_TX_OFF: 564 tsync_tx_ctl = 0; 565 case HWTSTAMP_TX_ON: 566 break; 567 default: 568 return -ERANGE; 569 } 570 571 switch (config.rx_filter) { 572 case HWTSTAMP_FILTER_NONE: 573 tsync_rx_ctl = 0; 574 break; 575 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 576 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; 577 tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG; 578 is_l4 = true; 579 break; 580 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 581 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; 582 tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG; 583 is_l4 = true; 584 break; 585 case HWTSTAMP_FILTER_PTP_V2_SYNC: 586 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 587 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 588 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2; 589 tsync_rx_mtrl = IXGBE_RXMTRL_V2_SYNC_MSG; 590 is_l2 = true; 591 is_l4 = true; 592 config.rx_filter = HWTSTAMP_FILTER_SOME; 593 break; 594 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 595 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 596 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 597 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2; 598 tsync_rx_mtrl = IXGBE_RXMTRL_V2_DELAY_REQ_MSG; 599 is_l2 = true; 600 is_l4 = true; 601 config.rx_filter = HWTSTAMP_FILTER_SOME; 602 break; 603 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 604 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 605 case HWTSTAMP_FILTER_PTP_V2_EVENT: 606 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; 607 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 608 is_l2 = true; 609 is_l4 = true; 610 break; 611 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 612 case HWTSTAMP_FILTER_ALL: 613 default: 614 /* 615 * register RXMTRL must be set, therefore it is not 616 * possible to time stamp both V1 Sync and Delay_Req messages 617 * and hardware does not support timestamping all packets 618 * => return error 619 */ 620 return -ERANGE; 621 } 622 623 if (hw->mac.type == ixgbe_mac_82598EB) { 624 if (tsync_rx_ctl | tsync_tx_ctl) 625 return -ERANGE; 626 return 0; 627 } 628 629 /* define ethertype filter for timestamped packets */ 630 if (is_l2) 631 IXGBE_WRITE_REG(hw, IXGBE_ETQF(3), 632 (IXGBE_ETQF_FILTER_EN | /* enable filter */ 633 IXGBE_ETQF_1588 | /* enable timestamping */ 634 ETH_P_1588)); /* 1588 eth protocol type */ 635 else 636 IXGBE_WRITE_REG(hw, IXGBE_ETQF(3), 0); 637 638 #define PTP_PORT 319 639 /* L4 Queue Filter[3]: filter by destination port and protocol */ 640 if (is_l4) { 641 u32 ftqf = (IXGBE_FTQF_PROTOCOL_UDP /* UDP */ 642 | IXGBE_FTQF_POOL_MASK_EN /* Pool not compared */ 643 | IXGBE_FTQF_QUEUE_ENABLE); 644 645 ftqf |= ((IXGBE_FTQF_PROTOCOL_COMP_MASK /* protocol check */ 646 & IXGBE_FTQF_DEST_PORT_MASK /* dest check */ 647 & IXGBE_FTQF_SOURCE_PORT_MASK) /* source check */ 648 << IXGBE_FTQF_5TUPLE_MASK_SHIFT); 649 650 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(3), 651 (3 << IXGBE_IMIR_RX_QUEUE_SHIFT_82599 | 652 IXGBE_IMIR_SIZE_BP_82599)); 653 654 /* enable port check */ 655 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(3), 656 (htons(PTP_PORT) | 657 htons(PTP_PORT) << 16)); 658 659 IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), ftqf); 660 661 tsync_rx_mtrl |= PTP_PORT << 16; 662 } else { 663 IXGBE_WRITE_REG(hw, IXGBE_FTQF(3), 0); 664 } 665 666 /* enable/disable TX */ 667 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 668 regval &= ~IXGBE_TSYNCTXCTL_ENABLED; 669 regval |= tsync_tx_ctl; 670 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval); 671 672 /* enable/disable RX */ 673 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 674 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK); 675 regval |= tsync_rx_ctl; 676 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval); 677 678 /* define which PTP packets are time stamped */ 679 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl); 680 681 IXGBE_WRITE_FLUSH(hw); 682 683 /* clear TX/RX time stamp registers, just to be sure */ 684 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH); 685 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH); 686 687 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 688 -EFAULT : 0; 689 } 690 691 /** 692 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw 693 * @adapter - pointer to the adapter structure 694 * 695 * this function initializes the timecounter and cyclecounter 696 * structures for use in generated a ns counter from the arbitrary 697 * fixed point cycles registers in the hardware. 698 * 699 * A change in link speed impacts the frequency of the DMA clock on 700 * the device, which is used to generate the cycle counter 701 * registers. Therefor this function is called whenever the link speed 702 * changes. 703 * 704 * This function also turns on the SDP pin for clock out feature (X540 705 * only), because this is where the shift is first calculated. 706 */ 707 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter) 708 { 709 struct ixgbe_hw *hw = &adapter->hw; 710 u32 incval = 0; 711 u32 shift = 0; 712 u32 cycle_speed; 713 unsigned long flags; 714 715 /** 716 * Determine what speed we need to set the cyclecounter 717 * for. It should be different for 100Mb, 1Gb, and 10Gb. Treat 718 * unknown speeds as 10Gb. (Hence why we can't just copy the 719 * link_speed. 720 */ 721 switch (adapter->link_speed) { 722 case IXGBE_LINK_SPEED_100_FULL: 723 case IXGBE_LINK_SPEED_1GB_FULL: 724 case IXGBE_LINK_SPEED_10GB_FULL: 725 cycle_speed = adapter->link_speed; 726 break; 727 default: 728 /* cycle speed should be 10Gb when there is no link */ 729 cycle_speed = IXGBE_LINK_SPEED_10GB_FULL; 730 break; 731 } 732 733 /* Bail if the cycle speed didn't change */ 734 if (adapter->cycle_speed == cycle_speed) 735 return; 736 737 /* disable the SDP clock out */ 738 ixgbe_ptp_disable_sdp(hw); 739 740 /** 741 * Scale the NIC cycle counter by a large factor so that 742 * relatively small corrections to the frequency can be added 743 * or subtracted. The drawbacks of a large factor include 744 * (a) the clock register overflows more quickly, (b) the cycle 745 * counter structure must be able to convert the systime value 746 * to nanoseconds using only a multiplier and a right-shift, 747 * and (c) the value must fit within the timinca register space 748 * => math based on internal DMA clock rate and available bits 749 */ 750 switch (cycle_speed) { 751 case IXGBE_LINK_SPEED_100_FULL: 752 incval = IXGBE_INCVAL_100; 753 shift = IXGBE_INCVAL_SHIFT_100; 754 break; 755 case IXGBE_LINK_SPEED_1GB_FULL: 756 incval = IXGBE_INCVAL_1GB; 757 shift = IXGBE_INCVAL_SHIFT_1GB; 758 break; 759 case IXGBE_LINK_SPEED_10GB_FULL: 760 incval = IXGBE_INCVAL_10GB; 761 shift = IXGBE_INCVAL_SHIFT_10GB; 762 break; 763 } 764 765 /** 766 * Modify the calculated values to fit within the correct 767 * number of bits specified by the hardware. The 82599 doesn't 768 * have the same space as the X540, so bitshift the calculated 769 * values to fit. 770 */ 771 switch (hw->mac.type) { 772 case ixgbe_mac_X540: 773 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 774 break; 775 case ixgbe_mac_82599EB: 776 incval >>= IXGBE_INCVAL_SHIFT_82599; 777 shift -= IXGBE_INCVAL_SHIFT_82599; 778 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 779 (1 << IXGBE_INCPER_SHIFT_82599) | 780 incval); 781 break; 782 default: 783 /* other devices aren't supported */ 784 return; 785 } 786 787 /* reset the system time registers */ 788 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000); 789 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000); 790 IXGBE_WRITE_FLUSH(hw); 791 792 /* now that the shift has been calculated and the systime 793 * registers reset, (re-)enable the Clock out feature*/ 794 ixgbe_ptp_enable_sdp(hw, shift); 795 796 /* store the new cycle speed */ 797 adapter->cycle_speed = cycle_speed; 798 799 ACCESS_ONCE(adapter->base_incval) = incval; 800 smp_mb(); 801 802 /* grab the ptp lock */ 803 spin_lock_irqsave(&adapter->tmreg_lock, flags); 804 805 memset(&adapter->cc, 0, sizeof(adapter->cc)); 806 adapter->cc.read = ixgbe_ptp_read; 807 adapter->cc.mask = CLOCKSOURCE_MASK(64); 808 adapter->cc.shift = shift; 809 adapter->cc.mult = 1; 810 811 /* reset the ns time counter */ 812 timecounter_init(&adapter->tc, &adapter->cc, 813 ktime_to_ns(ktime_get_real())); 814 815 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 816 } 817 818 /** 819 * ixgbe_ptp_init 820 * @adapter - the ixgbe private adapter structure 821 * 822 * This function performs the required steps for enabling ptp 823 * support. If ptp support has already been loaded it simply calls the 824 * cyclecounter init routine and exits. 825 */ 826 void ixgbe_ptp_init(struct ixgbe_adapter *adapter) 827 { 828 struct net_device *netdev = adapter->netdev; 829 830 switch (adapter->hw.mac.type) { 831 case ixgbe_mac_X540: 832 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 833 adapter->ptp_caps.owner = THIS_MODULE; 834 adapter->ptp_caps.max_adj = 250000000; 835 adapter->ptp_caps.n_alarm = 0; 836 adapter->ptp_caps.n_ext_ts = 0; 837 adapter->ptp_caps.n_per_out = 0; 838 adapter->ptp_caps.pps = 1; 839 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq; 840 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; 841 adapter->ptp_caps.gettime = ixgbe_ptp_gettime; 842 adapter->ptp_caps.settime = ixgbe_ptp_settime; 843 adapter->ptp_caps.enable = ixgbe_ptp_enable; 844 break; 845 case ixgbe_mac_82599EB: 846 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 847 adapter->ptp_caps.owner = THIS_MODULE; 848 adapter->ptp_caps.max_adj = 250000000; 849 adapter->ptp_caps.n_alarm = 0; 850 adapter->ptp_caps.n_ext_ts = 0; 851 adapter->ptp_caps.n_per_out = 0; 852 adapter->ptp_caps.pps = 0; 853 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq; 854 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; 855 adapter->ptp_caps.gettime = ixgbe_ptp_gettime; 856 adapter->ptp_caps.settime = ixgbe_ptp_settime; 857 adapter->ptp_caps.enable = ixgbe_ptp_enable; 858 break; 859 default: 860 adapter->ptp_clock = NULL; 861 return; 862 } 863 864 spin_lock_init(&adapter->tmreg_lock); 865 866 ixgbe_ptp_start_cyclecounter(adapter); 867 868 /* (Re)start the overflow check */ 869 adapter->flags2 |= IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED; 870 871 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps); 872 if (IS_ERR(adapter->ptp_clock)) { 873 adapter->ptp_clock = NULL; 874 e_dev_err("ptp_clock_register failed\n"); 875 } else 876 e_dev_info("registered PHC device on %s\n", netdev->name); 877 878 return; 879 } 880 881 /** 882 * ixgbe_ptp_stop - disable ptp device and stop the overflow check 883 * @adapter: pointer to adapter struct 884 * 885 * this function stops the ptp support, and cancels the delayed work. 886 */ 887 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter) 888 { 889 ixgbe_ptp_disable_sdp(&adapter->hw); 890 891 /* stop the overflow check task */ 892 adapter->flags2 &= ~IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED; 893 894 if (adapter->ptp_clock) { 895 ptp_clock_unregister(adapter->ptp_clock); 896 adapter->ptp_clock = NULL; 897 e_dev_info("removed PHC on %s\n", 898 adapter->netdev->name); 899 } 900 } 901