1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 #include "ixgbe.h" 28 #include <linux/export.h> 29 #include <linux/ptp_classify.h> 30 31 /* 32 * The 82599 and the X540 do not have true 64bit nanosecond scale 33 * counter registers. Instead, SYSTIME is defined by a fixed point 34 * system which allows the user to define the scale counter increment 35 * value at every level change of the oscillator driving the SYSTIME 36 * value. For both devices the TIMINCA:IV field defines this 37 * increment. On the X540 device, 31 bits are provided. However on the 38 * 82599 only provides 24 bits. The time unit is determined by the 39 * clock frequency of the oscillator in combination with the TIMINCA 40 * register. When these devices link at 10Gb the oscillator has a 41 * period of 6.4ns. In order to convert the scale counter into 42 * nanoseconds the cyclecounter and timecounter structures are 43 * used. The SYSTIME registers need to be converted to ns values by use 44 * of only a right shift (division by power of 2). The following math 45 * determines the largest incvalue that will fit into the available 46 * bits in the TIMINCA register. 47 * 48 * PeriodWidth: Number of bits to store the clock period 49 * MaxWidth: The maximum width value of the TIMINCA register 50 * Period: The clock period for the oscillator 51 * round(): discard the fractional portion of the calculation 52 * 53 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ] 54 * 55 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns 56 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns 57 * 58 * The period also changes based on the link speed: 59 * At 10Gb link or no link, the period remains the same. 60 * At 1Gb link, the period is multiplied by 10. (64ns) 61 * At 100Mb link, the period is multiplied by 100. (640ns) 62 * 63 * The calculated value allows us to right shift the SYSTIME register 64 * value in order to quickly convert it into a nanosecond clock, 65 * while allowing for the maximum possible adjustment value. 66 * 67 * These diagrams are only for the 10Gb link period 68 * 69 * SYSTIMEH SYSTIMEL 70 * +--------------+ +--------------+ 71 * X540 | 32 | | 1 | 3 | 28 | 72 * *--------------+ +--------------+ 73 * \________ 36 bits ______/ fract 74 * 75 * +--------------+ +--------------+ 76 * 82599 | 32 | | 8 | 3 | 21 | 77 * *--------------+ +--------------+ 78 * \________ 43 bits ______/ fract 79 * 80 * The 36 bit X540 SYSTIME overflows every 81 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds 82 * 83 * The 43 bit 82599 SYSTIME overflows every 84 * 2^43 * 10^-9 / 3600 = 2.4 hours 85 */ 86 #define IXGBE_INCVAL_10GB 0x66666666 87 #define IXGBE_INCVAL_1GB 0x40000000 88 #define IXGBE_INCVAL_100 0x50000000 89 90 #define IXGBE_INCVAL_SHIFT_10GB 28 91 #define IXGBE_INCVAL_SHIFT_1GB 24 92 #define IXGBE_INCVAL_SHIFT_100 21 93 94 #define IXGBE_INCVAL_SHIFT_82599 7 95 #define IXGBE_INCPER_SHIFT_82599 24 96 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL 97 98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30) 99 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15) 100 101 #ifndef NSECS_PER_SEC 102 #define NSECS_PER_SEC 1000000000ULL 103 #endif 104 105 /** 106 * ixgbe_ptp_setup_sdp 107 * @hw: the hardware private structure 108 * 109 * this function enables or disables the clock out feature on SDP0 for 110 * the X540 device. It will create a 1second periodic output that can 111 * be used as the PPS (via an interrupt). 112 * 113 * It calculates when the systime will be on an exact second, and then 114 * aligns the start of the PPS signal to that value. The shift is 115 * necessary because it can change based on the link speed. 116 */ 117 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter) 118 { 119 struct ixgbe_hw *hw = &adapter->hw; 120 int shift = adapter->cc.shift; 121 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem; 122 u64 ns = 0, clock_edge = 0; 123 124 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) && 125 (hw->mac.type == ixgbe_mac_X540)) { 126 127 /* disable the pin first */ 128 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0); 129 IXGBE_WRITE_FLUSH(hw); 130 131 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 132 133 /* 134 * enable the SDP0 pin as output, and connected to the 135 * native function for Timesync (ClockOut) 136 */ 137 esdp |= (IXGBE_ESDP_SDP0_DIR | 138 IXGBE_ESDP_SDP0_NATIVE); 139 140 /* 141 * enable the Clock Out feature on SDP0, and allow 142 * interrupts to occur when the pin changes 143 */ 144 tsauxc = (IXGBE_TSAUXC_EN_CLK | 145 IXGBE_TSAUXC_SYNCLK | 146 IXGBE_TSAUXC_SDP0_INT); 147 148 /* clock period (or pulse length) */ 149 clktiml = (u32)(NSECS_PER_SEC << shift); 150 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32); 151 152 /* 153 * Account for the cyclecounter wrap-around value by 154 * using the converted ns value of the current time to 155 * check for when the next aligned second would occur. 156 */ 157 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 158 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; 159 ns = timecounter_cyc2time(&adapter->tc, clock_edge); 160 161 div_u64_rem(ns, NSECS_PER_SEC, &rem); 162 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift); 163 164 /* specify the initial clock start time */ 165 trgttiml = (u32)clock_edge; 166 trgttimh = (u32)(clock_edge >> 32); 167 168 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml); 169 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh); 170 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml); 171 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh); 172 173 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 174 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 175 } else { 176 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0); 177 } 178 179 IXGBE_WRITE_FLUSH(hw); 180 } 181 182 /** 183 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter) 184 * @cc: the cyclecounter structure 185 * 186 * this function reads the cyclecounter registers and is called by the 187 * cyclecounter structure used to construct a ns counter from the 188 * arbitrary fixed point registers 189 */ 190 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc) 191 { 192 struct ixgbe_adapter *adapter = 193 container_of(cc, struct ixgbe_adapter, cc); 194 struct ixgbe_hw *hw = &adapter->hw; 195 u64 stamp = 0; 196 197 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 198 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; 199 200 return stamp; 201 } 202 203 /** 204 * ixgbe_ptp_adjfreq 205 * @ptp: the ptp clock structure 206 * @ppb: parts per billion adjustment from base 207 * 208 * adjust the frequency of the ptp cycle counter by the 209 * indicated ppb from the base frequency. 210 */ 211 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 212 { 213 struct ixgbe_adapter *adapter = 214 container_of(ptp, struct ixgbe_adapter, ptp_caps); 215 struct ixgbe_hw *hw = &adapter->hw; 216 u64 freq; 217 u32 diff, incval; 218 int neg_adj = 0; 219 220 if (ppb < 0) { 221 neg_adj = 1; 222 ppb = -ppb; 223 } 224 225 smp_mb(); 226 incval = ACCESS_ONCE(adapter->base_incval); 227 228 freq = incval; 229 freq *= ppb; 230 diff = div_u64(freq, 1000000000ULL); 231 232 incval = neg_adj ? (incval - diff) : (incval + diff); 233 234 switch (hw->mac.type) { 235 case ixgbe_mac_X540: 236 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 237 break; 238 case ixgbe_mac_82599EB: 239 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 240 (1 << IXGBE_INCPER_SHIFT_82599) | 241 incval); 242 break; 243 default: 244 break; 245 } 246 247 return 0; 248 } 249 250 /** 251 * ixgbe_ptp_adjtime 252 * @ptp: the ptp clock structure 253 * @delta: offset to adjust the cycle counter by 254 * 255 * adjust the timer by resetting the timecounter structure. 256 */ 257 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 258 { 259 struct ixgbe_adapter *adapter = 260 container_of(ptp, struct ixgbe_adapter, ptp_caps); 261 unsigned long flags; 262 u64 now; 263 264 spin_lock_irqsave(&adapter->tmreg_lock, flags); 265 266 now = timecounter_read(&adapter->tc); 267 now += delta; 268 269 /* reset the timecounter */ 270 timecounter_init(&adapter->tc, 271 &adapter->cc, 272 now); 273 274 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 275 276 ixgbe_ptp_setup_sdp(adapter); 277 278 return 0; 279 } 280 281 /** 282 * ixgbe_ptp_gettime 283 * @ptp: the ptp clock structure 284 * @ts: timespec structure to hold the current time value 285 * 286 * read the timecounter and return the correct value on ns, 287 * after converting it into a struct timespec. 288 */ 289 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 290 { 291 struct ixgbe_adapter *adapter = 292 container_of(ptp, struct ixgbe_adapter, ptp_caps); 293 u64 ns; 294 u32 remainder; 295 unsigned long flags; 296 297 spin_lock_irqsave(&adapter->tmreg_lock, flags); 298 ns = timecounter_read(&adapter->tc); 299 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 300 301 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder); 302 ts->tv_nsec = remainder; 303 304 return 0; 305 } 306 307 /** 308 * ixgbe_ptp_settime 309 * @ptp: the ptp clock structure 310 * @ts: the timespec containing the new time for the cycle counter 311 * 312 * reset the timecounter to use a new base value instead of the kernel 313 * wall timer value. 314 */ 315 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp, 316 const struct timespec *ts) 317 { 318 struct ixgbe_adapter *adapter = 319 container_of(ptp, struct ixgbe_adapter, ptp_caps); 320 u64 ns; 321 unsigned long flags; 322 323 ns = ts->tv_sec * 1000000000ULL; 324 ns += ts->tv_nsec; 325 326 /* reset the timecounter */ 327 spin_lock_irqsave(&adapter->tmreg_lock, flags); 328 timecounter_init(&adapter->tc, &adapter->cc, ns); 329 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 330 331 ixgbe_ptp_setup_sdp(adapter); 332 return 0; 333 } 334 335 /** 336 * ixgbe_ptp_enable 337 * @ptp: the ptp clock structure 338 * @rq: the requested feature to change 339 * @on: whether to enable or disable the feature 340 * 341 * enable (or disable) ancillary features of the phc subsystem. 342 * our driver only supports the PPS feature on the X540 343 */ 344 static int ixgbe_ptp_enable(struct ptp_clock_info *ptp, 345 struct ptp_clock_request *rq, int on) 346 { 347 struct ixgbe_adapter *adapter = 348 container_of(ptp, struct ixgbe_adapter, ptp_caps); 349 350 /** 351 * When PPS is enabled, unmask the interrupt for the ClockOut 352 * feature, so that the interrupt handler can send the PPS 353 * event when the clock SDP triggers. Clear mask when PPS is 354 * disabled 355 */ 356 if (rq->type == PTP_CLK_REQ_PPS) { 357 switch (adapter->hw.mac.type) { 358 case ixgbe_mac_X540: 359 if (on) 360 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED; 361 else 362 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED; 363 364 ixgbe_ptp_setup_sdp(adapter); 365 return 0; 366 default: 367 break; 368 } 369 } 370 371 return -ENOTSUPP; 372 } 373 374 /** 375 * ixgbe_ptp_check_pps_event 376 * @adapter: the private adapter structure 377 * @eicr: the interrupt cause register value 378 * 379 * This function is called by the interrupt routine when checking for 380 * interrupts. It will check and handle a pps event. 381 */ 382 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr) 383 { 384 struct ixgbe_hw *hw = &adapter->hw; 385 struct ptp_clock_event event; 386 387 event.type = PTP_CLOCK_PPS; 388 389 /* this check is necessary in case the interrupt was enabled via some 390 * alternative means (ex. debug_fs). Better to check here than 391 * everywhere that calls this function. 392 */ 393 if (!adapter->ptp_clock) 394 return; 395 396 switch (hw->mac.type) { 397 case ixgbe_mac_X540: 398 ptp_clock_event(adapter->ptp_clock, &event); 399 break; 400 default: 401 break; 402 } 403 } 404 405 /** 406 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow 407 * @adapter: private adapter struct 408 * 409 * this watchdog task periodically reads the timecounter 410 * in order to prevent missing when the system time registers wrap 411 * around. This needs to be run approximately twice a minute. 412 */ 413 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter) 414 { 415 bool timeout = time_is_before_jiffies(adapter->last_overflow_check + 416 IXGBE_OVERFLOW_PERIOD); 417 struct timespec ts; 418 419 if (timeout) { 420 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts); 421 adapter->last_overflow_check = jiffies; 422 } 423 } 424 425 /** 426 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched 427 * @adapter: private network adapter structure 428 * 429 * this watchdog task is scheduled to detect error case where hardware has 430 * dropped an Rx packet that was timestamped when the ring is full. The 431 * particular error is rare but leaves the device in a state unable to timestamp 432 * any future packets. 433 */ 434 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter) 435 { 436 struct ixgbe_hw *hw = &adapter->hw; 437 struct ixgbe_ring *rx_ring; 438 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 439 unsigned long rx_event; 440 int n; 441 442 /* if we don't have a valid timestamp in the registers, just update the 443 * timeout counter and exit 444 */ 445 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) { 446 adapter->last_rx_ptp_check = jiffies; 447 return; 448 } 449 450 /* determine the most recent watchdog or rx_timestamp event */ 451 rx_event = adapter->last_rx_ptp_check; 452 for (n = 0; n < adapter->num_rx_queues; n++) { 453 rx_ring = adapter->rx_ring[n]; 454 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 455 rx_event = rx_ring->last_rx_timestamp; 456 } 457 458 /* only need to read the high RXSTMP register to clear the lock */ 459 if (time_is_before_jiffies(rx_event + 5*HZ)) { 460 IXGBE_READ_REG(hw, IXGBE_RXSTMPH); 461 adapter->last_rx_ptp_check = jiffies; 462 463 e_warn(drv, "clearing RX Timestamp hang"); 464 } 465 } 466 467 /** 468 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp 469 * @adapter: the private adapter struct 470 * 471 * if the timestamp is valid, we convert it into the timecounter ns 472 * value, then store that result into the shhwtstamps structure which 473 * is passed up the network stack 474 */ 475 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter) 476 { 477 struct ixgbe_hw *hw = &adapter->hw; 478 struct skb_shared_hwtstamps shhwtstamps; 479 u64 regval = 0, ns; 480 unsigned long flags; 481 482 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 483 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32; 484 485 spin_lock_irqsave(&adapter->tmreg_lock, flags); 486 ns = timecounter_cyc2time(&adapter->tc, regval); 487 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 488 489 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 490 shhwtstamps.hwtstamp = ns_to_ktime(ns); 491 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 492 493 dev_kfree_skb_any(adapter->ptp_tx_skb); 494 adapter->ptp_tx_skb = NULL; 495 } 496 497 /** 498 * ixgbe_ptp_tx_hwtstamp_work 499 * @work: pointer to the work struct 500 * 501 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware 502 * timestamp has been taken for the current skb. It is necesary, because the 503 * descriptor's "done" bit does not correlate with the timestamp event. 504 */ 505 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work) 506 { 507 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter, 508 ptp_tx_work); 509 struct ixgbe_hw *hw = &adapter->hw; 510 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 511 IXGBE_PTP_TX_TIMEOUT); 512 u32 tsynctxctl; 513 514 /* we have to have a valid skb */ 515 if (!adapter->ptp_tx_skb) 516 return; 517 518 if (timeout) { 519 dev_kfree_skb_any(adapter->ptp_tx_skb); 520 adapter->ptp_tx_skb = NULL; 521 e_warn(drv, "clearing Tx Timestamp hang"); 522 return; 523 } 524 525 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 526 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) 527 ixgbe_ptp_tx_hwtstamp(adapter); 528 else 529 /* reschedule to keep checking if it's not available yet */ 530 schedule_work(&adapter->ptp_tx_work); 531 } 532 533 /** 534 * __ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp 535 * @q_vector: structure containing interrupt and ring information 536 * @skb: particular skb to send timestamp with 537 * 538 * if the timestamp is valid, we convert it into the timecounter ns 539 * value, then store that result into the shhwtstamps structure which 540 * is passed up the network stack 541 */ 542 void __ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector, 543 struct sk_buff *skb) 544 { 545 struct ixgbe_adapter *adapter; 546 struct ixgbe_hw *hw; 547 struct skb_shared_hwtstamps *shhwtstamps; 548 u64 regval = 0, ns; 549 u32 tsyncrxctl; 550 unsigned long flags; 551 552 /* we cannot process timestamps on a ring without a q_vector */ 553 if (!q_vector || !q_vector->adapter) 554 return; 555 556 adapter = q_vector->adapter; 557 hw = &adapter->hw; 558 559 /* 560 * Read the tsyncrxctl register afterwards in order to prevent taking an 561 * I/O hit on every packet. 562 */ 563 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 564 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) 565 return; 566 567 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 568 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32; 569 570 571 spin_lock_irqsave(&adapter->tmreg_lock, flags); 572 ns = timecounter_cyc2time(&adapter->tc, regval); 573 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 574 575 shhwtstamps = skb_hwtstamps(skb); 576 shhwtstamps->hwtstamp = ns_to_ktime(ns); 577 } 578 579 /** 580 * ixgbe_ptp_hwtstamp_ioctl - control hardware time stamping 581 * @adapter: pointer to adapter struct 582 * @ifreq: ioctl data 583 * @cmd: particular ioctl requested 584 * 585 * Outgoing time stamping can be enabled and disabled. Play nice and 586 * disable it when requested, although it shouldn't case any overhead 587 * when no packet needs it. At most one packet in the queue may be 588 * marked for time stamping, otherwise it would be impossible to tell 589 * for sure to which packet the hardware time stamp belongs. 590 * 591 * Incoming time stamping has to be configured via the hardware 592 * filters. Not all combinations are supported, in particular event 593 * type has to be specified. Matching the kind of event packet is 594 * not supported, with the exception of "all V2 events regardless of 595 * level 2 or 4". 596 * 597 * Since hardware always timestamps Path delay packets when timestamping V2 598 * packets, regardless of the type specified in the register, only use V2 599 * Event mode. This more accurately tells the user what the hardware is going 600 * to do anyways. 601 */ 602 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter, 603 struct ifreq *ifr, int cmd) 604 { 605 struct ixgbe_hw *hw = &adapter->hw; 606 struct hwtstamp_config config; 607 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; 608 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; 609 u32 tsync_rx_mtrl = PTP_EV_PORT << 16; 610 bool is_l2 = false; 611 u32 regval; 612 613 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 614 return -EFAULT; 615 616 /* reserved for future extensions */ 617 if (config.flags) 618 return -EINVAL; 619 620 switch (config.tx_type) { 621 case HWTSTAMP_TX_OFF: 622 tsync_tx_ctl = 0; 623 case HWTSTAMP_TX_ON: 624 break; 625 default: 626 return -ERANGE; 627 } 628 629 switch (config.rx_filter) { 630 case HWTSTAMP_FILTER_NONE: 631 tsync_rx_ctl = 0; 632 tsync_rx_mtrl = 0; 633 break; 634 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 635 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; 636 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG; 637 break; 638 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 639 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; 640 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG; 641 break; 642 case HWTSTAMP_FILTER_PTP_V2_EVENT: 643 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 644 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 645 case HWTSTAMP_FILTER_PTP_V2_SYNC: 646 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 647 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 648 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 649 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 650 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 651 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; 652 is_l2 = true; 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 654 break; 655 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 656 case HWTSTAMP_FILTER_ALL: 657 default: 658 /* 659 * register RXMTRL must be set in order to do V1 packets, 660 * therefore it is not possible to time stamp both V1 Sync and 661 * Delay_Req messages and hardware does not support 662 * timestamping all packets => return error 663 */ 664 config.rx_filter = HWTSTAMP_FILTER_NONE; 665 return -ERANGE; 666 } 667 668 if (hw->mac.type == ixgbe_mac_82598EB) { 669 if (tsync_rx_ctl | tsync_tx_ctl) 670 return -ERANGE; 671 return 0; 672 } 673 674 /* define ethertype filter for timestamping L2 packets */ 675 if (is_l2) 676 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 677 (IXGBE_ETQF_FILTER_EN | /* enable filter */ 678 IXGBE_ETQF_1588 | /* enable timestamping */ 679 ETH_P_1588)); /* 1588 eth protocol type */ 680 else 681 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 682 683 684 /* enable/disable TX */ 685 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 686 regval &= ~IXGBE_TSYNCTXCTL_ENABLED; 687 regval |= tsync_tx_ctl; 688 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval); 689 690 /* enable/disable RX */ 691 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 692 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK); 693 regval |= tsync_rx_ctl; 694 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval); 695 696 /* define which PTP packets are time stamped */ 697 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl); 698 699 IXGBE_WRITE_FLUSH(hw); 700 701 /* clear TX/RX time stamp registers, just to be sure */ 702 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH); 703 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH); 704 705 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 706 -EFAULT : 0; 707 } 708 709 /** 710 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw 711 * @adapter: pointer to the adapter structure 712 * 713 * This function should be called to set the proper values for the TIMINCA 714 * register and tell the cyclecounter structure what the tick rate of SYSTIME 715 * is. It does not directly modify SYSTIME registers or the timecounter 716 * structure. It should be called whenever a new TIMINCA value is necessary, 717 * such as during initialization or when the link speed changes. 718 */ 719 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter) 720 { 721 struct ixgbe_hw *hw = &adapter->hw; 722 u32 incval = 0; 723 u32 shift = 0; 724 unsigned long flags; 725 726 /** 727 * Scale the NIC cycle counter by a large factor so that 728 * relatively small corrections to the frequency can be added 729 * or subtracted. The drawbacks of a large factor include 730 * (a) the clock register overflows more quickly, (b) the cycle 731 * counter structure must be able to convert the systime value 732 * to nanoseconds using only a multiplier and a right-shift, 733 * and (c) the value must fit within the timinca register space 734 * => math based on internal DMA clock rate and available bits 735 * 736 * Note that when there is no link, internal DMA clock is same as when 737 * link speed is 10Gb. Set the registers correctly even when link is 738 * down to preserve the clock setting 739 */ 740 switch (adapter->link_speed) { 741 case IXGBE_LINK_SPEED_100_FULL: 742 incval = IXGBE_INCVAL_100; 743 shift = IXGBE_INCVAL_SHIFT_100; 744 break; 745 case IXGBE_LINK_SPEED_1GB_FULL: 746 incval = IXGBE_INCVAL_1GB; 747 shift = IXGBE_INCVAL_SHIFT_1GB; 748 break; 749 case IXGBE_LINK_SPEED_10GB_FULL: 750 default: 751 incval = IXGBE_INCVAL_10GB; 752 shift = IXGBE_INCVAL_SHIFT_10GB; 753 break; 754 } 755 756 /** 757 * Modify the calculated values to fit within the correct 758 * number of bits specified by the hardware. The 82599 doesn't 759 * have the same space as the X540, so bitshift the calculated 760 * values to fit. 761 */ 762 switch (hw->mac.type) { 763 case ixgbe_mac_X540: 764 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 765 break; 766 case ixgbe_mac_82599EB: 767 incval >>= IXGBE_INCVAL_SHIFT_82599; 768 shift -= IXGBE_INCVAL_SHIFT_82599; 769 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 770 (1 << IXGBE_INCPER_SHIFT_82599) | 771 incval); 772 break; 773 default: 774 /* other devices aren't supported */ 775 return; 776 } 777 778 /* update the base incval used to calculate frequency adjustment */ 779 ACCESS_ONCE(adapter->base_incval) = incval; 780 smp_mb(); 781 782 /* need lock to prevent incorrect read while modifying cyclecounter */ 783 spin_lock_irqsave(&adapter->tmreg_lock, flags); 784 785 memset(&adapter->cc, 0, sizeof(adapter->cc)); 786 adapter->cc.read = ixgbe_ptp_read; 787 adapter->cc.mask = CLOCKSOURCE_MASK(64); 788 adapter->cc.shift = shift; 789 adapter->cc.mult = 1; 790 791 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 792 } 793 794 /** 795 * ixgbe_ptp_reset 796 * @adapter: the ixgbe private board structure 797 * 798 * When the MAC resets, all timesync features are reset. This function should be 799 * called to re-enable the PTP clock structure. It will re-init the timecounter 800 * structure based on the kernel time as well as setup the cycle counter data. 801 */ 802 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter) 803 { 804 struct ixgbe_hw *hw = &adapter->hw; 805 unsigned long flags; 806 807 /* set SYSTIME registers to 0 just in case */ 808 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000); 809 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000); 810 IXGBE_WRITE_FLUSH(hw); 811 812 ixgbe_ptp_start_cyclecounter(adapter); 813 814 spin_lock_irqsave(&adapter->tmreg_lock, flags); 815 816 /* reset the ns time counter */ 817 timecounter_init(&adapter->tc, &adapter->cc, 818 ktime_to_ns(ktime_get_real())); 819 820 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 821 822 /* 823 * Now that the shift has been calculated and the systime 824 * registers reset, (re-)enable the Clock out feature 825 */ 826 ixgbe_ptp_setup_sdp(adapter); 827 } 828 829 /** 830 * ixgbe_ptp_init 831 * @adapter: the ixgbe private adapter structure 832 * 833 * This function performs the required steps for enabling ptp 834 * support. If ptp support has already been loaded it simply calls the 835 * cyclecounter init routine and exits. 836 */ 837 void ixgbe_ptp_init(struct ixgbe_adapter *adapter) 838 { 839 struct net_device *netdev = adapter->netdev; 840 841 switch (adapter->hw.mac.type) { 842 case ixgbe_mac_X540: 843 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name); 844 adapter->ptp_caps.owner = THIS_MODULE; 845 adapter->ptp_caps.max_adj = 250000000; 846 adapter->ptp_caps.n_alarm = 0; 847 adapter->ptp_caps.n_ext_ts = 0; 848 adapter->ptp_caps.n_per_out = 0; 849 adapter->ptp_caps.pps = 1; 850 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq; 851 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; 852 adapter->ptp_caps.gettime = ixgbe_ptp_gettime; 853 adapter->ptp_caps.settime = ixgbe_ptp_settime; 854 adapter->ptp_caps.enable = ixgbe_ptp_enable; 855 break; 856 case ixgbe_mac_82599EB: 857 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name); 858 adapter->ptp_caps.owner = THIS_MODULE; 859 adapter->ptp_caps.max_adj = 250000000; 860 adapter->ptp_caps.n_alarm = 0; 861 adapter->ptp_caps.n_ext_ts = 0; 862 adapter->ptp_caps.n_per_out = 0; 863 adapter->ptp_caps.pps = 0; 864 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq; 865 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; 866 adapter->ptp_caps.gettime = ixgbe_ptp_gettime; 867 adapter->ptp_caps.settime = ixgbe_ptp_settime; 868 adapter->ptp_caps.enable = ixgbe_ptp_enable; 869 break; 870 default: 871 adapter->ptp_clock = NULL; 872 return; 873 } 874 875 spin_lock_init(&adapter->tmreg_lock); 876 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work); 877 878 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 879 &adapter->pdev->dev); 880 if (IS_ERR(adapter->ptp_clock)) { 881 adapter->ptp_clock = NULL; 882 e_dev_err("ptp_clock_register failed\n"); 883 } else 884 e_dev_info("registered PHC device on %s\n", netdev->name); 885 886 ixgbe_ptp_reset(adapter); 887 888 /* enter the IXGBE_PTP_RUNNING state */ 889 set_bit(__IXGBE_PTP_RUNNING, &adapter->state); 890 891 return; 892 } 893 894 /** 895 * ixgbe_ptp_stop - disable ptp device and stop the overflow check 896 * @adapter: pointer to adapter struct 897 * 898 * this function stops the ptp support, and cancels the delayed work. 899 */ 900 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter) 901 { 902 /* Leave the IXGBE_PTP_RUNNING state. */ 903 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 904 return; 905 906 /* stop the PPS signal */ 907 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED; 908 ixgbe_ptp_setup_sdp(adapter); 909 910 cancel_work_sync(&adapter->ptp_tx_work); 911 if (adapter->ptp_tx_skb) { 912 dev_kfree_skb_any(adapter->ptp_tx_skb); 913 adapter->ptp_tx_skb = NULL; 914 } 915 916 if (adapter->ptp_clock) { 917 ptp_clock_unregister(adapter->ptp_clock); 918 adapter->ptp_clock = NULL; 919 e_dev_info("removed PHC on %s\n", 920 adapter->netdev->name); 921 } 922 } 923