1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #ifndef _IXGBE_PHY_H_
5 #define _IXGBE_PHY_H_
6 
7 #include "ixgbe_type.h"
8 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
9 #define IXGBE_I2C_EEPROM_DEV_ADDR2   0xA2
10 
11 /* EEPROM byte offsets */
12 #define IXGBE_SFF_IDENTIFIER		0x0
13 #define IXGBE_SFF_IDENTIFIER_SFP	0x3
14 #define IXGBE_SFF_VENDOR_OUI_BYTE0	0x25
15 #define IXGBE_SFF_VENDOR_OUI_BYTE1	0x26
16 #define IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
17 #define IXGBE_SFF_1GBE_COMP_CODES	0x6
18 #define IXGBE_SFF_10GBE_COMP_CODES	0x3
19 #define IXGBE_SFF_CABLE_TECHNOLOGY	0x8
20 #define IXGBE_SFF_CABLE_SPEC_COMP	0x3C
21 #define IXGBE_SFF_SFF_8472_SWAP		0x5C
22 #define IXGBE_SFF_SFF_8472_COMP		0x5E
23 #define IXGBE_SFF_SFF_8472_OSCB		0x6E
24 #define IXGBE_SFF_SFF_8472_ESCB		0x76
25 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS	0xD
26 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0	0xA5
27 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1	0xA6
28 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2	0xA7
29 #define IXGBE_SFF_QSFP_CONNECTOR	0x82
30 #define IXGBE_SFF_QSFP_10GBE_COMP	0x83
31 #define IXGBE_SFF_QSFP_1GBE_COMP	0x86
32 #define IXGBE_SFF_QSFP_CABLE_LENGTH	0x92
33 #define IXGBE_SFF_QSFP_DEVICE_TECH	0x93
34 
35 /* Bitmasks */
36 #define IXGBE_SFF_DA_PASSIVE_CABLE		0x4
37 #define IXGBE_SFF_DA_ACTIVE_CABLE		0x8
38 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING	0x4
39 #define IXGBE_SFF_1GBASESX_CAPABLE		0x1
40 #define IXGBE_SFF_1GBASELX_CAPABLE		0x2
41 #define IXGBE_SFF_1GBASET_CAPABLE		0x8
42 #define IXGBE_SFF_10GBASESR_CAPABLE		0x10
43 #define IXGBE_SFF_10GBASELR_CAPABLE		0x20
44 #define IXGBE_SFF_SOFT_RS_SELECT_MASK		0x8
45 #define IXGBE_SFF_SOFT_RS_SELECT_10G		0x8
46 #define IXGBE_SFF_SOFT_RS_SELECT_1G		0x0
47 #define IXGBE_SFF_ADDRESSING_MODE		0x4
48 #define IXGBE_SFF_DDM_IMPLEMENTED		0x40
49 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE		0x1
50 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE		0x8
51 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE	0x23
52 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL	0x0
53 #define IXGBE_I2C_EEPROM_READ_MASK		0x100
54 #define IXGBE_I2C_EEPROM_STATUS_MASK		0x3
55 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
56 #define IXGBE_I2C_EEPROM_STATUS_PASS		0x1
57 #define IXGBE_I2C_EEPROM_STATUS_FAIL		0x2
58 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS	0x3
59 #define IXGBE_CS4227				0xBE    /* CS4227 address */
60 #define IXGBE_CS4227_GLOBAL_ID_LSB		0
61 #define IXGBE_CS4227_GLOBAL_ID_MSB		1
62 #define IXGBE_CS4227_SCRATCH			2
63 #define IXGBE_CS4227_EFUSE_PDF_SKU		0x19F
64 #define IXGBE_CS4223_SKU_ID			0x0010  /* Quad port */
65 #define IXGBE_CS4227_SKU_ID			0x0014  /* Dual port */
66 #define IXGBE_CS4227_RESET_PENDING		0x1357
67 #define IXGBE_CS4227_RESET_COMPLETE		0x5AA5
68 #define IXGBE_CS4227_RETRIES			15
69 #define IXGBE_CS4227_EFUSE_STATUS		0x0181
70 #define IXGBE_CS4227_LINE_SPARE22_MSB		0x12AD	/* Reg to set speed */
71 #define IXGBE_CS4227_LINE_SPARE24_LSB		0x12B0	/* Reg to set EDC */
72 #define IXGBE_CS4227_HOST_SPARE22_MSB		0x1AAD	/* Reg to set speed */
73 #define IXGBE_CS4227_HOST_SPARE24_LSB		0x1AB0	/* Reg to program EDC */
74 #define IXGBE_CS4227_EEPROM_STATUS		0x5001
75 #define IXGBE_CS4227_EEPROM_LOAD_OK		0x0001
76 #define IXGBE_CS4227_SPEED_1G			0x8000
77 #define IXGBE_CS4227_SPEED_10G			0
78 #define IXGBE_CS4227_EDC_MODE_CX1		0x0002
79 #define IXGBE_CS4227_EDC_MODE_SR		0x0004
80 #define IXGBE_CS4227_EDC_MODE_DIAG		0x0008
81 #define IXGBE_CS4227_RESET_HOLD			500	/* microseconds */
82 #define IXGBE_CS4227_RESET_DELAY		500	/* milliseconds */
83 #define IXGBE_CS4227_CHECK_DELAY		30	/* milliseconds */
84 #define IXGBE_PE				0xE0	/* Port expander addr */
85 #define IXGBE_PE_OUTPUT				1	/* Output reg offset */
86 #define IXGBE_PE_CONFIG				3	/* Config reg offset */
87 #define IXGBE_PE_BIT1				BIT(1)
88 
89 /* Flow control defines */
90 #define IXGBE_TAF_SYM_PAUSE                  0x400
91 #define IXGBE_TAF_ASM_PAUSE                  0x800
92 
93 /* Bit-shift macros */
94 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
95 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
96 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
97 
98 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
99 #define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
100 #define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
101 #define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
102 #define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
103 
104 /* I2C SDA and SCL timing parameters for standard mode */
105 #define IXGBE_I2C_T_HD_STA  4
106 #define IXGBE_I2C_T_LOW     5
107 #define IXGBE_I2C_T_HIGH    4
108 #define IXGBE_I2C_T_SU_STA  5
109 #define IXGBE_I2C_T_HD_DATA 5
110 #define IXGBE_I2C_T_SU_DATA 1
111 #define IXGBE_I2C_T_RISE    1
112 #define IXGBE_I2C_T_FALL    1
113 #define IXGBE_I2C_T_SU_STO  4
114 #define IXGBE_I2C_T_BUF     5
115 
116 #define IXGBE_SFP_DETECT_RETRIES	2
117 
118 #define IXGBE_TN_LASI_STATUS_REG        0x9005
119 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
120 
121 /* SFP+ SFF-8472 Compliance code */
122 #define IXGBE_SFF_SFF_8472_UNSUP      0x00
123 
124 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw);
125 
126 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
127 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
128 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
129 			       u32 device_type, u16 *phy_data);
130 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
131 				u32 device_type, u16 phy_data);
132 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
133 			   u32 device_type, u16 *phy_data);
134 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
135 			    u32 device_type, u16 phy_data);
136 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
137 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
138 				       ixgbe_link_speed speed,
139 				       bool autoneg_wait_to_complete);
140 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
141 					       ixgbe_link_speed *speed,
142 					       bool *autoneg);
143 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
144 
145 /* PHY specific */
146 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
147 			     ixgbe_link_speed *speed,
148 			     bool *link_up);
149 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
150 
151 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
152 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
153 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
154 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
155 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
156 					u16 *list_offset,
157 					u16 *data_offset);
158 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
159 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
160 				u8 dev_addr, u8 *data);
161 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
162 					 u8 dev_addr, u8 *data);
163 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
164 				 u8 dev_addr, u8 data);
165 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
166 					  u8 dev_addr, u8 data);
167 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
168 				  u8 *eeprom_data);
169 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
170 				   u8 *sff8472_data);
171 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
172 				   u8 eeprom_data);
173 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
174 					u16 *val, bool lock);
175 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
176 					 u16 val, bool lock);
177 #endif /* _IXGBE_PHY_H_ */
178