1 /*******************************************************************************
2 
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2016 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _IXGBE_PHY_H_
30 #define _IXGBE_PHY_H_
31 
32 #include "ixgbe_type.h"
33 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
34 #define IXGBE_I2C_EEPROM_DEV_ADDR2   0xA2
35 
36 /* EEPROM byte offsets */
37 #define IXGBE_SFF_IDENTIFIER		0x0
38 #define IXGBE_SFF_IDENTIFIER_SFP	0x3
39 #define IXGBE_SFF_VENDOR_OUI_BYTE0	0x25
40 #define IXGBE_SFF_VENDOR_OUI_BYTE1	0x26
41 #define IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
42 #define IXGBE_SFF_1GBE_COMP_CODES	0x6
43 #define IXGBE_SFF_10GBE_COMP_CODES	0x3
44 #define IXGBE_SFF_CABLE_TECHNOLOGY	0x8
45 #define IXGBE_SFF_CABLE_SPEC_COMP	0x3C
46 #define IXGBE_SFF_SFF_8472_SWAP		0x5C
47 #define IXGBE_SFF_SFF_8472_COMP		0x5E
48 #define IXGBE_SFF_SFF_8472_OSCB		0x6E
49 #define IXGBE_SFF_SFF_8472_ESCB		0x76
50 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS	0xD
51 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0	0xA5
52 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1	0xA6
53 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2	0xA7
54 #define IXGBE_SFF_QSFP_CONNECTOR	0x82
55 #define IXGBE_SFF_QSFP_10GBE_COMP	0x83
56 #define IXGBE_SFF_QSFP_1GBE_COMP	0x86
57 #define IXGBE_SFF_QSFP_CABLE_LENGTH	0x92
58 #define IXGBE_SFF_QSFP_DEVICE_TECH	0x93
59 
60 /* Bitmasks */
61 #define IXGBE_SFF_DA_PASSIVE_CABLE		0x4
62 #define IXGBE_SFF_DA_ACTIVE_CABLE		0x8
63 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING	0x4
64 #define IXGBE_SFF_1GBASESX_CAPABLE		0x1
65 #define IXGBE_SFF_1GBASELX_CAPABLE		0x2
66 #define IXGBE_SFF_1GBASET_CAPABLE		0x8
67 #define IXGBE_SFF_10GBASESR_CAPABLE		0x10
68 #define IXGBE_SFF_10GBASELR_CAPABLE		0x20
69 #define IXGBE_SFF_SOFT_RS_SELECT_MASK		0x8
70 #define IXGBE_SFF_SOFT_RS_SELECT_10G		0x8
71 #define IXGBE_SFF_SOFT_RS_SELECT_1G		0x0
72 #define IXGBE_SFF_ADDRESSING_MODE		0x4
73 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE		0x1
74 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE		0x8
75 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE	0x23
76 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL	0x0
77 #define IXGBE_I2C_EEPROM_READ_MASK		0x100
78 #define IXGBE_I2C_EEPROM_STATUS_MASK		0x3
79 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
80 #define IXGBE_I2C_EEPROM_STATUS_PASS		0x1
81 #define IXGBE_I2C_EEPROM_STATUS_FAIL		0x2
82 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS	0x3
83 #define IXGBE_CS4227				0xBE    /* CS4227 address */
84 #define IXGBE_CS4227_GLOBAL_ID_LSB		0
85 #define IXGBE_CS4227_GLOBAL_ID_MSB		1
86 #define IXGBE_CS4227_SCRATCH			2
87 #define IXGBE_CS4227_EFUSE_PDF_SKU		0x19F
88 #define IXGBE_CS4223_SKU_ID			0x0010  /* Quad port */
89 #define IXGBE_CS4227_SKU_ID			0x0014  /* Dual port */
90 #define IXGBE_CS4227_RESET_PENDING		0x1357
91 #define IXGBE_CS4227_RESET_COMPLETE		0x5AA5
92 #define IXGBE_CS4227_RETRIES			15
93 #define IXGBE_CS4227_EFUSE_STATUS		0x0181
94 #define IXGBE_CS4227_LINE_SPARE22_MSB		0x12AD	/* Reg to set speed */
95 #define IXGBE_CS4227_LINE_SPARE24_LSB		0x12B0	/* Reg to set EDC */
96 #define IXGBE_CS4227_HOST_SPARE22_MSB		0x1AAD	/* Reg to set speed */
97 #define IXGBE_CS4227_HOST_SPARE24_LSB		0x1AB0	/* Reg to program EDC */
98 #define IXGBE_CS4227_EEPROM_STATUS		0x5001
99 #define IXGBE_CS4227_EEPROM_LOAD_OK		0x0001
100 #define IXGBE_CS4227_SPEED_1G			0x8000
101 #define IXGBE_CS4227_SPEED_10G			0
102 #define IXGBE_CS4227_EDC_MODE_CX1		0x0002
103 #define IXGBE_CS4227_EDC_MODE_SR		0x0004
104 #define IXGBE_CS4227_EDC_MODE_DIAG		0x0008
105 #define IXGBE_CS4227_RESET_HOLD			500	/* microseconds */
106 #define IXGBE_CS4227_RESET_DELAY		500	/* milliseconds */
107 #define IXGBE_CS4227_CHECK_DELAY		30	/* milliseconds */
108 #define IXGBE_PE				0xE0	/* Port expander addr */
109 #define IXGBE_PE_OUTPUT				1	/* Output reg offset */
110 #define IXGBE_PE_CONFIG				3	/* Config reg offset */
111 #define IXGBE_PE_BIT1				BIT(1)
112 
113 /* Flow control defines */
114 #define IXGBE_TAF_SYM_PAUSE                  0x400
115 #define IXGBE_TAF_ASM_PAUSE                  0x800
116 
117 /* Bit-shift macros */
118 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
119 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
120 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
121 
122 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
123 #define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
124 #define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
125 #define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
126 #define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
127 
128 /* I2C SDA and SCL timing parameters for standard mode */
129 #define IXGBE_I2C_T_HD_STA  4
130 #define IXGBE_I2C_T_LOW     5
131 #define IXGBE_I2C_T_HIGH    4
132 #define IXGBE_I2C_T_SU_STA  5
133 #define IXGBE_I2C_T_HD_DATA 5
134 #define IXGBE_I2C_T_SU_DATA 1
135 #define IXGBE_I2C_T_RISE    1
136 #define IXGBE_I2C_T_FALL    1
137 #define IXGBE_I2C_T_SU_STO  4
138 #define IXGBE_I2C_T_BUF     5
139 
140 #define IXGBE_SFP_DETECT_RETRIES	2
141 
142 #define IXGBE_TN_LASI_STATUS_REG        0x9005
143 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
144 
145 /* SFP+ SFF-8472 Compliance code */
146 #define IXGBE_SFF_SFF_8472_UNSUP      0x00
147 
148 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
149 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
150 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
151 			       u32 device_type, u16 *phy_data);
152 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
153 				u32 device_type, u16 phy_data);
154 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
155 			   u32 device_type, u16 *phy_data);
156 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
157 			    u32 device_type, u16 phy_data);
158 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
159 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
160 				       ixgbe_link_speed speed,
161 				       bool autoneg_wait_to_complete);
162 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
163 					       ixgbe_link_speed *speed,
164 					       bool *autoneg);
165 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
166 
167 /* PHY specific */
168 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
169 			     ixgbe_link_speed *speed,
170 			     bool *link_up);
171 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
172 
173 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
174 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
175 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
176 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
177 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
178 					u16 *list_offset,
179 					u16 *data_offset);
180 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
181 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
182 				u8 dev_addr, u8 *data);
183 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
184 					 u8 dev_addr, u8 *data);
185 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
186 				 u8 dev_addr, u8 data);
187 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
188 					  u8 dev_addr, u8 data);
189 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
190 				  u8 *eeprom_data);
191 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
192 				   u8 *sff8472_data);
193 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
194 				   u8 eeprom_data);
195 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
196 					u16 *val, bool lock);
197 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
198 					 u16 val, bool lock);
199 #endif /* _IXGBE_PHY_H_ */
200