1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/pci.h> 5 #include <linux/delay.h> 6 #include <linux/iopoll.h> 7 #include <linux/sched.h> 8 9 #include "ixgbe.h" 10 #include "ixgbe_phy.h" 11 12 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 14 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 15 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 16 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 17 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 18 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 21 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 24 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 25 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 26 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 27 28 /** 29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 30 * @hw: pointer to the hardware structure 31 * @byte: byte to send 32 * 33 * Returns an error code on error. 34 **/ 35 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 36 { 37 s32 status; 38 39 status = ixgbe_clock_out_i2c_byte(hw, byte); 40 if (status) 41 return status; 42 return ixgbe_get_i2c_ack(hw); 43 } 44 45 /** 46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 47 * @hw: pointer to the hardware structure 48 * @byte: pointer to a u8 to receive the byte 49 * 50 * Returns an error code on error. 51 **/ 52 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 53 { 54 s32 status; 55 56 status = ixgbe_clock_in_i2c_byte(hw, byte); 57 if (status) 58 return status; 59 /* ACK */ 60 return ixgbe_clock_out_i2c_bit(hw, false); 61 } 62 63 /** 64 * ixgbe_ones_comp_byte_add - Perform one's complement addition 65 * @add1: addend 1 66 * @add2: addend 2 67 * 68 * Returns one's complement 8-bit sum. 69 **/ 70 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 71 { 72 u16 sum = add1 + add2; 73 74 sum = (sum & 0xFF) + (sum >> 8); 75 return sum & 0xFF; 76 } 77 78 /** 79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 80 * @hw: pointer to the hardware structure 81 * @addr: I2C bus address to read from 82 * @reg: I2C device register to read from 83 * @val: pointer to location to receive read value 84 * @lock: true if to take and release semaphore 85 * 86 * Returns an error code on error. 87 */ 88 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 89 u16 reg, u16 *val, bool lock) 90 { 91 u32 swfw_mask = hw->phy.phy_semaphore_mask; 92 int max_retry = 3; 93 int retry = 0; 94 u8 csum_byte; 95 u8 high_bits; 96 u8 low_bits; 97 u8 reg_high; 98 u8 csum; 99 100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 102 csum = ~csum; 103 do { 104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 105 return IXGBE_ERR_SWFW_SYNC; 106 ixgbe_i2c_start(hw); 107 /* Device Address and write indication */ 108 if (ixgbe_out_i2c_byte_ack(hw, addr)) 109 goto fail; 110 /* Write bits 14:8 */ 111 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 112 goto fail; 113 /* Write bits 7:0 */ 114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 115 goto fail; 116 /* Write csum */ 117 if (ixgbe_out_i2c_byte_ack(hw, csum)) 118 goto fail; 119 /* Re-start condition */ 120 ixgbe_i2c_start(hw); 121 /* Device Address and read indication */ 122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 123 goto fail; 124 /* Get upper bits */ 125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 126 goto fail; 127 /* Get low bits */ 128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 129 goto fail; 130 /* Get csum */ 131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 132 goto fail; 133 /* NACK */ 134 if (ixgbe_clock_out_i2c_bit(hw, false)) 135 goto fail; 136 ixgbe_i2c_stop(hw); 137 if (lock) 138 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 139 *val = (high_bits << 8) | low_bits; 140 return 0; 141 142 fail: 143 ixgbe_i2c_bus_clear(hw); 144 if (lock) 145 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 146 retry++; 147 if (retry < max_retry) 148 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); 149 else 150 hw_dbg(hw, "I2C byte read combined error.\n"); 151 } while (retry < max_retry); 152 153 return IXGBE_ERR_I2C; 154 } 155 156 /** 157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 158 * @hw: pointer to the hardware structure 159 * @addr: I2C bus address to write to 160 * @reg: I2C device register to write to 161 * @val: value to write 162 * @lock: true if to take and release semaphore 163 * 164 * Returns an error code on error. 165 */ 166 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 167 u16 reg, u16 val, bool lock) 168 { 169 u32 swfw_mask = hw->phy.phy_semaphore_mask; 170 int max_retry = 1; 171 int retry = 0; 172 u8 reg_high; 173 u8 csum; 174 175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 179 csum = ~csum; 180 do { 181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 182 return IXGBE_ERR_SWFW_SYNC; 183 ixgbe_i2c_start(hw); 184 /* Device Address and write indication */ 185 if (ixgbe_out_i2c_byte_ack(hw, addr)) 186 goto fail; 187 /* Write bits 14:8 */ 188 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 189 goto fail; 190 /* Write bits 7:0 */ 191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 192 goto fail; 193 /* Write data 15:8 */ 194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 195 goto fail; 196 /* Write data 7:0 */ 197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 198 goto fail; 199 /* Write csum */ 200 if (ixgbe_out_i2c_byte_ack(hw, csum)) 201 goto fail; 202 ixgbe_i2c_stop(hw); 203 if (lock) 204 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 205 return 0; 206 207 fail: 208 ixgbe_i2c_bus_clear(hw); 209 if (lock) 210 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 211 retry++; 212 if (retry < max_retry) 213 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); 214 else 215 hw_dbg(hw, "I2C byte write combined error.\n"); 216 } while (retry < max_retry); 217 218 return IXGBE_ERR_I2C; 219 } 220 221 /** 222 * ixgbe_probe_phy - Probe a single address for a PHY 223 * @hw: pointer to hardware structure 224 * @phy_addr: PHY address to probe 225 * 226 * Returns true if PHY found 227 **/ 228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 229 { 230 u16 ext_ability = 0; 231 232 hw->phy.mdio.prtad = phy_addr; 233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0) 234 return false; 235 236 if (ixgbe_get_phy_id(hw)) 237 return false; 238 239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 240 241 if (hw->phy.type == ixgbe_phy_unknown) { 242 hw->phy.ops.read_reg(hw, 243 MDIO_PMA_EXTABLE, 244 MDIO_MMD_PMAPMD, 245 &ext_ability); 246 if (ext_ability & 247 (MDIO_PMA_EXTABLE_10GBT | 248 MDIO_PMA_EXTABLE_1000BT)) 249 hw->phy.type = ixgbe_phy_cu_unknown; 250 else 251 hw->phy.type = ixgbe_phy_generic; 252 } 253 254 return true; 255 } 256 257 /** 258 * ixgbe_identify_phy_generic - Get physical layer module 259 * @hw: pointer to hardware structure 260 * 261 * Determines the physical layer module found on the current adapter. 262 **/ 263 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 264 { 265 u32 phy_addr; 266 u32 status = IXGBE_ERR_PHY_ADDR_INVALID; 267 268 if (!hw->phy.phy_semaphore_mask) { 269 if (hw->bus.lan_id) 270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 271 else 272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 273 } 274 275 if (hw->phy.type != ixgbe_phy_unknown) 276 return 0; 277 278 if (hw->phy.nw_mng_if_sel) { 279 phy_addr = (hw->phy.nw_mng_if_sel & 280 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 281 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 282 if (ixgbe_probe_phy(hw, phy_addr)) 283 return 0; 284 else 285 return IXGBE_ERR_PHY_ADDR_INVALID; 286 } 287 288 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 289 if (ixgbe_probe_phy(hw, phy_addr)) { 290 status = 0; 291 break; 292 } 293 } 294 295 /* Certain media types do not have a phy so an address will not 296 * be found and the code will take this path. Caller has to 297 * decide if it is an error or not. 298 */ 299 if (status) 300 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 301 302 return status; 303 } 304 305 /** 306 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 307 * @hw: pointer to the hardware structure 308 * 309 * This function checks the MMNGC.MNG_VETO bit to see if there are 310 * any constraints on link from manageability. For MAC's that don't 311 * have this bit just return false since the link can not be blocked 312 * via this method. 313 **/ 314 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 315 { 316 u32 mmngc; 317 318 /* If we don't have this bit, it can't be blocking */ 319 if (hw->mac.type == ixgbe_mac_82598EB) 320 return false; 321 322 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 323 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 324 hw_dbg(hw, "MNG_VETO bit detected.\n"); 325 return true; 326 } 327 328 return false; 329 } 330 331 /** 332 * ixgbe_get_phy_id - Get the phy type 333 * @hw: pointer to hardware structure 334 * 335 **/ 336 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 337 { 338 s32 status; 339 u16 phy_id_high = 0; 340 u16 phy_id_low = 0; 341 342 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 343 &phy_id_high); 344 345 if (!status) { 346 hw->phy.id = (u32)(phy_id_high << 16); 347 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 348 &phy_id_low); 349 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 350 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 351 } 352 return status; 353 } 354 355 /** 356 * ixgbe_get_phy_type_from_id - Get the phy type 357 * @phy_id: hardware phy id 358 * 359 **/ 360 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 361 { 362 enum ixgbe_phy_type phy_type; 363 364 switch (phy_id) { 365 case TN1010_PHY_ID: 366 phy_type = ixgbe_phy_tn; 367 break; 368 case X550_PHY_ID2: 369 case X550_PHY_ID3: 370 case X540_PHY_ID: 371 phy_type = ixgbe_phy_aq; 372 break; 373 case QT2022_PHY_ID: 374 phy_type = ixgbe_phy_qt; 375 break; 376 case ATH_PHY_ID: 377 phy_type = ixgbe_phy_nl; 378 break; 379 case X557_PHY_ID: 380 case X557_PHY_ID2: 381 phy_type = ixgbe_phy_x550em_ext_t; 382 break; 383 default: 384 phy_type = ixgbe_phy_unknown; 385 break; 386 } 387 388 return phy_type; 389 } 390 391 /** 392 * ixgbe_reset_phy_generic - Performs a PHY reset 393 * @hw: pointer to hardware structure 394 **/ 395 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 396 { 397 u32 i; 398 u16 ctrl = 0; 399 s32 status = 0; 400 401 if (hw->phy.type == ixgbe_phy_unknown) 402 status = ixgbe_identify_phy_generic(hw); 403 404 if (status != 0 || hw->phy.type == ixgbe_phy_none) 405 return status; 406 407 /* Don't reset PHY if it's shut down due to overtemp. */ 408 if (!hw->phy.reset_if_overtemp && 409 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 410 return 0; 411 412 /* Blocked by MNG FW so bail */ 413 if (ixgbe_check_reset_blocked(hw)) 414 return 0; 415 416 /* 417 * Perform soft PHY reset to the PHY_XS. 418 * This will cause a soft reset to the PHY 419 */ 420 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 421 MDIO_MMD_PHYXS, 422 MDIO_CTRL1_RESET); 423 424 /* 425 * Poll for reset bit to self-clear indicating reset is complete. 426 * Some PHYs could take up to 3 seconds to complete and need about 427 * 1.7 usec delay after the reset is complete. 428 */ 429 for (i = 0; i < 30; i++) { 430 msleep(100); 431 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 432 status = hw->phy.ops.read_reg(hw, 433 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 434 MDIO_MMD_PMAPMD, &ctrl); 435 if (status) 436 return status; 437 438 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 439 udelay(2); 440 break; 441 } 442 } else { 443 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, 444 MDIO_MMD_PHYXS, &ctrl); 445 if (status) 446 return status; 447 448 if (!(ctrl & MDIO_CTRL1_RESET)) { 449 udelay(2); 450 break; 451 } 452 } 453 } 454 455 if (ctrl & MDIO_CTRL1_RESET) { 456 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 457 return IXGBE_ERR_RESET_FAILED; 458 } 459 460 return 0; 461 } 462 463 /** 464 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 465 * the SWFW lock 466 * @hw: pointer to hardware structure 467 * @reg_addr: 32 bit address of PHY register to read 468 * @device_type: 5 bit device type 469 * @phy_data: Pointer to read data from PHY register 470 **/ 471 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 472 u16 *phy_data) 473 { 474 u32 i, data, command; 475 476 /* Setup and write the address cycle command */ 477 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 478 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 479 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 480 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 481 482 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 483 484 /* Check every 10 usec to see if the address cycle completed. 485 * The MDI Command bit will clear when the operation is 486 * complete 487 */ 488 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 489 udelay(10); 490 491 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 492 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 493 break; 494 } 495 496 497 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 498 hw_dbg(hw, "PHY address command did not complete.\n"); 499 return IXGBE_ERR_PHY; 500 } 501 502 /* Address cycle complete, setup and write the read 503 * command 504 */ 505 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 506 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 507 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 508 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 509 510 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 511 512 /* Check every 10 usec to see if the address cycle 513 * completed. The MDI Command bit will clear when the 514 * operation is complete 515 */ 516 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 517 udelay(10); 518 519 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 520 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 521 break; 522 } 523 524 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 525 hw_dbg(hw, "PHY read command didn't complete\n"); 526 return IXGBE_ERR_PHY; 527 } 528 529 /* Read operation is complete. Get the data 530 * from MSRWD 531 */ 532 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 533 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 534 *phy_data = (u16)(data); 535 536 return 0; 537 } 538 539 /** 540 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 541 * using the SWFW lock - this function is needed in most cases 542 * @hw: pointer to hardware structure 543 * @reg_addr: 32 bit address of PHY register to read 544 * @device_type: 5 bit device type 545 * @phy_data: Pointer to read data from PHY register 546 **/ 547 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 548 u32 device_type, u16 *phy_data) 549 { 550 s32 status; 551 u32 gssr = hw->phy.phy_semaphore_mask; 552 553 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 554 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 555 phy_data); 556 hw->mac.ops.release_swfw_sync(hw, gssr); 557 } else { 558 return IXGBE_ERR_SWFW_SYNC; 559 } 560 561 return status; 562 } 563 564 /** 565 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 566 * without SWFW lock 567 * @hw: pointer to hardware structure 568 * @reg_addr: 32 bit PHY register to write 569 * @device_type: 5 bit device type 570 * @phy_data: Data to write to the PHY register 571 **/ 572 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 573 u32 device_type, u16 phy_data) 574 { 575 u32 i, command; 576 577 /* Put the data in the MDI single read and write data register*/ 578 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 579 580 /* Setup and write the address cycle command */ 581 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 582 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 583 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 584 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 585 586 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 587 588 /* 589 * Check every 10 usec to see if the address cycle completed. 590 * The MDI Command bit will clear when the operation is 591 * complete 592 */ 593 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 594 udelay(10); 595 596 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 597 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 598 break; 599 } 600 601 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 602 hw_dbg(hw, "PHY address cmd didn't complete\n"); 603 return IXGBE_ERR_PHY; 604 } 605 606 /* 607 * Address cycle complete, setup and write the write 608 * command 609 */ 610 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 611 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 612 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 613 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 614 615 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 616 617 /* Check every 10 usec to see if the address cycle 618 * completed. The MDI Command bit will clear when the 619 * operation is complete 620 */ 621 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 622 udelay(10); 623 624 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 625 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 626 break; 627 } 628 629 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 630 hw_dbg(hw, "PHY write cmd didn't complete\n"); 631 return IXGBE_ERR_PHY; 632 } 633 634 return 0; 635 } 636 637 /** 638 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 639 * using SWFW lock- this function is needed in most cases 640 * @hw: pointer to hardware structure 641 * @reg_addr: 32 bit PHY register to write 642 * @device_type: 5 bit device type 643 * @phy_data: Data to write to the PHY register 644 **/ 645 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 646 u32 device_type, u16 phy_data) 647 { 648 s32 status; 649 u32 gssr = hw->phy.phy_semaphore_mask; 650 651 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 652 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 653 phy_data); 654 hw->mac.ops.release_swfw_sync(hw, gssr); 655 } else { 656 return IXGBE_ERR_SWFW_SYNC; 657 } 658 659 return status; 660 } 661 662 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr) 663 664 /** 665 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout 666 * @hw: pointer to hardware structure 667 * @cmd: command register value to write 668 **/ 669 static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd) 670 { 671 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd); 672 673 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd, 674 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10, 675 10 * IXGBE_MDIO_COMMAND_TIMEOUT); 676 } 677 678 /** 679 * ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags 680 * @hw: pointer to hardware structure 681 * @addr: address 682 * @regnum: register number 683 * @gssr: semaphore flags to acquire 684 **/ 685 static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr, 686 int regnum, u32 gssr) 687 { 688 u32 hwaddr, cmd; 689 s32 data; 690 691 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 692 return -EBUSY; 693 694 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT; 695 if (regnum & MII_ADDR_C45) { 696 hwaddr |= regnum & GENMASK(21, 0); 697 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND; 698 } else { 699 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT; 700 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | 701 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND; 702 } 703 704 data = ixgbe_msca_cmd(hw, cmd); 705 if (data < 0) 706 goto mii_bus_read_done; 707 708 /* For a clause 45 access the address cycle just completed, we still 709 * need to do the read command, otherwise just get the data 710 */ 711 if (!(regnum & MII_ADDR_C45)) 712 goto do_mii_bus_read; 713 714 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND; 715 data = ixgbe_msca_cmd(hw, cmd); 716 if (data < 0) 717 goto mii_bus_read_done; 718 719 do_mii_bus_read: 720 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 721 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0); 722 723 mii_bus_read_done: 724 hw->mac.ops.release_swfw_sync(hw, gssr); 725 return data; 726 } 727 728 /** 729 * ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags 730 * @hw: pointer to hardware structure 731 * @addr: address 732 * @regnum: register number 733 * @val: value to write 734 * @gssr: semaphore flags to acquire 735 **/ 736 static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr, 737 int regnum, u16 val, u32 gssr) 738 { 739 u32 hwaddr, cmd; 740 s32 err; 741 742 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 743 return -EBUSY; 744 745 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val); 746 747 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT; 748 if (regnum & MII_ADDR_C45) { 749 hwaddr |= regnum & GENMASK(21, 0); 750 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND; 751 } else { 752 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT; 753 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | 754 IXGBE_MSCA_MDI_COMMAND; 755 } 756 757 /* For clause 45 this is an address cycle, for clause 22 this is the 758 * entire transaction 759 */ 760 err = ixgbe_msca_cmd(hw, cmd); 761 if (err < 0 || !(regnum & MII_ADDR_C45)) 762 goto mii_bus_write_done; 763 764 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND; 765 err = ixgbe_msca_cmd(hw, cmd); 766 767 mii_bus_write_done: 768 hw->mac.ops.release_swfw_sync(hw, gssr); 769 return err; 770 } 771 772 /** 773 * ixgbe_mii_bus_read - Read a clause 22/45 register 774 * @hw: pointer to hardware structure 775 * @addr: address 776 * @regnum: register number 777 **/ 778 static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum) 779 { 780 struct ixgbe_adapter *adapter = bus->priv; 781 struct ixgbe_hw *hw = &adapter->hw; 782 u32 gssr = hw->phy.phy_semaphore_mask; 783 784 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr); 785 } 786 787 /** 788 * ixgbe_mii_bus_write - Write a clause 22/45 register 789 * @hw: pointer to hardware structure 790 * @addr: address 791 * @regnum: register number 792 * @val: value to write 793 **/ 794 static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum, 795 u16 val) 796 { 797 struct ixgbe_adapter *adapter = bus->priv; 798 struct ixgbe_hw *hw = &adapter->hw; 799 u32 gssr = hw->phy.phy_semaphore_mask; 800 801 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr); 802 } 803 804 /** 805 * ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a 806 * @hw: pointer to hardware structure 807 * @addr: address 808 * @regnum: register number 809 **/ 810 static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr, 811 int regnum) 812 { 813 struct ixgbe_adapter *adapter = bus->priv; 814 struct ixgbe_hw *hw = &adapter->hw; 815 u32 gssr = hw->phy.phy_semaphore_mask; 816 817 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM; 818 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr); 819 } 820 821 /** 822 * ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a 823 * @hw: pointer to hardware structure 824 * @addr: address 825 * @regnum: register number 826 * @val: value to write 827 **/ 828 static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr, 829 int regnum, u16 val) 830 { 831 struct ixgbe_adapter *adapter = bus->priv; 832 struct ixgbe_hw *hw = &adapter->hw; 833 u32 gssr = hw->phy.phy_semaphore_mask; 834 835 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM; 836 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr); 837 } 838 839 /** 840 * ixgbe_get_first_secondary_devfn - get first device downstream of root port 841 * @devfn: PCI_DEVFN of root port on domain 0, bus 0 842 * 843 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root 844 * on domain 0, bus 0, devfn = 'devfn' 845 **/ 846 static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn) 847 { 848 struct pci_dev *rp_pdev; 849 int bus; 850 851 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn); 852 if (rp_pdev && rp_pdev->subordinate) { 853 bus = rp_pdev->subordinate->number; 854 return pci_get_domain_bus_and_slot(0, bus, 0); 855 } 856 857 return NULL; 858 } 859 860 /** 861 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function? 862 * @hw: pointer to hardware structure 863 * 864 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in 865 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a, 866 * but we only want to register one MDIO bus. 867 **/ 868 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw) 869 { 870 struct ixgbe_adapter *adapter = hw->back; 871 struct pci_dev *pdev = adapter->pdev; 872 struct pci_dev *func0_pdev; 873 874 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices 875 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0 876 * It's not valid for function 0 to be disabled and function 1 is up, 877 * so the lowest numbered ixgbe dev will be device 0 function 0 on one 878 * of those two root ports 879 */ 880 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0)); 881 if (func0_pdev) { 882 if (func0_pdev == pdev) 883 return true; 884 else 885 return false; 886 } 887 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0)); 888 if (func0_pdev == pdev) 889 return true; 890 891 return false; 892 } 893 894 /** 895 * ixgbe_mii_bus_init - mii_bus structure setup 896 * @hw: pointer to hardware structure 897 * 898 * Returns 0 on success, negative on failure 899 * 900 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter 901 **/ 902 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw) 903 { 904 struct ixgbe_adapter *adapter = hw->back; 905 struct pci_dev *pdev = adapter->pdev; 906 struct device *dev = &adapter->netdev->dev; 907 struct mii_bus *bus; 908 909 adapter->mii_bus = devm_mdiobus_alloc(dev); 910 if (!adapter->mii_bus) 911 return -ENOMEM; 912 913 bus = adapter->mii_bus; 914 915 switch (hw->device_id) { 916 /* C3000 SoCs */ 917 case IXGBE_DEV_ID_X550EM_A_KR: 918 case IXGBE_DEV_ID_X550EM_A_KR_L: 919 case IXGBE_DEV_ID_X550EM_A_SFP_N: 920 case IXGBE_DEV_ID_X550EM_A_SGMII: 921 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 922 case IXGBE_DEV_ID_X550EM_A_10G_T: 923 case IXGBE_DEV_ID_X550EM_A_SFP: 924 case IXGBE_DEV_ID_X550EM_A_1G_T: 925 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 926 if (!ixgbe_x550em_a_has_mii(hw)) 927 goto ixgbe_no_mii_bus; 928 bus->read = &ixgbe_x550em_a_mii_bus_read; 929 bus->write = &ixgbe_x550em_a_mii_bus_write; 930 break; 931 default: 932 bus->read = &ixgbe_mii_bus_read; 933 bus->write = &ixgbe_mii_bus_write; 934 break; 935 } 936 937 /* Use the position of the device in the PCI hierarchy as the id */ 938 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name, 939 pci_name(pdev)); 940 941 bus->name = "ixgbe-mdio"; 942 bus->priv = adapter; 943 bus->parent = dev; 944 bus->phy_mask = GENMASK(31, 0); 945 946 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22 947 * unfortunately that causes some clause 22 frames to be sent with 948 * clause 45 addressing. We don't want that. 949 */ 950 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22; 951 952 return mdiobus_register(bus); 953 954 ixgbe_no_mii_bus: 955 devm_mdiobus_free(dev, bus); 956 adapter->mii_bus = NULL; 957 return -ENODEV; 958 } 959 960 /** 961 * ixgbe_setup_phy_link_generic - Set and restart autoneg 962 * @hw: pointer to hardware structure 963 * 964 * Restart autonegotiation and PHY and waits for completion. 965 **/ 966 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 967 { 968 s32 status = 0; 969 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 970 bool autoneg = false; 971 ixgbe_link_speed speed; 972 973 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 974 975 /* Set or unset auto-negotiation 10G advertisement */ 976 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg); 977 978 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 979 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 980 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 981 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 982 983 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg); 984 985 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 986 MDIO_MMD_AN, &autoneg_reg); 987 988 if (hw->mac.type == ixgbe_mac_X550) { 989 /* Set or unset auto-negotiation 5G advertisement */ 990 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 991 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 992 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 993 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 994 995 /* Set or unset auto-negotiation 2.5G advertisement */ 996 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 997 if ((hw->phy.autoneg_advertised & 998 IXGBE_LINK_SPEED_2_5GB_FULL) && 999 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 1000 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 1001 } 1002 1003 /* Set or unset auto-negotiation 1G advertisement */ 1004 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 1005 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 1006 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 1007 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 1008 1009 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 1010 MDIO_MMD_AN, autoneg_reg); 1011 1012 /* Set or unset auto-negotiation 100M advertisement */ 1013 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); 1014 1015 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF); 1016 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 1017 (speed & IXGBE_LINK_SPEED_100_FULL)) 1018 autoneg_reg |= ADVERTISE_100FULL; 1019 1020 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); 1021 1022 /* Blocked by MNG FW so don't reset PHY */ 1023 if (ixgbe_check_reset_blocked(hw)) 1024 return 0; 1025 1026 /* Restart PHY autonegotiation and wait for completion */ 1027 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 1028 MDIO_MMD_AN, &autoneg_reg); 1029 1030 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 1031 1032 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 1033 MDIO_MMD_AN, autoneg_reg); 1034 1035 return status; 1036 } 1037 1038 /** 1039 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 1040 * @hw: pointer to hardware structure 1041 * @speed: new link speed 1042 * @autoneg_wait_to_complete: unused 1043 **/ 1044 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 1045 ixgbe_link_speed speed, 1046 bool autoneg_wait_to_complete) 1047 { 1048 /* Clear autoneg_advertised and set new values based on input link 1049 * speed. 1050 */ 1051 hw->phy.autoneg_advertised = 0; 1052 1053 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1054 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 1055 1056 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 1057 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 1058 1059 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 1060 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 1061 1062 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1063 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 1064 1065 if (speed & IXGBE_LINK_SPEED_100_FULL) 1066 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 1067 1068 if (speed & IXGBE_LINK_SPEED_10_FULL) 1069 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 1070 1071 /* Setup link based on the new speed settings */ 1072 if (hw->phy.ops.setup_link) 1073 hw->phy.ops.setup_link(hw); 1074 1075 return 0; 1076 } 1077 1078 /** 1079 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy 1080 * @hw: pointer to hardware structure 1081 * 1082 * Determines the supported link capabilities by reading the PHY auto 1083 * negotiation register. 1084 */ 1085 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 1086 { 1087 u16 speed_ability; 1088 s32 status; 1089 1090 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 1091 &speed_ability); 1092 if (status) 1093 return status; 1094 1095 if (speed_ability & MDIO_SPEED_10G) 1096 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 1097 if (speed_ability & MDIO_PMA_SPEED_1000) 1098 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 1099 if (speed_ability & MDIO_PMA_SPEED_100) 1100 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 1101 1102 switch (hw->mac.type) { 1103 case ixgbe_mac_X550: 1104 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 1105 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 1106 break; 1107 case ixgbe_mac_X550EM_x: 1108 case ixgbe_mac_x550em_a: 1109 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 1110 break; 1111 default: 1112 break; 1113 } 1114 1115 return 0; 1116 } 1117 1118 /** 1119 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 1120 * @hw: pointer to hardware structure 1121 * @speed: pointer to link speed 1122 * @autoneg: boolean auto-negotiation value 1123 */ 1124 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 1125 ixgbe_link_speed *speed, 1126 bool *autoneg) 1127 { 1128 s32 status = 0; 1129 1130 *autoneg = true; 1131 if (!hw->phy.speeds_supported) 1132 status = ixgbe_get_copper_speeds_supported(hw); 1133 1134 *speed = hw->phy.speeds_supported; 1135 return status; 1136 } 1137 1138 /** 1139 * ixgbe_check_phy_link_tnx - Determine link and speed status 1140 * @hw: pointer to hardware structure 1141 * @speed: link speed 1142 * @link_up: status of link 1143 * 1144 * Reads the VS1 register to determine if link is up and the current speed for 1145 * the PHY. 1146 **/ 1147 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1148 bool *link_up) 1149 { 1150 s32 status; 1151 u32 time_out; 1152 u32 max_time_out = 10; 1153 u16 phy_link = 0; 1154 u16 phy_speed = 0; 1155 u16 phy_data = 0; 1156 1157 /* Initialize speed and link to default case */ 1158 *link_up = false; 1159 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1160 1161 /* 1162 * Check current speed and link status of the PHY register. 1163 * This is a vendor specific register and may have to 1164 * be changed for other copper PHYs. 1165 */ 1166 for (time_out = 0; time_out < max_time_out; time_out++) { 1167 udelay(10); 1168 status = hw->phy.ops.read_reg(hw, 1169 MDIO_STAT1, 1170 MDIO_MMD_VEND1, 1171 &phy_data); 1172 phy_link = phy_data & 1173 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1174 phy_speed = phy_data & 1175 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1176 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1177 *link_up = true; 1178 if (phy_speed == 1179 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1180 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1181 break; 1182 } 1183 } 1184 1185 return status; 1186 } 1187 1188 /** 1189 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 1190 * @hw: pointer to hardware structure 1191 * 1192 * Restart autonegotiation and PHY and waits for completion. 1193 * This function always returns success, this is nessary since 1194 * it is called via a function pointer that could call other 1195 * functions that could return an error. 1196 **/ 1197 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1198 { 1199 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1200 bool autoneg = false; 1201 ixgbe_link_speed speed; 1202 1203 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1204 1205 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1206 /* Set or unset auto-negotiation 10G advertisement */ 1207 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 1208 MDIO_MMD_AN, 1209 &autoneg_reg); 1210 1211 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 1212 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1213 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 1214 1215 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 1216 MDIO_MMD_AN, 1217 autoneg_reg); 1218 } 1219 1220 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1221 /* Set or unset auto-negotiation 1G advertisement */ 1222 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1223 MDIO_MMD_AN, 1224 &autoneg_reg); 1225 1226 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1227 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1228 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1229 1230 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1231 MDIO_MMD_AN, 1232 autoneg_reg); 1233 } 1234 1235 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1236 /* Set or unset auto-negotiation 100M advertisement */ 1237 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 1238 MDIO_MMD_AN, 1239 &autoneg_reg); 1240 1241 autoneg_reg &= ~(ADVERTISE_100FULL | 1242 ADVERTISE_100HALF); 1243 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1244 autoneg_reg |= ADVERTISE_100FULL; 1245 1246 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 1247 MDIO_MMD_AN, 1248 autoneg_reg); 1249 } 1250 1251 /* Blocked by MNG FW so don't reset PHY */ 1252 if (ixgbe_check_reset_blocked(hw)) 1253 return 0; 1254 1255 /* Restart PHY autonegotiation and wait for completion */ 1256 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 1257 MDIO_MMD_AN, &autoneg_reg); 1258 1259 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 1260 1261 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 1262 MDIO_MMD_AN, autoneg_reg); 1263 return 0; 1264 } 1265 1266 /** 1267 * ixgbe_reset_phy_nl - Performs a PHY reset 1268 * @hw: pointer to hardware structure 1269 **/ 1270 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1271 { 1272 u16 phy_offset, control, eword, edata, block_crc; 1273 bool end_data = false; 1274 u16 list_offset, data_offset; 1275 u16 phy_data = 0; 1276 s32 ret_val; 1277 u32 i; 1278 1279 /* Blocked by MNG FW so bail */ 1280 if (ixgbe_check_reset_blocked(hw)) 1281 return 0; 1282 1283 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 1284 1285 /* reset the PHY and poll for completion */ 1286 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 1287 (phy_data | MDIO_CTRL1_RESET)); 1288 1289 for (i = 0; i < 100; i++) { 1290 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 1291 &phy_data); 1292 if ((phy_data & MDIO_CTRL1_RESET) == 0) 1293 break; 1294 usleep_range(10000, 20000); 1295 } 1296 1297 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 1298 hw_dbg(hw, "PHY reset did not complete.\n"); 1299 return IXGBE_ERR_PHY; 1300 } 1301 1302 /* Get init offsets */ 1303 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1304 &data_offset); 1305 if (ret_val) 1306 return ret_val; 1307 1308 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1309 data_offset++; 1310 while (!end_data) { 1311 /* 1312 * Read control word from PHY init contents offset 1313 */ 1314 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1315 if (ret_val) 1316 goto err_eeprom; 1317 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1318 IXGBE_CONTROL_SHIFT_NL; 1319 edata = eword & IXGBE_DATA_MASK_NL; 1320 switch (control) { 1321 case IXGBE_DELAY_NL: 1322 data_offset++; 1323 hw_dbg(hw, "DELAY: %d MS\n", edata); 1324 usleep_range(edata * 1000, edata * 2000); 1325 break; 1326 case IXGBE_DATA_NL: 1327 hw_dbg(hw, "DATA:\n"); 1328 data_offset++; 1329 ret_val = hw->eeprom.ops.read(hw, data_offset++, 1330 &phy_offset); 1331 if (ret_val) 1332 goto err_eeprom; 1333 for (i = 0; i < edata; i++) { 1334 ret_val = hw->eeprom.ops.read(hw, data_offset, 1335 &eword); 1336 if (ret_val) 1337 goto err_eeprom; 1338 hw->phy.ops.write_reg(hw, phy_offset, 1339 MDIO_MMD_PMAPMD, eword); 1340 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 1341 phy_offset); 1342 data_offset++; 1343 phy_offset++; 1344 } 1345 break; 1346 case IXGBE_CONTROL_NL: 1347 data_offset++; 1348 hw_dbg(hw, "CONTROL:\n"); 1349 if (edata == IXGBE_CONTROL_EOL_NL) { 1350 hw_dbg(hw, "EOL\n"); 1351 end_data = true; 1352 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1353 hw_dbg(hw, "SOL\n"); 1354 } else { 1355 hw_dbg(hw, "Bad control value\n"); 1356 return IXGBE_ERR_PHY; 1357 } 1358 break; 1359 default: 1360 hw_dbg(hw, "Bad control type\n"); 1361 return IXGBE_ERR_PHY; 1362 } 1363 } 1364 1365 return ret_val; 1366 1367 err_eeprom: 1368 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 1369 return IXGBE_ERR_PHY; 1370 } 1371 1372 /** 1373 * ixgbe_identify_module_generic - Identifies module type 1374 * @hw: pointer to hardware structure 1375 * 1376 * Determines HW type and calls appropriate function. 1377 **/ 1378 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1379 { 1380 switch (hw->mac.ops.get_media_type(hw)) { 1381 case ixgbe_media_type_fiber: 1382 return ixgbe_identify_sfp_module_generic(hw); 1383 case ixgbe_media_type_fiber_qsfp: 1384 return ixgbe_identify_qsfp_module_generic(hw); 1385 default: 1386 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1387 return IXGBE_ERR_SFP_NOT_PRESENT; 1388 } 1389 1390 return IXGBE_ERR_SFP_NOT_PRESENT; 1391 } 1392 1393 /** 1394 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1395 * @hw: pointer to hardware structure 1396 * 1397 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1398 **/ 1399 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1400 { 1401 struct ixgbe_adapter *adapter = hw->back; 1402 s32 status; 1403 u32 vendor_oui = 0; 1404 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1405 u8 identifier = 0; 1406 u8 comp_codes_1g = 0; 1407 u8 comp_codes_10g = 0; 1408 u8 oui_bytes[3] = {0, 0, 0}; 1409 u8 cable_tech = 0; 1410 u8 cable_spec = 0; 1411 u16 enforce_sfp = 0; 1412 1413 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1414 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1415 return IXGBE_ERR_SFP_NOT_PRESENT; 1416 } 1417 1418 /* LAN ID is needed for sfp_type determination */ 1419 hw->mac.ops.set_lan_id(hw); 1420 1421 status = hw->phy.ops.read_i2c_eeprom(hw, 1422 IXGBE_SFF_IDENTIFIER, 1423 &identifier); 1424 1425 if (status) 1426 goto err_read_i2c_eeprom; 1427 1428 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1429 hw->phy.type = ixgbe_phy_sfp_unsupported; 1430 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1431 } 1432 status = hw->phy.ops.read_i2c_eeprom(hw, 1433 IXGBE_SFF_1GBE_COMP_CODES, 1434 &comp_codes_1g); 1435 1436 if (status) 1437 goto err_read_i2c_eeprom; 1438 1439 status = hw->phy.ops.read_i2c_eeprom(hw, 1440 IXGBE_SFF_10GBE_COMP_CODES, 1441 &comp_codes_10g); 1442 1443 if (status) 1444 goto err_read_i2c_eeprom; 1445 status = hw->phy.ops.read_i2c_eeprom(hw, 1446 IXGBE_SFF_CABLE_TECHNOLOGY, 1447 &cable_tech); 1448 1449 if (status) 1450 goto err_read_i2c_eeprom; 1451 1452 /* ID Module 1453 * ========= 1454 * 0 SFP_DA_CU 1455 * 1 SFP_SR 1456 * 2 SFP_LR 1457 * 3 SFP_DA_CORE0 - 82599-specific 1458 * 4 SFP_DA_CORE1 - 82599-specific 1459 * 5 SFP_SR/LR_CORE0 - 82599-specific 1460 * 6 SFP_SR/LR_CORE1 - 82599-specific 1461 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1462 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1463 * 9 SFP_1g_cu_CORE0 - 82599-specific 1464 * 10 SFP_1g_cu_CORE1 - 82599-specific 1465 * 11 SFP_1g_sx_CORE0 - 82599-specific 1466 * 12 SFP_1g_sx_CORE1 - 82599-specific 1467 */ 1468 if (hw->mac.type == ixgbe_mac_82598EB) { 1469 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1470 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1471 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1472 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1473 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1474 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1475 else 1476 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1477 } else { 1478 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1479 if (hw->bus.lan_id == 0) 1480 hw->phy.sfp_type = 1481 ixgbe_sfp_type_da_cu_core0; 1482 else 1483 hw->phy.sfp_type = 1484 ixgbe_sfp_type_da_cu_core1; 1485 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1486 hw->phy.ops.read_i2c_eeprom( 1487 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1488 &cable_spec); 1489 if (cable_spec & 1490 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1491 if (hw->bus.lan_id == 0) 1492 hw->phy.sfp_type = 1493 ixgbe_sfp_type_da_act_lmt_core0; 1494 else 1495 hw->phy.sfp_type = 1496 ixgbe_sfp_type_da_act_lmt_core1; 1497 } else { 1498 hw->phy.sfp_type = 1499 ixgbe_sfp_type_unknown; 1500 } 1501 } else if (comp_codes_10g & 1502 (IXGBE_SFF_10GBASESR_CAPABLE | 1503 IXGBE_SFF_10GBASELR_CAPABLE)) { 1504 if (hw->bus.lan_id == 0) 1505 hw->phy.sfp_type = 1506 ixgbe_sfp_type_srlr_core0; 1507 else 1508 hw->phy.sfp_type = 1509 ixgbe_sfp_type_srlr_core1; 1510 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1511 if (hw->bus.lan_id == 0) 1512 hw->phy.sfp_type = 1513 ixgbe_sfp_type_1g_cu_core0; 1514 else 1515 hw->phy.sfp_type = 1516 ixgbe_sfp_type_1g_cu_core1; 1517 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1518 if (hw->bus.lan_id == 0) 1519 hw->phy.sfp_type = 1520 ixgbe_sfp_type_1g_sx_core0; 1521 else 1522 hw->phy.sfp_type = 1523 ixgbe_sfp_type_1g_sx_core1; 1524 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1525 if (hw->bus.lan_id == 0) 1526 hw->phy.sfp_type = 1527 ixgbe_sfp_type_1g_lx_core0; 1528 else 1529 hw->phy.sfp_type = 1530 ixgbe_sfp_type_1g_lx_core1; 1531 } else { 1532 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1533 } 1534 } 1535 1536 if (hw->phy.sfp_type != stored_sfp_type) 1537 hw->phy.sfp_setup_needed = true; 1538 1539 /* Determine if the SFP+ PHY is dual speed or not. */ 1540 hw->phy.multispeed_fiber = false; 1541 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1542 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1543 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1544 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1545 hw->phy.multispeed_fiber = true; 1546 1547 /* Determine PHY vendor */ 1548 if (hw->phy.type != ixgbe_phy_nl) { 1549 hw->phy.id = identifier; 1550 status = hw->phy.ops.read_i2c_eeprom(hw, 1551 IXGBE_SFF_VENDOR_OUI_BYTE0, 1552 &oui_bytes[0]); 1553 1554 if (status != 0) 1555 goto err_read_i2c_eeprom; 1556 1557 status = hw->phy.ops.read_i2c_eeprom(hw, 1558 IXGBE_SFF_VENDOR_OUI_BYTE1, 1559 &oui_bytes[1]); 1560 1561 if (status != 0) 1562 goto err_read_i2c_eeprom; 1563 1564 status = hw->phy.ops.read_i2c_eeprom(hw, 1565 IXGBE_SFF_VENDOR_OUI_BYTE2, 1566 &oui_bytes[2]); 1567 1568 if (status != 0) 1569 goto err_read_i2c_eeprom; 1570 1571 vendor_oui = 1572 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1573 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1574 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1575 1576 switch (vendor_oui) { 1577 case IXGBE_SFF_VENDOR_OUI_TYCO: 1578 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1579 hw->phy.type = 1580 ixgbe_phy_sfp_passive_tyco; 1581 break; 1582 case IXGBE_SFF_VENDOR_OUI_FTL: 1583 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1584 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1585 else 1586 hw->phy.type = ixgbe_phy_sfp_ftl; 1587 break; 1588 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1589 hw->phy.type = ixgbe_phy_sfp_avago; 1590 break; 1591 case IXGBE_SFF_VENDOR_OUI_INTEL: 1592 hw->phy.type = ixgbe_phy_sfp_intel; 1593 break; 1594 default: 1595 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1596 hw->phy.type = 1597 ixgbe_phy_sfp_passive_unknown; 1598 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1599 hw->phy.type = 1600 ixgbe_phy_sfp_active_unknown; 1601 else 1602 hw->phy.type = ixgbe_phy_sfp_unknown; 1603 break; 1604 } 1605 } 1606 1607 /* Allow any DA cable vendor */ 1608 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1609 IXGBE_SFF_DA_ACTIVE_CABLE)) 1610 return 0; 1611 1612 /* Verify supported 1G SFP modules */ 1613 if (comp_codes_10g == 0 && 1614 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1615 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1616 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1617 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1618 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1619 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1620 hw->phy.type = ixgbe_phy_sfp_unsupported; 1621 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1622 } 1623 1624 /* Anything else 82598-based is supported */ 1625 if (hw->mac.type == ixgbe_mac_82598EB) 1626 return 0; 1627 1628 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1629 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1630 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1631 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1632 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1633 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1634 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1635 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1636 /* Make sure we're a supported PHY type */ 1637 if (hw->phy.type == ixgbe_phy_sfp_intel) 1638 return 0; 1639 if (hw->allow_unsupported_sfp) { 1640 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1641 return 0; 1642 } 1643 hw_dbg(hw, "SFP+ module not supported\n"); 1644 hw->phy.type = ixgbe_phy_sfp_unsupported; 1645 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1646 } 1647 return 0; 1648 1649 err_read_i2c_eeprom: 1650 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1651 if (hw->phy.type != ixgbe_phy_nl) { 1652 hw->phy.id = 0; 1653 hw->phy.type = ixgbe_phy_unknown; 1654 } 1655 return IXGBE_ERR_SFP_NOT_PRESENT; 1656 } 1657 1658 /** 1659 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1660 * @hw: pointer to hardware structure 1661 * 1662 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1663 **/ 1664 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1665 { 1666 struct ixgbe_adapter *adapter = hw->back; 1667 s32 status; 1668 u32 vendor_oui = 0; 1669 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1670 u8 identifier = 0; 1671 u8 comp_codes_1g = 0; 1672 u8 comp_codes_10g = 0; 1673 u8 oui_bytes[3] = {0, 0, 0}; 1674 u16 enforce_sfp = 0; 1675 u8 connector = 0; 1676 u8 cable_length = 0; 1677 u8 device_tech = 0; 1678 bool active_cable = false; 1679 1680 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1681 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1682 return IXGBE_ERR_SFP_NOT_PRESENT; 1683 } 1684 1685 /* LAN ID is needed for sfp_type determination */ 1686 hw->mac.ops.set_lan_id(hw); 1687 1688 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1689 &identifier); 1690 1691 if (status != 0) 1692 goto err_read_i2c_eeprom; 1693 1694 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1695 hw->phy.type = ixgbe_phy_sfp_unsupported; 1696 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1697 } 1698 1699 hw->phy.id = identifier; 1700 1701 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1702 &comp_codes_10g); 1703 1704 if (status != 0) 1705 goto err_read_i2c_eeprom; 1706 1707 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1708 &comp_codes_1g); 1709 1710 if (status != 0) 1711 goto err_read_i2c_eeprom; 1712 1713 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1714 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1715 if (hw->bus.lan_id == 0) 1716 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1717 else 1718 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1719 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1720 IXGBE_SFF_10GBASELR_CAPABLE)) { 1721 if (hw->bus.lan_id == 0) 1722 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1723 else 1724 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1725 } else { 1726 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1727 active_cable = true; 1728 1729 if (!active_cable) { 1730 /* check for active DA cables that pre-date 1731 * SFF-8436 v3.6 1732 */ 1733 hw->phy.ops.read_i2c_eeprom(hw, 1734 IXGBE_SFF_QSFP_CONNECTOR, 1735 &connector); 1736 1737 hw->phy.ops.read_i2c_eeprom(hw, 1738 IXGBE_SFF_QSFP_CABLE_LENGTH, 1739 &cable_length); 1740 1741 hw->phy.ops.read_i2c_eeprom(hw, 1742 IXGBE_SFF_QSFP_DEVICE_TECH, 1743 &device_tech); 1744 1745 if ((connector == 1746 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1747 (cable_length > 0) && 1748 ((device_tech >> 4) == 1749 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1750 active_cable = true; 1751 } 1752 1753 if (active_cable) { 1754 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1755 if (hw->bus.lan_id == 0) 1756 hw->phy.sfp_type = 1757 ixgbe_sfp_type_da_act_lmt_core0; 1758 else 1759 hw->phy.sfp_type = 1760 ixgbe_sfp_type_da_act_lmt_core1; 1761 } else { 1762 /* unsupported module type */ 1763 hw->phy.type = ixgbe_phy_sfp_unsupported; 1764 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1765 } 1766 } 1767 1768 if (hw->phy.sfp_type != stored_sfp_type) 1769 hw->phy.sfp_setup_needed = true; 1770 1771 /* Determine if the QSFP+ PHY is dual speed or not. */ 1772 hw->phy.multispeed_fiber = false; 1773 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1774 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1775 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1776 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1777 hw->phy.multispeed_fiber = true; 1778 1779 /* Determine PHY vendor for optical modules */ 1780 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1781 IXGBE_SFF_10GBASELR_CAPABLE)) { 1782 status = hw->phy.ops.read_i2c_eeprom(hw, 1783 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1784 &oui_bytes[0]); 1785 1786 if (status != 0) 1787 goto err_read_i2c_eeprom; 1788 1789 status = hw->phy.ops.read_i2c_eeprom(hw, 1790 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1791 &oui_bytes[1]); 1792 1793 if (status != 0) 1794 goto err_read_i2c_eeprom; 1795 1796 status = hw->phy.ops.read_i2c_eeprom(hw, 1797 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1798 &oui_bytes[2]); 1799 1800 if (status != 0) 1801 goto err_read_i2c_eeprom; 1802 1803 vendor_oui = 1804 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1805 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1806 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1807 1808 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1809 hw->phy.type = ixgbe_phy_qsfp_intel; 1810 else 1811 hw->phy.type = ixgbe_phy_qsfp_unknown; 1812 1813 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1814 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1815 /* Make sure we're a supported PHY type */ 1816 if (hw->phy.type == ixgbe_phy_qsfp_intel) 1817 return 0; 1818 if (hw->allow_unsupported_sfp) { 1819 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1820 return 0; 1821 } 1822 hw_dbg(hw, "QSFP module not supported\n"); 1823 hw->phy.type = ixgbe_phy_sfp_unsupported; 1824 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1825 } 1826 return 0; 1827 } 1828 return 0; 1829 1830 err_read_i2c_eeprom: 1831 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1832 hw->phy.id = 0; 1833 hw->phy.type = ixgbe_phy_unknown; 1834 1835 return IXGBE_ERR_SFP_NOT_PRESENT; 1836 } 1837 1838 /** 1839 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1840 * @hw: pointer to hardware structure 1841 * @list_offset: offset to the SFP ID list 1842 * @data_offset: offset to the SFP data block 1843 * 1844 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1845 * so it returns the offsets to the phy init sequence block. 1846 **/ 1847 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1848 u16 *list_offset, 1849 u16 *data_offset) 1850 { 1851 u16 sfp_id; 1852 u16 sfp_type = hw->phy.sfp_type; 1853 1854 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1855 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1856 1857 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1858 return IXGBE_ERR_SFP_NOT_PRESENT; 1859 1860 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1861 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1862 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1863 1864 /* 1865 * Limiting active cables and 1G Phys must be initialized as 1866 * SR modules 1867 */ 1868 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1869 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1870 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1871 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1872 sfp_type = ixgbe_sfp_type_srlr_core0; 1873 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1874 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1875 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1876 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1877 sfp_type = ixgbe_sfp_type_srlr_core1; 1878 1879 /* Read offset to PHY init contents */ 1880 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1881 hw_err(hw, "eeprom read at %d failed\n", 1882 IXGBE_PHY_INIT_OFFSET_NL); 1883 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1884 } 1885 1886 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1887 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1888 1889 /* Shift offset to first ID word */ 1890 (*list_offset)++; 1891 1892 /* 1893 * Find the matching SFP ID in the EEPROM 1894 * and program the init sequence 1895 */ 1896 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1897 goto err_phy; 1898 1899 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1900 if (sfp_id == sfp_type) { 1901 (*list_offset)++; 1902 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1903 goto err_phy; 1904 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1905 hw_dbg(hw, "SFP+ module not supported\n"); 1906 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1907 } else { 1908 break; 1909 } 1910 } else { 1911 (*list_offset) += 2; 1912 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1913 goto err_phy; 1914 } 1915 } 1916 1917 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1918 hw_dbg(hw, "No matching SFP+ module found\n"); 1919 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1920 } 1921 1922 return 0; 1923 1924 err_phy: 1925 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); 1926 return IXGBE_ERR_PHY; 1927 } 1928 1929 /** 1930 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1931 * @hw: pointer to hardware structure 1932 * @byte_offset: EEPROM byte offset to read 1933 * @eeprom_data: value read 1934 * 1935 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1936 **/ 1937 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1938 u8 *eeprom_data) 1939 { 1940 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1941 IXGBE_I2C_EEPROM_DEV_ADDR, 1942 eeprom_data); 1943 } 1944 1945 /** 1946 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1947 * @hw: pointer to hardware structure 1948 * @byte_offset: byte offset at address 0xA2 1949 * @sff8472_data: value read 1950 * 1951 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1952 **/ 1953 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1954 u8 *sff8472_data) 1955 { 1956 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1957 IXGBE_I2C_EEPROM_DEV_ADDR2, 1958 sff8472_data); 1959 } 1960 1961 /** 1962 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1963 * @hw: pointer to hardware structure 1964 * @byte_offset: EEPROM byte offset to write 1965 * @eeprom_data: value to write 1966 * 1967 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1968 **/ 1969 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1970 u8 eeprom_data) 1971 { 1972 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1973 IXGBE_I2C_EEPROM_DEV_ADDR, 1974 eeprom_data); 1975 } 1976 1977 /** 1978 * ixgbe_is_sfp_probe - Returns true if SFP is being detected 1979 * @hw: pointer to hardware structure 1980 * @offset: eeprom offset to be read 1981 * @addr: I2C address to be read 1982 */ 1983 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1984 { 1985 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1986 offset == IXGBE_SFF_IDENTIFIER && 1987 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1988 return true; 1989 return false; 1990 } 1991 1992 /** 1993 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1994 * @hw: pointer to hardware structure 1995 * @byte_offset: byte offset to read 1996 * @dev_addr: device address 1997 * @data: value read 1998 * @lock: true if to take and release semaphore 1999 * 2000 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2001 * a specified device address. 2002 */ 2003 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2004 u8 dev_addr, u8 *data, bool lock) 2005 { 2006 s32 status; 2007 u32 max_retry = 10; 2008 u32 retry = 0; 2009 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2010 bool nack = true; 2011 2012 if (hw->mac.type >= ixgbe_mac_X550) 2013 max_retry = 3; 2014 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2015 max_retry = IXGBE_SFP_DETECT_RETRIES; 2016 2017 *data = 0; 2018 2019 do { 2020 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2021 return IXGBE_ERR_SWFW_SYNC; 2022 2023 ixgbe_i2c_start(hw); 2024 2025 /* Device Address and write indication */ 2026 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2027 if (status != 0) 2028 goto fail; 2029 2030 status = ixgbe_get_i2c_ack(hw); 2031 if (status != 0) 2032 goto fail; 2033 2034 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2035 if (status != 0) 2036 goto fail; 2037 2038 status = ixgbe_get_i2c_ack(hw); 2039 if (status != 0) 2040 goto fail; 2041 2042 ixgbe_i2c_start(hw); 2043 2044 /* Device Address and read indication */ 2045 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2046 if (status != 0) 2047 goto fail; 2048 2049 status = ixgbe_get_i2c_ack(hw); 2050 if (status != 0) 2051 goto fail; 2052 2053 status = ixgbe_clock_in_i2c_byte(hw, data); 2054 if (status != 0) 2055 goto fail; 2056 2057 status = ixgbe_clock_out_i2c_bit(hw, nack); 2058 if (status != 0) 2059 goto fail; 2060 2061 ixgbe_i2c_stop(hw); 2062 if (lock) 2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2064 return 0; 2065 2066 fail: 2067 ixgbe_i2c_bus_clear(hw); 2068 if (lock) { 2069 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2070 msleep(100); 2071 } 2072 retry++; 2073 if (retry < max_retry) 2074 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 2075 else 2076 hw_dbg(hw, "I2C byte read error.\n"); 2077 2078 } while (retry < max_retry); 2079 2080 return status; 2081 } 2082 2083 /** 2084 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2085 * @hw: pointer to hardware structure 2086 * @byte_offset: byte offset to read 2087 * @dev_addr: device address 2088 * @data: value read 2089 * 2090 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2091 * a specified device address. 2092 */ 2093 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2094 u8 dev_addr, u8 *data) 2095 { 2096 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2097 data, true); 2098 } 2099 2100 /** 2101 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2102 * @hw: pointer to hardware structure 2103 * @byte_offset: byte offset to read 2104 * @dev_addr: device address 2105 * @data: value read 2106 * 2107 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2108 * a specified device address. 2109 */ 2110 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2111 u8 dev_addr, u8 *data) 2112 { 2113 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2114 data, false); 2115 } 2116 2117 /** 2118 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2119 * @hw: pointer to hardware structure 2120 * @byte_offset: byte offset to write 2121 * @dev_addr: device address 2122 * @data: value to write 2123 * @lock: true if to take and release semaphore 2124 * 2125 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2126 * a specified device address. 2127 */ 2128 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2129 u8 dev_addr, u8 data, bool lock) 2130 { 2131 s32 status; 2132 u32 max_retry = 1; 2133 u32 retry = 0; 2134 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2135 2136 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2137 return IXGBE_ERR_SWFW_SYNC; 2138 2139 do { 2140 ixgbe_i2c_start(hw); 2141 2142 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2143 if (status != 0) 2144 goto fail; 2145 2146 status = ixgbe_get_i2c_ack(hw); 2147 if (status != 0) 2148 goto fail; 2149 2150 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2151 if (status != 0) 2152 goto fail; 2153 2154 status = ixgbe_get_i2c_ack(hw); 2155 if (status != 0) 2156 goto fail; 2157 2158 status = ixgbe_clock_out_i2c_byte(hw, data); 2159 if (status != 0) 2160 goto fail; 2161 2162 status = ixgbe_get_i2c_ack(hw); 2163 if (status != 0) 2164 goto fail; 2165 2166 ixgbe_i2c_stop(hw); 2167 if (lock) 2168 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2169 return 0; 2170 2171 fail: 2172 ixgbe_i2c_bus_clear(hw); 2173 retry++; 2174 if (retry < max_retry) 2175 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 2176 else 2177 hw_dbg(hw, "I2C byte write error.\n"); 2178 } while (retry < max_retry); 2179 2180 if (lock) 2181 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2182 2183 return status; 2184 } 2185 2186 /** 2187 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2188 * @hw: pointer to hardware structure 2189 * @byte_offset: byte offset to write 2190 * @dev_addr: device address 2191 * @data: value to write 2192 * 2193 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2194 * a specified device address. 2195 */ 2196 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2197 u8 dev_addr, u8 data) 2198 { 2199 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2200 data, true); 2201 } 2202 2203 /** 2204 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2205 * @hw: pointer to hardware structure 2206 * @byte_offset: byte offset to write 2207 * @dev_addr: device address 2208 * @data: value to write 2209 * 2210 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2211 * a specified device address. 2212 */ 2213 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2214 u8 dev_addr, u8 data) 2215 { 2216 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2217 data, false); 2218 } 2219 2220 /** 2221 * ixgbe_i2c_start - Sets I2C start condition 2222 * @hw: pointer to hardware structure 2223 * 2224 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2225 * Set bit-bang mode on X550 hardware. 2226 **/ 2227 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2228 { 2229 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2230 2231 i2cctl |= IXGBE_I2C_BB_EN(hw); 2232 2233 /* Start condition must begin with data and clock high */ 2234 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2235 ixgbe_raise_i2c_clk(hw, &i2cctl); 2236 2237 /* Setup time for start condition (4.7us) */ 2238 udelay(IXGBE_I2C_T_SU_STA); 2239 2240 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2241 2242 /* Hold time for start condition (4us) */ 2243 udelay(IXGBE_I2C_T_HD_STA); 2244 2245 ixgbe_lower_i2c_clk(hw, &i2cctl); 2246 2247 /* Minimum low period of clock is 4.7 us */ 2248 udelay(IXGBE_I2C_T_LOW); 2249 2250 } 2251 2252 /** 2253 * ixgbe_i2c_stop - Sets I2C stop condition 2254 * @hw: pointer to hardware structure 2255 * 2256 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2257 * Disables bit-bang mode and negates data output enable on X550 2258 * hardware. 2259 **/ 2260 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2261 { 2262 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2263 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2264 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); 2265 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw); 2266 2267 /* Stop condition must begin with data low and clock high */ 2268 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2269 ixgbe_raise_i2c_clk(hw, &i2cctl); 2270 2271 /* Setup time for stop condition (4us) */ 2272 udelay(IXGBE_I2C_T_SU_STO); 2273 2274 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2275 2276 /* bus free time between stop and start (4.7us)*/ 2277 udelay(IXGBE_I2C_T_BUF); 2278 2279 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2280 i2cctl &= ~bb_en_bit; 2281 i2cctl |= data_oe_bit | clk_oe_bit; 2282 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2283 IXGBE_WRITE_FLUSH(hw); 2284 } 2285 } 2286 2287 /** 2288 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2289 * @hw: pointer to hardware structure 2290 * @data: data byte to clock in 2291 * 2292 * Clocks in one byte data via I2C data/clock 2293 **/ 2294 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2295 { 2296 s32 i; 2297 bool bit = false; 2298 2299 *data = 0; 2300 for (i = 7; i >= 0; i--) { 2301 ixgbe_clock_in_i2c_bit(hw, &bit); 2302 *data |= bit << i; 2303 } 2304 2305 return 0; 2306 } 2307 2308 /** 2309 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2310 * @hw: pointer to hardware structure 2311 * @data: data byte clocked out 2312 * 2313 * Clocks out one byte data via I2C data/clock 2314 **/ 2315 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2316 { 2317 s32 status; 2318 s32 i; 2319 u32 i2cctl; 2320 bool bit = false; 2321 2322 for (i = 7; i >= 0; i--) { 2323 bit = (data >> i) & 0x1; 2324 status = ixgbe_clock_out_i2c_bit(hw, bit); 2325 2326 if (status != 0) 2327 break; 2328 } 2329 2330 /* Release SDA line (set high) */ 2331 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2332 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2333 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw); 2334 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2335 IXGBE_WRITE_FLUSH(hw); 2336 2337 return status; 2338 } 2339 2340 /** 2341 * ixgbe_get_i2c_ack - Polls for I2C ACK 2342 * @hw: pointer to hardware structure 2343 * 2344 * Clocks in/out one bit via I2C data/clock 2345 **/ 2346 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2347 { 2348 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2349 s32 status = 0; 2350 u32 i = 0; 2351 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2352 u32 timeout = 10; 2353 bool ack = true; 2354 2355 if (data_oe_bit) { 2356 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2357 i2cctl |= data_oe_bit; 2358 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2359 IXGBE_WRITE_FLUSH(hw); 2360 } 2361 ixgbe_raise_i2c_clk(hw, &i2cctl); 2362 2363 /* Minimum high period of clock is 4us */ 2364 udelay(IXGBE_I2C_T_HIGH); 2365 2366 /* Poll for ACK. Note that ACK in I2C spec is 2367 * transition from 1 to 0 */ 2368 for (i = 0; i < timeout; i++) { 2369 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2370 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2371 2372 udelay(1); 2373 if (ack == 0) 2374 break; 2375 } 2376 2377 if (ack == 1) { 2378 hw_dbg(hw, "I2C ack was not received.\n"); 2379 status = IXGBE_ERR_I2C; 2380 } 2381 2382 ixgbe_lower_i2c_clk(hw, &i2cctl); 2383 2384 /* Minimum low period of clock is 4.7 us */ 2385 udelay(IXGBE_I2C_T_LOW); 2386 2387 return status; 2388 } 2389 2390 /** 2391 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2392 * @hw: pointer to hardware structure 2393 * @data: read data value 2394 * 2395 * Clocks in one bit via I2C data/clock 2396 **/ 2397 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2398 { 2399 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2400 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2401 2402 if (data_oe_bit) { 2403 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2404 i2cctl |= data_oe_bit; 2405 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 2406 IXGBE_WRITE_FLUSH(hw); 2407 } 2408 ixgbe_raise_i2c_clk(hw, &i2cctl); 2409 2410 /* Minimum high period of clock is 4us */ 2411 udelay(IXGBE_I2C_T_HIGH); 2412 2413 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2414 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2415 2416 ixgbe_lower_i2c_clk(hw, &i2cctl); 2417 2418 /* Minimum low period of clock is 4.7 us */ 2419 udelay(IXGBE_I2C_T_LOW); 2420 2421 return 0; 2422 } 2423 2424 /** 2425 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2426 * @hw: pointer to hardware structure 2427 * @data: data value to write 2428 * 2429 * Clocks out one bit via I2C data/clock 2430 **/ 2431 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2432 { 2433 s32 status; 2434 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2435 2436 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2437 if (status == 0) { 2438 ixgbe_raise_i2c_clk(hw, &i2cctl); 2439 2440 /* Minimum high period of clock is 4us */ 2441 udelay(IXGBE_I2C_T_HIGH); 2442 2443 ixgbe_lower_i2c_clk(hw, &i2cctl); 2444 2445 /* Minimum low period of clock is 4.7 us. 2446 * This also takes care of the data hold time. 2447 */ 2448 udelay(IXGBE_I2C_T_LOW); 2449 } else { 2450 hw_dbg(hw, "I2C data was not set to %X\n", data); 2451 return IXGBE_ERR_I2C; 2452 } 2453 2454 return 0; 2455 } 2456 /** 2457 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2458 * @hw: pointer to hardware structure 2459 * @i2cctl: Current value of I2CCTL register 2460 * 2461 * Raises the I2C clock line '0'->'1' 2462 * Negates the I2C clock output enable on X550 hardware. 2463 **/ 2464 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2465 { 2466 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw); 2467 u32 i = 0; 2468 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2469 u32 i2cctl_r = 0; 2470 2471 if (clk_oe_bit) { 2472 *i2cctl |= clk_oe_bit; 2473 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2474 } 2475 2476 for (i = 0; i < timeout; i++) { 2477 *i2cctl |= IXGBE_I2C_CLK_OUT(hw); 2478 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2479 IXGBE_WRITE_FLUSH(hw); 2480 /* SCL rise time (1000ns) */ 2481 udelay(IXGBE_I2C_T_RISE); 2482 2483 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2484 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw)) 2485 break; 2486 } 2487 } 2488 2489 /** 2490 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2491 * @hw: pointer to hardware structure 2492 * @i2cctl: Current value of I2CCTL register 2493 * 2494 * Lowers the I2C clock line '1'->'0' 2495 * Asserts the I2C clock output enable on X550 hardware. 2496 **/ 2497 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2498 { 2499 2500 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw); 2501 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw); 2502 2503 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2504 IXGBE_WRITE_FLUSH(hw); 2505 2506 /* SCL fall time (300ns) */ 2507 udelay(IXGBE_I2C_T_FALL); 2508 } 2509 2510 /** 2511 * ixgbe_set_i2c_data - Sets the I2C data bit 2512 * @hw: pointer to hardware structure 2513 * @i2cctl: Current value of I2CCTL register 2514 * @data: I2C data value (0 or 1) to set 2515 * 2516 * Sets the I2C data bit 2517 * Asserts the I2C data output enable on X550 hardware. 2518 **/ 2519 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2520 { 2521 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2522 2523 if (data) 2524 *i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2525 else 2526 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw); 2527 *i2cctl &= ~data_oe_bit; 2528 2529 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2530 IXGBE_WRITE_FLUSH(hw); 2531 2532 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2533 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2534 2535 if (!data) /* Can't verify data in this case */ 2536 return 0; 2537 if (data_oe_bit) { 2538 *i2cctl |= data_oe_bit; 2539 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2540 IXGBE_WRITE_FLUSH(hw); 2541 } 2542 2543 /* Verify data was set correctly */ 2544 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2545 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2546 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 2547 return IXGBE_ERR_I2C; 2548 } 2549 2550 return 0; 2551 } 2552 2553 /** 2554 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2555 * @hw: pointer to hardware structure 2556 * @i2cctl: Current value of I2CCTL register 2557 * 2558 * Returns the I2C data bit value 2559 * Negates the I2C data output enable on X550 hardware. 2560 **/ 2561 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2562 { 2563 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw); 2564 2565 if (data_oe_bit) { 2566 *i2cctl |= data_oe_bit; 2567 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2568 IXGBE_WRITE_FLUSH(hw); 2569 udelay(IXGBE_I2C_T_FALL); 2570 } 2571 2572 if (*i2cctl & IXGBE_I2C_DATA_IN(hw)) 2573 return true; 2574 return false; 2575 } 2576 2577 /** 2578 * ixgbe_i2c_bus_clear - Clears the I2C bus 2579 * @hw: pointer to hardware structure 2580 * 2581 * Clears the I2C bus by sending nine clock pulses. 2582 * Used when data line is stuck low. 2583 **/ 2584 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2585 { 2586 u32 i2cctl; 2587 u32 i; 2588 2589 ixgbe_i2c_start(hw); 2590 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2591 2592 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2593 2594 for (i = 0; i < 9; i++) { 2595 ixgbe_raise_i2c_clk(hw, &i2cctl); 2596 2597 /* Min high period of clock is 4us */ 2598 udelay(IXGBE_I2C_T_HIGH); 2599 2600 ixgbe_lower_i2c_clk(hw, &i2cctl); 2601 2602 /* Min low period of clock is 4.7us*/ 2603 udelay(IXGBE_I2C_T_LOW); 2604 } 2605 2606 ixgbe_i2c_start(hw); 2607 2608 /* Put the i2c bus back to default state */ 2609 ixgbe_i2c_stop(hw); 2610 } 2611 2612 /** 2613 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2614 * @hw: pointer to hardware structure 2615 * 2616 * Checks if the LASI temp alarm status was triggered due to overtemp 2617 **/ 2618 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2619 { 2620 u16 phy_data = 0; 2621 2622 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2623 return 0; 2624 2625 /* Check that the LASI temp alarm status was triggered */ 2626 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2627 MDIO_MMD_PMAPMD, &phy_data); 2628 2629 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2630 return 0; 2631 2632 return IXGBE_ERR_OVERTEMP; 2633 } 2634 2635 /** ixgbe_set_copper_phy_power - Control power for copper phy 2636 * @hw: pointer to hardware structure 2637 * @on: true for on, false for off 2638 **/ 2639 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2640 { 2641 u32 status; 2642 u16 reg; 2643 2644 /* Bail if we don't have copper phy */ 2645 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2646 return 0; 2647 2648 if (!on && ixgbe_mng_present(hw)) 2649 return 0; 2650 2651 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®); 2652 if (status) 2653 return status; 2654 2655 if (on) { 2656 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2657 } else { 2658 if (ixgbe_check_reset_blocked(hw)) 2659 return 0; 2660 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2661 } 2662 2663 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); 2664 return status; 2665 } 2666