1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 #include <linux/sched.h> 32 33 #include "ixgbe.h" 34 #include "ixgbe_phy.h" 35 36 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 51 52 /** 53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 54 * @hw: pointer to the hardware structure 55 * @byte: byte to send 56 * 57 * Returns an error code on error. 58 **/ 59 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 60 { 61 s32 status; 62 63 status = ixgbe_clock_out_i2c_byte(hw, byte); 64 if (status) 65 return status; 66 return ixgbe_get_i2c_ack(hw); 67 } 68 69 /** 70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 71 * @hw: pointer to the hardware structure 72 * @byte: pointer to a u8 to receive the byte 73 * 74 * Returns an error code on error. 75 **/ 76 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 77 { 78 s32 status; 79 80 status = ixgbe_clock_in_i2c_byte(hw, byte); 81 if (status) 82 return status; 83 /* ACK */ 84 return ixgbe_clock_out_i2c_bit(hw, false); 85 } 86 87 /** 88 * ixgbe_ones_comp_byte_add - Perform one's complement addition 89 * @add1: addend 1 90 * @add2: addend 2 91 * 92 * Returns one's complement 8-bit sum. 93 **/ 94 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 95 { 96 u16 sum = add1 + add2; 97 98 sum = (sum & 0xFF) + (sum >> 8); 99 return sum & 0xFF; 100 } 101 102 /** 103 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 104 * @hw: pointer to the hardware structure 105 * @addr: I2C bus address to read from 106 * @reg: I2C device register to read from 107 * @val: pointer to location to receive read value 108 * 109 * Returns an error code on error. 110 **/ 111 s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 112 u16 reg, u16 *val) 113 { 114 u32 swfw_mask = hw->phy.phy_semaphore_mask; 115 int max_retry = 10; 116 int retry = 0; 117 u8 csum_byte; 118 u8 high_bits; 119 u8 low_bits; 120 u8 reg_high; 121 u8 csum; 122 123 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 124 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 125 csum = ~csum; 126 do { 127 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 128 return IXGBE_ERR_SWFW_SYNC; 129 ixgbe_i2c_start(hw); 130 /* Device Address and write indication */ 131 if (ixgbe_out_i2c_byte_ack(hw, addr)) 132 goto fail; 133 /* Write bits 14:8 */ 134 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 135 goto fail; 136 /* Write bits 7:0 */ 137 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 138 goto fail; 139 /* Write csum */ 140 if (ixgbe_out_i2c_byte_ack(hw, csum)) 141 goto fail; 142 /* Re-start condition */ 143 ixgbe_i2c_start(hw); 144 /* Device Address and read indication */ 145 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 146 goto fail; 147 /* Get upper bits */ 148 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 149 goto fail; 150 /* Get low bits */ 151 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 152 goto fail; 153 /* Get csum */ 154 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 155 goto fail; 156 /* NACK */ 157 if (ixgbe_clock_out_i2c_bit(hw, false)) 158 goto fail; 159 ixgbe_i2c_stop(hw); 160 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 161 *val = (high_bits << 8) | low_bits; 162 return 0; 163 164 fail: 165 ixgbe_i2c_bus_clear(hw); 166 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 167 retry++; 168 if (retry < max_retry) 169 hw_dbg(hw, "I2C byte read combined error - Retry.\n"); 170 else 171 hw_dbg(hw, "I2C byte read combined error.\n"); 172 } while (retry < max_retry); 173 174 return IXGBE_ERR_I2C; 175 } 176 177 /** 178 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 179 * @hw: pointer to the hardware structure 180 * @addr: I2C bus address to write to 181 * @reg: I2C device register to write to 182 * @val: value to write 183 * 184 * Returns an error code on error. 185 **/ 186 s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 187 u8 addr, u16 reg, u16 val) 188 { 189 int max_retry = 1; 190 int retry = 0; 191 u8 reg_high; 192 u8 csum; 193 194 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 195 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 196 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 197 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 198 csum = ~csum; 199 do { 200 ixgbe_i2c_start(hw); 201 /* Device Address and write indication */ 202 if (ixgbe_out_i2c_byte_ack(hw, addr)) 203 goto fail; 204 /* Write bits 14:8 */ 205 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 206 goto fail; 207 /* Write bits 7:0 */ 208 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 209 goto fail; 210 /* Write data 15:8 */ 211 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 212 goto fail; 213 /* Write data 7:0 */ 214 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 215 goto fail; 216 /* Write csum */ 217 if (ixgbe_out_i2c_byte_ack(hw, csum)) 218 goto fail; 219 ixgbe_i2c_stop(hw); 220 return 0; 221 222 fail: 223 ixgbe_i2c_bus_clear(hw); 224 retry++; 225 if (retry < max_retry) 226 hw_dbg(hw, "I2C byte write combined error - Retry.\n"); 227 else 228 hw_dbg(hw, "I2C byte write combined error.\n"); 229 } while (retry < max_retry); 230 231 return IXGBE_ERR_I2C; 232 } 233 234 /** 235 * ixgbe_identify_phy_generic - Get physical layer module 236 * @hw: pointer to hardware structure 237 * 238 * Determines the physical layer module found on the current adapter. 239 **/ 240 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 241 { 242 u32 phy_addr; 243 u16 ext_ability = 0; 244 245 if (!hw->phy.phy_semaphore_mask) { 246 if (hw->bus.lan_id) 247 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 248 else 249 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 250 } 251 252 if (hw->phy.type == ixgbe_phy_unknown) { 253 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 254 hw->phy.mdio.prtad = phy_addr; 255 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { 256 ixgbe_get_phy_id(hw); 257 hw->phy.type = 258 ixgbe_get_phy_type_from_id(hw->phy.id); 259 260 if (hw->phy.type == ixgbe_phy_unknown) { 261 hw->phy.ops.read_reg(hw, 262 MDIO_PMA_EXTABLE, 263 MDIO_MMD_PMAPMD, 264 &ext_ability); 265 if (ext_ability & 266 (MDIO_PMA_EXTABLE_10GBT | 267 MDIO_PMA_EXTABLE_1000BT)) 268 hw->phy.type = 269 ixgbe_phy_cu_unknown; 270 else 271 hw->phy.type = 272 ixgbe_phy_generic; 273 } 274 275 return 0; 276 } 277 } 278 /* clear value if nothing found */ 279 hw->phy.mdio.prtad = 0; 280 return IXGBE_ERR_PHY_ADDR_INVALID; 281 } 282 return 0; 283 } 284 285 /** 286 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 287 * @hw: pointer to the hardware structure 288 * 289 * This function checks the MMNGC.MNG_VETO bit to see if there are 290 * any constraints on link from manageability. For MAC's that don't 291 * have this bit just return false since the link can not be blocked 292 * via this method. 293 **/ 294 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 295 { 296 u32 mmngc; 297 298 /* If we don't have this bit, it can't be blocking */ 299 if (hw->mac.type == ixgbe_mac_82598EB) 300 return false; 301 302 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 303 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 304 hw_dbg(hw, "MNG_VETO bit detected.\n"); 305 return true; 306 } 307 308 return false; 309 } 310 311 /** 312 * ixgbe_get_phy_id - Get the phy type 313 * @hw: pointer to hardware structure 314 * 315 **/ 316 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 317 { 318 s32 status; 319 u16 phy_id_high = 0; 320 u16 phy_id_low = 0; 321 322 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 323 &phy_id_high); 324 325 if (!status) { 326 hw->phy.id = (u32)(phy_id_high << 16); 327 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 328 &phy_id_low); 329 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 330 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 331 } 332 return status; 333 } 334 335 /** 336 * ixgbe_get_phy_type_from_id - Get the phy type 337 * @hw: pointer to hardware structure 338 * 339 **/ 340 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 341 { 342 enum ixgbe_phy_type phy_type; 343 344 switch (phy_id) { 345 case TN1010_PHY_ID: 346 phy_type = ixgbe_phy_tn; 347 break; 348 case X550_PHY_ID: 349 case X540_PHY_ID: 350 phy_type = ixgbe_phy_aq; 351 break; 352 case QT2022_PHY_ID: 353 phy_type = ixgbe_phy_qt; 354 break; 355 case ATH_PHY_ID: 356 phy_type = ixgbe_phy_nl; 357 break; 358 case X557_PHY_ID: 359 phy_type = ixgbe_phy_x550em_ext_t; 360 break; 361 default: 362 phy_type = ixgbe_phy_unknown; 363 break; 364 } 365 366 return phy_type; 367 } 368 369 /** 370 * ixgbe_reset_phy_generic - Performs a PHY reset 371 * @hw: pointer to hardware structure 372 **/ 373 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 374 { 375 u32 i; 376 u16 ctrl = 0; 377 s32 status = 0; 378 379 if (hw->phy.type == ixgbe_phy_unknown) 380 status = ixgbe_identify_phy_generic(hw); 381 382 if (status != 0 || hw->phy.type == ixgbe_phy_none) 383 return status; 384 385 /* Don't reset PHY if it's shut down due to overtemp. */ 386 if (!hw->phy.reset_if_overtemp && 387 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 388 return 0; 389 390 /* Blocked by MNG FW so bail */ 391 if (ixgbe_check_reset_blocked(hw)) 392 return 0; 393 394 /* 395 * Perform soft PHY reset to the PHY_XS. 396 * This will cause a soft reset to the PHY 397 */ 398 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 399 MDIO_MMD_PHYXS, 400 MDIO_CTRL1_RESET); 401 402 /* 403 * Poll for reset bit to self-clear indicating reset is complete. 404 * Some PHYs could take up to 3 seconds to complete and need about 405 * 1.7 usec delay after the reset is complete. 406 */ 407 for (i = 0; i < 30; i++) { 408 msleep(100); 409 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 410 MDIO_MMD_PHYXS, &ctrl); 411 if (!(ctrl & MDIO_CTRL1_RESET)) { 412 udelay(2); 413 break; 414 } 415 } 416 417 if (ctrl & MDIO_CTRL1_RESET) { 418 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 419 return IXGBE_ERR_RESET_FAILED; 420 } 421 422 return 0; 423 } 424 425 /** 426 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 427 * the SWFW lock 428 * @hw: pointer to hardware structure 429 * @reg_addr: 32 bit address of PHY register to read 430 * @phy_data: Pointer to read data from PHY register 431 **/ 432 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 433 u16 *phy_data) 434 { 435 u32 i, data, command; 436 437 /* Setup and write the address cycle command */ 438 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 439 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 440 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 441 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 442 443 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 444 445 /* Check every 10 usec to see if the address cycle completed. 446 * The MDI Command bit will clear when the operation is 447 * complete 448 */ 449 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 450 udelay(10); 451 452 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 453 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 454 break; 455 } 456 457 458 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 459 hw_dbg(hw, "PHY address command did not complete.\n"); 460 return IXGBE_ERR_PHY; 461 } 462 463 /* Address cycle complete, setup and write the read 464 * command 465 */ 466 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 467 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 468 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 469 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 470 471 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 472 473 /* Check every 10 usec to see if the address cycle 474 * completed. The MDI Command bit will clear when the 475 * operation is complete 476 */ 477 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 478 udelay(10); 479 480 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 481 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 482 break; 483 } 484 485 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 486 hw_dbg(hw, "PHY read command didn't complete\n"); 487 return IXGBE_ERR_PHY; 488 } 489 490 /* Read operation is complete. Get the data 491 * from MSRWD 492 */ 493 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 494 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 495 *phy_data = (u16)(data); 496 497 return 0; 498 } 499 500 /** 501 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 502 * using the SWFW lock - this function is needed in most cases 503 * @hw: pointer to hardware structure 504 * @reg_addr: 32 bit address of PHY register to read 505 * @phy_data: Pointer to read data from PHY register 506 **/ 507 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 508 u32 device_type, u16 *phy_data) 509 { 510 s32 status; 511 u32 gssr = hw->phy.phy_semaphore_mask; 512 513 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 514 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 515 phy_data); 516 hw->mac.ops.release_swfw_sync(hw, gssr); 517 } else { 518 return IXGBE_ERR_SWFW_SYNC; 519 } 520 521 return status; 522 } 523 524 /** 525 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 526 * without SWFW lock 527 * @hw: pointer to hardware structure 528 * @reg_addr: 32 bit PHY register to write 529 * @device_type: 5 bit device type 530 * @phy_data: Data to write to the PHY register 531 **/ 532 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 533 u32 device_type, u16 phy_data) 534 { 535 u32 i, command; 536 537 /* Put the data in the MDI single read and write data register*/ 538 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 539 540 /* Setup and write the address cycle command */ 541 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 542 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 543 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 544 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 545 546 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 547 548 /* 549 * Check every 10 usec to see if the address cycle completed. 550 * The MDI Command bit will clear when the operation is 551 * complete 552 */ 553 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 554 udelay(10); 555 556 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 557 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 558 break; 559 } 560 561 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 562 hw_dbg(hw, "PHY address cmd didn't complete\n"); 563 return IXGBE_ERR_PHY; 564 } 565 566 /* 567 * Address cycle complete, setup and write the write 568 * command 569 */ 570 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 571 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 572 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 573 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 574 575 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 576 577 /* Check every 10 usec to see if the address cycle 578 * completed. The MDI Command bit will clear when the 579 * operation is complete 580 */ 581 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 582 udelay(10); 583 584 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 585 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 586 break; 587 } 588 589 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 590 hw_dbg(hw, "PHY write cmd didn't complete\n"); 591 return IXGBE_ERR_PHY; 592 } 593 594 return 0; 595 } 596 597 /** 598 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 599 * using SWFW lock- this function is needed in most cases 600 * @hw: pointer to hardware structure 601 * @reg_addr: 32 bit PHY register to write 602 * @device_type: 5 bit device type 603 * @phy_data: Data to write to the PHY register 604 **/ 605 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 606 u32 device_type, u16 phy_data) 607 { 608 s32 status; 609 u32 gssr = hw->phy.phy_semaphore_mask; 610 611 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 612 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 613 phy_data); 614 hw->mac.ops.release_swfw_sync(hw, gssr); 615 } else { 616 return IXGBE_ERR_SWFW_SYNC; 617 } 618 619 return status; 620 } 621 622 /** 623 * ixgbe_setup_phy_link_generic - Set and restart autoneg 624 * @hw: pointer to hardware structure 625 * 626 * Restart autonegotiation and PHY and waits for completion. 627 **/ 628 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 629 { 630 s32 status = 0; 631 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 632 bool autoneg = false; 633 ixgbe_link_speed speed; 634 635 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 636 637 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 638 /* Set or unset auto-negotiation 10G advertisement */ 639 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 640 MDIO_MMD_AN, 641 &autoneg_reg); 642 643 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 644 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 645 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 646 647 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 648 MDIO_MMD_AN, 649 autoneg_reg); 650 } 651 652 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 653 /* Set or unset auto-negotiation 1G advertisement */ 654 hw->phy.ops.read_reg(hw, 655 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 656 MDIO_MMD_AN, 657 &autoneg_reg); 658 659 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 661 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 662 663 hw->phy.ops.write_reg(hw, 664 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 665 MDIO_MMD_AN, 666 autoneg_reg); 667 } 668 669 if (speed & IXGBE_LINK_SPEED_100_FULL) { 670 /* Set or unset auto-negotiation 100M advertisement */ 671 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 672 MDIO_MMD_AN, 673 &autoneg_reg); 674 675 autoneg_reg &= ~(ADVERTISE_100FULL | 676 ADVERTISE_100HALF); 677 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 678 autoneg_reg |= ADVERTISE_100FULL; 679 680 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 681 MDIO_MMD_AN, 682 autoneg_reg); 683 } 684 685 /* Blocked by MNG FW so don't reset PHY */ 686 if (ixgbe_check_reset_blocked(hw)) 687 return 0; 688 689 /* Restart PHY autonegotiation and wait for completion */ 690 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 691 MDIO_MMD_AN, &autoneg_reg); 692 693 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 694 695 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 696 MDIO_MMD_AN, autoneg_reg); 697 698 return status; 699 } 700 701 /** 702 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 703 * @hw: pointer to hardware structure 704 * @speed: new link speed 705 **/ 706 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 707 ixgbe_link_speed speed, 708 bool autoneg_wait_to_complete) 709 { 710 711 /* 712 * Clear autoneg_advertised and set new values based on input link 713 * speed. 714 */ 715 hw->phy.autoneg_advertised = 0; 716 717 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 718 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 719 720 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 721 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 722 723 if (speed & IXGBE_LINK_SPEED_100_FULL) 724 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 725 726 /* Setup link based on the new speed settings */ 727 hw->phy.ops.setup_link(hw); 728 729 return 0; 730 } 731 732 /** 733 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy 734 * @hw: pointer to hardware structure 735 * 736 * Determines the supported link capabilities by reading the PHY auto 737 * negotiation register. 738 */ 739 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 740 { 741 u16 speed_ability; 742 s32 status; 743 744 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 745 &speed_ability); 746 if (status) 747 return status; 748 749 if (speed_ability & MDIO_SPEED_10G) 750 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 751 if (speed_ability & MDIO_PMA_SPEED_1000) 752 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 753 if (speed_ability & MDIO_PMA_SPEED_100) 754 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 755 756 switch (hw->mac.type) { 757 case ixgbe_mac_X550: 758 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 759 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 760 break; 761 case ixgbe_mac_X550EM_x: 762 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 763 break; 764 default: 765 break; 766 } 767 768 return 0; 769 } 770 771 /** 772 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 773 * @hw: pointer to hardware structure 774 * @speed: pointer to link speed 775 * @autoneg: boolean auto-negotiation value 776 */ 777 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 778 ixgbe_link_speed *speed, 779 bool *autoneg) 780 { 781 s32 status = 0; 782 783 *autoneg = true; 784 if (!hw->phy.speeds_supported) 785 status = ixgbe_get_copper_speeds_supported(hw); 786 787 *speed = hw->phy.speeds_supported; 788 return status; 789 } 790 791 /** 792 * ixgbe_check_phy_link_tnx - Determine link and speed status 793 * @hw: pointer to hardware structure 794 * 795 * Reads the VS1 register to determine if link is up and the current speed for 796 * the PHY. 797 **/ 798 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 799 bool *link_up) 800 { 801 s32 status; 802 u32 time_out; 803 u32 max_time_out = 10; 804 u16 phy_link = 0; 805 u16 phy_speed = 0; 806 u16 phy_data = 0; 807 808 /* Initialize speed and link to default case */ 809 *link_up = false; 810 *speed = IXGBE_LINK_SPEED_10GB_FULL; 811 812 /* 813 * Check current speed and link status of the PHY register. 814 * This is a vendor specific register and may have to 815 * be changed for other copper PHYs. 816 */ 817 for (time_out = 0; time_out < max_time_out; time_out++) { 818 udelay(10); 819 status = hw->phy.ops.read_reg(hw, 820 MDIO_STAT1, 821 MDIO_MMD_VEND1, 822 &phy_data); 823 phy_link = phy_data & 824 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 825 phy_speed = phy_data & 826 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 827 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 828 *link_up = true; 829 if (phy_speed == 830 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 831 *speed = IXGBE_LINK_SPEED_1GB_FULL; 832 break; 833 } 834 } 835 836 return status; 837 } 838 839 /** 840 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 841 * @hw: pointer to hardware structure 842 * 843 * Restart autonegotiation and PHY and waits for completion. 844 * This function always returns success, this is nessary since 845 * it is called via a function pointer that could call other 846 * functions that could return an error. 847 **/ 848 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 849 { 850 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 851 bool autoneg = false; 852 ixgbe_link_speed speed; 853 854 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 855 856 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 857 /* Set or unset auto-negotiation 10G advertisement */ 858 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 859 MDIO_MMD_AN, 860 &autoneg_reg); 861 862 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 863 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 864 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 865 866 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 867 MDIO_MMD_AN, 868 autoneg_reg); 869 } 870 871 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 872 /* Set or unset auto-negotiation 1G advertisement */ 873 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 874 MDIO_MMD_AN, 875 &autoneg_reg); 876 877 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 878 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 879 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 880 881 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 882 MDIO_MMD_AN, 883 autoneg_reg); 884 } 885 886 if (speed & IXGBE_LINK_SPEED_100_FULL) { 887 /* Set or unset auto-negotiation 100M advertisement */ 888 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 889 MDIO_MMD_AN, 890 &autoneg_reg); 891 892 autoneg_reg &= ~(ADVERTISE_100FULL | 893 ADVERTISE_100HALF); 894 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 895 autoneg_reg |= ADVERTISE_100FULL; 896 897 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 898 MDIO_MMD_AN, 899 autoneg_reg); 900 } 901 902 /* Blocked by MNG FW so don't reset PHY */ 903 if (ixgbe_check_reset_blocked(hw)) 904 return 0; 905 906 /* Restart PHY autonegotiation and wait for completion */ 907 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 908 MDIO_MMD_AN, &autoneg_reg); 909 910 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 911 912 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 913 MDIO_MMD_AN, autoneg_reg); 914 return 0; 915 } 916 917 /** 918 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 919 * @hw: pointer to hardware structure 920 * @firmware_version: pointer to the PHY Firmware Version 921 **/ 922 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 923 u16 *firmware_version) 924 { 925 s32 status; 926 927 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 928 MDIO_MMD_VEND1, 929 firmware_version); 930 931 return status; 932 } 933 934 /** 935 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 936 * @hw: pointer to hardware structure 937 * @firmware_version: pointer to the PHY Firmware Version 938 **/ 939 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 940 u16 *firmware_version) 941 { 942 s32 status; 943 944 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 945 MDIO_MMD_VEND1, 946 firmware_version); 947 948 return status; 949 } 950 951 /** 952 * ixgbe_reset_phy_nl - Performs a PHY reset 953 * @hw: pointer to hardware structure 954 **/ 955 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 956 { 957 u16 phy_offset, control, eword, edata, block_crc; 958 bool end_data = false; 959 u16 list_offset, data_offset; 960 u16 phy_data = 0; 961 s32 ret_val; 962 u32 i; 963 964 /* Blocked by MNG FW so bail */ 965 if (ixgbe_check_reset_blocked(hw)) 966 return 0; 967 968 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 969 970 /* reset the PHY and poll for completion */ 971 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 972 (phy_data | MDIO_CTRL1_RESET)); 973 974 for (i = 0; i < 100; i++) { 975 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 976 &phy_data); 977 if ((phy_data & MDIO_CTRL1_RESET) == 0) 978 break; 979 usleep_range(10000, 20000); 980 } 981 982 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 983 hw_dbg(hw, "PHY reset did not complete.\n"); 984 return IXGBE_ERR_PHY; 985 } 986 987 /* Get init offsets */ 988 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 989 &data_offset); 990 if (ret_val) 991 return ret_val; 992 993 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 994 data_offset++; 995 while (!end_data) { 996 /* 997 * Read control word from PHY init contents offset 998 */ 999 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1000 if (ret_val) 1001 goto err_eeprom; 1002 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1003 IXGBE_CONTROL_SHIFT_NL; 1004 edata = eword & IXGBE_DATA_MASK_NL; 1005 switch (control) { 1006 case IXGBE_DELAY_NL: 1007 data_offset++; 1008 hw_dbg(hw, "DELAY: %d MS\n", edata); 1009 usleep_range(edata * 1000, edata * 2000); 1010 break; 1011 case IXGBE_DATA_NL: 1012 hw_dbg(hw, "DATA:\n"); 1013 data_offset++; 1014 ret_val = hw->eeprom.ops.read(hw, data_offset++, 1015 &phy_offset); 1016 if (ret_val) 1017 goto err_eeprom; 1018 for (i = 0; i < edata; i++) { 1019 ret_val = hw->eeprom.ops.read(hw, data_offset, 1020 &eword); 1021 if (ret_val) 1022 goto err_eeprom; 1023 hw->phy.ops.write_reg(hw, phy_offset, 1024 MDIO_MMD_PMAPMD, eword); 1025 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 1026 phy_offset); 1027 data_offset++; 1028 phy_offset++; 1029 } 1030 break; 1031 case IXGBE_CONTROL_NL: 1032 data_offset++; 1033 hw_dbg(hw, "CONTROL:\n"); 1034 if (edata == IXGBE_CONTROL_EOL_NL) { 1035 hw_dbg(hw, "EOL\n"); 1036 end_data = true; 1037 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1038 hw_dbg(hw, "SOL\n"); 1039 } else { 1040 hw_dbg(hw, "Bad control value\n"); 1041 return IXGBE_ERR_PHY; 1042 } 1043 break; 1044 default: 1045 hw_dbg(hw, "Bad control type\n"); 1046 return IXGBE_ERR_PHY; 1047 } 1048 } 1049 1050 return ret_val; 1051 1052 err_eeprom: 1053 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 1054 return IXGBE_ERR_PHY; 1055 } 1056 1057 /** 1058 * ixgbe_identify_module_generic - Identifies module type 1059 * @hw: pointer to hardware structure 1060 * 1061 * Determines HW type and calls appropriate function. 1062 **/ 1063 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1064 { 1065 switch (hw->mac.ops.get_media_type(hw)) { 1066 case ixgbe_media_type_fiber: 1067 return ixgbe_identify_sfp_module_generic(hw); 1068 case ixgbe_media_type_fiber_qsfp: 1069 return ixgbe_identify_qsfp_module_generic(hw); 1070 default: 1071 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1072 return IXGBE_ERR_SFP_NOT_PRESENT; 1073 } 1074 1075 return IXGBE_ERR_SFP_NOT_PRESENT; 1076 } 1077 1078 /** 1079 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1080 * @hw: pointer to hardware structure 1081 * 1082 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1083 **/ 1084 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1085 { 1086 struct ixgbe_adapter *adapter = hw->back; 1087 s32 status; 1088 u32 vendor_oui = 0; 1089 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1090 u8 identifier = 0; 1091 u8 comp_codes_1g = 0; 1092 u8 comp_codes_10g = 0; 1093 u8 oui_bytes[3] = {0, 0, 0}; 1094 u8 cable_tech = 0; 1095 u8 cable_spec = 0; 1096 u16 enforce_sfp = 0; 1097 1098 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1099 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1100 return IXGBE_ERR_SFP_NOT_PRESENT; 1101 } 1102 1103 status = hw->phy.ops.read_i2c_eeprom(hw, 1104 IXGBE_SFF_IDENTIFIER, 1105 &identifier); 1106 1107 if (status) 1108 goto err_read_i2c_eeprom; 1109 1110 /* LAN ID is needed for sfp_type determination */ 1111 hw->mac.ops.set_lan_id(hw); 1112 1113 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1114 hw->phy.type = ixgbe_phy_sfp_unsupported; 1115 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1116 } 1117 status = hw->phy.ops.read_i2c_eeprom(hw, 1118 IXGBE_SFF_1GBE_COMP_CODES, 1119 &comp_codes_1g); 1120 1121 if (status) 1122 goto err_read_i2c_eeprom; 1123 1124 status = hw->phy.ops.read_i2c_eeprom(hw, 1125 IXGBE_SFF_10GBE_COMP_CODES, 1126 &comp_codes_10g); 1127 1128 if (status) 1129 goto err_read_i2c_eeprom; 1130 status = hw->phy.ops.read_i2c_eeprom(hw, 1131 IXGBE_SFF_CABLE_TECHNOLOGY, 1132 &cable_tech); 1133 1134 if (status) 1135 goto err_read_i2c_eeprom; 1136 1137 /* ID Module 1138 * ========= 1139 * 0 SFP_DA_CU 1140 * 1 SFP_SR 1141 * 2 SFP_LR 1142 * 3 SFP_DA_CORE0 - 82599-specific 1143 * 4 SFP_DA_CORE1 - 82599-specific 1144 * 5 SFP_SR/LR_CORE0 - 82599-specific 1145 * 6 SFP_SR/LR_CORE1 - 82599-specific 1146 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1147 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1148 * 9 SFP_1g_cu_CORE0 - 82599-specific 1149 * 10 SFP_1g_cu_CORE1 - 82599-specific 1150 * 11 SFP_1g_sx_CORE0 - 82599-specific 1151 * 12 SFP_1g_sx_CORE1 - 82599-specific 1152 */ 1153 if (hw->mac.type == ixgbe_mac_82598EB) { 1154 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1155 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1156 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1157 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1158 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1159 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1160 else 1161 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1162 } else if (hw->mac.type == ixgbe_mac_82599EB) { 1163 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1164 if (hw->bus.lan_id == 0) 1165 hw->phy.sfp_type = 1166 ixgbe_sfp_type_da_cu_core0; 1167 else 1168 hw->phy.sfp_type = 1169 ixgbe_sfp_type_da_cu_core1; 1170 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1171 hw->phy.ops.read_i2c_eeprom( 1172 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1173 &cable_spec); 1174 if (cable_spec & 1175 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1176 if (hw->bus.lan_id == 0) 1177 hw->phy.sfp_type = 1178 ixgbe_sfp_type_da_act_lmt_core0; 1179 else 1180 hw->phy.sfp_type = 1181 ixgbe_sfp_type_da_act_lmt_core1; 1182 } else { 1183 hw->phy.sfp_type = 1184 ixgbe_sfp_type_unknown; 1185 } 1186 } else if (comp_codes_10g & 1187 (IXGBE_SFF_10GBASESR_CAPABLE | 1188 IXGBE_SFF_10GBASELR_CAPABLE)) { 1189 if (hw->bus.lan_id == 0) 1190 hw->phy.sfp_type = 1191 ixgbe_sfp_type_srlr_core0; 1192 else 1193 hw->phy.sfp_type = 1194 ixgbe_sfp_type_srlr_core1; 1195 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1196 if (hw->bus.lan_id == 0) 1197 hw->phy.sfp_type = 1198 ixgbe_sfp_type_1g_cu_core0; 1199 else 1200 hw->phy.sfp_type = 1201 ixgbe_sfp_type_1g_cu_core1; 1202 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1203 if (hw->bus.lan_id == 0) 1204 hw->phy.sfp_type = 1205 ixgbe_sfp_type_1g_sx_core0; 1206 else 1207 hw->phy.sfp_type = 1208 ixgbe_sfp_type_1g_sx_core1; 1209 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1210 if (hw->bus.lan_id == 0) 1211 hw->phy.sfp_type = 1212 ixgbe_sfp_type_1g_lx_core0; 1213 else 1214 hw->phy.sfp_type = 1215 ixgbe_sfp_type_1g_lx_core1; 1216 } else { 1217 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1218 } 1219 } 1220 1221 if (hw->phy.sfp_type != stored_sfp_type) 1222 hw->phy.sfp_setup_needed = true; 1223 1224 /* Determine if the SFP+ PHY is dual speed or not. */ 1225 hw->phy.multispeed_fiber = false; 1226 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1227 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1228 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1229 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1230 hw->phy.multispeed_fiber = true; 1231 1232 /* Determine PHY vendor */ 1233 if (hw->phy.type != ixgbe_phy_nl) { 1234 hw->phy.id = identifier; 1235 status = hw->phy.ops.read_i2c_eeprom(hw, 1236 IXGBE_SFF_VENDOR_OUI_BYTE0, 1237 &oui_bytes[0]); 1238 1239 if (status != 0) 1240 goto err_read_i2c_eeprom; 1241 1242 status = hw->phy.ops.read_i2c_eeprom(hw, 1243 IXGBE_SFF_VENDOR_OUI_BYTE1, 1244 &oui_bytes[1]); 1245 1246 if (status != 0) 1247 goto err_read_i2c_eeprom; 1248 1249 status = hw->phy.ops.read_i2c_eeprom(hw, 1250 IXGBE_SFF_VENDOR_OUI_BYTE2, 1251 &oui_bytes[2]); 1252 1253 if (status != 0) 1254 goto err_read_i2c_eeprom; 1255 1256 vendor_oui = 1257 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1258 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1259 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1260 1261 switch (vendor_oui) { 1262 case IXGBE_SFF_VENDOR_OUI_TYCO: 1263 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1264 hw->phy.type = 1265 ixgbe_phy_sfp_passive_tyco; 1266 break; 1267 case IXGBE_SFF_VENDOR_OUI_FTL: 1268 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1269 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1270 else 1271 hw->phy.type = ixgbe_phy_sfp_ftl; 1272 break; 1273 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1274 hw->phy.type = ixgbe_phy_sfp_avago; 1275 break; 1276 case IXGBE_SFF_VENDOR_OUI_INTEL: 1277 hw->phy.type = ixgbe_phy_sfp_intel; 1278 break; 1279 default: 1280 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1281 hw->phy.type = 1282 ixgbe_phy_sfp_passive_unknown; 1283 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1284 hw->phy.type = 1285 ixgbe_phy_sfp_active_unknown; 1286 else 1287 hw->phy.type = ixgbe_phy_sfp_unknown; 1288 break; 1289 } 1290 } 1291 1292 /* Allow any DA cable vendor */ 1293 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1294 IXGBE_SFF_DA_ACTIVE_CABLE)) 1295 return 0; 1296 1297 /* Verify supported 1G SFP modules */ 1298 if (comp_codes_10g == 0 && 1299 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1300 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1301 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1302 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1303 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1304 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1305 hw->phy.type = ixgbe_phy_sfp_unsupported; 1306 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1307 } 1308 1309 /* Anything else 82598-based is supported */ 1310 if (hw->mac.type == ixgbe_mac_82598EB) 1311 return 0; 1312 1313 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1314 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1315 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1316 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1317 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1318 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1319 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1320 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1321 /* Make sure we're a supported PHY type */ 1322 if (hw->phy.type == ixgbe_phy_sfp_intel) 1323 return 0; 1324 if (hw->allow_unsupported_sfp) { 1325 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1326 return 0; 1327 } 1328 hw_dbg(hw, "SFP+ module not supported\n"); 1329 hw->phy.type = ixgbe_phy_sfp_unsupported; 1330 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1331 } 1332 return 0; 1333 1334 err_read_i2c_eeprom: 1335 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1336 if (hw->phy.type != ixgbe_phy_nl) { 1337 hw->phy.id = 0; 1338 hw->phy.type = ixgbe_phy_unknown; 1339 } 1340 return IXGBE_ERR_SFP_NOT_PRESENT; 1341 } 1342 1343 /** 1344 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1345 * @hw: pointer to hardware structure 1346 * 1347 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1348 **/ 1349 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1350 { 1351 struct ixgbe_adapter *adapter = hw->back; 1352 s32 status; 1353 u32 vendor_oui = 0; 1354 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1355 u8 identifier = 0; 1356 u8 comp_codes_1g = 0; 1357 u8 comp_codes_10g = 0; 1358 u8 oui_bytes[3] = {0, 0, 0}; 1359 u16 enforce_sfp = 0; 1360 u8 connector = 0; 1361 u8 cable_length = 0; 1362 u8 device_tech = 0; 1363 bool active_cable = false; 1364 1365 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1366 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1367 return IXGBE_ERR_SFP_NOT_PRESENT; 1368 } 1369 1370 /* LAN ID is needed for sfp_type determination */ 1371 hw->mac.ops.set_lan_id(hw); 1372 1373 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1374 &identifier); 1375 1376 if (status != 0) 1377 goto err_read_i2c_eeprom; 1378 1379 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1380 hw->phy.type = ixgbe_phy_sfp_unsupported; 1381 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1382 } 1383 1384 hw->phy.id = identifier; 1385 1386 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1387 &comp_codes_10g); 1388 1389 if (status != 0) 1390 goto err_read_i2c_eeprom; 1391 1392 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1393 &comp_codes_1g); 1394 1395 if (status != 0) 1396 goto err_read_i2c_eeprom; 1397 1398 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1399 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1400 if (hw->bus.lan_id == 0) 1401 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1402 else 1403 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1404 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1405 IXGBE_SFF_10GBASELR_CAPABLE)) { 1406 if (hw->bus.lan_id == 0) 1407 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1408 else 1409 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1410 } else { 1411 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1412 active_cable = true; 1413 1414 if (!active_cable) { 1415 /* check for active DA cables that pre-date 1416 * SFF-8436 v3.6 1417 */ 1418 hw->phy.ops.read_i2c_eeprom(hw, 1419 IXGBE_SFF_QSFP_CONNECTOR, 1420 &connector); 1421 1422 hw->phy.ops.read_i2c_eeprom(hw, 1423 IXGBE_SFF_QSFP_CABLE_LENGTH, 1424 &cable_length); 1425 1426 hw->phy.ops.read_i2c_eeprom(hw, 1427 IXGBE_SFF_QSFP_DEVICE_TECH, 1428 &device_tech); 1429 1430 if ((connector == 1431 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1432 (cable_length > 0) && 1433 ((device_tech >> 4) == 1434 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1435 active_cable = true; 1436 } 1437 1438 if (active_cable) { 1439 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1440 if (hw->bus.lan_id == 0) 1441 hw->phy.sfp_type = 1442 ixgbe_sfp_type_da_act_lmt_core0; 1443 else 1444 hw->phy.sfp_type = 1445 ixgbe_sfp_type_da_act_lmt_core1; 1446 } else { 1447 /* unsupported module type */ 1448 hw->phy.type = ixgbe_phy_sfp_unsupported; 1449 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1450 } 1451 } 1452 1453 if (hw->phy.sfp_type != stored_sfp_type) 1454 hw->phy.sfp_setup_needed = true; 1455 1456 /* Determine if the QSFP+ PHY is dual speed or not. */ 1457 hw->phy.multispeed_fiber = false; 1458 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1459 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1460 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1461 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1462 hw->phy.multispeed_fiber = true; 1463 1464 /* Determine PHY vendor for optical modules */ 1465 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1466 IXGBE_SFF_10GBASELR_CAPABLE)) { 1467 status = hw->phy.ops.read_i2c_eeprom(hw, 1468 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1469 &oui_bytes[0]); 1470 1471 if (status != 0) 1472 goto err_read_i2c_eeprom; 1473 1474 status = hw->phy.ops.read_i2c_eeprom(hw, 1475 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1476 &oui_bytes[1]); 1477 1478 if (status != 0) 1479 goto err_read_i2c_eeprom; 1480 1481 status = hw->phy.ops.read_i2c_eeprom(hw, 1482 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1483 &oui_bytes[2]); 1484 1485 if (status != 0) 1486 goto err_read_i2c_eeprom; 1487 1488 vendor_oui = 1489 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1490 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1491 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1492 1493 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1494 hw->phy.type = ixgbe_phy_qsfp_intel; 1495 else 1496 hw->phy.type = ixgbe_phy_qsfp_unknown; 1497 1498 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1499 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1500 /* Make sure we're a supported PHY type */ 1501 if (hw->phy.type == ixgbe_phy_qsfp_intel) 1502 return 0; 1503 if (hw->allow_unsupported_sfp) { 1504 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1505 return 0; 1506 } 1507 hw_dbg(hw, "QSFP module not supported\n"); 1508 hw->phy.type = ixgbe_phy_sfp_unsupported; 1509 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1510 } 1511 return 0; 1512 } 1513 return 0; 1514 1515 err_read_i2c_eeprom: 1516 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1517 hw->phy.id = 0; 1518 hw->phy.type = ixgbe_phy_unknown; 1519 1520 return IXGBE_ERR_SFP_NOT_PRESENT; 1521 } 1522 1523 /** 1524 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1525 * @hw: pointer to hardware structure 1526 * @list_offset: offset to the SFP ID list 1527 * @data_offset: offset to the SFP data block 1528 * 1529 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1530 * so it returns the offsets to the phy init sequence block. 1531 **/ 1532 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1533 u16 *list_offset, 1534 u16 *data_offset) 1535 { 1536 u16 sfp_id; 1537 u16 sfp_type = hw->phy.sfp_type; 1538 1539 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1540 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1541 1542 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1543 return IXGBE_ERR_SFP_NOT_PRESENT; 1544 1545 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1546 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1547 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1548 1549 /* 1550 * Limiting active cables and 1G Phys must be initialized as 1551 * SR modules 1552 */ 1553 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1554 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1555 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1556 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1557 sfp_type = ixgbe_sfp_type_srlr_core0; 1558 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1559 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1560 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1561 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1562 sfp_type = ixgbe_sfp_type_srlr_core1; 1563 1564 /* Read offset to PHY init contents */ 1565 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1566 hw_err(hw, "eeprom read at %d failed\n", 1567 IXGBE_PHY_INIT_OFFSET_NL); 1568 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1569 } 1570 1571 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1572 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1573 1574 /* Shift offset to first ID word */ 1575 (*list_offset)++; 1576 1577 /* 1578 * Find the matching SFP ID in the EEPROM 1579 * and program the init sequence 1580 */ 1581 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1582 goto err_phy; 1583 1584 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1585 if (sfp_id == sfp_type) { 1586 (*list_offset)++; 1587 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1588 goto err_phy; 1589 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1590 hw_dbg(hw, "SFP+ module not supported\n"); 1591 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1592 } else { 1593 break; 1594 } 1595 } else { 1596 (*list_offset) += 2; 1597 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1598 goto err_phy; 1599 } 1600 } 1601 1602 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1603 hw_dbg(hw, "No matching SFP+ module found\n"); 1604 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1605 } 1606 1607 return 0; 1608 1609 err_phy: 1610 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); 1611 return IXGBE_ERR_PHY; 1612 } 1613 1614 /** 1615 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1616 * @hw: pointer to hardware structure 1617 * @byte_offset: EEPROM byte offset to read 1618 * @eeprom_data: value read 1619 * 1620 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1621 **/ 1622 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1623 u8 *eeprom_data) 1624 { 1625 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1626 IXGBE_I2C_EEPROM_DEV_ADDR, 1627 eeprom_data); 1628 } 1629 1630 /** 1631 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1632 * @hw: pointer to hardware structure 1633 * @byte_offset: byte offset at address 0xA2 1634 * @eeprom_data: value read 1635 * 1636 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1637 **/ 1638 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1639 u8 *sff8472_data) 1640 { 1641 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1642 IXGBE_I2C_EEPROM_DEV_ADDR2, 1643 sff8472_data); 1644 } 1645 1646 /** 1647 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1648 * @hw: pointer to hardware structure 1649 * @byte_offset: EEPROM byte offset to write 1650 * @eeprom_data: value to write 1651 * 1652 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1653 **/ 1654 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1655 u8 eeprom_data) 1656 { 1657 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1658 IXGBE_I2C_EEPROM_DEV_ADDR, 1659 eeprom_data); 1660 } 1661 1662 /** 1663 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1664 * @hw: pointer to hardware structure 1665 * @byte_offset: byte offset to read 1666 * @data: value read 1667 * 1668 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1669 * a specified device address. 1670 **/ 1671 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1672 u8 dev_addr, u8 *data) 1673 { 1674 s32 status; 1675 u32 max_retry = 10; 1676 u32 retry = 0; 1677 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1678 bool nack = true; 1679 *data = 0; 1680 1681 do { 1682 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1683 return IXGBE_ERR_SWFW_SYNC; 1684 1685 ixgbe_i2c_start(hw); 1686 1687 /* Device Address and write indication */ 1688 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1689 if (status != 0) 1690 goto fail; 1691 1692 status = ixgbe_get_i2c_ack(hw); 1693 if (status != 0) 1694 goto fail; 1695 1696 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1697 if (status != 0) 1698 goto fail; 1699 1700 status = ixgbe_get_i2c_ack(hw); 1701 if (status != 0) 1702 goto fail; 1703 1704 ixgbe_i2c_start(hw); 1705 1706 /* Device Address and read indication */ 1707 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1708 if (status != 0) 1709 goto fail; 1710 1711 status = ixgbe_get_i2c_ack(hw); 1712 if (status != 0) 1713 goto fail; 1714 1715 status = ixgbe_clock_in_i2c_byte(hw, data); 1716 if (status != 0) 1717 goto fail; 1718 1719 status = ixgbe_clock_out_i2c_bit(hw, nack); 1720 if (status != 0) 1721 goto fail; 1722 1723 ixgbe_i2c_stop(hw); 1724 break; 1725 1726 fail: 1727 ixgbe_i2c_bus_clear(hw); 1728 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1729 msleep(100); 1730 retry++; 1731 if (retry < max_retry) 1732 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 1733 else 1734 hw_dbg(hw, "I2C byte read error.\n"); 1735 1736 } while (retry < max_retry); 1737 1738 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1739 1740 return status; 1741 } 1742 1743 /** 1744 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1745 * @hw: pointer to hardware structure 1746 * @byte_offset: byte offset to write 1747 * @data: value to write 1748 * 1749 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1750 * a specified device address. 1751 **/ 1752 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1753 u8 dev_addr, u8 data) 1754 { 1755 s32 status; 1756 u32 max_retry = 1; 1757 u32 retry = 0; 1758 u32 swfw_mask = hw->phy.phy_semaphore_mask; 1759 1760 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1761 return IXGBE_ERR_SWFW_SYNC; 1762 1763 do { 1764 ixgbe_i2c_start(hw); 1765 1766 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1767 if (status != 0) 1768 goto fail; 1769 1770 status = ixgbe_get_i2c_ack(hw); 1771 if (status != 0) 1772 goto fail; 1773 1774 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1775 if (status != 0) 1776 goto fail; 1777 1778 status = ixgbe_get_i2c_ack(hw); 1779 if (status != 0) 1780 goto fail; 1781 1782 status = ixgbe_clock_out_i2c_byte(hw, data); 1783 if (status != 0) 1784 goto fail; 1785 1786 status = ixgbe_get_i2c_ack(hw); 1787 if (status != 0) 1788 goto fail; 1789 1790 ixgbe_i2c_stop(hw); 1791 break; 1792 1793 fail: 1794 ixgbe_i2c_bus_clear(hw); 1795 retry++; 1796 if (retry < max_retry) 1797 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 1798 else 1799 hw_dbg(hw, "I2C byte write error.\n"); 1800 } while (retry < max_retry); 1801 1802 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1803 1804 return status; 1805 } 1806 1807 /** 1808 * ixgbe_i2c_start - Sets I2C start condition 1809 * @hw: pointer to hardware structure 1810 * 1811 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1812 **/ 1813 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1814 { 1815 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1816 1817 /* Start condition must begin with data and clock high */ 1818 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1819 ixgbe_raise_i2c_clk(hw, &i2cctl); 1820 1821 /* Setup time for start condition (4.7us) */ 1822 udelay(IXGBE_I2C_T_SU_STA); 1823 1824 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1825 1826 /* Hold time for start condition (4us) */ 1827 udelay(IXGBE_I2C_T_HD_STA); 1828 1829 ixgbe_lower_i2c_clk(hw, &i2cctl); 1830 1831 /* Minimum low period of clock is 4.7 us */ 1832 udelay(IXGBE_I2C_T_LOW); 1833 1834 } 1835 1836 /** 1837 * ixgbe_i2c_stop - Sets I2C stop condition 1838 * @hw: pointer to hardware structure 1839 * 1840 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1841 **/ 1842 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1843 { 1844 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1845 1846 /* Stop condition must begin with data low and clock high */ 1847 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1848 ixgbe_raise_i2c_clk(hw, &i2cctl); 1849 1850 /* Setup time for stop condition (4us) */ 1851 udelay(IXGBE_I2C_T_SU_STO); 1852 1853 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1854 1855 /* bus free time between stop and start (4.7us)*/ 1856 udelay(IXGBE_I2C_T_BUF); 1857 } 1858 1859 /** 1860 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1861 * @hw: pointer to hardware structure 1862 * @data: data byte to clock in 1863 * 1864 * Clocks in one byte data via I2C data/clock 1865 **/ 1866 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1867 { 1868 s32 i; 1869 bool bit = false; 1870 1871 for (i = 7; i >= 0; i--) { 1872 ixgbe_clock_in_i2c_bit(hw, &bit); 1873 *data |= bit << i; 1874 } 1875 1876 return 0; 1877 } 1878 1879 /** 1880 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1881 * @hw: pointer to hardware structure 1882 * @data: data byte clocked out 1883 * 1884 * Clocks out one byte data via I2C data/clock 1885 **/ 1886 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1887 { 1888 s32 status; 1889 s32 i; 1890 u32 i2cctl; 1891 bool bit = false; 1892 1893 for (i = 7; i >= 0; i--) { 1894 bit = (data >> i) & 0x1; 1895 status = ixgbe_clock_out_i2c_bit(hw, bit); 1896 1897 if (status != 0) 1898 break; 1899 } 1900 1901 /* Release SDA line (set high) */ 1902 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1903 i2cctl |= IXGBE_I2C_DATA_OUT(hw); 1904 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl); 1905 IXGBE_WRITE_FLUSH(hw); 1906 1907 return status; 1908 } 1909 1910 /** 1911 * ixgbe_get_i2c_ack - Polls for I2C ACK 1912 * @hw: pointer to hardware structure 1913 * 1914 * Clocks in/out one bit via I2C data/clock 1915 **/ 1916 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1917 { 1918 s32 status = 0; 1919 u32 i = 0; 1920 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1921 u32 timeout = 10; 1922 bool ack = true; 1923 1924 ixgbe_raise_i2c_clk(hw, &i2cctl); 1925 1926 1927 /* Minimum high period of clock is 4us */ 1928 udelay(IXGBE_I2C_T_HIGH); 1929 1930 /* Poll for ACK. Note that ACK in I2C spec is 1931 * transition from 1 to 0 */ 1932 for (i = 0; i < timeout; i++) { 1933 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1934 ack = ixgbe_get_i2c_data(hw, &i2cctl); 1935 1936 udelay(1); 1937 if (ack == 0) 1938 break; 1939 } 1940 1941 if (ack == 1) { 1942 hw_dbg(hw, "I2C ack was not received.\n"); 1943 status = IXGBE_ERR_I2C; 1944 } 1945 1946 ixgbe_lower_i2c_clk(hw, &i2cctl); 1947 1948 /* Minimum low period of clock is 4.7 us */ 1949 udelay(IXGBE_I2C_T_LOW); 1950 1951 return status; 1952 } 1953 1954 /** 1955 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1956 * @hw: pointer to hardware structure 1957 * @data: read data value 1958 * 1959 * Clocks in one bit via I2C data/clock 1960 **/ 1961 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1962 { 1963 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1964 1965 ixgbe_raise_i2c_clk(hw, &i2cctl); 1966 1967 /* Minimum high period of clock is 4us */ 1968 udelay(IXGBE_I2C_T_HIGH); 1969 1970 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1971 *data = ixgbe_get_i2c_data(hw, &i2cctl); 1972 1973 ixgbe_lower_i2c_clk(hw, &i2cctl); 1974 1975 /* Minimum low period of clock is 4.7 us */ 1976 udelay(IXGBE_I2C_T_LOW); 1977 1978 return 0; 1979 } 1980 1981 /** 1982 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1983 * @hw: pointer to hardware structure 1984 * @data: data value to write 1985 * 1986 * Clocks out one bit via I2C data/clock 1987 **/ 1988 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1989 { 1990 s32 status; 1991 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 1992 1993 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1994 if (status == 0) { 1995 ixgbe_raise_i2c_clk(hw, &i2cctl); 1996 1997 /* Minimum high period of clock is 4us */ 1998 udelay(IXGBE_I2C_T_HIGH); 1999 2000 ixgbe_lower_i2c_clk(hw, &i2cctl); 2001 2002 /* Minimum low period of clock is 4.7 us. 2003 * This also takes care of the data hold time. 2004 */ 2005 udelay(IXGBE_I2C_T_LOW); 2006 } else { 2007 hw_dbg(hw, "I2C data was not set to %X\n", data); 2008 return IXGBE_ERR_I2C; 2009 } 2010 2011 return 0; 2012 } 2013 /** 2014 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2015 * @hw: pointer to hardware structure 2016 * @i2cctl: Current value of I2CCTL register 2017 * 2018 * Raises the I2C clock line '0'->'1' 2019 **/ 2020 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2021 { 2022 u32 i = 0; 2023 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2024 u32 i2cctl_r = 0; 2025 2026 for (i = 0; i < timeout; i++) { 2027 *i2cctl |= IXGBE_I2C_CLK_OUT(hw); 2028 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2029 IXGBE_WRITE_FLUSH(hw); 2030 /* SCL rise time (1000ns) */ 2031 udelay(IXGBE_I2C_T_RISE); 2032 2033 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2034 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw)) 2035 break; 2036 } 2037 } 2038 2039 /** 2040 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2041 * @hw: pointer to hardware structure 2042 * @i2cctl: Current value of I2CCTL register 2043 * 2044 * Lowers the I2C clock line '1'->'0' 2045 **/ 2046 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2047 { 2048 2049 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw); 2050 2051 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2052 IXGBE_WRITE_FLUSH(hw); 2053 2054 /* SCL fall time (300ns) */ 2055 udelay(IXGBE_I2C_T_FALL); 2056 } 2057 2058 /** 2059 * ixgbe_set_i2c_data - Sets the I2C data bit 2060 * @hw: pointer to hardware structure 2061 * @i2cctl: Current value of I2CCTL register 2062 * @data: I2C data value (0 or 1) to set 2063 * 2064 * Sets the I2C data bit 2065 **/ 2066 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2067 { 2068 if (data) 2069 *i2cctl |= IXGBE_I2C_DATA_OUT(hw); 2070 else 2071 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw); 2072 2073 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl); 2074 IXGBE_WRITE_FLUSH(hw); 2075 2076 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2077 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2078 2079 /* Verify data was set correctly */ 2080 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2081 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2082 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 2083 return IXGBE_ERR_I2C; 2084 } 2085 2086 return 0; 2087 } 2088 2089 /** 2090 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2091 * @hw: pointer to hardware structure 2092 * @i2cctl: Current value of I2CCTL register 2093 * 2094 * Returns the I2C data bit value 2095 **/ 2096 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2097 { 2098 if (*i2cctl & IXGBE_I2C_DATA_IN(hw)) 2099 return true; 2100 return false; 2101 } 2102 2103 /** 2104 * ixgbe_i2c_bus_clear - Clears the I2C bus 2105 * @hw: pointer to hardware structure 2106 * 2107 * Clears the I2C bus by sending nine clock pulses. 2108 * Used when data line is stuck low. 2109 **/ 2110 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2111 { 2112 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw)); 2113 u32 i; 2114 2115 ixgbe_i2c_start(hw); 2116 2117 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2118 2119 for (i = 0; i < 9; i++) { 2120 ixgbe_raise_i2c_clk(hw, &i2cctl); 2121 2122 /* Min high period of clock is 4us */ 2123 udelay(IXGBE_I2C_T_HIGH); 2124 2125 ixgbe_lower_i2c_clk(hw, &i2cctl); 2126 2127 /* Min low period of clock is 4.7us*/ 2128 udelay(IXGBE_I2C_T_LOW); 2129 } 2130 2131 ixgbe_i2c_start(hw); 2132 2133 /* Put the i2c bus back to default state */ 2134 ixgbe_i2c_stop(hw); 2135 } 2136 2137 /** 2138 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2139 * @hw: pointer to hardware structure 2140 * 2141 * Checks if the LASI temp alarm status was triggered due to overtemp 2142 **/ 2143 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2144 { 2145 u16 phy_data = 0; 2146 2147 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2148 return 0; 2149 2150 /* Check that the LASI temp alarm status was triggered */ 2151 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2152 MDIO_MMD_PMAPMD, &phy_data); 2153 2154 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2155 return 0; 2156 2157 return IXGBE_ERR_OVERTEMP; 2158 } 2159 2160 /** ixgbe_set_copper_phy_power - Control power for copper phy 2161 * @hw: pointer to hardware structure 2162 * @on: true for on, false for off 2163 **/ 2164 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2165 { 2166 u32 status; 2167 u16 reg; 2168 2169 /* Bail if we don't have copper phy */ 2170 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2171 return 0; 2172 2173 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2174 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2175 ®); 2176 if (status) 2177 return status; 2178 2179 if (on) { 2180 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2181 } else { 2182 if (ixgbe_check_reset_blocked(hw)) 2183 return 0; 2184 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2185 } 2186 2187 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2188 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2189 reg); 2190 return status; 2191 } 2192