1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6 #include <linux/iopoll.h>
7 #include <linux/sched.h>
8 
9 #include "ixgbe.h"
10 #include "ixgbe_phy.h"
11 
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27 
28 /**
29  *  ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30  *  @hw: pointer to the hardware structure
31  *  @byte: byte to send
32  *
33  *  Returns an error code on error.
34  **/
35 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36 {
37 	s32 status;
38 
39 	status = ixgbe_clock_out_i2c_byte(hw, byte);
40 	if (status)
41 		return status;
42 	return ixgbe_get_i2c_ack(hw);
43 }
44 
45 /**
46  *  ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47  *  @hw: pointer to the hardware structure
48  *  @byte: pointer to a u8 to receive the byte
49  *
50  *  Returns an error code on error.
51  **/
52 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53 {
54 	s32 status;
55 
56 	status = ixgbe_clock_in_i2c_byte(hw, byte);
57 	if (status)
58 		return status;
59 	/* ACK */
60 	return ixgbe_clock_out_i2c_bit(hw, false);
61 }
62 
63 /**
64  *  ixgbe_ones_comp_byte_add - Perform one's complement addition
65  *  @add1: addend 1
66  *  @add2: addend 2
67  *
68  *  Returns one's complement 8-bit sum.
69  **/
70 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71 {
72 	u16 sum = add1 + add2;
73 
74 	sum = (sum & 0xFF) + (sum >> 8);
75 	return sum & 0xFF;
76 }
77 
78 /**
79  *  ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80  *  @hw: pointer to the hardware structure
81  *  @addr: I2C bus address to read from
82  *  @reg: I2C device register to read from
83  *  @val: pointer to location to receive read value
84  *  @lock: true if to take and release semaphore
85  *
86  *  Returns an error code on error.
87  */
88 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 					u16 reg, u16 *val, bool lock)
90 {
91 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 	int max_retry = 3;
93 	int retry = 0;
94 	u8 csum_byte;
95 	u8 high_bits;
96 	u8 low_bits;
97 	u8 reg_high;
98 	u8 csum;
99 
100 	reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
101 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 	csum = ~csum;
103 	do {
104 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 			return -EBUSY;
106 		ixgbe_i2c_start(hw);
107 		/* Device Address and write indication */
108 		if (ixgbe_out_i2c_byte_ack(hw, addr))
109 			goto fail;
110 		/* Write bits 14:8 */
111 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 			goto fail;
113 		/* Write bits 7:0 */
114 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 			goto fail;
116 		/* Write csum */
117 		if (ixgbe_out_i2c_byte_ack(hw, csum))
118 			goto fail;
119 		/* Re-start condition */
120 		ixgbe_i2c_start(hw);
121 		/* Device Address and read indication */
122 		if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 			goto fail;
124 		/* Get upper bits */
125 		if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 			goto fail;
127 		/* Get low bits */
128 		if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 			goto fail;
130 		/* Get csum */
131 		if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 			goto fail;
133 		/* NACK */
134 		if (ixgbe_clock_out_i2c_bit(hw, false))
135 			goto fail;
136 		ixgbe_i2c_stop(hw);
137 		if (lock)
138 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 		*val = (high_bits << 8) | low_bits;
140 		return 0;
141 
142 fail:
143 		ixgbe_i2c_bus_clear(hw);
144 		if (lock)
145 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 		retry++;
147 		if (retry < max_retry)
148 			hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 		else
150 			hw_dbg(hw, "I2C byte read combined error.\n");
151 	} while (retry < max_retry);
152 
153 	return -EIO;
154 }
155 
156 /**
157  *  ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158  *  @hw: pointer to the hardware structure
159  *  @addr: I2C bus address to write to
160  *  @reg: I2C device register to write to
161  *  @val: value to write
162  *  @lock: true if to take and release semaphore
163  *
164  *  Returns an error code on error.
165  */
166 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 					 u16 reg, u16 val, bool lock)
168 {
169 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 	int max_retry = 1;
171 	int retry = 0;
172 	u8 reg_high;
173 	u8 csum;
174 
175 	reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
176 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 	csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 	csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 	csum = ~csum;
180 	do {
181 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 			return -EBUSY;
183 		ixgbe_i2c_start(hw);
184 		/* Device Address and write indication */
185 		if (ixgbe_out_i2c_byte_ack(hw, addr))
186 			goto fail;
187 		/* Write bits 14:8 */
188 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 			goto fail;
190 		/* Write bits 7:0 */
191 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 			goto fail;
193 		/* Write data 15:8 */
194 		if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 			goto fail;
196 		/* Write data 7:0 */
197 		if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 			goto fail;
199 		/* Write csum */
200 		if (ixgbe_out_i2c_byte_ack(hw, csum))
201 			goto fail;
202 		ixgbe_i2c_stop(hw);
203 		if (lock)
204 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 		return 0;
206 
207 fail:
208 		ixgbe_i2c_bus_clear(hw);
209 		if (lock)
210 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 		retry++;
212 		if (retry < max_retry)
213 			hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 		else
215 			hw_dbg(hw, "I2C byte write combined error.\n");
216 	} while (retry < max_retry);
217 
218 	return -EIO;
219 }
220 
221 /**
222  *  ixgbe_probe_phy - Probe a single address for a PHY
223  *  @hw: pointer to hardware structure
224  *  @phy_addr: PHY address to probe
225  *
226  *  Returns true if PHY found
227  **/
228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229 {
230 	u16 ext_ability = 0;
231 
232 	hw->phy.mdio.prtad = phy_addr;
233 	if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 		return false;
235 
236 	if (ixgbe_get_phy_id(hw))
237 		return false;
238 
239 	hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240 
241 	if (hw->phy.type == ixgbe_phy_unknown) {
242 		hw->phy.ops.read_reg(hw,
243 				     MDIO_PMA_EXTABLE,
244 				     MDIO_MMD_PMAPMD,
245 				     &ext_ability);
246 		if (ext_ability &
247 		    (MDIO_PMA_EXTABLE_10GBT |
248 		     MDIO_PMA_EXTABLE_1000BT))
249 			hw->phy.type = ixgbe_phy_cu_unknown;
250 		else
251 			hw->phy.type = ixgbe_phy_generic;
252 	}
253 
254 	return true;
255 }
256 
257 /**
258  *  ixgbe_identify_phy_generic - Get physical layer module
259  *  @hw: pointer to hardware structure
260  *
261  *  Determines the physical layer module found on the current adapter.
262  **/
263 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264 {
265 	u32 status = -EFAULT;
266 	u32 phy_addr;
267 
268 	if (!hw->phy.phy_semaphore_mask) {
269 		if (hw->bus.lan_id)
270 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 		else
272 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 	}
274 
275 	if (hw->phy.type != ixgbe_phy_unknown)
276 		return 0;
277 
278 	if (hw->phy.nw_mng_if_sel) {
279 		phy_addr = (hw->phy.nw_mng_if_sel &
280 			    IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281 			   IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282 		if (ixgbe_probe_phy(hw, phy_addr))
283 			return 0;
284 		else
285 			return -EFAULT;
286 	}
287 
288 	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289 		if (ixgbe_probe_phy(hw, phy_addr)) {
290 			status = 0;
291 			break;
292 		}
293 	}
294 
295 	/* Certain media types do not have a phy so an address will not
296 	 * be found and the code will take this path.  Caller has to
297 	 * decide if it is an error or not.
298 	 */
299 	if (status)
300 		hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
301 
302 	return status;
303 }
304 
305 /**
306  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
307  * @hw: pointer to the hardware structure
308  *
309  * This function checks the MMNGC.MNG_VETO bit to see if there are
310  * any constraints on link from manageability.  For MAC's that don't
311  * have this bit just return false since the link can not be blocked
312  * via this method.
313  **/
314 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
315 {
316 	u32 mmngc;
317 
318 	/* If we don't have this bit, it can't be blocking */
319 	if (hw->mac.type == ixgbe_mac_82598EB)
320 		return false;
321 
322 	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324 		hw_dbg(hw, "MNG_VETO bit detected.\n");
325 		return true;
326 	}
327 
328 	return false;
329 }
330 
331 /**
332  *  ixgbe_get_phy_id - Get the phy type
333  *  @hw: pointer to hardware structure
334  *
335  **/
336 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
337 {
338 	s32 status;
339 	u16 phy_id_high = 0;
340 	u16 phy_id_low = 0;
341 
342 	status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
343 				      &phy_id_high);
344 
345 	if (!status) {
346 		hw->phy.id = (u32)(phy_id_high << 16);
347 		status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 					      &phy_id_low);
349 		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350 		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
351 	}
352 	return status;
353 }
354 
355 /**
356  *  ixgbe_get_phy_type_from_id - Get the phy type
357  *  @phy_id: hardware phy id
358  *
359  **/
360 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
361 {
362 	enum ixgbe_phy_type phy_type;
363 
364 	switch (phy_id) {
365 	case TN1010_PHY_ID:
366 		phy_type = ixgbe_phy_tn;
367 		break;
368 	case X550_PHY_ID2:
369 	case X550_PHY_ID3:
370 	case X540_PHY_ID:
371 		phy_type = ixgbe_phy_aq;
372 		break;
373 	case QT2022_PHY_ID:
374 		phy_type = ixgbe_phy_qt;
375 		break;
376 	case ATH_PHY_ID:
377 		phy_type = ixgbe_phy_nl;
378 		break;
379 	case X557_PHY_ID:
380 	case X557_PHY_ID2:
381 		phy_type = ixgbe_phy_x550em_ext_t;
382 		break;
383 	case BCM54616S_E_PHY_ID:
384 		phy_type = ixgbe_phy_ext_1g_t;
385 		break;
386 	default:
387 		phy_type = ixgbe_phy_unknown;
388 		break;
389 	}
390 
391 	return phy_type;
392 }
393 
394 /**
395  *  ixgbe_reset_phy_generic - Performs a PHY reset
396  *  @hw: pointer to hardware structure
397  **/
398 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
399 {
400 	u32 i;
401 	u16 ctrl = 0;
402 	s32 status = 0;
403 
404 	if (hw->phy.type == ixgbe_phy_unknown)
405 		status = ixgbe_identify_phy_generic(hw);
406 
407 	if (status != 0 || hw->phy.type == ixgbe_phy_none)
408 		return status;
409 
410 	/* Don't reset PHY if it's shut down due to overtemp. */
411 	if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
412 		return 0;
413 
414 	/* Blocked by MNG FW so bail */
415 	if (ixgbe_check_reset_blocked(hw))
416 		return 0;
417 
418 	/*
419 	 * Perform soft PHY reset to the PHY_XS.
420 	 * This will cause a soft reset to the PHY
421 	 */
422 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
423 			      MDIO_MMD_PHYXS,
424 			      MDIO_CTRL1_RESET);
425 
426 	/*
427 	 * Poll for reset bit to self-clear indicating reset is complete.
428 	 * Some PHYs could take up to 3 seconds to complete and need about
429 	 * 1.7 usec delay after the reset is complete.
430 	 */
431 	for (i = 0; i < 30; i++) {
432 		msleep(100);
433 		if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
434 			status = hw->phy.ops.read_reg(hw,
435 						  IXGBE_MDIO_TX_VENDOR_ALARMS_3,
436 						  MDIO_MMD_PMAPMD, &ctrl);
437 			if (status)
438 				return status;
439 
440 			if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
441 				udelay(2);
442 				break;
443 			}
444 		} else {
445 			status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
446 						      MDIO_MMD_PHYXS, &ctrl);
447 			if (status)
448 				return status;
449 
450 			if (!(ctrl & MDIO_CTRL1_RESET)) {
451 				udelay(2);
452 				break;
453 			}
454 		}
455 	}
456 
457 	if (ctrl & MDIO_CTRL1_RESET) {
458 		hw_dbg(hw, "PHY reset polling failed to complete.\n");
459 		return -EIO;
460 	}
461 
462 	return 0;
463 }
464 
465 /**
466  *  ixgbe_read_phy_reg_mdi - read PHY register
467  *  @hw: pointer to hardware structure
468  *  @reg_addr: 32 bit address of PHY register to read
469  *  @device_type: 5 bit device type
470  *  @phy_data: Pointer to read data from PHY register
471  *
472  *  Reads a value from a specified PHY register without the SWFW lock
473  **/
474 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
475 		       u16 *phy_data)
476 {
477 	u32 i, data, command;
478 
479 	/* Setup and write the address cycle command */
480 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
481 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
482 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
483 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
484 
485 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
486 
487 	/* Check every 10 usec to see if the address cycle completed.
488 	 * The MDI Command bit will clear when the operation is
489 	 * complete
490 	 */
491 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
492 		udelay(10);
493 
494 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
495 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
496 				break;
497 	}
498 
499 
500 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
501 		hw_dbg(hw, "PHY address command did not complete.\n");
502 		return -EIO;
503 	}
504 
505 	/* Address cycle complete, setup and write the read
506 	 * command
507 	 */
508 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
509 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
510 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
511 		   (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
512 
513 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
514 
515 	/* Check every 10 usec to see if the address cycle
516 	 * completed. The MDI Command bit will clear when the
517 	 * operation is complete
518 	 */
519 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
520 		udelay(10);
521 
522 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
523 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
524 			break;
525 	}
526 
527 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
528 		hw_dbg(hw, "PHY read command didn't complete\n");
529 		return -EIO;
530 	}
531 
532 	/* Read operation is complete.  Get the data
533 	 * from MSRWD
534 	 */
535 	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
536 	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
537 	*phy_data = (u16)(data);
538 
539 	return 0;
540 }
541 
542 /**
543  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
544  *  using the SWFW lock - this function is needed in most cases
545  *  @hw: pointer to hardware structure
546  *  @reg_addr: 32 bit address of PHY register to read
547  *  @device_type: 5 bit device type
548  *  @phy_data: Pointer to read data from PHY register
549  **/
550 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
551 			       u32 device_type, u16 *phy_data)
552 {
553 	s32 status;
554 	u32 gssr = hw->phy.phy_semaphore_mask;
555 
556 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
557 		status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
558 						phy_data);
559 		hw->mac.ops.release_swfw_sync(hw, gssr);
560 	} else {
561 		return -EBUSY;
562 	}
563 
564 	return status;
565 }
566 
567 /**
568  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
569  *  without SWFW lock
570  *  @hw: pointer to hardware structure
571  *  @reg_addr: 32 bit PHY register to write
572  *  @device_type: 5 bit device type
573  *  @phy_data: Data to write to the PHY register
574  **/
575 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
576 				u32 device_type, u16 phy_data)
577 {
578 	u32 i, command;
579 
580 	/* Put the data in the MDI single read and write data register*/
581 	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
582 
583 	/* Setup and write the address cycle command */
584 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
585 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
586 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
587 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
588 
589 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
590 
591 	/*
592 	 * Check every 10 usec to see if the address cycle completed.
593 	 * The MDI Command bit will clear when the operation is
594 	 * complete
595 	 */
596 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
597 		udelay(10);
598 
599 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
600 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
601 			break;
602 	}
603 
604 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
605 		hw_dbg(hw, "PHY address cmd didn't complete\n");
606 		return -EIO;
607 	}
608 
609 	/*
610 	 * Address cycle complete, setup and write the write
611 	 * command
612 	 */
613 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
614 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
615 		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
616 		   (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
617 
618 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
619 
620 	/* Check every 10 usec to see if the address cycle
621 	 * completed. The MDI Command bit will clear when the
622 	 * operation is complete
623 	 */
624 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
625 		udelay(10);
626 
627 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
628 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
629 			break;
630 	}
631 
632 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
633 		hw_dbg(hw, "PHY write cmd didn't complete\n");
634 		return -EIO;
635 	}
636 
637 	return 0;
638 }
639 
640 /**
641  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
642  *  using SWFW lock- this function is needed in most cases
643  *  @hw: pointer to hardware structure
644  *  @reg_addr: 32 bit PHY register to write
645  *  @device_type: 5 bit device type
646  *  @phy_data: Data to write to the PHY register
647  **/
648 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
649 				u32 device_type, u16 phy_data)
650 {
651 	s32 status;
652 	u32 gssr = hw->phy.phy_semaphore_mask;
653 
654 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
655 		status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
656 						 phy_data);
657 		hw->mac.ops.release_swfw_sync(hw, gssr);
658 	} else {
659 		return -EBUSY;
660 	}
661 
662 	return status;
663 }
664 
665 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
666 
667 /**
668  *  ixgbe_msca_cmd - Write the command register and poll for completion/timeout
669  *  @hw: pointer to hardware structure
670  *  @cmd: command register value to write
671  **/
672 static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
673 {
674 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
675 
676 	return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
677 				  !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
678 				  10 * IXGBE_MDIO_COMMAND_TIMEOUT);
679 }
680 
681 /**
682  *  ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
683  *  @hw: pointer to hardware structure
684  *  @addr: address
685  *  @regnum: register number
686  *  @gssr: semaphore flags to acquire
687  **/
688 static s32 ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr,
689 					  int regnum, u32 gssr)
690 {
691 	u32 hwaddr, cmd;
692 	s32 data;
693 
694 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
695 		return -EBUSY;
696 
697 	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
698 	hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
699 	cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
700 		IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
701 
702 	data = ixgbe_msca_cmd(hw, cmd);
703 	if (data < 0)
704 		goto mii_bus_read_done;
705 
706 	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
707 	data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
708 
709 mii_bus_read_done:
710 	hw->mac.ops.release_swfw_sync(hw, gssr);
711 	return data;
712 }
713 
714 /**
715  *  ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
716  *  @hw: pointer to hardware structure
717  *  @addr: address
718  *  @devad: device address to read
719  *  @regnum: register number
720  *  @gssr: semaphore flags to acquire
721  **/
722 static s32 ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr,
723 					  int devad, int regnum, u32 gssr)
724 {
725 	u32 hwaddr, cmd;
726 	s32 data;
727 
728 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
729 		return -EBUSY;
730 
731 	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
732 	hwaddr |= devad << 16 | regnum;
733 	cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
734 
735 	data = ixgbe_msca_cmd(hw, cmd);
736 	if (data < 0)
737 		goto mii_bus_read_done;
738 
739 	cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
740 	data = ixgbe_msca_cmd(hw, cmd);
741 	if (data < 0)
742 		goto mii_bus_read_done;
743 
744 	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
745 	data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
746 
747 mii_bus_read_done:
748 	hw->mac.ops.release_swfw_sync(hw, gssr);
749 	return data;
750 }
751 
752 /**
753  *  ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
754  *  @hw: pointer to hardware structure
755  *  @addr: address
756  *  @regnum: register number
757  *  @val: value to write
758  *  @gssr: semaphore flags to acquire
759  **/
760 static s32 ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr,
761 					   int regnum, u16 val, u32 gssr)
762 {
763 	u32 hwaddr, cmd;
764 	s32 err;
765 
766 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
767 		return -EBUSY;
768 
769 	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
770 
771 	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
772 	hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
773 	cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
774 		IXGBE_MSCA_MDI_COMMAND;
775 
776 	err = ixgbe_msca_cmd(hw, cmd);
777 
778 	hw->mac.ops.release_swfw_sync(hw, gssr);
779 	return err;
780 }
781 
782 /**
783  *  ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
784  *  @hw: pointer to hardware structure
785  *  @addr: address
786  *  @devad: device address to read
787  *  @regnum: register number
788  *  @val: value to write
789  *  @gssr: semaphore flags to acquire
790  **/
791 static s32 ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr,
792 					   int devad, int regnum, u16 val,
793 					   u32 gssr)
794 {
795 	u32 hwaddr, cmd;
796 	s32 err;
797 
798 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
799 		return -EBUSY;
800 
801 	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
802 
803 	hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
804 	hwaddr |= devad << 16 | regnum;
805 	cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
806 
807 	err = ixgbe_msca_cmd(hw, cmd);
808 	if (err < 0)
809 		goto mii_bus_write_done;
810 
811 	cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
812 	err = ixgbe_msca_cmd(hw, cmd);
813 
814 mii_bus_write_done:
815 	hw->mac.ops.release_swfw_sync(hw, gssr);
816 	return err;
817 }
818 
819 /**
820  *  ixgbe_mii_bus_read_c22 - Read a clause 22 register
821  *  @bus: pointer to mii_bus structure which points to our driver private
822  *  @addr: address
823  *  @regnum: register number
824  **/
825 static s32 ixgbe_mii_bus_read_c22(struct mii_bus *bus, int addr, int regnum)
826 {
827 	struct ixgbe_adapter *adapter = bus->priv;
828 	struct ixgbe_hw *hw = &adapter->hw;
829 	u32 gssr = hw->phy.phy_semaphore_mask;
830 
831 	return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
832 }
833 
834 /**
835  *  ixgbe_mii_bus_read_c45 - Read a clause 45 register
836  *  @bus: pointer to mii_bus structure which points to our driver private
837  *  @devad: device address to read
838  *  @addr: address
839  *  @regnum: register number
840  **/
841 static s32 ixgbe_mii_bus_read_c45(struct mii_bus *bus, int devad, int addr,
842 				  int regnum)
843 {
844 	struct ixgbe_adapter *adapter = bus->priv;
845 	struct ixgbe_hw *hw = &adapter->hw;
846 	u32 gssr = hw->phy.phy_semaphore_mask;
847 
848 	return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
849 }
850 
851 /**
852  *  ixgbe_mii_bus_write_c22 - Write a clause 22 register
853  *  @bus: pointer to mii_bus structure which points to our driver private
854  *  @addr: address
855  *  @regnum: register number
856  *  @val: value to write
857  **/
858 static s32 ixgbe_mii_bus_write_c22(struct mii_bus *bus, int addr, int regnum,
859 				   u16 val)
860 {
861 	struct ixgbe_adapter *adapter = bus->priv;
862 	struct ixgbe_hw *hw = &adapter->hw;
863 	u32 gssr = hw->phy.phy_semaphore_mask;
864 
865 	return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
866 }
867 
868 /**
869  *  ixgbe_mii_bus_write_c45 - Write a clause 45 register
870  *  @bus: pointer to mii_bus structure which points to our driver private
871  *  @addr: address
872  *  @devad: device address to read
873  *  @regnum: register number
874  *  @val: value to write
875  **/
876 static s32 ixgbe_mii_bus_write_c45(struct mii_bus *bus, int addr, int devad,
877 				   int regnum, u16 val)
878 {
879 	struct ixgbe_adapter *adapter = bus->priv;
880 	struct ixgbe_hw *hw = &adapter->hw;
881 	u32 gssr = hw->phy.phy_semaphore_mask;
882 
883 	return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
884 					       gssr);
885 }
886 
887 /**
888  *  ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a
889  *  @bus: pointer to mii_bus structure which points to our driver private
890  *  @addr: address
891  *  @regnum: register number
892  **/
893 static s32 ixgbe_x550em_a_mii_bus_read_c22(struct mii_bus *bus, int addr,
894 					   int regnum)
895 {
896 	struct ixgbe_adapter *adapter = bus->priv;
897 	struct ixgbe_hw *hw = &adapter->hw;
898 	u32 gssr = hw->phy.phy_semaphore_mask;
899 
900 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
901 	return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
902 }
903 
904 /**
905  *  ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a
906  *  @bus: pointer to mii_bus structure which points to our driver private
907  *  @addr: address
908  *  @devad: device address to read
909  *  @regnum: register number
910  **/
911 static s32 ixgbe_x550em_a_mii_bus_read_c45(struct mii_bus *bus, int addr,
912 					   int devad, int regnum)
913 {
914 	struct ixgbe_adapter *adapter = bus->priv;
915 	struct ixgbe_hw *hw = &adapter->hw;
916 	u32 gssr = hw->phy.phy_semaphore_mask;
917 
918 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
919 	return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
920 }
921 
922 /**
923  *  ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a
924  *  @bus: pointer to mii_bus structure which points to our driver private
925  *  @addr: address
926  *  @regnum: register number
927  *  @val: value to write
928  **/
929 static s32 ixgbe_x550em_a_mii_bus_write_c22(struct mii_bus *bus, int addr,
930 					    int regnum, u16 val)
931 {
932 	struct ixgbe_adapter *adapter = bus->priv;
933 	struct ixgbe_hw *hw = &adapter->hw;
934 	u32 gssr = hw->phy.phy_semaphore_mask;
935 
936 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
937 	return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
938 }
939 
940 /**
941  *  ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a
942  *  @bus: pointer to mii_bus structure which points to our driver private
943  *  @addr: address
944  *  @devad: device address to read
945  *  @regnum: register number
946  *  @val: value to write
947  **/
948 static s32 ixgbe_x550em_a_mii_bus_write_c45(struct mii_bus *bus, int addr,
949 					    int devad, int regnum, u16 val)
950 {
951 	struct ixgbe_adapter *adapter = bus->priv;
952 	struct ixgbe_hw *hw = &adapter->hw;
953 	u32 gssr = hw->phy.phy_semaphore_mask;
954 
955 	gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
956 	return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
957 					       gssr);
958 }
959 
960 /**
961  * ixgbe_get_first_secondary_devfn - get first device downstream of root port
962  * @devfn: PCI_DEVFN of root port on domain 0, bus 0
963  *
964  * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
965  * on domain 0, bus 0, devfn = 'devfn'
966  **/
967 static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
968 {
969 	struct pci_dev *rp_pdev;
970 	int bus;
971 
972 	rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
973 	if (rp_pdev && rp_pdev->subordinate) {
974 		bus = rp_pdev->subordinate->number;
975 		pci_dev_put(rp_pdev);
976 		return pci_get_domain_bus_and_slot(0, bus, 0);
977 	}
978 
979 	pci_dev_put(rp_pdev);
980 	return NULL;
981 }
982 
983 /**
984  * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
985  * @hw: pointer to hardware structure
986  *
987  * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
988  * the SoC.  There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
989  * but we only want to register one MDIO bus.
990  **/
991 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
992 {
993 	struct ixgbe_adapter *adapter = hw->back;
994 	struct pci_dev *pdev = adapter->pdev;
995 	struct pci_dev *func0_pdev;
996 	bool has_mii = false;
997 
998 	/* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
999 	 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
1000 	 * It's not valid for function 0 to be disabled and function 1 is up,
1001 	 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
1002 	 * of those two root ports
1003 	 */
1004 	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
1005 	if (func0_pdev) {
1006 		if (func0_pdev == pdev)
1007 			has_mii = true;
1008 		goto out;
1009 	}
1010 	func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
1011 	if (func0_pdev == pdev)
1012 		has_mii = true;
1013 
1014 out:
1015 	pci_dev_put(func0_pdev);
1016 	return has_mii;
1017 }
1018 
1019 /**
1020  * ixgbe_mii_bus_init - mii_bus structure setup
1021  * @hw: pointer to hardware structure
1022  *
1023  * Returns 0 on success, negative on failure
1024  *
1025  * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
1026  **/
1027 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
1028 {
1029 	s32 (*write_c22)(struct mii_bus *bus, int addr, int regnum, u16 val);
1030 	s32 (*read_c22)(struct mii_bus *bus, int addr, int regnum);
1031 	s32 (*write_c45)(struct mii_bus *bus, int addr, int devad, int regnum,
1032 			 u16 val);
1033 	s32 (*read_c45)(struct mii_bus *bus, int addr, int devad, int regnum);
1034 	struct ixgbe_adapter *adapter = hw->back;
1035 	struct pci_dev *pdev = adapter->pdev;
1036 	struct device *dev = &adapter->netdev->dev;
1037 	struct mii_bus *bus;
1038 
1039 	switch (hw->device_id) {
1040 	/* C3000 SoCs */
1041 	case IXGBE_DEV_ID_X550EM_A_KR:
1042 	case IXGBE_DEV_ID_X550EM_A_KR_L:
1043 	case IXGBE_DEV_ID_X550EM_A_SFP_N:
1044 	case IXGBE_DEV_ID_X550EM_A_SGMII:
1045 	case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1046 	case IXGBE_DEV_ID_X550EM_A_10G_T:
1047 	case IXGBE_DEV_ID_X550EM_A_SFP:
1048 	case IXGBE_DEV_ID_X550EM_A_1G_T:
1049 	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1050 		if (!ixgbe_x550em_a_has_mii(hw))
1051 			return 0;
1052 		read_c22 = ixgbe_x550em_a_mii_bus_read_c22;
1053 		write_c22 = ixgbe_x550em_a_mii_bus_write_c22;
1054 		read_c45 = ixgbe_x550em_a_mii_bus_read_c45;
1055 		write_c45 = ixgbe_x550em_a_mii_bus_write_c45;
1056 		break;
1057 	default:
1058 		read_c22 = ixgbe_mii_bus_read_c22;
1059 		write_c22 = ixgbe_mii_bus_write_c22;
1060 		read_c45 = ixgbe_mii_bus_read_c45;
1061 		write_c45 = ixgbe_mii_bus_write_c45;
1062 		break;
1063 	}
1064 
1065 	bus = devm_mdiobus_alloc(dev);
1066 	if (!bus)
1067 		return -ENOMEM;
1068 
1069 	bus->read = read_c22;
1070 	bus->write = write_c22;
1071 	bus->read_c45 = read_c45;
1072 	bus->write_c45 = write_c45;
1073 
1074 	/* Use the position of the device in the PCI hierarchy as the id */
1075 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
1076 		 pci_name(pdev));
1077 
1078 	bus->name = "ixgbe-mdio";
1079 	bus->priv = adapter;
1080 	bus->parent = dev;
1081 	bus->phy_mask = GENMASK(31, 0);
1082 
1083 	/* Support clause 22/45 natively.  ixgbe_probe() sets MDIO_EMULATE_C22
1084 	 * unfortunately that causes some clause 22 frames to be sent with
1085 	 * clause 45 addressing.  We don't want that.
1086 	 */
1087 	hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
1088 
1089 	adapter->mii_bus = bus;
1090 	return mdiobus_register(bus);
1091 }
1092 
1093 /**
1094  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
1095  *  @hw: pointer to hardware structure
1096  *
1097  *  Restart autonegotiation and PHY and waits for completion.
1098  **/
1099 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
1100 {
1101 	s32 status = 0;
1102 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1103 	bool autoneg = false;
1104 	ixgbe_link_speed speed;
1105 
1106 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1107 
1108 	/* Set or unset auto-negotiation 10G advertisement */
1109 	hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1110 
1111 	autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1112 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
1113 	    (speed & IXGBE_LINK_SPEED_10GB_FULL))
1114 		autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1115 
1116 	hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1117 
1118 	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1119 			     MDIO_MMD_AN, &autoneg_reg);
1120 
1121 	if (hw->mac.type == ixgbe_mac_X550) {
1122 		/* Set or unset auto-negotiation 5G advertisement */
1123 		autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
1124 		if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
1125 		    (speed & IXGBE_LINK_SPEED_5GB_FULL))
1126 			autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
1127 
1128 		/* Set or unset auto-negotiation 2.5G advertisement */
1129 		autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1130 		if ((hw->phy.autoneg_advertised &
1131 		     IXGBE_LINK_SPEED_2_5GB_FULL) &&
1132 		    (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1133 			autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1134 	}
1135 
1136 	/* Set or unset auto-negotiation 1G advertisement */
1137 	autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1138 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1139 	    (speed & IXGBE_LINK_SPEED_1GB_FULL))
1140 		autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1141 
1142 	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1143 			      MDIO_MMD_AN, autoneg_reg);
1144 
1145 	/* Set or unset auto-negotiation 100M advertisement */
1146 	hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1147 
1148 	autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1149 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1150 	    (speed & IXGBE_LINK_SPEED_100_FULL))
1151 		autoneg_reg |= ADVERTISE_100FULL;
1152 
1153 	hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1154 
1155 	/* Blocked by MNG FW so don't reset PHY */
1156 	if (ixgbe_check_reset_blocked(hw))
1157 		return 0;
1158 
1159 	/* Restart PHY autonegotiation and wait for completion */
1160 	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1161 			     MDIO_MMD_AN, &autoneg_reg);
1162 
1163 	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1164 
1165 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1166 			      MDIO_MMD_AN, autoneg_reg);
1167 
1168 	return status;
1169 }
1170 
1171 /**
1172  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1173  *  @hw: pointer to hardware structure
1174  *  @speed: new link speed
1175  *  @autoneg_wait_to_complete: unused
1176  **/
1177 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1178 				       ixgbe_link_speed speed,
1179 				       bool autoneg_wait_to_complete)
1180 {
1181 	/* Clear autoneg_advertised and set new values based on input link
1182 	 * speed.
1183 	 */
1184 	hw->phy.autoneg_advertised = 0;
1185 
1186 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1187 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1188 
1189 	if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1190 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1191 
1192 	if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1193 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1194 
1195 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1196 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1197 
1198 	if (speed & IXGBE_LINK_SPEED_100_FULL)
1199 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1200 
1201 	if (speed & IXGBE_LINK_SPEED_10_FULL)
1202 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1203 
1204 	/* Setup link based on the new speed settings */
1205 	if (hw->phy.ops.setup_link)
1206 		hw->phy.ops.setup_link(hw);
1207 
1208 	return 0;
1209 }
1210 
1211 /**
1212  * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1213  * @hw: pointer to hardware structure
1214  *
1215  * Determines the supported link capabilities by reading the PHY auto
1216  * negotiation register.
1217  */
1218 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1219 {
1220 	u16 speed_ability;
1221 	s32 status;
1222 
1223 	status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1224 				      &speed_ability);
1225 	if (status)
1226 		return status;
1227 
1228 	if (speed_ability & MDIO_SPEED_10G)
1229 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1230 	if (speed_ability & MDIO_PMA_SPEED_1000)
1231 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1232 	if (speed_ability & MDIO_PMA_SPEED_100)
1233 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1234 
1235 	switch (hw->mac.type) {
1236 	case ixgbe_mac_X550:
1237 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1238 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1239 		break;
1240 	case ixgbe_mac_X550EM_x:
1241 	case ixgbe_mac_x550em_a:
1242 		hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1243 		break;
1244 	default:
1245 		break;
1246 	}
1247 
1248 	return 0;
1249 }
1250 
1251 /**
1252  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1253  * @hw: pointer to hardware structure
1254  * @speed: pointer to link speed
1255  * @autoneg: boolean auto-negotiation value
1256  */
1257 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1258 					       ixgbe_link_speed *speed,
1259 					       bool *autoneg)
1260 {
1261 	s32 status = 0;
1262 
1263 	*autoneg = true;
1264 	if (!hw->phy.speeds_supported)
1265 		status = ixgbe_get_copper_speeds_supported(hw);
1266 
1267 	*speed = hw->phy.speeds_supported;
1268 	return status;
1269 }
1270 
1271 /**
1272  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1273  *  @hw: pointer to hardware structure
1274  *  @speed: link speed
1275  *  @link_up: status of link
1276  *
1277  *  Reads the VS1 register to determine if link is up and the current speed for
1278  *  the PHY.
1279  **/
1280 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1281 			     bool *link_up)
1282 {
1283 	s32 status;
1284 	u32 time_out;
1285 	u32 max_time_out = 10;
1286 	u16 phy_link = 0;
1287 	u16 phy_speed = 0;
1288 	u16 phy_data = 0;
1289 
1290 	/* Initialize speed and link to default case */
1291 	*link_up = false;
1292 	*speed = IXGBE_LINK_SPEED_10GB_FULL;
1293 
1294 	/*
1295 	 * Check current speed and link status of the PHY register.
1296 	 * This is a vendor specific register and may have to
1297 	 * be changed for other copper PHYs.
1298 	 */
1299 	for (time_out = 0; time_out < max_time_out; time_out++) {
1300 		udelay(10);
1301 		status = hw->phy.ops.read_reg(hw,
1302 					      MDIO_STAT1,
1303 					      MDIO_MMD_VEND1,
1304 					      &phy_data);
1305 		phy_link = phy_data &
1306 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1307 		phy_speed = phy_data &
1308 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1309 		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1310 			*link_up = true;
1311 			if (phy_speed ==
1312 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1313 				*speed = IXGBE_LINK_SPEED_1GB_FULL;
1314 			break;
1315 		}
1316 	}
1317 
1318 	return status;
1319 }
1320 
1321 /**
1322  *	ixgbe_setup_phy_link_tnx - Set and restart autoneg
1323  *	@hw: pointer to hardware structure
1324  *
1325  *	Restart autonegotiation and PHY and waits for completion.
1326  *      This function always returns success, this is nessary since
1327  *	it is called via a function pointer that could call other
1328  *	functions that could return an error.
1329  **/
1330 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1331 {
1332 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1333 	bool autoneg = false;
1334 	ixgbe_link_speed speed;
1335 
1336 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1337 
1338 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1339 		/* Set or unset auto-negotiation 10G advertisement */
1340 		hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1341 				     MDIO_MMD_AN,
1342 				     &autoneg_reg);
1343 
1344 		autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1345 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1346 			autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1347 
1348 		hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1349 				      MDIO_MMD_AN,
1350 				      autoneg_reg);
1351 	}
1352 
1353 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1354 		/* Set or unset auto-negotiation 1G advertisement */
1355 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1356 				     MDIO_MMD_AN,
1357 				     &autoneg_reg);
1358 
1359 		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1360 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1361 			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1362 
1363 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1364 				      MDIO_MMD_AN,
1365 				      autoneg_reg);
1366 	}
1367 
1368 	if (speed & IXGBE_LINK_SPEED_100_FULL) {
1369 		/* Set or unset auto-negotiation 100M advertisement */
1370 		hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1371 				     MDIO_MMD_AN,
1372 				     &autoneg_reg);
1373 
1374 		autoneg_reg &= ~(ADVERTISE_100FULL |
1375 				 ADVERTISE_100HALF);
1376 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1377 			autoneg_reg |= ADVERTISE_100FULL;
1378 
1379 		hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1380 				      MDIO_MMD_AN,
1381 				      autoneg_reg);
1382 	}
1383 
1384 	/* Blocked by MNG FW so don't reset PHY */
1385 	if (ixgbe_check_reset_blocked(hw))
1386 		return 0;
1387 
1388 	/* Restart PHY autonegotiation and wait for completion */
1389 	hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1390 			     MDIO_MMD_AN, &autoneg_reg);
1391 
1392 	autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1393 
1394 	hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1395 			      MDIO_MMD_AN, autoneg_reg);
1396 	return 0;
1397 }
1398 
1399 /**
1400  *  ixgbe_reset_phy_nl - Performs a PHY reset
1401  *  @hw: pointer to hardware structure
1402  **/
1403 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1404 {
1405 	u16 phy_offset, control, eword, edata, block_crc;
1406 	bool end_data = false;
1407 	u16 list_offset, data_offset;
1408 	u16 phy_data = 0;
1409 	s32 ret_val;
1410 	u32 i;
1411 
1412 	/* Blocked by MNG FW so bail */
1413 	if (ixgbe_check_reset_blocked(hw))
1414 		return 0;
1415 
1416 	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1417 
1418 	/* reset the PHY and poll for completion */
1419 	hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1420 			      (phy_data | MDIO_CTRL1_RESET));
1421 
1422 	for (i = 0; i < 100; i++) {
1423 		hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1424 				     &phy_data);
1425 		if ((phy_data & MDIO_CTRL1_RESET) == 0)
1426 			break;
1427 		usleep_range(10000, 20000);
1428 	}
1429 
1430 	if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1431 		hw_dbg(hw, "PHY reset did not complete.\n");
1432 		return -EIO;
1433 	}
1434 
1435 	/* Get init offsets */
1436 	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1437 						      &data_offset);
1438 	if (ret_val)
1439 		return ret_val;
1440 
1441 	ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1442 	data_offset++;
1443 	while (!end_data) {
1444 		/*
1445 		 * Read control word from PHY init contents offset
1446 		 */
1447 		ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1448 		if (ret_val)
1449 			goto err_eeprom;
1450 		control = (eword & IXGBE_CONTROL_MASK_NL) >>
1451 			   IXGBE_CONTROL_SHIFT_NL;
1452 		edata = eword & IXGBE_DATA_MASK_NL;
1453 		switch (control) {
1454 		case IXGBE_DELAY_NL:
1455 			data_offset++;
1456 			hw_dbg(hw, "DELAY: %d MS\n", edata);
1457 			usleep_range(edata * 1000, edata * 2000);
1458 			break;
1459 		case IXGBE_DATA_NL:
1460 			hw_dbg(hw, "DATA:\n");
1461 			data_offset++;
1462 			ret_val = hw->eeprom.ops.read(hw, data_offset++,
1463 						      &phy_offset);
1464 			if (ret_val)
1465 				goto err_eeprom;
1466 			for (i = 0; i < edata; i++) {
1467 				ret_val = hw->eeprom.ops.read(hw, data_offset,
1468 							      &eword);
1469 				if (ret_val)
1470 					goto err_eeprom;
1471 				hw->phy.ops.write_reg(hw, phy_offset,
1472 						      MDIO_MMD_PMAPMD, eword);
1473 				hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1474 				       phy_offset);
1475 				data_offset++;
1476 				phy_offset++;
1477 			}
1478 			break;
1479 		case IXGBE_CONTROL_NL:
1480 			data_offset++;
1481 			hw_dbg(hw, "CONTROL:\n");
1482 			if (edata == IXGBE_CONTROL_EOL_NL) {
1483 				hw_dbg(hw, "EOL\n");
1484 				end_data = true;
1485 			} else if (edata == IXGBE_CONTROL_SOL_NL) {
1486 				hw_dbg(hw, "SOL\n");
1487 			} else {
1488 				hw_dbg(hw, "Bad control value\n");
1489 				return -EIO;
1490 			}
1491 			break;
1492 		default:
1493 			hw_dbg(hw, "Bad control type\n");
1494 			return -EIO;
1495 		}
1496 	}
1497 
1498 	return ret_val;
1499 
1500 err_eeprom:
1501 	hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1502 	return -EIO;
1503 }
1504 
1505 /**
1506  *  ixgbe_identify_module_generic - Identifies module type
1507  *  @hw: pointer to hardware structure
1508  *
1509  *  Determines HW type and calls appropriate function.
1510  **/
1511 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1512 {
1513 	switch (hw->mac.ops.get_media_type(hw)) {
1514 	case ixgbe_media_type_fiber:
1515 		return ixgbe_identify_sfp_module_generic(hw);
1516 	case ixgbe_media_type_fiber_qsfp:
1517 		return ixgbe_identify_qsfp_module_generic(hw);
1518 	default:
1519 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1520 		return -ENOENT;
1521 	}
1522 
1523 	return -ENOENT;
1524 }
1525 
1526 /**
1527  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1528  *  @hw: pointer to hardware structure
1529  *
1530  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1531  **/
1532 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1533 {
1534 	struct ixgbe_adapter *adapter = hw->back;
1535 	s32 status;
1536 	u32 vendor_oui = 0;
1537 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1538 	u8 identifier = 0;
1539 	u8 comp_codes_1g = 0;
1540 	u8 comp_codes_10g = 0;
1541 	u8 oui_bytes[3] = {0, 0, 0};
1542 	u8 cable_tech = 0;
1543 	u8 cable_spec = 0;
1544 	u16 enforce_sfp = 0;
1545 
1546 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1547 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1548 		return -ENOENT;
1549 	}
1550 
1551 	/* LAN ID is needed for sfp_type determination */
1552 	hw->mac.ops.set_lan_id(hw);
1553 
1554 	status = hw->phy.ops.read_i2c_eeprom(hw,
1555 					     IXGBE_SFF_IDENTIFIER,
1556 					     &identifier);
1557 
1558 	if (status)
1559 		goto err_read_i2c_eeprom;
1560 
1561 	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1562 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1563 		return -EOPNOTSUPP;
1564 	}
1565 	status = hw->phy.ops.read_i2c_eeprom(hw,
1566 					     IXGBE_SFF_1GBE_COMP_CODES,
1567 					     &comp_codes_1g);
1568 
1569 	if (status)
1570 		goto err_read_i2c_eeprom;
1571 
1572 	status = hw->phy.ops.read_i2c_eeprom(hw,
1573 					     IXGBE_SFF_10GBE_COMP_CODES,
1574 					     &comp_codes_10g);
1575 
1576 	if (status)
1577 		goto err_read_i2c_eeprom;
1578 	status = hw->phy.ops.read_i2c_eeprom(hw,
1579 					     IXGBE_SFF_CABLE_TECHNOLOGY,
1580 					     &cable_tech);
1581 
1582 	if (status)
1583 		goto err_read_i2c_eeprom;
1584 
1585 	 /* ID Module
1586 	  * =========
1587 	  * 0   SFP_DA_CU
1588 	  * 1   SFP_SR
1589 	  * 2   SFP_LR
1590 	  * 3   SFP_DA_CORE0 - 82599-specific
1591 	  * 4   SFP_DA_CORE1 - 82599-specific
1592 	  * 5   SFP_SR/LR_CORE0 - 82599-specific
1593 	  * 6   SFP_SR/LR_CORE1 - 82599-specific
1594 	  * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1595 	  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1596 	  * 9   SFP_1g_cu_CORE0 - 82599-specific
1597 	  * 10  SFP_1g_cu_CORE1 - 82599-specific
1598 	  * 11  SFP_1g_sx_CORE0 - 82599-specific
1599 	  * 12  SFP_1g_sx_CORE1 - 82599-specific
1600 	  */
1601 	if (hw->mac.type == ixgbe_mac_82598EB) {
1602 		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1603 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1604 		else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1605 			hw->phy.sfp_type = ixgbe_sfp_type_sr;
1606 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1607 			hw->phy.sfp_type = ixgbe_sfp_type_lr;
1608 		else
1609 			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1610 	} else {
1611 		if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1612 			if (hw->bus.lan_id == 0)
1613 				hw->phy.sfp_type =
1614 					     ixgbe_sfp_type_da_cu_core0;
1615 			else
1616 				hw->phy.sfp_type =
1617 					     ixgbe_sfp_type_da_cu_core1;
1618 		} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1619 			hw->phy.ops.read_i2c_eeprom(
1620 					hw, IXGBE_SFF_CABLE_SPEC_COMP,
1621 					&cable_spec);
1622 			if (cable_spec &
1623 			    IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1624 				if (hw->bus.lan_id == 0)
1625 					hw->phy.sfp_type =
1626 					ixgbe_sfp_type_da_act_lmt_core0;
1627 				else
1628 					hw->phy.sfp_type =
1629 					ixgbe_sfp_type_da_act_lmt_core1;
1630 			} else {
1631 				hw->phy.sfp_type =
1632 						ixgbe_sfp_type_unknown;
1633 			}
1634 		} else if (comp_codes_10g &
1635 			   (IXGBE_SFF_10GBASESR_CAPABLE |
1636 			    IXGBE_SFF_10GBASELR_CAPABLE)) {
1637 			if (hw->bus.lan_id == 0)
1638 				hw->phy.sfp_type =
1639 					      ixgbe_sfp_type_srlr_core0;
1640 			else
1641 				hw->phy.sfp_type =
1642 					      ixgbe_sfp_type_srlr_core1;
1643 		} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1644 			if (hw->bus.lan_id == 0)
1645 				hw->phy.sfp_type =
1646 					ixgbe_sfp_type_1g_cu_core0;
1647 			else
1648 				hw->phy.sfp_type =
1649 					ixgbe_sfp_type_1g_cu_core1;
1650 		} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1651 			if (hw->bus.lan_id == 0)
1652 				hw->phy.sfp_type =
1653 					ixgbe_sfp_type_1g_sx_core0;
1654 			else
1655 				hw->phy.sfp_type =
1656 					ixgbe_sfp_type_1g_sx_core1;
1657 		} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1658 			if (hw->bus.lan_id == 0)
1659 				hw->phy.sfp_type =
1660 					ixgbe_sfp_type_1g_lx_core0;
1661 			else
1662 				hw->phy.sfp_type =
1663 					ixgbe_sfp_type_1g_lx_core1;
1664 		} else {
1665 			hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1666 		}
1667 	}
1668 
1669 	if (hw->phy.sfp_type != stored_sfp_type)
1670 		hw->phy.sfp_setup_needed = true;
1671 
1672 	/* Determine if the SFP+ PHY is dual speed or not. */
1673 	hw->phy.multispeed_fiber = false;
1674 	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1675 	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1676 	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1677 	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1678 		hw->phy.multispeed_fiber = true;
1679 
1680 	/* Determine PHY vendor */
1681 	if (hw->phy.type != ixgbe_phy_nl) {
1682 		hw->phy.id = identifier;
1683 		status = hw->phy.ops.read_i2c_eeprom(hw,
1684 					    IXGBE_SFF_VENDOR_OUI_BYTE0,
1685 					    &oui_bytes[0]);
1686 
1687 		if (status != 0)
1688 			goto err_read_i2c_eeprom;
1689 
1690 		status = hw->phy.ops.read_i2c_eeprom(hw,
1691 					    IXGBE_SFF_VENDOR_OUI_BYTE1,
1692 					    &oui_bytes[1]);
1693 
1694 		if (status != 0)
1695 			goto err_read_i2c_eeprom;
1696 
1697 		status = hw->phy.ops.read_i2c_eeprom(hw,
1698 					    IXGBE_SFF_VENDOR_OUI_BYTE2,
1699 					    &oui_bytes[2]);
1700 
1701 		if (status != 0)
1702 			goto err_read_i2c_eeprom;
1703 
1704 		vendor_oui =
1705 		  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1706 		   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1707 		   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1708 
1709 		switch (vendor_oui) {
1710 		case IXGBE_SFF_VENDOR_OUI_TYCO:
1711 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1712 				hw->phy.type =
1713 					    ixgbe_phy_sfp_passive_tyco;
1714 			break;
1715 		case IXGBE_SFF_VENDOR_OUI_FTL:
1716 			if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1717 				hw->phy.type = ixgbe_phy_sfp_ftl_active;
1718 			else
1719 				hw->phy.type = ixgbe_phy_sfp_ftl;
1720 			break;
1721 		case IXGBE_SFF_VENDOR_OUI_AVAGO:
1722 			hw->phy.type = ixgbe_phy_sfp_avago;
1723 			break;
1724 		case IXGBE_SFF_VENDOR_OUI_INTEL:
1725 			hw->phy.type = ixgbe_phy_sfp_intel;
1726 			break;
1727 		default:
1728 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1729 				hw->phy.type =
1730 					 ixgbe_phy_sfp_passive_unknown;
1731 			else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1732 				hw->phy.type =
1733 					ixgbe_phy_sfp_active_unknown;
1734 			else
1735 				hw->phy.type = ixgbe_phy_sfp_unknown;
1736 			break;
1737 		}
1738 	}
1739 
1740 	/* Allow any DA cable vendor */
1741 	if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1742 	    IXGBE_SFF_DA_ACTIVE_CABLE))
1743 		return 0;
1744 
1745 	/* Verify supported 1G SFP modules */
1746 	if (comp_codes_10g == 0 &&
1747 	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1748 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1749 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1750 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1751 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1752 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1753 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1754 		return -EOPNOTSUPP;
1755 	}
1756 
1757 	/* Anything else 82598-based is supported */
1758 	if (hw->mac.type == ixgbe_mac_82598EB)
1759 		return 0;
1760 
1761 	hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1762 	if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1763 	    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1764 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1765 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1766 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1767 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1768 	      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1769 		/* Make sure we're a supported PHY type */
1770 		if (hw->phy.type == ixgbe_phy_sfp_intel)
1771 			return 0;
1772 		if (hw->allow_unsupported_sfp) {
1773 			e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1774 			return 0;
1775 		}
1776 		hw_dbg(hw, "SFP+ module not supported\n");
1777 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1778 		return -EOPNOTSUPP;
1779 	}
1780 	return 0;
1781 
1782 err_read_i2c_eeprom:
1783 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1784 	if (hw->phy.type != ixgbe_phy_nl) {
1785 		hw->phy.id = 0;
1786 		hw->phy.type = ixgbe_phy_unknown;
1787 	}
1788 	return -ENOENT;
1789 }
1790 
1791 /**
1792  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1793  * @hw: pointer to hardware structure
1794  *
1795  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1796  **/
1797 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1798 {
1799 	struct ixgbe_adapter *adapter = hw->back;
1800 	s32 status;
1801 	u32 vendor_oui = 0;
1802 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1803 	u8 identifier = 0;
1804 	u8 comp_codes_1g = 0;
1805 	u8 comp_codes_10g = 0;
1806 	u8 oui_bytes[3] = {0, 0, 0};
1807 	u16 enforce_sfp = 0;
1808 	u8 connector = 0;
1809 	u8 cable_length = 0;
1810 	u8 device_tech = 0;
1811 	bool active_cable = false;
1812 
1813 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1814 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1815 		return -ENOENT;
1816 	}
1817 
1818 	/* LAN ID is needed for sfp_type determination */
1819 	hw->mac.ops.set_lan_id(hw);
1820 
1821 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1822 					     &identifier);
1823 
1824 	if (status != 0)
1825 		goto err_read_i2c_eeprom;
1826 
1827 	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1828 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1829 		return -EOPNOTSUPP;
1830 	}
1831 
1832 	hw->phy.id = identifier;
1833 
1834 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1835 					     &comp_codes_10g);
1836 
1837 	if (status != 0)
1838 		goto err_read_i2c_eeprom;
1839 
1840 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1841 					     &comp_codes_1g);
1842 
1843 	if (status != 0)
1844 		goto err_read_i2c_eeprom;
1845 
1846 	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1847 		hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1848 		if (hw->bus.lan_id == 0)
1849 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1850 		else
1851 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1852 	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1853 				     IXGBE_SFF_10GBASELR_CAPABLE)) {
1854 		if (hw->bus.lan_id == 0)
1855 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1856 		else
1857 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1858 	} else {
1859 		if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1860 			active_cable = true;
1861 
1862 		if (!active_cable) {
1863 			/* check for active DA cables that pre-date
1864 			 * SFF-8436 v3.6
1865 			 */
1866 			hw->phy.ops.read_i2c_eeprom(hw,
1867 					IXGBE_SFF_QSFP_CONNECTOR,
1868 					&connector);
1869 
1870 			hw->phy.ops.read_i2c_eeprom(hw,
1871 					IXGBE_SFF_QSFP_CABLE_LENGTH,
1872 					&cable_length);
1873 
1874 			hw->phy.ops.read_i2c_eeprom(hw,
1875 					IXGBE_SFF_QSFP_DEVICE_TECH,
1876 					&device_tech);
1877 
1878 			if ((connector ==
1879 				     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1880 			    (cable_length > 0) &&
1881 			    ((device_tech >> 4) ==
1882 				     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1883 				active_cable = true;
1884 		}
1885 
1886 		if (active_cable) {
1887 			hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1888 			if (hw->bus.lan_id == 0)
1889 				hw->phy.sfp_type =
1890 						ixgbe_sfp_type_da_act_lmt_core0;
1891 			else
1892 				hw->phy.sfp_type =
1893 						ixgbe_sfp_type_da_act_lmt_core1;
1894 		} else {
1895 			/* unsupported module type */
1896 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1897 			return -EOPNOTSUPP;
1898 		}
1899 	}
1900 
1901 	if (hw->phy.sfp_type != stored_sfp_type)
1902 		hw->phy.sfp_setup_needed = true;
1903 
1904 	/* Determine if the QSFP+ PHY is dual speed or not. */
1905 	hw->phy.multispeed_fiber = false;
1906 	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1907 	     (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1908 	    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1909 	     (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1910 		hw->phy.multispeed_fiber = true;
1911 
1912 	/* Determine PHY vendor for optical modules */
1913 	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1914 			      IXGBE_SFF_10GBASELR_CAPABLE)) {
1915 		status = hw->phy.ops.read_i2c_eeprom(hw,
1916 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1917 					&oui_bytes[0]);
1918 
1919 		if (status != 0)
1920 			goto err_read_i2c_eeprom;
1921 
1922 		status = hw->phy.ops.read_i2c_eeprom(hw,
1923 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1924 					&oui_bytes[1]);
1925 
1926 		if (status != 0)
1927 			goto err_read_i2c_eeprom;
1928 
1929 		status = hw->phy.ops.read_i2c_eeprom(hw,
1930 					IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1931 					&oui_bytes[2]);
1932 
1933 		if (status != 0)
1934 			goto err_read_i2c_eeprom;
1935 
1936 		vendor_oui =
1937 			((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1938 			 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1939 			 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1940 
1941 		if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1942 			hw->phy.type = ixgbe_phy_qsfp_intel;
1943 		else
1944 			hw->phy.type = ixgbe_phy_qsfp_unknown;
1945 
1946 		hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1947 		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1948 			/* Make sure we're a supported PHY type */
1949 			if (hw->phy.type == ixgbe_phy_qsfp_intel)
1950 				return 0;
1951 			if (hw->allow_unsupported_sfp) {
1952 				e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1953 				return 0;
1954 			}
1955 			hw_dbg(hw, "QSFP module not supported\n");
1956 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1957 			return -EOPNOTSUPP;
1958 		}
1959 		return 0;
1960 	}
1961 	return 0;
1962 
1963 err_read_i2c_eeprom:
1964 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1965 	hw->phy.id = 0;
1966 	hw->phy.type = ixgbe_phy_unknown;
1967 
1968 	return -ENOENT;
1969 }
1970 
1971 /**
1972  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1973  *  @hw: pointer to hardware structure
1974  *  @list_offset: offset to the SFP ID list
1975  *  @data_offset: offset to the SFP data block
1976  *
1977  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1978  *  so it returns the offsets to the phy init sequence block.
1979  **/
1980 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1981 					u16 *list_offset,
1982 					u16 *data_offset)
1983 {
1984 	u16 sfp_id;
1985 	u16 sfp_type = hw->phy.sfp_type;
1986 
1987 	if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1988 		return -EOPNOTSUPP;
1989 
1990 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1991 		return -ENOENT;
1992 
1993 	if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1994 	    (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1995 		return -EOPNOTSUPP;
1996 
1997 	/*
1998 	 * Limiting active cables and 1G Phys must be initialized as
1999 	 * SR modules
2000 	 */
2001 	if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
2002 	    sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2003 	    sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
2004 	    sfp_type == ixgbe_sfp_type_1g_sx_core0)
2005 		sfp_type = ixgbe_sfp_type_srlr_core0;
2006 	else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
2007 		 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
2008 		 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
2009 		 sfp_type == ixgbe_sfp_type_1g_sx_core1)
2010 		sfp_type = ixgbe_sfp_type_srlr_core1;
2011 
2012 	/* Read offset to PHY init contents */
2013 	if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
2014 		hw_err(hw, "eeprom read at %d failed\n",
2015 		       IXGBE_PHY_INIT_OFFSET_NL);
2016 		return -EIO;
2017 	}
2018 
2019 	if ((!*list_offset) || (*list_offset == 0xFFFF))
2020 		return -EIO;
2021 
2022 	/* Shift offset to first ID word */
2023 	(*list_offset)++;
2024 
2025 	/*
2026 	 * Find the matching SFP ID in the EEPROM
2027 	 * and program the init sequence
2028 	 */
2029 	if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2030 		goto err_phy;
2031 
2032 	while (sfp_id != IXGBE_PHY_INIT_END_NL) {
2033 		if (sfp_id == sfp_type) {
2034 			(*list_offset)++;
2035 			if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
2036 				goto err_phy;
2037 			if ((!*data_offset) || (*data_offset == 0xFFFF)) {
2038 				hw_dbg(hw, "SFP+ module not supported\n");
2039 				return -EOPNOTSUPP;
2040 			} else {
2041 				break;
2042 			}
2043 		} else {
2044 			(*list_offset) += 2;
2045 			if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2046 				goto err_phy;
2047 		}
2048 	}
2049 
2050 	if (sfp_id == IXGBE_PHY_INIT_END_NL) {
2051 		hw_dbg(hw, "No matching SFP+ module found\n");
2052 		return -EOPNOTSUPP;
2053 	}
2054 
2055 	return 0;
2056 
2057 err_phy:
2058 	hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
2059 	return -EIO;
2060 }
2061 
2062 /**
2063  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
2064  *  @hw: pointer to hardware structure
2065  *  @byte_offset: EEPROM byte offset to read
2066  *  @eeprom_data: value read
2067  *
2068  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
2069  **/
2070 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2071 				  u8 *eeprom_data)
2072 {
2073 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2074 					 IXGBE_I2C_EEPROM_DEV_ADDR,
2075 					 eeprom_data);
2076 }
2077 
2078 /**
2079  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2080  *  @hw: pointer to hardware structure
2081  *  @byte_offset: byte offset at address 0xA2
2082  *  @sff8472_data: value read
2083  *
2084  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
2085  **/
2086 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2087 				   u8 *sff8472_data)
2088 {
2089 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2090 					 IXGBE_I2C_EEPROM_DEV_ADDR2,
2091 					 sff8472_data);
2092 }
2093 
2094 /**
2095  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2096  *  @hw: pointer to hardware structure
2097  *  @byte_offset: EEPROM byte offset to write
2098  *  @eeprom_data: value to write
2099  *
2100  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
2101  **/
2102 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2103 				   u8 eeprom_data)
2104 {
2105 	return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2106 					  IXGBE_I2C_EEPROM_DEV_ADDR,
2107 					  eeprom_data);
2108 }
2109 
2110 /**
2111  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2112  * @hw: pointer to hardware structure
2113  * @offset: eeprom offset to be read
2114  * @addr: I2C address to be read
2115  */
2116 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2117 {
2118 	if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2119 	    offset == IXGBE_SFF_IDENTIFIER &&
2120 	    hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2121 		return true;
2122 	return false;
2123 }
2124 
2125 /**
2126  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2127  *  @hw: pointer to hardware structure
2128  *  @byte_offset: byte offset to read
2129  *  @dev_addr: device address
2130  *  @data: value read
2131  *  @lock: true if to take and release semaphore
2132  *
2133  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2134  *  a specified device address.
2135  */
2136 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2137 					   u8 dev_addr, u8 *data, bool lock)
2138 {
2139 	s32 status;
2140 	u32 max_retry = 10;
2141 	u32 retry = 0;
2142 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2143 	bool nack = true;
2144 
2145 	if (hw->mac.type >= ixgbe_mac_X550)
2146 		max_retry = 3;
2147 	if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2148 		max_retry = IXGBE_SFP_DETECT_RETRIES;
2149 
2150 	*data = 0;
2151 
2152 	do {
2153 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2154 			return -EBUSY;
2155 
2156 		ixgbe_i2c_start(hw);
2157 
2158 		/* Device Address and write indication */
2159 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2160 		if (status != 0)
2161 			goto fail;
2162 
2163 		status = ixgbe_get_i2c_ack(hw);
2164 		if (status != 0)
2165 			goto fail;
2166 
2167 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2168 		if (status != 0)
2169 			goto fail;
2170 
2171 		status = ixgbe_get_i2c_ack(hw);
2172 		if (status != 0)
2173 			goto fail;
2174 
2175 		ixgbe_i2c_start(hw);
2176 
2177 		/* Device Address and read indication */
2178 		status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2179 		if (status != 0)
2180 			goto fail;
2181 
2182 		status = ixgbe_get_i2c_ack(hw);
2183 		if (status != 0)
2184 			goto fail;
2185 
2186 		status = ixgbe_clock_in_i2c_byte(hw, data);
2187 		if (status != 0)
2188 			goto fail;
2189 
2190 		status = ixgbe_clock_out_i2c_bit(hw, nack);
2191 		if (status != 0)
2192 			goto fail;
2193 
2194 		ixgbe_i2c_stop(hw);
2195 		if (lock)
2196 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2197 		return 0;
2198 
2199 fail:
2200 		ixgbe_i2c_bus_clear(hw);
2201 		if (lock) {
2202 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2203 			msleep(100);
2204 		}
2205 		retry++;
2206 		if (retry < max_retry)
2207 			hw_dbg(hw, "I2C byte read error - Retrying.\n");
2208 		else
2209 			hw_dbg(hw, "I2C byte read error.\n");
2210 
2211 	} while (retry < max_retry);
2212 
2213 	return status;
2214 }
2215 
2216 /**
2217  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2218  *  @hw: pointer to hardware structure
2219  *  @byte_offset: byte offset to read
2220  *  @dev_addr: device address
2221  *  @data: value read
2222  *
2223  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2224  *  a specified device address.
2225  */
2226 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2227 				u8 dev_addr, u8 *data)
2228 {
2229 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2230 					       data, true);
2231 }
2232 
2233 /**
2234  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2235  *  @hw: pointer to hardware structure
2236  *  @byte_offset: byte offset to read
2237  *  @dev_addr: device address
2238  *  @data: value read
2239  *
2240  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2241  *  a specified device address.
2242  */
2243 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2244 					 u8 dev_addr, u8 *data)
2245 {
2246 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2247 					       data, false);
2248 }
2249 
2250 /**
2251  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2252  *  @hw: pointer to hardware structure
2253  *  @byte_offset: byte offset to write
2254  *  @dev_addr: device address
2255  *  @data: value to write
2256  *  @lock: true if to take and release semaphore
2257  *
2258  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2259  *  a specified device address.
2260  */
2261 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2262 					    u8 dev_addr, u8 data, bool lock)
2263 {
2264 	s32 status;
2265 	u32 max_retry = 1;
2266 	u32 retry = 0;
2267 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2268 
2269 	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2270 		return -EBUSY;
2271 
2272 	do {
2273 		ixgbe_i2c_start(hw);
2274 
2275 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2276 		if (status != 0)
2277 			goto fail;
2278 
2279 		status = ixgbe_get_i2c_ack(hw);
2280 		if (status != 0)
2281 			goto fail;
2282 
2283 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2284 		if (status != 0)
2285 			goto fail;
2286 
2287 		status = ixgbe_get_i2c_ack(hw);
2288 		if (status != 0)
2289 			goto fail;
2290 
2291 		status = ixgbe_clock_out_i2c_byte(hw, data);
2292 		if (status != 0)
2293 			goto fail;
2294 
2295 		status = ixgbe_get_i2c_ack(hw);
2296 		if (status != 0)
2297 			goto fail;
2298 
2299 		ixgbe_i2c_stop(hw);
2300 		if (lock)
2301 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2302 		return 0;
2303 
2304 fail:
2305 		ixgbe_i2c_bus_clear(hw);
2306 		retry++;
2307 		if (retry < max_retry)
2308 			hw_dbg(hw, "I2C byte write error - Retrying.\n");
2309 		else
2310 			hw_dbg(hw, "I2C byte write error.\n");
2311 	} while (retry < max_retry);
2312 
2313 	if (lock)
2314 		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2315 
2316 	return status;
2317 }
2318 
2319 /**
2320  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2321  *  @hw: pointer to hardware structure
2322  *  @byte_offset: byte offset to write
2323  *  @dev_addr: device address
2324  *  @data: value to write
2325  *
2326  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2327  *  a specified device address.
2328  */
2329 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2330 				 u8 dev_addr, u8 data)
2331 {
2332 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2333 						data, true);
2334 }
2335 
2336 /**
2337  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2338  *  @hw: pointer to hardware structure
2339  *  @byte_offset: byte offset to write
2340  *  @dev_addr: device address
2341  *  @data: value to write
2342  *
2343  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2344  *  a specified device address.
2345  */
2346 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2347 					  u8 dev_addr, u8 data)
2348 {
2349 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2350 						data, false);
2351 }
2352 
2353 /**
2354  *  ixgbe_i2c_start - Sets I2C start condition
2355  *  @hw: pointer to hardware structure
2356  *
2357  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2358  *  Set bit-bang mode on X550 hardware.
2359  **/
2360 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2361 {
2362 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2363 
2364 	i2cctl |= IXGBE_I2C_BB_EN(hw);
2365 
2366 	/* Start condition must begin with data and clock high */
2367 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2368 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2369 
2370 	/* Setup time for start condition (4.7us) */
2371 	udelay(IXGBE_I2C_T_SU_STA);
2372 
2373 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
2374 
2375 	/* Hold time for start condition (4us) */
2376 	udelay(IXGBE_I2C_T_HD_STA);
2377 
2378 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2379 
2380 	/* Minimum low period of clock is 4.7 us */
2381 	udelay(IXGBE_I2C_T_LOW);
2382 
2383 }
2384 
2385 /**
2386  *  ixgbe_i2c_stop - Sets I2C stop condition
2387  *  @hw: pointer to hardware structure
2388  *
2389  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2390  *  Disables bit-bang mode and negates data output enable on X550
2391  *  hardware.
2392  **/
2393 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2394 {
2395 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2396 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2397 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2398 	u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2399 
2400 	/* Stop condition must begin with data low and clock high */
2401 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
2402 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2403 
2404 	/* Setup time for stop condition (4us) */
2405 	udelay(IXGBE_I2C_T_SU_STO);
2406 
2407 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2408 
2409 	/* bus free time between stop and start (4.7us)*/
2410 	udelay(IXGBE_I2C_T_BUF);
2411 
2412 	if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2413 		i2cctl &= ~bb_en_bit;
2414 		i2cctl |= data_oe_bit | clk_oe_bit;
2415 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2416 		IXGBE_WRITE_FLUSH(hw);
2417 	}
2418 }
2419 
2420 /**
2421  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2422  *  @hw: pointer to hardware structure
2423  *  @data: data byte to clock in
2424  *
2425  *  Clocks in one byte data via I2C data/clock
2426  **/
2427 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2428 {
2429 	s32 i;
2430 	bool bit = false;
2431 
2432 	*data = 0;
2433 	for (i = 7; i >= 0; i--) {
2434 		ixgbe_clock_in_i2c_bit(hw, &bit);
2435 		*data |= bit << i;
2436 	}
2437 
2438 	return 0;
2439 }
2440 
2441 /**
2442  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2443  *  @hw: pointer to hardware structure
2444  *  @data: data byte clocked out
2445  *
2446  *  Clocks out one byte data via I2C data/clock
2447  **/
2448 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2449 {
2450 	s32 status;
2451 	s32 i;
2452 	u32 i2cctl;
2453 	bool bit = false;
2454 
2455 	for (i = 7; i >= 0; i--) {
2456 		bit = (data >> i) & 0x1;
2457 		status = ixgbe_clock_out_i2c_bit(hw, bit);
2458 
2459 		if (status != 0)
2460 			break;
2461 	}
2462 
2463 	/* Release SDA line (set high) */
2464 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2465 	i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2466 	i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2467 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2468 	IXGBE_WRITE_FLUSH(hw);
2469 
2470 	return status;
2471 }
2472 
2473 /**
2474  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2475  *  @hw: pointer to hardware structure
2476  *
2477  *  Clocks in/out one bit via I2C data/clock
2478  **/
2479 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2480 {
2481 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2482 	s32 status = 0;
2483 	u32 i = 0;
2484 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2485 	u32 timeout = 10;
2486 	bool ack = true;
2487 
2488 	if (data_oe_bit) {
2489 		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2490 		i2cctl |= data_oe_bit;
2491 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2492 		IXGBE_WRITE_FLUSH(hw);
2493 	}
2494 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2495 
2496 	/* Minimum high period of clock is 4us */
2497 	udelay(IXGBE_I2C_T_HIGH);
2498 
2499 	/* Poll for ACK.  Note that ACK in I2C spec is
2500 	 * transition from 1 to 0 */
2501 	for (i = 0; i < timeout; i++) {
2502 		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2503 		ack = ixgbe_get_i2c_data(hw, &i2cctl);
2504 
2505 		udelay(1);
2506 		if (ack == 0)
2507 			break;
2508 	}
2509 
2510 	if (ack == 1) {
2511 		hw_dbg(hw, "I2C ack was not received.\n");
2512 		status = -EIO;
2513 	}
2514 
2515 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2516 
2517 	/* Minimum low period of clock is 4.7 us */
2518 	udelay(IXGBE_I2C_T_LOW);
2519 
2520 	return status;
2521 }
2522 
2523 /**
2524  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2525  *  @hw: pointer to hardware structure
2526  *  @data: read data value
2527  *
2528  *  Clocks in one bit via I2C data/clock
2529  **/
2530 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2531 {
2532 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2533 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2534 
2535 	if (data_oe_bit) {
2536 		i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2537 		i2cctl |= data_oe_bit;
2538 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2539 		IXGBE_WRITE_FLUSH(hw);
2540 	}
2541 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2542 
2543 	/* Minimum high period of clock is 4us */
2544 	udelay(IXGBE_I2C_T_HIGH);
2545 
2546 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2547 	*data = ixgbe_get_i2c_data(hw, &i2cctl);
2548 
2549 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2550 
2551 	/* Minimum low period of clock is 4.7 us */
2552 	udelay(IXGBE_I2C_T_LOW);
2553 
2554 	return 0;
2555 }
2556 
2557 /**
2558  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2559  *  @hw: pointer to hardware structure
2560  *  @data: data value to write
2561  *
2562  *  Clocks out one bit via I2C data/clock
2563  **/
2564 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2565 {
2566 	s32 status;
2567 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2568 
2569 	status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2570 	if (status == 0) {
2571 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2572 
2573 		/* Minimum high period of clock is 4us */
2574 		udelay(IXGBE_I2C_T_HIGH);
2575 
2576 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2577 
2578 		/* Minimum low period of clock is 4.7 us.
2579 		 * This also takes care of the data hold time.
2580 		 */
2581 		udelay(IXGBE_I2C_T_LOW);
2582 	} else {
2583 		hw_dbg(hw, "I2C data was not set to %X\n", data);
2584 		return -EIO;
2585 	}
2586 
2587 	return 0;
2588 }
2589 /**
2590  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2591  *  @hw: pointer to hardware structure
2592  *  @i2cctl: Current value of I2CCTL register
2593  *
2594  *  Raises the I2C clock line '0'->'1'
2595  *  Negates the I2C clock output enable on X550 hardware.
2596  **/
2597 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2598 {
2599 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2600 	u32 i = 0;
2601 	u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2602 	u32 i2cctl_r = 0;
2603 
2604 	if (clk_oe_bit) {
2605 		*i2cctl |= clk_oe_bit;
2606 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2607 	}
2608 
2609 	for (i = 0; i < timeout; i++) {
2610 		*i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2611 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2612 		IXGBE_WRITE_FLUSH(hw);
2613 		/* SCL rise time (1000ns) */
2614 		udelay(IXGBE_I2C_T_RISE);
2615 
2616 		i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2617 		if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2618 			break;
2619 	}
2620 }
2621 
2622 /**
2623  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2624  *  @hw: pointer to hardware structure
2625  *  @i2cctl: Current value of I2CCTL register
2626  *
2627  *  Lowers the I2C clock line '1'->'0'
2628  *  Asserts the I2C clock output enable on X550 hardware.
2629  **/
2630 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2631 {
2632 
2633 	*i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2634 	*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2635 
2636 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2637 	IXGBE_WRITE_FLUSH(hw);
2638 
2639 	/* SCL fall time (300ns) */
2640 	udelay(IXGBE_I2C_T_FALL);
2641 }
2642 
2643 /**
2644  *  ixgbe_set_i2c_data - Sets the I2C data bit
2645  *  @hw: pointer to hardware structure
2646  *  @i2cctl: Current value of I2CCTL register
2647  *  @data: I2C data value (0 or 1) to set
2648  *
2649  *  Sets the I2C data bit
2650  *  Asserts the I2C data output enable on X550 hardware.
2651  **/
2652 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2653 {
2654 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2655 
2656 	if (data)
2657 		*i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2658 	else
2659 		*i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2660 	*i2cctl &= ~data_oe_bit;
2661 
2662 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2663 	IXGBE_WRITE_FLUSH(hw);
2664 
2665 	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2666 	udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2667 
2668 	if (!data)	/* Can't verify data in this case */
2669 		return 0;
2670 	if (data_oe_bit) {
2671 		*i2cctl |= data_oe_bit;
2672 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2673 		IXGBE_WRITE_FLUSH(hw);
2674 	}
2675 
2676 	/* Verify data was set correctly */
2677 	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2678 	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2679 		hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2680 		return -EIO;
2681 	}
2682 
2683 	return 0;
2684 }
2685 
2686 /**
2687  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2688  *  @hw: pointer to hardware structure
2689  *  @i2cctl: Current value of I2CCTL register
2690  *
2691  *  Returns the I2C data bit value
2692  *  Negates the I2C data output enable on X550 hardware.
2693  **/
2694 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2695 {
2696 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2697 
2698 	if (data_oe_bit) {
2699 		*i2cctl |= data_oe_bit;
2700 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2701 		IXGBE_WRITE_FLUSH(hw);
2702 		udelay(IXGBE_I2C_T_FALL);
2703 	}
2704 
2705 	if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2706 		return true;
2707 	return false;
2708 }
2709 
2710 /**
2711  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2712  *  @hw: pointer to hardware structure
2713  *
2714  *  Clears the I2C bus by sending nine clock pulses.
2715  *  Used when data line is stuck low.
2716  **/
2717 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2718 {
2719 	u32 i2cctl;
2720 	u32 i;
2721 
2722 	ixgbe_i2c_start(hw);
2723 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2724 
2725 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2726 
2727 	for (i = 0; i < 9; i++) {
2728 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2729 
2730 		/* Min high period of clock is 4us */
2731 		udelay(IXGBE_I2C_T_HIGH);
2732 
2733 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2734 
2735 		/* Min low period of clock is 4.7us*/
2736 		udelay(IXGBE_I2C_T_LOW);
2737 	}
2738 
2739 	ixgbe_i2c_start(hw);
2740 
2741 	/* Put the i2c bus back to default state */
2742 	ixgbe_i2c_stop(hw);
2743 }
2744 
2745 /**
2746  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2747  *  @hw: pointer to hardware structure
2748  *
2749  *  Checks if the LASI temp alarm status was triggered due to overtemp
2750  *
2751  *  Return true when an overtemp event detected, otherwise false.
2752  **/
2753 bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2754 {
2755 	u16 phy_data = 0;
2756 	u32 status;
2757 
2758 	if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2759 		return false;
2760 
2761 	/* Check that the LASI temp alarm status was triggered */
2762 	status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2763 				      MDIO_MMD_PMAPMD, &phy_data);
2764 	if (status)
2765 		return false;
2766 
2767 	return !!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM);
2768 }
2769 
2770 /** ixgbe_set_copper_phy_power - Control power for copper phy
2771  *  @hw: pointer to hardware structure
2772  *  @on: true for on, false for off
2773  **/
2774 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2775 {
2776 	u32 status;
2777 	u16 reg;
2778 
2779 	/* Bail if we don't have copper phy */
2780 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2781 		return 0;
2782 
2783 	if (!on && ixgbe_mng_present(hw))
2784 		return 0;
2785 
2786 	status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
2787 	if (status)
2788 		return status;
2789 
2790 	if (on) {
2791 		reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2792 	} else {
2793 		if (ixgbe_check_reset_blocked(hw))
2794 			return 0;
2795 		reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2796 	}
2797 
2798 	status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2799 	return status;
2800 }
2801