1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe_common.h" 33 #include "ixgbe_phy.h" 34 35 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 42 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 45 static bool ixgbe_get_i2c_data(u32 *i2cctl); 46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 49 50 /** 51 * ixgbe_identify_phy_generic - Get physical layer module 52 * @hw: pointer to hardware structure 53 * 54 * Determines the physical layer module found on the current adapter. 55 **/ 56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 57 { 58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 59 u32 phy_addr; 60 u16 ext_ability = 0; 61 62 if (hw->phy.type == ixgbe_phy_unknown) { 63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 64 hw->phy.mdio.prtad = phy_addr; 65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { 66 ixgbe_get_phy_id(hw); 67 hw->phy.type = 68 ixgbe_get_phy_type_from_id(hw->phy.id); 69 70 if (hw->phy.type == ixgbe_phy_unknown) { 71 hw->phy.ops.read_reg(hw, 72 MDIO_PMA_EXTABLE, 73 MDIO_MMD_PMAPMD, 74 &ext_ability); 75 if (ext_ability & 76 (MDIO_PMA_EXTABLE_10GBT | 77 MDIO_PMA_EXTABLE_1000BT)) 78 hw->phy.type = 79 ixgbe_phy_cu_unknown; 80 else 81 hw->phy.type = 82 ixgbe_phy_generic; 83 } 84 85 status = 0; 86 break; 87 } 88 } 89 /* clear value if nothing found */ 90 if (status != 0) 91 hw->phy.mdio.prtad = 0; 92 } else { 93 status = 0; 94 } 95 96 return status; 97 } 98 99 /** 100 * ixgbe_get_phy_id - Get the phy type 101 * @hw: pointer to hardware structure 102 * 103 **/ 104 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 105 { 106 u32 status; 107 u16 phy_id_high = 0; 108 u16 phy_id_low = 0; 109 110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 111 &phy_id_high); 112 113 if (status == 0) { 114 hw->phy.id = (u32)(phy_id_high << 16); 115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 116 &phy_id_low); 117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 119 } 120 return status; 121 } 122 123 /** 124 * ixgbe_get_phy_type_from_id - Get the phy type 125 * @hw: pointer to hardware structure 126 * 127 **/ 128 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 129 { 130 enum ixgbe_phy_type phy_type; 131 132 switch (phy_id) { 133 case TN1010_PHY_ID: 134 phy_type = ixgbe_phy_tn; 135 break; 136 case X540_PHY_ID: 137 phy_type = ixgbe_phy_aq; 138 break; 139 case QT2022_PHY_ID: 140 phy_type = ixgbe_phy_qt; 141 break; 142 case ATH_PHY_ID: 143 phy_type = ixgbe_phy_nl; 144 break; 145 default: 146 phy_type = ixgbe_phy_unknown; 147 break; 148 } 149 150 return phy_type; 151 } 152 153 /** 154 * ixgbe_reset_phy_generic - Performs a PHY reset 155 * @hw: pointer to hardware structure 156 **/ 157 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 158 { 159 u32 i; 160 u16 ctrl = 0; 161 s32 status = 0; 162 163 if (hw->phy.type == ixgbe_phy_unknown) 164 status = ixgbe_identify_phy_generic(hw); 165 166 if (status != 0 || hw->phy.type == ixgbe_phy_none) 167 goto out; 168 169 /* Don't reset PHY if it's shut down due to overtemp. */ 170 if (!hw->phy.reset_if_overtemp && 171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 172 goto out; 173 174 /* 175 * Perform soft PHY reset to the PHY_XS. 176 * This will cause a soft reset to the PHY 177 */ 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 179 MDIO_MMD_PHYXS, 180 MDIO_CTRL1_RESET); 181 182 /* 183 * Poll for reset bit to self-clear indicating reset is complete. 184 * Some PHYs could take up to 3 seconds to complete and need about 185 * 1.7 usec delay after the reset is complete. 186 */ 187 for (i = 0; i < 30; i++) { 188 msleep(100); 189 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 190 MDIO_MMD_PHYXS, &ctrl); 191 if (!(ctrl & MDIO_CTRL1_RESET)) { 192 udelay(2); 193 break; 194 } 195 } 196 197 if (ctrl & MDIO_CTRL1_RESET) { 198 status = IXGBE_ERR_RESET_FAILED; 199 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 200 } 201 202 out: 203 return status; 204 } 205 206 /** 207 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 208 * @hw: pointer to hardware structure 209 * @reg_addr: 32 bit address of PHY register to read 210 * @phy_data: Pointer to read data from PHY register 211 **/ 212 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 213 u32 device_type, u16 *phy_data) 214 { 215 u32 command; 216 u32 i; 217 u32 data; 218 s32 status = 0; 219 u16 gssr; 220 221 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 222 gssr = IXGBE_GSSR_PHY1_SM; 223 else 224 gssr = IXGBE_GSSR_PHY0_SM; 225 226 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) 227 status = IXGBE_ERR_SWFW_SYNC; 228 229 if (status == 0) { 230 /* Setup and write the address cycle command */ 231 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 232 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 233 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 234 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 235 236 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 237 238 /* 239 * Check every 10 usec to see if the address cycle completed. 240 * The MDI Command bit will clear when the operation is 241 * complete 242 */ 243 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 244 udelay(10); 245 246 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 247 248 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 249 break; 250 } 251 252 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 253 hw_dbg(hw, "PHY address command did not complete.\n"); 254 status = IXGBE_ERR_PHY; 255 } 256 257 if (status == 0) { 258 /* 259 * Address cycle complete, setup and write the read 260 * command 261 */ 262 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 263 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 264 (hw->phy.mdio.prtad << 265 IXGBE_MSCA_PHY_ADDR_SHIFT) | 266 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 267 268 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 269 270 /* 271 * Check every 10 usec to see if the address cycle 272 * completed. The MDI Command bit will clear when the 273 * operation is complete 274 */ 275 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 276 udelay(10); 277 278 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 279 280 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 281 break; 282 } 283 284 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 285 hw_dbg(hw, "PHY read command didn't complete\n"); 286 status = IXGBE_ERR_PHY; 287 } else { 288 /* 289 * Read operation is complete. Get the data 290 * from MSRWD 291 */ 292 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 293 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 294 *phy_data = (u16)(data); 295 } 296 } 297 298 hw->mac.ops.release_swfw_sync(hw, gssr); 299 } 300 301 return status; 302 } 303 304 /** 305 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 306 * @hw: pointer to hardware structure 307 * @reg_addr: 32 bit PHY register to write 308 * @device_type: 5 bit device type 309 * @phy_data: Data to write to the PHY register 310 **/ 311 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 312 u32 device_type, u16 phy_data) 313 { 314 u32 command; 315 u32 i; 316 s32 status = 0; 317 u16 gssr; 318 319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 320 gssr = IXGBE_GSSR_PHY1_SM; 321 else 322 gssr = IXGBE_GSSR_PHY0_SM; 323 324 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) 325 status = IXGBE_ERR_SWFW_SYNC; 326 327 if (status == 0) { 328 /* Put the data in the MDI single read and write data register*/ 329 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 330 331 /* Setup and write the address cycle command */ 332 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 333 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 334 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 335 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 336 337 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 338 339 /* 340 * Check every 10 usec to see if the address cycle completed. 341 * The MDI Command bit will clear when the operation is 342 * complete 343 */ 344 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 345 udelay(10); 346 347 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 348 349 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 350 break; 351 } 352 353 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 354 hw_dbg(hw, "PHY address cmd didn't complete\n"); 355 status = IXGBE_ERR_PHY; 356 } 357 358 if (status == 0) { 359 /* 360 * Address cycle complete, setup and write the write 361 * command 362 */ 363 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 364 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 365 (hw->phy.mdio.prtad << 366 IXGBE_MSCA_PHY_ADDR_SHIFT) | 367 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 368 369 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 370 371 /* 372 * Check every 10 usec to see if the address cycle 373 * completed. The MDI Command bit will clear when the 374 * operation is complete 375 */ 376 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 377 udelay(10); 378 379 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 380 381 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 382 break; 383 } 384 385 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 386 hw_dbg(hw, "PHY address cmd didn't complete\n"); 387 status = IXGBE_ERR_PHY; 388 } 389 } 390 391 hw->mac.ops.release_swfw_sync(hw, gssr); 392 } 393 394 return status; 395 } 396 397 /** 398 * ixgbe_setup_phy_link_generic - Set and restart autoneg 399 * @hw: pointer to hardware structure 400 * 401 * Restart autonegotiation and PHY and waits for completion. 402 **/ 403 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 404 { 405 s32 status = 0; 406 u32 time_out; 407 u32 max_time_out = 10; 408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 409 bool autoneg = false; 410 ixgbe_link_speed speed; 411 412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 413 414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 415 /* Set or unset auto-negotiation 10G advertisement */ 416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 417 MDIO_MMD_AN, 418 &autoneg_reg); 419 420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 423 424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 425 MDIO_MMD_AN, 426 autoneg_reg); 427 } 428 429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 430 /* Set or unset auto-negotiation 1G advertisement */ 431 hw->phy.ops.read_reg(hw, 432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 433 MDIO_MMD_AN, 434 &autoneg_reg); 435 436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 439 440 hw->phy.ops.write_reg(hw, 441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 442 MDIO_MMD_AN, 443 autoneg_reg); 444 } 445 446 if (speed & IXGBE_LINK_SPEED_100_FULL) { 447 /* Set or unset auto-negotiation 100M advertisement */ 448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 449 MDIO_MMD_AN, 450 &autoneg_reg); 451 452 autoneg_reg &= ~(ADVERTISE_100FULL | 453 ADVERTISE_100HALF); 454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 455 autoneg_reg |= ADVERTISE_100FULL; 456 457 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 458 MDIO_MMD_AN, 459 autoneg_reg); 460 } 461 462 /* Restart PHY autonegotiation and wait for completion */ 463 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 464 MDIO_MMD_AN, &autoneg_reg); 465 466 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 467 468 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 469 MDIO_MMD_AN, autoneg_reg); 470 471 /* Wait for autonegotiation to finish */ 472 for (time_out = 0; time_out < max_time_out; time_out++) { 473 udelay(10); 474 /* Restart PHY autonegotiation and wait for completion */ 475 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, 476 MDIO_MMD_AN, 477 &autoneg_reg); 478 479 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 480 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { 481 break; 482 } 483 } 484 485 if (time_out == max_time_out) { 486 status = IXGBE_ERR_LINK_SETUP; 487 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out"); 488 } 489 490 return status; 491 } 492 493 /** 494 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 495 * @hw: pointer to hardware structure 496 * @speed: new link speed 497 **/ 498 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 499 ixgbe_link_speed speed, 500 bool autoneg_wait_to_complete) 501 { 502 503 /* 504 * Clear autoneg_advertised and set new values based on input link 505 * speed. 506 */ 507 hw->phy.autoneg_advertised = 0; 508 509 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 510 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 511 512 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 513 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 514 515 if (speed & IXGBE_LINK_SPEED_100_FULL) 516 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 517 518 /* Setup link based on the new speed settings */ 519 hw->phy.ops.setup_link(hw); 520 521 return 0; 522 } 523 524 /** 525 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 526 * @hw: pointer to hardware structure 527 * @speed: pointer to link speed 528 * @autoneg: boolean auto-negotiation value 529 * 530 * Determines the link capabilities by reading the AUTOC register. 531 */ 532 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 533 ixgbe_link_speed *speed, 534 bool *autoneg) 535 { 536 s32 status = IXGBE_ERR_LINK_SETUP; 537 u16 speed_ability; 538 539 *speed = 0; 540 *autoneg = true; 541 542 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 543 &speed_ability); 544 545 if (status == 0) { 546 if (speed_ability & MDIO_SPEED_10G) 547 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 548 if (speed_ability & MDIO_PMA_SPEED_1000) 549 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 550 if (speed_ability & MDIO_PMA_SPEED_100) 551 *speed |= IXGBE_LINK_SPEED_100_FULL; 552 } 553 554 return status; 555 } 556 557 /** 558 * ixgbe_check_phy_link_tnx - Determine link and speed status 559 * @hw: pointer to hardware structure 560 * 561 * Reads the VS1 register to determine if link is up and the current speed for 562 * the PHY. 563 **/ 564 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 565 bool *link_up) 566 { 567 s32 status = 0; 568 u32 time_out; 569 u32 max_time_out = 10; 570 u16 phy_link = 0; 571 u16 phy_speed = 0; 572 u16 phy_data = 0; 573 574 /* Initialize speed and link to default case */ 575 *link_up = false; 576 *speed = IXGBE_LINK_SPEED_10GB_FULL; 577 578 /* 579 * Check current speed and link status of the PHY register. 580 * This is a vendor specific register and may have to 581 * be changed for other copper PHYs. 582 */ 583 for (time_out = 0; time_out < max_time_out; time_out++) { 584 udelay(10); 585 status = hw->phy.ops.read_reg(hw, 586 MDIO_STAT1, 587 MDIO_MMD_VEND1, 588 &phy_data); 589 phy_link = phy_data & 590 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 591 phy_speed = phy_data & 592 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 593 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 594 *link_up = true; 595 if (phy_speed == 596 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 597 *speed = IXGBE_LINK_SPEED_1GB_FULL; 598 break; 599 } 600 } 601 602 return status; 603 } 604 605 /** 606 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 607 * @hw: pointer to hardware structure 608 * 609 * Restart autonegotiation and PHY and waits for completion. 610 **/ 611 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 612 { 613 s32 status = 0; 614 u32 time_out; 615 u32 max_time_out = 10; 616 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 617 bool autoneg = false; 618 ixgbe_link_speed speed; 619 620 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 621 622 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 623 /* Set or unset auto-negotiation 10G advertisement */ 624 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 625 MDIO_MMD_AN, 626 &autoneg_reg); 627 628 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 629 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 630 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 631 632 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 633 MDIO_MMD_AN, 634 autoneg_reg); 635 } 636 637 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 638 /* Set or unset auto-negotiation 1G advertisement */ 639 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 640 MDIO_MMD_AN, 641 &autoneg_reg); 642 643 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 644 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 645 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 646 647 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 648 MDIO_MMD_AN, 649 autoneg_reg); 650 } 651 652 if (speed & IXGBE_LINK_SPEED_100_FULL) { 653 /* Set or unset auto-negotiation 100M advertisement */ 654 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 655 MDIO_MMD_AN, 656 &autoneg_reg); 657 658 autoneg_reg &= ~(ADVERTISE_100FULL | 659 ADVERTISE_100HALF); 660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 661 autoneg_reg |= ADVERTISE_100FULL; 662 663 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 664 MDIO_MMD_AN, 665 autoneg_reg); 666 } 667 668 /* Restart PHY autonegotiation and wait for completion */ 669 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 670 MDIO_MMD_AN, &autoneg_reg); 671 672 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 673 674 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 675 MDIO_MMD_AN, autoneg_reg); 676 677 /* Wait for autonegotiation to finish */ 678 for (time_out = 0; time_out < max_time_out; time_out++) { 679 udelay(10); 680 /* Restart PHY autonegotiation and wait for completion */ 681 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, 682 MDIO_MMD_AN, 683 &autoneg_reg); 684 685 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 686 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) 687 break; 688 } 689 690 if (time_out == max_time_out) { 691 status = IXGBE_ERR_LINK_SETUP; 692 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out"); 693 } 694 695 return status; 696 } 697 698 /** 699 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 700 * @hw: pointer to hardware structure 701 * @firmware_version: pointer to the PHY Firmware Version 702 **/ 703 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 704 u16 *firmware_version) 705 { 706 s32 status = 0; 707 708 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 709 MDIO_MMD_VEND1, 710 firmware_version); 711 712 return status; 713 } 714 715 /** 716 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 717 * @hw: pointer to hardware structure 718 * @firmware_version: pointer to the PHY Firmware Version 719 **/ 720 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 721 u16 *firmware_version) 722 { 723 s32 status = 0; 724 725 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 726 MDIO_MMD_VEND1, 727 firmware_version); 728 729 return status; 730 } 731 732 /** 733 * ixgbe_reset_phy_nl - Performs a PHY reset 734 * @hw: pointer to hardware structure 735 **/ 736 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 737 { 738 u16 phy_offset, control, eword, edata, block_crc; 739 bool end_data = false; 740 u16 list_offset, data_offset; 741 u16 phy_data = 0; 742 s32 ret_val = 0; 743 u32 i; 744 745 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 746 747 /* reset the PHY and poll for completion */ 748 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 749 (phy_data | MDIO_CTRL1_RESET)); 750 751 for (i = 0; i < 100; i++) { 752 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 753 &phy_data); 754 if ((phy_data & MDIO_CTRL1_RESET) == 0) 755 break; 756 usleep_range(10000, 20000); 757 } 758 759 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 760 hw_dbg(hw, "PHY reset did not complete.\n"); 761 ret_val = IXGBE_ERR_PHY; 762 goto out; 763 } 764 765 /* Get init offsets */ 766 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 767 &data_offset); 768 if (ret_val != 0) 769 goto out; 770 771 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 772 data_offset++; 773 while (!end_data) { 774 /* 775 * Read control word from PHY init contents offset 776 */ 777 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 778 control = (eword & IXGBE_CONTROL_MASK_NL) >> 779 IXGBE_CONTROL_SHIFT_NL; 780 edata = eword & IXGBE_DATA_MASK_NL; 781 switch (control) { 782 case IXGBE_DELAY_NL: 783 data_offset++; 784 hw_dbg(hw, "DELAY: %d MS\n", edata); 785 usleep_range(edata * 1000, edata * 2000); 786 break; 787 case IXGBE_DATA_NL: 788 hw_dbg(hw, "DATA:\n"); 789 data_offset++; 790 hw->eeprom.ops.read(hw, data_offset++, 791 &phy_offset); 792 for (i = 0; i < edata; i++) { 793 hw->eeprom.ops.read(hw, data_offset, &eword); 794 hw->phy.ops.write_reg(hw, phy_offset, 795 MDIO_MMD_PMAPMD, eword); 796 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 797 phy_offset); 798 data_offset++; 799 phy_offset++; 800 } 801 break; 802 case IXGBE_CONTROL_NL: 803 data_offset++; 804 hw_dbg(hw, "CONTROL:\n"); 805 if (edata == IXGBE_CONTROL_EOL_NL) { 806 hw_dbg(hw, "EOL\n"); 807 end_data = true; 808 } else if (edata == IXGBE_CONTROL_SOL_NL) { 809 hw_dbg(hw, "SOL\n"); 810 } else { 811 hw_dbg(hw, "Bad control value\n"); 812 ret_val = IXGBE_ERR_PHY; 813 goto out; 814 } 815 break; 816 default: 817 hw_dbg(hw, "Bad control type\n"); 818 ret_val = IXGBE_ERR_PHY; 819 goto out; 820 } 821 } 822 823 out: 824 return ret_val; 825 } 826 827 /** 828 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 829 * @hw: pointer to hardware structure 830 * 831 * Searches for and identifies the SFP module and assigns appropriate PHY type. 832 **/ 833 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 834 { 835 struct ixgbe_adapter *adapter = hw->back; 836 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 837 u32 vendor_oui = 0; 838 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 839 u8 identifier = 0; 840 u8 comp_codes_1g = 0; 841 u8 comp_codes_10g = 0; 842 u8 oui_bytes[3] = {0, 0, 0}; 843 u8 cable_tech = 0; 844 u8 cable_spec = 0; 845 u16 enforce_sfp = 0; 846 847 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 848 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 849 status = IXGBE_ERR_SFP_NOT_PRESENT; 850 goto out; 851 } 852 853 status = hw->phy.ops.read_i2c_eeprom(hw, 854 IXGBE_SFF_IDENTIFIER, 855 &identifier); 856 857 if (status != 0) 858 goto err_read_i2c_eeprom; 859 860 /* LAN ID is needed for sfp_type determination */ 861 hw->mac.ops.set_lan_id(hw); 862 863 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 864 hw->phy.type = ixgbe_phy_sfp_unsupported; 865 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 866 } else { 867 status = hw->phy.ops.read_i2c_eeprom(hw, 868 IXGBE_SFF_1GBE_COMP_CODES, 869 &comp_codes_1g); 870 871 if (status != 0) 872 goto err_read_i2c_eeprom; 873 874 status = hw->phy.ops.read_i2c_eeprom(hw, 875 IXGBE_SFF_10GBE_COMP_CODES, 876 &comp_codes_10g); 877 878 if (status != 0) 879 goto err_read_i2c_eeprom; 880 status = hw->phy.ops.read_i2c_eeprom(hw, 881 IXGBE_SFF_CABLE_TECHNOLOGY, 882 &cable_tech); 883 884 if (status != 0) 885 goto err_read_i2c_eeprom; 886 887 /* ID Module 888 * ========= 889 * 0 SFP_DA_CU 890 * 1 SFP_SR 891 * 2 SFP_LR 892 * 3 SFP_DA_CORE0 - 82599-specific 893 * 4 SFP_DA_CORE1 - 82599-specific 894 * 5 SFP_SR/LR_CORE0 - 82599-specific 895 * 6 SFP_SR/LR_CORE1 - 82599-specific 896 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 897 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 898 * 9 SFP_1g_cu_CORE0 - 82599-specific 899 * 10 SFP_1g_cu_CORE1 - 82599-specific 900 * 11 SFP_1g_sx_CORE0 - 82599-specific 901 * 12 SFP_1g_sx_CORE1 - 82599-specific 902 */ 903 if (hw->mac.type == ixgbe_mac_82598EB) { 904 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 905 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 906 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 907 hw->phy.sfp_type = ixgbe_sfp_type_sr; 908 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 909 hw->phy.sfp_type = ixgbe_sfp_type_lr; 910 else 911 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 912 } else if (hw->mac.type == ixgbe_mac_82599EB) { 913 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 914 if (hw->bus.lan_id == 0) 915 hw->phy.sfp_type = 916 ixgbe_sfp_type_da_cu_core0; 917 else 918 hw->phy.sfp_type = 919 ixgbe_sfp_type_da_cu_core1; 920 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 921 hw->phy.ops.read_i2c_eeprom( 922 hw, IXGBE_SFF_CABLE_SPEC_COMP, 923 &cable_spec); 924 if (cable_spec & 925 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 926 if (hw->bus.lan_id == 0) 927 hw->phy.sfp_type = 928 ixgbe_sfp_type_da_act_lmt_core0; 929 else 930 hw->phy.sfp_type = 931 ixgbe_sfp_type_da_act_lmt_core1; 932 } else { 933 hw->phy.sfp_type = 934 ixgbe_sfp_type_unknown; 935 } 936 } else if (comp_codes_10g & 937 (IXGBE_SFF_10GBASESR_CAPABLE | 938 IXGBE_SFF_10GBASELR_CAPABLE)) { 939 if (hw->bus.lan_id == 0) 940 hw->phy.sfp_type = 941 ixgbe_sfp_type_srlr_core0; 942 else 943 hw->phy.sfp_type = 944 ixgbe_sfp_type_srlr_core1; 945 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 946 if (hw->bus.lan_id == 0) 947 hw->phy.sfp_type = 948 ixgbe_sfp_type_1g_cu_core0; 949 else 950 hw->phy.sfp_type = 951 ixgbe_sfp_type_1g_cu_core1; 952 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 953 if (hw->bus.lan_id == 0) 954 hw->phy.sfp_type = 955 ixgbe_sfp_type_1g_sx_core0; 956 else 957 hw->phy.sfp_type = 958 ixgbe_sfp_type_1g_sx_core1; 959 } else { 960 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 961 } 962 } 963 964 if (hw->phy.sfp_type != stored_sfp_type) 965 hw->phy.sfp_setup_needed = true; 966 967 /* Determine if the SFP+ PHY is dual speed or not. */ 968 hw->phy.multispeed_fiber = false; 969 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 970 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 971 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 972 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 973 hw->phy.multispeed_fiber = true; 974 975 /* Determine PHY vendor */ 976 if (hw->phy.type != ixgbe_phy_nl) { 977 hw->phy.id = identifier; 978 status = hw->phy.ops.read_i2c_eeprom(hw, 979 IXGBE_SFF_VENDOR_OUI_BYTE0, 980 &oui_bytes[0]); 981 982 if (status != 0) 983 goto err_read_i2c_eeprom; 984 985 status = hw->phy.ops.read_i2c_eeprom(hw, 986 IXGBE_SFF_VENDOR_OUI_BYTE1, 987 &oui_bytes[1]); 988 989 if (status != 0) 990 goto err_read_i2c_eeprom; 991 992 status = hw->phy.ops.read_i2c_eeprom(hw, 993 IXGBE_SFF_VENDOR_OUI_BYTE2, 994 &oui_bytes[2]); 995 996 if (status != 0) 997 goto err_read_i2c_eeprom; 998 999 vendor_oui = 1000 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1001 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1002 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1003 1004 switch (vendor_oui) { 1005 case IXGBE_SFF_VENDOR_OUI_TYCO: 1006 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1007 hw->phy.type = 1008 ixgbe_phy_sfp_passive_tyco; 1009 break; 1010 case IXGBE_SFF_VENDOR_OUI_FTL: 1011 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1012 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1013 else 1014 hw->phy.type = ixgbe_phy_sfp_ftl; 1015 break; 1016 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1017 hw->phy.type = ixgbe_phy_sfp_avago; 1018 break; 1019 case IXGBE_SFF_VENDOR_OUI_INTEL: 1020 hw->phy.type = ixgbe_phy_sfp_intel; 1021 break; 1022 default: 1023 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1024 hw->phy.type = 1025 ixgbe_phy_sfp_passive_unknown; 1026 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1027 hw->phy.type = 1028 ixgbe_phy_sfp_active_unknown; 1029 else 1030 hw->phy.type = ixgbe_phy_sfp_unknown; 1031 break; 1032 } 1033 } 1034 1035 /* Allow any DA cable vendor */ 1036 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1037 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1038 status = 0; 1039 goto out; 1040 } 1041 1042 /* Verify supported 1G SFP modules */ 1043 if (comp_codes_10g == 0 && 1044 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1045 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1046 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1047 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1048 hw->phy.type = ixgbe_phy_sfp_unsupported; 1049 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1050 goto out; 1051 } 1052 1053 /* Anything else 82598-based is supported */ 1054 if (hw->mac.type == ixgbe_mac_82598EB) { 1055 status = 0; 1056 goto out; 1057 } 1058 1059 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1060 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1061 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1062 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) || 1063 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) || 1064 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) { 1065 /* Make sure we're a supported PHY type */ 1066 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1067 status = 0; 1068 } else { 1069 if (hw->allow_unsupported_sfp) { 1070 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules."); 1071 status = 0; 1072 } else { 1073 hw_dbg(hw, 1074 "SFP+ module not supported\n"); 1075 hw->phy.type = 1076 ixgbe_phy_sfp_unsupported; 1077 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1078 } 1079 } 1080 } else { 1081 status = 0; 1082 } 1083 } 1084 1085 out: 1086 return status; 1087 1088 err_read_i2c_eeprom: 1089 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1090 if (hw->phy.type != ixgbe_phy_nl) { 1091 hw->phy.id = 0; 1092 hw->phy.type = ixgbe_phy_unknown; 1093 } 1094 return IXGBE_ERR_SFP_NOT_PRESENT; 1095 } 1096 1097 /** 1098 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1099 * @hw: pointer to hardware structure 1100 * @list_offset: offset to the SFP ID list 1101 * @data_offset: offset to the SFP data block 1102 * 1103 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1104 * so it returns the offsets to the phy init sequence block. 1105 **/ 1106 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1107 u16 *list_offset, 1108 u16 *data_offset) 1109 { 1110 u16 sfp_id; 1111 u16 sfp_type = hw->phy.sfp_type; 1112 1113 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1114 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1115 1116 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1117 return IXGBE_ERR_SFP_NOT_PRESENT; 1118 1119 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1120 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1121 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1122 1123 /* 1124 * Limiting active cables and 1G Phys must be initialized as 1125 * SR modules 1126 */ 1127 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1128 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1129 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1130 sfp_type = ixgbe_sfp_type_srlr_core0; 1131 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1132 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1133 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1134 sfp_type = ixgbe_sfp_type_srlr_core1; 1135 1136 /* Read offset to PHY init contents */ 1137 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1138 1139 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1140 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1141 1142 /* Shift offset to first ID word */ 1143 (*list_offset)++; 1144 1145 /* 1146 * Find the matching SFP ID in the EEPROM 1147 * and program the init sequence 1148 */ 1149 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1150 1151 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1152 if (sfp_id == sfp_type) { 1153 (*list_offset)++; 1154 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1155 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1156 hw_dbg(hw, "SFP+ module not supported\n"); 1157 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1158 } else { 1159 break; 1160 } 1161 } else { 1162 (*list_offset) += 2; 1163 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1164 return IXGBE_ERR_PHY; 1165 } 1166 } 1167 1168 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1169 hw_dbg(hw, "No matching SFP+ module found\n"); 1170 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1171 } 1172 1173 return 0; 1174 } 1175 1176 /** 1177 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1178 * @hw: pointer to hardware structure 1179 * @byte_offset: EEPROM byte offset to read 1180 * @eeprom_data: value read 1181 * 1182 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1183 **/ 1184 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1185 u8 *eeprom_data) 1186 { 1187 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1188 IXGBE_I2C_EEPROM_DEV_ADDR, 1189 eeprom_data); 1190 } 1191 1192 /** 1193 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1194 * @hw: pointer to hardware structure 1195 * @byte_offset: byte offset at address 0xA2 1196 * @eeprom_data: value read 1197 * 1198 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1199 **/ 1200 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1201 u8 *sff8472_data) 1202 { 1203 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1204 IXGBE_I2C_EEPROM_DEV_ADDR2, 1205 sff8472_data); 1206 } 1207 1208 /** 1209 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1210 * @hw: pointer to hardware structure 1211 * @byte_offset: EEPROM byte offset to write 1212 * @eeprom_data: value to write 1213 * 1214 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1215 **/ 1216 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1217 u8 eeprom_data) 1218 { 1219 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1220 IXGBE_I2C_EEPROM_DEV_ADDR, 1221 eeprom_data); 1222 } 1223 1224 /** 1225 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1226 * @hw: pointer to hardware structure 1227 * @byte_offset: byte offset to read 1228 * @data: value read 1229 * 1230 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1231 * a specified device address. 1232 **/ 1233 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1234 u8 dev_addr, u8 *data) 1235 { 1236 s32 status = 0; 1237 u32 max_retry = 10; 1238 u32 retry = 0; 1239 u16 swfw_mask = 0; 1240 bool nack = true; 1241 *data = 0; 1242 1243 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1244 swfw_mask = IXGBE_GSSR_PHY1_SM; 1245 else 1246 swfw_mask = IXGBE_GSSR_PHY0_SM; 1247 1248 do { 1249 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { 1250 status = IXGBE_ERR_SWFW_SYNC; 1251 goto read_byte_out; 1252 } 1253 1254 ixgbe_i2c_start(hw); 1255 1256 /* Device Address and write indication */ 1257 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1258 if (status != 0) 1259 goto fail; 1260 1261 status = ixgbe_get_i2c_ack(hw); 1262 if (status != 0) 1263 goto fail; 1264 1265 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1266 if (status != 0) 1267 goto fail; 1268 1269 status = ixgbe_get_i2c_ack(hw); 1270 if (status != 0) 1271 goto fail; 1272 1273 ixgbe_i2c_start(hw); 1274 1275 /* Device Address and read indication */ 1276 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1277 if (status != 0) 1278 goto fail; 1279 1280 status = ixgbe_get_i2c_ack(hw); 1281 if (status != 0) 1282 goto fail; 1283 1284 status = ixgbe_clock_in_i2c_byte(hw, data); 1285 if (status != 0) 1286 goto fail; 1287 1288 status = ixgbe_clock_out_i2c_bit(hw, nack); 1289 if (status != 0) 1290 goto fail; 1291 1292 ixgbe_i2c_stop(hw); 1293 break; 1294 1295 fail: 1296 ixgbe_i2c_bus_clear(hw); 1297 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1298 msleep(100); 1299 retry++; 1300 if (retry < max_retry) 1301 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 1302 else 1303 hw_dbg(hw, "I2C byte read error.\n"); 1304 1305 } while (retry < max_retry); 1306 1307 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1308 1309 read_byte_out: 1310 return status; 1311 } 1312 1313 /** 1314 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1315 * @hw: pointer to hardware structure 1316 * @byte_offset: byte offset to write 1317 * @data: value to write 1318 * 1319 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1320 * a specified device address. 1321 **/ 1322 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1323 u8 dev_addr, u8 data) 1324 { 1325 s32 status = 0; 1326 u32 max_retry = 1; 1327 u32 retry = 0; 1328 u16 swfw_mask = 0; 1329 1330 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1331 swfw_mask = IXGBE_GSSR_PHY1_SM; 1332 else 1333 swfw_mask = IXGBE_GSSR_PHY0_SM; 1334 1335 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { 1336 status = IXGBE_ERR_SWFW_SYNC; 1337 goto write_byte_out; 1338 } 1339 1340 do { 1341 ixgbe_i2c_start(hw); 1342 1343 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1344 if (status != 0) 1345 goto fail; 1346 1347 status = ixgbe_get_i2c_ack(hw); 1348 if (status != 0) 1349 goto fail; 1350 1351 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1352 if (status != 0) 1353 goto fail; 1354 1355 status = ixgbe_get_i2c_ack(hw); 1356 if (status != 0) 1357 goto fail; 1358 1359 status = ixgbe_clock_out_i2c_byte(hw, data); 1360 if (status != 0) 1361 goto fail; 1362 1363 status = ixgbe_get_i2c_ack(hw); 1364 if (status != 0) 1365 goto fail; 1366 1367 ixgbe_i2c_stop(hw); 1368 break; 1369 1370 fail: 1371 ixgbe_i2c_bus_clear(hw); 1372 retry++; 1373 if (retry < max_retry) 1374 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 1375 else 1376 hw_dbg(hw, "I2C byte write error.\n"); 1377 } while (retry < max_retry); 1378 1379 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1380 1381 write_byte_out: 1382 return status; 1383 } 1384 1385 /** 1386 * ixgbe_i2c_start - Sets I2C start condition 1387 * @hw: pointer to hardware structure 1388 * 1389 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1390 **/ 1391 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1392 { 1393 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1394 1395 /* Start condition must begin with data and clock high */ 1396 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1397 ixgbe_raise_i2c_clk(hw, &i2cctl); 1398 1399 /* Setup time for start condition (4.7us) */ 1400 udelay(IXGBE_I2C_T_SU_STA); 1401 1402 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1403 1404 /* Hold time for start condition (4us) */ 1405 udelay(IXGBE_I2C_T_HD_STA); 1406 1407 ixgbe_lower_i2c_clk(hw, &i2cctl); 1408 1409 /* Minimum low period of clock is 4.7 us */ 1410 udelay(IXGBE_I2C_T_LOW); 1411 1412 } 1413 1414 /** 1415 * ixgbe_i2c_stop - Sets I2C stop condition 1416 * @hw: pointer to hardware structure 1417 * 1418 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1419 **/ 1420 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1421 { 1422 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1423 1424 /* Stop condition must begin with data low and clock high */ 1425 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1426 ixgbe_raise_i2c_clk(hw, &i2cctl); 1427 1428 /* Setup time for stop condition (4us) */ 1429 udelay(IXGBE_I2C_T_SU_STO); 1430 1431 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1432 1433 /* bus free time between stop and start (4.7us)*/ 1434 udelay(IXGBE_I2C_T_BUF); 1435 } 1436 1437 /** 1438 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1439 * @hw: pointer to hardware structure 1440 * @data: data byte to clock in 1441 * 1442 * Clocks in one byte data via I2C data/clock 1443 **/ 1444 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1445 { 1446 s32 i; 1447 bool bit = false; 1448 1449 for (i = 7; i >= 0; i--) { 1450 ixgbe_clock_in_i2c_bit(hw, &bit); 1451 *data |= bit << i; 1452 } 1453 1454 return 0; 1455 } 1456 1457 /** 1458 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1459 * @hw: pointer to hardware structure 1460 * @data: data byte clocked out 1461 * 1462 * Clocks out one byte data via I2C data/clock 1463 **/ 1464 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1465 { 1466 s32 status = 0; 1467 s32 i; 1468 u32 i2cctl; 1469 bool bit = false; 1470 1471 for (i = 7; i >= 0; i--) { 1472 bit = (data >> i) & 0x1; 1473 status = ixgbe_clock_out_i2c_bit(hw, bit); 1474 1475 if (status != 0) 1476 break; 1477 } 1478 1479 /* Release SDA line (set high) */ 1480 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1481 i2cctl |= IXGBE_I2C_DATA_OUT; 1482 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1483 IXGBE_WRITE_FLUSH(hw); 1484 1485 return status; 1486 } 1487 1488 /** 1489 * ixgbe_get_i2c_ack - Polls for I2C ACK 1490 * @hw: pointer to hardware structure 1491 * 1492 * Clocks in/out one bit via I2C data/clock 1493 **/ 1494 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1495 { 1496 s32 status = 0; 1497 u32 i = 0; 1498 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1499 u32 timeout = 10; 1500 bool ack = true; 1501 1502 ixgbe_raise_i2c_clk(hw, &i2cctl); 1503 1504 1505 /* Minimum high period of clock is 4us */ 1506 udelay(IXGBE_I2C_T_HIGH); 1507 1508 /* Poll for ACK. Note that ACK in I2C spec is 1509 * transition from 1 to 0 */ 1510 for (i = 0; i < timeout; i++) { 1511 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1512 ack = ixgbe_get_i2c_data(&i2cctl); 1513 1514 udelay(1); 1515 if (ack == 0) 1516 break; 1517 } 1518 1519 if (ack == 1) { 1520 hw_dbg(hw, "I2C ack was not received.\n"); 1521 status = IXGBE_ERR_I2C; 1522 } 1523 1524 ixgbe_lower_i2c_clk(hw, &i2cctl); 1525 1526 /* Minimum low period of clock is 4.7 us */ 1527 udelay(IXGBE_I2C_T_LOW); 1528 1529 return status; 1530 } 1531 1532 /** 1533 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1534 * @hw: pointer to hardware structure 1535 * @data: read data value 1536 * 1537 * Clocks in one bit via I2C data/clock 1538 **/ 1539 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1540 { 1541 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1542 1543 ixgbe_raise_i2c_clk(hw, &i2cctl); 1544 1545 /* Minimum high period of clock is 4us */ 1546 udelay(IXGBE_I2C_T_HIGH); 1547 1548 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1549 *data = ixgbe_get_i2c_data(&i2cctl); 1550 1551 ixgbe_lower_i2c_clk(hw, &i2cctl); 1552 1553 /* Minimum low period of clock is 4.7 us */ 1554 udelay(IXGBE_I2C_T_LOW); 1555 1556 return 0; 1557 } 1558 1559 /** 1560 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1561 * @hw: pointer to hardware structure 1562 * @data: data value to write 1563 * 1564 * Clocks out one bit via I2C data/clock 1565 **/ 1566 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1567 { 1568 s32 status; 1569 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1570 1571 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1572 if (status == 0) { 1573 ixgbe_raise_i2c_clk(hw, &i2cctl); 1574 1575 /* Minimum high period of clock is 4us */ 1576 udelay(IXGBE_I2C_T_HIGH); 1577 1578 ixgbe_lower_i2c_clk(hw, &i2cctl); 1579 1580 /* Minimum low period of clock is 4.7 us. 1581 * This also takes care of the data hold time. 1582 */ 1583 udelay(IXGBE_I2C_T_LOW); 1584 } else { 1585 status = IXGBE_ERR_I2C; 1586 hw_dbg(hw, "I2C data was not set to %X\n", data); 1587 } 1588 1589 return status; 1590 } 1591 /** 1592 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1593 * @hw: pointer to hardware structure 1594 * @i2cctl: Current value of I2CCTL register 1595 * 1596 * Raises the I2C clock line '0'->'1' 1597 **/ 1598 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1599 { 1600 u32 i = 0; 1601 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1602 u32 i2cctl_r = 0; 1603 1604 for (i = 0; i < timeout; i++) { 1605 *i2cctl |= IXGBE_I2C_CLK_OUT; 1606 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1607 IXGBE_WRITE_FLUSH(hw); 1608 /* SCL rise time (1000ns) */ 1609 udelay(IXGBE_I2C_T_RISE); 1610 1611 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1612 if (i2cctl_r & IXGBE_I2C_CLK_IN) 1613 break; 1614 } 1615 } 1616 1617 /** 1618 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1619 * @hw: pointer to hardware structure 1620 * @i2cctl: Current value of I2CCTL register 1621 * 1622 * Lowers the I2C clock line '1'->'0' 1623 **/ 1624 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1625 { 1626 1627 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1628 1629 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1630 IXGBE_WRITE_FLUSH(hw); 1631 1632 /* SCL fall time (300ns) */ 1633 udelay(IXGBE_I2C_T_FALL); 1634 } 1635 1636 /** 1637 * ixgbe_set_i2c_data - Sets the I2C data bit 1638 * @hw: pointer to hardware structure 1639 * @i2cctl: Current value of I2CCTL register 1640 * @data: I2C data value (0 or 1) to set 1641 * 1642 * Sets the I2C data bit 1643 **/ 1644 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1645 { 1646 s32 status = 0; 1647 1648 if (data) 1649 *i2cctl |= IXGBE_I2C_DATA_OUT; 1650 else 1651 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1652 1653 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1654 IXGBE_WRITE_FLUSH(hw); 1655 1656 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1657 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1658 1659 /* Verify data was set correctly */ 1660 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1661 if (data != ixgbe_get_i2c_data(i2cctl)) { 1662 status = IXGBE_ERR_I2C; 1663 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 1664 } 1665 1666 return status; 1667 } 1668 1669 /** 1670 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1671 * @hw: pointer to hardware structure 1672 * @i2cctl: Current value of I2CCTL register 1673 * 1674 * Returns the I2C data bit value 1675 **/ 1676 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1677 { 1678 bool data; 1679 1680 if (*i2cctl & IXGBE_I2C_DATA_IN) 1681 data = true; 1682 else 1683 data = false; 1684 1685 return data; 1686 } 1687 1688 /** 1689 * ixgbe_i2c_bus_clear - Clears the I2C bus 1690 * @hw: pointer to hardware structure 1691 * 1692 * Clears the I2C bus by sending nine clock pulses. 1693 * Used when data line is stuck low. 1694 **/ 1695 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1696 { 1697 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1698 u32 i; 1699 1700 ixgbe_i2c_start(hw); 1701 1702 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1703 1704 for (i = 0; i < 9; i++) { 1705 ixgbe_raise_i2c_clk(hw, &i2cctl); 1706 1707 /* Min high period of clock is 4us */ 1708 udelay(IXGBE_I2C_T_HIGH); 1709 1710 ixgbe_lower_i2c_clk(hw, &i2cctl); 1711 1712 /* Min low period of clock is 4.7us*/ 1713 udelay(IXGBE_I2C_T_LOW); 1714 } 1715 1716 ixgbe_i2c_start(hw); 1717 1718 /* Put the i2c bus back to default state */ 1719 ixgbe_i2c_stop(hw); 1720 } 1721 1722 /** 1723 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1724 * @hw: pointer to hardware structure 1725 * 1726 * Checks if the LASI temp alarm status was triggered due to overtemp 1727 **/ 1728 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1729 { 1730 s32 status = 0; 1731 u16 phy_data = 0; 1732 1733 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1734 goto out; 1735 1736 /* Check that the LASI temp alarm status was triggered */ 1737 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1738 MDIO_MMD_PMAPMD, &phy_data); 1739 1740 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1741 goto out; 1742 1743 status = IXGBE_ERR_OVERTEMP; 1744 out: 1745 return status; 1746 } 1747