1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe_common.h" 33 #include "ixgbe_phy.h" 34 35 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 42 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 45 static bool ixgbe_get_i2c_data(u32 *i2cctl); 46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 49 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw); 50 51 /** 52 * ixgbe_identify_phy_generic - Get physical layer module 53 * @hw: pointer to hardware structure 54 * 55 * Determines the physical layer module found on the current adapter. 56 **/ 57 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 58 { 59 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 60 u32 phy_addr; 61 u16 ext_ability = 0; 62 63 if (hw->phy.type == ixgbe_phy_unknown) { 64 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 65 hw->phy.mdio.prtad = phy_addr; 66 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { 67 ixgbe_get_phy_id(hw); 68 hw->phy.type = 69 ixgbe_get_phy_type_from_id(hw->phy.id); 70 71 if (hw->phy.type == ixgbe_phy_unknown) { 72 hw->phy.ops.read_reg(hw, 73 MDIO_PMA_EXTABLE, 74 MDIO_MMD_PMAPMD, 75 &ext_ability); 76 if (ext_ability & 77 (MDIO_PMA_EXTABLE_10GBT | 78 MDIO_PMA_EXTABLE_1000BT)) 79 hw->phy.type = 80 ixgbe_phy_cu_unknown; 81 else 82 hw->phy.type = 83 ixgbe_phy_generic; 84 } 85 86 status = 0; 87 break; 88 } 89 } 90 /* clear value if nothing found */ 91 if (status != 0) 92 hw->phy.mdio.prtad = 0; 93 } else { 94 status = 0; 95 } 96 97 return status; 98 } 99 100 /** 101 * ixgbe_get_phy_id - Get the phy type 102 * @hw: pointer to hardware structure 103 * 104 **/ 105 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 106 { 107 u32 status; 108 u16 phy_id_high = 0; 109 u16 phy_id_low = 0; 110 111 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 112 &phy_id_high); 113 114 if (status == 0) { 115 hw->phy.id = (u32)(phy_id_high << 16); 116 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 117 &phy_id_low); 118 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 119 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 120 } 121 return status; 122 } 123 124 /** 125 * ixgbe_get_phy_type_from_id - Get the phy type 126 * @hw: pointer to hardware structure 127 * 128 **/ 129 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 130 { 131 enum ixgbe_phy_type phy_type; 132 133 switch (phy_id) { 134 case TN1010_PHY_ID: 135 phy_type = ixgbe_phy_tn; 136 break; 137 case X540_PHY_ID: 138 phy_type = ixgbe_phy_aq; 139 break; 140 case QT2022_PHY_ID: 141 phy_type = ixgbe_phy_qt; 142 break; 143 case ATH_PHY_ID: 144 phy_type = ixgbe_phy_nl; 145 break; 146 default: 147 phy_type = ixgbe_phy_unknown; 148 break; 149 } 150 151 return phy_type; 152 } 153 154 /** 155 * ixgbe_reset_phy_generic - Performs a PHY reset 156 * @hw: pointer to hardware structure 157 **/ 158 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 159 { 160 u32 i; 161 u16 ctrl = 0; 162 s32 status = 0; 163 164 if (hw->phy.type == ixgbe_phy_unknown) 165 status = ixgbe_identify_phy_generic(hw); 166 167 if (status != 0 || hw->phy.type == ixgbe_phy_none) 168 goto out; 169 170 /* Don't reset PHY if it's shut down due to overtemp. */ 171 if (!hw->phy.reset_if_overtemp && 172 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 173 goto out; 174 175 /* 176 * Perform soft PHY reset to the PHY_XS. 177 * This will cause a soft reset to the PHY 178 */ 179 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 180 MDIO_MMD_PHYXS, 181 MDIO_CTRL1_RESET); 182 183 /* 184 * Poll for reset bit to self-clear indicating reset is complete. 185 * Some PHYs could take up to 3 seconds to complete and need about 186 * 1.7 usec delay after the reset is complete. 187 */ 188 for (i = 0; i < 30; i++) { 189 msleep(100); 190 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 191 MDIO_MMD_PHYXS, &ctrl); 192 if (!(ctrl & MDIO_CTRL1_RESET)) { 193 udelay(2); 194 break; 195 } 196 } 197 198 if (ctrl & MDIO_CTRL1_RESET) { 199 status = IXGBE_ERR_RESET_FAILED; 200 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 201 } 202 203 out: 204 return status; 205 } 206 207 /** 208 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 209 * the SWFW lock 210 * @hw: pointer to hardware structure 211 * @reg_addr: 32 bit address of PHY register to read 212 * @phy_data: Pointer to read data from PHY register 213 **/ 214 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 215 u16 *phy_data) 216 { 217 u32 i, data, command; 218 219 /* Setup and write the address cycle command */ 220 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 221 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 222 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 223 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 224 225 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 226 227 /* Check every 10 usec to see if the address cycle completed. 228 * The MDI Command bit will clear when the operation is 229 * complete 230 */ 231 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 232 udelay(10); 233 234 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 235 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 236 break; 237 } 238 239 240 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 241 hw_dbg(hw, "PHY address command did not complete.\n"); 242 return IXGBE_ERR_PHY; 243 } 244 245 /* Address cycle complete, setup and write the read 246 * command 247 */ 248 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 249 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 250 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 251 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 252 253 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 254 255 /* Check every 10 usec to see if the address cycle 256 * completed. The MDI Command bit will clear when the 257 * operation is complete 258 */ 259 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 260 udelay(10); 261 262 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 263 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 264 break; 265 } 266 267 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 268 hw_dbg(hw, "PHY read command didn't complete\n"); 269 return IXGBE_ERR_PHY; 270 } 271 272 /* Read operation is complete. Get the data 273 * from MSRWD 274 */ 275 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 276 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 277 *phy_data = (u16)(data); 278 279 return 0; 280 } 281 282 /** 283 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 284 * using the SWFW lock - this function is needed in most cases 285 * @hw: pointer to hardware structure 286 * @reg_addr: 32 bit address of PHY register to read 287 * @phy_data: Pointer to read data from PHY register 288 **/ 289 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 290 u32 device_type, u16 *phy_data) 291 { 292 s32 status; 293 u16 gssr; 294 295 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 296 gssr = IXGBE_GSSR_PHY1_SM; 297 else 298 gssr = IXGBE_GSSR_PHY0_SM; 299 300 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 301 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 302 phy_data); 303 hw->mac.ops.release_swfw_sync(hw, gssr); 304 } else { 305 status = IXGBE_ERR_SWFW_SYNC; 306 } 307 308 return status; 309 } 310 311 /** 312 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 313 * without SWFW lock 314 * @hw: pointer to hardware structure 315 * @reg_addr: 32 bit PHY register to write 316 * @device_type: 5 bit device type 317 * @phy_data: Data to write to the PHY register 318 **/ 319 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 320 u32 device_type, u16 phy_data) 321 { 322 u32 i, command; 323 324 /* Put the data in the MDI single read and write data register*/ 325 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 326 327 /* Setup and write the address cycle command */ 328 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 329 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 330 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 331 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 332 333 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 334 335 /* 336 * Check every 10 usec to see if the address cycle completed. 337 * The MDI Command bit will clear when the operation is 338 * complete 339 */ 340 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 341 udelay(10); 342 343 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 344 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 345 break; 346 } 347 348 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 349 hw_dbg(hw, "PHY address cmd didn't complete\n"); 350 return IXGBE_ERR_PHY; 351 } 352 353 /* 354 * Address cycle complete, setup and write the write 355 * command 356 */ 357 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 358 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 359 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 360 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 361 362 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 363 364 /* Check every 10 usec to see if the address cycle 365 * completed. The MDI Command bit will clear when the 366 * operation is complete 367 */ 368 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 369 udelay(10); 370 371 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 372 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 373 break; 374 } 375 376 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 377 hw_dbg(hw, "PHY write cmd didn't complete\n"); 378 return IXGBE_ERR_PHY; 379 } 380 381 return 0; 382 } 383 384 /** 385 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 386 * using SWFW lock- this function is needed in most cases 387 * @hw: pointer to hardware structure 388 * @reg_addr: 32 bit PHY register to write 389 * @device_type: 5 bit device type 390 * @phy_data: Data to write to the PHY register 391 **/ 392 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 393 u32 device_type, u16 phy_data) 394 { 395 s32 status; 396 u16 gssr; 397 398 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 399 gssr = IXGBE_GSSR_PHY1_SM; 400 else 401 gssr = IXGBE_GSSR_PHY0_SM; 402 403 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) { 404 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 405 phy_data); 406 hw->mac.ops.release_swfw_sync(hw, gssr); 407 } else { 408 status = IXGBE_ERR_SWFW_SYNC; 409 } 410 411 return status; 412 } 413 414 /** 415 * ixgbe_setup_phy_link_generic - Set and restart autoneg 416 * @hw: pointer to hardware structure 417 * 418 * Restart autonegotiation and PHY and waits for completion. 419 **/ 420 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 421 { 422 s32 status = 0; 423 u32 time_out; 424 u32 max_time_out = 10; 425 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 426 bool autoneg = false; 427 ixgbe_link_speed speed; 428 429 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 430 431 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 432 /* Set or unset auto-negotiation 10G advertisement */ 433 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 434 MDIO_MMD_AN, 435 &autoneg_reg); 436 437 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 438 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 439 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 440 441 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 442 MDIO_MMD_AN, 443 autoneg_reg); 444 } 445 446 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 447 /* Set or unset auto-negotiation 1G advertisement */ 448 hw->phy.ops.read_reg(hw, 449 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 450 MDIO_MMD_AN, 451 &autoneg_reg); 452 453 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 455 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 456 457 hw->phy.ops.write_reg(hw, 458 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 459 MDIO_MMD_AN, 460 autoneg_reg); 461 } 462 463 if (speed & IXGBE_LINK_SPEED_100_FULL) { 464 /* Set or unset auto-negotiation 100M advertisement */ 465 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 466 MDIO_MMD_AN, 467 &autoneg_reg); 468 469 autoneg_reg &= ~(ADVERTISE_100FULL | 470 ADVERTISE_100HALF); 471 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 472 autoneg_reg |= ADVERTISE_100FULL; 473 474 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 475 MDIO_MMD_AN, 476 autoneg_reg); 477 } 478 479 /* Restart PHY autonegotiation and wait for completion */ 480 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 481 MDIO_MMD_AN, &autoneg_reg); 482 483 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 484 485 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 486 MDIO_MMD_AN, autoneg_reg); 487 488 /* Wait for autonegotiation to finish */ 489 for (time_out = 0; time_out < max_time_out; time_out++) { 490 udelay(10); 491 /* Restart PHY autonegotiation and wait for completion */ 492 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, 493 MDIO_MMD_AN, 494 &autoneg_reg); 495 496 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 497 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { 498 break; 499 } 500 } 501 502 if (time_out == max_time_out) { 503 status = IXGBE_ERR_LINK_SETUP; 504 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out"); 505 } 506 507 return status; 508 } 509 510 /** 511 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 512 * @hw: pointer to hardware structure 513 * @speed: new link speed 514 **/ 515 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 516 ixgbe_link_speed speed, 517 bool autoneg_wait_to_complete) 518 { 519 520 /* 521 * Clear autoneg_advertised and set new values based on input link 522 * speed. 523 */ 524 hw->phy.autoneg_advertised = 0; 525 526 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 527 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 528 529 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 530 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 531 532 if (speed & IXGBE_LINK_SPEED_100_FULL) 533 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 534 535 /* Setup link based on the new speed settings */ 536 hw->phy.ops.setup_link(hw); 537 538 return 0; 539 } 540 541 /** 542 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 543 * @hw: pointer to hardware structure 544 * @speed: pointer to link speed 545 * @autoneg: boolean auto-negotiation value 546 * 547 * Determines the link capabilities by reading the AUTOC register. 548 */ 549 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 550 ixgbe_link_speed *speed, 551 bool *autoneg) 552 { 553 s32 status = IXGBE_ERR_LINK_SETUP; 554 u16 speed_ability; 555 556 *speed = 0; 557 *autoneg = true; 558 559 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 560 &speed_ability); 561 562 if (status == 0) { 563 if (speed_ability & MDIO_SPEED_10G) 564 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 565 if (speed_ability & MDIO_PMA_SPEED_1000) 566 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 567 if (speed_ability & MDIO_PMA_SPEED_100) 568 *speed |= IXGBE_LINK_SPEED_100_FULL; 569 } 570 571 return status; 572 } 573 574 /** 575 * ixgbe_check_phy_link_tnx - Determine link and speed status 576 * @hw: pointer to hardware structure 577 * 578 * Reads the VS1 register to determine if link is up and the current speed for 579 * the PHY. 580 **/ 581 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 582 bool *link_up) 583 { 584 s32 status = 0; 585 u32 time_out; 586 u32 max_time_out = 10; 587 u16 phy_link = 0; 588 u16 phy_speed = 0; 589 u16 phy_data = 0; 590 591 /* Initialize speed and link to default case */ 592 *link_up = false; 593 *speed = IXGBE_LINK_SPEED_10GB_FULL; 594 595 /* 596 * Check current speed and link status of the PHY register. 597 * This is a vendor specific register and may have to 598 * be changed for other copper PHYs. 599 */ 600 for (time_out = 0; time_out < max_time_out; time_out++) { 601 udelay(10); 602 status = hw->phy.ops.read_reg(hw, 603 MDIO_STAT1, 604 MDIO_MMD_VEND1, 605 &phy_data); 606 phy_link = phy_data & 607 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 608 phy_speed = phy_data & 609 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 610 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 611 *link_up = true; 612 if (phy_speed == 613 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 614 *speed = IXGBE_LINK_SPEED_1GB_FULL; 615 break; 616 } 617 } 618 619 return status; 620 } 621 622 /** 623 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 624 * @hw: pointer to hardware structure 625 * 626 * Restart autonegotiation and PHY and waits for completion. 627 **/ 628 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 629 { 630 s32 status = 0; 631 u32 time_out; 632 u32 max_time_out = 10; 633 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 634 bool autoneg = false; 635 ixgbe_link_speed speed; 636 637 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 638 639 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 640 /* Set or unset auto-negotiation 10G advertisement */ 641 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 642 MDIO_MMD_AN, 643 &autoneg_reg); 644 645 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 646 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 647 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 648 649 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 650 MDIO_MMD_AN, 651 autoneg_reg); 652 } 653 654 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 655 /* Set or unset auto-negotiation 1G advertisement */ 656 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 657 MDIO_MMD_AN, 658 &autoneg_reg); 659 660 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 661 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 662 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 663 664 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 665 MDIO_MMD_AN, 666 autoneg_reg); 667 } 668 669 if (speed & IXGBE_LINK_SPEED_100_FULL) { 670 /* Set or unset auto-negotiation 100M advertisement */ 671 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 672 MDIO_MMD_AN, 673 &autoneg_reg); 674 675 autoneg_reg &= ~(ADVERTISE_100FULL | 676 ADVERTISE_100HALF); 677 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 678 autoneg_reg |= ADVERTISE_100FULL; 679 680 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 681 MDIO_MMD_AN, 682 autoneg_reg); 683 } 684 685 /* Restart PHY autonegotiation and wait for completion */ 686 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 687 MDIO_MMD_AN, &autoneg_reg); 688 689 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 690 691 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 692 MDIO_MMD_AN, autoneg_reg); 693 694 /* Wait for autonegotiation to finish */ 695 for (time_out = 0; time_out < max_time_out; time_out++) { 696 udelay(10); 697 /* Restart PHY autonegotiation and wait for completion */ 698 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, 699 MDIO_MMD_AN, 700 &autoneg_reg); 701 702 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 703 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) 704 break; 705 } 706 707 if (time_out == max_time_out) { 708 status = IXGBE_ERR_LINK_SETUP; 709 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out"); 710 } 711 712 return status; 713 } 714 715 /** 716 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 717 * @hw: pointer to hardware structure 718 * @firmware_version: pointer to the PHY Firmware Version 719 **/ 720 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 721 u16 *firmware_version) 722 { 723 s32 status = 0; 724 725 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 726 MDIO_MMD_VEND1, 727 firmware_version); 728 729 return status; 730 } 731 732 /** 733 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 734 * @hw: pointer to hardware structure 735 * @firmware_version: pointer to the PHY Firmware Version 736 **/ 737 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 738 u16 *firmware_version) 739 { 740 s32 status = 0; 741 742 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 743 MDIO_MMD_VEND1, 744 firmware_version); 745 746 return status; 747 } 748 749 /** 750 * ixgbe_reset_phy_nl - Performs a PHY reset 751 * @hw: pointer to hardware structure 752 **/ 753 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 754 { 755 u16 phy_offset, control, eword, edata, block_crc; 756 bool end_data = false; 757 u16 list_offset, data_offset; 758 u16 phy_data = 0; 759 s32 ret_val = 0; 760 u32 i; 761 762 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 763 764 /* reset the PHY and poll for completion */ 765 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 766 (phy_data | MDIO_CTRL1_RESET)); 767 768 for (i = 0; i < 100; i++) { 769 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 770 &phy_data); 771 if ((phy_data & MDIO_CTRL1_RESET) == 0) 772 break; 773 usleep_range(10000, 20000); 774 } 775 776 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 777 hw_dbg(hw, "PHY reset did not complete.\n"); 778 ret_val = IXGBE_ERR_PHY; 779 goto out; 780 } 781 782 /* Get init offsets */ 783 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 784 &data_offset); 785 if (ret_val != 0) 786 goto out; 787 788 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 789 data_offset++; 790 while (!end_data) { 791 /* 792 * Read control word from PHY init contents offset 793 */ 794 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 795 if (ret_val) 796 goto err_eeprom; 797 control = (eword & IXGBE_CONTROL_MASK_NL) >> 798 IXGBE_CONTROL_SHIFT_NL; 799 edata = eword & IXGBE_DATA_MASK_NL; 800 switch (control) { 801 case IXGBE_DELAY_NL: 802 data_offset++; 803 hw_dbg(hw, "DELAY: %d MS\n", edata); 804 usleep_range(edata * 1000, edata * 2000); 805 break; 806 case IXGBE_DATA_NL: 807 hw_dbg(hw, "DATA:\n"); 808 data_offset++; 809 ret_val = hw->eeprom.ops.read(hw, data_offset++, 810 &phy_offset); 811 if (ret_val) 812 goto err_eeprom; 813 for (i = 0; i < edata; i++) { 814 ret_val = hw->eeprom.ops.read(hw, data_offset, 815 &eword); 816 if (ret_val) 817 goto err_eeprom; 818 hw->phy.ops.write_reg(hw, phy_offset, 819 MDIO_MMD_PMAPMD, eword); 820 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 821 phy_offset); 822 data_offset++; 823 phy_offset++; 824 } 825 break; 826 case IXGBE_CONTROL_NL: 827 data_offset++; 828 hw_dbg(hw, "CONTROL:\n"); 829 if (edata == IXGBE_CONTROL_EOL_NL) { 830 hw_dbg(hw, "EOL\n"); 831 end_data = true; 832 } else if (edata == IXGBE_CONTROL_SOL_NL) { 833 hw_dbg(hw, "SOL\n"); 834 } else { 835 hw_dbg(hw, "Bad control value\n"); 836 ret_val = IXGBE_ERR_PHY; 837 goto out; 838 } 839 break; 840 default: 841 hw_dbg(hw, "Bad control type\n"); 842 ret_val = IXGBE_ERR_PHY; 843 goto out; 844 } 845 } 846 847 out: 848 return ret_val; 849 850 err_eeprom: 851 hw_err(hw, "eeprom read at offset %d failed\n", data_offset); 852 return IXGBE_ERR_PHY; 853 } 854 855 /** 856 * ixgbe_identify_module_generic - Identifies module type 857 * @hw: pointer to hardware structure 858 * 859 * Determines HW type and calls appropriate function. 860 **/ 861 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 862 { 863 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 864 865 switch (hw->mac.ops.get_media_type(hw)) { 866 case ixgbe_media_type_fiber: 867 status = ixgbe_identify_sfp_module_generic(hw); 868 break; 869 case ixgbe_media_type_fiber_qsfp: 870 status = ixgbe_identify_qsfp_module_generic(hw); 871 break; 872 default: 873 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 874 status = IXGBE_ERR_SFP_NOT_PRESENT; 875 break; 876 } 877 878 return status; 879 } 880 881 /** 882 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 883 * @hw: pointer to hardware structure 884 * 885 * Searches for and identifies the SFP module and assigns appropriate PHY type. 886 **/ 887 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 888 { 889 struct ixgbe_adapter *adapter = hw->back; 890 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 891 u32 vendor_oui = 0; 892 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 893 u8 identifier = 0; 894 u8 comp_codes_1g = 0; 895 u8 comp_codes_10g = 0; 896 u8 oui_bytes[3] = {0, 0, 0}; 897 u8 cable_tech = 0; 898 u8 cable_spec = 0; 899 u16 enforce_sfp = 0; 900 901 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 902 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 903 status = IXGBE_ERR_SFP_NOT_PRESENT; 904 goto out; 905 } 906 907 status = hw->phy.ops.read_i2c_eeprom(hw, 908 IXGBE_SFF_IDENTIFIER, 909 &identifier); 910 911 if (status != 0) 912 goto err_read_i2c_eeprom; 913 914 /* LAN ID is needed for sfp_type determination */ 915 hw->mac.ops.set_lan_id(hw); 916 917 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 918 hw->phy.type = ixgbe_phy_sfp_unsupported; 919 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 920 } else { 921 status = hw->phy.ops.read_i2c_eeprom(hw, 922 IXGBE_SFF_1GBE_COMP_CODES, 923 &comp_codes_1g); 924 925 if (status != 0) 926 goto err_read_i2c_eeprom; 927 928 status = hw->phy.ops.read_i2c_eeprom(hw, 929 IXGBE_SFF_10GBE_COMP_CODES, 930 &comp_codes_10g); 931 932 if (status != 0) 933 goto err_read_i2c_eeprom; 934 status = hw->phy.ops.read_i2c_eeprom(hw, 935 IXGBE_SFF_CABLE_TECHNOLOGY, 936 &cable_tech); 937 938 if (status != 0) 939 goto err_read_i2c_eeprom; 940 941 /* ID Module 942 * ========= 943 * 0 SFP_DA_CU 944 * 1 SFP_SR 945 * 2 SFP_LR 946 * 3 SFP_DA_CORE0 - 82599-specific 947 * 4 SFP_DA_CORE1 - 82599-specific 948 * 5 SFP_SR/LR_CORE0 - 82599-specific 949 * 6 SFP_SR/LR_CORE1 - 82599-specific 950 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 951 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 952 * 9 SFP_1g_cu_CORE0 - 82599-specific 953 * 10 SFP_1g_cu_CORE1 - 82599-specific 954 * 11 SFP_1g_sx_CORE0 - 82599-specific 955 * 12 SFP_1g_sx_CORE1 - 82599-specific 956 */ 957 if (hw->mac.type == ixgbe_mac_82598EB) { 958 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 959 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 960 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 961 hw->phy.sfp_type = ixgbe_sfp_type_sr; 962 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 963 hw->phy.sfp_type = ixgbe_sfp_type_lr; 964 else 965 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 966 } else if (hw->mac.type == ixgbe_mac_82599EB) { 967 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 968 if (hw->bus.lan_id == 0) 969 hw->phy.sfp_type = 970 ixgbe_sfp_type_da_cu_core0; 971 else 972 hw->phy.sfp_type = 973 ixgbe_sfp_type_da_cu_core1; 974 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 975 hw->phy.ops.read_i2c_eeprom( 976 hw, IXGBE_SFF_CABLE_SPEC_COMP, 977 &cable_spec); 978 if (cable_spec & 979 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 980 if (hw->bus.lan_id == 0) 981 hw->phy.sfp_type = 982 ixgbe_sfp_type_da_act_lmt_core0; 983 else 984 hw->phy.sfp_type = 985 ixgbe_sfp_type_da_act_lmt_core1; 986 } else { 987 hw->phy.sfp_type = 988 ixgbe_sfp_type_unknown; 989 } 990 } else if (comp_codes_10g & 991 (IXGBE_SFF_10GBASESR_CAPABLE | 992 IXGBE_SFF_10GBASELR_CAPABLE)) { 993 if (hw->bus.lan_id == 0) 994 hw->phy.sfp_type = 995 ixgbe_sfp_type_srlr_core0; 996 else 997 hw->phy.sfp_type = 998 ixgbe_sfp_type_srlr_core1; 999 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1000 if (hw->bus.lan_id == 0) 1001 hw->phy.sfp_type = 1002 ixgbe_sfp_type_1g_cu_core0; 1003 else 1004 hw->phy.sfp_type = 1005 ixgbe_sfp_type_1g_cu_core1; 1006 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1007 if (hw->bus.lan_id == 0) 1008 hw->phy.sfp_type = 1009 ixgbe_sfp_type_1g_sx_core0; 1010 else 1011 hw->phy.sfp_type = 1012 ixgbe_sfp_type_1g_sx_core1; 1013 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1014 if (hw->bus.lan_id == 0) 1015 hw->phy.sfp_type = 1016 ixgbe_sfp_type_1g_lx_core0; 1017 else 1018 hw->phy.sfp_type = 1019 ixgbe_sfp_type_1g_lx_core1; 1020 } else { 1021 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1022 } 1023 } 1024 1025 if (hw->phy.sfp_type != stored_sfp_type) 1026 hw->phy.sfp_setup_needed = true; 1027 1028 /* Determine if the SFP+ PHY is dual speed or not. */ 1029 hw->phy.multispeed_fiber = false; 1030 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1031 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1032 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1033 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1034 hw->phy.multispeed_fiber = true; 1035 1036 /* Determine PHY vendor */ 1037 if (hw->phy.type != ixgbe_phy_nl) { 1038 hw->phy.id = identifier; 1039 status = hw->phy.ops.read_i2c_eeprom(hw, 1040 IXGBE_SFF_VENDOR_OUI_BYTE0, 1041 &oui_bytes[0]); 1042 1043 if (status != 0) 1044 goto err_read_i2c_eeprom; 1045 1046 status = hw->phy.ops.read_i2c_eeprom(hw, 1047 IXGBE_SFF_VENDOR_OUI_BYTE1, 1048 &oui_bytes[1]); 1049 1050 if (status != 0) 1051 goto err_read_i2c_eeprom; 1052 1053 status = hw->phy.ops.read_i2c_eeprom(hw, 1054 IXGBE_SFF_VENDOR_OUI_BYTE2, 1055 &oui_bytes[2]); 1056 1057 if (status != 0) 1058 goto err_read_i2c_eeprom; 1059 1060 vendor_oui = 1061 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1062 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1063 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1064 1065 switch (vendor_oui) { 1066 case IXGBE_SFF_VENDOR_OUI_TYCO: 1067 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1068 hw->phy.type = 1069 ixgbe_phy_sfp_passive_tyco; 1070 break; 1071 case IXGBE_SFF_VENDOR_OUI_FTL: 1072 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1073 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1074 else 1075 hw->phy.type = ixgbe_phy_sfp_ftl; 1076 break; 1077 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1078 hw->phy.type = ixgbe_phy_sfp_avago; 1079 break; 1080 case IXGBE_SFF_VENDOR_OUI_INTEL: 1081 hw->phy.type = ixgbe_phy_sfp_intel; 1082 break; 1083 default: 1084 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1085 hw->phy.type = 1086 ixgbe_phy_sfp_passive_unknown; 1087 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1088 hw->phy.type = 1089 ixgbe_phy_sfp_active_unknown; 1090 else 1091 hw->phy.type = ixgbe_phy_sfp_unknown; 1092 break; 1093 } 1094 } 1095 1096 /* Allow any DA cable vendor */ 1097 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1098 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1099 status = 0; 1100 goto out; 1101 } 1102 1103 /* Verify supported 1G SFP modules */ 1104 if (comp_codes_10g == 0 && 1105 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1106 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1107 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1108 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1109 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1110 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1111 hw->phy.type = ixgbe_phy_sfp_unsupported; 1112 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1113 goto out; 1114 } 1115 1116 /* Anything else 82598-based is supported */ 1117 if (hw->mac.type == ixgbe_mac_82598EB) { 1118 status = 0; 1119 goto out; 1120 } 1121 1122 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1123 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1124 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1125 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1126 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1127 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1128 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1129 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1130 /* Make sure we're a supported PHY type */ 1131 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1132 status = 0; 1133 } else { 1134 if (hw->allow_unsupported_sfp) { 1135 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules."); 1136 status = 0; 1137 } else { 1138 hw_dbg(hw, 1139 "SFP+ module not supported\n"); 1140 hw->phy.type = 1141 ixgbe_phy_sfp_unsupported; 1142 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1143 } 1144 } 1145 } else { 1146 status = 0; 1147 } 1148 } 1149 1150 out: 1151 return status; 1152 1153 err_read_i2c_eeprom: 1154 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1155 if (hw->phy.type != ixgbe_phy_nl) { 1156 hw->phy.id = 0; 1157 hw->phy.type = ixgbe_phy_unknown; 1158 } 1159 return IXGBE_ERR_SFP_NOT_PRESENT; 1160 } 1161 1162 /** 1163 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1164 * @hw: pointer to hardware structure 1165 * 1166 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1167 **/ 1168 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1169 { 1170 struct ixgbe_adapter *adapter = hw->back; 1171 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1172 u32 vendor_oui = 0; 1173 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1174 u8 identifier = 0; 1175 u8 comp_codes_1g = 0; 1176 u8 comp_codes_10g = 0; 1177 u8 oui_bytes[3] = {0, 0, 0}; 1178 u16 enforce_sfp = 0; 1179 u8 connector = 0; 1180 u8 cable_length = 0; 1181 u8 device_tech = 0; 1182 bool active_cable = false; 1183 1184 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1185 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1186 status = IXGBE_ERR_SFP_NOT_PRESENT; 1187 goto out; 1188 } 1189 1190 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1191 &identifier); 1192 1193 if (status != 0) 1194 goto err_read_i2c_eeprom; 1195 1196 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1197 hw->phy.type = ixgbe_phy_sfp_unsupported; 1198 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1199 goto out; 1200 } 1201 1202 hw->phy.id = identifier; 1203 1204 /* LAN ID is needed for sfp_type determination */ 1205 hw->mac.ops.set_lan_id(hw); 1206 1207 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1208 &comp_codes_10g); 1209 1210 if (status != 0) 1211 goto err_read_i2c_eeprom; 1212 1213 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1214 &comp_codes_1g); 1215 1216 if (status != 0) 1217 goto err_read_i2c_eeprom; 1218 1219 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1220 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1221 if (hw->bus.lan_id == 0) 1222 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1223 else 1224 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1225 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1226 IXGBE_SFF_10GBASELR_CAPABLE)) { 1227 if (hw->bus.lan_id == 0) 1228 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1229 else 1230 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1231 } else { 1232 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1233 active_cable = true; 1234 1235 if (!active_cable) { 1236 /* check for active DA cables that pre-date 1237 * SFF-8436 v3.6 1238 */ 1239 hw->phy.ops.read_i2c_eeprom(hw, 1240 IXGBE_SFF_QSFP_CONNECTOR, 1241 &connector); 1242 1243 hw->phy.ops.read_i2c_eeprom(hw, 1244 IXGBE_SFF_QSFP_CABLE_LENGTH, 1245 &cable_length); 1246 1247 hw->phy.ops.read_i2c_eeprom(hw, 1248 IXGBE_SFF_QSFP_DEVICE_TECH, 1249 &device_tech); 1250 1251 if ((connector == 1252 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1253 (cable_length > 0) && 1254 ((device_tech >> 4) == 1255 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1256 active_cable = true; 1257 } 1258 1259 if (active_cable) { 1260 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1261 if (hw->bus.lan_id == 0) 1262 hw->phy.sfp_type = 1263 ixgbe_sfp_type_da_act_lmt_core0; 1264 else 1265 hw->phy.sfp_type = 1266 ixgbe_sfp_type_da_act_lmt_core1; 1267 } else { 1268 /* unsupported module type */ 1269 hw->phy.type = ixgbe_phy_sfp_unsupported; 1270 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1271 goto out; 1272 } 1273 } 1274 1275 if (hw->phy.sfp_type != stored_sfp_type) 1276 hw->phy.sfp_setup_needed = true; 1277 1278 /* Determine if the QSFP+ PHY is dual speed or not. */ 1279 hw->phy.multispeed_fiber = false; 1280 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1281 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1282 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1283 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1284 hw->phy.multispeed_fiber = true; 1285 1286 /* Determine PHY vendor for optical modules */ 1287 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1288 IXGBE_SFF_10GBASELR_CAPABLE)) { 1289 status = hw->phy.ops.read_i2c_eeprom(hw, 1290 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1291 &oui_bytes[0]); 1292 1293 if (status != 0) 1294 goto err_read_i2c_eeprom; 1295 1296 status = hw->phy.ops.read_i2c_eeprom(hw, 1297 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1298 &oui_bytes[1]); 1299 1300 if (status != 0) 1301 goto err_read_i2c_eeprom; 1302 1303 status = hw->phy.ops.read_i2c_eeprom(hw, 1304 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1305 &oui_bytes[2]); 1306 1307 if (status != 0) 1308 goto err_read_i2c_eeprom; 1309 1310 vendor_oui = 1311 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1312 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1313 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1314 1315 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1316 hw->phy.type = ixgbe_phy_qsfp_intel; 1317 else 1318 hw->phy.type = ixgbe_phy_qsfp_unknown; 1319 1320 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1321 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1322 /* Make sure we're a supported PHY type */ 1323 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1324 status = 0; 1325 } else { 1326 if (hw->allow_unsupported_sfp == true) { 1327 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1328 status = 0; 1329 } else { 1330 hw_dbg(hw, 1331 "QSFP module not supported\n"); 1332 hw->phy.type = 1333 ixgbe_phy_sfp_unsupported; 1334 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1335 } 1336 } 1337 } else { 1338 status = 0; 1339 } 1340 } 1341 1342 out: 1343 return status; 1344 1345 err_read_i2c_eeprom: 1346 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1347 hw->phy.id = 0; 1348 hw->phy.type = ixgbe_phy_unknown; 1349 1350 return IXGBE_ERR_SFP_NOT_PRESENT; 1351 } 1352 1353 /** 1354 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1355 * @hw: pointer to hardware structure 1356 * @list_offset: offset to the SFP ID list 1357 * @data_offset: offset to the SFP data block 1358 * 1359 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1360 * so it returns the offsets to the phy init sequence block. 1361 **/ 1362 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1363 u16 *list_offset, 1364 u16 *data_offset) 1365 { 1366 u16 sfp_id; 1367 u16 sfp_type = hw->phy.sfp_type; 1368 1369 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1370 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1371 1372 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1373 return IXGBE_ERR_SFP_NOT_PRESENT; 1374 1375 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1376 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1377 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1378 1379 /* 1380 * Limiting active cables and 1G Phys must be initialized as 1381 * SR modules 1382 */ 1383 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1384 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1385 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1386 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1387 sfp_type = ixgbe_sfp_type_srlr_core0; 1388 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1389 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1390 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1391 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1392 sfp_type = ixgbe_sfp_type_srlr_core1; 1393 1394 /* Read offset to PHY init contents */ 1395 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1396 hw_err(hw, "eeprom read at %d failed\n", 1397 IXGBE_PHY_INIT_OFFSET_NL); 1398 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1399 } 1400 1401 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1402 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1403 1404 /* Shift offset to first ID word */ 1405 (*list_offset)++; 1406 1407 /* 1408 * Find the matching SFP ID in the EEPROM 1409 * and program the init sequence 1410 */ 1411 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1412 goto err_phy; 1413 1414 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1415 if (sfp_id == sfp_type) { 1416 (*list_offset)++; 1417 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1418 goto err_phy; 1419 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1420 hw_dbg(hw, "SFP+ module not supported\n"); 1421 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1422 } else { 1423 break; 1424 } 1425 } else { 1426 (*list_offset) += 2; 1427 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1428 goto err_phy; 1429 } 1430 } 1431 1432 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1433 hw_dbg(hw, "No matching SFP+ module found\n"); 1434 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1435 } 1436 1437 return 0; 1438 1439 err_phy: 1440 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset); 1441 return IXGBE_ERR_PHY; 1442 } 1443 1444 /** 1445 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1446 * @hw: pointer to hardware structure 1447 * @byte_offset: EEPROM byte offset to read 1448 * @eeprom_data: value read 1449 * 1450 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1451 **/ 1452 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1453 u8 *eeprom_data) 1454 { 1455 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1456 IXGBE_I2C_EEPROM_DEV_ADDR, 1457 eeprom_data); 1458 } 1459 1460 /** 1461 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1462 * @hw: pointer to hardware structure 1463 * @byte_offset: byte offset at address 0xA2 1464 * @eeprom_data: value read 1465 * 1466 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1467 **/ 1468 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1469 u8 *sff8472_data) 1470 { 1471 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1472 IXGBE_I2C_EEPROM_DEV_ADDR2, 1473 sff8472_data); 1474 } 1475 1476 /** 1477 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1478 * @hw: pointer to hardware structure 1479 * @byte_offset: EEPROM byte offset to write 1480 * @eeprom_data: value to write 1481 * 1482 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1483 **/ 1484 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1485 u8 eeprom_data) 1486 { 1487 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1488 IXGBE_I2C_EEPROM_DEV_ADDR, 1489 eeprom_data); 1490 } 1491 1492 /** 1493 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1494 * @hw: pointer to hardware structure 1495 * @byte_offset: byte offset to read 1496 * @data: value read 1497 * 1498 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1499 * a specified device address. 1500 **/ 1501 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1502 u8 dev_addr, u8 *data) 1503 { 1504 s32 status = 0; 1505 u32 max_retry = 10; 1506 u32 retry = 0; 1507 u16 swfw_mask = 0; 1508 bool nack = true; 1509 *data = 0; 1510 1511 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1512 swfw_mask = IXGBE_GSSR_PHY1_SM; 1513 else 1514 swfw_mask = IXGBE_GSSR_PHY0_SM; 1515 1516 do { 1517 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { 1518 status = IXGBE_ERR_SWFW_SYNC; 1519 goto read_byte_out; 1520 } 1521 1522 ixgbe_i2c_start(hw); 1523 1524 /* Device Address and write indication */ 1525 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1526 if (status != 0) 1527 goto fail; 1528 1529 status = ixgbe_get_i2c_ack(hw); 1530 if (status != 0) 1531 goto fail; 1532 1533 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1534 if (status != 0) 1535 goto fail; 1536 1537 status = ixgbe_get_i2c_ack(hw); 1538 if (status != 0) 1539 goto fail; 1540 1541 ixgbe_i2c_start(hw); 1542 1543 /* Device Address and read indication */ 1544 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1545 if (status != 0) 1546 goto fail; 1547 1548 status = ixgbe_get_i2c_ack(hw); 1549 if (status != 0) 1550 goto fail; 1551 1552 status = ixgbe_clock_in_i2c_byte(hw, data); 1553 if (status != 0) 1554 goto fail; 1555 1556 status = ixgbe_clock_out_i2c_bit(hw, nack); 1557 if (status != 0) 1558 goto fail; 1559 1560 ixgbe_i2c_stop(hw); 1561 break; 1562 1563 fail: 1564 ixgbe_i2c_bus_clear(hw); 1565 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1566 msleep(100); 1567 retry++; 1568 if (retry < max_retry) 1569 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 1570 else 1571 hw_dbg(hw, "I2C byte read error.\n"); 1572 1573 } while (retry < max_retry); 1574 1575 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1576 1577 read_byte_out: 1578 return status; 1579 } 1580 1581 /** 1582 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1583 * @hw: pointer to hardware structure 1584 * @byte_offset: byte offset to write 1585 * @data: value to write 1586 * 1587 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1588 * a specified device address. 1589 **/ 1590 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1591 u8 dev_addr, u8 data) 1592 { 1593 s32 status = 0; 1594 u32 max_retry = 1; 1595 u32 retry = 0; 1596 u16 swfw_mask = 0; 1597 1598 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1599 swfw_mask = IXGBE_GSSR_PHY1_SM; 1600 else 1601 swfw_mask = IXGBE_GSSR_PHY0_SM; 1602 1603 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { 1604 status = IXGBE_ERR_SWFW_SYNC; 1605 goto write_byte_out; 1606 } 1607 1608 do { 1609 ixgbe_i2c_start(hw); 1610 1611 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1612 if (status != 0) 1613 goto fail; 1614 1615 status = ixgbe_get_i2c_ack(hw); 1616 if (status != 0) 1617 goto fail; 1618 1619 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1620 if (status != 0) 1621 goto fail; 1622 1623 status = ixgbe_get_i2c_ack(hw); 1624 if (status != 0) 1625 goto fail; 1626 1627 status = ixgbe_clock_out_i2c_byte(hw, data); 1628 if (status != 0) 1629 goto fail; 1630 1631 status = ixgbe_get_i2c_ack(hw); 1632 if (status != 0) 1633 goto fail; 1634 1635 ixgbe_i2c_stop(hw); 1636 break; 1637 1638 fail: 1639 ixgbe_i2c_bus_clear(hw); 1640 retry++; 1641 if (retry < max_retry) 1642 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 1643 else 1644 hw_dbg(hw, "I2C byte write error.\n"); 1645 } while (retry < max_retry); 1646 1647 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1648 1649 write_byte_out: 1650 return status; 1651 } 1652 1653 /** 1654 * ixgbe_i2c_start - Sets I2C start condition 1655 * @hw: pointer to hardware structure 1656 * 1657 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1658 **/ 1659 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1660 { 1661 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1662 1663 /* Start condition must begin with data and clock high */ 1664 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1665 ixgbe_raise_i2c_clk(hw, &i2cctl); 1666 1667 /* Setup time for start condition (4.7us) */ 1668 udelay(IXGBE_I2C_T_SU_STA); 1669 1670 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1671 1672 /* Hold time for start condition (4us) */ 1673 udelay(IXGBE_I2C_T_HD_STA); 1674 1675 ixgbe_lower_i2c_clk(hw, &i2cctl); 1676 1677 /* Minimum low period of clock is 4.7 us */ 1678 udelay(IXGBE_I2C_T_LOW); 1679 1680 } 1681 1682 /** 1683 * ixgbe_i2c_stop - Sets I2C stop condition 1684 * @hw: pointer to hardware structure 1685 * 1686 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1687 **/ 1688 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1689 { 1690 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1691 1692 /* Stop condition must begin with data low and clock high */ 1693 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1694 ixgbe_raise_i2c_clk(hw, &i2cctl); 1695 1696 /* Setup time for stop condition (4us) */ 1697 udelay(IXGBE_I2C_T_SU_STO); 1698 1699 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1700 1701 /* bus free time between stop and start (4.7us)*/ 1702 udelay(IXGBE_I2C_T_BUF); 1703 } 1704 1705 /** 1706 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1707 * @hw: pointer to hardware structure 1708 * @data: data byte to clock in 1709 * 1710 * Clocks in one byte data via I2C data/clock 1711 **/ 1712 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1713 { 1714 s32 i; 1715 bool bit = false; 1716 1717 for (i = 7; i >= 0; i--) { 1718 ixgbe_clock_in_i2c_bit(hw, &bit); 1719 *data |= bit << i; 1720 } 1721 1722 return 0; 1723 } 1724 1725 /** 1726 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1727 * @hw: pointer to hardware structure 1728 * @data: data byte clocked out 1729 * 1730 * Clocks out one byte data via I2C data/clock 1731 **/ 1732 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1733 { 1734 s32 status = 0; 1735 s32 i; 1736 u32 i2cctl; 1737 bool bit = false; 1738 1739 for (i = 7; i >= 0; i--) { 1740 bit = (data >> i) & 0x1; 1741 status = ixgbe_clock_out_i2c_bit(hw, bit); 1742 1743 if (status != 0) 1744 break; 1745 } 1746 1747 /* Release SDA line (set high) */ 1748 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1749 i2cctl |= IXGBE_I2C_DATA_OUT; 1750 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1751 IXGBE_WRITE_FLUSH(hw); 1752 1753 return status; 1754 } 1755 1756 /** 1757 * ixgbe_get_i2c_ack - Polls for I2C ACK 1758 * @hw: pointer to hardware structure 1759 * 1760 * Clocks in/out one bit via I2C data/clock 1761 **/ 1762 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1763 { 1764 s32 status = 0; 1765 u32 i = 0; 1766 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1767 u32 timeout = 10; 1768 bool ack = true; 1769 1770 ixgbe_raise_i2c_clk(hw, &i2cctl); 1771 1772 1773 /* Minimum high period of clock is 4us */ 1774 udelay(IXGBE_I2C_T_HIGH); 1775 1776 /* Poll for ACK. Note that ACK in I2C spec is 1777 * transition from 1 to 0 */ 1778 for (i = 0; i < timeout; i++) { 1779 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1780 ack = ixgbe_get_i2c_data(&i2cctl); 1781 1782 udelay(1); 1783 if (ack == 0) 1784 break; 1785 } 1786 1787 if (ack == 1) { 1788 hw_dbg(hw, "I2C ack was not received.\n"); 1789 status = IXGBE_ERR_I2C; 1790 } 1791 1792 ixgbe_lower_i2c_clk(hw, &i2cctl); 1793 1794 /* Minimum low period of clock is 4.7 us */ 1795 udelay(IXGBE_I2C_T_LOW); 1796 1797 return status; 1798 } 1799 1800 /** 1801 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1802 * @hw: pointer to hardware structure 1803 * @data: read data value 1804 * 1805 * Clocks in one bit via I2C data/clock 1806 **/ 1807 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1808 { 1809 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1810 1811 ixgbe_raise_i2c_clk(hw, &i2cctl); 1812 1813 /* Minimum high period of clock is 4us */ 1814 udelay(IXGBE_I2C_T_HIGH); 1815 1816 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1817 *data = ixgbe_get_i2c_data(&i2cctl); 1818 1819 ixgbe_lower_i2c_clk(hw, &i2cctl); 1820 1821 /* Minimum low period of clock is 4.7 us */ 1822 udelay(IXGBE_I2C_T_LOW); 1823 1824 return 0; 1825 } 1826 1827 /** 1828 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1829 * @hw: pointer to hardware structure 1830 * @data: data value to write 1831 * 1832 * Clocks out one bit via I2C data/clock 1833 **/ 1834 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1835 { 1836 s32 status; 1837 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1838 1839 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1840 if (status == 0) { 1841 ixgbe_raise_i2c_clk(hw, &i2cctl); 1842 1843 /* Minimum high period of clock is 4us */ 1844 udelay(IXGBE_I2C_T_HIGH); 1845 1846 ixgbe_lower_i2c_clk(hw, &i2cctl); 1847 1848 /* Minimum low period of clock is 4.7 us. 1849 * This also takes care of the data hold time. 1850 */ 1851 udelay(IXGBE_I2C_T_LOW); 1852 } else { 1853 status = IXGBE_ERR_I2C; 1854 hw_dbg(hw, "I2C data was not set to %X\n", data); 1855 } 1856 1857 return status; 1858 } 1859 /** 1860 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1861 * @hw: pointer to hardware structure 1862 * @i2cctl: Current value of I2CCTL register 1863 * 1864 * Raises the I2C clock line '0'->'1' 1865 **/ 1866 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1867 { 1868 u32 i = 0; 1869 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1870 u32 i2cctl_r = 0; 1871 1872 for (i = 0; i < timeout; i++) { 1873 *i2cctl |= IXGBE_I2C_CLK_OUT; 1874 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1875 IXGBE_WRITE_FLUSH(hw); 1876 /* SCL rise time (1000ns) */ 1877 udelay(IXGBE_I2C_T_RISE); 1878 1879 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1880 if (i2cctl_r & IXGBE_I2C_CLK_IN) 1881 break; 1882 } 1883 } 1884 1885 /** 1886 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1887 * @hw: pointer to hardware structure 1888 * @i2cctl: Current value of I2CCTL register 1889 * 1890 * Lowers the I2C clock line '1'->'0' 1891 **/ 1892 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1893 { 1894 1895 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1896 1897 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1898 IXGBE_WRITE_FLUSH(hw); 1899 1900 /* SCL fall time (300ns) */ 1901 udelay(IXGBE_I2C_T_FALL); 1902 } 1903 1904 /** 1905 * ixgbe_set_i2c_data - Sets the I2C data bit 1906 * @hw: pointer to hardware structure 1907 * @i2cctl: Current value of I2CCTL register 1908 * @data: I2C data value (0 or 1) to set 1909 * 1910 * Sets the I2C data bit 1911 **/ 1912 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1913 { 1914 s32 status = 0; 1915 1916 if (data) 1917 *i2cctl |= IXGBE_I2C_DATA_OUT; 1918 else 1919 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1920 1921 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1922 IXGBE_WRITE_FLUSH(hw); 1923 1924 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1925 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1926 1927 /* Verify data was set correctly */ 1928 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1929 if (data != ixgbe_get_i2c_data(i2cctl)) { 1930 status = IXGBE_ERR_I2C; 1931 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 1932 } 1933 1934 return status; 1935 } 1936 1937 /** 1938 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1939 * @hw: pointer to hardware structure 1940 * @i2cctl: Current value of I2CCTL register 1941 * 1942 * Returns the I2C data bit value 1943 **/ 1944 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1945 { 1946 bool data; 1947 1948 if (*i2cctl & IXGBE_I2C_DATA_IN) 1949 data = true; 1950 else 1951 data = false; 1952 1953 return data; 1954 } 1955 1956 /** 1957 * ixgbe_i2c_bus_clear - Clears the I2C bus 1958 * @hw: pointer to hardware structure 1959 * 1960 * Clears the I2C bus by sending nine clock pulses. 1961 * Used when data line is stuck low. 1962 **/ 1963 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1964 { 1965 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1966 u32 i; 1967 1968 ixgbe_i2c_start(hw); 1969 1970 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1971 1972 for (i = 0; i < 9; i++) { 1973 ixgbe_raise_i2c_clk(hw, &i2cctl); 1974 1975 /* Min high period of clock is 4us */ 1976 udelay(IXGBE_I2C_T_HIGH); 1977 1978 ixgbe_lower_i2c_clk(hw, &i2cctl); 1979 1980 /* Min low period of clock is 4.7us*/ 1981 udelay(IXGBE_I2C_T_LOW); 1982 } 1983 1984 ixgbe_i2c_start(hw); 1985 1986 /* Put the i2c bus back to default state */ 1987 ixgbe_i2c_stop(hw); 1988 } 1989 1990 /** 1991 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1992 * @hw: pointer to hardware structure 1993 * 1994 * Checks if the LASI temp alarm status was triggered due to overtemp 1995 **/ 1996 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1997 { 1998 s32 status = 0; 1999 u16 phy_data = 0; 2000 2001 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2002 goto out; 2003 2004 /* Check that the LASI temp alarm status was triggered */ 2005 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2006 MDIO_MMD_PMAPMD, &phy_data); 2007 2008 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2009 goto out; 2010 2011 status = IXGBE_ERR_OVERTEMP; 2012 out: 2013 return status; 2014 } 2015