1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 #include <linux/sched.h> 31 32 #include "ixgbe_common.h" 33 #include "ixgbe_phy.h" 34 35 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 42 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 45 static bool ixgbe_get_i2c_data(u32 *i2cctl); 46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 49 50 /** 51 * ixgbe_identify_phy_generic - Get physical layer module 52 * @hw: pointer to hardware structure 53 * 54 * Determines the physical layer module found on the current adapter. 55 **/ 56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 57 { 58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 59 u32 phy_addr; 60 u16 ext_ability = 0; 61 62 if (hw->phy.type == ixgbe_phy_unknown) { 63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 64 hw->phy.mdio.prtad = phy_addr; 65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { 66 ixgbe_get_phy_id(hw); 67 hw->phy.type = 68 ixgbe_get_phy_type_from_id(hw->phy.id); 69 70 if (hw->phy.type == ixgbe_phy_unknown) { 71 hw->phy.ops.read_reg(hw, 72 MDIO_PMA_EXTABLE, 73 MDIO_MMD_PMAPMD, 74 &ext_ability); 75 if (ext_ability & 76 (MDIO_PMA_EXTABLE_10GBT | 77 MDIO_PMA_EXTABLE_1000BT)) 78 hw->phy.type = 79 ixgbe_phy_cu_unknown; 80 else 81 hw->phy.type = 82 ixgbe_phy_generic; 83 } 84 85 status = 0; 86 break; 87 } 88 } 89 /* clear value if nothing found */ 90 if (status != 0) 91 hw->phy.mdio.prtad = 0; 92 } else { 93 status = 0; 94 } 95 96 return status; 97 } 98 99 /** 100 * ixgbe_get_phy_id - Get the phy type 101 * @hw: pointer to hardware structure 102 * 103 **/ 104 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 105 { 106 u32 status; 107 u16 phy_id_high = 0; 108 u16 phy_id_low = 0; 109 110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, 111 &phy_id_high); 112 113 if (status == 0) { 114 hw->phy.id = (u32)(phy_id_high << 16); 115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, 116 &phy_id_low); 117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 119 } 120 return status; 121 } 122 123 /** 124 * ixgbe_get_phy_type_from_id - Get the phy type 125 * @hw: pointer to hardware structure 126 * 127 **/ 128 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 129 { 130 enum ixgbe_phy_type phy_type; 131 132 switch (phy_id) { 133 case TN1010_PHY_ID: 134 phy_type = ixgbe_phy_tn; 135 break; 136 case X540_PHY_ID: 137 phy_type = ixgbe_phy_aq; 138 break; 139 case QT2022_PHY_ID: 140 phy_type = ixgbe_phy_qt; 141 break; 142 case ATH_PHY_ID: 143 phy_type = ixgbe_phy_nl; 144 break; 145 default: 146 phy_type = ixgbe_phy_unknown; 147 break; 148 } 149 150 return phy_type; 151 } 152 153 /** 154 * ixgbe_reset_phy_generic - Performs a PHY reset 155 * @hw: pointer to hardware structure 156 **/ 157 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 158 { 159 u32 i; 160 u16 ctrl = 0; 161 s32 status = 0; 162 163 if (hw->phy.type == ixgbe_phy_unknown) 164 status = ixgbe_identify_phy_generic(hw); 165 166 if (status != 0 || hw->phy.type == ixgbe_phy_none) 167 goto out; 168 169 /* Don't reset PHY if it's shut down due to overtemp. */ 170 if (!hw->phy.reset_if_overtemp && 171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 172 goto out; 173 174 /* 175 * Perform soft PHY reset to the PHY_XS. 176 * This will cause a soft reset to the PHY 177 */ 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 179 MDIO_MMD_PHYXS, 180 MDIO_CTRL1_RESET); 181 182 /* 183 * Poll for reset bit to self-clear indicating reset is complete. 184 * Some PHYs could take up to 3 seconds to complete and need about 185 * 1.7 usec delay after the reset is complete. 186 */ 187 for (i = 0; i < 30; i++) { 188 msleep(100); 189 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 190 MDIO_MMD_PHYXS, &ctrl); 191 if (!(ctrl & MDIO_CTRL1_RESET)) { 192 udelay(2); 193 break; 194 } 195 } 196 197 if (ctrl & MDIO_CTRL1_RESET) { 198 status = IXGBE_ERR_RESET_FAILED; 199 hw_dbg(hw, "PHY reset polling failed to complete.\n"); 200 } 201 202 out: 203 return status; 204 } 205 206 /** 207 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 208 * @hw: pointer to hardware structure 209 * @reg_addr: 32 bit address of PHY register to read 210 * @phy_data: Pointer to read data from PHY register 211 **/ 212 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 213 u32 device_type, u16 *phy_data) 214 { 215 u32 command; 216 u32 i; 217 u32 data; 218 s32 status = 0; 219 u16 gssr; 220 221 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 222 gssr = IXGBE_GSSR_PHY1_SM; 223 else 224 gssr = IXGBE_GSSR_PHY0_SM; 225 226 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) 227 status = IXGBE_ERR_SWFW_SYNC; 228 229 if (status == 0) { 230 /* Setup and write the address cycle command */ 231 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 232 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 233 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 234 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 235 236 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 237 238 /* 239 * Check every 10 usec to see if the address cycle completed. 240 * The MDI Command bit will clear when the operation is 241 * complete 242 */ 243 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 244 udelay(10); 245 246 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 247 248 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 249 break; 250 } 251 252 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 253 hw_dbg(hw, "PHY address command did not complete.\n"); 254 status = IXGBE_ERR_PHY; 255 } 256 257 if (status == 0) { 258 /* 259 * Address cycle complete, setup and write the read 260 * command 261 */ 262 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 263 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 264 (hw->phy.mdio.prtad << 265 IXGBE_MSCA_PHY_ADDR_SHIFT) | 266 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 267 268 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 269 270 /* 271 * Check every 10 usec to see if the address cycle 272 * completed. The MDI Command bit will clear when the 273 * operation is complete 274 */ 275 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 276 udelay(10); 277 278 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 279 280 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 281 break; 282 } 283 284 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 285 hw_dbg(hw, "PHY read command didn't complete\n"); 286 status = IXGBE_ERR_PHY; 287 } else { 288 /* 289 * Read operation is complete. Get the data 290 * from MSRWD 291 */ 292 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 293 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 294 *phy_data = (u16)(data); 295 } 296 } 297 298 hw->mac.ops.release_swfw_sync(hw, gssr); 299 } 300 301 return status; 302 } 303 304 /** 305 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 306 * @hw: pointer to hardware structure 307 * @reg_addr: 32 bit PHY register to write 308 * @device_type: 5 bit device type 309 * @phy_data: Data to write to the PHY register 310 **/ 311 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 312 u32 device_type, u16 phy_data) 313 { 314 u32 command; 315 u32 i; 316 s32 status = 0; 317 u16 gssr; 318 319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 320 gssr = IXGBE_GSSR_PHY1_SM; 321 else 322 gssr = IXGBE_GSSR_PHY0_SM; 323 324 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) 325 status = IXGBE_ERR_SWFW_SYNC; 326 327 if (status == 0) { 328 /* Put the data in the MDI single read and write data register*/ 329 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 330 331 /* Setup and write the address cycle command */ 332 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 333 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 334 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | 335 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 336 337 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 338 339 /* 340 * Check every 10 usec to see if the address cycle completed. 341 * The MDI Command bit will clear when the operation is 342 * complete 343 */ 344 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 345 udelay(10); 346 347 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 348 349 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 350 break; 351 } 352 353 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 354 hw_dbg(hw, "PHY address cmd didn't complete\n"); 355 status = IXGBE_ERR_PHY; 356 } 357 358 if (status == 0) { 359 /* 360 * Address cycle complete, setup and write the write 361 * command 362 */ 363 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 364 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 365 (hw->phy.mdio.prtad << 366 IXGBE_MSCA_PHY_ADDR_SHIFT) | 367 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 368 369 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 370 371 /* 372 * Check every 10 usec to see if the address cycle 373 * completed. The MDI Command bit will clear when the 374 * operation is complete 375 */ 376 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 377 udelay(10); 378 379 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 380 381 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 382 break; 383 } 384 385 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 386 hw_dbg(hw, "PHY address cmd didn't complete\n"); 387 status = IXGBE_ERR_PHY; 388 } 389 } 390 391 hw->mac.ops.release_swfw_sync(hw, gssr); 392 } 393 394 return status; 395 } 396 397 /** 398 * ixgbe_setup_phy_link_generic - Set and restart autoneg 399 * @hw: pointer to hardware structure 400 * 401 * Restart autonegotiation and PHY and waits for completion. 402 **/ 403 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 404 { 405 s32 status = 0; 406 u32 time_out; 407 u32 max_time_out = 10; 408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 409 bool autoneg = false; 410 ixgbe_link_speed speed; 411 412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 413 414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 415 /* Set or unset auto-negotiation 10G advertisement */ 416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 417 MDIO_MMD_AN, 418 &autoneg_reg); 419 420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 423 424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 425 MDIO_MMD_AN, 426 autoneg_reg); 427 } 428 429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 430 /* Set or unset auto-negotiation 1G advertisement */ 431 hw->phy.ops.read_reg(hw, 432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 433 MDIO_MMD_AN, 434 &autoneg_reg); 435 436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 439 440 hw->phy.ops.write_reg(hw, 441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 442 MDIO_MMD_AN, 443 autoneg_reg); 444 } 445 446 if (speed & IXGBE_LINK_SPEED_100_FULL) { 447 /* Set or unset auto-negotiation 100M advertisement */ 448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 449 MDIO_MMD_AN, 450 &autoneg_reg); 451 452 autoneg_reg &= ~(ADVERTISE_100FULL | 453 ADVERTISE_100HALF); 454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 455 autoneg_reg |= ADVERTISE_100FULL; 456 457 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 458 MDIO_MMD_AN, 459 autoneg_reg); 460 } 461 462 /* Restart PHY autonegotiation and wait for completion */ 463 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 464 MDIO_MMD_AN, &autoneg_reg); 465 466 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 467 468 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 469 MDIO_MMD_AN, autoneg_reg); 470 471 /* Wait for autonegotiation to finish */ 472 for (time_out = 0; time_out < max_time_out; time_out++) { 473 udelay(10); 474 /* Restart PHY autonegotiation and wait for completion */ 475 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, 476 MDIO_MMD_AN, 477 &autoneg_reg); 478 479 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 480 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { 481 break; 482 } 483 } 484 485 if (time_out == max_time_out) { 486 status = IXGBE_ERR_LINK_SETUP; 487 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out"); 488 } 489 490 return status; 491 } 492 493 /** 494 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 495 * @hw: pointer to hardware structure 496 * @speed: new link speed 497 **/ 498 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 499 ixgbe_link_speed speed, 500 bool autoneg_wait_to_complete) 501 { 502 503 /* 504 * Clear autoneg_advertised and set new values based on input link 505 * speed. 506 */ 507 hw->phy.autoneg_advertised = 0; 508 509 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 510 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 511 512 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 513 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 514 515 if (speed & IXGBE_LINK_SPEED_100_FULL) 516 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 517 518 /* Setup link based on the new speed settings */ 519 hw->phy.ops.setup_link(hw); 520 521 return 0; 522 } 523 524 /** 525 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 526 * @hw: pointer to hardware structure 527 * @speed: pointer to link speed 528 * @autoneg: boolean auto-negotiation value 529 * 530 * Determines the link capabilities by reading the AUTOC register. 531 */ 532 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 533 ixgbe_link_speed *speed, 534 bool *autoneg) 535 { 536 s32 status = IXGBE_ERR_LINK_SETUP; 537 u16 speed_ability; 538 539 *speed = 0; 540 *autoneg = true; 541 542 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, 543 &speed_ability); 544 545 if (status == 0) { 546 if (speed_ability & MDIO_SPEED_10G) 547 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 548 if (speed_ability & MDIO_PMA_SPEED_1000) 549 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 550 if (speed_ability & MDIO_PMA_SPEED_100) 551 *speed |= IXGBE_LINK_SPEED_100_FULL; 552 } 553 554 return status; 555 } 556 557 /** 558 * ixgbe_check_phy_link_tnx - Determine link and speed status 559 * @hw: pointer to hardware structure 560 * 561 * Reads the VS1 register to determine if link is up and the current speed for 562 * the PHY. 563 **/ 564 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 565 bool *link_up) 566 { 567 s32 status = 0; 568 u32 time_out; 569 u32 max_time_out = 10; 570 u16 phy_link = 0; 571 u16 phy_speed = 0; 572 u16 phy_data = 0; 573 574 /* Initialize speed and link to default case */ 575 *link_up = false; 576 *speed = IXGBE_LINK_SPEED_10GB_FULL; 577 578 /* 579 * Check current speed and link status of the PHY register. 580 * This is a vendor specific register and may have to 581 * be changed for other copper PHYs. 582 */ 583 for (time_out = 0; time_out < max_time_out; time_out++) { 584 udelay(10); 585 status = hw->phy.ops.read_reg(hw, 586 MDIO_STAT1, 587 MDIO_MMD_VEND1, 588 &phy_data); 589 phy_link = phy_data & 590 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 591 phy_speed = phy_data & 592 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 593 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 594 *link_up = true; 595 if (phy_speed == 596 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 597 *speed = IXGBE_LINK_SPEED_1GB_FULL; 598 break; 599 } 600 } 601 602 return status; 603 } 604 605 /** 606 * ixgbe_setup_phy_link_tnx - Set and restart autoneg 607 * @hw: pointer to hardware structure 608 * 609 * Restart autonegotiation and PHY and waits for completion. 610 **/ 611 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 612 { 613 s32 status = 0; 614 u32 time_out; 615 u32 max_time_out = 10; 616 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 617 bool autoneg = false; 618 ixgbe_link_speed speed; 619 620 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 621 622 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 623 /* Set or unset auto-negotiation 10G advertisement */ 624 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 625 MDIO_MMD_AN, 626 &autoneg_reg); 627 628 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 629 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 630 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 631 632 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, 633 MDIO_MMD_AN, 634 autoneg_reg); 635 } 636 637 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 638 /* Set or unset auto-negotiation 1G advertisement */ 639 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 640 MDIO_MMD_AN, 641 &autoneg_reg); 642 643 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 644 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 645 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 646 647 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 648 MDIO_MMD_AN, 649 autoneg_reg); 650 } 651 652 if (speed & IXGBE_LINK_SPEED_100_FULL) { 653 /* Set or unset auto-negotiation 100M advertisement */ 654 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, 655 MDIO_MMD_AN, 656 &autoneg_reg); 657 658 autoneg_reg &= ~(ADVERTISE_100FULL | 659 ADVERTISE_100HALF); 660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 661 autoneg_reg |= ADVERTISE_100FULL; 662 663 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, 664 MDIO_MMD_AN, 665 autoneg_reg); 666 } 667 668 /* Restart PHY autonegotiation and wait for completion */ 669 hw->phy.ops.read_reg(hw, MDIO_CTRL1, 670 MDIO_MMD_AN, &autoneg_reg); 671 672 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 673 674 hw->phy.ops.write_reg(hw, MDIO_CTRL1, 675 MDIO_MMD_AN, autoneg_reg); 676 677 /* Wait for autonegotiation to finish */ 678 for (time_out = 0; time_out < max_time_out; time_out++) { 679 udelay(10); 680 /* Restart PHY autonegotiation and wait for completion */ 681 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, 682 MDIO_MMD_AN, 683 &autoneg_reg); 684 685 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 686 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) 687 break; 688 } 689 690 if (time_out == max_time_out) { 691 status = IXGBE_ERR_LINK_SETUP; 692 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out"); 693 } 694 695 return status; 696 } 697 698 /** 699 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 700 * @hw: pointer to hardware structure 701 * @firmware_version: pointer to the PHY Firmware Version 702 **/ 703 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 704 u16 *firmware_version) 705 { 706 s32 status = 0; 707 708 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 709 MDIO_MMD_VEND1, 710 firmware_version); 711 712 return status; 713 } 714 715 /** 716 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 717 * @hw: pointer to hardware structure 718 * @firmware_version: pointer to the PHY Firmware Version 719 **/ 720 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 721 u16 *firmware_version) 722 { 723 s32 status = 0; 724 725 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 726 MDIO_MMD_VEND1, 727 firmware_version); 728 729 return status; 730 } 731 732 /** 733 * ixgbe_reset_phy_nl - Performs a PHY reset 734 * @hw: pointer to hardware structure 735 **/ 736 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 737 { 738 u16 phy_offset, control, eword, edata, block_crc; 739 bool end_data = false; 740 u16 list_offset, data_offset; 741 u16 phy_data = 0; 742 s32 ret_val = 0; 743 u32 i; 744 745 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); 746 747 /* reset the PHY and poll for completion */ 748 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 749 (phy_data | MDIO_CTRL1_RESET)); 750 751 for (i = 0; i < 100; i++) { 752 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 753 &phy_data); 754 if ((phy_data & MDIO_CTRL1_RESET) == 0) 755 break; 756 usleep_range(10000, 20000); 757 } 758 759 if ((phy_data & MDIO_CTRL1_RESET) != 0) { 760 hw_dbg(hw, "PHY reset did not complete.\n"); 761 ret_val = IXGBE_ERR_PHY; 762 goto out; 763 } 764 765 /* Get init offsets */ 766 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 767 &data_offset); 768 if (ret_val != 0) 769 goto out; 770 771 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 772 data_offset++; 773 while (!end_data) { 774 /* 775 * Read control word from PHY init contents offset 776 */ 777 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 778 control = (eword & IXGBE_CONTROL_MASK_NL) >> 779 IXGBE_CONTROL_SHIFT_NL; 780 edata = eword & IXGBE_DATA_MASK_NL; 781 switch (control) { 782 case IXGBE_DELAY_NL: 783 data_offset++; 784 hw_dbg(hw, "DELAY: %d MS\n", edata); 785 usleep_range(edata * 1000, edata * 2000); 786 break; 787 case IXGBE_DATA_NL: 788 hw_dbg(hw, "DATA:\n"); 789 data_offset++; 790 hw->eeprom.ops.read(hw, data_offset++, 791 &phy_offset); 792 for (i = 0; i < edata; i++) { 793 hw->eeprom.ops.read(hw, data_offset, &eword); 794 hw->phy.ops.write_reg(hw, phy_offset, 795 MDIO_MMD_PMAPMD, eword); 796 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, 797 phy_offset); 798 data_offset++; 799 phy_offset++; 800 } 801 break; 802 case IXGBE_CONTROL_NL: 803 data_offset++; 804 hw_dbg(hw, "CONTROL:\n"); 805 if (edata == IXGBE_CONTROL_EOL_NL) { 806 hw_dbg(hw, "EOL\n"); 807 end_data = true; 808 } else if (edata == IXGBE_CONTROL_SOL_NL) { 809 hw_dbg(hw, "SOL\n"); 810 } else { 811 hw_dbg(hw, "Bad control value\n"); 812 ret_val = IXGBE_ERR_PHY; 813 goto out; 814 } 815 break; 816 default: 817 hw_dbg(hw, "Bad control type\n"); 818 ret_val = IXGBE_ERR_PHY; 819 goto out; 820 } 821 } 822 823 out: 824 return ret_val; 825 } 826 827 /** 828 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 829 * @hw: pointer to hardware structure 830 * 831 * Searches for and identifies the SFP module and assigns appropriate PHY type. 832 **/ 833 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 834 { 835 struct ixgbe_adapter *adapter = hw->back; 836 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 837 u32 vendor_oui = 0; 838 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 839 u8 identifier = 0; 840 u8 comp_codes_1g = 0; 841 u8 comp_codes_10g = 0; 842 u8 oui_bytes[3] = {0, 0, 0}; 843 u8 cable_tech = 0; 844 u8 cable_spec = 0; 845 u16 enforce_sfp = 0; 846 847 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 848 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 849 status = IXGBE_ERR_SFP_NOT_PRESENT; 850 goto out; 851 } 852 853 status = hw->phy.ops.read_i2c_eeprom(hw, 854 IXGBE_SFF_IDENTIFIER, 855 &identifier); 856 857 if (status != 0) 858 goto err_read_i2c_eeprom; 859 860 /* LAN ID is needed for sfp_type determination */ 861 hw->mac.ops.set_lan_id(hw); 862 863 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 864 hw->phy.type = ixgbe_phy_sfp_unsupported; 865 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 866 } else { 867 status = hw->phy.ops.read_i2c_eeprom(hw, 868 IXGBE_SFF_1GBE_COMP_CODES, 869 &comp_codes_1g); 870 871 if (status != 0) 872 goto err_read_i2c_eeprom; 873 874 status = hw->phy.ops.read_i2c_eeprom(hw, 875 IXGBE_SFF_10GBE_COMP_CODES, 876 &comp_codes_10g); 877 878 if (status != 0) 879 goto err_read_i2c_eeprom; 880 status = hw->phy.ops.read_i2c_eeprom(hw, 881 IXGBE_SFF_CABLE_TECHNOLOGY, 882 &cable_tech); 883 884 if (status != 0) 885 goto err_read_i2c_eeprom; 886 887 /* ID Module 888 * ========= 889 * 0 SFP_DA_CU 890 * 1 SFP_SR 891 * 2 SFP_LR 892 * 3 SFP_DA_CORE0 - 82599-specific 893 * 4 SFP_DA_CORE1 - 82599-specific 894 * 5 SFP_SR/LR_CORE0 - 82599-specific 895 * 6 SFP_SR/LR_CORE1 - 82599-specific 896 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 897 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 898 * 9 SFP_1g_cu_CORE0 - 82599-specific 899 * 10 SFP_1g_cu_CORE1 - 82599-specific 900 * 11 SFP_1g_sx_CORE0 - 82599-specific 901 * 12 SFP_1g_sx_CORE1 - 82599-specific 902 */ 903 if (hw->mac.type == ixgbe_mac_82598EB) { 904 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 905 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 906 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 907 hw->phy.sfp_type = ixgbe_sfp_type_sr; 908 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 909 hw->phy.sfp_type = ixgbe_sfp_type_lr; 910 else 911 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 912 } else if (hw->mac.type == ixgbe_mac_82599EB) { 913 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 914 if (hw->bus.lan_id == 0) 915 hw->phy.sfp_type = 916 ixgbe_sfp_type_da_cu_core0; 917 else 918 hw->phy.sfp_type = 919 ixgbe_sfp_type_da_cu_core1; 920 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 921 hw->phy.ops.read_i2c_eeprom( 922 hw, IXGBE_SFF_CABLE_SPEC_COMP, 923 &cable_spec); 924 if (cable_spec & 925 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 926 if (hw->bus.lan_id == 0) 927 hw->phy.sfp_type = 928 ixgbe_sfp_type_da_act_lmt_core0; 929 else 930 hw->phy.sfp_type = 931 ixgbe_sfp_type_da_act_lmt_core1; 932 } else { 933 hw->phy.sfp_type = 934 ixgbe_sfp_type_unknown; 935 } 936 } else if (comp_codes_10g & 937 (IXGBE_SFF_10GBASESR_CAPABLE | 938 IXGBE_SFF_10GBASELR_CAPABLE)) { 939 if (hw->bus.lan_id == 0) 940 hw->phy.sfp_type = 941 ixgbe_sfp_type_srlr_core0; 942 else 943 hw->phy.sfp_type = 944 ixgbe_sfp_type_srlr_core1; 945 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 946 if (hw->bus.lan_id == 0) 947 hw->phy.sfp_type = 948 ixgbe_sfp_type_1g_cu_core0; 949 else 950 hw->phy.sfp_type = 951 ixgbe_sfp_type_1g_cu_core1; 952 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 953 if (hw->bus.lan_id == 0) 954 hw->phy.sfp_type = 955 ixgbe_sfp_type_1g_sx_core0; 956 else 957 hw->phy.sfp_type = 958 ixgbe_sfp_type_1g_sx_core1; 959 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 960 if (hw->bus.lan_id == 0) 961 hw->phy.sfp_type = 962 ixgbe_sfp_type_1g_lx_core0; 963 else 964 hw->phy.sfp_type = 965 ixgbe_sfp_type_1g_lx_core1; 966 } else { 967 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 968 } 969 } 970 971 if (hw->phy.sfp_type != stored_sfp_type) 972 hw->phy.sfp_setup_needed = true; 973 974 /* Determine if the SFP+ PHY is dual speed or not. */ 975 hw->phy.multispeed_fiber = false; 976 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 977 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 978 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 979 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 980 hw->phy.multispeed_fiber = true; 981 982 /* Determine PHY vendor */ 983 if (hw->phy.type != ixgbe_phy_nl) { 984 hw->phy.id = identifier; 985 status = hw->phy.ops.read_i2c_eeprom(hw, 986 IXGBE_SFF_VENDOR_OUI_BYTE0, 987 &oui_bytes[0]); 988 989 if (status != 0) 990 goto err_read_i2c_eeprom; 991 992 status = hw->phy.ops.read_i2c_eeprom(hw, 993 IXGBE_SFF_VENDOR_OUI_BYTE1, 994 &oui_bytes[1]); 995 996 if (status != 0) 997 goto err_read_i2c_eeprom; 998 999 status = hw->phy.ops.read_i2c_eeprom(hw, 1000 IXGBE_SFF_VENDOR_OUI_BYTE2, 1001 &oui_bytes[2]); 1002 1003 if (status != 0) 1004 goto err_read_i2c_eeprom; 1005 1006 vendor_oui = 1007 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1008 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1009 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1010 1011 switch (vendor_oui) { 1012 case IXGBE_SFF_VENDOR_OUI_TYCO: 1013 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1014 hw->phy.type = 1015 ixgbe_phy_sfp_passive_tyco; 1016 break; 1017 case IXGBE_SFF_VENDOR_OUI_FTL: 1018 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1019 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1020 else 1021 hw->phy.type = ixgbe_phy_sfp_ftl; 1022 break; 1023 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1024 hw->phy.type = ixgbe_phy_sfp_avago; 1025 break; 1026 case IXGBE_SFF_VENDOR_OUI_INTEL: 1027 hw->phy.type = ixgbe_phy_sfp_intel; 1028 break; 1029 default: 1030 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1031 hw->phy.type = 1032 ixgbe_phy_sfp_passive_unknown; 1033 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1034 hw->phy.type = 1035 ixgbe_phy_sfp_active_unknown; 1036 else 1037 hw->phy.type = ixgbe_phy_sfp_unknown; 1038 break; 1039 } 1040 } 1041 1042 /* Allow any DA cable vendor */ 1043 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1044 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1045 status = 0; 1046 goto out; 1047 } 1048 1049 /* Verify supported 1G SFP modules */ 1050 if (comp_codes_10g == 0 && 1051 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1052 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1053 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1054 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1055 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1056 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1057 hw->phy.type = ixgbe_phy_sfp_unsupported; 1058 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1059 goto out; 1060 } 1061 1062 /* Anything else 82598-based is supported */ 1063 if (hw->mac.type == ixgbe_mac_82598EB) { 1064 status = 0; 1065 goto out; 1066 } 1067 1068 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1069 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1070 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1071 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1072 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1073 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1074 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1075 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1076 /* Make sure we're a supported PHY type */ 1077 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1078 status = 0; 1079 } else { 1080 if (hw->allow_unsupported_sfp) { 1081 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules."); 1082 status = 0; 1083 } else { 1084 hw_dbg(hw, 1085 "SFP+ module not supported\n"); 1086 hw->phy.type = 1087 ixgbe_phy_sfp_unsupported; 1088 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1089 } 1090 } 1091 } else { 1092 status = 0; 1093 } 1094 } 1095 1096 out: 1097 return status; 1098 1099 err_read_i2c_eeprom: 1100 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1101 if (hw->phy.type != ixgbe_phy_nl) { 1102 hw->phy.id = 0; 1103 hw->phy.type = ixgbe_phy_unknown; 1104 } 1105 return IXGBE_ERR_SFP_NOT_PRESENT; 1106 } 1107 1108 /** 1109 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1110 * @hw: pointer to hardware structure 1111 * @list_offset: offset to the SFP ID list 1112 * @data_offset: offset to the SFP data block 1113 * 1114 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1115 * so it returns the offsets to the phy init sequence block. 1116 **/ 1117 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1118 u16 *list_offset, 1119 u16 *data_offset) 1120 { 1121 u16 sfp_id; 1122 u16 sfp_type = hw->phy.sfp_type; 1123 1124 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1125 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1126 1127 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1128 return IXGBE_ERR_SFP_NOT_PRESENT; 1129 1130 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1131 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1132 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1133 1134 /* 1135 * Limiting active cables and 1G Phys must be initialized as 1136 * SR modules 1137 */ 1138 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1139 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1140 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1141 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1142 sfp_type = ixgbe_sfp_type_srlr_core0; 1143 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1144 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1145 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1146 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1147 sfp_type = ixgbe_sfp_type_srlr_core1; 1148 1149 /* Read offset to PHY init contents */ 1150 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 1151 1152 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1153 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1154 1155 /* Shift offset to first ID word */ 1156 (*list_offset)++; 1157 1158 /* 1159 * Find the matching SFP ID in the EEPROM 1160 * and program the init sequence 1161 */ 1162 hw->eeprom.ops.read(hw, *list_offset, &sfp_id); 1163 1164 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1165 if (sfp_id == sfp_type) { 1166 (*list_offset)++; 1167 hw->eeprom.ops.read(hw, *list_offset, data_offset); 1168 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1169 hw_dbg(hw, "SFP+ module not supported\n"); 1170 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1171 } else { 1172 break; 1173 } 1174 } else { 1175 (*list_offset) += 2; 1176 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1177 return IXGBE_ERR_PHY; 1178 } 1179 } 1180 1181 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1182 hw_dbg(hw, "No matching SFP+ module found\n"); 1183 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1184 } 1185 1186 return 0; 1187 } 1188 1189 /** 1190 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1191 * @hw: pointer to hardware structure 1192 * @byte_offset: EEPROM byte offset to read 1193 * @eeprom_data: value read 1194 * 1195 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1196 **/ 1197 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1198 u8 *eeprom_data) 1199 { 1200 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1201 IXGBE_I2C_EEPROM_DEV_ADDR, 1202 eeprom_data); 1203 } 1204 1205 /** 1206 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1207 * @hw: pointer to hardware structure 1208 * @byte_offset: byte offset at address 0xA2 1209 * @eeprom_data: value read 1210 * 1211 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1212 **/ 1213 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1214 u8 *sff8472_data) 1215 { 1216 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1217 IXGBE_I2C_EEPROM_DEV_ADDR2, 1218 sff8472_data); 1219 } 1220 1221 /** 1222 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1223 * @hw: pointer to hardware structure 1224 * @byte_offset: EEPROM byte offset to write 1225 * @eeprom_data: value to write 1226 * 1227 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1228 **/ 1229 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1230 u8 eeprom_data) 1231 { 1232 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1233 IXGBE_I2C_EEPROM_DEV_ADDR, 1234 eeprom_data); 1235 } 1236 1237 /** 1238 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1239 * @hw: pointer to hardware structure 1240 * @byte_offset: byte offset to read 1241 * @data: value read 1242 * 1243 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1244 * a specified device address. 1245 **/ 1246 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1247 u8 dev_addr, u8 *data) 1248 { 1249 s32 status = 0; 1250 u32 max_retry = 10; 1251 u32 retry = 0; 1252 u16 swfw_mask = 0; 1253 bool nack = true; 1254 *data = 0; 1255 1256 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1257 swfw_mask = IXGBE_GSSR_PHY1_SM; 1258 else 1259 swfw_mask = IXGBE_GSSR_PHY0_SM; 1260 1261 do { 1262 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { 1263 status = IXGBE_ERR_SWFW_SYNC; 1264 goto read_byte_out; 1265 } 1266 1267 ixgbe_i2c_start(hw); 1268 1269 /* Device Address and write indication */ 1270 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1271 if (status != 0) 1272 goto fail; 1273 1274 status = ixgbe_get_i2c_ack(hw); 1275 if (status != 0) 1276 goto fail; 1277 1278 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1279 if (status != 0) 1280 goto fail; 1281 1282 status = ixgbe_get_i2c_ack(hw); 1283 if (status != 0) 1284 goto fail; 1285 1286 ixgbe_i2c_start(hw); 1287 1288 /* Device Address and read indication */ 1289 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1290 if (status != 0) 1291 goto fail; 1292 1293 status = ixgbe_get_i2c_ack(hw); 1294 if (status != 0) 1295 goto fail; 1296 1297 status = ixgbe_clock_in_i2c_byte(hw, data); 1298 if (status != 0) 1299 goto fail; 1300 1301 status = ixgbe_clock_out_i2c_bit(hw, nack); 1302 if (status != 0) 1303 goto fail; 1304 1305 ixgbe_i2c_stop(hw); 1306 break; 1307 1308 fail: 1309 ixgbe_i2c_bus_clear(hw); 1310 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1311 msleep(100); 1312 retry++; 1313 if (retry < max_retry) 1314 hw_dbg(hw, "I2C byte read error - Retrying.\n"); 1315 else 1316 hw_dbg(hw, "I2C byte read error.\n"); 1317 1318 } while (retry < max_retry); 1319 1320 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1321 1322 read_byte_out: 1323 return status; 1324 } 1325 1326 /** 1327 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1328 * @hw: pointer to hardware structure 1329 * @byte_offset: byte offset to write 1330 * @data: value to write 1331 * 1332 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1333 * a specified device address. 1334 **/ 1335 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1336 u8 dev_addr, u8 data) 1337 { 1338 s32 status = 0; 1339 u32 max_retry = 1; 1340 u32 retry = 0; 1341 u16 swfw_mask = 0; 1342 1343 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1344 swfw_mask = IXGBE_GSSR_PHY1_SM; 1345 else 1346 swfw_mask = IXGBE_GSSR_PHY0_SM; 1347 1348 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { 1349 status = IXGBE_ERR_SWFW_SYNC; 1350 goto write_byte_out; 1351 } 1352 1353 do { 1354 ixgbe_i2c_start(hw); 1355 1356 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1357 if (status != 0) 1358 goto fail; 1359 1360 status = ixgbe_get_i2c_ack(hw); 1361 if (status != 0) 1362 goto fail; 1363 1364 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1365 if (status != 0) 1366 goto fail; 1367 1368 status = ixgbe_get_i2c_ack(hw); 1369 if (status != 0) 1370 goto fail; 1371 1372 status = ixgbe_clock_out_i2c_byte(hw, data); 1373 if (status != 0) 1374 goto fail; 1375 1376 status = ixgbe_get_i2c_ack(hw); 1377 if (status != 0) 1378 goto fail; 1379 1380 ixgbe_i2c_stop(hw); 1381 break; 1382 1383 fail: 1384 ixgbe_i2c_bus_clear(hw); 1385 retry++; 1386 if (retry < max_retry) 1387 hw_dbg(hw, "I2C byte write error - Retrying.\n"); 1388 else 1389 hw_dbg(hw, "I2C byte write error.\n"); 1390 } while (retry < max_retry); 1391 1392 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1393 1394 write_byte_out: 1395 return status; 1396 } 1397 1398 /** 1399 * ixgbe_i2c_start - Sets I2C start condition 1400 * @hw: pointer to hardware structure 1401 * 1402 * Sets I2C start condition (High -> Low on SDA while SCL is High) 1403 **/ 1404 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 1405 { 1406 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1407 1408 /* Start condition must begin with data and clock high */ 1409 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1410 ixgbe_raise_i2c_clk(hw, &i2cctl); 1411 1412 /* Setup time for start condition (4.7us) */ 1413 udelay(IXGBE_I2C_T_SU_STA); 1414 1415 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1416 1417 /* Hold time for start condition (4us) */ 1418 udelay(IXGBE_I2C_T_HD_STA); 1419 1420 ixgbe_lower_i2c_clk(hw, &i2cctl); 1421 1422 /* Minimum low period of clock is 4.7 us */ 1423 udelay(IXGBE_I2C_T_LOW); 1424 1425 } 1426 1427 /** 1428 * ixgbe_i2c_stop - Sets I2C stop condition 1429 * @hw: pointer to hardware structure 1430 * 1431 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1432 **/ 1433 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1434 { 1435 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1436 1437 /* Stop condition must begin with data low and clock high */ 1438 ixgbe_set_i2c_data(hw, &i2cctl, 0); 1439 ixgbe_raise_i2c_clk(hw, &i2cctl); 1440 1441 /* Setup time for stop condition (4us) */ 1442 udelay(IXGBE_I2C_T_SU_STO); 1443 1444 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1445 1446 /* bus free time between stop and start (4.7us)*/ 1447 udelay(IXGBE_I2C_T_BUF); 1448 } 1449 1450 /** 1451 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1452 * @hw: pointer to hardware structure 1453 * @data: data byte to clock in 1454 * 1455 * Clocks in one byte data via I2C data/clock 1456 **/ 1457 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1458 { 1459 s32 i; 1460 bool bit = false; 1461 1462 for (i = 7; i >= 0; i--) { 1463 ixgbe_clock_in_i2c_bit(hw, &bit); 1464 *data |= bit << i; 1465 } 1466 1467 return 0; 1468 } 1469 1470 /** 1471 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1472 * @hw: pointer to hardware structure 1473 * @data: data byte clocked out 1474 * 1475 * Clocks out one byte data via I2C data/clock 1476 **/ 1477 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1478 { 1479 s32 status = 0; 1480 s32 i; 1481 u32 i2cctl; 1482 bool bit = false; 1483 1484 for (i = 7; i >= 0; i--) { 1485 bit = (data >> i) & 0x1; 1486 status = ixgbe_clock_out_i2c_bit(hw, bit); 1487 1488 if (status != 0) 1489 break; 1490 } 1491 1492 /* Release SDA line (set high) */ 1493 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1494 i2cctl |= IXGBE_I2C_DATA_OUT; 1495 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1496 IXGBE_WRITE_FLUSH(hw); 1497 1498 return status; 1499 } 1500 1501 /** 1502 * ixgbe_get_i2c_ack - Polls for I2C ACK 1503 * @hw: pointer to hardware structure 1504 * 1505 * Clocks in/out one bit via I2C data/clock 1506 **/ 1507 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1508 { 1509 s32 status = 0; 1510 u32 i = 0; 1511 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1512 u32 timeout = 10; 1513 bool ack = true; 1514 1515 ixgbe_raise_i2c_clk(hw, &i2cctl); 1516 1517 1518 /* Minimum high period of clock is 4us */ 1519 udelay(IXGBE_I2C_T_HIGH); 1520 1521 /* Poll for ACK. Note that ACK in I2C spec is 1522 * transition from 1 to 0 */ 1523 for (i = 0; i < timeout; i++) { 1524 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1525 ack = ixgbe_get_i2c_data(&i2cctl); 1526 1527 udelay(1); 1528 if (ack == 0) 1529 break; 1530 } 1531 1532 if (ack == 1) { 1533 hw_dbg(hw, "I2C ack was not received.\n"); 1534 status = IXGBE_ERR_I2C; 1535 } 1536 1537 ixgbe_lower_i2c_clk(hw, &i2cctl); 1538 1539 /* Minimum low period of clock is 4.7 us */ 1540 udelay(IXGBE_I2C_T_LOW); 1541 1542 return status; 1543 } 1544 1545 /** 1546 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1547 * @hw: pointer to hardware structure 1548 * @data: read data value 1549 * 1550 * Clocks in one bit via I2C data/clock 1551 **/ 1552 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1553 { 1554 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1555 1556 ixgbe_raise_i2c_clk(hw, &i2cctl); 1557 1558 /* Minimum high period of clock is 4us */ 1559 udelay(IXGBE_I2C_T_HIGH); 1560 1561 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1562 *data = ixgbe_get_i2c_data(&i2cctl); 1563 1564 ixgbe_lower_i2c_clk(hw, &i2cctl); 1565 1566 /* Minimum low period of clock is 4.7 us */ 1567 udelay(IXGBE_I2C_T_LOW); 1568 1569 return 0; 1570 } 1571 1572 /** 1573 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1574 * @hw: pointer to hardware structure 1575 * @data: data value to write 1576 * 1577 * Clocks out one bit via I2C data/clock 1578 **/ 1579 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1580 { 1581 s32 status; 1582 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1583 1584 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1585 if (status == 0) { 1586 ixgbe_raise_i2c_clk(hw, &i2cctl); 1587 1588 /* Minimum high period of clock is 4us */ 1589 udelay(IXGBE_I2C_T_HIGH); 1590 1591 ixgbe_lower_i2c_clk(hw, &i2cctl); 1592 1593 /* Minimum low period of clock is 4.7 us. 1594 * This also takes care of the data hold time. 1595 */ 1596 udelay(IXGBE_I2C_T_LOW); 1597 } else { 1598 status = IXGBE_ERR_I2C; 1599 hw_dbg(hw, "I2C data was not set to %X\n", data); 1600 } 1601 1602 return status; 1603 } 1604 /** 1605 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1606 * @hw: pointer to hardware structure 1607 * @i2cctl: Current value of I2CCTL register 1608 * 1609 * Raises the I2C clock line '0'->'1' 1610 **/ 1611 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1612 { 1613 u32 i = 0; 1614 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1615 u32 i2cctl_r = 0; 1616 1617 for (i = 0; i < timeout; i++) { 1618 *i2cctl |= IXGBE_I2C_CLK_OUT; 1619 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1620 IXGBE_WRITE_FLUSH(hw); 1621 /* SCL rise time (1000ns) */ 1622 udelay(IXGBE_I2C_T_RISE); 1623 1624 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1625 if (i2cctl_r & IXGBE_I2C_CLK_IN) 1626 break; 1627 } 1628 } 1629 1630 /** 1631 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1632 * @hw: pointer to hardware structure 1633 * @i2cctl: Current value of I2CCTL register 1634 * 1635 * Lowers the I2C clock line '1'->'0' 1636 **/ 1637 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1638 { 1639 1640 *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1641 1642 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1643 IXGBE_WRITE_FLUSH(hw); 1644 1645 /* SCL fall time (300ns) */ 1646 udelay(IXGBE_I2C_T_FALL); 1647 } 1648 1649 /** 1650 * ixgbe_set_i2c_data - Sets the I2C data bit 1651 * @hw: pointer to hardware structure 1652 * @i2cctl: Current value of I2CCTL register 1653 * @data: I2C data value (0 or 1) to set 1654 * 1655 * Sets the I2C data bit 1656 **/ 1657 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1658 { 1659 s32 status = 0; 1660 1661 if (data) 1662 *i2cctl |= IXGBE_I2C_DATA_OUT; 1663 else 1664 *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1665 1666 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1667 IXGBE_WRITE_FLUSH(hw); 1668 1669 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1670 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1671 1672 /* Verify data was set correctly */ 1673 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1674 if (data != ixgbe_get_i2c_data(i2cctl)) { 1675 status = IXGBE_ERR_I2C; 1676 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); 1677 } 1678 1679 return status; 1680 } 1681 1682 /** 1683 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1684 * @hw: pointer to hardware structure 1685 * @i2cctl: Current value of I2CCTL register 1686 * 1687 * Returns the I2C data bit value 1688 **/ 1689 static bool ixgbe_get_i2c_data(u32 *i2cctl) 1690 { 1691 bool data; 1692 1693 if (*i2cctl & IXGBE_I2C_DATA_IN) 1694 data = true; 1695 else 1696 data = false; 1697 1698 return data; 1699 } 1700 1701 /** 1702 * ixgbe_i2c_bus_clear - Clears the I2C bus 1703 * @hw: pointer to hardware structure 1704 * 1705 * Clears the I2C bus by sending nine clock pulses. 1706 * Used when data line is stuck low. 1707 **/ 1708 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1709 { 1710 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1711 u32 i; 1712 1713 ixgbe_i2c_start(hw); 1714 1715 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1716 1717 for (i = 0; i < 9; i++) { 1718 ixgbe_raise_i2c_clk(hw, &i2cctl); 1719 1720 /* Min high period of clock is 4us */ 1721 udelay(IXGBE_I2C_T_HIGH); 1722 1723 ixgbe_lower_i2c_clk(hw, &i2cctl); 1724 1725 /* Min low period of clock is 4.7us*/ 1726 udelay(IXGBE_I2C_T_LOW); 1727 } 1728 1729 ixgbe_i2c_start(hw); 1730 1731 /* Put the i2c bus back to default state */ 1732 ixgbe_i2c_stop(hw); 1733 } 1734 1735 /** 1736 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1737 * @hw: pointer to hardware structure 1738 * 1739 * Checks if the LASI temp alarm status was triggered due to overtemp 1740 **/ 1741 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1742 { 1743 s32 status = 0; 1744 u16 phy_data = 0; 1745 1746 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1747 goto out; 1748 1749 /* Check that the LASI temp alarm status was triggered */ 1750 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1751 MDIO_MMD_PMAPMD, &phy_data); 1752 1753 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1754 goto out; 1755 1756 status = IXGBE_ERR_OVERTEMP; 1757 out: 1758 return status; 1759 } 1760