1 /*******************************************************************************
2 
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2014 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/ethtool.h>
46 #include <linux/if.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_macvlan.h>
49 #include <linux/if_bridge.h>
50 #include <linux/prefetch.h>
51 #include <scsi/fc/fc_fcoe.h>
52 
53 #include "ixgbe.h"
54 #include "ixgbe_common.h"
55 #include "ixgbe_dcb_82599.h"
56 #include "ixgbe_sriov.h"
57 
58 char ixgbe_driver_name[] = "ixgbe";
59 static const char ixgbe_driver_string[] =
60 			      "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #ifdef IXGBE_FCOE
62 char ixgbe_default_device_descr[] =
63 			      "Intel(R) 10 Gigabit Network Connection";
64 #else
65 static char ixgbe_default_device_descr[] =
66 			      "Intel(R) 10 Gigabit Network Connection";
67 #endif
68 #define DRV_VERSION "3.19.1-k"
69 const char ixgbe_driver_version[] = DRV_VERSION;
70 static const char ixgbe_copyright[] =
71 				"Copyright (c) 1999-2014 Intel Corporation.";
72 
73 static const struct ixgbe_info *ixgbe_info_tbl[] = {
74 	[board_82598] = &ixgbe_82598_info,
75 	[board_82599] = &ixgbe_82599_info,
76 	[board_X540] = &ixgbe_X540_info,
77 };
78 
79 /* ixgbe_pci_tbl - PCI Device ID Table
80  *
81  * Wildcard entries (PCI_ANY_ID) should come last
82  * Last entry must be all 0s
83  *
84  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85  *   Class, Class Mask, private data (not used) }
86  */
87 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
88 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
114 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
115 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
118 	/* required last entry */
119 	{0, }
120 };
121 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122 
123 #ifdef CONFIG_IXGBE_DCA
124 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 			    void *p);
126 static struct notifier_block dca_notifier = {
127 	.notifier_call = ixgbe_notify_dca,
128 	.next          = NULL,
129 	.priority      = 0
130 };
131 #endif
132 
133 #ifdef CONFIG_PCI_IOV
134 static unsigned int max_vfs;
135 module_param(max_vfs, uint, 0);
136 MODULE_PARM_DESC(max_vfs,
137 		 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
138 #endif /* CONFIG_PCI_IOV */
139 
140 static unsigned int allow_unsupported_sfp;
141 module_param(allow_unsupported_sfp, uint, 0);
142 MODULE_PARM_DESC(allow_unsupported_sfp,
143 		 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144 
145 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146 static int debug = -1;
147 module_param(debug, int, 0);
148 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149 
150 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152 MODULE_LICENSE("GPL");
153 MODULE_VERSION(DRV_VERSION);
154 
155 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156 
157 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 					  u32 reg, u16 *value)
159 {
160 	struct pci_dev *parent_dev;
161 	struct pci_bus *parent_bus;
162 
163 	parent_bus = adapter->pdev->bus->parent;
164 	if (!parent_bus)
165 		return -1;
166 
167 	parent_dev = parent_bus->self;
168 	if (!parent_dev)
169 		return -1;
170 
171 	if (!pci_is_pcie(parent_dev))
172 		return -1;
173 
174 	pcie_capability_read_word(parent_dev, reg, value);
175 	if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 	    ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 		return -1;
178 	return 0;
179 }
180 
181 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182 {
183 	struct ixgbe_hw *hw = &adapter->hw;
184 	u16 link_status = 0;
185 	int err;
186 
187 	hw->bus.type = ixgbe_bus_type_pci_express;
188 
189 	/* Get the negotiated link width and speed from PCI config space of the
190 	 * parent, as this device is behind a switch
191 	 */
192 	err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193 
194 	/* assume caller will handle error case */
195 	if (err)
196 		return err;
197 
198 	hw->bus.width = ixgbe_convert_bus_width(link_status);
199 	hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200 
201 	return 0;
202 }
203 
204 /**
205  * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206  * @hw: hw specific details
207  *
208  * This function is used by probe to determine whether a device's PCI-Express
209  * bandwidth details should be gathered from the parent bus instead of from the
210  * device. Used to ensure that various locations all have the correct device ID
211  * checks.
212  */
213 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214 {
215 	switch (hw->device_id) {
216 	case IXGBE_DEV_ID_82599_SFP_SF_QP:
217 	case IXGBE_DEV_ID_82599_QSFP_SF_QP:
218 		return true;
219 	default:
220 		return false;
221 	}
222 }
223 
224 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 				     int expected_gts)
226 {
227 	int max_gts = 0;
228 	enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 	enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 	struct pci_dev *pdev;
231 
232 	/* determine whether to use the the parent device
233 	 */
234 	if (ixgbe_pcie_from_parent(&adapter->hw))
235 		pdev = adapter->pdev->bus->parent->self;
236 	else
237 		pdev = adapter->pdev;
238 
239 	if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 	    speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 		e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 		return;
243 	}
244 
245 	switch (speed) {
246 	case PCIE_SPEED_2_5GT:
247 		/* 8b/10b encoding reduces max throughput by 20% */
248 		max_gts = 2 * width;
249 		break;
250 	case PCIE_SPEED_5_0GT:
251 		/* 8b/10b encoding reduces max throughput by 20% */
252 		max_gts = 4 * width;
253 		break;
254 	case PCIE_SPEED_8_0GT:
255 		/* 128b/130b encoding reduces throughput by less than 2% */
256 		max_gts = 8 * width;
257 		break;
258 	default:
259 		e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 		return;
261 	}
262 
263 	e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 		   max_gts);
265 	e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 		   (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 		    speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 		    speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 		    "Unknown"),
270 		   width,
271 		   (speed == PCIE_SPEED_2_5GT ? "20%" :
272 		    speed == PCIE_SPEED_5_0GT ? "20%" :
273 		    speed == PCIE_SPEED_8_0GT ? "<2%" :
274 		    "Unknown"));
275 
276 	if (max_gts < expected_gts) {
277 		e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 		e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 			expected_gts);
280 		e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 	}
282 }
283 
284 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285 {
286 	if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
287 	    !test_bit(__IXGBE_REMOVING, &adapter->state) &&
288 	    !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 		schedule_work(&adapter->service_task);
290 }
291 
292 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293 {
294 	struct ixgbe_adapter *adapter = hw->back;
295 
296 	if (!hw->hw_addr)
297 		return;
298 	hw->hw_addr = NULL;
299 	e_dev_err("Adapter removed\n");
300 	if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 		ixgbe_service_event_schedule(adapter);
302 }
303 
304 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
305 {
306 	u32 value;
307 
308 	/* The following check not only optimizes a bit by not
309 	 * performing a read on the status register when the
310 	 * register just read was a status register read that
311 	 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 	 * potential recursion.
313 	 */
314 	if (reg == IXGBE_STATUS) {
315 		ixgbe_remove_adapter(hw);
316 		return;
317 	}
318 	value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 	if (value == IXGBE_FAILED_READ_REG)
320 		ixgbe_remove_adapter(hw);
321 }
322 
323 /**
324  * ixgbe_read_reg - Read from device register
325  * @hw: hw specific details
326  * @reg: offset of register to read
327  *
328  * Returns : value read or IXGBE_FAILED_READ_REG if removed
329  *
330  * This function is used to read device registers. It checks for device
331  * removal by confirming any read that returns all ones by checking the
332  * status register value for all ones. This function avoids reading from
333  * the hardware if a removal was previously detected in which case it
334  * returns IXGBE_FAILED_READ_REG (all ones).
335  */
336 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337 {
338 	u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 	u32 value;
340 
341 	if (ixgbe_removed(reg_addr))
342 		return IXGBE_FAILED_READ_REG;
343 	value = readl(reg_addr + reg);
344 	if (unlikely(value == IXGBE_FAILED_READ_REG))
345 		ixgbe_check_remove(hw, reg);
346 	return value;
347 }
348 
349 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350 {
351 	u16 value;
352 
353 	pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 	if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 		ixgbe_remove_adapter(hw);
356 		return true;
357 	}
358 	return false;
359 }
360 
361 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362 {
363 	struct ixgbe_adapter *adapter = hw->back;
364 	u16 value;
365 
366 	if (ixgbe_removed(hw->hw_addr))
367 		return IXGBE_FAILED_READ_CFG_WORD;
368 	pci_read_config_word(adapter->pdev, reg, &value);
369 	if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 	    ixgbe_check_cfg_remove(hw, adapter->pdev))
371 		return IXGBE_FAILED_READ_CFG_WORD;
372 	return value;
373 }
374 
375 #ifdef CONFIG_PCI_IOV
376 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377 {
378 	struct ixgbe_adapter *adapter = hw->back;
379 	u32 value;
380 
381 	if (ixgbe_removed(hw->hw_addr))
382 		return IXGBE_FAILED_READ_CFG_DWORD;
383 	pci_read_config_dword(adapter->pdev, reg, &value);
384 	if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 	    ixgbe_check_cfg_remove(hw, adapter->pdev))
386 		return IXGBE_FAILED_READ_CFG_DWORD;
387 	return value;
388 }
389 #endif /* CONFIG_PCI_IOV */
390 
391 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392 {
393 	struct ixgbe_adapter *adapter = hw->back;
394 
395 	if (ixgbe_removed(hw->hw_addr))
396 		return;
397 	pci_write_config_word(adapter->pdev, reg, value);
398 }
399 
400 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401 {
402 	BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403 
404 	/* flush memory to make sure state is correct before next watchdog */
405 	smp_mb__before_atomic();
406 	clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407 }
408 
409 struct ixgbe_reg_info {
410 	u32 ofs;
411 	char *name;
412 };
413 
414 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415 
416 	/* General Registers */
417 	{IXGBE_CTRL, "CTRL"},
418 	{IXGBE_STATUS, "STATUS"},
419 	{IXGBE_CTRL_EXT, "CTRL_EXT"},
420 
421 	/* Interrupt Registers */
422 	{IXGBE_EICR, "EICR"},
423 
424 	/* RX Registers */
425 	{IXGBE_SRRCTL(0), "SRRCTL"},
426 	{IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 	{IXGBE_RDLEN(0), "RDLEN"},
428 	{IXGBE_RDH(0), "RDH"},
429 	{IXGBE_RDT(0), "RDT"},
430 	{IXGBE_RXDCTL(0), "RXDCTL"},
431 	{IXGBE_RDBAL(0), "RDBAL"},
432 	{IXGBE_RDBAH(0), "RDBAH"},
433 
434 	/* TX Registers */
435 	{IXGBE_TDBAL(0), "TDBAL"},
436 	{IXGBE_TDBAH(0), "TDBAH"},
437 	{IXGBE_TDLEN(0), "TDLEN"},
438 	{IXGBE_TDH(0), "TDH"},
439 	{IXGBE_TDT(0), "TDT"},
440 	{IXGBE_TXDCTL(0), "TXDCTL"},
441 
442 	/* List Terminator */
443 	{}
444 };
445 
446 
447 /*
448  * ixgbe_regdump - register printout routine
449  */
450 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451 {
452 	int i = 0, j = 0;
453 	char rname[16];
454 	u32 regs[64];
455 
456 	switch (reginfo->ofs) {
457 	case IXGBE_SRRCTL(0):
458 		for (i = 0; i < 64; i++)
459 			regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 		break;
461 	case IXGBE_DCA_RXCTRL(0):
462 		for (i = 0; i < 64; i++)
463 			regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 		break;
465 	case IXGBE_RDLEN(0):
466 		for (i = 0; i < 64; i++)
467 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 		break;
469 	case IXGBE_RDH(0):
470 		for (i = 0; i < 64; i++)
471 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 		break;
473 	case IXGBE_RDT(0):
474 		for (i = 0; i < 64; i++)
475 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 		break;
477 	case IXGBE_RXDCTL(0):
478 		for (i = 0; i < 64; i++)
479 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 		break;
481 	case IXGBE_RDBAL(0):
482 		for (i = 0; i < 64; i++)
483 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 		break;
485 	case IXGBE_RDBAH(0):
486 		for (i = 0; i < 64; i++)
487 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 		break;
489 	case IXGBE_TDBAL(0):
490 		for (i = 0; i < 64; i++)
491 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 		break;
493 	case IXGBE_TDBAH(0):
494 		for (i = 0; i < 64; i++)
495 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 		break;
497 	case IXGBE_TDLEN(0):
498 		for (i = 0; i < 64; i++)
499 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 		break;
501 	case IXGBE_TDH(0):
502 		for (i = 0; i < 64; i++)
503 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 		break;
505 	case IXGBE_TDT(0):
506 		for (i = 0; i < 64; i++)
507 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 		break;
509 	case IXGBE_TXDCTL(0):
510 		for (i = 0; i < 64; i++)
511 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 		break;
513 	default:
514 		pr_info("%-15s %08x\n", reginfo->name,
515 			IXGBE_READ_REG(hw, reginfo->ofs));
516 		return;
517 	}
518 
519 	for (i = 0; i < 8; i++) {
520 		snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
521 		pr_err("%-15s", rname);
522 		for (j = 0; j < 8; j++)
523 			pr_cont(" %08x", regs[i*8+j]);
524 		pr_cont("\n");
525 	}
526 
527 }
528 
529 /*
530  * ixgbe_dump - Print registers, tx-rings and rx-rings
531  */
532 static void ixgbe_dump(struct ixgbe_adapter *adapter)
533 {
534 	struct net_device *netdev = adapter->netdev;
535 	struct ixgbe_hw *hw = &adapter->hw;
536 	struct ixgbe_reg_info *reginfo;
537 	int n = 0;
538 	struct ixgbe_ring *tx_ring;
539 	struct ixgbe_tx_buffer *tx_buffer;
540 	union ixgbe_adv_tx_desc *tx_desc;
541 	struct my_u0 { u64 a; u64 b; } *u0;
542 	struct ixgbe_ring *rx_ring;
543 	union ixgbe_adv_rx_desc *rx_desc;
544 	struct ixgbe_rx_buffer *rx_buffer_info;
545 	u32 staterr;
546 	int i = 0;
547 
548 	if (!netif_msg_hw(adapter))
549 		return;
550 
551 	/* Print netdevice Info */
552 	if (netdev) {
553 		dev_info(&adapter->pdev->dev, "Net device Info\n");
554 		pr_info("Device Name     state            "
555 			"trans_start      last_rx\n");
556 		pr_info("%-15s %016lX %016lX %016lX\n",
557 			netdev->name,
558 			netdev->state,
559 			netdev->trans_start,
560 			netdev->last_rx);
561 	}
562 
563 	/* Print Registers */
564 	dev_info(&adapter->pdev->dev, "Register Dump\n");
565 	pr_info(" Register Name   Value\n");
566 	for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 	     reginfo->name; reginfo++) {
568 		ixgbe_regdump(hw, reginfo);
569 	}
570 
571 	/* Print TX Ring Summary */
572 	if (!netdev || !netif_running(netdev))
573 		goto exit;
574 
575 	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
576 	pr_info(" %s     %s              %s        %s\n",
577 		"Queue [NTU] [NTC] [bi(ntc)->dma  ]",
578 		"leng", "ntw", "timestamp");
579 	for (n = 0; n < adapter->num_tx_queues; n++) {
580 		tx_ring = adapter->tx_ring[n];
581 		tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
582 		pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
583 			   n, tx_ring->next_to_use, tx_ring->next_to_clean,
584 			   (u64)dma_unmap_addr(tx_buffer, dma),
585 			   dma_unmap_len(tx_buffer, len),
586 			   tx_buffer->next_to_watch,
587 			   (u64)tx_buffer->time_stamp);
588 	}
589 
590 	/* Print TX Rings */
591 	if (!netif_msg_tx_done(adapter))
592 		goto rx_ring_summary;
593 
594 	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595 
596 	/* Transmit Descriptor Formats
597 	 *
598 	 * 82598 Advanced Transmit Descriptor
599 	 *   +--------------------------------------------------------------+
600 	 * 0 |         Buffer Address [63:0]                                |
601 	 *   +--------------------------------------------------------------+
602 	 * 8 |  PAYLEN  | POPTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
603 	 *   +--------------------------------------------------------------+
604 	 *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
605 	 *
606 	 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 	 *   +--------------------------------------------------------------+
608 	 * 0 |                          RSV [63:0]                          |
609 	 *   +--------------------------------------------------------------+
610 	 * 8 |            RSV           |  STA  |          NXTSEQ           |
611 	 *   +--------------------------------------------------------------+
612 	 *   63                       36 35   32 31                         0
613 	 *
614 	 * 82599+ Advanced Transmit Descriptor
615 	 *   +--------------------------------------------------------------+
616 	 * 0 |         Buffer Address [63:0]                                |
617 	 *   +--------------------------------------------------------------+
618 	 * 8 |PAYLEN  |POPTS|CC|IDX  |STA  |DCMD  |DTYP |MAC  |RSV  |DTALEN |
619 	 *   +--------------------------------------------------------------+
620 	 *   63     46 45 40 39 38 36 35 32 31  24 23 20 19 18 17 16 15     0
621 	 *
622 	 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 	 *   +--------------------------------------------------------------+
624 	 * 0 |                          RSV [63:0]                          |
625 	 *   +--------------------------------------------------------------+
626 	 * 8 |            RSV           |  STA  |           RSV             |
627 	 *   +--------------------------------------------------------------+
628 	 *   63                       36 35   32 31                         0
629 	 */
630 
631 	for (n = 0; n < adapter->num_tx_queues; n++) {
632 		tx_ring = adapter->tx_ring[n];
633 		pr_info("------------------------------------\n");
634 		pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 		pr_info("------------------------------------\n");
636 		pr_info("%s%s    %s              %s        %s          %s\n",
637 			"T [desc]     [address 63:0  ] ",
638 			"[PlPOIdStDDt Ln] [bi->dma       ] ",
639 			"leng", "ntw", "timestamp", "bi->skb");
640 
641 		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
642 			tx_desc = IXGBE_TX_DESC(tx_ring, i);
643 			tx_buffer = &tx_ring->tx_buffer_info[i];
644 			u0 = (struct my_u0 *)tx_desc;
645 			if (dma_unmap_len(tx_buffer, len) > 0) {
646 				pr_info("T [0x%03X]    %016llX %016llX %016llX %08X %p %016llX %p",
647 					i,
648 					le64_to_cpu(u0->a),
649 					le64_to_cpu(u0->b),
650 					(u64)dma_unmap_addr(tx_buffer, dma),
651 					dma_unmap_len(tx_buffer, len),
652 					tx_buffer->next_to_watch,
653 					(u64)tx_buffer->time_stamp,
654 					tx_buffer->skb);
655 				if (i == tx_ring->next_to_use &&
656 					i == tx_ring->next_to_clean)
657 					pr_cont(" NTC/U\n");
658 				else if (i == tx_ring->next_to_use)
659 					pr_cont(" NTU\n");
660 				else if (i == tx_ring->next_to_clean)
661 					pr_cont(" NTC\n");
662 				else
663 					pr_cont("\n");
664 
665 				if (netif_msg_pktdata(adapter) &&
666 				    tx_buffer->skb)
667 					print_hex_dump(KERN_INFO, "",
668 						DUMP_PREFIX_ADDRESS, 16, 1,
669 						tx_buffer->skb->data,
670 						dma_unmap_len(tx_buffer, len),
671 						true);
672 			}
673 		}
674 	}
675 
676 	/* Print RX Rings Summary */
677 rx_ring_summary:
678 	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
679 	pr_info("Queue [NTU] [NTC]\n");
680 	for (n = 0; n < adapter->num_rx_queues; n++) {
681 		rx_ring = adapter->rx_ring[n];
682 		pr_info("%5d %5X %5X\n",
683 			n, rx_ring->next_to_use, rx_ring->next_to_clean);
684 	}
685 
686 	/* Print RX Rings */
687 	if (!netif_msg_rx_status(adapter))
688 		goto exit;
689 
690 	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691 
692 	/* Receive Descriptor Formats
693 	 *
694 	 * 82598 Advanced Receive Descriptor (Read) Format
695 	 *    63                                           1        0
696 	 *    +-----------------------------------------------------+
697 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
698 	 *    +----------------------------------------------+------+
699 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
700 	 *    +-----------------------------------------------------+
701 	 *
702 	 *
703 	 * 82598 Advanced Receive Descriptor (Write-Back) Format
704 	 *
705 	 *   63       48 47    32 31  30      21 20 16 15   4 3     0
706 	 *   +------------------------------------------------------+
707 	 * 0 |       RSS Hash /  |SPH| HDR_LEN  | RSV |Packet|  RSS |
708 	 *   | Packet   | IP     |   |          |     | Type | Type |
709 	 *   | Checksum | Ident  |   |          |     |      |      |
710 	 *   +------------------------------------------------------+
711 	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 	 *   +------------------------------------------------------+
713 	 *   63       48 47    32 31            20 19               0
714 	 *
715 	 * 82599+ Advanced Receive Descriptor (Read) Format
716 	 *    63                                           1        0
717 	 *    +-----------------------------------------------------+
718 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
719 	 *    +----------------------------------------------+------+
720 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
721 	 *    +-----------------------------------------------------+
722 	 *
723 	 *
724 	 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 	 *
726 	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
727 	 *   +------------------------------------------------------+
728 	 * 0 |RSS / Frag Checksum|SPH| HDR_LEN  |RSC- |Packet|  RSS |
729 	 *   |/ RTT / PCoE_PARAM |   |          | CNT | Type | Type |
730 	 *   |/ Flow Dir Flt ID  |   |          |     |      |      |
731 	 *   +------------------------------------------------------+
732 	 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 	 *   +------------------------------------------------------+
734 	 *   63       48 47    32 31          20 19                 0
735 	 */
736 
737 	for (n = 0; n < adapter->num_rx_queues; n++) {
738 		rx_ring = adapter->rx_ring[n];
739 		pr_info("------------------------------------\n");
740 		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 		pr_info("------------------------------------\n");
742 		pr_info("%s%s%s",
743 			"R  [desc]      [ PktBuf     A0] ",
744 			"[  HeadBuf   DD] [bi->dma       ] [bi->skb       ] ",
745 			"<-- Adv Rx Read format\n");
746 		pr_info("%s%s%s",
747 			"RWB[desc]      [PcsmIpSHl PtRs] ",
748 			"[vl er S cks ln] ---------------- [bi->skb       ] ",
749 			"<-- Adv Rx Write-Back format\n");
750 
751 		for (i = 0; i < rx_ring->count; i++) {
752 			rx_buffer_info = &rx_ring->rx_buffer_info[i];
753 			rx_desc = IXGBE_RX_DESC(rx_ring, i);
754 			u0 = (struct my_u0 *)rx_desc;
755 			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 			if (staterr & IXGBE_RXD_STAT_DD) {
757 				/* Descriptor Done */
758 				pr_info("RWB[0x%03X]     %016llX "
759 					"%016llX ---------------- %p", i,
760 					le64_to_cpu(u0->a),
761 					le64_to_cpu(u0->b),
762 					rx_buffer_info->skb);
763 			} else {
764 				pr_info("R  [0x%03X]     %016llX "
765 					"%016llX %016llX %p", i,
766 					le64_to_cpu(u0->a),
767 					le64_to_cpu(u0->b),
768 					(u64)rx_buffer_info->dma,
769 					rx_buffer_info->skb);
770 
771 				if (netif_msg_pktdata(adapter) &&
772 				    rx_buffer_info->dma) {
773 					print_hex_dump(KERN_INFO, "",
774 					   DUMP_PREFIX_ADDRESS, 16, 1,
775 					   page_address(rx_buffer_info->page) +
776 						    rx_buffer_info->page_offset,
777 					   ixgbe_rx_bufsz(rx_ring), true);
778 				}
779 			}
780 
781 			if (i == rx_ring->next_to_use)
782 				pr_cont(" NTU\n");
783 			else if (i == rx_ring->next_to_clean)
784 				pr_cont(" NTC\n");
785 			else
786 				pr_cont("\n");
787 
788 		}
789 	}
790 
791 exit:
792 	return;
793 }
794 
795 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
796 {
797 	u32 ctrl_ext;
798 
799 	/* Let firmware take over control of h/w */
800 	ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
801 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
802 			ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
803 }
804 
805 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
806 {
807 	u32 ctrl_ext;
808 
809 	/* Let firmware know the driver has taken over */
810 	ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
811 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
812 			ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
813 }
814 
815 /**
816  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
817  * @adapter: pointer to adapter struct
818  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
819  * @queue: queue to map the corresponding interrupt to
820  * @msix_vector: the vector to map to the corresponding queue
821  *
822  */
823 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
824 			   u8 queue, u8 msix_vector)
825 {
826 	u32 ivar, index;
827 	struct ixgbe_hw *hw = &adapter->hw;
828 	switch (hw->mac.type) {
829 	case ixgbe_mac_82598EB:
830 		msix_vector |= IXGBE_IVAR_ALLOC_VAL;
831 		if (direction == -1)
832 			direction = 0;
833 		index = (((direction * 64) + queue) >> 2) & 0x1F;
834 		ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
835 		ivar &= ~(0xFF << (8 * (queue & 0x3)));
836 		ivar |= (msix_vector << (8 * (queue & 0x3)));
837 		IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
838 		break;
839 	case ixgbe_mac_82599EB:
840 	case ixgbe_mac_X540:
841 		if (direction == -1) {
842 			/* other causes */
843 			msix_vector |= IXGBE_IVAR_ALLOC_VAL;
844 			index = ((queue & 1) * 8);
845 			ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
846 			ivar &= ~(0xFF << index);
847 			ivar |= (msix_vector << index);
848 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
849 			break;
850 		} else {
851 			/* tx or rx causes */
852 			msix_vector |= IXGBE_IVAR_ALLOC_VAL;
853 			index = ((16 * (queue & 1)) + (8 * direction));
854 			ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
855 			ivar &= ~(0xFF << index);
856 			ivar |= (msix_vector << index);
857 			IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
858 			break;
859 		}
860 	default:
861 		break;
862 	}
863 }
864 
865 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
866 					  u64 qmask)
867 {
868 	u32 mask;
869 
870 	switch (adapter->hw.mac.type) {
871 	case ixgbe_mac_82598EB:
872 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
873 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
874 		break;
875 	case ixgbe_mac_82599EB:
876 	case ixgbe_mac_X540:
877 		mask = (qmask & 0xFFFFFFFF);
878 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
879 		mask = (qmask >> 32);
880 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
881 		break;
882 	default:
883 		break;
884 	}
885 }
886 
887 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
888 				      struct ixgbe_tx_buffer *tx_buffer)
889 {
890 	if (tx_buffer->skb) {
891 		dev_kfree_skb_any(tx_buffer->skb);
892 		if (dma_unmap_len(tx_buffer, len))
893 			dma_unmap_single(ring->dev,
894 					 dma_unmap_addr(tx_buffer, dma),
895 					 dma_unmap_len(tx_buffer, len),
896 					 DMA_TO_DEVICE);
897 	} else if (dma_unmap_len(tx_buffer, len)) {
898 		dma_unmap_page(ring->dev,
899 			       dma_unmap_addr(tx_buffer, dma),
900 			       dma_unmap_len(tx_buffer, len),
901 			       DMA_TO_DEVICE);
902 	}
903 	tx_buffer->next_to_watch = NULL;
904 	tx_buffer->skb = NULL;
905 	dma_unmap_len_set(tx_buffer, len, 0);
906 	/* tx_buffer must be completely set up in the transmit path */
907 }
908 
909 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
910 {
911 	struct ixgbe_hw *hw = &adapter->hw;
912 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
913 	int i;
914 	u32 data;
915 
916 	if ((hw->fc.current_mode != ixgbe_fc_full) &&
917 	    (hw->fc.current_mode != ixgbe_fc_rx_pause))
918 		return;
919 
920 	switch (hw->mac.type) {
921 	case ixgbe_mac_82598EB:
922 		data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
923 		break;
924 	default:
925 		data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
926 	}
927 	hwstats->lxoffrxc += data;
928 
929 	/* refill credits (no tx hang) if we received xoff */
930 	if (!data)
931 		return;
932 
933 	for (i = 0; i < adapter->num_tx_queues; i++)
934 		clear_bit(__IXGBE_HANG_CHECK_ARMED,
935 			  &adapter->tx_ring[i]->state);
936 }
937 
938 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
939 {
940 	struct ixgbe_hw *hw = &adapter->hw;
941 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
942 	u32 xoff[8] = {0};
943 	u8 tc;
944 	int i;
945 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
946 
947 	if (adapter->ixgbe_ieee_pfc)
948 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
949 
950 	if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
951 		ixgbe_update_xoff_rx_lfc(adapter);
952 		return;
953 	}
954 
955 	/* update stats for each tc, only valid with PFC enabled */
956 	for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
957 		u32 pxoffrxc;
958 
959 		switch (hw->mac.type) {
960 		case ixgbe_mac_82598EB:
961 			pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
962 			break;
963 		default:
964 			pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
965 		}
966 		hwstats->pxoffrxc[i] += pxoffrxc;
967 		/* Get the TC for given UP */
968 		tc = netdev_get_prio_tc_map(adapter->netdev, i);
969 		xoff[tc] += pxoffrxc;
970 	}
971 
972 	/* disarm tx queues that have received xoff frames */
973 	for (i = 0; i < adapter->num_tx_queues; i++) {
974 		struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
975 
976 		tc = tx_ring->dcb_tc;
977 		if (xoff[tc])
978 			clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
979 	}
980 }
981 
982 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
983 {
984 	return ring->stats.packets;
985 }
986 
987 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
988 {
989 	struct ixgbe_adapter *adapter;
990 	struct ixgbe_hw *hw;
991 	u32 head, tail;
992 
993 	if (ring->l2_accel_priv)
994 		adapter = ring->l2_accel_priv->real_adapter;
995 	else
996 		adapter = netdev_priv(ring->netdev);
997 
998 	hw = &adapter->hw;
999 	head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1000 	tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1001 
1002 	if (head != tail)
1003 		return (head < tail) ?
1004 			tail - head : (tail + ring->count - head);
1005 
1006 	return 0;
1007 }
1008 
1009 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1010 {
1011 	u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1012 	u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1013 	u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1014 	bool ret = false;
1015 
1016 	clear_check_for_tx_hang(tx_ring);
1017 
1018 	/*
1019 	 * Check for a hung queue, but be thorough. This verifies
1020 	 * that a transmit has been completed since the previous
1021 	 * check AND there is at least one packet pending. The
1022 	 * ARMED bit is set to indicate a potential hang. The
1023 	 * bit is cleared if a pause frame is received to remove
1024 	 * false hang detection due to PFC or 802.3x frames. By
1025 	 * requiring this to fail twice we avoid races with
1026 	 * pfc clearing the ARMED bit and conditions where we
1027 	 * run the check_tx_hang logic with a transmit completion
1028 	 * pending but without time to complete it yet.
1029 	 */
1030 	if ((tx_done_old == tx_done) && tx_pending) {
1031 		/* make sure it is true for two checks in a row */
1032 		ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1033 				       &tx_ring->state);
1034 	} else {
1035 		/* update completed stats and continue */
1036 		tx_ring->tx_stats.tx_done_old = tx_done;
1037 		/* reset the countdown */
1038 		clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1039 	}
1040 
1041 	return ret;
1042 }
1043 
1044 /**
1045  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1046  * @adapter: driver private struct
1047  **/
1048 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1049 {
1050 
1051 	/* Do the reset outside of interrupt context */
1052 	if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1053 		adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1054 		e_warn(drv, "initiating reset due to tx timeout\n");
1055 		ixgbe_service_event_schedule(adapter);
1056 	}
1057 }
1058 
1059 /**
1060  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1061  * @q_vector: structure containing interrupt and ring information
1062  * @tx_ring: tx ring to clean
1063  **/
1064 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1065 			       struct ixgbe_ring *tx_ring)
1066 {
1067 	struct ixgbe_adapter *adapter = q_vector->adapter;
1068 	struct ixgbe_tx_buffer *tx_buffer;
1069 	union ixgbe_adv_tx_desc *tx_desc;
1070 	unsigned int total_bytes = 0, total_packets = 0;
1071 	unsigned int budget = q_vector->tx.work_limit;
1072 	unsigned int i = tx_ring->next_to_clean;
1073 
1074 	if (test_bit(__IXGBE_DOWN, &adapter->state))
1075 		return true;
1076 
1077 	tx_buffer = &tx_ring->tx_buffer_info[i];
1078 	tx_desc = IXGBE_TX_DESC(tx_ring, i);
1079 	i -= tx_ring->count;
1080 
1081 	do {
1082 		union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1083 
1084 		/* if next_to_watch is not set then there is no work pending */
1085 		if (!eop_desc)
1086 			break;
1087 
1088 		/* prevent any other reads prior to eop_desc */
1089 		read_barrier_depends();
1090 
1091 		/* if DD is not set pending work has not been completed */
1092 		if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1093 			break;
1094 
1095 		/* clear next_to_watch to prevent false hangs */
1096 		tx_buffer->next_to_watch = NULL;
1097 
1098 		/* update the statistics for this packet */
1099 		total_bytes += tx_buffer->bytecount;
1100 		total_packets += tx_buffer->gso_segs;
1101 
1102 		/* free the skb */
1103 		dev_kfree_skb_any(tx_buffer->skb);
1104 
1105 		/* unmap skb header data */
1106 		dma_unmap_single(tx_ring->dev,
1107 				 dma_unmap_addr(tx_buffer, dma),
1108 				 dma_unmap_len(tx_buffer, len),
1109 				 DMA_TO_DEVICE);
1110 
1111 		/* clear tx_buffer data */
1112 		tx_buffer->skb = NULL;
1113 		dma_unmap_len_set(tx_buffer, len, 0);
1114 
1115 		/* unmap remaining buffers */
1116 		while (tx_desc != eop_desc) {
1117 			tx_buffer++;
1118 			tx_desc++;
1119 			i++;
1120 			if (unlikely(!i)) {
1121 				i -= tx_ring->count;
1122 				tx_buffer = tx_ring->tx_buffer_info;
1123 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1124 			}
1125 
1126 			/* unmap any remaining paged data */
1127 			if (dma_unmap_len(tx_buffer, len)) {
1128 				dma_unmap_page(tx_ring->dev,
1129 					       dma_unmap_addr(tx_buffer, dma),
1130 					       dma_unmap_len(tx_buffer, len),
1131 					       DMA_TO_DEVICE);
1132 				dma_unmap_len_set(tx_buffer, len, 0);
1133 			}
1134 		}
1135 
1136 		/* move us one more past the eop_desc for start of next pkt */
1137 		tx_buffer++;
1138 		tx_desc++;
1139 		i++;
1140 		if (unlikely(!i)) {
1141 			i -= tx_ring->count;
1142 			tx_buffer = tx_ring->tx_buffer_info;
1143 			tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1144 		}
1145 
1146 		/* issue prefetch for next Tx descriptor */
1147 		prefetch(tx_desc);
1148 
1149 		/* update budget accounting */
1150 		budget--;
1151 	} while (likely(budget));
1152 
1153 	i += tx_ring->count;
1154 	tx_ring->next_to_clean = i;
1155 	u64_stats_update_begin(&tx_ring->syncp);
1156 	tx_ring->stats.bytes += total_bytes;
1157 	tx_ring->stats.packets += total_packets;
1158 	u64_stats_update_end(&tx_ring->syncp);
1159 	q_vector->tx.total_bytes += total_bytes;
1160 	q_vector->tx.total_packets += total_packets;
1161 
1162 	if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1163 		/* schedule immediate reset if we believe we hung */
1164 		struct ixgbe_hw *hw = &adapter->hw;
1165 		e_err(drv, "Detected Tx Unit Hang\n"
1166 			"  Tx Queue             <%d>\n"
1167 			"  TDH, TDT             <%x>, <%x>\n"
1168 			"  next_to_use          <%x>\n"
1169 			"  next_to_clean        <%x>\n"
1170 			"tx_buffer_info[next_to_clean]\n"
1171 			"  time_stamp           <%lx>\n"
1172 			"  jiffies              <%lx>\n",
1173 			tx_ring->queue_index,
1174 			IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1175 			IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1176 			tx_ring->next_to_use, i,
1177 			tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1178 
1179 		netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1180 
1181 		e_info(probe,
1182 		       "tx hang %d detected on queue %d, resetting adapter\n",
1183 			adapter->tx_timeout_count + 1, tx_ring->queue_index);
1184 
1185 		/* schedule immediate reset if we believe we hung */
1186 		ixgbe_tx_timeout_reset(adapter);
1187 
1188 		/* the adapter is about to reset, no point in enabling stuff */
1189 		return true;
1190 	}
1191 
1192 	netdev_tx_completed_queue(txring_txq(tx_ring),
1193 				  total_packets, total_bytes);
1194 
1195 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1196 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1197 		     (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1198 		/* Make sure that anybody stopping the queue after this
1199 		 * sees the new next_to_clean.
1200 		 */
1201 		smp_mb();
1202 		if (__netif_subqueue_stopped(tx_ring->netdev,
1203 					     tx_ring->queue_index)
1204 		    && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1205 			netif_wake_subqueue(tx_ring->netdev,
1206 					    tx_ring->queue_index);
1207 			++tx_ring->tx_stats.restart_queue;
1208 		}
1209 	}
1210 
1211 	return !!budget;
1212 }
1213 
1214 #ifdef CONFIG_IXGBE_DCA
1215 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1216 				struct ixgbe_ring *tx_ring,
1217 				int cpu)
1218 {
1219 	struct ixgbe_hw *hw = &adapter->hw;
1220 	u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1221 	u16 reg_offset;
1222 
1223 	switch (hw->mac.type) {
1224 	case ixgbe_mac_82598EB:
1225 		reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1226 		break;
1227 	case ixgbe_mac_82599EB:
1228 	case ixgbe_mac_X540:
1229 		reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1230 		txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1231 		break;
1232 	default:
1233 		/* for unknown hardware do not write register */
1234 		return;
1235 	}
1236 
1237 	/*
1238 	 * We can enable relaxed ordering for reads, but not writes when
1239 	 * DCA is enabled.  This is due to a known issue in some chipsets
1240 	 * which will cause the DCA tag to be cleared.
1241 	 */
1242 	txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1243 		  IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1244 		  IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1245 
1246 	IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1247 }
1248 
1249 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1250 				struct ixgbe_ring *rx_ring,
1251 				int cpu)
1252 {
1253 	struct ixgbe_hw *hw = &adapter->hw;
1254 	u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1255 	u8 reg_idx = rx_ring->reg_idx;
1256 
1257 
1258 	switch (hw->mac.type) {
1259 	case ixgbe_mac_82599EB:
1260 	case ixgbe_mac_X540:
1261 		rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1262 		break;
1263 	default:
1264 		break;
1265 	}
1266 
1267 	/*
1268 	 * We can enable relaxed ordering for reads, but not writes when
1269 	 * DCA is enabled.  This is due to a known issue in some chipsets
1270 	 * which will cause the DCA tag to be cleared.
1271 	 */
1272 	rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1273 		  IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1274 
1275 	IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1276 }
1277 
1278 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1279 {
1280 	struct ixgbe_adapter *adapter = q_vector->adapter;
1281 	struct ixgbe_ring *ring;
1282 	int cpu = get_cpu();
1283 
1284 	if (q_vector->cpu == cpu)
1285 		goto out_no_update;
1286 
1287 	ixgbe_for_each_ring(ring, q_vector->tx)
1288 		ixgbe_update_tx_dca(adapter, ring, cpu);
1289 
1290 	ixgbe_for_each_ring(ring, q_vector->rx)
1291 		ixgbe_update_rx_dca(adapter, ring, cpu);
1292 
1293 	q_vector->cpu = cpu;
1294 out_no_update:
1295 	put_cpu();
1296 }
1297 
1298 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1299 {
1300 	int i;
1301 
1302 	if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1303 		return;
1304 
1305 	/* always use CB2 mode, difference is masked in the CB driver */
1306 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1307 
1308 	for (i = 0; i < adapter->num_q_vectors; i++) {
1309 		adapter->q_vector[i]->cpu = -1;
1310 		ixgbe_update_dca(adapter->q_vector[i]);
1311 	}
1312 }
1313 
1314 static int __ixgbe_notify_dca(struct device *dev, void *data)
1315 {
1316 	struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1317 	unsigned long event = *(unsigned long *)data;
1318 
1319 	if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1320 		return 0;
1321 
1322 	switch (event) {
1323 	case DCA_PROVIDER_ADD:
1324 		/* if we're already enabled, don't do it again */
1325 		if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1326 			break;
1327 		if (dca_add_requester(dev) == 0) {
1328 			adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1329 			ixgbe_setup_dca(adapter);
1330 			break;
1331 		}
1332 		/* Fall Through since DCA is disabled. */
1333 	case DCA_PROVIDER_REMOVE:
1334 		if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1335 			dca_remove_requester(dev);
1336 			adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1337 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1338 		}
1339 		break;
1340 	}
1341 
1342 	return 0;
1343 }
1344 
1345 #endif /* CONFIG_IXGBE_DCA */
1346 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1347 				 union ixgbe_adv_rx_desc *rx_desc,
1348 				 struct sk_buff *skb)
1349 {
1350 	if (ring->netdev->features & NETIF_F_RXHASH)
1351 		skb_set_hash(skb,
1352 			     le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1353 			     PKT_HASH_TYPE_L3);
1354 }
1355 
1356 #ifdef IXGBE_FCOE
1357 /**
1358  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1359  * @ring: structure containing ring specific data
1360  * @rx_desc: advanced rx descriptor
1361  *
1362  * Returns : true if it is FCoE pkt
1363  */
1364 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1365 				    union ixgbe_adv_rx_desc *rx_desc)
1366 {
1367 	__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1368 
1369 	return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1370 	       ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1371 		(cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1372 			     IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1373 }
1374 
1375 #endif /* IXGBE_FCOE */
1376 /**
1377  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1378  * @ring: structure containing ring specific data
1379  * @rx_desc: current Rx descriptor being processed
1380  * @skb: skb currently being received and modified
1381  **/
1382 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1383 				     union ixgbe_adv_rx_desc *rx_desc,
1384 				     struct sk_buff *skb)
1385 {
1386 	skb_checksum_none_assert(skb);
1387 
1388 	/* Rx csum disabled */
1389 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
1390 		return;
1391 
1392 	/* if IP and error */
1393 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1394 	    ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1395 		ring->rx_stats.csum_err++;
1396 		return;
1397 	}
1398 
1399 	if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1400 		return;
1401 
1402 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1403 		__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1404 
1405 		/*
1406 		 * 82599 errata, UDP frames with a 0 checksum can be marked as
1407 		 * checksum errors.
1408 		 */
1409 		if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1410 		    test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1411 			return;
1412 
1413 		ring->rx_stats.csum_err++;
1414 		return;
1415 	}
1416 
1417 	/* It must be a TCP or UDP packet with a valid checksum */
1418 	skb->ip_summed = CHECKSUM_UNNECESSARY;
1419 }
1420 
1421 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1422 {
1423 	rx_ring->next_to_use = val;
1424 
1425 	/* update next to alloc since we have filled the ring */
1426 	rx_ring->next_to_alloc = val;
1427 	/*
1428 	 * Force memory writes to complete before letting h/w
1429 	 * know there are new descriptors to fetch.  (Only
1430 	 * applicable for weak-ordered memory model archs,
1431 	 * such as IA-64).
1432 	 */
1433 	wmb();
1434 	ixgbe_write_tail(rx_ring, val);
1435 }
1436 
1437 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1438 				    struct ixgbe_rx_buffer *bi)
1439 {
1440 	struct page *page = bi->page;
1441 	dma_addr_t dma = bi->dma;
1442 
1443 	/* since we are recycling buffers we should seldom need to alloc */
1444 	if (likely(dma))
1445 		return true;
1446 
1447 	/* alloc new page for storage */
1448 	if (likely(!page)) {
1449 		page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1450 					 bi->skb, ixgbe_rx_pg_order(rx_ring));
1451 		if (unlikely(!page)) {
1452 			rx_ring->rx_stats.alloc_rx_page_failed++;
1453 			return false;
1454 		}
1455 		bi->page = page;
1456 	}
1457 
1458 	/* map page for use */
1459 	dma = dma_map_page(rx_ring->dev, page, 0,
1460 			   ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1461 
1462 	/*
1463 	 * if mapping failed free memory back to system since
1464 	 * there isn't much point in holding memory we can't use
1465 	 */
1466 	if (dma_mapping_error(rx_ring->dev, dma)) {
1467 		__free_pages(page, ixgbe_rx_pg_order(rx_ring));
1468 		bi->page = NULL;
1469 
1470 		rx_ring->rx_stats.alloc_rx_page_failed++;
1471 		return false;
1472 	}
1473 
1474 	bi->dma = dma;
1475 	bi->page_offset = 0;
1476 
1477 	return true;
1478 }
1479 
1480 /**
1481  * ixgbe_alloc_rx_buffers - Replace used receive buffers
1482  * @rx_ring: ring to place buffers on
1483  * @cleaned_count: number of buffers to replace
1484  **/
1485 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1486 {
1487 	union ixgbe_adv_rx_desc *rx_desc;
1488 	struct ixgbe_rx_buffer *bi;
1489 	u16 i = rx_ring->next_to_use;
1490 
1491 	/* nothing to do */
1492 	if (!cleaned_count)
1493 		return;
1494 
1495 	rx_desc = IXGBE_RX_DESC(rx_ring, i);
1496 	bi = &rx_ring->rx_buffer_info[i];
1497 	i -= rx_ring->count;
1498 
1499 	do {
1500 		if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1501 			break;
1502 
1503 		/*
1504 		 * Refresh the desc even if buffer_addrs didn't change
1505 		 * because each write-back erases this info.
1506 		 */
1507 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1508 
1509 		rx_desc++;
1510 		bi++;
1511 		i++;
1512 		if (unlikely(!i)) {
1513 			rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1514 			bi = rx_ring->rx_buffer_info;
1515 			i -= rx_ring->count;
1516 		}
1517 
1518 		/* clear the hdr_addr for the next_to_use descriptor */
1519 		rx_desc->read.hdr_addr = 0;
1520 
1521 		cleaned_count--;
1522 	} while (cleaned_count);
1523 
1524 	i += rx_ring->count;
1525 
1526 	if (rx_ring->next_to_use != i)
1527 		ixgbe_release_rx_desc(rx_ring, i);
1528 }
1529 
1530 /**
1531  * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1532  * @data: pointer to the start of the headers
1533  * @max_len: total length of section to find headers in
1534  *
1535  * This function is meant to determine the length of headers that will
1536  * be recognized by hardware for LRO, GRO, and RSC offloads.  The main
1537  * motivation of doing this is to only perform one pull for IPv4 TCP
1538  * packets so that we can do basic things like calculating the gso_size
1539  * based on the average data per packet.
1540  **/
1541 static unsigned int ixgbe_get_headlen(unsigned char *data,
1542 				      unsigned int max_len)
1543 {
1544 	union {
1545 		unsigned char *network;
1546 		/* l2 headers */
1547 		struct ethhdr *eth;
1548 		struct vlan_hdr *vlan;
1549 		/* l3 headers */
1550 		struct iphdr *ipv4;
1551 		struct ipv6hdr *ipv6;
1552 	} hdr;
1553 	__be16 protocol;
1554 	u8 nexthdr = 0;	/* default to not TCP */
1555 	u8 hlen;
1556 
1557 	/* this should never happen, but better safe than sorry */
1558 	if (max_len < ETH_HLEN)
1559 		return max_len;
1560 
1561 	/* initialize network frame pointer */
1562 	hdr.network = data;
1563 
1564 	/* set first protocol and move network header forward */
1565 	protocol = hdr.eth->h_proto;
1566 	hdr.network += ETH_HLEN;
1567 
1568 	/* handle any vlan tag if present */
1569 	if (protocol == htons(ETH_P_8021Q)) {
1570 		if ((hdr.network - data) > (max_len - VLAN_HLEN))
1571 			return max_len;
1572 
1573 		protocol = hdr.vlan->h_vlan_encapsulated_proto;
1574 		hdr.network += VLAN_HLEN;
1575 	}
1576 
1577 	/* handle L3 protocols */
1578 	if (protocol == htons(ETH_P_IP)) {
1579 		if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1580 			return max_len;
1581 
1582 		/* access ihl as a u8 to avoid unaligned access on ia64 */
1583 		hlen = (hdr.network[0] & 0x0F) << 2;
1584 
1585 		/* verify hlen meets minimum size requirements */
1586 		if (hlen < sizeof(struct iphdr))
1587 			return hdr.network - data;
1588 
1589 		/* record next protocol if header is present */
1590 		if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
1591 			nexthdr = hdr.ipv4->protocol;
1592 	} else if (protocol == htons(ETH_P_IPV6)) {
1593 		if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1594 			return max_len;
1595 
1596 		/* record next protocol */
1597 		nexthdr = hdr.ipv6->nexthdr;
1598 		hlen = sizeof(struct ipv6hdr);
1599 #ifdef IXGBE_FCOE
1600 	} else if (protocol == htons(ETH_P_FCOE)) {
1601 		if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1602 			return max_len;
1603 		hlen = FCOE_HEADER_LEN;
1604 #endif
1605 	} else {
1606 		return hdr.network - data;
1607 	}
1608 
1609 	/* relocate pointer to start of L4 header */
1610 	hdr.network += hlen;
1611 
1612 	/* finally sort out TCP/UDP */
1613 	if (nexthdr == IPPROTO_TCP) {
1614 		if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1615 			return max_len;
1616 
1617 		/* access doff as a u8 to avoid unaligned access on ia64 */
1618 		hlen = (hdr.network[12] & 0xF0) >> 2;
1619 
1620 		/* verify hlen meets minimum size requirements */
1621 		if (hlen < sizeof(struct tcphdr))
1622 			return hdr.network - data;
1623 
1624 		hdr.network += hlen;
1625 	} else if (nexthdr == IPPROTO_UDP) {
1626 		if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1627 			return max_len;
1628 
1629 		hdr.network += sizeof(struct udphdr);
1630 	}
1631 
1632 	/*
1633 	 * If everything has gone correctly hdr.network should be the
1634 	 * data section of the packet and will be the end of the header.
1635 	 * If not then it probably represents the end of the last recognized
1636 	 * header.
1637 	 */
1638 	if ((hdr.network - data) < max_len)
1639 		return hdr.network - data;
1640 	else
1641 		return max_len;
1642 }
1643 
1644 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1645 				   struct sk_buff *skb)
1646 {
1647 	u16 hdr_len = skb_headlen(skb);
1648 
1649 	/* set gso_size to avoid messing up TCP MSS */
1650 	skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1651 						 IXGBE_CB(skb)->append_cnt);
1652 	skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1653 }
1654 
1655 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1656 				   struct sk_buff *skb)
1657 {
1658 	/* if append_cnt is 0 then frame is not RSC */
1659 	if (!IXGBE_CB(skb)->append_cnt)
1660 		return;
1661 
1662 	rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1663 	rx_ring->rx_stats.rsc_flush++;
1664 
1665 	ixgbe_set_rsc_gso_size(rx_ring, skb);
1666 
1667 	/* gso_size is computed using append_cnt so always clear it last */
1668 	IXGBE_CB(skb)->append_cnt = 0;
1669 }
1670 
1671 /**
1672  * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1673  * @rx_ring: rx descriptor ring packet is being transacted on
1674  * @rx_desc: pointer to the EOP Rx descriptor
1675  * @skb: pointer to current skb being populated
1676  *
1677  * This function checks the ring, descriptor, and packet information in
1678  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1679  * other fields within the skb.
1680  **/
1681 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1682 				     union ixgbe_adv_rx_desc *rx_desc,
1683 				     struct sk_buff *skb)
1684 {
1685 	struct net_device *dev = rx_ring->netdev;
1686 
1687 	ixgbe_update_rsc_stats(rx_ring, skb);
1688 
1689 	ixgbe_rx_hash(rx_ring, rx_desc, skb);
1690 
1691 	ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1692 
1693 	if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1694 		ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1695 
1696 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1697 	    ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1698 		u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1699 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1700 	}
1701 
1702 	skb_record_rx_queue(skb, rx_ring->queue_index);
1703 
1704 	skb->protocol = eth_type_trans(skb, dev);
1705 }
1706 
1707 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1708 			 struct sk_buff *skb)
1709 {
1710 	struct ixgbe_adapter *adapter = q_vector->adapter;
1711 
1712 	if (ixgbe_qv_busy_polling(q_vector))
1713 		netif_receive_skb(skb);
1714 	else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1715 		napi_gro_receive(&q_vector->napi, skb);
1716 	else
1717 		netif_rx(skb);
1718 }
1719 
1720 /**
1721  * ixgbe_is_non_eop - process handling of non-EOP buffers
1722  * @rx_ring: Rx ring being processed
1723  * @rx_desc: Rx descriptor for current buffer
1724  * @skb: Current socket buffer containing buffer in progress
1725  *
1726  * This function updates next to clean.  If the buffer is an EOP buffer
1727  * this function exits returning false, otherwise it will place the
1728  * sk_buff in the next buffer to be chained and return true indicating
1729  * that this is in fact a non-EOP buffer.
1730  **/
1731 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1732 			     union ixgbe_adv_rx_desc *rx_desc,
1733 			     struct sk_buff *skb)
1734 {
1735 	u32 ntc = rx_ring->next_to_clean + 1;
1736 
1737 	/* fetch, update, and store next to clean */
1738 	ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 	rx_ring->next_to_clean = ntc;
1740 
1741 	prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1742 
1743 	/* update RSC append count if present */
1744 	if (ring_is_rsc_enabled(rx_ring)) {
1745 		__le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1746 				     cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1747 
1748 		if (unlikely(rsc_enabled)) {
1749 			u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1750 
1751 			rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1752 			IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1753 
1754 			/* update ntc based on RSC value */
1755 			ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1756 			ntc &= IXGBE_RXDADV_NEXTP_MASK;
1757 			ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1758 		}
1759 	}
1760 
1761 	/* if we are the last buffer then there is nothing else to do */
1762 	if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1763 		return false;
1764 
1765 	/* place skb in next buffer to be received */
1766 	rx_ring->rx_buffer_info[ntc].skb = skb;
1767 	rx_ring->rx_stats.non_eop_descs++;
1768 
1769 	return true;
1770 }
1771 
1772 /**
1773  * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1774  * @rx_ring: rx descriptor ring packet is being transacted on
1775  * @skb: pointer to current skb being adjusted
1776  *
1777  * This function is an ixgbe specific version of __pskb_pull_tail.  The
1778  * main difference between this version and the original function is that
1779  * this function can make several assumptions about the state of things
1780  * that allow for significant optimizations versus the standard function.
1781  * As a result we can do things like drop a frag and maintain an accurate
1782  * truesize for the skb.
1783  */
1784 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1785 			    struct sk_buff *skb)
1786 {
1787 	struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1788 	unsigned char *va;
1789 	unsigned int pull_len;
1790 
1791 	/*
1792 	 * it is valid to use page_address instead of kmap since we are
1793 	 * working with pages allocated out of the lomem pool per
1794 	 * alloc_page(GFP_ATOMIC)
1795 	 */
1796 	va = skb_frag_address(frag);
1797 
1798 	/*
1799 	 * we need the header to contain the greater of either ETH_HLEN or
1800 	 * 60 bytes if the skb->len is less than 60 for skb_pad.
1801 	 */
1802 	pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1803 
1804 	/* align pull length to size of long to optimize memcpy performance */
1805 	skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1806 
1807 	/* update all of the pointers */
1808 	skb_frag_size_sub(frag, pull_len);
1809 	frag->page_offset += pull_len;
1810 	skb->data_len -= pull_len;
1811 	skb->tail += pull_len;
1812 }
1813 
1814 /**
1815  * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1816  * @rx_ring: rx descriptor ring packet is being transacted on
1817  * @skb: pointer to current skb being updated
1818  *
1819  * This function provides a basic DMA sync up for the first fragment of an
1820  * skb.  The reason for doing this is that the first fragment cannot be
1821  * unmapped until we have reached the end of packet descriptor for a buffer
1822  * chain.
1823  */
1824 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1825 				struct sk_buff *skb)
1826 {
1827 	/* if the page was released unmap it, else just sync our portion */
1828 	if (unlikely(IXGBE_CB(skb)->page_released)) {
1829 		dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1830 			       ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1831 		IXGBE_CB(skb)->page_released = false;
1832 	} else {
1833 		struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1834 
1835 		dma_sync_single_range_for_cpu(rx_ring->dev,
1836 					      IXGBE_CB(skb)->dma,
1837 					      frag->page_offset,
1838 					      ixgbe_rx_bufsz(rx_ring),
1839 					      DMA_FROM_DEVICE);
1840 	}
1841 	IXGBE_CB(skb)->dma = 0;
1842 }
1843 
1844 /**
1845  * ixgbe_cleanup_headers - Correct corrupted or empty headers
1846  * @rx_ring: rx descriptor ring packet is being transacted on
1847  * @rx_desc: pointer to the EOP Rx descriptor
1848  * @skb: pointer to current skb being fixed
1849  *
1850  * Check for corrupted packet headers caused by senders on the local L2
1851  * embedded NIC switch not setting up their Tx Descriptors right.  These
1852  * should be very rare.
1853  *
1854  * Also address the case where we are pulling data in on pages only
1855  * and as such no data is present in the skb header.
1856  *
1857  * In addition if skb is not at least 60 bytes we need to pad it so that
1858  * it is large enough to qualify as a valid Ethernet frame.
1859  *
1860  * Returns true if an error was encountered and skb was freed.
1861  **/
1862 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1863 				  union ixgbe_adv_rx_desc *rx_desc,
1864 				  struct sk_buff *skb)
1865 {
1866 	struct net_device *netdev = rx_ring->netdev;
1867 
1868 	/* verify that the packet does not have any known errors */
1869 	if (unlikely(ixgbe_test_staterr(rx_desc,
1870 					IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1871 	    !(netdev->features & NETIF_F_RXALL))) {
1872 		dev_kfree_skb_any(skb);
1873 		return true;
1874 	}
1875 
1876 	/* place header in linear portion of buffer */
1877 	if (skb_is_nonlinear(skb))
1878 		ixgbe_pull_tail(rx_ring, skb);
1879 
1880 #ifdef IXGBE_FCOE
1881 	/* do not attempt to pad FCoE Frames as this will disrupt DDP */
1882 	if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1883 		return false;
1884 
1885 #endif
1886 	/* if skb_pad returns an error the skb was freed */
1887 	if (unlikely(skb->len < 60)) {
1888 		int pad_len = 60 - skb->len;
1889 
1890 		if (skb_pad(skb, pad_len))
1891 			return true;
1892 		__skb_put(skb, pad_len);
1893 	}
1894 
1895 	return false;
1896 }
1897 
1898 /**
1899  * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1900  * @rx_ring: rx descriptor ring to store buffers on
1901  * @old_buff: donor buffer to have page reused
1902  *
1903  * Synchronizes page for reuse by the adapter
1904  **/
1905 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1906 				struct ixgbe_rx_buffer *old_buff)
1907 {
1908 	struct ixgbe_rx_buffer *new_buff;
1909 	u16 nta = rx_ring->next_to_alloc;
1910 
1911 	new_buff = &rx_ring->rx_buffer_info[nta];
1912 
1913 	/* update, and store next to alloc */
1914 	nta++;
1915 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1916 
1917 	/* transfer page from old buffer to new buffer */
1918 	new_buff->page = old_buff->page;
1919 	new_buff->dma = old_buff->dma;
1920 	new_buff->page_offset = old_buff->page_offset;
1921 
1922 	/* sync the buffer for use by the device */
1923 	dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1924 					 new_buff->page_offset,
1925 					 ixgbe_rx_bufsz(rx_ring),
1926 					 DMA_FROM_DEVICE);
1927 }
1928 
1929 /**
1930  * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1931  * @rx_ring: rx descriptor ring to transact packets on
1932  * @rx_buffer: buffer containing page to add
1933  * @rx_desc: descriptor containing length of buffer written by hardware
1934  * @skb: sk_buff to place the data into
1935  *
1936  * This function will add the data contained in rx_buffer->page to the skb.
1937  * This is done either through a direct copy if the data in the buffer is
1938  * less than the skb header size, otherwise it will just attach the page as
1939  * a frag to the skb.
1940  *
1941  * The function will then update the page offset if necessary and return
1942  * true if the buffer can be reused by the adapter.
1943  **/
1944 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1945 			      struct ixgbe_rx_buffer *rx_buffer,
1946 			      union ixgbe_adv_rx_desc *rx_desc,
1947 			      struct sk_buff *skb)
1948 {
1949 	struct page *page = rx_buffer->page;
1950 	unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1951 #if (PAGE_SIZE < 8192)
1952 	unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1953 #else
1954 	unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1955 	unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1956 				   ixgbe_rx_bufsz(rx_ring);
1957 #endif
1958 
1959 	if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1960 		unsigned char *va = page_address(page) + rx_buffer->page_offset;
1961 
1962 		memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1963 
1964 		/* we can reuse buffer as-is, just make sure it is local */
1965 		if (likely(page_to_nid(page) == numa_node_id()))
1966 			return true;
1967 
1968 		/* this page cannot be reused so discard it */
1969 		put_page(page);
1970 		return false;
1971 	}
1972 
1973 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1974 			rx_buffer->page_offset, size, truesize);
1975 
1976 	/* avoid re-using remote pages */
1977 	if (unlikely(page_to_nid(page) != numa_node_id()))
1978 		return false;
1979 
1980 #if (PAGE_SIZE < 8192)
1981 	/* if we are only owner of page we can reuse it */
1982 	if (unlikely(page_count(page) != 1))
1983 		return false;
1984 
1985 	/* flip page offset to other buffer */
1986 	rx_buffer->page_offset ^= truesize;
1987 
1988 	/*
1989 	 * since we are the only owner of the page and we need to
1990 	 * increment it, just set the value to 2 in order to avoid
1991 	 * an unecessary locked operation
1992 	 */
1993 	atomic_set(&page->_count, 2);
1994 #else
1995 	/* move offset up to the next cache line */
1996 	rx_buffer->page_offset += truesize;
1997 
1998 	if (rx_buffer->page_offset > last_offset)
1999 		return false;
2000 
2001 	/* bump ref count on page before it is given to the stack */
2002 	get_page(page);
2003 #endif
2004 
2005 	return true;
2006 }
2007 
2008 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
2009 					     union ixgbe_adv_rx_desc *rx_desc)
2010 {
2011 	struct ixgbe_rx_buffer *rx_buffer;
2012 	struct sk_buff *skb;
2013 	struct page *page;
2014 
2015 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2016 	page = rx_buffer->page;
2017 	prefetchw(page);
2018 
2019 	skb = rx_buffer->skb;
2020 
2021 	if (likely(!skb)) {
2022 		void *page_addr = page_address(page) +
2023 				  rx_buffer->page_offset;
2024 
2025 		/* prefetch first cache line of first page */
2026 		prefetch(page_addr);
2027 #if L1_CACHE_BYTES < 128
2028 		prefetch(page_addr + L1_CACHE_BYTES);
2029 #endif
2030 
2031 		/* allocate a skb to store the frags */
2032 		skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
2033 						IXGBE_RX_HDR_SIZE);
2034 		if (unlikely(!skb)) {
2035 			rx_ring->rx_stats.alloc_rx_buff_failed++;
2036 			return NULL;
2037 		}
2038 
2039 		/*
2040 		 * we will be copying header into skb->data in
2041 		 * pskb_may_pull so it is in our interest to prefetch
2042 		 * it now to avoid a possible cache miss
2043 		 */
2044 		prefetchw(skb->data);
2045 
2046 		/*
2047 		 * Delay unmapping of the first packet. It carries the
2048 		 * header information, HW may still access the header
2049 		 * after the writeback.  Only unmap it when EOP is
2050 		 * reached
2051 		 */
2052 		if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2053 			goto dma_sync;
2054 
2055 		IXGBE_CB(skb)->dma = rx_buffer->dma;
2056 	} else {
2057 		if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2058 			ixgbe_dma_sync_frag(rx_ring, skb);
2059 
2060 dma_sync:
2061 		/* we are reusing so sync this buffer for CPU use */
2062 		dma_sync_single_range_for_cpu(rx_ring->dev,
2063 					      rx_buffer->dma,
2064 					      rx_buffer->page_offset,
2065 					      ixgbe_rx_bufsz(rx_ring),
2066 					      DMA_FROM_DEVICE);
2067 	}
2068 
2069 	/* pull page into skb */
2070 	if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2071 		/* hand second half of page back to the ring */
2072 		ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2073 	} else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2074 		/* the page has been released from the ring */
2075 		IXGBE_CB(skb)->page_released = true;
2076 	} else {
2077 		/* we are not reusing the buffer so unmap it */
2078 		dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2079 			       ixgbe_rx_pg_size(rx_ring),
2080 			       DMA_FROM_DEVICE);
2081 	}
2082 
2083 	/* clear contents of buffer_info */
2084 	rx_buffer->skb = NULL;
2085 	rx_buffer->dma = 0;
2086 	rx_buffer->page = NULL;
2087 
2088 	return skb;
2089 }
2090 
2091 /**
2092  * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2093  * @q_vector: structure containing interrupt and ring information
2094  * @rx_ring: rx descriptor ring to transact packets on
2095  * @budget: Total limit on number of packets to process
2096  *
2097  * This function provides a "bounce buffer" approach to Rx interrupt
2098  * processing.  The advantage to this is that on systems that have
2099  * expensive overhead for IOMMU access this provides a means of avoiding
2100  * it by maintaining the mapping of the page to the syste.
2101  *
2102  * Returns amount of work completed
2103  **/
2104 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2105 			       struct ixgbe_ring *rx_ring,
2106 			       const int budget)
2107 {
2108 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2109 #ifdef IXGBE_FCOE
2110 	struct ixgbe_adapter *adapter = q_vector->adapter;
2111 	int ddp_bytes;
2112 	unsigned int mss = 0;
2113 #endif /* IXGBE_FCOE */
2114 	u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2115 
2116 	while (likely(total_rx_packets < budget)) {
2117 		union ixgbe_adv_rx_desc *rx_desc;
2118 		struct sk_buff *skb;
2119 
2120 		/* return some buffers to hardware, one at a time is too slow */
2121 		if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2122 			ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2123 			cleaned_count = 0;
2124 		}
2125 
2126 		rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2127 
2128 		if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2129 			break;
2130 
2131 		/*
2132 		 * This memory barrier is needed to keep us from reading
2133 		 * any other fields out of the rx_desc until we know the
2134 		 * RXD_STAT_DD bit is set
2135 		 */
2136 		rmb();
2137 
2138 		/* retrieve a buffer from the ring */
2139 		skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2140 
2141 		/* exit if we failed to retrieve a buffer */
2142 		if (!skb)
2143 			break;
2144 
2145 		cleaned_count++;
2146 
2147 		/* place incomplete frames back on ring for completion */
2148 		if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2149 			continue;
2150 
2151 		/* verify the packet layout is correct */
2152 		if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2153 			continue;
2154 
2155 		/* probably a little skewed due to removing CRC */
2156 		total_rx_bytes += skb->len;
2157 
2158 		/* populate checksum, timestamp, VLAN, and protocol */
2159 		ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2160 
2161 #ifdef IXGBE_FCOE
2162 		/* if ddp, not passing to ULD unless for FCP_RSP or error */
2163 		if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2164 			ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2165 			/* include DDPed FCoE data */
2166 			if (ddp_bytes > 0) {
2167 				if (!mss) {
2168 					mss = rx_ring->netdev->mtu -
2169 						sizeof(struct fcoe_hdr) -
2170 						sizeof(struct fc_frame_header) -
2171 						sizeof(struct fcoe_crc_eof);
2172 					if (mss > 512)
2173 						mss &= ~511;
2174 				}
2175 				total_rx_bytes += ddp_bytes;
2176 				total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2177 								 mss);
2178 			}
2179 			if (!ddp_bytes) {
2180 				dev_kfree_skb_any(skb);
2181 				continue;
2182 			}
2183 		}
2184 
2185 #endif /* IXGBE_FCOE */
2186 		skb_mark_napi_id(skb, &q_vector->napi);
2187 		ixgbe_rx_skb(q_vector, skb);
2188 
2189 		/* update budget accounting */
2190 		total_rx_packets++;
2191 	}
2192 
2193 	u64_stats_update_begin(&rx_ring->syncp);
2194 	rx_ring->stats.packets += total_rx_packets;
2195 	rx_ring->stats.bytes += total_rx_bytes;
2196 	u64_stats_update_end(&rx_ring->syncp);
2197 	q_vector->rx.total_packets += total_rx_packets;
2198 	q_vector->rx.total_bytes += total_rx_bytes;
2199 
2200 	if (cleaned_count)
2201 		ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2202 
2203 	return total_rx_packets;
2204 }
2205 
2206 #ifdef CONFIG_NET_RX_BUSY_POLL
2207 /* must be called with local_bh_disable()d */
2208 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2209 {
2210 	struct ixgbe_q_vector *q_vector =
2211 			container_of(napi, struct ixgbe_q_vector, napi);
2212 	struct ixgbe_adapter *adapter = q_vector->adapter;
2213 	struct ixgbe_ring  *ring;
2214 	int found = 0;
2215 
2216 	if (test_bit(__IXGBE_DOWN, &adapter->state))
2217 		return LL_FLUSH_FAILED;
2218 
2219 	if (!ixgbe_qv_lock_poll(q_vector))
2220 		return LL_FLUSH_BUSY;
2221 
2222 	ixgbe_for_each_ring(ring, q_vector->rx) {
2223 		found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2224 #ifdef BP_EXTENDED_STATS
2225 		if (found)
2226 			ring->stats.cleaned += found;
2227 		else
2228 			ring->stats.misses++;
2229 #endif
2230 		if (found)
2231 			break;
2232 	}
2233 
2234 	ixgbe_qv_unlock_poll(q_vector);
2235 
2236 	return found;
2237 }
2238 #endif	/* CONFIG_NET_RX_BUSY_POLL */
2239 
2240 /**
2241  * ixgbe_configure_msix - Configure MSI-X hardware
2242  * @adapter: board private structure
2243  *
2244  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2245  * interrupts.
2246  **/
2247 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2248 {
2249 	struct ixgbe_q_vector *q_vector;
2250 	int v_idx;
2251 	u32 mask;
2252 
2253 	/* Populate MSIX to EITR Select */
2254 	if (adapter->num_vfs > 32) {
2255 		u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2256 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2257 	}
2258 
2259 	/*
2260 	 * Populate the IVAR table and set the ITR values to the
2261 	 * corresponding register.
2262 	 */
2263 	for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2264 		struct ixgbe_ring *ring;
2265 		q_vector = adapter->q_vector[v_idx];
2266 
2267 		ixgbe_for_each_ring(ring, q_vector->rx)
2268 			ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2269 
2270 		ixgbe_for_each_ring(ring, q_vector->tx)
2271 			ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2272 
2273 		ixgbe_write_eitr(q_vector);
2274 	}
2275 
2276 	switch (adapter->hw.mac.type) {
2277 	case ixgbe_mac_82598EB:
2278 		ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2279 			       v_idx);
2280 		break;
2281 	case ixgbe_mac_82599EB:
2282 	case ixgbe_mac_X540:
2283 		ixgbe_set_ivar(adapter, -1, 1, v_idx);
2284 		break;
2285 	default:
2286 		break;
2287 	}
2288 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2289 
2290 	/* set up to autoclear timer, and the vectors */
2291 	mask = IXGBE_EIMS_ENABLE_MASK;
2292 	mask &= ~(IXGBE_EIMS_OTHER |
2293 		  IXGBE_EIMS_MAILBOX |
2294 		  IXGBE_EIMS_LSC);
2295 
2296 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2297 }
2298 
2299 enum latency_range {
2300 	lowest_latency = 0,
2301 	low_latency = 1,
2302 	bulk_latency = 2,
2303 	latency_invalid = 255
2304 };
2305 
2306 /**
2307  * ixgbe_update_itr - update the dynamic ITR value based on statistics
2308  * @q_vector: structure containing interrupt and ring information
2309  * @ring_container: structure containing ring performance data
2310  *
2311  *      Stores a new ITR value based on packets and byte
2312  *      counts during the last interrupt.  The advantage of per interrupt
2313  *      computation is faster updates and more accurate ITR for the current
2314  *      traffic pattern.  Constants in this function were computed
2315  *      based on theoretical maximum wire speed and thresholds were set based
2316  *      on testing data as well as attempting to minimize response time
2317  *      while increasing bulk throughput.
2318  *      this functionality is controlled by the InterruptThrottleRate module
2319  *      parameter (see ixgbe_param.c)
2320  **/
2321 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2322 			     struct ixgbe_ring_container *ring_container)
2323 {
2324 	int bytes = ring_container->total_bytes;
2325 	int packets = ring_container->total_packets;
2326 	u32 timepassed_us;
2327 	u64 bytes_perint;
2328 	u8 itr_setting = ring_container->itr;
2329 
2330 	if (packets == 0)
2331 		return;
2332 
2333 	/* simple throttlerate management
2334 	 *   0-10MB/s   lowest (100000 ints/s)
2335 	 *  10-20MB/s   low    (20000 ints/s)
2336 	 *  20-1249MB/s bulk   (8000 ints/s)
2337 	 */
2338 	/* what was last interrupt timeslice? */
2339 	timepassed_us = q_vector->itr >> 2;
2340 	if (timepassed_us == 0)
2341 		return;
2342 
2343 	bytes_perint = bytes / timepassed_us; /* bytes/usec */
2344 
2345 	switch (itr_setting) {
2346 	case lowest_latency:
2347 		if (bytes_perint > 10)
2348 			itr_setting = low_latency;
2349 		break;
2350 	case low_latency:
2351 		if (bytes_perint > 20)
2352 			itr_setting = bulk_latency;
2353 		else if (bytes_perint <= 10)
2354 			itr_setting = lowest_latency;
2355 		break;
2356 	case bulk_latency:
2357 		if (bytes_perint <= 20)
2358 			itr_setting = low_latency;
2359 		break;
2360 	}
2361 
2362 	/* clear work counters since we have the values we need */
2363 	ring_container->total_bytes = 0;
2364 	ring_container->total_packets = 0;
2365 
2366 	/* write updated itr to ring container */
2367 	ring_container->itr = itr_setting;
2368 }
2369 
2370 /**
2371  * ixgbe_write_eitr - write EITR register in hardware specific way
2372  * @q_vector: structure containing interrupt and ring information
2373  *
2374  * This function is made to be called by ethtool and by the driver
2375  * when it needs to update EITR registers at runtime.  Hardware
2376  * specific quirks/differences are taken care of here.
2377  */
2378 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2379 {
2380 	struct ixgbe_adapter *adapter = q_vector->adapter;
2381 	struct ixgbe_hw *hw = &adapter->hw;
2382 	int v_idx = q_vector->v_idx;
2383 	u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2384 
2385 	switch (adapter->hw.mac.type) {
2386 	case ixgbe_mac_82598EB:
2387 		/* must write high and low 16 bits to reset counter */
2388 		itr_reg |= (itr_reg << 16);
2389 		break;
2390 	case ixgbe_mac_82599EB:
2391 	case ixgbe_mac_X540:
2392 		/*
2393 		 * set the WDIS bit to not clear the timer bits and cause an
2394 		 * immediate assertion of the interrupt
2395 		 */
2396 		itr_reg |= IXGBE_EITR_CNT_WDIS;
2397 		break;
2398 	default:
2399 		break;
2400 	}
2401 	IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2402 }
2403 
2404 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2405 {
2406 	u32 new_itr = q_vector->itr;
2407 	u8 current_itr;
2408 
2409 	ixgbe_update_itr(q_vector, &q_vector->tx);
2410 	ixgbe_update_itr(q_vector, &q_vector->rx);
2411 
2412 	current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2413 
2414 	switch (current_itr) {
2415 	/* counts and packets in update_itr are dependent on these numbers */
2416 	case lowest_latency:
2417 		new_itr = IXGBE_100K_ITR;
2418 		break;
2419 	case low_latency:
2420 		new_itr = IXGBE_20K_ITR;
2421 		break;
2422 	case bulk_latency:
2423 		new_itr = IXGBE_8K_ITR;
2424 		break;
2425 	default:
2426 		break;
2427 	}
2428 
2429 	if (new_itr != q_vector->itr) {
2430 		/* do an exponential smoothing */
2431 		new_itr = (10 * new_itr * q_vector->itr) /
2432 			  ((9 * new_itr) + q_vector->itr);
2433 
2434 		/* save the algorithm value here */
2435 		q_vector->itr = new_itr;
2436 
2437 		ixgbe_write_eitr(q_vector);
2438 	}
2439 }
2440 
2441 /**
2442  * ixgbe_check_overtemp_subtask - check for over temperature
2443  * @adapter: pointer to adapter
2444  **/
2445 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2446 {
2447 	struct ixgbe_hw *hw = &adapter->hw;
2448 	u32 eicr = adapter->interrupt_event;
2449 
2450 	if (test_bit(__IXGBE_DOWN, &adapter->state))
2451 		return;
2452 
2453 	if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2454 	    !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2455 		return;
2456 
2457 	adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2458 
2459 	switch (hw->device_id) {
2460 	case IXGBE_DEV_ID_82599_T3_LOM:
2461 		/*
2462 		 * Since the warning interrupt is for both ports
2463 		 * we don't have to check if:
2464 		 *  - This interrupt wasn't for our port.
2465 		 *  - We may have missed the interrupt so always have to
2466 		 *    check if we  got a LSC
2467 		 */
2468 		if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2469 		    !(eicr & IXGBE_EICR_LSC))
2470 			return;
2471 
2472 		if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2473 			u32 speed;
2474 			bool link_up = false;
2475 
2476 			hw->mac.ops.check_link(hw, &speed, &link_up, false);
2477 
2478 			if (link_up)
2479 				return;
2480 		}
2481 
2482 		/* Check if this is not due to overtemp */
2483 		if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2484 			return;
2485 
2486 		break;
2487 	default:
2488 		if (!(eicr & IXGBE_EICR_GPI_SDP0))
2489 			return;
2490 		break;
2491 	}
2492 	e_crit(drv,
2493 	       "Network adapter has been stopped because it has over heated. "
2494 	       "Restart the computer. If the problem persists, "
2495 	       "power off the system and replace the adapter\n");
2496 
2497 	adapter->interrupt_event = 0;
2498 }
2499 
2500 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2501 {
2502 	struct ixgbe_hw *hw = &adapter->hw;
2503 
2504 	if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2505 	    (eicr & IXGBE_EICR_GPI_SDP1)) {
2506 		e_crit(probe, "Fan has stopped, replace the adapter\n");
2507 		/* write to clear the interrupt */
2508 		IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2509 	}
2510 }
2511 
2512 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2513 {
2514 	if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2515 		return;
2516 
2517 	switch (adapter->hw.mac.type) {
2518 	case ixgbe_mac_82599EB:
2519 		/*
2520 		 * Need to check link state so complete overtemp check
2521 		 * on service task
2522 		 */
2523 		if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2524 		    (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2525 			adapter->interrupt_event = eicr;
2526 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2527 			ixgbe_service_event_schedule(adapter);
2528 			return;
2529 		}
2530 		return;
2531 	case ixgbe_mac_X540:
2532 		if (!(eicr & IXGBE_EICR_TS))
2533 			return;
2534 		break;
2535 	default:
2536 		return;
2537 	}
2538 
2539 	e_crit(drv,
2540 	       "Network adapter has been stopped because it has over heated. "
2541 	       "Restart the computer. If the problem persists, "
2542 	       "power off the system and replace the adapter\n");
2543 }
2544 
2545 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2546 {
2547 	struct ixgbe_hw *hw = &adapter->hw;
2548 
2549 	if (eicr & IXGBE_EICR_GPI_SDP2) {
2550 		/* Clear the interrupt */
2551 		IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2552 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2553 			adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2554 			ixgbe_service_event_schedule(adapter);
2555 		}
2556 	}
2557 
2558 	if (eicr & IXGBE_EICR_GPI_SDP1) {
2559 		/* Clear the interrupt */
2560 		IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2561 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2562 			adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2563 			ixgbe_service_event_schedule(adapter);
2564 		}
2565 	}
2566 }
2567 
2568 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2569 {
2570 	struct ixgbe_hw *hw = &adapter->hw;
2571 
2572 	adapter->lsc_int++;
2573 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2574 	adapter->link_check_timeout = jiffies;
2575 	if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2576 		IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2577 		IXGBE_WRITE_FLUSH(hw);
2578 		ixgbe_service_event_schedule(adapter);
2579 	}
2580 }
2581 
2582 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2583 					   u64 qmask)
2584 {
2585 	u32 mask;
2586 	struct ixgbe_hw *hw = &adapter->hw;
2587 
2588 	switch (hw->mac.type) {
2589 	case ixgbe_mac_82598EB:
2590 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2591 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2592 		break;
2593 	case ixgbe_mac_82599EB:
2594 	case ixgbe_mac_X540:
2595 		mask = (qmask & 0xFFFFFFFF);
2596 		if (mask)
2597 			IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2598 		mask = (qmask >> 32);
2599 		if (mask)
2600 			IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2601 		break;
2602 	default:
2603 		break;
2604 	}
2605 	/* skip the flush */
2606 }
2607 
2608 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2609 					    u64 qmask)
2610 {
2611 	u32 mask;
2612 	struct ixgbe_hw *hw = &adapter->hw;
2613 
2614 	switch (hw->mac.type) {
2615 	case ixgbe_mac_82598EB:
2616 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2617 		IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2618 		break;
2619 	case ixgbe_mac_82599EB:
2620 	case ixgbe_mac_X540:
2621 		mask = (qmask & 0xFFFFFFFF);
2622 		if (mask)
2623 			IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2624 		mask = (qmask >> 32);
2625 		if (mask)
2626 			IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2627 		break;
2628 	default:
2629 		break;
2630 	}
2631 	/* skip the flush */
2632 }
2633 
2634 /**
2635  * ixgbe_irq_enable - Enable default interrupt generation settings
2636  * @adapter: board private structure
2637  **/
2638 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2639 				    bool flush)
2640 {
2641 	u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2642 
2643 	/* don't reenable LSC while waiting for link */
2644 	if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2645 		mask &= ~IXGBE_EIMS_LSC;
2646 
2647 	if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2648 		switch (adapter->hw.mac.type) {
2649 		case ixgbe_mac_82599EB:
2650 			mask |= IXGBE_EIMS_GPI_SDP0;
2651 			break;
2652 		case ixgbe_mac_X540:
2653 			mask |= IXGBE_EIMS_TS;
2654 			break;
2655 		default:
2656 			break;
2657 		}
2658 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2659 		mask |= IXGBE_EIMS_GPI_SDP1;
2660 	switch (adapter->hw.mac.type) {
2661 	case ixgbe_mac_82599EB:
2662 		mask |= IXGBE_EIMS_GPI_SDP1;
2663 		mask |= IXGBE_EIMS_GPI_SDP2;
2664 	case ixgbe_mac_X540:
2665 		mask |= IXGBE_EIMS_ECC;
2666 		mask |= IXGBE_EIMS_MAILBOX;
2667 		break;
2668 	default:
2669 		break;
2670 	}
2671 
2672 	if (adapter->hw.mac.type == ixgbe_mac_X540)
2673 		mask |= IXGBE_EIMS_TIMESYNC;
2674 
2675 	if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2676 	    !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2677 		mask |= IXGBE_EIMS_FLOW_DIR;
2678 
2679 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2680 	if (queues)
2681 		ixgbe_irq_enable_queues(adapter, ~0);
2682 	if (flush)
2683 		IXGBE_WRITE_FLUSH(&adapter->hw);
2684 }
2685 
2686 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2687 {
2688 	struct ixgbe_adapter *adapter = data;
2689 	struct ixgbe_hw *hw = &adapter->hw;
2690 	u32 eicr;
2691 
2692 	/*
2693 	 * Workaround for Silicon errata.  Use clear-by-write instead
2694 	 * of clear-by-read.  Reading with EICS will return the
2695 	 * interrupt causes without clearing, which later be done
2696 	 * with the write to EICR.
2697 	 */
2698 	eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2699 
2700 	/* The lower 16bits of the EICR register are for the queue interrupts
2701 	 * which should be masked here in order to not accidently clear them if
2702 	 * the bits are high when ixgbe_msix_other is called. There is a race
2703 	 * condition otherwise which results in possible performance loss
2704 	 * especially if the ixgbe_msix_other interrupt is triggering
2705 	 * consistently (as it would when PPS is turned on for the X540 device)
2706 	 */
2707 	eicr &= 0xFFFF0000;
2708 
2709 	IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2710 
2711 	if (eicr & IXGBE_EICR_LSC)
2712 		ixgbe_check_lsc(adapter);
2713 
2714 	if (eicr & IXGBE_EICR_MAILBOX)
2715 		ixgbe_msg_task(adapter);
2716 
2717 	switch (hw->mac.type) {
2718 	case ixgbe_mac_82599EB:
2719 	case ixgbe_mac_X540:
2720 		if (eicr & IXGBE_EICR_ECC) {
2721 			e_info(link, "Received ECC Err, initiating reset\n");
2722 			adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2723 			ixgbe_service_event_schedule(adapter);
2724 			IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2725 		}
2726 		/* Handle Flow Director Full threshold interrupt */
2727 		if (eicr & IXGBE_EICR_FLOW_DIR) {
2728 			int reinit_count = 0;
2729 			int i;
2730 			for (i = 0; i < adapter->num_tx_queues; i++) {
2731 				struct ixgbe_ring *ring = adapter->tx_ring[i];
2732 				if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2733 						       &ring->state))
2734 					reinit_count++;
2735 			}
2736 			if (reinit_count) {
2737 				/* no more flow director interrupts until after init */
2738 				IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2739 				adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2740 				ixgbe_service_event_schedule(adapter);
2741 			}
2742 		}
2743 		ixgbe_check_sfp_event(adapter, eicr);
2744 		ixgbe_check_overtemp_event(adapter, eicr);
2745 		break;
2746 	default:
2747 		break;
2748 	}
2749 
2750 	ixgbe_check_fan_failure(adapter, eicr);
2751 
2752 	if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2753 		ixgbe_ptp_check_pps_event(adapter, eicr);
2754 
2755 	/* re-enable the original interrupt state, no lsc, no queues */
2756 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
2757 		ixgbe_irq_enable(adapter, false, false);
2758 
2759 	return IRQ_HANDLED;
2760 }
2761 
2762 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2763 {
2764 	struct ixgbe_q_vector *q_vector = data;
2765 
2766 	/* EIAM disabled interrupts (on this vector) for us */
2767 
2768 	if (q_vector->rx.ring || q_vector->tx.ring)
2769 		napi_schedule(&q_vector->napi);
2770 
2771 	return IRQ_HANDLED;
2772 }
2773 
2774 /**
2775  * ixgbe_poll - NAPI Rx polling callback
2776  * @napi: structure for representing this polling device
2777  * @budget: how many packets driver is allowed to clean
2778  *
2779  * This function is used for legacy and MSI, NAPI mode
2780  **/
2781 int ixgbe_poll(struct napi_struct *napi, int budget)
2782 {
2783 	struct ixgbe_q_vector *q_vector =
2784 				container_of(napi, struct ixgbe_q_vector, napi);
2785 	struct ixgbe_adapter *adapter = q_vector->adapter;
2786 	struct ixgbe_ring *ring;
2787 	int per_ring_budget;
2788 	bool clean_complete = true;
2789 
2790 #ifdef CONFIG_IXGBE_DCA
2791 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2792 		ixgbe_update_dca(q_vector);
2793 #endif
2794 
2795 	ixgbe_for_each_ring(ring, q_vector->tx)
2796 		clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2797 
2798 	if (!ixgbe_qv_lock_napi(q_vector))
2799 		return budget;
2800 
2801 	/* attempt to distribute budget to each queue fairly, but don't allow
2802 	 * the budget to go below 1 because we'll exit polling */
2803 	if (q_vector->rx.count > 1)
2804 		per_ring_budget = max(budget/q_vector->rx.count, 1);
2805 	else
2806 		per_ring_budget = budget;
2807 
2808 	ixgbe_for_each_ring(ring, q_vector->rx)
2809 		clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2810 				   per_ring_budget) < per_ring_budget);
2811 
2812 	ixgbe_qv_unlock_napi(q_vector);
2813 	/* If all work not completed, return budget and keep polling */
2814 	if (!clean_complete)
2815 		return budget;
2816 
2817 	/* all work done, exit the polling mode */
2818 	napi_complete(napi);
2819 	if (adapter->rx_itr_setting & 1)
2820 		ixgbe_set_itr(q_vector);
2821 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
2822 		ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2823 
2824 	return 0;
2825 }
2826 
2827 /**
2828  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2829  * @adapter: board private structure
2830  *
2831  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2832  * interrupts from the kernel.
2833  **/
2834 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2835 {
2836 	struct net_device *netdev = adapter->netdev;
2837 	int vector, err;
2838 	int ri = 0, ti = 0;
2839 
2840 	for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2841 		struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2842 		struct msix_entry *entry = &adapter->msix_entries[vector];
2843 
2844 		if (q_vector->tx.ring && q_vector->rx.ring) {
2845 			snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2846 				 "%s-%s-%d", netdev->name, "TxRx", ri++);
2847 			ti++;
2848 		} else if (q_vector->rx.ring) {
2849 			snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2850 				 "%s-%s-%d", netdev->name, "rx", ri++);
2851 		} else if (q_vector->tx.ring) {
2852 			snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2853 				 "%s-%s-%d", netdev->name, "tx", ti++);
2854 		} else {
2855 			/* skip this unused q_vector */
2856 			continue;
2857 		}
2858 		err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2859 				  q_vector->name, q_vector);
2860 		if (err) {
2861 			e_err(probe, "request_irq failed for MSIX interrupt "
2862 			      "Error: %d\n", err);
2863 			goto free_queue_irqs;
2864 		}
2865 		/* If Flow Director is enabled, set interrupt affinity */
2866 		if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2867 			/* assign the mask for this irq */
2868 			irq_set_affinity_hint(entry->vector,
2869 					      &q_vector->affinity_mask);
2870 		}
2871 	}
2872 
2873 	err = request_irq(adapter->msix_entries[vector].vector,
2874 			  ixgbe_msix_other, 0, netdev->name, adapter);
2875 	if (err) {
2876 		e_err(probe, "request_irq for msix_other failed: %d\n", err);
2877 		goto free_queue_irqs;
2878 	}
2879 
2880 	return 0;
2881 
2882 free_queue_irqs:
2883 	while (vector) {
2884 		vector--;
2885 		irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2886 				      NULL);
2887 		free_irq(adapter->msix_entries[vector].vector,
2888 			 adapter->q_vector[vector]);
2889 	}
2890 	adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2891 	pci_disable_msix(adapter->pdev);
2892 	kfree(adapter->msix_entries);
2893 	adapter->msix_entries = NULL;
2894 	return err;
2895 }
2896 
2897 /**
2898  * ixgbe_intr - legacy mode Interrupt Handler
2899  * @irq: interrupt number
2900  * @data: pointer to a network interface device structure
2901  **/
2902 static irqreturn_t ixgbe_intr(int irq, void *data)
2903 {
2904 	struct ixgbe_adapter *adapter = data;
2905 	struct ixgbe_hw *hw = &adapter->hw;
2906 	struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2907 	u32 eicr;
2908 
2909 	/*
2910 	 * Workaround for silicon errata #26 on 82598.  Mask the interrupt
2911 	 * before the read of EICR.
2912 	 */
2913 	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2914 
2915 	/* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2916 	 * therefore no explicit interrupt disable is necessary */
2917 	eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2918 	if (!eicr) {
2919 		/*
2920 		 * shared interrupt alert!
2921 		 * make sure interrupts are enabled because the read will
2922 		 * have disabled interrupts due to EIAM
2923 		 * finish the workaround of silicon errata on 82598.  Unmask
2924 		 * the interrupt that we masked before the EICR read.
2925 		 */
2926 		if (!test_bit(__IXGBE_DOWN, &adapter->state))
2927 			ixgbe_irq_enable(adapter, true, true);
2928 		return IRQ_NONE;	/* Not our interrupt */
2929 	}
2930 
2931 	if (eicr & IXGBE_EICR_LSC)
2932 		ixgbe_check_lsc(adapter);
2933 
2934 	switch (hw->mac.type) {
2935 	case ixgbe_mac_82599EB:
2936 		ixgbe_check_sfp_event(adapter, eicr);
2937 		/* Fall through */
2938 	case ixgbe_mac_X540:
2939 		if (eicr & IXGBE_EICR_ECC) {
2940 			e_info(link, "Received ECC Err, initiating reset\n");
2941 			adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2942 			ixgbe_service_event_schedule(adapter);
2943 			IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2944 		}
2945 		ixgbe_check_overtemp_event(adapter, eicr);
2946 		break;
2947 	default:
2948 		break;
2949 	}
2950 
2951 	ixgbe_check_fan_failure(adapter, eicr);
2952 	if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2953 		ixgbe_ptp_check_pps_event(adapter, eicr);
2954 
2955 	/* would disable interrupts here but EIAM disabled it */
2956 	napi_schedule(&q_vector->napi);
2957 
2958 	/*
2959 	 * re-enable link(maybe) and non-queue interrupts, no flush.
2960 	 * ixgbe_poll will re-enable the queue interrupts
2961 	 */
2962 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
2963 		ixgbe_irq_enable(adapter, false, false);
2964 
2965 	return IRQ_HANDLED;
2966 }
2967 
2968 /**
2969  * ixgbe_request_irq - initialize interrupts
2970  * @adapter: board private structure
2971  *
2972  * Attempts to configure interrupts using the best available
2973  * capabilities of the hardware and kernel.
2974  **/
2975 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2976 {
2977 	struct net_device *netdev = adapter->netdev;
2978 	int err;
2979 
2980 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2981 		err = ixgbe_request_msix_irqs(adapter);
2982 	else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2983 		err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2984 				  netdev->name, adapter);
2985 	else
2986 		err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2987 				  netdev->name, adapter);
2988 
2989 	if (err)
2990 		e_err(probe, "request_irq failed, Error %d\n", err);
2991 
2992 	return err;
2993 }
2994 
2995 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2996 {
2997 	int vector;
2998 
2999 	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3000 		free_irq(adapter->pdev->irq, adapter);
3001 		return;
3002 	}
3003 
3004 	for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3005 		struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3006 		struct msix_entry *entry = &adapter->msix_entries[vector];
3007 
3008 		/* free only the irqs that were actually requested */
3009 		if (!q_vector->rx.ring && !q_vector->tx.ring)
3010 			continue;
3011 
3012 		/* clear the affinity_mask in the IRQ descriptor */
3013 		irq_set_affinity_hint(entry->vector, NULL);
3014 
3015 		free_irq(entry->vector, q_vector);
3016 	}
3017 
3018 	free_irq(adapter->msix_entries[vector++].vector, adapter);
3019 }
3020 
3021 /**
3022  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3023  * @adapter: board private structure
3024  **/
3025 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3026 {
3027 	switch (adapter->hw.mac.type) {
3028 	case ixgbe_mac_82598EB:
3029 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3030 		break;
3031 	case ixgbe_mac_82599EB:
3032 	case ixgbe_mac_X540:
3033 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3034 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3035 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3036 		break;
3037 	default:
3038 		break;
3039 	}
3040 	IXGBE_WRITE_FLUSH(&adapter->hw);
3041 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3042 		int vector;
3043 
3044 		for (vector = 0; vector < adapter->num_q_vectors; vector++)
3045 			synchronize_irq(adapter->msix_entries[vector].vector);
3046 
3047 		synchronize_irq(adapter->msix_entries[vector++].vector);
3048 	} else {
3049 		synchronize_irq(adapter->pdev->irq);
3050 	}
3051 }
3052 
3053 /**
3054  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3055  *
3056  **/
3057 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3058 {
3059 	struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3060 
3061 	ixgbe_write_eitr(q_vector);
3062 
3063 	ixgbe_set_ivar(adapter, 0, 0, 0);
3064 	ixgbe_set_ivar(adapter, 1, 0, 0);
3065 
3066 	e_info(hw, "Legacy interrupt IVAR setup done\n");
3067 }
3068 
3069 /**
3070  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3071  * @adapter: board private structure
3072  * @ring: structure containing ring specific data
3073  *
3074  * Configure the Tx descriptor ring after a reset.
3075  **/
3076 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3077 			     struct ixgbe_ring *ring)
3078 {
3079 	struct ixgbe_hw *hw = &adapter->hw;
3080 	u64 tdba = ring->dma;
3081 	int wait_loop = 10;
3082 	u32 txdctl = IXGBE_TXDCTL_ENABLE;
3083 	u8 reg_idx = ring->reg_idx;
3084 
3085 	/* disable queue to avoid issues while updating state */
3086 	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3087 	IXGBE_WRITE_FLUSH(hw);
3088 
3089 	IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3090 			(tdba & DMA_BIT_MASK(32)));
3091 	IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3092 	IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3093 			ring->count * sizeof(union ixgbe_adv_tx_desc));
3094 	IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3095 	IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3096 	ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3097 
3098 	/*
3099 	 * set WTHRESH to encourage burst writeback, it should not be set
3100 	 * higher than 1 when:
3101 	 * - ITR is 0 as it could cause false TX hangs
3102 	 * - ITR is set to > 100k int/sec and BQL is enabled
3103 	 *
3104 	 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3105 	 * to or less than the number of on chip descriptors, which is
3106 	 * currently 40.
3107 	 */
3108 #if IS_ENABLED(CONFIG_BQL)
3109 	if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3110 #else
3111 	if (!ring->q_vector || (ring->q_vector->itr < 8))
3112 #endif
3113 		txdctl |= (1 << 16);	/* WTHRESH = 1 */
3114 	else
3115 		txdctl |= (8 << 16);	/* WTHRESH = 8 */
3116 
3117 	/*
3118 	 * Setting PTHRESH to 32 both improves performance
3119 	 * and avoids a TX hang with DFP enabled
3120 	 */
3121 	txdctl |= (1 << 8) |	/* HTHRESH = 1 */
3122 		   32;		/* PTHRESH = 32 */
3123 
3124 	/* reinitialize flowdirector state */
3125 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3126 		ring->atr_sample_rate = adapter->atr_sample_rate;
3127 		ring->atr_count = 0;
3128 		set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3129 	} else {
3130 		ring->atr_sample_rate = 0;
3131 	}
3132 
3133 	/* initialize XPS */
3134 	if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3135 		struct ixgbe_q_vector *q_vector = ring->q_vector;
3136 
3137 		if (q_vector)
3138 			netif_set_xps_queue(ring->netdev,
3139 					    &q_vector->affinity_mask,
3140 					    ring->queue_index);
3141 	}
3142 
3143 	clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3144 
3145 	/* enable queue */
3146 	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3147 
3148 	/* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3149 	if (hw->mac.type == ixgbe_mac_82598EB &&
3150 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3151 		return;
3152 
3153 	/* poll to verify queue is enabled */
3154 	do {
3155 		usleep_range(1000, 2000);
3156 		txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3157 	} while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3158 	if (!wait_loop)
3159 		e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3160 }
3161 
3162 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3163 {
3164 	struct ixgbe_hw *hw = &adapter->hw;
3165 	u32 rttdcs, mtqc;
3166 	u8 tcs = netdev_get_num_tc(adapter->netdev);
3167 
3168 	if (hw->mac.type == ixgbe_mac_82598EB)
3169 		return;
3170 
3171 	/* disable the arbiter while setting MTQC */
3172 	rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3173 	rttdcs |= IXGBE_RTTDCS_ARBDIS;
3174 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3175 
3176 	/* set transmit pool layout */
3177 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3178 		mtqc = IXGBE_MTQC_VT_ENA;
3179 		if (tcs > 4)
3180 			mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3181 		else if (tcs > 1)
3182 			mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3183 		else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3184 			mtqc |= IXGBE_MTQC_32VF;
3185 		else
3186 			mtqc |= IXGBE_MTQC_64VF;
3187 	} else {
3188 		if (tcs > 4)
3189 			mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3190 		else if (tcs > 1)
3191 			mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3192 		else
3193 			mtqc = IXGBE_MTQC_64Q_1PB;
3194 	}
3195 
3196 	IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3197 
3198 	/* Enable Security TX Buffer IFG for multiple pb */
3199 	if (tcs) {
3200 		u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3201 		sectx |= IXGBE_SECTX_DCB;
3202 		IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3203 	}
3204 
3205 	/* re-enable the arbiter */
3206 	rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3207 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3208 }
3209 
3210 /**
3211  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3212  * @adapter: board private structure
3213  *
3214  * Configure the Tx unit of the MAC after a reset.
3215  **/
3216 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3217 {
3218 	struct ixgbe_hw *hw = &adapter->hw;
3219 	u32 dmatxctl;
3220 	u32 i;
3221 
3222 	ixgbe_setup_mtqc(adapter);
3223 
3224 	if (hw->mac.type != ixgbe_mac_82598EB) {
3225 		/* DMATXCTL.EN must be before Tx queues are enabled */
3226 		dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3227 		dmatxctl |= IXGBE_DMATXCTL_TE;
3228 		IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3229 	}
3230 
3231 	/* Setup the HW Tx Head and Tail descriptor pointers */
3232 	for (i = 0; i < adapter->num_tx_queues; i++)
3233 		ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3234 }
3235 
3236 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3237 				 struct ixgbe_ring *ring)
3238 {
3239 	struct ixgbe_hw *hw = &adapter->hw;
3240 	u8 reg_idx = ring->reg_idx;
3241 	u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3242 
3243 	srrctl |= IXGBE_SRRCTL_DROP_EN;
3244 
3245 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3246 }
3247 
3248 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3249 				  struct ixgbe_ring *ring)
3250 {
3251 	struct ixgbe_hw *hw = &adapter->hw;
3252 	u8 reg_idx = ring->reg_idx;
3253 	u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3254 
3255 	srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3256 
3257 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3258 }
3259 
3260 #ifdef CONFIG_IXGBE_DCB
3261 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3262 #else
3263 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3264 #endif
3265 {
3266 	int i;
3267 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3268 
3269 	if (adapter->ixgbe_ieee_pfc)
3270 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3271 
3272 	/*
3273 	 * We should set the drop enable bit if:
3274 	 *  SR-IOV is enabled
3275 	 *   or
3276 	 *  Number of Rx queues > 1 and flow control is disabled
3277 	 *
3278 	 *  This allows us to avoid head of line blocking for security
3279 	 *  and performance reasons.
3280 	 */
3281 	if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3282 	    !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3283 		for (i = 0; i < adapter->num_rx_queues; i++)
3284 			ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3285 	} else {
3286 		for (i = 0; i < adapter->num_rx_queues; i++)
3287 			ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3288 	}
3289 }
3290 
3291 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3292 
3293 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3294 				   struct ixgbe_ring *rx_ring)
3295 {
3296 	struct ixgbe_hw *hw = &adapter->hw;
3297 	u32 srrctl;
3298 	u8 reg_idx = rx_ring->reg_idx;
3299 
3300 	if (hw->mac.type == ixgbe_mac_82598EB) {
3301 		u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3302 
3303 		/*
3304 		 * if VMDq is not active we must program one srrctl register
3305 		 * per RSS queue since we have enabled RDRXCTL.MVMEN
3306 		 */
3307 		reg_idx &= mask;
3308 	}
3309 
3310 	/* configure header buffer length, needed for RSC */
3311 	srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3312 
3313 	/* configure the packet buffer length */
3314 	srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3315 
3316 	/* configure descriptor type */
3317 	srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3318 
3319 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3320 }
3321 
3322 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3323 {
3324 	struct ixgbe_hw *hw = &adapter->hw;
3325 	static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
3326 			  0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3327 			  0x6A3E67EA, 0x14364D17, 0x3BED200D};
3328 	u32 mrqc = 0, reta = 0;
3329 	u32 rxcsum;
3330 	int i, j;
3331 	u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3332 
3333 	/*
3334 	 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3335 	 * make full use of any rings they may have.  We will use the
3336 	 * PSRTYPE register to control how many rings we use within the PF.
3337 	 */
3338 	if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3339 		rss_i = 2;
3340 
3341 	/* Fill out hash function seeds */
3342 	for (i = 0; i < 10; i++)
3343 		IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3344 
3345 	/* Fill out redirection table */
3346 	for (i = 0, j = 0; i < 128; i++, j++) {
3347 		if (j == rss_i)
3348 			j = 0;
3349 		/* reta = 4-byte sliding window of
3350 		 * 0x00..(indices-1)(indices-1)00..etc. */
3351 		reta = (reta << 8) | (j * 0x11);
3352 		if ((i & 3) == 3)
3353 			IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3354 	}
3355 
3356 	/* Disable indicating checksum in descriptor, enables RSS hash */
3357 	rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3358 	rxcsum |= IXGBE_RXCSUM_PCSD;
3359 	IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3360 
3361 	if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3362 		if (adapter->ring_feature[RING_F_RSS].mask)
3363 			mrqc = IXGBE_MRQC_RSSEN;
3364 	} else {
3365 		u8 tcs = netdev_get_num_tc(adapter->netdev);
3366 
3367 		if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3368 			if (tcs > 4)
3369 				mrqc = IXGBE_MRQC_VMDQRT8TCEN;	/* 8 TCs */
3370 			else if (tcs > 1)
3371 				mrqc = IXGBE_MRQC_VMDQRT4TCEN;	/* 4 TCs */
3372 			else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3373 				mrqc = IXGBE_MRQC_VMDQRSS32EN;
3374 			else
3375 				mrqc = IXGBE_MRQC_VMDQRSS64EN;
3376 		} else {
3377 			if (tcs > 4)
3378 				mrqc = IXGBE_MRQC_RTRSS8TCEN;
3379 			else if (tcs > 1)
3380 				mrqc = IXGBE_MRQC_RTRSS4TCEN;
3381 			else
3382 				mrqc = IXGBE_MRQC_RSSEN;
3383 		}
3384 	}
3385 
3386 	/* Perform hash on these packet types */
3387 	mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3388 		IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3389 		IXGBE_MRQC_RSS_FIELD_IPV6 |
3390 		IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3391 
3392 	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3393 		mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3394 	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3395 		mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3396 
3397 	IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3398 }
3399 
3400 /**
3401  * ixgbe_configure_rscctl - enable RSC for the indicated ring
3402  * @adapter:    address of board private structure
3403  * @index:      index of ring to set
3404  **/
3405 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3406 				   struct ixgbe_ring *ring)
3407 {
3408 	struct ixgbe_hw *hw = &adapter->hw;
3409 	u32 rscctrl;
3410 	u8 reg_idx = ring->reg_idx;
3411 
3412 	if (!ring_is_rsc_enabled(ring))
3413 		return;
3414 
3415 	rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3416 	rscctrl |= IXGBE_RSCCTL_RSCEN;
3417 	/*
3418 	 * we must limit the number of descriptors so that the
3419 	 * total size of max desc * buf_len is not greater
3420 	 * than 65536
3421 	 */
3422 	rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3423 	IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3424 }
3425 
3426 #define IXGBE_MAX_RX_DESC_POLL 10
3427 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3428 				       struct ixgbe_ring *ring)
3429 {
3430 	struct ixgbe_hw *hw = &adapter->hw;
3431 	int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3432 	u32 rxdctl;
3433 	u8 reg_idx = ring->reg_idx;
3434 
3435 	if (ixgbe_removed(hw->hw_addr))
3436 		return;
3437 	/* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3438 	if (hw->mac.type == ixgbe_mac_82598EB &&
3439 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3440 		return;
3441 
3442 	do {
3443 		usleep_range(1000, 2000);
3444 		rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3445 	} while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3446 
3447 	if (!wait_loop) {
3448 		e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3449 		      "the polling period\n", reg_idx);
3450 	}
3451 }
3452 
3453 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3454 			    struct ixgbe_ring *ring)
3455 {
3456 	struct ixgbe_hw *hw = &adapter->hw;
3457 	int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3458 	u32 rxdctl;
3459 	u8 reg_idx = ring->reg_idx;
3460 
3461 	if (ixgbe_removed(hw->hw_addr))
3462 		return;
3463 	rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3464 	rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3465 
3466 	/* write value back with RXDCTL.ENABLE bit cleared */
3467 	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3468 
3469 	if (hw->mac.type == ixgbe_mac_82598EB &&
3470 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3471 		return;
3472 
3473 	/* the hardware may take up to 100us to really disable the rx queue */
3474 	do {
3475 		udelay(10);
3476 		rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3477 	} while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3478 
3479 	if (!wait_loop) {
3480 		e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3481 		      "the polling period\n", reg_idx);
3482 	}
3483 }
3484 
3485 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3486 			     struct ixgbe_ring *ring)
3487 {
3488 	struct ixgbe_hw *hw = &adapter->hw;
3489 	u64 rdba = ring->dma;
3490 	u32 rxdctl;
3491 	u8 reg_idx = ring->reg_idx;
3492 
3493 	/* disable queue to avoid issues while updating state */
3494 	rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3495 	ixgbe_disable_rx_queue(adapter, ring);
3496 
3497 	IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3498 	IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3499 	IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3500 			ring->count * sizeof(union ixgbe_adv_rx_desc));
3501 	IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3502 	IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3503 	ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3504 
3505 	ixgbe_configure_srrctl(adapter, ring);
3506 	ixgbe_configure_rscctl(adapter, ring);
3507 
3508 	if (hw->mac.type == ixgbe_mac_82598EB) {
3509 		/*
3510 		 * enable cache line friendly hardware writes:
3511 		 * PTHRESH=32 descriptors (half the internal cache),
3512 		 * this also removes ugly rx_no_buffer_count increment
3513 		 * HTHRESH=4 descriptors (to minimize latency on fetch)
3514 		 * WTHRESH=8 burst writeback up to two cache lines
3515 		 */
3516 		rxdctl &= ~0x3FFFFF;
3517 		rxdctl |=  0x080420;
3518 	}
3519 
3520 	/* enable receive descriptor ring */
3521 	rxdctl |= IXGBE_RXDCTL_ENABLE;
3522 	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3523 
3524 	ixgbe_rx_desc_queue_enable(adapter, ring);
3525 	ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3526 }
3527 
3528 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3529 {
3530 	struct ixgbe_hw *hw = &adapter->hw;
3531 	int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3532 	u16 pool;
3533 
3534 	/* PSRTYPE must be initialized in non 82598 adapters */
3535 	u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3536 		      IXGBE_PSRTYPE_UDPHDR |
3537 		      IXGBE_PSRTYPE_IPV4HDR |
3538 		      IXGBE_PSRTYPE_L2HDR |
3539 		      IXGBE_PSRTYPE_IPV6HDR;
3540 
3541 	if (hw->mac.type == ixgbe_mac_82598EB)
3542 		return;
3543 
3544 	if (rss_i > 3)
3545 		psrtype |= 2 << 29;
3546 	else if (rss_i > 1)
3547 		psrtype |= 1 << 29;
3548 
3549 	for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3550 		IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3551 }
3552 
3553 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3554 {
3555 	struct ixgbe_hw *hw = &adapter->hw;
3556 	u32 reg_offset, vf_shift;
3557 	u32 gcr_ext, vmdctl;
3558 	int i;
3559 
3560 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3561 		return;
3562 
3563 	vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3564 	vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3565 	vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3566 	vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3567 	vmdctl |= IXGBE_VT_CTL_REPLEN;
3568 	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3569 
3570 	vf_shift = VMDQ_P(0) % 32;
3571 	reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3572 
3573 	/* Enable only the PF's pool for Tx/Rx */
3574 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3575 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3576 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3577 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3578 	if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3579 		IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3580 
3581 	/* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3582 	hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3583 
3584 	/*
3585 	 * Set up VF register offsets for selected VT Mode,
3586 	 * i.e. 32 or 64 VFs for SR-IOV
3587 	 */
3588 	switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3589 	case IXGBE_82599_VMDQ_8Q_MASK:
3590 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3591 		break;
3592 	case IXGBE_82599_VMDQ_4Q_MASK:
3593 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3594 		break;
3595 	default:
3596 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3597 		break;
3598 	}
3599 
3600 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3601 
3602 
3603 	/* Enable MAC Anti-Spoofing */
3604 	hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3605 					  adapter->num_vfs);
3606 	/* For VFs that have spoof checking turned off */
3607 	for (i = 0; i < adapter->num_vfs; i++) {
3608 		if (!adapter->vfinfo[i].spoofchk_enabled)
3609 			ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3610 	}
3611 }
3612 
3613 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3614 {
3615 	struct ixgbe_hw *hw = &adapter->hw;
3616 	struct net_device *netdev = adapter->netdev;
3617 	int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3618 	struct ixgbe_ring *rx_ring;
3619 	int i;
3620 	u32 mhadd, hlreg0;
3621 
3622 #ifdef IXGBE_FCOE
3623 	/* adjust max frame to be able to do baby jumbo for FCoE */
3624 	if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3625 	    (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3626 		max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3627 
3628 #endif /* IXGBE_FCOE */
3629 
3630 	/* adjust max frame to be at least the size of a standard frame */
3631 	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3632 		max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3633 
3634 	mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3635 	if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3636 		mhadd &= ~IXGBE_MHADD_MFS_MASK;
3637 		mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3638 
3639 		IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3640 	}
3641 
3642 	hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3643 	/* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3644 	hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3645 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3646 
3647 	/*
3648 	 * Setup the HW Rx Head and Tail Descriptor Pointers and
3649 	 * the Base and Length of the Rx Descriptor Ring
3650 	 */
3651 	for (i = 0; i < adapter->num_rx_queues; i++) {
3652 		rx_ring = adapter->rx_ring[i];
3653 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3654 			set_ring_rsc_enabled(rx_ring);
3655 		else
3656 			clear_ring_rsc_enabled(rx_ring);
3657 	}
3658 }
3659 
3660 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3661 {
3662 	struct ixgbe_hw *hw = &adapter->hw;
3663 	u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3664 
3665 	switch (hw->mac.type) {
3666 	case ixgbe_mac_82598EB:
3667 		/*
3668 		 * For VMDq support of different descriptor types or
3669 		 * buffer sizes through the use of multiple SRRCTL
3670 		 * registers, RDRXCTL.MVMEN must be set to 1
3671 		 *
3672 		 * also, the manual doesn't mention it clearly but DCA hints
3673 		 * will only use queue 0's tags unless this bit is set.  Side
3674 		 * effects of setting this bit are only that SRRCTL must be
3675 		 * fully programmed [0..15]
3676 		 */
3677 		rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3678 		break;
3679 	case ixgbe_mac_82599EB:
3680 	case ixgbe_mac_X540:
3681 		/* Disable RSC for ACK packets */
3682 		IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3683 		   (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3684 		rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3685 		/* hardware requires some bits to be set by default */
3686 		rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3687 		rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3688 		break;
3689 	default:
3690 		/* We should do nothing since we don't know this hardware */
3691 		return;
3692 	}
3693 
3694 	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3695 }
3696 
3697 /**
3698  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3699  * @adapter: board private structure
3700  *
3701  * Configure the Rx unit of the MAC after a reset.
3702  **/
3703 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3704 {
3705 	struct ixgbe_hw *hw = &adapter->hw;
3706 	int i;
3707 	u32 rxctrl, rfctl;
3708 
3709 	/* disable receives while setting up the descriptors */
3710 	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3711 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3712 
3713 	ixgbe_setup_psrtype(adapter);
3714 	ixgbe_setup_rdrxctl(adapter);
3715 
3716 	/* RSC Setup */
3717 	rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3718 	rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3719 	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3720 		rfctl |= IXGBE_RFCTL_RSC_DIS;
3721 	IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3722 
3723 	/* Program registers for the distribution of queues */
3724 	ixgbe_setup_mrqc(adapter);
3725 
3726 	/* set_rx_buffer_len must be called before ring initialization */
3727 	ixgbe_set_rx_buffer_len(adapter);
3728 
3729 	/*
3730 	 * Setup the HW Rx Head and Tail Descriptor Pointers and
3731 	 * the Base and Length of the Rx Descriptor Ring
3732 	 */
3733 	for (i = 0; i < adapter->num_rx_queues; i++)
3734 		ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3735 
3736 	/* disable drop enable for 82598 parts */
3737 	if (hw->mac.type == ixgbe_mac_82598EB)
3738 		rxctrl |= IXGBE_RXCTRL_DMBYPS;
3739 
3740 	/* enable all receives */
3741 	rxctrl |= IXGBE_RXCTRL_RXEN;
3742 	hw->mac.ops.enable_rx_dma(hw, rxctrl);
3743 }
3744 
3745 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3746 				 __be16 proto, u16 vid)
3747 {
3748 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3749 	struct ixgbe_hw *hw = &adapter->hw;
3750 
3751 	/* add VID to filter table */
3752 	hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3753 	set_bit(vid, adapter->active_vlans);
3754 
3755 	return 0;
3756 }
3757 
3758 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3759 				  __be16 proto, u16 vid)
3760 {
3761 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3762 	struct ixgbe_hw *hw = &adapter->hw;
3763 
3764 	/* remove VID from filter table */
3765 	hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3766 	clear_bit(vid, adapter->active_vlans);
3767 
3768 	return 0;
3769 }
3770 
3771 /**
3772  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3773  * @adapter: driver data
3774  */
3775 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3776 {
3777 	struct ixgbe_hw *hw = &adapter->hw;
3778 	u32 vlnctrl;
3779 	int i, j;
3780 
3781 	switch (hw->mac.type) {
3782 	case ixgbe_mac_82598EB:
3783 		vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3784 		vlnctrl &= ~IXGBE_VLNCTRL_VME;
3785 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3786 		break;
3787 	case ixgbe_mac_82599EB:
3788 	case ixgbe_mac_X540:
3789 		for (i = 0; i < adapter->num_rx_queues; i++) {
3790 			struct ixgbe_ring *ring = adapter->rx_ring[i];
3791 
3792 			if (ring->l2_accel_priv)
3793 				continue;
3794 			j = ring->reg_idx;
3795 			vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3796 			vlnctrl &= ~IXGBE_RXDCTL_VME;
3797 			IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3798 		}
3799 		break;
3800 	default:
3801 		break;
3802 	}
3803 }
3804 
3805 /**
3806  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3807  * @adapter: driver data
3808  */
3809 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3810 {
3811 	struct ixgbe_hw *hw = &adapter->hw;
3812 	u32 vlnctrl;
3813 	int i, j;
3814 
3815 	switch (hw->mac.type) {
3816 	case ixgbe_mac_82598EB:
3817 		vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3818 		vlnctrl |= IXGBE_VLNCTRL_VME;
3819 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3820 		break;
3821 	case ixgbe_mac_82599EB:
3822 	case ixgbe_mac_X540:
3823 		for (i = 0; i < adapter->num_rx_queues; i++) {
3824 			struct ixgbe_ring *ring = adapter->rx_ring[i];
3825 
3826 			if (ring->l2_accel_priv)
3827 				continue;
3828 			j = ring->reg_idx;
3829 			vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3830 			vlnctrl |= IXGBE_RXDCTL_VME;
3831 			IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3832 		}
3833 		break;
3834 	default:
3835 		break;
3836 	}
3837 }
3838 
3839 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3840 {
3841 	u16 vid;
3842 
3843 	ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3844 
3845 	for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3846 		ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
3847 }
3848 
3849 /**
3850  * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3851  * @netdev: network interface device structure
3852  *
3853  * Writes multicast address list to the MTA hash table.
3854  * Returns: -ENOMEM on failure
3855  *                0 on no addresses written
3856  *                X on writing X addresses to MTA
3857  **/
3858 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3859 {
3860 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3861 	struct ixgbe_hw *hw = &adapter->hw;
3862 
3863 	if (!netif_running(netdev))
3864 		return 0;
3865 
3866 	if (hw->mac.ops.update_mc_addr_list)
3867 		hw->mac.ops.update_mc_addr_list(hw, netdev);
3868 	else
3869 		return -ENOMEM;
3870 
3871 #ifdef CONFIG_PCI_IOV
3872 	ixgbe_restore_vf_multicasts(adapter);
3873 #endif
3874 
3875 	return netdev_mc_count(netdev);
3876 }
3877 
3878 #ifdef CONFIG_PCI_IOV
3879 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3880 {
3881 	struct ixgbe_hw *hw = &adapter->hw;
3882 	int i;
3883 	for (i = 0; i < hw->mac.num_rar_entries; i++) {
3884 		if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3885 			hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3886 					    adapter->mac_table[i].queue,
3887 					    IXGBE_RAH_AV);
3888 		else
3889 			hw->mac.ops.clear_rar(hw, i);
3890 
3891 		adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3892 	}
3893 }
3894 #endif
3895 
3896 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3897 {
3898 	struct ixgbe_hw *hw = &adapter->hw;
3899 	int i;
3900 	for (i = 0; i < hw->mac.num_rar_entries; i++) {
3901 		if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3902 			if (adapter->mac_table[i].state &
3903 			    IXGBE_MAC_STATE_IN_USE)
3904 				hw->mac.ops.set_rar(hw, i,
3905 						adapter->mac_table[i].addr,
3906 						adapter->mac_table[i].queue,
3907 						IXGBE_RAH_AV);
3908 			else
3909 				hw->mac.ops.clear_rar(hw, i);
3910 
3911 			adapter->mac_table[i].state &=
3912 						~(IXGBE_MAC_STATE_MODIFIED);
3913 		}
3914 	}
3915 }
3916 
3917 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3918 {
3919 	int i;
3920 	struct ixgbe_hw *hw = &adapter->hw;
3921 
3922 	for (i = 0; i < hw->mac.num_rar_entries; i++) {
3923 		adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3924 		adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3925 		memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3926 		adapter->mac_table[i].queue = 0;
3927 	}
3928 	ixgbe_sync_mac_table(adapter);
3929 }
3930 
3931 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3932 {
3933 	struct ixgbe_hw *hw = &adapter->hw;
3934 	int i, count = 0;
3935 
3936 	for (i = 0; i < hw->mac.num_rar_entries; i++) {
3937 		if (adapter->mac_table[i].state == 0)
3938 			count++;
3939 	}
3940 	return count;
3941 }
3942 
3943 /* this function destroys the first RAR entry */
3944 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3945 					 u8 *addr)
3946 {
3947 	struct ixgbe_hw *hw = &adapter->hw;
3948 
3949 	memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3950 	adapter->mac_table[0].queue = VMDQ_P(0);
3951 	adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3952 				       IXGBE_MAC_STATE_IN_USE);
3953 	hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3954 			    adapter->mac_table[0].queue,
3955 			    IXGBE_RAH_AV);
3956 }
3957 
3958 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3959 {
3960 	struct ixgbe_hw *hw = &adapter->hw;
3961 	int i;
3962 
3963 	if (is_zero_ether_addr(addr))
3964 		return -EINVAL;
3965 
3966 	for (i = 0; i < hw->mac.num_rar_entries; i++) {
3967 		if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3968 			continue;
3969 		adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3970 						IXGBE_MAC_STATE_IN_USE);
3971 		ether_addr_copy(adapter->mac_table[i].addr, addr);
3972 		adapter->mac_table[i].queue = queue;
3973 		ixgbe_sync_mac_table(adapter);
3974 		return i;
3975 	}
3976 	return -ENOMEM;
3977 }
3978 
3979 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3980 {
3981 	/* search table for addr, if found, set to 0 and sync */
3982 	int i;
3983 	struct ixgbe_hw *hw = &adapter->hw;
3984 
3985 	if (is_zero_ether_addr(addr))
3986 		return -EINVAL;
3987 
3988 	for (i = 0; i < hw->mac.num_rar_entries; i++) {
3989 		if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3990 		    adapter->mac_table[i].queue == queue) {
3991 			adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3992 			adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3993 			memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3994 			adapter->mac_table[i].queue = 0;
3995 			ixgbe_sync_mac_table(adapter);
3996 			return 0;
3997 		}
3998 	}
3999 	return -ENOMEM;
4000 }
4001 /**
4002  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4003  * @netdev: network interface device structure
4004  *
4005  * Writes unicast address list to the RAR table.
4006  * Returns: -ENOMEM on failure/insufficient address space
4007  *                0 on no addresses written
4008  *                X on writing X addresses to the RAR table
4009  **/
4010 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4011 {
4012 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4013 	int count = 0;
4014 
4015 	/* return ENOMEM indicating insufficient memory for addresses */
4016 	if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
4017 		return -ENOMEM;
4018 
4019 	if (!netdev_uc_empty(netdev)) {
4020 		struct netdev_hw_addr *ha;
4021 		netdev_for_each_uc_addr(ha, netdev) {
4022 			ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4023 			ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4024 			count++;
4025 		}
4026 	}
4027 	return count;
4028 }
4029 
4030 /**
4031  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4032  * @netdev: network interface device structure
4033  *
4034  * The set_rx_method entry point is called whenever the unicast/multicast
4035  * address list or the network interface flags are updated.  This routine is
4036  * responsible for configuring the hardware for proper unicast, multicast and
4037  * promiscuous mode.
4038  **/
4039 void ixgbe_set_rx_mode(struct net_device *netdev)
4040 {
4041 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4042 	struct ixgbe_hw *hw = &adapter->hw;
4043 	u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4044 	u32 vlnctrl;
4045 	int count;
4046 
4047 	/* Check for Promiscuous and All Multicast modes */
4048 	fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4049 	vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4050 
4051 	/* set all bits that we expect to always be set */
4052 	fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4053 	fctrl |= IXGBE_FCTRL_BAM;
4054 	fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4055 	fctrl |= IXGBE_FCTRL_PMCF;
4056 
4057 	/* clear the bits we are changing the status of */
4058 	fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4059 	vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4060 	if (netdev->flags & IFF_PROMISC) {
4061 		hw->addr_ctrl.user_set_promisc = true;
4062 		fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4063 		vmolr |= IXGBE_VMOLR_MPE;
4064 		/* Only disable hardware filter vlans in promiscuous mode
4065 		 * if SR-IOV and VMDQ are disabled - otherwise ensure
4066 		 * that hardware VLAN filters remain enabled.
4067 		 */
4068 		if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4069 					IXGBE_FLAG_SRIOV_ENABLED)))
4070 			vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4071 	} else {
4072 		if (netdev->flags & IFF_ALLMULTI) {
4073 			fctrl |= IXGBE_FCTRL_MPE;
4074 			vmolr |= IXGBE_VMOLR_MPE;
4075 		}
4076 		vlnctrl |= IXGBE_VLNCTRL_VFE;
4077 		hw->addr_ctrl.user_set_promisc = false;
4078 	}
4079 
4080 	/*
4081 	 * Write addresses to available RAR registers, if there is not
4082 	 * sufficient space to store all the addresses then enable
4083 	 * unicast promiscuous mode
4084 	 */
4085 	count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
4086 	if (count < 0) {
4087 		fctrl |= IXGBE_FCTRL_UPE;
4088 		vmolr |= IXGBE_VMOLR_ROPE;
4089 	}
4090 
4091 	/* Write addresses to the MTA, if the attempt fails
4092 	 * then we should just turn on promiscuous mode so
4093 	 * that we can at least receive multicast traffic
4094 	 */
4095 	count = ixgbe_write_mc_addr_list(netdev);
4096 	if (count < 0) {
4097 		fctrl |= IXGBE_FCTRL_MPE;
4098 		vmolr |= IXGBE_VMOLR_MPE;
4099 	} else if (count) {
4100 		vmolr |= IXGBE_VMOLR_ROMPE;
4101 	}
4102 
4103 	if (hw->mac.type != ixgbe_mac_82598EB) {
4104 		vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4105 			 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4106 			   IXGBE_VMOLR_ROPE);
4107 		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4108 	}
4109 
4110 	/* This is useful for sniffing bad packets. */
4111 	if (adapter->netdev->features & NETIF_F_RXALL) {
4112 		/* UPE and MPE will be handled by normal PROMISC logic
4113 		 * in e1000e_set_rx_mode */
4114 		fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4115 			  IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4116 			  IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4117 
4118 		fctrl &= ~(IXGBE_FCTRL_DPF);
4119 		/* NOTE:  VLAN filtering is disabled by setting PROMISC */
4120 	}
4121 
4122 	IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4123 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4124 
4125 	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4126 		ixgbe_vlan_strip_enable(adapter);
4127 	else
4128 		ixgbe_vlan_strip_disable(adapter);
4129 }
4130 
4131 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4132 {
4133 	int q_idx;
4134 
4135 	for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4136 		ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4137 		napi_enable(&adapter->q_vector[q_idx]->napi);
4138 	}
4139 }
4140 
4141 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4142 {
4143 	int q_idx;
4144 
4145 	for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4146 		napi_disable(&adapter->q_vector[q_idx]->napi);
4147 		while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4148 			pr_info("QV %d locked\n", q_idx);
4149 			usleep_range(1000, 20000);
4150 		}
4151 	}
4152 }
4153 
4154 #ifdef CONFIG_IXGBE_DCB
4155 /**
4156  * ixgbe_configure_dcb - Configure DCB hardware
4157  * @adapter: ixgbe adapter struct
4158  *
4159  * This is called by the driver on open to configure the DCB hardware.
4160  * This is also called by the gennetlink interface when reconfiguring
4161  * the DCB state.
4162  */
4163 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4164 {
4165 	struct ixgbe_hw *hw = &adapter->hw;
4166 	int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4167 
4168 	if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4169 		if (hw->mac.type == ixgbe_mac_82598EB)
4170 			netif_set_gso_max_size(adapter->netdev, 65536);
4171 		return;
4172 	}
4173 
4174 	if (hw->mac.type == ixgbe_mac_82598EB)
4175 		netif_set_gso_max_size(adapter->netdev, 32768);
4176 
4177 #ifdef IXGBE_FCOE
4178 	if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4179 		max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4180 #endif
4181 
4182 	/* reconfigure the hardware */
4183 	if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4184 		ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4185 						DCB_TX_CONFIG);
4186 		ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4187 						DCB_RX_CONFIG);
4188 		ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4189 	} else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4190 		ixgbe_dcb_hw_ets(&adapter->hw,
4191 				 adapter->ixgbe_ieee_ets,
4192 				 max_frame);
4193 		ixgbe_dcb_hw_pfc_config(&adapter->hw,
4194 					adapter->ixgbe_ieee_pfc->pfc_en,
4195 					adapter->ixgbe_ieee_ets->prio_tc);
4196 	}
4197 
4198 	/* Enable RSS Hash per TC */
4199 	if (hw->mac.type != ixgbe_mac_82598EB) {
4200 		u32 msb = 0;
4201 		u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4202 
4203 		while (rss_i) {
4204 			msb++;
4205 			rss_i >>= 1;
4206 		}
4207 
4208 		/* write msb to all 8 TCs in one write */
4209 		IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4210 	}
4211 }
4212 #endif
4213 
4214 /* Additional bittime to account for IXGBE framing */
4215 #define IXGBE_ETH_FRAMING 20
4216 
4217 /**
4218  * ixgbe_hpbthresh - calculate high water mark for flow control
4219  *
4220  * @adapter: board private structure to calculate for
4221  * @pb: packet buffer to calculate
4222  */
4223 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4224 {
4225 	struct ixgbe_hw *hw = &adapter->hw;
4226 	struct net_device *dev = adapter->netdev;
4227 	int link, tc, kb, marker;
4228 	u32 dv_id, rx_pba;
4229 
4230 	/* Calculate max LAN frame size */
4231 	tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4232 
4233 #ifdef IXGBE_FCOE
4234 	/* FCoE traffic class uses FCOE jumbo frames */
4235 	if ((dev->features & NETIF_F_FCOE_MTU) &&
4236 	    (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4237 	    (pb == ixgbe_fcoe_get_tc(adapter)))
4238 		tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4239 #endif
4240 
4241 	/* Calculate delay value for device */
4242 	switch (hw->mac.type) {
4243 	case ixgbe_mac_X540:
4244 		dv_id = IXGBE_DV_X540(link, tc);
4245 		break;
4246 	default:
4247 		dv_id = IXGBE_DV(link, tc);
4248 		break;
4249 	}
4250 
4251 	/* Loopback switch introduces additional latency */
4252 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4253 		dv_id += IXGBE_B2BT(tc);
4254 
4255 	/* Delay value is calculated in bit times convert to KB */
4256 	kb = IXGBE_BT2KB(dv_id);
4257 	rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4258 
4259 	marker = rx_pba - kb;
4260 
4261 	/* It is possible that the packet buffer is not large enough
4262 	 * to provide required headroom. In this case throw an error
4263 	 * to user and a do the best we can.
4264 	 */
4265 	if (marker < 0) {
4266 		e_warn(drv, "Packet Buffer(%i) can not provide enough"
4267 			    "headroom to support flow control."
4268 			    "Decrease MTU or number of traffic classes\n", pb);
4269 		marker = tc + 1;
4270 	}
4271 
4272 	return marker;
4273 }
4274 
4275 /**
4276  * ixgbe_lpbthresh - calculate low water mark for for flow control
4277  *
4278  * @adapter: board private structure to calculate for
4279  * @pb: packet buffer to calculate
4280  */
4281 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4282 {
4283 	struct ixgbe_hw *hw = &adapter->hw;
4284 	struct net_device *dev = adapter->netdev;
4285 	int tc;
4286 	u32 dv_id;
4287 
4288 	/* Calculate max LAN frame size */
4289 	tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4290 
4291 #ifdef IXGBE_FCOE
4292 	/* FCoE traffic class uses FCOE jumbo frames */
4293 	if ((dev->features & NETIF_F_FCOE_MTU) &&
4294 	    (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4295 	    (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4296 		tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4297 #endif
4298 
4299 	/* Calculate delay value for device */
4300 	switch (hw->mac.type) {
4301 	case ixgbe_mac_X540:
4302 		dv_id = IXGBE_LOW_DV_X540(tc);
4303 		break;
4304 	default:
4305 		dv_id = IXGBE_LOW_DV(tc);
4306 		break;
4307 	}
4308 
4309 	/* Delay value is calculated in bit times convert to KB */
4310 	return IXGBE_BT2KB(dv_id);
4311 }
4312 
4313 /*
4314  * ixgbe_pbthresh_setup - calculate and setup high low water marks
4315  */
4316 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4317 {
4318 	struct ixgbe_hw *hw = &adapter->hw;
4319 	int num_tc = netdev_get_num_tc(adapter->netdev);
4320 	int i;
4321 
4322 	if (!num_tc)
4323 		num_tc = 1;
4324 
4325 	for (i = 0; i < num_tc; i++) {
4326 		hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4327 		hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4328 
4329 		/* Low water marks must not be larger than high water marks */
4330 		if (hw->fc.low_water[i] > hw->fc.high_water[i])
4331 			hw->fc.low_water[i] = 0;
4332 	}
4333 
4334 	for (; i < MAX_TRAFFIC_CLASS; i++)
4335 		hw->fc.high_water[i] = 0;
4336 }
4337 
4338 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4339 {
4340 	struct ixgbe_hw *hw = &adapter->hw;
4341 	int hdrm;
4342 	u8 tc = netdev_get_num_tc(adapter->netdev);
4343 
4344 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4345 	    adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4346 		hdrm = 32 << adapter->fdir_pballoc;
4347 	else
4348 		hdrm = 0;
4349 
4350 	hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4351 	ixgbe_pbthresh_setup(adapter);
4352 }
4353 
4354 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4355 {
4356 	struct ixgbe_hw *hw = &adapter->hw;
4357 	struct hlist_node *node2;
4358 	struct ixgbe_fdir_filter *filter;
4359 
4360 	spin_lock(&adapter->fdir_perfect_lock);
4361 
4362 	if (!hlist_empty(&adapter->fdir_filter_list))
4363 		ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4364 
4365 	hlist_for_each_entry_safe(filter, node2,
4366 				  &adapter->fdir_filter_list, fdir_node) {
4367 		ixgbe_fdir_write_perfect_filter_82599(hw,
4368 				&filter->filter,
4369 				filter->sw_idx,
4370 				(filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4371 				IXGBE_FDIR_DROP_QUEUE :
4372 				adapter->rx_ring[filter->action]->reg_idx);
4373 	}
4374 
4375 	spin_unlock(&adapter->fdir_perfect_lock);
4376 }
4377 
4378 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4379 				      struct ixgbe_adapter *adapter)
4380 {
4381 	struct ixgbe_hw *hw = &adapter->hw;
4382 	u32 vmolr;
4383 
4384 	/* No unicast promiscuous support for VMDQ devices. */
4385 	vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4386 	vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4387 
4388 	/* clear the affected bit */
4389 	vmolr &= ~IXGBE_VMOLR_MPE;
4390 
4391 	if (dev->flags & IFF_ALLMULTI) {
4392 		vmolr |= IXGBE_VMOLR_MPE;
4393 	} else {
4394 		vmolr |= IXGBE_VMOLR_ROMPE;
4395 		hw->mac.ops.update_mc_addr_list(hw, dev);
4396 	}
4397 	ixgbe_write_uc_addr_list(adapter->netdev, pool);
4398 	IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4399 }
4400 
4401 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4402 {
4403 	struct ixgbe_adapter *adapter = vadapter->real_adapter;
4404 	int rss_i = adapter->num_rx_queues_per_pool;
4405 	struct ixgbe_hw *hw = &adapter->hw;
4406 	u16 pool = vadapter->pool;
4407 	u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4408 		      IXGBE_PSRTYPE_UDPHDR |
4409 		      IXGBE_PSRTYPE_IPV4HDR |
4410 		      IXGBE_PSRTYPE_L2HDR |
4411 		      IXGBE_PSRTYPE_IPV6HDR;
4412 
4413 	if (hw->mac.type == ixgbe_mac_82598EB)
4414 		return;
4415 
4416 	if (rss_i > 3)
4417 		psrtype |= 2 << 29;
4418 	else if (rss_i > 1)
4419 		psrtype |= 1 << 29;
4420 
4421 	IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4422 }
4423 
4424 /**
4425  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4426  * @rx_ring: ring to free buffers from
4427  **/
4428 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4429 {
4430 	struct device *dev = rx_ring->dev;
4431 	unsigned long size;
4432 	u16 i;
4433 
4434 	/* ring already cleared, nothing to do */
4435 	if (!rx_ring->rx_buffer_info)
4436 		return;
4437 
4438 	/* Free all the Rx ring sk_buffs */
4439 	for (i = 0; i < rx_ring->count; i++) {
4440 		struct ixgbe_rx_buffer *rx_buffer;
4441 
4442 		rx_buffer = &rx_ring->rx_buffer_info[i];
4443 		if (rx_buffer->skb) {
4444 			struct sk_buff *skb = rx_buffer->skb;
4445 			if (IXGBE_CB(skb)->page_released) {
4446 				dma_unmap_page(dev,
4447 					       IXGBE_CB(skb)->dma,
4448 					       ixgbe_rx_bufsz(rx_ring),
4449 					       DMA_FROM_DEVICE);
4450 				IXGBE_CB(skb)->page_released = false;
4451 			}
4452 			dev_kfree_skb(skb);
4453 		}
4454 		rx_buffer->skb = NULL;
4455 		if (rx_buffer->dma)
4456 			dma_unmap_page(dev, rx_buffer->dma,
4457 				       ixgbe_rx_pg_size(rx_ring),
4458 				       DMA_FROM_DEVICE);
4459 		rx_buffer->dma = 0;
4460 		if (rx_buffer->page)
4461 			__free_pages(rx_buffer->page,
4462 				     ixgbe_rx_pg_order(rx_ring));
4463 		rx_buffer->page = NULL;
4464 	}
4465 
4466 	size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4467 	memset(rx_ring->rx_buffer_info, 0, size);
4468 
4469 	/* Zero out the descriptor ring */
4470 	memset(rx_ring->desc, 0, rx_ring->size);
4471 
4472 	rx_ring->next_to_alloc = 0;
4473 	rx_ring->next_to_clean = 0;
4474 	rx_ring->next_to_use = 0;
4475 }
4476 
4477 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4478 				   struct ixgbe_ring *rx_ring)
4479 {
4480 	struct ixgbe_adapter *adapter = vadapter->real_adapter;
4481 	int index = rx_ring->queue_index + vadapter->rx_base_queue;
4482 
4483 	/* shutdown specific queue receive and wait for dma to settle */
4484 	ixgbe_disable_rx_queue(adapter, rx_ring);
4485 	usleep_range(10000, 20000);
4486 	ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4487 	ixgbe_clean_rx_ring(rx_ring);
4488 	rx_ring->l2_accel_priv = NULL;
4489 }
4490 
4491 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4492 			       struct ixgbe_fwd_adapter *accel)
4493 {
4494 	struct ixgbe_adapter *adapter = accel->real_adapter;
4495 	unsigned int rxbase = accel->rx_base_queue;
4496 	unsigned int txbase = accel->tx_base_queue;
4497 	int i;
4498 
4499 	netif_tx_stop_all_queues(vdev);
4500 
4501 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4502 		ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4503 		adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4504 	}
4505 
4506 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4507 		adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4508 		adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4509 	}
4510 
4511 
4512 	return 0;
4513 }
4514 
4515 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4516 			     struct ixgbe_fwd_adapter *accel)
4517 {
4518 	struct ixgbe_adapter *adapter = accel->real_adapter;
4519 	unsigned int rxbase, txbase, queues;
4520 	int i, baseq, err = 0;
4521 
4522 	if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4523 		return 0;
4524 
4525 	baseq = accel->pool * adapter->num_rx_queues_per_pool;
4526 	netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4527 		   accel->pool, adapter->num_rx_pools,
4528 		   baseq, baseq + adapter->num_rx_queues_per_pool,
4529 		   adapter->fwd_bitmask);
4530 
4531 	accel->netdev = vdev;
4532 	accel->rx_base_queue = rxbase = baseq;
4533 	accel->tx_base_queue = txbase = baseq;
4534 
4535 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4536 		ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4537 
4538 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4539 		adapter->rx_ring[rxbase + i]->netdev = vdev;
4540 		adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4541 		ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4542 	}
4543 
4544 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4545 		adapter->tx_ring[txbase + i]->netdev = vdev;
4546 		adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4547 	}
4548 
4549 	queues = min_t(unsigned int,
4550 		       adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4551 	err = netif_set_real_num_tx_queues(vdev, queues);
4552 	if (err)
4553 		goto fwd_queue_err;
4554 
4555 	err = netif_set_real_num_rx_queues(vdev, queues);
4556 	if (err)
4557 		goto fwd_queue_err;
4558 
4559 	if (is_valid_ether_addr(vdev->dev_addr))
4560 		ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4561 
4562 	ixgbe_fwd_psrtype(accel);
4563 	ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4564 	return err;
4565 fwd_queue_err:
4566 	ixgbe_fwd_ring_down(vdev, accel);
4567 	return err;
4568 }
4569 
4570 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4571 {
4572 	struct net_device *upper;
4573 	struct list_head *iter;
4574 	int err;
4575 
4576 	netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4577 		if (netif_is_macvlan(upper)) {
4578 			struct macvlan_dev *dfwd = netdev_priv(upper);
4579 			struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4580 
4581 			if (dfwd->fwd_priv) {
4582 				err = ixgbe_fwd_ring_up(upper, vadapter);
4583 				if (err)
4584 					continue;
4585 			}
4586 		}
4587 	}
4588 }
4589 
4590 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4591 {
4592 	struct ixgbe_hw *hw = &adapter->hw;
4593 
4594 	ixgbe_configure_pb(adapter);
4595 #ifdef CONFIG_IXGBE_DCB
4596 	ixgbe_configure_dcb(adapter);
4597 #endif
4598 	/*
4599 	 * We must restore virtualization before VLANs or else
4600 	 * the VLVF registers will not be populated
4601 	 */
4602 	ixgbe_configure_virtualization(adapter);
4603 
4604 	ixgbe_set_rx_mode(adapter->netdev);
4605 	ixgbe_restore_vlan(adapter);
4606 
4607 	switch (hw->mac.type) {
4608 	case ixgbe_mac_82599EB:
4609 	case ixgbe_mac_X540:
4610 		hw->mac.ops.disable_rx_buff(hw);
4611 		break;
4612 	default:
4613 		break;
4614 	}
4615 
4616 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4617 		ixgbe_init_fdir_signature_82599(&adapter->hw,
4618 						adapter->fdir_pballoc);
4619 	} else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4620 		ixgbe_init_fdir_perfect_82599(&adapter->hw,
4621 					      adapter->fdir_pballoc);
4622 		ixgbe_fdir_filter_restore(adapter);
4623 	}
4624 
4625 	switch (hw->mac.type) {
4626 	case ixgbe_mac_82599EB:
4627 	case ixgbe_mac_X540:
4628 		hw->mac.ops.enable_rx_buff(hw);
4629 		break;
4630 	default:
4631 		break;
4632 	}
4633 
4634 #ifdef IXGBE_FCOE
4635 	/* configure FCoE L2 filters, redirection table, and Rx control */
4636 	ixgbe_configure_fcoe(adapter);
4637 
4638 #endif /* IXGBE_FCOE */
4639 	ixgbe_configure_tx(adapter);
4640 	ixgbe_configure_rx(adapter);
4641 	ixgbe_configure_dfwd(adapter);
4642 }
4643 
4644 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4645 {
4646 	switch (hw->phy.type) {
4647 	case ixgbe_phy_sfp_avago:
4648 	case ixgbe_phy_sfp_ftl:
4649 	case ixgbe_phy_sfp_intel:
4650 	case ixgbe_phy_sfp_unknown:
4651 	case ixgbe_phy_sfp_passive_tyco:
4652 	case ixgbe_phy_sfp_passive_unknown:
4653 	case ixgbe_phy_sfp_active_unknown:
4654 	case ixgbe_phy_sfp_ftl_active:
4655 	case ixgbe_phy_qsfp_passive_unknown:
4656 	case ixgbe_phy_qsfp_active_unknown:
4657 	case ixgbe_phy_qsfp_intel:
4658 	case ixgbe_phy_qsfp_unknown:
4659 	/* ixgbe_phy_none is set when no SFP module is present */
4660 	case ixgbe_phy_none:
4661 		return true;
4662 	case ixgbe_phy_nl:
4663 		if (hw->mac.type == ixgbe_mac_82598EB)
4664 			return true;
4665 	default:
4666 		return false;
4667 	}
4668 }
4669 
4670 /**
4671  * ixgbe_sfp_link_config - set up SFP+ link
4672  * @adapter: pointer to private adapter struct
4673  **/
4674 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4675 {
4676 	/*
4677 	 * We are assuming the worst case scenario here, and that
4678 	 * is that an SFP was inserted/removed after the reset
4679 	 * but before SFP detection was enabled.  As such the best
4680 	 * solution is to just start searching as soon as we start
4681 	 */
4682 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4683 		adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4684 
4685 	adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4686 }
4687 
4688 /**
4689  * ixgbe_non_sfp_link_config - set up non-SFP+ link
4690  * @hw: pointer to private hardware struct
4691  *
4692  * Returns 0 on success, negative on failure
4693  **/
4694 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4695 {
4696 	u32 speed;
4697 	bool autoneg, link_up = false;
4698 	u32 ret = IXGBE_ERR_LINK_SETUP;
4699 
4700 	if (hw->mac.ops.check_link)
4701 		ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4702 
4703 	if (ret)
4704 		goto link_cfg_out;
4705 
4706 	speed = hw->phy.autoneg_advertised;
4707 	if ((!speed) && (hw->mac.ops.get_link_capabilities))
4708 		ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4709 							&autoneg);
4710 	if (ret)
4711 		goto link_cfg_out;
4712 
4713 	if (hw->mac.ops.setup_link)
4714 		ret = hw->mac.ops.setup_link(hw, speed, link_up);
4715 link_cfg_out:
4716 	return ret;
4717 }
4718 
4719 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4720 {
4721 	struct ixgbe_hw *hw = &adapter->hw;
4722 	u32 gpie = 0;
4723 
4724 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4725 		gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4726 		       IXGBE_GPIE_OCD;
4727 		gpie |= IXGBE_GPIE_EIAME;
4728 		/*
4729 		 * use EIAM to auto-mask when MSI-X interrupt is asserted
4730 		 * this saves a register write for every interrupt
4731 		 */
4732 		switch (hw->mac.type) {
4733 		case ixgbe_mac_82598EB:
4734 			IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4735 			break;
4736 		case ixgbe_mac_82599EB:
4737 		case ixgbe_mac_X540:
4738 		default:
4739 			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4740 			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4741 			break;
4742 		}
4743 	} else {
4744 		/* legacy interrupts, use EIAM to auto-mask when reading EICR,
4745 		 * specifically only auto mask tx and rx interrupts */
4746 		IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4747 	}
4748 
4749 	/* XXX: to interrupt immediately for EICS writes, enable this */
4750 	/* gpie |= IXGBE_GPIE_EIMEN; */
4751 
4752 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4753 		gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4754 
4755 		switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4756 		case IXGBE_82599_VMDQ_8Q_MASK:
4757 			gpie |= IXGBE_GPIE_VTMODE_16;
4758 			break;
4759 		case IXGBE_82599_VMDQ_4Q_MASK:
4760 			gpie |= IXGBE_GPIE_VTMODE_32;
4761 			break;
4762 		default:
4763 			gpie |= IXGBE_GPIE_VTMODE_64;
4764 			break;
4765 		}
4766 	}
4767 
4768 	/* Enable Thermal over heat sensor interrupt */
4769 	if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4770 		switch (adapter->hw.mac.type) {
4771 		case ixgbe_mac_82599EB:
4772 			gpie |= IXGBE_SDP0_GPIEN;
4773 			break;
4774 		case ixgbe_mac_X540:
4775 			gpie |= IXGBE_EIMS_TS;
4776 			break;
4777 		default:
4778 			break;
4779 		}
4780 	}
4781 
4782 	/* Enable fan failure interrupt */
4783 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4784 		gpie |= IXGBE_SDP1_GPIEN;
4785 
4786 	if (hw->mac.type == ixgbe_mac_82599EB) {
4787 		gpie |= IXGBE_SDP1_GPIEN;
4788 		gpie |= IXGBE_SDP2_GPIEN;
4789 	}
4790 
4791 	IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4792 }
4793 
4794 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4795 {
4796 	struct ixgbe_hw *hw = &adapter->hw;
4797 	int err;
4798 	u32 ctrl_ext;
4799 
4800 	ixgbe_get_hw_control(adapter);
4801 	ixgbe_setup_gpie(adapter);
4802 
4803 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4804 		ixgbe_configure_msix(adapter);
4805 	else
4806 		ixgbe_configure_msi_and_legacy(adapter);
4807 
4808 	/* enable the optics for 82599 SFP+ fiber */
4809 	if (hw->mac.ops.enable_tx_laser)
4810 		hw->mac.ops.enable_tx_laser(hw);
4811 
4812 	smp_mb__before_atomic();
4813 	clear_bit(__IXGBE_DOWN, &adapter->state);
4814 	ixgbe_napi_enable_all(adapter);
4815 
4816 	if (ixgbe_is_sfp(hw)) {
4817 		ixgbe_sfp_link_config(adapter);
4818 	} else {
4819 		err = ixgbe_non_sfp_link_config(hw);
4820 		if (err)
4821 			e_err(probe, "link_config FAILED %d\n", err);
4822 	}
4823 
4824 	/* clear any pending interrupts, may auto mask */
4825 	IXGBE_READ_REG(hw, IXGBE_EICR);
4826 	ixgbe_irq_enable(adapter, true, true);
4827 
4828 	/*
4829 	 * If this adapter has a fan, check to see if we had a failure
4830 	 * before we enabled the interrupt.
4831 	 */
4832 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4833 		u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4834 		if (esdp & IXGBE_ESDP_SDP1)
4835 			e_crit(drv, "Fan has stopped, replace the adapter\n");
4836 	}
4837 
4838 	/* bring the link up in the watchdog, this could race with our first
4839 	 * link up interrupt but shouldn't be a problem */
4840 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4841 	adapter->link_check_timeout = jiffies;
4842 	mod_timer(&adapter->service_timer, jiffies);
4843 
4844 	/* Set PF Reset Done bit so PF/VF Mail Ops can work */
4845 	ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4846 	ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4847 	IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4848 }
4849 
4850 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4851 {
4852 	WARN_ON(in_interrupt());
4853 	/* put off any impending NetWatchDogTimeout */
4854 	adapter->netdev->trans_start = jiffies;
4855 
4856 	while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4857 		usleep_range(1000, 2000);
4858 	ixgbe_down(adapter);
4859 	/*
4860 	 * If SR-IOV enabled then wait a bit before bringing the adapter
4861 	 * back up to give the VFs time to respond to the reset.  The
4862 	 * two second wait is based upon the watchdog timer cycle in
4863 	 * the VF driver.
4864 	 */
4865 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4866 		msleep(2000);
4867 	ixgbe_up(adapter);
4868 	clear_bit(__IXGBE_RESETTING, &adapter->state);
4869 }
4870 
4871 void ixgbe_up(struct ixgbe_adapter *adapter)
4872 {
4873 	/* hardware has been reset, we need to reload some things */
4874 	ixgbe_configure(adapter);
4875 
4876 	ixgbe_up_complete(adapter);
4877 }
4878 
4879 void ixgbe_reset(struct ixgbe_adapter *adapter)
4880 {
4881 	struct ixgbe_hw *hw = &adapter->hw;
4882 	struct net_device *netdev = adapter->netdev;
4883 	int err;
4884 	u8 old_addr[ETH_ALEN];
4885 
4886 	if (ixgbe_removed(hw->hw_addr))
4887 		return;
4888 	/* lock SFP init bit to prevent race conditions with the watchdog */
4889 	while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4890 		usleep_range(1000, 2000);
4891 
4892 	/* clear all SFP and link config related flags while holding SFP_INIT */
4893 	adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4894 			     IXGBE_FLAG2_SFP_NEEDS_RESET);
4895 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4896 
4897 	err = hw->mac.ops.init_hw(hw);
4898 	switch (err) {
4899 	case 0:
4900 	case IXGBE_ERR_SFP_NOT_PRESENT:
4901 	case IXGBE_ERR_SFP_NOT_SUPPORTED:
4902 		break;
4903 	case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4904 		e_dev_err("master disable timed out\n");
4905 		break;
4906 	case IXGBE_ERR_EEPROM_VERSION:
4907 		/* We are running on a pre-production device, log a warning */
4908 		e_dev_warn("This device is a pre-production adapter/LOM. "
4909 			   "Please be aware there may be issues associated with "
4910 			   "your hardware.  If you are experiencing problems "
4911 			   "please contact your Intel or hardware "
4912 			   "representative who provided you with this "
4913 			   "hardware.\n");
4914 		break;
4915 	default:
4916 		e_dev_err("Hardware Error: %d\n", err);
4917 	}
4918 
4919 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4920 	/* do not flush user set addresses */
4921 	memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4922 	ixgbe_flush_sw_mac_table(adapter);
4923 	ixgbe_mac_set_default_filter(adapter, old_addr);
4924 
4925 	/* update SAN MAC vmdq pool selection */
4926 	if (hw->mac.san_mac_rar_index)
4927 		hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
4928 
4929 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
4930 		ixgbe_ptp_reset(adapter);
4931 }
4932 
4933 /**
4934  * ixgbe_clean_tx_ring - Free Tx Buffers
4935  * @tx_ring: ring to be cleaned
4936  **/
4937 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4938 {
4939 	struct ixgbe_tx_buffer *tx_buffer_info;
4940 	unsigned long size;
4941 	u16 i;
4942 
4943 	/* ring already cleared, nothing to do */
4944 	if (!tx_ring->tx_buffer_info)
4945 		return;
4946 
4947 	/* Free all the Tx ring sk_buffs */
4948 	for (i = 0; i < tx_ring->count; i++) {
4949 		tx_buffer_info = &tx_ring->tx_buffer_info[i];
4950 		ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4951 	}
4952 
4953 	netdev_tx_reset_queue(txring_txq(tx_ring));
4954 
4955 	size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4956 	memset(tx_ring->tx_buffer_info, 0, size);
4957 
4958 	/* Zero out the descriptor ring */
4959 	memset(tx_ring->desc, 0, tx_ring->size);
4960 
4961 	tx_ring->next_to_use = 0;
4962 	tx_ring->next_to_clean = 0;
4963 }
4964 
4965 /**
4966  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4967  * @adapter: board private structure
4968  **/
4969 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4970 {
4971 	int i;
4972 
4973 	for (i = 0; i < adapter->num_rx_queues; i++)
4974 		ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4975 }
4976 
4977 /**
4978  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4979  * @adapter: board private structure
4980  **/
4981 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4982 {
4983 	int i;
4984 
4985 	for (i = 0; i < adapter->num_tx_queues; i++)
4986 		ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4987 }
4988 
4989 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4990 {
4991 	struct hlist_node *node2;
4992 	struct ixgbe_fdir_filter *filter;
4993 
4994 	spin_lock(&adapter->fdir_perfect_lock);
4995 
4996 	hlist_for_each_entry_safe(filter, node2,
4997 				  &adapter->fdir_filter_list, fdir_node) {
4998 		hlist_del(&filter->fdir_node);
4999 		kfree(filter);
5000 	}
5001 	adapter->fdir_filter_count = 0;
5002 
5003 	spin_unlock(&adapter->fdir_perfect_lock);
5004 }
5005 
5006 void ixgbe_down(struct ixgbe_adapter *adapter)
5007 {
5008 	struct net_device *netdev = adapter->netdev;
5009 	struct ixgbe_hw *hw = &adapter->hw;
5010 	struct net_device *upper;
5011 	struct list_head *iter;
5012 	u32 rxctrl;
5013 	int i;
5014 
5015 	/* signal that we are down to the interrupt handler */
5016 	if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5017 		return; /* do nothing if already down */
5018 
5019 	/* disable receives */
5020 	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5021 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
5022 
5023 	/* disable all enabled rx queues */
5024 	for (i = 0; i < adapter->num_rx_queues; i++)
5025 		/* this call also flushes the previous write */
5026 		ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5027 
5028 	usleep_range(10000, 20000);
5029 
5030 	netif_tx_stop_all_queues(netdev);
5031 
5032 	/* call carrier off first to avoid false dev_watchdog timeouts */
5033 	netif_carrier_off(netdev);
5034 	netif_tx_disable(netdev);
5035 
5036 	/* disable any upper devices */
5037 	netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5038 		if (netif_is_macvlan(upper)) {
5039 			struct macvlan_dev *vlan = netdev_priv(upper);
5040 
5041 			if (vlan->fwd_priv) {
5042 				netif_tx_stop_all_queues(upper);
5043 				netif_carrier_off(upper);
5044 				netif_tx_disable(upper);
5045 			}
5046 		}
5047 	}
5048 
5049 	ixgbe_irq_disable(adapter);
5050 
5051 	ixgbe_napi_disable_all(adapter);
5052 
5053 	adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5054 			     IXGBE_FLAG2_RESET_REQUESTED);
5055 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5056 
5057 	del_timer_sync(&adapter->service_timer);
5058 
5059 	if (adapter->num_vfs) {
5060 		/* Clear EITR Select mapping */
5061 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5062 
5063 		/* Mark all the VFs as inactive */
5064 		for (i = 0 ; i < adapter->num_vfs; i++)
5065 			adapter->vfinfo[i].clear_to_send = false;
5066 
5067 		/* ping all the active vfs to let them know we are going down */
5068 		ixgbe_ping_all_vfs(adapter);
5069 
5070 		/* Disable all VFTE/VFRE TX/RX */
5071 		ixgbe_disable_tx_rx(adapter);
5072 	}
5073 
5074 	/* disable transmits in the hardware now that interrupts are off */
5075 	for (i = 0; i < adapter->num_tx_queues; i++) {
5076 		u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5077 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5078 	}
5079 
5080 	/* Disable the Tx DMA engine on 82599 and X540 */
5081 	switch (hw->mac.type) {
5082 	case ixgbe_mac_82599EB:
5083 	case ixgbe_mac_X540:
5084 		IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5085 				(IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5086 				 ~IXGBE_DMATXCTL_TE));
5087 		break;
5088 	default:
5089 		break;
5090 	}
5091 
5092 	if (!pci_channel_offline(adapter->pdev))
5093 		ixgbe_reset(adapter);
5094 
5095 	/* power down the optics for 82599 SFP+ fiber */
5096 	if (hw->mac.ops.disable_tx_laser)
5097 		hw->mac.ops.disable_tx_laser(hw);
5098 
5099 	ixgbe_clean_all_tx_rings(adapter);
5100 	ixgbe_clean_all_rx_rings(adapter);
5101 
5102 #ifdef CONFIG_IXGBE_DCA
5103 	/* since we reset the hardware DCA settings were cleared */
5104 	ixgbe_setup_dca(adapter);
5105 #endif
5106 }
5107 
5108 /**
5109  * ixgbe_tx_timeout - Respond to a Tx Hang
5110  * @netdev: network interface device structure
5111  **/
5112 static void ixgbe_tx_timeout(struct net_device *netdev)
5113 {
5114 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
5115 
5116 	/* Do the reset outside of interrupt context */
5117 	ixgbe_tx_timeout_reset(adapter);
5118 }
5119 
5120 /**
5121  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5122  * @adapter: board private structure to initialize
5123  *
5124  * ixgbe_sw_init initializes the Adapter private data structure.
5125  * Fields are initialized based on PCI device information and
5126  * OS network device settings (MTU size).
5127  **/
5128 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5129 {
5130 	struct ixgbe_hw *hw = &adapter->hw;
5131 	struct pci_dev *pdev = adapter->pdev;
5132 	unsigned int rss, fdir;
5133 	u32 fwsm;
5134 #ifdef CONFIG_IXGBE_DCB
5135 	int j;
5136 	struct tc_configuration *tc;
5137 #endif
5138 
5139 	/* PCI config space info */
5140 
5141 	hw->vendor_id = pdev->vendor;
5142 	hw->device_id = pdev->device;
5143 	hw->revision_id = pdev->revision;
5144 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
5145 	hw->subsystem_device_id = pdev->subsystem_device;
5146 
5147 	/* Set common capability flags and settings */
5148 	rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
5149 	adapter->ring_feature[RING_F_RSS].limit = rss;
5150 	adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5151 	adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5152 	adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5153 	adapter->atr_sample_rate = 20;
5154 	fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5155 	adapter->ring_feature[RING_F_FDIR].limit = fdir;
5156 	adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5157 #ifdef CONFIG_IXGBE_DCA
5158 	adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5159 #endif
5160 #ifdef IXGBE_FCOE
5161 	adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5162 	adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5163 #ifdef CONFIG_IXGBE_DCB
5164 	/* Default traffic class to use for FCoE */
5165 	adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5166 #endif /* CONFIG_IXGBE_DCB */
5167 #endif /* IXGBE_FCOE */
5168 
5169 	adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5170 				     hw->mac.num_rar_entries,
5171 				     GFP_ATOMIC);
5172 
5173 	/* Set MAC specific capability flags and exceptions */
5174 	switch (hw->mac.type) {
5175 	case ixgbe_mac_82598EB:
5176 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5177 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5178 
5179 		if (hw->device_id == IXGBE_DEV_ID_82598AT)
5180 			adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5181 
5182 		adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5183 		adapter->ring_feature[RING_F_FDIR].limit = 0;
5184 		adapter->atr_sample_rate = 0;
5185 		adapter->fdir_pballoc = 0;
5186 #ifdef IXGBE_FCOE
5187 		adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5188 		adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5189 #ifdef CONFIG_IXGBE_DCB
5190 		adapter->fcoe.up = 0;
5191 #endif /* IXGBE_DCB */
5192 #endif /* IXGBE_FCOE */
5193 		break;
5194 	case ixgbe_mac_82599EB:
5195 		if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5196 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5197 		break;
5198 	case ixgbe_mac_X540:
5199 		fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5200 		if (fwsm & IXGBE_FWSM_TS_ENABLED)
5201 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5202 		break;
5203 	default:
5204 		break;
5205 	}
5206 
5207 #ifdef IXGBE_FCOE
5208 	/* FCoE support exists, always init the FCoE lock */
5209 	spin_lock_init(&adapter->fcoe.lock);
5210 
5211 #endif
5212 	/* n-tuple support exists, always init our spinlock */
5213 	spin_lock_init(&adapter->fdir_perfect_lock);
5214 
5215 #ifdef CONFIG_IXGBE_DCB
5216 	switch (hw->mac.type) {
5217 	case ixgbe_mac_X540:
5218 		adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5219 		adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5220 		break;
5221 	default:
5222 		adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5223 		adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5224 		break;
5225 	}
5226 
5227 	/* Configure DCB traffic classes */
5228 	for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5229 		tc = &adapter->dcb_cfg.tc_config[j];
5230 		tc->path[DCB_TX_CONFIG].bwg_id = 0;
5231 		tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5232 		tc->path[DCB_RX_CONFIG].bwg_id = 0;
5233 		tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5234 		tc->dcb_pfc = pfc_disabled;
5235 	}
5236 
5237 	/* Initialize default user to priority mapping, UPx->TC0 */
5238 	tc = &adapter->dcb_cfg.tc_config[0];
5239 	tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5240 	tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5241 
5242 	adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5243 	adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5244 	adapter->dcb_cfg.pfc_mode_enable = false;
5245 	adapter->dcb_set_bitmap = 0x00;
5246 	adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5247 	memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5248 	       sizeof(adapter->temp_dcb_cfg));
5249 
5250 #endif
5251 
5252 	/* default flow control settings */
5253 	hw->fc.requested_mode = ixgbe_fc_full;
5254 	hw->fc.current_mode = ixgbe_fc_full;	/* init for ethtool output */
5255 	ixgbe_pbthresh_setup(adapter);
5256 	hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5257 	hw->fc.send_xon = true;
5258 	hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5259 
5260 #ifdef CONFIG_PCI_IOV
5261 	if (max_vfs > 0)
5262 		e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5263 
5264 	/* assign number of SR-IOV VFs */
5265 	if (hw->mac.type != ixgbe_mac_82598EB) {
5266 		if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5267 			adapter->num_vfs = 0;
5268 			e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5269 		} else {
5270 			adapter->num_vfs = max_vfs;
5271 		}
5272 	}
5273 #endif /* CONFIG_PCI_IOV */
5274 
5275 	/* enable itr by default in dynamic mode */
5276 	adapter->rx_itr_setting = 1;
5277 	adapter->tx_itr_setting = 1;
5278 
5279 	/* set default ring sizes */
5280 	adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5281 	adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5282 
5283 	/* set default work limits */
5284 	adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5285 
5286 	/* initialize eeprom parameters */
5287 	if (ixgbe_init_eeprom_params_generic(hw)) {
5288 		e_dev_err("EEPROM initialization failed\n");
5289 		return -EIO;
5290 	}
5291 
5292 	/* PF holds first pool slot */
5293 	set_bit(0, &adapter->fwd_bitmask);
5294 	set_bit(__IXGBE_DOWN, &adapter->state);
5295 
5296 	return 0;
5297 }
5298 
5299 /**
5300  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5301  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5302  *
5303  * Return 0 on success, negative on failure
5304  **/
5305 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5306 {
5307 	struct device *dev = tx_ring->dev;
5308 	int orig_node = dev_to_node(dev);
5309 	int numa_node = -1;
5310 	int size;
5311 
5312 	size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5313 
5314 	if (tx_ring->q_vector)
5315 		numa_node = tx_ring->q_vector->numa_node;
5316 
5317 	tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
5318 	if (!tx_ring->tx_buffer_info)
5319 		tx_ring->tx_buffer_info = vzalloc(size);
5320 	if (!tx_ring->tx_buffer_info)
5321 		goto err;
5322 
5323 	u64_stats_init(&tx_ring->syncp);
5324 
5325 	/* round up to nearest 4K */
5326 	tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5327 	tx_ring->size = ALIGN(tx_ring->size, 4096);
5328 
5329 	set_dev_node(dev, numa_node);
5330 	tx_ring->desc = dma_alloc_coherent(dev,
5331 					   tx_ring->size,
5332 					   &tx_ring->dma,
5333 					   GFP_KERNEL);
5334 	set_dev_node(dev, orig_node);
5335 	if (!tx_ring->desc)
5336 		tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5337 						   &tx_ring->dma, GFP_KERNEL);
5338 	if (!tx_ring->desc)
5339 		goto err;
5340 
5341 	tx_ring->next_to_use = 0;
5342 	tx_ring->next_to_clean = 0;
5343 	return 0;
5344 
5345 err:
5346 	vfree(tx_ring->tx_buffer_info);
5347 	tx_ring->tx_buffer_info = NULL;
5348 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5349 	return -ENOMEM;
5350 }
5351 
5352 /**
5353  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5354  * @adapter: board private structure
5355  *
5356  * If this function returns with an error, then it's possible one or
5357  * more of the rings is populated (while the rest are not).  It is the
5358  * callers duty to clean those orphaned rings.
5359  *
5360  * Return 0 on success, negative on failure
5361  **/
5362 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5363 {
5364 	int i, err = 0;
5365 
5366 	for (i = 0; i < adapter->num_tx_queues; i++) {
5367 		err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5368 		if (!err)
5369 			continue;
5370 
5371 		e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5372 		goto err_setup_tx;
5373 	}
5374 
5375 	return 0;
5376 err_setup_tx:
5377 	/* rewind the index freeing the rings as we go */
5378 	while (i--)
5379 		ixgbe_free_tx_resources(adapter->tx_ring[i]);
5380 	return err;
5381 }
5382 
5383 /**
5384  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5385  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5386  *
5387  * Returns 0 on success, negative on failure
5388  **/
5389 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5390 {
5391 	struct device *dev = rx_ring->dev;
5392 	int orig_node = dev_to_node(dev);
5393 	int numa_node = -1;
5394 	int size;
5395 
5396 	size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5397 
5398 	if (rx_ring->q_vector)
5399 		numa_node = rx_ring->q_vector->numa_node;
5400 
5401 	rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
5402 	if (!rx_ring->rx_buffer_info)
5403 		rx_ring->rx_buffer_info = vzalloc(size);
5404 	if (!rx_ring->rx_buffer_info)
5405 		goto err;
5406 
5407 	u64_stats_init(&rx_ring->syncp);
5408 
5409 	/* Round up to nearest 4K */
5410 	rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5411 	rx_ring->size = ALIGN(rx_ring->size, 4096);
5412 
5413 	set_dev_node(dev, numa_node);
5414 	rx_ring->desc = dma_alloc_coherent(dev,
5415 					   rx_ring->size,
5416 					   &rx_ring->dma,
5417 					   GFP_KERNEL);
5418 	set_dev_node(dev, orig_node);
5419 	if (!rx_ring->desc)
5420 		rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5421 						   &rx_ring->dma, GFP_KERNEL);
5422 	if (!rx_ring->desc)
5423 		goto err;
5424 
5425 	rx_ring->next_to_clean = 0;
5426 	rx_ring->next_to_use = 0;
5427 
5428 	return 0;
5429 err:
5430 	vfree(rx_ring->rx_buffer_info);
5431 	rx_ring->rx_buffer_info = NULL;
5432 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5433 	return -ENOMEM;
5434 }
5435 
5436 /**
5437  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5438  * @adapter: board private structure
5439  *
5440  * If this function returns with an error, then it's possible one or
5441  * more of the rings is populated (while the rest are not).  It is the
5442  * callers duty to clean those orphaned rings.
5443  *
5444  * Return 0 on success, negative on failure
5445  **/
5446 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5447 {
5448 	int i, err = 0;
5449 
5450 	for (i = 0; i < adapter->num_rx_queues; i++) {
5451 		err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5452 		if (!err)
5453 			continue;
5454 
5455 		e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5456 		goto err_setup_rx;
5457 	}
5458 
5459 #ifdef IXGBE_FCOE
5460 	err = ixgbe_setup_fcoe_ddp_resources(adapter);
5461 	if (!err)
5462 #endif
5463 		return 0;
5464 err_setup_rx:
5465 	/* rewind the index freeing the rings as we go */
5466 	while (i--)
5467 		ixgbe_free_rx_resources(adapter->rx_ring[i]);
5468 	return err;
5469 }
5470 
5471 /**
5472  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5473  * @tx_ring: Tx descriptor ring for a specific queue
5474  *
5475  * Free all transmit software resources
5476  **/
5477 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5478 {
5479 	ixgbe_clean_tx_ring(tx_ring);
5480 
5481 	vfree(tx_ring->tx_buffer_info);
5482 	tx_ring->tx_buffer_info = NULL;
5483 
5484 	/* if not set, then don't free */
5485 	if (!tx_ring->desc)
5486 		return;
5487 
5488 	dma_free_coherent(tx_ring->dev, tx_ring->size,
5489 			  tx_ring->desc, tx_ring->dma);
5490 
5491 	tx_ring->desc = NULL;
5492 }
5493 
5494 /**
5495  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5496  * @adapter: board private structure
5497  *
5498  * Free all transmit software resources
5499  **/
5500 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5501 {
5502 	int i;
5503 
5504 	for (i = 0; i < adapter->num_tx_queues; i++)
5505 		if (adapter->tx_ring[i]->desc)
5506 			ixgbe_free_tx_resources(adapter->tx_ring[i]);
5507 }
5508 
5509 /**
5510  * ixgbe_free_rx_resources - Free Rx Resources
5511  * @rx_ring: ring to clean the resources from
5512  *
5513  * Free all receive software resources
5514  **/
5515 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5516 {
5517 	ixgbe_clean_rx_ring(rx_ring);
5518 
5519 	vfree(rx_ring->rx_buffer_info);
5520 	rx_ring->rx_buffer_info = NULL;
5521 
5522 	/* if not set, then don't free */
5523 	if (!rx_ring->desc)
5524 		return;
5525 
5526 	dma_free_coherent(rx_ring->dev, rx_ring->size,
5527 			  rx_ring->desc, rx_ring->dma);
5528 
5529 	rx_ring->desc = NULL;
5530 }
5531 
5532 /**
5533  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5534  * @adapter: board private structure
5535  *
5536  * Free all receive software resources
5537  **/
5538 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5539 {
5540 	int i;
5541 
5542 #ifdef IXGBE_FCOE
5543 	ixgbe_free_fcoe_ddp_resources(adapter);
5544 
5545 #endif
5546 	for (i = 0; i < adapter->num_rx_queues; i++)
5547 		if (adapter->rx_ring[i]->desc)
5548 			ixgbe_free_rx_resources(adapter->rx_ring[i]);
5549 }
5550 
5551 /**
5552  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5553  * @netdev: network interface device structure
5554  * @new_mtu: new value for maximum frame size
5555  *
5556  * Returns 0 on success, negative on failure
5557  **/
5558 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5559 {
5560 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
5561 	int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5562 
5563 	/* MTU < 68 is an error and causes problems on some kernels */
5564 	if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5565 		return -EINVAL;
5566 
5567 	/*
5568 	 * For 82599EB we cannot allow legacy VFs to enable their receive
5569 	 * paths when MTU greater than 1500 is configured.  So display a
5570 	 * warning that legacy VFs will be disabled.
5571 	 */
5572 	if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5573 	    (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5574 	    (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5575 		e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5576 
5577 	e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5578 
5579 	/* must set new MTU before calling down or up */
5580 	netdev->mtu = new_mtu;
5581 
5582 	if (netif_running(netdev))
5583 		ixgbe_reinit_locked(adapter);
5584 
5585 	return 0;
5586 }
5587 
5588 /**
5589  * ixgbe_open - Called when a network interface is made active
5590  * @netdev: network interface device structure
5591  *
5592  * Returns 0 on success, negative value on failure
5593  *
5594  * The open entry point is called when a network interface is made
5595  * active by the system (IFF_UP).  At this point all resources needed
5596  * for transmit and receive operations are allocated, the interrupt
5597  * handler is registered with the OS, the watchdog timer is started,
5598  * and the stack is notified that the interface is ready.
5599  **/
5600 static int ixgbe_open(struct net_device *netdev)
5601 {
5602 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
5603 	int err, queues;
5604 
5605 	/* disallow open during test */
5606 	if (test_bit(__IXGBE_TESTING, &adapter->state))
5607 		return -EBUSY;
5608 
5609 	netif_carrier_off(netdev);
5610 
5611 	/* allocate transmit descriptors */
5612 	err = ixgbe_setup_all_tx_resources(adapter);
5613 	if (err)
5614 		goto err_setup_tx;
5615 
5616 	/* allocate receive descriptors */
5617 	err = ixgbe_setup_all_rx_resources(adapter);
5618 	if (err)
5619 		goto err_setup_rx;
5620 
5621 	ixgbe_configure(adapter);
5622 
5623 	err = ixgbe_request_irq(adapter);
5624 	if (err)
5625 		goto err_req_irq;
5626 
5627 	/* Notify the stack of the actual queue counts. */
5628 	if (adapter->num_rx_pools > 1)
5629 		queues = adapter->num_rx_queues_per_pool;
5630 	else
5631 		queues = adapter->num_tx_queues;
5632 
5633 	err = netif_set_real_num_tx_queues(netdev, queues);
5634 	if (err)
5635 		goto err_set_queues;
5636 
5637 	if (adapter->num_rx_pools > 1 &&
5638 	    adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5639 		queues = IXGBE_MAX_L2A_QUEUES;
5640 	else
5641 		queues = adapter->num_rx_queues;
5642 	err = netif_set_real_num_rx_queues(netdev, queues);
5643 	if (err)
5644 		goto err_set_queues;
5645 
5646 	ixgbe_ptp_init(adapter);
5647 
5648 	ixgbe_up_complete(adapter);
5649 
5650 	return 0;
5651 
5652 err_set_queues:
5653 	ixgbe_free_irq(adapter);
5654 err_req_irq:
5655 	ixgbe_free_all_rx_resources(adapter);
5656 err_setup_rx:
5657 	ixgbe_free_all_tx_resources(adapter);
5658 err_setup_tx:
5659 	ixgbe_reset(adapter);
5660 
5661 	return err;
5662 }
5663 
5664 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5665 {
5666 	ixgbe_ptp_suspend(adapter);
5667 
5668 	ixgbe_down(adapter);
5669 	ixgbe_free_irq(adapter);
5670 
5671 	ixgbe_free_all_tx_resources(adapter);
5672 	ixgbe_free_all_rx_resources(adapter);
5673 }
5674 
5675 /**
5676  * ixgbe_close - Disables a network interface
5677  * @netdev: network interface device structure
5678  *
5679  * Returns 0, this is not allowed to fail
5680  *
5681  * The close entry point is called when an interface is de-activated
5682  * by the OS.  The hardware is still under the drivers control, but
5683  * needs to be disabled.  A global MAC reset is issued to stop the
5684  * hardware, and all transmit and receive resources are freed.
5685  **/
5686 static int ixgbe_close(struct net_device *netdev)
5687 {
5688 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
5689 
5690 	ixgbe_ptp_stop(adapter);
5691 
5692 	ixgbe_close_suspend(adapter);
5693 
5694 	ixgbe_fdir_filter_exit(adapter);
5695 
5696 	ixgbe_release_hw_control(adapter);
5697 
5698 	return 0;
5699 }
5700 
5701 #ifdef CONFIG_PM
5702 static int ixgbe_resume(struct pci_dev *pdev)
5703 {
5704 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5705 	struct net_device *netdev = adapter->netdev;
5706 	u32 err;
5707 
5708 	adapter->hw.hw_addr = adapter->io_addr;
5709 	pci_set_power_state(pdev, PCI_D0);
5710 	pci_restore_state(pdev);
5711 	/*
5712 	 * pci_restore_state clears dev->state_saved so call
5713 	 * pci_save_state to restore it.
5714 	 */
5715 	pci_save_state(pdev);
5716 
5717 	err = pci_enable_device_mem(pdev);
5718 	if (err) {
5719 		e_dev_err("Cannot enable PCI device from suspend\n");
5720 		return err;
5721 	}
5722 	smp_mb__before_atomic();
5723 	clear_bit(__IXGBE_DISABLED, &adapter->state);
5724 	pci_set_master(pdev);
5725 
5726 	pci_wake_from_d3(pdev, false);
5727 
5728 	ixgbe_reset(adapter);
5729 
5730 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5731 
5732 	rtnl_lock();
5733 	err = ixgbe_init_interrupt_scheme(adapter);
5734 	if (!err && netif_running(netdev))
5735 		err = ixgbe_open(netdev);
5736 
5737 	rtnl_unlock();
5738 
5739 	if (err)
5740 		return err;
5741 
5742 	netif_device_attach(netdev);
5743 
5744 	return 0;
5745 }
5746 #endif /* CONFIG_PM */
5747 
5748 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5749 {
5750 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5751 	struct net_device *netdev = adapter->netdev;
5752 	struct ixgbe_hw *hw = &adapter->hw;
5753 	u32 ctrl, fctrl;
5754 	u32 wufc = adapter->wol;
5755 #ifdef CONFIG_PM
5756 	int retval = 0;
5757 #endif
5758 
5759 	netif_device_detach(netdev);
5760 
5761 	rtnl_lock();
5762 	if (netif_running(netdev))
5763 		ixgbe_close_suspend(adapter);
5764 	rtnl_unlock();
5765 
5766 	ixgbe_clear_interrupt_scheme(adapter);
5767 
5768 #ifdef CONFIG_PM
5769 	retval = pci_save_state(pdev);
5770 	if (retval)
5771 		return retval;
5772 
5773 #endif
5774 	if (hw->mac.ops.stop_link_on_d3)
5775 		hw->mac.ops.stop_link_on_d3(hw);
5776 
5777 	if (wufc) {
5778 		ixgbe_set_rx_mode(netdev);
5779 
5780 		/* enable the optics for 82599 SFP+ fiber as we can WoL */
5781 		if (hw->mac.ops.enable_tx_laser)
5782 			hw->mac.ops.enable_tx_laser(hw);
5783 
5784 		/* turn on all-multi mode if wake on multicast is enabled */
5785 		if (wufc & IXGBE_WUFC_MC) {
5786 			fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5787 			fctrl |= IXGBE_FCTRL_MPE;
5788 			IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5789 		}
5790 
5791 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5792 		ctrl |= IXGBE_CTRL_GIO_DIS;
5793 		IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5794 
5795 		IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5796 	} else {
5797 		IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5798 		IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5799 	}
5800 
5801 	switch (hw->mac.type) {
5802 	case ixgbe_mac_82598EB:
5803 		pci_wake_from_d3(pdev, false);
5804 		break;
5805 	case ixgbe_mac_82599EB:
5806 	case ixgbe_mac_X540:
5807 		pci_wake_from_d3(pdev, !!wufc);
5808 		break;
5809 	default:
5810 		break;
5811 	}
5812 
5813 	*enable_wake = !!wufc;
5814 
5815 	ixgbe_release_hw_control(adapter);
5816 
5817 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5818 		pci_disable_device(pdev);
5819 
5820 	return 0;
5821 }
5822 
5823 #ifdef CONFIG_PM
5824 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5825 {
5826 	int retval;
5827 	bool wake;
5828 
5829 	retval = __ixgbe_shutdown(pdev, &wake);
5830 	if (retval)
5831 		return retval;
5832 
5833 	if (wake) {
5834 		pci_prepare_to_sleep(pdev);
5835 	} else {
5836 		pci_wake_from_d3(pdev, false);
5837 		pci_set_power_state(pdev, PCI_D3hot);
5838 	}
5839 
5840 	return 0;
5841 }
5842 #endif /* CONFIG_PM */
5843 
5844 static void ixgbe_shutdown(struct pci_dev *pdev)
5845 {
5846 	bool wake;
5847 
5848 	__ixgbe_shutdown(pdev, &wake);
5849 
5850 	if (system_state == SYSTEM_POWER_OFF) {
5851 		pci_wake_from_d3(pdev, wake);
5852 		pci_set_power_state(pdev, PCI_D3hot);
5853 	}
5854 }
5855 
5856 /**
5857  * ixgbe_update_stats - Update the board statistics counters.
5858  * @adapter: board private structure
5859  **/
5860 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5861 {
5862 	struct net_device *netdev = adapter->netdev;
5863 	struct ixgbe_hw *hw = &adapter->hw;
5864 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
5865 	u64 total_mpc = 0;
5866 	u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5867 	u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5868 	u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5869 	u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5870 
5871 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5872 	    test_bit(__IXGBE_RESETTING, &adapter->state))
5873 		return;
5874 
5875 	if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5876 		u64 rsc_count = 0;
5877 		u64 rsc_flush = 0;
5878 		for (i = 0; i < adapter->num_rx_queues; i++) {
5879 			rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5880 			rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5881 		}
5882 		adapter->rsc_total_count = rsc_count;
5883 		adapter->rsc_total_flush = rsc_flush;
5884 	}
5885 
5886 	for (i = 0; i < adapter->num_rx_queues; i++) {
5887 		struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5888 		non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5889 		alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5890 		alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5891 		hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5892 		bytes += rx_ring->stats.bytes;
5893 		packets += rx_ring->stats.packets;
5894 	}
5895 	adapter->non_eop_descs = non_eop_descs;
5896 	adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5897 	adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5898 	adapter->hw_csum_rx_error = hw_csum_rx_error;
5899 	netdev->stats.rx_bytes = bytes;
5900 	netdev->stats.rx_packets = packets;
5901 
5902 	bytes = 0;
5903 	packets = 0;
5904 	/* gather some stats to the adapter struct that are per queue */
5905 	for (i = 0; i < adapter->num_tx_queues; i++) {
5906 		struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5907 		restart_queue += tx_ring->tx_stats.restart_queue;
5908 		tx_busy += tx_ring->tx_stats.tx_busy;
5909 		bytes += tx_ring->stats.bytes;
5910 		packets += tx_ring->stats.packets;
5911 	}
5912 	adapter->restart_queue = restart_queue;
5913 	adapter->tx_busy = tx_busy;
5914 	netdev->stats.tx_bytes = bytes;
5915 	netdev->stats.tx_packets = packets;
5916 
5917 	hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5918 
5919 	/* 8 register reads */
5920 	for (i = 0; i < 8; i++) {
5921 		/* for packet buffers not used, the register should read 0 */
5922 		mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5923 		missed_rx += mpc;
5924 		hwstats->mpc[i] += mpc;
5925 		total_mpc += hwstats->mpc[i];
5926 		hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5927 		hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5928 		switch (hw->mac.type) {
5929 		case ixgbe_mac_82598EB:
5930 			hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5931 			hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5932 			hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5933 			hwstats->pxonrxc[i] +=
5934 				IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5935 			break;
5936 		case ixgbe_mac_82599EB:
5937 		case ixgbe_mac_X540:
5938 			hwstats->pxonrxc[i] +=
5939 				IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5940 			break;
5941 		default:
5942 			break;
5943 		}
5944 	}
5945 
5946 	/*16 register reads */
5947 	for (i = 0; i < 16; i++) {
5948 		hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5949 		hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5950 		if ((hw->mac.type == ixgbe_mac_82599EB) ||
5951 		    (hw->mac.type == ixgbe_mac_X540)) {
5952 			hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5953 			IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5954 			hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5955 			IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5956 		}
5957 	}
5958 
5959 	hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5960 	/* work around hardware counting issue */
5961 	hwstats->gprc -= missed_rx;
5962 
5963 	ixgbe_update_xoff_received(adapter);
5964 
5965 	/* 82598 hardware only has a 32 bit counter in the high register */
5966 	switch (hw->mac.type) {
5967 	case ixgbe_mac_82598EB:
5968 		hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5969 		hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5970 		hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5971 		hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5972 		break;
5973 	case ixgbe_mac_X540:
5974 		/* OS2BMC stats are X540 only*/
5975 		hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5976 		hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5977 		hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5978 		hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5979 	case ixgbe_mac_82599EB:
5980 		for (i = 0; i < 16; i++)
5981 			adapter->hw_rx_no_dma_resources +=
5982 					     IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5983 		hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5984 		IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5985 		hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5986 		IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5987 		hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5988 		IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5989 		hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5990 		hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5991 		hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5992 #ifdef IXGBE_FCOE
5993 		hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5994 		hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5995 		hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5996 		hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5997 		hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5998 		hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5999 		/* Add up per cpu counters for total ddp aloc fail */
6000 		if (adapter->fcoe.ddp_pool) {
6001 			struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6002 			struct ixgbe_fcoe_ddp_pool *ddp_pool;
6003 			unsigned int cpu;
6004 			u64 noddp = 0, noddp_ext_buff = 0;
6005 			for_each_possible_cpu(cpu) {
6006 				ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6007 				noddp += ddp_pool->noddp;
6008 				noddp_ext_buff += ddp_pool->noddp_ext_buff;
6009 			}
6010 			hwstats->fcoe_noddp = noddp;
6011 			hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6012 		}
6013 #endif /* IXGBE_FCOE */
6014 		break;
6015 	default:
6016 		break;
6017 	}
6018 	bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6019 	hwstats->bprc += bprc;
6020 	hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6021 	if (hw->mac.type == ixgbe_mac_82598EB)
6022 		hwstats->mprc -= bprc;
6023 	hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6024 	hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6025 	hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6026 	hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6027 	hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6028 	hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6029 	hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6030 	hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6031 	lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6032 	hwstats->lxontxc += lxon;
6033 	lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6034 	hwstats->lxofftxc += lxoff;
6035 	hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6036 	hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6037 	/*
6038 	 * 82598 errata - tx of flow control packets is included in tx counters
6039 	 */
6040 	xon_off_tot = lxon + lxoff;
6041 	hwstats->gptc -= xon_off_tot;
6042 	hwstats->mptc -= xon_off_tot;
6043 	hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6044 	hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6045 	hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6046 	hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6047 	hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6048 	hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6049 	hwstats->ptc64 -= xon_off_tot;
6050 	hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6051 	hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6052 	hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6053 	hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6054 	hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6055 	hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6056 
6057 	/* Fill out the OS statistics structure */
6058 	netdev->stats.multicast = hwstats->mprc;
6059 
6060 	/* Rx Errors */
6061 	netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6062 	netdev->stats.rx_dropped = 0;
6063 	netdev->stats.rx_length_errors = hwstats->rlec;
6064 	netdev->stats.rx_crc_errors = hwstats->crcerrs;
6065 	netdev->stats.rx_missed_errors = total_mpc;
6066 }
6067 
6068 /**
6069  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6070  * @adapter: pointer to the device adapter structure
6071  **/
6072 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6073 {
6074 	struct ixgbe_hw *hw = &adapter->hw;
6075 	int i;
6076 
6077 	if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6078 		return;
6079 
6080 	adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6081 
6082 	/* if interface is down do nothing */
6083 	if (test_bit(__IXGBE_DOWN, &adapter->state))
6084 		return;
6085 
6086 	/* do nothing if we are not using signature filters */
6087 	if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6088 		return;
6089 
6090 	adapter->fdir_overflow++;
6091 
6092 	if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6093 		for (i = 0; i < adapter->num_tx_queues; i++)
6094 			set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6095 				&(adapter->tx_ring[i]->state));
6096 		/* re-enable flow director interrupts */
6097 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6098 	} else {
6099 		e_err(probe, "failed to finish FDIR re-initialization, "
6100 		      "ignored adding FDIR ATR filters\n");
6101 	}
6102 }
6103 
6104 /**
6105  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6106  * @adapter: pointer to the device adapter structure
6107  *
6108  * This function serves two purposes.  First it strobes the interrupt lines
6109  * in order to make certain interrupts are occurring.  Secondly it sets the
6110  * bits needed to check for TX hangs.  As a result we should immediately
6111  * determine if a hang has occurred.
6112  */
6113 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6114 {
6115 	struct ixgbe_hw *hw = &adapter->hw;
6116 	u64 eics = 0;
6117 	int i;
6118 
6119 	/* If we're down, removing or resetting, just bail */
6120 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6121 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
6122 	    test_bit(__IXGBE_RESETTING, &adapter->state))
6123 		return;
6124 
6125 	/* Force detection of hung controller */
6126 	if (netif_carrier_ok(adapter->netdev)) {
6127 		for (i = 0; i < adapter->num_tx_queues; i++)
6128 			set_check_for_tx_hang(adapter->tx_ring[i]);
6129 	}
6130 
6131 	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6132 		/*
6133 		 * for legacy and MSI interrupts don't set any bits
6134 		 * that are enabled for EIAM, because this operation
6135 		 * would set *both* EIMS and EICS for any bit in EIAM
6136 		 */
6137 		IXGBE_WRITE_REG(hw, IXGBE_EICS,
6138 			(IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6139 	} else {
6140 		/* get one bit for every active tx/rx interrupt vector */
6141 		for (i = 0; i < adapter->num_q_vectors; i++) {
6142 			struct ixgbe_q_vector *qv = adapter->q_vector[i];
6143 			if (qv->rx.ring || qv->tx.ring)
6144 				eics |= ((u64)1 << i);
6145 		}
6146 	}
6147 
6148 	/* Cause software interrupt to ensure rings are cleaned */
6149 	ixgbe_irq_rearm_queues(adapter, eics);
6150 
6151 }
6152 
6153 /**
6154  * ixgbe_watchdog_update_link - update the link status
6155  * @adapter: pointer to the device adapter structure
6156  * @link_speed: pointer to a u32 to store the link_speed
6157  **/
6158 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6159 {
6160 	struct ixgbe_hw *hw = &adapter->hw;
6161 	u32 link_speed = adapter->link_speed;
6162 	bool link_up = adapter->link_up;
6163 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6164 
6165 	if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6166 		return;
6167 
6168 	if (hw->mac.ops.check_link) {
6169 		hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6170 	} else {
6171 		/* always assume link is up, if no check link function */
6172 		link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6173 		link_up = true;
6174 	}
6175 
6176 	if (adapter->ixgbe_ieee_pfc)
6177 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6178 
6179 	if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6180 		hw->mac.ops.fc_enable(hw);
6181 		ixgbe_set_rx_drop_en(adapter);
6182 	}
6183 
6184 	if (link_up ||
6185 	    time_after(jiffies, (adapter->link_check_timeout +
6186 				 IXGBE_TRY_LINK_TIMEOUT))) {
6187 		adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6188 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6189 		IXGBE_WRITE_FLUSH(hw);
6190 	}
6191 
6192 	adapter->link_up = link_up;
6193 	adapter->link_speed = link_speed;
6194 }
6195 
6196 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6197 {
6198 #ifdef CONFIG_IXGBE_DCB
6199 	struct net_device *netdev = adapter->netdev;
6200 	struct dcb_app app = {
6201 			      .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6202 			      .protocol = 0,
6203 			     };
6204 	u8 up = 0;
6205 
6206 	if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6207 		up = dcb_ieee_getapp_mask(netdev, &app);
6208 
6209 	adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6210 #endif
6211 }
6212 
6213 /**
6214  * ixgbe_watchdog_link_is_up - update netif_carrier status and
6215  *                             print link up message
6216  * @adapter: pointer to the device adapter structure
6217  **/
6218 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6219 {
6220 	struct net_device *netdev = adapter->netdev;
6221 	struct ixgbe_hw *hw = &adapter->hw;
6222 	struct net_device *upper;
6223 	struct list_head *iter;
6224 	u32 link_speed = adapter->link_speed;
6225 	bool flow_rx, flow_tx;
6226 
6227 	/* only continue if link was previously down */
6228 	if (netif_carrier_ok(netdev))
6229 		return;
6230 
6231 	adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6232 
6233 	switch (hw->mac.type) {
6234 	case ixgbe_mac_82598EB: {
6235 		u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6236 		u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6237 		flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6238 		flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6239 	}
6240 		break;
6241 	case ixgbe_mac_X540:
6242 	case ixgbe_mac_82599EB: {
6243 		u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6244 		u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6245 		flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6246 		flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6247 	}
6248 		break;
6249 	default:
6250 		flow_tx = false;
6251 		flow_rx = false;
6252 		break;
6253 	}
6254 
6255 	adapter->last_rx_ptp_check = jiffies;
6256 
6257 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6258 		ixgbe_ptp_start_cyclecounter(adapter);
6259 
6260 	e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6261 	       (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6262 	       "10 Gbps" :
6263 	       (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6264 	       "1 Gbps" :
6265 	       (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6266 	       "100 Mbps" :
6267 	       "unknown speed"))),
6268 	       ((flow_rx && flow_tx) ? "RX/TX" :
6269 	       (flow_rx ? "RX" :
6270 	       (flow_tx ? "TX" : "None"))));
6271 
6272 	netif_carrier_on(netdev);
6273 	ixgbe_check_vf_rate_limit(adapter);
6274 
6275 	/* enable transmits */
6276 	netif_tx_wake_all_queues(adapter->netdev);
6277 
6278 	/* enable any upper devices */
6279 	rtnl_lock();
6280 	netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6281 		if (netif_is_macvlan(upper)) {
6282 			struct macvlan_dev *vlan = netdev_priv(upper);
6283 
6284 			if (vlan->fwd_priv)
6285 				netif_tx_wake_all_queues(upper);
6286 		}
6287 	}
6288 	rtnl_unlock();
6289 
6290 	/* update the default user priority for VFs */
6291 	ixgbe_update_default_up(adapter);
6292 
6293 	/* ping all the active vfs to let them know link has changed */
6294 	ixgbe_ping_all_vfs(adapter);
6295 }
6296 
6297 /**
6298  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6299  *                               print link down message
6300  * @adapter: pointer to the adapter structure
6301  **/
6302 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6303 {
6304 	struct net_device *netdev = adapter->netdev;
6305 	struct ixgbe_hw *hw = &adapter->hw;
6306 
6307 	adapter->link_up = false;
6308 	adapter->link_speed = 0;
6309 
6310 	/* only continue if link was up previously */
6311 	if (!netif_carrier_ok(netdev))
6312 		return;
6313 
6314 	/* poll for SFP+ cable when link is down */
6315 	if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6316 		adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6317 
6318 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6319 		ixgbe_ptp_start_cyclecounter(adapter);
6320 
6321 	e_info(drv, "NIC Link is Down\n");
6322 	netif_carrier_off(netdev);
6323 
6324 	/* ping all the active vfs to let them know link has changed */
6325 	ixgbe_ping_all_vfs(adapter);
6326 }
6327 
6328 /**
6329  * ixgbe_watchdog_flush_tx - flush queues on link down
6330  * @adapter: pointer to the device adapter structure
6331  **/
6332 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6333 {
6334 	int i;
6335 	int some_tx_pending = 0;
6336 
6337 	if (!netif_carrier_ok(adapter->netdev)) {
6338 		for (i = 0; i < adapter->num_tx_queues; i++) {
6339 			struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6340 			if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6341 				some_tx_pending = 1;
6342 				break;
6343 			}
6344 		}
6345 
6346 		if (some_tx_pending) {
6347 			/* We've lost link, so the controller stops DMA,
6348 			 * but we've got queued Tx work that's never going
6349 			 * to get done, so reset controller to flush Tx.
6350 			 * (Do the reset outside of interrupt context).
6351 			 */
6352 			e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6353 			adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6354 		}
6355 	}
6356 }
6357 
6358 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6359 {
6360 	u32 ssvpc;
6361 
6362 	/* Do not perform spoof check for 82598 or if not in IOV mode */
6363 	if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6364 	    adapter->num_vfs == 0)
6365 		return;
6366 
6367 	ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6368 
6369 	/*
6370 	 * ssvpc register is cleared on read, if zero then no
6371 	 * spoofed packets in the last interval.
6372 	 */
6373 	if (!ssvpc)
6374 		return;
6375 
6376 	e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6377 }
6378 
6379 /**
6380  * ixgbe_watchdog_subtask - check and bring link up
6381  * @adapter: pointer to the device adapter structure
6382  **/
6383 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6384 {
6385 	/* if interface is down, removing or resetting, do nothing */
6386 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6387 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
6388 	    test_bit(__IXGBE_RESETTING, &adapter->state))
6389 		return;
6390 
6391 	ixgbe_watchdog_update_link(adapter);
6392 
6393 	if (adapter->link_up)
6394 		ixgbe_watchdog_link_is_up(adapter);
6395 	else
6396 		ixgbe_watchdog_link_is_down(adapter);
6397 
6398 	ixgbe_spoof_check(adapter);
6399 	ixgbe_update_stats(adapter);
6400 
6401 	ixgbe_watchdog_flush_tx(adapter);
6402 }
6403 
6404 /**
6405  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6406  * @adapter: the ixgbe adapter structure
6407  **/
6408 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6409 {
6410 	struct ixgbe_hw *hw = &adapter->hw;
6411 	s32 err;
6412 
6413 	/* not searching for SFP so there is nothing to do here */
6414 	if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6415 	    !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6416 		return;
6417 
6418 	/* someone else is in init, wait until next service event */
6419 	if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6420 		return;
6421 
6422 	err = hw->phy.ops.identify_sfp(hw);
6423 	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6424 		goto sfp_out;
6425 
6426 	if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6427 		/* If no cable is present, then we need to reset
6428 		 * the next time we find a good cable. */
6429 		adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6430 	}
6431 
6432 	/* exit on error */
6433 	if (err)
6434 		goto sfp_out;
6435 
6436 	/* exit if reset not needed */
6437 	if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6438 		goto sfp_out;
6439 
6440 	adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6441 
6442 	/*
6443 	 * A module may be identified correctly, but the EEPROM may not have
6444 	 * support for that module.  setup_sfp() will fail in that case, so
6445 	 * we should not allow that module to load.
6446 	 */
6447 	if (hw->mac.type == ixgbe_mac_82598EB)
6448 		err = hw->phy.ops.reset(hw);
6449 	else
6450 		err = hw->mac.ops.setup_sfp(hw);
6451 
6452 	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6453 		goto sfp_out;
6454 
6455 	adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6456 	e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6457 
6458 sfp_out:
6459 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6460 
6461 	if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6462 	    (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6463 		e_dev_err("failed to initialize because an unsupported "
6464 			  "SFP+ module type was detected.\n");
6465 		e_dev_err("Reload the driver after installing a "
6466 			  "supported module.\n");
6467 		unregister_netdev(adapter->netdev);
6468 	}
6469 }
6470 
6471 /**
6472  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6473  * @adapter: the ixgbe adapter structure
6474  **/
6475 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6476 {
6477 	struct ixgbe_hw *hw = &adapter->hw;
6478 	u32 speed;
6479 	bool autoneg = false;
6480 
6481 	if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6482 		return;
6483 
6484 	/* someone else is in init, wait until next service event */
6485 	if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6486 		return;
6487 
6488 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6489 
6490 	speed = hw->phy.autoneg_advertised;
6491 	if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6492 		hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6493 
6494 		/* setup the highest link when no autoneg */
6495 		if (!autoneg) {
6496 			if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6497 				speed = IXGBE_LINK_SPEED_10GB_FULL;
6498 		}
6499 	}
6500 
6501 	if (hw->mac.ops.setup_link)
6502 		hw->mac.ops.setup_link(hw, speed, true);
6503 
6504 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6505 	adapter->link_check_timeout = jiffies;
6506 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6507 }
6508 
6509 #ifdef CONFIG_PCI_IOV
6510 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6511 {
6512 	int vf;
6513 	struct ixgbe_hw *hw = &adapter->hw;
6514 	struct net_device *netdev = adapter->netdev;
6515 	u32 gpc;
6516 	u32 ciaa, ciad;
6517 
6518 	gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6519 	if (gpc) /* If incrementing then no need for the check below */
6520 		return;
6521 	/*
6522 	 * Check to see if a bad DMA write target from an errant or
6523 	 * malicious VF has caused a PCIe error.  If so then we can
6524 	 * issue a VFLR to the offending VF(s) and then resume without
6525 	 * requesting a full slot reset.
6526 	 */
6527 
6528 	for (vf = 0; vf < adapter->num_vfs; vf++) {
6529 		ciaa = (vf << 16) | 0x80000000;
6530 		/* 32 bit read so align, we really want status at offset 6 */
6531 		ciaa |= PCI_COMMAND;
6532 		IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6533 		ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6534 		ciaa &= 0x7FFFFFFF;
6535 		/* disable debug mode asap after reading data */
6536 		IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6537 		/* Get the upper 16 bits which will be the PCI status reg */
6538 		ciad >>= 16;
6539 		if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6540 			netdev_err(netdev, "VF %d Hung DMA\n", vf);
6541 			/* Issue VFLR */
6542 			ciaa = (vf << 16) | 0x80000000;
6543 			ciaa |= 0xA8;
6544 			IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6545 			ciad = 0x00008000;  /* VFLR */
6546 			IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6547 			ciaa &= 0x7FFFFFFF;
6548 			IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6549 		}
6550 	}
6551 }
6552 
6553 #endif
6554 /**
6555  * ixgbe_service_timer - Timer Call-back
6556  * @data: pointer to adapter cast into an unsigned long
6557  **/
6558 static void ixgbe_service_timer(unsigned long data)
6559 {
6560 	struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6561 	unsigned long next_event_offset;
6562 	bool ready = true;
6563 
6564 	/* poll faster when waiting for link */
6565 	if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6566 		next_event_offset = HZ / 10;
6567 	else
6568 		next_event_offset = HZ * 2;
6569 
6570 #ifdef CONFIG_PCI_IOV
6571 	/*
6572 	 * don't bother with SR-IOV VF DMA hang check if there are
6573 	 * no VFs or the link is down
6574 	 */
6575 	if (!adapter->num_vfs ||
6576 	    (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6577 		goto normal_timer_service;
6578 
6579 	/* If we have VFs allocated then we must check for DMA hangs */
6580 	ixgbe_check_for_bad_vf(adapter);
6581 	next_event_offset = HZ / 50;
6582 	adapter->timer_event_accumulator++;
6583 
6584 	if (adapter->timer_event_accumulator >= 100)
6585 		adapter->timer_event_accumulator = 0;
6586 	else
6587 		ready = false;
6588 
6589 normal_timer_service:
6590 #endif
6591 	/* Reset the timer */
6592 	mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6593 
6594 	if (ready)
6595 		ixgbe_service_event_schedule(adapter);
6596 }
6597 
6598 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6599 {
6600 	if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6601 		return;
6602 
6603 	adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6604 
6605 	/* If we're already down, removing or resetting, just bail */
6606 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6607 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
6608 	    test_bit(__IXGBE_RESETTING, &adapter->state))
6609 		return;
6610 
6611 	ixgbe_dump(adapter);
6612 	netdev_err(adapter->netdev, "Reset adapter\n");
6613 	adapter->tx_timeout_count++;
6614 
6615 	rtnl_lock();
6616 	ixgbe_reinit_locked(adapter);
6617 	rtnl_unlock();
6618 }
6619 
6620 /**
6621  * ixgbe_service_task - manages and runs subtasks
6622  * @work: pointer to work_struct containing our data
6623  **/
6624 static void ixgbe_service_task(struct work_struct *work)
6625 {
6626 	struct ixgbe_adapter *adapter = container_of(work,
6627 						     struct ixgbe_adapter,
6628 						     service_task);
6629 	if (ixgbe_removed(adapter->hw.hw_addr)) {
6630 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6631 			rtnl_lock();
6632 			ixgbe_down(adapter);
6633 			rtnl_unlock();
6634 		}
6635 		ixgbe_service_event_complete(adapter);
6636 		return;
6637 	}
6638 	ixgbe_reset_subtask(adapter);
6639 	ixgbe_sfp_detection_subtask(adapter);
6640 	ixgbe_sfp_link_config_subtask(adapter);
6641 	ixgbe_check_overtemp_subtask(adapter);
6642 	ixgbe_watchdog_subtask(adapter);
6643 	ixgbe_fdir_reinit_subtask(adapter);
6644 	ixgbe_check_hang_subtask(adapter);
6645 
6646 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6647 		ixgbe_ptp_overflow_check(adapter);
6648 		ixgbe_ptp_rx_hang(adapter);
6649 	}
6650 
6651 	ixgbe_service_event_complete(adapter);
6652 }
6653 
6654 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6655 		     struct ixgbe_tx_buffer *first,
6656 		     u8 *hdr_len)
6657 {
6658 	struct sk_buff *skb = first->skb;
6659 	u32 vlan_macip_lens, type_tucmd;
6660 	u32 mss_l4len_idx, l4len;
6661 	int err;
6662 
6663 	if (skb->ip_summed != CHECKSUM_PARTIAL)
6664 		return 0;
6665 
6666 	if (!skb_is_gso(skb))
6667 		return 0;
6668 
6669 	err = skb_cow_head(skb, 0);
6670 	if (err < 0)
6671 		return err;
6672 
6673 	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6674 	type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6675 
6676 	if (first->protocol == htons(ETH_P_IP)) {
6677 		struct iphdr *iph = ip_hdr(skb);
6678 		iph->tot_len = 0;
6679 		iph->check = 0;
6680 		tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6681 							 iph->daddr, 0,
6682 							 IPPROTO_TCP,
6683 							 0);
6684 		type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6685 		first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6686 				   IXGBE_TX_FLAGS_CSUM |
6687 				   IXGBE_TX_FLAGS_IPV4;
6688 	} else if (skb_is_gso_v6(skb)) {
6689 		ipv6_hdr(skb)->payload_len = 0;
6690 		tcp_hdr(skb)->check =
6691 		    ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6692 				     &ipv6_hdr(skb)->daddr,
6693 				     0, IPPROTO_TCP, 0);
6694 		first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6695 				   IXGBE_TX_FLAGS_CSUM;
6696 	}
6697 
6698 	/* compute header lengths */
6699 	l4len = tcp_hdrlen(skb);
6700 	*hdr_len = skb_transport_offset(skb) + l4len;
6701 
6702 	/* update gso size and bytecount with header size */
6703 	first->gso_segs = skb_shinfo(skb)->gso_segs;
6704 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
6705 
6706 	/* mss_l4len_id: use 0 as index for TSO */
6707 	mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6708 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6709 
6710 	/* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6711 	vlan_macip_lens = skb_network_header_len(skb);
6712 	vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6713 	vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6714 
6715 	ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6716 			  mss_l4len_idx);
6717 
6718 	return 1;
6719 }
6720 
6721 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6722 			  struct ixgbe_tx_buffer *first)
6723 {
6724 	struct sk_buff *skb = first->skb;
6725 	u32 vlan_macip_lens = 0;
6726 	u32 mss_l4len_idx = 0;
6727 	u32 type_tucmd = 0;
6728 
6729 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
6730 		if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6731 		    !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6732 			return;
6733 	} else {
6734 		u8 l4_hdr = 0;
6735 		switch (first->protocol) {
6736 		case htons(ETH_P_IP):
6737 			vlan_macip_lens |= skb_network_header_len(skb);
6738 			type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6739 			l4_hdr = ip_hdr(skb)->protocol;
6740 			break;
6741 		case htons(ETH_P_IPV6):
6742 			vlan_macip_lens |= skb_network_header_len(skb);
6743 			l4_hdr = ipv6_hdr(skb)->nexthdr;
6744 			break;
6745 		default:
6746 			if (unlikely(net_ratelimit())) {
6747 				dev_warn(tx_ring->dev,
6748 				 "partial checksum but proto=%x!\n",
6749 				 first->protocol);
6750 			}
6751 			break;
6752 		}
6753 
6754 		switch (l4_hdr) {
6755 		case IPPROTO_TCP:
6756 			type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6757 			mss_l4len_idx = tcp_hdrlen(skb) <<
6758 					IXGBE_ADVTXD_L4LEN_SHIFT;
6759 			break;
6760 		case IPPROTO_SCTP:
6761 			type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6762 			mss_l4len_idx = sizeof(struct sctphdr) <<
6763 					IXGBE_ADVTXD_L4LEN_SHIFT;
6764 			break;
6765 		case IPPROTO_UDP:
6766 			mss_l4len_idx = sizeof(struct udphdr) <<
6767 					IXGBE_ADVTXD_L4LEN_SHIFT;
6768 			break;
6769 		default:
6770 			if (unlikely(net_ratelimit())) {
6771 				dev_warn(tx_ring->dev,
6772 				 "partial checksum but l4 proto=%x!\n",
6773 				 l4_hdr);
6774 			}
6775 			break;
6776 		}
6777 
6778 		/* update TX checksum flag */
6779 		first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
6780 	}
6781 
6782 	/* vlan_macip_lens: MACLEN, VLAN tag */
6783 	vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6784 	vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6785 
6786 	ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6787 			  type_tucmd, mss_l4len_idx);
6788 }
6789 
6790 #define IXGBE_SET_FLAG(_input, _flag, _result) \
6791 	((_flag <= _result) ? \
6792 	 ((u32)(_input & _flag) * (_result / _flag)) : \
6793 	 ((u32)(_input & _flag) / (_flag / _result)))
6794 
6795 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6796 {
6797 	/* set type for advanced descriptor with frame checksum insertion */
6798 	u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6799 		       IXGBE_ADVTXD_DCMD_DEXT |
6800 		       IXGBE_ADVTXD_DCMD_IFCS;
6801 
6802 	/* set HW vlan bit if vlan is present */
6803 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6804 				   IXGBE_ADVTXD_DCMD_VLE);
6805 
6806 	/* set segmentation enable bits for TSO/FSO */
6807 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6808 				   IXGBE_ADVTXD_DCMD_TSE);
6809 
6810 	/* set timestamp bit if present */
6811 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6812 				   IXGBE_ADVTXD_MAC_TSTAMP);
6813 
6814 	/* insert frame checksum */
6815 	cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
6816 
6817 	return cmd_type;
6818 }
6819 
6820 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6821 				   u32 tx_flags, unsigned int paylen)
6822 {
6823 	u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
6824 
6825 	/* enable L4 checksum for TSO and TX checksum offload */
6826 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6827 					IXGBE_TX_FLAGS_CSUM,
6828 					IXGBE_ADVTXD_POPTS_TXSM);
6829 
6830 	/* enble IPv4 checksum for TSO */
6831 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6832 					IXGBE_TX_FLAGS_IPV4,
6833 					IXGBE_ADVTXD_POPTS_IXSM);
6834 
6835 	/*
6836 	 * Check Context must be set if Tx switch is enabled, which it
6837 	 * always is for case where virtual functions are running
6838 	 */
6839 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6840 					IXGBE_TX_FLAGS_CC,
6841 					IXGBE_ADVTXD_CC);
6842 
6843 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6844 }
6845 
6846 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6847 		       IXGBE_TXD_CMD_RS)
6848 
6849 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6850 			 struct ixgbe_tx_buffer *first,
6851 			 const u8 hdr_len)
6852 {
6853 	struct sk_buff *skb = first->skb;
6854 	struct ixgbe_tx_buffer *tx_buffer;
6855 	union ixgbe_adv_tx_desc *tx_desc;
6856 	struct skb_frag_struct *frag;
6857 	dma_addr_t dma;
6858 	unsigned int data_len, size;
6859 	u32 tx_flags = first->tx_flags;
6860 	u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
6861 	u16 i = tx_ring->next_to_use;
6862 
6863 	tx_desc = IXGBE_TX_DESC(tx_ring, i);
6864 
6865 	ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6866 
6867 	size = skb_headlen(skb);
6868 	data_len = skb->data_len;
6869 
6870 #ifdef IXGBE_FCOE
6871 	if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6872 		if (data_len < sizeof(struct fcoe_crc_eof)) {
6873 			size -= sizeof(struct fcoe_crc_eof) - data_len;
6874 			data_len = 0;
6875 		} else {
6876 			data_len -= sizeof(struct fcoe_crc_eof);
6877 		}
6878 	}
6879 
6880 #endif
6881 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6882 
6883 	tx_buffer = first;
6884 
6885 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6886 		if (dma_mapping_error(tx_ring->dev, dma))
6887 			goto dma_error;
6888 
6889 		/* record length, and DMA address */
6890 		dma_unmap_len_set(tx_buffer, len, size);
6891 		dma_unmap_addr_set(tx_buffer, dma, dma);
6892 
6893 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
6894 
6895 		while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
6896 			tx_desc->read.cmd_type_len =
6897 				cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
6898 
6899 			i++;
6900 			tx_desc++;
6901 			if (i == tx_ring->count) {
6902 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6903 				i = 0;
6904 			}
6905 			tx_desc->read.olinfo_status = 0;
6906 
6907 			dma += IXGBE_MAX_DATA_PER_TXD;
6908 			size -= IXGBE_MAX_DATA_PER_TXD;
6909 
6910 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
6911 		}
6912 
6913 		if (likely(!data_len))
6914 			break;
6915 
6916 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6917 
6918 		i++;
6919 		tx_desc++;
6920 		if (i == tx_ring->count) {
6921 			tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6922 			i = 0;
6923 		}
6924 		tx_desc->read.olinfo_status = 0;
6925 
6926 #ifdef IXGBE_FCOE
6927 		size = min_t(unsigned int, data_len, skb_frag_size(frag));
6928 #else
6929 		size = skb_frag_size(frag);
6930 #endif
6931 		data_len -= size;
6932 
6933 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6934 				       DMA_TO_DEVICE);
6935 
6936 		tx_buffer = &tx_ring->tx_buffer_info[i];
6937 	}
6938 
6939 	/* write last descriptor with RS and EOP bits */
6940 	cmd_type |= size | IXGBE_TXD_CMD;
6941 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6942 
6943 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6944 
6945 	/* set the timestamp */
6946 	first->time_stamp = jiffies;
6947 
6948 	/*
6949 	 * Force memory writes to complete before letting h/w know there
6950 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
6951 	 * memory model archs, such as IA-64).
6952 	 *
6953 	 * We also need this memory barrier to make certain all of the
6954 	 * status bits have been updated before next_to_watch is written.
6955 	 */
6956 	wmb();
6957 
6958 	/* set next_to_watch value indicating a packet is present */
6959 	first->next_to_watch = tx_desc;
6960 
6961 	i++;
6962 	if (i == tx_ring->count)
6963 		i = 0;
6964 
6965 	tx_ring->next_to_use = i;
6966 
6967 	/* notify HW of packet */
6968 	ixgbe_write_tail(tx_ring, i);
6969 
6970 	return;
6971 dma_error:
6972 	dev_err(tx_ring->dev, "TX DMA map failed\n");
6973 
6974 	/* clear dma mappings for failed tx_buffer_info map */
6975 	for (;;) {
6976 		tx_buffer = &tx_ring->tx_buffer_info[i];
6977 		ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6978 		if (tx_buffer == first)
6979 			break;
6980 		if (i == 0)
6981 			i = tx_ring->count;
6982 		i--;
6983 	}
6984 
6985 	tx_ring->next_to_use = i;
6986 }
6987 
6988 static void ixgbe_atr(struct ixgbe_ring *ring,
6989 		      struct ixgbe_tx_buffer *first)
6990 {
6991 	struct ixgbe_q_vector *q_vector = ring->q_vector;
6992 	union ixgbe_atr_hash_dword input = { .dword = 0 };
6993 	union ixgbe_atr_hash_dword common = { .dword = 0 };
6994 	union {
6995 		unsigned char *network;
6996 		struct iphdr *ipv4;
6997 		struct ipv6hdr *ipv6;
6998 	} hdr;
6999 	struct tcphdr *th;
7000 	__be16 vlan_id;
7001 
7002 	/* if ring doesn't have a interrupt vector, cannot perform ATR */
7003 	if (!q_vector)
7004 		return;
7005 
7006 	/* do nothing if sampling is disabled */
7007 	if (!ring->atr_sample_rate)
7008 		return;
7009 
7010 	ring->atr_count++;
7011 
7012 	/* snag network header to get L4 type and address */
7013 	hdr.network = skb_network_header(first->skb);
7014 
7015 	/* Currently only IPv4/IPv6 with TCP is supported */
7016 	if ((first->protocol != htons(ETH_P_IPV6) ||
7017 	     hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7018 	    (first->protocol != htons(ETH_P_IP) ||
7019 	     hdr.ipv4->protocol != IPPROTO_TCP))
7020 		return;
7021 
7022 	th = tcp_hdr(first->skb);
7023 
7024 	/* skip this packet since it is invalid or the socket is closing */
7025 	if (!th || th->fin)
7026 		return;
7027 
7028 	/* sample on all syn packets or once every atr sample count */
7029 	if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7030 		return;
7031 
7032 	/* reset sample count */
7033 	ring->atr_count = 0;
7034 
7035 	vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7036 
7037 	/*
7038 	 * src and dst are inverted, think how the receiver sees them
7039 	 *
7040 	 * The input is broken into two sections, a non-compressed section
7041 	 * containing vm_pool, vlan_id, and flow_type.  The rest of the data
7042 	 * is XORed together and stored in the compressed dword.
7043 	 */
7044 	input.formatted.vlan_id = vlan_id;
7045 
7046 	/*
7047 	 * since src port and flex bytes occupy the same word XOR them together
7048 	 * and write the value to source port portion of compressed dword
7049 	 */
7050 	if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7051 		common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7052 	else
7053 		common.port.src ^= th->dest ^ first->protocol;
7054 	common.port.dst ^= th->source;
7055 
7056 	if (first->protocol == htons(ETH_P_IP)) {
7057 		input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7058 		common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7059 	} else {
7060 		input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7061 		common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7062 			     hdr.ipv6->saddr.s6_addr32[1] ^
7063 			     hdr.ipv6->saddr.s6_addr32[2] ^
7064 			     hdr.ipv6->saddr.s6_addr32[3] ^
7065 			     hdr.ipv6->daddr.s6_addr32[0] ^
7066 			     hdr.ipv6->daddr.s6_addr32[1] ^
7067 			     hdr.ipv6->daddr.s6_addr32[2] ^
7068 			     hdr.ipv6->daddr.s6_addr32[3];
7069 	}
7070 
7071 	/* This assumes the Rx queue and Tx queue are bound to the same CPU */
7072 	ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7073 					      input, common, ring->queue_index);
7074 }
7075 
7076 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7077 {
7078 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7079 	/* Herbert's original patch had:
7080 	 *  smp_mb__after_netif_stop_queue();
7081 	 * but since that doesn't exist yet, just open code it. */
7082 	smp_mb();
7083 
7084 	/* We need to check again in a case another CPU has just
7085 	 * made room available. */
7086 	if (likely(ixgbe_desc_unused(tx_ring) < size))
7087 		return -EBUSY;
7088 
7089 	/* A reprieve! - use start_queue because it doesn't call schedule */
7090 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7091 	++tx_ring->tx_stats.restart_queue;
7092 	return 0;
7093 }
7094 
7095 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7096 {
7097 	if (likely(ixgbe_desc_unused(tx_ring) >= size))
7098 		return 0;
7099 	return __ixgbe_maybe_stop_tx(tx_ring, size);
7100 }
7101 
7102 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7103 			      void *accel_priv, select_queue_fallback_t fallback)
7104 {
7105 	struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7106 #ifdef IXGBE_FCOE
7107 	struct ixgbe_adapter *adapter;
7108 	struct ixgbe_ring_feature *f;
7109 	int txq;
7110 #endif
7111 
7112 	if (fwd_adapter)
7113 		return skb->queue_mapping + fwd_adapter->tx_base_queue;
7114 
7115 #ifdef IXGBE_FCOE
7116 
7117 	/*
7118 	 * only execute the code below if protocol is FCoE
7119 	 * or FIP and we have FCoE enabled on the adapter
7120 	 */
7121 	switch (vlan_get_protocol(skb)) {
7122 	case htons(ETH_P_FCOE):
7123 	case htons(ETH_P_FIP):
7124 		adapter = netdev_priv(dev);
7125 
7126 		if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7127 			break;
7128 	default:
7129 		return fallback(dev, skb);
7130 	}
7131 
7132 	f = &adapter->ring_feature[RING_F_FCOE];
7133 
7134 	txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7135 					   smp_processor_id();
7136 
7137 	while (txq >= f->indices)
7138 		txq -= f->indices;
7139 
7140 	return txq + f->offset;
7141 #else
7142 	return fallback(dev, skb);
7143 #endif
7144 }
7145 
7146 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7147 			  struct ixgbe_adapter *adapter,
7148 			  struct ixgbe_ring *tx_ring)
7149 {
7150 	struct ixgbe_tx_buffer *first;
7151 	int tso;
7152 	u32 tx_flags = 0;
7153 	unsigned short f;
7154 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
7155 	__be16 protocol = skb->protocol;
7156 	u8 hdr_len = 0;
7157 
7158 	/*
7159 	 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7160 	 *       + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7161 	 *       + 2 desc gap to keep tail from touching head,
7162 	 *       + 1 desc for context descriptor,
7163 	 * otherwise try next time
7164 	 */
7165 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7166 		count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7167 
7168 	if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7169 		tx_ring->tx_stats.tx_busy++;
7170 		return NETDEV_TX_BUSY;
7171 	}
7172 
7173 	/* record the location of the first descriptor for this packet */
7174 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7175 	first->skb = skb;
7176 	first->bytecount = skb->len;
7177 	first->gso_segs = 1;
7178 
7179 	/* if we have a HW VLAN tag being added default to the HW one */
7180 	if (vlan_tx_tag_present(skb)) {
7181 		tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7182 		tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7183 	/* else if it is a SW VLAN check the next protocol and store the tag */
7184 	} else if (protocol == htons(ETH_P_8021Q)) {
7185 		struct vlan_hdr *vhdr, _vhdr;
7186 		vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7187 		if (!vhdr)
7188 			goto out_drop;
7189 
7190 		protocol = vhdr->h_vlan_encapsulated_proto;
7191 		tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7192 				  IXGBE_TX_FLAGS_VLAN_SHIFT;
7193 		tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7194 	}
7195 
7196 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
7197 		     !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7198 					    &adapter->state))) {
7199 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7200 		tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7201 
7202 		/* schedule check for Tx timestamp */
7203 		adapter->ptp_tx_skb = skb_get(skb);
7204 		adapter->ptp_tx_start = jiffies;
7205 		schedule_work(&adapter->ptp_tx_work);
7206 	}
7207 
7208 	skb_tx_timestamp(skb);
7209 
7210 #ifdef CONFIG_PCI_IOV
7211 	/*
7212 	 * Use the l2switch_enable flag - would be false if the DMA
7213 	 * Tx switch had been disabled.
7214 	 */
7215 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7216 		tx_flags |= IXGBE_TX_FLAGS_CC;
7217 
7218 #endif
7219 	/* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7220 	if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7221 	    ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7222 	     (skb->priority != TC_PRIO_CONTROL))) {
7223 		tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7224 		tx_flags |= (skb->priority & 0x7) <<
7225 					IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7226 		if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7227 			struct vlan_ethhdr *vhdr;
7228 
7229 			if (skb_cow_head(skb, 0))
7230 				goto out_drop;
7231 			vhdr = (struct vlan_ethhdr *)skb->data;
7232 			vhdr->h_vlan_TCI = htons(tx_flags >>
7233 						 IXGBE_TX_FLAGS_VLAN_SHIFT);
7234 		} else {
7235 			tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7236 		}
7237 	}
7238 
7239 	/* record initial flags and protocol */
7240 	first->tx_flags = tx_flags;
7241 	first->protocol = protocol;
7242 
7243 #ifdef IXGBE_FCOE
7244 	/* setup tx offload for FCoE */
7245 	if ((protocol == htons(ETH_P_FCOE)) &&
7246 	    (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7247 		tso = ixgbe_fso(tx_ring, first, &hdr_len);
7248 		if (tso < 0)
7249 			goto out_drop;
7250 
7251 		goto xmit_fcoe;
7252 	}
7253 
7254 #endif /* IXGBE_FCOE */
7255 	tso = ixgbe_tso(tx_ring, first, &hdr_len);
7256 	if (tso < 0)
7257 		goto out_drop;
7258 	else if (!tso)
7259 		ixgbe_tx_csum(tx_ring, first);
7260 
7261 	/* add the ATR filter if ATR is on */
7262 	if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7263 		ixgbe_atr(tx_ring, first);
7264 
7265 #ifdef IXGBE_FCOE
7266 xmit_fcoe:
7267 #endif /* IXGBE_FCOE */
7268 	ixgbe_tx_map(tx_ring, first, hdr_len);
7269 
7270 	ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7271 
7272 	return NETDEV_TX_OK;
7273 
7274 out_drop:
7275 	dev_kfree_skb_any(first->skb);
7276 	first->skb = NULL;
7277 
7278 	return NETDEV_TX_OK;
7279 }
7280 
7281 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7282 				      struct net_device *netdev,
7283 				      struct ixgbe_ring *ring)
7284 {
7285 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7286 	struct ixgbe_ring *tx_ring;
7287 
7288 	/*
7289 	 * The minimum packet size for olinfo paylen is 17 so pad the skb
7290 	 * in order to meet this minimum size requirement.
7291 	 */
7292 	if (unlikely(skb->len < 17)) {
7293 		if (skb_pad(skb, 17 - skb->len))
7294 			return NETDEV_TX_OK;
7295 		skb->len = 17;
7296 		skb_set_tail_pointer(skb, 17);
7297 	}
7298 
7299 	tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7300 
7301 	return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7302 }
7303 
7304 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7305 				    struct net_device *netdev)
7306 {
7307 	return __ixgbe_xmit_frame(skb, netdev, NULL);
7308 }
7309 
7310 /**
7311  * ixgbe_set_mac - Change the Ethernet Address of the NIC
7312  * @netdev: network interface device structure
7313  * @p: pointer to an address structure
7314  *
7315  * Returns 0 on success, negative on failure
7316  **/
7317 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7318 {
7319 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7320 	struct ixgbe_hw *hw = &adapter->hw;
7321 	struct sockaddr *addr = p;
7322 	int ret;
7323 
7324 	if (!is_valid_ether_addr(addr->sa_data))
7325 		return -EADDRNOTAVAIL;
7326 
7327 	ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7328 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7329 	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7330 
7331 	ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7332 	return ret > 0 ? 0 : ret;
7333 }
7334 
7335 static int
7336 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7337 {
7338 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7339 	struct ixgbe_hw *hw = &adapter->hw;
7340 	u16 value;
7341 	int rc;
7342 
7343 	if (prtad != hw->phy.mdio.prtad)
7344 		return -EINVAL;
7345 	rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7346 	if (!rc)
7347 		rc = value;
7348 	return rc;
7349 }
7350 
7351 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7352 			    u16 addr, u16 value)
7353 {
7354 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7355 	struct ixgbe_hw *hw = &adapter->hw;
7356 
7357 	if (prtad != hw->phy.mdio.prtad)
7358 		return -EINVAL;
7359 	return hw->phy.ops.write_reg(hw, addr, devad, value);
7360 }
7361 
7362 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7363 {
7364 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7365 
7366 	switch (cmd) {
7367 	case SIOCSHWTSTAMP:
7368 		return ixgbe_ptp_set_ts_config(adapter, req);
7369 	case SIOCGHWTSTAMP:
7370 		return ixgbe_ptp_get_ts_config(adapter, req);
7371 	default:
7372 		return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7373 	}
7374 }
7375 
7376 /**
7377  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7378  * netdev->dev_addrs
7379  * @netdev: network interface device structure
7380  *
7381  * Returns non-zero on failure
7382  **/
7383 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7384 {
7385 	int err = 0;
7386 	struct ixgbe_adapter *adapter = netdev_priv(dev);
7387 	struct ixgbe_hw *hw = &adapter->hw;
7388 
7389 	if (is_valid_ether_addr(hw->mac.san_addr)) {
7390 		rtnl_lock();
7391 		err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7392 		rtnl_unlock();
7393 
7394 		/* update SAN MAC vmdq pool selection */
7395 		hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7396 	}
7397 	return err;
7398 }
7399 
7400 /**
7401  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7402  * netdev->dev_addrs
7403  * @netdev: network interface device structure
7404  *
7405  * Returns non-zero on failure
7406  **/
7407 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7408 {
7409 	int err = 0;
7410 	struct ixgbe_adapter *adapter = netdev_priv(dev);
7411 	struct ixgbe_mac_info *mac = &adapter->hw.mac;
7412 
7413 	if (is_valid_ether_addr(mac->san_addr)) {
7414 		rtnl_lock();
7415 		err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7416 		rtnl_unlock();
7417 	}
7418 	return err;
7419 }
7420 
7421 #ifdef CONFIG_NET_POLL_CONTROLLER
7422 /*
7423  * Polling 'interrupt' - used by things like netconsole to send skbs
7424  * without having to re-enable interrupts. It's not called while
7425  * the interrupt routine is executing.
7426  */
7427 static void ixgbe_netpoll(struct net_device *netdev)
7428 {
7429 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7430 	int i;
7431 
7432 	/* if interface is down do nothing */
7433 	if (test_bit(__IXGBE_DOWN, &adapter->state))
7434 		return;
7435 
7436 	adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7437 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7438 		for (i = 0; i < adapter->num_q_vectors; i++)
7439 			ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7440 	} else {
7441 		ixgbe_intr(adapter->pdev->irq, netdev);
7442 	}
7443 	adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7444 }
7445 
7446 #endif
7447 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7448 						   struct rtnl_link_stats64 *stats)
7449 {
7450 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7451 	int i;
7452 
7453 	rcu_read_lock();
7454 	for (i = 0; i < adapter->num_rx_queues; i++) {
7455 		struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7456 		u64 bytes, packets;
7457 		unsigned int start;
7458 
7459 		if (ring) {
7460 			do {
7461 				start = u64_stats_fetch_begin_irq(&ring->syncp);
7462 				packets = ring->stats.packets;
7463 				bytes   = ring->stats.bytes;
7464 			} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7465 			stats->rx_packets += packets;
7466 			stats->rx_bytes   += bytes;
7467 		}
7468 	}
7469 
7470 	for (i = 0; i < adapter->num_tx_queues; i++) {
7471 		struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7472 		u64 bytes, packets;
7473 		unsigned int start;
7474 
7475 		if (ring) {
7476 			do {
7477 				start = u64_stats_fetch_begin_irq(&ring->syncp);
7478 				packets = ring->stats.packets;
7479 				bytes   = ring->stats.bytes;
7480 			} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7481 			stats->tx_packets += packets;
7482 			stats->tx_bytes   += bytes;
7483 		}
7484 	}
7485 	rcu_read_unlock();
7486 	/* following stats updated by ixgbe_watchdog_task() */
7487 	stats->multicast	= netdev->stats.multicast;
7488 	stats->rx_errors	= netdev->stats.rx_errors;
7489 	stats->rx_length_errors	= netdev->stats.rx_length_errors;
7490 	stats->rx_crc_errors	= netdev->stats.rx_crc_errors;
7491 	stats->rx_missed_errors	= netdev->stats.rx_missed_errors;
7492 	return stats;
7493 }
7494 
7495 #ifdef CONFIG_IXGBE_DCB
7496 /**
7497  * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7498  * @adapter: pointer to ixgbe_adapter
7499  * @tc: number of traffic classes currently enabled
7500  *
7501  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7502  * 802.1Q priority maps to a packet buffer that exists.
7503  */
7504 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7505 {
7506 	struct ixgbe_hw *hw = &adapter->hw;
7507 	u32 reg, rsave;
7508 	int i;
7509 
7510 	/* 82598 have a static priority to TC mapping that can not
7511 	 * be changed so no validation is needed.
7512 	 */
7513 	if (hw->mac.type == ixgbe_mac_82598EB)
7514 		return;
7515 
7516 	reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7517 	rsave = reg;
7518 
7519 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7520 		u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7521 
7522 		/* If up2tc is out of bounds default to zero */
7523 		if (up2tc > tc)
7524 			reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7525 	}
7526 
7527 	if (reg != rsave)
7528 		IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7529 
7530 	return;
7531 }
7532 
7533 /**
7534  * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7535  * @adapter: Pointer to adapter struct
7536  *
7537  * Populate the netdev user priority to tc map
7538  */
7539 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7540 {
7541 	struct net_device *dev = adapter->netdev;
7542 	struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7543 	struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7544 	u8 prio;
7545 
7546 	for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7547 		u8 tc = 0;
7548 
7549 		if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7550 			tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7551 		else if (ets)
7552 			tc = ets->prio_tc[prio];
7553 
7554 		netdev_set_prio_tc_map(dev, prio, tc);
7555 	}
7556 }
7557 
7558 #endif /* CONFIG_IXGBE_DCB */
7559 /**
7560  * ixgbe_setup_tc - configure net_device for multiple traffic classes
7561  *
7562  * @netdev: net device to configure
7563  * @tc: number of traffic classes to enable
7564  */
7565 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7566 {
7567 	struct ixgbe_adapter *adapter = netdev_priv(dev);
7568 	struct ixgbe_hw *hw = &adapter->hw;
7569 	bool pools;
7570 
7571 	/* Hardware supports up to 8 traffic classes */
7572 	if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7573 	    (hw->mac.type == ixgbe_mac_82598EB &&
7574 	     tc < MAX_TRAFFIC_CLASS))
7575 		return -EINVAL;
7576 
7577 	pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7578 	if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7579 		return -EBUSY;
7580 
7581 	/* Hardware has to reinitialize queues and interrupts to
7582 	 * match packet buffer alignment. Unfortunately, the
7583 	 * hardware is not flexible enough to do this dynamically.
7584 	 */
7585 	if (netif_running(dev))
7586 		ixgbe_close(dev);
7587 	ixgbe_clear_interrupt_scheme(adapter);
7588 
7589 #ifdef CONFIG_IXGBE_DCB
7590 	if (tc) {
7591 		netdev_set_num_tc(dev, tc);
7592 		ixgbe_set_prio_tc_map(adapter);
7593 
7594 		adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7595 
7596 		if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7597 			adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7598 			adapter->hw.fc.requested_mode = ixgbe_fc_none;
7599 		}
7600 	} else {
7601 		netdev_reset_tc(dev);
7602 
7603 		if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7604 			adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7605 
7606 		adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7607 
7608 		adapter->temp_dcb_cfg.pfc_mode_enable = false;
7609 		adapter->dcb_cfg.pfc_mode_enable = false;
7610 	}
7611 
7612 	ixgbe_validate_rtr(adapter, tc);
7613 
7614 #endif /* CONFIG_IXGBE_DCB */
7615 	ixgbe_init_interrupt_scheme(adapter);
7616 
7617 	if (netif_running(dev))
7618 		return ixgbe_open(dev);
7619 
7620 	return 0;
7621 }
7622 
7623 #ifdef CONFIG_PCI_IOV
7624 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7625 {
7626 	struct net_device *netdev = adapter->netdev;
7627 
7628 	rtnl_lock();
7629 	ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7630 	rtnl_unlock();
7631 }
7632 
7633 #endif
7634 void ixgbe_do_reset(struct net_device *netdev)
7635 {
7636 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7637 
7638 	if (netif_running(netdev))
7639 		ixgbe_reinit_locked(adapter);
7640 	else
7641 		ixgbe_reset(adapter);
7642 }
7643 
7644 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7645 					    netdev_features_t features)
7646 {
7647 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7648 
7649 	/* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7650 	if (!(features & NETIF_F_RXCSUM))
7651 		features &= ~NETIF_F_LRO;
7652 
7653 	/* Turn off LRO if not RSC capable */
7654 	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7655 		features &= ~NETIF_F_LRO;
7656 
7657 	return features;
7658 }
7659 
7660 static int ixgbe_set_features(struct net_device *netdev,
7661 			      netdev_features_t features)
7662 {
7663 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
7664 	netdev_features_t changed = netdev->features ^ features;
7665 	bool need_reset = false;
7666 
7667 	/* Make sure RSC matches LRO, reset if change */
7668 	if (!(features & NETIF_F_LRO)) {
7669 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7670 			need_reset = true;
7671 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7672 	} else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7673 		   !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7674 		if (adapter->rx_itr_setting == 1 ||
7675 		    adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7676 			adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7677 			need_reset = true;
7678 		} else if ((changed ^ features) & NETIF_F_LRO) {
7679 			e_info(probe, "rx-usecs set too low, "
7680 			       "disabling RSC\n");
7681 		}
7682 	}
7683 
7684 	/*
7685 	 * Check if Flow Director n-tuple support was enabled or disabled.  If
7686 	 * the state changed, we need to reset.
7687 	 */
7688 	switch (features & NETIF_F_NTUPLE) {
7689 	case NETIF_F_NTUPLE:
7690 		/* turn off ATR, enable perfect filters and reset */
7691 		if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7692 			need_reset = true;
7693 
7694 		adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7695 		adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7696 		break;
7697 	default:
7698 		/* turn off perfect filters, enable ATR and reset */
7699 		if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7700 			need_reset = true;
7701 
7702 		adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7703 
7704 		/* We cannot enable ATR if SR-IOV is enabled */
7705 		if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7706 			break;
7707 
7708 		/* We cannot enable ATR if we have 2 or more traffic classes */
7709 		if (netdev_get_num_tc(netdev) > 1)
7710 			break;
7711 
7712 		/* We cannot enable ATR if RSS is disabled */
7713 		if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7714 			break;
7715 
7716 		/* A sample rate of 0 indicates ATR disabled */
7717 		if (!adapter->atr_sample_rate)
7718 			break;
7719 
7720 		adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7721 		break;
7722 	}
7723 
7724 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
7725 		ixgbe_vlan_strip_enable(adapter);
7726 	else
7727 		ixgbe_vlan_strip_disable(adapter);
7728 
7729 	if (changed & NETIF_F_RXALL)
7730 		need_reset = true;
7731 
7732 	netdev->features = features;
7733 	if (need_reset)
7734 		ixgbe_do_reset(netdev);
7735 
7736 	return 0;
7737 }
7738 
7739 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
7740 			     struct net_device *dev,
7741 			     const unsigned char *addr,
7742 			     u16 flags)
7743 {
7744 	struct ixgbe_adapter *adapter = netdev_priv(dev);
7745 	int err;
7746 
7747 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7748 		return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
7749 
7750 	/* Hardware does not support aging addresses so if a
7751 	 * ndm_state is given only allow permanent addresses
7752 	 */
7753 	if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
7754 		pr_info("%s: FDB only supports static addresses\n",
7755 			ixgbe_driver_name);
7756 		return -EINVAL;
7757 	}
7758 
7759 	if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
7760 		u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7761 
7762 		if (netdev_uc_count(dev) < rar_uc_entries)
7763 			err = dev_uc_add_excl(dev, addr);
7764 		else
7765 			err = -ENOMEM;
7766 	} else if (is_multicast_ether_addr(addr)) {
7767 		err = dev_mc_add_excl(dev, addr);
7768 	} else {
7769 		err = -EINVAL;
7770 	}
7771 
7772 	/* Only return duplicate errors if NLM_F_EXCL is set */
7773 	if (err == -EEXIST && !(flags & NLM_F_EXCL))
7774 		err = 0;
7775 
7776 	return err;
7777 }
7778 
7779 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7780 				    struct nlmsghdr *nlh)
7781 {
7782 	struct ixgbe_adapter *adapter = netdev_priv(dev);
7783 	struct nlattr *attr, *br_spec;
7784 	int rem;
7785 
7786 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7787 		return -EOPNOTSUPP;
7788 
7789 	br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7790 
7791 	nla_for_each_nested(attr, br_spec, rem) {
7792 		__u16 mode;
7793 		u32 reg = 0;
7794 
7795 		if (nla_type(attr) != IFLA_BRIDGE_MODE)
7796 			continue;
7797 
7798 		mode = nla_get_u16(attr);
7799 		if (mode == BRIDGE_MODE_VEPA) {
7800 			reg = 0;
7801 			adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7802 		} else if (mode == BRIDGE_MODE_VEB) {
7803 			reg = IXGBE_PFDTXGSWC_VT_LBEN;
7804 			adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7805 		} else
7806 			return -EINVAL;
7807 
7808 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7809 
7810 		e_info(drv, "enabling bridge mode: %s\n",
7811 			mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7812 	}
7813 
7814 	return 0;
7815 }
7816 
7817 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
7818 				    struct net_device *dev,
7819 				    u32 filter_mask)
7820 {
7821 	struct ixgbe_adapter *adapter = netdev_priv(dev);
7822 	u16 mode;
7823 
7824 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7825 		return 0;
7826 
7827 	if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
7828 		mode = BRIDGE_MODE_VEB;
7829 	else
7830 		mode = BRIDGE_MODE_VEPA;
7831 
7832 	return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7833 }
7834 
7835 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7836 {
7837 	struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7838 	struct ixgbe_adapter *adapter = netdev_priv(pdev);
7839 	unsigned int limit;
7840 	int pool, err;
7841 
7842 #ifdef CONFIG_RPS
7843 	if (vdev->num_rx_queues != vdev->num_tx_queues) {
7844 		netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7845 			    vdev->name);
7846 		return ERR_PTR(-EINVAL);
7847 	}
7848 #endif
7849 	/* Check for hardware restriction on number of rx/tx queues */
7850 	if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
7851 	    vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7852 		netdev_info(pdev,
7853 			    "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7854 			    pdev->name);
7855 		return ERR_PTR(-EINVAL);
7856 	}
7857 
7858 	if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7859 	      adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7860 	    (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7861 		return ERR_PTR(-EBUSY);
7862 
7863 	fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7864 	if (!fwd_adapter)
7865 		return ERR_PTR(-ENOMEM);
7866 
7867 	pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7868 	adapter->num_rx_pools++;
7869 	set_bit(pool, &adapter->fwd_bitmask);
7870 	limit = find_last_bit(&adapter->fwd_bitmask, 32);
7871 
7872 	/* Enable VMDq flag so device will be set in VM mode */
7873 	adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
7874 	adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7875 	adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
7876 
7877 	/* Force reinit of ring allocation with VMDQ enabled */
7878 	err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7879 	if (err)
7880 		goto fwd_add_err;
7881 	fwd_adapter->pool = pool;
7882 	fwd_adapter->real_adapter = adapter;
7883 	err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7884 	if (err)
7885 		goto fwd_add_err;
7886 	netif_tx_start_all_queues(vdev);
7887 	return fwd_adapter;
7888 fwd_add_err:
7889 	/* unwind counter and free adapter struct */
7890 	netdev_info(pdev,
7891 		    "%s: dfwd hardware acceleration failed\n", vdev->name);
7892 	clear_bit(pool, &adapter->fwd_bitmask);
7893 	adapter->num_rx_pools--;
7894 	kfree(fwd_adapter);
7895 	return ERR_PTR(err);
7896 }
7897 
7898 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7899 {
7900 	struct ixgbe_fwd_adapter *fwd_adapter = priv;
7901 	struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
7902 	unsigned int limit;
7903 
7904 	clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7905 	adapter->num_rx_pools--;
7906 
7907 	limit = find_last_bit(&adapter->fwd_bitmask, 32);
7908 	adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
7909 	ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7910 	ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7911 	netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7912 		   fwd_adapter->pool, adapter->num_rx_pools,
7913 		   fwd_adapter->rx_base_queue,
7914 		   fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7915 		   adapter->fwd_bitmask);
7916 	kfree(fwd_adapter);
7917 }
7918 
7919 static const struct net_device_ops ixgbe_netdev_ops = {
7920 	.ndo_open		= ixgbe_open,
7921 	.ndo_stop		= ixgbe_close,
7922 	.ndo_start_xmit		= ixgbe_xmit_frame,
7923 	.ndo_select_queue	= ixgbe_select_queue,
7924 	.ndo_set_rx_mode	= ixgbe_set_rx_mode,
7925 	.ndo_validate_addr	= eth_validate_addr,
7926 	.ndo_set_mac_address	= ixgbe_set_mac,
7927 	.ndo_change_mtu		= ixgbe_change_mtu,
7928 	.ndo_tx_timeout		= ixgbe_tx_timeout,
7929 	.ndo_vlan_rx_add_vid	= ixgbe_vlan_rx_add_vid,
7930 	.ndo_vlan_rx_kill_vid	= ixgbe_vlan_rx_kill_vid,
7931 	.ndo_do_ioctl		= ixgbe_ioctl,
7932 	.ndo_set_vf_mac		= ixgbe_ndo_set_vf_mac,
7933 	.ndo_set_vf_vlan	= ixgbe_ndo_set_vf_vlan,
7934 	.ndo_set_vf_rate	= ixgbe_ndo_set_vf_bw,
7935 	.ndo_set_vf_spoofchk	= ixgbe_ndo_set_vf_spoofchk,
7936 	.ndo_get_vf_config	= ixgbe_ndo_get_vf_config,
7937 	.ndo_get_stats64	= ixgbe_get_stats64,
7938 #ifdef CONFIG_IXGBE_DCB
7939 	.ndo_setup_tc		= ixgbe_setup_tc,
7940 #endif
7941 #ifdef CONFIG_NET_POLL_CONTROLLER
7942 	.ndo_poll_controller	= ixgbe_netpoll,
7943 #endif
7944 #ifdef CONFIG_NET_RX_BUSY_POLL
7945 	.ndo_busy_poll		= ixgbe_low_latency_recv,
7946 #endif
7947 #ifdef IXGBE_FCOE
7948 	.ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7949 	.ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7950 	.ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7951 	.ndo_fcoe_enable = ixgbe_fcoe_enable,
7952 	.ndo_fcoe_disable = ixgbe_fcoe_disable,
7953 	.ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7954 	.ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
7955 #endif /* IXGBE_FCOE */
7956 	.ndo_set_features = ixgbe_set_features,
7957 	.ndo_fix_features = ixgbe_fix_features,
7958 	.ndo_fdb_add		= ixgbe_ndo_fdb_add,
7959 	.ndo_bridge_setlink	= ixgbe_ndo_bridge_setlink,
7960 	.ndo_bridge_getlink	= ixgbe_ndo_bridge_getlink,
7961 	.ndo_dfwd_add_station	= ixgbe_fwd_add,
7962 	.ndo_dfwd_del_station	= ixgbe_fwd_del,
7963 };
7964 
7965 /**
7966  * ixgbe_enumerate_functions - Get the number of ports this device has
7967  * @adapter: adapter structure
7968  *
7969  * This function enumerates the phsyical functions co-located on a single slot,
7970  * in order to determine how many ports a device has. This is most useful in
7971  * determining the required GT/s of PCIe bandwidth necessary for optimal
7972  * performance.
7973  **/
7974 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7975 {
7976 	struct list_head *entry;
7977 	int physfns = 0;
7978 
7979 	/* Some cards can not use the generic count PCIe functions method,
7980 	 * because they are behind a parent switch, so we hardcode these with
7981 	 * the correct number of functions.
7982 	 */
7983 	if (ixgbe_pcie_from_parent(&adapter->hw)) {
7984 		physfns = 4;
7985 	} else {
7986 		list_for_each(entry, &adapter->pdev->bus_list) {
7987 			struct pci_dev *pdev =
7988 				list_entry(entry, struct pci_dev, bus_list);
7989 			/* don't count virtual functions */
7990 			if (!pdev->is_virtfn)
7991 				physfns++;
7992 		}
7993 	}
7994 
7995 	return physfns;
7996 }
7997 
7998 /**
7999  * ixgbe_wol_supported - Check whether device supports WoL
8000  * @hw: hw specific details
8001  * @device_id: the device ID
8002  * @subdev_id: the subsystem device ID
8003  *
8004  * This function is used by probe and ethtool to determine
8005  * which devices have WoL support
8006  *
8007  **/
8008 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8009 			u16 subdevice_id)
8010 {
8011 	struct ixgbe_hw *hw = &adapter->hw;
8012 	u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8013 	int is_wol_supported = 0;
8014 
8015 	switch (device_id) {
8016 	case IXGBE_DEV_ID_82599_SFP:
8017 		/* Only these subdevices could supports WOL */
8018 		switch (subdevice_id) {
8019 		case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8020 		case IXGBE_SUBDEV_ID_82599_560FLR:
8021 			/* only support first port */
8022 			if (hw->bus.func != 0)
8023 				break;
8024 		case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8025 		case IXGBE_SUBDEV_ID_82599_SFP:
8026 		case IXGBE_SUBDEV_ID_82599_RNDC:
8027 		case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8028 		case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8029 			is_wol_supported = 1;
8030 			break;
8031 		}
8032 		break;
8033 	case IXGBE_DEV_ID_82599EN_SFP:
8034 		/* Only this subdevice supports WOL */
8035 		switch (subdevice_id) {
8036 		case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8037 			is_wol_supported = 1;
8038 			break;
8039 		}
8040 		break;
8041 	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8042 		/* All except this subdevice support WOL */
8043 		if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8044 			is_wol_supported = 1;
8045 		break;
8046 	case IXGBE_DEV_ID_82599_KX4:
8047 		is_wol_supported = 1;
8048 		break;
8049 	case IXGBE_DEV_ID_X540T:
8050 	case IXGBE_DEV_ID_X540T1:
8051 		/* check eeprom to see if enabled wol */
8052 		if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8053 		    ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8054 		     (hw->bus.func == 0))) {
8055 			is_wol_supported = 1;
8056 		}
8057 		break;
8058 	}
8059 
8060 	return is_wol_supported;
8061 }
8062 
8063 /**
8064  * ixgbe_probe - Device Initialization Routine
8065  * @pdev: PCI device information struct
8066  * @ent: entry in ixgbe_pci_tbl
8067  *
8068  * Returns 0 on success, negative on failure
8069  *
8070  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8071  * The OS initialization, configuring of the adapter private structure,
8072  * and a hardware reset occur.
8073  **/
8074 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8075 {
8076 	struct net_device *netdev;
8077 	struct ixgbe_adapter *adapter = NULL;
8078 	struct ixgbe_hw *hw;
8079 	const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
8080 	static int cards_found;
8081 	int i, err, pci_using_dac, expected_gts;
8082 	unsigned int indices = MAX_TX_QUEUES;
8083 	u8 part_str[IXGBE_PBANUM_LENGTH];
8084 #ifdef IXGBE_FCOE
8085 	u16 device_caps;
8086 #endif
8087 	u32 eec;
8088 
8089 	/* Catch broken hardware that put the wrong VF device ID in
8090 	 * the PCIe SR-IOV capability.
8091 	 */
8092 	if (pdev->is_virtfn) {
8093 		WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8094 		     pci_name(pdev), pdev->vendor, pdev->device);
8095 		return -EINVAL;
8096 	}
8097 
8098 	err = pci_enable_device_mem(pdev);
8099 	if (err)
8100 		return err;
8101 
8102 	if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8103 		pci_using_dac = 1;
8104 	} else {
8105 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8106 		if (err) {
8107 			dev_err(&pdev->dev,
8108 				"No usable DMA configuration, aborting\n");
8109 			goto err_dma;
8110 		}
8111 		pci_using_dac = 0;
8112 	}
8113 
8114 	err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8115 					   IORESOURCE_MEM), ixgbe_driver_name);
8116 	if (err) {
8117 		dev_err(&pdev->dev,
8118 			"pci_request_selected_regions failed 0x%x\n", err);
8119 		goto err_pci_reg;
8120 	}
8121 
8122 	pci_enable_pcie_error_reporting(pdev);
8123 
8124 	pci_set_master(pdev);
8125 	pci_save_state(pdev);
8126 
8127 	if (ii->mac == ixgbe_mac_82598EB) {
8128 #ifdef CONFIG_IXGBE_DCB
8129 		/* 8 TC w/ 4 queues per TC */
8130 		indices = 4 * MAX_TRAFFIC_CLASS;
8131 #else
8132 		indices = IXGBE_MAX_RSS_INDICES;
8133 #endif
8134 	}
8135 
8136 	netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8137 	if (!netdev) {
8138 		err = -ENOMEM;
8139 		goto err_alloc_etherdev;
8140 	}
8141 
8142 	SET_NETDEV_DEV(netdev, &pdev->dev);
8143 
8144 	adapter = netdev_priv(netdev);
8145 	pci_set_drvdata(pdev, adapter);
8146 
8147 	adapter->netdev = netdev;
8148 	adapter->pdev = pdev;
8149 	hw = &adapter->hw;
8150 	hw->back = adapter;
8151 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8152 
8153 	hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8154 			      pci_resource_len(pdev, 0));
8155 	adapter->io_addr = hw->hw_addr;
8156 	if (!hw->hw_addr) {
8157 		err = -EIO;
8158 		goto err_ioremap;
8159 	}
8160 
8161 	netdev->netdev_ops = &ixgbe_netdev_ops;
8162 	ixgbe_set_ethtool_ops(netdev);
8163 	netdev->watchdog_timeo = 5 * HZ;
8164 	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
8165 
8166 	adapter->bd_number = cards_found;
8167 
8168 	/* Setup hw api */
8169 	memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8170 	hw->mac.type  = ii->mac;
8171 
8172 	/* EEPROM */
8173 	memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8174 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8175 	if (ixgbe_removed(hw->hw_addr)) {
8176 		err = -EIO;
8177 		goto err_ioremap;
8178 	}
8179 	/* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8180 	if (!(eec & (1 << 8)))
8181 		hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8182 
8183 	/* PHY */
8184 	memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8185 	hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8186 	/* ixgbe_identify_phy_generic will set prtad and mmds properly */
8187 	hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8188 	hw->phy.mdio.mmds = 0;
8189 	hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8190 	hw->phy.mdio.dev = netdev;
8191 	hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8192 	hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8193 
8194 	ii->get_invariants(hw);
8195 
8196 	/* setup the private structure */
8197 	err = ixgbe_sw_init(adapter);
8198 	if (err)
8199 		goto err_sw_init;
8200 
8201 	/* Make it possible the adapter to be woken up via WOL */
8202 	switch (adapter->hw.mac.type) {
8203 	case ixgbe_mac_82599EB:
8204 	case ixgbe_mac_X540:
8205 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8206 		break;
8207 	default:
8208 		break;
8209 	}
8210 
8211 	/*
8212 	 * If there is a fan on this device and it has failed log the
8213 	 * failure.
8214 	 */
8215 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8216 		u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8217 		if (esdp & IXGBE_ESDP_SDP1)
8218 			e_crit(probe, "Fan has stopped, replace the adapter\n");
8219 	}
8220 
8221 	if (allow_unsupported_sfp)
8222 		hw->allow_unsupported_sfp = allow_unsupported_sfp;
8223 
8224 	/* reset_hw fills in the perm_addr as well */
8225 	hw->phy.reset_if_overtemp = true;
8226 	err = hw->mac.ops.reset_hw(hw);
8227 	hw->phy.reset_if_overtemp = false;
8228 	if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8229 	    hw->mac.type == ixgbe_mac_82598EB) {
8230 		err = 0;
8231 	} else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8232 		e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8233 		e_dev_err("Reload the driver after installing a supported module.\n");
8234 		goto err_sw_init;
8235 	} else if (err) {
8236 		e_dev_err("HW Init failed: %d\n", err);
8237 		goto err_sw_init;
8238 	}
8239 
8240 #ifdef CONFIG_PCI_IOV
8241 	/* SR-IOV not supported on the 82598 */
8242 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8243 		goto skip_sriov;
8244 	/* Mailbox */
8245 	ixgbe_init_mbx_params_pf(hw);
8246 	memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8247 	pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8248 	ixgbe_enable_sriov(adapter);
8249 skip_sriov:
8250 
8251 #endif
8252 	netdev->features = NETIF_F_SG |
8253 			   NETIF_F_IP_CSUM |
8254 			   NETIF_F_IPV6_CSUM |
8255 			   NETIF_F_HW_VLAN_CTAG_TX |
8256 			   NETIF_F_HW_VLAN_CTAG_RX |
8257 			   NETIF_F_HW_VLAN_CTAG_FILTER |
8258 			   NETIF_F_TSO |
8259 			   NETIF_F_TSO6 |
8260 			   NETIF_F_RXHASH |
8261 			   NETIF_F_RXCSUM;
8262 
8263 	netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8264 
8265 	switch (adapter->hw.mac.type) {
8266 	case ixgbe_mac_82599EB:
8267 	case ixgbe_mac_X540:
8268 		netdev->features |= NETIF_F_SCTP_CSUM;
8269 		netdev->hw_features |= NETIF_F_SCTP_CSUM |
8270 				       NETIF_F_NTUPLE;
8271 		break;
8272 	default:
8273 		break;
8274 	}
8275 
8276 	netdev->hw_features |= NETIF_F_RXALL;
8277 
8278 	netdev->vlan_features |= NETIF_F_TSO;
8279 	netdev->vlan_features |= NETIF_F_TSO6;
8280 	netdev->vlan_features |= NETIF_F_IP_CSUM;
8281 	netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8282 	netdev->vlan_features |= NETIF_F_SG;
8283 
8284 	netdev->priv_flags |= IFF_UNICAST_FLT;
8285 	netdev->priv_flags |= IFF_SUPP_NOFCS;
8286 
8287 #ifdef CONFIG_IXGBE_DCB
8288 	netdev->dcbnl_ops = &dcbnl_ops;
8289 #endif
8290 
8291 #ifdef IXGBE_FCOE
8292 	if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8293 		unsigned int fcoe_l;
8294 
8295 		if (hw->mac.ops.get_device_caps) {
8296 			hw->mac.ops.get_device_caps(hw, &device_caps);
8297 			if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8298 				adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8299 		}
8300 
8301 
8302 		fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8303 		adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8304 
8305 		netdev->features |= NETIF_F_FSO |
8306 				    NETIF_F_FCOE_CRC;
8307 
8308 		netdev->vlan_features |= NETIF_F_FSO |
8309 					 NETIF_F_FCOE_CRC |
8310 					 NETIF_F_FCOE_MTU;
8311 	}
8312 #endif /* IXGBE_FCOE */
8313 	if (pci_using_dac) {
8314 		netdev->features |= NETIF_F_HIGHDMA;
8315 		netdev->vlan_features |= NETIF_F_HIGHDMA;
8316 	}
8317 
8318 	if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8319 		netdev->hw_features |= NETIF_F_LRO;
8320 	if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8321 		netdev->features |= NETIF_F_LRO;
8322 
8323 	/* make sure the EEPROM is good */
8324 	if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8325 		e_dev_err("The EEPROM Checksum Is Not Valid\n");
8326 		err = -EIO;
8327 		goto err_sw_init;
8328 	}
8329 
8330 	memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8331 
8332 	if (!is_valid_ether_addr(netdev->dev_addr)) {
8333 		e_dev_err("invalid MAC address\n");
8334 		err = -EIO;
8335 		goto err_sw_init;
8336 	}
8337 
8338 	ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8339 
8340 	setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8341 		    (unsigned long) adapter);
8342 
8343 	if (ixgbe_removed(hw->hw_addr)) {
8344 		err = -EIO;
8345 		goto err_sw_init;
8346 	}
8347 	INIT_WORK(&adapter->service_task, ixgbe_service_task);
8348 	set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8349 	clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8350 
8351 	err = ixgbe_init_interrupt_scheme(adapter);
8352 	if (err)
8353 		goto err_sw_init;
8354 
8355 	/* WOL not supported for all devices */
8356 	adapter->wol = 0;
8357 	hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8358 	hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8359 						pdev->subsystem_device);
8360 	if (hw->wol_enabled)
8361 		adapter->wol = IXGBE_WUFC_MAG;
8362 
8363 	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8364 
8365 	/* save off EEPROM version number */
8366 	hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8367 	hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8368 
8369 	/* pick up the PCI bus settings for reporting later */
8370 	hw->mac.ops.get_bus_info(hw);
8371 	if (ixgbe_pcie_from_parent(hw))
8372 		ixgbe_get_parent_bus_info(adapter);
8373 
8374 	/* calculate the expected PCIe bandwidth required for optimal
8375 	 * performance. Note that some older parts will never have enough
8376 	 * bandwidth due to being older generation PCIe parts. We clamp these
8377 	 * parts to ensure no warning is displayed if it can't be fixed.
8378 	 */
8379 	switch (hw->mac.type) {
8380 	case ixgbe_mac_82598EB:
8381 		expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8382 		break;
8383 	default:
8384 		expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8385 		break;
8386 	}
8387 	ixgbe_check_minimum_link(adapter, expected_gts);
8388 
8389 	err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8390 	if (err)
8391 		strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8392 	if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8393 		e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8394 			   hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8395 			   part_str);
8396 	else
8397 		e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8398 			   hw->mac.type, hw->phy.type, part_str);
8399 
8400 	e_dev_info("%pM\n", netdev->dev_addr);
8401 
8402 	/* reset the hardware with the new settings */
8403 	err = hw->mac.ops.start_hw(hw);
8404 	if (err == IXGBE_ERR_EEPROM_VERSION) {
8405 		/* We are running on a pre-production device, log a warning */
8406 		e_dev_warn("This device is a pre-production adapter/LOM. "
8407 			   "Please be aware there may be issues associated "
8408 			   "with your hardware.  If you are experiencing "
8409 			   "problems please contact your Intel or hardware "
8410 			   "representative who provided you with this "
8411 			   "hardware.\n");
8412 	}
8413 	strcpy(netdev->name, "eth%d");
8414 	err = register_netdev(netdev);
8415 	if (err)
8416 		goto err_register;
8417 
8418 	/* power down the optics for 82599 SFP+ fiber */
8419 	if (hw->mac.ops.disable_tx_laser)
8420 		hw->mac.ops.disable_tx_laser(hw);
8421 
8422 	/* carrier off reporting is important to ethtool even BEFORE open */
8423 	netif_carrier_off(netdev);
8424 
8425 #ifdef CONFIG_IXGBE_DCA
8426 	if (dca_add_requester(&pdev->dev) == 0) {
8427 		adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8428 		ixgbe_setup_dca(adapter);
8429 	}
8430 #endif
8431 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8432 		e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8433 		for (i = 0; i < adapter->num_vfs; i++)
8434 			ixgbe_vf_configuration(pdev, (i | 0x10000000));
8435 	}
8436 
8437 	/* firmware requires driver version to be 0xFFFFFFFF
8438 	 * since os does not support feature
8439 	 */
8440 	if (hw->mac.ops.set_fw_drv_ver)
8441 		hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8442 					   0xFF);
8443 
8444 	/* add san mac addr to netdev */
8445 	ixgbe_add_sanmac_netdev(netdev);
8446 
8447 	e_dev_info("%s\n", ixgbe_default_device_descr);
8448 	cards_found++;
8449 
8450 #ifdef CONFIG_IXGBE_HWMON
8451 	if (ixgbe_sysfs_init(adapter))
8452 		e_err(probe, "failed to allocate sysfs resources\n");
8453 #endif /* CONFIG_IXGBE_HWMON */
8454 
8455 	ixgbe_dbg_adapter_init(adapter);
8456 
8457 	/* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8458 	if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
8459 		hw->mac.ops.setup_link(hw,
8460 			IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8461 			true);
8462 
8463 	return 0;
8464 
8465 err_register:
8466 	ixgbe_release_hw_control(adapter);
8467 	ixgbe_clear_interrupt_scheme(adapter);
8468 err_sw_init:
8469 	ixgbe_disable_sriov(adapter);
8470 	adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
8471 	iounmap(adapter->io_addr);
8472 	kfree(adapter->mac_table);
8473 err_ioremap:
8474 	free_netdev(netdev);
8475 err_alloc_etherdev:
8476 	pci_release_selected_regions(pdev,
8477 				     pci_select_bars(pdev, IORESOURCE_MEM));
8478 err_pci_reg:
8479 err_dma:
8480 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8481 		pci_disable_device(pdev);
8482 	return err;
8483 }
8484 
8485 /**
8486  * ixgbe_remove - Device Removal Routine
8487  * @pdev: PCI device information struct
8488  *
8489  * ixgbe_remove is called by the PCI subsystem to alert the driver
8490  * that it should release a PCI device.  The could be caused by a
8491  * Hot-Plug event, or because the driver is going to be removed from
8492  * memory.
8493  **/
8494 static void ixgbe_remove(struct pci_dev *pdev)
8495 {
8496 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8497 	struct net_device *netdev = adapter->netdev;
8498 
8499 	ixgbe_dbg_adapter_exit(adapter);
8500 
8501 	set_bit(__IXGBE_REMOVING, &adapter->state);
8502 	cancel_work_sync(&adapter->service_task);
8503 
8504 
8505 #ifdef CONFIG_IXGBE_DCA
8506 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8507 		adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8508 		dca_remove_requester(&pdev->dev);
8509 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8510 	}
8511 
8512 #endif
8513 #ifdef CONFIG_IXGBE_HWMON
8514 	ixgbe_sysfs_exit(adapter);
8515 #endif /* CONFIG_IXGBE_HWMON */
8516 
8517 	/* remove the added san mac */
8518 	ixgbe_del_sanmac_netdev(netdev);
8519 
8520 	if (netdev->reg_state == NETREG_REGISTERED)
8521 		unregister_netdev(netdev);
8522 
8523 #ifdef CONFIG_PCI_IOV
8524 	/*
8525 	 * Only disable SR-IOV on unload if the user specified the now
8526 	 * deprecated max_vfs module parameter.
8527 	 */
8528 	if (max_vfs)
8529 		ixgbe_disable_sriov(adapter);
8530 #endif
8531 	ixgbe_clear_interrupt_scheme(adapter);
8532 
8533 	ixgbe_release_hw_control(adapter);
8534 
8535 #ifdef CONFIG_DCB
8536 	kfree(adapter->ixgbe_ieee_pfc);
8537 	kfree(adapter->ixgbe_ieee_ets);
8538 
8539 #endif
8540 	iounmap(adapter->io_addr);
8541 	pci_release_selected_regions(pdev, pci_select_bars(pdev,
8542 				     IORESOURCE_MEM));
8543 
8544 	e_dev_info("complete\n");
8545 
8546 	kfree(adapter->mac_table);
8547 	free_netdev(netdev);
8548 
8549 	pci_disable_pcie_error_reporting(pdev);
8550 
8551 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8552 		pci_disable_device(pdev);
8553 }
8554 
8555 /**
8556  * ixgbe_io_error_detected - called when PCI error is detected
8557  * @pdev: Pointer to PCI device
8558  * @state: The current pci connection state
8559  *
8560  * This function is called after a PCI bus error affecting
8561  * this device has been detected.
8562  */
8563 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
8564 						pci_channel_state_t state)
8565 {
8566 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8567 	struct net_device *netdev = adapter->netdev;
8568 
8569 #ifdef CONFIG_PCI_IOV
8570 	struct ixgbe_hw *hw = &adapter->hw;
8571 	struct pci_dev *bdev, *vfdev;
8572 	u32 dw0, dw1, dw2, dw3;
8573 	int vf, pos;
8574 	u16 req_id, pf_func;
8575 
8576 	if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8577 	    adapter->num_vfs == 0)
8578 		goto skip_bad_vf_detection;
8579 
8580 	bdev = pdev->bus->self;
8581 	while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
8582 		bdev = bdev->bus->self;
8583 
8584 	if (!bdev)
8585 		goto skip_bad_vf_detection;
8586 
8587 	pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8588 	if (!pos)
8589 		goto skip_bad_vf_detection;
8590 
8591 	dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8592 	dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8593 	dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8594 	dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8595 	if (ixgbe_removed(hw->hw_addr))
8596 		goto skip_bad_vf_detection;
8597 
8598 	req_id = dw1 >> 16;
8599 	/* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8600 	if (!(req_id & 0x0080))
8601 		goto skip_bad_vf_detection;
8602 
8603 	pf_func = req_id & 0x01;
8604 	if ((pf_func & 1) == (pdev->devfn & 1)) {
8605 		unsigned int device_id;
8606 
8607 		vf = (req_id & 0x7F) >> 1;
8608 		e_dev_err("VF %d has caused a PCIe error\n", vf);
8609 		e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8610 				"%8.8x\tdw3: %8.8x\n",
8611 		dw0, dw1, dw2, dw3);
8612 		switch (adapter->hw.mac.type) {
8613 		case ixgbe_mac_82599EB:
8614 			device_id = IXGBE_82599_VF_DEVICE_ID;
8615 			break;
8616 		case ixgbe_mac_X540:
8617 			device_id = IXGBE_X540_VF_DEVICE_ID;
8618 			break;
8619 		default:
8620 			device_id = 0;
8621 			break;
8622 		}
8623 
8624 		/* Find the pci device of the offending VF */
8625 		vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
8626 		while (vfdev) {
8627 			if (vfdev->devfn == (req_id & 0xFF))
8628 				break;
8629 			vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
8630 					       device_id, vfdev);
8631 		}
8632 		/*
8633 		 * There's a slim chance the VF could have been hot plugged,
8634 		 * so if it is no longer present we don't need to issue the
8635 		 * VFLR.  Just clean up the AER in that case.
8636 		 */
8637 		if (vfdev) {
8638 			e_dev_err("Issuing VFLR to VF %d\n", vf);
8639 			pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8640 			/* Free device reference count */
8641 			pci_dev_put(vfdev);
8642 		}
8643 
8644 		pci_cleanup_aer_uncorrect_error_status(pdev);
8645 	}
8646 
8647 	/*
8648 	 * Even though the error may have occurred on the other port
8649 	 * we still need to increment the vf error reference count for
8650 	 * both ports because the I/O resume function will be called
8651 	 * for both of them.
8652 	 */
8653 	adapter->vferr_refcount++;
8654 
8655 	return PCI_ERS_RESULT_RECOVERED;
8656 
8657 skip_bad_vf_detection:
8658 #endif /* CONFIG_PCI_IOV */
8659 	if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8660 		return PCI_ERS_RESULT_DISCONNECT;
8661 
8662 	rtnl_lock();
8663 	netif_device_detach(netdev);
8664 
8665 	if (state == pci_channel_io_perm_failure) {
8666 		rtnl_unlock();
8667 		return PCI_ERS_RESULT_DISCONNECT;
8668 	}
8669 
8670 	if (netif_running(netdev))
8671 		ixgbe_down(adapter);
8672 
8673 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8674 		pci_disable_device(pdev);
8675 	rtnl_unlock();
8676 
8677 	/* Request a slot reset. */
8678 	return PCI_ERS_RESULT_NEED_RESET;
8679 }
8680 
8681 /**
8682  * ixgbe_io_slot_reset - called after the pci bus has been reset.
8683  * @pdev: Pointer to PCI device
8684  *
8685  * Restart the card from scratch, as if from a cold-boot.
8686  */
8687 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8688 {
8689 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8690 	pci_ers_result_t result;
8691 	int err;
8692 
8693 	if (pci_enable_device_mem(pdev)) {
8694 		e_err(probe, "Cannot re-enable PCI device after reset.\n");
8695 		result = PCI_ERS_RESULT_DISCONNECT;
8696 	} else {
8697 		smp_mb__before_atomic();
8698 		clear_bit(__IXGBE_DISABLED, &adapter->state);
8699 		adapter->hw.hw_addr = adapter->io_addr;
8700 		pci_set_master(pdev);
8701 		pci_restore_state(pdev);
8702 		pci_save_state(pdev);
8703 
8704 		pci_wake_from_d3(pdev, false);
8705 
8706 		ixgbe_reset(adapter);
8707 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8708 		result = PCI_ERS_RESULT_RECOVERED;
8709 	}
8710 
8711 	err = pci_cleanup_aer_uncorrect_error_status(pdev);
8712 	if (err) {
8713 		e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8714 			  "failed 0x%0x\n", err);
8715 		/* non-fatal, continue */
8716 	}
8717 
8718 	return result;
8719 }
8720 
8721 /**
8722  * ixgbe_io_resume - called when traffic can start flowing again.
8723  * @pdev: Pointer to PCI device
8724  *
8725  * This callback is called when the error recovery driver tells us that
8726  * its OK to resume normal operation.
8727  */
8728 static void ixgbe_io_resume(struct pci_dev *pdev)
8729 {
8730 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8731 	struct net_device *netdev = adapter->netdev;
8732 
8733 #ifdef CONFIG_PCI_IOV
8734 	if (adapter->vferr_refcount) {
8735 		e_info(drv, "Resuming after VF err\n");
8736 		adapter->vferr_refcount--;
8737 		return;
8738 	}
8739 
8740 #endif
8741 	if (netif_running(netdev))
8742 		ixgbe_up(adapter);
8743 
8744 	netif_device_attach(netdev);
8745 }
8746 
8747 static const struct pci_error_handlers ixgbe_err_handler = {
8748 	.error_detected = ixgbe_io_error_detected,
8749 	.slot_reset = ixgbe_io_slot_reset,
8750 	.resume = ixgbe_io_resume,
8751 };
8752 
8753 static struct pci_driver ixgbe_driver = {
8754 	.name     = ixgbe_driver_name,
8755 	.id_table = ixgbe_pci_tbl,
8756 	.probe    = ixgbe_probe,
8757 	.remove   = ixgbe_remove,
8758 #ifdef CONFIG_PM
8759 	.suspend  = ixgbe_suspend,
8760 	.resume   = ixgbe_resume,
8761 #endif
8762 	.shutdown = ixgbe_shutdown,
8763 	.sriov_configure = ixgbe_pci_sriov_configure,
8764 	.err_handler = &ixgbe_err_handler
8765 };
8766 
8767 /**
8768  * ixgbe_init_module - Driver Registration Routine
8769  *
8770  * ixgbe_init_module is the first routine called when the driver is
8771  * loaded. All it does is register with the PCI subsystem.
8772  **/
8773 static int __init ixgbe_init_module(void)
8774 {
8775 	int ret;
8776 	pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8777 	pr_info("%s\n", ixgbe_copyright);
8778 
8779 	ixgbe_dbg_init();
8780 
8781 	ret = pci_register_driver(&ixgbe_driver);
8782 	if (ret) {
8783 		ixgbe_dbg_exit();
8784 		return ret;
8785 	}
8786 
8787 #ifdef CONFIG_IXGBE_DCA
8788 	dca_register_notify(&dca_notifier);
8789 #endif
8790 
8791 	return 0;
8792 }
8793 
8794 module_init(ixgbe_init_module);
8795 
8796 /**
8797  * ixgbe_exit_module - Driver Exit Cleanup Routine
8798  *
8799  * ixgbe_exit_module is called just before the driver is removed
8800  * from memory.
8801  **/
8802 static void __exit ixgbe_exit_module(void)
8803 {
8804 #ifdef CONFIG_IXGBE_DCA
8805 	dca_unregister_notify(&dca_notifier);
8806 #endif
8807 	pci_unregister_driver(&ixgbe_driver);
8808 
8809 	ixgbe_dbg_exit();
8810 
8811 	rcu_barrier(); /* Wait for completion of call_rcu()'s */
8812 }
8813 
8814 #ifdef CONFIG_IXGBE_DCA
8815 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8816 			    void *p)
8817 {
8818 	int ret_val;
8819 
8820 	ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8821 					 __ixgbe_notify_dca);
8822 
8823 	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8824 }
8825 
8826 #endif /* CONFIG_IXGBE_DCA */
8827 
8828 module_exit(ixgbe_exit_module);
8829 
8830 /* ixgbe_main.c */
8831