1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <generated/utsrelease.h> 32 #include <scsi/fc/fc_fcoe.h> 33 #include <net/udp_tunnel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/vxlan.h> 38 #include <net/mpls.h> 39 #include <net/netdev_queues.h> 40 #include <net/xdp_sock_drv.h> 41 #include <net/xfrm.h> 42 43 #include "ixgbe.h" 44 #include "ixgbe_common.h" 45 #include "ixgbe_dcb_82599.h" 46 #include "ixgbe_phy.h" 47 #include "ixgbe_sriov.h" 48 #include "ixgbe_model.h" 49 #include "ixgbe_txrx_common.h" 50 51 char ixgbe_driver_name[] = "ixgbe"; 52 static const char ixgbe_driver_string[] = 53 "Intel(R) 10 Gigabit PCI Express Network Driver"; 54 #ifdef IXGBE_FCOE 55 char ixgbe_default_device_descr[] = 56 "Intel(R) 10 Gigabit Network Connection"; 57 #else 58 static char ixgbe_default_device_descr[] = 59 "Intel(R) 10 Gigabit Network Connection"; 60 #endif 61 static const char ixgbe_copyright[] = 62 "Copyright (c) 1999-2016 Intel Corporation."; 63 64 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 65 66 static const struct ixgbe_info *ixgbe_info_tbl[] = { 67 [board_82598] = &ixgbe_82598_info, 68 [board_82599] = &ixgbe_82599_info, 69 [board_X540] = &ixgbe_X540_info, 70 [board_X550] = &ixgbe_X550_info, 71 [board_X550EM_x] = &ixgbe_X550EM_x_info, 72 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 73 [board_x550em_a] = &ixgbe_x550em_a_info, 74 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 75 }; 76 77 /* ixgbe_pci_tbl - PCI Device ID Table 78 * 79 * Wildcard entries (PCI_ANY_ID) should come last 80 * Last entry must be all 0s 81 * 82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 83 * Class, Class Mask, private data (not used) } 84 */ 85 static const struct pci_device_id ixgbe_pci_tbl[] = { 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 133 /* required last entry */ 134 {0, } 135 }; 136 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 137 138 #ifdef CONFIG_IXGBE_DCA 139 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 140 void *p); 141 static struct notifier_block dca_notifier = { 142 .notifier_call = ixgbe_notify_dca, 143 .next = NULL, 144 .priority = 0 145 }; 146 #endif 147 148 #ifdef CONFIG_PCI_IOV 149 static unsigned int max_vfs; 150 module_param(max_vfs, uint, 0); 151 MODULE_PARM_DESC(max_vfs, 152 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 153 #endif /* CONFIG_PCI_IOV */ 154 155 static bool allow_unsupported_sfp; 156 module_param(allow_unsupported_sfp, bool, 0); 157 MODULE_PARM_DESC(allow_unsupported_sfp, 158 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 159 160 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 161 static int debug = -1; 162 module_param(debug, int, 0); 163 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 164 165 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 166 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 167 MODULE_LICENSE("GPL v2"); 168 169 DEFINE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 170 EXPORT_SYMBOL(ixgbe_xdp_locking_key); 171 172 static struct workqueue_struct *ixgbe_wq; 173 174 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 175 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 176 177 static const struct net_device_ops ixgbe_netdev_ops; 178 179 static bool netif_is_ixgbe(struct net_device *dev) 180 { 181 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 182 } 183 184 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 185 u32 reg, u16 *value) 186 { 187 struct pci_dev *parent_dev; 188 struct pci_bus *parent_bus; 189 190 parent_bus = adapter->pdev->bus->parent; 191 if (!parent_bus) 192 return -1; 193 194 parent_dev = parent_bus->self; 195 if (!parent_dev) 196 return -1; 197 198 if (!pci_is_pcie(parent_dev)) 199 return -1; 200 201 pcie_capability_read_word(parent_dev, reg, value); 202 if (*value == IXGBE_FAILED_READ_CFG_WORD && 203 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 204 return -1; 205 return 0; 206 } 207 208 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 209 { 210 struct ixgbe_hw *hw = &adapter->hw; 211 u16 link_status = 0; 212 int err; 213 214 hw->bus.type = ixgbe_bus_type_pci_express; 215 216 /* Get the negotiated link width and speed from PCI config space of the 217 * parent, as this device is behind a switch 218 */ 219 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 220 221 /* assume caller will handle error case */ 222 if (err) 223 return err; 224 225 hw->bus.width = ixgbe_convert_bus_width(link_status); 226 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 227 228 return 0; 229 } 230 231 /** 232 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent 233 * @hw: hw specific details 234 * 235 * This function is used by probe to determine whether a device's PCI-Express 236 * bandwidth details should be gathered from the parent bus instead of from the 237 * device. Used to ensure that various locations all have the correct device ID 238 * checks. 239 */ 240 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 241 { 242 switch (hw->device_id) { 243 case IXGBE_DEV_ID_82599_SFP_SF_QP: 244 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 245 return true; 246 default: 247 return false; 248 } 249 } 250 251 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 252 int expected_gts) 253 { 254 struct ixgbe_hw *hw = &adapter->hw; 255 struct pci_dev *pdev; 256 257 /* Some devices are not connected over PCIe and thus do not negotiate 258 * speed. These devices do not have valid bus info, and thus any report 259 * we generate may not be correct. 260 */ 261 if (hw->bus.type == ixgbe_bus_type_internal) 262 return; 263 264 /* determine whether to use the parent device */ 265 if (ixgbe_pcie_from_parent(&adapter->hw)) 266 pdev = adapter->pdev->bus->parent->self; 267 else 268 pdev = adapter->pdev; 269 270 pcie_print_link_status(pdev); 271 } 272 273 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 274 { 275 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 276 !test_bit(__IXGBE_REMOVING, &adapter->state) && 277 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 278 queue_work(ixgbe_wq, &adapter->service_task); 279 } 280 281 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 282 { 283 struct ixgbe_adapter *adapter = hw->back; 284 285 if (!hw->hw_addr) 286 return; 287 hw->hw_addr = NULL; 288 e_dev_err("Adapter removed\n"); 289 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 290 ixgbe_service_event_schedule(adapter); 291 } 292 293 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 294 { 295 u8 __iomem *reg_addr; 296 u32 value; 297 int i; 298 299 reg_addr = READ_ONCE(hw->hw_addr); 300 if (ixgbe_removed(reg_addr)) 301 return IXGBE_FAILED_READ_REG; 302 303 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 304 * so perform several status register reads to determine if the adapter 305 * has been removed. 306 */ 307 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 308 value = readl(reg_addr + IXGBE_STATUS); 309 if (value != IXGBE_FAILED_READ_REG) 310 break; 311 mdelay(3); 312 } 313 314 if (value == IXGBE_FAILED_READ_REG) 315 ixgbe_remove_adapter(hw); 316 else 317 value = readl(reg_addr + reg); 318 return value; 319 } 320 321 /** 322 * ixgbe_read_reg - Read from device register 323 * @hw: hw specific details 324 * @reg: offset of register to read 325 * 326 * Returns : value read or IXGBE_FAILED_READ_REG if removed 327 * 328 * This function is used to read device registers. It checks for device 329 * removal by confirming any read that returns all ones by checking the 330 * status register value for all ones. This function avoids reading from 331 * the hardware if a removal was previously detected in which case it 332 * returns IXGBE_FAILED_READ_REG (all ones). 333 */ 334 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 335 { 336 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 337 u32 value; 338 339 if (ixgbe_removed(reg_addr)) 340 return IXGBE_FAILED_READ_REG; 341 if (unlikely(hw->phy.nw_mng_if_sel & 342 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 343 struct ixgbe_adapter *adapter; 344 int i; 345 346 for (i = 0; i < 200; ++i) { 347 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 348 if (likely(!value)) 349 goto writes_completed; 350 if (value == IXGBE_FAILED_READ_REG) { 351 ixgbe_remove_adapter(hw); 352 return IXGBE_FAILED_READ_REG; 353 } 354 udelay(5); 355 } 356 357 adapter = hw->back; 358 e_warn(hw, "register writes incomplete %08x\n", value); 359 } 360 361 writes_completed: 362 value = readl(reg_addr + reg); 363 if (unlikely(value == IXGBE_FAILED_READ_REG)) 364 value = ixgbe_check_remove(hw, reg); 365 return value; 366 } 367 368 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 369 { 370 u16 value; 371 372 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 373 if (value == IXGBE_FAILED_READ_CFG_WORD) { 374 ixgbe_remove_adapter(hw); 375 return true; 376 } 377 return false; 378 } 379 380 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 381 { 382 struct ixgbe_adapter *adapter = hw->back; 383 u16 value; 384 385 if (ixgbe_removed(hw->hw_addr)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 pci_read_config_word(adapter->pdev, reg, &value); 388 if (value == IXGBE_FAILED_READ_CFG_WORD && 389 ixgbe_check_cfg_remove(hw, adapter->pdev)) 390 return IXGBE_FAILED_READ_CFG_WORD; 391 return value; 392 } 393 394 #ifdef CONFIG_PCI_IOV 395 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 396 { 397 struct ixgbe_adapter *adapter = hw->back; 398 u32 value; 399 400 if (ixgbe_removed(hw->hw_addr)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 pci_read_config_dword(adapter->pdev, reg, &value); 403 if (value == IXGBE_FAILED_READ_CFG_DWORD && 404 ixgbe_check_cfg_remove(hw, adapter->pdev)) 405 return IXGBE_FAILED_READ_CFG_DWORD; 406 return value; 407 } 408 #endif /* CONFIG_PCI_IOV */ 409 410 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 411 { 412 struct ixgbe_adapter *adapter = hw->back; 413 414 if (ixgbe_removed(hw->hw_addr)) 415 return; 416 pci_write_config_word(adapter->pdev, reg, value); 417 } 418 419 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 420 { 421 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 422 423 /* flush memory to make sure state is correct before next watchdog */ 424 smp_mb__before_atomic(); 425 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 426 } 427 428 struct ixgbe_reg_info { 429 u32 ofs; 430 char *name; 431 }; 432 433 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 434 435 /* General Registers */ 436 {IXGBE_CTRL, "CTRL"}, 437 {IXGBE_STATUS, "STATUS"}, 438 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 439 440 /* Interrupt Registers */ 441 {IXGBE_EICR, "EICR"}, 442 443 /* RX Registers */ 444 {IXGBE_SRRCTL(0), "SRRCTL"}, 445 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 446 {IXGBE_RDLEN(0), "RDLEN"}, 447 {IXGBE_RDH(0), "RDH"}, 448 {IXGBE_RDT(0), "RDT"}, 449 {IXGBE_RXDCTL(0), "RXDCTL"}, 450 {IXGBE_RDBAL(0), "RDBAL"}, 451 {IXGBE_RDBAH(0), "RDBAH"}, 452 453 /* TX Registers */ 454 {IXGBE_TDBAL(0), "TDBAL"}, 455 {IXGBE_TDBAH(0), "TDBAH"}, 456 {IXGBE_TDLEN(0), "TDLEN"}, 457 {IXGBE_TDH(0), "TDH"}, 458 {IXGBE_TDT(0), "TDT"}, 459 {IXGBE_TXDCTL(0), "TXDCTL"}, 460 461 /* List Terminator */ 462 { .name = NULL } 463 }; 464 465 466 /* 467 * ixgbe_regdump - register printout routine 468 */ 469 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 470 { 471 int i; 472 char rname[16]; 473 u32 regs[64]; 474 475 switch (reginfo->ofs) { 476 case IXGBE_SRRCTL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 479 break; 480 case IXGBE_DCA_RXCTRL(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 483 break; 484 case IXGBE_RDLEN(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 487 break; 488 case IXGBE_RDH(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 491 break; 492 case IXGBE_RDT(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 495 break; 496 case IXGBE_RXDCTL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 499 break; 500 case IXGBE_RDBAL(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 503 break; 504 case IXGBE_RDBAH(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 507 break; 508 case IXGBE_TDBAL(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 511 break; 512 case IXGBE_TDBAH(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 515 break; 516 case IXGBE_TDLEN(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 519 break; 520 case IXGBE_TDH(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 523 break; 524 case IXGBE_TDT(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 527 break; 528 case IXGBE_TXDCTL(0): 529 for (i = 0; i < 64; i++) 530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 531 break; 532 default: 533 pr_info("%-15s %08x\n", 534 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 535 return; 536 } 537 538 i = 0; 539 while (i < 64) { 540 int j; 541 char buf[9 * 8 + 1]; 542 char *p = buf; 543 544 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 545 for (j = 0; j < 8; j++) 546 p += sprintf(p, " %08x", regs[i++]); 547 pr_err("%-15s%s\n", rname, buf); 548 } 549 550 } 551 552 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 553 { 554 struct ixgbe_tx_buffer *tx_buffer; 555 556 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 557 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 558 n, ring->next_to_use, ring->next_to_clean, 559 (u64)dma_unmap_addr(tx_buffer, dma), 560 dma_unmap_len(tx_buffer, len), 561 tx_buffer->next_to_watch, 562 (u64)tx_buffer->time_stamp); 563 } 564 565 /* 566 * ixgbe_dump - Print registers, tx-rings and rx-rings 567 */ 568 static void ixgbe_dump(struct ixgbe_adapter *adapter) 569 { 570 struct net_device *netdev = adapter->netdev; 571 struct ixgbe_hw *hw = &adapter->hw; 572 struct ixgbe_reg_info *reginfo; 573 int n = 0; 574 struct ixgbe_ring *ring; 575 struct ixgbe_tx_buffer *tx_buffer; 576 union ixgbe_adv_tx_desc *tx_desc; 577 struct my_u0 { u64 a; u64 b; } *u0; 578 struct ixgbe_ring *rx_ring; 579 union ixgbe_adv_rx_desc *rx_desc; 580 struct ixgbe_rx_buffer *rx_buffer_info; 581 int i = 0; 582 583 if (!netif_msg_hw(adapter)) 584 return; 585 586 /* Print netdevice Info */ 587 if (netdev) { 588 dev_info(&adapter->pdev->dev, "Net device Info\n"); 589 pr_info("Device Name state " 590 "trans_start\n"); 591 pr_info("%-15s %016lX %016lX\n", 592 netdev->name, 593 netdev->state, 594 dev_trans_start(netdev)); 595 } 596 597 /* Print Registers */ 598 dev_info(&adapter->pdev->dev, "Register Dump\n"); 599 pr_info(" Register Name Value\n"); 600 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 601 reginfo->name; reginfo++) { 602 ixgbe_regdump(hw, reginfo); 603 } 604 605 /* Print TX Ring Summary */ 606 if (!netdev || !netif_running(netdev)) 607 return; 608 609 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 610 pr_info(" %s %s %s %s\n", 611 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 612 "leng", "ntw", "timestamp"); 613 for (n = 0; n < adapter->num_tx_queues; n++) { 614 ring = adapter->tx_ring[n]; 615 ixgbe_print_buffer(ring, n); 616 } 617 618 for (n = 0; n < adapter->num_xdp_queues; n++) { 619 ring = adapter->xdp_ring[n]; 620 ixgbe_print_buffer(ring, n); 621 } 622 623 /* Print TX Rings */ 624 if (!netif_msg_tx_done(adapter)) 625 goto rx_ring_summary; 626 627 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 628 629 /* Transmit Descriptor Formats 630 * 631 * 82598 Advanced Transmit Descriptor 632 * +--------------------------------------------------------------+ 633 * 0 | Buffer Address [63:0] | 634 * +--------------------------------------------------------------+ 635 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 636 * +--------------------------------------------------------------+ 637 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 638 * 639 * 82598 Advanced Transmit Descriptor (Write-Back Format) 640 * +--------------------------------------------------------------+ 641 * 0 | RSV [63:0] | 642 * +--------------------------------------------------------------+ 643 * 8 | RSV | STA | NXTSEQ | 644 * +--------------------------------------------------------------+ 645 * 63 36 35 32 31 0 646 * 647 * 82599+ Advanced Transmit Descriptor 648 * +--------------------------------------------------------------+ 649 * 0 | Buffer Address [63:0] | 650 * +--------------------------------------------------------------+ 651 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 652 * +--------------------------------------------------------------+ 653 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 654 * 655 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 656 * +--------------------------------------------------------------+ 657 * 0 | RSV [63:0] | 658 * +--------------------------------------------------------------+ 659 * 8 | RSV | STA | RSV | 660 * +--------------------------------------------------------------+ 661 * 63 36 35 32 31 0 662 */ 663 664 for (n = 0; n < adapter->num_tx_queues; n++) { 665 ring = adapter->tx_ring[n]; 666 pr_info("------------------------------------\n"); 667 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 668 pr_info("------------------------------------\n"); 669 pr_info("%s%s %s %s %s %s\n", 670 "T [desc] [address 63:0 ] ", 671 "[PlPOIdStDDt Ln] [bi->dma ] ", 672 "leng", "ntw", "timestamp", "bi->skb"); 673 674 for (i = 0; ring->desc && (i < ring->count); i++) { 675 tx_desc = IXGBE_TX_DESC(ring, i); 676 tx_buffer = &ring->tx_buffer_info[i]; 677 u0 = (struct my_u0 *)tx_desc; 678 if (dma_unmap_len(tx_buffer, len) > 0) { 679 const char *ring_desc; 680 681 if (i == ring->next_to_use && 682 i == ring->next_to_clean) 683 ring_desc = " NTC/U"; 684 else if (i == ring->next_to_use) 685 ring_desc = " NTU"; 686 else if (i == ring->next_to_clean) 687 ring_desc = " NTC"; 688 else 689 ring_desc = ""; 690 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 691 i, 692 le64_to_cpu((__force __le64)u0->a), 693 le64_to_cpu((__force __le64)u0->b), 694 (u64)dma_unmap_addr(tx_buffer, dma), 695 dma_unmap_len(tx_buffer, len), 696 tx_buffer->next_to_watch, 697 (u64)tx_buffer->time_stamp, 698 tx_buffer->skb, 699 ring_desc); 700 701 if (netif_msg_pktdata(adapter) && 702 tx_buffer->skb) 703 print_hex_dump(KERN_INFO, "", 704 DUMP_PREFIX_ADDRESS, 16, 1, 705 tx_buffer->skb->data, 706 dma_unmap_len(tx_buffer, len), 707 true); 708 } 709 } 710 } 711 712 /* Print RX Rings Summary */ 713 rx_ring_summary: 714 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 715 pr_info("Queue [NTU] [NTC]\n"); 716 for (n = 0; n < adapter->num_rx_queues; n++) { 717 rx_ring = adapter->rx_ring[n]; 718 pr_info("%5d %5X %5X\n", 719 n, rx_ring->next_to_use, rx_ring->next_to_clean); 720 } 721 722 /* Print RX Rings */ 723 if (!netif_msg_rx_status(adapter)) 724 return; 725 726 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 727 728 /* Receive Descriptor Formats 729 * 730 * 82598 Advanced Receive Descriptor (Read) Format 731 * 63 1 0 732 * +-----------------------------------------------------+ 733 * 0 | Packet Buffer Address [63:1] |A0/NSE| 734 * +----------------------------------------------+------+ 735 * 8 | Header Buffer Address [63:1] | DD | 736 * +-----------------------------------------------------+ 737 * 738 * 739 * 82598 Advanced Receive Descriptor (Write-Back) Format 740 * 741 * 63 48 47 32 31 30 21 20 16 15 4 3 0 742 * +------------------------------------------------------+ 743 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 744 * | Packet | IP | | | | Type | Type | 745 * | Checksum | Ident | | | | | | 746 * +------------------------------------------------------+ 747 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 748 * +------------------------------------------------------+ 749 * 63 48 47 32 31 20 19 0 750 * 751 * 82599+ Advanced Receive Descriptor (Read) Format 752 * 63 1 0 753 * +-----------------------------------------------------+ 754 * 0 | Packet Buffer Address [63:1] |A0/NSE| 755 * +----------------------------------------------+------+ 756 * 8 | Header Buffer Address [63:1] | DD | 757 * +-----------------------------------------------------+ 758 * 759 * 760 * 82599+ Advanced Receive Descriptor (Write-Back) Format 761 * 762 * 63 48 47 32 31 30 21 20 17 16 4 3 0 763 * +------------------------------------------------------+ 764 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 765 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 766 * |/ Flow Dir Flt ID | | | | | | 767 * +------------------------------------------------------+ 768 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 769 * +------------------------------------------------------+ 770 * 63 48 47 32 31 20 19 0 771 */ 772 773 for (n = 0; n < adapter->num_rx_queues; n++) { 774 rx_ring = adapter->rx_ring[n]; 775 pr_info("------------------------------------\n"); 776 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 777 pr_info("------------------------------------\n"); 778 pr_info("%s%s%s\n", 779 "R [desc] [ PktBuf A0] ", 780 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 781 "<-- Adv Rx Read format"); 782 pr_info("%s%s%s\n", 783 "RWB[desc] [PcsmIpSHl PtRs] ", 784 "[vl er S cks ln] ---------------- [bi->skb ] ", 785 "<-- Adv Rx Write-Back format"); 786 787 for (i = 0; i < rx_ring->count; i++) { 788 const char *ring_desc; 789 790 if (i == rx_ring->next_to_use) 791 ring_desc = " NTU"; 792 else if (i == rx_ring->next_to_clean) 793 ring_desc = " NTC"; 794 else 795 ring_desc = ""; 796 797 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 798 rx_desc = IXGBE_RX_DESC(rx_ring, i); 799 u0 = (struct my_u0 *)rx_desc; 800 if (rx_desc->wb.upper.length) { 801 /* Descriptor Done */ 802 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 803 i, 804 le64_to_cpu((__force __le64)u0->a), 805 le64_to_cpu((__force __le64)u0->b), 806 rx_buffer_info->skb, 807 ring_desc); 808 } else { 809 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 810 i, 811 le64_to_cpu((__force __le64)u0->a), 812 le64_to_cpu((__force __le64)u0->b), 813 (u64)rx_buffer_info->dma, 814 rx_buffer_info->skb, 815 ring_desc); 816 817 if (netif_msg_pktdata(adapter) && 818 rx_buffer_info->dma) { 819 print_hex_dump(KERN_INFO, "", 820 DUMP_PREFIX_ADDRESS, 16, 1, 821 page_address(rx_buffer_info->page) + 822 rx_buffer_info->page_offset, 823 ixgbe_rx_bufsz(rx_ring), true); 824 } 825 } 826 } 827 } 828 } 829 830 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 831 { 832 u32 ctrl_ext; 833 834 /* Let firmware take over control of h/w */ 835 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 837 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 838 } 839 840 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 841 { 842 u32 ctrl_ext; 843 844 /* Let firmware know the driver has taken over */ 845 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 846 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 847 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 848 } 849 850 /** 851 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 852 * @adapter: pointer to adapter struct 853 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 854 * @queue: queue to map the corresponding interrupt to 855 * @msix_vector: the vector to map to the corresponding queue 856 * 857 */ 858 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 859 u8 queue, u8 msix_vector) 860 { 861 u32 ivar, index; 862 struct ixgbe_hw *hw = &adapter->hw; 863 switch (hw->mac.type) { 864 case ixgbe_mac_82598EB: 865 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 866 if (direction == -1) 867 direction = 0; 868 index = (((direction * 64) + queue) >> 2) & 0x1F; 869 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 870 ivar &= ~(0xFF << (8 * (queue & 0x3))); 871 ivar |= (msix_vector << (8 * (queue & 0x3))); 872 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 873 break; 874 case ixgbe_mac_82599EB: 875 case ixgbe_mac_X540: 876 case ixgbe_mac_X550: 877 case ixgbe_mac_X550EM_x: 878 case ixgbe_mac_x550em_a: 879 if (direction == -1) { 880 /* other causes */ 881 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 882 index = ((queue & 1) * 8); 883 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 884 ivar &= ~(0xFF << index); 885 ivar |= (msix_vector << index); 886 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 887 break; 888 } else { 889 /* tx or rx causes */ 890 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 891 index = ((16 * (queue & 1)) + (8 * direction)); 892 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 893 ivar &= ~(0xFF << index); 894 ivar |= (msix_vector << index); 895 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 896 break; 897 } 898 default: 899 break; 900 } 901 } 902 903 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 904 u64 qmask) 905 { 906 u32 mask; 907 908 switch (adapter->hw.mac.type) { 909 case ixgbe_mac_82598EB: 910 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 912 break; 913 case ixgbe_mac_82599EB: 914 case ixgbe_mac_X540: 915 case ixgbe_mac_X550: 916 case ixgbe_mac_X550EM_x: 917 case ixgbe_mac_x550em_a: 918 mask = (qmask & 0xFFFFFFFF); 919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 920 mask = (qmask >> 32); 921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 922 break; 923 default: 924 break; 925 } 926 } 927 928 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 929 { 930 struct ixgbe_hw *hw = &adapter->hw; 931 struct ixgbe_hw_stats *hwstats = &adapter->stats; 932 int i; 933 u32 data; 934 935 if ((hw->fc.current_mode != ixgbe_fc_full) && 936 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 937 return; 938 939 switch (hw->mac.type) { 940 case ixgbe_mac_82598EB: 941 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 942 break; 943 default: 944 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 945 } 946 hwstats->lxoffrxc += data; 947 948 /* refill credits (no tx hang) if we received xoff */ 949 if (!data) 950 return; 951 952 for (i = 0; i < adapter->num_tx_queues; i++) 953 clear_bit(__IXGBE_HANG_CHECK_ARMED, 954 &adapter->tx_ring[i]->state); 955 956 for (i = 0; i < adapter->num_xdp_queues; i++) 957 clear_bit(__IXGBE_HANG_CHECK_ARMED, 958 &adapter->xdp_ring[i]->state); 959 } 960 961 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 962 { 963 struct ixgbe_hw *hw = &adapter->hw; 964 struct ixgbe_hw_stats *hwstats = &adapter->stats; 965 u32 xoff[8] = {0}; 966 u8 tc; 967 int i; 968 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 969 970 if (adapter->ixgbe_ieee_pfc) 971 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 972 973 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 974 ixgbe_update_xoff_rx_lfc(adapter); 975 return; 976 } 977 978 /* update stats for each tc, only valid with PFC enabled */ 979 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 980 u32 pxoffrxc; 981 982 switch (hw->mac.type) { 983 case ixgbe_mac_82598EB: 984 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 985 break; 986 default: 987 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 988 } 989 hwstats->pxoffrxc[i] += pxoffrxc; 990 /* Get the TC for given UP */ 991 tc = netdev_get_prio_tc_map(adapter->netdev, i); 992 xoff[tc] += pxoffrxc; 993 } 994 995 /* disarm tx queues that have received xoff frames */ 996 for (i = 0; i < adapter->num_tx_queues; i++) { 997 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 998 999 tc = tx_ring->dcb_tc; 1000 if (xoff[tc]) 1001 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1002 } 1003 1004 for (i = 0; i < adapter->num_xdp_queues; i++) { 1005 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1006 1007 tc = xdp_ring->dcb_tc; 1008 if (xoff[tc]) 1009 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1010 } 1011 } 1012 1013 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1014 { 1015 return ring->stats.packets; 1016 } 1017 1018 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1019 { 1020 unsigned int head, tail; 1021 1022 head = ring->next_to_clean; 1023 tail = ring->next_to_use; 1024 1025 return ((head <= tail) ? tail : tail + ring->count) - head; 1026 } 1027 1028 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1029 { 1030 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1031 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1032 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1033 1034 clear_check_for_tx_hang(tx_ring); 1035 1036 /* 1037 * Check for a hung queue, but be thorough. This verifies 1038 * that a transmit has been completed since the previous 1039 * check AND there is at least one packet pending. The 1040 * ARMED bit is set to indicate a potential hang. The 1041 * bit is cleared if a pause frame is received to remove 1042 * false hang detection due to PFC or 802.3x frames. By 1043 * requiring this to fail twice we avoid races with 1044 * pfc clearing the ARMED bit and conditions where we 1045 * run the check_tx_hang logic with a transmit completion 1046 * pending but without time to complete it yet. 1047 */ 1048 if (tx_done_old == tx_done && tx_pending) 1049 /* make sure it is true for two checks in a row */ 1050 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1051 &tx_ring->state); 1052 /* update completed stats and continue */ 1053 tx_ring->tx_stats.tx_done_old = tx_done; 1054 /* reset the countdown */ 1055 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1056 1057 return false; 1058 } 1059 1060 /** 1061 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1062 * @adapter: driver private struct 1063 **/ 1064 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1065 { 1066 1067 /* Do the reset outside of interrupt context */ 1068 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1069 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1070 e_warn(drv, "initiating reset due to tx timeout\n"); 1071 ixgbe_service_event_schedule(adapter); 1072 } 1073 } 1074 1075 /** 1076 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1077 * @netdev: network interface device structure 1078 * @queue_index: Tx queue to set 1079 * @maxrate: desired maximum transmit bitrate 1080 **/ 1081 static int ixgbe_tx_maxrate(struct net_device *netdev, 1082 int queue_index, u32 maxrate) 1083 { 1084 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1085 struct ixgbe_hw *hw = &adapter->hw; 1086 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1087 1088 if (!maxrate) 1089 return 0; 1090 1091 /* Calculate the rate factor values to set */ 1092 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1093 bcnrc_val /= maxrate; 1094 1095 /* clear everything but the rate factor */ 1096 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1097 IXGBE_RTTBCNRC_RF_DEC_MASK; 1098 1099 /* enable the rate scheduler */ 1100 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1101 1102 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1103 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1104 1105 return 0; 1106 } 1107 1108 /** 1109 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1110 * @q_vector: structure containing interrupt and ring information 1111 * @tx_ring: tx ring to clean 1112 * @napi_budget: Used to determine if we are in netpoll 1113 **/ 1114 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1115 struct ixgbe_ring *tx_ring, int napi_budget) 1116 { 1117 struct ixgbe_adapter *adapter = q_vector->adapter; 1118 struct ixgbe_tx_buffer *tx_buffer; 1119 union ixgbe_adv_tx_desc *tx_desc; 1120 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1121 unsigned int budget = q_vector->tx.work_limit; 1122 unsigned int i = tx_ring->next_to_clean; 1123 struct netdev_queue *txq; 1124 1125 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1126 return true; 1127 1128 tx_buffer = &tx_ring->tx_buffer_info[i]; 1129 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1130 i -= tx_ring->count; 1131 1132 do { 1133 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1134 1135 /* if next_to_watch is not set then there is no work pending */ 1136 if (!eop_desc) 1137 break; 1138 1139 /* prevent any other reads prior to eop_desc */ 1140 smp_rmb(); 1141 1142 /* if DD is not set pending work has not been completed */ 1143 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1144 break; 1145 1146 /* clear next_to_watch to prevent false hangs */ 1147 tx_buffer->next_to_watch = NULL; 1148 1149 /* update the statistics for this packet */ 1150 total_bytes += tx_buffer->bytecount; 1151 total_packets += tx_buffer->gso_segs; 1152 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1153 total_ipsec++; 1154 1155 /* free the skb */ 1156 if (ring_is_xdp(tx_ring)) 1157 xdp_return_frame(tx_buffer->xdpf); 1158 else 1159 napi_consume_skb(tx_buffer->skb, napi_budget); 1160 1161 /* unmap skb header data */ 1162 dma_unmap_single(tx_ring->dev, 1163 dma_unmap_addr(tx_buffer, dma), 1164 dma_unmap_len(tx_buffer, len), 1165 DMA_TO_DEVICE); 1166 1167 /* clear tx_buffer data */ 1168 dma_unmap_len_set(tx_buffer, len, 0); 1169 1170 /* unmap remaining buffers */ 1171 while (tx_desc != eop_desc) { 1172 tx_buffer++; 1173 tx_desc++; 1174 i++; 1175 if (unlikely(!i)) { 1176 i -= tx_ring->count; 1177 tx_buffer = tx_ring->tx_buffer_info; 1178 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1179 } 1180 1181 /* unmap any remaining paged data */ 1182 if (dma_unmap_len(tx_buffer, len)) { 1183 dma_unmap_page(tx_ring->dev, 1184 dma_unmap_addr(tx_buffer, dma), 1185 dma_unmap_len(tx_buffer, len), 1186 DMA_TO_DEVICE); 1187 dma_unmap_len_set(tx_buffer, len, 0); 1188 } 1189 } 1190 1191 /* move us one more past the eop_desc for start of next pkt */ 1192 tx_buffer++; 1193 tx_desc++; 1194 i++; 1195 if (unlikely(!i)) { 1196 i -= tx_ring->count; 1197 tx_buffer = tx_ring->tx_buffer_info; 1198 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1199 } 1200 1201 /* issue prefetch for next Tx descriptor */ 1202 prefetch(tx_desc); 1203 1204 /* update budget accounting */ 1205 budget--; 1206 } while (likely(budget)); 1207 1208 i += tx_ring->count; 1209 tx_ring->next_to_clean = i; 1210 u64_stats_update_begin(&tx_ring->syncp); 1211 tx_ring->stats.bytes += total_bytes; 1212 tx_ring->stats.packets += total_packets; 1213 u64_stats_update_end(&tx_ring->syncp); 1214 q_vector->tx.total_bytes += total_bytes; 1215 q_vector->tx.total_packets += total_packets; 1216 adapter->tx_ipsec += total_ipsec; 1217 1218 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1219 /* schedule immediate reset if we believe we hung */ 1220 struct ixgbe_hw *hw = &adapter->hw; 1221 e_err(drv, "Detected Tx Unit Hang %s\n" 1222 " Tx Queue <%d>\n" 1223 " TDH, TDT <%x>, <%x>\n" 1224 " next_to_use <%x>\n" 1225 " next_to_clean <%x>\n" 1226 "tx_buffer_info[next_to_clean]\n" 1227 " time_stamp <%lx>\n" 1228 " jiffies <%lx>\n", 1229 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1230 tx_ring->queue_index, 1231 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1232 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1233 tx_ring->next_to_use, i, 1234 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1235 1236 if (!ring_is_xdp(tx_ring)) 1237 netif_stop_subqueue(tx_ring->netdev, 1238 tx_ring->queue_index); 1239 1240 e_info(probe, 1241 "tx hang %d detected on queue %d, resetting adapter\n", 1242 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1243 1244 /* schedule immediate reset if we believe we hung */ 1245 ixgbe_tx_timeout_reset(adapter); 1246 1247 /* the adapter is about to reset, no point in enabling stuff */ 1248 return true; 1249 } 1250 1251 if (ring_is_xdp(tx_ring)) 1252 return !!budget; 1253 1254 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1255 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 1256 if (!__netif_txq_completed_wake(txq, total_packets, total_bytes, 1257 ixgbe_desc_unused(tx_ring), 1258 TX_WAKE_THRESHOLD, 1259 !netif_carrier_ok(tx_ring->netdev) || 1260 test_bit(__IXGBE_DOWN, &adapter->state))) 1261 ++tx_ring->tx_stats.restart_queue; 1262 1263 return !!budget; 1264 } 1265 1266 #ifdef CONFIG_IXGBE_DCA 1267 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1268 struct ixgbe_ring *tx_ring, 1269 int cpu) 1270 { 1271 struct ixgbe_hw *hw = &adapter->hw; 1272 u32 txctrl = 0; 1273 u16 reg_offset; 1274 1275 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1276 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1277 1278 switch (hw->mac.type) { 1279 case ixgbe_mac_82598EB: 1280 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1281 break; 1282 case ixgbe_mac_82599EB: 1283 case ixgbe_mac_X540: 1284 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1285 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1286 break; 1287 default: 1288 /* for unknown hardware do not write register */ 1289 return; 1290 } 1291 1292 /* 1293 * We can enable relaxed ordering for reads, but not writes when 1294 * DCA is enabled. This is due to a known issue in some chipsets 1295 * which will cause the DCA tag to be cleared. 1296 */ 1297 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1298 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1299 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1300 1301 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1302 } 1303 1304 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1305 struct ixgbe_ring *rx_ring, 1306 int cpu) 1307 { 1308 struct ixgbe_hw *hw = &adapter->hw; 1309 u32 rxctrl = 0; 1310 u8 reg_idx = rx_ring->reg_idx; 1311 1312 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1313 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1314 1315 switch (hw->mac.type) { 1316 case ixgbe_mac_82599EB: 1317 case ixgbe_mac_X540: 1318 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 /* 1325 * We can enable relaxed ordering for reads, but not writes when 1326 * DCA is enabled. This is due to a known issue in some chipsets 1327 * which will cause the DCA tag to be cleared. 1328 */ 1329 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1330 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1331 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1332 1333 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1334 } 1335 1336 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1337 { 1338 struct ixgbe_adapter *adapter = q_vector->adapter; 1339 struct ixgbe_ring *ring; 1340 int cpu = get_cpu(); 1341 1342 if (q_vector->cpu == cpu) 1343 goto out_no_update; 1344 1345 ixgbe_for_each_ring(ring, q_vector->tx) 1346 ixgbe_update_tx_dca(adapter, ring, cpu); 1347 1348 ixgbe_for_each_ring(ring, q_vector->rx) 1349 ixgbe_update_rx_dca(adapter, ring, cpu); 1350 1351 q_vector->cpu = cpu; 1352 out_no_update: 1353 put_cpu(); 1354 } 1355 1356 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1357 { 1358 int i; 1359 1360 /* always use CB2 mode, difference is masked in the CB driver */ 1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1363 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1364 else 1365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1366 IXGBE_DCA_CTRL_DCA_DISABLE); 1367 1368 for (i = 0; i < adapter->num_q_vectors; i++) { 1369 adapter->q_vector[i]->cpu = -1; 1370 ixgbe_update_dca(adapter->q_vector[i]); 1371 } 1372 } 1373 1374 static int __ixgbe_notify_dca(struct device *dev, void *data) 1375 { 1376 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1377 unsigned long event = *(unsigned long *)data; 1378 1379 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1380 return 0; 1381 1382 switch (event) { 1383 case DCA_PROVIDER_ADD: 1384 /* if we're already enabled, don't do it again */ 1385 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1386 break; 1387 if (dca_add_requester(dev) == 0) { 1388 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1390 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1391 break; 1392 } 1393 fallthrough; /* DCA is disabled. */ 1394 case DCA_PROVIDER_REMOVE: 1395 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1396 dca_remove_requester(dev); 1397 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1399 IXGBE_DCA_CTRL_DCA_DISABLE); 1400 } 1401 break; 1402 } 1403 1404 return 0; 1405 } 1406 1407 #endif /* CONFIG_IXGBE_DCA */ 1408 1409 #define IXGBE_RSS_L4_TYPES_MASK \ 1410 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1411 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1412 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1413 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1414 1415 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1416 union ixgbe_adv_rx_desc *rx_desc, 1417 struct sk_buff *skb) 1418 { 1419 u16 rss_type; 1420 1421 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1422 return; 1423 1424 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1425 IXGBE_RXDADV_RSSTYPE_MASK; 1426 1427 if (!rss_type) 1428 return; 1429 1430 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1431 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1432 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1433 } 1434 1435 #ifdef IXGBE_FCOE 1436 /** 1437 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1438 * @ring: structure containing ring specific data 1439 * @rx_desc: advanced rx descriptor 1440 * 1441 * Returns : true if it is FCoE pkt 1442 */ 1443 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1444 union ixgbe_adv_rx_desc *rx_desc) 1445 { 1446 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1447 1448 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1449 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1450 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1451 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1452 } 1453 1454 #endif /* IXGBE_FCOE */ 1455 /** 1456 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1457 * @ring: structure containing ring specific data 1458 * @rx_desc: current Rx descriptor being processed 1459 * @skb: skb currently being received and modified 1460 **/ 1461 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1462 union ixgbe_adv_rx_desc *rx_desc, 1463 struct sk_buff *skb) 1464 { 1465 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1466 bool encap_pkt = false; 1467 1468 skb_checksum_none_assert(skb); 1469 1470 /* Rx csum disabled */ 1471 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1472 return; 1473 1474 /* check for VXLAN and Geneve packets */ 1475 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1476 encap_pkt = true; 1477 skb->encapsulation = 1; 1478 } 1479 1480 /* if IP and error */ 1481 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1482 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1483 ring->rx_stats.csum_err++; 1484 return; 1485 } 1486 1487 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1488 return; 1489 1490 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1491 /* 1492 * 82599 errata, UDP frames with a 0 checksum can be marked as 1493 * checksum errors. 1494 */ 1495 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1496 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1497 return; 1498 1499 ring->rx_stats.csum_err++; 1500 return; 1501 } 1502 1503 /* It must be a TCP or UDP packet with a valid checksum */ 1504 skb->ip_summed = CHECKSUM_UNNECESSARY; 1505 if (encap_pkt) { 1506 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1507 return; 1508 1509 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1510 skb->ip_summed = CHECKSUM_NONE; 1511 return; 1512 } 1513 /* If we checked the outer header let the stack know */ 1514 skb->csum_level = 1; 1515 } 1516 } 1517 1518 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1519 { 1520 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1521 } 1522 1523 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1524 struct ixgbe_rx_buffer *bi) 1525 { 1526 struct page *page = bi->page; 1527 dma_addr_t dma; 1528 1529 /* since we are recycling buffers we should seldom need to alloc */ 1530 if (likely(page)) 1531 return true; 1532 1533 /* alloc new page for storage */ 1534 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1535 if (unlikely(!page)) { 1536 rx_ring->rx_stats.alloc_rx_page_failed++; 1537 return false; 1538 } 1539 1540 /* map page for use */ 1541 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1542 ixgbe_rx_pg_size(rx_ring), 1543 DMA_FROM_DEVICE, 1544 IXGBE_RX_DMA_ATTR); 1545 1546 /* 1547 * if mapping failed free memory back to system since 1548 * there isn't much point in holding memory we can't use 1549 */ 1550 if (dma_mapping_error(rx_ring->dev, dma)) { 1551 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1552 1553 rx_ring->rx_stats.alloc_rx_page_failed++; 1554 return false; 1555 } 1556 1557 bi->dma = dma; 1558 bi->page = page; 1559 bi->page_offset = rx_ring->rx_offset; 1560 page_ref_add(page, USHRT_MAX - 1); 1561 bi->pagecnt_bias = USHRT_MAX; 1562 rx_ring->rx_stats.alloc_rx_page++; 1563 1564 return true; 1565 } 1566 1567 /** 1568 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1569 * @rx_ring: ring to place buffers on 1570 * @cleaned_count: number of buffers to replace 1571 **/ 1572 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1573 { 1574 union ixgbe_adv_rx_desc *rx_desc; 1575 struct ixgbe_rx_buffer *bi; 1576 u16 i = rx_ring->next_to_use; 1577 u16 bufsz; 1578 1579 /* nothing to do */ 1580 if (!cleaned_count) 1581 return; 1582 1583 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1584 bi = &rx_ring->rx_buffer_info[i]; 1585 i -= rx_ring->count; 1586 1587 bufsz = ixgbe_rx_bufsz(rx_ring); 1588 1589 do { 1590 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1591 break; 1592 1593 /* sync the buffer for use by the device */ 1594 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1595 bi->page_offset, bufsz, 1596 DMA_FROM_DEVICE); 1597 1598 /* 1599 * Refresh the desc even if buffer_addrs didn't change 1600 * because each write-back erases this info. 1601 */ 1602 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1603 1604 rx_desc++; 1605 bi++; 1606 i++; 1607 if (unlikely(!i)) { 1608 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1609 bi = rx_ring->rx_buffer_info; 1610 i -= rx_ring->count; 1611 } 1612 1613 /* clear the length for the next_to_use descriptor */ 1614 rx_desc->wb.upper.length = 0; 1615 1616 cleaned_count--; 1617 } while (cleaned_count); 1618 1619 i += rx_ring->count; 1620 1621 if (rx_ring->next_to_use != i) { 1622 rx_ring->next_to_use = i; 1623 1624 /* update next to alloc since we have filled the ring */ 1625 rx_ring->next_to_alloc = i; 1626 1627 /* Force memory writes to complete before letting h/w 1628 * know there are new descriptors to fetch. (Only 1629 * applicable for weak-ordered memory model archs, 1630 * such as IA-64). 1631 */ 1632 wmb(); 1633 writel(i, rx_ring->tail); 1634 } 1635 } 1636 1637 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1638 struct sk_buff *skb) 1639 { 1640 u16 hdr_len = skb_headlen(skb); 1641 1642 /* set gso_size to avoid messing up TCP MSS */ 1643 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1644 IXGBE_CB(skb)->append_cnt); 1645 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1646 } 1647 1648 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1649 struct sk_buff *skb) 1650 { 1651 /* if append_cnt is 0 then frame is not RSC */ 1652 if (!IXGBE_CB(skb)->append_cnt) 1653 return; 1654 1655 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1656 rx_ring->rx_stats.rsc_flush++; 1657 1658 ixgbe_set_rsc_gso_size(rx_ring, skb); 1659 1660 /* gso_size is computed using append_cnt so always clear it last */ 1661 IXGBE_CB(skb)->append_cnt = 0; 1662 } 1663 1664 /** 1665 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1666 * @rx_ring: rx descriptor ring packet is being transacted on 1667 * @rx_desc: pointer to the EOP Rx descriptor 1668 * @skb: pointer to current skb being populated 1669 * 1670 * This function checks the ring, descriptor, and packet information in 1671 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1672 * other fields within the skb. 1673 **/ 1674 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1675 union ixgbe_adv_rx_desc *rx_desc, 1676 struct sk_buff *skb) 1677 { 1678 struct net_device *dev = rx_ring->netdev; 1679 u32 flags = rx_ring->q_vector->adapter->flags; 1680 1681 ixgbe_update_rsc_stats(rx_ring, skb); 1682 1683 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1684 1685 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1686 1687 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1688 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1689 1690 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1691 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1692 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1693 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1694 } 1695 1696 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1697 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1698 1699 /* record Rx queue, or update MACVLAN statistics */ 1700 if (netif_is_ixgbe(dev)) 1701 skb_record_rx_queue(skb, rx_ring->queue_index); 1702 else 1703 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1704 false); 1705 1706 skb->protocol = eth_type_trans(skb, dev); 1707 } 1708 1709 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1710 struct sk_buff *skb) 1711 { 1712 napi_gro_receive(&q_vector->napi, skb); 1713 } 1714 1715 /** 1716 * ixgbe_is_non_eop - process handling of non-EOP buffers 1717 * @rx_ring: Rx ring being processed 1718 * @rx_desc: Rx descriptor for current buffer 1719 * @skb: Current socket buffer containing buffer in progress 1720 * 1721 * This function updates next to clean. If the buffer is an EOP buffer 1722 * this function exits returning false, otherwise it will place the 1723 * sk_buff in the next buffer to be chained and return true indicating 1724 * that this is in fact a non-EOP buffer. 1725 **/ 1726 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1727 union ixgbe_adv_rx_desc *rx_desc, 1728 struct sk_buff *skb) 1729 { 1730 u32 ntc = rx_ring->next_to_clean + 1; 1731 1732 /* fetch, update, and store next to clean */ 1733 ntc = (ntc < rx_ring->count) ? ntc : 0; 1734 rx_ring->next_to_clean = ntc; 1735 1736 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1737 1738 /* update RSC append count if present */ 1739 if (ring_is_rsc_enabled(rx_ring)) { 1740 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1741 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1742 1743 if (unlikely(rsc_enabled)) { 1744 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1745 1746 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1747 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1748 1749 /* update ntc based on RSC value */ 1750 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1751 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1752 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1753 } 1754 } 1755 1756 /* if we are the last buffer then there is nothing else to do */ 1757 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1758 return false; 1759 1760 /* place skb in next buffer to be received */ 1761 rx_ring->rx_buffer_info[ntc].skb = skb; 1762 rx_ring->rx_stats.non_eop_descs++; 1763 1764 return true; 1765 } 1766 1767 /** 1768 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1769 * @rx_ring: rx descriptor ring packet is being transacted on 1770 * @skb: pointer to current skb being adjusted 1771 * 1772 * This function is an ixgbe specific version of __pskb_pull_tail. The 1773 * main difference between this version and the original function is that 1774 * this function can make several assumptions about the state of things 1775 * that allow for significant optimizations versus the standard function. 1776 * As a result we can do things like drop a frag and maintain an accurate 1777 * truesize for the skb. 1778 */ 1779 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1780 struct sk_buff *skb) 1781 { 1782 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1783 unsigned char *va; 1784 unsigned int pull_len; 1785 1786 /* 1787 * it is valid to use page_address instead of kmap since we are 1788 * working with pages allocated out of the lomem pool per 1789 * alloc_page(GFP_ATOMIC) 1790 */ 1791 va = skb_frag_address(frag); 1792 1793 /* 1794 * we need the header to contain the greater of either ETH_HLEN or 1795 * 60 bytes if the skb->len is less than 60 for skb_pad. 1796 */ 1797 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1798 1799 /* align pull length to size of long to optimize memcpy performance */ 1800 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1801 1802 /* update all of the pointers */ 1803 skb_frag_size_sub(frag, pull_len); 1804 skb_frag_off_add(frag, pull_len); 1805 skb->data_len -= pull_len; 1806 skb->tail += pull_len; 1807 } 1808 1809 /** 1810 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1811 * @rx_ring: rx descriptor ring packet is being transacted on 1812 * @skb: pointer to current skb being updated 1813 * 1814 * This function provides a basic DMA sync up for the first fragment of an 1815 * skb. The reason for doing this is that the first fragment cannot be 1816 * unmapped until we have reached the end of packet descriptor for a buffer 1817 * chain. 1818 */ 1819 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1820 struct sk_buff *skb) 1821 { 1822 if (ring_uses_build_skb(rx_ring)) { 1823 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1; 1824 unsigned long offset = (unsigned long)(skb->data) & mask; 1825 1826 dma_sync_single_range_for_cpu(rx_ring->dev, 1827 IXGBE_CB(skb)->dma, 1828 offset, 1829 skb_headlen(skb), 1830 DMA_FROM_DEVICE); 1831 } else { 1832 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1833 1834 dma_sync_single_range_for_cpu(rx_ring->dev, 1835 IXGBE_CB(skb)->dma, 1836 skb_frag_off(frag), 1837 skb_frag_size(frag), 1838 DMA_FROM_DEVICE); 1839 } 1840 1841 /* If the page was released, just unmap it. */ 1842 if (unlikely(IXGBE_CB(skb)->page_released)) { 1843 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1844 ixgbe_rx_pg_size(rx_ring), 1845 DMA_FROM_DEVICE, 1846 IXGBE_RX_DMA_ATTR); 1847 } 1848 } 1849 1850 /** 1851 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1852 * @rx_ring: rx descriptor ring packet is being transacted on 1853 * @rx_desc: pointer to the EOP Rx descriptor 1854 * @skb: pointer to current skb being fixed 1855 * 1856 * Check if the skb is valid in the XDP case it will be an error pointer. 1857 * Return true in this case to abort processing and advance to next 1858 * descriptor. 1859 * 1860 * Check for corrupted packet headers caused by senders on the local L2 1861 * embedded NIC switch not setting up their Tx Descriptors right. These 1862 * should be very rare. 1863 * 1864 * Also address the case where we are pulling data in on pages only 1865 * and as such no data is present in the skb header. 1866 * 1867 * In addition if skb is not at least 60 bytes we need to pad it so that 1868 * it is large enough to qualify as a valid Ethernet frame. 1869 * 1870 * Returns true if an error was encountered and skb was freed. 1871 **/ 1872 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1873 union ixgbe_adv_rx_desc *rx_desc, 1874 struct sk_buff *skb) 1875 { 1876 struct net_device *netdev = rx_ring->netdev; 1877 1878 /* XDP packets use error pointer so abort at this point */ 1879 if (IS_ERR(skb)) 1880 return true; 1881 1882 /* Verify netdev is present, and that packet does not have any 1883 * errors that would be unacceptable to the netdev. 1884 */ 1885 if (!netdev || 1886 (unlikely(ixgbe_test_staterr(rx_desc, 1887 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1888 !(netdev->features & NETIF_F_RXALL)))) { 1889 dev_kfree_skb_any(skb); 1890 return true; 1891 } 1892 1893 /* place header in linear portion of buffer */ 1894 if (!skb_headlen(skb)) 1895 ixgbe_pull_tail(rx_ring, skb); 1896 1897 #ifdef IXGBE_FCOE 1898 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1899 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1900 return false; 1901 1902 #endif 1903 /* if eth_skb_pad returns an error the skb was freed */ 1904 if (eth_skb_pad(skb)) 1905 return true; 1906 1907 return false; 1908 } 1909 1910 /** 1911 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1912 * @rx_ring: rx descriptor ring to store buffers on 1913 * @old_buff: donor buffer to have page reused 1914 * 1915 * Synchronizes page for reuse by the adapter 1916 **/ 1917 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1918 struct ixgbe_rx_buffer *old_buff) 1919 { 1920 struct ixgbe_rx_buffer *new_buff; 1921 u16 nta = rx_ring->next_to_alloc; 1922 1923 new_buff = &rx_ring->rx_buffer_info[nta]; 1924 1925 /* update, and store next to alloc */ 1926 nta++; 1927 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1928 1929 /* Transfer page from old buffer to new buffer. 1930 * Move each member individually to avoid possible store 1931 * forwarding stalls and unnecessary copy of skb. 1932 */ 1933 new_buff->dma = old_buff->dma; 1934 new_buff->page = old_buff->page; 1935 new_buff->page_offset = old_buff->page_offset; 1936 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1937 } 1938 1939 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 1940 int rx_buffer_pgcnt) 1941 { 1942 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1943 struct page *page = rx_buffer->page; 1944 1945 /* avoid re-using remote and pfmemalloc pages */ 1946 if (!dev_page_is_reusable(page)) 1947 return false; 1948 1949 #if (PAGE_SIZE < 8192) 1950 /* if we are only owner of page we can reuse it */ 1951 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1952 return false; 1953 #else 1954 /* The last offset is a bit aggressive in that we assume the 1955 * worst case of FCoE being enabled and using a 3K buffer. 1956 * However this should have minimal impact as the 1K extra is 1957 * still less than one buffer in size. 1958 */ 1959 #define IXGBE_LAST_OFFSET \ 1960 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1961 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1962 return false; 1963 #endif 1964 1965 /* If we have drained the page fragment pool we need to update 1966 * the pagecnt_bias and page count so that we fully restock the 1967 * number of references the driver holds. 1968 */ 1969 if (unlikely(pagecnt_bias == 1)) { 1970 page_ref_add(page, USHRT_MAX - 1); 1971 rx_buffer->pagecnt_bias = USHRT_MAX; 1972 } 1973 1974 return true; 1975 } 1976 1977 /** 1978 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1979 * @rx_ring: rx descriptor ring to transact packets on 1980 * @rx_buffer: buffer containing page to add 1981 * @skb: sk_buff to place the data into 1982 * @size: size of data in rx_buffer 1983 * 1984 * This function will add the data contained in rx_buffer->page to the skb. 1985 * This is done either through a direct copy if the data in the buffer is 1986 * less than the skb header size, otherwise it will just attach the page as 1987 * a frag to the skb. 1988 * 1989 * The function will then update the page offset if necessary and return 1990 * true if the buffer can be reused by the adapter. 1991 **/ 1992 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1993 struct ixgbe_rx_buffer *rx_buffer, 1994 struct sk_buff *skb, 1995 unsigned int size) 1996 { 1997 #if (PAGE_SIZE < 8192) 1998 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 1999 #else 2000 unsigned int truesize = rx_ring->rx_offset ? 2001 SKB_DATA_ALIGN(rx_ring->rx_offset + size) : 2002 SKB_DATA_ALIGN(size); 2003 #endif 2004 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2005 rx_buffer->page_offset, size, truesize); 2006 #if (PAGE_SIZE < 8192) 2007 rx_buffer->page_offset ^= truesize; 2008 #else 2009 rx_buffer->page_offset += truesize; 2010 #endif 2011 } 2012 2013 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2014 union ixgbe_adv_rx_desc *rx_desc, 2015 struct sk_buff **skb, 2016 const unsigned int size, 2017 int *rx_buffer_pgcnt) 2018 { 2019 struct ixgbe_rx_buffer *rx_buffer; 2020 2021 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2022 *rx_buffer_pgcnt = 2023 #if (PAGE_SIZE < 8192) 2024 page_count(rx_buffer->page); 2025 #else 2026 0; 2027 #endif 2028 prefetchw(rx_buffer->page); 2029 *skb = rx_buffer->skb; 2030 2031 /* Delay unmapping of the first packet. It carries the header 2032 * information, HW may still access the header after the writeback. 2033 * Only unmap it when EOP is reached 2034 */ 2035 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2036 if (!*skb) 2037 goto skip_sync; 2038 } else { 2039 if (*skb) 2040 ixgbe_dma_sync_frag(rx_ring, *skb); 2041 } 2042 2043 /* we are reusing so sync this buffer for CPU use */ 2044 dma_sync_single_range_for_cpu(rx_ring->dev, 2045 rx_buffer->dma, 2046 rx_buffer->page_offset, 2047 size, 2048 DMA_FROM_DEVICE); 2049 skip_sync: 2050 rx_buffer->pagecnt_bias--; 2051 2052 return rx_buffer; 2053 } 2054 2055 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2056 struct ixgbe_rx_buffer *rx_buffer, 2057 struct sk_buff *skb, 2058 int rx_buffer_pgcnt) 2059 { 2060 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2061 /* hand second half of page back to the ring */ 2062 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2063 } else { 2064 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2065 /* the page has been released from the ring */ 2066 IXGBE_CB(skb)->page_released = true; 2067 } else { 2068 /* we are not reusing the buffer so unmap it */ 2069 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2070 ixgbe_rx_pg_size(rx_ring), 2071 DMA_FROM_DEVICE, 2072 IXGBE_RX_DMA_ATTR); 2073 } 2074 __page_frag_cache_drain(rx_buffer->page, 2075 rx_buffer->pagecnt_bias); 2076 } 2077 2078 /* clear contents of rx_buffer */ 2079 rx_buffer->page = NULL; 2080 rx_buffer->skb = NULL; 2081 } 2082 2083 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2084 struct ixgbe_rx_buffer *rx_buffer, 2085 struct xdp_buff *xdp, 2086 union ixgbe_adv_rx_desc *rx_desc) 2087 { 2088 unsigned int size = xdp->data_end - xdp->data; 2089 #if (PAGE_SIZE < 8192) 2090 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2091 #else 2092 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2093 xdp->data_hard_start); 2094 #endif 2095 struct sk_buff *skb; 2096 2097 /* prefetch first cache line of first page */ 2098 net_prefetch(xdp->data); 2099 2100 /* Note, we get here by enabling legacy-rx via: 2101 * 2102 * ethtool --set-priv-flags <dev> legacy-rx on 2103 * 2104 * In this mode, we currently get 0 extra XDP headroom as 2105 * opposed to having legacy-rx off, where we process XDP 2106 * packets going to stack via ixgbe_build_skb(). The latter 2107 * provides us currently with 192 bytes of headroom. 2108 * 2109 * For ixgbe_construct_skb() mode it means that the 2110 * xdp->data_meta will always point to xdp->data, since 2111 * the helper cannot expand the head. Should this ever 2112 * change in future for legacy-rx mode on, then lets also 2113 * add xdp->data_meta handling here. 2114 */ 2115 2116 /* allocate a skb to store the frags */ 2117 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2118 if (unlikely(!skb)) 2119 return NULL; 2120 2121 if (size > IXGBE_RX_HDR_SIZE) { 2122 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2123 IXGBE_CB(skb)->dma = rx_buffer->dma; 2124 2125 skb_add_rx_frag(skb, 0, rx_buffer->page, 2126 xdp->data - page_address(rx_buffer->page), 2127 size, truesize); 2128 #if (PAGE_SIZE < 8192) 2129 rx_buffer->page_offset ^= truesize; 2130 #else 2131 rx_buffer->page_offset += truesize; 2132 #endif 2133 } else { 2134 memcpy(__skb_put(skb, size), 2135 xdp->data, ALIGN(size, sizeof(long))); 2136 rx_buffer->pagecnt_bias++; 2137 } 2138 2139 return skb; 2140 } 2141 2142 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2143 struct ixgbe_rx_buffer *rx_buffer, 2144 struct xdp_buff *xdp, 2145 union ixgbe_adv_rx_desc *rx_desc) 2146 { 2147 unsigned int metasize = xdp->data - xdp->data_meta; 2148 #if (PAGE_SIZE < 8192) 2149 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2150 #else 2151 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2152 SKB_DATA_ALIGN(xdp->data_end - 2153 xdp->data_hard_start); 2154 #endif 2155 struct sk_buff *skb; 2156 2157 /* Prefetch first cache line of first page. If xdp->data_meta 2158 * is unused, this points extactly as xdp->data, otherwise we 2159 * likely have a consumer accessing first few bytes of meta 2160 * data, and then actual data. 2161 */ 2162 net_prefetch(xdp->data_meta); 2163 2164 /* build an skb to around the page buffer */ 2165 skb = napi_build_skb(xdp->data_hard_start, truesize); 2166 if (unlikely(!skb)) 2167 return NULL; 2168 2169 /* update pointers within the skb to store the data */ 2170 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2171 __skb_put(skb, xdp->data_end - xdp->data); 2172 if (metasize) 2173 skb_metadata_set(skb, metasize); 2174 2175 /* record DMA address if this is the start of a chain of buffers */ 2176 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2177 IXGBE_CB(skb)->dma = rx_buffer->dma; 2178 2179 /* update buffer offset */ 2180 #if (PAGE_SIZE < 8192) 2181 rx_buffer->page_offset ^= truesize; 2182 #else 2183 rx_buffer->page_offset += truesize; 2184 #endif 2185 2186 return skb; 2187 } 2188 2189 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2190 struct ixgbe_ring *rx_ring, 2191 struct xdp_buff *xdp) 2192 { 2193 int err, result = IXGBE_XDP_PASS; 2194 struct bpf_prog *xdp_prog; 2195 struct ixgbe_ring *ring; 2196 struct xdp_frame *xdpf; 2197 u32 act; 2198 2199 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2200 2201 if (!xdp_prog) 2202 goto xdp_out; 2203 2204 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2205 2206 act = bpf_prog_run_xdp(xdp_prog, xdp); 2207 switch (act) { 2208 case XDP_PASS: 2209 break; 2210 case XDP_TX: 2211 xdpf = xdp_convert_buff_to_frame(xdp); 2212 if (unlikely(!xdpf)) 2213 goto out_failure; 2214 ring = ixgbe_determine_xdp_ring(adapter); 2215 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2216 spin_lock(&ring->tx_lock); 2217 result = ixgbe_xmit_xdp_ring(ring, xdpf); 2218 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2219 spin_unlock(&ring->tx_lock); 2220 if (result == IXGBE_XDP_CONSUMED) 2221 goto out_failure; 2222 break; 2223 case XDP_REDIRECT: 2224 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2225 if (err) 2226 goto out_failure; 2227 result = IXGBE_XDP_REDIR; 2228 break; 2229 default: 2230 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2231 fallthrough; 2232 case XDP_ABORTED: 2233 out_failure: 2234 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2235 fallthrough; /* handle aborts by dropping packet */ 2236 case XDP_DROP: 2237 result = IXGBE_XDP_CONSUMED; 2238 break; 2239 } 2240 xdp_out: 2241 return ERR_PTR(-result); 2242 } 2243 2244 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2245 unsigned int size) 2246 { 2247 unsigned int truesize; 2248 2249 #if (PAGE_SIZE < 8192) 2250 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2251 #else 2252 truesize = rx_ring->rx_offset ? 2253 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 2254 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2255 SKB_DATA_ALIGN(size); 2256 #endif 2257 return truesize; 2258 } 2259 2260 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2261 struct ixgbe_rx_buffer *rx_buffer, 2262 unsigned int size) 2263 { 2264 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2265 #if (PAGE_SIZE < 8192) 2266 rx_buffer->page_offset ^= truesize; 2267 #else 2268 rx_buffer->page_offset += truesize; 2269 #endif 2270 } 2271 2272 /** 2273 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2274 * @q_vector: structure containing interrupt and ring information 2275 * @rx_ring: rx descriptor ring to transact packets on 2276 * @budget: Total limit on number of packets to process 2277 * 2278 * This function provides a "bounce buffer" approach to Rx interrupt 2279 * processing. The advantage to this is that on systems that have 2280 * expensive overhead for IOMMU access this provides a means of avoiding 2281 * it by maintaining the mapping of the page to the syste. 2282 * 2283 * Returns amount of work completed 2284 **/ 2285 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2286 struct ixgbe_ring *rx_ring, 2287 const int budget) 2288 { 2289 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; 2290 struct ixgbe_adapter *adapter = q_vector->adapter; 2291 #ifdef IXGBE_FCOE 2292 int ddp_bytes; 2293 unsigned int mss = 0; 2294 #endif /* IXGBE_FCOE */ 2295 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2296 unsigned int offset = rx_ring->rx_offset; 2297 unsigned int xdp_xmit = 0; 2298 struct xdp_buff xdp; 2299 2300 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2301 #if (PAGE_SIZE < 8192) 2302 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2303 #endif 2304 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 2305 2306 while (likely(total_rx_packets < budget)) { 2307 union ixgbe_adv_rx_desc *rx_desc; 2308 struct ixgbe_rx_buffer *rx_buffer; 2309 struct sk_buff *skb; 2310 int rx_buffer_pgcnt; 2311 unsigned int size; 2312 2313 /* return some buffers to hardware, one at a time is too slow */ 2314 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2315 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2316 cleaned_count = 0; 2317 } 2318 2319 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2320 size = le16_to_cpu(rx_desc->wb.upper.length); 2321 if (!size) 2322 break; 2323 2324 /* This memory barrier is needed to keep us from reading 2325 * any other fields out of the rx_desc until we know the 2326 * descriptor has been written back 2327 */ 2328 dma_rmb(); 2329 2330 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2331 2332 /* retrieve a buffer from the ring */ 2333 if (!skb) { 2334 unsigned char *hard_start; 2335 2336 hard_start = page_address(rx_buffer->page) + 2337 rx_buffer->page_offset - offset; 2338 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 2339 xdp_buff_clear_frags_flag(&xdp); 2340 #if (PAGE_SIZE > 4096) 2341 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2342 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2343 #endif 2344 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2345 } 2346 2347 if (IS_ERR(skb)) { 2348 unsigned int xdp_res = -PTR_ERR(skb); 2349 2350 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2351 xdp_xmit |= xdp_res; 2352 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2353 } else { 2354 rx_buffer->pagecnt_bias++; 2355 } 2356 total_rx_packets++; 2357 total_rx_bytes += size; 2358 } else if (skb) { 2359 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2360 } else if (ring_uses_build_skb(rx_ring)) { 2361 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2362 &xdp, rx_desc); 2363 } else { 2364 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2365 &xdp, rx_desc); 2366 } 2367 2368 /* exit if we failed to retrieve a buffer */ 2369 if (!skb) { 2370 rx_ring->rx_stats.alloc_rx_buff_failed++; 2371 rx_buffer->pagecnt_bias++; 2372 break; 2373 } 2374 2375 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2376 cleaned_count++; 2377 2378 /* place incomplete frames back on ring for completion */ 2379 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2380 continue; 2381 2382 /* verify the packet layout is correct */ 2383 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2384 continue; 2385 2386 /* probably a little skewed due to removing CRC */ 2387 total_rx_bytes += skb->len; 2388 2389 /* populate checksum, timestamp, VLAN, and protocol */ 2390 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2391 2392 #ifdef IXGBE_FCOE 2393 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2394 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2395 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2396 /* include DDPed FCoE data */ 2397 if (ddp_bytes > 0) { 2398 if (!mss) { 2399 mss = rx_ring->netdev->mtu - 2400 sizeof(struct fcoe_hdr) - 2401 sizeof(struct fc_frame_header) - 2402 sizeof(struct fcoe_crc_eof); 2403 if (mss > 512) 2404 mss &= ~511; 2405 } 2406 total_rx_bytes += ddp_bytes; 2407 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2408 mss); 2409 } 2410 if (!ddp_bytes) { 2411 dev_kfree_skb_any(skb); 2412 continue; 2413 } 2414 } 2415 2416 #endif /* IXGBE_FCOE */ 2417 ixgbe_rx_skb(q_vector, skb); 2418 2419 /* update budget accounting */ 2420 total_rx_packets++; 2421 } 2422 2423 if (xdp_xmit & IXGBE_XDP_REDIR) 2424 xdp_do_flush_map(); 2425 2426 if (xdp_xmit & IXGBE_XDP_TX) { 2427 struct ixgbe_ring *ring = ixgbe_determine_xdp_ring(adapter); 2428 2429 ixgbe_xdp_ring_update_tail_locked(ring); 2430 } 2431 2432 u64_stats_update_begin(&rx_ring->syncp); 2433 rx_ring->stats.packets += total_rx_packets; 2434 rx_ring->stats.bytes += total_rx_bytes; 2435 u64_stats_update_end(&rx_ring->syncp); 2436 q_vector->rx.total_packets += total_rx_packets; 2437 q_vector->rx.total_bytes += total_rx_bytes; 2438 2439 return total_rx_packets; 2440 } 2441 2442 /** 2443 * ixgbe_configure_msix - Configure MSI-X hardware 2444 * @adapter: board private structure 2445 * 2446 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2447 * interrupts. 2448 **/ 2449 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2450 { 2451 struct ixgbe_q_vector *q_vector; 2452 int v_idx; 2453 u32 mask; 2454 2455 /* Populate MSIX to EITR Select */ 2456 if (adapter->num_vfs > 32) { 2457 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2458 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2459 } 2460 2461 /* 2462 * Populate the IVAR table and set the ITR values to the 2463 * corresponding register. 2464 */ 2465 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2466 struct ixgbe_ring *ring; 2467 q_vector = adapter->q_vector[v_idx]; 2468 2469 ixgbe_for_each_ring(ring, q_vector->rx) 2470 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2471 2472 ixgbe_for_each_ring(ring, q_vector->tx) 2473 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2474 2475 ixgbe_write_eitr(q_vector); 2476 } 2477 2478 switch (adapter->hw.mac.type) { 2479 case ixgbe_mac_82598EB: 2480 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2481 v_idx); 2482 break; 2483 case ixgbe_mac_82599EB: 2484 case ixgbe_mac_X540: 2485 case ixgbe_mac_X550: 2486 case ixgbe_mac_X550EM_x: 2487 case ixgbe_mac_x550em_a: 2488 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2489 break; 2490 default: 2491 break; 2492 } 2493 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2494 2495 /* set up to autoclear timer, and the vectors */ 2496 mask = IXGBE_EIMS_ENABLE_MASK; 2497 mask &= ~(IXGBE_EIMS_OTHER | 2498 IXGBE_EIMS_MAILBOX | 2499 IXGBE_EIMS_LSC); 2500 2501 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2502 } 2503 2504 /** 2505 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2506 * @q_vector: structure containing interrupt and ring information 2507 * @ring_container: structure containing ring performance data 2508 * 2509 * Stores a new ITR value based on packets and byte 2510 * counts during the last interrupt. The advantage of per interrupt 2511 * computation is faster updates and more accurate ITR for the current 2512 * traffic pattern. Constants in this function were computed 2513 * based on theoretical maximum wire speed and thresholds were set based 2514 * on testing data as well as attempting to minimize response time 2515 * while increasing bulk throughput. 2516 **/ 2517 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2518 struct ixgbe_ring_container *ring_container) 2519 { 2520 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2521 IXGBE_ITR_ADAPTIVE_LATENCY; 2522 unsigned int avg_wire_size, packets, bytes; 2523 unsigned long next_update = jiffies; 2524 2525 /* If we don't have any rings just leave ourselves set for maximum 2526 * possible latency so we take ourselves out of the equation. 2527 */ 2528 if (!ring_container->ring) 2529 return; 2530 2531 /* If we didn't update within up to 1 - 2 jiffies we can assume 2532 * that either packets are coming in so slow there hasn't been 2533 * any work, or that there is so much work that NAPI is dealing 2534 * with interrupt moderation and we don't need to do anything. 2535 */ 2536 if (time_after(next_update, ring_container->next_update)) 2537 goto clear_counts; 2538 2539 packets = ring_container->total_packets; 2540 2541 /* We have no packets to actually measure against. This means 2542 * either one of the other queues on this vector is active or 2543 * we are a Tx queue doing TSO with too high of an interrupt rate. 2544 * 2545 * When this occurs just tick up our delay by the minimum value 2546 * and hope that this extra delay will prevent us from being called 2547 * without any work on our queue. 2548 */ 2549 if (!packets) { 2550 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2551 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2552 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2553 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2554 goto clear_counts; 2555 } 2556 2557 bytes = ring_container->total_bytes; 2558 2559 /* If packets are less than 4 or bytes are less than 9000 assume 2560 * insufficient data to use bulk rate limiting approach. We are 2561 * likely latency driven. 2562 */ 2563 if (packets < 4 && bytes < 9000) { 2564 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2565 goto adjust_by_size; 2566 } 2567 2568 /* Between 4 and 48 we can assume that our current interrupt delay 2569 * is only slightly too low. As such we should increase it by a small 2570 * fixed amount. 2571 */ 2572 if (packets < 48) { 2573 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2574 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2575 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2576 goto clear_counts; 2577 } 2578 2579 /* Between 48 and 96 is our "goldilocks" zone where we are working 2580 * out "just right". Just report that our current ITR is good for us. 2581 */ 2582 if (packets < 96) { 2583 itr = q_vector->itr >> 2; 2584 goto clear_counts; 2585 } 2586 2587 /* If packet count is 96 or greater we are likely looking at a slight 2588 * overrun of the delay we want. Try halving our delay to see if that 2589 * will cut the number of packets in half per interrupt. 2590 */ 2591 if (packets < 256) { 2592 itr = q_vector->itr >> 3; 2593 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2594 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2595 goto clear_counts; 2596 } 2597 2598 /* The paths below assume we are dealing with a bulk ITR since number 2599 * of packets is 256 or greater. We are just going to have to compute 2600 * a value and try to bring the count under control, though for smaller 2601 * packet sizes there isn't much we can do as NAPI polling will likely 2602 * be kicking in sooner rather than later. 2603 */ 2604 itr = IXGBE_ITR_ADAPTIVE_BULK; 2605 2606 adjust_by_size: 2607 /* If packet counts are 256 or greater we can assume we have a gross 2608 * overestimation of what the rate should be. Instead of trying to fine 2609 * tune it just use the formula below to try and dial in an exact value 2610 * give the current packet size of the frame. 2611 */ 2612 avg_wire_size = bytes / packets; 2613 2614 /* The following is a crude approximation of: 2615 * wmem_default / (size + overhead) = desired_pkts_per_int 2616 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2617 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2618 * 2619 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2620 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2621 * formula down to 2622 * 2623 * (170 * (size + 24)) / (size + 640) = ITR 2624 * 2625 * We first do some math on the packet size and then finally bitshift 2626 * by 8 after rounding up. We also have to account for PCIe link speed 2627 * difference as ITR scales based on this. 2628 */ 2629 if (avg_wire_size <= 60) { 2630 /* Start at 50k ints/sec */ 2631 avg_wire_size = 5120; 2632 } else if (avg_wire_size <= 316) { 2633 /* 50K ints/sec to 16K ints/sec */ 2634 avg_wire_size *= 40; 2635 avg_wire_size += 2720; 2636 } else if (avg_wire_size <= 1084) { 2637 /* 16K ints/sec to 9.2K ints/sec */ 2638 avg_wire_size *= 15; 2639 avg_wire_size += 11452; 2640 } else if (avg_wire_size < 1968) { 2641 /* 9.2K ints/sec to 8K ints/sec */ 2642 avg_wire_size *= 5; 2643 avg_wire_size += 22420; 2644 } else { 2645 /* plateau at a limit of 8K ints/sec */ 2646 avg_wire_size = 32256; 2647 } 2648 2649 /* If we are in low latency mode half our delay which doubles the rate 2650 * to somewhere between 100K to 16K ints/sec 2651 */ 2652 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2653 avg_wire_size >>= 1; 2654 2655 /* Resultant value is 256 times larger than it needs to be. This 2656 * gives us room to adjust the value as needed to either increase 2657 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2658 * 2659 * Use addition as we have already recorded the new latency flag 2660 * for the ITR value. 2661 */ 2662 switch (q_vector->adapter->link_speed) { 2663 case IXGBE_LINK_SPEED_10GB_FULL: 2664 case IXGBE_LINK_SPEED_100_FULL: 2665 default: 2666 itr += DIV_ROUND_UP(avg_wire_size, 2667 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2668 IXGBE_ITR_ADAPTIVE_MIN_INC; 2669 break; 2670 case IXGBE_LINK_SPEED_2_5GB_FULL: 2671 case IXGBE_LINK_SPEED_1GB_FULL: 2672 case IXGBE_LINK_SPEED_10_FULL: 2673 if (avg_wire_size > 8064) 2674 avg_wire_size = 8064; 2675 itr += DIV_ROUND_UP(avg_wire_size, 2676 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2677 IXGBE_ITR_ADAPTIVE_MIN_INC; 2678 break; 2679 } 2680 2681 clear_counts: 2682 /* write back value */ 2683 ring_container->itr = itr; 2684 2685 /* next update should occur within next jiffy */ 2686 ring_container->next_update = next_update + 1; 2687 2688 ring_container->total_bytes = 0; 2689 ring_container->total_packets = 0; 2690 } 2691 2692 /** 2693 * ixgbe_write_eitr - write EITR register in hardware specific way 2694 * @q_vector: structure containing interrupt and ring information 2695 * 2696 * This function is made to be called by ethtool and by the driver 2697 * when it needs to update EITR registers at runtime. Hardware 2698 * specific quirks/differences are taken care of here. 2699 */ 2700 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2701 { 2702 struct ixgbe_adapter *adapter = q_vector->adapter; 2703 struct ixgbe_hw *hw = &adapter->hw; 2704 int v_idx = q_vector->v_idx; 2705 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2706 2707 switch (adapter->hw.mac.type) { 2708 case ixgbe_mac_82598EB: 2709 /* must write high and low 16 bits to reset counter */ 2710 itr_reg |= (itr_reg << 16); 2711 break; 2712 case ixgbe_mac_82599EB: 2713 case ixgbe_mac_X540: 2714 case ixgbe_mac_X550: 2715 case ixgbe_mac_X550EM_x: 2716 case ixgbe_mac_x550em_a: 2717 /* 2718 * set the WDIS bit to not clear the timer bits and cause an 2719 * immediate assertion of the interrupt 2720 */ 2721 itr_reg |= IXGBE_EITR_CNT_WDIS; 2722 break; 2723 default: 2724 break; 2725 } 2726 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2727 } 2728 2729 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2730 { 2731 u32 new_itr; 2732 2733 ixgbe_update_itr(q_vector, &q_vector->tx); 2734 ixgbe_update_itr(q_vector, &q_vector->rx); 2735 2736 /* use the smallest value of new ITR delay calculations */ 2737 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2738 2739 /* Clear latency flag if set, shift into correct position */ 2740 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2741 new_itr <<= 2; 2742 2743 if (new_itr != q_vector->itr) { 2744 /* save the algorithm value here */ 2745 q_vector->itr = new_itr; 2746 2747 ixgbe_write_eitr(q_vector); 2748 } 2749 } 2750 2751 /** 2752 * ixgbe_check_overtemp_subtask - check for over temperature 2753 * @adapter: pointer to adapter 2754 **/ 2755 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2756 { 2757 struct ixgbe_hw *hw = &adapter->hw; 2758 u32 eicr = adapter->interrupt_event; 2759 2760 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2761 return; 2762 2763 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2764 return; 2765 2766 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2767 2768 switch (hw->device_id) { 2769 case IXGBE_DEV_ID_82599_T3_LOM: 2770 /* 2771 * Since the warning interrupt is for both ports 2772 * we don't have to check if: 2773 * - This interrupt wasn't for our port. 2774 * - We may have missed the interrupt so always have to 2775 * check if we got a LSC 2776 */ 2777 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2778 !(eicr & IXGBE_EICR_LSC)) 2779 return; 2780 2781 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2782 u32 speed; 2783 bool link_up = false; 2784 2785 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2786 2787 if (link_up) 2788 return; 2789 } 2790 2791 /* Check if this is not due to overtemp */ 2792 if (!hw->phy.ops.check_overtemp(hw)) 2793 return; 2794 2795 break; 2796 case IXGBE_DEV_ID_X550EM_A_1G_T: 2797 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2798 if (!hw->phy.ops.check_overtemp(hw)) 2799 return; 2800 break; 2801 default: 2802 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2803 return; 2804 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2805 return; 2806 break; 2807 } 2808 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2809 2810 adapter->interrupt_event = 0; 2811 } 2812 2813 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2814 { 2815 struct ixgbe_hw *hw = &adapter->hw; 2816 2817 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2818 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2819 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2820 /* write to clear the interrupt */ 2821 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2822 } 2823 } 2824 2825 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2826 { 2827 struct ixgbe_hw *hw = &adapter->hw; 2828 2829 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2830 return; 2831 2832 switch (adapter->hw.mac.type) { 2833 case ixgbe_mac_82599EB: 2834 /* 2835 * Need to check link state so complete overtemp check 2836 * on service task 2837 */ 2838 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2839 (eicr & IXGBE_EICR_LSC)) && 2840 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2841 adapter->interrupt_event = eicr; 2842 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2843 ixgbe_service_event_schedule(adapter); 2844 return; 2845 } 2846 return; 2847 case ixgbe_mac_x550em_a: 2848 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2849 adapter->interrupt_event = eicr; 2850 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2851 ixgbe_service_event_schedule(adapter); 2852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2853 IXGBE_EICR_GPI_SDP0_X550EM_a); 2854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2855 IXGBE_EICR_GPI_SDP0_X550EM_a); 2856 } 2857 return; 2858 case ixgbe_mac_X550: 2859 case ixgbe_mac_X540: 2860 if (!(eicr & IXGBE_EICR_TS)) 2861 return; 2862 break; 2863 default: 2864 return; 2865 } 2866 2867 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2868 } 2869 2870 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2871 { 2872 switch (hw->mac.type) { 2873 case ixgbe_mac_82598EB: 2874 if (hw->phy.type == ixgbe_phy_nl) 2875 return true; 2876 return false; 2877 case ixgbe_mac_82599EB: 2878 case ixgbe_mac_X550EM_x: 2879 case ixgbe_mac_x550em_a: 2880 switch (hw->mac.ops.get_media_type(hw)) { 2881 case ixgbe_media_type_fiber: 2882 case ixgbe_media_type_fiber_qsfp: 2883 return true; 2884 default: 2885 return false; 2886 } 2887 default: 2888 return false; 2889 } 2890 } 2891 2892 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2893 { 2894 struct ixgbe_hw *hw = &adapter->hw; 2895 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2896 2897 if (!ixgbe_is_sfp(hw)) 2898 return; 2899 2900 /* Later MAC's use different SDP */ 2901 if (hw->mac.type >= ixgbe_mac_X540) 2902 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2903 2904 if (eicr & eicr_mask) { 2905 /* Clear the interrupt */ 2906 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2907 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2908 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2909 adapter->sfp_poll_time = 0; 2910 ixgbe_service_event_schedule(adapter); 2911 } 2912 } 2913 2914 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2915 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2916 /* Clear the interrupt */ 2917 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2918 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2919 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2920 ixgbe_service_event_schedule(adapter); 2921 } 2922 } 2923 } 2924 2925 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2926 { 2927 struct ixgbe_hw *hw = &adapter->hw; 2928 2929 adapter->lsc_int++; 2930 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2931 adapter->link_check_timeout = jiffies; 2932 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2933 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2934 IXGBE_WRITE_FLUSH(hw); 2935 ixgbe_service_event_schedule(adapter); 2936 } 2937 } 2938 2939 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2940 u64 qmask) 2941 { 2942 struct ixgbe_hw *hw = &adapter->hw; 2943 u32 mask; 2944 2945 switch (hw->mac.type) { 2946 case ixgbe_mac_82598EB: 2947 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2948 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2949 break; 2950 case ixgbe_mac_82599EB: 2951 case ixgbe_mac_X540: 2952 case ixgbe_mac_X550: 2953 case ixgbe_mac_X550EM_x: 2954 case ixgbe_mac_x550em_a: 2955 mask = (qmask & 0xFFFFFFFF); 2956 if (mask) 2957 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2958 mask = (qmask >> 32); 2959 if (mask) 2960 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2961 break; 2962 default: 2963 break; 2964 } 2965 /* skip the flush */ 2966 } 2967 2968 /** 2969 * ixgbe_irq_enable - Enable default interrupt generation settings 2970 * @adapter: board private structure 2971 * @queues: enable irqs for queues 2972 * @flush: flush register write 2973 **/ 2974 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2975 bool flush) 2976 { 2977 struct ixgbe_hw *hw = &adapter->hw; 2978 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2979 2980 /* don't reenable LSC while waiting for link */ 2981 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2982 mask &= ~IXGBE_EIMS_LSC; 2983 2984 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2985 switch (adapter->hw.mac.type) { 2986 case ixgbe_mac_82599EB: 2987 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2988 break; 2989 case ixgbe_mac_X540: 2990 case ixgbe_mac_X550: 2991 case ixgbe_mac_X550EM_x: 2992 case ixgbe_mac_x550em_a: 2993 mask |= IXGBE_EIMS_TS; 2994 break; 2995 default: 2996 break; 2997 } 2998 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2999 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3000 switch (adapter->hw.mac.type) { 3001 case ixgbe_mac_82599EB: 3002 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3003 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3004 fallthrough; 3005 case ixgbe_mac_X540: 3006 case ixgbe_mac_X550: 3007 case ixgbe_mac_X550EM_x: 3008 case ixgbe_mac_x550em_a: 3009 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3010 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3011 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3012 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3013 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3014 mask |= IXGBE_EICR_GPI_SDP0_X540; 3015 mask |= IXGBE_EIMS_ECC; 3016 mask |= IXGBE_EIMS_MAILBOX; 3017 break; 3018 default: 3019 break; 3020 } 3021 3022 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3023 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3024 mask |= IXGBE_EIMS_FLOW_DIR; 3025 3026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3027 if (queues) 3028 ixgbe_irq_enable_queues(adapter, ~0); 3029 if (flush) 3030 IXGBE_WRITE_FLUSH(&adapter->hw); 3031 } 3032 3033 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3034 { 3035 struct ixgbe_adapter *adapter = data; 3036 struct ixgbe_hw *hw = &adapter->hw; 3037 u32 eicr; 3038 3039 /* 3040 * Workaround for Silicon errata. Use clear-by-write instead 3041 * of clear-by-read. Reading with EICS will return the 3042 * interrupt causes without clearing, which later be done 3043 * with the write to EICR. 3044 */ 3045 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3046 3047 /* The lower 16bits of the EICR register are for the queue interrupts 3048 * which should be masked here in order to not accidentally clear them if 3049 * the bits are high when ixgbe_msix_other is called. There is a race 3050 * condition otherwise which results in possible performance loss 3051 * especially if the ixgbe_msix_other interrupt is triggering 3052 * consistently (as it would when PPS is turned on for the X540 device) 3053 */ 3054 eicr &= 0xFFFF0000; 3055 3056 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3057 3058 if (eicr & IXGBE_EICR_LSC) 3059 ixgbe_check_lsc(adapter); 3060 3061 if (eicr & IXGBE_EICR_MAILBOX) 3062 ixgbe_msg_task(adapter); 3063 3064 switch (hw->mac.type) { 3065 case ixgbe_mac_82599EB: 3066 case ixgbe_mac_X540: 3067 case ixgbe_mac_X550: 3068 case ixgbe_mac_X550EM_x: 3069 case ixgbe_mac_x550em_a: 3070 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3071 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3072 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3073 ixgbe_service_event_schedule(adapter); 3074 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3075 IXGBE_EICR_GPI_SDP0_X540); 3076 } 3077 if (eicr & IXGBE_EICR_ECC) { 3078 e_info(link, "Received ECC Err, initiating reset\n"); 3079 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3080 ixgbe_service_event_schedule(adapter); 3081 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3082 } 3083 /* Handle Flow Director Full threshold interrupt */ 3084 if (eicr & IXGBE_EICR_FLOW_DIR) { 3085 int reinit_count = 0; 3086 int i; 3087 for (i = 0; i < adapter->num_tx_queues; i++) { 3088 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3089 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3090 &ring->state)) 3091 reinit_count++; 3092 } 3093 if (reinit_count) { 3094 /* no more flow director interrupts until after init */ 3095 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3096 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3097 ixgbe_service_event_schedule(adapter); 3098 } 3099 } 3100 ixgbe_check_sfp_event(adapter, eicr); 3101 ixgbe_check_overtemp_event(adapter, eicr); 3102 break; 3103 default: 3104 break; 3105 } 3106 3107 ixgbe_check_fan_failure(adapter, eicr); 3108 3109 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3110 ixgbe_ptp_check_pps_event(adapter); 3111 3112 /* re-enable the original interrupt state, no lsc, no queues */ 3113 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3114 ixgbe_irq_enable(adapter, false, false); 3115 3116 return IRQ_HANDLED; 3117 } 3118 3119 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3120 { 3121 struct ixgbe_q_vector *q_vector = data; 3122 3123 /* EIAM disabled interrupts (on this vector) for us */ 3124 3125 if (q_vector->rx.ring || q_vector->tx.ring) 3126 napi_schedule_irqoff(&q_vector->napi); 3127 3128 return IRQ_HANDLED; 3129 } 3130 3131 /** 3132 * ixgbe_poll - NAPI Rx polling callback 3133 * @napi: structure for representing this polling device 3134 * @budget: how many packets driver is allowed to clean 3135 * 3136 * This function is used for legacy and MSI, NAPI mode 3137 **/ 3138 int ixgbe_poll(struct napi_struct *napi, int budget) 3139 { 3140 struct ixgbe_q_vector *q_vector = 3141 container_of(napi, struct ixgbe_q_vector, napi); 3142 struct ixgbe_adapter *adapter = q_vector->adapter; 3143 struct ixgbe_ring *ring; 3144 int per_ring_budget, work_done = 0; 3145 bool clean_complete = true; 3146 3147 #ifdef CONFIG_IXGBE_DCA 3148 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3149 ixgbe_update_dca(q_vector); 3150 #endif 3151 3152 ixgbe_for_each_ring(ring, q_vector->tx) { 3153 bool wd = ring->xsk_pool ? 3154 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3155 ixgbe_clean_tx_irq(q_vector, ring, budget); 3156 3157 if (!wd) 3158 clean_complete = false; 3159 } 3160 3161 /* Exit if we are called by netpoll */ 3162 if (budget <= 0) 3163 return budget; 3164 3165 /* attempt to distribute budget to each queue fairly, but don't allow 3166 * the budget to go below 1 because we'll exit polling */ 3167 if (q_vector->rx.count > 1) 3168 per_ring_budget = max(budget/q_vector->rx.count, 1); 3169 else 3170 per_ring_budget = budget; 3171 3172 ixgbe_for_each_ring(ring, q_vector->rx) { 3173 int cleaned = ring->xsk_pool ? 3174 ixgbe_clean_rx_irq_zc(q_vector, ring, 3175 per_ring_budget) : 3176 ixgbe_clean_rx_irq(q_vector, ring, 3177 per_ring_budget); 3178 3179 work_done += cleaned; 3180 if (cleaned >= per_ring_budget) 3181 clean_complete = false; 3182 } 3183 3184 /* If all work not completed, return budget and keep polling */ 3185 if (!clean_complete) 3186 return budget; 3187 3188 /* all work done, exit the polling mode */ 3189 if (likely(napi_complete_done(napi, work_done))) { 3190 if (adapter->rx_itr_setting & 1) 3191 ixgbe_set_itr(q_vector); 3192 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3193 ixgbe_irq_enable_queues(adapter, 3194 BIT_ULL(q_vector->v_idx)); 3195 } 3196 3197 return min(work_done, budget - 1); 3198 } 3199 3200 /** 3201 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3202 * @adapter: board private structure 3203 * 3204 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3205 * interrupts from the kernel. 3206 **/ 3207 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3208 { 3209 struct net_device *netdev = adapter->netdev; 3210 unsigned int ri = 0, ti = 0; 3211 int vector, err; 3212 3213 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3214 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3215 struct msix_entry *entry = &adapter->msix_entries[vector]; 3216 3217 if (q_vector->tx.ring && q_vector->rx.ring) { 3218 snprintf(q_vector->name, sizeof(q_vector->name), 3219 "%s-TxRx-%u", netdev->name, ri++); 3220 ti++; 3221 } else if (q_vector->rx.ring) { 3222 snprintf(q_vector->name, sizeof(q_vector->name), 3223 "%s-rx-%u", netdev->name, ri++); 3224 } else if (q_vector->tx.ring) { 3225 snprintf(q_vector->name, sizeof(q_vector->name), 3226 "%s-tx-%u", netdev->name, ti++); 3227 } else { 3228 /* skip this unused q_vector */ 3229 continue; 3230 } 3231 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3232 q_vector->name, q_vector); 3233 if (err) { 3234 e_err(probe, "request_irq failed for MSIX interrupt " 3235 "Error: %d\n", err); 3236 goto free_queue_irqs; 3237 } 3238 /* If Flow Director is enabled, set interrupt affinity */ 3239 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3240 /* assign the mask for this irq */ 3241 irq_update_affinity_hint(entry->vector, 3242 &q_vector->affinity_mask); 3243 } 3244 } 3245 3246 err = request_irq(adapter->msix_entries[vector].vector, 3247 ixgbe_msix_other, 0, netdev->name, adapter); 3248 if (err) { 3249 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3250 goto free_queue_irqs; 3251 } 3252 3253 return 0; 3254 3255 free_queue_irqs: 3256 while (vector) { 3257 vector--; 3258 irq_update_affinity_hint(adapter->msix_entries[vector].vector, 3259 NULL); 3260 free_irq(adapter->msix_entries[vector].vector, 3261 adapter->q_vector[vector]); 3262 } 3263 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3264 pci_disable_msix(adapter->pdev); 3265 kfree(adapter->msix_entries); 3266 adapter->msix_entries = NULL; 3267 return err; 3268 } 3269 3270 /** 3271 * ixgbe_intr - legacy mode Interrupt Handler 3272 * @irq: interrupt number 3273 * @data: pointer to a network interface device structure 3274 **/ 3275 static irqreturn_t ixgbe_intr(int irq, void *data) 3276 { 3277 struct ixgbe_adapter *adapter = data; 3278 struct ixgbe_hw *hw = &adapter->hw; 3279 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3280 u32 eicr; 3281 3282 /* 3283 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3284 * before the read of EICR. 3285 */ 3286 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3287 3288 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3289 * therefore no explicit interrupt disable is necessary */ 3290 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3291 if (!eicr) { 3292 /* 3293 * shared interrupt alert! 3294 * make sure interrupts are enabled because the read will 3295 * have disabled interrupts due to EIAM 3296 * finish the workaround of silicon errata on 82598. Unmask 3297 * the interrupt that we masked before the EICR read. 3298 */ 3299 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3300 ixgbe_irq_enable(adapter, true, true); 3301 return IRQ_NONE; /* Not our interrupt */ 3302 } 3303 3304 if (eicr & IXGBE_EICR_LSC) 3305 ixgbe_check_lsc(adapter); 3306 3307 switch (hw->mac.type) { 3308 case ixgbe_mac_82599EB: 3309 ixgbe_check_sfp_event(adapter, eicr); 3310 fallthrough; 3311 case ixgbe_mac_X540: 3312 case ixgbe_mac_X550: 3313 case ixgbe_mac_X550EM_x: 3314 case ixgbe_mac_x550em_a: 3315 if (eicr & IXGBE_EICR_ECC) { 3316 e_info(link, "Received ECC Err, initiating reset\n"); 3317 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3318 ixgbe_service_event_schedule(adapter); 3319 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3320 } 3321 ixgbe_check_overtemp_event(adapter, eicr); 3322 break; 3323 default: 3324 break; 3325 } 3326 3327 ixgbe_check_fan_failure(adapter, eicr); 3328 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3329 ixgbe_ptp_check_pps_event(adapter); 3330 3331 /* would disable interrupts here but EIAM disabled it */ 3332 napi_schedule_irqoff(&q_vector->napi); 3333 3334 /* 3335 * re-enable link(maybe) and non-queue interrupts, no flush. 3336 * ixgbe_poll will re-enable the queue interrupts 3337 */ 3338 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3339 ixgbe_irq_enable(adapter, false, false); 3340 3341 return IRQ_HANDLED; 3342 } 3343 3344 /** 3345 * ixgbe_request_irq - initialize interrupts 3346 * @adapter: board private structure 3347 * 3348 * Attempts to configure interrupts using the best available 3349 * capabilities of the hardware and kernel. 3350 **/ 3351 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3352 { 3353 struct net_device *netdev = adapter->netdev; 3354 int err; 3355 3356 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3357 err = ixgbe_request_msix_irqs(adapter); 3358 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3359 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3360 netdev->name, adapter); 3361 else 3362 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3363 netdev->name, adapter); 3364 3365 if (err) 3366 e_err(probe, "request_irq failed, Error %d\n", err); 3367 3368 return err; 3369 } 3370 3371 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3372 { 3373 int vector; 3374 3375 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3376 free_irq(adapter->pdev->irq, adapter); 3377 return; 3378 } 3379 3380 if (!adapter->msix_entries) 3381 return; 3382 3383 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3384 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3385 struct msix_entry *entry = &adapter->msix_entries[vector]; 3386 3387 /* free only the irqs that were actually requested */ 3388 if (!q_vector->rx.ring && !q_vector->tx.ring) 3389 continue; 3390 3391 /* clear the affinity_mask in the IRQ descriptor */ 3392 irq_update_affinity_hint(entry->vector, NULL); 3393 3394 free_irq(entry->vector, q_vector); 3395 } 3396 3397 free_irq(adapter->msix_entries[vector].vector, adapter); 3398 } 3399 3400 /** 3401 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3402 * @adapter: board private structure 3403 **/ 3404 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3405 { 3406 switch (adapter->hw.mac.type) { 3407 case ixgbe_mac_82598EB: 3408 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3409 break; 3410 case ixgbe_mac_82599EB: 3411 case ixgbe_mac_X540: 3412 case ixgbe_mac_X550: 3413 case ixgbe_mac_X550EM_x: 3414 case ixgbe_mac_x550em_a: 3415 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3418 break; 3419 default: 3420 break; 3421 } 3422 IXGBE_WRITE_FLUSH(&adapter->hw); 3423 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3424 int vector; 3425 3426 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3427 synchronize_irq(adapter->msix_entries[vector].vector); 3428 3429 synchronize_irq(adapter->msix_entries[vector++].vector); 3430 } else { 3431 synchronize_irq(adapter->pdev->irq); 3432 } 3433 } 3434 3435 /** 3436 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3437 * @adapter: board private structure 3438 * 3439 **/ 3440 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3441 { 3442 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3443 3444 ixgbe_write_eitr(q_vector); 3445 3446 ixgbe_set_ivar(adapter, 0, 0, 0); 3447 ixgbe_set_ivar(adapter, 1, 0, 0); 3448 3449 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3450 } 3451 3452 /** 3453 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3454 * @adapter: board private structure 3455 * @ring: structure containing ring specific data 3456 * 3457 * Configure the Tx descriptor ring after a reset. 3458 **/ 3459 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3460 struct ixgbe_ring *ring) 3461 { 3462 struct ixgbe_hw *hw = &adapter->hw; 3463 u64 tdba = ring->dma; 3464 int wait_loop = 10; 3465 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3466 u8 reg_idx = ring->reg_idx; 3467 3468 ring->xsk_pool = NULL; 3469 if (ring_is_xdp(ring)) 3470 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3471 3472 /* disable queue to avoid issues while updating state */ 3473 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3474 IXGBE_WRITE_FLUSH(hw); 3475 3476 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3477 (tdba & DMA_BIT_MASK(32))); 3478 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3479 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3480 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3481 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3482 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3483 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3484 3485 /* 3486 * set WTHRESH to encourage burst writeback, it should not be set 3487 * higher than 1 when: 3488 * - ITR is 0 as it could cause false TX hangs 3489 * - ITR is set to > 100k int/sec and BQL is enabled 3490 * 3491 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3492 * to or less than the number of on chip descriptors, which is 3493 * currently 40. 3494 */ 3495 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3496 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3497 else 3498 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3499 3500 /* 3501 * Setting PTHRESH to 32 both improves performance 3502 * and avoids a TX hang with DFP enabled 3503 */ 3504 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3505 32; /* PTHRESH = 32 */ 3506 3507 /* reinitialize flowdirector state */ 3508 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3509 ring->atr_sample_rate = adapter->atr_sample_rate; 3510 ring->atr_count = 0; 3511 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3512 } else { 3513 ring->atr_sample_rate = 0; 3514 } 3515 3516 /* initialize XPS */ 3517 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3518 struct ixgbe_q_vector *q_vector = ring->q_vector; 3519 3520 if (q_vector) 3521 netif_set_xps_queue(ring->netdev, 3522 &q_vector->affinity_mask, 3523 ring->queue_index); 3524 } 3525 3526 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3527 3528 /* reinitialize tx_buffer_info */ 3529 memset(ring->tx_buffer_info, 0, 3530 sizeof(struct ixgbe_tx_buffer) * ring->count); 3531 3532 /* enable queue */ 3533 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3534 3535 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3536 if (hw->mac.type == ixgbe_mac_82598EB && 3537 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3538 return; 3539 3540 /* poll to verify queue is enabled */ 3541 do { 3542 usleep_range(1000, 2000); 3543 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3544 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3545 if (!wait_loop) 3546 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3547 } 3548 3549 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3550 { 3551 struct ixgbe_hw *hw = &adapter->hw; 3552 u32 rttdcs, mtqc; 3553 u8 tcs = adapter->hw_tcs; 3554 3555 if (hw->mac.type == ixgbe_mac_82598EB) 3556 return; 3557 3558 /* disable the arbiter while setting MTQC */ 3559 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3560 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3561 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3562 3563 /* set transmit pool layout */ 3564 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3565 mtqc = IXGBE_MTQC_VT_ENA; 3566 if (tcs > 4) 3567 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3568 else if (tcs > 1) 3569 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3570 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3571 IXGBE_82599_VMDQ_4Q_MASK) 3572 mtqc |= IXGBE_MTQC_32VF; 3573 else 3574 mtqc |= IXGBE_MTQC_64VF; 3575 } else { 3576 if (tcs > 4) { 3577 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3578 } else if (tcs > 1) { 3579 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3580 } else { 3581 u8 max_txq = adapter->num_tx_queues + 3582 adapter->num_xdp_queues; 3583 if (max_txq > 63) 3584 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3585 else 3586 mtqc = IXGBE_MTQC_64Q_1PB; 3587 } 3588 } 3589 3590 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3591 3592 /* Enable Security TX Buffer IFG for multiple pb */ 3593 if (tcs) { 3594 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3595 sectx |= IXGBE_SECTX_DCB; 3596 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3597 } 3598 3599 /* re-enable the arbiter */ 3600 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3601 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3602 } 3603 3604 /** 3605 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3606 * @adapter: board private structure 3607 * 3608 * Configure the Tx unit of the MAC after a reset. 3609 **/ 3610 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3611 { 3612 struct ixgbe_hw *hw = &adapter->hw; 3613 u32 dmatxctl; 3614 u32 i; 3615 3616 ixgbe_setup_mtqc(adapter); 3617 3618 if (hw->mac.type != ixgbe_mac_82598EB) { 3619 /* DMATXCTL.EN must be before Tx queues are enabled */ 3620 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3621 dmatxctl |= IXGBE_DMATXCTL_TE; 3622 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3623 } 3624 3625 /* Setup the HW Tx Head and Tail descriptor pointers */ 3626 for (i = 0; i < adapter->num_tx_queues; i++) 3627 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3628 for (i = 0; i < adapter->num_xdp_queues; i++) 3629 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3630 } 3631 3632 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3633 struct ixgbe_ring *ring) 3634 { 3635 struct ixgbe_hw *hw = &adapter->hw; 3636 u8 reg_idx = ring->reg_idx; 3637 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3638 3639 srrctl |= IXGBE_SRRCTL_DROP_EN; 3640 3641 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3642 } 3643 3644 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3645 struct ixgbe_ring *ring) 3646 { 3647 struct ixgbe_hw *hw = &adapter->hw; 3648 u8 reg_idx = ring->reg_idx; 3649 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3650 3651 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3652 3653 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3654 } 3655 3656 #ifdef CONFIG_IXGBE_DCB 3657 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3658 #else 3659 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3660 #endif 3661 { 3662 int i; 3663 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3664 3665 if (adapter->ixgbe_ieee_pfc) 3666 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3667 3668 /* 3669 * We should set the drop enable bit if: 3670 * SR-IOV is enabled 3671 * or 3672 * Number of Rx queues > 1 and flow control is disabled 3673 * 3674 * This allows us to avoid head of line blocking for security 3675 * and performance reasons. 3676 */ 3677 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3678 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3679 for (i = 0; i < adapter->num_rx_queues; i++) 3680 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3681 } else { 3682 for (i = 0; i < adapter->num_rx_queues; i++) 3683 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3684 } 3685 } 3686 3687 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3688 3689 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3690 struct ixgbe_ring *rx_ring) 3691 { 3692 struct ixgbe_hw *hw = &adapter->hw; 3693 u32 srrctl; 3694 u8 reg_idx = rx_ring->reg_idx; 3695 3696 if (hw->mac.type == ixgbe_mac_82598EB) { 3697 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3698 3699 /* 3700 * if VMDq is not active we must program one srrctl register 3701 * per RSS queue since we have enabled RDRXCTL.MVMEN 3702 */ 3703 reg_idx &= mask; 3704 } 3705 3706 /* configure header buffer length, needed for RSC */ 3707 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3708 3709 /* configure the packet buffer length */ 3710 if (rx_ring->xsk_pool) { 3711 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 3712 3713 /* If the MAC support setting RXDCTL.RLPML, the 3714 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3715 * RXDCTL.RLPML is set to the actual UMEM buffer 3716 * size. If not, then we are stuck with a 1k buffer 3717 * size resolution. In this case frames larger than 3718 * the UMEM buffer size viewed in a 1k resolution will 3719 * be dropped. 3720 */ 3721 if (hw->mac.type != ixgbe_mac_82599EB) 3722 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3723 else 3724 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3725 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3726 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3727 } else { 3728 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3729 } 3730 3731 /* configure descriptor type */ 3732 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3733 3734 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3735 } 3736 3737 /** 3738 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3739 * @adapter: device handle 3740 * 3741 * - 82598/82599/X540: 128 3742 * - X550(non-SRIOV mode): 512 3743 * - X550(SRIOV mode): 64 3744 */ 3745 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3746 { 3747 if (adapter->hw.mac.type < ixgbe_mac_X550) 3748 return 128; 3749 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3750 return 64; 3751 else 3752 return 512; 3753 } 3754 3755 /** 3756 * ixgbe_store_key - Write the RSS key to HW 3757 * @adapter: device handle 3758 * 3759 * Write the RSS key stored in adapter.rss_key to HW. 3760 */ 3761 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3762 { 3763 struct ixgbe_hw *hw = &adapter->hw; 3764 int i; 3765 3766 for (i = 0; i < 10; i++) 3767 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3768 } 3769 3770 /** 3771 * ixgbe_init_rss_key - Initialize adapter RSS key 3772 * @adapter: device handle 3773 * 3774 * Allocates and initializes the RSS key if it is not allocated. 3775 **/ 3776 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3777 { 3778 u32 *rss_key; 3779 3780 if (!adapter->rss_key) { 3781 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3782 if (unlikely(!rss_key)) 3783 return -ENOMEM; 3784 3785 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3786 adapter->rss_key = rss_key; 3787 } 3788 3789 return 0; 3790 } 3791 3792 /** 3793 * ixgbe_store_reta - Write the RETA table to HW 3794 * @adapter: device handle 3795 * 3796 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3797 */ 3798 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3799 { 3800 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3801 struct ixgbe_hw *hw = &adapter->hw; 3802 u32 reta = 0; 3803 u32 indices_multi; 3804 u8 *indir_tbl = adapter->rss_indir_tbl; 3805 3806 /* Fill out the redirection table as follows: 3807 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3808 * indices. 3809 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3810 * - X550: 8 bit wide entries containing 6 bit RSS index 3811 */ 3812 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3813 indices_multi = 0x11; 3814 else 3815 indices_multi = 0x1; 3816 3817 /* Write redirection table to HW */ 3818 for (i = 0; i < reta_entries; i++) { 3819 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3820 if ((i & 3) == 3) { 3821 if (i < 128) 3822 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3823 else 3824 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3825 reta); 3826 reta = 0; 3827 } 3828 } 3829 } 3830 3831 /** 3832 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3833 * @adapter: device handle 3834 * 3835 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3836 */ 3837 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3838 { 3839 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3840 struct ixgbe_hw *hw = &adapter->hw; 3841 u32 vfreta = 0; 3842 3843 /* Write redirection table to HW */ 3844 for (i = 0; i < reta_entries; i++) { 3845 u16 pool = adapter->num_rx_pools; 3846 3847 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3848 if ((i & 3) != 3) 3849 continue; 3850 3851 while (pool--) 3852 IXGBE_WRITE_REG(hw, 3853 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3854 vfreta); 3855 vfreta = 0; 3856 } 3857 } 3858 3859 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3860 { 3861 u32 i, j; 3862 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3863 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3864 3865 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3866 * make full use of any rings they may have. We will use the 3867 * PSRTYPE register to control how many rings we use within the PF. 3868 */ 3869 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3870 rss_i = 4; 3871 3872 /* Fill out hash function seeds */ 3873 ixgbe_store_key(adapter); 3874 3875 /* Fill out redirection table */ 3876 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3877 3878 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3879 if (j == rss_i) 3880 j = 0; 3881 3882 adapter->rss_indir_tbl[i] = j; 3883 } 3884 3885 ixgbe_store_reta(adapter); 3886 } 3887 3888 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3889 { 3890 struct ixgbe_hw *hw = &adapter->hw; 3891 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3892 int i, j; 3893 3894 /* Fill out hash function seeds */ 3895 for (i = 0; i < 10; i++) { 3896 u16 pool = adapter->num_rx_pools; 3897 3898 while (pool--) 3899 IXGBE_WRITE_REG(hw, 3900 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3901 *(adapter->rss_key + i)); 3902 } 3903 3904 /* Fill out the redirection table */ 3905 for (i = 0, j = 0; i < 64; i++, j++) { 3906 if (j == rss_i) 3907 j = 0; 3908 3909 adapter->rss_indir_tbl[i] = j; 3910 } 3911 3912 ixgbe_store_vfreta(adapter); 3913 } 3914 3915 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3916 { 3917 struct ixgbe_hw *hw = &adapter->hw; 3918 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3919 u32 rxcsum; 3920 3921 /* Disable indicating checksum in descriptor, enables RSS hash */ 3922 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3923 rxcsum |= IXGBE_RXCSUM_PCSD; 3924 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3925 3926 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3927 if (adapter->ring_feature[RING_F_RSS].mask) 3928 mrqc = IXGBE_MRQC_RSSEN; 3929 } else { 3930 u8 tcs = adapter->hw_tcs; 3931 3932 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3933 if (tcs > 4) 3934 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3935 else if (tcs > 1) 3936 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3937 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3938 IXGBE_82599_VMDQ_4Q_MASK) 3939 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3940 else 3941 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3942 3943 /* Enable L3/L4 for Tx Switched packets only for X550, 3944 * older devices do not support this feature 3945 */ 3946 if (hw->mac.type >= ixgbe_mac_X550) 3947 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3948 } else { 3949 if (tcs > 4) 3950 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3951 else if (tcs > 1) 3952 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3953 else 3954 mrqc = IXGBE_MRQC_RSSEN; 3955 } 3956 } 3957 3958 /* Perform hash on these packet types */ 3959 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3960 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3961 IXGBE_MRQC_RSS_FIELD_IPV6 | 3962 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3963 3964 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3965 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3966 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3967 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3968 3969 if ((hw->mac.type >= ixgbe_mac_X550) && 3970 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3971 u16 pool = adapter->num_rx_pools; 3972 3973 /* Enable VF RSS mode */ 3974 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3975 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3976 3977 /* Setup RSS through the VF registers */ 3978 ixgbe_setup_vfreta(adapter); 3979 vfmrqc = IXGBE_MRQC_RSSEN; 3980 vfmrqc |= rss_field; 3981 3982 while (pool--) 3983 IXGBE_WRITE_REG(hw, 3984 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3985 vfmrqc); 3986 } else { 3987 ixgbe_setup_reta(adapter); 3988 mrqc |= rss_field; 3989 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3990 } 3991 } 3992 3993 /** 3994 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3995 * @adapter: address of board private structure 3996 * @ring: structure containing ring specific data 3997 **/ 3998 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3999 struct ixgbe_ring *ring) 4000 { 4001 struct ixgbe_hw *hw = &adapter->hw; 4002 u32 rscctrl; 4003 u8 reg_idx = ring->reg_idx; 4004 4005 if (!ring_is_rsc_enabled(ring)) 4006 return; 4007 4008 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4009 rscctrl |= IXGBE_RSCCTL_RSCEN; 4010 /* 4011 * we must limit the number of descriptors so that the 4012 * total size of max desc * buf_len is not greater 4013 * than 65536 4014 */ 4015 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4016 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4017 } 4018 4019 #define IXGBE_MAX_RX_DESC_POLL 10 4020 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4021 struct ixgbe_ring *ring) 4022 { 4023 struct ixgbe_hw *hw = &adapter->hw; 4024 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4025 u32 rxdctl; 4026 u8 reg_idx = ring->reg_idx; 4027 4028 if (ixgbe_removed(hw->hw_addr)) 4029 return; 4030 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4031 if (hw->mac.type == ixgbe_mac_82598EB && 4032 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4033 return; 4034 4035 do { 4036 usleep_range(1000, 2000); 4037 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4038 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4039 4040 if (!wait_loop) { 4041 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4042 "the polling period\n", reg_idx); 4043 } 4044 } 4045 4046 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4047 struct ixgbe_ring *ring) 4048 { 4049 struct ixgbe_hw *hw = &adapter->hw; 4050 union ixgbe_adv_rx_desc *rx_desc; 4051 u64 rdba = ring->dma; 4052 u32 rxdctl; 4053 u8 reg_idx = ring->reg_idx; 4054 4055 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4056 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4057 if (ring->xsk_pool) { 4058 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4059 MEM_TYPE_XSK_BUFF_POOL, 4060 NULL)); 4061 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4062 } else { 4063 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4064 MEM_TYPE_PAGE_SHARED, NULL)); 4065 } 4066 4067 /* disable queue to avoid use of these values while updating state */ 4068 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4069 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4070 4071 /* write value back with RXDCTL.ENABLE bit cleared */ 4072 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4073 IXGBE_WRITE_FLUSH(hw); 4074 4075 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4076 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4077 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4078 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4079 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4080 IXGBE_WRITE_FLUSH(hw); 4081 4082 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4083 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4084 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4085 4086 ixgbe_configure_srrctl(adapter, ring); 4087 ixgbe_configure_rscctl(adapter, ring); 4088 4089 if (hw->mac.type == ixgbe_mac_82598EB) { 4090 /* 4091 * enable cache line friendly hardware writes: 4092 * PTHRESH=32 descriptors (half the internal cache), 4093 * this also removes ugly rx_no_buffer_count increment 4094 * HTHRESH=4 descriptors (to minimize latency on fetch) 4095 * WTHRESH=8 burst writeback up to two cache lines 4096 */ 4097 rxdctl &= ~0x3FFFFF; 4098 rxdctl |= 0x080420; 4099 #if (PAGE_SIZE < 8192) 4100 /* RXDCTL.RLPML does not work on 82599 */ 4101 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4102 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4103 IXGBE_RXDCTL_RLPML_EN); 4104 4105 /* Limit the maximum frame size so we don't overrun the skb. 4106 * This can happen in SRIOV mode when the MTU of the VF is 4107 * higher than the MTU of the PF. 4108 */ 4109 if (ring_uses_build_skb(ring) && 4110 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4111 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4112 IXGBE_RXDCTL_RLPML_EN; 4113 #endif 4114 } 4115 4116 ring->rx_offset = ixgbe_rx_offset(ring); 4117 4118 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4119 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4120 4121 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4122 IXGBE_RXDCTL_RLPML_EN); 4123 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4124 4125 ring->rx_buf_len = xsk_buf_len; 4126 } 4127 4128 /* initialize rx_buffer_info */ 4129 memset(ring->rx_buffer_info, 0, 4130 sizeof(struct ixgbe_rx_buffer) * ring->count); 4131 4132 /* initialize Rx descriptor 0 */ 4133 rx_desc = IXGBE_RX_DESC(ring, 0); 4134 rx_desc->wb.upper.length = 0; 4135 4136 /* enable receive descriptor ring */ 4137 rxdctl |= IXGBE_RXDCTL_ENABLE; 4138 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4139 4140 ixgbe_rx_desc_queue_enable(adapter, ring); 4141 if (ring->xsk_pool) 4142 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4143 else 4144 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4145 } 4146 4147 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4148 { 4149 struct ixgbe_hw *hw = &adapter->hw; 4150 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4151 u16 pool = adapter->num_rx_pools; 4152 4153 /* PSRTYPE must be initialized in non 82598 adapters */ 4154 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4155 IXGBE_PSRTYPE_UDPHDR | 4156 IXGBE_PSRTYPE_IPV4HDR | 4157 IXGBE_PSRTYPE_L2HDR | 4158 IXGBE_PSRTYPE_IPV6HDR; 4159 4160 if (hw->mac.type == ixgbe_mac_82598EB) 4161 return; 4162 4163 if (rss_i > 3) 4164 psrtype |= 2u << 29; 4165 else if (rss_i > 1) 4166 psrtype |= 1u << 29; 4167 4168 while (pool--) 4169 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4170 } 4171 4172 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4173 { 4174 struct ixgbe_hw *hw = &adapter->hw; 4175 u16 pool = adapter->num_rx_pools; 4176 u32 reg_offset, vf_shift, vmolr; 4177 u32 gcr_ext, vmdctl; 4178 int i; 4179 4180 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4181 return; 4182 4183 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4184 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4186 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4187 vmdctl |= IXGBE_VT_CTL_REPLEN; 4188 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4189 4190 /* accept untagged packets until a vlan tag is 4191 * specifically set for the VMDQ queue/pool 4192 */ 4193 vmolr = IXGBE_VMOLR_AUPE; 4194 while (pool--) 4195 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4196 4197 vf_shift = VMDQ_P(0) % 32; 4198 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4199 4200 /* Enable only the PF's pool for Tx/Rx */ 4201 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4202 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4203 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4204 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4205 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4206 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4207 4208 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4209 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4210 4211 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4212 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4213 4214 /* 4215 * Set up VF register offsets for selected VT Mode, 4216 * i.e. 32 or 64 VFs for SR-IOV 4217 */ 4218 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4219 case IXGBE_82599_VMDQ_8Q_MASK: 4220 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4221 break; 4222 case IXGBE_82599_VMDQ_4Q_MASK: 4223 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4224 break; 4225 default: 4226 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4227 break; 4228 } 4229 4230 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4231 4232 for (i = 0; i < adapter->num_vfs; i++) { 4233 /* configure spoof checking */ 4234 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4235 adapter->vfinfo[i].spoofchk_enabled); 4236 4237 /* Enable/Disable RSS query feature */ 4238 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4239 adapter->vfinfo[i].rss_query_enabled); 4240 } 4241 } 4242 4243 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4244 { 4245 struct ixgbe_hw *hw = &adapter->hw; 4246 struct net_device *netdev = adapter->netdev; 4247 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4248 struct ixgbe_ring *rx_ring; 4249 int i; 4250 u32 mhadd, hlreg0; 4251 4252 #ifdef IXGBE_FCOE 4253 /* adjust max frame to be able to do baby jumbo for FCoE */ 4254 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4255 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4256 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4257 4258 #endif /* IXGBE_FCOE */ 4259 4260 /* adjust max frame to be at least the size of a standard frame */ 4261 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4262 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4263 4264 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4265 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4266 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4267 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4268 4269 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4270 } 4271 4272 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4273 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4274 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4275 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4276 4277 /* 4278 * Setup the HW Rx Head and Tail Descriptor Pointers and 4279 * the Base and Length of the Rx Descriptor Ring 4280 */ 4281 for (i = 0; i < adapter->num_rx_queues; i++) { 4282 rx_ring = adapter->rx_ring[i]; 4283 4284 clear_ring_rsc_enabled(rx_ring); 4285 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4286 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4287 4288 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4289 set_ring_rsc_enabled(rx_ring); 4290 4291 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4292 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4293 4294 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4295 continue; 4296 4297 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4298 4299 #if (PAGE_SIZE < 8192) 4300 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4301 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4302 4303 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4304 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4305 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4306 #endif 4307 } 4308 } 4309 4310 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4311 { 4312 struct ixgbe_hw *hw = &adapter->hw; 4313 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4314 4315 switch (hw->mac.type) { 4316 case ixgbe_mac_82598EB: 4317 /* 4318 * For VMDq support of different descriptor types or 4319 * buffer sizes through the use of multiple SRRCTL 4320 * registers, RDRXCTL.MVMEN must be set to 1 4321 * 4322 * also, the manual doesn't mention it clearly but DCA hints 4323 * will only use queue 0's tags unless this bit is set. Side 4324 * effects of setting this bit are only that SRRCTL must be 4325 * fully programmed [0..15] 4326 */ 4327 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4328 break; 4329 case ixgbe_mac_X550: 4330 case ixgbe_mac_X550EM_x: 4331 case ixgbe_mac_x550em_a: 4332 if (adapter->num_vfs) 4333 rdrxctl |= IXGBE_RDRXCTL_PSP; 4334 fallthrough; 4335 case ixgbe_mac_82599EB: 4336 case ixgbe_mac_X540: 4337 /* Disable RSC for ACK packets */ 4338 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4339 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4340 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4341 /* hardware requires some bits to be set by default */ 4342 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4343 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4344 break; 4345 default: 4346 /* We should do nothing since we don't know this hardware */ 4347 return; 4348 } 4349 4350 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4351 } 4352 4353 /** 4354 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4355 * @adapter: board private structure 4356 * 4357 * Configure the Rx unit of the MAC after a reset. 4358 **/ 4359 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4360 { 4361 struct ixgbe_hw *hw = &adapter->hw; 4362 int i; 4363 u32 rxctrl, rfctl; 4364 4365 /* disable receives while setting up the descriptors */ 4366 hw->mac.ops.disable_rx(hw); 4367 4368 ixgbe_setup_psrtype(adapter); 4369 ixgbe_setup_rdrxctl(adapter); 4370 4371 /* RSC Setup */ 4372 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4373 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4374 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4375 rfctl |= IXGBE_RFCTL_RSC_DIS; 4376 4377 /* disable NFS filtering */ 4378 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4379 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4380 4381 /* Program registers for the distribution of queues */ 4382 ixgbe_setup_mrqc(adapter); 4383 4384 /* set_rx_buffer_len must be called before ring initialization */ 4385 ixgbe_set_rx_buffer_len(adapter); 4386 4387 /* 4388 * Setup the HW Rx Head and Tail Descriptor Pointers and 4389 * the Base and Length of the Rx Descriptor Ring 4390 */ 4391 for (i = 0; i < adapter->num_rx_queues; i++) 4392 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4393 4394 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4395 /* disable drop enable for 82598 parts */ 4396 if (hw->mac.type == ixgbe_mac_82598EB) 4397 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4398 4399 /* enable all receives */ 4400 rxctrl |= IXGBE_RXCTRL_RXEN; 4401 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4402 } 4403 4404 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4405 __be16 proto, u16 vid) 4406 { 4407 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4408 struct ixgbe_hw *hw = &adapter->hw; 4409 4410 /* add VID to filter table */ 4411 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4412 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4413 4414 set_bit(vid, adapter->active_vlans); 4415 4416 return 0; 4417 } 4418 4419 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4420 { 4421 u32 vlvf; 4422 int idx; 4423 4424 /* short cut the special case */ 4425 if (vlan == 0) 4426 return 0; 4427 4428 /* Search for the vlan id in the VLVF entries */ 4429 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4430 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4431 if ((vlvf & VLAN_VID_MASK) == vlan) 4432 break; 4433 } 4434 4435 return idx; 4436 } 4437 4438 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4439 { 4440 struct ixgbe_hw *hw = &adapter->hw; 4441 u32 bits, word; 4442 int idx; 4443 4444 idx = ixgbe_find_vlvf_entry(hw, vid); 4445 if (!idx) 4446 return; 4447 4448 /* See if any other pools are set for this VLAN filter 4449 * entry other than the PF. 4450 */ 4451 word = idx * 2 + (VMDQ_P(0) / 32); 4452 bits = ~BIT(VMDQ_P(0) % 32); 4453 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4454 4455 /* Disable the filter so this falls into the default pool. */ 4456 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4457 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4458 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4459 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4460 } 4461 } 4462 4463 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4464 __be16 proto, u16 vid) 4465 { 4466 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4467 struct ixgbe_hw *hw = &adapter->hw; 4468 4469 /* remove VID from filter table */ 4470 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4471 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4472 4473 clear_bit(vid, adapter->active_vlans); 4474 4475 return 0; 4476 } 4477 4478 /** 4479 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4480 * @adapter: driver data 4481 */ 4482 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4483 { 4484 struct ixgbe_hw *hw = &adapter->hw; 4485 u32 vlnctrl; 4486 int i, j; 4487 4488 switch (hw->mac.type) { 4489 case ixgbe_mac_82598EB: 4490 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4491 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4492 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4493 break; 4494 case ixgbe_mac_82599EB: 4495 case ixgbe_mac_X540: 4496 case ixgbe_mac_X550: 4497 case ixgbe_mac_X550EM_x: 4498 case ixgbe_mac_x550em_a: 4499 for (i = 0; i < adapter->num_rx_queues; i++) { 4500 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4501 4502 if (!netif_is_ixgbe(ring->netdev)) 4503 continue; 4504 4505 j = ring->reg_idx; 4506 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4507 vlnctrl &= ~IXGBE_RXDCTL_VME; 4508 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4509 } 4510 break; 4511 default: 4512 break; 4513 } 4514 } 4515 4516 /** 4517 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4518 * @adapter: driver data 4519 */ 4520 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4521 { 4522 struct ixgbe_hw *hw = &adapter->hw; 4523 u32 vlnctrl; 4524 int i, j; 4525 4526 switch (hw->mac.type) { 4527 case ixgbe_mac_82598EB: 4528 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4529 vlnctrl |= IXGBE_VLNCTRL_VME; 4530 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4531 break; 4532 case ixgbe_mac_82599EB: 4533 case ixgbe_mac_X540: 4534 case ixgbe_mac_X550: 4535 case ixgbe_mac_X550EM_x: 4536 case ixgbe_mac_x550em_a: 4537 for (i = 0; i < adapter->num_rx_queues; i++) { 4538 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4539 4540 if (!netif_is_ixgbe(ring->netdev)) 4541 continue; 4542 4543 j = ring->reg_idx; 4544 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4545 vlnctrl |= IXGBE_RXDCTL_VME; 4546 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4547 } 4548 break; 4549 default: 4550 break; 4551 } 4552 } 4553 4554 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4555 { 4556 struct ixgbe_hw *hw = &adapter->hw; 4557 u32 vlnctrl, i; 4558 4559 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4560 4561 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4562 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4563 vlnctrl |= IXGBE_VLNCTRL_VFE; 4564 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4565 } else { 4566 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4567 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4568 return; 4569 } 4570 4571 /* Nothing to do for 82598 */ 4572 if (hw->mac.type == ixgbe_mac_82598EB) 4573 return; 4574 4575 /* We are already in VLAN promisc, nothing to do */ 4576 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4577 return; 4578 4579 /* Set flag so we don't redo unnecessary work */ 4580 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4581 4582 /* Add PF to all active pools */ 4583 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4584 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4585 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4586 4587 vlvfb |= BIT(VMDQ_P(0) % 32); 4588 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4589 } 4590 4591 /* Set all bits in the VLAN filter table array */ 4592 for (i = hw->mac.vft_size; i--;) 4593 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4594 } 4595 4596 #define VFTA_BLOCK_SIZE 8 4597 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4598 { 4599 struct ixgbe_hw *hw = &adapter->hw; 4600 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4601 u32 vid_start = vfta_offset * 32; 4602 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4603 u32 i, vid, word, bits; 4604 4605 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4606 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4607 4608 /* pull VLAN ID from VLVF */ 4609 vid = vlvf & VLAN_VID_MASK; 4610 4611 /* only concern outselves with a certain range */ 4612 if (vid < vid_start || vid >= vid_end) 4613 continue; 4614 4615 if (vlvf) { 4616 /* record VLAN ID in VFTA */ 4617 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4618 4619 /* if PF is part of this then continue */ 4620 if (test_bit(vid, adapter->active_vlans)) 4621 continue; 4622 } 4623 4624 /* remove PF from the pool */ 4625 word = i * 2 + VMDQ_P(0) / 32; 4626 bits = ~BIT(VMDQ_P(0) % 32); 4627 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4628 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4629 } 4630 4631 /* extract values from active_vlans and write back to VFTA */ 4632 for (i = VFTA_BLOCK_SIZE; i--;) { 4633 vid = (vfta_offset + i) * 32; 4634 word = vid / BITS_PER_LONG; 4635 bits = vid % BITS_PER_LONG; 4636 4637 vfta[i] |= adapter->active_vlans[word] >> bits; 4638 4639 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4640 } 4641 } 4642 4643 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4644 { 4645 struct ixgbe_hw *hw = &adapter->hw; 4646 u32 vlnctrl, i; 4647 4648 /* Set VLAN filtering to enabled */ 4649 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4650 vlnctrl |= IXGBE_VLNCTRL_VFE; 4651 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4652 4653 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4654 hw->mac.type == ixgbe_mac_82598EB) 4655 return; 4656 4657 /* We are not in VLAN promisc, nothing to do */ 4658 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4659 return; 4660 4661 /* Set flag so we don't redo unnecessary work */ 4662 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4663 4664 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4665 ixgbe_scrub_vfta(adapter, i); 4666 } 4667 4668 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4669 { 4670 u16 vid = 1; 4671 4672 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4673 4674 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4675 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4676 } 4677 4678 /** 4679 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4680 * @netdev: network interface device structure 4681 * 4682 * Writes multicast address list to the MTA hash table. 4683 * Returns: -ENOMEM on failure 4684 * 0 on no addresses written 4685 * X on writing X addresses to MTA 4686 **/ 4687 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4688 { 4689 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4690 struct ixgbe_hw *hw = &adapter->hw; 4691 4692 if (!netif_running(netdev)) 4693 return 0; 4694 4695 if (hw->mac.ops.update_mc_addr_list) 4696 hw->mac.ops.update_mc_addr_list(hw, netdev); 4697 else 4698 return -ENOMEM; 4699 4700 #ifdef CONFIG_PCI_IOV 4701 ixgbe_restore_vf_multicasts(adapter); 4702 #endif 4703 4704 return netdev_mc_count(netdev); 4705 } 4706 4707 #ifdef CONFIG_PCI_IOV 4708 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4709 { 4710 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4711 struct ixgbe_hw *hw = &adapter->hw; 4712 int i; 4713 4714 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4715 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4716 4717 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4718 hw->mac.ops.set_rar(hw, i, 4719 mac_table->addr, 4720 mac_table->pool, 4721 IXGBE_RAH_AV); 4722 else 4723 hw->mac.ops.clear_rar(hw, i); 4724 } 4725 } 4726 4727 #endif 4728 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4729 { 4730 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4731 struct ixgbe_hw *hw = &adapter->hw; 4732 int i; 4733 4734 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4735 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4736 continue; 4737 4738 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4739 4740 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4741 hw->mac.ops.set_rar(hw, i, 4742 mac_table->addr, 4743 mac_table->pool, 4744 IXGBE_RAH_AV); 4745 else 4746 hw->mac.ops.clear_rar(hw, i); 4747 } 4748 } 4749 4750 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4751 { 4752 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4753 struct ixgbe_hw *hw = &adapter->hw; 4754 int i; 4755 4756 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4757 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4758 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4759 } 4760 4761 ixgbe_sync_mac_table(adapter); 4762 } 4763 4764 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4765 { 4766 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4767 struct ixgbe_hw *hw = &adapter->hw; 4768 int i, count = 0; 4769 4770 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4771 /* do not count default RAR as available */ 4772 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4773 continue; 4774 4775 /* only count unused and addresses that belong to us */ 4776 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4777 if (mac_table->pool != pool) 4778 continue; 4779 } 4780 4781 count++; 4782 } 4783 4784 return count; 4785 } 4786 4787 /* this function destroys the first RAR entry */ 4788 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4789 { 4790 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4791 struct ixgbe_hw *hw = &adapter->hw; 4792 4793 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4794 mac_table->pool = VMDQ_P(0); 4795 4796 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4797 4798 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4799 IXGBE_RAH_AV); 4800 } 4801 4802 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4803 const u8 *addr, u16 pool) 4804 { 4805 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4806 struct ixgbe_hw *hw = &adapter->hw; 4807 int i; 4808 4809 if (is_zero_ether_addr(addr)) 4810 return -EINVAL; 4811 4812 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4813 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4814 continue; 4815 4816 ether_addr_copy(mac_table->addr, addr); 4817 mac_table->pool = pool; 4818 4819 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4820 IXGBE_MAC_STATE_IN_USE; 4821 4822 ixgbe_sync_mac_table(adapter); 4823 4824 return i; 4825 } 4826 4827 return -ENOMEM; 4828 } 4829 4830 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4831 const u8 *addr, u16 pool) 4832 { 4833 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4834 struct ixgbe_hw *hw = &adapter->hw; 4835 int i; 4836 4837 if (is_zero_ether_addr(addr)) 4838 return -EINVAL; 4839 4840 /* search table for addr, if found clear IN_USE flag and sync */ 4841 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4842 /* we can only delete an entry if it is in use */ 4843 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4844 continue; 4845 /* we only care about entries that belong to the given pool */ 4846 if (mac_table->pool != pool) 4847 continue; 4848 /* we only care about a specific MAC address */ 4849 if (!ether_addr_equal(addr, mac_table->addr)) 4850 continue; 4851 4852 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4853 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4854 4855 ixgbe_sync_mac_table(adapter); 4856 4857 return 0; 4858 } 4859 4860 return -ENOMEM; 4861 } 4862 4863 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4864 { 4865 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4866 int ret; 4867 4868 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4869 4870 return min_t(int, ret, 0); 4871 } 4872 4873 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4874 { 4875 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4876 4877 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4878 4879 return 0; 4880 } 4881 4882 /** 4883 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4884 * @netdev: network interface device structure 4885 * 4886 * The set_rx_method entry point is called whenever the unicast/multicast 4887 * address list or the network interface flags are updated. This routine is 4888 * responsible for configuring the hardware for proper unicast, multicast and 4889 * promiscuous mode. 4890 **/ 4891 void ixgbe_set_rx_mode(struct net_device *netdev) 4892 { 4893 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4894 struct ixgbe_hw *hw = &adapter->hw; 4895 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4896 netdev_features_t features = netdev->features; 4897 int count; 4898 4899 /* Check for Promiscuous and All Multicast modes */ 4900 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4901 4902 /* set all bits that we expect to always be set */ 4903 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4904 fctrl |= IXGBE_FCTRL_BAM; 4905 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4906 fctrl |= IXGBE_FCTRL_PMCF; 4907 4908 /* clear the bits we are changing the status of */ 4909 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4910 if (netdev->flags & IFF_PROMISC) { 4911 hw->addr_ctrl.user_set_promisc = true; 4912 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4913 vmolr |= IXGBE_VMOLR_MPE; 4914 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4915 } else { 4916 if (netdev->flags & IFF_ALLMULTI) { 4917 fctrl |= IXGBE_FCTRL_MPE; 4918 vmolr |= IXGBE_VMOLR_MPE; 4919 } 4920 hw->addr_ctrl.user_set_promisc = false; 4921 } 4922 4923 /* 4924 * Write addresses to available RAR registers, if there is not 4925 * sufficient space to store all the addresses then enable 4926 * unicast promiscuous mode 4927 */ 4928 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4929 fctrl |= IXGBE_FCTRL_UPE; 4930 vmolr |= IXGBE_VMOLR_ROPE; 4931 } 4932 4933 /* Write addresses to the MTA, if the attempt fails 4934 * then we should just turn on promiscuous mode so 4935 * that we can at least receive multicast traffic 4936 */ 4937 count = ixgbe_write_mc_addr_list(netdev); 4938 if (count < 0) { 4939 fctrl |= IXGBE_FCTRL_MPE; 4940 vmolr |= IXGBE_VMOLR_MPE; 4941 } else if (count) { 4942 vmolr |= IXGBE_VMOLR_ROMPE; 4943 } 4944 4945 if (hw->mac.type != ixgbe_mac_82598EB) { 4946 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4947 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4948 IXGBE_VMOLR_ROPE); 4949 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4950 } 4951 4952 /* This is useful for sniffing bad packets. */ 4953 if (features & NETIF_F_RXALL) { 4954 /* UPE and MPE will be handled by normal PROMISC logic 4955 * in e1000e_set_rx_mode */ 4956 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4957 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4958 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4959 4960 fctrl &= ~(IXGBE_FCTRL_DPF); 4961 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4962 } 4963 4964 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4965 4966 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4967 ixgbe_vlan_strip_enable(adapter); 4968 else 4969 ixgbe_vlan_strip_disable(adapter); 4970 4971 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4972 ixgbe_vlan_promisc_disable(adapter); 4973 else 4974 ixgbe_vlan_promisc_enable(adapter); 4975 } 4976 4977 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4978 { 4979 int q_idx; 4980 4981 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4982 napi_enable(&adapter->q_vector[q_idx]->napi); 4983 } 4984 4985 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4986 { 4987 int q_idx; 4988 4989 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4990 napi_disable(&adapter->q_vector[q_idx]->napi); 4991 } 4992 4993 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 4994 { 4995 struct ixgbe_adapter *adapter = netdev_priv(dev); 4996 struct ixgbe_hw *hw = &adapter->hw; 4997 struct udp_tunnel_info ti; 4998 4999 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5000 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5001 adapter->vxlan_port = ti.port; 5002 else 5003 adapter->geneve_port = ti.port; 5004 5005 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5006 ntohs(adapter->vxlan_port) | 5007 ntohs(adapter->geneve_port) << 5008 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5009 return 0; 5010 } 5011 5012 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5013 .sync_table = ixgbe_udp_tunnel_sync, 5014 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5015 .tables = { 5016 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5017 }, 5018 }; 5019 5020 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5021 .sync_table = ixgbe_udp_tunnel_sync, 5022 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5023 .tables = { 5024 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5025 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5026 }, 5027 }; 5028 5029 #ifdef CONFIG_IXGBE_DCB 5030 /** 5031 * ixgbe_configure_dcb - Configure DCB hardware 5032 * @adapter: ixgbe adapter struct 5033 * 5034 * This is called by the driver on open to configure the DCB hardware. 5035 * This is also called by the gennetlink interface when reconfiguring 5036 * the DCB state. 5037 */ 5038 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5039 { 5040 struct ixgbe_hw *hw = &adapter->hw; 5041 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5042 5043 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5044 if (hw->mac.type == ixgbe_mac_82598EB) 5045 netif_set_tso_max_size(adapter->netdev, 65536); 5046 return; 5047 } 5048 5049 if (hw->mac.type == ixgbe_mac_82598EB) 5050 netif_set_tso_max_size(adapter->netdev, 32768); 5051 5052 #ifdef IXGBE_FCOE 5053 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5054 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5055 #endif 5056 5057 /* reconfigure the hardware */ 5058 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5059 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5060 DCB_TX_CONFIG); 5061 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5062 DCB_RX_CONFIG); 5063 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5064 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5065 ixgbe_dcb_hw_ets(&adapter->hw, 5066 adapter->ixgbe_ieee_ets, 5067 max_frame); 5068 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5069 adapter->ixgbe_ieee_pfc->pfc_en, 5070 adapter->ixgbe_ieee_ets->prio_tc); 5071 } 5072 5073 /* Enable RSS Hash per TC */ 5074 if (hw->mac.type != ixgbe_mac_82598EB) { 5075 u32 msb = 0; 5076 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5077 5078 while (rss_i) { 5079 msb++; 5080 rss_i >>= 1; 5081 } 5082 5083 /* write msb to all 8 TCs in one write */ 5084 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5085 } 5086 } 5087 #endif 5088 5089 /* Additional bittime to account for IXGBE framing */ 5090 #define IXGBE_ETH_FRAMING 20 5091 5092 /** 5093 * ixgbe_hpbthresh - calculate high water mark for flow control 5094 * 5095 * @adapter: board private structure to calculate for 5096 * @pb: packet buffer to calculate 5097 */ 5098 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5099 { 5100 struct ixgbe_hw *hw = &adapter->hw; 5101 struct net_device *dev = adapter->netdev; 5102 int link, tc, kb, marker; 5103 u32 dv_id, rx_pba; 5104 5105 /* Calculate max LAN frame size */ 5106 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5107 5108 #ifdef IXGBE_FCOE 5109 /* FCoE traffic class uses FCOE jumbo frames */ 5110 if ((dev->features & NETIF_F_FCOE_MTU) && 5111 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5112 (pb == ixgbe_fcoe_get_tc(adapter))) 5113 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5114 #endif 5115 5116 /* Calculate delay value for device */ 5117 switch (hw->mac.type) { 5118 case ixgbe_mac_X540: 5119 case ixgbe_mac_X550: 5120 case ixgbe_mac_X550EM_x: 5121 case ixgbe_mac_x550em_a: 5122 dv_id = IXGBE_DV_X540(link, tc); 5123 break; 5124 default: 5125 dv_id = IXGBE_DV(link, tc); 5126 break; 5127 } 5128 5129 /* Loopback switch introduces additional latency */ 5130 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5131 dv_id += IXGBE_B2BT(tc); 5132 5133 /* Delay value is calculated in bit times convert to KB */ 5134 kb = IXGBE_BT2KB(dv_id); 5135 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5136 5137 marker = rx_pba - kb; 5138 5139 /* It is possible that the packet buffer is not large enough 5140 * to provide required headroom. In this case throw an error 5141 * to user and a do the best we can. 5142 */ 5143 if (marker < 0) { 5144 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5145 "headroom to support flow control." 5146 "Decrease MTU or number of traffic classes\n", pb); 5147 marker = tc + 1; 5148 } 5149 5150 return marker; 5151 } 5152 5153 /** 5154 * ixgbe_lpbthresh - calculate low water mark for flow control 5155 * 5156 * @adapter: board private structure to calculate for 5157 * @pb: packet buffer to calculate 5158 */ 5159 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5160 { 5161 struct ixgbe_hw *hw = &adapter->hw; 5162 struct net_device *dev = adapter->netdev; 5163 int tc; 5164 u32 dv_id; 5165 5166 /* Calculate max LAN frame size */ 5167 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5168 5169 #ifdef IXGBE_FCOE 5170 /* FCoE traffic class uses FCOE jumbo frames */ 5171 if ((dev->features & NETIF_F_FCOE_MTU) && 5172 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5173 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5174 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5175 #endif 5176 5177 /* Calculate delay value for device */ 5178 switch (hw->mac.type) { 5179 case ixgbe_mac_X540: 5180 case ixgbe_mac_X550: 5181 case ixgbe_mac_X550EM_x: 5182 case ixgbe_mac_x550em_a: 5183 dv_id = IXGBE_LOW_DV_X540(tc); 5184 break; 5185 default: 5186 dv_id = IXGBE_LOW_DV(tc); 5187 break; 5188 } 5189 5190 /* Delay value is calculated in bit times convert to KB */ 5191 return IXGBE_BT2KB(dv_id); 5192 } 5193 5194 /* 5195 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5196 */ 5197 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5198 { 5199 struct ixgbe_hw *hw = &adapter->hw; 5200 int num_tc = adapter->hw_tcs; 5201 int i; 5202 5203 if (!num_tc) 5204 num_tc = 1; 5205 5206 for (i = 0; i < num_tc; i++) { 5207 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5208 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5209 5210 /* Low water marks must not be larger than high water marks */ 5211 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5212 hw->fc.low_water[i] = 0; 5213 } 5214 5215 for (; i < MAX_TRAFFIC_CLASS; i++) 5216 hw->fc.high_water[i] = 0; 5217 } 5218 5219 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5220 { 5221 struct ixgbe_hw *hw = &adapter->hw; 5222 int hdrm; 5223 u8 tc = adapter->hw_tcs; 5224 5225 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5226 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5227 hdrm = 32 << adapter->fdir_pballoc; 5228 else 5229 hdrm = 0; 5230 5231 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5232 ixgbe_pbthresh_setup(adapter); 5233 } 5234 5235 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5236 { 5237 struct ixgbe_hw *hw = &adapter->hw; 5238 struct hlist_node *node2; 5239 struct ixgbe_fdir_filter *filter; 5240 u8 queue; 5241 5242 spin_lock(&adapter->fdir_perfect_lock); 5243 5244 if (!hlist_empty(&adapter->fdir_filter_list)) 5245 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5246 5247 hlist_for_each_entry_safe(filter, node2, 5248 &adapter->fdir_filter_list, fdir_node) { 5249 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5250 queue = IXGBE_FDIR_DROP_QUEUE; 5251 } else { 5252 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5253 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5254 5255 if (!vf && (ring >= adapter->num_rx_queues)) { 5256 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5257 ring); 5258 continue; 5259 } else if (vf && 5260 ((vf > adapter->num_vfs) || 5261 ring >= adapter->num_rx_queues_per_pool)) { 5262 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5263 vf, ring); 5264 continue; 5265 } 5266 5267 /* Map the ring onto the absolute queue index */ 5268 if (!vf) 5269 queue = adapter->rx_ring[ring]->reg_idx; 5270 else 5271 queue = ((vf - 1) * 5272 adapter->num_rx_queues_per_pool) + ring; 5273 } 5274 5275 ixgbe_fdir_write_perfect_filter_82599(hw, 5276 &filter->filter, filter->sw_idx, queue); 5277 } 5278 5279 spin_unlock(&adapter->fdir_perfect_lock); 5280 } 5281 5282 /** 5283 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5284 * @rx_ring: ring to free buffers from 5285 **/ 5286 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5287 { 5288 u16 i = rx_ring->next_to_clean; 5289 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5290 5291 if (rx_ring->xsk_pool) { 5292 ixgbe_xsk_clean_rx_ring(rx_ring); 5293 goto skip_free; 5294 } 5295 5296 /* Free all the Rx ring sk_buffs */ 5297 while (i != rx_ring->next_to_alloc) { 5298 if (rx_buffer->skb) { 5299 struct sk_buff *skb = rx_buffer->skb; 5300 if (IXGBE_CB(skb)->page_released) 5301 dma_unmap_page_attrs(rx_ring->dev, 5302 IXGBE_CB(skb)->dma, 5303 ixgbe_rx_pg_size(rx_ring), 5304 DMA_FROM_DEVICE, 5305 IXGBE_RX_DMA_ATTR); 5306 dev_kfree_skb(skb); 5307 } 5308 5309 /* Invalidate cache lines that may have been written to by 5310 * device so that we avoid corrupting memory. 5311 */ 5312 dma_sync_single_range_for_cpu(rx_ring->dev, 5313 rx_buffer->dma, 5314 rx_buffer->page_offset, 5315 ixgbe_rx_bufsz(rx_ring), 5316 DMA_FROM_DEVICE); 5317 5318 /* free resources associated with mapping */ 5319 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5320 ixgbe_rx_pg_size(rx_ring), 5321 DMA_FROM_DEVICE, 5322 IXGBE_RX_DMA_ATTR); 5323 __page_frag_cache_drain(rx_buffer->page, 5324 rx_buffer->pagecnt_bias); 5325 5326 i++; 5327 rx_buffer++; 5328 if (i == rx_ring->count) { 5329 i = 0; 5330 rx_buffer = rx_ring->rx_buffer_info; 5331 } 5332 } 5333 5334 skip_free: 5335 rx_ring->next_to_alloc = 0; 5336 rx_ring->next_to_clean = 0; 5337 rx_ring->next_to_use = 0; 5338 } 5339 5340 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5341 struct ixgbe_fwd_adapter *accel) 5342 { 5343 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5344 int num_tc = netdev_get_num_tc(adapter->netdev); 5345 struct net_device *vdev = accel->netdev; 5346 int i, baseq, err; 5347 5348 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5349 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5350 accel->pool, adapter->num_rx_pools, 5351 baseq, baseq + adapter->num_rx_queues_per_pool); 5352 5353 accel->rx_base_queue = baseq; 5354 accel->tx_base_queue = baseq; 5355 5356 /* record configuration for macvlan interface in vdev */ 5357 for (i = 0; i < num_tc; i++) 5358 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5359 i, rss_i, baseq + (rss_i * i)); 5360 5361 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5362 adapter->rx_ring[baseq + i]->netdev = vdev; 5363 5364 /* Guarantee all rings are updated before we update the 5365 * MAC address filter. 5366 */ 5367 wmb(); 5368 5369 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5370 * need to only treat it as an error value if it is negative. 5371 */ 5372 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5373 VMDQ_P(accel->pool)); 5374 if (err >= 0) 5375 return 0; 5376 5377 /* if we cannot add the MAC rule then disable the offload */ 5378 macvlan_release_l2fw_offload(vdev); 5379 5380 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5381 adapter->rx_ring[baseq + i]->netdev = NULL; 5382 5383 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5384 5385 /* unbind the queues and drop the subordinate channel config */ 5386 netdev_unbind_sb_channel(adapter->netdev, vdev); 5387 netdev_set_sb_channel(vdev, 0); 5388 5389 clear_bit(accel->pool, adapter->fwd_bitmask); 5390 kfree(accel); 5391 5392 return err; 5393 } 5394 5395 static int ixgbe_macvlan_up(struct net_device *vdev, 5396 struct netdev_nested_priv *priv) 5397 { 5398 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5399 struct ixgbe_fwd_adapter *accel; 5400 5401 if (!netif_is_macvlan(vdev)) 5402 return 0; 5403 5404 accel = macvlan_accel_priv(vdev); 5405 if (!accel) 5406 return 0; 5407 5408 ixgbe_fwd_ring_up(adapter, accel); 5409 5410 return 0; 5411 } 5412 5413 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5414 { 5415 struct netdev_nested_priv priv = { 5416 .data = (void *)adapter, 5417 }; 5418 5419 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5420 ixgbe_macvlan_up, &priv); 5421 } 5422 5423 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5424 { 5425 struct ixgbe_hw *hw = &adapter->hw; 5426 5427 ixgbe_configure_pb(adapter); 5428 #ifdef CONFIG_IXGBE_DCB 5429 ixgbe_configure_dcb(adapter); 5430 #endif 5431 /* 5432 * We must restore virtualization before VLANs or else 5433 * the VLVF registers will not be populated 5434 */ 5435 ixgbe_configure_virtualization(adapter); 5436 5437 ixgbe_set_rx_mode(adapter->netdev); 5438 ixgbe_restore_vlan(adapter); 5439 ixgbe_ipsec_restore(adapter); 5440 5441 switch (hw->mac.type) { 5442 case ixgbe_mac_82599EB: 5443 case ixgbe_mac_X540: 5444 hw->mac.ops.disable_rx_buff(hw); 5445 break; 5446 default: 5447 break; 5448 } 5449 5450 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5451 ixgbe_init_fdir_signature_82599(&adapter->hw, 5452 adapter->fdir_pballoc); 5453 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5454 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5455 adapter->fdir_pballoc); 5456 ixgbe_fdir_filter_restore(adapter); 5457 } 5458 5459 switch (hw->mac.type) { 5460 case ixgbe_mac_82599EB: 5461 case ixgbe_mac_X540: 5462 hw->mac.ops.enable_rx_buff(hw); 5463 break; 5464 default: 5465 break; 5466 } 5467 5468 #ifdef CONFIG_IXGBE_DCA 5469 /* configure DCA */ 5470 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5471 ixgbe_setup_dca(adapter); 5472 #endif /* CONFIG_IXGBE_DCA */ 5473 5474 #ifdef IXGBE_FCOE 5475 /* configure FCoE L2 filters, redirection table, and Rx control */ 5476 ixgbe_configure_fcoe(adapter); 5477 5478 #endif /* IXGBE_FCOE */ 5479 ixgbe_configure_tx(adapter); 5480 ixgbe_configure_rx(adapter); 5481 ixgbe_configure_dfwd(adapter); 5482 } 5483 5484 /** 5485 * ixgbe_sfp_link_config - set up SFP+ link 5486 * @adapter: pointer to private adapter struct 5487 **/ 5488 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5489 { 5490 /* 5491 * We are assuming the worst case scenario here, and that 5492 * is that an SFP was inserted/removed after the reset 5493 * but before SFP detection was enabled. As such the best 5494 * solution is to just start searching as soon as we start 5495 */ 5496 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5497 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5498 5499 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5500 adapter->sfp_poll_time = 0; 5501 } 5502 5503 /** 5504 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5505 * @hw: pointer to private hardware struct 5506 * 5507 * Returns 0 on success, negative on failure 5508 **/ 5509 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5510 { 5511 u32 speed; 5512 bool autoneg, link_up = false; 5513 int ret = -EIO; 5514 5515 if (hw->mac.ops.check_link) 5516 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5517 5518 if (ret) 5519 return ret; 5520 5521 speed = hw->phy.autoneg_advertised; 5522 if (!speed && hw->mac.ops.get_link_capabilities) { 5523 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5524 &autoneg); 5525 /* remove NBASE-T speeds from default autonegotiation 5526 * to accommodate broken network switches in the field 5527 * which cannot cope with advertised NBASE-T speeds 5528 */ 5529 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 5530 IXGBE_LINK_SPEED_2_5GB_FULL); 5531 } 5532 5533 if (ret) 5534 return ret; 5535 5536 if (hw->mac.ops.setup_link) 5537 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5538 5539 return ret; 5540 } 5541 5542 /** 5543 * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset 5544 * @adapter: board private structure 5545 * 5546 * On a reset we need to clear out the VF stats or accounting gets 5547 * messed up because they're not clear on read. 5548 **/ 5549 static void ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter) 5550 { 5551 struct ixgbe_hw *hw = &adapter->hw; 5552 int i; 5553 5554 for (i = 0; i < adapter->num_vfs; i++) { 5555 adapter->vfinfo[i].last_vfstats.gprc = 5556 IXGBE_READ_REG(hw, IXGBE_PVFGPRC(i)); 5557 adapter->vfinfo[i].saved_rst_vfstats.gprc += 5558 adapter->vfinfo[i].vfstats.gprc; 5559 adapter->vfinfo[i].vfstats.gprc = 0; 5560 adapter->vfinfo[i].last_vfstats.gptc = 5561 IXGBE_READ_REG(hw, IXGBE_PVFGPTC(i)); 5562 adapter->vfinfo[i].saved_rst_vfstats.gptc += 5563 adapter->vfinfo[i].vfstats.gptc; 5564 adapter->vfinfo[i].vfstats.gptc = 0; 5565 adapter->vfinfo[i].last_vfstats.gorc = 5566 IXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i)); 5567 adapter->vfinfo[i].saved_rst_vfstats.gorc += 5568 adapter->vfinfo[i].vfstats.gorc; 5569 adapter->vfinfo[i].vfstats.gorc = 0; 5570 adapter->vfinfo[i].last_vfstats.gotc = 5571 IXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i)); 5572 adapter->vfinfo[i].saved_rst_vfstats.gotc += 5573 adapter->vfinfo[i].vfstats.gotc; 5574 adapter->vfinfo[i].vfstats.gotc = 0; 5575 adapter->vfinfo[i].last_vfstats.mprc = 5576 IXGBE_READ_REG(hw, IXGBE_PVFMPRC(i)); 5577 adapter->vfinfo[i].saved_rst_vfstats.mprc += 5578 adapter->vfinfo[i].vfstats.mprc; 5579 adapter->vfinfo[i].vfstats.mprc = 0; 5580 } 5581 } 5582 5583 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5584 { 5585 struct ixgbe_hw *hw = &adapter->hw; 5586 u32 gpie = 0; 5587 5588 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5589 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5590 IXGBE_GPIE_OCD; 5591 gpie |= IXGBE_GPIE_EIAME; 5592 /* 5593 * use EIAM to auto-mask when MSI-X interrupt is asserted 5594 * this saves a register write for every interrupt 5595 */ 5596 switch (hw->mac.type) { 5597 case ixgbe_mac_82598EB: 5598 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5599 break; 5600 case ixgbe_mac_82599EB: 5601 case ixgbe_mac_X540: 5602 case ixgbe_mac_X550: 5603 case ixgbe_mac_X550EM_x: 5604 case ixgbe_mac_x550em_a: 5605 default: 5606 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5607 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5608 break; 5609 } 5610 } else { 5611 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5612 * specifically only auto mask tx and rx interrupts */ 5613 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5614 } 5615 5616 /* XXX: to interrupt immediately for EICS writes, enable this */ 5617 /* gpie |= IXGBE_GPIE_EIMEN; */ 5618 5619 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5620 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5621 5622 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5623 case IXGBE_82599_VMDQ_8Q_MASK: 5624 gpie |= IXGBE_GPIE_VTMODE_16; 5625 break; 5626 case IXGBE_82599_VMDQ_4Q_MASK: 5627 gpie |= IXGBE_GPIE_VTMODE_32; 5628 break; 5629 default: 5630 gpie |= IXGBE_GPIE_VTMODE_64; 5631 break; 5632 } 5633 } 5634 5635 /* Enable Thermal over heat sensor interrupt */ 5636 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5637 switch (adapter->hw.mac.type) { 5638 case ixgbe_mac_82599EB: 5639 gpie |= IXGBE_SDP0_GPIEN_8259X; 5640 break; 5641 default: 5642 break; 5643 } 5644 } 5645 5646 /* Enable fan failure interrupt */ 5647 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5648 gpie |= IXGBE_SDP1_GPIEN(hw); 5649 5650 switch (hw->mac.type) { 5651 case ixgbe_mac_82599EB: 5652 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5653 break; 5654 case ixgbe_mac_X550EM_x: 5655 case ixgbe_mac_x550em_a: 5656 gpie |= IXGBE_SDP0_GPIEN_X540; 5657 break; 5658 default: 5659 break; 5660 } 5661 5662 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5663 } 5664 5665 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5666 { 5667 struct ixgbe_hw *hw = &adapter->hw; 5668 int err; 5669 u32 ctrl_ext; 5670 5671 ixgbe_get_hw_control(adapter); 5672 ixgbe_setup_gpie(adapter); 5673 5674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5675 ixgbe_configure_msix(adapter); 5676 else 5677 ixgbe_configure_msi_and_legacy(adapter); 5678 5679 /* enable the optics for 82599 SFP+ fiber */ 5680 if (hw->mac.ops.enable_tx_laser) 5681 hw->mac.ops.enable_tx_laser(hw); 5682 5683 if (hw->phy.ops.set_phy_power) 5684 hw->phy.ops.set_phy_power(hw, true); 5685 5686 smp_mb__before_atomic(); 5687 clear_bit(__IXGBE_DOWN, &adapter->state); 5688 ixgbe_napi_enable_all(adapter); 5689 5690 if (ixgbe_is_sfp(hw)) { 5691 ixgbe_sfp_link_config(adapter); 5692 } else { 5693 err = ixgbe_non_sfp_link_config(hw); 5694 if (err) 5695 e_err(probe, "link_config FAILED %d\n", err); 5696 } 5697 5698 /* clear any pending interrupts, may auto mask */ 5699 IXGBE_READ_REG(hw, IXGBE_EICR); 5700 ixgbe_irq_enable(adapter, true, true); 5701 5702 /* 5703 * If this adapter has a fan, check to see if we had a failure 5704 * before we enabled the interrupt. 5705 */ 5706 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5707 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5708 if (esdp & IXGBE_ESDP_SDP1) 5709 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5710 } 5711 5712 /* bring the link up in the watchdog, this could race with our first 5713 * link up interrupt but shouldn't be a problem */ 5714 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5715 adapter->link_check_timeout = jiffies; 5716 mod_timer(&adapter->service_timer, jiffies); 5717 5718 ixgbe_clear_vf_stats_counters(adapter); 5719 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5720 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5721 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5722 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5723 5724 /* update setting rx tx for all active vfs */ 5725 ixgbe_set_all_vfs(adapter); 5726 } 5727 5728 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5729 { 5730 /* put off any impending NetWatchDogTimeout */ 5731 netif_trans_update(adapter->netdev); 5732 5733 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5734 usleep_range(1000, 2000); 5735 if (adapter->hw.phy.type == ixgbe_phy_fw) 5736 ixgbe_watchdog_link_is_down(adapter); 5737 ixgbe_down(adapter); 5738 /* 5739 * If SR-IOV enabled then wait a bit before bringing the adapter 5740 * back up to give the VFs time to respond to the reset. The 5741 * two second wait is based upon the watchdog timer cycle in 5742 * the VF driver. 5743 */ 5744 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5745 msleep(2000); 5746 ixgbe_up(adapter); 5747 clear_bit(__IXGBE_RESETTING, &adapter->state); 5748 } 5749 5750 void ixgbe_up(struct ixgbe_adapter *adapter) 5751 { 5752 /* hardware has been reset, we need to reload some things */ 5753 ixgbe_configure(adapter); 5754 5755 ixgbe_up_complete(adapter); 5756 } 5757 5758 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5759 { 5760 u16 devctl2; 5761 5762 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5763 5764 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5765 case IXGBE_PCIDEVCTRL2_17_34s: 5766 case IXGBE_PCIDEVCTRL2_4_8s: 5767 /* For now we cap the upper limit on delay to 2 seconds 5768 * as we end up going up to 34 seconds of delay in worst 5769 * case timeout value. 5770 */ 5771 case IXGBE_PCIDEVCTRL2_1_2s: 5772 return 2000000ul; /* 2.0 s */ 5773 case IXGBE_PCIDEVCTRL2_260_520ms: 5774 return 520000ul; /* 520 ms */ 5775 case IXGBE_PCIDEVCTRL2_65_130ms: 5776 return 130000ul; /* 130 ms */ 5777 case IXGBE_PCIDEVCTRL2_16_32ms: 5778 return 32000ul; /* 32 ms */ 5779 case IXGBE_PCIDEVCTRL2_1_2ms: 5780 return 2000ul; /* 2 ms */ 5781 case IXGBE_PCIDEVCTRL2_50_100us: 5782 return 100ul; /* 100 us */ 5783 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5784 return 32000ul; /* 32 ms */ 5785 default: 5786 break; 5787 } 5788 5789 /* We shouldn't need to hit this path, but just in case default as 5790 * though completion timeout is not supported and support 32ms. 5791 */ 5792 return 32000ul; 5793 } 5794 5795 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5796 { 5797 unsigned long wait_delay, delay_interval; 5798 struct ixgbe_hw *hw = &adapter->hw; 5799 int i, wait_loop; 5800 u32 rxdctl; 5801 5802 /* disable receives */ 5803 hw->mac.ops.disable_rx(hw); 5804 5805 if (ixgbe_removed(hw->hw_addr)) 5806 return; 5807 5808 /* disable all enabled Rx queues */ 5809 for (i = 0; i < adapter->num_rx_queues; i++) { 5810 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5811 u8 reg_idx = ring->reg_idx; 5812 5813 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5814 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5815 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5816 5817 /* write value back with RXDCTL.ENABLE bit cleared */ 5818 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5819 } 5820 5821 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5822 if (hw->mac.type == ixgbe_mac_82598EB && 5823 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5824 return; 5825 5826 /* Determine our minimum delay interval. We will increase this value 5827 * with each subsequent test. This way if the device returns quickly 5828 * we should spend as little time as possible waiting, however as 5829 * the time increases we will wait for larger periods of time. 5830 * 5831 * The trick here is that we increase the interval using the 5832 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5833 * of that wait is that it totals up to 100x whatever interval we 5834 * choose. Since our minimum wait is 100us we can just divide the 5835 * total timeout by 100 to get our minimum delay interval. 5836 */ 5837 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5838 5839 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5840 wait_delay = delay_interval; 5841 5842 while (wait_loop--) { 5843 usleep_range(wait_delay, wait_delay + 10); 5844 wait_delay += delay_interval * 2; 5845 rxdctl = 0; 5846 5847 /* OR together the reading of all the active RXDCTL registers, 5848 * and then test the result. We need the disable to complete 5849 * before we start freeing the memory and invalidating the 5850 * DMA mappings. 5851 */ 5852 for (i = 0; i < adapter->num_rx_queues; i++) { 5853 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5854 u8 reg_idx = ring->reg_idx; 5855 5856 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5857 } 5858 5859 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5860 return; 5861 } 5862 5863 e_err(drv, 5864 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5865 } 5866 5867 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5868 { 5869 unsigned long wait_delay, delay_interval; 5870 struct ixgbe_hw *hw = &adapter->hw; 5871 int i, wait_loop; 5872 u32 txdctl; 5873 5874 if (ixgbe_removed(hw->hw_addr)) 5875 return; 5876 5877 /* disable all enabled Tx queues */ 5878 for (i = 0; i < adapter->num_tx_queues; i++) { 5879 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5880 u8 reg_idx = ring->reg_idx; 5881 5882 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5883 } 5884 5885 /* disable all enabled XDP Tx queues */ 5886 for (i = 0; i < adapter->num_xdp_queues; i++) { 5887 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5888 u8 reg_idx = ring->reg_idx; 5889 5890 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5891 } 5892 5893 /* If the link is not up there shouldn't be much in the way of 5894 * pending transactions. Those that are left will be flushed out 5895 * when the reset logic goes through the flush sequence to clean out 5896 * the pending Tx transactions. 5897 */ 5898 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5899 goto dma_engine_disable; 5900 5901 /* Determine our minimum delay interval. We will increase this value 5902 * with each subsequent test. This way if the device returns quickly 5903 * we should spend as little time as possible waiting, however as 5904 * the time increases we will wait for larger periods of time. 5905 * 5906 * The trick here is that we increase the interval using the 5907 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5908 * of that wait is that it totals up to 100x whatever interval we 5909 * choose. Since our minimum wait is 100us we can just divide the 5910 * total timeout by 100 to get our minimum delay interval. 5911 */ 5912 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5913 5914 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5915 wait_delay = delay_interval; 5916 5917 while (wait_loop--) { 5918 usleep_range(wait_delay, wait_delay + 10); 5919 wait_delay += delay_interval * 2; 5920 txdctl = 0; 5921 5922 /* OR together the reading of all the active TXDCTL registers, 5923 * and then test the result. We need the disable to complete 5924 * before we start freeing the memory and invalidating the 5925 * DMA mappings. 5926 */ 5927 for (i = 0; i < adapter->num_tx_queues; i++) { 5928 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5929 u8 reg_idx = ring->reg_idx; 5930 5931 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5932 } 5933 for (i = 0; i < adapter->num_xdp_queues; i++) { 5934 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5935 u8 reg_idx = ring->reg_idx; 5936 5937 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5938 } 5939 5940 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5941 goto dma_engine_disable; 5942 } 5943 5944 e_err(drv, 5945 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5946 5947 dma_engine_disable: 5948 /* Disable the Tx DMA engine on 82599 and later MAC */ 5949 switch (hw->mac.type) { 5950 case ixgbe_mac_82599EB: 5951 case ixgbe_mac_X540: 5952 case ixgbe_mac_X550: 5953 case ixgbe_mac_X550EM_x: 5954 case ixgbe_mac_x550em_a: 5955 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5956 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5957 ~IXGBE_DMATXCTL_TE)); 5958 fallthrough; 5959 default: 5960 break; 5961 } 5962 } 5963 5964 void ixgbe_reset(struct ixgbe_adapter *adapter) 5965 { 5966 struct ixgbe_hw *hw = &adapter->hw; 5967 struct net_device *netdev = adapter->netdev; 5968 int err; 5969 5970 if (ixgbe_removed(hw->hw_addr)) 5971 return; 5972 /* lock SFP init bit to prevent race conditions with the watchdog */ 5973 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5974 usleep_range(1000, 2000); 5975 5976 /* clear all SFP and link config related flags while holding SFP_INIT */ 5977 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5978 IXGBE_FLAG2_SFP_NEEDS_RESET); 5979 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5980 5981 err = hw->mac.ops.init_hw(hw); 5982 switch (err) { 5983 case 0: 5984 case -ENOENT: 5985 case -EOPNOTSUPP: 5986 break; 5987 case -EALREADY: 5988 e_dev_err("primary disable timed out\n"); 5989 break; 5990 case -EACCES: 5991 /* We are running on a pre-production device, log a warning */ 5992 e_dev_warn("This device is a pre-production adapter/LOM. " 5993 "Please be aware there may be issues associated with " 5994 "your hardware. If you are experiencing problems " 5995 "please contact your Intel or hardware " 5996 "representative who provided you with this " 5997 "hardware.\n"); 5998 break; 5999 default: 6000 e_dev_err("Hardware Error: %d\n", err); 6001 } 6002 6003 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6004 6005 /* flush entries out of MAC table */ 6006 ixgbe_flush_sw_mac_table(adapter); 6007 __dev_uc_unsync(netdev, NULL); 6008 6009 /* do not flush user set addresses */ 6010 ixgbe_mac_set_default_filter(adapter); 6011 6012 /* update SAN MAC vmdq pool selection */ 6013 if (hw->mac.san_mac_rar_index) 6014 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 6015 6016 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6017 ixgbe_ptp_reset(adapter); 6018 6019 if (hw->phy.ops.set_phy_power) { 6020 if (!netif_running(adapter->netdev) && !adapter->wol) 6021 hw->phy.ops.set_phy_power(hw, false); 6022 else 6023 hw->phy.ops.set_phy_power(hw, true); 6024 } 6025 } 6026 6027 /** 6028 * ixgbe_clean_tx_ring - Free Tx Buffers 6029 * @tx_ring: ring to be cleaned 6030 **/ 6031 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 6032 { 6033 u16 i = tx_ring->next_to_clean; 6034 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 6035 6036 if (tx_ring->xsk_pool) { 6037 ixgbe_xsk_clean_tx_ring(tx_ring); 6038 goto out; 6039 } 6040 6041 while (i != tx_ring->next_to_use) { 6042 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 6043 6044 /* Free all the Tx ring sk_buffs */ 6045 if (ring_is_xdp(tx_ring)) 6046 xdp_return_frame(tx_buffer->xdpf); 6047 else 6048 dev_kfree_skb_any(tx_buffer->skb); 6049 6050 /* unmap skb header data */ 6051 dma_unmap_single(tx_ring->dev, 6052 dma_unmap_addr(tx_buffer, dma), 6053 dma_unmap_len(tx_buffer, len), 6054 DMA_TO_DEVICE); 6055 6056 /* check for eop_desc to determine the end of the packet */ 6057 eop_desc = tx_buffer->next_to_watch; 6058 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6059 6060 /* unmap remaining buffers */ 6061 while (tx_desc != eop_desc) { 6062 tx_buffer++; 6063 tx_desc++; 6064 i++; 6065 if (unlikely(i == tx_ring->count)) { 6066 i = 0; 6067 tx_buffer = tx_ring->tx_buffer_info; 6068 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6069 } 6070 6071 /* unmap any remaining paged data */ 6072 if (dma_unmap_len(tx_buffer, len)) 6073 dma_unmap_page(tx_ring->dev, 6074 dma_unmap_addr(tx_buffer, dma), 6075 dma_unmap_len(tx_buffer, len), 6076 DMA_TO_DEVICE); 6077 } 6078 6079 /* move us one more past the eop_desc for start of next pkt */ 6080 tx_buffer++; 6081 i++; 6082 if (unlikely(i == tx_ring->count)) { 6083 i = 0; 6084 tx_buffer = tx_ring->tx_buffer_info; 6085 } 6086 } 6087 6088 /* reset BQL for queue */ 6089 if (!ring_is_xdp(tx_ring)) 6090 netdev_tx_reset_queue(txring_txq(tx_ring)); 6091 6092 out: 6093 /* reset next_to_use and next_to_clean */ 6094 tx_ring->next_to_use = 0; 6095 tx_ring->next_to_clean = 0; 6096 } 6097 6098 /** 6099 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6100 * @adapter: board private structure 6101 **/ 6102 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6103 { 6104 int i; 6105 6106 for (i = 0; i < adapter->num_rx_queues; i++) 6107 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6108 } 6109 6110 /** 6111 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6112 * @adapter: board private structure 6113 **/ 6114 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6115 { 6116 int i; 6117 6118 for (i = 0; i < adapter->num_tx_queues; i++) 6119 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6120 for (i = 0; i < adapter->num_xdp_queues; i++) 6121 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6122 } 6123 6124 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6125 { 6126 struct hlist_node *node2; 6127 struct ixgbe_fdir_filter *filter; 6128 6129 spin_lock(&adapter->fdir_perfect_lock); 6130 6131 hlist_for_each_entry_safe(filter, node2, 6132 &adapter->fdir_filter_list, fdir_node) { 6133 hlist_del(&filter->fdir_node); 6134 kfree(filter); 6135 } 6136 adapter->fdir_filter_count = 0; 6137 6138 spin_unlock(&adapter->fdir_perfect_lock); 6139 } 6140 6141 void ixgbe_down(struct ixgbe_adapter *adapter) 6142 { 6143 struct net_device *netdev = adapter->netdev; 6144 struct ixgbe_hw *hw = &adapter->hw; 6145 int i; 6146 6147 /* signal that we are down to the interrupt handler */ 6148 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6149 return; /* do nothing if already down */ 6150 6151 /* Shut off incoming Tx traffic */ 6152 netif_tx_stop_all_queues(netdev); 6153 6154 /* call carrier off first to avoid false dev_watchdog timeouts */ 6155 netif_carrier_off(netdev); 6156 netif_tx_disable(netdev); 6157 6158 /* Disable Rx */ 6159 ixgbe_disable_rx(adapter); 6160 6161 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6162 if (adapter->xdp_ring[0]) 6163 synchronize_rcu(); 6164 6165 ixgbe_irq_disable(adapter); 6166 6167 ixgbe_napi_disable_all(adapter); 6168 6169 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6170 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6171 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6172 6173 del_timer_sync(&adapter->service_timer); 6174 6175 if (adapter->num_vfs) { 6176 /* Clear EITR Select mapping */ 6177 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6178 6179 /* Mark all the VFs as inactive */ 6180 for (i = 0 ; i < adapter->num_vfs; i++) 6181 adapter->vfinfo[i].clear_to_send = false; 6182 6183 /* update setting rx tx for all active vfs */ 6184 ixgbe_set_all_vfs(adapter); 6185 } 6186 6187 /* disable transmits in the hardware now that interrupts are off */ 6188 ixgbe_disable_tx(adapter); 6189 6190 if (!pci_channel_offline(adapter->pdev)) 6191 ixgbe_reset(adapter); 6192 6193 /* power down the optics for 82599 SFP+ fiber */ 6194 if (hw->mac.ops.disable_tx_laser) 6195 hw->mac.ops.disable_tx_laser(hw); 6196 6197 ixgbe_clean_all_tx_rings(adapter); 6198 ixgbe_clean_all_rx_rings(adapter); 6199 } 6200 6201 /** 6202 * ixgbe_set_eee_capable - helper function to determine EEE support on X550 6203 * @adapter: board private structure 6204 */ 6205 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6206 { 6207 struct ixgbe_hw *hw = &adapter->hw; 6208 6209 switch (hw->device_id) { 6210 case IXGBE_DEV_ID_X550EM_A_1G_T: 6211 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6212 if (!hw->phy.eee_speeds_supported) 6213 break; 6214 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6215 if (!hw->phy.eee_speeds_advertised) 6216 break; 6217 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6218 break; 6219 default: 6220 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6221 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6222 break; 6223 } 6224 } 6225 6226 /** 6227 * ixgbe_tx_timeout - Respond to a Tx Hang 6228 * @netdev: network interface device structure 6229 * @txqueue: queue number that timed out 6230 **/ 6231 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6232 { 6233 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6234 6235 /* Do the reset outside of interrupt context */ 6236 ixgbe_tx_timeout_reset(adapter); 6237 } 6238 6239 #ifdef CONFIG_IXGBE_DCB 6240 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6241 { 6242 struct ixgbe_hw *hw = &adapter->hw; 6243 struct tc_configuration *tc; 6244 int j; 6245 6246 switch (hw->mac.type) { 6247 case ixgbe_mac_82598EB: 6248 case ixgbe_mac_82599EB: 6249 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6250 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6251 break; 6252 case ixgbe_mac_X540: 6253 case ixgbe_mac_X550: 6254 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6255 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6256 break; 6257 case ixgbe_mac_X550EM_x: 6258 case ixgbe_mac_x550em_a: 6259 default: 6260 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6261 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6262 break; 6263 } 6264 6265 /* Configure DCB traffic classes */ 6266 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6267 tc = &adapter->dcb_cfg.tc_config[j]; 6268 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6269 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6270 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6271 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6272 tc->dcb_pfc = pfc_disabled; 6273 } 6274 6275 /* Initialize default user to priority mapping, UPx->TC0 */ 6276 tc = &adapter->dcb_cfg.tc_config[0]; 6277 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6278 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6279 6280 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6281 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6282 adapter->dcb_cfg.pfc_mode_enable = false; 6283 adapter->dcb_set_bitmap = 0x00; 6284 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6285 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6286 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6287 sizeof(adapter->temp_dcb_cfg)); 6288 } 6289 #endif 6290 6291 /** 6292 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6293 * @adapter: board private structure to initialize 6294 * @ii: pointer to ixgbe_info for device 6295 * 6296 * ixgbe_sw_init initializes the Adapter private data structure. 6297 * Fields are initialized based on PCI device information and 6298 * OS network device settings (MTU size). 6299 **/ 6300 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6301 const struct ixgbe_info *ii) 6302 { 6303 struct ixgbe_hw *hw = &adapter->hw; 6304 struct pci_dev *pdev = adapter->pdev; 6305 unsigned int rss, fdir; 6306 u32 fwsm; 6307 int i; 6308 6309 /* PCI config space info */ 6310 6311 hw->vendor_id = pdev->vendor; 6312 hw->device_id = pdev->device; 6313 hw->revision_id = pdev->revision; 6314 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6315 hw->subsystem_device_id = pdev->subsystem_device; 6316 6317 /* get_invariants needs the device IDs */ 6318 ii->get_invariants(hw); 6319 6320 /* Set common capability flags and settings */ 6321 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6322 adapter->ring_feature[RING_F_RSS].limit = rss; 6323 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6324 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6325 adapter->atr_sample_rate = 20; 6326 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6327 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6328 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6329 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6330 #ifdef CONFIG_IXGBE_DCA 6331 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6332 #endif 6333 #ifdef CONFIG_IXGBE_DCB 6334 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6335 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6336 #endif 6337 #ifdef IXGBE_FCOE 6338 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6339 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6340 #ifdef CONFIG_IXGBE_DCB 6341 /* Default traffic class to use for FCoE */ 6342 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6343 #endif /* CONFIG_IXGBE_DCB */ 6344 #endif /* IXGBE_FCOE */ 6345 6346 /* initialize static ixgbe jump table entries */ 6347 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6348 GFP_KERNEL); 6349 if (!adapter->jump_tables[0]) 6350 return -ENOMEM; 6351 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6352 6353 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6354 adapter->jump_tables[i] = NULL; 6355 6356 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6357 sizeof(struct ixgbe_mac_addr), 6358 GFP_KERNEL); 6359 if (!adapter->mac_table) 6360 return -ENOMEM; 6361 6362 if (ixgbe_init_rss_key(adapter)) 6363 return -ENOMEM; 6364 6365 adapter->af_xdp_zc_qps = bitmap_zalloc(IXGBE_MAX_XDP_QS, GFP_KERNEL); 6366 if (!adapter->af_xdp_zc_qps) 6367 return -ENOMEM; 6368 6369 /* Set MAC specific capability flags and exceptions */ 6370 switch (hw->mac.type) { 6371 case ixgbe_mac_82598EB: 6372 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6373 6374 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6375 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6376 6377 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6378 adapter->ring_feature[RING_F_FDIR].limit = 0; 6379 adapter->atr_sample_rate = 0; 6380 adapter->fdir_pballoc = 0; 6381 #ifdef IXGBE_FCOE 6382 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6383 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6384 #ifdef CONFIG_IXGBE_DCB 6385 adapter->fcoe.up = 0; 6386 #endif /* IXGBE_DCB */ 6387 #endif /* IXGBE_FCOE */ 6388 break; 6389 case ixgbe_mac_82599EB: 6390 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6391 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6392 break; 6393 case ixgbe_mac_X540: 6394 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6395 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6396 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6397 break; 6398 case ixgbe_mac_x550em_a: 6399 switch (hw->device_id) { 6400 case IXGBE_DEV_ID_X550EM_A_1G_T: 6401 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6402 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6403 break; 6404 default: 6405 break; 6406 } 6407 fallthrough; 6408 case ixgbe_mac_X550EM_x: 6409 #ifdef CONFIG_IXGBE_DCB 6410 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6411 #endif 6412 #ifdef IXGBE_FCOE 6413 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6414 #ifdef CONFIG_IXGBE_DCB 6415 adapter->fcoe.up = 0; 6416 #endif /* IXGBE_DCB */ 6417 #endif /* IXGBE_FCOE */ 6418 fallthrough; 6419 case ixgbe_mac_X550: 6420 if (hw->mac.type == ixgbe_mac_X550) 6421 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6422 #ifdef CONFIG_IXGBE_DCA 6423 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6424 #endif 6425 break; 6426 default: 6427 break; 6428 } 6429 6430 #ifdef IXGBE_FCOE 6431 /* FCoE support exists, always init the FCoE lock */ 6432 spin_lock_init(&adapter->fcoe.lock); 6433 6434 #endif 6435 /* n-tuple support exists, always init our spinlock */ 6436 spin_lock_init(&adapter->fdir_perfect_lock); 6437 6438 /* init spinlock to avoid concurrency of VF resources */ 6439 spin_lock_init(&adapter->vfs_lock); 6440 6441 #ifdef CONFIG_IXGBE_DCB 6442 ixgbe_init_dcb(adapter); 6443 #endif 6444 ixgbe_init_ipsec_offload(adapter); 6445 6446 /* default flow control settings */ 6447 hw->fc.requested_mode = ixgbe_fc_full; 6448 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6449 ixgbe_pbthresh_setup(adapter); 6450 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6451 hw->fc.send_xon = true; 6452 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6453 6454 #ifdef CONFIG_PCI_IOV 6455 if (max_vfs > 0) 6456 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6457 6458 /* assign number of SR-IOV VFs */ 6459 if (hw->mac.type != ixgbe_mac_82598EB) { 6460 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6461 max_vfs = 0; 6462 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6463 } 6464 } 6465 #endif /* CONFIG_PCI_IOV */ 6466 6467 /* enable itr by default in dynamic mode */ 6468 adapter->rx_itr_setting = 1; 6469 adapter->tx_itr_setting = 1; 6470 6471 /* set default ring sizes */ 6472 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6473 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6474 6475 /* set default work limits */ 6476 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6477 6478 /* initialize eeprom parameters */ 6479 if (ixgbe_init_eeprom_params_generic(hw)) { 6480 e_dev_err("EEPROM initialization failed\n"); 6481 return -EIO; 6482 } 6483 6484 /* PF holds first pool slot */ 6485 set_bit(0, adapter->fwd_bitmask); 6486 set_bit(__IXGBE_DOWN, &adapter->state); 6487 6488 /* enable locking for XDP_TX if we have more CPUs than queues */ 6489 if (nr_cpu_ids > IXGBE_MAX_XDP_QS) 6490 static_branch_enable(&ixgbe_xdp_locking_key); 6491 6492 return 0; 6493 } 6494 6495 /** 6496 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6497 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6498 * 6499 * Return 0 on success, negative on failure 6500 **/ 6501 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6502 { 6503 struct device *dev = tx_ring->dev; 6504 int orig_node = dev_to_node(dev); 6505 int ring_node = NUMA_NO_NODE; 6506 int size; 6507 6508 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6509 6510 if (tx_ring->q_vector) 6511 ring_node = tx_ring->q_vector->numa_node; 6512 6513 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6514 if (!tx_ring->tx_buffer_info) 6515 tx_ring->tx_buffer_info = vmalloc(size); 6516 if (!tx_ring->tx_buffer_info) 6517 goto err; 6518 6519 /* round up to nearest 4K */ 6520 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6521 tx_ring->size = ALIGN(tx_ring->size, 4096); 6522 6523 set_dev_node(dev, ring_node); 6524 tx_ring->desc = dma_alloc_coherent(dev, 6525 tx_ring->size, 6526 &tx_ring->dma, 6527 GFP_KERNEL); 6528 set_dev_node(dev, orig_node); 6529 if (!tx_ring->desc) 6530 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6531 &tx_ring->dma, GFP_KERNEL); 6532 if (!tx_ring->desc) 6533 goto err; 6534 6535 tx_ring->next_to_use = 0; 6536 tx_ring->next_to_clean = 0; 6537 return 0; 6538 6539 err: 6540 vfree(tx_ring->tx_buffer_info); 6541 tx_ring->tx_buffer_info = NULL; 6542 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6543 return -ENOMEM; 6544 } 6545 6546 /** 6547 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6548 * @adapter: board private structure 6549 * 6550 * If this function returns with an error, then it's possible one or 6551 * more of the rings is populated (while the rest are not). It is the 6552 * callers duty to clean those orphaned rings. 6553 * 6554 * Return 0 on success, negative on failure 6555 **/ 6556 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6557 { 6558 int i, j = 0, err = 0; 6559 6560 for (i = 0; i < adapter->num_tx_queues; i++) { 6561 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6562 if (!err) 6563 continue; 6564 6565 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6566 goto err_setup_tx; 6567 } 6568 for (j = 0; j < adapter->num_xdp_queues; j++) { 6569 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6570 if (!err) 6571 continue; 6572 6573 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6574 goto err_setup_tx; 6575 } 6576 6577 return 0; 6578 err_setup_tx: 6579 /* rewind the index freeing the rings as we go */ 6580 while (j--) 6581 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6582 while (i--) 6583 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6584 return err; 6585 } 6586 6587 static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring) 6588 { 6589 struct ixgbe_q_vector *q_vector = rx_ring->q_vector; 6590 6591 return q_vector ? q_vector->napi.napi_id : 0; 6592 } 6593 6594 /** 6595 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6596 * @adapter: pointer to ixgbe_adapter 6597 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6598 * 6599 * Returns 0 on success, negative on failure 6600 **/ 6601 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6602 struct ixgbe_ring *rx_ring) 6603 { 6604 struct device *dev = rx_ring->dev; 6605 int orig_node = dev_to_node(dev); 6606 int ring_node = NUMA_NO_NODE; 6607 int size; 6608 6609 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6610 6611 if (rx_ring->q_vector) 6612 ring_node = rx_ring->q_vector->numa_node; 6613 6614 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6615 if (!rx_ring->rx_buffer_info) 6616 rx_ring->rx_buffer_info = vmalloc(size); 6617 if (!rx_ring->rx_buffer_info) 6618 goto err; 6619 6620 /* Round up to nearest 4K */ 6621 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6622 rx_ring->size = ALIGN(rx_ring->size, 4096); 6623 6624 set_dev_node(dev, ring_node); 6625 rx_ring->desc = dma_alloc_coherent(dev, 6626 rx_ring->size, 6627 &rx_ring->dma, 6628 GFP_KERNEL); 6629 set_dev_node(dev, orig_node); 6630 if (!rx_ring->desc) 6631 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6632 &rx_ring->dma, GFP_KERNEL); 6633 if (!rx_ring->desc) 6634 goto err; 6635 6636 rx_ring->next_to_clean = 0; 6637 rx_ring->next_to_use = 0; 6638 6639 /* XDP RX-queue info */ 6640 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6641 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0) 6642 goto err; 6643 6644 WRITE_ONCE(rx_ring->xdp_prog, adapter->xdp_prog); 6645 6646 return 0; 6647 err: 6648 vfree(rx_ring->rx_buffer_info); 6649 rx_ring->rx_buffer_info = NULL; 6650 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6651 return -ENOMEM; 6652 } 6653 6654 /** 6655 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6656 * @adapter: board private structure 6657 * 6658 * If this function returns with an error, then it's possible one or 6659 * more of the rings is populated (while the rest are not). It is the 6660 * callers duty to clean those orphaned rings. 6661 * 6662 * Return 0 on success, negative on failure 6663 **/ 6664 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6665 { 6666 int i, err = 0; 6667 6668 for (i = 0; i < adapter->num_rx_queues; i++) { 6669 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6670 if (!err) 6671 continue; 6672 6673 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6674 goto err_setup_rx; 6675 } 6676 6677 #ifdef IXGBE_FCOE 6678 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6679 if (!err) 6680 #endif 6681 return 0; 6682 err_setup_rx: 6683 /* rewind the index freeing the rings as we go */ 6684 while (i--) 6685 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6686 return err; 6687 } 6688 6689 /** 6690 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6691 * @tx_ring: Tx descriptor ring for a specific queue 6692 * 6693 * Free all transmit software resources 6694 **/ 6695 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6696 { 6697 ixgbe_clean_tx_ring(tx_ring); 6698 6699 vfree(tx_ring->tx_buffer_info); 6700 tx_ring->tx_buffer_info = NULL; 6701 6702 /* if not set, then don't free */ 6703 if (!tx_ring->desc) 6704 return; 6705 6706 dma_free_coherent(tx_ring->dev, tx_ring->size, 6707 tx_ring->desc, tx_ring->dma); 6708 6709 tx_ring->desc = NULL; 6710 } 6711 6712 /** 6713 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6714 * @adapter: board private structure 6715 * 6716 * Free all transmit software resources 6717 **/ 6718 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6719 { 6720 int i; 6721 6722 for (i = 0; i < adapter->num_tx_queues; i++) 6723 if (adapter->tx_ring[i]->desc) 6724 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6725 for (i = 0; i < adapter->num_xdp_queues; i++) 6726 if (adapter->xdp_ring[i]->desc) 6727 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6728 } 6729 6730 /** 6731 * ixgbe_free_rx_resources - Free Rx Resources 6732 * @rx_ring: ring to clean the resources from 6733 * 6734 * Free all receive software resources 6735 **/ 6736 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6737 { 6738 ixgbe_clean_rx_ring(rx_ring); 6739 6740 rx_ring->xdp_prog = NULL; 6741 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6742 vfree(rx_ring->rx_buffer_info); 6743 rx_ring->rx_buffer_info = NULL; 6744 6745 /* if not set, then don't free */ 6746 if (!rx_ring->desc) 6747 return; 6748 6749 dma_free_coherent(rx_ring->dev, rx_ring->size, 6750 rx_ring->desc, rx_ring->dma); 6751 6752 rx_ring->desc = NULL; 6753 } 6754 6755 /** 6756 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6757 * @adapter: board private structure 6758 * 6759 * Free all receive software resources 6760 **/ 6761 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6762 { 6763 int i; 6764 6765 #ifdef IXGBE_FCOE 6766 ixgbe_free_fcoe_ddp_resources(adapter); 6767 6768 #endif 6769 for (i = 0; i < adapter->num_rx_queues; i++) 6770 if (adapter->rx_ring[i]->desc) 6771 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6772 } 6773 6774 /** 6775 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP 6776 * @adapter: device handle, pointer to adapter 6777 */ 6778 static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter) 6779 { 6780 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 6781 return IXGBE_RXBUFFER_2K; 6782 else 6783 return IXGBE_RXBUFFER_3K; 6784 } 6785 6786 /** 6787 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6788 * @netdev: network interface device structure 6789 * @new_mtu: new value for maximum frame size 6790 * 6791 * Returns 0 on success, negative on failure 6792 **/ 6793 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6794 { 6795 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6796 6797 if (ixgbe_enabled_xdp_adapter(adapter)) { 6798 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD; 6799 6800 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) { 6801 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6802 return -EINVAL; 6803 } 6804 } 6805 6806 /* 6807 * For 82599EB we cannot allow legacy VFs to enable their receive 6808 * paths when MTU greater than 1500 is configured. So display a 6809 * warning that legacy VFs will be disabled. 6810 */ 6811 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6812 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6813 (new_mtu > ETH_DATA_LEN)) 6814 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6815 6816 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6817 netdev->mtu, new_mtu); 6818 6819 /* must set new MTU before calling down or up */ 6820 netdev->mtu = new_mtu; 6821 6822 if (netif_running(netdev)) 6823 ixgbe_reinit_locked(adapter); 6824 6825 return 0; 6826 } 6827 6828 /** 6829 * ixgbe_open - Called when a network interface is made active 6830 * @netdev: network interface device structure 6831 * 6832 * Returns 0 on success, negative value on failure 6833 * 6834 * The open entry point is called when a network interface is made 6835 * active by the system (IFF_UP). At this point all resources needed 6836 * for transmit and receive operations are allocated, the interrupt 6837 * handler is registered with the OS, the watchdog timer is started, 6838 * and the stack is notified that the interface is ready. 6839 **/ 6840 int ixgbe_open(struct net_device *netdev) 6841 { 6842 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6843 struct ixgbe_hw *hw = &adapter->hw; 6844 int err, queues; 6845 6846 /* disallow open during test */ 6847 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6848 return -EBUSY; 6849 6850 netif_carrier_off(netdev); 6851 6852 /* allocate transmit descriptors */ 6853 err = ixgbe_setup_all_tx_resources(adapter); 6854 if (err) 6855 goto err_setup_tx; 6856 6857 /* allocate receive descriptors */ 6858 err = ixgbe_setup_all_rx_resources(adapter); 6859 if (err) 6860 goto err_setup_rx; 6861 6862 ixgbe_configure(adapter); 6863 6864 err = ixgbe_request_irq(adapter); 6865 if (err) 6866 goto err_req_irq; 6867 6868 /* Notify the stack of the actual queue counts. */ 6869 queues = adapter->num_tx_queues; 6870 err = netif_set_real_num_tx_queues(netdev, queues); 6871 if (err) 6872 goto err_set_queues; 6873 6874 queues = adapter->num_rx_queues; 6875 err = netif_set_real_num_rx_queues(netdev, queues); 6876 if (err) 6877 goto err_set_queues; 6878 6879 ixgbe_ptp_init(adapter); 6880 6881 ixgbe_up_complete(adapter); 6882 6883 udp_tunnel_nic_reset_ntf(netdev); 6884 6885 return 0; 6886 6887 err_set_queues: 6888 ixgbe_free_irq(adapter); 6889 err_req_irq: 6890 ixgbe_free_all_rx_resources(adapter); 6891 if (hw->phy.ops.set_phy_power && !adapter->wol) 6892 hw->phy.ops.set_phy_power(&adapter->hw, false); 6893 err_setup_rx: 6894 ixgbe_free_all_tx_resources(adapter); 6895 err_setup_tx: 6896 ixgbe_reset(adapter); 6897 6898 return err; 6899 } 6900 6901 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6902 { 6903 ixgbe_ptp_suspend(adapter); 6904 6905 if (adapter->hw.phy.ops.enter_lplu) { 6906 adapter->hw.phy.reset_disable = true; 6907 ixgbe_down(adapter); 6908 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6909 adapter->hw.phy.reset_disable = false; 6910 } else { 6911 ixgbe_down(adapter); 6912 } 6913 6914 ixgbe_free_irq(adapter); 6915 6916 ixgbe_free_all_tx_resources(adapter); 6917 ixgbe_free_all_rx_resources(adapter); 6918 } 6919 6920 /** 6921 * ixgbe_close - Disables a network interface 6922 * @netdev: network interface device structure 6923 * 6924 * Returns 0, this is not allowed to fail 6925 * 6926 * The close entry point is called when an interface is de-activated 6927 * by the OS. The hardware is still under the drivers control, but 6928 * needs to be disabled. A global MAC reset is issued to stop the 6929 * hardware, and all transmit and receive resources are freed. 6930 **/ 6931 int ixgbe_close(struct net_device *netdev) 6932 { 6933 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6934 6935 ixgbe_ptp_stop(adapter); 6936 6937 if (netif_device_present(netdev)) 6938 ixgbe_close_suspend(adapter); 6939 6940 ixgbe_fdir_filter_exit(adapter); 6941 6942 ixgbe_release_hw_control(adapter); 6943 6944 return 0; 6945 } 6946 6947 static int __maybe_unused ixgbe_resume(struct device *dev_d) 6948 { 6949 struct pci_dev *pdev = to_pci_dev(dev_d); 6950 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6951 struct net_device *netdev = adapter->netdev; 6952 u32 err; 6953 6954 adapter->hw.hw_addr = adapter->io_addr; 6955 6956 err = pci_enable_device_mem(pdev); 6957 if (err) { 6958 e_dev_err("Cannot enable PCI device from suspend\n"); 6959 return err; 6960 } 6961 smp_mb__before_atomic(); 6962 clear_bit(__IXGBE_DISABLED, &adapter->state); 6963 pci_set_master(pdev); 6964 6965 device_wakeup_disable(dev_d); 6966 6967 ixgbe_reset(adapter); 6968 6969 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6970 6971 rtnl_lock(); 6972 err = ixgbe_init_interrupt_scheme(adapter); 6973 if (!err && netif_running(netdev)) 6974 err = ixgbe_open(netdev); 6975 6976 6977 if (!err) 6978 netif_device_attach(netdev); 6979 rtnl_unlock(); 6980 6981 return err; 6982 } 6983 6984 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6985 { 6986 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6987 struct net_device *netdev = adapter->netdev; 6988 struct ixgbe_hw *hw = &adapter->hw; 6989 u32 ctrl; 6990 u32 wufc = adapter->wol; 6991 6992 rtnl_lock(); 6993 netif_device_detach(netdev); 6994 6995 if (netif_running(netdev)) 6996 ixgbe_close_suspend(adapter); 6997 6998 ixgbe_clear_interrupt_scheme(adapter); 6999 rtnl_unlock(); 7000 7001 if (hw->mac.ops.stop_link_on_d3) 7002 hw->mac.ops.stop_link_on_d3(hw); 7003 7004 if (wufc) { 7005 u32 fctrl; 7006 7007 ixgbe_set_rx_mode(netdev); 7008 7009 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 7010 if (hw->mac.ops.enable_tx_laser) 7011 hw->mac.ops.enable_tx_laser(hw); 7012 7013 /* enable the reception of multicast packets */ 7014 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7015 fctrl |= IXGBE_FCTRL_MPE; 7016 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 7017 7018 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 7019 ctrl |= IXGBE_CTRL_GIO_DIS; 7020 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 7021 7022 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 7023 } else { 7024 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 7025 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 7026 } 7027 7028 switch (hw->mac.type) { 7029 case ixgbe_mac_82598EB: 7030 pci_wake_from_d3(pdev, false); 7031 break; 7032 case ixgbe_mac_82599EB: 7033 case ixgbe_mac_X540: 7034 case ixgbe_mac_X550: 7035 case ixgbe_mac_X550EM_x: 7036 case ixgbe_mac_x550em_a: 7037 pci_wake_from_d3(pdev, !!wufc); 7038 break; 7039 default: 7040 break; 7041 } 7042 7043 *enable_wake = !!wufc; 7044 if (hw->phy.ops.set_phy_power && !*enable_wake) 7045 hw->phy.ops.set_phy_power(hw, false); 7046 7047 ixgbe_release_hw_control(adapter); 7048 7049 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 7050 pci_disable_device(pdev); 7051 7052 return 0; 7053 } 7054 7055 static int __maybe_unused ixgbe_suspend(struct device *dev_d) 7056 { 7057 struct pci_dev *pdev = to_pci_dev(dev_d); 7058 int retval; 7059 bool wake; 7060 7061 retval = __ixgbe_shutdown(pdev, &wake); 7062 7063 device_set_wakeup_enable(dev_d, wake); 7064 7065 return retval; 7066 } 7067 7068 static void ixgbe_shutdown(struct pci_dev *pdev) 7069 { 7070 bool wake; 7071 7072 __ixgbe_shutdown(pdev, &wake); 7073 7074 if (system_state == SYSTEM_POWER_OFF) { 7075 pci_wake_from_d3(pdev, wake); 7076 pci_set_power_state(pdev, PCI_D3hot); 7077 } 7078 } 7079 7080 /** 7081 * ixgbe_update_stats - Update the board statistics counters. 7082 * @adapter: board private structure 7083 **/ 7084 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7085 { 7086 struct net_device *netdev = adapter->netdev; 7087 struct ixgbe_hw *hw = &adapter->hw; 7088 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7089 u64 total_mpc = 0; 7090 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7091 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7092 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7093 u64 alloc_rx_page = 0; 7094 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7095 7096 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7097 test_bit(__IXGBE_RESETTING, &adapter->state)) 7098 return; 7099 7100 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7101 u64 rsc_count = 0; 7102 u64 rsc_flush = 0; 7103 for (i = 0; i < adapter->num_rx_queues; i++) { 7104 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7105 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7106 } 7107 adapter->rsc_total_count = rsc_count; 7108 adapter->rsc_total_flush = rsc_flush; 7109 } 7110 7111 for (i = 0; i < adapter->num_rx_queues; i++) { 7112 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7113 7114 if (!rx_ring) 7115 continue; 7116 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7117 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7118 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7119 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7120 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7121 bytes += rx_ring->stats.bytes; 7122 packets += rx_ring->stats.packets; 7123 } 7124 adapter->non_eop_descs = non_eop_descs; 7125 adapter->alloc_rx_page = alloc_rx_page; 7126 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7127 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7128 adapter->hw_csum_rx_error = hw_csum_rx_error; 7129 netdev->stats.rx_bytes = bytes; 7130 netdev->stats.rx_packets = packets; 7131 7132 bytes = 0; 7133 packets = 0; 7134 /* gather some stats to the adapter struct that are per queue */ 7135 for (i = 0; i < adapter->num_tx_queues; i++) { 7136 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7137 7138 if (!tx_ring) 7139 continue; 7140 restart_queue += tx_ring->tx_stats.restart_queue; 7141 tx_busy += tx_ring->tx_stats.tx_busy; 7142 bytes += tx_ring->stats.bytes; 7143 packets += tx_ring->stats.packets; 7144 } 7145 for (i = 0; i < adapter->num_xdp_queues; i++) { 7146 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7147 7148 if (!xdp_ring) 7149 continue; 7150 restart_queue += xdp_ring->tx_stats.restart_queue; 7151 tx_busy += xdp_ring->tx_stats.tx_busy; 7152 bytes += xdp_ring->stats.bytes; 7153 packets += xdp_ring->stats.packets; 7154 } 7155 adapter->restart_queue = restart_queue; 7156 adapter->tx_busy = tx_busy; 7157 netdev->stats.tx_bytes = bytes; 7158 netdev->stats.tx_packets = packets; 7159 7160 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7161 7162 /* 8 register reads */ 7163 for (i = 0; i < 8; i++) { 7164 /* for packet buffers not used, the register should read 0 */ 7165 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7166 missed_rx += mpc; 7167 hwstats->mpc[i] += mpc; 7168 total_mpc += hwstats->mpc[i]; 7169 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7170 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7171 switch (hw->mac.type) { 7172 case ixgbe_mac_82598EB: 7173 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7174 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7175 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7176 hwstats->pxonrxc[i] += 7177 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7178 break; 7179 case ixgbe_mac_82599EB: 7180 case ixgbe_mac_X540: 7181 case ixgbe_mac_X550: 7182 case ixgbe_mac_X550EM_x: 7183 case ixgbe_mac_x550em_a: 7184 hwstats->pxonrxc[i] += 7185 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7186 break; 7187 default: 7188 break; 7189 } 7190 } 7191 7192 /*16 register reads */ 7193 for (i = 0; i < 16; i++) { 7194 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7195 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7196 if ((hw->mac.type == ixgbe_mac_82599EB) || 7197 (hw->mac.type == ixgbe_mac_X540) || 7198 (hw->mac.type == ixgbe_mac_X550) || 7199 (hw->mac.type == ixgbe_mac_X550EM_x) || 7200 (hw->mac.type == ixgbe_mac_x550em_a)) { 7201 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7202 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7203 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7204 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7205 } 7206 } 7207 7208 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7209 /* work around hardware counting issue */ 7210 hwstats->gprc -= missed_rx; 7211 7212 ixgbe_update_xoff_received(adapter); 7213 7214 /* 82598 hardware only has a 32 bit counter in the high register */ 7215 switch (hw->mac.type) { 7216 case ixgbe_mac_82598EB: 7217 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7218 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7219 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7220 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7221 break; 7222 case ixgbe_mac_X540: 7223 case ixgbe_mac_X550: 7224 case ixgbe_mac_X550EM_x: 7225 case ixgbe_mac_x550em_a: 7226 /* OS2BMC stats are X540 and later */ 7227 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7228 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7229 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7230 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7231 fallthrough; 7232 case ixgbe_mac_82599EB: 7233 for (i = 0; i < 16; i++) 7234 adapter->hw_rx_no_dma_resources += 7235 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7236 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7237 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7238 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7239 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7240 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7241 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7242 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7243 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7244 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7245 #ifdef IXGBE_FCOE 7246 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7247 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7248 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7249 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7250 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7251 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7252 /* Add up per cpu counters for total ddp aloc fail */ 7253 if (adapter->fcoe.ddp_pool) { 7254 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7255 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7256 unsigned int cpu; 7257 u64 noddp = 0, noddp_ext_buff = 0; 7258 for_each_possible_cpu(cpu) { 7259 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7260 noddp += ddp_pool->noddp; 7261 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7262 } 7263 hwstats->fcoe_noddp = noddp; 7264 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7265 } 7266 #endif /* IXGBE_FCOE */ 7267 break; 7268 default: 7269 break; 7270 } 7271 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7272 hwstats->bprc += bprc; 7273 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7274 if (hw->mac.type == ixgbe_mac_82598EB) 7275 hwstats->mprc -= bprc; 7276 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7277 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7278 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7279 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7280 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7281 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7282 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7283 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7284 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7285 hwstats->lxontxc += lxon; 7286 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7287 hwstats->lxofftxc += lxoff; 7288 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7289 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7290 /* 7291 * 82598 errata - tx of flow control packets is included in tx counters 7292 */ 7293 xon_off_tot = lxon + lxoff; 7294 hwstats->gptc -= xon_off_tot; 7295 hwstats->mptc -= xon_off_tot; 7296 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7297 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7298 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7299 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7300 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7301 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7302 hwstats->ptc64 -= xon_off_tot; 7303 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7304 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7305 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7306 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7307 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7308 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7309 7310 /* Fill out the OS statistics structure */ 7311 netdev->stats.multicast = hwstats->mprc; 7312 7313 /* Rx Errors */ 7314 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7315 netdev->stats.rx_dropped = 0; 7316 netdev->stats.rx_length_errors = hwstats->rlec; 7317 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7318 netdev->stats.rx_missed_errors = total_mpc; 7319 7320 /* VF Stats Collection - skip while resetting because these 7321 * are not clear on read and otherwise you'll sometimes get 7322 * crazy values. 7323 */ 7324 if (!test_bit(__IXGBE_RESETTING, &adapter->state)) { 7325 for (i = 0; i < adapter->num_vfs; i++) { 7326 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i), 7327 adapter->vfinfo[i].last_vfstats.gprc, 7328 adapter->vfinfo[i].vfstats.gprc); 7329 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i), 7330 adapter->vfinfo[i].last_vfstats.gptc, 7331 adapter->vfinfo[i].vfstats.gptc); 7332 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i), 7333 IXGBE_PVFGORC_MSB(i), 7334 adapter->vfinfo[i].last_vfstats.gorc, 7335 adapter->vfinfo[i].vfstats.gorc); 7336 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i), 7337 IXGBE_PVFGOTC_MSB(i), 7338 adapter->vfinfo[i].last_vfstats.gotc, 7339 adapter->vfinfo[i].vfstats.gotc); 7340 UPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i), 7341 adapter->vfinfo[i].last_vfstats.mprc, 7342 adapter->vfinfo[i].vfstats.mprc); 7343 } 7344 } 7345 } 7346 7347 /** 7348 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7349 * @adapter: pointer to the device adapter structure 7350 **/ 7351 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7352 { 7353 struct ixgbe_hw *hw = &adapter->hw; 7354 int i; 7355 7356 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7357 return; 7358 7359 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7360 7361 /* if interface is down do nothing */ 7362 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7363 return; 7364 7365 /* do nothing if we are not using signature filters */ 7366 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7367 return; 7368 7369 adapter->fdir_overflow++; 7370 7371 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7372 for (i = 0; i < adapter->num_tx_queues; i++) 7373 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7374 &(adapter->tx_ring[i]->state)); 7375 for (i = 0; i < adapter->num_xdp_queues; i++) 7376 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7377 &adapter->xdp_ring[i]->state); 7378 /* re-enable flow director interrupts */ 7379 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7380 } else { 7381 e_err(probe, "failed to finish FDIR re-initialization, " 7382 "ignored adding FDIR ATR filters\n"); 7383 } 7384 } 7385 7386 /** 7387 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7388 * @adapter: pointer to the device adapter structure 7389 * 7390 * This function serves two purposes. First it strobes the interrupt lines 7391 * in order to make certain interrupts are occurring. Secondly it sets the 7392 * bits needed to check for TX hangs. As a result we should immediately 7393 * determine if a hang has occurred. 7394 */ 7395 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7396 { 7397 struct ixgbe_hw *hw = &adapter->hw; 7398 u64 eics = 0; 7399 int i; 7400 7401 /* If we're down, removing or resetting, just bail */ 7402 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7403 test_bit(__IXGBE_REMOVING, &adapter->state) || 7404 test_bit(__IXGBE_RESETTING, &adapter->state)) 7405 return; 7406 7407 /* Force detection of hung controller */ 7408 if (netif_carrier_ok(adapter->netdev)) { 7409 for (i = 0; i < adapter->num_tx_queues; i++) 7410 set_check_for_tx_hang(adapter->tx_ring[i]); 7411 for (i = 0; i < adapter->num_xdp_queues; i++) 7412 set_check_for_tx_hang(adapter->xdp_ring[i]); 7413 } 7414 7415 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7416 /* 7417 * for legacy and MSI interrupts don't set any bits 7418 * that are enabled for EIAM, because this operation 7419 * would set *both* EIMS and EICS for any bit in EIAM 7420 */ 7421 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7422 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7423 } else { 7424 /* get one bit for every active tx/rx interrupt vector */ 7425 for (i = 0; i < adapter->num_q_vectors; i++) { 7426 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7427 if (qv->rx.ring || qv->tx.ring) 7428 eics |= BIT_ULL(i); 7429 } 7430 } 7431 7432 /* Cause software interrupt to ensure rings are cleaned */ 7433 ixgbe_irq_rearm_queues(adapter, eics); 7434 } 7435 7436 /** 7437 * ixgbe_watchdog_update_link - update the link status 7438 * @adapter: pointer to the device adapter structure 7439 **/ 7440 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7441 { 7442 struct ixgbe_hw *hw = &adapter->hw; 7443 u32 link_speed = adapter->link_speed; 7444 bool link_up = adapter->link_up; 7445 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7446 7447 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7448 return; 7449 7450 if (hw->mac.ops.check_link) { 7451 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7452 } else { 7453 /* always assume link is up, if no check link function */ 7454 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7455 link_up = true; 7456 } 7457 7458 if (adapter->ixgbe_ieee_pfc) 7459 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7460 7461 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7462 hw->mac.ops.fc_enable(hw); 7463 ixgbe_set_rx_drop_en(adapter); 7464 } 7465 7466 if (link_up || 7467 time_after(jiffies, (adapter->link_check_timeout + 7468 IXGBE_TRY_LINK_TIMEOUT))) { 7469 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7470 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7471 IXGBE_WRITE_FLUSH(hw); 7472 } 7473 7474 adapter->link_up = link_up; 7475 adapter->link_speed = link_speed; 7476 } 7477 7478 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7479 { 7480 #ifdef CONFIG_IXGBE_DCB 7481 struct net_device *netdev = adapter->netdev; 7482 struct dcb_app app = { 7483 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7484 .protocol = 0, 7485 }; 7486 u8 up = 0; 7487 7488 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7489 up = dcb_ieee_getapp_mask(netdev, &app); 7490 7491 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7492 #endif 7493 } 7494 7495 /** 7496 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7497 * print link up message 7498 * @adapter: pointer to the device adapter structure 7499 **/ 7500 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7501 { 7502 struct net_device *netdev = adapter->netdev; 7503 struct ixgbe_hw *hw = &adapter->hw; 7504 u32 link_speed = adapter->link_speed; 7505 const char *speed_str; 7506 bool flow_rx, flow_tx; 7507 7508 /* only continue if link was previously down */ 7509 if (netif_carrier_ok(netdev)) 7510 return; 7511 7512 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7513 7514 switch (hw->mac.type) { 7515 case ixgbe_mac_82598EB: { 7516 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7517 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7518 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7519 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7520 } 7521 break; 7522 case ixgbe_mac_X540: 7523 case ixgbe_mac_X550: 7524 case ixgbe_mac_X550EM_x: 7525 case ixgbe_mac_x550em_a: 7526 case ixgbe_mac_82599EB: { 7527 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7528 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7529 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7530 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7531 } 7532 break; 7533 default: 7534 flow_tx = false; 7535 flow_rx = false; 7536 break; 7537 } 7538 7539 adapter->last_rx_ptp_check = jiffies; 7540 7541 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7542 ixgbe_ptp_start_cyclecounter(adapter); 7543 7544 switch (link_speed) { 7545 case IXGBE_LINK_SPEED_10GB_FULL: 7546 speed_str = "10 Gbps"; 7547 break; 7548 case IXGBE_LINK_SPEED_5GB_FULL: 7549 speed_str = "5 Gbps"; 7550 break; 7551 case IXGBE_LINK_SPEED_2_5GB_FULL: 7552 speed_str = "2.5 Gbps"; 7553 break; 7554 case IXGBE_LINK_SPEED_1GB_FULL: 7555 speed_str = "1 Gbps"; 7556 break; 7557 case IXGBE_LINK_SPEED_100_FULL: 7558 speed_str = "100 Mbps"; 7559 break; 7560 case IXGBE_LINK_SPEED_10_FULL: 7561 speed_str = "10 Mbps"; 7562 break; 7563 default: 7564 speed_str = "unknown speed"; 7565 break; 7566 } 7567 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7568 ((flow_rx && flow_tx) ? "RX/TX" : 7569 (flow_rx ? "RX" : 7570 (flow_tx ? "TX" : "None")))); 7571 7572 netif_carrier_on(netdev); 7573 ixgbe_check_vf_rate_limit(adapter); 7574 7575 /* enable transmits */ 7576 netif_tx_wake_all_queues(adapter->netdev); 7577 7578 /* update the default user priority for VFs */ 7579 ixgbe_update_default_up(adapter); 7580 7581 /* ping all the active vfs to let them know link has changed */ 7582 ixgbe_ping_all_vfs(adapter); 7583 } 7584 7585 /** 7586 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7587 * print link down message 7588 * @adapter: pointer to the adapter structure 7589 **/ 7590 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7591 { 7592 struct net_device *netdev = adapter->netdev; 7593 struct ixgbe_hw *hw = &adapter->hw; 7594 7595 adapter->link_up = false; 7596 adapter->link_speed = 0; 7597 7598 /* only continue if link was up previously */ 7599 if (!netif_carrier_ok(netdev)) 7600 return; 7601 7602 /* poll for SFP+ cable when link is down */ 7603 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7604 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7605 7606 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7607 ixgbe_ptp_start_cyclecounter(adapter); 7608 7609 e_info(drv, "NIC Link is Down\n"); 7610 netif_carrier_off(netdev); 7611 7612 /* ping all the active vfs to let them know link has changed */ 7613 ixgbe_ping_all_vfs(adapter); 7614 } 7615 7616 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7617 { 7618 int i; 7619 7620 for (i = 0; i < adapter->num_tx_queues; i++) { 7621 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7622 7623 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7624 return true; 7625 } 7626 7627 for (i = 0; i < adapter->num_xdp_queues; i++) { 7628 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7629 7630 if (ring->next_to_use != ring->next_to_clean) 7631 return true; 7632 } 7633 7634 return false; 7635 } 7636 7637 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7638 { 7639 struct ixgbe_hw *hw = &adapter->hw; 7640 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7641 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7642 7643 int i, j; 7644 7645 if (!adapter->num_vfs) 7646 return false; 7647 7648 /* resetting the PF is only needed for MAC before X550 */ 7649 if (hw->mac.type >= ixgbe_mac_X550) 7650 return false; 7651 7652 for (i = 0; i < adapter->num_vfs; i++) { 7653 for (j = 0; j < q_per_pool; j++) { 7654 u32 h, t; 7655 7656 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7657 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7658 7659 if (h != t) 7660 return true; 7661 } 7662 } 7663 7664 return false; 7665 } 7666 7667 /** 7668 * ixgbe_watchdog_flush_tx - flush queues on link down 7669 * @adapter: pointer to the device adapter structure 7670 **/ 7671 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7672 { 7673 if (!netif_carrier_ok(adapter->netdev)) { 7674 if (ixgbe_ring_tx_pending(adapter) || 7675 ixgbe_vf_tx_pending(adapter)) { 7676 /* We've lost link, so the controller stops DMA, 7677 * but we've got queued Tx work that's never going 7678 * to get done, so reset controller to flush Tx. 7679 * (Do the reset outside of interrupt context). 7680 */ 7681 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7682 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7683 } 7684 } 7685 } 7686 7687 #ifdef CONFIG_PCI_IOV 7688 static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf) 7689 { 7690 struct ixgbe_hw *hw = &adapter->hw; 7691 7692 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 7693 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) { 7694 adapter->vfinfo[vf].primary_abort_count++; 7695 if (adapter->vfinfo[vf].primary_abort_count == 7696 IXGBE_PRIMARY_ABORT_LIMIT) { 7697 ixgbe_set_vf_link_state(adapter, vf, 7698 IFLA_VF_LINK_STATE_DISABLE); 7699 adapter->vfinfo[vf].primary_abort_count = 0; 7700 7701 e_info(drv, 7702 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on", 7703 hw->bus.func, vf, 7704 adapter->vfinfo[vf].vf_mac_addresses); 7705 } 7706 } 7707 } 7708 7709 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7710 { 7711 struct ixgbe_hw *hw = &adapter->hw; 7712 struct pci_dev *pdev = adapter->pdev; 7713 unsigned int vf; 7714 u32 gpc; 7715 7716 if (!(netif_carrier_ok(adapter->netdev))) 7717 return; 7718 7719 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7720 if (gpc) /* If incrementing then no need for the check below */ 7721 return; 7722 /* Check to see if a bad DMA write target from an errant or 7723 * malicious VF has caused a PCIe error. If so then we can 7724 * issue a VFLR to the offending VF(s) and then resume without 7725 * requesting a full slot reset. 7726 */ 7727 7728 if (!pdev) 7729 return; 7730 7731 /* check status reg for all VFs owned by this PF */ 7732 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7733 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7734 u16 status_reg; 7735 7736 if (!vfdev) 7737 continue; 7738 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7739 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7740 status_reg & PCI_STATUS_REC_MASTER_ABORT) { 7741 ixgbe_bad_vf_abort(adapter, vf); 7742 pcie_flr(vfdev); 7743 } 7744 } 7745 } 7746 7747 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7748 { 7749 u32 ssvpc; 7750 7751 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7752 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7753 adapter->num_vfs == 0) 7754 return; 7755 7756 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7757 7758 /* 7759 * ssvpc register is cleared on read, if zero then no 7760 * spoofed packets in the last interval. 7761 */ 7762 if (!ssvpc) 7763 return; 7764 7765 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7766 } 7767 #else 7768 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7769 { 7770 } 7771 7772 static void 7773 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7774 { 7775 } 7776 #endif /* CONFIG_PCI_IOV */ 7777 7778 7779 /** 7780 * ixgbe_watchdog_subtask - check and bring link up 7781 * @adapter: pointer to the device adapter structure 7782 **/ 7783 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7784 { 7785 /* if interface is down, removing or resetting, do nothing */ 7786 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7787 test_bit(__IXGBE_REMOVING, &adapter->state) || 7788 test_bit(__IXGBE_RESETTING, &adapter->state)) 7789 return; 7790 7791 ixgbe_watchdog_update_link(adapter); 7792 7793 if (adapter->link_up) 7794 ixgbe_watchdog_link_is_up(adapter); 7795 else 7796 ixgbe_watchdog_link_is_down(adapter); 7797 7798 ixgbe_check_for_bad_vf(adapter); 7799 ixgbe_spoof_check(adapter); 7800 ixgbe_update_stats(adapter); 7801 7802 ixgbe_watchdog_flush_tx(adapter); 7803 } 7804 7805 /** 7806 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7807 * @adapter: the ixgbe adapter structure 7808 **/ 7809 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7810 { 7811 struct ixgbe_hw *hw = &adapter->hw; 7812 s32 err; 7813 7814 /* not searching for SFP so there is nothing to do here */ 7815 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7816 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7817 return; 7818 7819 if (adapter->sfp_poll_time && 7820 time_after(adapter->sfp_poll_time, jiffies)) 7821 return; /* If not yet time to poll for SFP */ 7822 7823 /* someone else is in init, wait until next service event */ 7824 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7825 return; 7826 7827 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7828 7829 err = hw->phy.ops.identify_sfp(hw); 7830 if (err == -EOPNOTSUPP) 7831 goto sfp_out; 7832 7833 if (err == -ENOENT) { 7834 /* If no cable is present, then we need to reset 7835 * the next time we find a good cable. */ 7836 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7837 } 7838 7839 /* exit on error */ 7840 if (err) 7841 goto sfp_out; 7842 7843 /* exit if reset not needed */ 7844 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7845 goto sfp_out; 7846 7847 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7848 7849 /* 7850 * A module may be identified correctly, but the EEPROM may not have 7851 * support for that module. setup_sfp() will fail in that case, so 7852 * we should not allow that module to load. 7853 */ 7854 if (hw->mac.type == ixgbe_mac_82598EB) 7855 err = hw->phy.ops.reset(hw); 7856 else 7857 err = hw->mac.ops.setup_sfp(hw); 7858 7859 if (err == -EOPNOTSUPP) 7860 goto sfp_out; 7861 7862 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7863 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7864 7865 sfp_out: 7866 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7867 7868 if (err == -EOPNOTSUPP && 7869 adapter->netdev->reg_state == NETREG_REGISTERED) { 7870 e_dev_err("failed to initialize because an unsupported " 7871 "SFP+ module type was detected.\n"); 7872 e_dev_err("Reload the driver after installing a " 7873 "supported module.\n"); 7874 unregister_netdev(adapter->netdev); 7875 } 7876 } 7877 7878 /** 7879 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7880 * @adapter: the ixgbe adapter structure 7881 **/ 7882 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7883 { 7884 struct ixgbe_hw *hw = &adapter->hw; 7885 u32 cap_speed; 7886 u32 speed; 7887 bool autoneg = false; 7888 7889 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7890 return; 7891 7892 /* someone else is in init, wait until next service event */ 7893 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7894 return; 7895 7896 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7897 7898 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7899 7900 /* advertise highest capable link speed */ 7901 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7902 speed = IXGBE_LINK_SPEED_10GB_FULL; 7903 else 7904 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7905 IXGBE_LINK_SPEED_1GB_FULL); 7906 7907 if (hw->mac.ops.setup_link) 7908 hw->mac.ops.setup_link(hw, speed, true); 7909 7910 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7911 adapter->link_check_timeout = jiffies; 7912 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7913 } 7914 7915 /** 7916 * ixgbe_service_timer - Timer Call-back 7917 * @t: pointer to timer_list structure 7918 **/ 7919 static void ixgbe_service_timer(struct timer_list *t) 7920 { 7921 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7922 unsigned long next_event_offset; 7923 7924 /* poll faster when waiting for link */ 7925 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7926 next_event_offset = HZ / 10; 7927 else 7928 next_event_offset = HZ * 2; 7929 7930 /* Reset the timer */ 7931 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7932 7933 ixgbe_service_event_schedule(adapter); 7934 } 7935 7936 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7937 { 7938 struct ixgbe_hw *hw = &adapter->hw; 7939 bool overtemp; 7940 7941 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7942 return; 7943 7944 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7945 7946 if (!hw->phy.ops.handle_lasi) 7947 return; 7948 7949 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp); 7950 if (overtemp) 7951 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7952 } 7953 7954 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7955 { 7956 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7957 return; 7958 7959 rtnl_lock(); 7960 /* If we're already down, removing or resetting, just bail */ 7961 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7962 test_bit(__IXGBE_REMOVING, &adapter->state) || 7963 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7964 rtnl_unlock(); 7965 return; 7966 } 7967 7968 ixgbe_dump(adapter); 7969 netdev_err(adapter->netdev, "Reset adapter\n"); 7970 adapter->tx_timeout_count++; 7971 7972 ixgbe_reinit_locked(adapter); 7973 rtnl_unlock(); 7974 } 7975 7976 /** 7977 * ixgbe_check_fw_error - Check firmware for errors 7978 * @adapter: the adapter private structure 7979 * 7980 * Check firmware errors in register FWSM 7981 */ 7982 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7983 { 7984 struct ixgbe_hw *hw = &adapter->hw; 7985 u32 fwsm; 7986 7987 /* read fwsm.ext_err_ind register and log errors */ 7988 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7989 7990 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7991 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7992 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7993 fwsm); 7994 7995 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7996 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7997 return true; 7998 } 7999 8000 return false; 8001 } 8002 8003 /** 8004 * ixgbe_service_task - manages and runs subtasks 8005 * @work: pointer to work_struct containing our data 8006 **/ 8007 static void ixgbe_service_task(struct work_struct *work) 8008 { 8009 struct ixgbe_adapter *adapter = container_of(work, 8010 struct ixgbe_adapter, 8011 service_task); 8012 if (ixgbe_removed(adapter->hw.hw_addr)) { 8013 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 8014 rtnl_lock(); 8015 ixgbe_down(adapter); 8016 rtnl_unlock(); 8017 } 8018 ixgbe_service_event_complete(adapter); 8019 return; 8020 } 8021 if (ixgbe_check_fw_error(adapter)) { 8022 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 8023 unregister_netdev(adapter->netdev); 8024 ixgbe_service_event_complete(adapter); 8025 return; 8026 } 8027 ixgbe_reset_subtask(adapter); 8028 ixgbe_phy_interrupt_subtask(adapter); 8029 ixgbe_sfp_detection_subtask(adapter); 8030 ixgbe_sfp_link_config_subtask(adapter); 8031 ixgbe_check_overtemp_subtask(adapter); 8032 ixgbe_watchdog_subtask(adapter); 8033 ixgbe_fdir_reinit_subtask(adapter); 8034 ixgbe_check_hang_subtask(adapter); 8035 8036 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 8037 ixgbe_ptp_overflow_check(adapter); 8038 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 8039 ixgbe_ptp_rx_hang(adapter); 8040 ixgbe_ptp_tx_hang(adapter); 8041 } 8042 8043 ixgbe_service_event_complete(adapter); 8044 } 8045 8046 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 8047 struct ixgbe_tx_buffer *first, 8048 u8 *hdr_len, 8049 struct ixgbe_ipsec_tx_data *itd) 8050 { 8051 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 8052 struct sk_buff *skb = first->skb; 8053 union { 8054 struct iphdr *v4; 8055 struct ipv6hdr *v6; 8056 unsigned char *hdr; 8057 } ip; 8058 union { 8059 struct tcphdr *tcp; 8060 struct udphdr *udp; 8061 unsigned char *hdr; 8062 } l4; 8063 u32 paylen, l4_offset; 8064 u32 fceof_saidx = 0; 8065 int err; 8066 8067 if (skb->ip_summed != CHECKSUM_PARTIAL) 8068 return 0; 8069 8070 if (!skb_is_gso(skb)) 8071 return 0; 8072 8073 err = skb_cow_head(skb, 0); 8074 if (err < 0) 8075 return err; 8076 8077 if (eth_p_mpls(first->protocol)) 8078 ip.hdr = skb_inner_network_header(skb); 8079 else 8080 ip.hdr = skb_network_header(skb); 8081 l4.hdr = skb_checksum_start(skb); 8082 8083 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 8084 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 8085 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 8086 8087 /* initialize outer IP header fields */ 8088 if (ip.v4->version == 4) { 8089 unsigned char *csum_start = skb_checksum_start(skb); 8090 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 8091 int len = csum_start - trans_start; 8092 8093 /* IP header will have to cancel out any data that 8094 * is not a part of the outer IP header, so set to 8095 * a reverse csum if needed, else init check to 0. 8096 */ 8097 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 8098 csum_fold(csum_partial(trans_start, 8099 len, 0)) : 0; 8100 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 8101 8102 ip.v4->tot_len = 0; 8103 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8104 IXGBE_TX_FLAGS_CSUM | 8105 IXGBE_TX_FLAGS_IPV4; 8106 } else { 8107 ip.v6->payload_len = 0; 8108 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8109 IXGBE_TX_FLAGS_CSUM; 8110 } 8111 8112 /* determine offset of inner transport header */ 8113 l4_offset = l4.hdr - skb->data; 8114 8115 /* remove payload length from inner checksum */ 8116 paylen = skb->len - l4_offset; 8117 8118 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8119 /* compute length of segmentation header */ 8120 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8121 csum_replace_by_diff(&l4.tcp->check, 8122 (__force __wsum)htonl(paylen)); 8123 } else { 8124 /* compute length of segmentation header */ 8125 *hdr_len = sizeof(*l4.udp) + l4_offset; 8126 csum_replace_by_diff(&l4.udp->check, 8127 (__force __wsum)htonl(paylen)); 8128 } 8129 8130 /* update gso size and bytecount with header size */ 8131 first->gso_segs = skb_shinfo(skb)->gso_segs; 8132 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8133 8134 /* mss_l4len_id: use 0 as index for TSO */ 8135 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8136 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8137 8138 fceof_saidx |= itd->sa_idx; 8139 type_tucmd |= itd->flags | itd->trailer_len; 8140 8141 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8142 vlan_macip_lens = l4.hdr - ip.hdr; 8143 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8144 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8145 8146 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8147 mss_l4len_idx); 8148 8149 return 1; 8150 } 8151 8152 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8153 struct ixgbe_tx_buffer *first, 8154 struct ixgbe_ipsec_tx_data *itd) 8155 { 8156 struct sk_buff *skb = first->skb; 8157 u32 vlan_macip_lens = 0; 8158 u32 fceof_saidx = 0; 8159 u32 type_tucmd = 0; 8160 8161 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8162 csum_failed: 8163 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8164 IXGBE_TX_FLAGS_CC))) 8165 return; 8166 goto no_csum; 8167 } 8168 8169 switch (skb->csum_offset) { 8170 case offsetof(struct tcphdr, check): 8171 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8172 fallthrough; 8173 case offsetof(struct udphdr, check): 8174 break; 8175 case offsetof(struct sctphdr, checksum): 8176 /* validate that this is actually an SCTP request */ 8177 if (skb_csum_is_sctp(skb)) { 8178 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8179 break; 8180 } 8181 fallthrough; 8182 default: 8183 skb_checksum_help(skb); 8184 goto csum_failed; 8185 } 8186 8187 /* update TX checksum flag */ 8188 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8189 vlan_macip_lens = skb_checksum_start_offset(skb) - 8190 skb_network_offset(skb); 8191 no_csum: 8192 /* vlan_macip_lens: MACLEN, VLAN tag */ 8193 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8194 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8195 8196 fceof_saidx |= itd->sa_idx; 8197 type_tucmd |= itd->flags | itd->trailer_len; 8198 8199 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8200 } 8201 8202 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8203 ((_flag <= _result) ? \ 8204 ((u32)(_input & _flag) * (_result / _flag)) : \ 8205 ((u32)(_input & _flag) / (_flag / _result))) 8206 8207 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8208 { 8209 /* set type for advanced descriptor with frame checksum insertion */ 8210 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8211 IXGBE_ADVTXD_DCMD_DEXT | 8212 IXGBE_ADVTXD_DCMD_IFCS; 8213 8214 /* set HW vlan bit if vlan is present */ 8215 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8216 IXGBE_ADVTXD_DCMD_VLE); 8217 8218 /* set segmentation enable bits for TSO/FSO */ 8219 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8220 IXGBE_ADVTXD_DCMD_TSE); 8221 8222 /* set timestamp bit if present */ 8223 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8224 IXGBE_ADVTXD_MAC_TSTAMP); 8225 8226 /* insert frame checksum */ 8227 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8228 8229 return cmd_type; 8230 } 8231 8232 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8233 u32 tx_flags, unsigned int paylen) 8234 { 8235 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8236 8237 /* enable L4 checksum for TSO and TX checksum offload */ 8238 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8239 IXGBE_TX_FLAGS_CSUM, 8240 IXGBE_ADVTXD_POPTS_TXSM); 8241 8242 /* enable IPv4 checksum for TSO */ 8243 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8244 IXGBE_TX_FLAGS_IPV4, 8245 IXGBE_ADVTXD_POPTS_IXSM); 8246 8247 /* enable IPsec */ 8248 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8249 IXGBE_TX_FLAGS_IPSEC, 8250 IXGBE_ADVTXD_POPTS_IPSEC); 8251 8252 /* 8253 * Check Context must be set if Tx switch is enabled, which it 8254 * always is for case where virtual functions are running 8255 */ 8256 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8257 IXGBE_TX_FLAGS_CC, 8258 IXGBE_ADVTXD_CC); 8259 8260 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8261 } 8262 8263 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8264 { 8265 if (!netif_subqueue_try_stop(tx_ring->netdev, tx_ring->queue_index, 8266 ixgbe_desc_unused(tx_ring), size)) 8267 return -EBUSY; 8268 8269 ++tx_ring->tx_stats.restart_queue; 8270 return 0; 8271 } 8272 8273 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8274 { 8275 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8276 return 0; 8277 8278 return __ixgbe_maybe_stop_tx(tx_ring, size); 8279 } 8280 8281 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8282 struct ixgbe_tx_buffer *first, 8283 const u8 hdr_len) 8284 { 8285 struct sk_buff *skb = first->skb; 8286 struct ixgbe_tx_buffer *tx_buffer; 8287 union ixgbe_adv_tx_desc *tx_desc; 8288 skb_frag_t *frag; 8289 dma_addr_t dma; 8290 unsigned int data_len, size; 8291 u32 tx_flags = first->tx_flags; 8292 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8293 u16 i = tx_ring->next_to_use; 8294 8295 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8296 8297 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8298 8299 size = skb_headlen(skb); 8300 data_len = skb->data_len; 8301 8302 #ifdef IXGBE_FCOE 8303 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8304 if (data_len < sizeof(struct fcoe_crc_eof)) { 8305 size -= sizeof(struct fcoe_crc_eof) - data_len; 8306 data_len = 0; 8307 } else { 8308 data_len -= sizeof(struct fcoe_crc_eof); 8309 } 8310 } 8311 8312 #endif 8313 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8314 8315 tx_buffer = first; 8316 8317 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8318 if (dma_mapping_error(tx_ring->dev, dma)) 8319 goto dma_error; 8320 8321 /* record length, and DMA address */ 8322 dma_unmap_len_set(tx_buffer, len, size); 8323 dma_unmap_addr_set(tx_buffer, dma, dma); 8324 8325 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8326 8327 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8328 tx_desc->read.cmd_type_len = 8329 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8330 8331 i++; 8332 tx_desc++; 8333 if (i == tx_ring->count) { 8334 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8335 i = 0; 8336 } 8337 tx_desc->read.olinfo_status = 0; 8338 8339 dma += IXGBE_MAX_DATA_PER_TXD; 8340 size -= IXGBE_MAX_DATA_PER_TXD; 8341 8342 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8343 } 8344 8345 if (likely(!data_len)) 8346 break; 8347 8348 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8349 8350 i++; 8351 tx_desc++; 8352 if (i == tx_ring->count) { 8353 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8354 i = 0; 8355 } 8356 tx_desc->read.olinfo_status = 0; 8357 8358 #ifdef IXGBE_FCOE 8359 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8360 #else 8361 size = skb_frag_size(frag); 8362 #endif 8363 data_len -= size; 8364 8365 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8366 DMA_TO_DEVICE); 8367 8368 tx_buffer = &tx_ring->tx_buffer_info[i]; 8369 } 8370 8371 /* write last descriptor with RS and EOP bits */ 8372 cmd_type |= size | IXGBE_TXD_CMD; 8373 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8374 8375 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8376 8377 /* set the timestamp */ 8378 first->time_stamp = jiffies; 8379 8380 skb_tx_timestamp(skb); 8381 8382 /* 8383 * Force memory writes to complete before letting h/w know there 8384 * are new descriptors to fetch. (Only applicable for weak-ordered 8385 * memory model archs, such as IA-64). 8386 * 8387 * We also need this memory barrier to make certain all of the 8388 * status bits have been updated before next_to_watch is written. 8389 */ 8390 wmb(); 8391 8392 /* set next_to_watch value indicating a packet is present */ 8393 first->next_to_watch = tx_desc; 8394 8395 i++; 8396 if (i == tx_ring->count) 8397 i = 0; 8398 8399 tx_ring->next_to_use = i; 8400 8401 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8402 8403 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8404 writel(i, tx_ring->tail); 8405 } 8406 8407 return 0; 8408 dma_error: 8409 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8410 8411 /* clear dma mappings for failed tx_buffer_info map */ 8412 for (;;) { 8413 tx_buffer = &tx_ring->tx_buffer_info[i]; 8414 if (dma_unmap_len(tx_buffer, len)) 8415 dma_unmap_page(tx_ring->dev, 8416 dma_unmap_addr(tx_buffer, dma), 8417 dma_unmap_len(tx_buffer, len), 8418 DMA_TO_DEVICE); 8419 dma_unmap_len_set(tx_buffer, len, 0); 8420 if (tx_buffer == first) 8421 break; 8422 if (i == 0) 8423 i += tx_ring->count; 8424 i--; 8425 } 8426 8427 dev_kfree_skb_any(first->skb); 8428 first->skb = NULL; 8429 8430 tx_ring->next_to_use = i; 8431 8432 return -1; 8433 } 8434 8435 static void ixgbe_atr(struct ixgbe_ring *ring, 8436 struct ixgbe_tx_buffer *first) 8437 { 8438 struct ixgbe_q_vector *q_vector = ring->q_vector; 8439 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8440 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8441 union { 8442 unsigned char *network; 8443 struct iphdr *ipv4; 8444 struct ipv6hdr *ipv6; 8445 } hdr; 8446 struct tcphdr *th; 8447 unsigned int hlen; 8448 struct sk_buff *skb; 8449 __be16 vlan_id; 8450 int l4_proto; 8451 8452 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8453 if (!q_vector) 8454 return; 8455 8456 /* do nothing if sampling is disabled */ 8457 if (!ring->atr_sample_rate) 8458 return; 8459 8460 ring->atr_count++; 8461 8462 /* currently only IPv4/IPv6 with TCP is supported */ 8463 if ((first->protocol != htons(ETH_P_IP)) && 8464 (first->protocol != htons(ETH_P_IPV6))) 8465 return; 8466 8467 /* snag network header to get L4 type and address */ 8468 skb = first->skb; 8469 hdr.network = skb_network_header(skb); 8470 if (unlikely(hdr.network <= skb->data)) 8471 return; 8472 if (skb->encapsulation && 8473 first->protocol == htons(ETH_P_IP) && 8474 hdr.ipv4->protocol == IPPROTO_UDP) { 8475 struct ixgbe_adapter *adapter = q_vector->adapter; 8476 8477 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8478 vxlan_headroom(0))) 8479 return; 8480 8481 /* verify the port is recognized as VXLAN */ 8482 if (adapter->vxlan_port && 8483 udp_hdr(skb)->dest == adapter->vxlan_port) 8484 hdr.network = skb_inner_network_header(skb); 8485 8486 if (adapter->geneve_port && 8487 udp_hdr(skb)->dest == adapter->geneve_port) 8488 hdr.network = skb_inner_network_header(skb); 8489 } 8490 8491 /* Make sure we have at least [minimum IPv4 header + TCP] 8492 * or [IPv6 header] bytes 8493 */ 8494 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8495 return; 8496 8497 /* Currently only IPv4/IPv6 with TCP is supported */ 8498 switch (hdr.ipv4->version) { 8499 case IPVERSION: 8500 /* access ihl as u8 to avoid unaligned access on ia64 */ 8501 hlen = (hdr.network[0] & 0x0F) << 2; 8502 l4_proto = hdr.ipv4->protocol; 8503 break; 8504 case 6: 8505 hlen = hdr.network - skb->data; 8506 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8507 hlen -= hdr.network - skb->data; 8508 break; 8509 default: 8510 return; 8511 } 8512 8513 if (l4_proto != IPPROTO_TCP) 8514 return; 8515 8516 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8517 hlen + sizeof(struct tcphdr))) 8518 return; 8519 8520 th = (struct tcphdr *)(hdr.network + hlen); 8521 8522 /* skip this packet since the socket is closing */ 8523 if (th->fin) 8524 return; 8525 8526 /* sample on all syn packets or once every atr sample count */ 8527 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8528 return; 8529 8530 /* reset sample count */ 8531 ring->atr_count = 0; 8532 8533 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8534 8535 /* 8536 * src and dst are inverted, think how the receiver sees them 8537 * 8538 * The input is broken into two sections, a non-compressed section 8539 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8540 * is XORed together and stored in the compressed dword. 8541 */ 8542 input.formatted.vlan_id = vlan_id; 8543 8544 /* 8545 * since src port and flex bytes occupy the same word XOR them together 8546 * and write the value to source port portion of compressed dword 8547 */ 8548 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8549 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8550 else 8551 common.port.src ^= th->dest ^ first->protocol; 8552 common.port.dst ^= th->source; 8553 8554 switch (hdr.ipv4->version) { 8555 case IPVERSION: 8556 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8557 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8558 break; 8559 case 6: 8560 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8561 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8562 hdr.ipv6->saddr.s6_addr32[1] ^ 8563 hdr.ipv6->saddr.s6_addr32[2] ^ 8564 hdr.ipv6->saddr.s6_addr32[3] ^ 8565 hdr.ipv6->daddr.s6_addr32[0] ^ 8566 hdr.ipv6->daddr.s6_addr32[1] ^ 8567 hdr.ipv6->daddr.s6_addr32[2] ^ 8568 hdr.ipv6->daddr.s6_addr32[3]; 8569 break; 8570 default: 8571 break; 8572 } 8573 8574 if (hdr.network != skb_network_header(skb)) 8575 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8576 8577 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8578 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8579 input, common, ring->queue_index); 8580 } 8581 8582 #ifdef IXGBE_FCOE 8583 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8584 struct net_device *sb_dev) 8585 { 8586 struct ixgbe_adapter *adapter; 8587 struct ixgbe_ring_feature *f; 8588 int txq; 8589 8590 if (sb_dev) { 8591 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8592 struct net_device *vdev = sb_dev; 8593 8594 txq = vdev->tc_to_txq[tc].offset; 8595 txq += reciprocal_scale(skb_get_hash(skb), 8596 vdev->tc_to_txq[tc].count); 8597 8598 return txq; 8599 } 8600 8601 /* 8602 * only execute the code below if protocol is FCoE 8603 * or FIP and we have FCoE enabled on the adapter 8604 */ 8605 switch (vlan_get_protocol(skb)) { 8606 case htons(ETH_P_FCOE): 8607 case htons(ETH_P_FIP): 8608 adapter = netdev_priv(dev); 8609 8610 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8611 break; 8612 fallthrough; 8613 default: 8614 return netdev_pick_tx(dev, skb, sb_dev); 8615 } 8616 8617 f = &adapter->ring_feature[RING_F_FCOE]; 8618 8619 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8620 smp_processor_id(); 8621 8622 while (txq >= f->indices) 8623 txq -= f->indices; 8624 8625 return txq + f->offset; 8626 } 8627 8628 #endif 8629 int ixgbe_xmit_xdp_ring(struct ixgbe_ring *ring, 8630 struct xdp_frame *xdpf) 8631 { 8632 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 8633 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 8634 u16 i = 0, index = ring->next_to_use; 8635 struct ixgbe_tx_buffer *tx_head = &ring->tx_buffer_info[index]; 8636 struct ixgbe_tx_buffer *tx_buff = tx_head; 8637 union ixgbe_adv_tx_desc *tx_desc = IXGBE_TX_DESC(ring, index); 8638 u32 cmd_type, len = xdpf->len; 8639 void *data = xdpf->data; 8640 8641 if (unlikely(ixgbe_desc_unused(ring) < 1 + nr_frags)) 8642 return IXGBE_XDP_CONSUMED; 8643 8644 tx_head->bytecount = xdp_get_frame_len(xdpf); 8645 tx_head->gso_segs = 1; 8646 tx_head->xdpf = xdpf; 8647 8648 tx_desc->read.olinfo_status = 8649 cpu_to_le32(tx_head->bytecount << IXGBE_ADVTXD_PAYLEN_SHIFT); 8650 8651 for (;;) { 8652 dma_addr_t dma; 8653 8654 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 8655 if (dma_mapping_error(ring->dev, dma)) 8656 goto unmap; 8657 8658 dma_unmap_len_set(tx_buff, len, len); 8659 dma_unmap_addr_set(tx_buff, dma, dma); 8660 8661 cmd_type = IXGBE_ADVTXD_DTYP_DATA | IXGBE_ADVTXD_DCMD_DEXT | 8662 IXGBE_ADVTXD_DCMD_IFCS | len; 8663 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8664 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8665 tx_buff->protocol = 0; 8666 8667 if (++index == ring->count) 8668 index = 0; 8669 8670 if (i == nr_frags) 8671 break; 8672 8673 tx_buff = &ring->tx_buffer_info[index]; 8674 tx_desc = IXGBE_TX_DESC(ring, index); 8675 tx_desc->read.olinfo_status = 0; 8676 8677 data = skb_frag_address(&sinfo->frags[i]); 8678 len = skb_frag_size(&sinfo->frags[i]); 8679 i++; 8680 } 8681 /* put descriptor type bits */ 8682 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD); 8683 8684 /* Avoid any potential race with xdp_xmit and cleanup */ 8685 smp_wmb(); 8686 8687 tx_head->next_to_watch = tx_desc; 8688 ring->next_to_use = index; 8689 8690 return IXGBE_XDP_TX; 8691 8692 unmap: 8693 for (;;) { 8694 tx_buff = &ring->tx_buffer_info[index]; 8695 if (dma_unmap_len(tx_buff, len)) 8696 dma_unmap_page(ring->dev, dma_unmap_addr(tx_buff, dma), 8697 dma_unmap_len(tx_buff, len), 8698 DMA_TO_DEVICE); 8699 dma_unmap_len_set(tx_buff, len, 0); 8700 if (tx_buff == tx_head) 8701 break; 8702 8703 if (!index) 8704 index += ring->count; 8705 index--; 8706 } 8707 8708 return IXGBE_XDP_CONSUMED; 8709 } 8710 8711 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8712 struct ixgbe_adapter *adapter, 8713 struct ixgbe_ring *tx_ring) 8714 { 8715 struct ixgbe_tx_buffer *first; 8716 int tso; 8717 u32 tx_flags = 0; 8718 unsigned short f; 8719 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8720 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8721 __be16 protocol = skb->protocol; 8722 u8 hdr_len = 0; 8723 8724 /* 8725 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8726 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8727 * + 2 desc gap to keep tail from touching head, 8728 * + 1 desc for context descriptor, 8729 * otherwise try next time 8730 */ 8731 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8732 count += TXD_USE_COUNT(skb_frag_size( 8733 &skb_shinfo(skb)->frags[f])); 8734 8735 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8736 tx_ring->tx_stats.tx_busy++; 8737 return NETDEV_TX_BUSY; 8738 } 8739 8740 /* record the location of the first descriptor for this packet */ 8741 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8742 first->skb = skb; 8743 first->bytecount = skb->len; 8744 first->gso_segs = 1; 8745 8746 /* if we have a HW VLAN tag being added default to the HW one */ 8747 if (skb_vlan_tag_present(skb)) { 8748 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8749 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8750 /* else if it is a SW VLAN check the next protocol and store the tag */ 8751 } else if (protocol == htons(ETH_P_8021Q)) { 8752 struct vlan_hdr *vhdr, _vhdr; 8753 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8754 if (!vhdr) 8755 goto out_drop; 8756 8757 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8758 IXGBE_TX_FLAGS_VLAN_SHIFT; 8759 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8760 } 8761 protocol = vlan_get_protocol(skb); 8762 8763 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8764 adapter->ptp_clock) { 8765 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 8766 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8767 &adapter->state)) { 8768 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8769 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8770 8771 /* schedule check for Tx timestamp */ 8772 adapter->ptp_tx_skb = skb_get(skb); 8773 adapter->ptp_tx_start = jiffies; 8774 schedule_work(&adapter->ptp_tx_work); 8775 } else { 8776 adapter->tx_hwtstamp_skipped++; 8777 } 8778 } 8779 8780 #ifdef CONFIG_PCI_IOV 8781 /* 8782 * Use the l2switch_enable flag - would be false if the DMA 8783 * Tx switch had been disabled. 8784 */ 8785 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8786 tx_flags |= IXGBE_TX_FLAGS_CC; 8787 8788 #endif 8789 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8790 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8791 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8792 (skb->priority != TC_PRIO_CONTROL))) { 8793 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8794 tx_flags |= (skb->priority & 0x7) << 8795 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8796 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8797 struct vlan_ethhdr *vhdr; 8798 8799 if (skb_cow_head(skb, 0)) 8800 goto out_drop; 8801 vhdr = skb_vlan_eth_hdr(skb); 8802 vhdr->h_vlan_TCI = htons(tx_flags >> 8803 IXGBE_TX_FLAGS_VLAN_SHIFT); 8804 } else { 8805 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8806 } 8807 } 8808 8809 /* record initial flags and protocol */ 8810 first->tx_flags = tx_flags; 8811 first->protocol = protocol; 8812 8813 #ifdef IXGBE_FCOE 8814 /* setup tx offload for FCoE */ 8815 if ((protocol == htons(ETH_P_FCOE)) && 8816 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8817 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8818 if (tso < 0) 8819 goto out_drop; 8820 8821 goto xmit_fcoe; 8822 } 8823 8824 #endif /* IXGBE_FCOE */ 8825 8826 #ifdef CONFIG_IXGBE_IPSEC 8827 if (xfrm_offload(skb) && 8828 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8829 goto out_drop; 8830 #endif 8831 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8832 if (tso < 0) 8833 goto out_drop; 8834 else if (!tso) 8835 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8836 8837 /* add the ATR filter if ATR is on */ 8838 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8839 ixgbe_atr(tx_ring, first); 8840 8841 #ifdef IXGBE_FCOE 8842 xmit_fcoe: 8843 #endif /* IXGBE_FCOE */ 8844 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8845 goto cleanup_tx_timestamp; 8846 8847 return NETDEV_TX_OK; 8848 8849 out_drop: 8850 dev_kfree_skb_any(first->skb); 8851 first->skb = NULL; 8852 cleanup_tx_timestamp: 8853 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8854 dev_kfree_skb_any(adapter->ptp_tx_skb); 8855 adapter->ptp_tx_skb = NULL; 8856 cancel_work_sync(&adapter->ptp_tx_work); 8857 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8858 } 8859 8860 return NETDEV_TX_OK; 8861 } 8862 8863 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8864 struct net_device *netdev, 8865 struct ixgbe_ring *ring) 8866 { 8867 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8868 struct ixgbe_ring *tx_ring; 8869 8870 /* 8871 * The minimum packet size for olinfo paylen is 17 so pad the skb 8872 * in order to meet this minimum size requirement. 8873 */ 8874 if (skb_put_padto(skb, 17)) 8875 return NETDEV_TX_OK; 8876 8877 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 8878 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8879 return NETDEV_TX_BUSY; 8880 8881 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8882 } 8883 8884 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8885 struct net_device *netdev) 8886 { 8887 return __ixgbe_xmit_frame(skb, netdev, NULL); 8888 } 8889 8890 /** 8891 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8892 * @netdev: network interface device structure 8893 * @p: pointer to an address structure 8894 * 8895 * Returns 0 on success, negative on failure 8896 **/ 8897 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8898 { 8899 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8900 struct ixgbe_hw *hw = &adapter->hw; 8901 struct sockaddr *addr = p; 8902 8903 if (!is_valid_ether_addr(addr->sa_data)) 8904 return -EADDRNOTAVAIL; 8905 8906 eth_hw_addr_set(netdev, addr->sa_data); 8907 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8908 8909 ixgbe_mac_set_default_filter(adapter); 8910 8911 return 0; 8912 } 8913 8914 static int 8915 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8916 { 8917 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8918 struct ixgbe_hw *hw = &adapter->hw; 8919 u16 value; 8920 int rc; 8921 8922 if (adapter->mii_bus) { 8923 int regnum = addr; 8924 8925 if (devad != MDIO_DEVAD_NONE) 8926 return mdiobus_c45_read(adapter->mii_bus, prtad, 8927 devad, regnum); 8928 8929 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8930 } 8931 8932 if (prtad != hw->phy.mdio.prtad) 8933 return -EINVAL; 8934 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8935 if (!rc) 8936 rc = value; 8937 return rc; 8938 } 8939 8940 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8941 u16 addr, u16 value) 8942 { 8943 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8944 struct ixgbe_hw *hw = &adapter->hw; 8945 8946 if (adapter->mii_bus) { 8947 int regnum = addr; 8948 8949 if (devad != MDIO_DEVAD_NONE) 8950 return mdiobus_c45_write(adapter->mii_bus, prtad, devad, 8951 regnum, value); 8952 8953 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8954 } 8955 8956 if (prtad != hw->phy.mdio.prtad) 8957 return -EINVAL; 8958 return hw->phy.ops.write_reg(hw, addr, devad, value); 8959 } 8960 8961 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8962 { 8963 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8964 8965 switch (cmd) { 8966 case SIOCSHWTSTAMP: 8967 return ixgbe_ptp_set_ts_config(adapter, req); 8968 case SIOCGHWTSTAMP: 8969 return ixgbe_ptp_get_ts_config(adapter, req); 8970 case SIOCGMIIPHY: 8971 if (!adapter->hw.phy.ops.read_reg) 8972 return -EOPNOTSUPP; 8973 fallthrough; 8974 default: 8975 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8976 } 8977 } 8978 8979 /** 8980 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8981 * netdev->dev_addrs 8982 * @dev: network interface device structure 8983 * 8984 * Returns non-zero on failure 8985 **/ 8986 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8987 { 8988 int err = 0; 8989 struct ixgbe_adapter *adapter = netdev_priv(dev); 8990 struct ixgbe_hw *hw = &adapter->hw; 8991 8992 if (is_valid_ether_addr(hw->mac.san_addr)) { 8993 rtnl_lock(); 8994 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8995 rtnl_unlock(); 8996 8997 /* update SAN MAC vmdq pool selection */ 8998 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8999 } 9000 return err; 9001 } 9002 9003 /** 9004 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 9005 * netdev->dev_addrs 9006 * @dev: network interface device structure 9007 * 9008 * Returns non-zero on failure 9009 **/ 9010 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 9011 { 9012 int err = 0; 9013 struct ixgbe_adapter *adapter = netdev_priv(dev); 9014 struct ixgbe_mac_info *mac = &adapter->hw.mac; 9015 9016 if (is_valid_ether_addr(mac->san_addr)) { 9017 rtnl_lock(); 9018 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 9019 rtnl_unlock(); 9020 } 9021 return err; 9022 } 9023 9024 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 9025 struct ixgbe_ring *ring) 9026 { 9027 u64 bytes, packets; 9028 unsigned int start; 9029 9030 if (ring) { 9031 do { 9032 start = u64_stats_fetch_begin(&ring->syncp); 9033 packets = ring->stats.packets; 9034 bytes = ring->stats.bytes; 9035 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9036 stats->tx_packets += packets; 9037 stats->tx_bytes += bytes; 9038 } 9039 } 9040 9041 static void ixgbe_get_stats64(struct net_device *netdev, 9042 struct rtnl_link_stats64 *stats) 9043 { 9044 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9045 int i; 9046 9047 rcu_read_lock(); 9048 for (i = 0; i < adapter->num_rx_queues; i++) { 9049 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 9050 u64 bytes, packets; 9051 unsigned int start; 9052 9053 if (ring) { 9054 do { 9055 start = u64_stats_fetch_begin(&ring->syncp); 9056 packets = ring->stats.packets; 9057 bytes = ring->stats.bytes; 9058 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9059 stats->rx_packets += packets; 9060 stats->rx_bytes += bytes; 9061 } 9062 } 9063 9064 for (i = 0; i < adapter->num_tx_queues; i++) { 9065 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 9066 9067 ixgbe_get_ring_stats64(stats, ring); 9068 } 9069 for (i = 0; i < adapter->num_xdp_queues; i++) { 9070 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 9071 9072 ixgbe_get_ring_stats64(stats, ring); 9073 } 9074 rcu_read_unlock(); 9075 9076 /* following stats updated by ixgbe_watchdog_task() */ 9077 stats->multicast = netdev->stats.multicast; 9078 stats->rx_errors = netdev->stats.rx_errors; 9079 stats->rx_length_errors = netdev->stats.rx_length_errors; 9080 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 9081 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 9082 } 9083 9084 static int ixgbe_ndo_get_vf_stats(struct net_device *netdev, int vf, 9085 struct ifla_vf_stats *vf_stats) 9086 { 9087 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9088 9089 if (vf < 0 || vf >= adapter->num_vfs) 9090 return -EINVAL; 9091 9092 vf_stats->rx_packets = adapter->vfinfo[vf].vfstats.gprc; 9093 vf_stats->rx_bytes = adapter->vfinfo[vf].vfstats.gorc; 9094 vf_stats->tx_packets = adapter->vfinfo[vf].vfstats.gptc; 9095 vf_stats->tx_bytes = adapter->vfinfo[vf].vfstats.gotc; 9096 vf_stats->multicast = adapter->vfinfo[vf].vfstats.mprc; 9097 9098 return 0; 9099 } 9100 9101 #ifdef CONFIG_IXGBE_DCB 9102 /** 9103 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 9104 * @adapter: pointer to ixgbe_adapter 9105 * @tc: number of traffic classes currently enabled 9106 * 9107 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 9108 * 802.1Q priority maps to a packet buffer that exists. 9109 */ 9110 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 9111 { 9112 struct ixgbe_hw *hw = &adapter->hw; 9113 u32 reg, rsave; 9114 int i; 9115 9116 /* 82598 have a static priority to TC mapping that can not 9117 * be changed so no validation is needed. 9118 */ 9119 if (hw->mac.type == ixgbe_mac_82598EB) 9120 return; 9121 9122 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 9123 rsave = reg; 9124 9125 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 9126 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 9127 9128 /* If up2tc is out of bounds default to zero */ 9129 if (up2tc > tc) 9130 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9131 } 9132 9133 if (reg != rsave) 9134 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9135 9136 return; 9137 } 9138 9139 /** 9140 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9141 * @adapter: Pointer to adapter struct 9142 * 9143 * Populate the netdev user priority to tc map 9144 */ 9145 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9146 { 9147 struct net_device *dev = adapter->netdev; 9148 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9149 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9150 u8 prio; 9151 9152 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9153 u8 tc = 0; 9154 9155 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9156 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9157 else if (ets) 9158 tc = ets->prio_tc[prio]; 9159 9160 netdev_set_prio_tc_map(dev, prio, tc); 9161 } 9162 } 9163 9164 #endif /* CONFIG_IXGBE_DCB */ 9165 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9166 struct netdev_nested_priv *priv) 9167 { 9168 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9169 struct ixgbe_fwd_adapter *accel; 9170 int pool; 9171 9172 /* we only care about macvlans... */ 9173 if (!netif_is_macvlan(vdev)) 9174 return 0; 9175 9176 /* that have hardware offload enabled... */ 9177 accel = macvlan_accel_priv(vdev); 9178 if (!accel) 9179 return 0; 9180 9181 /* If we can relocate to a different bit do so */ 9182 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9183 if (pool < adapter->num_rx_pools) { 9184 set_bit(pool, adapter->fwd_bitmask); 9185 accel->pool = pool; 9186 return 0; 9187 } 9188 9189 /* if we cannot find a free pool then disable the offload */ 9190 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9191 macvlan_release_l2fw_offload(vdev); 9192 9193 /* unbind the queues and drop the subordinate channel config */ 9194 netdev_unbind_sb_channel(adapter->netdev, vdev); 9195 netdev_set_sb_channel(vdev, 0); 9196 9197 kfree(accel); 9198 9199 return 0; 9200 } 9201 9202 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9203 { 9204 struct ixgbe_adapter *adapter = netdev_priv(dev); 9205 struct netdev_nested_priv priv = { 9206 .data = (void *)adapter, 9207 }; 9208 9209 /* flush any stale bits out of the fwd bitmask */ 9210 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9211 9212 /* walk through upper devices reassigning pools */ 9213 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9214 &priv); 9215 } 9216 9217 /** 9218 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9219 * 9220 * @dev: net device to configure 9221 * @tc: number of traffic classes to enable 9222 */ 9223 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9224 { 9225 struct ixgbe_adapter *adapter = netdev_priv(dev); 9226 struct ixgbe_hw *hw = &adapter->hw; 9227 9228 /* Hardware supports up to 8 traffic classes */ 9229 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9230 return -EINVAL; 9231 9232 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9233 return -EINVAL; 9234 9235 /* Hardware has to reinitialize queues and interrupts to 9236 * match packet buffer alignment. Unfortunately, the 9237 * hardware is not flexible enough to do this dynamically. 9238 */ 9239 if (netif_running(dev)) 9240 ixgbe_close(dev); 9241 else 9242 ixgbe_reset(adapter); 9243 9244 ixgbe_clear_interrupt_scheme(adapter); 9245 9246 #ifdef CONFIG_IXGBE_DCB 9247 if (tc) { 9248 if (adapter->xdp_prog) { 9249 e_warn(probe, "DCB is not supported with XDP\n"); 9250 9251 ixgbe_init_interrupt_scheme(adapter); 9252 if (netif_running(dev)) 9253 ixgbe_open(dev); 9254 return -EINVAL; 9255 } 9256 9257 netdev_set_num_tc(dev, tc); 9258 ixgbe_set_prio_tc_map(adapter); 9259 9260 adapter->hw_tcs = tc; 9261 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9262 9263 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9264 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9265 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9266 } 9267 } else { 9268 netdev_reset_tc(dev); 9269 9270 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9271 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9272 9273 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9274 adapter->hw_tcs = tc; 9275 9276 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9277 adapter->dcb_cfg.pfc_mode_enable = false; 9278 } 9279 9280 ixgbe_validate_rtr(adapter, tc); 9281 9282 #endif /* CONFIG_IXGBE_DCB */ 9283 ixgbe_init_interrupt_scheme(adapter); 9284 9285 ixgbe_defrag_macvlan_pools(dev); 9286 9287 if (netif_running(dev)) 9288 return ixgbe_open(dev); 9289 9290 return 0; 9291 } 9292 9293 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9294 struct tc_cls_u32_offload *cls) 9295 { 9296 u32 hdl = cls->knode.handle; 9297 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9298 u32 loc = cls->knode.handle & 0xfffff; 9299 int err = 0, i, j; 9300 struct ixgbe_jump_table *jump = NULL; 9301 9302 if (loc > IXGBE_MAX_HW_ENTRIES) 9303 return -EINVAL; 9304 9305 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9306 return -EINVAL; 9307 9308 /* Clear this filter in the link data it is associated with */ 9309 if (uhtid != 0x800) { 9310 jump = adapter->jump_tables[uhtid]; 9311 if (!jump) 9312 return -EINVAL; 9313 if (!test_bit(loc - 1, jump->child_loc_map)) 9314 return -EINVAL; 9315 clear_bit(loc - 1, jump->child_loc_map); 9316 } 9317 9318 /* Check if the filter being deleted is a link */ 9319 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9320 jump = adapter->jump_tables[i]; 9321 if (jump && jump->link_hdl == hdl) { 9322 /* Delete filters in the hardware in the child hash 9323 * table associated with this link 9324 */ 9325 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9326 if (!test_bit(j, jump->child_loc_map)) 9327 continue; 9328 spin_lock(&adapter->fdir_perfect_lock); 9329 err = ixgbe_update_ethtool_fdir_entry(adapter, 9330 NULL, 9331 j + 1); 9332 spin_unlock(&adapter->fdir_perfect_lock); 9333 clear_bit(j, jump->child_loc_map); 9334 } 9335 /* Remove resources for this link */ 9336 kfree(jump->input); 9337 kfree(jump->mask); 9338 kfree(jump); 9339 adapter->jump_tables[i] = NULL; 9340 return err; 9341 } 9342 } 9343 9344 spin_lock(&adapter->fdir_perfect_lock); 9345 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9346 spin_unlock(&adapter->fdir_perfect_lock); 9347 return err; 9348 } 9349 9350 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9351 struct tc_cls_u32_offload *cls) 9352 { 9353 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9354 9355 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9356 return -EINVAL; 9357 9358 /* This ixgbe devices do not support hash tables at the moment 9359 * so abort when given hash tables. 9360 */ 9361 if (cls->hnode.divisor > 0) 9362 return -EINVAL; 9363 9364 set_bit(uhtid - 1, &adapter->tables); 9365 return 0; 9366 } 9367 9368 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9369 struct tc_cls_u32_offload *cls) 9370 { 9371 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9372 9373 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9374 return -EINVAL; 9375 9376 clear_bit(uhtid - 1, &adapter->tables); 9377 return 0; 9378 } 9379 9380 #ifdef CONFIG_NET_CLS_ACT 9381 struct upper_walk_data { 9382 struct ixgbe_adapter *adapter; 9383 u64 action; 9384 int ifindex; 9385 u8 queue; 9386 }; 9387 9388 static int get_macvlan_queue(struct net_device *upper, 9389 struct netdev_nested_priv *priv) 9390 { 9391 if (netif_is_macvlan(upper)) { 9392 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9393 struct ixgbe_adapter *adapter; 9394 struct upper_walk_data *data; 9395 int ifindex; 9396 9397 data = (struct upper_walk_data *)priv->data; 9398 ifindex = data->ifindex; 9399 adapter = data->adapter; 9400 if (vadapter && upper->ifindex == ifindex) { 9401 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9402 data->action = data->queue; 9403 return 1; 9404 } 9405 } 9406 9407 return 0; 9408 } 9409 9410 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9411 u8 *queue, u64 *action) 9412 { 9413 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9414 unsigned int num_vfs = adapter->num_vfs, vf; 9415 struct netdev_nested_priv priv; 9416 struct upper_walk_data data; 9417 struct net_device *upper; 9418 9419 /* redirect to a SRIOV VF */ 9420 for (vf = 0; vf < num_vfs; ++vf) { 9421 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9422 if (upper->ifindex == ifindex) { 9423 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9424 *action = vf + 1; 9425 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9426 return 0; 9427 } 9428 } 9429 9430 /* redirect to a offloaded macvlan netdev */ 9431 data.adapter = adapter; 9432 data.ifindex = ifindex; 9433 data.action = 0; 9434 data.queue = 0; 9435 priv.data = (void *)&data; 9436 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9437 get_macvlan_queue, &priv)) { 9438 *action = data.action; 9439 *queue = data.queue; 9440 9441 return 0; 9442 } 9443 9444 return -EINVAL; 9445 } 9446 9447 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9448 struct tcf_exts *exts, u64 *action, u8 *queue) 9449 { 9450 const struct tc_action *a; 9451 int i; 9452 9453 if (!tcf_exts_has_actions(exts)) 9454 return -EINVAL; 9455 9456 tcf_exts_for_each_action(i, a, exts) { 9457 /* Drop action */ 9458 if (is_tcf_gact_shot(a)) { 9459 *action = IXGBE_FDIR_DROP_QUEUE; 9460 *queue = IXGBE_FDIR_DROP_QUEUE; 9461 return 0; 9462 } 9463 9464 /* Redirect to a VF or a offloaded macvlan */ 9465 if (is_tcf_mirred_egress_redirect(a)) { 9466 struct net_device *dev = tcf_mirred_dev(a); 9467 9468 if (!dev) 9469 return -EINVAL; 9470 return handle_redirect_action(adapter, dev->ifindex, 9471 queue, action); 9472 } 9473 9474 return -EINVAL; 9475 } 9476 9477 return -EINVAL; 9478 } 9479 #else 9480 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9481 struct tcf_exts *exts, u64 *action, u8 *queue) 9482 { 9483 return -EINVAL; 9484 } 9485 #endif /* CONFIG_NET_CLS_ACT */ 9486 9487 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9488 union ixgbe_atr_input *mask, 9489 struct tc_cls_u32_offload *cls, 9490 struct ixgbe_mat_field *field_ptr, 9491 struct ixgbe_nexthdr *nexthdr) 9492 { 9493 int i, j, off; 9494 __be32 val, m; 9495 bool found_entry = false, found_jump_field = false; 9496 9497 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9498 off = cls->knode.sel->keys[i].off; 9499 val = cls->knode.sel->keys[i].val; 9500 m = cls->knode.sel->keys[i].mask; 9501 9502 for (j = 0; field_ptr[j].val; j++) { 9503 if (field_ptr[j].off == off) { 9504 field_ptr[j].val(input, mask, (__force u32)val, 9505 (__force u32)m); 9506 input->filter.formatted.flow_type |= 9507 field_ptr[j].type; 9508 found_entry = true; 9509 break; 9510 } 9511 } 9512 if (nexthdr) { 9513 if (nexthdr->off == cls->knode.sel->keys[i].off && 9514 nexthdr->val == 9515 (__force u32)cls->knode.sel->keys[i].val && 9516 nexthdr->mask == 9517 (__force u32)cls->knode.sel->keys[i].mask) 9518 found_jump_field = true; 9519 else 9520 continue; 9521 } 9522 } 9523 9524 if (nexthdr && !found_jump_field) 9525 return -EINVAL; 9526 9527 if (!found_entry) 9528 return 0; 9529 9530 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9531 IXGBE_ATR_L4TYPE_MASK; 9532 9533 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9534 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9535 9536 return 0; 9537 } 9538 9539 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9540 struct tc_cls_u32_offload *cls) 9541 { 9542 __be16 protocol = cls->common.protocol; 9543 u32 loc = cls->knode.handle & 0xfffff; 9544 struct ixgbe_hw *hw = &adapter->hw; 9545 struct ixgbe_mat_field *field_ptr; 9546 struct ixgbe_fdir_filter *input = NULL; 9547 union ixgbe_atr_input *mask = NULL; 9548 struct ixgbe_jump_table *jump = NULL; 9549 int i, err = -EINVAL; 9550 u8 queue; 9551 u32 uhtid, link_uhtid; 9552 9553 uhtid = TC_U32_USERHTID(cls->knode.handle); 9554 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9555 9556 /* At the moment cls_u32 jumps to network layer and skips past 9557 * L2 headers. The canonical method to match L2 frames is to use 9558 * negative values. However this is error prone at best but really 9559 * just broken because there is no way to "know" what sort of hdr 9560 * is in front of the network layer. Fix cls_u32 to support L2 9561 * headers when needed. 9562 */ 9563 if (protocol != htons(ETH_P_IP)) 9564 return err; 9565 9566 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9567 e_err(drv, "Location out of range\n"); 9568 return err; 9569 } 9570 9571 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9572 * links and also the fields used to advance the parser across each 9573 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9574 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9575 * To add support for new nodes update ixgbe_model.h parse structures 9576 * this function _should_ be generic try not to hardcode values here. 9577 */ 9578 if (uhtid == 0x800) { 9579 field_ptr = (adapter->jump_tables[0])->mat; 9580 } else { 9581 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9582 return err; 9583 if (!adapter->jump_tables[uhtid]) 9584 return err; 9585 field_ptr = (adapter->jump_tables[uhtid])->mat; 9586 } 9587 9588 if (!field_ptr) 9589 return err; 9590 9591 /* At this point we know the field_ptr is valid and need to either 9592 * build cls_u32 link or attach filter. Because adding a link to 9593 * a handle that does not exist is invalid and the same for adding 9594 * rules to handles that don't exist. 9595 */ 9596 9597 if (link_uhtid) { 9598 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9599 9600 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9601 return err; 9602 9603 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9604 return err; 9605 9606 /* Multiple filters as links to the same hash table are not 9607 * supported. To add a new filter with the same next header 9608 * but different match/jump conditions, create a new hash table 9609 * and link to it. 9610 */ 9611 if (adapter->jump_tables[link_uhtid] && 9612 (adapter->jump_tables[link_uhtid])->link_hdl) { 9613 e_err(drv, "Link filter exists for link: %x\n", 9614 link_uhtid); 9615 return err; 9616 } 9617 9618 for (i = 0; nexthdr[i].jump; i++) { 9619 if (nexthdr[i].o != cls->knode.sel->offoff || 9620 nexthdr[i].s != cls->knode.sel->offshift || 9621 nexthdr[i].m != 9622 (__force u32)cls->knode.sel->offmask) 9623 return err; 9624 9625 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9626 if (!jump) 9627 return -ENOMEM; 9628 input = kzalloc(sizeof(*input), GFP_KERNEL); 9629 if (!input) { 9630 err = -ENOMEM; 9631 goto free_jump; 9632 } 9633 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9634 if (!mask) { 9635 err = -ENOMEM; 9636 goto free_input; 9637 } 9638 jump->input = input; 9639 jump->mask = mask; 9640 jump->link_hdl = cls->knode.handle; 9641 9642 err = ixgbe_clsu32_build_input(input, mask, cls, 9643 field_ptr, &nexthdr[i]); 9644 if (!err) { 9645 jump->mat = nexthdr[i].jump; 9646 adapter->jump_tables[link_uhtid] = jump; 9647 break; 9648 } else { 9649 kfree(mask); 9650 kfree(input); 9651 kfree(jump); 9652 } 9653 } 9654 return 0; 9655 } 9656 9657 input = kzalloc(sizeof(*input), GFP_KERNEL); 9658 if (!input) 9659 return -ENOMEM; 9660 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9661 if (!mask) { 9662 err = -ENOMEM; 9663 goto free_input; 9664 } 9665 9666 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9667 if ((adapter->jump_tables[uhtid])->input) 9668 memcpy(input, (adapter->jump_tables[uhtid])->input, 9669 sizeof(*input)); 9670 if ((adapter->jump_tables[uhtid])->mask) 9671 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9672 sizeof(*mask)); 9673 9674 /* Lookup in all child hash tables if this location is already 9675 * filled with a filter 9676 */ 9677 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9678 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9679 9680 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9681 e_err(drv, "Filter exists in location: %x\n", 9682 loc); 9683 err = -EINVAL; 9684 goto err_out; 9685 } 9686 } 9687 } 9688 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9689 if (err) 9690 goto err_out; 9691 9692 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9693 &queue); 9694 if (err < 0) 9695 goto err_out; 9696 9697 input->sw_idx = loc; 9698 9699 spin_lock(&adapter->fdir_perfect_lock); 9700 9701 if (hlist_empty(&adapter->fdir_filter_list)) { 9702 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9703 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9704 if (err) 9705 goto err_out_w_lock; 9706 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9707 err = -EINVAL; 9708 goto err_out_w_lock; 9709 } 9710 9711 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9712 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9713 input->sw_idx, queue); 9714 if (err) 9715 goto err_out_w_lock; 9716 9717 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9718 spin_unlock(&adapter->fdir_perfect_lock); 9719 9720 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9721 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9722 9723 kfree(mask); 9724 return err; 9725 err_out_w_lock: 9726 spin_unlock(&adapter->fdir_perfect_lock); 9727 err_out: 9728 kfree(mask); 9729 free_input: 9730 kfree(input); 9731 free_jump: 9732 kfree(jump); 9733 return err; 9734 } 9735 9736 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9737 struct tc_cls_u32_offload *cls_u32) 9738 { 9739 switch (cls_u32->command) { 9740 case TC_CLSU32_NEW_KNODE: 9741 case TC_CLSU32_REPLACE_KNODE: 9742 return ixgbe_configure_clsu32(adapter, cls_u32); 9743 case TC_CLSU32_DELETE_KNODE: 9744 return ixgbe_delete_clsu32(adapter, cls_u32); 9745 case TC_CLSU32_NEW_HNODE: 9746 case TC_CLSU32_REPLACE_HNODE: 9747 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9748 case TC_CLSU32_DELETE_HNODE: 9749 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9750 default: 9751 return -EOPNOTSUPP; 9752 } 9753 } 9754 9755 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9756 void *cb_priv) 9757 { 9758 struct ixgbe_adapter *adapter = cb_priv; 9759 9760 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9761 return -EOPNOTSUPP; 9762 9763 switch (type) { 9764 case TC_SETUP_CLSU32: 9765 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9766 default: 9767 return -EOPNOTSUPP; 9768 } 9769 } 9770 9771 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9772 struct tc_mqprio_qopt *mqprio) 9773 { 9774 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9775 return ixgbe_setup_tc(dev, mqprio->num_tc); 9776 } 9777 9778 static LIST_HEAD(ixgbe_block_cb_list); 9779 9780 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9781 void *type_data) 9782 { 9783 struct ixgbe_adapter *adapter = netdev_priv(dev); 9784 9785 switch (type) { 9786 case TC_SETUP_BLOCK: 9787 return flow_block_cb_setup_simple(type_data, 9788 &ixgbe_block_cb_list, 9789 ixgbe_setup_tc_block_cb, 9790 adapter, adapter, true); 9791 case TC_SETUP_QDISC_MQPRIO: 9792 return ixgbe_setup_tc_mqprio(dev, type_data); 9793 default: 9794 return -EOPNOTSUPP; 9795 } 9796 } 9797 9798 #ifdef CONFIG_PCI_IOV 9799 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9800 { 9801 struct net_device *netdev = adapter->netdev; 9802 9803 rtnl_lock(); 9804 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9805 rtnl_unlock(); 9806 } 9807 9808 #endif 9809 void ixgbe_do_reset(struct net_device *netdev) 9810 { 9811 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9812 9813 if (netif_running(netdev)) 9814 ixgbe_reinit_locked(adapter); 9815 else 9816 ixgbe_reset(adapter); 9817 } 9818 9819 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9820 netdev_features_t features) 9821 { 9822 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9823 9824 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9825 if (!(features & NETIF_F_RXCSUM)) 9826 features &= ~NETIF_F_LRO; 9827 9828 /* Turn off LRO if not RSC capable */ 9829 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9830 features &= ~NETIF_F_LRO; 9831 9832 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9833 e_dev_err("LRO is not supported with XDP\n"); 9834 features &= ~NETIF_F_LRO; 9835 } 9836 9837 return features; 9838 } 9839 9840 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9841 { 9842 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9843 num_online_cpus()); 9844 9845 /* go back to full RSS if we're not running SR-IOV */ 9846 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9847 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9848 IXGBE_FLAG_SRIOV_ENABLED); 9849 9850 adapter->ring_feature[RING_F_RSS].limit = rss; 9851 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9852 9853 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9854 } 9855 9856 static int ixgbe_set_features(struct net_device *netdev, 9857 netdev_features_t features) 9858 { 9859 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9860 netdev_features_t changed = netdev->features ^ features; 9861 bool need_reset = false; 9862 9863 /* Make sure RSC matches LRO, reset if change */ 9864 if (!(features & NETIF_F_LRO)) { 9865 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9866 need_reset = true; 9867 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9868 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9869 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9870 if (adapter->rx_itr_setting == 1 || 9871 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9872 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9873 need_reset = true; 9874 } else if ((changed ^ features) & NETIF_F_LRO) { 9875 e_info(probe, "rx-usecs set too low, " 9876 "disabling RSC\n"); 9877 } 9878 } 9879 9880 /* 9881 * Check if Flow Director n-tuple support or hw_tc support was 9882 * enabled or disabled. If the state changed, we need to reset. 9883 */ 9884 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9885 /* turn off ATR, enable perfect filters and reset */ 9886 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9887 need_reset = true; 9888 9889 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9890 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9891 } else { 9892 /* turn off perfect filters, enable ATR and reset */ 9893 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9894 need_reset = true; 9895 9896 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9897 9898 /* We cannot enable ATR if SR-IOV is enabled */ 9899 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9900 /* We cannot enable ATR if we have 2 or more tcs */ 9901 (adapter->hw_tcs > 1) || 9902 /* We cannot enable ATR if RSS is disabled */ 9903 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9904 /* A sample rate of 0 indicates ATR disabled */ 9905 (!adapter->atr_sample_rate)) 9906 ; /* do nothing not supported */ 9907 else /* otherwise supported and set the flag */ 9908 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9909 } 9910 9911 if (changed & NETIF_F_RXALL) 9912 need_reset = true; 9913 9914 netdev->features = features; 9915 9916 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9917 ixgbe_reset_l2fw_offload(adapter); 9918 else if (need_reset) 9919 ixgbe_do_reset(netdev); 9920 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9921 NETIF_F_HW_VLAN_CTAG_FILTER)) 9922 ixgbe_set_rx_mode(netdev); 9923 9924 return 1; 9925 } 9926 9927 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9928 struct net_device *dev, 9929 const unsigned char *addr, u16 vid, 9930 u16 flags, 9931 struct netlink_ext_ack *extack) 9932 { 9933 /* guarantee we can provide a unique filter for the unicast address */ 9934 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9935 struct ixgbe_adapter *adapter = netdev_priv(dev); 9936 u16 pool = VMDQ_P(0); 9937 9938 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9939 return -ENOMEM; 9940 } 9941 9942 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9943 } 9944 9945 /** 9946 * ixgbe_configure_bridge_mode - set various bridge modes 9947 * @adapter: the private structure 9948 * @mode: requested bridge mode 9949 * 9950 * Configure some settings require for various bridge modes. 9951 **/ 9952 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9953 __u16 mode) 9954 { 9955 struct ixgbe_hw *hw = &adapter->hw; 9956 unsigned int p, num_pools; 9957 u32 vmdctl; 9958 9959 switch (mode) { 9960 case BRIDGE_MODE_VEPA: 9961 /* disable Tx loopback, rely on switch hairpin mode */ 9962 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9963 9964 /* must enable Rx switching replication to allow multicast 9965 * packet reception on all VFs, and to enable source address 9966 * pruning. 9967 */ 9968 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9969 vmdctl |= IXGBE_VT_CTL_REPLEN; 9970 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9971 9972 /* enable Rx source address pruning. Note, this requires 9973 * replication to be enabled or else it does nothing. 9974 */ 9975 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9976 for (p = 0; p < num_pools; p++) { 9977 if (hw->mac.ops.set_source_address_pruning) 9978 hw->mac.ops.set_source_address_pruning(hw, 9979 true, 9980 p); 9981 } 9982 break; 9983 case BRIDGE_MODE_VEB: 9984 /* enable Tx loopback for internal VF/PF communication */ 9985 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9986 IXGBE_PFDTXGSWC_VT_LBEN); 9987 9988 /* disable Rx switching replication unless we have SR-IOV 9989 * virtual functions 9990 */ 9991 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9992 if (!adapter->num_vfs) 9993 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9994 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9995 9996 /* disable Rx source address pruning, since we don't expect to 9997 * be receiving external loopback of our transmitted frames. 9998 */ 9999 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10000 for (p = 0; p < num_pools; p++) { 10001 if (hw->mac.ops.set_source_address_pruning) 10002 hw->mac.ops.set_source_address_pruning(hw, 10003 false, 10004 p); 10005 } 10006 break; 10007 default: 10008 return -EINVAL; 10009 } 10010 10011 adapter->bridge_mode = mode; 10012 10013 e_info(drv, "enabling bridge mode: %s\n", 10014 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10015 10016 return 0; 10017 } 10018 10019 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10020 struct nlmsghdr *nlh, u16 flags, 10021 struct netlink_ext_ack *extack) 10022 { 10023 struct ixgbe_adapter *adapter = netdev_priv(dev); 10024 struct nlattr *attr, *br_spec; 10025 int rem; 10026 10027 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10028 return -EOPNOTSUPP; 10029 10030 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10031 if (!br_spec) 10032 return -EINVAL; 10033 10034 nla_for_each_nested(attr, br_spec, rem) { 10035 int status; 10036 __u16 mode; 10037 10038 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10039 continue; 10040 10041 mode = nla_get_u16(attr); 10042 status = ixgbe_configure_bridge_mode(adapter, mode); 10043 if (status) 10044 return status; 10045 10046 break; 10047 } 10048 10049 return 0; 10050 } 10051 10052 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10053 struct net_device *dev, 10054 u32 filter_mask, int nlflags) 10055 { 10056 struct ixgbe_adapter *adapter = netdev_priv(dev); 10057 10058 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10059 return 0; 10060 10061 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10062 adapter->bridge_mode, 0, 0, nlflags, 10063 filter_mask, NULL); 10064 } 10065 10066 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10067 { 10068 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10069 struct ixgbe_fwd_adapter *accel; 10070 int tcs = adapter->hw_tcs ? : 1; 10071 int pool, err; 10072 10073 if (adapter->xdp_prog) { 10074 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10075 return ERR_PTR(-EINVAL); 10076 } 10077 10078 /* The hardware supported by ixgbe only filters on the destination MAC 10079 * address. In order to avoid issues we only support offloading modes 10080 * where the hardware can actually provide the functionality. 10081 */ 10082 if (!macvlan_supports_dest_filter(vdev)) 10083 return ERR_PTR(-EMEDIUMTYPE); 10084 10085 /* We need to lock down the macvlan to be a single queue device so that 10086 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10087 * the queue mapping to our netdev. 10088 */ 10089 if (netif_is_multiqueue(vdev)) 10090 return ERR_PTR(-ERANGE); 10091 10092 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10093 if (pool == adapter->num_rx_pools) { 10094 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10095 u16 reserved_pools; 10096 10097 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10098 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10099 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10100 return ERR_PTR(-EBUSY); 10101 10102 /* Hardware has a limited number of available pools. Each VF, 10103 * and the PF require a pool. Check to ensure we don't 10104 * attempt to use more then the available number of pools. 10105 */ 10106 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10107 return ERR_PTR(-EBUSY); 10108 10109 /* Enable VMDq flag so device will be set in VM mode */ 10110 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10111 IXGBE_FLAG_SRIOV_ENABLED; 10112 10113 /* Try to reserve as many queues per pool as possible, 10114 * we start with the configurations that support 4 queues 10115 * per pools, followed by 2, and then by just 1 per pool. 10116 */ 10117 if (used_pools < 32 && adapter->num_rx_pools < 16) 10118 reserved_pools = min_t(u16, 10119 32 - used_pools, 10120 16 - adapter->num_rx_pools); 10121 else if (adapter->num_rx_pools < 32) 10122 reserved_pools = min_t(u16, 10123 64 - used_pools, 10124 32 - adapter->num_rx_pools); 10125 else 10126 reserved_pools = 64 - used_pools; 10127 10128 10129 if (!reserved_pools) 10130 return ERR_PTR(-EBUSY); 10131 10132 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10133 10134 /* Force reinit of ring allocation with VMDQ enabled */ 10135 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10136 if (err) 10137 return ERR_PTR(err); 10138 10139 if (pool >= adapter->num_rx_pools) 10140 return ERR_PTR(-ENOMEM); 10141 } 10142 10143 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10144 if (!accel) 10145 return ERR_PTR(-ENOMEM); 10146 10147 set_bit(pool, adapter->fwd_bitmask); 10148 netdev_set_sb_channel(vdev, pool); 10149 accel->pool = pool; 10150 accel->netdev = vdev; 10151 10152 if (!netif_running(pdev)) 10153 return accel; 10154 10155 err = ixgbe_fwd_ring_up(adapter, accel); 10156 if (err) 10157 return ERR_PTR(err); 10158 10159 return accel; 10160 } 10161 10162 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10163 { 10164 struct ixgbe_fwd_adapter *accel = priv; 10165 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10166 unsigned int rxbase = accel->rx_base_queue; 10167 unsigned int i; 10168 10169 /* delete unicast filter associated with offloaded interface */ 10170 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10171 VMDQ_P(accel->pool)); 10172 10173 /* Allow remaining Rx packets to get flushed out of the 10174 * Rx FIFO before we drop the netdev for the ring. 10175 */ 10176 usleep_range(10000, 20000); 10177 10178 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10179 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10180 struct ixgbe_q_vector *qv = ring->q_vector; 10181 10182 /* Make sure we aren't processing any packets and clear 10183 * netdev to shut down the ring. 10184 */ 10185 if (netif_running(adapter->netdev)) 10186 napi_synchronize(&qv->napi); 10187 ring->netdev = NULL; 10188 } 10189 10190 /* unbind the queues and drop the subordinate channel config */ 10191 netdev_unbind_sb_channel(pdev, accel->netdev); 10192 netdev_set_sb_channel(accel->netdev, 0); 10193 10194 clear_bit(accel->pool, adapter->fwd_bitmask); 10195 kfree(accel); 10196 } 10197 10198 #define IXGBE_MAX_MAC_HDR_LEN 127 10199 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10200 10201 static netdev_features_t 10202 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10203 netdev_features_t features) 10204 { 10205 unsigned int network_hdr_len, mac_hdr_len; 10206 10207 /* Make certain the headers can be described by a context descriptor */ 10208 mac_hdr_len = skb_network_header(skb) - skb->data; 10209 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10210 return features & ~(NETIF_F_HW_CSUM | 10211 NETIF_F_SCTP_CRC | 10212 NETIF_F_GSO_UDP_L4 | 10213 NETIF_F_HW_VLAN_CTAG_TX | 10214 NETIF_F_TSO | 10215 NETIF_F_TSO6); 10216 10217 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10218 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10219 return features & ~(NETIF_F_HW_CSUM | 10220 NETIF_F_SCTP_CRC | 10221 NETIF_F_GSO_UDP_L4 | 10222 NETIF_F_TSO | 10223 NETIF_F_TSO6); 10224 10225 /* We can only support IPV4 TSO in tunnels if we can mangle the 10226 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10227 * IPsec offoad sets skb->encapsulation but still can handle 10228 * the TSO, so it's the exception. 10229 */ 10230 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10231 #ifdef CONFIG_IXGBE_IPSEC 10232 if (!secpath_exists(skb)) 10233 #endif 10234 features &= ~NETIF_F_TSO; 10235 } 10236 10237 return features; 10238 } 10239 10240 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10241 { 10242 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10243 struct ixgbe_adapter *adapter = netdev_priv(dev); 10244 struct bpf_prog *old_prog; 10245 bool need_reset; 10246 int num_queues; 10247 10248 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10249 return -EINVAL; 10250 10251 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10252 return -EINVAL; 10253 10254 /* verify ixgbe ring attributes are sufficient for XDP */ 10255 for (i = 0; i < adapter->num_rx_queues; i++) { 10256 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10257 10258 if (ring_is_rsc_enabled(ring)) 10259 return -EINVAL; 10260 10261 if (frame_size > ixgbe_rx_bufsz(ring)) 10262 return -EINVAL; 10263 } 10264 10265 /* if the number of cpus is much larger than the maximum of queues, 10266 * we should stop it and then return with ENOMEM like before. 10267 */ 10268 if (nr_cpu_ids > IXGBE_MAX_XDP_QS * 2) 10269 return -ENOMEM; 10270 10271 old_prog = xchg(&adapter->xdp_prog, prog); 10272 need_reset = (!!prog != !!old_prog); 10273 10274 /* If transitioning XDP modes reconfigure rings */ 10275 if (need_reset) { 10276 int err; 10277 10278 if (!prog) 10279 /* Wait until ndo_xsk_wakeup completes. */ 10280 synchronize_rcu(); 10281 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10282 10283 if (err) 10284 return -EINVAL; 10285 if (!prog) 10286 xdp_features_clear_redirect_target(dev); 10287 } else { 10288 for (i = 0; i < adapter->num_rx_queues; i++) { 10289 WRITE_ONCE(adapter->rx_ring[i]->xdp_prog, 10290 adapter->xdp_prog); 10291 } 10292 } 10293 10294 if (old_prog) 10295 bpf_prog_put(old_prog); 10296 10297 /* Kick start the NAPI context if there is an AF_XDP socket open 10298 * on that queue id. This so that receiving will start. 10299 */ 10300 if (need_reset && prog) { 10301 num_queues = min_t(int, adapter->num_rx_queues, 10302 adapter->num_xdp_queues); 10303 for (i = 0; i < num_queues; i++) 10304 if (adapter->xdp_ring[i]->xsk_pool) 10305 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10306 XDP_WAKEUP_RX); 10307 xdp_features_set_redirect_target(dev, true); 10308 } 10309 10310 return 0; 10311 } 10312 10313 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10314 { 10315 struct ixgbe_adapter *adapter = netdev_priv(dev); 10316 10317 switch (xdp->command) { 10318 case XDP_SETUP_PROG: 10319 return ixgbe_xdp_setup(dev, xdp->prog); 10320 case XDP_SETUP_XSK_POOL: 10321 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10322 xdp->xsk.queue_id); 10323 10324 default: 10325 return -EINVAL; 10326 } 10327 } 10328 10329 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10330 { 10331 /* Force memory writes to complete before letting h/w know there 10332 * are new descriptors to fetch. 10333 */ 10334 wmb(); 10335 writel(ring->next_to_use, ring->tail); 10336 } 10337 10338 void ixgbe_xdp_ring_update_tail_locked(struct ixgbe_ring *ring) 10339 { 10340 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10341 spin_lock(&ring->tx_lock); 10342 ixgbe_xdp_ring_update_tail(ring); 10343 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10344 spin_unlock(&ring->tx_lock); 10345 } 10346 10347 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10348 struct xdp_frame **frames, u32 flags) 10349 { 10350 struct ixgbe_adapter *adapter = netdev_priv(dev); 10351 struct ixgbe_ring *ring; 10352 int nxmit = 0; 10353 int i; 10354 10355 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10356 return -ENETDOWN; 10357 10358 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10359 return -EINVAL; 10360 10361 /* During program transitions its possible adapter->xdp_prog is assigned 10362 * but ring has not been configured yet. In this case simply abort xmit. 10363 */ 10364 ring = adapter->xdp_prog ? ixgbe_determine_xdp_ring(adapter) : NULL; 10365 if (unlikely(!ring)) 10366 return -ENXIO; 10367 10368 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10369 return -ENXIO; 10370 10371 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10372 spin_lock(&ring->tx_lock); 10373 10374 for (i = 0; i < n; i++) { 10375 struct xdp_frame *xdpf = frames[i]; 10376 int err; 10377 10378 err = ixgbe_xmit_xdp_ring(ring, xdpf); 10379 if (err != IXGBE_XDP_TX) 10380 break; 10381 nxmit++; 10382 } 10383 10384 if (unlikely(flags & XDP_XMIT_FLUSH)) 10385 ixgbe_xdp_ring_update_tail(ring); 10386 10387 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10388 spin_unlock(&ring->tx_lock); 10389 10390 return nxmit; 10391 } 10392 10393 static const struct net_device_ops ixgbe_netdev_ops = { 10394 .ndo_open = ixgbe_open, 10395 .ndo_stop = ixgbe_close, 10396 .ndo_start_xmit = ixgbe_xmit_frame, 10397 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10398 .ndo_validate_addr = eth_validate_addr, 10399 .ndo_set_mac_address = ixgbe_set_mac, 10400 .ndo_change_mtu = ixgbe_change_mtu, 10401 .ndo_tx_timeout = ixgbe_tx_timeout, 10402 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10403 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10404 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10405 .ndo_eth_ioctl = ixgbe_ioctl, 10406 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10407 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10408 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10409 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10410 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state, 10411 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10412 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10413 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10414 .ndo_get_vf_stats = ixgbe_ndo_get_vf_stats, 10415 .ndo_get_stats64 = ixgbe_get_stats64, 10416 .ndo_setup_tc = __ixgbe_setup_tc, 10417 #ifdef IXGBE_FCOE 10418 .ndo_select_queue = ixgbe_select_queue, 10419 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10420 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10421 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10422 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10423 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10424 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10425 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10426 #endif /* IXGBE_FCOE */ 10427 .ndo_set_features = ixgbe_set_features, 10428 .ndo_fix_features = ixgbe_fix_features, 10429 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10430 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10431 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10432 .ndo_dfwd_add_station = ixgbe_fwd_add, 10433 .ndo_dfwd_del_station = ixgbe_fwd_del, 10434 .ndo_features_check = ixgbe_features_check, 10435 .ndo_bpf = ixgbe_xdp, 10436 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10437 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10438 }; 10439 10440 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10441 struct ixgbe_ring *tx_ring) 10442 { 10443 unsigned long wait_delay, delay_interval; 10444 struct ixgbe_hw *hw = &adapter->hw; 10445 u8 reg_idx = tx_ring->reg_idx; 10446 int wait_loop; 10447 u32 txdctl; 10448 10449 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10450 10451 /* delay mechanism from ixgbe_disable_tx */ 10452 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10453 10454 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10455 wait_delay = delay_interval; 10456 10457 while (wait_loop--) { 10458 usleep_range(wait_delay, wait_delay + 10); 10459 wait_delay += delay_interval * 2; 10460 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10461 10462 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10463 return; 10464 } 10465 10466 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10467 } 10468 10469 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10470 struct ixgbe_ring *tx_ring) 10471 { 10472 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10473 ixgbe_disable_txr_hw(adapter, tx_ring); 10474 } 10475 10476 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10477 struct ixgbe_ring *rx_ring) 10478 { 10479 unsigned long wait_delay, delay_interval; 10480 struct ixgbe_hw *hw = &adapter->hw; 10481 u8 reg_idx = rx_ring->reg_idx; 10482 int wait_loop; 10483 u32 rxdctl; 10484 10485 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10486 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10487 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10488 10489 /* write value back with RXDCTL.ENABLE bit cleared */ 10490 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10491 10492 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10493 if (hw->mac.type == ixgbe_mac_82598EB && 10494 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10495 return; 10496 10497 /* delay mechanism from ixgbe_disable_rx */ 10498 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10499 10500 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10501 wait_delay = delay_interval; 10502 10503 while (wait_loop--) { 10504 usleep_range(wait_delay, wait_delay + 10); 10505 wait_delay += delay_interval * 2; 10506 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10507 10508 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10509 return; 10510 } 10511 10512 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10513 } 10514 10515 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10516 { 10517 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10518 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10519 } 10520 10521 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10522 { 10523 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10524 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10525 } 10526 10527 /** 10528 * ixgbe_irq_disable_single - Disable single IRQ vector 10529 * @adapter: adapter structure 10530 * @ring: ring index 10531 **/ 10532 static void ixgbe_irq_disable_single(struct ixgbe_adapter *adapter, u32 ring) 10533 { 10534 struct ixgbe_hw *hw = &adapter->hw; 10535 u64 qmask = BIT_ULL(ring); 10536 u32 mask; 10537 10538 switch (adapter->hw.mac.type) { 10539 case ixgbe_mac_82598EB: 10540 mask = qmask & IXGBE_EIMC_RTX_QUEUE; 10541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); 10542 break; 10543 case ixgbe_mac_82599EB: 10544 case ixgbe_mac_X540: 10545 case ixgbe_mac_X550: 10546 case ixgbe_mac_X550EM_x: 10547 case ixgbe_mac_x550em_a: 10548 mask = (qmask & 0xFFFFFFFF); 10549 if (mask) 10550 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 10551 mask = (qmask >> 32); 10552 if (mask) 10553 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 10554 break; 10555 default: 10556 break; 10557 } 10558 IXGBE_WRITE_FLUSH(&adapter->hw); 10559 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 10560 synchronize_irq(adapter->msix_entries[ring].vector); 10561 else 10562 synchronize_irq(adapter->pdev->irq); 10563 } 10564 10565 /** 10566 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10567 * @adapter: adapter structure 10568 * @ring: ring index 10569 * 10570 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10571 * assumes that the netdev is running. 10572 **/ 10573 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10574 { 10575 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10576 10577 rx_ring = adapter->rx_ring[ring]; 10578 tx_ring = adapter->tx_ring[ring]; 10579 xdp_ring = adapter->xdp_ring[ring]; 10580 10581 ixgbe_irq_disable_single(adapter, ring); 10582 10583 /* Rx/Tx/XDP Tx share the same napi context. */ 10584 napi_disable(&rx_ring->q_vector->napi); 10585 10586 ixgbe_disable_txr(adapter, tx_ring); 10587 if (xdp_ring) 10588 ixgbe_disable_txr(adapter, xdp_ring); 10589 ixgbe_disable_rxr_hw(adapter, rx_ring); 10590 10591 if (xdp_ring) 10592 synchronize_rcu(); 10593 10594 ixgbe_clean_tx_ring(tx_ring); 10595 if (xdp_ring) 10596 ixgbe_clean_tx_ring(xdp_ring); 10597 ixgbe_clean_rx_ring(rx_ring); 10598 10599 ixgbe_reset_txr_stats(tx_ring); 10600 if (xdp_ring) 10601 ixgbe_reset_txr_stats(xdp_ring); 10602 ixgbe_reset_rxr_stats(rx_ring); 10603 } 10604 10605 /** 10606 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10607 * @adapter: adapter structure 10608 * @ring: ring index 10609 * 10610 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10611 * assumes that the netdev is running. 10612 **/ 10613 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10614 { 10615 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10616 10617 rx_ring = adapter->rx_ring[ring]; 10618 tx_ring = adapter->tx_ring[ring]; 10619 xdp_ring = adapter->xdp_ring[ring]; 10620 10621 ixgbe_configure_tx_ring(adapter, tx_ring); 10622 if (xdp_ring) 10623 ixgbe_configure_tx_ring(adapter, xdp_ring); 10624 ixgbe_configure_rx_ring(adapter, rx_ring); 10625 10626 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10627 if (xdp_ring) 10628 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10629 10630 /* Rx/Tx/XDP Tx share the same napi context. */ 10631 napi_enable(&rx_ring->q_vector->napi); 10632 ixgbe_irq_enable_queues(adapter, BIT_ULL(ring)); 10633 IXGBE_WRITE_FLUSH(&adapter->hw); 10634 } 10635 10636 /** 10637 * ixgbe_enumerate_functions - Get the number of ports this device has 10638 * @adapter: adapter structure 10639 * 10640 * This function enumerates the phsyical functions co-located on a single slot, 10641 * in order to determine how many ports a device has. This is most useful in 10642 * determining the required GT/s of PCIe bandwidth necessary for optimal 10643 * performance. 10644 **/ 10645 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10646 { 10647 struct pci_dev *entry, *pdev = adapter->pdev; 10648 int physfns = 0; 10649 10650 /* Some cards can not use the generic count PCIe functions method, 10651 * because they are behind a parent switch, so we hardcode these with 10652 * the correct number of functions. 10653 */ 10654 if (ixgbe_pcie_from_parent(&adapter->hw)) 10655 physfns = 4; 10656 10657 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10658 /* don't count virtual functions */ 10659 if (entry->is_virtfn) 10660 continue; 10661 10662 /* When the devices on the bus don't all match our device ID, 10663 * we can't reliably determine the correct number of 10664 * functions. This can occur if a function has been direct 10665 * attached to a virtual machine using VT-d, for example. In 10666 * this case, simply return -1 to indicate this. 10667 */ 10668 if ((entry->vendor != pdev->vendor) || 10669 (entry->device != pdev->device)) 10670 return -1; 10671 10672 physfns++; 10673 } 10674 10675 return physfns; 10676 } 10677 10678 /** 10679 * ixgbe_wol_supported - Check whether device supports WoL 10680 * @adapter: the adapter private structure 10681 * @device_id: the device ID 10682 * @subdevice_id: the subsystem device ID 10683 * 10684 * This function is used by probe and ethtool to determine 10685 * which devices have WoL support 10686 * 10687 **/ 10688 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10689 u16 subdevice_id) 10690 { 10691 struct ixgbe_hw *hw = &adapter->hw; 10692 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10693 10694 /* WOL not supported on 82598 */ 10695 if (hw->mac.type == ixgbe_mac_82598EB) 10696 return false; 10697 10698 /* check eeprom to see if WOL is enabled for X540 and newer */ 10699 if (hw->mac.type >= ixgbe_mac_X540) { 10700 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10701 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10702 (hw->bus.func == 0))) 10703 return true; 10704 } 10705 10706 /* WOL is determined based on device IDs for 82599 MACs */ 10707 switch (device_id) { 10708 case IXGBE_DEV_ID_82599_SFP: 10709 /* Only these subdevices could supports WOL */ 10710 switch (subdevice_id) { 10711 case IXGBE_SUBDEV_ID_82599_560FLR: 10712 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10713 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10714 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10715 /* only support first port */ 10716 if (hw->bus.func != 0) 10717 break; 10718 fallthrough; 10719 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10720 case IXGBE_SUBDEV_ID_82599_SFP: 10721 case IXGBE_SUBDEV_ID_82599_RNDC: 10722 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10723 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10724 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10725 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10726 return true; 10727 } 10728 break; 10729 case IXGBE_DEV_ID_82599EN_SFP: 10730 /* Only these subdevices support WOL */ 10731 switch (subdevice_id) { 10732 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10733 return true; 10734 } 10735 break; 10736 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10737 /* All except this subdevice support WOL */ 10738 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10739 return true; 10740 break; 10741 case IXGBE_DEV_ID_82599_KX4: 10742 return true; 10743 default: 10744 break; 10745 } 10746 10747 return false; 10748 } 10749 10750 /** 10751 * ixgbe_set_fw_version - Set FW version 10752 * @adapter: the adapter private structure 10753 * 10754 * This function is used by probe and ethtool to determine the FW version to 10755 * format to display. The FW version is taken from the EEPROM/NVM. 10756 */ 10757 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10758 { 10759 struct ixgbe_hw *hw = &adapter->hw; 10760 struct ixgbe_nvm_version nvm_ver; 10761 10762 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10763 if (nvm_ver.oem_valid) { 10764 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10765 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10766 nvm_ver.oem_release); 10767 return; 10768 } 10769 10770 ixgbe_get_etk_id(hw, &nvm_ver); 10771 ixgbe_get_orom_version(hw, &nvm_ver); 10772 10773 if (nvm_ver.or_valid) { 10774 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10775 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10776 nvm_ver.or_build, nvm_ver.or_patch); 10777 return; 10778 } 10779 10780 /* Set ETrack ID format */ 10781 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10782 "0x%08x", nvm_ver.etk_id); 10783 } 10784 10785 /** 10786 * ixgbe_probe - Device Initialization Routine 10787 * @pdev: PCI device information struct 10788 * @ent: entry in ixgbe_pci_tbl 10789 * 10790 * Returns 0 on success, negative on failure 10791 * 10792 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10793 * The OS initialization, configuring of the adapter private structure, 10794 * and a hardware reset occur. 10795 **/ 10796 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10797 { 10798 struct net_device *netdev; 10799 struct ixgbe_adapter *adapter = NULL; 10800 struct ixgbe_hw *hw; 10801 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10802 unsigned int indices = MAX_TX_QUEUES; 10803 u8 part_str[IXGBE_PBANUM_LENGTH]; 10804 int i, err, expected_gts; 10805 bool disable_dev = false; 10806 #ifdef IXGBE_FCOE 10807 u16 device_caps; 10808 #endif 10809 u32 eec; 10810 10811 /* Catch broken hardware that put the wrong VF device ID in 10812 * the PCIe SR-IOV capability. 10813 */ 10814 if (pdev->is_virtfn) { 10815 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10816 pci_name(pdev), pdev->vendor, pdev->device); 10817 return -EINVAL; 10818 } 10819 10820 err = pci_enable_device_mem(pdev); 10821 if (err) 10822 return err; 10823 10824 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 10825 if (err) { 10826 dev_err(&pdev->dev, 10827 "No usable DMA configuration, aborting\n"); 10828 goto err_dma; 10829 } 10830 10831 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10832 if (err) { 10833 dev_err(&pdev->dev, 10834 "pci_request_selected_regions failed 0x%x\n", err); 10835 goto err_pci_reg; 10836 } 10837 10838 pci_set_master(pdev); 10839 pci_save_state(pdev); 10840 10841 if (ii->mac == ixgbe_mac_82598EB) { 10842 #ifdef CONFIG_IXGBE_DCB 10843 /* 8 TC w/ 4 queues per TC */ 10844 indices = 4 * MAX_TRAFFIC_CLASS; 10845 #else 10846 indices = IXGBE_MAX_RSS_INDICES; 10847 #endif 10848 } 10849 10850 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10851 if (!netdev) { 10852 err = -ENOMEM; 10853 goto err_alloc_etherdev; 10854 } 10855 10856 SET_NETDEV_DEV(netdev, &pdev->dev); 10857 10858 adapter = netdev_priv(netdev); 10859 10860 adapter->netdev = netdev; 10861 adapter->pdev = pdev; 10862 hw = &adapter->hw; 10863 hw->back = adapter; 10864 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10865 10866 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10867 pci_resource_len(pdev, 0)); 10868 adapter->io_addr = hw->hw_addr; 10869 if (!hw->hw_addr) { 10870 err = -EIO; 10871 goto err_ioremap; 10872 } 10873 10874 netdev->netdev_ops = &ixgbe_netdev_ops; 10875 ixgbe_set_ethtool_ops(netdev); 10876 netdev->watchdog_timeo = 5 * HZ; 10877 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10878 10879 /* Setup hw api */ 10880 hw->mac.ops = *ii->mac_ops; 10881 hw->mac.type = ii->mac; 10882 hw->mvals = ii->mvals; 10883 if (ii->link_ops) 10884 hw->link.ops = *ii->link_ops; 10885 10886 /* EEPROM */ 10887 hw->eeprom.ops = *ii->eeprom_ops; 10888 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10889 if (ixgbe_removed(hw->hw_addr)) { 10890 err = -EIO; 10891 goto err_ioremap; 10892 } 10893 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10894 if (!(eec & BIT(8))) 10895 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10896 10897 /* PHY */ 10898 hw->phy.ops = *ii->phy_ops; 10899 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10900 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10901 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10902 hw->phy.mdio.mmds = 0; 10903 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10904 hw->phy.mdio.dev = netdev; 10905 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10906 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10907 10908 /* setup the private structure */ 10909 err = ixgbe_sw_init(adapter, ii); 10910 if (err) 10911 goto err_sw_init; 10912 10913 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 10914 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 10915 10916 switch (adapter->hw.mac.type) { 10917 case ixgbe_mac_X550: 10918 case ixgbe_mac_X550EM_x: 10919 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 10920 break; 10921 case ixgbe_mac_x550em_a: 10922 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 10923 break; 10924 default: 10925 break; 10926 } 10927 10928 /* Make sure the SWFW semaphore is in a valid state */ 10929 if (hw->mac.ops.init_swfw_sync) 10930 hw->mac.ops.init_swfw_sync(hw); 10931 10932 /* Make it possible the adapter to be woken up via WOL */ 10933 switch (adapter->hw.mac.type) { 10934 case ixgbe_mac_82599EB: 10935 case ixgbe_mac_X540: 10936 case ixgbe_mac_X550: 10937 case ixgbe_mac_X550EM_x: 10938 case ixgbe_mac_x550em_a: 10939 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10940 break; 10941 default: 10942 break; 10943 } 10944 10945 /* 10946 * If there is a fan on this device and it has failed log the 10947 * failure. 10948 */ 10949 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10950 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10951 if (esdp & IXGBE_ESDP_SDP1) 10952 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10953 } 10954 10955 if (allow_unsupported_sfp) 10956 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10957 10958 /* reset_hw fills in the perm_addr as well */ 10959 hw->phy.reset_if_overtemp = true; 10960 err = hw->mac.ops.reset_hw(hw); 10961 hw->phy.reset_if_overtemp = false; 10962 ixgbe_set_eee_capable(adapter); 10963 if (err == -ENOENT) { 10964 err = 0; 10965 } else if (err == -EOPNOTSUPP) { 10966 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10967 e_dev_err("Reload the driver after installing a supported module.\n"); 10968 goto err_sw_init; 10969 } else if (err) { 10970 e_dev_err("HW Init failed: %d\n", err); 10971 goto err_sw_init; 10972 } 10973 10974 #ifdef CONFIG_PCI_IOV 10975 /* SR-IOV not supported on the 82598 */ 10976 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10977 goto skip_sriov; 10978 /* Mailbox */ 10979 ixgbe_init_mbx_params_pf(hw); 10980 hw->mbx.ops = ii->mbx_ops; 10981 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10982 ixgbe_enable_sriov(adapter, max_vfs); 10983 skip_sriov: 10984 10985 #endif 10986 netdev->features = NETIF_F_SG | 10987 NETIF_F_TSO | 10988 NETIF_F_TSO6 | 10989 NETIF_F_RXHASH | 10990 NETIF_F_RXCSUM | 10991 NETIF_F_HW_CSUM; 10992 10993 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10994 NETIF_F_GSO_GRE_CSUM | \ 10995 NETIF_F_GSO_IPXIP4 | \ 10996 NETIF_F_GSO_IPXIP6 | \ 10997 NETIF_F_GSO_UDP_TUNNEL | \ 10998 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10999 11000 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 11001 netdev->features |= NETIF_F_GSO_PARTIAL | 11002 IXGBE_GSO_PARTIAL_FEATURES; 11003 11004 if (hw->mac.type >= ixgbe_mac_82599EB) 11005 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 11006 11007 #ifdef CONFIG_IXGBE_IPSEC 11008 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 11009 NETIF_F_HW_ESP_TX_CSUM | \ 11010 NETIF_F_GSO_ESP) 11011 11012 if (adapter->ipsec) 11013 netdev->features |= IXGBE_ESP_FEATURES; 11014 #endif 11015 /* copy netdev features into list of user selectable features */ 11016 netdev->hw_features |= netdev->features | 11017 NETIF_F_HW_VLAN_CTAG_FILTER | 11018 NETIF_F_HW_VLAN_CTAG_RX | 11019 NETIF_F_HW_VLAN_CTAG_TX | 11020 NETIF_F_RXALL | 11021 NETIF_F_HW_L2FW_DOFFLOAD; 11022 11023 if (hw->mac.type >= ixgbe_mac_82599EB) 11024 netdev->hw_features |= NETIF_F_NTUPLE | 11025 NETIF_F_HW_TC; 11026 11027 netdev->features |= NETIF_F_HIGHDMA; 11028 11029 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 11030 netdev->hw_enc_features |= netdev->vlan_features; 11031 netdev->mpls_features |= NETIF_F_SG | 11032 NETIF_F_TSO | 11033 NETIF_F_TSO6 | 11034 NETIF_F_HW_CSUM; 11035 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 11036 11037 /* set this bit last since it cannot be part of vlan_features */ 11038 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 11039 NETIF_F_HW_VLAN_CTAG_RX | 11040 NETIF_F_HW_VLAN_CTAG_TX; 11041 11042 netdev->priv_flags |= IFF_UNICAST_FLT; 11043 netdev->priv_flags |= IFF_SUPP_NOFCS; 11044 11045 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 11046 NETDEV_XDP_ACT_XSK_ZEROCOPY; 11047 11048 /* MTU range: 68 - 9710 */ 11049 netdev->min_mtu = ETH_MIN_MTU; 11050 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 11051 11052 #ifdef CONFIG_IXGBE_DCB 11053 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 11054 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 11055 #endif 11056 11057 #ifdef IXGBE_FCOE 11058 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 11059 unsigned int fcoe_l; 11060 11061 if (hw->mac.ops.get_device_caps) { 11062 hw->mac.ops.get_device_caps(hw, &device_caps); 11063 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 11064 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 11065 } 11066 11067 11068 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 11069 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 11070 11071 netdev->features |= NETIF_F_FSO | 11072 NETIF_F_FCOE_CRC; 11073 11074 netdev->vlan_features |= NETIF_F_FSO | 11075 NETIF_F_FCOE_CRC | 11076 NETIF_F_FCOE_MTU; 11077 } 11078 #endif /* IXGBE_FCOE */ 11079 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 11080 netdev->hw_features |= NETIF_F_LRO; 11081 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 11082 netdev->features |= NETIF_F_LRO; 11083 11084 if (ixgbe_check_fw_error(adapter)) { 11085 err = -EIO; 11086 goto err_sw_init; 11087 } 11088 11089 /* make sure the EEPROM is good */ 11090 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11091 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11092 err = -EIO; 11093 goto err_sw_init; 11094 } 11095 11096 eth_platform_get_mac_address(&adapter->pdev->dev, 11097 adapter->hw.mac.perm_addr); 11098 11099 eth_hw_addr_set(netdev, hw->mac.perm_addr); 11100 11101 if (!is_valid_ether_addr(netdev->dev_addr)) { 11102 e_dev_err("invalid MAC address\n"); 11103 err = -EIO; 11104 goto err_sw_init; 11105 } 11106 11107 /* Set hw->mac.addr to permanent MAC address */ 11108 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11109 ixgbe_mac_set_default_filter(adapter); 11110 11111 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11112 11113 if (ixgbe_removed(hw->hw_addr)) { 11114 err = -EIO; 11115 goto err_sw_init; 11116 } 11117 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11118 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11119 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11120 11121 err = ixgbe_init_interrupt_scheme(adapter); 11122 if (err) 11123 goto err_sw_init; 11124 11125 for (i = 0; i < adapter->num_rx_queues; i++) 11126 u64_stats_init(&adapter->rx_ring[i]->syncp); 11127 for (i = 0; i < adapter->num_tx_queues; i++) 11128 u64_stats_init(&adapter->tx_ring[i]->syncp); 11129 for (i = 0; i < adapter->num_xdp_queues; i++) 11130 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11131 11132 /* WOL not supported for all devices */ 11133 adapter->wol = 0; 11134 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11135 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11136 pdev->subsystem_device); 11137 if (hw->wol_enabled) 11138 adapter->wol = IXGBE_WUFC_MAG; 11139 11140 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11141 11142 /* save off EEPROM version number */ 11143 ixgbe_set_fw_version(adapter); 11144 11145 /* pick up the PCI bus settings for reporting later */ 11146 if (ixgbe_pcie_from_parent(hw)) 11147 ixgbe_get_parent_bus_info(adapter); 11148 else 11149 hw->mac.ops.get_bus_info(hw); 11150 11151 /* calculate the expected PCIe bandwidth required for optimal 11152 * performance. Note that some older parts will never have enough 11153 * bandwidth due to being older generation PCIe parts. We clamp these 11154 * parts to ensure no warning is displayed if it can't be fixed. 11155 */ 11156 switch (hw->mac.type) { 11157 case ixgbe_mac_82598EB: 11158 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11159 break; 11160 default: 11161 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11162 break; 11163 } 11164 11165 /* don't check link if we failed to enumerate functions */ 11166 if (expected_gts > 0) 11167 ixgbe_check_minimum_link(adapter, expected_gts); 11168 11169 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11170 if (err) 11171 strscpy(part_str, "Unknown", sizeof(part_str)); 11172 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11173 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11174 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11175 part_str); 11176 else 11177 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11178 hw->mac.type, hw->phy.type, part_str); 11179 11180 e_dev_info("%pM\n", netdev->dev_addr); 11181 11182 /* reset the hardware with the new settings */ 11183 err = hw->mac.ops.start_hw(hw); 11184 if (err == -EACCES) { 11185 /* We are running on a pre-production device, log a warning */ 11186 e_dev_warn("This device is a pre-production adapter/LOM. " 11187 "Please be aware there may be issues associated " 11188 "with your hardware. If you are experiencing " 11189 "problems please contact your Intel or hardware " 11190 "representative who provided you with this " 11191 "hardware.\n"); 11192 } 11193 strcpy(netdev->name, "eth%d"); 11194 pci_set_drvdata(pdev, adapter); 11195 err = register_netdev(netdev); 11196 if (err) 11197 goto err_register; 11198 11199 11200 /* power down the optics for 82599 SFP+ fiber */ 11201 if (hw->mac.ops.disable_tx_laser) 11202 hw->mac.ops.disable_tx_laser(hw); 11203 11204 /* carrier off reporting is important to ethtool even BEFORE open */ 11205 netif_carrier_off(netdev); 11206 11207 #ifdef CONFIG_IXGBE_DCA 11208 if (dca_add_requester(&pdev->dev) == 0) { 11209 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11210 ixgbe_setup_dca(adapter); 11211 } 11212 #endif 11213 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11214 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11215 for (i = 0; i < adapter->num_vfs; i++) 11216 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11217 } 11218 11219 /* firmware requires driver version to be 0xFFFFFFFF 11220 * since os does not support feature 11221 */ 11222 if (hw->mac.ops.set_fw_drv_ver) 11223 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11224 sizeof(UTS_RELEASE) - 1, 11225 UTS_RELEASE); 11226 11227 /* add san mac addr to netdev */ 11228 ixgbe_add_sanmac_netdev(netdev); 11229 11230 e_dev_info("%s\n", ixgbe_default_device_descr); 11231 11232 #ifdef CONFIG_IXGBE_HWMON 11233 if (ixgbe_sysfs_init(adapter)) 11234 e_err(probe, "failed to allocate sysfs resources\n"); 11235 #endif /* CONFIG_IXGBE_HWMON */ 11236 11237 ixgbe_dbg_adapter_init(adapter); 11238 11239 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11240 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11241 hw->mac.ops.setup_link(hw, 11242 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11243 true); 11244 11245 err = ixgbe_mii_bus_init(hw); 11246 if (err) 11247 goto err_netdev; 11248 11249 return 0; 11250 11251 err_netdev: 11252 unregister_netdev(netdev); 11253 err_register: 11254 ixgbe_release_hw_control(adapter); 11255 ixgbe_clear_interrupt_scheme(adapter); 11256 err_sw_init: 11257 ixgbe_disable_sriov(adapter); 11258 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11259 iounmap(adapter->io_addr); 11260 kfree(adapter->jump_tables[0]); 11261 kfree(adapter->mac_table); 11262 kfree(adapter->rss_key); 11263 bitmap_free(adapter->af_xdp_zc_qps); 11264 err_ioremap: 11265 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11266 free_netdev(netdev); 11267 err_alloc_etherdev: 11268 pci_release_mem_regions(pdev); 11269 err_pci_reg: 11270 err_dma: 11271 if (!adapter || disable_dev) 11272 pci_disable_device(pdev); 11273 return err; 11274 } 11275 11276 /** 11277 * ixgbe_remove - Device Removal Routine 11278 * @pdev: PCI device information struct 11279 * 11280 * ixgbe_remove is called by the PCI subsystem to alert the driver 11281 * that it should release a PCI device. The could be caused by a 11282 * Hot-Plug event, or because the driver is going to be removed from 11283 * memory. 11284 **/ 11285 static void ixgbe_remove(struct pci_dev *pdev) 11286 { 11287 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11288 struct net_device *netdev; 11289 bool disable_dev; 11290 int i; 11291 11292 /* if !adapter then we already cleaned up in probe */ 11293 if (!adapter) 11294 return; 11295 11296 netdev = adapter->netdev; 11297 ixgbe_dbg_adapter_exit(adapter); 11298 11299 set_bit(__IXGBE_REMOVING, &adapter->state); 11300 cancel_work_sync(&adapter->service_task); 11301 11302 if (adapter->mii_bus) 11303 mdiobus_unregister(adapter->mii_bus); 11304 11305 #ifdef CONFIG_IXGBE_DCA 11306 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11307 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11308 dca_remove_requester(&pdev->dev); 11309 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11310 IXGBE_DCA_CTRL_DCA_DISABLE); 11311 } 11312 11313 #endif 11314 #ifdef CONFIG_IXGBE_HWMON 11315 ixgbe_sysfs_exit(adapter); 11316 #endif /* CONFIG_IXGBE_HWMON */ 11317 11318 /* remove the added san mac */ 11319 ixgbe_del_sanmac_netdev(netdev); 11320 11321 #ifdef CONFIG_PCI_IOV 11322 ixgbe_disable_sriov(adapter); 11323 #endif 11324 if (netdev->reg_state == NETREG_REGISTERED) 11325 unregister_netdev(netdev); 11326 11327 ixgbe_stop_ipsec_offload(adapter); 11328 ixgbe_clear_interrupt_scheme(adapter); 11329 11330 ixgbe_release_hw_control(adapter); 11331 11332 #ifdef CONFIG_DCB 11333 kfree(adapter->ixgbe_ieee_pfc); 11334 kfree(adapter->ixgbe_ieee_ets); 11335 11336 #endif 11337 iounmap(adapter->io_addr); 11338 pci_release_mem_regions(pdev); 11339 11340 e_dev_info("complete\n"); 11341 11342 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11343 if (adapter->jump_tables[i]) { 11344 kfree(adapter->jump_tables[i]->input); 11345 kfree(adapter->jump_tables[i]->mask); 11346 } 11347 kfree(adapter->jump_tables[i]); 11348 } 11349 11350 kfree(adapter->mac_table); 11351 kfree(adapter->rss_key); 11352 bitmap_free(adapter->af_xdp_zc_qps); 11353 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11354 free_netdev(netdev); 11355 11356 if (disable_dev) 11357 pci_disable_device(pdev); 11358 } 11359 11360 /** 11361 * ixgbe_io_error_detected - called when PCI error is detected 11362 * @pdev: Pointer to PCI device 11363 * @state: The current pci connection state 11364 * 11365 * This function is called after a PCI bus error affecting 11366 * this device has been detected. 11367 */ 11368 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11369 pci_channel_state_t state) 11370 { 11371 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11372 struct net_device *netdev = adapter->netdev; 11373 11374 #ifdef CONFIG_PCI_IOV 11375 struct ixgbe_hw *hw = &adapter->hw; 11376 struct pci_dev *bdev, *vfdev; 11377 u32 dw0, dw1, dw2, dw3; 11378 int vf, pos; 11379 u16 req_id, pf_func; 11380 11381 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11382 adapter->num_vfs == 0) 11383 goto skip_bad_vf_detection; 11384 11385 bdev = pdev->bus->self; 11386 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11387 bdev = bdev->bus->self; 11388 11389 if (!bdev) 11390 goto skip_bad_vf_detection; 11391 11392 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11393 if (!pos) 11394 goto skip_bad_vf_detection; 11395 11396 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11397 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11398 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11399 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11400 if (ixgbe_removed(hw->hw_addr)) 11401 goto skip_bad_vf_detection; 11402 11403 req_id = dw1 >> 16; 11404 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11405 if (!(req_id & 0x0080)) 11406 goto skip_bad_vf_detection; 11407 11408 pf_func = req_id & 0x01; 11409 if ((pf_func & 1) == (pdev->devfn & 1)) { 11410 unsigned int device_id; 11411 11412 vf = FIELD_GET(0x7F, req_id); 11413 e_dev_err("VF %d has caused a PCIe error\n", vf); 11414 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11415 "%8.8x\tdw3: %8.8x\n", 11416 dw0, dw1, dw2, dw3); 11417 switch (adapter->hw.mac.type) { 11418 case ixgbe_mac_82599EB: 11419 device_id = IXGBE_82599_VF_DEVICE_ID; 11420 break; 11421 case ixgbe_mac_X540: 11422 device_id = IXGBE_X540_VF_DEVICE_ID; 11423 break; 11424 case ixgbe_mac_X550: 11425 device_id = IXGBE_DEV_ID_X550_VF; 11426 break; 11427 case ixgbe_mac_X550EM_x: 11428 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11429 break; 11430 case ixgbe_mac_x550em_a: 11431 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11432 break; 11433 default: 11434 device_id = 0; 11435 break; 11436 } 11437 11438 /* Find the pci device of the offending VF */ 11439 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11440 while (vfdev) { 11441 if (vfdev->devfn == (req_id & 0xFF)) 11442 break; 11443 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11444 device_id, vfdev); 11445 } 11446 /* 11447 * There's a slim chance the VF could have been hot plugged, 11448 * so if it is no longer present we don't need to issue the 11449 * VFLR. Just clean up the AER in that case. 11450 */ 11451 if (vfdev) { 11452 pcie_flr(vfdev); 11453 /* Free device reference count */ 11454 pci_dev_put(vfdev); 11455 } 11456 } 11457 11458 /* 11459 * Even though the error may have occurred on the other port 11460 * we still need to increment the vf error reference count for 11461 * both ports because the I/O resume function will be called 11462 * for both of them. 11463 */ 11464 adapter->vferr_refcount++; 11465 11466 return PCI_ERS_RESULT_RECOVERED; 11467 11468 skip_bad_vf_detection: 11469 #endif /* CONFIG_PCI_IOV */ 11470 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11471 return PCI_ERS_RESULT_DISCONNECT; 11472 11473 if (!netif_device_present(netdev)) 11474 return PCI_ERS_RESULT_DISCONNECT; 11475 11476 rtnl_lock(); 11477 netif_device_detach(netdev); 11478 11479 if (netif_running(netdev)) 11480 ixgbe_close_suspend(adapter); 11481 11482 if (state == pci_channel_io_perm_failure) { 11483 rtnl_unlock(); 11484 return PCI_ERS_RESULT_DISCONNECT; 11485 } 11486 11487 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11488 pci_disable_device(pdev); 11489 rtnl_unlock(); 11490 11491 /* Request a slot reset. */ 11492 return PCI_ERS_RESULT_NEED_RESET; 11493 } 11494 11495 /** 11496 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11497 * @pdev: Pointer to PCI device 11498 * 11499 * Restart the card from scratch, as if from a cold-boot. 11500 */ 11501 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11502 { 11503 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11504 pci_ers_result_t result; 11505 11506 if (pci_enable_device_mem(pdev)) { 11507 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11508 result = PCI_ERS_RESULT_DISCONNECT; 11509 } else { 11510 smp_mb__before_atomic(); 11511 clear_bit(__IXGBE_DISABLED, &adapter->state); 11512 adapter->hw.hw_addr = adapter->io_addr; 11513 pci_set_master(pdev); 11514 pci_restore_state(pdev); 11515 pci_save_state(pdev); 11516 11517 pci_wake_from_d3(pdev, false); 11518 11519 ixgbe_reset(adapter); 11520 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11521 result = PCI_ERS_RESULT_RECOVERED; 11522 } 11523 11524 return result; 11525 } 11526 11527 /** 11528 * ixgbe_io_resume - called when traffic can start flowing again. 11529 * @pdev: Pointer to PCI device 11530 * 11531 * This callback is called when the error recovery driver tells us that 11532 * its OK to resume normal operation. 11533 */ 11534 static void ixgbe_io_resume(struct pci_dev *pdev) 11535 { 11536 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11537 struct net_device *netdev = adapter->netdev; 11538 11539 #ifdef CONFIG_PCI_IOV 11540 if (adapter->vferr_refcount) { 11541 e_info(drv, "Resuming after VF err\n"); 11542 adapter->vferr_refcount--; 11543 return; 11544 } 11545 11546 #endif 11547 rtnl_lock(); 11548 if (netif_running(netdev)) 11549 ixgbe_open(netdev); 11550 11551 netif_device_attach(netdev); 11552 rtnl_unlock(); 11553 } 11554 11555 static const struct pci_error_handlers ixgbe_err_handler = { 11556 .error_detected = ixgbe_io_error_detected, 11557 .slot_reset = ixgbe_io_slot_reset, 11558 .resume = ixgbe_io_resume, 11559 }; 11560 11561 static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11562 11563 static struct pci_driver ixgbe_driver = { 11564 .name = ixgbe_driver_name, 11565 .id_table = ixgbe_pci_tbl, 11566 .probe = ixgbe_probe, 11567 .remove = ixgbe_remove, 11568 .driver.pm = &ixgbe_pm_ops, 11569 .shutdown = ixgbe_shutdown, 11570 .sriov_configure = ixgbe_pci_sriov_configure, 11571 .err_handler = &ixgbe_err_handler 11572 }; 11573 11574 /** 11575 * ixgbe_init_module - Driver Registration Routine 11576 * 11577 * ixgbe_init_module is the first routine called when the driver is 11578 * loaded. All it does is register with the PCI subsystem. 11579 **/ 11580 static int __init ixgbe_init_module(void) 11581 { 11582 int ret; 11583 pr_info("%s\n", ixgbe_driver_string); 11584 pr_info("%s\n", ixgbe_copyright); 11585 11586 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11587 if (!ixgbe_wq) { 11588 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11589 return -ENOMEM; 11590 } 11591 11592 ixgbe_dbg_init(); 11593 11594 ret = pci_register_driver(&ixgbe_driver); 11595 if (ret) { 11596 destroy_workqueue(ixgbe_wq); 11597 ixgbe_dbg_exit(); 11598 return ret; 11599 } 11600 11601 #ifdef CONFIG_IXGBE_DCA 11602 dca_register_notify(&dca_notifier); 11603 #endif 11604 11605 return 0; 11606 } 11607 11608 module_init(ixgbe_init_module); 11609 11610 /** 11611 * ixgbe_exit_module - Driver Exit Cleanup Routine 11612 * 11613 * ixgbe_exit_module is called just before the driver is removed 11614 * from memory. 11615 **/ 11616 static void __exit ixgbe_exit_module(void) 11617 { 11618 #ifdef CONFIG_IXGBE_DCA 11619 dca_unregister_notify(&dca_notifier); 11620 #endif 11621 pci_unregister_driver(&ixgbe_driver); 11622 11623 ixgbe_dbg_exit(); 11624 if (ixgbe_wq) { 11625 destroy_workqueue(ixgbe_wq); 11626 ixgbe_wq = NULL; 11627 } 11628 } 11629 11630 #ifdef CONFIG_IXGBE_DCA 11631 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11632 void *p) 11633 { 11634 int ret_val; 11635 11636 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11637 __ixgbe_notify_dca); 11638 11639 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11640 } 11641 11642 #endif /* CONFIG_IXGBE_DCA */ 11643 11644 module_exit(ixgbe_exit_module); 11645 11646 /* ixgbe_main.c */ 11647