1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <scsi/fc/fc_fcoe.h> 32 #include <net/udp_tunnel.h> 33 #include <net/pkt_cls.h> 34 #include <net/tc_act/tc_gact.h> 35 #include <net/tc_act/tc_mirred.h> 36 #include <net/vxlan.h> 37 #include <net/mpls.h> 38 #include <net/xdp_sock.h> 39 #include <net/xfrm.h> 40 41 #include "ixgbe.h" 42 #include "ixgbe_common.h" 43 #include "ixgbe_dcb_82599.h" 44 #include "ixgbe_phy.h" 45 #include "ixgbe_sriov.h" 46 #include "ixgbe_model.h" 47 #include "ixgbe_txrx_common.h" 48 49 char ixgbe_driver_name[] = "ixgbe"; 50 static const char ixgbe_driver_string[] = 51 "Intel(R) 10 Gigabit PCI Express Network Driver"; 52 #ifdef IXGBE_FCOE 53 char ixgbe_default_device_descr[] = 54 "Intel(R) 10 Gigabit Network Connection"; 55 #else 56 static char ixgbe_default_device_descr[] = 57 "Intel(R) 10 Gigabit Network Connection"; 58 #endif 59 #define DRV_VERSION "5.1.0-k" 60 const char ixgbe_driver_version[] = DRV_VERSION; 61 static const char ixgbe_copyright[] = 62 "Copyright (c) 1999-2016 Intel Corporation."; 63 64 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 65 66 static const struct ixgbe_info *ixgbe_info_tbl[] = { 67 [board_82598] = &ixgbe_82598_info, 68 [board_82599] = &ixgbe_82599_info, 69 [board_X540] = &ixgbe_X540_info, 70 [board_X550] = &ixgbe_X550_info, 71 [board_X550EM_x] = &ixgbe_X550EM_x_info, 72 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 73 [board_x550em_a] = &ixgbe_x550em_a_info, 74 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 75 }; 76 77 /* ixgbe_pci_tbl - PCI Device ID Table 78 * 79 * Wildcard entries (PCI_ANY_ID) should come last 80 * Last entry must be all 0s 81 * 82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 83 * Class, Class Mask, private data (not used) } 84 */ 85 static const struct pci_device_id ixgbe_pci_tbl[] = { 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 133 /* required last entry */ 134 {0, } 135 }; 136 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 137 138 #ifdef CONFIG_IXGBE_DCA 139 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 140 void *p); 141 static struct notifier_block dca_notifier = { 142 .notifier_call = ixgbe_notify_dca, 143 .next = NULL, 144 .priority = 0 145 }; 146 #endif 147 148 #ifdef CONFIG_PCI_IOV 149 static unsigned int max_vfs; 150 module_param(max_vfs, uint, 0); 151 MODULE_PARM_DESC(max_vfs, 152 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 153 #endif /* CONFIG_PCI_IOV */ 154 155 static unsigned int allow_unsupported_sfp; 156 module_param(allow_unsupported_sfp, uint, 0); 157 MODULE_PARM_DESC(allow_unsupported_sfp, 158 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 159 160 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 161 static int debug = -1; 162 module_param(debug, int, 0); 163 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 164 165 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 166 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 167 MODULE_LICENSE("GPL v2"); 168 MODULE_VERSION(DRV_VERSION); 169 170 static struct workqueue_struct *ixgbe_wq; 171 172 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 173 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 174 175 static const struct net_device_ops ixgbe_netdev_ops; 176 177 static bool netif_is_ixgbe(struct net_device *dev) 178 { 179 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 180 } 181 182 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 183 u32 reg, u16 *value) 184 { 185 struct pci_dev *parent_dev; 186 struct pci_bus *parent_bus; 187 188 parent_bus = adapter->pdev->bus->parent; 189 if (!parent_bus) 190 return -1; 191 192 parent_dev = parent_bus->self; 193 if (!parent_dev) 194 return -1; 195 196 if (!pci_is_pcie(parent_dev)) 197 return -1; 198 199 pcie_capability_read_word(parent_dev, reg, value); 200 if (*value == IXGBE_FAILED_READ_CFG_WORD && 201 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 202 return -1; 203 return 0; 204 } 205 206 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 207 { 208 struct ixgbe_hw *hw = &adapter->hw; 209 u16 link_status = 0; 210 int err; 211 212 hw->bus.type = ixgbe_bus_type_pci_express; 213 214 /* Get the negotiated link width and speed from PCI config space of the 215 * parent, as this device is behind a switch 216 */ 217 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 218 219 /* assume caller will handle error case */ 220 if (err) 221 return err; 222 223 hw->bus.width = ixgbe_convert_bus_width(link_status); 224 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 225 226 return 0; 227 } 228 229 /** 230 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 231 * @hw: hw specific details 232 * 233 * This function is used by probe to determine whether a device's PCI-Express 234 * bandwidth details should be gathered from the parent bus instead of from the 235 * device. Used to ensure that various locations all have the correct device ID 236 * checks. 237 */ 238 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 239 { 240 switch (hw->device_id) { 241 case IXGBE_DEV_ID_82599_SFP_SF_QP: 242 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 243 return true; 244 default: 245 return false; 246 } 247 } 248 249 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 250 int expected_gts) 251 { 252 struct ixgbe_hw *hw = &adapter->hw; 253 struct pci_dev *pdev; 254 255 /* Some devices are not connected over PCIe and thus do not negotiate 256 * speed. These devices do not have valid bus info, and thus any report 257 * we generate may not be correct. 258 */ 259 if (hw->bus.type == ixgbe_bus_type_internal) 260 return; 261 262 /* determine whether to use the parent device */ 263 if (ixgbe_pcie_from_parent(&adapter->hw)) 264 pdev = adapter->pdev->bus->parent->self; 265 else 266 pdev = adapter->pdev; 267 268 pcie_print_link_status(pdev); 269 } 270 271 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 272 { 273 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 274 !test_bit(__IXGBE_REMOVING, &adapter->state) && 275 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 276 queue_work(ixgbe_wq, &adapter->service_task); 277 } 278 279 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 280 { 281 struct ixgbe_adapter *adapter = hw->back; 282 283 if (!hw->hw_addr) 284 return; 285 hw->hw_addr = NULL; 286 e_dev_err("Adapter removed\n"); 287 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 288 ixgbe_service_event_schedule(adapter); 289 } 290 291 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 292 { 293 u8 __iomem *reg_addr; 294 u32 value; 295 int i; 296 297 reg_addr = READ_ONCE(hw->hw_addr); 298 if (ixgbe_removed(reg_addr)) 299 return IXGBE_FAILED_READ_REG; 300 301 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 302 * so perform several status register reads to determine if the adapter 303 * has been removed. 304 */ 305 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 306 value = readl(reg_addr + IXGBE_STATUS); 307 if (value != IXGBE_FAILED_READ_REG) 308 break; 309 mdelay(3); 310 } 311 312 if (value == IXGBE_FAILED_READ_REG) 313 ixgbe_remove_adapter(hw); 314 else 315 value = readl(reg_addr + reg); 316 return value; 317 } 318 319 /** 320 * ixgbe_read_reg - Read from device register 321 * @hw: hw specific details 322 * @reg: offset of register to read 323 * 324 * Returns : value read or IXGBE_FAILED_READ_REG if removed 325 * 326 * This function is used to read device registers. It checks for device 327 * removal by confirming any read that returns all ones by checking the 328 * status register value for all ones. This function avoids reading from 329 * the hardware if a removal was previously detected in which case it 330 * returns IXGBE_FAILED_READ_REG (all ones). 331 */ 332 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 333 { 334 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 335 u32 value; 336 337 if (ixgbe_removed(reg_addr)) 338 return IXGBE_FAILED_READ_REG; 339 if (unlikely(hw->phy.nw_mng_if_sel & 340 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 341 struct ixgbe_adapter *adapter; 342 int i; 343 344 for (i = 0; i < 200; ++i) { 345 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 346 if (likely(!value)) 347 goto writes_completed; 348 if (value == IXGBE_FAILED_READ_REG) { 349 ixgbe_remove_adapter(hw); 350 return IXGBE_FAILED_READ_REG; 351 } 352 udelay(5); 353 } 354 355 adapter = hw->back; 356 e_warn(hw, "register writes incomplete %08x\n", value); 357 } 358 359 writes_completed: 360 value = readl(reg_addr + reg); 361 if (unlikely(value == IXGBE_FAILED_READ_REG)) 362 value = ixgbe_check_remove(hw, reg); 363 return value; 364 } 365 366 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 367 { 368 u16 value; 369 370 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 371 if (value == IXGBE_FAILED_READ_CFG_WORD) { 372 ixgbe_remove_adapter(hw); 373 return true; 374 } 375 return false; 376 } 377 378 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 379 { 380 struct ixgbe_adapter *adapter = hw->back; 381 u16 value; 382 383 if (ixgbe_removed(hw->hw_addr)) 384 return IXGBE_FAILED_READ_CFG_WORD; 385 pci_read_config_word(adapter->pdev, reg, &value); 386 if (value == IXGBE_FAILED_READ_CFG_WORD && 387 ixgbe_check_cfg_remove(hw, adapter->pdev)) 388 return IXGBE_FAILED_READ_CFG_WORD; 389 return value; 390 } 391 392 #ifdef CONFIG_PCI_IOV 393 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 394 { 395 struct ixgbe_adapter *adapter = hw->back; 396 u32 value; 397 398 if (ixgbe_removed(hw->hw_addr)) 399 return IXGBE_FAILED_READ_CFG_DWORD; 400 pci_read_config_dword(adapter->pdev, reg, &value); 401 if (value == IXGBE_FAILED_READ_CFG_DWORD && 402 ixgbe_check_cfg_remove(hw, adapter->pdev)) 403 return IXGBE_FAILED_READ_CFG_DWORD; 404 return value; 405 } 406 #endif /* CONFIG_PCI_IOV */ 407 408 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 409 { 410 struct ixgbe_adapter *adapter = hw->back; 411 412 if (ixgbe_removed(hw->hw_addr)) 413 return; 414 pci_write_config_word(adapter->pdev, reg, value); 415 } 416 417 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 418 { 419 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 420 421 /* flush memory to make sure state is correct before next watchdog */ 422 smp_mb__before_atomic(); 423 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 424 } 425 426 struct ixgbe_reg_info { 427 u32 ofs; 428 char *name; 429 }; 430 431 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 432 433 /* General Registers */ 434 {IXGBE_CTRL, "CTRL"}, 435 {IXGBE_STATUS, "STATUS"}, 436 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 437 438 /* Interrupt Registers */ 439 {IXGBE_EICR, "EICR"}, 440 441 /* RX Registers */ 442 {IXGBE_SRRCTL(0), "SRRCTL"}, 443 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 444 {IXGBE_RDLEN(0), "RDLEN"}, 445 {IXGBE_RDH(0), "RDH"}, 446 {IXGBE_RDT(0), "RDT"}, 447 {IXGBE_RXDCTL(0), "RXDCTL"}, 448 {IXGBE_RDBAL(0), "RDBAL"}, 449 {IXGBE_RDBAH(0), "RDBAH"}, 450 451 /* TX Registers */ 452 {IXGBE_TDBAL(0), "TDBAL"}, 453 {IXGBE_TDBAH(0), "TDBAH"}, 454 {IXGBE_TDLEN(0), "TDLEN"}, 455 {IXGBE_TDH(0), "TDH"}, 456 {IXGBE_TDT(0), "TDT"}, 457 {IXGBE_TXDCTL(0), "TXDCTL"}, 458 459 /* List Terminator */ 460 { .name = NULL } 461 }; 462 463 464 /* 465 * ixgbe_regdump - register printout routine 466 */ 467 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 468 { 469 int i; 470 char rname[16]; 471 u32 regs[64]; 472 473 switch (reginfo->ofs) { 474 case IXGBE_SRRCTL(0): 475 for (i = 0; i < 64; i++) 476 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 477 break; 478 case IXGBE_DCA_RXCTRL(0): 479 for (i = 0; i < 64; i++) 480 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 481 break; 482 case IXGBE_RDLEN(0): 483 for (i = 0; i < 64; i++) 484 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 485 break; 486 case IXGBE_RDH(0): 487 for (i = 0; i < 64; i++) 488 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 489 break; 490 case IXGBE_RDT(0): 491 for (i = 0; i < 64; i++) 492 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 493 break; 494 case IXGBE_RXDCTL(0): 495 for (i = 0; i < 64; i++) 496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 497 break; 498 case IXGBE_RDBAL(0): 499 for (i = 0; i < 64; i++) 500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 501 break; 502 case IXGBE_RDBAH(0): 503 for (i = 0; i < 64; i++) 504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 505 break; 506 case IXGBE_TDBAL(0): 507 for (i = 0; i < 64; i++) 508 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 509 break; 510 case IXGBE_TDBAH(0): 511 for (i = 0; i < 64; i++) 512 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 513 break; 514 case IXGBE_TDLEN(0): 515 for (i = 0; i < 64; i++) 516 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 517 break; 518 case IXGBE_TDH(0): 519 for (i = 0; i < 64; i++) 520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 521 break; 522 case IXGBE_TDT(0): 523 for (i = 0; i < 64; i++) 524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 525 break; 526 case IXGBE_TXDCTL(0): 527 for (i = 0; i < 64; i++) 528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 529 break; 530 default: 531 pr_info("%-15s %08x\n", 532 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 533 return; 534 } 535 536 i = 0; 537 while (i < 64) { 538 int j; 539 char buf[9 * 8 + 1]; 540 char *p = buf; 541 542 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 543 for (j = 0; j < 8; j++) 544 p += sprintf(p, " %08x", regs[i++]); 545 pr_err("%-15s%s\n", rname, buf); 546 } 547 548 } 549 550 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 551 { 552 struct ixgbe_tx_buffer *tx_buffer; 553 554 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 555 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 556 n, ring->next_to_use, ring->next_to_clean, 557 (u64)dma_unmap_addr(tx_buffer, dma), 558 dma_unmap_len(tx_buffer, len), 559 tx_buffer->next_to_watch, 560 (u64)tx_buffer->time_stamp); 561 } 562 563 /* 564 * ixgbe_dump - Print registers, tx-rings and rx-rings 565 */ 566 static void ixgbe_dump(struct ixgbe_adapter *adapter) 567 { 568 struct net_device *netdev = adapter->netdev; 569 struct ixgbe_hw *hw = &adapter->hw; 570 struct ixgbe_reg_info *reginfo; 571 int n = 0; 572 struct ixgbe_ring *ring; 573 struct ixgbe_tx_buffer *tx_buffer; 574 union ixgbe_adv_tx_desc *tx_desc; 575 struct my_u0 { u64 a; u64 b; } *u0; 576 struct ixgbe_ring *rx_ring; 577 union ixgbe_adv_rx_desc *rx_desc; 578 struct ixgbe_rx_buffer *rx_buffer_info; 579 int i = 0; 580 581 if (!netif_msg_hw(adapter)) 582 return; 583 584 /* Print netdevice Info */ 585 if (netdev) { 586 dev_info(&adapter->pdev->dev, "Net device Info\n"); 587 pr_info("Device Name state " 588 "trans_start\n"); 589 pr_info("%-15s %016lX %016lX\n", 590 netdev->name, 591 netdev->state, 592 dev_trans_start(netdev)); 593 } 594 595 /* Print Registers */ 596 dev_info(&adapter->pdev->dev, "Register Dump\n"); 597 pr_info(" Register Name Value\n"); 598 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 599 reginfo->name; reginfo++) { 600 ixgbe_regdump(hw, reginfo); 601 } 602 603 /* Print TX Ring Summary */ 604 if (!netdev || !netif_running(netdev)) 605 return; 606 607 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 608 pr_info(" %s %s %s %s\n", 609 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 610 "leng", "ntw", "timestamp"); 611 for (n = 0; n < adapter->num_tx_queues; n++) { 612 ring = adapter->tx_ring[n]; 613 ixgbe_print_buffer(ring, n); 614 } 615 616 for (n = 0; n < adapter->num_xdp_queues; n++) { 617 ring = adapter->xdp_ring[n]; 618 ixgbe_print_buffer(ring, n); 619 } 620 621 /* Print TX Rings */ 622 if (!netif_msg_tx_done(adapter)) 623 goto rx_ring_summary; 624 625 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 626 627 /* Transmit Descriptor Formats 628 * 629 * 82598 Advanced Transmit Descriptor 630 * +--------------------------------------------------------------+ 631 * 0 | Buffer Address [63:0] | 632 * +--------------------------------------------------------------+ 633 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 634 * +--------------------------------------------------------------+ 635 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 636 * 637 * 82598 Advanced Transmit Descriptor (Write-Back Format) 638 * +--------------------------------------------------------------+ 639 * 0 | RSV [63:0] | 640 * +--------------------------------------------------------------+ 641 * 8 | RSV | STA | NXTSEQ | 642 * +--------------------------------------------------------------+ 643 * 63 36 35 32 31 0 644 * 645 * 82599+ Advanced Transmit Descriptor 646 * +--------------------------------------------------------------+ 647 * 0 | Buffer Address [63:0] | 648 * +--------------------------------------------------------------+ 649 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 650 * +--------------------------------------------------------------+ 651 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 652 * 653 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 654 * +--------------------------------------------------------------+ 655 * 0 | RSV [63:0] | 656 * +--------------------------------------------------------------+ 657 * 8 | RSV | STA | RSV | 658 * +--------------------------------------------------------------+ 659 * 63 36 35 32 31 0 660 */ 661 662 for (n = 0; n < adapter->num_tx_queues; n++) { 663 ring = adapter->tx_ring[n]; 664 pr_info("------------------------------------\n"); 665 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 666 pr_info("------------------------------------\n"); 667 pr_info("%s%s %s %s %s %s\n", 668 "T [desc] [address 63:0 ] ", 669 "[PlPOIdStDDt Ln] [bi->dma ] ", 670 "leng", "ntw", "timestamp", "bi->skb"); 671 672 for (i = 0; ring->desc && (i < ring->count); i++) { 673 tx_desc = IXGBE_TX_DESC(ring, i); 674 tx_buffer = &ring->tx_buffer_info[i]; 675 u0 = (struct my_u0 *)tx_desc; 676 if (dma_unmap_len(tx_buffer, len) > 0) { 677 const char *ring_desc; 678 679 if (i == ring->next_to_use && 680 i == ring->next_to_clean) 681 ring_desc = " NTC/U"; 682 else if (i == ring->next_to_use) 683 ring_desc = " NTU"; 684 else if (i == ring->next_to_clean) 685 ring_desc = " NTC"; 686 else 687 ring_desc = ""; 688 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 689 i, 690 le64_to_cpu((__force __le64)u0->a), 691 le64_to_cpu((__force __le64)u0->b), 692 (u64)dma_unmap_addr(tx_buffer, dma), 693 dma_unmap_len(tx_buffer, len), 694 tx_buffer->next_to_watch, 695 (u64)tx_buffer->time_stamp, 696 tx_buffer->skb, 697 ring_desc); 698 699 if (netif_msg_pktdata(adapter) && 700 tx_buffer->skb) 701 print_hex_dump(KERN_INFO, "", 702 DUMP_PREFIX_ADDRESS, 16, 1, 703 tx_buffer->skb->data, 704 dma_unmap_len(tx_buffer, len), 705 true); 706 } 707 } 708 } 709 710 /* Print RX Rings Summary */ 711 rx_ring_summary: 712 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 713 pr_info("Queue [NTU] [NTC]\n"); 714 for (n = 0; n < adapter->num_rx_queues; n++) { 715 rx_ring = adapter->rx_ring[n]; 716 pr_info("%5d %5X %5X\n", 717 n, rx_ring->next_to_use, rx_ring->next_to_clean); 718 } 719 720 /* Print RX Rings */ 721 if (!netif_msg_rx_status(adapter)) 722 return; 723 724 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 725 726 /* Receive Descriptor Formats 727 * 728 * 82598 Advanced Receive Descriptor (Read) Format 729 * 63 1 0 730 * +-----------------------------------------------------+ 731 * 0 | Packet Buffer Address [63:1] |A0/NSE| 732 * +----------------------------------------------+------+ 733 * 8 | Header Buffer Address [63:1] | DD | 734 * +-----------------------------------------------------+ 735 * 736 * 737 * 82598 Advanced Receive Descriptor (Write-Back) Format 738 * 739 * 63 48 47 32 31 30 21 20 16 15 4 3 0 740 * +------------------------------------------------------+ 741 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 742 * | Packet | IP | | | | Type | Type | 743 * | Checksum | Ident | | | | | | 744 * +------------------------------------------------------+ 745 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 746 * +------------------------------------------------------+ 747 * 63 48 47 32 31 20 19 0 748 * 749 * 82599+ Advanced Receive Descriptor (Read) Format 750 * 63 1 0 751 * +-----------------------------------------------------+ 752 * 0 | Packet Buffer Address [63:1] |A0/NSE| 753 * +----------------------------------------------+------+ 754 * 8 | Header Buffer Address [63:1] | DD | 755 * +-----------------------------------------------------+ 756 * 757 * 758 * 82599+ Advanced Receive Descriptor (Write-Back) Format 759 * 760 * 63 48 47 32 31 30 21 20 17 16 4 3 0 761 * +------------------------------------------------------+ 762 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 763 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 764 * |/ Flow Dir Flt ID | | | | | | 765 * +------------------------------------------------------+ 766 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 767 * +------------------------------------------------------+ 768 * 63 48 47 32 31 20 19 0 769 */ 770 771 for (n = 0; n < adapter->num_rx_queues; n++) { 772 rx_ring = adapter->rx_ring[n]; 773 pr_info("------------------------------------\n"); 774 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 775 pr_info("------------------------------------\n"); 776 pr_info("%s%s%s\n", 777 "R [desc] [ PktBuf A0] ", 778 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 779 "<-- Adv Rx Read format"); 780 pr_info("%s%s%s\n", 781 "RWB[desc] [PcsmIpSHl PtRs] ", 782 "[vl er S cks ln] ---------------- [bi->skb ] ", 783 "<-- Adv Rx Write-Back format"); 784 785 for (i = 0; i < rx_ring->count; i++) { 786 const char *ring_desc; 787 788 if (i == rx_ring->next_to_use) 789 ring_desc = " NTU"; 790 else if (i == rx_ring->next_to_clean) 791 ring_desc = " NTC"; 792 else 793 ring_desc = ""; 794 795 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 796 rx_desc = IXGBE_RX_DESC(rx_ring, i); 797 u0 = (struct my_u0 *)rx_desc; 798 if (rx_desc->wb.upper.length) { 799 /* Descriptor Done */ 800 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 801 i, 802 le64_to_cpu((__force __le64)u0->a), 803 le64_to_cpu((__force __le64)u0->b), 804 rx_buffer_info->skb, 805 ring_desc); 806 } else { 807 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 808 i, 809 le64_to_cpu((__force __le64)u0->a), 810 le64_to_cpu((__force __le64)u0->b), 811 (u64)rx_buffer_info->dma, 812 rx_buffer_info->skb, 813 ring_desc); 814 815 if (netif_msg_pktdata(adapter) && 816 rx_buffer_info->dma) { 817 print_hex_dump(KERN_INFO, "", 818 DUMP_PREFIX_ADDRESS, 16, 1, 819 page_address(rx_buffer_info->page) + 820 rx_buffer_info->page_offset, 821 ixgbe_rx_bufsz(rx_ring), true); 822 } 823 } 824 } 825 } 826 } 827 828 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 829 { 830 u32 ctrl_ext; 831 832 /* Let firmware take over control of h/w */ 833 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 835 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 836 } 837 838 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 839 { 840 u32 ctrl_ext; 841 842 /* Let firmware know the driver has taken over */ 843 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 845 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 846 } 847 848 /** 849 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 850 * @adapter: pointer to adapter struct 851 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 852 * @queue: queue to map the corresponding interrupt to 853 * @msix_vector: the vector to map to the corresponding queue 854 * 855 */ 856 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 857 u8 queue, u8 msix_vector) 858 { 859 u32 ivar, index; 860 struct ixgbe_hw *hw = &adapter->hw; 861 switch (hw->mac.type) { 862 case ixgbe_mac_82598EB: 863 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 864 if (direction == -1) 865 direction = 0; 866 index = (((direction * 64) + queue) >> 2) & 0x1F; 867 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 868 ivar &= ~(0xFF << (8 * (queue & 0x3))); 869 ivar |= (msix_vector << (8 * (queue & 0x3))); 870 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 871 break; 872 case ixgbe_mac_82599EB: 873 case ixgbe_mac_X540: 874 case ixgbe_mac_X550: 875 case ixgbe_mac_X550EM_x: 876 case ixgbe_mac_x550em_a: 877 if (direction == -1) { 878 /* other causes */ 879 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 880 index = ((queue & 1) * 8); 881 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 882 ivar &= ~(0xFF << index); 883 ivar |= (msix_vector << index); 884 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 885 break; 886 } else { 887 /* tx or rx causes */ 888 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 889 index = ((16 * (queue & 1)) + (8 * direction)); 890 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 891 ivar &= ~(0xFF << index); 892 ivar |= (msix_vector << index); 893 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 894 break; 895 } 896 default: 897 break; 898 } 899 } 900 901 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 902 u64 qmask) 903 { 904 u32 mask; 905 906 switch (adapter->hw.mac.type) { 907 case ixgbe_mac_82598EB: 908 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 910 break; 911 case ixgbe_mac_82599EB: 912 case ixgbe_mac_X540: 913 case ixgbe_mac_X550: 914 case ixgbe_mac_X550EM_x: 915 case ixgbe_mac_x550em_a: 916 mask = (qmask & 0xFFFFFFFF); 917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 918 mask = (qmask >> 32); 919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 920 break; 921 default: 922 break; 923 } 924 } 925 926 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 927 { 928 struct ixgbe_hw *hw = &adapter->hw; 929 struct ixgbe_hw_stats *hwstats = &adapter->stats; 930 int i; 931 u32 data; 932 933 if ((hw->fc.current_mode != ixgbe_fc_full) && 934 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 935 return; 936 937 switch (hw->mac.type) { 938 case ixgbe_mac_82598EB: 939 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 940 break; 941 default: 942 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 943 } 944 hwstats->lxoffrxc += data; 945 946 /* refill credits (no tx hang) if we received xoff */ 947 if (!data) 948 return; 949 950 for (i = 0; i < adapter->num_tx_queues; i++) 951 clear_bit(__IXGBE_HANG_CHECK_ARMED, 952 &adapter->tx_ring[i]->state); 953 954 for (i = 0; i < adapter->num_xdp_queues; i++) 955 clear_bit(__IXGBE_HANG_CHECK_ARMED, 956 &adapter->xdp_ring[i]->state); 957 } 958 959 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 960 { 961 struct ixgbe_hw *hw = &adapter->hw; 962 struct ixgbe_hw_stats *hwstats = &adapter->stats; 963 u32 xoff[8] = {0}; 964 u8 tc; 965 int i; 966 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 967 968 if (adapter->ixgbe_ieee_pfc) 969 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 970 971 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 972 ixgbe_update_xoff_rx_lfc(adapter); 973 return; 974 } 975 976 /* update stats for each tc, only valid with PFC enabled */ 977 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 978 u32 pxoffrxc; 979 980 switch (hw->mac.type) { 981 case ixgbe_mac_82598EB: 982 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 983 break; 984 default: 985 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 986 } 987 hwstats->pxoffrxc[i] += pxoffrxc; 988 /* Get the TC for given UP */ 989 tc = netdev_get_prio_tc_map(adapter->netdev, i); 990 xoff[tc] += pxoffrxc; 991 } 992 993 /* disarm tx queues that have received xoff frames */ 994 for (i = 0; i < adapter->num_tx_queues; i++) { 995 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 996 997 tc = tx_ring->dcb_tc; 998 if (xoff[tc]) 999 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1000 } 1001 1002 for (i = 0; i < adapter->num_xdp_queues; i++) { 1003 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1004 1005 tc = xdp_ring->dcb_tc; 1006 if (xoff[tc]) 1007 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1008 } 1009 } 1010 1011 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1012 { 1013 return ring->stats.packets; 1014 } 1015 1016 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1017 { 1018 unsigned int head, tail; 1019 1020 head = ring->next_to_clean; 1021 tail = ring->next_to_use; 1022 1023 return ((head <= tail) ? tail : tail + ring->count) - head; 1024 } 1025 1026 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1027 { 1028 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1029 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1030 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1031 1032 clear_check_for_tx_hang(tx_ring); 1033 1034 /* 1035 * Check for a hung queue, but be thorough. This verifies 1036 * that a transmit has been completed since the previous 1037 * check AND there is at least one packet pending. The 1038 * ARMED bit is set to indicate a potential hang. The 1039 * bit is cleared if a pause frame is received to remove 1040 * false hang detection due to PFC or 802.3x frames. By 1041 * requiring this to fail twice we avoid races with 1042 * pfc clearing the ARMED bit and conditions where we 1043 * run the check_tx_hang logic with a transmit completion 1044 * pending but without time to complete it yet. 1045 */ 1046 if (tx_done_old == tx_done && tx_pending) 1047 /* make sure it is true for two checks in a row */ 1048 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1049 &tx_ring->state); 1050 /* update completed stats and continue */ 1051 tx_ring->tx_stats.tx_done_old = tx_done; 1052 /* reset the countdown */ 1053 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1054 1055 return false; 1056 } 1057 1058 /** 1059 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1060 * @adapter: driver private struct 1061 **/ 1062 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1063 { 1064 1065 /* Do the reset outside of interrupt context */ 1066 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1067 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1068 e_warn(drv, "initiating reset due to tx timeout\n"); 1069 ixgbe_service_event_schedule(adapter); 1070 } 1071 } 1072 1073 /** 1074 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1075 * @netdev: network interface device structure 1076 * @queue_index: Tx queue to set 1077 * @maxrate: desired maximum transmit bitrate 1078 **/ 1079 static int ixgbe_tx_maxrate(struct net_device *netdev, 1080 int queue_index, u32 maxrate) 1081 { 1082 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1083 struct ixgbe_hw *hw = &adapter->hw; 1084 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1085 1086 if (!maxrate) 1087 return 0; 1088 1089 /* Calculate the rate factor values to set */ 1090 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1091 bcnrc_val /= maxrate; 1092 1093 /* clear everything but the rate factor */ 1094 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1095 IXGBE_RTTBCNRC_RF_DEC_MASK; 1096 1097 /* enable the rate scheduler */ 1098 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1099 1100 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1101 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1102 1103 return 0; 1104 } 1105 1106 /** 1107 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1108 * @q_vector: structure containing interrupt and ring information 1109 * @tx_ring: tx ring to clean 1110 * @napi_budget: Used to determine if we are in netpoll 1111 **/ 1112 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1113 struct ixgbe_ring *tx_ring, int napi_budget) 1114 { 1115 struct ixgbe_adapter *adapter = q_vector->adapter; 1116 struct ixgbe_tx_buffer *tx_buffer; 1117 union ixgbe_adv_tx_desc *tx_desc; 1118 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1119 unsigned int budget = q_vector->tx.work_limit; 1120 unsigned int i = tx_ring->next_to_clean; 1121 1122 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1123 return true; 1124 1125 tx_buffer = &tx_ring->tx_buffer_info[i]; 1126 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1127 i -= tx_ring->count; 1128 1129 do { 1130 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1131 1132 /* if next_to_watch is not set then there is no work pending */ 1133 if (!eop_desc) 1134 break; 1135 1136 /* prevent any other reads prior to eop_desc */ 1137 smp_rmb(); 1138 1139 /* if DD is not set pending work has not been completed */ 1140 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1141 break; 1142 1143 /* clear next_to_watch to prevent false hangs */ 1144 tx_buffer->next_to_watch = NULL; 1145 1146 /* update the statistics for this packet */ 1147 total_bytes += tx_buffer->bytecount; 1148 total_packets += tx_buffer->gso_segs; 1149 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1150 total_ipsec++; 1151 1152 /* free the skb */ 1153 if (ring_is_xdp(tx_ring)) 1154 xdp_return_frame(tx_buffer->xdpf); 1155 else 1156 napi_consume_skb(tx_buffer->skb, napi_budget); 1157 1158 /* unmap skb header data */ 1159 dma_unmap_single(tx_ring->dev, 1160 dma_unmap_addr(tx_buffer, dma), 1161 dma_unmap_len(tx_buffer, len), 1162 DMA_TO_DEVICE); 1163 1164 /* clear tx_buffer data */ 1165 dma_unmap_len_set(tx_buffer, len, 0); 1166 1167 /* unmap remaining buffers */ 1168 while (tx_desc != eop_desc) { 1169 tx_buffer++; 1170 tx_desc++; 1171 i++; 1172 if (unlikely(!i)) { 1173 i -= tx_ring->count; 1174 tx_buffer = tx_ring->tx_buffer_info; 1175 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1176 } 1177 1178 /* unmap any remaining paged data */ 1179 if (dma_unmap_len(tx_buffer, len)) { 1180 dma_unmap_page(tx_ring->dev, 1181 dma_unmap_addr(tx_buffer, dma), 1182 dma_unmap_len(tx_buffer, len), 1183 DMA_TO_DEVICE); 1184 dma_unmap_len_set(tx_buffer, len, 0); 1185 } 1186 } 1187 1188 /* move us one more past the eop_desc for start of next pkt */ 1189 tx_buffer++; 1190 tx_desc++; 1191 i++; 1192 if (unlikely(!i)) { 1193 i -= tx_ring->count; 1194 tx_buffer = tx_ring->tx_buffer_info; 1195 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1196 } 1197 1198 /* issue prefetch for next Tx descriptor */ 1199 prefetch(tx_desc); 1200 1201 /* update budget accounting */ 1202 budget--; 1203 } while (likely(budget)); 1204 1205 i += tx_ring->count; 1206 tx_ring->next_to_clean = i; 1207 u64_stats_update_begin(&tx_ring->syncp); 1208 tx_ring->stats.bytes += total_bytes; 1209 tx_ring->stats.packets += total_packets; 1210 u64_stats_update_end(&tx_ring->syncp); 1211 q_vector->tx.total_bytes += total_bytes; 1212 q_vector->tx.total_packets += total_packets; 1213 adapter->tx_ipsec += total_ipsec; 1214 1215 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1216 /* schedule immediate reset if we believe we hung */ 1217 struct ixgbe_hw *hw = &adapter->hw; 1218 e_err(drv, "Detected Tx Unit Hang %s\n" 1219 " Tx Queue <%d>\n" 1220 " TDH, TDT <%x>, <%x>\n" 1221 " next_to_use <%x>\n" 1222 " next_to_clean <%x>\n" 1223 "tx_buffer_info[next_to_clean]\n" 1224 " time_stamp <%lx>\n" 1225 " jiffies <%lx>\n", 1226 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1227 tx_ring->queue_index, 1228 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1229 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1230 tx_ring->next_to_use, i, 1231 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1232 1233 if (!ring_is_xdp(tx_ring)) 1234 netif_stop_subqueue(tx_ring->netdev, 1235 tx_ring->queue_index); 1236 1237 e_info(probe, 1238 "tx hang %d detected on queue %d, resetting adapter\n", 1239 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1240 1241 /* schedule immediate reset if we believe we hung */ 1242 ixgbe_tx_timeout_reset(adapter); 1243 1244 /* the adapter is about to reset, no point in enabling stuff */ 1245 return true; 1246 } 1247 1248 if (ring_is_xdp(tx_ring)) 1249 return !!budget; 1250 1251 netdev_tx_completed_queue(txring_txq(tx_ring), 1252 total_packets, total_bytes); 1253 1254 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1255 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1256 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1257 /* Make sure that anybody stopping the queue after this 1258 * sees the new next_to_clean. 1259 */ 1260 smp_mb(); 1261 if (__netif_subqueue_stopped(tx_ring->netdev, 1262 tx_ring->queue_index) 1263 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1264 netif_wake_subqueue(tx_ring->netdev, 1265 tx_ring->queue_index); 1266 ++tx_ring->tx_stats.restart_queue; 1267 } 1268 } 1269 1270 return !!budget; 1271 } 1272 1273 #ifdef CONFIG_IXGBE_DCA 1274 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1275 struct ixgbe_ring *tx_ring, 1276 int cpu) 1277 { 1278 struct ixgbe_hw *hw = &adapter->hw; 1279 u32 txctrl = 0; 1280 u16 reg_offset; 1281 1282 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1283 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1284 1285 switch (hw->mac.type) { 1286 case ixgbe_mac_82598EB: 1287 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1288 break; 1289 case ixgbe_mac_82599EB: 1290 case ixgbe_mac_X540: 1291 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1292 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1293 break; 1294 default: 1295 /* for unknown hardware do not write register */ 1296 return; 1297 } 1298 1299 /* 1300 * We can enable relaxed ordering for reads, but not writes when 1301 * DCA is enabled. This is due to a known issue in some chipsets 1302 * which will cause the DCA tag to be cleared. 1303 */ 1304 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1305 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1306 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1307 1308 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1309 } 1310 1311 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1312 struct ixgbe_ring *rx_ring, 1313 int cpu) 1314 { 1315 struct ixgbe_hw *hw = &adapter->hw; 1316 u32 rxctrl = 0; 1317 u8 reg_idx = rx_ring->reg_idx; 1318 1319 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1320 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1321 1322 switch (hw->mac.type) { 1323 case ixgbe_mac_82599EB: 1324 case ixgbe_mac_X540: 1325 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1326 break; 1327 default: 1328 break; 1329 } 1330 1331 /* 1332 * We can enable relaxed ordering for reads, but not writes when 1333 * DCA is enabled. This is due to a known issue in some chipsets 1334 * which will cause the DCA tag to be cleared. 1335 */ 1336 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1337 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1338 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1339 1340 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1341 } 1342 1343 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1344 { 1345 struct ixgbe_adapter *adapter = q_vector->adapter; 1346 struct ixgbe_ring *ring; 1347 int cpu = get_cpu(); 1348 1349 if (q_vector->cpu == cpu) 1350 goto out_no_update; 1351 1352 ixgbe_for_each_ring(ring, q_vector->tx) 1353 ixgbe_update_tx_dca(adapter, ring, cpu); 1354 1355 ixgbe_for_each_ring(ring, q_vector->rx) 1356 ixgbe_update_rx_dca(adapter, ring, cpu); 1357 1358 q_vector->cpu = cpu; 1359 out_no_update: 1360 put_cpu(); 1361 } 1362 1363 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1364 { 1365 int i; 1366 1367 /* always use CB2 mode, difference is masked in the CB driver */ 1368 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1369 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1370 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1371 else 1372 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1373 IXGBE_DCA_CTRL_DCA_DISABLE); 1374 1375 for (i = 0; i < adapter->num_q_vectors; i++) { 1376 adapter->q_vector[i]->cpu = -1; 1377 ixgbe_update_dca(adapter->q_vector[i]); 1378 } 1379 } 1380 1381 static int __ixgbe_notify_dca(struct device *dev, void *data) 1382 { 1383 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1384 unsigned long event = *(unsigned long *)data; 1385 1386 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1387 return 0; 1388 1389 switch (event) { 1390 case DCA_PROVIDER_ADD: 1391 /* if we're already enabled, don't do it again */ 1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1393 break; 1394 if (dca_add_requester(dev) == 0) { 1395 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1397 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1398 break; 1399 } 1400 /* fall through - DCA is disabled. */ 1401 case DCA_PROVIDER_REMOVE: 1402 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1403 dca_remove_requester(dev); 1404 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1405 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1406 IXGBE_DCA_CTRL_DCA_DISABLE); 1407 } 1408 break; 1409 } 1410 1411 return 0; 1412 } 1413 1414 #endif /* CONFIG_IXGBE_DCA */ 1415 1416 #define IXGBE_RSS_L4_TYPES_MASK \ 1417 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1419 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1420 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1421 1422 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1423 union ixgbe_adv_rx_desc *rx_desc, 1424 struct sk_buff *skb) 1425 { 1426 u16 rss_type; 1427 1428 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1429 return; 1430 1431 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1432 IXGBE_RXDADV_RSSTYPE_MASK; 1433 1434 if (!rss_type) 1435 return; 1436 1437 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1438 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1439 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1440 } 1441 1442 #ifdef IXGBE_FCOE 1443 /** 1444 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1445 * @ring: structure containing ring specific data 1446 * @rx_desc: advanced rx descriptor 1447 * 1448 * Returns : true if it is FCoE pkt 1449 */ 1450 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1451 union ixgbe_adv_rx_desc *rx_desc) 1452 { 1453 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1454 1455 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1456 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1457 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1458 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1459 } 1460 1461 #endif /* IXGBE_FCOE */ 1462 /** 1463 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1464 * @ring: structure containing ring specific data 1465 * @rx_desc: current Rx descriptor being processed 1466 * @skb: skb currently being received and modified 1467 **/ 1468 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1469 union ixgbe_adv_rx_desc *rx_desc, 1470 struct sk_buff *skb) 1471 { 1472 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1473 bool encap_pkt = false; 1474 1475 skb_checksum_none_assert(skb); 1476 1477 /* Rx csum disabled */ 1478 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1479 return; 1480 1481 /* check for VXLAN and Geneve packets */ 1482 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1483 encap_pkt = true; 1484 skb->encapsulation = 1; 1485 } 1486 1487 /* if IP and error */ 1488 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1489 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1490 ring->rx_stats.csum_err++; 1491 return; 1492 } 1493 1494 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1495 return; 1496 1497 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1498 /* 1499 * 82599 errata, UDP frames with a 0 checksum can be marked as 1500 * checksum errors. 1501 */ 1502 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1503 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1504 return; 1505 1506 ring->rx_stats.csum_err++; 1507 return; 1508 } 1509 1510 /* It must be a TCP or UDP packet with a valid checksum */ 1511 skb->ip_summed = CHECKSUM_UNNECESSARY; 1512 if (encap_pkt) { 1513 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1514 return; 1515 1516 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1517 skb->ip_summed = CHECKSUM_NONE; 1518 return; 1519 } 1520 /* If we checked the outer header let the stack know */ 1521 skb->csum_level = 1; 1522 } 1523 } 1524 1525 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1526 { 1527 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1528 } 1529 1530 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1531 struct ixgbe_rx_buffer *bi) 1532 { 1533 struct page *page = bi->page; 1534 dma_addr_t dma; 1535 1536 /* since we are recycling buffers we should seldom need to alloc */ 1537 if (likely(page)) 1538 return true; 1539 1540 /* alloc new page for storage */ 1541 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1542 if (unlikely(!page)) { 1543 rx_ring->rx_stats.alloc_rx_page_failed++; 1544 return false; 1545 } 1546 1547 /* map page for use */ 1548 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1549 ixgbe_rx_pg_size(rx_ring), 1550 DMA_FROM_DEVICE, 1551 IXGBE_RX_DMA_ATTR); 1552 1553 /* 1554 * if mapping failed free memory back to system since 1555 * there isn't much point in holding memory we can't use 1556 */ 1557 if (dma_mapping_error(rx_ring->dev, dma)) { 1558 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1559 1560 rx_ring->rx_stats.alloc_rx_page_failed++; 1561 return false; 1562 } 1563 1564 bi->dma = dma; 1565 bi->page = page; 1566 bi->page_offset = ixgbe_rx_offset(rx_ring); 1567 page_ref_add(page, USHRT_MAX - 1); 1568 bi->pagecnt_bias = USHRT_MAX; 1569 rx_ring->rx_stats.alloc_rx_page++; 1570 1571 return true; 1572 } 1573 1574 /** 1575 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1576 * @rx_ring: ring to place buffers on 1577 * @cleaned_count: number of buffers to replace 1578 **/ 1579 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1580 { 1581 union ixgbe_adv_rx_desc *rx_desc; 1582 struct ixgbe_rx_buffer *bi; 1583 u16 i = rx_ring->next_to_use; 1584 u16 bufsz; 1585 1586 /* nothing to do */ 1587 if (!cleaned_count) 1588 return; 1589 1590 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1591 bi = &rx_ring->rx_buffer_info[i]; 1592 i -= rx_ring->count; 1593 1594 bufsz = ixgbe_rx_bufsz(rx_ring); 1595 1596 do { 1597 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1598 break; 1599 1600 /* sync the buffer for use by the device */ 1601 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1602 bi->page_offset, bufsz, 1603 DMA_FROM_DEVICE); 1604 1605 /* 1606 * Refresh the desc even if buffer_addrs didn't change 1607 * because each write-back erases this info. 1608 */ 1609 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1610 1611 rx_desc++; 1612 bi++; 1613 i++; 1614 if (unlikely(!i)) { 1615 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1616 bi = rx_ring->rx_buffer_info; 1617 i -= rx_ring->count; 1618 } 1619 1620 /* clear the length for the next_to_use descriptor */ 1621 rx_desc->wb.upper.length = 0; 1622 1623 cleaned_count--; 1624 } while (cleaned_count); 1625 1626 i += rx_ring->count; 1627 1628 if (rx_ring->next_to_use != i) { 1629 rx_ring->next_to_use = i; 1630 1631 /* update next to alloc since we have filled the ring */ 1632 rx_ring->next_to_alloc = i; 1633 1634 /* Force memory writes to complete before letting h/w 1635 * know there are new descriptors to fetch. (Only 1636 * applicable for weak-ordered memory model archs, 1637 * such as IA-64). 1638 */ 1639 wmb(); 1640 writel(i, rx_ring->tail); 1641 } 1642 } 1643 1644 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1645 struct sk_buff *skb) 1646 { 1647 u16 hdr_len = skb_headlen(skb); 1648 1649 /* set gso_size to avoid messing up TCP MSS */ 1650 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1651 IXGBE_CB(skb)->append_cnt); 1652 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1653 } 1654 1655 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1656 struct sk_buff *skb) 1657 { 1658 /* if append_cnt is 0 then frame is not RSC */ 1659 if (!IXGBE_CB(skb)->append_cnt) 1660 return; 1661 1662 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1663 rx_ring->rx_stats.rsc_flush++; 1664 1665 ixgbe_set_rsc_gso_size(rx_ring, skb); 1666 1667 /* gso_size is computed using append_cnt so always clear it last */ 1668 IXGBE_CB(skb)->append_cnt = 0; 1669 } 1670 1671 /** 1672 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1673 * @rx_ring: rx descriptor ring packet is being transacted on 1674 * @rx_desc: pointer to the EOP Rx descriptor 1675 * @skb: pointer to current skb being populated 1676 * 1677 * This function checks the ring, descriptor, and packet information in 1678 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1679 * other fields within the skb. 1680 **/ 1681 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1682 union ixgbe_adv_rx_desc *rx_desc, 1683 struct sk_buff *skb) 1684 { 1685 struct net_device *dev = rx_ring->netdev; 1686 u32 flags = rx_ring->q_vector->adapter->flags; 1687 1688 ixgbe_update_rsc_stats(rx_ring, skb); 1689 1690 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1691 1692 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1693 1694 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1695 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1696 1697 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1698 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1699 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1700 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1701 } 1702 1703 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1704 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1705 1706 /* record Rx queue, or update MACVLAN statistics */ 1707 if (netif_is_ixgbe(dev)) 1708 skb_record_rx_queue(skb, rx_ring->queue_index); 1709 else 1710 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1711 false); 1712 1713 skb->protocol = eth_type_trans(skb, dev); 1714 } 1715 1716 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1717 struct sk_buff *skb) 1718 { 1719 napi_gro_receive(&q_vector->napi, skb); 1720 } 1721 1722 /** 1723 * ixgbe_is_non_eop - process handling of non-EOP buffers 1724 * @rx_ring: Rx ring being processed 1725 * @rx_desc: Rx descriptor for current buffer 1726 * @skb: Current socket buffer containing buffer in progress 1727 * 1728 * This function updates next to clean. If the buffer is an EOP buffer 1729 * this function exits returning false, otherwise it will place the 1730 * sk_buff in the next buffer to be chained and return true indicating 1731 * that this is in fact a non-EOP buffer. 1732 **/ 1733 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1734 union ixgbe_adv_rx_desc *rx_desc, 1735 struct sk_buff *skb) 1736 { 1737 u32 ntc = rx_ring->next_to_clean + 1; 1738 1739 /* fetch, update, and store next to clean */ 1740 ntc = (ntc < rx_ring->count) ? ntc : 0; 1741 rx_ring->next_to_clean = ntc; 1742 1743 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1744 1745 /* update RSC append count if present */ 1746 if (ring_is_rsc_enabled(rx_ring)) { 1747 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1748 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1749 1750 if (unlikely(rsc_enabled)) { 1751 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1752 1753 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1754 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1755 1756 /* update ntc based on RSC value */ 1757 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1758 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1759 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1760 } 1761 } 1762 1763 /* if we are the last buffer then there is nothing else to do */ 1764 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1765 return false; 1766 1767 /* place skb in next buffer to be received */ 1768 rx_ring->rx_buffer_info[ntc].skb = skb; 1769 rx_ring->rx_stats.non_eop_descs++; 1770 1771 return true; 1772 } 1773 1774 /** 1775 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1776 * @rx_ring: rx descriptor ring packet is being transacted on 1777 * @skb: pointer to current skb being adjusted 1778 * 1779 * This function is an ixgbe specific version of __pskb_pull_tail. The 1780 * main difference between this version and the original function is that 1781 * this function can make several assumptions about the state of things 1782 * that allow for significant optimizations versus the standard function. 1783 * As a result we can do things like drop a frag and maintain an accurate 1784 * truesize for the skb. 1785 */ 1786 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1787 struct sk_buff *skb) 1788 { 1789 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1790 unsigned char *va; 1791 unsigned int pull_len; 1792 1793 /* 1794 * it is valid to use page_address instead of kmap since we are 1795 * working with pages allocated out of the lomem pool per 1796 * alloc_page(GFP_ATOMIC) 1797 */ 1798 va = skb_frag_address(frag); 1799 1800 /* 1801 * we need the header to contain the greater of either ETH_HLEN or 1802 * 60 bytes if the skb->len is less than 60 for skb_pad. 1803 */ 1804 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1805 1806 /* align pull length to size of long to optimize memcpy performance */ 1807 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1808 1809 /* update all of the pointers */ 1810 skb_frag_size_sub(frag, pull_len); 1811 skb_frag_off_add(frag, pull_len); 1812 skb->data_len -= pull_len; 1813 skb->tail += pull_len; 1814 } 1815 1816 /** 1817 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1818 * @rx_ring: rx descriptor ring packet is being transacted on 1819 * @skb: pointer to current skb being updated 1820 * 1821 * This function provides a basic DMA sync up for the first fragment of an 1822 * skb. The reason for doing this is that the first fragment cannot be 1823 * unmapped until we have reached the end of packet descriptor for a buffer 1824 * chain. 1825 */ 1826 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1827 struct sk_buff *skb) 1828 { 1829 if (ring_uses_build_skb(rx_ring)) { 1830 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1831 1832 dma_sync_single_range_for_cpu(rx_ring->dev, 1833 IXGBE_CB(skb)->dma, 1834 offset, 1835 skb_headlen(skb), 1836 DMA_FROM_DEVICE); 1837 } else { 1838 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1839 1840 dma_sync_single_range_for_cpu(rx_ring->dev, 1841 IXGBE_CB(skb)->dma, 1842 skb_frag_off(frag), 1843 skb_frag_size(frag), 1844 DMA_FROM_DEVICE); 1845 } 1846 1847 /* If the page was released, just unmap it. */ 1848 if (unlikely(IXGBE_CB(skb)->page_released)) { 1849 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1850 ixgbe_rx_pg_size(rx_ring), 1851 DMA_FROM_DEVICE, 1852 IXGBE_RX_DMA_ATTR); 1853 } 1854 } 1855 1856 /** 1857 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1858 * @rx_ring: rx descriptor ring packet is being transacted on 1859 * @rx_desc: pointer to the EOP Rx descriptor 1860 * @skb: pointer to current skb being fixed 1861 * 1862 * Check if the skb is valid in the XDP case it will be an error pointer. 1863 * Return true in this case to abort processing and advance to next 1864 * descriptor. 1865 * 1866 * Check for corrupted packet headers caused by senders on the local L2 1867 * embedded NIC switch not setting up their Tx Descriptors right. These 1868 * should be very rare. 1869 * 1870 * Also address the case where we are pulling data in on pages only 1871 * and as such no data is present in the skb header. 1872 * 1873 * In addition if skb is not at least 60 bytes we need to pad it so that 1874 * it is large enough to qualify as a valid Ethernet frame. 1875 * 1876 * Returns true if an error was encountered and skb was freed. 1877 **/ 1878 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1879 union ixgbe_adv_rx_desc *rx_desc, 1880 struct sk_buff *skb) 1881 { 1882 struct net_device *netdev = rx_ring->netdev; 1883 1884 /* XDP packets use error pointer so abort at this point */ 1885 if (IS_ERR(skb)) 1886 return true; 1887 1888 /* Verify netdev is present, and that packet does not have any 1889 * errors that would be unacceptable to the netdev. 1890 */ 1891 if (!netdev || 1892 (unlikely(ixgbe_test_staterr(rx_desc, 1893 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1894 !(netdev->features & NETIF_F_RXALL)))) { 1895 dev_kfree_skb_any(skb); 1896 return true; 1897 } 1898 1899 /* place header in linear portion of buffer */ 1900 if (!skb_headlen(skb)) 1901 ixgbe_pull_tail(rx_ring, skb); 1902 1903 #ifdef IXGBE_FCOE 1904 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1905 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1906 return false; 1907 1908 #endif 1909 /* if eth_skb_pad returns an error the skb was freed */ 1910 if (eth_skb_pad(skb)) 1911 return true; 1912 1913 return false; 1914 } 1915 1916 /** 1917 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1918 * @rx_ring: rx descriptor ring to store buffers on 1919 * @old_buff: donor buffer to have page reused 1920 * 1921 * Synchronizes page for reuse by the adapter 1922 **/ 1923 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1924 struct ixgbe_rx_buffer *old_buff) 1925 { 1926 struct ixgbe_rx_buffer *new_buff; 1927 u16 nta = rx_ring->next_to_alloc; 1928 1929 new_buff = &rx_ring->rx_buffer_info[nta]; 1930 1931 /* update, and store next to alloc */ 1932 nta++; 1933 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1934 1935 /* Transfer page from old buffer to new buffer. 1936 * Move each member individually to avoid possible store 1937 * forwarding stalls and unnecessary copy of skb. 1938 */ 1939 new_buff->dma = old_buff->dma; 1940 new_buff->page = old_buff->page; 1941 new_buff->page_offset = old_buff->page_offset; 1942 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1943 } 1944 1945 static inline bool ixgbe_page_is_reserved(struct page *page) 1946 { 1947 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1948 } 1949 1950 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1951 { 1952 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1953 struct page *page = rx_buffer->page; 1954 1955 /* avoid re-using remote pages */ 1956 if (unlikely(ixgbe_page_is_reserved(page))) 1957 return false; 1958 1959 #if (PAGE_SIZE < 8192) 1960 /* if we are only owner of page we can reuse it */ 1961 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1962 return false; 1963 #else 1964 /* The last offset is a bit aggressive in that we assume the 1965 * worst case of FCoE being enabled and using a 3K buffer. 1966 * However this should have minimal impact as the 1K extra is 1967 * still less than one buffer in size. 1968 */ 1969 #define IXGBE_LAST_OFFSET \ 1970 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1971 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1972 return false; 1973 #endif 1974 1975 /* If we have drained the page fragment pool we need to update 1976 * the pagecnt_bias and page count so that we fully restock the 1977 * number of references the driver holds. 1978 */ 1979 if (unlikely(pagecnt_bias == 1)) { 1980 page_ref_add(page, USHRT_MAX - 1); 1981 rx_buffer->pagecnt_bias = USHRT_MAX; 1982 } 1983 1984 return true; 1985 } 1986 1987 /** 1988 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1989 * @rx_ring: rx descriptor ring to transact packets on 1990 * @rx_buffer: buffer containing page to add 1991 * @skb: sk_buff to place the data into 1992 * @size: size of data in rx_buffer 1993 * 1994 * This function will add the data contained in rx_buffer->page to the skb. 1995 * This is done either through a direct copy if the data in the buffer is 1996 * less than the skb header size, otherwise it will just attach the page as 1997 * a frag to the skb. 1998 * 1999 * The function will then update the page offset if necessary and return 2000 * true if the buffer can be reused by the adapter. 2001 **/ 2002 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2003 struct ixgbe_rx_buffer *rx_buffer, 2004 struct sk_buff *skb, 2005 unsigned int size) 2006 { 2007 #if (PAGE_SIZE < 8192) 2008 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2009 #else 2010 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2011 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2012 SKB_DATA_ALIGN(size); 2013 #endif 2014 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2015 rx_buffer->page_offset, size, truesize); 2016 #if (PAGE_SIZE < 8192) 2017 rx_buffer->page_offset ^= truesize; 2018 #else 2019 rx_buffer->page_offset += truesize; 2020 #endif 2021 } 2022 2023 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2024 union ixgbe_adv_rx_desc *rx_desc, 2025 struct sk_buff **skb, 2026 const unsigned int size) 2027 { 2028 struct ixgbe_rx_buffer *rx_buffer; 2029 2030 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2031 prefetchw(rx_buffer->page); 2032 *skb = rx_buffer->skb; 2033 2034 /* Delay unmapping of the first packet. It carries the header 2035 * information, HW may still access the header after the writeback. 2036 * Only unmap it when EOP is reached 2037 */ 2038 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2039 if (!*skb) 2040 goto skip_sync; 2041 } else { 2042 if (*skb) 2043 ixgbe_dma_sync_frag(rx_ring, *skb); 2044 } 2045 2046 /* we are reusing so sync this buffer for CPU use */ 2047 dma_sync_single_range_for_cpu(rx_ring->dev, 2048 rx_buffer->dma, 2049 rx_buffer->page_offset, 2050 size, 2051 DMA_FROM_DEVICE); 2052 skip_sync: 2053 rx_buffer->pagecnt_bias--; 2054 2055 return rx_buffer; 2056 } 2057 2058 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2059 struct ixgbe_rx_buffer *rx_buffer, 2060 struct sk_buff *skb) 2061 { 2062 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2063 /* hand second half of page back to the ring */ 2064 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2065 } else { 2066 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2067 /* the page has been released from the ring */ 2068 IXGBE_CB(skb)->page_released = true; 2069 } else { 2070 /* we are not reusing the buffer so unmap it */ 2071 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2072 ixgbe_rx_pg_size(rx_ring), 2073 DMA_FROM_DEVICE, 2074 IXGBE_RX_DMA_ATTR); 2075 } 2076 __page_frag_cache_drain(rx_buffer->page, 2077 rx_buffer->pagecnt_bias); 2078 } 2079 2080 /* clear contents of rx_buffer */ 2081 rx_buffer->page = NULL; 2082 rx_buffer->skb = NULL; 2083 } 2084 2085 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2086 struct ixgbe_rx_buffer *rx_buffer, 2087 struct xdp_buff *xdp, 2088 union ixgbe_adv_rx_desc *rx_desc) 2089 { 2090 unsigned int size = xdp->data_end - xdp->data; 2091 #if (PAGE_SIZE < 8192) 2092 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2093 #else 2094 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2095 xdp->data_hard_start); 2096 #endif 2097 struct sk_buff *skb; 2098 2099 /* prefetch first cache line of first page */ 2100 prefetch(xdp->data); 2101 #if L1_CACHE_BYTES < 128 2102 prefetch(xdp->data + L1_CACHE_BYTES); 2103 #endif 2104 /* Note, we get here by enabling legacy-rx via: 2105 * 2106 * ethtool --set-priv-flags <dev> legacy-rx on 2107 * 2108 * In this mode, we currently get 0 extra XDP headroom as 2109 * opposed to having legacy-rx off, where we process XDP 2110 * packets going to stack via ixgbe_build_skb(). The latter 2111 * provides us currently with 192 bytes of headroom. 2112 * 2113 * For ixgbe_construct_skb() mode it means that the 2114 * xdp->data_meta will always point to xdp->data, since 2115 * the helper cannot expand the head. Should this ever 2116 * change in future for legacy-rx mode on, then lets also 2117 * add xdp->data_meta handling here. 2118 */ 2119 2120 /* allocate a skb to store the frags */ 2121 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2122 if (unlikely(!skb)) 2123 return NULL; 2124 2125 if (size > IXGBE_RX_HDR_SIZE) { 2126 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2127 IXGBE_CB(skb)->dma = rx_buffer->dma; 2128 2129 skb_add_rx_frag(skb, 0, rx_buffer->page, 2130 xdp->data - page_address(rx_buffer->page), 2131 size, truesize); 2132 #if (PAGE_SIZE < 8192) 2133 rx_buffer->page_offset ^= truesize; 2134 #else 2135 rx_buffer->page_offset += truesize; 2136 #endif 2137 } else { 2138 memcpy(__skb_put(skb, size), 2139 xdp->data, ALIGN(size, sizeof(long))); 2140 rx_buffer->pagecnt_bias++; 2141 } 2142 2143 return skb; 2144 } 2145 2146 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2147 struct ixgbe_rx_buffer *rx_buffer, 2148 struct xdp_buff *xdp, 2149 union ixgbe_adv_rx_desc *rx_desc) 2150 { 2151 unsigned int metasize = xdp->data - xdp->data_meta; 2152 #if (PAGE_SIZE < 8192) 2153 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2154 #else 2155 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2156 SKB_DATA_ALIGN(xdp->data_end - 2157 xdp->data_hard_start); 2158 #endif 2159 struct sk_buff *skb; 2160 2161 /* Prefetch first cache line of first page. If xdp->data_meta 2162 * is unused, this points extactly as xdp->data, otherwise we 2163 * likely have a consumer accessing first few bytes of meta 2164 * data, and then actual data. 2165 */ 2166 prefetch(xdp->data_meta); 2167 #if L1_CACHE_BYTES < 128 2168 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2169 #endif 2170 2171 /* build an skb to around the page buffer */ 2172 skb = build_skb(xdp->data_hard_start, truesize); 2173 if (unlikely(!skb)) 2174 return NULL; 2175 2176 /* update pointers within the skb to store the data */ 2177 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2178 __skb_put(skb, xdp->data_end - xdp->data); 2179 if (metasize) 2180 skb_metadata_set(skb, metasize); 2181 2182 /* record DMA address if this is the start of a chain of buffers */ 2183 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2184 IXGBE_CB(skb)->dma = rx_buffer->dma; 2185 2186 /* update buffer offset */ 2187 #if (PAGE_SIZE < 8192) 2188 rx_buffer->page_offset ^= truesize; 2189 #else 2190 rx_buffer->page_offset += truesize; 2191 #endif 2192 2193 return skb; 2194 } 2195 2196 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2197 struct ixgbe_ring *rx_ring, 2198 struct xdp_buff *xdp) 2199 { 2200 int err, result = IXGBE_XDP_PASS; 2201 struct bpf_prog *xdp_prog; 2202 struct xdp_frame *xdpf; 2203 u32 act; 2204 2205 rcu_read_lock(); 2206 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2207 2208 if (!xdp_prog) 2209 goto xdp_out; 2210 2211 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2212 2213 act = bpf_prog_run_xdp(xdp_prog, xdp); 2214 switch (act) { 2215 case XDP_PASS: 2216 break; 2217 case XDP_TX: 2218 xdpf = convert_to_xdp_frame(xdp); 2219 if (unlikely(!xdpf)) { 2220 result = IXGBE_XDP_CONSUMED; 2221 break; 2222 } 2223 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2224 break; 2225 case XDP_REDIRECT: 2226 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2227 if (!err) 2228 result = IXGBE_XDP_REDIR; 2229 else 2230 result = IXGBE_XDP_CONSUMED; 2231 break; 2232 default: 2233 bpf_warn_invalid_xdp_action(act); 2234 /* fallthrough */ 2235 case XDP_ABORTED: 2236 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2237 /* fallthrough -- handle aborts by dropping packet */ 2238 case XDP_DROP: 2239 result = IXGBE_XDP_CONSUMED; 2240 break; 2241 } 2242 xdp_out: 2243 rcu_read_unlock(); 2244 return ERR_PTR(-result); 2245 } 2246 2247 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2248 struct ixgbe_rx_buffer *rx_buffer, 2249 unsigned int size) 2250 { 2251 #if (PAGE_SIZE < 8192) 2252 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2253 2254 rx_buffer->page_offset ^= truesize; 2255 #else 2256 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2257 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2258 SKB_DATA_ALIGN(size); 2259 2260 rx_buffer->page_offset += truesize; 2261 #endif 2262 } 2263 2264 /** 2265 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2266 * @q_vector: structure containing interrupt and ring information 2267 * @rx_ring: rx descriptor ring to transact packets on 2268 * @budget: Total limit on number of packets to process 2269 * 2270 * This function provides a "bounce buffer" approach to Rx interrupt 2271 * processing. The advantage to this is that on systems that have 2272 * expensive overhead for IOMMU access this provides a means of avoiding 2273 * it by maintaining the mapping of the page to the syste. 2274 * 2275 * Returns amount of work completed 2276 **/ 2277 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2278 struct ixgbe_ring *rx_ring, 2279 const int budget) 2280 { 2281 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2282 struct ixgbe_adapter *adapter = q_vector->adapter; 2283 #ifdef IXGBE_FCOE 2284 int ddp_bytes; 2285 unsigned int mss = 0; 2286 #endif /* IXGBE_FCOE */ 2287 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2288 unsigned int xdp_xmit = 0; 2289 struct xdp_buff xdp; 2290 2291 xdp.rxq = &rx_ring->xdp_rxq; 2292 2293 while (likely(total_rx_packets < budget)) { 2294 union ixgbe_adv_rx_desc *rx_desc; 2295 struct ixgbe_rx_buffer *rx_buffer; 2296 struct sk_buff *skb; 2297 unsigned int size; 2298 2299 /* return some buffers to hardware, one at a time is too slow */ 2300 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2301 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2302 cleaned_count = 0; 2303 } 2304 2305 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2306 size = le16_to_cpu(rx_desc->wb.upper.length); 2307 if (!size) 2308 break; 2309 2310 /* This memory barrier is needed to keep us from reading 2311 * any other fields out of the rx_desc until we know the 2312 * descriptor has been written back 2313 */ 2314 dma_rmb(); 2315 2316 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2317 2318 /* retrieve a buffer from the ring */ 2319 if (!skb) { 2320 xdp.data = page_address(rx_buffer->page) + 2321 rx_buffer->page_offset; 2322 xdp.data_meta = xdp.data; 2323 xdp.data_hard_start = xdp.data - 2324 ixgbe_rx_offset(rx_ring); 2325 xdp.data_end = xdp.data + size; 2326 2327 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2328 } 2329 2330 if (IS_ERR(skb)) { 2331 unsigned int xdp_res = -PTR_ERR(skb); 2332 2333 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2334 xdp_xmit |= xdp_res; 2335 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2336 } else { 2337 rx_buffer->pagecnt_bias++; 2338 } 2339 total_rx_packets++; 2340 total_rx_bytes += size; 2341 } else if (skb) { 2342 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2343 } else if (ring_uses_build_skb(rx_ring)) { 2344 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2345 &xdp, rx_desc); 2346 } else { 2347 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2348 &xdp, rx_desc); 2349 } 2350 2351 /* exit if we failed to retrieve a buffer */ 2352 if (!skb) { 2353 rx_ring->rx_stats.alloc_rx_buff_failed++; 2354 rx_buffer->pagecnt_bias++; 2355 break; 2356 } 2357 2358 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2359 cleaned_count++; 2360 2361 /* place incomplete frames back on ring for completion */ 2362 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2363 continue; 2364 2365 /* verify the packet layout is correct */ 2366 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2367 continue; 2368 2369 /* probably a little skewed due to removing CRC */ 2370 total_rx_bytes += skb->len; 2371 2372 /* populate checksum, timestamp, VLAN, and protocol */ 2373 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2374 2375 #ifdef IXGBE_FCOE 2376 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2377 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2378 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2379 /* include DDPed FCoE data */ 2380 if (ddp_bytes > 0) { 2381 if (!mss) { 2382 mss = rx_ring->netdev->mtu - 2383 sizeof(struct fcoe_hdr) - 2384 sizeof(struct fc_frame_header) - 2385 sizeof(struct fcoe_crc_eof); 2386 if (mss > 512) 2387 mss &= ~511; 2388 } 2389 total_rx_bytes += ddp_bytes; 2390 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2391 mss); 2392 } 2393 if (!ddp_bytes) { 2394 dev_kfree_skb_any(skb); 2395 continue; 2396 } 2397 } 2398 2399 #endif /* IXGBE_FCOE */ 2400 ixgbe_rx_skb(q_vector, skb); 2401 2402 /* update budget accounting */ 2403 total_rx_packets++; 2404 } 2405 2406 if (xdp_xmit & IXGBE_XDP_REDIR) 2407 xdp_do_flush_map(); 2408 2409 if (xdp_xmit & IXGBE_XDP_TX) { 2410 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2411 2412 /* Force memory writes to complete before letting h/w 2413 * know there are new descriptors to fetch. 2414 */ 2415 wmb(); 2416 writel(ring->next_to_use, ring->tail); 2417 } 2418 2419 u64_stats_update_begin(&rx_ring->syncp); 2420 rx_ring->stats.packets += total_rx_packets; 2421 rx_ring->stats.bytes += total_rx_bytes; 2422 u64_stats_update_end(&rx_ring->syncp); 2423 q_vector->rx.total_packets += total_rx_packets; 2424 q_vector->rx.total_bytes += total_rx_bytes; 2425 2426 return total_rx_packets; 2427 } 2428 2429 /** 2430 * ixgbe_configure_msix - Configure MSI-X hardware 2431 * @adapter: board private structure 2432 * 2433 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2434 * interrupts. 2435 **/ 2436 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2437 { 2438 struct ixgbe_q_vector *q_vector; 2439 int v_idx; 2440 u32 mask; 2441 2442 /* Populate MSIX to EITR Select */ 2443 if (adapter->num_vfs > 32) { 2444 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2446 } 2447 2448 /* 2449 * Populate the IVAR table and set the ITR values to the 2450 * corresponding register. 2451 */ 2452 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2453 struct ixgbe_ring *ring; 2454 q_vector = adapter->q_vector[v_idx]; 2455 2456 ixgbe_for_each_ring(ring, q_vector->rx) 2457 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2458 2459 ixgbe_for_each_ring(ring, q_vector->tx) 2460 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2461 2462 ixgbe_write_eitr(q_vector); 2463 } 2464 2465 switch (adapter->hw.mac.type) { 2466 case ixgbe_mac_82598EB: 2467 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2468 v_idx); 2469 break; 2470 case ixgbe_mac_82599EB: 2471 case ixgbe_mac_X540: 2472 case ixgbe_mac_X550: 2473 case ixgbe_mac_X550EM_x: 2474 case ixgbe_mac_x550em_a: 2475 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2476 break; 2477 default: 2478 break; 2479 } 2480 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2481 2482 /* set up to autoclear timer, and the vectors */ 2483 mask = IXGBE_EIMS_ENABLE_MASK; 2484 mask &= ~(IXGBE_EIMS_OTHER | 2485 IXGBE_EIMS_MAILBOX | 2486 IXGBE_EIMS_LSC); 2487 2488 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2489 } 2490 2491 /** 2492 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2493 * @q_vector: structure containing interrupt and ring information 2494 * @ring_container: structure containing ring performance data 2495 * 2496 * Stores a new ITR value based on packets and byte 2497 * counts during the last interrupt. The advantage of per interrupt 2498 * computation is faster updates and more accurate ITR for the current 2499 * traffic pattern. Constants in this function were computed 2500 * based on theoretical maximum wire speed and thresholds were set based 2501 * on testing data as well as attempting to minimize response time 2502 * while increasing bulk throughput. 2503 **/ 2504 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2505 struct ixgbe_ring_container *ring_container) 2506 { 2507 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2508 IXGBE_ITR_ADAPTIVE_LATENCY; 2509 unsigned int avg_wire_size, packets, bytes; 2510 unsigned long next_update = jiffies; 2511 2512 /* If we don't have any rings just leave ourselves set for maximum 2513 * possible latency so we take ourselves out of the equation. 2514 */ 2515 if (!ring_container->ring) 2516 return; 2517 2518 /* If we didn't update within up to 1 - 2 jiffies we can assume 2519 * that either packets are coming in so slow there hasn't been 2520 * any work, or that there is so much work that NAPI is dealing 2521 * with interrupt moderation and we don't need to do anything. 2522 */ 2523 if (time_after(next_update, ring_container->next_update)) 2524 goto clear_counts; 2525 2526 packets = ring_container->total_packets; 2527 2528 /* We have no packets to actually measure against. This means 2529 * either one of the other queues on this vector is active or 2530 * we are a Tx queue doing TSO with too high of an interrupt rate. 2531 * 2532 * When this occurs just tick up our delay by the minimum value 2533 * and hope that this extra delay will prevent us from being called 2534 * without any work on our queue. 2535 */ 2536 if (!packets) { 2537 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2538 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2539 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2540 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2541 goto clear_counts; 2542 } 2543 2544 bytes = ring_container->total_bytes; 2545 2546 /* If packets are less than 4 or bytes are less than 9000 assume 2547 * insufficient data to use bulk rate limiting approach. We are 2548 * likely latency driven. 2549 */ 2550 if (packets < 4 && bytes < 9000) { 2551 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2552 goto adjust_by_size; 2553 } 2554 2555 /* Between 4 and 48 we can assume that our current interrupt delay 2556 * is only slightly too low. As such we should increase it by a small 2557 * fixed amount. 2558 */ 2559 if (packets < 48) { 2560 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2561 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2562 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2563 goto clear_counts; 2564 } 2565 2566 /* Between 48 and 96 is our "goldilocks" zone where we are working 2567 * out "just right". Just report that our current ITR is good for us. 2568 */ 2569 if (packets < 96) { 2570 itr = q_vector->itr >> 2; 2571 goto clear_counts; 2572 } 2573 2574 /* If packet count is 96 or greater we are likely looking at a slight 2575 * overrun of the delay we want. Try halving our delay to see if that 2576 * will cut the number of packets in half per interrupt. 2577 */ 2578 if (packets < 256) { 2579 itr = q_vector->itr >> 3; 2580 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2581 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2582 goto clear_counts; 2583 } 2584 2585 /* The paths below assume we are dealing with a bulk ITR since number 2586 * of packets is 256 or greater. We are just going to have to compute 2587 * a value and try to bring the count under control, though for smaller 2588 * packet sizes there isn't much we can do as NAPI polling will likely 2589 * be kicking in sooner rather than later. 2590 */ 2591 itr = IXGBE_ITR_ADAPTIVE_BULK; 2592 2593 adjust_by_size: 2594 /* If packet counts are 256 or greater we can assume we have a gross 2595 * overestimation of what the rate should be. Instead of trying to fine 2596 * tune it just use the formula below to try and dial in an exact value 2597 * give the current packet size of the frame. 2598 */ 2599 avg_wire_size = bytes / packets; 2600 2601 /* The following is a crude approximation of: 2602 * wmem_default / (size + overhead) = desired_pkts_per_int 2603 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2604 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2605 * 2606 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2607 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2608 * formula down to 2609 * 2610 * (170 * (size + 24)) / (size + 640) = ITR 2611 * 2612 * We first do some math on the packet size and then finally bitshift 2613 * by 8 after rounding up. We also have to account for PCIe link speed 2614 * difference as ITR scales based on this. 2615 */ 2616 if (avg_wire_size <= 60) { 2617 /* Start at 50k ints/sec */ 2618 avg_wire_size = 5120; 2619 } else if (avg_wire_size <= 316) { 2620 /* 50K ints/sec to 16K ints/sec */ 2621 avg_wire_size *= 40; 2622 avg_wire_size += 2720; 2623 } else if (avg_wire_size <= 1084) { 2624 /* 16K ints/sec to 9.2K ints/sec */ 2625 avg_wire_size *= 15; 2626 avg_wire_size += 11452; 2627 } else if (avg_wire_size < 1968) { 2628 /* 9.2K ints/sec to 8K ints/sec */ 2629 avg_wire_size *= 5; 2630 avg_wire_size += 22420; 2631 } else { 2632 /* plateau at a limit of 8K ints/sec */ 2633 avg_wire_size = 32256; 2634 } 2635 2636 /* If we are in low latency mode half our delay which doubles the rate 2637 * to somewhere between 100K to 16K ints/sec 2638 */ 2639 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2640 avg_wire_size >>= 1; 2641 2642 /* Resultant value is 256 times larger than it needs to be. This 2643 * gives us room to adjust the value as needed to either increase 2644 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2645 * 2646 * Use addition as we have already recorded the new latency flag 2647 * for the ITR value. 2648 */ 2649 switch (q_vector->adapter->link_speed) { 2650 case IXGBE_LINK_SPEED_10GB_FULL: 2651 case IXGBE_LINK_SPEED_100_FULL: 2652 default: 2653 itr += DIV_ROUND_UP(avg_wire_size, 2654 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2655 IXGBE_ITR_ADAPTIVE_MIN_INC; 2656 break; 2657 case IXGBE_LINK_SPEED_2_5GB_FULL: 2658 case IXGBE_LINK_SPEED_1GB_FULL: 2659 case IXGBE_LINK_SPEED_10_FULL: 2660 if (avg_wire_size > 8064) 2661 avg_wire_size = 8064; 2662 itr += DIV_ROUND_UP(avg_wire_size, 2663 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2664 IXGBE_ITR_ADAPTIVE_MIN_INC; 2665 break; 2666 } 2667 2668 clear_counts: 2669 /* write back value */ 2670 ring_container->itr = itr; 2671 2672 /* next update should occur within next jiffy */ 2673 ring_container->next_update = next_update + 1; 2674 2675 ring_container->total_bytes = 0; 2676 ring_container->total_packets = 0; 2677 } 2678 2679 /** 2680 * ixgbe_write_eitr - write EITR register in hardware specific way 2681 * @q_vector: structure containing interrupt and ring information 2682 * 2683 * This function is made to be called by ethtool and by the driver 2684 * when it needs to update EITR registers at runtime. Hardware 2685 * specific quirks/differences are taken care of here. 2686 */ 2687 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2688 { 2689 struct ixgbe_adapter *adapter = q_vector->adapter; 2690 struct ixgbe_hw *hw = &adapter->hw; 2691 int v_idx = q_vector->v_idx; 2692 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2693 2694 switch (adapter->hw.mac.type) { 2695 case ixgbe_mac_82598EB: 2696 /* must write high and low 16 bits to reset counter */ 2697 itr_reg |= (itr_reg << 16); 2698 break; 2699 case ixgbe_mac_82599EB: 2700 case ixgbe_mac_X540: 2701 case ixgbe_mac_X550: 2702 case ixgbe_mac_X550EM_x: 2703 case ixgbe_mac_x550em_a: 2704 /* 2705 * set the WDIS bit to not clear the timer bits and cause an 2706 * immediate assertion of the interrupt 2707 */ 2708 itr_reg |= IXGBE_EITR_CNT_WDIS; 2709 break; 2710 default: 2711 break; 2712 } 2713 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2714 } 2715 2716 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2717 { 2718 u32 new_itr; 2719 2720 ixgbe_update_itr(q_vector, &q_vector->tx); 2721 ixgbe_update_itr(q_vector, &q_vector->rx); 2722 2723 /* use the smallest value of new ITR delay calculations */ 2724 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2725 2726 /* Clear latency flag if set, shift into correct position */ 2727 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2728 new_itr <<= 2; 2729 2730 if (new_itr != q_vector->itr) { 2731 /* save the algorithm value here */ 2732 q_vector->itr = new_itr; 2733 2734 ixgbe_write_eitr(q_vector); 2735 } 2736 } 2737 2738 /** 2739 * ixgbe_check_overtemp_subtask - check for over temperature 2740 * @adapter: pointer to adapter 2741 **/ 2742 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2743 { 2744 struct ixgbe_hw *hw = &adapter->hw; 2745 u32 eicr = adapter->interrupt_event; 2746 s32 rc; 2747 2748 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2749 return; 2750 2751 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2752 return; 2753 2754 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2755 2756 switch (hw->device_id) { 2757 case IXGBE_DEV_ID_82599_T3_LOM: 2758 /* 2759 * Since the warning interrupt is for both ports 2760 * we don't have to check if: 2761 * - This interrupt wasn't for our port. 2762 * - We may have missed the interrupt so always have to 2763 * check if we got a LSC 2764 */ 2765 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2766 !(eicr & IXGBE_EICR_LSC)) 2767 return; 2768 2769 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2770 u32 speed; 2771 bool link_up = false; 2772 2773 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2774 2775 if (link_up) 2776 return; 2777 } 2778 2779 /* Check if this is not due to overtemp */ 2780 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2781 return; 2782 2783 break; 2784 case IXGBE_DEV_ID_X550EM_A_1G_T: 2785 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2786 rc = hw->phy.ops.check_overtemp(hw); 2787 if (rc != IXGBE_ERR_OVERTEMP) 2788 return; 2789 break; 2790 default: 2791 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2792 return; 2793 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2794 return; 2795 break; 2796 } 2797 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2798 2799 adapter->interrupt_event = 0; 2800 } 2801 2802 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2803 { 2804 struct ixgbe_hw *hw = &adapter->hw; 2805 2806 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2807 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2808 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2809 /* write to clear the interrupt */ 2810 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2811 } 2812 } 2813 2814 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2815 { 2816 struct ixgbe_hw *hw = &adapter->hw; 2817 2818 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2819 return; 2820 2821 switch (adapter->hw.mac.type) { 2822 case ixgbe_mac_82599EB: 2823 /* 2824 * Need to check link state so complete overtemp check 2825 * on service task 2826 */ 2827 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2828 (eicr & IXGBE_EICR_LSC)) && 2829 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2830 adapter->interrupt_event = eicr; 2831 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2832 ixgbe_service_event_schedule(adapter); 2833 return; 2834 } 2835 return; 2836 case ixgbe_mac_x550em_a: 2837 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2838 adapter->interrupt_event = eicr; 2839 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2840 ixgbe_service_event_schedule(adapter); 2841 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2842 IXGBE_EICR_GPI_SDP0_X550EM_a); 2843 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2844 IXGBE_EICR_GPI_SDP0_X550EM_a); 2845 } 2846 return; 2847 case ixgbe_mac_X550: 2848 case ixgbe_mac_X540: 2849 if (!(eicr & IXGBE_EICR_TS)) 2850 return; 2851 break; 2852 default: 2853 return; 2854 } 2855 2856 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2857 } 2858 2859 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2860 { 2861 switch (hw->mac.type) { 2862 case ixgbe_mac_82598EB: 2863 if (hw->phy.type == ixgbe_phy_nl) 2864 return true; 2865 return false; 2866 case ixgbe_mac_82599EB: 2867 case ixgbe_mac_X550EM_x: 2868 case ixgbe_mac_x550em_a: 2869 switch (hw->mac.ops.get_media_type(hw)) { 2870 case ixgbe_media_type_fiber: 2871 case ixgbe_media_type_fiber_qsfp: 2872 return true; 2873 default: 2874 return false; 2875 } 2876 default: 2877 return false; 2878 } 2879 } 2880 2881 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2882 { 2883 struct ixgbe_hw *hw = &adapter->hw; 2884 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2885 2886 if (!ixgbe_is_sfp(hw)) 2887 return; 2888 2889 /* Later MAC's use different SDP */ 2890 if (hw->mac.type >= ixgbe_mac_X540) 2891 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2892 2893 if (eicr & eicr_mask) { 2894 /* Clear the interrupt */ 2895 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2896 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2897 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2898 adapter->sfp_poll_time = 0; 2899 ixgbe_service_event_schedule(adapter); 2900 } 2901 } 2902 2903 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2904 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2905 /* Clear the interrupt */ 2906 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2907 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2908 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2909 ixgbe_service_event_schedule(adapter); 2910 } 2911 } 2912 } 2913 2914 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2915 { 2916 struct ixgbe_hw *hw = &adapter->hw; 2917 2918 adapter->lsc_int++; 2919 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2920 adapter->link_check_timeout = jiffies; 2921 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2922 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2923 IXGBE_WRITE_FLUSH(hw); 2924 ixgbe_service_event_schedule(adapter); 2925 } 2926 } 2927 2928 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2929 u64 qmask) 2930 { 2931 u32 mask; 2932 struct ixgbe_hw *hw = &adapter->hw; 2933 2934 switch (hw->mac.type) { 2935 case ixgbe_mac_82598EB: 2936 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2937 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2938 break; 2939 case ixgbe_mac_82599EB: 2940 case ixgbe_mac_X540: 2941 case ixgbe_mac_X550: 2942 case ixgbe_mac_X550EM_x: 2943 case ixgbe_mac_x550em_a: 2944 mask = (qmask & 0xFFFFFFFF); 2945 if (mask) 2946 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2947 mask = (qmask >> 32); 2948 if (mask) 2949 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2950 break; 2951 default: 2952 break; 2953 } 2954 /* skip the flush */ 2955 } 2956 2957 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2958 u64 qmask) 2959 { 2960 u32 mask; 2961 struct ixgbe_hw *hw = &adapter->hw; 2962 2963 switch (hw->mac.type) { 2964 case ixgbe_mac_82598EB: 2965 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2966 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2967 break; 2968 case ixgbe_mac_82599EB: 2969 case ixgbe_mac_X540: 2970 case ixgbe_mac_X550: 2971 case ixgbe_mac_X550EM_x: 2972 case ixgbe_mac_x550em_a: 2973 mask = (qmask & 0xFFFFFFFF); 2974 if (mask) 2975 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2976 mask = (qmask >> 32); 2977 if (mask) 2978 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2979 break; 2980 default: 2981 break; 2982 } 2983 /* skip the flush */ 2984 } 2985 2986 /** 2987 * ixgbe_irq_enable - Enable default interrupt generation settings 2988 * @adapter: board private structure 2989 * @queues: enable irqs for queues 2990 * @flush: flush register write 2991 **/ 2992 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2993 bool flush) 2994 { 2995 struct ixgbe_hw *hw = &adapter->hw; 2996 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2997 2998 /* don't reenable LSC while waiting for link */ 2999 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3000 mask &= ~IXGBE_EIMS_LSC; 3001 3002 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3003 switch (adapter->hw.mac.type) { 3004 case ixgbe_mac_82599EB: 3005 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3006 break; 3007 case ixgbe_mac_X540: 3008 case ixgbe_mac_X550: 3009 case ixgbe_mac_X550EM_x: 3010 case ixgbe_mac_x550em_a: 3011 mask |= IXGBE_EIMS_TS; 3012 break; 3013 default: 3014 break; 3015 } 3016 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3017 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3018 switch (adapter->hw.mac.type) { 3019 case ixgbe_mac_82599EB: 3020 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3021 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3022 /* fall through */ 3023 case ixgbe_mac_X540: 3024 case ixgbe_mac_X550: 3025 case ixgbe_mac_X550EM_x: 3026 case ixgbe_mac_x550em_a: 3027 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3028 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3029 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3030 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3031 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3032 mask |= IXGBE_EICR_GPI_SDP0_X540; 3033 mask |= IXGBE_EIMS_ECC; 3034 mask |= IXGBE_EIMS_MAILBOX; 3035 break; 3036 default: 3037 break; 3038 } 3039 3040 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3041 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3042 mask |= IXGBE_EIMS_FLOW_DIR; 3043 3044 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3045 if (queues) 3046 ixgbe_irq_enable_queues(adapter, ~0); 3047 if (flush) 3048 IXGBE_WRITE_FLUSH(&adapter->hw); 3049 } 3050 3051 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3052 { 3053 struct ixgbe_adapter *adapter = data; 3054 struct ixgbe_hw *hw = &adapter->hw; 3055 u32 eicr; 3056 3057 /* 3058 * Workaround for Silicon errata. Use clear-by-write instead 3059 * of clear-by-read. Reading with EICS will return the 3060 * interrupt causes without clearing, which later be done 3061 * with the write to EICR. 3062 */ 3063 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3064 3065 /* The lower 16bits of the EICR register are for the queue interrupts 3066 * which should be masked here in order to not accidentally clear them if 3067 * the bits are high when ixgbe_msix_other is called. There is a race 3068 * condition otherwise which results in possible performance loss 3069 * especially if the ixgbe_msix_other interrupt is triggering 3070 * consistently (as it would when PPS is turned on for the X540 device) 3071 */ 3072 eicr &= 0xFFFF0000; 3073 3074 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3075 3076 if (eicr & IXGBE_EICR_LSC) 3077 ixgbe_check_lsc(adapter); 3078 3079 if (eicr & IXGBE_EICR_MAILBOX) 3080 ixgbe_msg_task(adapter); 3081 3082 switch (hw->mac.type) { 3083 case ixgbe_mac_82599EB: 3084 case ixgbe_mac_X540: 3085 case ixgbe_mac_X550: 3086 case ixgbe_mac_X550EM_x: 3087 case ixgbe_mac_x550em_a: 3088 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3089 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3090 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3091 ixgbe_service_event_schedule(adapter); 3092 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3093 IXGBE_EICR_GPI_SDP0_X540); 3094 } 3095 if (eicr & IXGBE_EICR_ECC) { 3096 e_info(link, "Received ECC Err, initiating reset\n"); 3097 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3098 ixgbe_service_event_schedule(adapter); 3099 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3100 } 3101 /* Handle Flow Director Full threshold interrupt */ 3102 if (eicr & IXGBE_EICR_FLOW_DIR) { 3103 int reinit_count = 0; 3104 int i; 3105 for (i = 0; i < adapter->num_tx_queues; i++) { 3106 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3107 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3108 &ring->state)) 3109 reinit_count++; 3110 } 3111 if (reinit_count) { 3112 /* no more flow director interrupts until after init */ 3113 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3114 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3115 ixgbe_service_event_schedule(adapter); 3116 } 3117 } 3118 ixgbe_check_sfp_event(adapter, eicr); 3119 ixgbe_check_overtemp_event(adapter, eicr); 3120 break; 3121 default: 3122 break; 3123 } 3124 3125 ixgbe_check_fan_failure(adapter, eicr); 3126 3127 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3128 ixgbe_ptp_check_pps_event(adapter); 3129 3130 /* re-enable the original interrupt state, no lsc, no queues */ 3131 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3132 ixgbe_irq_enable(adapter, false, false); 3133 3134 return IRQ_HANDLED; 3135 } 3136 3137 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3138 { 3139 struct ixgbe_q_vector *q_vector = data; 3140 3141 /* EIAM disabled interrupts (on this vector) for us */ 3142 3143 if (q_vector->rx.ring || q_vector->tx.ring) 3144 napi_schedule_irqoff(&q_vector->napi); 3145 3146 return IRQ_HANDLED; 3147 } 3148 3149 /** 3150 * ixgbe_poll - NAPI Rx polling callback 3151 * @napi: structure for representing this polling device 3152 * @budget: how many packets driver is allowed to clean 3153 * 3154 * This function is used for legacy and MSI, NAPI mode 3155 **/ 3156 int ixgbe_poll(struct napi_struct *napi, int budget) 3157 { 3158 struct ixgbe_q_vector *q_vector = 3159 container_of(napi, struct ixgbe_q_vector, napi); 3160 struct ixgbe_adapter *adapter = q_vector->adapter; 3161 struct ixgbe_ring *ring; 3162 int per_ring_budget, work_done = 0; 3163 bool clean_complete = true; 3164 3165 #ifdef CONFIG_IXGBE_DCA 3166 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3167 ixgbe_update_dca(q_vector); 3168 #endif 3169 3170 ixgbe_for_each_ring(ring, q_vector->tx) { 3171 bool wd = ring->xsk_umem ? 3172 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3173 ixgbe_clean_tx_irq(q_vector, ring, budget); 3174 3175 if (!wd) 3176 clean_complete = false; 3177 } 3178 3179 /* Exit if we are called by netpoll */ 3180 if (budget <= 0) 3181 return budget; 3182 3183 /* attempt to distribute budget to each queue fairly, but don't allow 3184 * the budget to go below 1 because we'll exit polling */ 3185 if (q_vector->rx.count > 1) 3186 per_ring_budget = max(budget/q_vector->rx.count, 1); 3187 else 3188 per_ring_budget = budget; 3189 3190 ixgbe_for_each_ring(ring, q_vector->rx) { 3191 int cleaned = ring->xsk_umem ? 3192 ixgbe_clean_rx_irq_zc(q_vector, ring, 3193 per_ring_budget) : 3194 ixgbe_clean_rx_irq(q_vector, ring, 3195 per_ring_budget); 3196 3197 work_done += cleaned; 3198 if (cleaned >= per_ring_budget) 3199 clean_complete = false; 3200 } 3201 3202 /* If all work not completed, return budget and keep polling */ 3203 if (!clean_complete) 3204 return budget; 3205 3206 /* all work done, exit the polling mode */ 3207 if (likely(napi_complete_done(napi, work_done))) { 3208 if (adapter->rx_itr_setting & 1) 3209 ixgbe_set_itr(q_vector); 3210 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3211 ixgbe_irq_enable_queues(adapter, 3212 BIT_ULL(q_vector->v_idx)); 3213 } 3214 3215 return min(work_done, budget - 1); 3216 } 3217 3218 /** 3219 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3220 * @adapter: board private structure 3221 * 3222 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3223 * interrupts from the kernel. 3224 **/ 3225 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3226 { 3227 struct net_device *netdev = adapter->netdev; 3228 unsigned int ri = 0, ti = 0; 3229 int vector, err; 3230 3231 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3232 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3233 struct msix_entry *entry = &adapter->msix_entries[vector]; 3234 3235 if (q_vector->tx.ring && q_vector->rx.ring) { 3236 snprintf(q_vector->name, sizeof(q_vector->name), 3237 "%s-TxRx-%u", netdev->name, ri++); 3238 ti++; 3239 } else if (q_vector->rx.ring) { 3240 snprintf(q_vector->name, sizeof(q_vector->name), 3241 "%s-rx-%u", netdev->name, ri++); 3242 } else if (q_vector->tx.ring) { 3243 snprintf(q_vector->name, sizeof(q_vector->name), 3244 "%s-tx-%u", netdev->name, ti++); 3245 } else { 3246 /* skip this unused q_vector */ 3247 continue; 3248 } 3249 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3250 q_vector->name, q_vector); 3251 if (err) { 3252 e_err(probe, "request_irq failed for MSIX interrupt " 3253 "Error: %d\n", err); 3254 goto free_queue_irqs; 3255 } 3256 /* If Flow Director is enabled, set interrupt affinity */ 3257 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3258 /* assign the mask for this irq */ 3259 irq_set_affinity_hint(entry->vector, 3260 &q_vector->affinity_mask); 3261 } 3262 } 3263 3264 err = request_irq(adapter->msix_entries[vector].vector, 3265 ixgbe_msix_other, 0, netdev->name, adapter); 3266 if (err) { 3267 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3268 goto free_queue_irqs; 3269 } 3270 3271 return 0; 3272 3273 free_queue_irqs: 3274 while (vector) { 3275 vector--; 3276 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3277 NULL); 3278 free_irq(adapter->msix_entries[vector].vector, 3279 adapter->q_vector[vector]); 3280 } 3281 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3282 pci_disable_msix(adapter->pdev); 3283 kfree(adapter->msix_entries); 3284 adapter->msix_entries = NULL; 3285 return err; 3286 } 3287 3288 /** 3289 * ixgbe_intr - legacy mode Interrupt Handler 3290 * @irq: interrupt number 3291 * @data: pointer to a network interface device structure 3292 **/ 3293 static irqreturn_t ixgbe_intr(int irq, void *data) 3294 { 3295 struct ixgbe_adapter *adapter = data; 3296 struct ixgbe_hw *hw = &adapter->hw; 3297 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3298 u32 eicr; 3299 3300 /* 3301 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3302 * before the read of EICR. 3303 */ 3304 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3305 3306 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3307 * therefore no explicit interrupt disable is necessary */ 3308 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3309 if (!eicr) { 3310 /* 3311 * shared interrupt alert! 3312 * make sure interrupts are enabled because the read will 3313 * have disabled interrupts due to EIAM 3314 * finish the workaround of silicon errata on 82598. Unmask 3315 * the interrupt that we masked before the EICR read. 3316 */ 3317 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3318 ixgbe_irq_enable(adapter, true, true); 3319 return IRQ_NONE; /* Not our interrupt */ 3320 } 3321 3322 if (eicr & IXGBE_EICR_LSC) 3323 ixgbe_check_lsc(adapter); 3324 3325 switch (hw->mac.type) { 3326 case ixgbe_mac_82599EB: 3327 ixgbe_check_sfp_event(adapter, eicr); 3328 /* Fall through */ 3329 case ixgbe_mac_X540: 3330 case ixgbe_mac_X550: 3331 case ixgbe_mac_X550EM_x: 3332 case ixgbe_mac_x550em_a: 3333 if (eicr & IXGBE_EICR_ECC) { 3334 e_info(link, "Received ECC Err, initiating reset\n"); 3335 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3336 ixgbe_service_event_schedule(adapter); 3337 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3338 } 3339 ixgbe_check_overtemp_event(adapter, eicr); 3340 break; 3341 default: 3342 break; 3343 } 3344 3345 ixgbe_check_fan_failure(adapter, eicr); 3346 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3347 ixgbe_ptp_check_pps_event(adapter); 3348 3349 /* would disable interrupts here but EIAM disabled it */ 3350 napi_schedule_irqoff(&q_vector->napi); 3351 3352 /* 3353 * re-enable link(maybe) and non-queue interrupts, no flush. 3354 * ixgbe_poll will re-enable the queue interrupts 3355 */ 3356 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3357 ixgbe_irq_enable(adapter, false, false); 3358 3359 return IRQ_HANDLED; 3360 } 3361 3362 /** 3363 * ixgbe_request_irq - initialize interrupts 3364 * @adapter: board private structure 3365 * 3366 * Attempts to configure interrupts using the best available 3367 * capabilities of the hardware and kernel. 3368 **/ 3369 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3370 { 3371 struct net_device *netdev = adapter->netdev; 3372 int err; 3373 3374 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3375 err = ixgbe_request_msix_irqs(adapter); 3376 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3377 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3378 netdev->name, adapter); 3379 else 3380 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3381 netdev->name, adapter); 3382 3383 if (err) 3384 e_err(probe, "request_irq failed, Error %d\n", err); 3385 3386 return err; 3387 } 3388 3389 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3390 { 3391 int vector; 3392 3393 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3394 free_irq(adapter->pdev->irq, adapter); 3395 return; 3396 } 3397 3398 if (!adapter->msix_entries) 3399 return; 3400 3401 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3402 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3403 struct msix_entry *entry = &adapter->msix_entries[vector]; 3404 3405 /* free only the irqs that were actually requested */ 3406 if (!q_vector->rx.ring && !q_vector->tx.ring) 3407 continue; 3408 3409 /* clear the affinity_mask in the IRQ descriptor */ 3410 irq_set_affinity_hint(entry->vector, NULL); 3411 3412 free_irq(entry->vector, q_vector); 3413 } 3414 3415 free_irq(adapter->msix_entries[vector].vector, adapter); 3416 } 3417 3418 /** 3419 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3420 * @adapter: board private structure 3421 **/ 3422 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3423 { 3424 switch (adapter->hw.mac.type) { 3425 case ixgbe_mac_82598EB: 3426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3427 break; 3428 case ixgbe_mac_82599EB: 3429 case ixgbe_mac_X540: 3430 case ixgbe_mac_X550: 3431 case ixgbe_mac_X550EM_x: 3432 case ixgbe_mac_x550em_a: 3433 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3436 break; 3437 default: 3438 break; 3439 } 3440 IXGBE_WRITE_FLUSH(&adapter->hw); 3441 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3442 int vector; 3443 3444 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3445 synchronize_irq(adapter->msix_entries[vector].vector); 3446 3447 synchronize_irq(adapter->msix_entries[vector++].vector); 3448 } else { 3449 synchronize_irq(adapter->pdev->irq); 3450 } 3451 } 3452 3453 /** 3454 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3455 * @adapter: board private structure 3456 * 3457 **/ 3458 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3459 { 3460 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3461 3462 ixgbe_write_eitr(q_vector); 3463 3464 ixgbe_set_ivar(adapter, 0, 0, 0); 3465 ixgbe_set_ivar(adapter, 1, 0, 0); 3466 3467 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3468 } 3469 3470 /** 3471 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3472 * @adapter: board private structure 3473 * @ring: structure containing ring specific data 3474 * 3475 * Configure the Tx descriptor ring after a reset. 3476 **/ 3477 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3478 struct ixgbe_ring *ring) 3479 { 3480 struct ixgbe_hw *hw = &adapter->hw; 3481 u64 tdba = ring->dma; 3482 int wait_loop = 10; 3483 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3484 u8 reg_idx = ring->reg_idx; 3485 3486 ring->xsk_umem = NULL; 3487 if (ring_is_xdp(ring)) 3488 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 3489 3490 /* disable queue to avoid issues while updating state */ 3491 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3492 IXGBE_WRITE_FLUSH(hw); 3493 3494 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3495 (tdba & DMA_BIT_MASK(32))); 3496 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3497 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3498 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3499 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3500 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3501 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3502 3503 /* 3504 * set WTHRESH to encourage burst writeback, it should not be set 3505 * higher than 1 when: 3506 * - ITR is 0 as it could cause false TX hangs 3507 * - ITR is set to > 100k int/sec and BQL is enabled 3508 * 3509 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3510 * to or less than the number of on chip descriptors, which is 3511 * currently 40. 3512 */ 3513 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3514 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3515 else 3516 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3517 3518 /* 3519 * Setting PTHRESH to 32 both improves performance 3520 * and avoids a TX hang with DFP enabled 3521 */ 3522 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3523 32; /* PTHRESH = 32 */ 3524 3525 /* reinitialize flowdirector state */ 3526 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3527 ring->atr_sample_rate = adapter->atr_sample_rate; 3528 ring->atr_count = 0; 3529 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3530 } else { 3531 ring->atr_sample_rate = 0; 3532 } 3533 3534 /* initialize XPS */ 3535 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3536 struct ixgbe_q_vector *q_vector = ring->q_vector; 3537 3538 if (q_vector) 3539 netif_set_xps_queue(ring->netdev, 3540 &q_vector->affinity_mask, 3541 ring->queue_index); 3542 } 3543 3544 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3545 3546 /* reinitialize tx_buffer_info */ 3547 memset(ring->tx_buffer_info, 0, 3548 sizeof(struct ixgbe_tx_buffer) * ring->count); 3549 3550 /* enable queue */ 3551 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3552 3553 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3554 if (hw->mac.type == ixgbe_mac_82598EB && 3555 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3556 return; 3557 3558 /* poll to verify queue is enabled */ 3559 do { 3560 usleep_range(1000, 2000); 3561 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3562 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3563 if (!wait_loop) 3564 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3565 } 3566 3567 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3568 { 3569 struct ixgbe_hw *hw = &adapter->hw; 3570 u32 rttdcs, mtqc; 3571 u8 tcs = adapter->hw_tcs; 3572 3573 if (hw->mac.type == ixgbe_mac_82598EB) 3574 return; 3575 3576 /* disable the arbiter while setting MTQC */ 3577 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3578 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3579 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3580 3581 /* set transmit pool layout */ 3582 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3583 mtqc = IXGBE_MTQC_VT_ENA; 3584 if (tcs > 4) 3585 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3586 else if (tcs > 1) 3587 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3588 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3589 IXGBE_82599_VMDQ_4Q_MASK) 3590 mtqc |= IXGBE_MTQC_32VF; 3591 else 3592 mtqc |= IXGBE_MTQC_64VF; 3593 } else { 3594 if (tcs > 4) { 3595 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3596 } else if (tcs > 1) { 3597 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3598 } else { 3599 u8 max_txq = adapter->num_tx_queues + 3600 adapter->num_xdp_queues; 3601 if (max_txq > 63) 3602 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3603 else 3604 mtqc = IXGBE_MTQC_64Q_1PB; 3605 } 3606 } 3607 3608 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3609 3610 /* Enable Security TX Buffer IFG for multiple pb */ 3611 if (tcs) { 3612 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3613 sectx |= IXGBE_SECTX_DCB; 3614 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3615 } 3616 3617 /* re-enable the arbiter */ 3618 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3619 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3620 } 3621 3622 /** 3623 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3624 * @adapter: board private structure 3625 * 3626 * Configure the Tx unit of the MAC after a reset. 3627 **/ 3628 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3629 { 3630 struct ixgbe_hw *hw = &adapter->hw; 3631 u32 dmatxctl; 3632 u32 i; 3633 3634 ixgbe_setup_mtqc(adapter); 3635 3636 if (hw->mac.type != ixgbe_mac_82598EB) { 3637 /* DMATXCTL.EN must be before Tx queues are enabled */ 3638 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3639 dmatxctl |= IXGBE_DMATXCTL_TE; 3640 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3641 } 3642 3643 /* Setup the HW Tx Head and Tail descriptor pointers */ 3644 for (i = 0; i < adapter->num_tx_queues; i++) 3645 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3646 for (i = 0; i < adapter->num_xdp_queues; i++) 3647 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3648 } 3649 3650 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3651 struct ixgbe_ring *ring) 3652 { 3653 struct ixgbe_hw *hw = &adapter->hw; 3654 u8 reg_idx = ring->reg_idx; 3655 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3656 3657 srrctl |= IXGBE_SRRCTL_DROP_EN; 3658 3659 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3660 } 3661 3662 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3663 struct ixgbe_ring *ring) 3664 { 3665 struct ixgbe_hw *hw = &adapter->hw; 3666 u8 reg_idx = ring->reg_idx; 3667 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3668 3669 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3670 3671 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3672 } 3673 3674 #ifdef CONFIG_IXGBE_DCB 3675 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3676 #else 3677 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3678 #endif 3679 { 3680 int i; 3681 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3682 3683 if (adapter->ixgbe_ieee_pfc) 3684 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3685 3686 /* 3687 * We should set the drop enable bit if: 3688 * SR-IOV is enabled 3689 * or 3690 * Number of Rx queues > 1 and flow control is disabled 3691 * 3692 * This allows us to avoid head of line blocking for security 3693 * and performance reasons. 3694 */ 3695 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3696 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3697 for (i = 0; i < adapter->num_rx_queues; i++) 3698 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3699 } else { 3700 for (i = 0; i < adapter->num_rx_queues; i++) 3701 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3702 } 3703 } 3704 3705 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3706 3707 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3708 struct ixgbe_ring *rx_ring) 3709 { 3710 struct ixgbe_hw *hw = &adapter->hw; 3711 u32 srrctl; 3712 u8 reg_idx = rx_ring->reg_idx; 3713 3714 if (hw->mac.type == ixgbe_mac_82598EB) { 3715 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3716 3717 /* 3718 * if VMDq is not active we must program one srrctl register 3719 * per RSS queue since we have enabled RDRXCTL.MVMEN 3720 */ 3721 reg_idx &= mask; 3722 } 3723 3724 /* configure header buffer length, needed for RSC */ 3725 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3726 3727 /* configure the packet buffer length */ 3728 if (rx_ring->xsk_umem) { 3729 u32 xsk_buf_len = rx_ring->xsk_umem->chunk_size_nohr - 3730 XDP_PACKET_HEADROOM; 3731 3732 /* If the MAC support setting RXDCTL.RLPML, the 3733 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3734 * RXDCTL.RLPML is set to the actual UMEM buffer 3735 * size. If not, then we are stuck with a 1k buffer 3736 * size resolution. In this case frames larger than 3737 * the UMEM buffer size viewed in a 1k resolution will 3738 * be dropped. 3739 */ 3740 if (hw->mac.type != ixgbe_mac_82599EB) 3741 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3742 else 3743 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3744 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3745 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3746 } else { 3747 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3748 } 3749 3750 /* configure descriptor type */ 3751 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3752 3753 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3754 } 3755 3756 /** 3757 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3758 * @adapter: device handle 3759 * 3760 * - 82598/82599/X540: 128 3761 * - X550(non-SRIOV mode): 512 3762 * - X550(SRIOV mode): 64 3763 */ 3764 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3765 { 3766 if (adapter->hw.mac.type < ixgbe_mac_X550) 3767 return 128; 3768 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3769 return 64; 3770 else 3771 return 512; 3772 } 3773 3774 /** 3775 * ixgbe_store_key - Write the RSS key to HW 3776 * @adapter: device handle 3777 * 3778 * Write the RSS key stored in adapter.rss_key to HW. 3779 */ 3780 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3781 { 3782 struct ixgbe_hw *hw = &adapter->hw; 3783 int i; 3784 3785 for (i = 0; i < 10; i++) 3786 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3787 } 3788 3789 /** 3790 * ixgbe_init_rss_key - Initialize adapter RSS key 3791 * @adapter: device handle 3792 * 3793 * Allocates and initializes the RSS key if it is not allocated. 3794 **/ 3795 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3796 { 3797 u32 *rss_key; 3798 3799 if (!adapter->rss_key) { 3800 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3801 if (unlikely(!rss_key)) 3802 return -ENOMEM; 3803 3804 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3805 adapter->rss_key = rss_key; 3806 } 3807 3808 return 0; 3809 } 3810 3811 /** 3812 * ixgbe_store_reta - Write the RETA table to HW 3813 * @adapter: device handle 3814 * 3815 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3816 */ 3817 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3818 { 3819 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3820 struct ixgbe_hw *hw = &adapter->hw; 3821 u32 reta = 0; 3822 u32 indices_multi; 3823 u8 *indir_tbl = adapter->rss_indir_tbl; 3824 3825 /* Fill out the redirection table as follows: 3826 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3827 * indices. 3828 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3829 * - X550: 8 bit wide entries containing 6 bit RSS index 3830 */ 3831 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3832 indices_multi = 0x11; 3833 else 3834 indices_multi = 0x1; 3835 3836 /* Write redirection table to HW */ 3837 for (i = 0; i < reta_entries; i++) { 3838 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3839 if ((i & 3) == 3) { 3840 if (i < 128) 3841 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3842 else 3843 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3844 reta); 3845 reta = 0; 3846 } 3847 } 3848 } 3849 3850 /** 3851 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3852 * @adapter: device handle 3853 * 3854 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3855 */ 3856 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3857 { 3858 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3859 struct ixgbe_hw *hw = &adapter->hw; 3860 u32 vfreta = 0; 3861 3862 /* Write redirection table to HW */ 3863 for (i = 0; i < reta_entries; i++) { 3864 u16 pool = adapter->num_rx_pools; 3865 3866 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3867 if ((i & 3) != 3) 3868 continue; 3869 3870 while (pool--) 3871 IXGBE_WRITE_REG(hw, 3872 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3873 vfreta); 3874 vfreta = 0; 3875 } 3876 } 3877 3878 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3879 { 3880 u32 i, j; 3881 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3882 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3883 3884 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3885 * make full use of any rings they may have. We will use the 3886 * PSRTYPE register to control how many rings we use within the PF. 3887 */ 3888 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3889 rss_i = 4; 3890 3891 /* Fill out hash function seeds */ 3892 ixgbe_store_key(adapter); 3893 3894 /* Fill out redirection table */ 3895 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3896 3897 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3898 if (j == rss_i) 3899 j = 0; 3900 3901 adapter->rss_indir_tbl[i] = j; 3902 } 3903 3904 ixgbe_store_reta(adapter); 3905 } 3906 3907 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3908 { 3909 struct ixgbe_hw *hw = &adapter->hw; 3910 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3911 int i, j; 3912 3913 /* Fill out hash function seeds */ 3914 for (i = 0; i < 10; i++) { 3915 u16 pool = adapter->num_rx_pools; 3916 3917 while (pool--) 3918 IXGBE_WRITE_REG(hw, 3919 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3920 *(adapter->rss_key + i)); 3921 } 3922 3923 /* Fill out the redirection table */ 3924 for (i = 0, j = 0; i < 64; i++, j++) { 3925 if (j == rss_i) 3926 j = 0; 3927 3928 adapter->rss_indir_tbl[i] = j; 3929 } 3930 3931 ixgbe_store_vfreta(adapter); 3932 } 3933 3934 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3935 { 3936 struct ixgbe_hw *hw = &adapter->hw; 3937 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3938 u32 rxcsum; 3939 3940 /* Disable indicating checksum in descriptor, enables RSS hash */ 3941 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3942 rxcsum |= IXGBE_RXCSUM_PCSD; 3943 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3944 3945 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3946 if (adapter->ring_feature[RING_F_RSS].mask) 3947 mrqc = IXGBE_MRQC_RSSEN; 3948 } else { 3949 u8 tcs = adapter->hw_tcs; 3950 3951 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3952 if (tcs > 4) 3953 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3954 else if (tcs > 1) 3955 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3956 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3957 IXGBE_82599_VMDQ_4Q_MASK) 3958 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3959 else 3960 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3961 3962 /* Enable L3/L4 for Tx Switched packets only for X550, 3963 * older devices do not support this feature 3964 */ 3965 if (hw->mac.type >= ixgbe_mac_X550) 3966 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3967 } else { 3968 if (tcs > 4) 3969 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3970 else if (tcs > 1) 3971 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3972 else 3973 mrqc = IXGBE_MRQC_RSSEN; 3974 } 3975 } 3976 3977 /* Perform hash on these packet types */ 3978 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3979 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3980 IXGBE_MRQC_RSS_FIELD_IPV6 | 3981 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3982 3983 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3984 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3985 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3986 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3987 3988 if ((hw->mac.type >= ixgbe_mac_X550) && 3989 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3990 u16 pool = adapter->num_rx_pools; 3991 3992 /* Enable VF RSS mode */ 3993 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3994 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3995 3996 /* Setup RSS through the VF registers */ 3997 ixgbe_setup_vfreta(adapter); 3998 vfmrqc = IXGBE_MRQC_RSSEN; 3999 vfmrqc |= rss_field; 4000 4001 while (pool--) 4002 IXGBE_WRITE_REG(hw, 4003 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4004 vfmrqc); 4005 } else { 4006 ixgbe_setup_reta(adapter); 4007 mrqc |= rss_field; 4008 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4009 } 4010 } 4011 4012 /** 4013 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4014 * @adapter: address of board private structure 4015 * @ring: structure containing ring specific data 4016 **/ 4017 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4018 struct ixgbe_ring *ring) 4019 { 4020 struct ixgbe_hw *hw = &adapter->hw; 4021 u32 rscctrl; 4022 u8 reg_idx = ring->reg_idx; 4023 4024 if (!ring_is_rsc_enabled(ring)) 4025 return; 4026 4027 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4028 rscctrl |= IXGBE_RSCCTL_RSCEN; 4029 /* 4030 * we must limit the number of descriptors so that the 4031 * total size of max desc * buf_len is not greater 4032 * than 65536 4033 */ 4034 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4035 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4036 } 4037 4038 #define IXGBE_MAX_RX_DESC_POLL 10 4039 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4040 struct ixgbe_ring *ring) 4041 { 4042 struct ixgbe_hw *hw = &adapter->hw; 4043 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4044 u32 rxdctl; 4045 u8 reg_idx = ring->reg_idx; 4046 4047 if (ixgbe_removed(hw->hw_addr)) 4048 return; 4049 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4050 if (hw->mac.type == ixgbe_mac_82598EB && 4051 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4052 return; 4053 4054 do { 4055 usleep_range(1000, 2000); 4056 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4057 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4058 4059 if (!wait_loop) { 4060 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4061 "the polling period\n", reg_idx); 4062 } 4063 } 4064 4065 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4066 struct ixgbe_ring *ring) 4067 { 4068 struct ixgbe_hw *hw = &adapter->hw; 4069 union ixgbe_adv_rx_desc *rx_desc; 4070 u64 rdba = ring->dma; 4071 u32 rxdctl; 4072 u8 reg_idx = ring->reg_idx; 4073 4074 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4075 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 4076 if (ring->xsk_umem) { 4077 ring->zca.free = ixgbe_zca_free; 4078 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4079 MEM_TYPE_ZERO_COPY, 4080 &ring->zca)); 4081 4082 } else { 4083 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4084 MEM_TYPE_PAGE_SHARED, NULL)); 4085 } 4086 4087 /* disable queue to avoid use of these values while updating state */ 4088 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4089 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4090 4091 /* write value back with RXDCTL.ENABLE bit cleared */ 4092 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4093 IXGBE_WRITE_FLUSH(hw); 4094 4095 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4096 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4097 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4098 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4099 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4100 IXGBE_WRITE_FLUSH(hw); 4101 4102 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4103 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4104 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4105 4106 ixgbe_configure_srrctl(adapter, ring); 4107 ixgbe_configure_rscctl(adapter, ring); 4108 4109 if (hw->mac.type == ixgbe_mac_82598EB) { 4110 /* 4111 * enable cache line friendly hardware writes: 4112 * PTHRESH=32 descriptors (half the internal cache), 4113 * this also removes ugly rx_no_buffer_count increment 4114 * HTHRESH=4 descriptors (to minimize latency on fetch) 4115 * WTHRESH=8 burst writeback up to two cache lines 4116 */ 4117 rxdctl &= ~0x3FFFFF; 4118 rxdctl |= 0x080420; 4119 #if (PAGE_SIZE < 8192) 4120 /* RXDCTL.RLPML does not work on 82599 */ 4121 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4122 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4123 IXGBE_RXDCTL_RLPML_EN); 4124 4125 /* Limit the maximum frame size so we don't overrun the skb. 4126 * This can happen in SRIOV mode when the MTU of the VF is 4127 * higher than the MTU of the PF. 4128 */ 4129 if (ring_uses_build_skb(ring) && 4130 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4131 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4132 IXGBE_RXDCTL_RLPML_EN; 4133 #endif 4134 } 4135 4136 if (ring->xsk_umem && hw->mac.type != ixgbe_mac_82599EB) { 4137 u32 xsk_buf_len = ring->xsk_umem->chunk_size_nohr - 4138 XDP_PACKET_HEADROOM; 4139 4140 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4141 IXGBE_RXDCTL_RLPML_EN); 4142 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4143 4144 ring->rx_buf_len = xsk_buf_len; 4145 } 4146 4147 /* initialize rx_buffer_info */ 4148 memset(ring->rx_buffer_info, 0, 4149 sizeof(struct ixgbe_rx_buffer) * ring->count); 4150 4151 /* initialize Rx descriptor 0 */ 4152 rx_desc = IXGBE_RX_DESC(ring, 0); 4153 rx_desc->wb.upper.length = 0; 4154 4155 /* enable receive descriptor ring */ 4156 rxdctl |= IXGBE_RXDCTL_ENABLE; 4157 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4158 4159 ixgbe_rx_desc_queue_enable(adapter, ring); 4160 if (ring->xsk_umem) 4161 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4162 else 4163 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4164 } 4165 4166 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4167 { 4168 struct ixgbe_hw *hw = &adapter->hw; 4169 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4170 u16 pool = adapter->num_rx_pools; 4171 4172 /* PSRTYPE must be initialized in non 82598 adapters */ 4173 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4174 IXGBE_PSRTYPE_UDPHDR | 4175 IXGBE_PSRTYPE_IPV4HDR | 4176 IXGBE_PSRTYPE_L2HDR | 4177 IXGBE_PSRTYPE_IPV6HDR; 4178 4179 if (hw->mac.type == ixgbe_mac_82598EB) 4180 return; 4181 4182 if (rss_i > 3) 4183 psrtype |= 2u << 29; 4184 else if (rss_i > 1) 4185 psrtype |= 1u << 29; 4186 4187 while (pool--) 4188 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4189 } 4190 4191 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4192 { 4193 struct ixgbe_hw *hw = &adapter->hw; 4194 u16 pool = adapter->num_rx_pools; 4195 u32 reg_offset, vf_shift, vmolr; 4196 u32 gcr_ext, vmdctl; 4197 int i; 4198 4199 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4200 return; 4201 4202 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4203 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4204 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4205 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4206 vmdctl |= IXGBE_VT_CTL_REPLEN; 4207 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4208 4209 /* accept untagged packets until a vlan tag is 4210 * specifically set for the VMDQ queue/pool 4211 */ 4212 vmolr = IXGBE_VMOLR_AUPE; 4213 while (pool--) 4214 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4215 4216 vf_shift = VMDQ_P(0) % 32; 4217 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4218 4219 /* Enable only the PF's pool for Tx/Rx */ 4220 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4221 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4222 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4223 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4224 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4225 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4226 4227 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4228 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4229 4230 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4231 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4232 4233 /* 4234 * Set up VF register offsets for selected VT Mode, 4235 * i.e. 32 or 64 VFs for SR-IOV 4236 */ 4237 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4238 case IXGBE_82599_VMDQ_8Q_MASK: 4239 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4240 break; 4241 case IXGBE_82599_VMDQ_4Q_MASK: 4242 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4243 break; 4244 default: 4245 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4246 break; 4247 } 4248 4249 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4250 4251 for (i = 0; i < adapter->num_vfs; i++) { 4252 /* configure spoof checking */ 4253 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4254 adapter->vfinfo[i].spoofchk_enabled); 4255 4256 /* Enable/Disable RSS query feature */ 4257 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4258 adapter->vfinfo[i].rss_query_enabled); 4259 } 4260 } 4261 4262 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4263 { 4264 struct ixgbe_hw *hw = &adapter->hw; 4265 struct net_device *netdev = adapter->netdev; 4266 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4267 struct ixgbe_ring *rx_ring; 4268 int i; 4269 u32 mhadd, hlreg0; 4270 4271 #ifdef IXGBE_FCOE 4272 /* adjust max frame to be able to do baby jumbo for FCoE */ 4273 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4274 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4275 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4276 4277 #endif /* IXGBE_FCOE */ 4278 4279 /* adjust max frame to be at least the size of a standard frame */ 4280 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4281 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4282 4283 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4284 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4285 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4286 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4287 4288 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4289 } 4290 4291 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4292 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4293 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4294 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4295 4296 /* 4297 * Setup the HW Rx Head and Tail Descriptor Pointers and 4298 * the Base and Length of the Rx Descriptor Ring 4299 */ 4300 for (i = 0; i < adapter->num_rx_queues; i++) { 4301 rx_ring = adapter->rx_ring[i]; 4302 4303 clear_ring_rsc_enabled(rx_ring); 4304 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4305 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4306 4307 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4308 set_ring_rsc_enabled(rx_ring); 4309 4310 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4311 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4312 4313 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4314 continue; 4315 4316 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4317 4318 #if (PAGE_SIZE < 8192) 4319 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4320 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4321 4322 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4323 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4324 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4325 #endif 4326 } 4327 } 4328 4329 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4330 { 4331 struct ixgbe_hw *hw = &adapter->hw; 4332 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4333 4334 switch (hw->mac.type) { 4335 case ixgbe_mac_82598EB: 4336 /* 4337 * For VMDq support of different descriptor types or 4338 * buffer sizes through the use of multiple SRRCTL 4339 * registers, RDRXCTL.MVMEN must be set to 1 4340 * 4341 * also, the manual doesn't mention it clearly but DCA hints 4342 * will only use queue 0's tags unless this bit is set. Side 4343 * effects of setting this bit are only that SRRCTL must be 4344 * fully programmed [0..15] 4345 */ 4346 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4347 break; 4348 case ixgbe_mac_X550: 4349 case ixgbe_mac_X550EM_x: 4350 case ixgbe_mac_x550em_a: 4351 if (adapter->num_vfs) 4352 rdrxctl |= IXGBE_RDRXCTL_PSP; 4353 /* fall through */ 4354 case ixgbe_mac_82599EB: 4355 case ixgbe_mac_X540: 4356 /* Disable RSC for ACK packets */ 4357 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4358 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4359 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4360 /* hardware requires some bits to be set by default */ 4361 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4362 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4363 break; 4364 default: 4365 /* We should do nothing since we don't know this hardware */ 4366 return; 4367 } 4368 4369 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4370 } 4371 4372 /** 4373 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4374 * @adapter: board private structure 4375 * 4376 * Configure the Rx unit of the MAC after a reset. 4377 **/ 4378 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4379 { 4380 struct ixgbe_hw *hw = &adapter->hw; 4381 int i; 4382 u32 rxctrl, rfctl; 4383 4384 /* disable receives while setting up the descriptors */ 4385 hw->mac.ops.disable_rx(hw); 4386 4387 ixgbe_setup_psrtype(adapter); 4388 ixgbe_setup_rdrxctl(adapter); 4389 4390 /* RSC Setup */ 4391 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4392 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4393 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4394 rfctl |= IXGBE_RFCTL_RSC_DIS; 4395 4396 /* disable NFS filtering */ 4397 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4398 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4399 4400 /* Program registers for the distribution of queues */ 4401 ixgbe_setup_mrqc(adapter); 4402 4403 /* set_rx_buffer_len must be called before ring initialization */ 4404 ixgbe_set_rx_buffer_len(adapter); 4405 4406 /* 4407 * Setup the HW Rx Head and Tail Descriptor Pointers and 4408 * the Base and Length of the Rx Descriptor Ring 4409 */ 4410 for (i = 0; i < adapter->num_rx_queues; i++) 4411 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4412 4413 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4414 /* disable drop enable for 82598 parts */ 4415 if (hw->mac.type == ixgbe_mac_82598EB) 4416 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4417 4418 /* enable all receives */ 4419 rxctrl |= IXGBE_RXCTRL_RXEN; 4420 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4421 } 4422 4423 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4424 __be16 proto, u16 vid) 4425 { 4426 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4427 struct ixgbe_hw *hw = &adapter->hw; 4428 4429 /* add VID to filter table */ 4430 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4431 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4432 4433 set_bit(vid, adapter->active_vlans); 4434 4435 return 0; 4436 } 4437 4438 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4439 { 4440 u32 vlvf; 4441 int idx; 4442 4443 /* short cut the special case */ 4444 if (vlan == 0) 4445 return 0; 4446 4447 /* Search for the vlan id in the VLVF entries */ 4448 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4449 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4450 if ((vlvf & VLAN_VID_MASK) == vlan) 4451 break; 4452 } 4453 4454 return idx; 4455 } 4456 4457 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4458 { 4459 struct ixgbe_hw *hw = &adapter->hw; 4460 u32 bits, word; 4461 int idx; 4462 4463 idx = ixgbe_find_vlvf_entry(hw, vid); 4464 if (!idx) 4465 return; 4466 4467 /* See if any other pools are set for this VLAN filter 4468 * entry other than the PF. 4469 */ 4470 word = idx * 2 + (VMDQ_P(0) / 32); 4471 bits = ~BIT(VMDQ_P(0) % 32); 4472 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4473 4474 /* Disable the filter so this falls into the default pool. */ 4475 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4476 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4477 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4478 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4479 } 4480 } 4481 4482 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4483 __be16 proto, u16 vid) 4484 { 4485 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4486 struct ixgbe_hw *hw = &adapter->hw; 4487 4488 /* remove VID from filter table */ 4489 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4490 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4491 4492 clear_bit(vid, adapter->active_vlans); 4493 4494 return 0; 4495 } 4496 4497 /** 4498 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4499 * @adapter: driver data 4500 */ 4501 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4502 { 4503 struct ixgbe_hw *hw = &adapter->hw; 4504 u32 vlnctrl; 4505 int i, j; 4506 4507 switch (hw->mac.type) { 4508 case ixgbe_mac_82598EB: 4509 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4510 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4511 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4512 break; 4513 case ixgbe_mac_82599EB: 4514 case ixgbe_mac_X540: 4515 case ixgbe_mac_X550: 4516 case ixgbe_mac_X550EM_x: 4517 case ixgbe_mac_x550em_a: 4518 for (i = 0; i < adapter->num_rx_queues; i++) { 4519 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4520 4521 if (!netif_is_ixgbe(ring->netdev)) 4522 continue; 4523 4524 j = ring->reg_idx; 4525 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4526 vlnctrl &= ~IXGBE_RXDCTL_VME; 4527 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4528 } 4529 break; 4530 default: 4531 break; 4532 } 4533 } 4534 4535 /** 4536 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4537 * @adapter: driver data 4538 */ 4539 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4540 { 4541 struct ixgbe_hw *hw = &adapter->hw; 4542 u32 vlnctrl; 4543 int i, j; 4544 4545 switch (hw->mac.type) { 4546 case ixgbe_mac_82598EB: 4547 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4548 vlnctrl |= IXGBE_VLNCTRL_VME; 4549 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4550 break; 4551 case ixgbe_mac_82599EB: 4552 case ixgbe_mac_X540: 4553 case ixgbe_mac_X550: 4554 case ixgbe_mac_X550EM_x: 4555 case ixgbe_mac_x550em_a: 4556 for (i = 0; i < adapter->num_rx_queues; i++) { 4557 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4558 4559 if (!netif_is_ixgbe(ring->netdev)) 4560 continue; 4561 4562 j = ring->reg_idx; 4563 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4564 vlnctrl |= IXGBE_RXDCTL_VME; 4565 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4566 } 4567 break; 4568 default: 4569 break; 4570 } 4571 } 4572 4573 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4574 { 4575 struct ixgbe_hw *hw = &adapter->hw; 4576 u32 vlnctrl, i; 4577 4578 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4579 4580 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4581 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4582 vlnctrl |= IXGBE_VLNCTRL_VFE; 4583 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4584 } else { 4585 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4586 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4587 return; 4588 } 4589 4590 /* Nothing to do for 82598 */ 4591 if (hw->mac.type == ixgbe_mac_82598EB) 4592 return; 4593 4594 /* We are already in VLAN promisc, nothing to do */ 4595 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4596 return; 4597 4598 /* Set flag so we don't redo unnecessary work */ 4599 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4600 4601 /* Add PF to all active pools */ 4602 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4603 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4604 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4605 4606 vlvfb |= BIT(VMDQ_P(0) % 32); 4607 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4608 } 4609 4610 /* Set all bits in the VLAN filter table array */ 4611 for (i = hw->mac.vft_size; i--;) 4612 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4613 } 4614 4615 #define VFTA_BLOCK_SIZE 8 4616 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4617 { 4618 struct ixgbe_hw *hw = &adapter->hw; 4619 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4620 u32 vid_start = vfta_offset * 32; 4621 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4622 u32 i, vid, word, bits; 4623 4624 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4625 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4626 4627 /* pull VLAN ID from VLVF */ 4628 vid = vlvf & VLAN_VID_MASK; 4629 4630 /* only concern outselves with a certain range */ 4631 if (vid < vid_start || vid >= vid_end) 4632 continue; 4633 4634 if (vlvf) { 4635 /* record VLAN ID in VFTA */ 4636 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4637 4638 /* if PF is part of this then continue */ 4639 if (test_bit(vid, adapter->active_vlans)) 4640 continue; 4641 } 4642 4643 /* remove PF from the pool */ 4644 word = i * 2 + VMDQ_P(0) / 32; 4645 bits = ~BIT(VMDQ_P(0) % 32); 4646 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4647 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4648 } 4649 4650 /* extract values from active_vlans and write back to VFTA */ 4651 for (i = VFTA_BLOCK_SIZE; i--;) { 4652 vid = (vfta_offset + i) * 32; 4653 word = vid / BITS_PER_LONG; 4654 bits = vid % BITS_PER_LONG; 4655 4656 vfta[i] |= adapter->active_vlans[word] >> bits; 4657 4658 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4659 } 4660 } 4661 4662 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4663 { 4664 struct ixgbe_hw *hw = &adapter->hw; 4665 u32 vlnctrl, i; 4666 4667 /* Set VLAN filtering to enabled */ 4668 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4669 vlnctrl |= IXGBE_VLNCTRL_VFE; 4670 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4671 4672 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4673 hw->mac.type == ixgbe_mac_82598EB) 4674 return; 4675 4676 /* We are not in VLAN promisc, nothing to do */ 4677 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4678 return; 4679 4680 /* Set flag so we don't redo unnecessary work */ 4681 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4682 4683 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4684 ixgbe_scrub_vfta(adapter, i); 4685 } 4686 4687 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4688 { 4689 u16 vid = 1; 4690 4691 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4692 4693 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4694 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4695 } 4696 4697 /** 4698 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4699 * @netdev: network interface device structure 4700 * 4701 * Writes multicast address list to the MTA hash table. 4702 * Returns: -ENOMEM on failure 4703 * 0 on no addresses written 4704 * X on writing X addresses to MTA 4705 **/ 4706 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4707 { 4708 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4709 struct ixgbe_hw *hw = &adapter->hw; 4710 4711 if (!netif_running(netdev)) 4712 return 0; 4713 4714 if (hw->mac.ops.update_mc_addr_list) 4715 hw->mac.ops.update_mc_addr_list(hw, netdev); 4716 else 4717 return -ENOMEM; 4718 4719 #ifdef CONFIG_PCI_IOV 4720 ixgbe_restore_vf_multicasts(adapter); 4721 #endif 4722 4723 return netdev_mc_count(netdev); 4724 } 4725 4726 #ifdef CONFIG_PCI_IOV 4727 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4728 { 4729 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4730 struct ixgbe_hw *hw = &adapter->hw; 4731 int i; 4732 4733 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4734 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4735 4736 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4737 hw->mac.ops.set_rar(hw, i, 4738 mac_table->addr, 4739 mac_table->pool, 4740 IXGBE_RAH_AV); 4741 else 4742 hw->mac.ops.clear_rar(hw, i); 4743 } 4744 } 4745 4746 #endif 4747 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4748 { 4749 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4750 struct ixgbe_hw *hw = &adapter->hw; 4751 int i; 4752 4753 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4754 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4755 continue; 4756 4757 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4758 4759 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4760 hw->mac.ops.set_rar(hw, i, 4761 mac_table->addr, 4762 mac_table->pool, 4763 IXGBE_RAH_AV); 4764 else 4765 hw->mac.ops.clear_rar(hw, i); 4766 } 4767 } 4768 4769 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4770 { 4771 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4772 struct ixgbe_hw *hw = &adapter->hw; 4773 int i; 4774 4775 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4776 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4777 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4778 } 4779 4780 ixgbe_sync_mac_table(adapter); 4781 } 4782 4783 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4784 { 4785 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4786 struct ixgbe_hw *hw = &adapter->hw; 4787 int i, count = 0; 4788 4789 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4790 /* do not count default RAR as available */ 4791 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4792 continue; 4793 4794 /* only count unused and addresses that belong to us */ 4795 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4796 if (mac_table->pool != pool) 4797 continue; 4798 } 4799 4800 count++; 4801 } 4802 4803 return count; 4804 } 4805 4806 /* this function destroys the first RAR entry */ 4807 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4808 { 4809 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4810 struct ixgbe_hw *hw = &adapter->hw; 4811 4812 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4813 mac_table->pool = VMDQ_P(0); 4814 4815 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4816 4817 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4818 IXGBE_RAH_AV); 4819 } 4820 4821 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4822 const u8 *addr, u16 pool) 4823 { 4824 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4825 struct ixgbe_hw *hw = &adapter->hw; 4826 int i; 4827 4828 if (is_zero_ether_addr(addr)) 4829 return -EINVAL; 4830 4831 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4832 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4833 continue; 4834 4835 ether_addr_copy(mac_table->addr, addr); 4836 mac_table->pool = pool; 4837 4838 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4839 IXGBE_MAC_STATE_IN_USE; 4840 4841 ixgbe_sync_mac_table(adapter); 4842 4843 return i; 4844 } 4845 4846 return -ENOMEM; 4847 } 4848 4849 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4850 const u8 *addr, u16 pool) 4851 { 4852 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4853 struct ixgbe_hw *hw = &adapter->hw; 4854 int i; 4855 4856 if (is_zero_ether_addr(addr)) 4857 return -EINVAL; 4858 4859 /* search table for addr, if found clear IN_USE flag and sync */ 4860 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4861 /* we can only delete an entry if it is in use */ 4862 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4863 continue; 4864 /* we only care about entries that belong to the given pool */ 4865 if (mac_table->pool != pool) 4866 continue; 4867 /* we only care about a specific MAC address */ 4868 if (!ether_addr_equal(addr, mac_table->addr)) 4869 continue; 4870 4871 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4872 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4873 4874 ixgbe_sync_mac_table(adapter); 4875 4876 return 0; 4877 } 4878 4879 return -ENOMEM; 4880 } 4881 4882 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4883 { 4884 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4885 int ret; 4886 4887 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4888 4889 return min_t(int, ret, 0); 4890 } 4891 4892 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4893 { 4894 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4895 4896 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4897 4898 return 0; 4899 } 4900 4901 /** 4902 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4903 * @netdev: network interface device structure 4904 * 4905 * The set_rx_method entry point is called whenever the unicast/multicast 4906 * address list or the network interface flags are updated. This routine is 4907 * responsible for configuring the hardware for proper unicast, multicast and 4908 * promiscuous mode. 4909 **/ 4910 void ixgbe_set_rx_mode(struct net_device *netdev) 4911 { 4912 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4913 struct ixgbe_hw *hw = &adapter->hw; 4914 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4915 netdev_features_t features = netdev->features; 4916 int count; 4917 4918 /* Check for Promiscuous and All Multicast modes */ 4919 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4920 4921 /* set all bits that we expect to always be set */ 4922 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4923 fctrl |= IXGBE_FCTRL_BAM; 4924 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4925 fctrl |= IXGBE_FCTRL_PMCF; 4926 4927 /* clear the bits we are changing the status of */ 4928 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4929 if (netdev->flags & IFF_PROMISC) { 4930 hw->addr_ctrl.user_set_promisc = true; 4931 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4932 vmolr |= IXGBE_VMOLR_MPE; 4933 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4934 } else { 4935 if (netdev->flags & IFF_ALLMULTI) { 4936 fctrl |= IXGBE_FCTRL_MPE; 4937 vmolr |= IXGBE_VMOLR_MPE; 4938 } 4939 hw->addr_ctrl.user_set_promisc = false; 4940 } 4941 4942 /* 4943 * Write addresses to available RAR registers, if there is not 4944 * sufficient space to store all the addresses then enable 4945 * unicast promiscuous mode 4946 */ 4947 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4948 fctrl |= IXGBE_FCTRL_UPE; 4949 vmolr |= IXGBE_VMOLR_ROPE; 4950 } 4951 4952 /* Write addresses to the MTA, if the attempt fails 4953 * then we should just turn on promiscuous mode so 4954 * that we can at least receive multicast traffic 4955 */ 4956 count = ixgbe_write_mc_addr_list(netdev); 4957 if (count < 0) { 4958 fctrl |= IXGBE_FCTRL_MPE; 4959 vmolr |= IXGBE_VMOLR_MPE; 4960 } else if (count) { 4961 vmolr |= IXGBE_VMOLR_ROMPE; 4962 } 4963 4964 if (hw->mac.type != ixgbe_mac_82598EB) { 4965 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4966 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4967 IXGBE_VMOLR_ROPE); 4968 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4969 } 4970 4971 /* This is useful for sniffing bad packets. */ 4972 if (features & NETIF_F_RXALL) { 4973 /* UPE and MPE will be handled by normal PROMISC logic 4974 * in e1000e_set_rx_mode */ 4975 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4976 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4977 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4978 4979 fctrl &= ~(IXGBE_FCTRL_DPF); 4980 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4981 } 4982 4983 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4984 4985 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4986 ixgbe_vlan_strip_enable(adapter); 4987 else 4988 ixgbe_vlan_strip_disable(adapter); 4989 4990 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4991 ixgbe_vlan_promisc_disable(adapter); 4992 else 4993 ixgbe_vlan_promisc_enable(adapter); 4994 } 4995 4996 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4997 { 4998 int q_idx; 4999 5000 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5001 napi_enable(&adapter->q_vector[q_idx]->napi); 5002 } 5003 5004 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5005 { 5006 int q_idx; 5007 5008 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5009 napi_disable(&adapter->q_vector[q_idx]->napi); 5010 } 5011 5012 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5013 { 5014 struct ixgbe_hw *hw = &adapter->hw; 5015 u32 vxlanctrl; 5016 5017 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5018 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5019 return; 5020 5021 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5022 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5023 5024 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5025 adapter->vxlan_port = 0; 5026 5027 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5028 adapter->geneve_port = 0; 5029 } 5030 5031 #ifdef CONFIG_IXGBE_DCB 5032 /** 5033 * ixgbe_configure_dcb - Configure DCB hardware 5034 * @adapter: ixgbe adapter struct 5035 * 5036 * This is called by the driver on open to configure the DCB hardware. 5037 * This is also called by the gennetlink interface when reconfiguring 5038 * the DCB state. 5039 */ 5040 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5041 { 5042 struct ixgbe_hw *hw = &adapter->hw; 5043 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5044 5045 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5046 if (hw->mac.type == ixgbe_mac_82598EB) 5047 netif_set_gso_max_size(adapter->netdev, 65536); 5048 return; 5049 } 5050 5051 if (hw->mac.type == ixgbe_mac_82598EB) 5052 netif_set_gso_max_size(adapter->netdev, 32768); 5053 5054 #ifdef IXGBE_FCOE 5055 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5056 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5057 #endif 5058 5059 /* reconfigure the hardware */ 5060 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5061 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5062 DCB_TX_CONFIG); 5063 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5064 DCB_RX_CONFIG); 5065 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5066 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5067 ixgbe_dcb_hw_ets(&adapter->hw, 5068 adapter->ixgbe_ieee_ets, 5069 max_frame); 5070 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5071 adapter->ixgbe_ieee_pfc->pfc_en, 5072 adapter->ixgbe_ieee_ets->prio_tc); 5073 } 5074 5075 /* Enable RSS Hash per TC */ 5076 if (hw->mac.type != ixgbe_mac_82598EB) { 5077 u32 msb = 0; 5078 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5079 5080 while (rss_i) { 5081 msb++; 5082 rss_i >>= 1; 5083 } 5084 5085 /* write msb to all 8 TCs in one write */ 5086 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5087 } 5088 } 5089 #endif 5090 5091 /* Additional bittime to account for IXGBE framing */ 5092 #define IXGBE_ETH_FRAMING 20 5093 5094 /** 5095 * ixgbe_hpbthresh - calculate high water mark for flow control 5096 * 5097 * @adapter: board private structure to calculate for 5098 * @pb: packet buffer to calculate 5099 */ 5100 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5101 { 5102 struct ixgbe_hw *hw = &adapter->hw; 5103 struct net_device *dev = adapter->netdev; 5104 int link, tc, kb, marker; 5105 u32 dv_id, rx_pba; 5106 5107 /* Calculate max LAN frame size */ 5108 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5109 5110 #ifdef IXGBE_FCOE 5111 /* FCoE traffic class uses FCOE jumbo frames */ 5112 if ((dev->features & NETIF_F_FCOE_MTU) && 5113 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5114 (pb == ixgbe_fcoe_get_tc(adapter))) 5115 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5116 #endif 5117 5118 /* Calculate delay value for device */ 5119 switch (hw->mac.type) { 5120 case ixgbe_mac_X540: 5121 case ixgbe_mac_X550: 5122 case ixgbe_mac_X550EM_x: 5123 case ixgbe_mac_x550em_a: 5124 dv_id = IXGBE_DV_X540(link, tc); 5125 break; 5126 default: 5127 dv_id = IXGBE_DV(link, tc); 5128 break; 5129 } 5130 5131 /* Loopback switch introduces additional latency */ 5132 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5133 dv_id += IXGBE_B2BT(tc); 5134 5135 /* Delay value is calculated in bit times convert to KB */ 5136 kb = IXGBE_BT2KB(dv_id); 5137 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5138 5139 marker = rx_pba - kb; 5140 5141 /* It is possible that the packet buffer is not large enough 5142 * to provide required headroom. In this case throw an error 5143 * to user and a do the best we can. 5144 */ 5145 if (marker < 0) { 5146 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5147 "headroom to support flow control." 5148 "Decrease MTU or number of traffic classes\n", pb); 5149 marker = tc + 1; 5150 } 5151 5152 return marker; 5153 } 5154 5155 /** 5156 * ixgbe_lpbthresh - calculate low water mark for for flow control 5157 * 5158 * @adapter: board private structure to calculate for 5159 * @pb: packet buffer to calculate 5160 */ 5161 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5162 { 5163 struct ixgbe_hw *hw = &adapter->hw; 5164 struct net_device *dev = adapter->netdev; 5165 int tc; 5166 u32 dv_id; 5167 5168 /* Calculate max LAN frame size */ 5169 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5170 5171 #ifdef IXGBE_FCOE 5172 /* FCoE traffic class uses FCOE jumbo frames */ 5173 if ((dev->features & NETIF_F_FCOE_MTU) && 5174 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5175 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5176 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5177 #endif 5178 5179 /* Calculate delay value for device */ 5180 switch (hw->mac.type) { 5181 case ixgbe_mac_X540: 5182 case ixgbe_mac_X550: 5183 case ixgbe_mac_X550EM_x: 5184 case ixgbe_mac_x550em_a: 5185 dv_id = IXGBE_LOW_DV_X540(tc); 5186 break; 5187 default: 5188 dv_id = IXGBE_LOW_DV(tc); 5189 break; 5190 } 5191 5192 /* Delay value is calculated in bit times convert to KB */ 5193 return IXGBE_BT2KB(dv_id); 5194 } 5195 5196 /* 5197 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5198 */ 5199 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5200 { 5201 struct ixgbe_hw *hw = &adapter->hw; 5202 int num_tc = adapter->hw_tcs; 5203 int i; 5204 5205 if (!num_tc) 5206 num_tc = 1; 5207 5208 for (i = 0; i < num_tc; i++) { 5209 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5210 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5211 5212 /* Low water marks must not be larger than high water marks */ 5213 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5214 hw->fc.low_water[i] = 0; 5215 } 5216 5217 for (; i < MAX_TRAFFIC_CLASS; i++) 5218 hw->fc.high_water[i] = 0; 5219 } 5220 5221 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5222 { 5223 struct ixgbe_hw *hw = &adapter->hw; 5224 int hdrm; 5225 u8 tc = adapter->hw_tcs; 5226 5227 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5228 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5229 hdrm = 32 << adapter->fdir_pballoc; 5230 else 5231 hdrm = 0; 5232 5233 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5234 ixgbe_pbthresh_setup(adapter); 5235 } 5236 5237 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5238 { 5239 struct ixgbe_hw *hw = &adapter->hw; 5240 struct hlist_node *node2; 5241 struct ixgbe_fdir_filter *filter; 5242 u64 action; 5243 5244 spin_lock(&adapter->fdir_perfect_lock); 5245 5246 if (!hlist_empty(&adapter->fdir_filter_list)) 5247 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5248 5249 hlist_for_each_entry_safe(filter, node2, 5250 &adapter->fdir_filter_list, fdir_node) { 5251 action = filter->action; 5252 if (action != IXGBE_FDIR_DROP_QUEUE && action != 0) 5253 action = 5254 (action >> ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF) - 1; 5255 5256 ixgbe_fdir_write_perfect_filter_82599(hw, 5257 &filter->filter, 5258 filter->sw_idx, 5259 (action == IXGBE_FDIR_DROP_QUEUE) ? 5260 IXGBE_FDIR_DROP_QUEUE : 5261 adapter->rx_ring[action]->reg_idx); 5262 } 5263 5264 spin_unlock(&adapter->fdir_perfect_lock); 5265 } 5266 5267 /** 5268 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5269 * @rx_ring: ring to free buffers from 5270 **/ 5271 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5272 { 5273 u16 i = rx_ring->next_to_clean; 5274 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5275 5276 if (rx_ring->xsk_umem) { 5277 ixgbe_xsk_clean_rx_ring(rx_ring); 5278 goto skip_free; 5279 } 5280 5281 /* Free all the Rx ring sk_buffs */ 5282 while (i != rx_ring->next_to_alloc) { 5283 if (rx_buffer->skb) { 5284 struct sk_buff *skb = rx_buffer->skb; 5285 if (IXGBE_CB(skb)->page_released) 5286 dma_unmap_page_attrs(rx_ring->dev, 5287 IXGBE_CB(skb)->dma, 5288 ixgbe_rx_pg_size(rx_ring), 5289 DMA_FROM_DEVICE, 5290 IXGBE_RX_DMA_ATTR); 5291 dev_kfree_skb(skb); 5292 } 5293 5294 /* Invalidate cache lines that may have been written to by 5295 * device so that we avoid corrupting memory. 5296 */ 5297 dma_sync_single_range_for_cpu(rx_ring->dev, 5298 rx_buffer->dma, 5299 rx_buffer->page_offset, 5300 ixgbe_rx_bufsz(rx_ring), 5301 DMA_FROM_DEVICE); 5302 5303 /* free resources associated with mapping */ 5304 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5305 ixgbe_rx_pg_size(rx_ring), 5306 DMA_FROM_DEVICE, 5307 IXGBE_RX_DMA_ATTR); 5308 __page_frag_cache_drain(rx_buffer->page, 5309 rx_buffer->pagecnt_bias); 5310 5311 i++; 5312 rx_buffer++; 5313 if (i == rx_ring->count) { 5314 i = 0; 5315 rx_buffer = rx_ring->rx_buffer_info; 5316 } 5317 } 5318 5319 skip_free: 5320 rx_ring->next_to_alloc = 0; 5321 rx_ring->next_to_clean = 0; 5322 rx_ring->next_to_use = 0; 5323 } 5324 5325 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5326 struct ixgbe_fwd_adapter *accel) 5327 { 5328 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5329 int num_tc = netdev_get_num_tc(adapter->netdev); 5330 struct net_device *vdev = accel->netdev; 5331 int i, baseq, err; 5332 5333 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5334 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5335 accel->pool, adapter->num_rx_pools, 5336 baseq, baseq + adapter->num_rx_queues_per_pool); 5337 5338 accel->rx_base_queue = baseq; 5339 accel->tx_base_queue = baseq; 5340 5341 /* record configuration for macvlan interface in vdev */ 5342 for (i = 0; i < num_tc; i++) 5343 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5344 i, rss_i, baseq + (rss_i * i)); 5345 5346 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5347 adapter->rx_ring[baseq + i]->netdev = vdev; 5348 5349 /* Guarantee all rings are updated before we update the 5350 * MAC address filter. 5351 */ 5352 wmb(); 5353 5354 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5355 * need to only treat it as an error value if it is negative. 5356 */ 5357 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5358 VMDQ_P(accel->pool)); 5359 if (err >= 0) 5360 return 0; 5361 5362 /* if we cannot add the MAC rule then disable the offload */ 5363 macvlan_release_l2fw_offload(vdev); 5364 5365 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5366 adapter->rx_ring[baseq + i]->netdev = NULL; 5367 5368 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5369 5370 /* unbind the queues and drop the subordinate channel config */ 5371 netdev_unbind_sb_channel(adapter->netdev, vdev); 5372 netdev_set_sb_channel(vdev, 0); 5373 5374 clear_bit(accel->pool, adapter->fwd_bitmask); 5375 kfree(accel); 5376 5377 return err; 5378 } 5379 5380 static int ixgbe_macvlan_up(struct net_device *vdev, void *data) 5381 { 5382 struct ixgbe_adapter *adapter = data; 5383 struct ixgbe_fwd_adapter *accel; 5384 5385 if (!netif_is_macvlan(vdev)) 5386 return 0; 5387 5388 accel = macvlan_accel_priv(vdev); 5389 if (!accel) 5390 return 0; 5391 5392 ixgbe_fwd_ring_up(adapter, accel); 5393 5394 return 0; 5395 } 5396 5397 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5398 { 5399 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5400 ixgbe_macvlan_up, adapter); 5401 } 5402 5403 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5404 { 5405 struct ixgbe_hw *hw = &adapter->hw; 5406 5407 ixgbe_configure_pb(adapter); 5408 #ifdef CONFIG_IXGBE_DCB 5409 ixgbe_configure_dcb(adapter); 5410 #endif 5411 /* 5412 * We must restore virtualization before VLANs or else 5413 * the VLVF registers will not be populated 5414 */ 5415 ixgbe_configure_virtualization(adapter); 5416 5417 ixgbe_set_rx_mode(adapter->netdev); 5418 ixgbe_restore_vlan(adapter); 5419 ixgbe_ipsec_restore(adapter); 5420 5421 switch (hw->mac.type) { 5422 case ixgbe_mac_82599EB: 5423 case ixgbe_mac_X540: 5424 hw->mac.ops.disable_rx_buff(hw); 5425 break; 5426 default: 5427 break; 5428 } 5429 5430 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5431 ixgbe_init_fdir_signature_82599(&adapter->hw, 5432 adapter->fdir_pballoc); 5433 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5434 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5435 adapter->fdir_pballoc); 5436 ixgbe_fdir_filter_restore(adapter); 5437 } 5438 5439 switch (hw->mac.type) { 5440 case ixgbe_mac_82599EB: 5441 case ixgbe_mac_X540: 5442 hw->mac.ops.enable_rx_buff(hw); 5443 break; 5444 default: 5445 break; 5446 } 5447 5448 #ifdef CONFIG_IXGBE_DCA 5449 /* configure DCA */ 5450 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5451 ixgbe_setup_dca(adapter); 5452 #endif /* CONFIG_IXGBE_DCA */ 5453 5454 #ifdef IXGBE_FCOE 5455 /* configure FCoE L2 filters, redirection table, and Rx control */ 5456 ixgbe_configure_fcoe(adapter); 5457 5458 #endif /* IXGBE_FCOE */ 5459 ixgbe_configure_tx(adapter); 5460 ixgbe_configure_rx(adapter); 5461 ixgbe_configure_dfwd(adapter); 5462 } 5463 5464 /** 5465 * ixgbe_sfp_link_config - set up SFP+ link 5466 * @adapter: pointer to private adapter struct 5467 **/ 5468 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5469 { 5470 /* 5471 * We are assuming the worst case scenario here, and that 5472 * is that an SFP was inserted/removed after the reset 5473 * but before SFP detection was enabled. As such the best 5474 * solution is to just start searching as soon as we start 5475 */ 5476 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5477 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5478 5479 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5480 adapter->sfp_poll_time = 0; 5481 } 5482 5483 /** 5484 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5485 * @hw: pointer to private hardware struct 5486 * 5487 * Returns 0 on success, negative on failure 5488 **/ 5489 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5490 { 5491 u32 speed; 5492 bool autoneg, link_up = false; 5493 int ret = IXGBE_ERR_LINK_SETUP; 5494 5495 if (hw->mac.ops.check_link) 5496 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5497 5498 if (ret) 5499 return ret; 5500 5501 speed = hw->phy.autoneg_advertised; 5502 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5503 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5504 &autoneg); 5505 if (ret) 5506 return ret; 5507 5508 if (hw->mac.ops.setup_link) 5509 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5510 5511 return ret; 5512 } 5513 5514 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5515 { 5516 struct ixgbe_hw *hw = &adapter->hw; 5517 u32 gpie = 0; 5518 5519 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5520 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5521 IXGBE_GPIE_OCD; 5522 gpie |= IXGBE_GPIE_EIAME; 5523 /* 5524 * use EIAM to auto-mask when MSI-X interrupt is asserted 5525 * this saves a register write for every interrupt 5526 */ 5527 switch (hw->mac.type) { 5528 case ixgbe_mac_82598EB: 5529 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5530 break; 5531 case ixgbe_mac_82599EB: 5532 case ixgbe_mac_X540: 5533 case ixgbe_mac_X550: 5534 case ixgbe_mac_X550EM_x: 5535 case ixgbe_mac_x550em_a: 5536 default: 5537 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5538 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5539 break; 5540 } 5541 } else { 5542 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5543 * specifically only auto mask tx and rx interrupts */ 5544 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5545 } 5546 5547 /* XXX: to interrupt immediately for EICS writes, enable this */ 5548 /* gpie |= IXGBE_GPIE_EIMEN; */ 5549 5550 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5551 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5552 5553 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5554 case IXGBE_82599_VMDQ_8Q_MASK: 5555 gpie |= IXGBE_GPIE_VTMODE_16; 5556 break; 5557 case IXGBE_82599_VMDQ_4Q_MASK: 5558 gpie |= IXGBE_GPIE_VTMODE_32; 5559 break; 5560 default: 5561 gpie |= IXGBE_GPIE_VTMODE_64; 5562 break; 5563 } 5564 } 5565 5566 /* Enable Thermal over heat sensor interrupt */ 5567 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5568 switch (adapter->hw.mac.type) { 5569 case ixgbe_mac_82599EB: 5570 gpie |= IXGBE_SDP0_GPIEN_8259X; 5571 break; 5572 default: 5573 break; 5574 } 5575 } 5576 5577 /* Enable fan failure interrupt */ 5578 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5579 gpie |= IXGBE_SDP1_GPIEN(hw); 5580 5581 switch (hw->mac.type) { 5582 case ixgbe_mac_82599EB: 5583 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5584 break; 5585 case ixgbe_mac_X550EM_x: 5586 case ixgbe_mac_x550em_a: 5587 gpie |= IXGBE_SDP0_GPIEN_X540; 5588 break; 5589 default: 5590 break; 5591 } 5592 5593 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5594 } 5595 5596 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5597 { 5598 struct ixgbe_hw *hw = &adapter->hw; 5599 int err; 5600 u32 ctrl_ext; 5601 5602 ixgbe_get_hw_control(adapter); 5603 ixgbe_setup_gpie(adapter); 5604 5605 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5606 ixgbe_configure_msix(adapter); 5607 else 5608 ixgbe_configure_msi_and_legacy(adapter); 5609 5610 /* enable the optics for 82599 SFP+ fiber */ 5611 if (hw->mac.ops.enable_tx_laser) 5612 hw->mac.ops.enable_tx_laser(hw); 5613 5614 if (hw->phy.ops.set_phy_power) 5615 hw->phy.ops.set_phy_power(hw, true); 5616 5617 smp_mb__before_atomic(); 5618 clear_bit(__IXGBE_DOWN, &adapter->state); 5619 ixgbe_napi_enable_all(adapter); 5620 5621 if (ixgbe_is_sfp(hw)) { 5622 ixgbe_sfp_link_config(adapter); 5623 } else { 5624 err = ixgbe_non_sfp_link_config(hw); 5625 if (err) 5626 e_err(probe, "link_config FAILED %d\n", err); 5627 } 5628 5629 /* clear any pending interrupts, may auto mask */ 5630 IXGBE_READ_REG(hw, IXGBE_EICR); 5631 ixgbe_irq_enable(adapter, true, true); 5632 5633 /* 5634 * If this adapter has a fan, check to see if we had a failure 5635 * before we enabled the interrupt. 5636 */ 5637 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5638 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5639 if (esdp & IXGBE_ESDP_SDP1) 5640 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5641 } 5642 5643 /* bring the link up in the watchdog, this could race with our first 5644 * link up interrupt but shouldn't be a problem */ 5645 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5646 adapter->link_check_timeout = jiffies; 5647 mod_timer(&adapter->service_timer, jiffies); 5648 5649 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5650 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5651 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5652 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5653 } 5654 5655 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5656 { 5657 WARN_ON(in_interrupt()); 5658 /* put off any impending NetWatchDogTimeout */ 5659 netif_trans_update(adapter->netdev); 5660 5661 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5662 usleep_range(1000, 2000); 5663 if (adapter->hw.phy.type == ixgbe_phy_fw) 5664 ixgbe_watchdog_link_is_down(adapter); 5665 ixgbe_down(adapter); 5666 /* 5667 * If SR-IOV enabled then wait a bit before bringing the adapter 5668 * back up to give the VFs time to respond to the reset. The 5669 * two second wait is based upon the watchdog timer cycle in 5670 * the VF driver. 5671 */ 5672 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5673 msleep(2000); 5674 ixgbe_up(adapter); 5675 clear_bit(__IXGBE_RESETTING, &adapter->state); 5676 } 5677 5678 void ixgbe_up(struct ixgbe_adapter *adapter) 5679 { 5680 /* hardware has been reset, we need to reload some things */ 5681 ixgbe_configure(adapter); 5682 5683 ixgbe_up_complete(adapter); 5684 } 5685 5686 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5687 { 5688 u16 devctl2; 5689 5690 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5691 5692 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5693 case IXGBE_PCIDEVCTRL2_17_34s: 5694 case IXGBE_PCIDEVCTRL2_4_8s: 5695 /* For now we cap the upper limit on delay to 2 seconds 5696 * as we end up going up to 34 seconds of delay in worst 5697 * case timeout value. 5698 */ 5699 case IXGBE_PCIDEVCTRL2_1_2s: 5700 return 2000000ul; /* 2.0 s */ 5701 case IXGBE_PCIDEVCTRL2_260_520ms: 5702 return 520000ul; /* 520 ms */ 5703 case IXGBE_PCIDEVCTRL2_65_130ms: 5704 return 130000ul; /* 130 ms */ 5705 case IXGBE_PCIDEVCTRL2_16_32ms: 5706 return 32000ul; /* 32 ms */ 5707 case IXGBE_PCIDEVCTRL2_1_2ms: 5708 return 2000ul; /* 2 ms */ 5709 case IXGBE_PCIDEVCTRL2_50_100us: 5710 return 100ul; /* 100 us */ 5711 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5712 return 32000ul; /* 32 ms */ 5713 default: 5714 break; 5715 } 5716 5717 /* We shouldn't need to hit this path, but just in case default as 5718 * though completion timeout is not supported and support 32ms. 5719 */ 5720 return 32000ul; 5721 } 5722 5723 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5724 { 5725 unsigned long wait_delay, delay_interval; 5726 struct ixgbe_hw *hw = &adapter->hw; 5727 int i, wait_loop; 5728 u32 rxdctl; 5729 5730 /* disable receives */ 5731 hw->mac.ops.disable_rx(hw); 5732 5733 if (ixgbe_removed(hw->hw_addr)) 5734 return; 5735 5736 /* disable all enabled Rx queues */ 5737 for (i = 0; i < adapter->num_rx_queues; i++) { 5738 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5739 u8 reg_idx = ring->reg_idx; 5740 5741 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5742 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5743 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5744 5745 /* write value back with RXDCTL.ENABLE bit cleared */ 5746 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5747 } 5748 5749 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5750 if (hw->mac.type == ixgbe_mac_82598EB && 5751 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5752 return; 5753 5754 /* Determine our minimum delay interval. We will increase this value 5755 * with each subsequent test. This way if the device returns quickly 5756 * we should spend as little time as possible waiting, however as 5757 * the time increases we will wait for larger periods of time. 5758 * 5759 * The trick here is that we increase the interval using the 5760 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5761 * of that wait is that it totals up to 100x whatever interval we 5762 * choose. Since our minimum wait is 100us we can just divide the 5763 * total timeout by 100 to get our minimum delay interval. 5764 */ 5765 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5766 5767 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5768 wait_delay = delay_interval; 5769 5770 while (wait_loop--) { 5771 usleep_range(wait_delay, wait_delay + 10); 5772 wait_delay += delay_interval * 2; 5773 rxdctl = 0; 5774 5775 /* OR together the reading of all the active RXDCTL registers, 5776 * and then test the result. We need the disable to complete 5777 * before we start freeing the memory and invalidating the 5778 * DMA mappings. 5779 */ 5780 for (i = 0; i < adapter->num_rx_queues; i++) { 5781 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5782 u8 reg_idx = ring->reg_idx; 5783 5784 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5785 } 5786 5787 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5788 return; 5789 } 5790 5791 e_err(drv, 5792 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5793 } 5794 5795 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5796 { 5797 unsigned long wait_delay, delay_interval; 5798 struct ixgbe_hw *hw = &adapter->hw; 5799 int i, wait_loop; 5800 u32 txdctl; 5801 5802 if (ixgbe_removed(hw->hw_addr)) 5803 return; 5804 5805 /* disable all enabled Tx queues */ 5806 for (i = 0; i < adapter->num_tx_queues; i++) { 5807 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5808 u8 reg_idx = ring->reg_idx; 5809 5810 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5811 } 5812 5813 /* disable all enabled XDP Tx queues */ 5814 for (i = 0; i < adapter->num_xdp_queues; i++) { 5815 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5816 u8 reg_idx = ring->reg_idx; 5817 5818 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5819 } 5820 5821 /* If the link is not up there shouldn't be much in the way of 5822 * pending transactions. Those that are left will be flushed out 5823 * when the reset logic goes through the flush sequence to clean out 5824 * the pending Tx transactions. 5825 */ 5826 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5827 goto dma_engine_disable; 5828 5829 /* Determine our minimum delay interval. We will increase this value 5830 * with each subsequent test. This way if the device returns quickly 5831 * we should spend as little time as possible waiting, however as 5832 * the time increases we will wait for larger periods of time. 5833 * 5834 * The trick here is that we increase the interval using the 5835 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5836 * of that wait is that it totals up to 100x whatever interval we 5837 * choose. Since our minimum wait is 100us we can just divide the 5838 * total timeout by 100 to get our minimum delay interval. 5839 */ 5840 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5841 5842 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5843 wait_delay = delay_interval; 5844 5845 while (wait_loop--) { 5846 usleep_range(wait_delay, wait_delay + 10); 5847 wait_delay += delay_interval * 2; 5848 txdctl = 0; 5849 5850 /* OR together the reading of all the active TXDCTL registers, 5851 * and then test the result. We need the disable to complete 5852 * before we start freeing the memory and invalidating the 5853 * DMA mappings. 5854 */ 5855 for (i = 0; i < adapter->num_tx_queues; i++) { 5856 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5857 u8 reg_idx = ring->reg_idx; 5858 5859 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5860 } 5861 for (i = 0; i < adapter->num_xdp_queues; i++) { 5862 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5863 u8 reg_idx = ring->reg_idx; 5864 5865 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5866 } 5867 5868 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5869 goto dma_engine_disable; 5870 } 5871 5872 e_err(drv, 5873 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5874 5875 dma_engine_disable: 5876 /* Disable the Tx DMA engine on 82599 and later MAC */ 5877 switch (hw->mac.type) { 5878 case ixgbe_mac_82599EB: 5879 case ixgbe_mac_X540: 5880 case ixgbe_mac_X550: 5881 case ixgbe_mac_X550EM_x: 5882 case ixgbe_mac_x550em_a: 5883 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5884 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5885 ~IXGBE_DMATXCTL_TE)); 5886 /* fall through */ 5887 default: 5888 break; 5889 } 5890 } 5891 5892 void ixgbe_reset(struct ixgbe_adapter *adapter) 5893 { 5894 struct ixgbe_hw *hw = &adapter->hw; 5895 struct net_device *netdev = adapter->netdev; 5896 int err; 5897 5898 if (ixgbe_removed(hw->hw_addr)) 5899 return; 5900 /* lock SFP init bit to prevent race conditions with the watchdog */ 5901 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5902 usleep_range(1000, 2000); 5903 5904 /* clear all SFP and link config related flags while holding SFP_INIT */ 5905 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5906 IXGBE_FLAG2_SFP_NEEDS_RESET); 5907 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5908 5909 err = hw->mac.ops.init_hw(hw); 5910 switch (err) { 5911 case 0: 5912 case IXGBE_ERR_SFP_NOT_PRESENT: 5913 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5914 break; 5915 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5916 e_dev_err("master disable timed out\n"); 5917 break; 5918 case IXGBE_ERR_EEPROM_VERSION: 5919 /* We are running on a pre-production device, log a warning */ 5920 e_dev_warn("This device is a pre-production adapter/LOM. " 5921 "Please be aware there may be issues associated with " 5922 "your hardware. If you are experiencing problems " 5923 "please contact your Intel or hardware " 5924 "representative who provided you with this " 5925 "hardware.\n"); 5926 break; 5927 default: 5928 e_dev_err("Hardware Error: %d\n", err); 5929 } 5930 5931 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5932 5933 /* flush entries out of MAC table */ 5934 ixgbe_flush_sw_mac_table(adapter); 5935 __dev_uc_unsync(netdev, NULL); 5936 5937 /* do not flush user set addresses */ 5938 ixgbe_mac_set_default_filter(adapter); 5939 5940 /* update SAN MAC vmdq pool selection */ 5941 if (hw->mac.san_mac_rar_index) 5942 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5943 5944 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5945 ixgbe_ptp_reset(adapter); 5946 5947 if (hw->phy.ops.set_phy_power) { 5948 if (!netif_running(adapter->netdev) && !adapter->wol) 5949 hw->phy.ops.set_phy_power(hw, false); 5950 else 5951 hw->phy.ops.set_phy_power(hw, true); 5952 } 5953 } 5954 5955 /** 5956 * ixgbe_clean_tx_ring - Free Tx Buffers 5957 * @tx_ring: ring to be cleaned 5958 **/ 5959 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5960 { 5961 u16 i = tx_ring->next_to_clean; 5962 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5963 5964 if (tx_ring->xsk_umem) { 5965 ixgbe_xsk_clean_tx_ring(tx_ring); 5966 goto out; 5967 } 5968 5969 while (i != tx_ring->next_to_use) { 5970 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5971 5972 /* Free all the Tx ring sk_buffs */ 5973 if (ring_is_xdp(tx_ring)) 5974 xdp_return_frame(tx_buffer->xdpf); 5975 else 5976 dev_kfree_skb_any(tx_buffer->skb); 5977 5978 /* unmap skb header data */ 5979 dma_unmap_single(tx_ring->dev, 5980 dma_unmap_addr(tx_buffer, dma), 5981 dma_unmap_len(tx_buffer, len), 5982 DMA_TO_DEVICE); 5983 5984 /* check for eop_desc to determine the end of the packet */ 5985 eop_desc = tx_buffer->next_to_watch; 5986 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5987 5988 /* unmap remaining buffers */ 5989 while (tx_desc != eop_desc) { 5990 tx_buffer++; 5991 tx_desc++; 5992 i++; 5993 if (unlikely(i == tx_ring->count)) { 5994 i = 0; 5995 tx_buffer = tx_ring->tx_buffer_info; 5996 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5997 } 5998 5999 /* unmap any remaining paged data */ 6000 if (dma_unmap_len(tx_buffer, len)) 6001 dma_unmap_page(tx_ring->dev, 6002 dma_unmap_addr(tx_buffer, dma), 6003 dma_unmap_len(tx_buffer, len), 6004 DMA_TO_DEVICE); 6005 } 6006 6007 /* move us one more past the eop_desc for start of next pkt */ 6008 tx_buffer++; 6009 i++; 6010 if (unlikely(i == tx_ring->count)) { 6011 i = 0; 6012 tx_buffer = tx_ring->tx_buffer_info; 6013 } 6014 } 6015 6016 /* reset BQL for queue */ 6017 if (!ring_is_xdp(tx_ring)) 6018 netdev_tx_reset_queue(txring_txq(tx_ring)); 6019 6020 out: 6021 /* reset next_to_use and next_to_clean */ 6022 tx_ring->next_to_use = 0; 6023 tx_ring->next_to_clean = 0; 6024 } 6025 6026 /** 6027 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6028 * @adapter: board private structure 6029 **/ 6030 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6031 { 6032 int i; 6033 6034 for (i = 0; i < adapter->num_rx_queues; i++) 6035 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6036 } 6037 6038 /** 6039 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6040 * @adapter: board private structure 6041 **/ 6042 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6043 { 6044 int i; 6045 6046 for (i = 0; i < adapter->num_tx_queues; i++) 6047 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6048 for (i = 0; i < adapter->num_xdp_queues; i++) 6049 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6050 } 6051 6052 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6053 { 6054 struct hlist_node *node2; 6055 struct ixgbe_fdir_filter *filter; 6056 6057 spin_lock(&adapter->fdir_perfect_lock); 6058 6059 hlist_for_each_entry_safe(filter, node2, 6060 &adapter->fdir_filter_list, fdir_node) { 6061 hlist_del(&filter->fdir_node); 6062 kfree(filter); 6063 } 6064 adapter->fdir_filter_count = 0; 6065 6066 spin_unlock(&adapter->fdir_perfect_lock); 6067 } 6068 6069 void ixgbe_down(struct ixgbe_adapter *adapter) 6070 { 6071 struct net_device *netdev = adapter->netdev; 6072 struct ixgbe_hw *hw = &adapter->hw; 6073 int i; 6074 6075 /* signal that we are down to the interrupt handler */ 6076 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6077 return; /* do nothing if already down */ 6078 6079 /* Shut off incoming Tx traffic */ 6080 netif_tx_stop_all_queues(netdev); 6081 6082 /* call carrier off first to avoid false dev_watchdog timeouts */ 6083 netif_carrier_off(netdev); 6084 netif_tx_disable(netdev); 6085 6086 /* Disable Rx */ 6087 ixgbe_disable_rx(adapter); 6088 6089 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6090 if (adapter->xdp_ring[0]) 6091 synchronize_rcu(); 6092 6093 ixgbe_irq_disable(adapter); 6094 6095 ixgbe_napi_disable_all(adapter); 6096 6097 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6098 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6099 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6100 6101 del_timer_sync(&adapter->service_timer); 6102 6103 if (adapter->num_vfs) { 6104 /* Clear EITR Select mapping */ 6105 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6106 6107 /* Mark all the VFs as inactive */ 6108 for (i = 0 ; i < adapter->num_vfs; i++) 6109 adapter->vfinfo[i].clear_to_send = false; 6110 6111 /* ping all the active vfs to let them know we are going down */ 6112 ixgbe_ping_all_vfs(adapter); 6113 6114 /* Disable all VFTE/VFRE TX/RX */ 6115 ixgbe_disable_tx_rx(adapter); 6116 } 6117 6118 /* disable transmits in the hardware now that interrupts are off */ 6119 ixgbe_disable_tx(adapter); 6120 6121 if (!pci_channel_offline(adapter->pdev)) 6122 ixgbe_reset(adapter); 6123 6124 /* power down the optics for 82599 SFP+ fiber */ 6125 if (hw->mac.ops.disable_tx_laser) 6126 hw->mac.ops.disable_tx_laser(hw); 6127 6128 ixgbe_clean_all_tx_rings(adapter); 6129 ixgbe_clean_all_rx_rings(adapter); 6130 } 6131 6132 /** 6133 * ixgbe_eee_capable - helper function to determine EEE support on X550 6134 * @adapter: board private structure 6135 */ 6136 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6137 { 6138 struct ixgbe_hw *hw = &adapter->hw; 6139 6140 switch (hw->device_id) { 6141 case IXGBE_DEV_ID_X550EM_A_1G_T: 6142 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6143 if (!hw->phy.eee_speeds_supported) 6144 break; 6145 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6146 if (!hw->phy.eee_speeds_advertised) 6147 break; 6148 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6149 break; 6150 default: 6151 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6152 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6153 break; 6154 } 6155 } 6156 6157 /** 6158 * ixgbe_tx_timeout - Respond to a Tx Hang 6159 * @netdev: network interface device structure 6160 **/ 6161 static void ixgbe_tx_timeout(struct net_device *netdev) 6162 { 6163 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6164 6165 /* Do the reset outside of interrupt context */ 6166 ixgbe_tx_timeout_reset(adapter); 6167 } 6168 6169 #ifdef CONFIG_IXGBE_DCB 6170 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6171 { 6172 struct ixgbe_hw *hw = &adapter->hw; 6173 struct tc_configuration *tc; 6174 int j; 6175 6176 switch (hw->mac.type) { 6177 case ixgbe_mac_82598EB: 6178 case ixgbe_mac_82599EB: 6179 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6180 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6181 break; 6182 case ixgbe_mac_X540: 6183 case ixgbe_mac_X550: 6184 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6185 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6186 break; 6187 case ixgbe_mac_X550EM_x: 6188 case ixgbe_mac_x550em_a: 6189 default: 6190 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6191 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6192 break; 6193 } 6194 6195 /* Configure DCB traffic classes */ 6196 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6197 tc = &adapter->dcb_cfg.tc_config[j]; 6198 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6199 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6200 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6201 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6202 tc->dcb_pfc = pfc_disabled; 6203 } 6204 6205 /* Initialize default user to priority mapping, UPx->TC0 */ 6206 tc = &adapter->dcb_cfg.tc_config[0]; 6207 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6208 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6209 6210 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6211 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6212 adapter->dcb_cfg.pfc_mode_enable = false; 6213 adapter->dcb_set_bitmap = 0x00; 6214 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6215 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6216 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6217 sizeof(adapter->temp_dcb_cfg)); 6218 } 6219 #endif 6220 6221 /** 6222 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6223 * @adapter: board private structure to initialize 6224 * @ii: pointer to ixgbe_info for device 6225 * 6226 * ixgbe_sw_init initializes the Adapter private data structure. 6227 * Fields are initialized based on PCI device information and 6228 * OS network device settings (MTU size). 6229 **/ 6230 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6231 const struct ixgbe_info *ii) 6232 { 6233 struct ixgbe_hw *hw = &adapter->hw; 6234 struct pci_dev *pdev = adapter->pdev; 6235 unsigned int rss, fdir; 6236 u32 fwsm; 6237 int i; 6238 6239 /* PCI config space info */ 6240 6241 hw->vendor_id = pdev->vendor; 6242 hw->device_id = pdev->device; 6243 hw->revision_id = pdev->revision; 6244 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6245 hw->subsystem_device_id = pdev->subsystem_device; 6246 6247 /* get_invariants needs the device IDs */ 6248 ii->get_invariants(hw); 6249 6250 /* Set common capability flags and settings */ 6251 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6252 adapter->ring_feature[RING_F_RSS].limit = rss; 6253 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6254 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6255 adapter->atr_sample_rate = 20; 6256 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6257 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6258 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6259 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6260 #ifdef CONFIG_IXGBE_DCA 6261 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6262 #endif 6263 #ifdef CONFIG_IXGBE_DCB 6264 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6265 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6266 #endif 6267 #ifdef IXGBE_FCOE 6268 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6269 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6270 #ifdef CONFIG_IXGBE_DCB 6271 /* Default traffic class to use for FCoE */ 6272 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6273 #endif /* CONFIG_IXGBE_DCB */ 6274 #endif /* IXGBE_FCOE */ 6275 6276 /* initialize static ixgbe jump table entries */ 6277 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6278 GFP_KERNEL); 6279 if (!adapter->jump_tables[0]) 6280 return -ENOMEM; 6281 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6282 6283 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6284 adapter->jump_tables[i] = NULL; 6285 6286 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6287 sizeof(struct ixgbe_mac_addr), 6288 GFP_KERNEL); 6289 if (!adapter->mac_table) 6290 return -ENOMEM; 6291 6292 if (ixgbe_init_rss_key(adapter)) 6293 return -ENOMEM; 6294 6295 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL); 6296 if (!adapter->af_xdp_zc_qps) 6297 return -ENOMEM; 6298 6299 /* Set MAC specific capability flags and exceptions */ 6300 switch (hw->mac.type) { 6301 case ixgbe_mac_82598EB: 6302 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6303 6304 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6305 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6306 6307 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6308 adapter->ring_feature[RING_F_FDIR].limit = 0; 6309 adapter->atr_sample_rate = 0; 6310 adapter->fdir_pballoc = 0; 6311 #ifdef IXGBE_FCOE 6312 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6313 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6314 #ifdef CONFIG_IXGBE_DCB 6315 adapter->fcoe.up = 0; 6316 #endif /* IXGBE_DCB */ 6317 #endif /* IXGBE_FCOE */ 6318 break; 6319 case ixgbe_mac_82599EB: 6320 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6321 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6322 break; 6323 case ixgbe_mac_X540: 6324 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6325 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6326 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6327 break; 6328 case ixgbe_mac_x550em_a: 6329 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6330 switch (hw->device_id) { 6331 case IXGBE_DEV_ID_X550EM_A_1G_T: 6332 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6333 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6334 break; 6335 default: 6336 break; 6337 } 6338 /* fall through */ 6339 case ixgbe_mac_X550EM_x: 6340 #ifdef CONFIG_IXGBE_DCB 6341 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6342 #endif 6343 #ifdef IXGBE_FCOE 6344 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6345 #ifdef CONFIG_IXGBE_DCB 6346 adapter->fcoe.up = 0; 6347 #endif /* IXGBE_DCB */ 6348 #endif /* IXGBE_FCOE */ 6349 /* Fall Through */ 6350 case ixgbe_mac_X550: 6351 if (hw->mac.type == ixgbe_mac_X550) 6352 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6353 #ifdef CONFIG_IXGBE_DCA 6354 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6355 #endif 6356 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6357 break; 6358 default: 6359 break; 6360 } 6361 6362 #ifdef IXGBE_FCOE 6363 /* FCoE support exists, always init the FCoE lock */ 6364 spin_lock_init(&adapter->fcoe.lock); 6365 6366 #endif 6367 /* n-tuple support exists, always init our spinlock */ 6368 spin_lock_init(&adapter->fdir_perfect_lock); 6369 6370 #ifdef CONFIG_IXGBE_DCB 6371 ixgbe_init_dcb(adapter); 6372 #endif 6373 ixgbe_init_ipsec_offload(adapter); 6374 6375 /* default flow control settings */ 6376 hw->fc.requested_mode = ixgbe_fc_full; 6377 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6378 ixgbe_pbthresh_setup(adapter); 6379 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6380 hw->fc.send_xon = true; 6381 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6382 6383 #ifdef CONFIG_PCI_IOV 6384 if (max_vfs > 0) 6385 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6386 6387 /* assign number of SR-IOV VFs */ 6388 if (hw->mac.type != ixgbe_mac_82598EB) { 6389 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6390 max_vfs = 0; 6391 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6392 } 6393 } 6394 #endif /* CONFIG_PCI_IOV */ 6395 6396 /* enable itr by default in dynamic mode */ 6397 adapter->rx_itr_setting = 1; 6398 adapter->tx_itr_setting = 1; 6399 6400 /* set default ring sizes */ 6401 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6402 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6403 6404 /* set default work limits */ 6405 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6406 6407 /* initialize eeprom parameters */ 6408 if (ixgbe_init_eeprom_params_generic(hw)) { 6409 e_dev_err("EEPROM initialization failed\n"); 6410 return -EIO; 6411 } 6412 6413 /* PF holds first pool slot */ 6414 set_bit(0, adapter->fwd_bitmask); 6415 set_bit(__IXGBE_DOWN, &adapter->state); 6416 6417 return 0; 6418 } 6419 6420 /** 6421 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6422 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6423 * 6424 * Return 0 on success, negative on failure 6425 **/ 6426 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6427 { 6428 struct device *dev = tx_ring->dev; 6429 int orig_node = dev_to_node(dev); 6430 int ring_node = NUMA_NO_NODE; 6431 int size; 6432 6433 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6434 6435 if (tx_ring->q_vector) 6436 ring_node = tx_ring->q_vector->numa_node; 6437 6438 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6439 if (!tx_ring->tx_buffer_info) 6440 tx_ring->tx_buffer_info = vmalloc(size); 6441 if (!tx_ring->tx_buffer_info) 6442 goto err; 6443 6444 /* round up to nearest 4K */ 6445 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6446 tx_ring->size = ALIGN(tx_ring->size, 4096); 6447 6448 set_dev_node(dev, ring_node); 6449 tx_ring->desc = dma_alloc_coherent(dev, 6450 tx_ring->size, 6451 &tx_ring->dma, 6452 GFP_KERNEL); 6453 set_dev_node(dev, orig_node); 6454 if (!tx_ring->desc) 6455 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6456 &tx_ring->dma, GFP_KERNEL); 6457 if (!tx_ring->desc) 6458 goto err; 6459 6460 tx_ring->next_to_use = 0; 6461 tx_ring->next_to_clean = 0; 6462 return 0; 6463 6464 err: 6465 vfree(tx_ring->tx_buffer_info); 6466 tx_ring->tx_buffer_info = NULL; 6467 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6468 return -ENOMEM; 6469 } 6470 6471 /** 6472 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6473 * @adapter: board private structure 6474 * 6475 * If this function returns with an error, then it's possible one or 6476 * more of the rings is populated (while the rest are not). It is the 6477 * callers duty to clean those orphaned rings. 6478 * 6479 * Return 0 on success, negative on failure 6480 **/ 6481 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6482 { 6483 int i, j = 0, err = 0; 6484 6485 for (i = 0; i < adapter->num_tx_queues; i++) { 6486 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6487 if (!err) 6488 continue; 6489 6490 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6491 goto err_setup_tx; 6492 } 6493 for (j = 0; j < adapter->num_xdp_queues; j++) { 6494 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6495 if (!err) 6496 continue; 6497 6498 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6499 goto err_setup_tx; 6500 } 6501 6502 return 0; 6503 err_setup_tx: 6504 /* rewind the index freeing the rings as we go */ 6505 while (j--) 6506 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6507 while (i--) 6508 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6509 return err; 6510 } 6511 6512 /** 6513 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6514 * @adapter: pointer to ixgbe_adapter 6515 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6516 * 6517 * Returns 0 on success, negative on failure 6518 **/ 6519 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6520 struct ixgbe_ring *rx_ring) 6521 { 6522 struct device *dev = rx_ring->dev; 6523 int orig_node = dev_to_node(dev); 6524 int ring_node = NUMA_NO_NODE; 6525 int size; 6526 6527 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6528 6529 if (rx_ring->q_vector) 6530 ring_node = rx_ring->q_vector->numa_node; 6531 6532 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6533 if (!rx_ring->rx_buffer_info) 6534 rx_ring->rx_buffer_info = vmalloc(size); 6535 if (!rx_ring->rx_buffer_info) 6536 goto err; 6537 6538 /* Round up to nearest 4K */ 6539 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6540 rx_ring->size = ALIGN(rx_ring->size, 4096); 6541 6542 set_dev_node(dev, ring_node); 6543 rx_ring->desc = dma_alloc_coherent(dev, 6544 rx_ring->size, 6545 &rx_ring->dma, 6546 GFP_KERNEL); 6547 set_dev_node(dev, orig_node); 6548 if (!rx_ring->desc) 6549 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6550 &rx_ring->dma, GFP_KERNEL); 6551 if (!rx_ring->desc) 6552 goto err; 6553 6554 rx_ring->next_to_clean = 0; 6555 rx_ring->next_to_use = 0; 6556 6557 /* XDP RX-queue info */ 6558 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6559 rx_ring->queue_index) < 0) 6560 goto err; 6561 6562 rx_ring->xdp_prog = adapter->xdp_prog; 6563 6564 return 0; 6565 err: 6566 vfree(rx_ring->rx_buffer_info); 6567 rx_ring->rx_buffer_info = NULL; 6568 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6569 return -ENOMEM; 6570 } 6571 6572 /** 6573 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6574 * @adapter: board private structure 6575 * 6576 * If this function returns with an error, then it's possible one or 6577 * more of the rings is populated (while the rest are not). It is the 6578 * callers duty to clean those orphaned rings. 6579 * 6580 * Return 0 on success, negative on failure 6581 **/ 6582 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6583 { 6584 int i, err = 0; 6585 6586 for (i = 0; i < adapter->num_rx_queues; i++) { 6587 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6588 if (!err) 6589 continue; 6590 6591 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6592 goto err_setup_rx; 6593 } 6594 6595 #ifdef IXGBE_FCOE 6596 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6597 if (!err) 6598 #endif 6599 return 0; 6600 err_setup_rx: 6601 /* rewind the index freeing the rings as we go */ 6602 while (i--) 6603 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6604 return err; 6605 } 6606 6607 /** 6608 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6609 * @tx_ring: Tx descriptor ring for a specific queue 6610 * 6611 * Free all transmit software resources 6612 **/ 6613 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6614 { 6615 ixgbe_clean_tx_ring(tx_ring); 6616 6617 vfree(tx_ring->tx_buffer_info); 6618 tx_ring->tx_buffer_info = NULL; 6619 6620 /* if not set, then don't free */ 6621 if (!tx_ring->desc) 6622 return; 6623 6624 dma_free_coherent(tx_ring->dev, tx_ring->size, 6625 tx_ring->desc, tx_ring->dma); 6626 6627 tx_ring->desc = NULL; 6628 } 6629 6630 /** 6631 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6632 * @adapter: board private structure 6633 * 6634 * Free all transmit software resources 6635 **/ 6636 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6637 { 6638 int i; 6639 6640 for (i = 0; i < adapter->num_tx_queues; i++) 6641 if (adapter->tx_ring[i]->desc) 6642 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6643 for (i = 0; i < adapter->num_xdp_queues; i++) 6644 if (adapter->xdp_ring[i]->desc) 6645 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6646 } 6647 6648 /** 6649 * ixgbe_free_rx_resources - Free Rx Resources 6650 * @rx_ring: ring to clean the resources from 6651 * 6652 * Free all receive software resources 6653 **/ 6654 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6655 { 6656 ixgbe_clean_rx_ring(rx_ring); 6657 6658 rx_ring->xdp_prog = NULL; 6659 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6660 vfree(rx_ring->rx_buffer_info); 6661 rx_ring->rx_buffer_info = NULL; 6662 6663 /* if not set, then don't free */ 6664 if (!rx_ring->desc) 6665 return; 6666 6667 dma_free_coherent(rx_ring->dev, rx_ring->size, 6668 rx_ring->desc, rx_ring->dma); 6669 6670 rx_ring->desc = NULL; 6671 } 6672 6673 /** 6674 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6675 * @adapter: board private structure 6676 * 6677 * Free all receive software resources 6678 **/ 6679 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6680 { 6681 int i; 6682 6683 #ifdef IXGBE_FCOE 6684 ixgbe_free_fcoe_ddp_resources(adapter); 6685 6686 #endif 6687 for (i = 0; i < adapter->num_rx_queues; i++) 6688 if (adapter->rx_ring[i]->desc) 6689 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6690 } 6691 6692 /** 6693 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6694 * @netdev: network interface device structure 6695 * @new_mtu: new value for maximum frame size 6696 * 6697 * Returns 0 on success, negative on failure 6698 **/ 6699 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6700 { 6701 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6702 6703 if (adapter->xdp_prog) { 6704 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 6705 VLAN_HLEN; 6706 int i; 6707 6708 for (i = 0; i < adapter->num_rx_queues; i++) { 6709 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6710 6711 if (new_frame_size > ixgbe_rx_bufsz(ring)) { 6712 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6713 return -EINVAL; 6714 } 6715 } 6716 } 6717 6718 /* 6719 * For 82599EB we cannot allow legacy VFs to enable their receive 6720 * paths when MTU greater than 1500 is configured. So display a 6721 * warning that legacy VFs will be disabled. 6722 */ 6723 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6724 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6725 (new_mtu > ETH_DATA_LEN)) 6726 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6727 6728 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6729 netdev->mtu, new_mtu); 6730 6731 /* must set new MTU before calling down or up */ 6732 netdev->mtu = new_mtu; 6733 6734 if (netif_running(netdev)) 6735 ixgbe_reinit_locked(adapter); 6736 6737 return 0; 6738 } 6739 6740 /** 6741 * ixgbe_open - Called when a network interface is made active 6742 * @netdev: network interface device structure 6743 * 6744 * Returns 0 on success, negative value on failure 6745 * 6746 * The open entry point is called when a network interface is made 6747 * active by the system (IFF_UP). At this point all resources needed 6748 * for transmit and receive operations are allocated, the interrupt 6749 * handler is registered with the OS, the watchdog timer is started, 6750 * and the stack is notified that the interface is ready. 6751 **/ 6752 int ixgbe_open(struct net_device *netdev) 6753 { 6754 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6755 struct ixgbe_hw *hw = &adapter->hw; 6756 int err, queues; 6757 6758 /* disallow open during test */ 6759 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6760 return -EBUSY; 6761 6762 netif_carrier_off(netdev); 6763 6764 /* allocate transmit descriptors */ 6765 err = ixgbe_setup_all_tx_resources(adapter); 6766 if (err) 6767 goto err_setup_tx; 6768 6769 /* allocate receive descriptors */ 6770 err = ixgbe_setup_all_rx_resources(adapter); 6771 if (err) 6772 goto err_setup_rx; 6773 6774 ixgbe_configure(adapter); 6775 6776 err = ixgbe_request_irq(adapter); 6777 if (err) 6778 goto err_req_irq; 6779 6780 /* Notify the stack of the actual queue counts. */ 6781 queues = adapter->num_tx_queues; 6782 err = netif_set_real_num_tx_queues(netdev, queues); 6783 if (err) 6784 goto err_set_queues; 6785 6786 queues = adapter->num_rx_queues; 6787 err = netif_set_real_num_rx_queues(netdev, queues); 6788 if (err) 6789 goto err_set_queues; 6790 6791 ixgbe_ptp_init(adapter); 6792 6793 ixgbe_up_complete(adapter); 6794 6795 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6796 udp_tunnel_get_rx_info(netdev); 6797 6798 return 0; 6799 6800 err_set_queues: 6801 ixgbe_free_irq(adapter); 6802 err_req_irq: 6803 ixgbe_free_all_rx_resources(adapter); 6804 if (hw->phy.ops.set_phy_power && !adapter->wol) 6805 hw->phy.ops.set_phy_power(&adapter->hw, false); 6806 err_setup_rx: 6807 ixgbe_free_all_tx_resources(adapter); 6808 err_setup_tx: 6809 ixgbe_reset(adapter); 6810 6811 return err; 6812 } 6813 6814 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6815 { 6816 ixgbe_ptp_suspend(adapter); 6817 6818 if (adapter->hw.phy.ops.enter_lplu) { 6819 adapter->hw.phy.reset_disable = true; 6820 ixgbe_down(adapter); 6821 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6822 adapter->hw.phy.reset_disable = false; 6823 } else { 6824 ixgbe_down(adapter); 6825 } 6826 6827 ixgbe_free_irq(adapter); 6828 6829 ixgbe_free_all_tx_resources(adapter); 6830 ixgbe_free_all_rx_resources(adapter); 6831 } 6832 6833 /** 6834 * ixgbe_close - Disables a network interface 6835 * @netdev: network interface device structure 6836 * 6837 * Returns 0, this is not allowed to fail 6838 * 6839 * The close entry point is called when an interface is de-activated 6840 * by the OS. The hardware is still under the drivers control, but 6841 * needs to be disabled. A global MAC reset is issued to stop the 6842 * hardware, and all transmit and receive resources are freed. 6843 **/ 6844 int ixgbe_close(struct net_device *netdev) 6845 { 6846 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6847 6848 ixgbe_ptp_stop(adapter); 6849 6850 if (netif_device_present(netdev)) 6851 ixgbe_close_suspend(adapter); 6852 6853 ixgbe_fdir_filter_exit(adapter); 6854 6855 ixgbe_release_hw_control(adapter); 6856 6857 return 0; 6858 } 6859 6860 #ifdef CONFIG_PM 6861 static int ixgbe_resume(struct pci_dev *pdev) 6862 { 6863 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6864 struct net_device *netdev = adapter->netdev; 6865 u32 err; 6866 6867 adapter->hw.hw_addr = adapter->io_addr; 6868 pci_set_power_state(pdev, PCI_D0); 6869 pci_restore_state(pdev); 6870 /* 6871 * pci_restore_state clears dev->state_saved so call 6872 * pci_save_state to restore it. 6873 */ 6874 pci_save_state(pdev); 6875 6876 err = pci_enable_device_mem(pdev); 6877 if (err) { 6878 e_dev_err("Cannot enable PCI device from suspend\n"); 6879 return err; 6880 } 6881 smp_mb__before_atomic(); 6882 clear_bit(__IXGBE_DISABLED, &adapter->state); 6883 pci_set_master(pdev); 6884 6885 pci_wake_from_d3(pdev, false); 6886 6887 ixgbe_reset(adapter); 6888 6889 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6890 6891 rtnl_lock(); 6892 err = ixgbe_init_interrupt_scheme(adapter); 6893 if (!err && netif_running(netdev)) 6894 err = ixgbe_open(netdev); 6895 6896 6897 if (!err) 6898 netif_device_attach(netdev); 6899 rtnl_unlock(); 6900 6901 return err; 6902 } 6903 #endif /* CONFIG_PM */ 6904 6905 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6906 { 6907 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6908 struct net_device *netdev = adapter->netdev; 6909 struct ixgbe_hw *hw = &adapter->hw; 6910 u32 ctrl; 6911 u32 wufc = adapter->wol; 6912 #ifdef CONFIG_PM 6913 int retval = 0; 6914 #endif 6915 6916 rtnl_lock(); 6917 netif_device_detach(netdev); 6918 6919 if (netif_running(netdev)) 6920 ixgbe_close_suspend(adapter); 6921 6922 ixgbe_clear_interrupt_scheme(adapter); 6923 rtnl_unlock(); 6924 6925 #ifdef CONFIG_PM 6926 retval = pci_save_state(pdev); 6927 if (retval) 6928 return retval; 6929 6930 #endif 6931 if (hw->mac.ops.stop_link_on_d3) 6932 hw->mac.ops.stop_link_on_d3(hw); 6933 6934 if (wufc) { 6935 u32 fctrl; 6936 6937 ixgbe_set_rx_mode(netdev); 6938 6939 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6940 if (hw->mac.ops.enable_tx_laser) 6941 hw->mac.ops.enable_tx_laser(hw); 6942 6943 /* enable the reception of multicast packets */ 6944 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6945 fctrl |= IXGBE_FCTRL_MPE; 6946 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6947 6948 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6949 ctrl |= IXGBE_CTRL_GIO_DIS; 6950 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6951 6952 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6953 } else { 6954 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6955 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6956 } 6957 6958 switch (hw->mac.type) { 6959 case ixgbe_mac_82598EB: 6960 pci_wake_from_d3(pdev, false); 6961 break; 6962 case ixgbe_mac_82599EB: 6963 case ixgbe_mac_X540: 6964 case ixgbe_mac_X550: 6965 case ixgbe_mac_X550EM_x: 6966 case ixgbe_mac_x550em_a: 6967 pci_wake_from_d3(pdev, !!wufc); 6968 break; 6969 default: 6970 break; 6971 } 6972 6973 *enable_wake = !!wufc; 6974 if (hw->phy.ops.set_phy_power && !*enable_wake) 6975 hw->phy.ops.set_phy_power(hw, false); 6976 6977 ixgbe_release_hw_control(adapter); 6978 6979 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6980 pci_disable_device(pdev); 6981 6982 return 0; 6983 } 6984 6985 #ifdef CONFIG_PM 6986 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6987 { 6988 int retval; 6989 bool wake; 6990 6991 retval = __ixgbe_shutdown(pdev, &wake); 6992 if (retval) 6993 return retval; 6994 6995 if (wake) { 6996 pci_prepare_to_sleep(pdev); 6997 } else { 6998 pci_wake_from_d3(pdev, false); 6999 pci_set_power_state(pdev, PCI_D3hot); 7000 } 7001 7002 return 0; 7003 } 7004 #endif /* CONFIG_PM */ 7005 7006 static void ixgbe_shutdown(struct pci_dev *pdev) 7007 { 7008 bool wake; 7009 7010 __ixgbe_shutdown(pdev, &wake); 7011 7012 if (system_state == SYSTEM_POWER_OFF) { 7013 pci_wake_from_d3(pdev, wake); 7014 pci_set_power_state(pdev, PCI_D3hot); 7015 } 7016 } 7017 7018 /** 7019 * ixgbe_update_stats - Update the board statistics counters. 7020 * @adapter: board private structure 7021 **/ 7022 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7023 { 7024 struct net_device *netdev = adapter->netdev; 7025 struct ixgbe_hw *hw = &adapter->hw; 7026 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7027 u64 total_mpc = 0; 7028 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7029 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7030 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7031 u64 alloc_rx_page = 0; 7032 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7033 7034 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7035 test_bit(__IXGBE_RESETTING, &adapter->state)) 7036 return; 7037 7038 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7039 u64 rsc_count = 0; 7040 u64 rsc_flush = 0; 7041 for (i = 0; i < adapter->num_rx_queues; i++) { 7042 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7043 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7044 } 7045 adapter->rsc_total_count = rsc_count; 7046 adapter->rsc_total_flush = rsc_flush; 7047 } 7048 7049 for (i = 0; i < adapter->num_rx_queues; i++) { 7050 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 7051 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7052 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7053 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7054 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7055 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7056 bytes += rx_ring->stats.bytes; 7057 packets += rx_ring->stats.packets; 7058 } 7059 adapter->non_eop_descs = non_eop_descs; 7060 adapter->alloc_rx_page = alloc_rx_page; 7061 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7062 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7063 adapter->hw_csum_rx_error = hw_csum_rx_error; 7064 netdev->stats.rx_bytes = bytes; 7065 netdev->stats.rx_packets = packets; 7066 7067 bytes = 0; 7068 packets = 0; 7069 /* gather some stats to the adapter struct that are per queue */ 7070 for (i = 0; i < adapter->num_tx_queues; i++) { 7071 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7072 restart_queue += tx_ring->tx_stats.restart_queue; 7073 tx_busy += tx_ring->tx_stats.tx_busy; 7074 bytes += tx_ring->stats.bytes; 7075 packets += tx_ring->stats.packets; 7076 } 7077 for (i = 0; i < adapter->num_xdp_queues; i++) { 7078 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 7079 7080 restart_queue += xdp_ring->tx_stats.restart_queue; 7081 tx_busy += xdp_ring->tx_stats.tx_busy; 7082 bytes += xdp_ring->stats.bytes; 7083 packets += xdp_ring->stats.packets; 7084 } 7085 adapter->restart_queue = restart_queue; 7086 adapter->tx_busy = tx_busy; 7087 netdev->stats.tx_bytes = bytes; 7088 netdev->stats.tx_packets = packets; 7089 7090 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7091 7092 /* 8 register reads */ 7093 for (i = 0; i < 8; i++) { 7094 /* for packet buffers not used, the register should read 0 */ 7095 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7096 missed_rx += mpc; 7097 hwstats->mpc[i] += mpc; 7098 total_mpc += hwstats->mpc[i]; 7099 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7100 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7101 switch (hw->mac.type) { 7102 case ixgbe_mac_82598EB: 7103 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7104 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7105 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7106 hwstats->pxonrxc[i] += 7107 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7108 break; 7109 case ixgbe_mac_82599EB: 7110 case ixgbe_mac_X540: 7111 case ixgbe_mac_X550: 7112 case ixgbe_mac_X550EM_x: 7113 case ixgbe_mac_x550em_a: 7114 hwstats->pxonrxc[i] += 7115 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7116 break; 7117 default: 7118 break; 7119 } 7120 } 7121 7122 /*16 register reads */ 7123 for (i = 0; i < 16; i++) { 7124 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7125 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7126 if ((hw->mac.type == ixgbe_mac_82599EB) || 7127 (hw->mac.type == ixgbe_mac_X540) || 7128 (hw->mac.type == ixgbe_mac_X550) || 7129 (hw->mac.type == ixgbe_mac_X550EM_x) || 7130 (hw->mac.type == ixgbe_mac_x550em_a)) { 7131 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7132 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7133 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7134 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7135 } 7136 } 7137 7138 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7139 /* work around hardware counting issue */ 7140 hwstats->gprc -= missed_rx; 7141 7142 ixgbe_update_xoff_received(adapter); 7143 7144 /* 82598 hardware only has a 32 bit counter in the high register */ 7145 switch (hw->mac.type) { 7146 case ixgbe_mac_82598EB: 7147 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7148 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7149 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7150 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7151 break; 7152 case ixgbe_mac_X540: 7153 case ixgbe_mac_X550: 7154 case ixgbe_mac_X550EM_x: 7155 case ixgbe_mac_x550em_a: 7156 /* OS2BMC stats are X540 and later */ 7157 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7158 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7159 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7160 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7161 /* fall through */ 7162 case ixgbe_mac_82599EB: 7163 for (i = 0; i < 16; i++) 7164 adapter->hw_rx_no_dma_resources += 7165 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7166 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7167 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7168 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7169 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7170 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7171 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7172 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7173 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7174 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7175 #ifdef IXGBE_FCOE 7176 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7177 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7178 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7179 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7180 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7181 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7182 /* Add up per cpu counters for total ddp aloc fail */ 7183 if (adapter->fcoe.ddp_pool) { 7184 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7185 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7186 unsigned int cpu; 7187 u64 noddp = 0, noddp_ext_buff = 0; 7188 for_each_possible_cpu(cpu) { 7189 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7190 noddp += ddp_pool->noddp; 7191 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7192 } 7193 hwstats->fcoe_noddp = noddp; 7194 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7195 } 7196 #endif /* IXGBE_FCOE */ 7197 break; 7198 default: 7199 break; 7200 } 7201 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7202 hwstats->bprc += bprc; 7203 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7204 if (hw->mac.type == ixgbe_mac_82598EB) 7205 hwstats->mprc -= bprc; 7206 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7207 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7208 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7209 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7210 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7211 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7212 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7213 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7214 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7215 hwstats->lxontxc += lxon; 7216 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7217 hwstats->lxofftxc += lxoff; 7218 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7219 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7220 /* 7221 * 82598 errata - tx of flow control packets is included in tx counters 7222 */ 7223 xon_off_tot = lxon + lxoff; 7224 hwstats->gptc -= xon_off_tot; 7225 hwstats->mptc -= xon_off_tot; 7226 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7227 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7228 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7229 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7230 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7231 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7232 hwstats->ptc64 -= xon_off_tot; 7233 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7234 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7235 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7236 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7237 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7238 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7239 7240 /* Fill out the OS statistics structure */ 7241 netdev->stats.multicast = hwstats->mprc; 7242 7243 /* Rx Errors */ 7244 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7245 netdev->stats.rx_dropped = 0; 7246 netdev->stats.rx_length_errors = hwstats->rlec; 7247 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7248 netdev->stats.rx_missed_errors = total_mpc; 7249 } 7250 7251 /** 7252 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7253 * @adapter: pointer to the device adapter structure 7254 **/ 7255 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7256 { 7257 struct ixgbe_hw *hw = &adapter->hw; 7258 int i; 7259 7260 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7261 return; 7262 7263 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7264 7265 /* if interface is down do nothing */ 7266 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7267 return; 7268 7269 /* do nothing if we are not using signature filters */ 7270 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7271 return; 7272 7273 adapter->fdir_overflow++; 7274 7275 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7276 for (i = 0; i < adapter->num_tx_queues; i++) 7277 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7278 &(adapter->tx_ring[i]->state)); 7279 for (i = 0; i < adapter->num_xdp_queues; i++) 7280 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7281 &adapter->xdp_ring[i]->state); 7282 /* re-enable flow director interrupts */ 7283 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7284 } else { 7285 e_err(probe, "failed to finish FDIR re-initialization, " 7286 "ignored adding FDIR ATR filters\n"); 7287 } 7288 } 7289 7290 /** 7291 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7292 * @adapter: pointer to the device adapter structure 7293 * 7294 * This function serves two purposes. First it strobes the interrupt lines 7295 * in order to make certain interrupts are occurring. Secondly it sets the 7296 * bits needed to check for TX hangs. As a result we should immediately 7297 * determine if a hang has occurred. 7298 */ 7299 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7300 { 7301 struct ixgbe_hw *hw = &adapter->hw; 7302 u64 eics = 0; 7303 int i; 7304 7305 /* If we're down, removing or resetting, just bail */ 7306 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7307 test_bit(__IXGBE_REMOVING, &adapter->state) || 7308 test_bit(__IXGBE_RESETTING, &adapter->state)) 7309 return; 7310 7311 /* Force detection of hung controller */ 7312 if (netif_carrier_ok(adapter->netdev)) { 7313 for (i = 0; i < adapter->num_tx_queues; i++) 7314 set_check_for_tx_hang(adapter->tx_ring[i]); 7315 for (i = 0; i < adapter->num_xdp_queues; i++) 7316 set_check_for_tx_hang(adapter->xdp_ring[i]); 7317 } 7318 7319 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7320 /* 7321 * for legacy and MSI interrupts don't set any bits 7322 * that are enabled for EIAM, because this operation 7323 * would set *both* EIMS and EICS for any bit in EIAM 7324 */ 7325 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7326 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7327 } else { 7328 /* get one bit for every active tx/rx interrupt vector */ 7329 for (i = 0; i < adapter->num_q_vectors; i++) { 7330 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7331 if (qv->rx.ring || qv->tx.ring) 7332 eics |= BIT_ULL(i); 7333 } 7334 } 7335 7336 /* Cause software interrupt to ensure rings are cleaned */ 7337 ixgbe_irq_rearm_queues(adapter, eics); 7338 } 7339 7340 /** 7341 * ixgbe_watchdog_update_link - update the link status 7342 * @adapter: pointer to the device adapter structure 7343 **/ 7344 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7345 { 7346 struct ixgbe_hw *hw = &adapter->hw; 7347 u32 link_speed = adapter->link_speed; 7348 bool link_up = adapter->link_up; 7349 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7350 7351 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7352 return; 7353 7354 if (hw->mac.ops.check_link) { 7355 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7356 } else { 7357 /* always assume link is up, if no check link function */ 7358 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7359 link_up = true; 7360 } 7361 7362 if (adapter->ixgbe_ieee_pfc) 7363 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7364 7365 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7366 hw->mac.ops.fc_enable(hw); 7367 ixgbe_set_rx_drop_en(adapter); 7368 } 7369 7370 if (link_up || 7371 time_after(jiffies, (adapter->link_check_timeout + 7372 IXGBE_TRY_LINK_TIMEOUT))) { 7373 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7374 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7375 IXGBE_WRITE_FLUSH(hw); 7376 } 7377 7378 adapter->link_up = link_up; 7379 adapter->link_speed = link_speed; 7380 } 7381 7382 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7383 { 7384 #ifdef CONFIG_IXGBE_DCB 7385 struct net_device *netdev = adapter->netdev; 7386 struct dcb_app app = { 7387 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7388 .protocol = 0, 7389 }; 7390 u8 up = 0; 7391 7392 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7393 up = dcb_ieee_getapp_mask(netdev, &app); 7394 7395 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7396 #endif 7397 } 7398 7399 /** 7400 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7401 * print link up message 7402 * @adapter: pointer to the device adapter structure 7403 **/ 7404 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7405 { 7406 struct net_device *netdev = adapter->netdev; 7407 struct ixgbe_hw *hw = &adapter->hw; 7408 u32 link_speed = adapter->link_speed; 7409 const char *speed_str; 7410 bool flow_rx, flow_tx; 7411 7412 /* only continue if link was previously down */ 7413 if (netif_carrier_ok(netdev)) 7414 return; 7415 7416 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7417 7418 switch (hw->mac.type) { 7419 case ixgbe_mac_82598EB: { 7420 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7421 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7422 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7423 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7424 } 7425 break; 7426 case ixgbe_mac_X540: 7427 case ixgbe_mac_X550: 7428 case ixgbe_mac_X550EM_x: 7429 case ixgbe_mac_x550em_a: 7430 case ixgbe_mac_82599EB: { 7431 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7432 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7433 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7434 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7435 } 7436 break; 7437 default: 7438 flow_tx = false; 7439 flow_rx = false; 7440 break; 7441 } 7442 7443 adapter->last_rx_ptp_check = jiffies; 7444 7445 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7446 ixgbe_ptp_start_cyclecounter(adapter); 7447 7448 switch (link_speed) { 7449 case IXGBE_LINK_SPEED_10GB_FULL: 7450 speed_str = "10 Gbps"; 7451 break; 7452 case IXGBE_LINK_SPEED_5GB_FULL: 7453 speed_str = "5 Gbps"; 7454 break; 7455 case IXGBE_LINK_SPEED_2_5GB_FULL: 7456 speed_str = "2.5 Gbps"; 7457 break; 7458 case IXGBE_LINK_SPEED_1GB_FULL: 7459 speed_str = "1 Gbps"; 7460 break; 7461 case IXGBE_LINK_SPEED_100_FULL: 7462 speed_str = "100 Mbps"; 7463 break; 7464 case IXGBE_LINK_SPEED_10_FULL: 7465 speed_str = "10 Mbps"; 7466 break; 7467 default: 7468 speed_str = "unknown speed"; 7469 break; 7470 } 7471 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7472 ((flow_rx && flow_tx) ? "RX/TX" : 7473 (flow_rx ? "RX" : 7474 (flow_tx ? "TX" : "None")))); 7475 7476 netif_carrier_on(netdev); 7477 ixgbe_check_vf_rate_limit(adapter); 7478 7479 /* enable transmits */ 7480 netif_tx_wake_all_queues(adapter->netdev); 7481 7482 /* update the default user priority for VFs */ 7483 ixgbe_update_default_up(adapter); 7484 7485 /* ping all the active vfs to let them know link has changed */ 7486 ixgbe_ping_all_vfs(adapter); 7487 } 7488 7489 /** 7490 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7491 * print link down message 7492 * @adapter: pointer to the adapter structure 7493 **/ 7494 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7495 { 7496 struct net_device *netdev = adapter->netdev; 7497 struct ixgbe_hw *hw = &adapter->hw; 7498 7499 adapter->link_up = false; 7500 adapter->link_speed = 0; 7501 7502 /* only continue if link was up previously */ 7503 if (!netif_carrier_ok(netdev)) 7504 return; 7505 7506 /* poll for SFP+ cable when link is down */ 7507 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7508 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7509 7510 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7511 ixgbe_ptp_start_cyclecounter(adapter); 7512 7513 e_info(drv, "NIC Link is Down\n"); 7514 netif_carrier_off(netdev); 7515 7516 /* ping all the active vfs to let them know link has changed */ 7517 ixgbe_ping_all_vfs(adapter); 7518 } 7519 7520 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7521 { 7522 int i; 7523 7524 for (i = 0; i < adapter->num_tx_queues; i++) { 7525 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7526 7527 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7528 return true; 7529 } 7530 7531 for (i = 0; i < adapter->num_xdp_queues; i++) { 7532 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7533 7534 if (ring->next_to_use != ring->next_to_clean) 7535 return true; 7536 } 7537 7538 return false; 7539 } 7540 7541 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7542 { 7543 struct ixgbe_hw *hw = &adapter->hw; 7544 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7545 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7546 7547 int i, j; 7548 7549 if (!adapter->num_vfs) 7550 return false; 7551 7552 /* resetting the PF is only needed for MAC before X550 */ 7553 if (hw->mac.type >= ixgbe_mac_X550) 7554 return false; 7555 7556 for (i = 0; i < adapter->num_vfs; i++) { 7557 for (j = 0; j < q_per_pool; j++) { 7558 u32 h, t; 7559 7560 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7561 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7562 7563 if (h != t) 7564 return true; 7565 } 7566 } 7567 7568 return false; 7569 } 7570 7571 /** 7572 * ixgbe_watchdog_flush_tx - flush queues on link down 7573 * @adapter: pointer to the device adapter structure 7574 **/ 7575 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7576 { 7577 if (!netif_carrier_ok(adapter->netdev)) { 7578 if (ixgbe_ring_tx_pending(adapter) || 7579 ixgbe_vf_tx_pending(adapter)) { 7580 /* We've lost link, so the controller stops DMA, 7581 * but we've got queued Tx work that's never going 7582 * to get done, so reset controller to flush Tx. 7583 * (Do the reset outside of interrupt context). 7584 */ 7585 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7586 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7587 } 7588 } 7589 } 7590 7591 #ifdef CONFIG_PCI_IOV 7592 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7593 { 7594 struct ixgbe_hw *hw = &adapter->hw; 7595 struct pci_dev *pdev = adapter->pdev; 7596 unsigned int vf; 7597 u32 gpc; 7598 7599 if (!(netif_carrier_ok(adapter->netdev))) 7600 return; 7601 7602 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7603 if (gpc) /* If incrementing then no need for the check below */ 7604 return; 7605 /* Check to see if a bad DMA write target from an errant or 7606 * malicious VF has caused a PCIe error. If so then we can 7607 * issue a VFLR to the offending VF(s) and then resume without 7608 * requesting a full slot reset. 7609 */ 7610 7611 if (!pdev) 7612 return; 7613 7614 /* check status reg for all VFs owned by this PF */ 7615 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7616 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7617 u16 status_reg; 7618 7619 if (!vfdev) 7620 continue; 7621 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7622 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7623 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7624 pcie_flr(vfdev); 7625 } 7626 } 7627 7628 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7629 { 7630 u32 ssvpc; 7631 7632 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7633 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7634 adapter->num_vfs == 0) 7635 return; 7636 7637 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7638 7639 /* 7640 * ssvpc register is cleared on read, if zero then no 7641 * spoofed packets in the last interval. 7642 */ 7643 if (!ssvpc) 7644 return; 7645 7646 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7647 } 7648 #else 7649 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7650 { 7651 } 7652 7653 static void 7654 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7655 { 7656 } 7657 #endif /* CONFIG_PCI_IOV */ 7658 7659 7660 /** 7661 * ixgbe_watchdog_subtask - check and bring link up 7662 * @adapter: pointer to the device adapter structure 7663 **/ 7664 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7665 { 7666 /* if interface is down, removing or resetting, do nothing */ 7667 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7668 test_bit(__IXGBE_REMOVING, &adapter->state) || 7669 test_bit(__IXGBE_RESETTING, &adapter->state)) 7670 return; 7671 7672 ixgbe_watchdog_update_link(adapter); 7673 7674 if (adapter->link_up) 7675 ixgbe_watchdog_link_is_up(adapter); 7676 else 7677 ixgbe_watchdog_link_is_down(adapter); 7678 7679 ixgbe_check_for_bad_vf(adapter); 7680 ixgbe_spoof_check(adapter); 7681 ixgbe_update_stats(adapter); 7682 7683 ixgbe_watchdog_flush_tx(adapter); 7684 } 7685 7686 /** 7687 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7688 * @adapter: the ixgbe adapter structure 7689 **/ 7690 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7691 { 7692 struct ixgbe_hw *hw = &adapter->hw; 7693 s32 err; 7694 7695 /* not searching for SFP so there is nothing to do here */ 7696 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7697 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7698 return; 7699 7700 if (adapter->sfp_poll_time && 7701 time_after(adapter->sfp_poll_time, jiffies)) 7702 return; /* If not yet time to poll for SFP */ 7703 7704 /* someone else is in init, wait until next service event */ 7705 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7706 return; 7707 7708 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7709 7710 err = hw->phy.ops.identify_sfp(hw); 7711 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7712 goto sfp_out; 7713 7714 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7715 /* If no cable is present, then we need to reset 7716 * the next time we find a good cable. */ 7717 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7718 } 7719 7720 /* exit on error */ 7721 if (err) 7722 goto sfp_out; 7723 7724 /* exit if reset not needed */ 7725 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7726 goto sfp_out; 7727 7728 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7729 7730 /* 7731 * A module may be identified correctly, but the EEPROM may not have 7732 * support for that module. setup_sfp() will fail in that case, so 7733 * we should not allow that module to load. 7734 */ 7735 if (hw->mac.type == ixgbe_mac_82598EB) 7736 err = hw->phy.ops.reset(hw); 7737 else 7738 err = hw->mac.ops.setup_sfp(hw); 7739 7740 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7741 goto sfp_out; 7742 7743 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7744 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7745 7746 sfp_out: 7747 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7748 7749 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7750 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7751 e_dev_err("failed to initialize because an unsupported " 7752 "SFP+ module type was detected.\n"); 7753 e_dev_err("Reload the driver after installing a " 7754 "supported module.\n"); 7755 unregister_netdev(adapter->netdev); 7756 } 7757 } 7758 7759 /** 7760 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7761 * @adapter: the ixgbe adapter structure 7762 **/ 7763 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7764 { 7765 struct ixgbe_hw *hw = &adapter->hw; 7766 u32 cap_speed; 7767 u32 speed; 7768 bool autoneg = false; 7769 7770 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7771 return; 7772 7773 /* someone else is in init, wait until next service event */ 7774 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7775 return; 7776 7777 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7778 7779 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7780 7781 /* advertise highest capable link speed */ 7782 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7783 speed = IXGBE_LINK_SPEED_10GB_FULL; 7784 else 7785 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7786 IXGBE_LINK_SPEED_1GB_FULL); 7787 7788 if (hw->mac.ops.setup_link) 7789 hw->mac.ops.setup_link(hw, speed, true); 7790 7791 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7792 adapter->link_check_timeout = jiffies; 7793 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7794 } 7795 7796 /** 7797 * ixgbe_service_timer - Timer Call-back 7798 * @t: pointer to timer_list structure 7799 **/ 7800 static void ixgbe_service_timer(struct timer_list *t) 7801 { 7802 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7803 unsigned long next_event_offset; 7804 7805 /* poll faster when waiting for link */ 7806 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7807 next_event_offset = HZ / 10; 7808 else 7809 next_event_offset = HZ * 2; 7810 7811 /* Reset the timer */ 7812 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7813 7814 ixgbe_service_event_schedule(adapter); 7815 } 7816 7817 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7818 { 7819 struct ixgbe_hw *hw = &adapter->hw; 7820 u32 status; 7821 7822 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7823 return; 7824 7825 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7826 7827 if (!hw->phy.ops.handle_lasi) 7828 return; 7829 7830 status = hw->phy.ops.handle_lasi(&adapter->hw); 7831 if (status != IXGBE_ERR_OVERTEMP) 7832 return; 7833 7834 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7835 } 7836 7837 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7838 { 7839 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7840 return; 7841 7842 rtnl_lock(); 7843 /* If we're already down, removing or resetting, just bail */ 7844 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7845 test_bit(__IXGBE_REMOVING, &adapter->state) || 7846 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7847 rtnl_unlock(); 7848 return; 7849 } 7850 7851 ixgbe_dump(adapter); 7852 netdev_err(adapter->netdev, "Reset adapter\n"); 7853 adapter->tx_timeout_count++; 7854 7855 ixgbe_reinit_locked(adapter); 7856 rtnl_unlock(); 7857 } 7858 7859 /** 7860 * ixgbe_check_fw_error - Check firmware for errors 7861 * @adapter: the adapter private structure 7862 * 7863 * Check firmware errors in register FWSM 7864 */ 7865 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7866 { 7867 struct ixgbe_hw *hw = &adapter->hw; 7868 u32 fwsm; 7869 7870 /* read fwsm.ext_err_ind register and log errors */ 7871 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7872 7873 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7874 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7875 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7876 fwsm); 7877 7878 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7879 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7880 return true; 7881 } 7882 7883 return false; 7884 } 7885 7886 /** 7887 * ixgbe_service_task - manages and runs subtasks 7888 * @work: pointer to work_struct containing our data 7889 **/ 7890 static void ixgbe_service_task(struct work_struct *work) 7891 { 7892 struct ixgbe_adapter *adapter = container_of(work, 7893 struct ixgbe_adapter, 7894 service_task); 7895 if (ixgbe_removed(adapter->hw.hw_addr)) { 7896 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7897 rtnl_lock(); 7898 ixgbe_down(adapter); 7899 rtnl_unlock(); 7900 } 7901 ixgbe_service_event_complete(adapter); 7902 return; 7903 } 7904 if (ixgbe_check_fw_error(adapter)) { 7905 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 7906 unregister_netdev(adapter->netdev); 7907 ixgbe_service_event_complete(adapter); 7908 return; 7909 } 7910 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7911 rtnl_lock(); 7912 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7913 udp_tunnel_get_rx_info(adapter->netdev); 7914 rtnl_unlock(); 7915 } 7916 ixgbe_reset_subtask(adapter); 7917 ixgbe_phy_interrupt_subtask(adapter); 7918 ixgbe_sfp_detection_subtask(adapter); 7919 ixgbe_sfp_link_config_subtask(adapter); 7920 ixgbe_check_overtemp_subtask(adapter); 7921 ixgbe_watchdog_subtask(adapter); 7922 ixgbe_fdir_reinit_subtask(adapter); 7923 ixgbe_check_hang_subtask(adapter); 7924 7925 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7926 ixgbe_ptp_overflow_check(adapter); 7927 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7928 ixgbe_ptp_rx_hang(adapter); 7929 ixgbe_ptp_tx_hang(adapter); 7930 } 7931 7932 ixgbe_service_event_complete(adapter); 7933 } 7934 7935 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7936 struct ixgbe_tx_buffer *first, 7937 u8 *hdr_len, 7938 struct ixgbe_ipsec_tx_data *itd) 7939 { 7940 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7941 struct sk_buff *skb = first->skb; 7942 union { 7943 struct iphdr *v4; 7944 struct ipv6hdr *v6; 7945 unsigned char *hdr; 7946 } ip; 7947 union { 7948 struct tcphdr *tcp; 7949 struct udphdr *udp; 7950 unsigned char *hdr; 7951 } l4; 7952 u32 paylen, l4_offset; 7953 u32 fceof_saidx = 0; 7954 int err; 7955 7956 if (skb->ip_summed != CHECKSUM_PARTIAL) 7957 return 0; 7958 7959 if (!skb_is_gso(skb)) 7960 return 0; 7961 7962 err = skb_cow_head(skb, 0); 7963 if (err < 0) 7964 return err; 7965 7966 if (eth_p_mpls(first->protocol)) 7967 ip.hdr = skb_inner_network_header(skb); 7968 else 7969 ip.hdr = skb_network_header(skb); 7970 l4.hdr = skb_checksum_start(skb); 7971 7972 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7973 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 7974 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 7975 7976 /* initialize outer IP header fields */ 7977 if (ip.v4->version == 4) { 7978 unsigned char *csum_start = skb_checksum_start(skb); 7979 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7980 int len = csum_start - trans_start; 7981 7982 /* IP header will have to cancel out any data that 7983 * is not a part of the outer IP header, so set to 7984 * a reverse csum if needed, else init check to 0. 7985 */ 7986 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7987 csum_fold(csum_partial(trans_start, 7988 len, 0)) : 0; 7989 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7990 7991 ip.v4->tot_len = 0; 7992 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7993 IXGBE_TX_FLAGS_CSUM | 7994 IXGBE_TX_FLAGS_IPV4; 7995 } else { 7996 ip.v6->payload_len = 0; 7997 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7998 IXGBE_TX_FLAGS_CSUM; 7999 } 8000 8001 /* determine offset of inner transport header */ 8002 l4_offset = l4.hdr - skb->data; 8003 8004 /* remove payload length from inner checksum */ 8005 paylen = skb->len - l4_offset; 8006 8007 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8008 /* compute length of segmentation header */ 8009 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8010 csum_replace_by_diff(&l4.tcp->check, 8011 (__force __wsum)htonl(paylen)); 8012 } else { 8013 /* compute length of segmentation header */ 8014 *hdr_len = sizeof(*l4.udp) + l4_offset; 8015 csum_replace_by_diff(&l4.udp->check, 8016 (__force __wsum)htonl(paylen)); 8017 } 8018 8019 /* update gso size and bytecount with header size */ 8020 first->gso_segs = skb_shinfo(skb)->gso_segs; 8021 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8022 8023 /* mss_l4len_id: use 0 as index for TSO */ 8024 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8025 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8026 8027 fceof_saidx |= itd->sa_idx; 8028 type_tucmd |= itd->flags | itd->trailer_len; 8029 8030 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8031 vlan_macip_lens = l4.hdr - ip.hdr; 8032 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8033 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8034 8035 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8036 mss_l4len_idx); 8037 8038 return 1; 8039 } 8040 8041 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 8042 { 8043 unsigned int offset = 0; 8044 8045 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 8046 8047 return offset == skb_checksum_start_offset(skb); 8048 } 8049 8050 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8051 struct ixgbe_tx_buffer *first, 8052 struct ixgbe_ipsec_tx_data *itd) 8053 { 8054 struct sk_buff *skb = first->skb; 8055 u32 vlan_macip_lens = 0; 8056 u32 fceof_saidx = 0; 8057 u32 type_tucmd = 0; 8058 8059 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8060 csum_failed: 8061 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8062 IXGBE_TX_FLAGS_CC))) 8063 return; 8064 goto no_csum; 8065 } 8066 8067 switch (skb->csum_offset) { 8068 case offsetof(struct tcphdr, check): 8069 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8070 /* fall through */ 8071 case offsetof(struct udphdr, check): 8072 break; 8073 case offsetof(struct sctphdr, checksum): 8074 /* validate that this is actually an SCTP request */ 8075 if (((first->protocol == htons(ETH_P_IP)) && 8076 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 8077 ((first->protocol == htons(ETH_P_IPV6)) && 8078 ixgbe_ipv6_csum_is_sctp(skb))) { 8079 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8080 break; 8081 } 8082 /* fall through */ 8083 default: 8084 skb_checksum_help(skb); 8085 goto csum_failed; 8086 } 8087 8088 /* update TX checksum flag */ 8089 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8090 vlan_macip_lens = skb_checksum_start_offset(skb) - 8091 skb_network_offset(skb); 8092 no_csum: 8093 /* vlan_macip_lens: MACLEN, VLAN tag */ 8094 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8095 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8096 8097 fceof_saidx |= itd->sa_idx; 8098 type_tucmd |= itd->flags | itd->trailer_len; 8099 8100 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8101 } 8102 8103 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8104 ((_flag <= _result) ? \ 8105 ((u32)(_input & _flag) * (_result / _flag)) : \ 8106 ((u32)(_input & _flag) / (_flag / _result))) 8107 8108 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8109 { 8110 /* set type for advanced descriptor with frame checksum insertion */ 8111 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8112 IXGBE_ADVTXD_DCMD_DEXT | 8113 IXGBE_ADVTXD_DCMD_IFCS; 8114 8115 /* set HW vlan bit if vlan is present */ 8116 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8117 IXGBE_ADVTXD_DCMD_VLE); 8118 8119 /* set segmentation enable bits for TSO/FSO */ 8120 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8121 IXGBE_ADVTXD_DCMD_TSE); 8122 8123 /* set timestamp bit if present */ 8124 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8125 IXGBE_ADVTXD_MAC_TSTAMP); 8126 8127 /* insert frame checksum */ 8128 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8129 8130 return cmd_type; 8131 } 8132 8133 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8134 u32 tx_flags, unsigned int paylen) 8135 { 8136 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8137 8138 /* enable L4 checksum for TSO and TX checksum offload */ 8139 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8140 IXGBE_TX_FLAGS_CSUM, 8141 IXGBE_ADVTXD_POPTS_TXSM); 8142 8143 /* enable IPv4 checksum for TSO */ 8144 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8145 IXGBE_TX_FLAGS_IPV4, 8146 IXGBE_ADVTXD_POPTS_IXSM); 8147 8148 /* enable IPsec */ 8149 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8150 IXGBE_TX_FLAGS_IPSEC, 8151 IXGBE_ADVTXD_POPTS_IPSEC); 8152 8153 /* 8154 * Check Context must be set if Tx switch is enabled, which it 8155 * always is for case where virtual functions are running 8156 */ 8157 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8158 IXGBE_TX_FLAGS_CC, 8159 IXGBE_ADVTXD_CC); 8160 8161 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8162 } 8163 8164 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8165 { 8166 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8167 8168 /* Herbert's original patch had: 8169 * smp_mb__after_netif_stop_queue(); 8170 * but since that doesn't exist yet, just open code it. 8171 */ 8172 smp_mb(); 8173 8174 /* We need to check again in a case another CPU has just 8175 * made room available. 8176 */ 8177 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8178 return -EBUSY; 8179 8180 /* A reprieve! - use start_queue because it doesn't call schedule */ 8181 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8182 ++tx_ring->tx_stats.restart_queue; 8183 return 0; 8184 } 8185 8186 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8187 { 8188 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8189 return 0; 8190 8191 return __ixgbe_maybe_stop_tx(tx_ring, size); 8192 } 8193 8194 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8195 struct ixgbe_tx_buffer *first, 8196 const u8 hdr_len) 8197 { 8198 struct sk_buff *skb = first->skb; 8199 struct ixgbe_tx_buffer *tx_buffer; 8200 union ixgbe_adv_tx_desc *tx_desc; 8201 skb_frag_t *frag; 8202 dma_addr_t dma; 8203 unsigned int data_len, size; 8204 u32 tx_flags = first->tx_flags; 8205 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8206 u16 i = tx_ring->next_to_use; 8207 8208 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8209 8210 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8211 8212 size = skb_headlen(skb); 8213 data_len = skb->data_len; 8214 8215 #ifdef IXGBE_FCOE 8216 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8217 if (data_len < sizeof(struct fcoe_crc_eof)) { 8218 size -= sizeof(struct fcoe_crc_eof) - data_len; 8219 data_len = 0; 8220 } else { 8221 data_len -= sizeof(struct fcoe_crc_eof); 8222 } 8223 } 8224 8225 #endif 8226 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8227 8228 tx_buffer = first; 8229 8230 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8231 if (dma_mapping_error(tx_ring->dev, dma)) 8232 goto dma_error; 8233 8234 /* record length, and DMA address */ 8235 dma_unmap_len_set(tx_buffer, len, size); 8236 dma_unmap_addr_set(tx_buffer, dma, dma); 8237 8238 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8239 8240 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8241 tx_desc->read.cmd_type_len = 8242 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8243 8244 i++; 8245 tx_desc++; 8246 if (i == tx_ring->count) { 8247 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8248 i = 0; 8249 } 8250 tx_desc->read.olinfo_status = 0; 8251 8252 dma += IXGBE_MAX_DATA_PER_TXD; 8253 size -= IXGBE_MAX_DATA_PER_TXD; 8254 8255 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8256 } 8257 8258 if (likely(!data_len)) 8259 break; 8260 8261 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8262 8263 i++; 8264 tx_desc++; 8265 if (i == tx_ring->count) { 8266 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8267 i = 0; 8268 } 8269 tx_desc->read.olinfo_status = 0; 8270 8271 #ifdef IXGBE_FCOE 8272 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8273 #else 8274 size = skb_frag_size(frag); 8275 #endif 8276 data_len -= size; 8277 8278 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8279 DMA_TO_DEVICE); 8280 8281 tx_buffer = &tx_ring->tx_buffer_info[i]; 8282 } 8283 8284 /* write last descriptor with RS and EOP bits */ 8285 cmd_type |= size | IXGBE_TXD_CMD; 8286 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8287 8288 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8289 8290 /* set the timestamp */ 8291 first->time_stamp = jiffies; 8292 8293 skb_tx_timestamp(skb); 8294 8295 /* 8296 * Force memory writes to complete before letting h/w know there 8297 * are new descriptors to fetch. (Only applicable for weak-ordered 8298 * memory model archs, such as IA-64). 8299 * 8300 * We also need this memory barrier to make certain all of the 8301 * status bits have been updated before next_to_watch is written. 8302 */ 8303 wmb(); 8304 8305 /* set next_to_watch value indicating a packet is present */ 8306 first->next_to_watch = tx_desc; 8307 8308 i++; 8309 if (i == tx_ring->count) 8310 i = 0; 8311 8312 tx_ring->next_to_use = i; 8313 8314 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8315 8316 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8317 writel(i, tx_ring->tail); 8318 } 8319 8320 return 0; 8321 dma_error: 8322 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8323 8324 /* clear dma mappings for failed tx_buffer_info map */ 8325 for (;;) { 8326 tx_buffer = &tx_ring->tx_buffer_info[i]; 8327 if (dma_unmap_len(tx_buffer, len)) 8328 dma_unmap_page(tx_ring->dev, 8329 dma_unmap_addr(tx_buffer, dma), 8330 dma_unmap_len(tx_buffer, len), 8331 DMA_TO_DEVICE); 8332 dma_unmap_len_set(tx_buffer, len, 0); 8333 if (tx_buffer == first) 8334 break; 8335 if (i == 0) 8336 i += tx_ring->count; 8337 i--; 8338 } 8339 8340 dev_kfree_skb_any(first->skb); 8341 first->skb = NULL; 8342 8343 tx_ring->next_to_use = i; 8344 8345 return -1; 8346 } 8347 8348 static void ixgbe_atr(struct ixgbe_ring *ring, 8349 struct ixgbe_tx_buffer *first) 8350 { 8351 struct ixgbe_q_vector *q_vector = ring->q_vector; 8352 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8353 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8354 union { 8355 unsigned char *network; 8356 struct iphdr *ipv4; 8357 struct ipv6hdr *ipv6; 8358 } hdr; 8359 struct tcphdr *th; 8360 unsigned int hlen; 8361 struct sk_buff *skb; 8362 __be16 vlan_id; 8363 int l4_proto; 8364 8365 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8366 if (!q_vector) 8367 return; 8368 8369 /* do nothing if sampling is disabled */ 8370 if (!ring->atr_sample_rate) 8371 return; 8372 8373 ring->atr_count++; 8374 8375 /* currently only IPv4/IPv6 with TCP is supported */ 8376 if ((first->protocol != htons(ETH_P_IP)) && 8377 (first->protocol != htons(ETH_P_IPV6))) 8378 return; 8379 8380 /* snag network header to get L4 type and address */ 8381 skb = first->skb; 8382 hdr.network = skb_network_header(skb); 8383 if (unlikely(hdr.network <= skb->data)) 8384 return; 8385 if (skb->encapsulation && 8386 first->protocol == htons(ETH_P_IP) && 8387 hdr.ipv4->protocol == IPPROTO_UDP) { 8388 struct ixgbe_adapter *adapter = q_vector->adapter; 8389 8390 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8391 VXLAN_HEADROOM)) 8392 return; 8393 8394 /* verify the port is recognized as VXLAN */ 8395 if (adapter->vxlan_port && 8396 udp_hdr(skb)->dest == adapter->vxlan_port) 8397 hdr.network = skb_inner_network_header(skb); 8398 8399 if (adapter->geneve_port && 8400 udp_hdr(skb)->dest == adapter->geneve_port) 8401 hdr.network = skb_inner_network_header(skb); 8402 } 8403 8404 /* Make sure we have at least [minimum IPv4 header + TCP] 8405 * or [IPv6 header] bytes 8406 */ 8407 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8408 return; 8409 8410 /* Currently only IPv4/IPv6 with TCP is supported */ 8411 switch (hdr.ipv4->version) { 8412 case IPVERSION: 8413 /* access ihl as u8 to avoid unaligned access on ia64 */ 8414 hlen = (hdr.network[0] & 0x0F) << 2; 8415 l4_proto = hdr.ipv4->protocol; 8416 break; 8417 case 6: 8418 hlen = hdr.network - skb->data; 8419 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8420 hlen -= hdr.network - skb->data; 8421 break; 8422 default: 8423 return; 8424 } 8425 8426 if (l4_proto != IPPROTO_TCP) 8427 return; 8428 8429 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8430 hlen + sizeof(struct tcphdr))) 8431 return; 8432 8433 th = (struct tcphdr *)(hdr.network + hlen); 8434 8435 /* skip this packet since the socket is closing */ 8436 if (th->fin) 8437 return; 8438 8439 /* sample on all syn packets or once every atr sample count */ 8440 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8441 return; 8442 8443 /* reset sample count */ 8444 ring->atr_count = 0; 8445 8446 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8447 8448 /* 8449 * src and dst are inverted, think how the receiver sees them 8450 * 8451 * The input is broken into two sections, a non-compressed section 8452 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8453 * is XORed together and stored in the compressed dword. 8454 */ 8455 input.formatted.vlan_id = vlan_id; 8456 8457 /* 8458 * since src port and flex bytes occupy the same word XOR them together 8459 * and write the value to source port portion of compressed dword 8460 */ 8461 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8462 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8463 else 8464 common.port.src ^= th->dest ^ first->protocol; 8465 common.port.dst ^= th->source; 8466 8467 switch (hdr.ipv4->version) { 8468 case IPVERSION: 8469 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8470 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8471 break; 8472 case 6: 8473 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8474 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8475 hdr.ipv6->saddr.s6_addr32[1] ^ 8476 hdr.ipv6->saddr.s6_addr32[2] ^ 8477 hdr.ipv6->saddr.s6_addr32[3] ^ 8478 hdr.ipv6->daddr.s6_addr32[0] ^ 8479 hdr.ipv6->daddr.s6_addr32[1] ^ 8480 hdr.ipv6->daddr.s6_addr32[2] ^ 8481 hdr.ipv6->daddr.s6_addr32[3]; 8482 break; 8483 default: 8484 break; 8485 } 8486 8487 if (hdr.network != skb_network_header(skb)) 8488 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8489 8490 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8491 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8492 input, common, ring->queue_index); 8493 } 8494 8495 #ifdef IXGBE_FCOE 8496 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8497 struct net_device *sb_dev) 8498 { 8499 struct ixgbe_adapter *adapter; 8500 struct ixgbe_ring_feature *f; 8501 int txq; 8502 8503 if (sb_dev) { 8504 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8505 struct net_device *vdev = sb_dev; 8506 8507 txq = vdev->tc_to_txq[tc].offset; 8508 txq += reciprocal_scale(skb_get_hash(skb), 8509 vdev->tc_to_txq[tc].count); 8510 8511 return txq; 8512 } 8513 8514 /* 8515 * only execute the code below if protocol is FCoE 8516 * or FIP and we have FCoE enabled on the adapter 8517 */ 8518 switch (vlan_get_protocol(skb)) { 8519 case htons(ETH_P_FCOE): 8520 case htons(ETH_P_FIP): 8521 adapter = netdev_priv(dev); 8522 8523 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8524 break; 8525 /* fall through */ 8526 default: 8527 return netdev_pick_tx(dev, skb, sb_dev); 8528 } 8529 8530 f = &adapter->ring_feature[RING_F_FCOE]; 8531 8532 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8533 smp_processor_id(); 8534 8535 while (txq >= f->indices) 8536 txq -= f->indices; 8537 8538 return txq + f->offset; 8539 } 8540 8541 #endif 8542 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8543 struct xdp_frame *xdpf) 8544 { 8545 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8546 struct ixgbe_tx_buffer *tx_buffer; 8547 union ixgbe_adv_tx_desc *tx_desc; 8548 u32 len, cmd_type; 8549 dma_addr_t dma; 8550 u16 i; 8551 8552 len = xdpf->len; 8553 8554 if (unlikely(!ixgbe_desc_unused(ring))) 8555 return IXGBE_XDP_CONSUMED; 8556 8557 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8558 if (dma_mapping_error(ring->dev, dma)) 8559 return IXGBE_XDP_CONSUMED; 8560 8561 /* record the location of the first descriptor for this packet */ 8562 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8563 tx_buffer->bytecount = len; 8564 tx_buffer->gso_segs = 1; 8565 tx_buffer->protocol = 0; 8566 8567 i = ring->next_to_use; 8568 tx_desc = IXGBE_TX_DESC(ring, i); 8569 8570 dma_unmap_len_set(tx_buffer, len, len); 8571 dma_unmap_addr_set(tx_buffer, dma, dma); 8572 tx_buffer->xdpf = xdpf; 8573 8574 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8575 8576 /* put descriptor type bits */ 8577 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8578 IXGBE_ADVTXD_DCMD_DEXT | 8579 IXGBE_ADVTXD_DCMD_IFCS; 8580 cmd_type |= len | IXGBE_TXD_CMD; 8581 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8582 tx_desc->read.olinfo_status = 8583 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8584 8585 /* Avoid any potential race with xdp_xmit and cleanup */ 8586 smp_wmb(); 8587 8588 /* set next_to_watch value indicating a packet is present */ 8589 i++; 8590 if (i == ring->count) 8591 i = 0; 8592 8593 tx_buffer->next_to_watch = tx_desc; 8594 ring->next_to_use = i; 8595 8596 return IXGBE_XDP_TX; 8597 } 8598 8599 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8600 struct ixgbe_adapter *adapter, 8601 struct ixgbe_ring *tx_ring) 8602 { 8603 struct ixgbe_tx_buffer *first; 8604 int tso; 8605 u32 tx_flags = 0; 8606 unsigned short f; 8607 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8608 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8609 __be16 protocol = skb->protocol; 8610 u8 hdr_len = 0; 8611 8612 /* 8613 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8614 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8615 * + 2 desc gap to keep tail from touching head, 8616 * + 1 desc for context descriptor, 8617 * otherwise try next time 8618 */ 8619 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8620 count += TXD_USE_COUNT(skb_frag_size( 8621 &skb_shinfo(skb)->frags[f])); 8622 8623 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8624 tx_ring->tx_stats.tx_busy++; 8625 return NETDEV_TX_BUSY; 8626 } 8627 8628 /* record the location of the first descriptor for this packet */ 8629 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8630 first->skb = skb; 8631 first->bytecount = skb->len; 8632 first->gso_segs = 1; 8633 8634 /* if we have a HW VLAN tag being added default to the HW one */ 8635 if (skb_vlan_tag_present(skb)) { 8636 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8637 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8638 /* else if it is a SW VLAN check the next protocol and store the tag */ 8639 } else if (protocol == htons(ETH_P_8021Q)) { 8640 struct vlan_hdr *vhdr, _vhdr; 8641 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8642 if (!vhdr) 8643 goto out_drop; 8644 8645 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8646 IXGBE_TX_FLAGS_VLAN_SHIFT; 8647 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8648 } 8649 protocol = vlan_get_protocol(skb); 8650 8651 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8652 adapter->ptp_clock) { 8653 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 8654 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8655 &adapter->state)) { 8656 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8657 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8658 8659 /* schedule check for Tx timestamp */ 8660 adapter->ptp_tx_skb = skb_get(skb); 8661 adapter->ptp_tx_start = jiffies; 8662 schedule_work(&adapter->ptp_tx_work); 8663 } else { 8664 adapter->tx_hwtstamp_skipped++; 8665 } 8666 } 8667 8668 #ifdef CONFIG_PCI_IOV 8669 /* 8670 * Use the l2switch_enable flag - would be false if the DMA 8671 * Tx switch had been disabled. 8672 */ 8673 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8674 tx_flags |= IXGBE_TX_FLAGS_CC; 8675 8676 #endif 8677 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8678 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8679 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8680 (skb->priority != TC_PRIO_CONTROL))) { 8681 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8682 tx_flags |= (skb->priority & 0x7) << 8683 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8684 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8685 struct vlan_ethhdr *vhdr; 8686 8687 if (skb_cow_head(skb, 0)) 8688 goto out_drop; 8689 vhdr = (struct vlan_ethhdr *)skb->data; 8690 vhdr->h_vlan_TCI = htons(tx_flags >> 8691 IXGBE_TX_FLAGS_VLAN_SHIFT); 8692 } else { 8693 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8694 } 8695 } 8696 8697 /* record initial flags and protocol */ 8698 first->tx_flags = tx_flags; 8699 first->protocol = protocol; 8700 8701 #ifdef IXGBE_FCOE 8702 /* setup tx offload for FCoE */ 8703 if ((protocol == htons(ETH_P_FCOE)) && 8704 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8705 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8706 if (tso < 0) 8707 goto out_drop; 8708 8709 goto xmit_fcoe; 8710 } 8711 8712 #endif /* IXGBE_FCOE */ 8713 8714 #ifdef CONFIG_IXGBE_IPSEC 8715 if (xfrm_offload(skb) && 8716 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8717 goto out_drop; 8718 #endif 8719 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8720 if (tso < 0) 8721 goto out_drop; 8722 else if (!tso) 8723 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8724 8725 /* add the ATR filter if ATR is on */ 8726 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8727 ixgbe_atr(tx_ring, first); 8728 8729 #ifdef IXGBE_FCOE 8730 xmit_fcoe: 8731 #endif /* IXGBE_FCOE */ 8732 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8733 goto cleanup_tx_timestamp; 8734 8735 return NETDEV_TX_OK; 8736 8737 out_drop: 8738 dev_kfree_skb_any(first->skb); 8739 first->skb = NULL; 8740 cleanup_tx_timestamp: 8741 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8742 dev_kfree_skb_any(adapter->ptp_tx_skb); 8743 adapter->ptp_tx_skb = NULL; 8744 cancel_work_sync(&adapter->ptp_tx_work); 8745 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8746 } 8747 8748 return NETDEV_TX_OK; 8749 } 8750 8751 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8752 struct net_device *netdev, 8753 struct ixgbe_ring *ring) 8754 { 8755 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8756 struct ixgbe_ring *tx_ring; 8757 8758 /* 8759 * The minimum packet size for olinfo paylen is 17 so pad the skb 8760 * in order to meet this minimum size requirement. 8761 */ 8762 if (skb_put_padto(skb, 17)) 8763 return NETDEV_TX_OK; 8764 8765 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 8766 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8767 return NETDEV_TX_BUSY; 8768 8769 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8770 } 8771 8772 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8773 struct net_device *netdev) 8774 { 8775 return __ixgbe_xmit_frame(skb, netdev, NULL); 8776 } 8777 8778 /** 8779 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8780 * @netdev: network interface device structure 8781 * @p: pointer to an address structure 8782 * 8783 * Returns 0 on success, negative on failure 8784 **/ 8785 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8786 { 8787 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8788 struct ixgbe_hw *hw = &adapter->hw; 8789 struct sockaddr *addr = p; 8790 8791 if (!is_valid_ether_addr(addr->sa_data)) 8792 return -EADDRNOTAVAIL; 8793 8794 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8795 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8796 8797 ixgbe_mac_set_default_filter(adapter); 8798 8799 return 0; 8800 } 8801 8802 static int 8803 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8804 { 8805 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8806 struct ixgbe_hw *hw = &adapter->hw; 8807 u16 value; 8808 int rc; 8809 8810 if (adapter->mii_bus) { 8811 int regnum = addr; 8812 8813 if (devad != MDIO_DEVAD_NONE) 8814 regnum |= (devad << 16) | MII_ADDR_C45; 8815 8816 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8817 } 8818 8819 if (prtad != hw->phy.mdio.prtad) 8820 return -EINVAL; 8821 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8822 if (!rc) 8823 rc = value; 8824 return rc; 8825 } 8826 8827 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8828 u16 addr, u16 value) 8829 { 8830 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8831 struct ixgbe_hw *hw = &adapter->hw; 8832 8833 if (adapter->mii_bus) { 8834 int regnum = addr; 8835 8836 if (devad != MDIO_DEVAD_NONE) 8837 regnum |= (devad << 16) | MII_ADDR_C45; 8838 8839 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8840 } 8841 8842 if (prtad != hw->phy.mdio.prtad) 8843 return -EINVAL; 8844 return hw->phy.ops.write_reg(hw, addr, devad, value); 8845 } 8846 8847 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8848 { 8849 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8850 8851 switch (cmd) { 8852 case SIOCSHWTSTAMP: 8853 return ixgbe_ptp_set_ts_config(adapter, req); 8854 case SIOCGHWTSTAMP: 8855 return ixgbe_ptp_get_ts_config(adapter, req); 8856 case SIOCGMIIPHY: 8857 if (!adapter->hw.phy.ops.read_reg) 8858 return -EOPNOTSUPP; 8859 /* fall through */ 8860 default: 8861 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8862 } 8863 } 8864 8865 /** 8866 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8867 * netdev->dev_addrs 8868 * @dev: network interface device structure 8869 * 8870 * Returns non-zero on failure 8871 **/ 8872 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8873 { 8874 int err = 0; 8875 struct ixgbe_adapter *adapter = netdev_priv(dev); 8876 struct ixgbe_hw *hw = &adapter->hw; 8877 8878 if (is_valid_ether_addr(hw->mac.san_addr)) { 8879 rtnl_lock(); 8880 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8881 rtnl_unlock(); 8882 8883 /* update SAN MAC vmdq pool selection */ 8884 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8885 } 8886 return err; 8887 } 8888 8889 /** 8890 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8891 * netdev->dev_addrs 8892 * @dev: network interface device structure 8893 * 8894 * Returns non-zero on failure 8895 **/ 8896 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8897 { 8898 int err = 0; 8899 struct ixgbe_adapter *adapter = netdev_priv(dev); 8900 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8901 8902 if (is_valid_ether_addr(mac->san_addr)) { 8903 rtnl_lock(); 8904 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8905 rtnl_unlock(); 8906 } 8907 return err; 8908 } 8909 8910 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8911 struct ixgbe_ring *ring) 8912 { 8913 u64 bytes, packets; 8914 unsigned int start; 8915 8916 if (ring) { 8917 do { 8918 start = u64_stats_fetch_begin_irq(&ring->syncp); 8919 packets = ring->stats.packets; 8920 bytes = ring->stats.bytes; 8921 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8922 stats->tx_packets += packets; 8923 stats->tx_bytes += bytes; 8924 } 8925 } 8926 8927 static void ixgbe_get_stats64(struct net_device *netdev, 8928 struct rtnl_link_stats64 *stats) 8929 { 8930 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8931 int i; 8932 8933 rcu_read_lock(); 8934 for (i = 0; i < adapter->num_rx_queues; i++) { 8935 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8936 u64 bytes, packets; 8937 unsigned int start; 8938 8939 if (ring) { 8940 do { 8941 start = u64_stats_fetch_begin_irq(&ring->syncp); 8942 packets = ring->stats.packets; 8943 bytes = ring->stats.bytes; 8944 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8945 stats->rx_packets += packets; 8946 stats->rx_bytes += bytes; 8947 } 8948 } 8949 8950 for (i = 0; i < adapter->num_tx_queues; i++) { 8951 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8952 8953 ixgbe_get_ring_stats64(stats, ring); 8954 } 8955 for (i = 0; i < adapter->num_xdp_queues; i++) { 8956 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8957 8958 ixgbe_get_ring_stats64(stats, ring); 8959 } 8960 rcu_read_unlock(); 8961 8962 /* following stats updated by ixgbe_watchdog_task() */ 8963 stats->multicast = netdev->stats.multicast; 8964 stats->rx_errors = netdev->stats.rx_errors; 8965 stats->rx_length_errors = netdev->stats.rx_length_errors; 8966 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8967 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8968 } 8969 8970 #ifdef CONFIG_IXGBE_DCB 8971 /** 8972 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8973 * @adapter: pointer to ixgbe_adapter 8974 * @tc: number of traffic classes currently enabled 8975 * 8976 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8977 * 802.1Q priority maps to a packet buffer that exists. 8978 */ 8979 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8980 { 8981 struct ixgbe_hw *hw = &adapter->hw; 8982 u32 reg, rsave; 8983 int i; 8984 8985 /* 82598 have a static priority to TC mapping that can not 8986 * be changed so no validation is needed. 8987 */ 8988 if (hw->mac.type == ixgbe_mac_82598EB) 8989 return; 8990 8991 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8992 rsave = reg; 8993 8994 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8995 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8996 8997 /* If up2tc is out of bounds default to zero */ 8998 if (up2tc > tc) 8999 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9000 } 9001 9002 if (reg != rsave) 9003 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9004 9005 return; 9006 } 9007 9008 /** 9009 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9010 * @adapter: Pointer to adapter struct 9011 * 9012 * Populate the netdev user priority to tc map 9013 */ 9014 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9015 { 9016 struct net_device *dev = adapter->netdev; 9017 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9018 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9019 u8 prio; 9020 9021 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9022 u8 tc = 0; 9023 9024 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9025 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9026 else if (ets) 9027 tc = ets->prio_tc[prio]; 9028 9029 netdev_set_prio_tc_map(dev, prio, tc); 9030 } 9031 } 9032 9033 #endif /* CONFIG_IXGBE_DCB */ 9034 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data) 9035 { 9036 struct ixgbe_adapter *adapter = data; 9037 struct ixgbe_fwd_adapter *accel; 9038 int pool; 9039 9040 /* we only care about macvlans... */ 9041 if (!netif_is_macvlan(vdev)) 9042 return 0; 9043 9044 /* that have hardware offload enabled... */ 9045 accel = macvlan_accel_priv(vdev); 9046 if (!accel) 9047 return 0; 9048 9049 /* If we can relocate to a different bit do so */ 9050 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9051 if (pool < adapter->num_rx_pools) { 9052 set_bit(pool, adapter->fwd_bitmask); 9053 accel->pool = pool; 9054 return 0; 9055 } 9056 9057 /* if we cannot find a free pool then disable the offload */ 9058 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9059 macvlan_release_l2fw_offload(vdev); 9060 9061 /* unbind the queues and drop the subordinate channel config */ 9062 netdev_unbind_sb_channel(adapter->netdev, vdev); 9063 netdev_set_sb_channel(vdev, 0); 9064 9065 kfree(accel); 9066 9067 return 0; 9068 } 9069 9070 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9071 { 9072 struct ixgbe_adapter *adapter = netdev_priv(dev); 9073 9074 /* flush any stale bits out of the fwd bitmask */ 9075 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9076 9077 /* walk through upper devices reassigning pools */ 9078 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9079 adapter); 9080 } 9081 9082 /** 9083 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9084 * 9085 * @dev: net device to configure 9086 * @tc: number of traffic classes to enable 9087 */ 9088 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9089 { 9090 struct ixgbe_adapter *adapter = netdev_priv(dev); 9091 struct ixgbe_hw *hw = &adapter->hw; 9092 9093 /* Hardware supports up to 8 traffic classes */ 9094 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9095 return -EINVAL; 9096 9097 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9098 return -EINVAL; 9099 9100 /* Hardware has to reinitialize queues and interrupts to 9101 * match packet buffer alignment. Unfortunately, the 9102 * hardware is not flexible enough to do this dynamically. 9103 */ 9104 if (netif_running(dev)) 9105 ixgbe_close(dev); 9106 else 9107 ixgbe_reset(adapter); 9108 9109 ixgbe_clear_interrupt_scheme(adapter); 9110 9111 #ifdef CONFIG_IXGBE_DCB 9112 if (tc) { 9113 if (adapter->xdp_prog) { 9114 e_warn(probe, "DCB is not supported with XDP\n"); 9115 9116 ixgbe_init_interrupt_scheme(adapter); 9117 if (netif_running(dev)) 9118 ixgbe_open(dev); 9119 return -EINVAL; 9120 } 9121 9122 netdev_set_num_tc(dev, tc); 9123 ixgbe_set_prio_tc_map(adapter); 9124 9125 adapter->hw_tcs = tc; 9126 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9127 9128 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9129 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9130 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9131 } 9132 } else { 9133 netdev_reset_tc(dev); 9134 9135 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9136 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9137 9138 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9139 adapter->hw_tcs = tc; 9140 9141 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9142 adapter->dcb_cfg.pfc_mode_enable = false; 9143 } 9144 9145 ixgbe_validate_rtr(adapter, tc); 9146 9147 #endif /* CONFIG_IXGBE_DCB */ 9148 ixgbe_init_interrupt_scheme(adapter); 9149 9150 ixgbe_defrag_macvlan_pools(dev); 9151 9152 if (netif_running(dev)) 9153 return ixgbe_open(dev); 9154 9155 return 0; 9156 } 9157 9158 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9159 struct tc_cls_u32_offload *cls) 9160 { 9161 u32 hdl = cls->knode.handle; 9162 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9163 u32 loc = cls->knode.handle & 0xfffff; 9164 int err = 0, i, j; 9165 struct ixgbe_jump_table *jump = NULL; 9166 9167 if (loc > IXGBE_MAX_HW_ENTRIES) 9168 return -EINVAL; 9169 9170 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9171 return -EINVAL; 9172 9173 /* Clear this filter in the link data it is associated with */ 9174 if (uhtid != 0x800) { 9175 jump = adapter->jump_tables[uhtid]; 9176 if (!jump) 9177 return -EINVAL; 9178 if (!test_bit(loc - 1, jump->child_loc_map)) 9179 return -EINVAL; 9180 clear_bit(loc - 1, jump->child_loc_map); 9181 } 9182 9183 /* Check if the filter being deleted is a link */ 9184 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9185 jump = adapter->jump_tables[i]; 9186 if (jump && jump->link_hdl == hdl) { 9187 /* Delete filters in the hardware in the child hash 9188 * table associated with this link 9189 */ 9190 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9191 if (!test_bit(j, jump->child_loc_map)) 9192 continue; 9193 spin_lock(&adapter->fdir_perfect_lock); 9194 err = ixgbe_update_ethtool_fdir_entry(adapter, 9195 NULL, 9196 j + 1); 9197 spin_unlock(&adapter->fdir_perfect_lock); 9198 clear_bit(j, jump->child_loc_map); 9199 } 9200 /* Remove resources for this link */ 9201 kfree(jump->input); 9202 kfree(jump->mask); 9203 kfree(jump); 9204 adapter->jump_tables[i] = NULL; 9205 return err; 9206 } 9207 } 9208 9209 spin_lock(&adapter->fdir_perfect_lock); 9210 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9211 spin_unlock(&adapter->fdir_perfect_lock); 9212 return err; 9213 } 9214 9215 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9216 struct tc_cls_u32_offload *cls) 9217 { 9218 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9219 9220 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9221 return -EINVAL; 9222 9223 /* This ixgbe devices do not support hash tables at the moment 9224 * so abort when given hash tables. 9225 */ 9226 if (cls->hnode.divisor > 0) 9227 return -EINVAL; 9228 9229 set_bit(uhtid - 1, &adapter->tables); 9230 return 0; 9231 } 9232 9233 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9234 struct tc_cls_u32_offload *cls) 9235 { 9236 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9237 9238 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9239 return -EINVAL; 9240 9241 clear_bit(uhtid - 1, &adapter->tables); 9242 return 0; 9243 } 9244 9245 #ifdef CONFIG_NET_CLS_ACT 9246 struct upper_walk_data { 9247 struct ixgbe_adapter *adapter; 9248 u64 action; 9249 int ifindex; 9250 u8 queue; 9251 }; 9252 9253 static int get_macvlan_queue(struct net_device *upper, void *_data) 9254 { 9255 if (netif_is_macvlan(upper)) { 9256 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9257 struct upper_walk_data *data = _data; 9258 struct ixgbe_adapter *adapter = data->adapter; 9259 int ifindex = data->ifindex; 9260 9261 if (vadapter && upper->ifindex == ifindex) { 9262 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9263 data->action = data->queue; 9264 return 1; 9265 } 9266 } 9267 9268 return 0; 9269 } 9270 9271 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9272 u8 *queue, u64 *action) 9273 { 9274 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9275 unsigned int num_vfs = adapter->num_vfs, vf; 9276 struct upper_walk_data data; 9277 struct net_device *upper; 9278 9279 /* redirect to a SRIOV VF */ 9280 for (vf = 0; vf < num_vfs; ++vf) { 9281 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9282 if (upper->ifindex == ifindex) { 9283 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9284 *action = vf + 1; 9285 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9286 return 0; 9287 } 9288 } 9289 9290 /* redirect to a offloaded macvlan netdev */ 9291 data.adapter = adapter; 9292 data.ifindex = ifindex; 9293 data.action = 0; 9294 data.queue = 0; 9295 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9296 get_macvlan_queue, &data)) { 9297 *action = data.action; 9298 *queue = data.queue; 9299 9300 return 0; 9301 } 9302 9303 return -EINVAL; 9304 } 9305 9306 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9307 struct tcf_exts *exts, u64 *action, u8 *queue) 9308 { 9309 const struct tc_action *a; 9310 int i; 9311 9312 if (!tcf_exts_has_actions(exts)) 9313 return -EINVAL; 9314 9315 tcf_exts_for_each_action(i, a, exts) { 9316 /* Drop action */ 9317 if (is_tcf_gact_shot(a)) { 9318 *action = IXGBE_FDIR_DROP_QUEUE; 9319 *queue = IXGBE_FDIR_DROP_QUEUE; 9320 return 0; 9321 } 9322 9323 /* Redirect to a VF or a offloaded macvlan */ 9324 if (is_tcf_mirred_egress_redirect(a)) { 9325 struct net_device *dev = tcf_mirred_dev(a); 9326 9327 if (!dev) 9328 return -EINVAL; 9329 return handle_redirect_action(adapter, dev->ifindex, 9330 queue, action); 9331 } 9332 9333 return -EINVAL; 9334 } 9335 9336 return -EINVAL; 9337 } 9338 #else 9339 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9340 struct tcf_exts *exts, u64 *action, u8 *queue) 9341 { 9342 return -EINVAL; 9343 } 9344 #endif /* CONFIG_NET_CLS_ACT */ 9345 9346 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9347 union ixgbe_atr_input *mask, 9348 struct tc_cls_u32_offload *cls, 9349 struct ixgbe_mat_field *field_ptr, 9350 struct ixgbe_nexthdr *nexthdr) 9351 { 9352 int i, j, off; 9353 __be32 val, m; 9354 bool found_entry = false, found_jump_field = false; 9355 9356 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9357 off = cls->knode.sel->keys[i].off; 9358 val = cls->knode.sel->keys[i].val; 9359 m = cls->knode.sel->keys[i].mask; 9360 9361 for (j = 0; field_ptr[j].val; j++) { 9362 if (field_ptr[j].off == off) { 9363 field_ptr[j].val(input, mask, (__force u32)val, 9364 (__force u32)m); 9365 input->filter.formatted.flow_type |= 9366 field_ptr[j].type; 9367 found_entry = true; 9368 break; 9369 } 9370 } 9371 if (nexthdr) { 9372 if (nexthdr->off == cls->knode.sel->keys[i].off && 9373 nexthdr->val == 9374 (__force u32)cls->knode.sel->keys[i].val && 9375 nexthdr->mask == 9376 (__force u32)cls->knode.sel->keys[i].mask) 9377 found_jump_field = true; 9378 else 9379 continue; 9380 } 9381 } 9382 9383 if (nexthdr && !found_jump_field) 9384 return -EINVAL; 9385 9386 if (!found_entry) 9387 return 0; 9388 9389 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9390 IXGBE_ATR_L4TYPE_MASK; 9391 9392 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9393 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9394 9395 return 0; 9396 } 9397 9398 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9399 struct tc_cls_u32_offload *cls) 9400 { 9401 __be16 protocol = cls->common.protocol; 9402 u32 loc = cls->knode.handle & 0xfffff; 9403 struct ixgbe_hw *hw = &adapter->hw; 9404 struct ixgbe_mat_field *field_ptr; 9405 struct ixgbe_fdir_filter *input = NULL; 9406 union ixgbe_atr_input *mask = NULL; 9407 struct ixgbe_jump_table *jump = NULL; 9408 int i, err = -EINVAL; 9409 u8 queue; 9410 u32 uhtid, link_uhtid; 9411 9412 uhtid = TC_U32_USERHTID(cls->knode.handle); 9413 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9414 9415 /* At the moment cls_u32 jumps to network layer and skips past 9416 * L2 headers. The canonical method to match L2 frames is to use 9417 * negative values. However this is error prone at best but really 9418 * just broken because there is no way to "know" what sort of hdr 9419 * is in front of the network layer. Fix cls_u32 to support L2 9420 * headers when needed. 9421 */ 9422 if (protocol != htons(ETH_P_IP)) 9423 return err; 9424 9425 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9426 e_err(drv, "Location out of range\n"); 9427 return err; 9428 } 9429 9430 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9431 * links and also the fields used to advance the parser across each 9432 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9433 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9434 * To add support for new nodes update ixgbe_model.h parse structures 9435 * this function _should_ be generic try not to hardcode values here. 9436 */ 9437 if (uhtid == 0x800) { 9438 field_ptr = (adapter->jump_tables[0])->mat; 9439 } else { 9440 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9441 return err; 9442 if (!adapter->jump_tables[uhtid]) 9443 return err; 9444 field_ptr = (adapter->jump_tables[uhtid])->mat; 9445 } 9446 9447 if (!field_ptr) 9448 return err; 9449 9450 /* At this point we know the field_ptr is valid and need to either 9451 * build cls_u32 link or attach filter. Because adding a link to 9452 * a handle that does not exist is invalid and the same for adding 9453 * rules to handles that don't exist. 9454 */ 9455 9456 if (link_uhtid) { 9457 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9458 9459 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9460 return err; 9461 9462 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9463 return err; 9464 9465 /* Multiple filters as links to the same hash table are not 9466 * supported. To add a new filter with the same next header 9467 * but different match/jump conditions, create a new hash table 9468 * and link to it. 9469 */ 9470 if (adapter->jump_tables[link_uhtid] && 9471 (adapter->jump_tables[link_uhtid])->link_hdl) { 9472 e_err(drv, "Link filter exists for link: %x\n", 9473 link_uhtid); 9474 return err; 9475 } 9476 9477 for (i = 0; nexthdr[i].jump; i++) { 9478 if (nexthdr[i].o != cls->knode.sel->offoff || 9479 nexthdr[i].s != cls->knode.sel->offshift || 9480 nexthdr[i].m != 9481 (__force u32)cls->knode.sel->offmask) 9482 return err; 9483 9484 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9485 if (!jump) 9486 return -ENOMEM; 9487 input = kzalloc(sizeof(*input), GFP_KERNEL); 9488 if (!input) { 9489 err = -ENOMEM; 9490 goto free_jump; 9491 } 9492 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9493 if (!mask) { 9494 err = -ENOMEM; 9495 goto free_input; 9496 } 9497 jump->input = input; 9498 jump->mask = mask; 9499 jump->link_hdl = cls->knode.handle; 9500 9501 err = ixgbe_clsu32_build_input(input, mask, cls, 9502 field_ptr, &nexthdr[i]); 9503 if (!err) { 9504 jump->mat = nexthdr[i].jump; 9505 adapter->jump_tables[link_uhtid] = jump; 9506 break; 9507 } else { 9508 kfree(mask); 9509 kfree(input); 9510 kfree(jump); 9511 } 9512 } 9513 return 0; 9514 } 9515 9516 input = kzalloc(sizeof(*input), GFP_KERNEL); 9517 if (!input) 9518 return -ENOMEM; 9519 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9520 if (!mask) { 9521 err = -ENOMEM; 9522 goto free_input; 9523 } 9524 9525 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9526 if ((adapter->jump_tables[uhtid])->input) 9527 memcpy(input, (adapter->jump_tables[uhtid])->input, 9528 sizeof(*input)); 9529 if ((adapter->jump_tables[uhtid])->mask) 9530 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9531 sizeof(*mask)); 9532 9533 /* Lookup in all child hash tables if this location is already 9534 * filled with a filter 9535 */ 9536 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9537 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9538 9539 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9540 e_err(drv, "Filter exists in location: %x\n", 9541 loc); 9542 err = -EINVAL; 9543 goto err_out; 9544 } 9545 } 9546 } 9547 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9548 if (err) 9549 goto err_out; 9550 9551 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9552 &queue); 9553 if (err < 0) 9554 goto err_out; 9555 9556 input->sw_idx = loc; 9557 9558 spin_lock(&adapter->fdir_perfect_lock); 9559 9560 if (hlist_empty(&adapter->fdir_filter_list)) { 9561 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9562 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9563 if (err) 9564 goto err_out_w_lock; 9565 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9566 err = -EINVAL; 9567 goto err_out_w_lock; 9568 } 9569 9570 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9571 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9572 input->sw_idx, queue); 9573 if (!err) 9574 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9575 spin_unlock(&adapter->fdir_perfect_lock); 9576 9577 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9578 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9579 9580 kfree(mask); 9581 return err; 9582 err_out_w_lock: 9583 spin_unlock(&adapter->fdir_perfect_lock); 9584 err_out: 9585 kfree(mask); 9586 free_input: 9587 kfree(input); 9588 free_jump: 9589 kfree(jump); 9590 return err; 9591 } 9592 9593 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9594 struct tc_cls_u32_offload *cls_u32) 9595 { 9596 switch (cls_u32->command) { 9597 case TC_CLSU32_NEW_KNODE: 9598 case TC_CLSU32_REPLACE_KNODE: 9599 return ixgbe_configure_clsu32(adapter, cls_u32); 9600 case TC_CLSU32_DELETE_KNODE: 9601 return ixgbe_delete_clsu32(adapter, cls_u32); 9602 case TC_CLSU32_NEW_HNODE: 9603 case TC_CLSU32_REPLACE_HNODE: 9604 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9605 case TC_CLSU32_DELETE_HNODE: 9606 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9607 default: 9608 return -EOPNOTSUPP; 9609 } 9610 } 9611 9612 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9613 void *cb_priv) 9614 { 9615 struct ixgbe_adapter *adapter = cb_priv; 9616 9617 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9618 return -EOPNOTSUPP; 9619 9620 switch (type) { 9621 case TC_SETUP_CLSU32: 9622 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9623 default: 9624 return -EOPNOTSUPP; 9625 } 9626 } 9627 9628 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9629 struct tc_mqprio_qopt *mqprio) 9630 { 9631 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9632 return ixgbe_setup_tc(dev, mqprio->num_tc); 9633 } 9634 9635 static LIST_HEAD(ixgbe_block_cb_list); 9636 9637 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9638 void *type_data) 9639 { 9640 struct ixgbe_adapter *adapter = netdev_priv(dev); 9641 9642 switch (type) { 9643 case TC_SETUP_BLOCK: 9644 return flow_block_cb_setup_simple(type_data, 9645 &ixgbe_block_cb_list, 9646 ixgbe_setup_tc_block_cb, 9647 adapter, adapter, true); 9648 case TC_SETUP_QDISC_MQPRIO: 9649 return ixgbe_setup_tc_mqprio(dev, type_data); 9650 default: 9651 return -EOPNOTSUPP; 9652 } 9653 } 9654 9655 #ifdef CONFIG_PCI_IOV 9656 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9657 { 9658 struct net_device *netdev = adapter->netdev; 9659 9660 rtnl_lock(); 9661 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9662 rtnl_unlock(); 9663 } 9664 9665 #endif 9666 void ixgbe_do_reset(struct net_device *netdev) 9667 { 9668 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9669 9670 if (netif_running(netdev)) 9671 ixgbe_reinit_locked(adapter); 9672 else 9673 ixgbe_reset(adapter); 9674 } 9675 9676 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9677 netdev_features_t features) 9678 { 9679 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9680 9681 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9682 if (!(features & NETIF_F_RXCSUM)) 9683 features &= ~NETIF_F_LRO; 9684 9685 /* Turn off LRO if not RSC capable */ 9686 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9687 features &= ~NETIF_F_LRO; 9688 9689 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9690 e_dev_err("LRO is not supported with XDP\n"); 9691 features &= ~NETIF_F_LRO; 9692 } 9693 9694 return features; 9695 } 9696 9697 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9698 { 9699 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9700 num_online_cpus()); 9701 9702 /* go back to full RSS if we're not running SR-IOV */ 9703 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9704 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9705 IXGBE_FLAG_SRIOV_ENABLED); 9706 9707 adapter->ring_feature[RING_F_RSS].limit = rss; 9708 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9709 9710 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9711 } 9712 9713 static int ixgbe_set_features(struct net_device *netdev, 9714 netdev_features_t features) 9715 { 9716 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9717 netdev_features_t changed = netdev->features ^ features; 9718 bool need_reset = false; 9719 9720 /* Make sure RSC matches LRO, reset if change */ 9721 if (!(features & NETIF_F_LRO)) { 9722 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9723 need_reset = true; 9724 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9725 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9726 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9727 if (adapter->rx_itr_setting == 1 || 9728 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9729 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9730 need_reset = true; 9731 } else if ((changed ^ features) & NETIF_F_LRO) { 9732 e_info(probe, "rx-usecs set too low, " 9733 "disabling RSC\n"); 9734 } 9735 } 9736 9737 /* 9738 * Check if Flow Director n-tuple support or hw_tc support was 9739 * enabled or disabled. If the state changed, we need to reset. 9740 */ 9741 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9742 /* turn off ATR, enable perfect filters and reset */ 9743 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9744 need_reset = true; 9745 9746 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9747 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9748 } else { 9749 /* turn off perfect filters, enable ATR and reset */ 9750 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9751 need_reset = true; 9752 9753 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9754 9755 /* We cannot enable ATR if SR-IOV is enabled */ 9756 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9757 /* We cannot enable ATR if we have 2 or more tcs */ 9758 (adapter->hw_tcs > 1) || 9759 /* We cannot enable ATR if RSS is disabled */ 9760 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9761 /* A sample rate of 0 indicates ATR disabled */ 9762 (!adapter->atr_sample_rate)) 9763 ; /* do nothing not supported */ 9764 else /* otherwise supported and set the flag */ 9765 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9766 } 9767 9768 if (changed & NETIF_F_RXALL) 9769 need_reset = true; 9770 9771 netdev->features = features; 9772 9773 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9774 if (features & NETIF_F_RXCSUM) { 9775 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9776 } else { 9777 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9778 9779 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9780 } 9781 } 9782 9783 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9784 if (features & NETIF_F_RXCSUM) { 9785 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9786 } else { 9787 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9788 9789 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9790 } 9791 } 9792 9793 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9794 ixgbe_reset_l2fw_offload(adapter); 9795 else if (need_reset) 9796 ixgbe_do_reset(netdev); 9797 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9798 NETIF_F_HW_VLAN_CTAG_FILTER)) 9799 ixgbe_set_rx_mode(netdev); 9800 9801 return 1; 9802 } 9803 9804 /** 9805 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9806 * @dev: The port's netdev 9807 * @ti: Tunnel endpoint information 9808 **/ 9809 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9810 struct udp_tunnel_info *ti) 9811 { 9812 struct ixgbe_adapter *adapter = netdev_priv(dev); 9813 struct ixgbe_hw *hw = &adapter->hw; 9814 __be16 port = ti->port; 9815 u32 port_shift = 0; 9816 u32 reg; 9817 9818 if (ti->sa_family != AF_INET) 9819 return; 9820 9821 switch (ti->type) { 9822 case UDP_TUNNEL_TYPE_VXLAN: 9823 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9824 return; 9825 9826 if (adapter->vxlan_port == port) 9827 return; 9828 9829 if (adapter->vxlan_port) { 9830 netdev_info(dev, 9831 "VXLAN port %d set, not adding port %d\n", 9832 ntohs(adapter->vxlan_port), 9833 ntohs(port)); 9834 return; 9835 } 9836 9837 adapter->vxlan_port = port; 9838 break; 9839 case UDP_TUNNEL_TYPE_GENEVE: 9840 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9841 return; 9842 9843 if (adapter->geneve_port == port) 9844 return; 9845 9846 if (adapter->geneve_port) { 9847 netdev_info(dev, 9848 "GENEVE port %d set, not adding port %d\n", 9849 ntohs(adapter->geneve_port), 9850 ntohs(port)); 9851 return; 9852 } 9853 9854 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9855 adapter->geneve_port = port; 9856 break; 9857 default: 9858 return; 9859 } 9860 9861 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9862 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9863 } 9864 9865 /** 9866 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9867 * @dev: The port's netdev 9868 * @ti: Tunnel endpoint information 9869 **/ 9870 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9871 struct udp_tunnel_info *ti) 9872 { 9873 struct ixgbe_adapter *adapter = netdev_priv(dev); 9874 u32 port_mask; 9875 9876 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9877 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9878 return; 9879 9880 if (ti->sa_family != AF_INET) 9881 return; 9882 9883 switch (ti->type) { 9884 case UDP_TUNNEL_TYPE_VXLAN: 9885 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9886 return; 9887 9888 if (adapter->vxlan_port != ti->port) { 9889 netdev_info(dev, "VXLAN port %d not found\n", 9890 ntohs(ti->port)); 9891 return; 9892 } 9893 9894 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9895 break; 9896 case UDP_TUNNEL_TYPE_GENEVE: 9897 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9898 return; 9899 9900 if (adapter->geneve_port != ti->port) { 9901 netdev_info(dev, "GENEVE port %d not found\n", 9902 ntohs(ti->port)); 9903 return; 9904 } 9905 9906 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9907 break; 9908 default: 9909 return; 9910 } 9911 9912 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9913 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9914 } 9915 9916 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9917 struct net_device *dev, 9918 const unsigned char *addr, u16 vid, 9919 u16 flags, 9920 struct netlink_ext_ack *extack) 9921 { 9922 /* guarantee we can provide a unique filter for the unicast address */ 9923 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9924 struct ixgbe_adapter *adapter = netdev_priv(dev); 9925 u16 pool = VMDQ_P(0); 9926 9927 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9928 return -ENOMEM; 9929 } 9930 9931 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9932 } 9933 9934 /** 9935 * ixgbe_configure_bridge_mode - set various bridge modes 9936 * @adapter: the private structure 9937 * @mode: requested bridge mode 9938 * 9939 * Configure some settings require for various bridge modes. 9940 **/ 9941 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9942 __u16 mode) 9943 { 9944 struct ixgbe_hw *hw = &adapter->hw; 9945 unsigned int p, num_pools; 9946 u32 vmdctl; 9947 9948 switch (mode) { 9949 case BRIDGE_MODE_VEPA: 9950 /* disable Tx loopback, rely on switch hairpin mode */ 9951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9952 9953 /* must enable Rx switching replication to allow multicast 9954 * packet reception on all VFs, and to enable source address 9955 * pruning. 9956 */ 9957 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9958 vmdctl |= IXGBE_VT_CTL_REPLEN; 9959 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9960 9961 /* enable Rx source address pruning. Note, this requires 9962 * replication to be enabled or else it does nothing. 9963 */ 9964 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9965 for (p = 0; p < num_pools; p++) { 9966 if (hw->mac.ops.set_source_address_pruning) 9967 hw->mac.ops.set_source_address_pruning(hw, 9968 true, 9969 p); 9970 } 9971 break; 9972 case BRIDGE_MODE_VEB: 9973 /* enable Tx loopback for internal VF/PF communication */ 9974 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9975 IXGBE_PFDTXGSWC_VT_LBEN); 9976 9977 /* disable Rx switching replication unless we have SR-IOV 9978 * virtual functions 9979 */ 9980 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9981 if (!adapter->num_vfs) 9982 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9983 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9984 9985 /* disable Rx source address pruning, since we don't expect to 9986 * be receiving external loopback of our transmitted frames. 9987 */ 9988 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9989 for (p = 0; p < num_pools; p++) { 9990 if (hw->mac.ops.set_source_address_pruning) 9991 hw->mac.ops.set_source_address_pruning(hw, 9992 false, 9993 p); 9994 } 9995 break; 9996 default: 9997 return -EINVAL; 9998 } 9999 10000 adapter->bridge_mode = mode; 10001 10002 e_info(drv, "enabling bridge mode: %s\n", 10003 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10004 10005 return 0; 10006 } 10007 10008 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10009 struct nlmsghdr *nlh, u16 flags, 10010 struct netlink_ext_ack *extack) 10011 { 10012 struct ixgbe_adapter *adapter = netdev_priv(dev); 10013 struct nlattr *attr, *br_spec; 10014 int rem; 10015 10016 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10017 return -EOPNOTSUPP; 10018 10019 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10020 if (!br_spec) 10021 return -EINVAL; 10022 10023 nla_for_each_nested(attr, br_spec, rem) { 10024 int status; 10025 __u16 mode; 10026 10027 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10028 continue; 10029 10030 if (nla_len(attr) < sizeof(mode)) 10031 return -EINVAL; 10032 10033 mode = nla_get_u16(attr); 10034 status = ixgbe_configure_bridge_mode(adapter, mode); 10035 if (status) 10036 return status; 10037 10038 break; 10039 } 10040 10041 return 0; 10042 } 10043 10044 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10045 struct net_device *dev, 10046 u32 filter_mask, int nlflags) 10047 { 10048 struct ixgbe_adapter *adapter = netdev_priv(dev); 10049 10050 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10051 return 0; 10052 10053 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10054 adapter->bridge_mode, 0, 0, nlflags, 10055 filter_mask, NULL); 10056 } 10057 10058 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10059 { 10060 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10061 struct ixgbe_fwd_adapter *accel; 10062 int tcs = adapter->hw_tcs ? : 1; 10063 int pool, err; 10064 10065 if (adapter->xdp_prog) { 10066 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10067 return ERR_PTR(-EINVAL); 10068 } 10069 10070 /* The hardware supported by ixgbe only filters on the destination MAC 10071 * address. In order to avoid issues we only support offloading modes 10072 * where the hardware can actually provide the functionality. 10073 */ 10074 if (!macvlan_supports_dest_filter(vdev)) 10075 return ERR_PTR(-EMEDIUMTYPE); 10076 10077 /* We need to lock down the macvlan to be a single queue device so that 10078 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10079 * the queue mapping to our netdev. 10080 */ 10081 if (netif_is_multiqueue(vdev)) 10082 return ERR_PTR(-ERANGE); 10083 10084 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10085 if (pool == adapter->num_rx_pools) { 10086 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10087 u16 reserved_pools; 10088 10089 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10090 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10091 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10092 return ERR_PTR(-EBUSY); 10093 10094 /* Hardware has a limited number of available pools. Each VF, 10095 * and the PF require a pool. Check to ensure we don't 10096 * attempt to use more then the available number of pools. 10097 */ 10098 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10099 return ERR_PTR(-EBUSY); 10100 10101 /* Enable VMDq flag so device will be set in VM mode */ 10102 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10103 IXGBE_FLAG_SRIOV_ENABLED; 10104 10105 /* Try to reserve as many queues per pool as possible, 10106 * we start with the configurations that support 4 queues 10107 * per pools, followed by 2, and then by just 1 per pool. 10108 */ 10109 if (used_pools < 32 && adapter->num_rx_pools < 16) 10110 reserved_pools = min_t(u16, 10111 32 - used_pools, 10112 16 - adapter->num_rx_pools); 10113 else if (adapter->num_rx_pools < 32) 10114 reserved_pools = min_t(u16, 10115 64 - used_pools, 10116 32 - adapter->num_rx_pools); 10117 else 10118 reserved_pools = 64 - used_pools; 10119 10120 10121 if (!reserved_pools) 10122 return ERR_PTR(-EBUSY); 10123 10124 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10125 10126 /* Force reinit of ring allocation with VMDQ enabled */ 10127 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10128 if (err) 10129 return ERR_PTR(err); 10130 10131 if (pool >= adapter->num_rx_pools) 10132 return ERR_PTR(-ENOMEM); 10133 } 10134 10135 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10136 if (!accel) 10137 return ERR_PTR(-ENOMEM); 10138 10139 set_bit(pool, adapter->fwd_bitmask); 10140 netdev_set_sb_channel(vdev, pool); 10141 accel->pool = pool; 10142 accel->netdev = vdev; 10143 10144 if (!netif_running(pdev)) 10145 return accel; 10146 10147 err = ixgbe_fwd_ring_up(adapter, accel); 10148 if (err) 10149 return ERR_PTR(err); 10150 10151 return accel; 10152 } 10153 10154 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10155 { 10156 struct ixgbe_fwd_adapter *accel = priv; 10157 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10158 unsigned int rxbase = accel->rx_base_queue; 10159 unsigned int i; 10160 10161 /* delete unicast filter associated with offloaded interface */ 10162 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10163 VMDQ_P(accel->pool)); 10164 10165 /* Allow remaining Rx packets to get flushed out of the 10166 * Rx FIFO before we drop the netdev for the ring. 10167 */ 10168 usleep_range(10000, 20000); 10169 10170 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10171 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10172 struct ixgbe_q_vector *qv = ring->q_vector; 10173 10174 /* Make sure we aren't processing any packets and clear 10175 * netdev to shut down the ring. 10176 */ 10177 if (netif_running(adapter->netdev)) 10178 napi_synchronize(&qv->napi); 10179 ring->netdev = NULL; 10180 } 10181 10182 /* unbind the queues and drop the subordinate channel config */ 10183 netdev_unbind_sb_channel(pdev, accel->netdev); 10184 netdev_set_sb_channel(accel->netdev, 0); 10185 10186 clear_bit(accel->pool, adapter->fwd_bitmask); 10187 kfree(accel); 10188 } 10189 10190 #define IXGBE_MAX_MAC_HDR_LEN 127 10191 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10192 10193 static netdev_features_t 10194 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10195 netdev_features_t features) 10196 { 10197 unsigned int network_hdr_len, mac_hdr_len; 10198 10199 /* Make certain the headers can be described by a context descriptor */ 10200 mac_hdr_len = skb_network_header(skb) - skb->data; 10201 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10202 return features & ~(NETIF_F_HW_CSUM | 10203 NETIF_F_SCTP_CRC | 10204 NETIF_F_GSO_UDP_L4 | 10205 NETIF_F_HW_VLAN_CTAG_TX | 10206 NETIF_F_TSO | 10207 NETIF_F_TSO6); 10208 10209 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10210 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10211 return features & ~(NETIF_F_HW_CSUM | 10212 NETIF_F_SCTP_CRC | 10213 NETIF_F_GSO_UDP_L4 | 10214 NETIF_F_TSO | 10215 NETIF_F_TSO6); 10216 10217 /* We can only support IPV4 TSO in tunnels if we can mangle the 10218 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10219 * IPsec offoad sets skb->encapsulation but still can handle 10220 * the TSO, so it's the exception. 10221 */ 10222 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10223 #ifdef CONFIG_IXGBE_IPSEC 10224 if (!secpath_exists(skb)) 10225 #endif 10226 features &= ~NETIF_F_TSO; 10227 } 10228 10229 return features; 10230 } 10231 10232 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10233 { 10234 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10235 struct ixgbe_adapter *adapter = netdev_priv(dev); 10236 struct bpf_prog *old_prog; 10237 bool need_reset; 10238 10239 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10240 return -EINVAL; 10241 10242 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10243 return -EINVAL; 10244 10245 /* verify ixgbe ring attributes are sufficient for XDP */ 10246 for (i = 0; i < adapter->num_rx_queues; i++) { 10247 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10248 10249 if (ring_is_rsc_enabled(ring)) 10250 return -EINVAL; 10251 10252 if (frame_size > ixgbe_rx_bufsz(ring)) 10253 return -EINVAL; 10254 } 10255 10256 if (nr_cpu_ids > MAX_XDP_QUEUES) 10257 return -ENOMEM; 10258 10259 old_prog = xchg(&adapter->xdp_prog, prog); 10260 need_reset = (!!prog != !!old_prog); 10261 10262 /* If transitioning XDP modes reconfigure rings */ 10263 if (need_reset) { 10264 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10265 10266 if (err) { 10267 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10268 return -EINVAL; 10269 } 10270 } else { 10271 for (i = 0; i < adapter->num_rx_queues; i++) 10272 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 10273 adapter->xdp_prog); 10274 } 10275 10276 if (old_prog) 10277 bpf_prog_put(old_prog); 10278 10279 /* Kick start the NAPI context if there is an AF_XDP socket open 10280 * on that queue id. This so that receiving will start. 10281 */ 10282 if (need_reset && prog) 10283 for (i = 0; i < adapter->num_rx_queues; i++) 10284 if (adapter->xdp_ring[i]->xsk_umem) 10285 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10286 XDP_WAKEUP_RX); 10287 10288 return 0; 10289 } 10290 10291 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10292 { 10293 struct ixgbe_adapter *adapter = netdev_priv(dev); 10294 10295 switch (xdp->command) { 10296 case XDP_SETUP_PROG: 10297 return ixgbe_xdp_setup(dev, xdp->prog); 10298 case XDP_QUERY_PROG: 10299 xdp->prog_id = adapter->xdp_prog ? 10300 adapter->xdp_prog->aux->id : 0; 10301 return 0; 10302 case XDP_SETUP_XSK_UMEM: 10303 return ixgbe_xsk_umem_setup(adapter, xdp->xsk.umem, 10304 xdp->xsk.queue_id); 10305 10306 default: 10307 return -EINVAL; 10308 } 10309 } 10310 10311 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10312 { 10313 /* Force memory writes to complete before letting h/w know there 10314 * are new descriptors to fetch. 10315 */ 10316 wmb(); 10317 writel(ring->next_to_use, ring->tail); 10318 } 10319 10320 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10321 struct xdp_frame **frames, u32 flags) 10322 { 10323 struct ixgbe_adapter *adapter = netdev_priv(dev); 10324 struct ixgbe_ring *ring; 10325 int drops = 0; 10326 int i; 10327 10328 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10329 return -ENETDOWN; 10330 10331 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10332 return -EINVAL; 10333 10334 /* During program transitions its possible adapter->xdp_prog is assigned 10335 * but ring has not been configured yet. In this case simply abort xmit. 10336 */ 10337 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10338 if (unlikely(!ring)) 10339 return -ENXIO; 10340 10341 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10342 return -ENXIO; 10343 10344 for (i = 0; i < n; i++) { 10345 struct xdp_frame *xdpf = frames[i]; 10346 int err; 10347 10348 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10349 if (err != IXGBE_XDP_TX) { 10350 xdp_return_frame_rx_napi(xdpf); 10351 drops++; 10352 } 10353 } 10354 10355 if (unlikely(flags & XDP_XMIT_FLUSH)) 10356 ixgbe_xdp_ring_update_tail(ring); 10357 10358 return n - drops; 10359 } 10360 10361 static const struct net_device_ops ixgbe_netdev_ops = { 10362 .ndo_open = ixgbe_open, 10363 .ndo_stop = ixgbe_close, 10364 .ndo_start_xmit = ixgbe_xmit_frame, 10365 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10366 .ndo_validate_addr = eth_validate_addr, 10367 .ndo_set_mac_address = ixgbe_set_mac, 10368 .ndo_change_mtu = ixgbe_change_mtu, 10369 .ndo_tx_timeout = ixgbe_tx_timeout, 10370 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10371 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10372 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10373 .ndo_do_ioctl = ixgbe_ioctl, 10374 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10375 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10376 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10377 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10378 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10379 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10380 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10381 .ndo_get_stats64 = ixgbe_get_stats64, 10382 .ndo_setup_tc = __ixgbe_setup_tc, 10383 #ifdef IXGBE_FCOE 10384 .ndo_select_queue = ixgbe_select_queue, 10385 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10386 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10387 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10388 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10389 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10390 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10391 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10392 #endif /* IXGBE_FCOE */ 10393 .ndo_set_features = ixgbe_set_features, 10394 .ndo_fix_features = ixgbe_fix_features, 10395 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10396 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10397 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10398 .ndo_dfwd_add_station = ixgbe_fwd_add, 10399 .ndo_dfwd_del_station = ixgbe_fwd_del, 10400 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10401 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10402 .ndo_features_check = ixgbe_features_check, 10403 .ndo_bpf = ixgbe_xdp, 10404 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10405 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10406 }; 10407 10408 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10409 struct ixgbe_ring *tx_ring) 10410 { 10411 unsigned long wait_delay, delay_interval; 10412 struct ixgbe_hw *hw = &adapter->hw; 10413 u8 reg_idx = tx_ring->reg_idx; 10414 int wait_loop; 10415 u32 txdctl; 10416 10417 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10418 10419 /* delay mechanism from ixgbe_disable_tx */ 10420 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10421 10422 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10423 wait_delay = delay_interval; 10424 10425 while (wait_loop--) { 10426 usleep_range(wait_delay, wait_delay + 10); 10427 wait_delay += delay_interval * 2; 10428 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10429 10430 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10431 return; 10432 } 10433 10434 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10435 } 10436 10437 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10438 struct ixgbe_ring *tx_ring) 10439 { 10440 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10441 ixgbe_disable_txr_hw(adapter, tx_ring); 10442 } 10443 10444 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10445 struct ixgbe_ring *rx_ring) 10446 { 10447 unsigned long wait_delay, delay_interval; 10448 struct ixgbe_hw *hw = &adapter->hw; 10449 u8 reg_idx = rx_ring->reg_idx; 10450 int wait_loop; 10451 u32 rxdctl; 10452 10453 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10454 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10455 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10456 10457 /* write value back with RXDCTL.ENABLE bit cleared */ 10458 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10459 10460 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10461 if (hw->mac.type == ixgbe_mac_82598EB && 10462 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10463 return; 10464 10465 /* delay mechanism from ixgbe_disable_rx */ 10466 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10467 10468 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10469 wait_delay = delay_interval; 10470 10471 while (wait_loop--) { 10472 usleep_range(wait_delay, wait_delay + 10); 10473 wait_delay += delay_interval * 2; 10474 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10475 10476 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10477 return; 10478 } 10479 10480 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10481 } 10482 10483 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10484 { 10485 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10486 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10487 } 10488 10489 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10490 { 10491 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10492 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10493 } 10494 10495 /** 10496 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10497 * @adapter: adapter structure 10498 * @ring: ring index 10499 * 10500 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10501 * assumes that the netdev is running. 10502 **/ 10503 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10504 { 10505 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10506 10507 rx_ring = adapter->rx_ring[ring]; 10508 tx_ring = adapter->tx_ring[ring]; 10509 xdp_ring = adapter->xdp_ring[ring]; 10510 10511 ixgbe_disable_txr(adapter, tx_ring); 10512 if (xdp_ring) 10513 ixgbe_disable_txr(adapter, xdp_ring); 10514 ixgbe_disable_rxr_hw(adapter, rx_ring); 10515 10516 if (xdp_ring) 10517 synchronize_rcu(); 10518 10519 /* Rx/Tx/XDP Tx share the same napi context. */ 10520 napi_disable(&rx_ring->q_vector->napi); 10521 10522 ixgbe_clean_tx_ring(tx_ring); 10523 if (xdp_ring) 10524 ixgbe_clean_tx_ring(xdp_ring); 10525 ixgbe_clean_rx_ring(rx_ring); 10526 10527 ixgbe_reset_txr_stats(tx_ring); 10528 if (xdp_ring) 10529 ixgbe_reset_txr_stats(xdp_ring); 10530 ixgbe_reset_rxr_stats(rx_ring); 10531 } 10532 10533 /** 10534 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10535 * @adapter: adapter structure 10536 * @ring: ring index 10537 * 10538 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10539 * assumes that the netdev is running. 10540 **/ 10541 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10542 { 10543 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10544 10545 rx_ring = adapter->rx_ring[ring]; 10546 tx_ring = adapter->tx_ring[ring]; 10547 xdp_ring = adapter->xdp_ring[ring]; 10548 10549 /* Rx/Tx/XDP Tx share the same napi context. */ 10550 napi_enable(&rx_ring->q_vector->napi); 10551 10552 ixgbe_configure_tx_ring(adapter, tx_ring); 10553 if (xdp_ring) 10554 ixgbe_configure_tx_ring(adapter, xdp_ring); 10555 ixgbe_configure_rx_ring(adapter, rx_ring); 10556 10557 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10558 if (xdp_ring) 10559 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10560 } 10561 10562 /** 10563 * ixgbe_enumerate_functions - Get the number of ports this device has 10564 * @adapter: adapter structure 10565 * 10566 * This function enumerates the phsyical functions co-located on a single slot, 10567 * in order to determine how many ports a device has. This is most useful in 10568 * determining the required GT/s of PCIe bandwidth necessary for optimal 10569 * performance. 10570 **/ 10571 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10572 { 10573 struct pci_dev *entry, *pdev = adapter->pdev; 10574 int physfns = 0; 10575 10576 /* Some cards can not use the generic count PCIe functions method, 10577 * because they are behind a parent switch, so we hardcode these with 10578 * the correct number of functions. 10579 */ 10580 if (ixgbe_pcie_from_parent(&adapter->hw)) 10581 physfns = 4; 10582 10583 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10584 /* don't count virtual functions */ 10585 if (entry->is_virtfn) 10586 continue; 10587 10588 /* When the devices on the bus don't all match our device ID, 10589 * we can't reliably determine the correct number of 10590 * functions. This can occur if a function has been direct 10591 * attached to a virtual machine using VT-d, for example. In 10592 * this case, simply return -1 to indicate this. 10593 */ 10594 if ((entry->vendor != pdev->vendor) || 10595 (entry->device != pdev->device)) 10596 return -1; 10597 10598 physfns++; 10599 } 10600 10601 return physfns; 10602 } 10603 10604 /** 10605 * ixgbe_wol_supported - Check whether device supports WoL 10606 * @adapter: the adapter private structure 10607 * @device_id: the device ID 10608 * @subdevice_id: the subsystem device ID 10609 * 10610 * This function is used by probe and ethtool to determine 10611 * which devices have WoL support 10612 * 10613 **/ 10614 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10615 u16 subdevice_id) 10616 { 10617 struct ixgbe_hw *hw = &adapter->hw; 10618 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10619 10620 /* WOL not supported on 82598 */ 10621 if (hw->mac.type == ixgbe_mac_82598EB) 10622 return false; 10623 10624 /* check eeprom to see if WOL is enabled for X540 and newer */ 10625 if (hw->mac.type >= ixgbe_mac_X540) { 10626 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10627 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10628 (hw->bus.func == 0))) 10629 return true; 10630 } 10631 10632 /* WOL is determined based on device IDs for 82599 MACs */ 10633 switch (device_id) { 10634 case IXGBE_DEV_ID_82599_SFP: 10635 /* Only these subdevices could supports WOL */ 10636 switch (subdevice_id) { 10637 case IXGBE_SUBDEV_ID_82599_560FLR: 10638 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10639 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10640 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10641 /* only support first port */ 10642 if (hw->bus.func != 0) 10643 break; 10644 /* fall through */ 10645 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10646 case IXGBE_SUBDEV_ID_82599_SFP: 10647 case IXGBE_SUBDEV_ID_82599_RNDC: 10648 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10649 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10650 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10651 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10652 return true; 10653 } 10654 break; 10655 case IXGBE_DEV_ID_82599EN_SFP: 10656 /* Only these subdevices support WOL */ 10657 switch (subdevice_id) { 10658 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10659 return true; 10660 } 10661 break; 10662 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10663 /* All except this subdevice support WOL */ 10664 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10665 return true; 10666 break; 10667 case IXGBE_DEV_ID_82599_KX4: 10668 return true; 10669 default: 10670 break; 10671 } 10672 10673 return false; 10674 } 10675 10676 /** 10677 * ixgbe_set_fw_version - Set FW version 10678 * @adapter: the adapter private structure 10679 * 10680 * This function is used by probe and ethtool to determine the FW version to 10681 * format to display. The FW version is taken from the EEPROM/NVM. 10682 */ 10683 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10684 { 10685 struct ixgbe_hw *hw = &adapter->hw; 10686 struct ixgbe_nvm_version nvm_ver; 10687 10688 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10689 if (nvm_ver.oem_valid) { 10690 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10691 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10692 nvm_ver.oem_release); 10693 return; 10694 } 10695 10696 ixgbe_get_etk_id(hw, &nvm_ver); 10697 ixgbe_get_orom_version(hw, &nvm_ver); 10698 10699 if (nvm_ver.or_valid) { 10700 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10701 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10702 nvm_ver.or_build, nvm_ver.or_patch); 10703 return; 10704 } 10705 10706 /* Set ETrack ID format */ 10707 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10708 "0x%08x", nvm_ver.etk_id); 10709 } 10710 10711 /** 10712 * ixgbe_probe - Device Initialization Routine 10713 * @pdev: PCI device information struct 10714 * @ent: entry in ixgbe_pci_tbl 10715 * 10716 * Returns 0 on success, negative on failure 10717 * 10718 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10719 * The OS initialization, configuring of the adapter private structure, 10720 * and a hardware reset occur. 10721 **/ 10722 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10723 { 10724 struct net_device *netdev; 10725 struct ixgbe_adapter *adapter = NULL; 10726 struct ixgbe_hw *hw; 10727 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10728 int i, err, pci_using_dac, expected_gts; 10729 unsigned int indices = MAX_TX_QUEUES; 10730 u8 part_str[IXGBE_PBANUM_LENGTH]; 10731 bool disable_dev = false; 10732 #ifdef IXGBE_FCOE 10733 u16 device_caps; 10734 #endif 10735 u32 eec; 10736 10737 /* Catch broken hardware that put the wrong VF device ID in 10738 * the PCIe SR-IOV capability. 10739 */ 10740 if (pdev->is_virtfn) { 10741 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10742 pci_name(pdev), pdev->vendor, pdev->device); 10743 return -EINVAL; 10744 } 10745 10746 err = pci_enable_device_mem(pdev); 10747 if (err) 10748 return err; 10749 10750 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10751 pci_using_dac = 1; 10752 } else { 10753 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10754 if (err) { 10755 dev_err(&pdev->dev, 10756 "No usable DMA configuration, aborting\n"); 10757 goto err_dma; 10758 } 10759 pci_using_dac = 0; 10760 } 10761 10762 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10763 if (err) { 10764 dev_err(&pdev->dev, 10765 "pci_request_selected_regions failed 0x%x\n", err); 10766 goto err_pci_reg; 10767 } 10768 10769 pci_enable_pcie_error_reporting(pdev); 10770 10771 pci_set_master(pdev); 10772 pci_save_state(pdev); 10773 10774 if (ii->mac == ixgbe_mac_82598EB) { 10775 #ifdef CONFIG_IXGBE_DCB 10776 /* 8 TC w/ 4 queues per TC */ 10777 indices = 4 * MAX_TRAFFIC_CLASS; 10778 #else 10779 indices = IXGBE_MAX_RSS_INDICES; 10780 #endif 10781 } 10782 10783 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10784 if (!netdev) { 10785 err = -ENOMEM; 10786 goto err_alloc_etherdev; 10787 } 10788 10789 SET_NETDEV_DEV(netdev, &pdev->dev); 10790 10791 adapter = netdev_priv(netdev); 10792 10793 adapter->netdev = netdev; 10794 adapter->pdev = pdev; 10795 hw = &adapter->hw; 10796 hw->back = adapter; 10797 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10798 10799 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10800 pci_resource_len(pdev, 0)); 10801 adapter->io_addr = hw->hw_addr; 10802 if (!hw->hw_addr) { 10803 err = -EIO; 10804 goto err_ioremap; 10805 } 10806 10807 netdev->netdev_ops = &ixgbe_netdev_ops; 10808 ixgbe_set_ethtool_ops(netdev); 10809 netdev->watchdog_timeo = 5 * HZ; 10810 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10811 10812 /* Setup hw api */ 10813 hw->mac.ops = *ii->mac_ops; 10814 hw->mac.type = ii->mac; 10815 hw->mvals = ii->mvals; 10816 if (ii->link_ops) 10817 hw->link.ops = *ii->link_ops; 10818 10819 /* EEPROM */ 10820 hw->eeprom.ops = *ii->eeprom_ops; 10821 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10822 if (ixgbe_removed(hw->hw_addr)) { 10823 err = -EIO; 10824 goto err_ioremap; 10825 } 10826 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10827 if (!(eec & BIT(8))) 10828 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10829 10830 /* PHY */ 10831 hw->phy.ops = *ii->phy_ops; 10832 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10833 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10834 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10835 hw->phy.mdio.mmds = 0; 10836 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10837 hw->phy.mdio.dev = netdev; 10838 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10839 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10840 10841 /* setup the private structure */ 10842 err = ixgbe_sw_init(adapter, ii); 10843 if (err) 10844 goto err_sw_init; 10845 10846 /* Make sure the SWFW semaphore is in a valid state */ 10847 if (hw->mac.ops.init_swfw_sync) 10848 hw->mac.ops.init_swfw_sync(hw); 10849 10850 /* Make it possible the adapter to be woken up via WOL */ 10851 switch (adapter->hw.mac.type) { 10852 case ixgbe_mac_82599EB: 10853 case ixgbe_mac_X540: 10854 case ixgbe_mac_X550: 10855 case ixgbe_mac_X550EM_x: 10856 case ixgbe_mac_x550em_a: 10857 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10858 break; 10859 default: 10860 break; 10861 } 10862 10863 /* 10864 * If there is a fan on this device and it has failed log the 10865 * failure. 10866 */ 10867 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10868 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10869 if (esdp & IXGBE_ESDP_SDP1) 10870 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10871 } 10872 10873 if (allow_unsupported_sfp) 10874 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10875 10876 /* reset_hw fills in the perm_addr as well */ 10877 hw->phy.reset_if_overtemp = true; 10878 err = hw->mac.ops.reset_hw(hw); 10879 hw->phy.reset_if_overtemp = false; 10880 ixgbe_set_eee_capable(adapter); 10881 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10882 err = 0; 10883 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10884 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10885 e_dev_err("Reload the driver after installing a supported module.\n"); 10886 goto err_sw_init; 10887 } else if (err) { 10888 e_dev_err("HW Init failed: %d\n", err); 10889 goto err_sw_init; 10890 } 10891 10892 #ifdef CONFIG_PCI_IOV 10893 /* SR-IOV not supported on the 82598 */ 10894 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10895 goto skip_sriov; 10896 /* Mailbox */ 10897 ixgbe_init_mbx_params_pf(hw); 10898 hw->mbx.ops = ii->mbx_ops; 10899 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10900 ixgbe_enable_sriov(adapter, max_vfs); 10901 skip_sriov: 10902 10903 #endif 10904 netdev->features = NETIF_F_SG | 10905 NETIF_F_TSO | 10906 NETIF_F_TSO6 | 10907 NETIF_F_RXHASH | 10908 NETIF_F_RXCSUM | 10909 NETIF_F_HW_CSUM; 10910 10911 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10912 NETIF_F_GSO_GRE_CSUM | \ 10913 NETIF_F_GSO_IPXIP4 | \ 10914 NETIF_F_GSO_IPXIP6 | \ 10915 NETIF_F_GSO_UDP_TUNNEL | \ 10916 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10917 10918 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10919 netdev->features |= NETIF_F_GSO_PARTIAL | 10920 IXGBE_GSO_PARTIAL_FEATURES; 10921 10922 if (hw->mac.type >= ixgbe_mac_82599EB) 10923 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 10924 10925 #ifdef CONFIG_IXGBE_IPSEC 10926 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10927 NETIF_F_HW_ESP_TX_CSUM | \ 10928 NETIF_F_GSO_ESP) 10929 10930 if (adapter->ipsec) 10931 netdev->features |= IXGBE_ESP_FEATURES; 10932 #endif 10933 /* copy netdev features into list of user selectable features */ 10934 netdev->hw_features |= netdev->features | 10935 NETIF_F_HW_VLAN_CTAG_FILTER | 10936 NETIF_F_HW_VLAN_CTAG_RX | 10937 NETIF_F_HW_VLAN_CTAG_TX | 10938 NETIF_F_RXALL | 10939 NETIF_F_HW_L2FW_DOFFLOAD; 10940 10941 if (hw->mac.type >= ixgbe_mac_82599EB) 10942 netdev->hw_features |= NETIF_F_NTUPLE | 10943 NETIF_F_HW_TC; 10944 10945 if (pci_using_dac) 10946 netdev->features |= NETIF_F_HIGHDMA; 10947 10948 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10949 netdev->hw_enc_features |= netdev->vlan_features; 10950 netdev->mpls_features |= NETIF_F_SG | 10951 NETIF_F_TSO | 10952 NETIF_F_TSO6 | 10953 NETIF_F_HW_CSUM; 10954 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10955 10956 /* set this bit last since it cannot be part of vlan_features */ 10957 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10958 NETIF_F_HW_VLAN_CTAG_RX | 10959 NETIF_F_HW_VLAN_CTAG_TX; 10960 10961 netdev->priv_flags |= IFF_UNICAST_FLT; 10962 netdev->priv_flags |= IFF_SUPP_NOFCS; 10963 10964 /* MTU range: 68 - 9710 */ 10965 netdev->min_mtu = ETH_MIN_MTU; 10966 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10967 10968 #ifdef CONFIG_IXGBE_DCB 10969 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10970 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10971 #endif 10972 10973 #ifdef IXGBE_FCOE 10974 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10975 unsigned int fcoe_l; 10976 10977 if (hw->mac.ops.get_device_caps) { 10978 hw->mac.ops.get_device_caps(hw, &device_caps); 10979 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10980 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10981 } 10982 10983 10984 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10985 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10986 10987 netdev->features |= NETIF_F_FSO | 10988 NETIF_F_FCOE_CRC; 10989 10990 netdev->vlan_features |= NETIF_F_FSO | 10991 NETIF_F_FCOE_CRC | 10992 NETIF_F_FCOE_MTU; 10993 } 10994 #endif /* IXGBE_FCOE */ 10995 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10996 netdev->hw_features |= NETIF_F_LRO; 10997 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10998 netdev->features |= NETIF_F_LRO; 10999 11000 if (ixgbe_check_fw_error(adapter)) { 11001 err = -EIO; 11002 goto err_sw_init; 11003 } 11004 11005 /* make sure the EEPROM is good */ 11006 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11007 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11008 err = -EIO; 11009 goto err_sw_init; 11010 } 11011 11012 eth_platform_get_mac_address(&adapter->pdev->dev, 11013 adapter->hw.mac.perm_addr); 11014 11015 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 11016 11017 if (!is_valid_ether_addr(netdev->dev_addr)) { 11018 e_dev_err("invalid MAC address\n"); 11019 err = -EIO; 11020 goto err_sw_init; 11021 } 11022 11023 /* Set hw->mac.addr to permanent MAC address */ 11024 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11025 ixgbe_mac_set_default_filter(adapter); 11026 11027 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11028 11029 if (ixgbe_removed(hw->hw_addr)) { 11030 err = -EIO; 11031 goto err_sw_init; 11032 } 11033 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11034 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11035 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11036 11037 err = ixgbe_init_interrupt_scheme(adapter); 11038 if (err) 11039 goto err_sw_init; 11040 11041 for (i = 0; i < adapter->num_rx_queues; i++) 11042 u64_stats_init(&adapter->rx_ring[i]->syncp); 11043 for (i = 0; i < adapter->num_tx_queues; i++) 11044 u64_stats_init(&adapter->tx_ring[i]->syncp); 11045 for (i = 0; i < adapter->num_xdp_queues; i++) 11046 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11047 11048 /* WOL not supported for all devices */ 11049 adapter->wol = 0; 11050 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11051 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11052 pdev->subsystem_device); 11053 if (hw->wol_enabled) 11054 adapter->wol = IXGBE_WUFC_MAG; 11055 11056 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11057 11058 /* save off EEPROM version number */ 11059 ixgbe_set_fw_version(adapter); 11060 11061 /* pick up the PCI bus settings for reporting later */ 11062 if (ixgbe_pcie_from_parent(hw)) 11063 ixgbe_get_parent_bus_info(adapter); 11064 else 11065 hw->mac.ops.get_bus_info(hw); 11066 11067 /* calculate the expected PCIe bandwidth required for optimal 11068 * performance. Note that some older parts will never have enough 11069 * bandwidth due to being older generation PCIe parts. We clamp these 11070 * parts to ensure no warning is displayed if it can't be fixed. 11071 */ 11072 switch (hw->mac.type) { 11073 case ixgbe_mac_82598EB: 11074 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11075 break; 11076 default: 11077 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11078 break; 11079 } 11080 11081 /* don't check link if we failed to enumerate functions */ 11082 if (expected_gts > 0) 11083 ixgbe_check_minimum_link(adapter, expected_gts); 11084 11085 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11086 if (err) 11087 strlcpy(part_str, "Unknown", sizeof(part_str)); 11088 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11089 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11090 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11091 part_str); 11092 else 11093 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11094 hw->mac.type, hw->phy.type, part_str); 11095 11096 e_dev_info("%pM\n", netdev->dev_addr); 11097 11098 /* reset the hardware with the new settings */ 11099 err = hw->mac.ops.start_hw(hw); 11100 if (err == IXGBE_ERR_EEPROM_VERSION) { 11101 /* We are running on a pre-production device, log a warning */ 11102 e_dev_warn("This device is a pre-production adapter/LOM. " 11103 "Please be aware there may be issues associated " 11104 "with your hardware. If you are experiencing " 11105 "problems please contact your Intel or hardware " 11106 "representative who provided you with this " 11107 "hardware.\n"); 11108 } 11109 strcpy(netdev->name, "eth%d"); 11110 pci_set_drvdata(pdev, adapter); 11111 err = register_netdev(netdev); 11112 if (err) 11113 goto err_register; 11114 11115 11116 /* power down the optics for 82599 SFP+ fiber */ 11117 if (hw->mac.ops.disable_tx_laser) 11118 hw->mac.ops.disable_tx_laser(hw); 11119 11120 /* carrier off reporting is important to ethtool even BEFORE open */ 11121 netif_carrier_off(netdev); 11122 11123 #ifdef CONFIG_IXGBE_DCA 11124 if (dca_add_requester(&pdev->dev) == 0) { 11125 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11126 ixgbe_setup_dca(adapter); 11127 } 11128 #endif 11129 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11130 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11131 for (i = 0; i < adapter->num_vfs; i++) 11132 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11133 } 11134 11135 /* firmware requires driver version to be 0xFFFFFFFF 11136 * since os does not support feature 11137 */ 11138 if (hw->mac.ops.set_fw_drv_ver) 11139 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11140 sizeof(ixgbe_driver_version) - 1, 11141 ixgbe_driver_version); 11142 11143 /* add san mac addr to netdev */ 11144 ixgbe_add_sanmac_netdev(netdev); 11145 11146 e_dev_info("%s\n", ixgbe_default_device_descr); 11147 11148 #ifdef CONFIG_IXGBE_HWMON 11149 if (ixgbe_sysfs_init(adapter)) 11150 e_err(probe, "failed to allocate sysfs resources\n"); 11151 #endif /* CONFIG_IXGBE_HWMON */ 11152 11153 ixgbe_dbg_adapter_init(adapter); 11154 11155 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11156 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11157 hw->mac.ops.setup_link(hw, 11158 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11159 true); 11160 11161 ixgbe_mii_bus_init(hw); 11162 11163 return 0; 11164 11165 err_register: 11166 ixgbe_release_hw_control(adapter); 11167 ixgbe_clear_interrupt_scheme(adapter); 11168 err_sw_init: 11169 ixgbe_disable_sriov(adapter); 11170 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11171 iounmap(adapter->io_addr); 11172 kfree(adapter->jump_tables[0]); 11173 kfree(adapter->mac_table); 11174 kfree(adapter->rss_key); 11175 bitmap_free(adapter->af_xdp_zc_qps); 11176 err_ioremap: 11177 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11178 free_netdev(netdev); 11179 err_alloc_etherdev: 11180 pci_release_mem_regions(pdev); 11181 err_pci_reg: 11182 err_dma: 11183 if (!adapter || disable_dev) 11184 pci_disable_device(pdev); 11185 return err; 11186 } 11187 11188 /** 11189 * ixgbe_remove - Device Removal Routine 11190 * @pdev: PCI device information struct 11191 * 11192 * ixgbe_remove is called by the PCI subsystem to alert the driver 11193 * that it should release a PCI device. The could be caused by a 11194 * Hot-Plug event, or because the driver is going to be removed from 11195 * memory. 11196 **/ 11197 static void ixgbe_remove(struct pci_dev *pdev) 11198 { 11199 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11200 struct net_device *netdev; 11201 bool disable_dev; 11202 int i; 11203 11204 /* if !adapter then we already cleaned up in probe */ 11205 if (!adapter) 11206 return; 11207 11208 netdev = adapter->netdev; 11209 ixgbe_dbg_adapter_exit(adapter); 11210 11211 set_bit(__IXGBE_REMOVING, &adapter->state); 11212 cancel_work_sync(&adapter->service_task); 11213 11214 if (adapter->mii_bus) 11215 mdiobus_unregister(adapter->mii_bus); 11216 11217 #ifdef CONFIG_IXGBE_DCA 11218 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11219 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11220 dca_remove_requester(&pdev->dev); 11221 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11222 IXGBE_DCA_CTRL_DCA_DISABLE); 11223 } 11224 11225 #endif 11226 #ifdef CONFIG_IXGBE_HWMON 11227 ixgbe_sysfs_exit(adapter); 11228 #endif /* CONFIG_IXGBE_HWMON */ 11229 11230 /* remove the added san mac */ 11231 ixgbe_del_sanmac_netdev(netdev); 11232 11233 #ifdef CONFIG_PCI_IOV 11234 ixgbe_disable_sriov(adapter); 11235 #endif 11236 if (netdev->reg_state == NETREG_REGISTERED) 11237 unregister_netdev(netdev); 11238 11239 ixgbe_stop_ipsec_offload(adapter); 11240 ixgbe_clear_interrupt_scheme(adapter); 11241 11242 ixgbe_release_hw_control(adapter); 11243 11244 #ifdef CONFIG_DCB 11245 kfree(adapter->ixgbe_ieee_pfc); 11246 kfree(adapter->ixgbe_ieee_ets); 11247 11248 #endif 11249 iounmap(adapter->io_addr); 11250 pci_release_mem_regions(pdev); 11251 11252 e_dev_info("complete\n"); 11253 11254 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11255 if (adapter->jump_tables[i]) { 11256 kfree(adapter->jump_tables[i]->input); 11257 kfree(adapter->jump_tables[i]->mask); 11258 } 11259 kfree(adapter->jump_tables[i]); 11260 } 11261 11262 kfree(adapter->mac_table); 11263 kfree(adapter->rss_key); 11264 bitmap_free(adapter->af_xdp_zc_qps); 11265 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11266 free_netdev(netdev); 11267 11268 pci_disable_pcie_error_reporting(pdev); 11269 11270 if (disable_dev) 11271 pci_disable_device(pdev); 11272 } 11273 11274 /** 11275 * ixgbe_io_error_detected - called when PCI error is detected 11276 * @pdev: Pointer to PCI device 11277 * @state: The current pci connection state 11278 * 11279 * This function is called after a PCI bus error affecting 11280 * this device has been detected. 11281 */ 11282 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11283 pci_channel_state_t state) 11284 { 11285 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11286 struct net_device *netdev = adapter->netdev; 11287 11288 #ifdef CONFIG_PCI_IOV 11289 struct ixgbe_hw *hw = &adapter->hw; 11290 struct pci_dev *bdev, *vfdev; 11291 u32 dw0, dw1, dw2, dw3; 11292 int vf, pos; 11293 u16 req_id, pf_func; 11294 11295 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11296 adapter->num_vfs == 0) 11297 goto skip_bad_vf_detection; 11298 11299 bdev = pdev->bus->self; 11300 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11301 bdev = bdev->bus->self; 11302 11303 if (!bdev) 11304 goto skip_bad_vf_detection; 11305 11306 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11307 if (!pos) 11308 goto skip_bad_vf_detection; 11309 11310 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11311 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11312 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11313 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11314 if (ixgbe_removed(hw->hw_addr)) 11315 goto skip_bad_vf_detection; 11316 11317 req_id = dw1 >> 16; 11318 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11319 if (!(req_id & 0x0080)) 11320 goto skip_bad_vf_detection; 11321 11322 pf_func = req_id & 0x01; 11323 if ((pf_func & 1) == (pdev->devfn & 1)) { 11324 unsigned int device_id; 11325 11326 vf = (req_id & 0x7F) >> 1; 11327 e_dev_err("VF %d has caused a PCIe error\n", vf); 11328 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11329 "%8.8x\tdw3: %8.8x\n", 11330 dw0, dw1, dw2, dw3); 11331 switch (adapter->hw.mac.type) { 11332 case ixgbe_mac_82599EB: 11333 device_id = IXGBE_82599_VF_DEVICE_ID; 11334 break; 11335 case ixgbe_mac_X540: 11336 device_id = IXGBE_X540_VF_DEVICE_ID; 11337 break; 11338 case ixgbe_mac_X550: 11339 device_id = IXGBE_DEV_ID_X550_VF; 11340 break; 11341 case ixgbe_mac_X550EM_x: 11342 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11343 break; 11344 case ixgbe_mac_x550em_a: 11345 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11346 break; 11347 default: 11348 device_id = 0; 11349 break; 11350 } 11351 11352 /* Find the pci device of the offending VF */ 11353 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11354 while (vfdev) { 11355 if (vfdev->devfn == (req_id & 0xFF)) 11356 break; 11357 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11358 device_id, vfdev); 11359 } 11360 /* 11361 * There's a slim chance the VF could have been hot plugged, 11362 * so if it is no longer present we don't need to issue the 11363 * VFLR. Just clean up the AER in that case. 11364 */ 11365 if (vfdev) { 11366 pcie_flr(vfdev); 11367 /* Free device reference count */ 11368 pci_dev_put(vfdev); 11369 } 11370 } 11371 11372 /* 11373 * Even though the error may have occurred on the other port 11374 * we still need to increment the vf error reference count for 11375 * both ports because the I/O resume function will be called 11376 * for both of them. 11377 */ 11378 adapter->vferr_refcount++; 11379 11380 return PCI_ERS_RESULT_RECOVERED; 11381 11382 skip_bad_vf_detection: 11383 #endif /* CONFIG_PCI_IOV */ 11384 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11385 return PCI_ERS_RESULT_DISCONNECT; 11386 11387 if (!netif_device_present(netdev)) 11388 return PCI_ERS_RESULT_DISCONNECT; 11389 11390 rtnl_lock(); 11391 netif_device_detach(netdev); 11392 11393 if (netif_running(netdev)) 11394 ixgbe_close_suspend(adapter); 11395 11396 if (state == pci_channel_io_perm_failure) { 11397 rtnl_unlock(); 11398 return PCI_ERS_RESULT_DISCONNECT; 11399 } 11400 11401 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11402 pci_disable_device(pdev); 11403 rtnl_unlock(); 11404 11405 /* Request a slot reset. */ 11406 return PCI_ERS_RESULT_NEED_RESET; 11407 } 11408 11409 /** 11410 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11411 * @pdev: Pointer to PCI device 11412 * 11413 * Restart the card from scratch, as if from a cold-boot. 11414 */ 11415 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11416 { 11417 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11418 pci_ers_result_t result; 11419 11420 if (pci_enable_device_mem(pdev)) { 11421 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11422 result = PCI_ERS_RESULT_DISCONNECT; 11423 } else { 11424 smp_mb__before_atomic(); 11425 clear_bit(__IXGBE_DISABLED, &adapter->state); 11426 adapter->hw.hw_addr = adapter->io_addr; 11427 pci_set_master(pdev); 11428 pci_restore_state(pdev); 11429 pci_save_state(pdev); 11430 11431 pci_wake_from_d3(pdev, false); 11432 11433 ixgbe_reset(adapter); 11434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11435 result = PCI_ERS_RESULT_RECOVERED; 11436 } 11437 11438 return result; 11439 } 11440 11441 /** 11442 * ixgbe_io_resume - called when traffic can start flowing again. 11443 * @pdev: Pointer to PCI device 11444 * 11445 * This callback is called when the error recovery driver tells us that 11446 * its OK to resume normal operation. 11447 */ 11448 static void ixgbe_io_resume(struct pci_dev *pdev) 11449 { 11450 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11451 struct net_device *netdev = adapter->netdev; 11452 11453 #ifdef CONFIG_PCI_IOV 11454 if (adapter->vferr_refcount) { 11455 e_info(drv, "Resuming after VF err\n"); 11456 adapter->vferr_refcount--; 11457 return; 11458 } 11459 11460 #endif 11461 rtnl_lock(); 11462 if (netif_running(netdev)) 11463 ixgbe_open(netdev); 11464 11465 netif_device_attach(netdev); 11466 rtnl_unlock(); 11467 } 11468 11469 static const struct pci_error_handlers ixgbe_err_handler = { 11470 .error_detected = ixgbe_io_error_detected, 11471 .slot_reset = ixgbe_io_slot_reset, 11472 .resume = ixgbe_io_resume, 11473 }; 11474 11475 static struct pci_driver ixgbe_driver = { 11476 .name = ixgbe_driver_name, 11477 .id_table = ixgbe_pci_tbl, 11478 .probe = ixgbe_probe, 11479 .remove = ixgbe_remove, 11480 #ifdef CONFIG_PM 11481 .suspend = ixgbe_suspend, 11482 .resume = ixgbe_resume, 11483 #endif 11484 .shutdown = ixgbe_shutdown, 11485 .sriov_configure = ixgbe_pci_sriov_configure, 11486 .err_handler = &ixgbe_err_handler 11487 }; 11488 11489 /** 11490 * ixgbe_init_module - Driver Registration Routine 11491 * 11492 * ixgbe_init_module is the first routine called when the driver is 11493 * loaded. All it does is register with the PCI subsystem. 11494 **/ 11495 static int __init ixgbe_init_module(void) 11496 { 11497 int ret; 11498 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11499 pr_info("%s\n", ixgbe_copyright); 11500 11501 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11502 if (!ixgbe_wq) { 11503 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11504 return -ENOMEM; 11505 } 11506 11507 ixgbe_dbg_init(); 11508 11509 ret = pci_register_driver(&ixgbe_driver); 11510 if (ret) { 11511 destroy_workqueue(ixgbe_wq); 11512 ixgbe_dbg_exit(); 11513 return ret; 11514 } 11515 11516 #ifdef CONFIG_IXGBE_DCA 11517 dca_register_notify(&dca_notifier); 11518 #endif 11519 11520 return 0; 11521 } 11522 11523 module_init(ixgbe_init_module); 11524 11525 /** 11526 * ixgbe_exit_module - Driver Exit Cleanup Routine 11527 * 11528 * ixgbe_exit_module is called just before the driver is removed 11529 * from memory. 11530 **/ 11531 static void __exit ixgbe_exit_module(void) 11532 { 11533 #ifdef CONFIG_IXGBE_DCA 11534 dca_unregister_notify(&dca_notifier); 11535 #endif 11536 pci_unregister_driver(&ixgbe_driver); 11537 11538 ixgbe_dbg_exit(); 11539 if (ixgbe_wq) { 11540 destroy_workqueue(ixgbe_wq); 11541 ixgbe_wq = NULL; 11542 } 11543 } 11544 11545 #ifdef CONFIG_IXGBE_DCA 11546 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11547 void *p) 11548 { 11549 int ret_val; 11550 11551 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11552 __ixgbe_notify_dca); 11553 11554 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11555 } 11556 11557 #endif /* CONFIG_IXGBE_DCA */ 11558 11559 module_exit(ixgbe_exit_module); 11560 11561 /* ixgbe_main.c */ 11562