1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <linux/bpf.h> 53 #include <linux/bpf_trace.h> 54 #include <linux/atomic.h> 55 #include <scsi/fc/fc_fcoe.h> 56 #include <net/udp_tunnel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/vxlan.h> 61 #include <net/mpls.h> 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 #include "ixgbe_model.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "5.1.0-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2016 Intel Corporation."; 83 84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 85 86 static const struct ixgbe_info *ixgbe_info_tbl[] = { 87 [board_82598] = &ixgbe_82598_info, 88 [board_82599] = &ixgbe_82599_info, 89 [board_X540] = &ixgbe_X540_info, 90 [board_X550] = &ixgbe_X550_info, 91 [board_X550EM_x] = &ixgbe_X550EM_x_info, 92 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 93 [board_x550em_a] = &ixgbe_x550em_a_info, 94 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 152 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 153 /* required last entry */ 154 {0, } 155 }; 156 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 157 158 #ifdef CONFIG_IXGBE_DCA 159 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 160 void *p); 161 static struct notifier_block dca_notifier = { 162 .notifier_call = ixgbe_notify_dca, 163 .next = NULL, 164 .priority = 0 165 }; 166 #endif 167 168 #ifdef CONFIG_PCI_IOV 169 static unsigned int max_vfs; 170 module_param(max_vfs, uint, 0); 171 MODULE_PARM_DESC(max_vfs, 172 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 173 #endif /* CONFIG_PCI_IOV */ 174 175 static unsigned int allow_unsupported_sfp; 176 module_param(allow_unsupported_sfp, uint, 0); 177 MODULE_PARM_DESC(allow_unsupported_sfp, 178 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 179 180 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 181 static int debug = -1; 182 module_param(debug, int, 0); 183 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 184 185 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 186 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 187 MODULE_LICENSE("GPL"); 188 MODULE_VERSION(DRV_VERSION); 189 190 static struct workqueue_struct *ixgbe_wq; 191 192 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 193 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 194 195 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 196 u32 reg, u16 *value) 197 { 198 struct pci_dev *parent_dev; 199 struct pci_bus *parent_bus; 200 201 parent_bus = adapter->pdev->bus->parent; 202 if (!parent_bus) 203 return -1; 204 205 parent_dev = parent_bus->self; 206 if (!parent_dev) 207 return -1; 208 209 if (!pci_is_pcie(parent_dev)) 210 return -1; 211 212 pcie_capability_read_word(parent_dev, reg, value); 213 if (*value == IXGBE_FAILED_READ_CFG_WORD && 214 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 215 return -1; 216 return 0; 217 } 218 219 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 220 { 221 struct ixgbe_hw *hw = &adapter->hw; 222 u16 link_status = 0; 223 int err; 224 225 hw->bus.type = ixgbe_bus_type_pci_express; 226 227 /* Get the negotiated link width and speed from PCI config space of the 228 * parent, as this device is behind a switch 229 */ 230 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 231 232 /* assume caller will handle error case */ 233 if (err) 234 return err; 235 236 hw->bus.width = ixgbe_convert_bus_width(link_status); 237 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 238 239 return 0; 240 } 241 242 /** 243 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 244 * @hw: hw specific details 245 * 246 * This function is used by probe to determine whether a device's PCI-Express 247 * bandwidth details should be gathered from the parent bus instead of from the 248 * device. Used to ensure that various locations all have the correct device ID 249 * checks. 250 */ 251 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 252 { 253 switch (hw->device_id) { 254 case IXGBE_DEV_ID_82599_SFP_SF_QP: 255 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 256 return true; 257 default: 258 return false; 259 } 260 } 261 262 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 263 int expected_gts) 264 { 265 struct ixgbe_hw *hw = &adapter->hw; 266 int max_gts = 0; 267 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 268 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 269 struct pci_dev *pdev; 270 271 /* Some devices are not connected over PCIe and thus do not negotiate 272 * speed. These devices do not have valid bus info, and thus any report 273 * we generate may not be correct. 274 */ 275 if (hw->bus.type == ixgbe_bus_type_internal) 276 return; 277 278 /* determine whether to use the parent device */ 279 if (ixgbe_pcie_from_parent(&adapter->hw)) 280 pdev = adapter->pdev->bus->parent->self; 281 else 282 pdev = adapter->pdev; 283 284 if (pcie_get_minimum_link(pdev, &speed, &width) || 285 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 286 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 287 return; 288 } 289 290 switch (speed) { 291 case PCIE_SPEED_2_5GT: 292 /* 8b/10b encoding reduces max throughput by 20% */ 293 max_gts = 2 * width; 294 break; 295 case PCIE_SPEED_5_0GT: 296 /* 8b/10b encoding reduces max throughput by 20% */ 297 max_gts = 4 * width; 298 break; 299 case PCIE_SPEED_8_0GT: 300 /* 128b/130b encoding reduces throughput by less than 2% */ 301 max_gts = 8 * width; 302 break; 303 default: 304 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 305 return; 306 } 307 308 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 309 max_gts); 310 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 311 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 312 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 313 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 314 "Unknown"), 315 width, 316 (speed == PCIE_SPEED_2_5GT ? "20%" : 317 speed == PCIE_SPEED_5_0GT ? "20%" : 318 speed == PCIE_SPEED_8_0GT ? "<2%" : 319 "Unknown")); 320 321 if (max_gts < expected_gts) { 322 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 323 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 324 expected_gts); 325 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 326 } 327 } 328 329 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 330 { 331 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 332 !test_bit(__IXGBE_REMOVING, &adapter->state) && 333 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 334 queue_work(ixgbe_wq, &adapter->service_task); 335 } 336 337 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 338 { 339 struct ixgbe_adapter *adapter = hw->back; 340 341 if (!hw->hw_addr) 342 return; 343 hw->hw_addr = NULL; 344 e_dev_err("Adapter removed\n"); 345 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 346 ixgbe_service_event_schedule(adapter); 347 } 348 349 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 350 { 351 u32 value; 352 353 /* The following check not only optimizes a bit by not 354 * performing a read on the status register when the 355 * register just read was a status register read that 356 * returned IXGBE_FAILED_READ_REG. It also blocks any 357 * potential recursion. 358 */ 359 if (reg == IXGBE_STATUS) { 360 ixgbe_remove_adapter(hw); 361 return; 362 } 363 value = ixgbe_read_reg(hw, IXGBE_STATUS); 364 if (value == IXGBE_FAILED_READ_REG) 365 ixgbe_remove_adapter(hw); 366 } 367 368 /** 369 * ixgbe_read_reg - Read from device register 370 * @hw: hw specific details 371 * @reg: offset of register to read 372 * 373 * Returns : value read or IXGBE_FAILED_READ_REG if removed 374 * 375 * This function is used to read device registers. It checks for device 376 * removal by confirming any read that returns all ones by checking the 377 * status register value for all ones. This function avoids reading from 378 * the hardware if a removal was previously detected in which case it 379 * returns IXGBE_FAILED_READ_REG (all ones). 380 */ 381 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 382 { 383 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 384 u32 value; 385 386 if (ixgbe_removed(reg_addr)) 387 return IXGBE_FAILED_READ_REG; 388 if (unlikely(hw->phy.nw_mng_if_sel & 389 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 390 struct ixgbe_adapter *adapter; 391 int i; 392 393 for (i = 0; i < 200; ++i) { 394 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 395 if (likely(!value)) 396 goto writes_completed; 397 if (value == IXGBE_FAILED_READ_REG) { 398 ixgbe_remove_adapter(hw); 399 return IXGBE_FAILED_READ_REG; 400 } 401 udelay(5); 402 } 403 404 adapter = hw->back; 405 e_warn(hw, "register writes incomplete %08x\n", value); 406 } 407 408 writes_completed: 409 value = readl(reg_addr + reg); 410 if (unlikely(value == IXGBE_FAILED_READ_REG)) 411 ixgbe_check_remove(hw, reg); 412 return value; 413 } 414 415 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 416 { 417 u16 value; 418 419 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 420 if (value == IXGBE_FAILED_READ_CFG_WORD) { 421 ixgbe_remove_adapter(hw); 422 return true; 423 } 424 return false; 425 } 426 427 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 428 { 429 struct ixgbe_adapter *adapter = hw->back; 430 u16 value; 431 432 if (ixgbe_removed(hw->hw_addr)) 433 return IXGBE_FAILED_READ_CFG_WORD; 434 pci_read_config_word(adapter->pdev, reg, &value); 435 if (value == IXGBE_FAILED_READ_CFG_WORD && 436 ixgbe_check_cfg_remove(hw, adapter->pdev)) 437 return IXGBE_FAILED_READ_CFG_WORD; 438 return value; 439 } 440 441 #ifdef CONFIG_PCI_IOV 442 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 443 { 444 struct ixgbe_adapter *adapter = hw->back; 445 u32 value; 446 447 if (ixgbe_removed(hw->hw_addr)) 448 return IXGBE_FAILED_READ_CFG_DWORD; 449 pci_read_config_dword(adapter->pdev, reg, &value); 450 if (value == IXGBE_FAILED_READ_CFG_DWORD && 451 ixgbe_check_cfg_remove(hw, adapter->pdev)) 452 return IXGBE_FAILED_READ_CFG_DWORD; 453 return value; 454 } 455 #endif /* CONFIG_PCI_IOV */ 456 457 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 458 { 459 struct ixgbe_adapter *adapter = hw->back; 460 461 if (ixgbe_removed(hw->hw_addr)) 462 return; 463 pci_write_config_word(adapter->pdev, reg, value); 464 } 465 466 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 467 { 468 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 469 470 /* flush memory to make sure state is correct before next watchdog */ 471 smp_mb__before_atomic(); 472 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 473 } 474 475 struct ixgbe_reg_info { 476 u32 ofs; 477 char *name; 478 }; 479 480 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 481 482 /* General Registers */ 483 {IXGBE_CTRL, "CTRL"}, 484 {IXGBE_STATUS, "STATUS"}, 485 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 486 487 /* Interrupt Registers */ 488 {IXGBE_EICR, "EICR"}, 489 490 /* RX Registers */ 491 {IXGBE_SRRCTL(0), "SRRCTL"}, 492 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 493 {IXGBE_RDLEN(0), "RDLEN"}, 494 {IXGBE_RDH(0), "RDH"}, 495 {IXGBE_RDT(0), "RDT"}, 496 {IXGBE_RXDCTL(0), "RXDCTL"}, 497 {IXGBE_RDBAL(0), "RDBAL"}, 498 {IXGBE_RDBAH(0), "RDBAH"}, 499 500 /* TX Registers */ 501 {IXGBE_TDBAL(0), "TDBAL"}, 502 {IXGBE_TDBAH(0), "TDBAH"}, 503 {IXGBE_TDLEN(0), "TDLEN"}, 504 {IXGBE_TDH(0), "TDH"}, 505 {IXGBE_TDT(0), "TDT"}, 506 {IXGBE_TXDCTL(0), "TXDCTL"}, 507 508 /* List Terminator */ 509 { .name = NULL } 510 }; 511 512 513 /* 514 * ixgbe_regdump - register printout routine 515 */ 516 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 517 { 518 int i; 519 char rname[16]; 520 u32 regs[64]; 521 522 switch (reginfo->ofs) { 523 case IXGBE_SRRCTL(0): 524 for (i = 0; i < 64; i++) 525 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 526 break; 527 case IXGBE_DCA_RXCTRL(0): 528 for (i = 0; i < 64; i++) 529 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 530 break; 531 case IXGBE_RDLEN(0): 532 for (i = 0; i < 64; i++) 533 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 534 break; 535 case IXGBE_RDH(0): 536 for (i = 0; i < 64; i++) 537 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 538 break; 539 case IXGBE_RDT(0): 540 for (i = 0; i < 64; i++) 541 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 542 break; 543 case IXGBE_RXDCTL(0): 544 for (i = 0; i < 64; i++) 545 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 546 break; 547 case IXGBE_RDBAL(0): 548 for (i = 0; i < 64; i++) 549 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 550 break; 551 case IXGBE_RDBAH(0): 552 for (i = 0; i < 64; i++) 553 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 554 break; 555 case IXGBE_TDBAL(0): 556 for (i = 0; i < 64; i++) 557 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 558 break; 559 case IXGBE_TDBAH(0): 560 for (i = 0; i < 64; i++) 561 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 562 break; 563 case IXGBE_TDLEN(0): 564 for (i = 0; i < 64; i++) 565 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 566 break; 567 case IXGBE_TDH(0): 568 for (i = 0; i < 64; i++) 569 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 570 break; 571 case IXGBE_TDT(0): 572 for (i = 0; i < 64; i++) 573 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 574 break; 575 case IXGBE_TXDCTL(0): 576 for (i = 0; i < 64; i++) 577 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 578 break; 579 default: 580 pr_info("%-15s %08x\n", 581 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 582 return; 583 } 584 585 i = 0; 586 while (i < 64) { 587 int j; 588 char buf[9 * 8 + 1]; 589 char *p = buf; 590 591 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 592 for (j = 0; j < 8; j++) 593 p += sprintf(p, " %08x", regs[i++]); 594 pr_err("%-15s%s\n", rname, buf); 595 } 596 597 } 598 599 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 600 { 601 struct ixgbe_tx_buffer *tx_buffer; 602 603 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 604 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 605 n, ring->next_to_use, ring->next_to_clean, 606 (u64)dma_unmap_addr(tx_buffer, dma), 607 dma_unmap_len(tx_buffer, len), 608 tx_buffer->next_to_watch, 609 (u64)tx_buffer->time_stamp); 610 } 611 612 /* 613 * ixgbe_dump - Print registers, tx-rings and rx-rings 614 */ 615 static void ixgbe_dump(struct ixgbe_adapter *adapter) 616 { 617 struct net_device *netdev = adapter->netdev; 618 struct ixgbe_hw *hw = &adapter->hw; 619 struct ixgbe_reg_info *reginfo; 620 int n = 0; 621 struct ixgbe_ring *ring; 622 struct ixgbe_tx_buffer *tx_buffer; 623 union ixgbe_adv_tx_desc *tx_desc; 624 struct my_u0 { u64 a; u64 b; } *u0; 625 struct ixgbe_ring *rx_ring; 626 union ixgbe_adv_rx_desc *rx_desc; 627 struct ixgbe_rx_buffer *rx_buffer_info; 628 int i = 0; 629 630 if (!netif_msg_hw(adapter)) 631 return; 632 633 /* Print netdevice Info */ 634 if (netdev) { 635 dev_info(&adapter->pdev->dev, "Net device Info\n"); 636 pr_info("Device Name state " 637 "trans_start\n"); 638 pr_info("%-15s %016lX %016lX\n", 639 netdev->name, 640 netdev->state, 641 dev_trans_start(netdev)); 642 } 643 644 /* Print Registers */ 645 dev_info(&adapter->pdev->dev, "Register Dump\n"); 646 pr_info(" Register Name Value\n"); 647 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 648 reginfo->name; reginfo++) { 649 ixgbe_regdump(hw, reginfo); 650 } 651 652 /* Print TX Ring Summary */ 653 if (!netdev || !netif_running(netdev)) 654 return; 655 656 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 657 pr_info(" %s %s %s %s\n", 658 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 659 "leng", "ntw", "timestamp"); 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 ring = adapter->tx_ring[n]; 662 ixgbe_print_buffer(ring, n); 663 } 664 665 for (n = 0; n < adapter->num_xdp_queues; n++) { 666 ring = adapter->xdp_ring[n]; 667 ixgbe_print_buffer(ring, n); 668 } 669 670 /* Print TX Rings */ 671 if (!netif_msg_tx_done(adapter)) 672 goto rx_ring_summary; 673 674 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 675 676 /* Transmit Descriptor Formats 677 * 678 * 82598 Advanced Transmit Descriptor 679 * +--------------------------------------------------------------+ 680 * 0 | Buffer Address [63:0] | 681 * +--------------------------------------------------------------+ 682 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 683 * +--------------------------------------------------------------+ 684 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 685 * 686 * 82598 Advanced Transmit Descriptor (Write-Back Format) 687 * +--------------------------------------------------------------+ 688 * 0 | RSV [63:0] | 689 * +--------------------------------------------------------------+ 690 * 8 | RSV | STA | NXTSEQ | 691 * +--------------------------------------------------------------+ 692 * 63 36 35 32 31 0 693 * 694 * 82599+ Advanced Transmit Descriptor 695 * +--------------------------------------------------------------+ 696 * 0 | Buffer Address [63:0] | 697 * +--------------------------------------------------------------+ 698 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 699 * +--------------------------------------------------------------+ 700 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 701 * 702 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 703 * +--------------------------------------------------------------+ 704 * 0 | RSV [63:0] | 705 * +--------------------------------------------------------------+ 706 * 8 | RSV | STA | RSV | 707 * +--------------------------------------------------------------+ 708 * 63 36 35 32 31 0 709 */ 710 711 for (n = 0; n < adapter->num_tx_queues; n++) { 712 ring = adapter->tx_ring[n]; 713 pr_info("------------------------------------\n"); 714 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 715 pr_info("------------------------------------\n"); 716 pr_info("%s%s %s %s %s %s\n", 717 "T [desc] [address 63:0 ] ", 718 "[PlPOIdStDDt Ln] [bi->dma ] ", 719 "leng", "ntw", "timestamp", "bi->skb"); 720 721 for (i = 0; ring->desc && (i < ring->count); i++) { 722 tx_desc = IXGBE_TX_DESC(ring, i); 723 tx_buffer = &ring->tx_buffer_info[i]; 724 u0 = (struct my_u0 *)tx_desc; 725 if (dma_unmap_len(tx_buffer, len) > 0) { 726 const char *ring_desc; 727 728 if (i == ring->next_to_use && 729 i == ring->next_to_clean) 730 ring_desc = " NTC/U"; 731 else if (i == ring->next_to_use) 732 ring_desc = " NTU"; 733 else if (i == ring->next_to_clean) 734 ring_desc = " NTC"; 735 else 736 ring_desc = ""; 737 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 738 i, 739 le64_to_cpu(u0->a), 740 le64_to_cpu(u0->b), 741 (u64)dma_unmap_addr(tx_buffer, dma), 742 dma_unmap_len(tx_buffer, len), 743 tx_buffer->next_to_watch, 744 (u64)tx_buffer->time_stamp, 745 tx_buffer->skb, 746 ring_desc); 747 748 if (netif_msg_pktdata(adapter) && 749 tx_buffer->skb) 750 print_hex_dump(KERN_INFO, "", 751 DUMP_PREFIX_ADDRESS, 16, 1, 752 tx_buffer->skb->data, 753 dma_unmap_len(tx_buffer, len), 754 true); 755 } 756 } 757 } 758 759 /* Print RX Rings Summary */ 760 rx_ring_summary: 761 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 762 pr_info("Queue [NTU] [NTC]\n"); 763 for (n = 0; n < adapter->num_rx_queues; n++) { 764 rx_ring = adapter->rx_ring[n]; 765 pr_info("%5d %5X %5X\n", 766 n, rx_ring->next_to_use, rx_ring->next_to_clean); 767 } 768 769 /* Print RX Rings */ 770 if (!netif_msg_rx_status(adapter)) 771 return; 772 773 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 774 775 /* Receive Descriptor Formats 776 * 777 * 82598 Advanced Receive Descriptor (Read) Format 778 * 63 1 0 779 * +-----------------------------------------------------+ 780 * 0 | Packet Buffer Address [63:1] |A0/NSE| 781 * +----------------------------------------------+------+ 782 * 8 | Header Buffer Address [63:1] | DD | 783 * +-----------------------------------------------------+ 784 * 785 * 786 * 82598 Advanced Receive Descriptor (Write-Back) Format 787 * 788 * 63 48 47 32 31 30 21 20 16 15 4 3 0 789 * +------------------------------------------------------+ 790 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 791 * | Packet | IP | | | | Type | Type | 792 * | Checksum | Ident | | | | | | 793 * +------------------------------------------------------+ 794 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 795 * +------------------------------------------------------+ 796 * 63 48 47 32 31 20 19 0 797 * 798 * 82599+ Advanced Receive Descriptor (Read) Format 799 * 63 1 0 800 * +-----------------------------------------------------+ 801 * 0 | Packet Buffer Address [63:1] |A0/NSE| 802 * +----------------------------------------------+------+ 803 * 8 | Header Buffer Address [63:1] | DD | 804 * +-----------------------------------------------------+ 805 * 806 * 807 * 82599+ Advanced Receive Descriptor (Write-Back) Format 808 * 809 * 63 48 47 32 31 30 21 20 17 16 4 3 0 810 * +------------------------------------------------------+ 811 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 812 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 813 * |/ Flow Dir Flt ID | | | | | | 814 * +------------------------------------------------------+ 815 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 816 * +------------------------------------------------------+ 817 * 63 48 47 32 31 20 19 0 818 */ 819 820 for (n = 0; n < adapter->num_rx_queues; n++) { 821 rx_ring = adapter->rx_ring[n]; 822 pr_info("------------------------------------\n"); 823 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 824 pr_info("------------------------------------\n"); 825 pr_info("%s%s%s\n", 826 "R [desc] [ PktBuf A0] ", 827 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 828 "<-- Adv Rx Read format"); 829 pr_info("%s%s%s\n", 830 "RWB[desc] [PcsmIpSHl PtRs] ", 831 "[vl er S cks ln] ---------------- [bi->skb ] ", 832 "<-- Adv Rx Write-Back format"); 833 834 for (i = 0; i < rx_ring->count; i++) { 835 const char *ring_desc; 836 837 if (i == rx_ring->next_to_use) 838 ring_desc = " NTU"; 839 else if (i == rx_ring->next_to_clean) 840 ring_desc = " NTC"; 841 else 842 ring_desc = ""; 843 844 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 845 rx_desc = IXGBE_RX_DESC(rx_ring, i); 846 u0 = (struct my_u0 *)rx_desc; 847 if (rx_desc->wb.upper.length) { 848 /* Descriptor Done */ 849 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 850 i, 851 le64_to_cpu(u0->a), 852 le64_to_cpu(u0->b), 853 rx_buffer_info->skb, 854 ring_desc); 855 } else { 856 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 857 i, 858 le64_to_cpu(u0->a), 859 le64_to_cpu(u0->b), 860 (u64)rx_buffer_info->dma, 861 rx_buffer_info->skb, 862 ring_desc); 863 864 if (netif_msg_pktdata(adapter) && 865 rx_buffer_info->dma) { 866 print_hex_dump(KERN_INFO, "", 867 DUMP_PREFIX_ADDRESS, 16, 1, 868 page_address(rx_buffer_info->page) + 869 rx_buffer_info->page_offset, 870 ixgbe_rx_bufsz(rx_ring), true); 871 } 872 } 873 } 874 } 875 } 876 877 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 878 { 879 u32 ctrl_ext; 880 881 /* Let firmware take over control of h/w */ 882 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 884 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 885 } 886 887 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 888 { 889 u32 ctrl_ext; 890 891 /* Let firmware know the driver has taken over */ 892 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 894 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 895 } 896 897 /** 898 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 899 * @adapter: pointer to adapter struct 900 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 901 * @queue: queue to map the corresponding interrupt to 902 * @msix_vector: the vector to map to the corresponding queue 903 * 904 */ 905 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 906 u8 queue, u8 msix_vector) 907 { 908 u32 ivar, index; 909 struct ixgbe_hw *hw = &adapter->hw; 910 switch (hw->mac.type) { 911 case ixgbe_mac_82598EB: 912 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 913 if (direction == -1) 914 direction = 0; 915 index = (((direction * 64) + queue) >> 2) & 0x1F; 916 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 917 ivar &= ~(0xFF << (8 * (queue & 0x3))); 918 ivar |= (msix_vector << (8 * (queue & 0x3))); 919 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 920 break; 921 case ixgbe_mac_82599EB: 922 case ixgbe_mac_X540: 923 case ixgbe_mac_X550: 924 case ixgbe_mac_X550EM_x: 925 case ixgbe_mac_x550em_a: 926 if (direction == -1) { 927 /* other causes */ 928 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 929 index = ((queue & 1) * 8); 930 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 931 ivar &= ~(0xFF << index); 932 ivar |= (msix_vector << index); 933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 934 break; 935 } else { 936 /* tx or rx causes */ 937 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 938 index = ((16 * (queue & 1)) + (8 * direction)); 939 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 940 ivar &= ~(0xFF << index); 941 ivar |= (msix_vector << index); 942 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 943 break; 944 } 945 default: 946 break; 947 } 948 } 949 950 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 951 u64 qmask) 952 { 953 u32 mask; 954 955 switch (adapter->hw.mac.type) { 956 case ixgbe_mac_82598EB: 957 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 959 break; 960 case ixgbe_mac_82599EB: 961 case ixgbe_mac_X540: 962 case ixgbe_mac_X550: 963 case ixgbe_mac_X550EM_x: 964 case ixgbe_mac_x550em_a: 965 mask = (qmask & 0xFFFFFFFF); 966 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 967 mask = (qmask >> 32); 968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 969 break; 970 default: 971 break; 972 } 973 } 974 975 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 976 { 977 struct ixgbe_hw *hw = &adapter->hw; 978 struct ixgbe_hw_stats *hwstats = &adapter->stats; 979 int i; 980 u32 data; 981 982 if ((hw->fc.current_mode != ixgbe_fc_full) && 983 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 984 return; 985 986 switch (hw->mac.type) { 987 case ixgbe_mac_82598EB: 988 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 989 break; 990 default: 991 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 992 } 993 hwstats->lxoffrxc += data; 994 995 /* refill credits (no tx hang) if we received xoff */ 996 if (!data) 997 return; 998 999 for (i = 0; i < adapter->num_tx_queues; i++) 1000 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1001 &adapter->tx_ring[i]->state); 1002 1003 for (i = 0; i < adapter->num_xdp_queues; i++) 1004 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1005 &adapter->xdp_ring[i]->state); 1006 } 1007 1008 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1009 { 1010 struct ixgbe_hw *hw = &adapter->hw; 1011 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1012 u32 xoff[8] = {0}; 1013 u8 tc; 1014 int i; 1015 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1016 1017 if (adapter->ixgbe_ieee_pfc) 1018 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1019 1020 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1021 ixgbe_update_xoff_rx_lfc(adapter); 1022 return; 1023 } 1024 1025 /* update stats for each tc, only valid with PFC enabled */ 1026 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1027 u32 pxoffrxc; 1028 1029 switch (hw->mac.type) { 1030 case ixgbe_mac_82598EB: 1031 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1032 break; 1033 default: 1034 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1035 } 1036 hwstats->pxoffrxc[i] += pxoffrxc; 1037 /* Get the TC for given UP */ 1038 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1039 xoff[tc] += pxoffrxc; 1040 } 1041 1042 /* disarm tx queues that have received xoff frames */ 1043 for (i = 0; i < adapter->num_tx_queues; i++) { 1044 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1045 1046 tc = tx_ring->dcb_tc; 1047 if (xoff[tc]) 1048 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1049 } 1050 1051 for (i = 0; i < adapter->num_xdp_queues; i++) { 1052 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1053 1054 tc = xdp_ring->dcb_tc; 1055 if (xoff[tc]) 1056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1057 } 1058 } 1059 1060 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1061 { 1062 return ring->stats.packets; 1063 } 1064 1065 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1066 { 1067 struct ixgbe_adapter *adapter; 1068 struct ixgbe_hw *hw; 1069 u32 head, tail; 1070 1071 if (ring->l2_accel_priv) 1072 adapter = ring->l2_accel_priv->real_adapter; 1073 else 1074 adapter = netdev_priv(ring->netdev); 1075 1076 hw = &adapter->hw; 1077 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1078 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1079 1080 if (head != tail) 1081 return (head < tail) ? 1082 tail - head : (tail + ring->count - head); 1083 1084 return 0; 1085 } 1086 1087 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1088 { 1089 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1090 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1091 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1092 1093 clear_check_for_tx_hang(tx_ring); 1094 1095 /* 1096 * Check for a hung queue, but be thorough. This verifies 1097 * that a transmit has been completed since the previous 1098 * check AND there is at least one packet pending. The 1099 * ARMED bit is set to indicate a potential hang. The 1100 * bit is cleared if a pause frame is received to remove 1101 * false hang detection due to PFC or 802.3x frames. By 1102 * requiring this to fail twice we avoid races with 1103 * pfc clearing the ARMED bit and conditions where we 1104 * run the check_tx_hang logic with a transmit completion 1105 * pending but without time to complete it yet. 1106 */ 1107 if (tx_done_old == tx_done && tx_pending) 1108 /* make sure it is true for two checks in a row */ 1109 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1110 &tx_ring->state); 1111 /* update completed stats and continue */ 1112 tx_ring->tx_stats.tx_done_old = tx_done; 1113 /* reset the countdown */ 1114 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1115 1116 return false; 1117 } 1118 1119 /** 1120 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1121 * @adapter: driver private struct 1122 **/ 1123 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1124 { 1125 1126 /* Do the reset outside of interrupt context */ 1127 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1128 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1129 e_warn(drv, "initiating reset due to tx timeout\n"); 1130 ixgbe_service_event_schedule(adapter); 1131 } 1132 } 1133 1134 /** 1135 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1136 **/ 1137 static int ixgbe_tx_maxrate(struct net_device *netdev, 1138 int queue_index, u32 maxrate) 1139 { 1140 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1141 struct ixgbe_hw *hw = &adapter->hw; 1142 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1143 1144 if (!maxrate) 1145 return 0; 1146 1147 /* Calculate the rate factor values to set */ 1148 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1149 bcnrc_val /= maxrate; 1150 1151 /* clear everything but the rate factor */ 1152 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1153 IXGBE_RTTBCNRC_RF_DEC_MASK; 1154 1155 /* enable the rate scheduler */ 1156 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1157 1158 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1159 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1160 1161 return 0; 1162 } 1163 1164 /** 1165 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1166 * @q_vector: structure containing interrupt and ring information 1167 * @tx_ring: tx ring to clean 1168 * @napi_budget: Used to determine if we are in netpoll 1169 **/ 1170 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1171 struct ixgbe_ring *tx_ring, int napi_budget) 1172 { 1173 struct ixgbe_adapter *adapter = q_vector->adapter; 1174 struct ixgbe_tx_buffer *tx_buffer; 1175 union ixgbe_adv_tx_desc *tx_desc; 1176 unsigned int total_bytes = 0, total_packets = 0; 1177 unsigned int budget = q_vector->tx.work_limit; 1178 unsigned int i = tx_ring->next_to_clean; 1179 1180 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1181 return true; 1182 1183 tx_buffer = &tx_ring->tx_buffer_info[i]; 1184 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1185 i -= tx_ring->count; 1186 1187 do { 1188 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1189 1190 /* if next_to_watch is not set then there is no work pending */ 1191 if (!eop_desc) 1192 break; 1193 1194 /* prevent any other reads prior to eop_desc */ 1195 smp_rmb(); 1196 1197 /* if DD is not set pending work has not been completed */ 1198 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1199 break; 1200 1201 /* clear next_to_watch to prevent false hangs */ 1202 tx_buffer->next_to_watch = NULL; 1203 1204 /* update the statistics for this packet */ 1205 total_bytes += tx_buffer->bytecount; 1206 total_packets += tx_buffer->gso_segs; 1207 1208 /* free the skb */ 1209 if (ring_is_xdp(tx_ring)) 1210 page_frag_free(tx_buffer->data); 1211 else 1212 napi_consume_skb(tx_buffer->skb, napi_budget); 1213 1214 /* unmap skb header data */ 1215 dma_unmap_single(tx_ring->dev, 1216 dma_unmap_addr(tx_buffer, dma), 1217 dma_unmap_len(tx_buffer, len), 1218 DMA_TO_DEVICE); 1219 1220 /* clear tx_buffer data */ 1221 dma_unmap_len_set(tx_buffer, len, 0); 1222 1223 /* unmap remaining buffers */ 1224 while (tx_desc != eop_desc) { 1225 tx_buffer++; 1226 tx_desc++; 1227 i++; 1228 if (unlikely(!i)) { 1229 i -= tx_ring->count; 1230 tx_buffer = tx_ring->tx_buffer_info; 1231 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1232 } 1233 1234 /* unmap any remaining paged data */ 1235 if (dma_unmap_len(tx_buffer, len)) { 1236 dma_unmap_page(tx_ring->dev, 1237 dma_unmap_addr(tx_buffer, dma), 1238 dma_unmap_len(tx_buffer, len), 1239 DMA_TO_DEVICE); 1240 dma_unmap_len_set(tx_buffer, len, 0); 1241 } 1242 } 1243 1244 /* move us one more past the eop_desc for start of next pkt */ 1245 tx_buffer++; 1246 tx_desc++; 1247 i++; 1248 if (unlikely(!i)) { 1249 i -= tx_ring->count; 1250 tx_buffer = tx_ring->tx_buffer_info; 1251 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1252 } 1253 1254 /* issue prefetch for next Tx descriptor */ 1255 prefetch(tx_desc); 1256 1257 /* update budget accounting */ 1258 budget--; 1259 } while (likely(budget)); 1260 1261 i += tx_ring->count; 1262 tx_ring->next_to_clean = i; 1263 u64_stats_update_begin(&tx_ring->syncp); 1264 tx_ring->stats.bytes += total_bytes; 1265 tx_ring->stats.packets += total_packets; 1266 u64_stats_update_end(&tx_ring->syncp); 1267 q_vector->tx.total_bytes += total_bytes; 1268 q_vector->tx.total_packets += total_packets; 1269 1270 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1271 /* schedule immediate reset if we believe we hung */ 1272 struct ixgbe_hw *hw = &adapter->hw; 1273 e_err(drv, "Detected Tx Unit Hang %s\n" 1274 " Tx Queue <%d>\n" 1275 " TDH, TDT <%x>, <%x>\n" 1276 " next_to_use <%x>\n" 1277 " next_to_clean <%x>\n" 1278 "tx_buffer_info[next_to_clean]\n" 1279 " time_stamp <%lx>\n" 1280 " jiffies <%lx>\n", 1281 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1282 tx_ring->queue_index, 1283 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1284 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1285 tx_ring->next_to_use, i, 1286 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1287 1288 if (!ring_is_xdp(tx_ring)) 1289 netif_stop_subqueue(tx_ring->netdev, 1290 tx_ring->queue_index); 1291 1292 e_info(probe, 1293 "tx hang %d detected on queue %d, resetting adapter\n", 1294 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1295 1296 /* schedule immediate reset if we believe we hung */ 1297 ixgbe_tx_timeout_reset(adapter); 1298 1299 /* the adapter is about to reset, no point in enabling stuff */ 1300 return true; 1301 } 1302 1303 if (ring_is_xdp(tx_ring)) 1304 return !!budget; 1305 1306 netdev_tx_completed_queue(txring_txq(tx_ring), 1307 total_packets, total_bytes); 1308 1309 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1310 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1311 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1312 /* Make sure that anybody stopping the queue after this 1313 * sees the new next_to_clean. 1314 */ 1315 smp_mb(); 1316 if (__netif_subqueue_stopped(tx_ring->netdev, 1317 tx_ring->queue_index) 1318 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1319 netif_wake_subqueue(tx_ring->netdev, 1320 tx_ring->queue_index); 1321 ++tx_ring->tx_stats.restart_queue; 1322 } 1323 } 1324 1325 return !!budget; 1326 } 1327 1328 #ifdef CONFIG_IXGBE_DCA 1329 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1330 struct ixgbe_ring *tx_ring, 1331 int cpu) 1332 { 1333 struct ixgbe_hw *hw = &adapter->hw; 1334 u32 txctrl = 0; 1335 u16 reg_offset; 1336 1337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1338 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1339 1340 switch (hw->mac.type) { 1341 case ixgbe_mac_82598EB: 1342 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1343 break; 1344 case ixgbe_mac_82599EB: 1345 case ixgbe_mac_X540: 1346 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1347 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1348 break; 1349 default: 1350 /* for unknown hardware do not write register */ 1351 return; 1352 } 1353 1354 /* 1355 * We can enable relaxed ordering for reads, but not writes when 1356 * DCA is enabled. This is due to a known issue in some chipsets 1357 * which will cause the DCA tag to be cleared. 1358 */ 1359 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1360 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1361 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1362 1363 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1364 } 1365 1366 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1367 struct ixgbe_ring *rx_ring, 1368 int cpu) 1369 { 1370 struct ixgbe_hw *hw = &adapter->hw; 1371 u32 rxctrl = 0; 1372 u8 reg_idx = rx_ring->reg_idx; 1373 1374 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1375 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1376 1377 switch (hw->mac.type) { 1378 case ixgbe_mac_82599EB: 1379 case ixgbe_mac_X540: 1380 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1381 break; 1382 default: 1383 break; 1384 } 1385 1386 /* 1387 * We can enable relaxed ordering for reads, but not writes when 1388 * DCA is enabled. This is due to a known issue in some chipsets 1389 * which will cause the DCA tag to be cleared. 1390 */ 1391 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1392 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1393 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1394 1395 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1396 } 1397 1398 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1399 { 1400 struct ixgbe_adapter *adapter = q_vector->adapter; 1401 struct ixgbe_ring *ring; 1402 int cpu = get_cpu(); 1403 1404 if (q_vector->cpu == cpu) 1405 goto out_no_update; 1406 1407 ixgbe_for_each_ring(ring, q_vector->tx) 1408 ixgbe_update_tx_dca(adapter, ring, cpu); 1409 1410 ixgbe_for_each_ring(ring, q_vector->rx) 1411 ixgbe_update_rx_dca(adapter, ring, cpu); 1412 1413 q_vector->cpu = cpu; 1414 out_no_update: 1415 put_cpu(); 1416 } 1417 1418 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1419 { 1420 int i; 1421 1422 /* always use CB2 mode, difference is masked in the CB driver */ 1423 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1425 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1426 else 1427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1428 IXGBE_DCA_CTRL_DCA_DISABLE); 1429 1430 for (i = 0; i < adapter->num_q_vectors; i++) { 1431 adapter->q_vector[i]->cpu = -1; 1432 ixgbe_update_dca(adapter->q_vector[i]); 1433 } 1434 } 1435 1436 static int __ixgbe_notify_dca(struct device *dev, void *data) 1437 { 1438 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1439 unsigned long event = *(unsigned long *)data; 1440 1441 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1442 return 0; 1443 1444 switch (event) { 1445 case DCA_PROVIDER_ADD: 1446 /* if we're already enabled, don't do it again */ 1447 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1448 break; 1449 if (dca_add_requester(dev) == 0) { 1450 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1452 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1453 break; 1454 } 1455 /* fall through - DCA is disabled. */ 1456 case DCA_PROVIDER_REMOVE: 1457 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1458 dca_remove_requester(dev); 1459 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1461 IXGBE_DCA_CTRL_DCA_DISABLE); 1462 } 1463 break; 1464 } 1465 1466 return 0; 1467 } 1468 1469 #endif /* CONFIG_IXGBE_DCA */ 1470 1471 #define IXGBE_RSS_L4_TYPES_MASK \ 1472 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1473 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1474 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1475 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1476 1477 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1478 union ixgbe_adv_rx_desc *rx_desc, 1479 struct sk_buff *skb) 1480 { 1481 u16 rss_type; 1482 1483 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1484 return; 1485 1486 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1487 IXGBE_RXDADV_RSSTYPE_MASK; 1488 1489 if (!rss_type) 1490 return; 1491 1492 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1493 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1494 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1495 } 1496 1497 #ifdef IXGBE_FCOE 1498 /** 1499 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1500 * @ring: structure containing ring specific data 1501 * @rx_desc: advanced rx descriptor 1502 * 1503 * Returns : true if it is FCoE pkt 1504 */ 1505 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1506 union ixgbe_adv_rx_desc *rx_desc) 1507 { 1508 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1509 1510 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1511 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1512 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1513 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1514 } 1515 1516 #endif /* IXGBE_FCOE */ 1517 /** 1518 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1519 * @ring: structure containing ring specific data 1520 * @rx_desc: current Rx descriptor being processed 1521 * @skb: skb currently being received and modified 1522 **/ 1523 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1524 union ixgbe_adv_rx_desc *rx_desc, 1525 struct sk_buff *skb) 1526 { 1527 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1528 bool encap_pkt = false; 1529 1530 skb_checksum_none_assert(skb); 1531 1532 /* Rx csum disabled */ 1533 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1534 return; 1535 1536 /* check for VXLAN and Geneve packets */ 1537 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1538 encap_pkt = true; 1539 skb->encapsulation = 1; 1540 } 1541 1542 /* if IP and error */ 1543 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1544 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1545 ring->rx_stats.csum_err++; 1546 return; 1547 } 1548 1549 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1550 return; 1551 1552 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1553 /* 1554 * 82599 errata, UDP frames with a 0 checksum can be marked as 1555 * checksum errors. 1556 */ 1557 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1558 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1559 return; 1560 1561 ring->rx_stats.csum_err++; 1562 return; 1563 } 1564 1565 /* It must be a TCP or UDP packet with a valid checksum */ 1566 skb->ip_summed = CHECKSUM_UNNECESSARY; 1567 if (encap_pkt) { 1568 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1569 return; 1570 1571 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1572 skb->ip_summed = CHECKSUM_NONE; 1573 return; 1574 } 1575 /* If we checked the outer header let the stack know */ 1576 skb->csum_level = 1; 1577 } 1578 } 1579 1580 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1581 { 1582 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1583 } 1584 1585 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1586 struct ixgbe_rx_buffer *bi) 1587 { 1588 struct page *page = bi->page; 1589 dma_addr_t dma; 1590 1591 /* since we are recycling buffers we should seldom need to alloc */ 1592 if (likely(page)) 1593 return true; 1594 1595 /* alloc new page for storage */ 1596 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1597 if (unlikely(!page)) { 1598 rx_ring->rx_stats.alloc_rx_page_failed++; 1599 return false; 1600 } 1601 1602 /* map page for use */ 1603 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1604 ixgbe_rx_pg_size(rx_ring), 1605 DMA_FROM_DEVICE, 1606 IXGBE_RX_DMA_ATTR); 1607 1608 /* 1609 * if mapping failed free memory back to system since 1610 * there isn't much point in holding memory we can't use 1611 */ 1612 if (dma_mapping_error(rx_ring->dev, dma)) { 1613 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1614 1615 rx_ring->rx_stats.alloc_rx_page_failed++; 1616 return false; 1617 } 1618 1619 bi->dma = dma; 1620 bi->page = page; 1621 bi->page_offset = ixgbe_rx_offset(rx_ring); 1622 bi->pagecnt_bias = 1; 1623 rx_ring->rx_stats.alloc_rx_page++; 1624 1625 return true; 1626 } 1627 1628 /** 1629 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1630 * @rx_ring: ring to place buffers on 1631 * @cleaned_count: number of buffers to replace 1632 **/ 1633 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1634 { 1635 union ixgbe_adv_rx_desc *rx_desc; 1636 struct ixgbe_rx_buffer *bi; 1637 u16 i = rx_ring->next_to_use; 1638 u16 bufsz; 1639 1640 /* nothing to do */ 1641 if (!cleaned_count) 1642 return; 1643 1644 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1645 bi = &rx_ring->rx_buffer_info[i]; 1646 i -= rx_ring->count; 1647 1648 bufsz = ixgbe_rx_bufsz(rx_ring); 1649 1650 do { 1651 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1652 break; 1653 1654 /* sync the buffer for use by the device */ 1655 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1656 bi->page_offset, bufsz, 1657 DMA_FROM_DEVICE); 1658 1659 /* 1660 * Refresh the desc even if buffer_addrs didn't change 1661 * because each write-back erases this info. 1662 */ 1663 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1664 1665 rx_desc++; 1666 bi++; 1667 i++; 1668 if (unlikely(!i)) { 1669 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1670 bi = rx_ring->rx_buffer_info; 1671 i -= rx_ring->count; 1672 } 1673 1674 /* clear the length for the next_to_use descriptor */ 1675 rx_desc->wb.upper.length = 0; 1676 1677 cleaned_count--; 1678 } while (cleaned_count); 1679 1680 i += rx_ring->count; 1681 1682 if (rx_ring->next_to_use != i) { 1683 rx_ring->next_to_use = i; 1684 1685 /* update next to alloc since we have filled the ring */ 1686 rx_ring->next_to_alloc = i; 1687 1688 /* Force memory writes to complete before letting h/w 1689 * know there are new descriptors to fetch. (Only 1690 * applicable for weak-ordered memory model archs, 1691 * such as IA-64). 1692 */ 1693 wmb(); 1694 writel(i, rx_ring->tail); 1695 } 1696 } 1697 1698 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1699 struct sk_buff *skb) 1700 { 1701 u16 hdr_len = skb_headlen(skb); 1702 1703 /* set gso_size to avoid messing up TCP MSS */ 1704 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1705 IXGBE_CB(skb)->append_cnt); 1706 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1707 } 1708 1709 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1710 struct sk_buff *skb) 1711 { 1712 /* if append_cnt is 0 then frame is not RSC */ 1713 if (!IXGBE_CB(skb)->append_cnt) 1714 return; 1715 1716 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1717 rx_ring->rx_stats.rsc_flush++; 1718 1719 ixgbe_set_rsc_gso_size(rx_ring, skb); 1720 1721 /* gso_size is computed using append_cnt so always clear it last */ 1722 IXGBE_CB(skb)->append_cnt = 0; 1723 } 1724 1725 /** 1726 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1727 * @rx_ring: rx descriptor ring packet is being transacted on 1728 * @rx_desc: pointer to the EOP Rx descriptor 1729 * @skb: pointer to current skb being populated 1730 * 1731 * This function checks the ring, descriptor, and packet information in 1732 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1733 * other fields within the skb. 1734 **/ 1735 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1736 union ixgbe_adv_rx_desc *rx_desc, 1737 struct sk_buff *skb) 1738 { 1739 struct net_device *dev = rx_ring->netdev; 1740 u32 flags = rx_ring->q_vector->adapter->flags; 1741 1742 ixgbe_update_rsc_stats(rx_ring, skb); 1743 1744 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1745 1746 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1747 1748 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1749 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1750 1751 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1752 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1753 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1754 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1755 } 1756 1757 skb_record_rx_queue(skb, rx_ring->queue_index); 1758 1759 skb->protocol = eth_type_trans(skb, dev); 1760 } 1761 1762 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1763 struct sk_buff *skb) 1764 { 1765 napi_gro_receive(&q_vector->napi, skb); 1766 } 1767 1768 /** 1769 * ixgbe_is_non_eop - process handling of non-EOP buffers 1770 * @rx_ring: Rx ring being processed 1771 * @rx_desc: Rx descriptor for current buffer 1772 * @skb: Current socket buffer containing buffer in progress 1773 * 1774 * This function updates next to clean. If the buffer is an EOP buffer 1775 * this function exits returning false, otherwise it will place the 1776 * sk_buff in the next buffer to be chained and return true indicating 1777 * that this is in fact a non-EOP buffer. 1778 **/ 1779 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1780 union ixgbe_adv_rx_desc *rx_desc, 1781 struct sk_buff *skb) 1782 { 1783 u32 ntc = rx_ring->next_to_clean + 1; 1784 1785 /* fetch, update, and store next to clean */ 1786 ntc = (ntc < rx_ring->count) ? ntc : 0; 1787 rx_ring->next_to_clean = ntc; 1788 1789 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1790 1791 /* update RSC append count if present */ 1792 if (ring_is_rsc_enabled(rx_ring)) { 1793 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1794 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1795 1796 if (unlikely(rsc_enabled)) { 1797 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1798 1799 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1800 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1801 1802 /* update ntc based on RSC value */ 1803 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1804 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1805 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1806 } 1807 } 1808 1809 /* if we are the last buffer then there is nothing else to do */ 1810 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1811 return false; 1812 1813 /* place skb in next buffer to be received */ 1814 rx_ring->rx_buffer_info[ntc].skb = skb; 1815 rx_ring->rx_stats.non_eop_descs++; 1816 1817 return true; 1818 } 1819 1820 /** 1821 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1822 * @rx_ring: rx descriptor ring packet is being transacted on 1823 * @skb: pointer to current skb being adjusted 1824 * 1825 * This function is an ixgbe specific version of __pskb_pull_tail. The 1826 * main difference between this version and the original function is that 1827 * this function can make several assumptions about the state of things 1828 * that allow for significant optimizations versus the standard function. 1829 * As a result we can do things like drop a frag and maintain an accurate 1830 * truesize for the skb. 1831 */ 1832 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1833 struct sk_buff *skb) 1834 { 1835 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1836 unsigned char *va; 1837 unsigned int pull_len; 1838 1839 /* 1840 * it is valid to use page_address instead of kmap since we are 1841 * working with pages allocated out of the lomem pool per 1842 * alloc_page(GFP_ATOMIC) 1843 */ 1844 va = skb_frag_address(frag); 1845 1846 /* 1847 * we need the header to contain the greater of either ETH_HLEN or 1848 * 60 bytes if the skb->len is less than 60 for skb_pad. 1849 */ 1850 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1851 1852 /* align pull length to size of long to optimize memcpy performance */ 1853 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1854 1855 /* update all of the pointers */ 1856 skb_frag_size_sub(frag, pull_len); 1857 frag->page_offset += pull_len; 1858 skb->data_len -= pull_len; 1859 skb->tail += pull_len; 1860 } 1861 1862 /** 1863 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1864 * @rx_ring: rx descriptor ring packet is being transacted on 1865 * @skb: pointer to current skb being updated 1866 * 1867 * This function provides a basic DMA sync up for the first fragment of an 1868 * skb. The reason for doing this is that the first fragment cannot be 1869 * unmapped until we have reached the end of packet descriptor for a buffer 1870 * chain. 1871 */ 1872 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1873 struct sk_buff *skb) 1874 { 1875 /* if the page was released unmap it, else just sync our portion */ 1876 if (unlikely(IXGBE_CB(skb)->page_released)) { 1877 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1878 ixgbe_rx_pg_size(rx_ring), 1879 DMA_FROM_DEVICE, 1880 IXGBE_RX_DMA_ATTR); 1881 } else { 1882 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1883 1884 dma_sync_single_range_for_cpu(rx_ring->dev, 1885 IXGBE_CB(skb)->dma, 1886 frag->page_offset, 1887 skb_frag_size(frag), 1888 DMA_FROM_DEVICE); 1889 } 1890 } 1891 1892 /** 1893 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1894 * @rx_ring: rx descriptor ring packet is being transacted on 1895 * @rx_desc: pointer to the EOP Rx descriptor 1896 * @skb: pointer to current skb being fixed 1897 * 1898 * Check if the skb is valid in the XDP case it will be an error pointer. 1899 * Return true in this case to abort processing and advance to next 1900 * descriptor. 1901 * 1902 * Check for corrupted packet headers caused by senders on the local L2 1903 * embedded NIC switch not setting up their Tx Descriptors right. These 1904 * should be very rare. 1905 * 1906 * Also address the case where we are pulling data in on pages only 1907 * and as such no data is present in the skb header. 1908 * 1909 * In addition if skb is not at least 60 bytes we need to pad it so that 1910 * it is large enough to qualify as a valid Ethernet frame. 1911 * 1912 * Returns true if an error was encountered and skb was freed. 1913 **/ 1914 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1915 union ixgbe_adv_rx_desc *rx_desc, 1916 struct sk_buff *skb) 1917 { 1918 struct net_device *netdev = rx_ring->netdev; 1919 1920 /* XDP packets use error pointer so abort at this point */ 1921 if (IS_ERR(skb)) 1922 return true; 1923 1924 /* verify that the packet does not have any known errors */ 1925 if (unlikely(ixgbe_test_staterr(rx_desc, 1926 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1927 !(netdev->features & NETIF_F_RXALL))) { 1928 dev_kfree_skb_any(skb); 1929 return true; 1930 } 1931 1932 /* place header in linear portion of buffer */ 1933 if (!skb_headlen(skb)) 1934 ixgbe_pull_tail(rx_ring, skb); 1935 1936 #ifdef IXGBE_FCOE 1937 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1938 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1939 return false; 1940 1941 #endif 1942 /* if eth_skb_pad returns an error the skb was freed */ 1943 if (eth_skb_pad(skb)) 1944 return true; 1945 1946 return false; 1947 } 1948 1949 /** 1950 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1951 * @rx_ring: rx descriptor ring to store buffers on 1952 * @old_buff: donor buffer to have page reused 1953 * 1954 * Synchronizes page for reuse by the adapter 1955 **/ 1956 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1957 struct ixgbe_rx_buffer *old_buff) 1958 { 1959 struct ixgbe_rx_buffer *new_buff; 1960 u16 nta = rx_ring->next_to_alloc; 1961 1962 new_buff = &rx_ring->rx_buffer_info[nta]; 1963 1964 /* update, and store next to alloc */ 1965 nta++; 1966 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1967 1968 /* Transfer page from old buffer to new buffer. 1969 * Move each member individually to avoid possible store 1970 * forwarding stalls and unnecessary copy of skb. 1971 */ 1972 new_buff->dma = old_buff->dma; 1973 new_buff->page = old_buff->page; 1974 new_buff->page_offset = old_buff->page_offset; 1975 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1976 } 1977 1978 static inline bool ixgbe_page_is_reserved(struct page *page) 1979 { 1980 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1981 } 1982 1983 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1984 { 1985 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1986 struct page *page = rx_buffer->page; 1987 1988 /* avoid re-using remote pages */ 1989 if (unlikely(ixgbe_page_is_reserved(page))) 1990 return false; 1991 1992 #if (PAGE_SIZE < 8192) 1993 /* if we are only owner of page we can reuse it */ 1994 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1995 return false; 1996 #else 1997 /* The last offset is a bit aggressive in that we assume the 1998 * worst case of FCoE being enabled and using a 3K buffer. 1999 * However this should have minimal impact as the 1K extra is 2000 * still less than one buffer in size. 2001 */ 2002 #define IXGBE_LAST_OFFSET \ 2003 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2004 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2005 return false; 2006 #endif 2007 2008 /* If we have drained the page fragment pool we need to update 2009 * the pagecnt_bias and page count so that we fully restock the 2010 * number of references the driver holds. 2011 */ 2012 if (unlikely(!pagecnt_bias)) { 2013 page_ref_add(page, USHRT_MAX); 2014 rx_buffer->pagecnt_bias = USHRT_MAX; 2015 } 2016 2017 return true; 2018 } 2019 2020 /** 2021 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2022 * @rx_ring: rx descriptor ring to transact packets on 2023 * @rx_buffer: buffer containing page to add 2024 * @rx_desc: descriptor containing length of buffer written by hardware 2025 * @skb: sk_buff to place the data into 2026 * 2027 * This function will add the data contained in rx_buffer->page to the skb. 2028 * This is done either through a direct copy if the data in the buffer is 2029 * less than the skb header size, otherwise it will just attach the page as 2030 * a frag to the skb. 2031 * 2032 * The function will then update the page offset if necessary and return 2033 * true if the buffer can be reused by the adapter. 2034 **/ 2035 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2036 struct ixgbe_rx_buffer *rx_buffer, 2037 struct sk_buff *skb, 2038 unsigned int size) 2039 { 2040 #if (PAGE_SIZE < 8192) 2041 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2042 #else 2043 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2044 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2045 SKB_DATA_ALIGN(size); 2046 #endif 2047 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2048 rx_buffer->page_offset, size, truesize); 2049 #if (PAGE_SIZE < 8192) 2050 rx_buffer->page_offset ^= truesize; 2051 #else 2052 rx_buffer->page_offset += truesize; 2053 #endif 2054 } 2055 2056 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2057 union ixgbe_adv_rx_desc *rx_desc, 2058 struct sk_buff **skb, 2059 const unsigned int size) 2060 { 2061 struct ixgbe_rx_buffer *rx_buffer; 2062 2063 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2064 prefetchw(rx_buffer->page); 2065 *skb = rx_buffer->skb; 2066 2067 /* Delay unmapping of the first packet. It carries the header 2068 * information, HW may still access the header after the writeback. 2069 * Only unmap it when EOP is reached 2070 */ 2071 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2072 if (!*skb) 2073 goto skip_sync; 2074 } else { 2075 if (*skb) 2076 ixgbe_dma_sync_frag(rx_ring, *skb); 2077 } 2078 2079 /* we are reusing so sync this buffer for CPU use */ 2080 dma_sync_single_range_for_cpu(rx_ring->dev, 2081 rx_buffer->dma, 2082 rx_buffer->page_offset, 2083 size, 2084 DMA_FROM_DEVICE); 2085 skip_sync: 2086 rx_buffer->pagecnt_bias--; 2087 2088 return rx_buffer; 2089 } 2090 2091 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2092 struct ixgbe_rx_buffer *rx_buffer, 2093 struct sk_buff *skb) 2094 { 2095 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2096 /* hand second half of page back to the ring */ 2097 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2098 } else { 2099 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2100 /* the page has been released from the ring */ 2101 IXGBE_CB(skb)->page_released = true; 2102 } else { 2103 /* we are not reusing the buffer so unmap it */ 2104 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2105 ixgbe_rx_pg_size(rx_ring), 2106 DMA_FROM_DEVICE, 2107 IXGBE_RX_DMA_ATTR); 2108 } 2109 __page_frag_cache_drain(rx_buffer->page, 2110 rx_buffer->pagecnt_bias); 2111 } 2112 2113 /* clear contents of rx_buffer */ 2114 rx_buffer->page = NULL; 2115 rx_buffer->skb = NULL; 2116 } 2117 2118 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2119 struct ixgbe_rx_buffer *rx_buffer, 2120 struct xdp_buff *xdp, 2121 union ixgbe_adv_rx_desc *rx_desc) 2122 { 2123 unsigned int size = xdp->data_end - xdp->data; 2124 #if (PAGE_SIZE < 8192) 2125 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2126 #else 2127 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2128 xdp->data_hard_start); 2129 #endif 2130 struct sk_buff *skb; 2131 2132 /* prefetch first cache line of first page */ 2133 prefetch(xdp->data); 2134 #if L1_CACHE_BYTES < 128 2135 prefetch(xdp->data + L1_CACHE_BYTES); 2136 #endif 2137 /* Note, we get here by enabling legacy-rx via: 2138 * 2139 * ethtool --set-priv-flags <dev> legacy-rx on 2140 * 2141 * In this mode, we currently get 0 extra XDP headroom as 2142 * opposed to having legacy-rx off, where we process XDP 2143 * packets going to stack via ixgbe_build_skb(). The latter 2144 * provides us currently with 192 bytes of headroom. 2145 * 2146 * For ixgbe_construct_skb() mode it means that the 2147 * xdp->data_meta will always point to xdp->data, since 2148 * the helper cannot expand the head. Should this ever 2149 * change in future for legacy-rx mode on, then lets also 2150 * add xdp->data_meta handling here. 2151 */ 2152 2153 /* allocate a skb to store the frags */ 2154 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2155 if (unlikely(!skb)) 2156 return NULL; 2157 2158 if (size > IXGBE_RX_HDR_SIZE) { 2159 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2160 IXGBE_CB(skb)->dma = rx_buffer->dma; 2161 2162 skb_add_rx_frag(skb, 0, rx_buffer->page, 2163 xdp->data - page_address(rx_buffer->page), 2164 size, truesize); 2165 #if (PAGE_SIZE < 8192) 2166 rx_buffer->page_offset ^= truesize; 2167 #else 2168 rx_buffer->page_offset += truesize; 2169 #endif 2170 } else { 2171 memcpy(__skb_put(skb, size), 2172 xdp->data, ALIGN(size, sizeof(long))); 2173 rx_buffer->pagecnt_bias++; 2174 } 2175 2176 return skb; 2177 } 2178 2179 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2180 struct ixgbe_rx_buffer *rx_buffer, 2181 struct xdp_buff *xdp, 2182 union ixgbe_adv_rx_desc *rx_desc) 2183 { 2184 unsigned int metasize = xdp->data - xdp->data_meta; 2185 #if (PAGE_SIZE < 8192) 2186 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2187 #else 2188 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2189 SKB_DATA_ALIGN(xdp->data_end - 2190 xdp->data_hard_start); 2191 #endif 2192 struct sk_buff *skb; 2193 2194 /* Prefetch first cache line of first page. If xdp->data_meta 2195 * is unused, this points extactly as xdp->data, otherwise we 2196 * likely have a consumer accessing first few bytes of meta 2197 * data, and then actual data. 2198 */ 2199 prefetch(xdp->data_meta); 2200 #if L1_CACHE_BYTES < 128 2201 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2202 #endif 2203 2204 /* build an skb to around the page buffer */ 2205 skb = build_skb(xdp->data_hard_start, truesize); 2206 if (unlikely(!skb)) 2207 return NULL; 2208 2209 /* update pointers within the skb to store the data */ 2210 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2211 __skb_put(skb, xdp->data_end - xdp->data); 2212 if (metasize) 2213 skb_metadata_set(skb, metasize); 2214 2215 /* record DMA address if this is the start of a chain of buffers */ 2216 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2217 IXGBE_CB(skb)->dma = rx_buffer->dma; 2218 2219 /* update buffer offset */ 2220 #if (PAGE_SIZE < 8192) 2221 rx_buffer->page_offset ^= truesize; 2222 #else 2223 rx_buffer->page_offset += truesize; 2224 #endif 2225 2226 return skb; 2227 } 2228 2229 #define IXGBE_XDP_PASS 0 2230 #define IXGBE_XDP_CONSUMED 1 2231 #define IXGBE_XDP_TX 2 2232 2233 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2234 struct xdp_buff *xdp); 2235 2236 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2237 struct ixgbe_ring *rx_ring, 2238 struct xdp_buff *xdp) 2239 { 2240 int err, result = IXGBE_XDP_PASS; 2241 struct bpf_prog *xdp_prog; 2242 u32 act; 2243 2244 rcu_read_lock(); 2245 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2246 2247 if (!xdp_prog) 2248 goto xdp_out; 2249 2250 act = bpf_prog_run_xdp(xdp_prog, xdp); 2251 switch (act) { 2252 case XDP_PASS: 2253 break; 2254 case XDP_TX: 2255 result = ixgbe_xmit_xdp_ring(adapter, xdp); 2256 break; 2257 case XDP_REDIRECT: 2258 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2259 if (!err) 2260 result = IXGBE_XDP_TX; 2261 else 2262 result = IXGBE_XDP_CONSUMED; 2263 break; 2264 default: 2265 bpf_warn_invalid_xdp_action(act); 2266 /* fallthrough */ 2267 case XDP_ABORTED: 2268 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2269 /* fallthrough -- handle aborts by dropping packet */ 2270 case XDP_DROP: 2271 result = IXGBE_XDP_CONSUMED; 2272 break; 2273 } 2274 xdp_out: 2275 rcu_read_unlock(); 2276 return ERR_PTR(-result); 2277 } 2278 2279 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2280 struct ixgbe_rx_buffer *rx_buffer, 2281 unsigned int size) 2282 { 2283 #if (PAGE_SIZE < 8192) 2284 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2285 2286 rx_buffer->page_offset ^= truesize; 2287 #else 2288 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2289 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2290 SKB_DATA_ALIGN(size); 2291 2292 rx_buffer->page_offset += truesize; 2293 #endif 2294 } 2295 2296 /** 2297 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2298 * @q_vector: structure containing interrupt and ring information 2299 * @rx_ring: rx descriptor ring to transact packets on 2300 * @budget: Total limit on number of packets to process 2301 * 2302 * This function provides a "bounce buffer" approach to Rx interrupt 2303 * processing. The advantage to this is that on systems that have 2304 * expensive overhead for IOMMU access this provides a means of avoiding 2305 * it by maintaining the mapping of the page to the syste. 2306 * 2307 * Returns amount of work completed 2308 **/ 2309 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2310 struct ixgbe_ring *rx_ring, 2311 const int budget) 2312 { 2313 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2314 struct ixgbe_adapter *adapter = q_vector->adapter; 2315 #ifdef IXGBE_FCOE 2316 int ddp_bytes; 2317 unsigned int mss = 0; 2318 #endif /* IXGBE_FCOE */ 2319 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2320 bool xdp_xmit = false; 2321 struct xdp_buff xdp; 2322 2323 xdp.rxq = &rx_ring->xdp_rxq; 2324 2325 while (likely(total_rx_packets < budget)) { 2326 union ixgbe_adv_rx_desc *rx_desc; 2327 struct ixgbe_rx_buffer *rx_buffer; 2328 struct sk_buff *skb; 2329 unsigned int size; 2330 2331 /* return some buffers to hardware, one at a time is too slow */ 2332 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2333 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2334 cleaned_count = 0; 2335 } 2336 2337 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2338 size = le16_to_cpu(rx_desc->wb.upper.length); 2339 if (!size) 2340 break; 2341 2342 /* This memory barrier is needed to keep us from reading 2343 * any other fields out of the rx_desc until we know the 2344 * descriptor has been written back 2345 */ 2346 dma_rmb(); 2347 2348 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2349 2350 /* retrieve a buffer from the ring */ 2351 if (!skb) { 2352 xdp.data = page_address(rx_buffer->page) + 2353 rx_buffer->page_offset; 2354 xdp.data_meta = xdp.data; 2355 xdp.data_hard_start = xdp.data - 2356 ixgbe_rx_offset(rx_ring); 2357 xdp.data_end = xdp.data + size; 2358 2359 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2360 } 2361 2362 if (IS_ERR(skb)) { 2363 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2364 xdp_xmit = true; 2365 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2366 } else { 2367 rx_buffer->pagecnt_bias++; 2368 } 2369 total_rx_packets++; 2370 total_rx_bytes += size; 2371 } else if (skb) { 2372 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2373 } else if (ring_uses_build_skb(rx_ring)) { 2374 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2375 &xdp, rx_desc); 2376 } else { 2377 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2378 &xdp, rx_desc); 2379 } 2380 2381 /* exit if we failed to retrieve a buffer */ 2382 if (!skb) { 2383 rx_ring->rx_stats.alloc_rx_buff_failed++; 2384 rx_buffer->pagecnt_bias++; 2385 break; 2386 } 2387 2388 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2389 cleaned_count++; 2390 2391 /* place incomplete frames back on ring for completion */ 2392 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2393 continue; 2394 2395 /* verify the packet layout is correct */ 2396 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2397 continue; 2398 2399 /* probably a little skewed due to removing CRC */ 2400 total_rx_bytes += skb->len; 2401 2402 /* populate checksum, timestamp, VLAN, and protocol */ 2403 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2404 2405 #ifdef IXGBE_FCOE 2406 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2407 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2408 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2409 /* include DDPed FCoE data */ 2410 if (ddp_bytes > 0) { 2411 if (!mss) { 2412 mss = rx_ring->netdev->mtu - 2413 sizeof(struct fcoe_hdr) - 2414 sizeof(struct fc_frame_header) - 2415 sizeof(struct fcoe_crc_eof); 2416 if (mss > 512) 2417 mss &= ~511; 2418 } 2419 total_rx_bytes += ddp_bytes; 2420 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2421 mss); 2422 } 2423 if (!ddp_bytes) { 2424 dev_kfree_skb_any(skb); 2425 continue; 2426 } 2427 } 2428 2429 #endif /* IXGBE_FCOE */ 2430 ixgbe_rx_skb(q_vector, skb); 2431 2432 /* update budget accounting */ 2433 total_rx_packets++; 2434 } 2435 2436 if (xdp_xmit) { 2437 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2438 2439 /* Force memory writes to complete before letting h/w 2440 * know there are new descriptors to fetch. 2441 */ 2442 wmb(); 2443 writel(ring->next_to_use, ring->tail); 2444 2445 xdp_do_flush_map(); 2446 } 2447 2448 u64_stats_update_begin(&rx_ring->syncp); 2449 rx_ring->stats.packets += total_rx_packets; 2450 rx_ring->stats.bytes += total_rx_bytes; 2451 u64_stats_update_end(&rx_ring->syncp); 2452 q_vector->rx.total_packets += total_rx_packets; 2453 q_vector->rx.total_bytes += total_rx_bytes; 2454 2455 return total_rx_packets; 2456 } 2457 2458 /** 2459 * ixgbe_configure_msix - Configure MSI-X hardware 2460 * @adapter: board private structure 2461 * 2462 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2463 * interrupts. 2464 **/ 2465 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2466 { 2467 struct ixgbe_q_vector *q_vector; 2468 int v_idx; 2469 u32 mask; 2470 2471 /* Populate MSIX to EITR Select */ 2472 if (adapter->num_vfs > 32) { 2473 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2475 } 2476 2477 /* 2478 * Populate the IVAR table and set the ITR values to the 2479 * corresponding register. 2480 */ 2481 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2482 struct ixgbe_ring *ring; 2483 q_vector = adapter->q_vector[v_idx]; 2484 2485 ixgbe_for_each_ring(ring, q_vector->rx) 2486 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2487 2488 ixgbe_for_each_ring(ring, q_vector->tx) 2489 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2490 2491 ixgbe_write_eitr(q_vector); 2492 } 2493 2494 switch (adapter->hw.mac.type) { 2495 case ixgbe_mac_82598EB: 2496 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2497 v_idx); 2498 break; 2499 case ixgbe_mac_82599EB: 2500 case ixgbe_mac_X540: 2501 case ixgbe_mac_X550: 2502 case ixgbe_mac_X550EM_x: 2503 case ixgbe_mac_x550em_a: 2504 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2505 break; 2506 default: 2507 break; 2508 } 2509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2510 2511 /* set up to autoclear timer, and the vectors */ 2512 mask = IXGBE_EIMS_ENABLE_MASK; 2513 mask &= ~(IXGBE_EIMS_OTHER | 2514 IXGBE_EIMS_MAILBOX | 2515 IXGBE_EIMS_LSC); 2516 2517 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2518 } 2519 2520 enum latency_range { 2521 lowest_latency = 0, 2522 low_latency = 1, 2523 bulk_latency = 2, 2524 latency_invalid = 255 2525 }; 2526 2527 /** 2528 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2529 * @q_vector: structure containing interrupt and ring information 2530 * @ring_container: structure containing ring performance data 2531 * 2532 * Stores a new ITR value based on packets and byte 2533 * counts during the last interrupt. The advantage of per interrupt 2534 * computation is faster updates and more accurate ITR for the current 2535 * traffic pattern. Constants in this function were computed 2536 * based on theoretical maximum wire speed and thresholds were set based 2537 * on testing data as well as attempting to minimize response time 2538 * while increasing bulk throughput. 2539 * this functionality is controlled by the InterruptThrottleRate module 2540 * parameter (see ixgbe_param.c) 2541 **/ 2542 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2543 struct ixgbe_ring_container *ring_container) 2544 { 2545 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2546 IXGBE_ITR_ADAPTIVE_LATENCY; 2547 unsigned int avg_wire_size, packets, bytes; 2548 unsigned long next_update = jiffies; 2549 2550 /* If we don't have any rings just leave ourselves set for maximum 2551 * possible latency so we take ourselves out of the equation. 2552 */ 2553 if (!ring_container->ring) 2554 return; 2555 2556 /* If we didn't update within up to 1 - 2 jiffies we can assume 2557 * that either packets are coming in so slow there hasn't been 2558 * any work, or that there is so much work that NAPI is dealing 2559 * with interrupt moderation and we don't need to do anything. 2560 */ 2561 if (time_after(next_update, ring_container->next_update)) 2562 goto clear_counts; 2563 2564 packets = ring_container->total_packets; 2565 2566 /* We have no packets to actually measure against. This means 2567 * either one of the other queues on this vector is active or 2568 * we are a Tx queue doing TSO with too high of an interrupt rate. 2569 * 2570 * When this occurs just tick up our delay by the minimum value 2571 * and hope that this extra delay will prevent us from being called 2572 * without any work on our queue. 2573 */ 2574 if (!packets) { 2575 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2576 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2577 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2578 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2579 goto clear_counts; 2580 } 2581 2582 bytes = ring_container->total_bytes; 2583 2584 /* If packets are less than 4 or bytes are less than 9000 assume 2585 * insufficient data to use bulk rate limiting approach. We are 2586 * likely latency driven. 2587 */ 2588 if (packets < 4 && bytes < 9000) { 2589 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2590 goto adjust_by_size; 2591 } 2592 2593 /* Between 4 and 48 we can assume that our current interrupt delay 2594 * is only slightly too low. As such we should increase it by a small 2595 * fixed amount. 2596 */ 2597 if (packets < 48) { 2598 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2599 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2600 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2601 goto clear_counts; 2602 } 2603 2604 /* Between 48 and 96 is our "goldilocks" zone where we are working 2605 * out "just right". Just report that our current ITR is good for us. 2606 */ 2607 if (packets < 96) { 2608 itr = q_vector->itr >> 2; 2609 goto clear_counts; 2610 } 2611 2612 /* If packet count is 96 or greater we are likely looking at a slight 2613 * overrun of the delay we want. Try halving our delay to see if that 2614 * will cut the number of packets in half per interrupt. 2615 */ 2616 if (packets < 256) { 2617 itr = q_vector->itr >> 3; 2618 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2619 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2620 goto clear_counts; 2621 } 2622 2623 /* The paths below assume we are dealing with a bulk ITR since number 2624 * of packets is 256 or greater. We are just going to have to compute 2625 * a value and try to bring the count under control, though for smaller 2626 * packet sizes there isn't much we can do as NAPI polling will likely 2627 * be kicking in sooner rather than later. 2628 */ 2629 itr = IXGBE_ITR_ADAPTIVE_BULK; 2630 2631 adjust_by_size: 2632 /* If packet counts are 256 or greater we can assume we have a gross 2633 * overestimation of what the rate should be. Instead of trying to fine 2634 * tune it just use the formula below to try and dial in an exact value 2635 * give the current packet size of the frame. 2636 */ 2637 avg_wire_size = bytes / packets; 2638 2639 /* The following is a crude approximation of: 2640 * wmem_default / (size + overhead) = desired_pkts_per_int 2641 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2642 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2643 * 2644 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2645 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2646 * formula down to 2647 * 2648 * (170 * (size + 24)) / (size + 640) = ITR 2649 * 2650 * We first do some math on the packet size and then finally bitshift 2651 * by 8 after rounding up. We also have to account for PCIe link speed 2652 * difference as ITR scales based on this. 2653 */ 2654 if (avg_wire_size <= 60) { 2655 /* Start at 50k ints/sec */ 2656 avg_wire_size = 5120; 2657 } else if (avg_wire_size <= 316) { 2658 /* 50K ints/sec to 16K ints/sec */ 2659 avg_wire_size *= 40; 2660 avg_wire_size += 2720; 2661 } else if (avg_wire_size <= 1084) { 2662 /* 16K ints/sec to 9.2K ints/sec */ 2663 avg_wire_size *= 15; 2664 avg_wire_size += 11452; 2665 } else if (avg_wire_size <= 1980) { 2666 /* 9.2K ints/sec to 8K ints/sec */ 2667 avg_wire_size *= 5; 2668 avg_wire_size += 22420; 2669 } else { 2670 /* plateau at a limit of 8K ints/sec */ 2671 avg_wire_size = 32256; 2672 } 2673 2674 /* If we are in low latency mode half our delay which doubles the rate 2675 * to somewhere between 100K to 16K ints/sec 2676 */ 2677 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2678 avg_wire_size >>= 1; 2679 2680 /* Resultant value is 256 times larger than it needs to be. This 2681 * gives us room to adjust the value as needed to either increase 2682 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2683 * 2684 * Use addition as we have already recorded the new latency flag 2685 * for the ITR value. 2686 */ 2687 switch (q_vector->adapter->link_speed) { 2688 case IXGBE_LINK_SPEED_10GB_FULL: 2689 case IXGBE_LINK_SPEED_100_FULL: 2690 default: 2691 itr += DIV_ROUND_UP(avg_wire_size, 2692 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2693 IXGBE_ITR_ADAPTIVE_MIN_INC; 2694 break; 2695 case IXGBE_LINK_SPEED_2_5GB_FULL: 2696 case IXGBE_LINK_SPEED_1GB_FULL: 2697 case IXGBE_LINK_SPEED_10_FULL: 2698 itr += DIV_ROUND_UP(avg_wire_size, 2699 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2700 IXGBE_ITR_ADAPTIVE_MIN_INC; 2701 break; 2702 } 2703 2704 clear_counts: 2705 /* write back value */ 2706 ring_container->itr = itr; 2707 2708 /* next update should occur within next jiffy */ 2709 ring_container->next_update = next_update + 1; 2710 2711 ring_container->total_bytes = 0; 2712 ring_container->total_packets = 0; 2713 } 2714 2715 /** 2716 * ixgbe_write_eitr - write EITR register in hardware specific way 2717 * @q_vector: structure containing interrupt and ring information 2718 * 2719 * This function is made to be called by ethtool and by the driver 2720 * when it needs to update EITR registers at runtime. Hardware 2721 * specific quirks/differences are taken care of here. 2722 */ 2723 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2724 { 2725 struct ixgbe_adapter *adapter = q_vector->adapter; 2726 struct ixgbe_hw *hw = &adapter->hw; 2727 int v_idx = q_vector->v_idx; 2728 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2729 2730 switch (adapter->hw.mac.type) { 2731 case ixgbe_mac_82598EB: 2732 /* must write high and low 16 bits to reset counter */ 2733 itr_reg |= (itr_reg << 16); 2734 break; 2735 case ixgbe_mac_82599EB: 2736 case ixgbe_mac_X540: 2737 case ixgbe_mac_X550: 2738 case ixgbe_mac_X550EM_x: 2739 case ixgbe_mac_x550em_a: 2740 /* 2741 * set the WDIS bit to not clear the timer bits and cause an 2742 * immediate assertion of the interrupt 2743 */ 2744 itr_reg |= IXGBE_EITR_CNT_WDIS; 2745 break; 2746 default: 2747 break; 2748 } 2749 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2750 } 2751 2752 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2753 { 2754 u32 new_itr; 2755 2756 ixgbe_update_itr(q_vector, &q_vector->tx); 2757 ixgbe_update_itr(q_vector, &q_vector->rx); 2758 2759 /* use the smallest value of new ITR delay calculations */ 2760 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2761 2762 /* Clear latency flag if set, shift into correct position */ 2763 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2764 new_itr <<= 2; 2765 2766 if (new_itr != q_vector->itr) { 2767 /* save the algorithm value here */ 2768 q_vector->itr = new_itr; 2769 2770 ixgbe_write_eitr(q_vector); 2771 } 2772 } 2773 2774 /** 2775 * ixgbe_check_overtemp_subtask - check for over temperature 2776 * @adapter: pointer to adapter 2777 **/ 2778 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2779 { 2780 struct ixgbe_hw *hw = &adapter->hw; 2781 u32 eicr = adapter->interrupt_event; 2782 s32 rc; 2783 2784 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2785 return; 2786 2787 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2788 return; 2789 2790 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2791 2792 switch (hw->device_id) { 2793 case IXGBE_DEV_ID_82599_T3_LOM: 2794 /* 2795 * Since the warning interrupt is for both ports 2796 * we don't have to check if: 2797 * - This interrupt wasn't for our port. 2798 * - We may have missed the interrupt so always have to 2799 * check if we got a LSC 2800 */ 2801 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2802 !(eicr & IXGBE_EICR_LSC)) 2803 return; 2804 2805 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2806 u32 speed; 2807 bool link_up = false; 2808 2809 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2810 2811 if (link_up) 2812 return; 2813 } 2814 2815 /* Check if this is not due to overtemp */ 2816 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2817 return; 2818 2819 break; 2820 case IXGBE_DEV_ID_X550EM_A_1G_T: 2821 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2822 rc = hw->phy.ops.check_overtemp(hw); 2823 if (rc != IXGBE_ERR_OVERTEMP) 2824 return; 2825 break; 2826 default: 2827 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2828 return; 2829 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2830 return; 2831 break; 2832 } 2833 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2834 2835 adapter->interrupt_event = 0; 2836 } 2837 2838 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2839 { 2840 struct ixgbe_hw *hw = &adapter->hw; 2841 2842 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2843 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2844 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2845 /* write to clear the interrupt */ 2846 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2847 } 2848 } 2849 2850 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2851 { 2852 struct ixgbe_hw *hw = &adapter->hw; 2853 2854 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2855 return; 2856 2857 switch (adapter->hw.mac.type) { 2858 case ixgbe_mac_82599EB: 2859 /* 2860 * Need to check link state so complete overtemp check 2861 * on service task 2862 */ 2863 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2864 (eicr & IXGBE_EICR_LSC)) && 2865 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2866 adapter->interrupt_event = eicr; 2867 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2868 ixgbe_service_event_schedule(adapter); 2869 return; 2870 } 2871 return; 2872 case ixgbe_mac_x550em_a: 2873 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2874 adapter->interrupt_event = eicr; 2875 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2876 ixgbe_service_event_schedule(adapter); 2877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2878 IXGBE_EICR_GPI_SDP0_X550EM_a); 2879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2880 IXGBE_EICR_GPI_SDP0_X550EM_a); 2881 } 2882 return; 2883 case ixgbe_mac_X550: 2884 case ixgbe_mac_X540: 2885 if (!(eicr & IXGBE_EICR_TS)) 2886 return; 2887 break; 2888 default: 2889 return; 2890 } 2891 2892 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2893 } 2894 2895 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2896 { 2897 switch (hw->mac.type) { 2898 case ixgbe_mac_82598EB: 2899 if (hw->phy.type == ixgbe_phy_nl) 2900 return true; 2901 return false; 2902 case ixgbe_mac_82599EB: 2903 case ixgbe_mac_X550EM_x: 2904 case ixgbe_mac_x550em_a: 2905 switch (hw->mac.ops.get_media_type(hw)) { 2906 case ixgbe_media_type_fiber: 2907 case ixgbe_media_type_fiber_qsfp: 2908 return true; 2909 default: 2910 return false; 2911 } 2912 default: 2913 return false; 2914 } 2915 } 2916 2917 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2918 { 2919 struct ixgbe_hw *hw = &adapter->hw; 2920 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2921 2922 if (!ixgbe_is_sfp(hw)) 2923 return; 2924 2925 /* Later MAC's use different SDP */ 2926 if (hw->mac.type >= ixgbe_mac_X540) 2927 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2928 2929 if (eicr & eicr_mask) { 2930 /* Clear the interrupt */ 2931 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2932 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2933 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2934 adapter->sfp_poll_time = 0; 2935 ixgbe_service_event_schedule(adapter); 2936 } 2937 } 2938 2939 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2940 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2941 /* Clear the interrupt */ 2942 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2943 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2944 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2945 ixgbe_service_event_schedule(adapter); 2946 } 2947 } 2948 } 2949 2950 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2951 { 2952 struct ixgbe_hw *hw = &adapter->hw; 2953 2954 adapter->lsc_int++; 2955 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2956 adapter->link_check_timeout = jiffies; 2957 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2958 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2959 IXGBE_WRITE_FLUSH(hw); 2960 ixgbe_service_event_schedule(adapter); 2961 } 2962 } 2963 2964 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2965 u64 qmask) 2966 { 2967 u32 mask; 2968 struct ixgbe_hw *hw = &adapter->hw; 2969 2970 switch (hw->mac.type) { 2971 case ixgbe_mac_82598EB: 2972 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2973 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2974 break; 2975 case ixgbe_mac_82599EB: 2976 case ixgbe_mac_X540: 2977 case ixgbe_mac_X550: 2978 case ixgbe_mac_X550EM_x: 2979 case ixgbe_mac_x550em_a: 2980 mask = (qmask & 0xFFFFFFFF); 2981 if (mask) 2982 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2983 mask = (qmask >> 32); 2984 if (mask) 2985 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2986 break; 2987 default: 2988 break; 2989 } 2990 /* skip the flush */ 2991 } 2992 2993 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2994 u64 qmask) 2995 { 2996 u32 mask; 2997 struct ixgbe_hw *hw = &adapter->hw; 2998 2999 switch (hw->mac.type) { 3000 case ixgbe_mac_82598EB: 3001 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3002 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3003 break; 3004 case ixgbe_mac_82599EB: 3005 case ixgbe_mac_X540: 3006 case ixgbe_mac_X550: 3007 case ixgbe_mac_X550EM_x: 3008 case ixgbe_mac_x550em_a: 3009 mask = (qmask & 0xFFFFFFFF); 3010 if (mask) 3011 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3012 mask = (qmask >> 32); 3013 if (mask) 3014 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3015 break; 3016 default: 3017 break; 3018 } 3019 /* skip the flush */ 3020 } 3021 3022 /** 3023 * ixgbe_irq_enable - Enable default interrupt generation settings 3024 * @adapter: board private structure 3025 **/ 3026 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3027 bool flush) 3028 { 3029 struct ixgbe_hw *hw = &adapter->hw; 3030 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3031 3032 /* don't reenable LSC while waiting for link */ 3033 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3034 mask &= ~IXGBE_EIMS_LSC; 3035 3036 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3037 switch (adapter->hw.mac.type) { 3038 case ixgbe_mac_82599EB: 3039 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3040 break; 3041 case ixgbe_mac_X540: 3042 case ixgbe_mac_X550: 3043 case ixgbe_mac_X550EM_x: 3044 case ixgbe_mac_x550em_a: 3045 mask |= IXGBE_EIMS_TS; 3046 break; 3047 default: 3048 break; 3049 } 3050 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3051 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3052 switch (adapter->hw.mac.type) { 3053 case ixgbe_mac_82599EB: 3054 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3055 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3056 /* fall through */ 3057 case ixgbe_mac_X540: 3058 case ixgbe_mac_X550: 3059 case ixgbe_mac_X550EM_x: 3060 case ixgbe_mac_x550em_a: 3061 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3062 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3063 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3064 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3065 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3066 mask |= IXGBE_EICR_GPI_SDP0_X540; 3067 mask |= IXGBE_EIMS_ECC; 3068 mask |= IXGBE_EIMS_MAILBOX; 3069 break; 3070 default: 3071 break; 3072 } 3073 3074 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3075 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3076 mask |= IXGBE_EIMS_FLOW_DIR; 3077 3078 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3079 if (queues) 3080 ixgbe_irq_enable_queues(adapter, ~0); 3081 if (flush) 3082 IXGBE_WRITE_FLUSH(&adapter->hw); 3083 } 3084 3085 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3086 { 3087 struct ixgbe_adapter *adapter = data; 3088 struct ixgbe_hw *hw = &adapter->hw; 3089 u32 eicr; 3090 3091 /* 3092 * Workaround for Silicon errata. Use clear-by-write instead 3093 * of clear-by-read. Reading with EICS will return the 3094 * interrupt causes without clearing, which later be done 3095 * with the write to EICR. 3096 */ 3097 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3098 3099 /* The lower 16bits of the EICR register are for the queue interrupts 3100 * which should be masked here in order to not accidentally clear them if 3101 * the bits are high when ixgbe_msix_other is called. There is a race 3102 * condition otherwise which results in possible performance loss 3103 * especially if the ixgbe_msix_other interrupt is triggering 3104 * consistently (as it would when PPS is turned on for the X540 device) 3105 */ 3106 eicr &= 0xFFFF0000; 3107 3108 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3109 3110 if (eicr & IXGBE_EICR_LSC) 3111 ixgbe_check_lsc(adapter); 3112 3113 if (eicr & IXGBE_EICR_MAILBOX) 3114 ixgbe_msg_task(adapter); 3115 3116 switch (hw->mac.type) { 3117 case ixgbe_mac_82599EB: 3118 case ixgbe_mac_X540: 3119 case ixgbe_mac_X550: 3120 case ixgbe_mac_X550EM_x: 3121 case ixgbe_mac_x550em_a: 3122 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3123 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3124 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3125 ixgbe_service_event_schedule(adapter); 3126 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3127 IXGBE_EICR_GPI_SDP0_X540); 3128 } 3129 if (eicr & IXGBE_EICR_ECC) { 3130 e_info(link, "Received ECC Err, initiating reset\n"); 3131 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3132 ixgbe_service_event_schedule(adapter); 3133 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3134 } 3135 /* Handle Flow Director Full threshold interrupt */ 3136 if (eicr & IXGBE_EICR_FLOW_DIR) { 3137 int reinit_count = 0; 3138 int i; 3139 for (i = 0; i < adapter->num_tx_queues; i++) { 3140 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3141 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3142 &ring->state)) 3143 reinit_count++; 3144 } 3145 if (reinit_count) { 3146 /* no more flow director interrupts until after init */ 3147 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3148 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3149 ixgbe_service_event_schedule(adapter); 3150 } 3151 } 3152 ixgbe_check_sfp_event(adapter, eicr); 3153 ixgbe_check_overtemp_event(adapter, eicr); 3154 break; 3155 default: 3156 break; 3157 } 3158 3159 ixgbe_check_fan_failure(adapter, eicr); 3160 3161 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3162 ixgbe_ptp_check_pps_event(adapter); 3163 3164 /* re-enable the original interrupt state, no lsc, no queues */ 3165 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3166 ixgbe_irq_enable(adapter, false, false); 3167 3168 return IRQ_HANDLED; 3169 } 3170 3171 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3172 { 3173 struct ixgbe_q_vector *q_vector = data; 3174 3175 /* EIAM disabled interrupts (on this vector) for us */ 3176 3177 if (q_vector->rx.ring || q_vector->tx.ring) 3178 napi_schedule_irqoff(&q_vector->napi); 3179 3180 return IRQ_HANDLED; 3181 } 3182 3183 /** 3184 * ixgbe_poll - NAPI Rx polling callback 3185 * @napi: structure for representing this polling device 3186 * @budget: how many packets driver is allowed to clean 3187 * 3188 * This function is used for legacy and MSI, NAPI mode 3189 **/ 3190 int ixgbe_poll(struct napi_struct *napi, int budget) 3191 { 3192 struct ixgbe_q_vector *q_vector = 3193 container_of(napi, struct ixgbe_q_vector, napi); 3194 struct ixgbe_adapter *adapter = q_vector->adapter; 3195 struct ixgbe_ring *ring; 3196 int per_ring_budget, work_done = 0; 3197 bool clean_complete = true; 3198 3199 #ifdef CONFIG_IXGBE_DCA 3200 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3201 ixgbe_update_dca(q_vector); 3202 #endif 3203 3204 ixgbe_for_each_ring(ring, q_vector->tx) { 3205 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3206 clean_complete = false; 3207 } 3208 3209 /* Exit if we are called by netpoll */ 3210 if (budget <= 0) 3211 return budget; 3212 3213 /* attempt to distribute budget to each queue fairly, but don't allow 3214 * the budget to go below 1 because we'll exit polling */ 3215 if (q_vector->rx.count > 1) 3216 per_ring_budget = max(budget/q_vector->rx.count, 1); 3217 else 3218 per_ring_budget = budget; 3219 3220 ixgbe_for_each_ring(ring, q_vector->rx) { 3221 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3222 per_ring_budget); 3223 3224 work_done += cleaned; 3225 if (cleaned >= per_ring_budget) 3226 clean_complete = false; 3227 } 3228 3229 /* If all work not completed, return budget and keep polling */ 3230 if (!clean_complete) 3231 return budget; 3232 3233 /* all work done, exit the polling mode */ 3234 napi_complete_done(napi, work_done); 3235 if (adapter->rx_itr_setting & 1) 3236 ixgbe_set_itr(q_vector); 3237 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3238 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3239 3240 return min(work_done, budget - 1); 3241 } 3242 3243 /** 3244 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3245 * @adapter: board private structure 3246 * 3247 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3248 * interrupts from the kernel. 3249 **/ 3250 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3251 { 3252 struct net_device *netdev = adapter->netdev; 3253 unsigned int ri = 0, ti = 0; 3254 int vector, err; 3255 3256 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3257 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3258 struct msix_entry *entry = &adapter->msix_entries[vector]; 3259 3260 if (q_vector->tx.ring && q_vector->rx.ring) { 3261 snprintf(q_vector->name, sizeof(q_vector->name), 3262 "%s-TxRx-%u", netdev->name, ri++); 3263 ti++; 3264 } else if (q_vector->rx.ring) { 3265 snprintf(q_vector->name, sizeof(q_vector->name), 3266 "%s-rx-%u", netdev->name, ri++); 3267 } else if (q_vector->tx.ring) { 3268 snprintf(q_vector->name, sizeof(q_vector->name), 3269 "%s-tx-%u", netdev->name, ti++); 3270 } else { 3271 /* skip this unused q_vector */ 3272 continue; 3273 } 3274 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3275 q_vector->name, q_vector); 3276 if (err) { 3277 e_err(probe, "request_irq failed for MSIX interrupt " 3278 "Error: %d\n", err); 3279 goto free_queue_irqs; 3280 } 3281 /* If Flow Director is enabled, set interrupt affinity */ 3282 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3283 /* assign the mask for this irq */ 3284 irq_set_affinity_hint(entry->vector, 3285 &q_vector->affinity_mask); 3286 } 3287 } 3288 3289 err = request_irq(adapter->msix_entries[vector].vector, 3290 ixgbe_msix_other, 0, netdev->name, adapter); 3291 if (err) { 3292 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3293 goto free_queue_irqs; 3294 } 3295 3296 return 0; 3297 3298 free_queue_irqs: 3299 while (vector) { 3300 vector--; 3301 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3302 NULL); 3303 free_irq(adapter->msix_entries[vector].vector, 3304 adapter->q_vector[vector]); 3305 } 3306 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3307 pci_disable_msix(adapter->pdev); 3308 kfree(adapter->msix_entries); 3309 adapter->msix_entries = NULL; 3310 return err; 3311 } 3312 3313 /** 3314 * ixgbe_intr - legacy mode Interrupt Handler 3315 * @irq: interrupt number 3316 * @data: pointer to a network interface device structure 3317 **/ 3318 static irqreturn_t ixgbe_intr(int irq, void *data) 3319 { 3320 struct ixgbe_adapter *adapter = data; 3321 struct ixgbe_hw *hw = &adapter->hw; 3322 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3323 u32 eicr; 3324 3325 /* 3326 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3327 * before the read of EICR. 3328 */ 3329 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3330 3331 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3332 * therefore no explicit interrupt disable is necessary */ 3333 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3334 if (!eicr) { 3335 /* 3336 * shared interrupt alert! 3337 * make sure interrupts are enabled because the read will 3338 * have disabled interrupts due to EIAM 3339 * finish the workaround of silicon errata on 82598. Unmask 3340 * the interrupt that we masked before the EICR read. 3341 */ 3342 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3343 ixgbe_irq_enable(adapter, true, true); 3344 return IRQ_NONE; /* Not our interrupt */ 3345 } 3346 3347 if (eicr & IXGBE_EICR_LSC) 3348 ixgbe_check_lsc(adapter); 3349 3350 switch (hw->mac.type) { 3351 case ixgbe_mac_82599EB: 3352 ixgbe_check_sfp_event(adapter, eicr); 3353 /* Fall through */ 3354 case ixgbe_mac_X540: 3355 case ixgbe_mac_X550: 3356 case ixgbe_mac_X550EM_x: 3357 case ixgbe_mac_x550em_a: 3358 if (eicr & IXGBE_EICR_ECC) { 3359 e_info(link, "Received ECC Err, initiating reset\n"); 3360 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3361 ixgbe_service_event_schedule(adapter); 3362 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3363 } 3364 ixgbe_check_overtemp_event(adapter, eicr); 3365 break; 3366 default: 3367 break; 3368 } 3369 3370 ixgbe_check_fan_failure(adapter, eicr); 3371 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3372 ixgbe_ptp_check_pps_event(adapter); 3373 3374 /* would disable interrupts here but EIAM disabled it */ 3375 napi_schedule_irqoff(&q_vector->napi); 3376 3377 /* 3378 * re-enable link(maybe) and non-queue interrupts, no flush. 3379 * ixgbe_poll will re-enable the queue interrupts 3380 */ 3381 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3382 ixgbe_irq_enable(adapter, false, false); 3383 3384 return IRQ_HANDLED; 3385 } 3386 3387 /** 3388 * ixgbe_request_irq - initialize interrupts 3389 * @adapter: board private structure 3390 * 3391 * Attempts to configure interrupts using the best available 3392 * capabilities of the hardware and kernel. 3393 **/ 3394 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3395 { 3396 struct net_device *netdev = adapter->netdev; 3397 int err; 3398 3399 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3400 err = ixgbe_request_msix_irqs(adapter); 3401 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3402 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3403 netdev->name, adapter); 3404 else 3405 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3406 netdev->name, adapter); 3407 3408 if (err) 3409 e_err(probe, "request_irq failed, Error %d\n", err); 3410 3411 return err; 3412 } 3413 3414 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3415 { 3416 int vector; 3417 3418 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3419 free_irq(adapter->pdev->irq, adapter); 3420 return; 3421 } 3422 3423 if (!adapter->msix_entries) 3424 return; 3425 3426 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3427 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3428 struct msix_entry *entry = &adapter->msix_entries[vector]; 3429 3430 /* free only the irqs that were actually requested */ 3431 if (!q_vector->rx.ring && !q_vector->tx.ring) 3432 continue; 3433 3434 /* clear the affinity_mask in the IRQ descriptor */ 3435 irq_set_affinity_hint(entry->vector, NULL); 3436 3437 free_irq(entry->vector, q_vector); 3438 } 3439 3440 free_irq(adapter->msix_entries[vector].vector, adapter); 3441 } 3442 3443 /** 3444 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3445 * @adapter: board private structure 3446 **/ 3447 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3448 { 3449 switch (adapter->hw.mac.type) { 3450 case ixgbe_mac_82598EB: 3451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3452 break; 3453 case ixgbe_mac_82599EB: 3454 case ixgbe_mac_X540: 3455 case ixgbe_mac_X550: 3456 case ixgbe_mac_X550EM_x: 3457 case ixgbe_mac_x550em_a: 3458 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3459 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3461 break; 3462 default: 3463 break; 3464 } 3465 IXGBE_WRITE_FLUSH(&adapter->hw); 3466 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3467 int vector; 3468 3469 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3470 synchronize_irq(adapter->msix_entries[vector].vector); 3471 3472 synchronize_irq(adapter->msix_entries[vector++].vector); 3473 } else { 3474 synchronize_irq(adapter->pdev->irq); 3475 } 3476 } 3477 3478 /** 3479 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3480 * 3481 **/ 3482 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3483 { 3484 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3485 3486 ixgbe_write_eitr(q_vector); 3487 3488 ixgbe_set_ivar(adapter, 0, 0, 0); 3489 ixgbe_set_ivar(adapter, 1, 0, 0); 3490 3491 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3492 } 3493 3494 /** 3495 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3496 * @adapter: board private structure 3497 * @ring: structure containing ring specific data 3498 * 3499 * Configure the Tx descriptor ring after a reset. 3500 **/ 3501 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3502 struct ixgbe_ring *ring) 3503 { 3504 struct ixgbe_hw *hw = &adapter->hw; 3505 u64 tdba = ring->dma; 3506 int wait_loop = 10; 3507 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3508 u8 reg_idx = ring->reg_idx; 3509 3510 /* disable queue to avoid issues while updating state */ 3511 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3512 IXGBE_WRITE_FLUSH(hw); 3513 3514 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3515 (tdba & DMA_BIT_MASK(32))); 3516 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3517 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3518 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3519 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3520 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3521 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3522 3523 /* 3524 * set WTHRESH to encourage burst writeback, it should not be set 3525 * higher than 1 when: 3526 * - ITR is 0 as it could cause false TX hangs 3527 * - ITR is set to > 100k int/sec and BQL is enabled 3528 * 3529 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3530 * to or less than the number of on chip descriptors, which is 3531 * currently 40. 3532 */ 3533 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3534 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3535 else 3536 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3537 3538 /* 3539 * Setting PTHRESH to 32 both improves performance 3540 * and avoids a TX hang with DFP enabled 3541 */ 3542 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3543 32; /* PTHRESH = 32 */ 3544 3545 /* reinitialize flowdirector state */ 3546 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3547 ring->atr_sample_rate = adapter->atr_sample_rate; 3548 ring->atr_count = 0; 3549 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3550 } else { 3551 ring->atr_sample_rate = 0; 3552 } 3553 3554 /* initialize XPS */ 3555 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3556 struct ixgbe_q_vector *q_vector = ring->q_vector; 3557 3558 if (q_vector) 3559 netif_set_xps_queue(ring->netdev, 3560 &q_vector->affinity_mask, 3561 ring->queue_index); 3562 } 3563 3564 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3565 3566 /* reinitialize tx_buffer_info */ 3567 memset(ring->tx_buffer_info, 0, 3568 sizeof(struct ixgbe_tx_buffer) * ring->count); 3569 3570 /* enable queue */ 3571 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3572 3573 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3574 if (hw->mac.type == ixgbe_mac_82598EB && 3575 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3576 return; 3577 3578 /* poll to verify queue is enabled */ 3579 do { 3580 usleep_range(1000, 2000); 3581 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3582 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3583 if (!wait_loop) 3584 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3585 } 3586 3587 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3588 { 3589 struct ixgbe_hw *hw = &adapter->hw; 3590 u32 rttdcs, mtqc; 3591 u8 tcs = netdev_get_num_tc(adapter->netdev); 3592 3593 if (hw->mac.type == ixgbe_mac_82598EB) 3594 return; 3595 3596 /* disable the arbiter while setting MTQC */ 3597 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3598 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3599 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3600 3601 /* set transmit pool layout */ 3602 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3603 mtqc = IXGBE_MTQC_VT_ENA; 3604 if (tcs > 4) 3605 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3606 else if (tcs > 1) 3607 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3608 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3609 IXGBE_82599_VMDQ_4Q_MASK) 3610 mtqc |= IXGBE_MTQC_32VF; 3611 else 3612 mtqc |= IXGBE_MTQC_64VF; 3613 } else { 3614 if (tcs > 4) 3615 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3616 else if (tcs > 1) 3617 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3618 else 3619 mtqc = IXGBE_MTQC_64Q_1PB; 3620 } 3621 3622 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3623 3624 /* Enable Security TX Buffer IFG for multiple pb */ 3625 if (tcs) { 3626 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3627 sectx |= IXGBE_SECTX_DCB; 3628 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3629 } 3630 3631 /* re-enable the arbiter */ 3632 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3633 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3634 } 3635 3636 /** 3637 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3638 * @adapter: board private structure 3639 * 3640 * Configure the Tx unit of the MAC after a reset. 3641 **/ 3642 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3643 { 3644 struct ixgbe_hw *hw = &adapter->hw; 3645 u32 dmatxctl; 3646 u32 i; 3647 3648 ixgbe_setup_mtqc(adapter); 3649 3650 if (hw->mac.type != ixgbe_mac_82598EB) { 3651 /* DMATXCTL.EN must be before Tx queues are enabled */ 3652 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3653 dmatxctl |= IXGBE_DMATXCTL_TE; 3654 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3655 } 3656 3657 /* Setup the HW Tx Head and Tail descriptor pointers */ 3658 for (i = 0; i < adapter->num_tx_queues; i++) 3659 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3660 for (i = 0; i < adapter->num_xdp_queues; i++) 3661 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3662 } 3663 3664 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3665 struct ixgbe_ring *ring) 3666 { 3667 struct ixgbe_hw *hw = &adapter->hw; 3668 u8 reg_idx = ring->reg_idx; 3669 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3670 3671 srrctl |= IXGBE_SRRCTL_DROP_EN; 3672 3673 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3674 } 3675 3676 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3677 struct ixgbe_ring *ring) 3678 { 3679 struct ixgbe_hw *hw = &adapter->hw; 3680 u8 reg_idx = ring->reg_idx; 3681 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3682 3683 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3684 3685 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3686 } 3687 3688 #ifdef CONFIG_IXGBE_DCB 3689 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3690 #else 3691 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3692 #endif 3693 { 3694 int i; 3695 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3696 3697 if (adapter->ixgbe_ieee_pfc) 3698 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3699 3700 /* 3701 * We should set the drop enable bit if: 3702 * SR-IOV is enabled 3703 * or 3704 * Number of Rx queues > 1 and flow control is disabled 3705 * 3706 * This allows us to avoid head of line blocking for security 3707 * and performance reasons. 3708 */ 3709 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3710 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3711 for (i = 0; i < adapter->num_rx_queues; i++) 3712 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3713 } else { 3714 for (i = 0; i < adapter->num_rx_queues; i++) 3715 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3716 } 3717 } 3718 3719 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3720 3721 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3722 struct ixgbe_ring *rx_ring) 3723 { 3724 struct ixgbe_hw *hw = &adapter->hw; 3725 u32 srrctl; 3726 u8 reg_idx = rx_ring->reg_idx; 3727 3728 if (hw->mac.type == ixgbe_mac_82598EB) { 3729 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3730 3731 /* 3732 * if VMDq is not active we must program one srrctl register 3733 * per RSS queue since we have enabled RDRXCTL.MVMEN 3734 */ 3735 reg_idx &= mask; 3736 } 3737 3738 /* configure header buffer length, needed for RSC */ 3739 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3740 3741 /* configure the packet buffer length */ 3742 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3743 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3744 else 3745 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3746 3747 /* configure descriptor type */ 3748 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3749 3750 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3751 } 3752 3753 /** 3754 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3755 * @adapter: device handle 3756 * 3757 * - 82598/82599/X540: 128 3758 * - X550(non-SRIOV mode): 512 3759 * - X550(SRIOV mode): 64 3760 */ 3761 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3762 { 3763 if (adapter->hw.mac.type < ixgbe_mac_X550) 3764 return 128; 3765 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3766 return 64; 3767 else 3768 return 512; 3769 } 3770 3771 /** 3772 * ixgbe_store_key - Write the RSS key to HW 3773 * @adapter: device handle 3774 * 3775 * Write the RSS key stored in adapter.rss_key to HW. 3776 */ 3777 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3778 { 3779 struct ixgbe_hw *hw = &adapter->hw; 3780 int i; 3781 3782 for (i = 0; i < 10; i++) 3783 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3784 } 3785 3786 /** 3787 * ixgbe_init_rss_key - Initialize adapter RSS key 3788 * @adapter: device handle 3789 * 3790 * Allocates and initializes the RSS key if it is not allocated. 3791 **/ 3792 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3793 { 3794 u32 *rss_key; 3795 3796 if (!adapter->rss_key) { 3797 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3798 if (unlikely(!rss_key)) 3799 return -ENOMEM; 3800 3801 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3802 adapter->rss_key = rss_key; 3803 } 3804 3805 return 0; 3806 } 3807 3808 /** 3809 * ixgbe_store_reta - Write the RETA table to HW 3810 * @adapter: device handle 3811 * 3812 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3813 */ 3814 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3815 { 3816 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3817 struct ixgbe_hw *hw = &adapter->hw; 3818 u32 reta = 0; 3819 u32 indices_multi; 3820 u8 *indir_tbl = adapter->rss_indir_tbl; 3821 3822 /* Fill out the redirection table as follows: 3823 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3824 * indices. 3825 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3826 * - X550: 8 bit wide entries containing 6 bit RSS index 3827 */ 3828 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3829 indices_multi = 0x11; 3830 else 3831 indices_multi = 0x1; 3832 3833 /* Write redirection table to HW */ 3834 for (i = 0; i < reta_entries; i++) { 3835 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3836 if ((i & 3) == 3) { 3837 if (i < 128) 3838 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3839 else 3840 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3841 reta); 3842 reta = 0; 3843 } 3844 } 3845 } 3846 3847 /** 3848 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3849 * @adapter: device handle 3850 * 3851 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3852 */ 3853 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3854 { 3855 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3856 struct ixgbe_hw *hw = &adapter->hw; 3857 u32 vfreta = 0; 3858 unsigned int pf_pool = adapter->num_vfs; 3859 3860 /* Write redirection table to HW */ 3861 for (i = 0; i < reta_entries; i++) { 3862 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3863 if ((i & 3) == 3) { 3864 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3865 vfreta); 3866 vfreta = 0; 3867 } 3868 } 3869 } 3870 3871 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3872 { 3873 u32 i, j; 3874 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3875 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3876 3877 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3878 * make full use of any rings they may have. We will use the 3879 * PSRTYPE register to control how many rings we use within the PF. 3880 */ 3881 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3882 rss_i = 4; 3883 3884 /* Fill out hash function seeds */ 3885 ixgbe_store_key(adapter); 3886 3887 /* Fill out redirection table */ 3888 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3889 3890 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3891 if (j == rss_i) 3892 j = 0; 3893 3894 adapter->rss_indir_tbl[i] = j; 3895 } 3896 3897 ixgbe_store_reta(adapter); 3898 } 3899 3900 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3901 { 3902 struct ixgbe_hw *hw = &adapter->hw; 3903 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3904 unsigned int pf_pool = adapter->num_vfs; 3905 int i, j; 3906 3907 /* Fill out hash function seeds */ 3908 for (i = 0; i < 10; i++) 3909 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), 3910 *(adapter->rss_key + i)); 3911 3912 /* Fill out the redirection table */ 3913 for (i = 0, j = 0; i < 64; i++, j++) { 3914 if (j == rss_i) 3915 j = 0; 3916 3917 adapter->rss_indir_tbl[i] = j; 3918 } 3919 3920 ixgbe_store_vfreta(adapter); 3921 } 3922 3923 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3924 { 3925 struct ixgbe_hw *hw = &adapter->hw; 3926 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3927 u32 rxcsum; 3928 3929 /* Disable indicating checksum in descriptor, enables RSS hash */ 3930 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3931 rxcsum |= IXGBE_RXCSUM_PCSD; 3932 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3933 3934 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3935 if (adapter->ring_feature[RING_F_RSS].mask) 3936 mrqc = IXGBE_MRQC_RSSEN; 3937 } else { 3938 u8 tcs = netdev_get_num_tc(adapter->netdev); 3939 3940 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3941 if (tcs > 4) 3942 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3943 else if (tcs > 1) 3944 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3945 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3946 IXGBE_82599_VMDQ_4Q_MASK) 3947 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3948 else 3949 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3950 3951 /* Enable L3/L4 for Tx Switched packets */ 3952 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3953 } else { 3954 if (tcs > 4) 3955 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3956 else if (tcs > 1) 3957 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3958 else 3959 mrqc = IXGBE_MRQC_RSSEN; 3960 } 3961 } 3962 3963 /* Perform hash on these packet types */ 3964 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3965 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3966 IXGBE_MRQC_RSS_FIELD_IPV6 | 3967 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3968 3969 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3970 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3971 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3972 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3973 3974 if ((hw->mac.type >= ixgbe_mac_X550) && 3975 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3976 unsigned int pf_pool = adapter->num_vfs; 3977 3978 /* Enable VF RSS mode */ 3979 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3980 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3981 3982 /* Setup RSS through the VF registers */ 3983 ixgbe_setup_vfreta(adapter); 3984 vfmrqc = IXGBE_MRQC_RSSEN; 3985 vfmrqc |= rss_field; 3986 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3987 } else { 3988 ixgbe_setup_reta(adapter); 3989 mrqc |= rss_field; 3990 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3991 } 3992 } 3993 3994 /** 3995 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3996 * @adapter: address of board private structure 3997 * @index: index of ring to set 3998 **/ 3999 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4000 struct ixgbe_ring *ring) 4001 { 4002 struct ixgbe_hw *hw = &adapter->hw; 4003 u32 rscctrl; 4004 u8 reg_idx = ring->reg_idx; 4005 4006 if (!ring_is_rsc_enabled(ring)) 4007 return; 4008 4009 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4010 rscctrl |= IXGBE_RSCCTL_RSCEN; 4011 /* 4012 * we must limit the number of descriptors so that the 4013 * total size of max desc * buf_len is not greater 4014 * than 65536 4015 */ 4016 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4017 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4018 } 4019 4020 #define IXGBE_MAX_RX_DESC_POLL 10 4021 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4022 struct ixgbe_ring *ring) 4023 { 4024 struct ixgbe_hw *hw = &adapter->hw; 4025 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4026 u32 rxdctl; 4027 u8 reg_idx = ring->reg_idx; 4028 4029 if (ixgbe_removed(hw->hw_addr)) 4030 return; 4031 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4032 if (hw->mac.type == ixgbe_mac_82598EB && 4033 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4034 return; 4035 4036 do { 4037 usleep_range(1000, 2000); 4038 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4039 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4040 4041 if (!wait_loop) { 4042 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4043 "the polling period\n", reg_idx); 4044 } 4045 } 4046 4047 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 4048 struct ixgbe_ring *ring) 4049 { 4050 struct ixgbe_hw *hw = &adapter->hw; 4051 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4052 u32 rxdctl; 4053 u8 reg_idx = ring->reg_idx; 4054 4055 if (ixgbe_removed(hw->hw_addr)) 4056 return; 4057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4058 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4059 4060 /* write value back with RXDCTL.ENABLE bit cleared */ 4061 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4062 4063 if (hw->mac.type == ixgbe_mac_82598EB && 4064 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4065 return; 4066 4067 /* the hardware may take up to 100us to really disable the rx queue */ 4068 do { 4069 udelay(10); 4070 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4071 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 4072 4073 if (!wait_loop) { 4074 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 4075 "the polling period\n", reg_idx); 4076 } 4077 } 4078 4079 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4080 struct ixgbe_ring *ring) 4081 { 4082 struct ixgbe_hw *hw = &adapter->hw; 4083 union ixgbe_adv_rx_desc *rx_desc; 4084 u64 rdba = ring->dma; 4085 u32 rxdctl; 4086 u8 reg_idx = ring->reg_idx; 4087 4088 /* disable queue to avoid issues while updating state */ 4089 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4090 ixgbe_disable_rx_queue(adapter, ring); 4091 4092 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4093 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4094 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4095 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4096 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4097 IXGBE_WRITE_FLUSH(hw); 4098 4099 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4100 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4101 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4102 4103 ixgbe_configure_srrctl(adapter, ring); 4104 ixgbe_configure_rscctl(adapter, ring); 4105 4106 if (hw->mac.type == ixgbe_mac_82598EB) { 4107 /* 4108 * enable cache line friendly hardware writes: 4109 * PTHRESH=32 descriptors (half the internal cache), 4110 * this also removes ugly rx_no_buffer_count increment 4111 * HTHRESH=4 descriptors (to minimize latency on fetch) 4112 * WTHRESH=8 burst writeback up to two cache lines 4113 */ 4114 rxdctl &= ~0x3FFFFF; 4115 rxdctl |= 0x080420; 4116 #if (PAGE_SIZE < 8192) 4117 } else { 4118 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4119 IXGBE_RXDCTL_RLPML_EN); 4120 4121 /* Limit the maximum frame size so we don't overrun the skb */ 4122 if (ring_uses_build_skb(ring) && 4123 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4124 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4125 IXGBE_RXDCTL_RLPML_EN; 4126 #endif 4127 } 4128 4129 /* initialize rx_buffer_info */ 4130 memset(ring->rx_buffer_info, 0, 4131 sizeof(struct ixgbe_rx_buffer) * ring->count); 4132 4133 /* initialize Rx descriptor 0 */ 4134 rx_desc = IXGBE_RX_DESC(ring, 0); 4135 rx_desc->wb.upper.length = 0; 4136 4137 /* enable receive descriptor ring */ 4138 rxdctl |= IXGBE_RXDCTL_ENABLE; 4139 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4140 4141 ixgbe_rx_desc_queue_enable(adapter, ring); 4142 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4143 } 4144 4145 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4146 { 4147 struct ixgbe_hw *hw = &adapter->hw; 4148 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4149 u16 pool; 4150 4151 /* PSRTYPE must be initialized in non 82598 adapters */ 4152 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4153 IXGBE_PSRTYPE_UDPHDR | 4154 IXGBE_PSRTYPE_IPV4HDR | 4155 IXGBE_PSRTYPE_L2HDR | 4156 IXGBE_PSRTYPE_IPV6HDR; 4157 4158 if (hw->mac.type == ixgbe_mac_82598EB) 4159 return; 4160 4161 if (rss_i > 3) 4162 psrtype |= 2u << 29; 4163 else if (rss_i > 1) 4164 psrtype |= 1u << 29; 4165 4166 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 4167 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4168 } 4169 4170 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4171 { 4172 struct ixgbe_hw *hw = &adapter->hw; 4173 u32 reg_offset, vf_shift; 4174 u32 gcr_ext, vmdctl; 4175 int i; 4176 4177 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4178 return; 4179 4180 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4181 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4182 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4183 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4184 vmdctl |= IXGBE_VT_CTL_REPLEN; 4185 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4186 4187 vf_shift = VMDQ_P(0) % 32; 4188 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4189 4190 /* Enable only the PF's pool for Tx/Rx */ 4191 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4192 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4193 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4194 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4195 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4196 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4197 4198 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4199 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4200 4201 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4202 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4203 4204 /* 4205 * Set up VF register offsets for selected VT Mode, 4206 * i.e. 32 or 64 VFs for SR-IOV 4207 */ 4208 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4209 case IXGBE_82599_VMDQ_8Q_MASK: 4210 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4211 break; 4212 case IXGBE_82599_VMDQ_4Q_MASK: 4213 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4214 break; 4215 default: 4216 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4217 break; 4218 } 4219 4220 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4221 4222 for (i = 0; i < adapter->num_vfs; i++) { 4223 /* configure spoof checking */ 4224 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4225 adapter->vfinfo[i].spoofchk_enabled); 4226 4227 /* Enable/Disable RSS query feature */ 4228 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4229 adapter->vfinfo[i].rss_query_enabled); 4230 } 4231 } 4232 4233 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4234 { 4235 struct ixgbe_hw *hw = &adapter->hw; 4236 struct net_device *netdev = adapter->netdev; 4237 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4238 struct ixgbe_ring *rx_ring; 4239 int i; 4240 u32 mhadd, hlreg0; 4241 4242 #ifdef IXGBE_FCOE 4243 /* adjust max frame to be able to do baby jumbo for FCoE */ 4244 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4245 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4246 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4247 4248 #endif /* IXGBE_FCOE */ 4249 4250 /* adjust max frame to be at least the size of a standard frame */ 4251 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4252 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4253 4254 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4255 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4256 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4257 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4258 4259 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4260 } 4261 4262 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4263 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4264 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4265 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4266 4267 /* 4268 * Setup the HW Rx Head and Tail Descriptor Pointers and 4269 * the Base and Length of the Rx Descriptor Ring 4270 */ 4271 for (i = 0; i < adapter->num_rx_queues; i++) { 4272 rx_ring = adapter->rx_ring[i]; 4273 4274 clear_ring_rsc_enabled(rx_ring); 4275 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4276 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4277 4278 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4279 set_ring_rsc_enabled(rx_ring); 4280 4281 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4282 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4283 4284 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4285 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4286 continue; 4287 4288 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4289 4290 #if (PAGE_SIZE < 8192) 4291 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4292 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4293 4294 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4295 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4296 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4297 #endif 4298 } 4299 } 4300 4301 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4302 { 4303 struct ixgbe_hw *hw = &adapter->hw; 4304 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4305 4306 switch (hw->mac.type) { 4307 case ixgbe_mac_82598EB: 4308 /* 4309 * For VMDq support of different descriptor types or 4310 * buffer sizes through the use of multiple SRRCTL 4311 * registers, RDRXCTL.MVMEN must be set to 1 4312 * 4313 * also, the manual doesn't mention it clearly but DCA hints 4314 * will only use queue 0's tags unless this bit is set. Side 4315 * effects of setting this bit are only that SRRCTL must be 4316 * fully programmed [0..15] 4317 */ 4318 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4319 break; 4320 case ixgbe_mac_X550: 4321 case ixgbe_mac_X550EM_x: 4322 case ixgbe_mac_x550em_a: 4323 if (adapter->num_vfs) 4324 rdrxctl |= IXGBE_RDRXCTL_PSP; 4325 /* fall through */ 4326 case ixgbe_mac_82599EB: 4327 case ixgbe_mac_X540: 4328 /* Disable RSC for ACK packets */ 4329 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4330 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4331 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4332 /* hardware requires some bits to be set by default */ 4333 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4334 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4335 break; 4336 default: 4337 /* We should do nothing since we don't know this hardware */ 4338 return; 4339 } 4340 4341 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4342 } 4343 4344 /** 4345 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4346 * @adapter: board private structure 4347 * 4348 * Configure the Rx unit of the MAC after a reset. 4349 **/ 4350 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4351 { 4352 struct ixgbe_hw *hw = &adapter->hw; 4353 int i; 4354 u32 rxctrl, rfctl; 4355 4356 /* disable receives while setting up the descriptors */ 4357 hw->mac.ops.disable_rx(hw); 4358 4359 ixgbe_setup_psrtype(adapter); 4360 ixgbe_setup_rdrxctl(adapter); 4361 4362 /* RSC Setup */ 4363 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4364 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4365 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4366 rfctl |= IXGBE_RFCTL_RSC_DIS; 4367 4368 /* disable NFS filtering */ 4369 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4370 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4371 4372 /* Program registers for the distribution of queues */ 4373 ixgbe_setup_mrqc(adapter); 4374 4375 /* set_rx_buffer_len must be called before ring initialization */ 4376 ixgbe_set_rx_buffer_len(adapter); 4377 4378 /* 4379 * Setup the HW Rx Head and Tail Descriptor Pointers and 4380 * the Base and Length of the Rx Descriptor Ring 4381 */ 4382 for (i = 0; i < adapter->num_rx_queues; i++) 4383 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4384 4385 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4386 /* disable drop enable for 82598 parts */ 4387 if (hw->mac.type == ixgbe_mac_82598EB) 4388 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4389 4390 /* enable all receives */ 4391 rxctrl |= IXGBE_RXCTRL_RXEN; 4392 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4393 } 4394 4395 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4396 __be16 proto, u16 vid) 4397 { 4398 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4399 struct ixgbe_hw *hw = &adapter->hw; 4400 4401 /* add VID to filter table */ 4402 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4403 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4404 4405 set_bit(vid, adapter->active_vlans); 4406 4407 return 0; 4408 } 4409 4410 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4411 { 4412 u32 vlvf; 4413 int idx; 4414 4415 /* short cut the special case */ 4416 if (vlan == 0) 4417 return 0; 4418 4419 /* Search for the vlan id in the VLVF entries */ 4420 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4421 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4422 if ((vlvf & VLAN_VID_MASK) == vlan) 4423 break; 4424 } 4425 4426 return idx; 4427 } 4428 4429 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4430 { 4431 struct ixgbe_hw *hw = &adapter->hw; 4432 u32 bits, word; 4433 int idx; 4434 4435 idx = ixgbe_find_vlvf_entry(hw, vid); 4436 if (!idx) 4437 return; 4438 4439 /* See if any other pools are set for this VLAN filter 4440 * entry other than the PF. 4441 */ 4442 word = idx * 2 + (VMDQ_P(0) / 32); 4443 bits = ~BIT(VMDQ_P(0) % 32); 4444 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4445 4446 /* Disable the filter so this falls into the default pool. */ 4447 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4448 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4449 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4450 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4451 } 4452 } 4453 4454 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4455 __be16 proto, u16 vid) 4456 { 4457 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4458 struct ixgbe_hw *hw = &adapter->hw; 4459 4460 /* remove VID from filter table */ 4461 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4462 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4463 4464 clear_bit(vid, adapter->active_vlans); 4465 4466 return 0; 4467 } 4468 4469 /** 4470 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4471 * @adapter: driver data 4472 */ 4473 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4474 { 4475 struct ixgbe_hw *hw = &adapter->hw; 4476 u32 vlnctrl; 4477 int i, j; 4478 4479 switch (hw->mac.type) { 4480 case ixgbe_mac_82598EB: 4481 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4482 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4483 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4484 break; 4485 case ixgbe_mac_82599EB: 4486 case ixgbe_mac_X540: 4487 case ixgbe_mac_X550: 4488 case ixgbe_mac_X550EM_x: 4489 case ixgbe_mac_x550em_a: 4490 for (i = 0; i < adapter->num_rx_queues; i++) { 4491 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4492 4493 if (ring->l2_accel_priv) 4494 continue; 4495 j = ring->reg_idx; 4496 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4497 vlnctrl &= ~IXGBE_RXDCTL_VME; 4498 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4499 } 4500 break; 4501 default: 4502 break; 4503 } 4504 } 4505 4506 /** 4507 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4508 * @adapter: driver data 4509 */ 4510 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4511 { 4512 struct ixgbe_hw *hw = &adapter->hw; 4513 u32 vlnctrl; 4514 int i, j; 4515 4516 switch (hw->mac.type) { 4517 case ixgbe_mac_82598EB: 4518 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4519 vlnctrl |= IXGBE_VLNCTRL_VME; 4520 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4521 break; 4522 case ixgbe_mac_82599EB: 4523 case ixgbe_mac_X540: 4524 case ixgbe_mac_X550: 4525 case ixgbe_mac_X550EM_x: 4526 case ixgbe_mac_x550em_a: 4527 for (i = 0; i < adapter->num_rx_queues; i++) { 4528 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4529 4530 if (ring->l2_accel_priv) 4531 continue; 4532 j = ring->reg_idx; 4533 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4534 vlnctrl |= IXGBE_RXDCTL_VME; 4535 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4536 } 4537 break; 4538 default: 4539 break; 4540 } 4541 } 4542 4543 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4544 { 4545 struct ixgbe_hw *hw = &adapter->hw; 4546 u32 vlnctrl, i; 4547 4548 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4549 4550 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4551 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4552 vlnctrl |= IXGBE_VLNCTRL_VFE; 4553 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4554 } else { 4555 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4556 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4557 return; 4558 } 4559 4560 /* Nothing to do for 82598 */ 4561 if (hw->mac.type == ixgbe_mac_82598EB) 4562 return; 4563 4564 /* We are already in VLAN promisc, nothing to do */ 4565 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4566 return; 4567 4568 /* Set flag so we don't redo unnecessary work */ 4569 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4570 4571 /* Add PF to all active pools */ 4572 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4573 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4574 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4575 4576 vlvfb |= BIT(VMDQ_P(0) % 32); 4577 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4578 } 4579 4580 /* Set all bits in the VLAN filter table array */ 4581 for (i = hw->mac.vft_size; i--;) 4582 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4583 } 4584 4585 #define VFTA_BLOCK_SIZE 8 4586 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4587 { 4588 struct ixgbe_hw *hw = &adapter->hw; 4589 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4590 u32 vid_start = vfta_offset * 32; 4591 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4592 u32 i, vid, word, bits; 4593 4594 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4595 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4596 4597 /* pull VLAN ID from VLVF */ 4598 vid = vlvf & VLAN_VID_MASK; 4599 4600 /* only concern outselves with a certain range */ 4601 if (vid < vid_start || vid >= vid_end) 4602 continue; 4603 4604 if (vlvf) { 4605 /* record VLAN ID in VFTA */ 4606 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4607 4608 /* if PF is part of this then continue */ 4609 if (test_bit(vid, adapter->active_vlans)) 4610 continue; 4611 } 4612 4613 /* remove PF from the pool */ 4614 word = i * 2 + VMDQ_P(0) / 32; 4615 bits = ~BIT(VMDQ_P(0) % 32); 4616 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4617 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4618 } 4619 4620 /* extract values from active_vlans and write back to VFTA */ 4621 for (i = VFTA_BLOCK_SIZE; i--;) { 4622 vid = (vfta_offset + i) * 32; 4623 word = vid / BITS_PER_LONG; 4624 bits = vid % BITS_PER_LONG; 4625 4626 vfta[i] |= adapter->active_vlans[word] >> bits; 4627 4628 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4629 } 4630 } 4631 4632 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4633 { 4634 struct ixgbe_hw *hw = &adapter->hw; 4635 u32 vlnctrl, i; 4636 4637 /* Set VLAN filtering to enabled */ 4638 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4639 vlnctrl |= IXGBE_VLNCTRL_VFE; 4640 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4641 4642 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4643 hw->mac.type == ixgbe_mac_82598EB) 4644 return; 4645 4646 /* We are not in VLAN promisc, nothing to do */ 4647 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4648 return; 4649 4650 /* Set flag so we don't redo unnecessary work */ 4651 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4652 4653 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4654 ixgbe_scrub_vfta(adapter, i); 4655 } 4656 4657 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4658 { 4659 u16 vid = 1; 4660 4661 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4662 4663 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4664 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4665 } 4666 4667 /** 4668 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4669 * @netdev: network interface device structure 4670 * 4671 * Writes multicast address list to the MTA hash table. 4672 * Returns: -ENOMEM on failure 4673 * 0 on no addresses written 4674 * X on writing X addresses to MTA 4675 **/ 4676 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4677 { 4678 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4679 struct ixgbe_hw *hw = &adapter->hw; 4680 4681 if (!netif_running(netdev)) 4682 return 0; 4683 4684 if (hw->mac.ops.update_mc_addr_list) 4685 hw->mac.ops.update_mc_addr_list(hw, netdev); 4686 else 4687 return -ENOMEM; 4688 4689 #ifdef CONFIG_PCI_IOV 4690 ixgbe_restore_vf_multicasts(adapter); 4691 #endif 4692 4693 return netdev_mc_count(netdev); 4694 } 4695 4696 #ifdef CONFIG_PCI_IOV 4697 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4698 { 4699 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4700 struct ixgbe_hw *hw = &adapter->hw; 4701 int i; 4702 4703 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4704 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4705 4706 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4707 hw->mac.ops.set_rar(hw, i, 4708 mac_table->addr, 4709 mac_table->pool, 4710 IXGBE_RAH_AV); 4711 else 4712 hw->mac.ops.clear_rar(hw, i); 4713 } 4714 } 4715 4716 #endif 4717 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4718 { 4719 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4720 struct ixgbe_hw *hw = &adapter->hw; 4721 int i; 4722 4723 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4724 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4725 continue; 4726 4727 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4728 4729 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4730 hw->mac.ops.set_rar(hw, i, 4731 mac_table->addr, 4732 mac_table->pool, 4733 IXGBE_RAH_AV); 4734 else 4735 hw->mac.ops.clear_rar(hw, i); 4736 } 4737 } 4738 4739 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4740 { 4741 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4742 struct ixgbe_hw *hw = &adapter->hw; 4743 int i; 4744 4745 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4746 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4747 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4748 } 4749 4750 ixgbe_sync_mac_table(adapter); 4751 } 4752 4753 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4754 { 4755 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4756 struct ixgbe_hw *hw = &adapter->hw; 4757 int i, count = 0; 4758 4759 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4760 /* do not count default RAR as available */ 4761 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4762 continue; 4763 4764 /* only count unused and addresses that belong to us */ 4765 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4766 if (mac_table->pool != pool) 4767 continue; 4768 } 4769 4770 count++; 4771 } 4772 4773 return count; 4774 } 4775 4776 /* this function destroys the first RAR entry */ 4777 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4778 { 4779 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4780 struct ixgbe_hw *hw = &adapter->hw; 4781 4782 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4783 mac_table->pool = VMDQ_P(0); 4784 4785 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4786 4787 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4788 IXGBE_RAH_AV); 4789 } 4790 4791 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4792 const u8 *addr, u16 pool) 4793 { 4794 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4795 struct ixgbe_hw *hw = &adapter->hw; 4796 int i; 4797 4798 if (is_zero_ether_addr(addr)) 4799 return -EINVAL; 4800 4801 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4802 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4803 continue; 4804 4805 ether_addr_copy(mac_table->addr, addr); 4806 mac_table->pool = pool; 4807 4808 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4809 IXGBE_MAC_STATE_IN_USE; 4810 4811 ixgbe_sync_mac_table(adapter); 4812 4813 return i; 4814 } 4815 4816 return -ENOMEM; 4817 } 4818 4819 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4820 const u8 *addr, u16 pool) 4821 { 4822 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4823 struct ixgbe_hw *hw = &adapter->hw; 4824 int i; 4825 4826 if (is_zero_ether_addr(addr)) 4827 return -EINVAL; 4828 4829 /* search table for addr, if found clear IN_USE flag and sync */ 4830 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4831 /* we can only delete an entry if it is in use */ 4832 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4833 continue; 4834 /* we only care about entries that belong to the given pool */ 4835 if (mac_table->pool != pool) 4836 continue; 4837 /* we only care about a specific MAC address */ 4838 if (!ether_addr_equal(addr, mac_table->addr)) 4839 continue; 4840 4841 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4842 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4843 4844 ixgbe_sync_mac_table(adapter); 4845 4846 return 0; 4847 } 4848 4849 return -ENOMEM; 4850 } 4851 /** 4852 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4853 * @netdev: network interface device structure 4854 * 4855 * Writes unicast address list to the RAR table. 4856 * Returns: -ENOMEM on failure/insufficient address space 4857 * 0 on no addresses written 4858 * X on writing X addresses to the RAR table 4859 **/ 4860 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4861 { 4862 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4863 int count = 0; 4864 4865 /* return ENOMEM indicating insufficient memory for addresses */ 4866 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) 4867 return -ENOMEM; 4868 4869 if (!netdev_uc_empty(netdev)) { 4870 struct netdev_hw_addr *ha; 4871 netdev_for_each_uc_addr(ha, netdev) { 4872 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4873 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4874 count++; 4875 } 4876 } 4877 return count; 4878 } 4879 4880 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4881 { 4882 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4883 int ret; 4884 4885 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4886 4887 return min_t(int, ret, 0); 4888 } 4889 4890 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4891 { 4892 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4893 4894 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4895 4896 return 0; 4897 } 4898 4899 /** 4900 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4901 * @netdev: network interface device structure 4902 * 4903 * The set_rx_method entry point is called whenever the unicast/multicast 4904 * address list or the network interface flags are updated. This routine is 4905 * responsible for configuring the hardware for proper unicast, multicast and 4906 * promiscuous mode. 4907 **/ 4908 void ixgbe_set_rx_mode(struct net_device *netdev) 4909 { 4910 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4911 struct ixgbe_hw *hw = &adapter->hw; 4912 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4913 netdev_features_t features = netdev->features; 4914 int count; 4915 4916 /* Check for Promiscuous and All Multicast modes */ 4917 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4918 4919 /* set all bits that we expect to always be set */ 4920 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4921 fctrl |= IXGBE_FCTRL_BAM; 4922 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4923 fctrl |= IXGBE_FCTRL_PMCF; 4924 4925 /* clear the bits we are changing the status of */ 4926 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4927 if (netdev->flags & IFF_PROMISC) { 4928 hw->addr_ctrl.user_set_promisc = true; 4929 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4930 vmolr |= IXGBE_VMOLR_MPE; 4931 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4932 } else { 4933 if (netdev->flags & IFF_ALLMULTI) { 4934 fctrl |= IXGBE_FCTRL_MPE; 4935 vmolr |= IXGBE_VMOLR_MPE; 4936 } 4937 hw->addr_ctrl.user_set_promisc = false; 4938 } 4939 4940 /* 4941 * Write addresses to available RAR registers, if there is not 4942 * sufficient space to store all the addresses then enable 4943 * unicast promiscuous mode 4944 */ 4945 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4946 fctrl |= IXGBE_FCTRL_UPE; 4947 vmolr |= IXGBE_VMOLR_ROPE; 4948 } 4949 4950 /* Write addresses to the MTA, if the attempt fails 4951 * then we should just turn on promiscuous mode so 4952 * that we can at least receive multicast traffic 4953 */ 4954 count = ixgbe_write_mc_addr_list(netdev); 4955 if (count < 0) { 4956 fctrl |= IXGBE_FCTRL_MPE; 4957 vmolr |= IXGBE_VMOLR_MPE; 4958 } else if (count) { 4959 vmolr |= IXGBE_VMOLR_ROMPE; 4960 } 4961 4962 if (hw->mac.type != ixgbe_mac_82598EB) { 4963 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4964 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4965 IXGBE_VMOLR_ROPE); 4966 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4967 } 4968 4969 /* This is useful for sniffing bad packets. */ 4970 if (features & NETIF_F_RXALL) { 4971 /* UPE and MPE will be handled by normal PROMISC logic 4972 * in e1000e_set_rx_mode */ 4973 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4974 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4975 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4976 4977 fctrl &= ~(IXGBE_FCTRL_DPF); 4978 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4979 } 4980 4981 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4982 4983 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4984 ixgbe_vlan_strip_enable(adapter); 4985 else 4986 ixgbe_vlan_strip_disable(adapter); 4987 4988 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4989 ixgbe_vlan_promisc_disable(adapter); 4990 else 4991 ixgbe_vlan_promisc_enable(adapter); 4992 } 4993 4994 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4995 { 4996 int q_idx; 4997 4998 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4999 napi_enable(&adapter->q_vector[q_idx]->napi); 5000 } 5001 5002 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5003 { 5004 int q_idx; 5005 5006 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5007 napi_disable(&adapter->q_vector[q_idx]->napi); 5008 } 5009 5010 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5011 { 5012 struct ixgbe_hw *hw = &adapter->hw; 5013 u32 vxlanctrl; 5014 5015 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5016 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5017 return; 5018 5019 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5020 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5021 5022 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5023 adapter->vxlan_port = 0; 5024 5025 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5026 adapter->geneve_port = 0; 5027 } 5028 5029 #ifdef CONFIG_IXGBE_DCB 5030 /** 5031 * ixgbe_configure_dcb - Configure DCB hardware 5032 * @adapter: ixgbe adapter struct 5033 * 5034 * This is called by the driver on open to configure the DCB hardware. 5035 * This is also called by the gennetlink interface when reconfiguring 5036 * the DCB state. 5037 */ 5038 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5039 { 5040 struct ixgbe_hw *hw = &adapter->hw; 5041 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5042 5043 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5044 if (hw->mac.type == ixgbe_mac_82598EB) 5045 netif_set_gso_max_size(adapter->netdev, 65536); 5046 return; 5047 } 5048 5049 if (hw->mac.type == ixgbe_mac_82598EB) 5050 netif_set_gso_max_size(adapter->netdev, 32768); 5051 5052 #ifdef IXGBE_FCOE 5053 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5054 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5055 #endif 5056 5057 /* reconfigure the hardware */ 5058 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5059 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5060 DCB_TX_CONFIG); 5061 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5062 DCB_RX_CONFIG); 5063 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5064 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5065 ixgbe_dcb_hw_ets(&adapter->hw, 5066 adapter->ixgbe_ieee_ets, 5067 max_frame); 5068 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5069 adapter->ixgbe_ieee_pfc->pfc_en, 5070 adapter->ixgbe_ieee_ets->prio_tc); 5071 } 5072 5073 /* Enable RSS Hash per TC */ 5074 if (hw->mac.type != ixgbe_mac_82598EB) { 5075 u32 msb = 0; 5076 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5077 5078 while (rss_i) { 5079 msb++; 5080 rss_i >>= 1; 5081 } 5082 5083 /* write msb to all 8 TCs in one write */ 5084 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5085 } 5086 } 5087 #endif 5088 5089 /* Additional bittime to account for IXGBE framing */ 5090 #define IXGBE_ETH_FRAMING 20 5091 5092 /** 5093 * ixgbe_hpbthresh - calculate high water mark for flow control 5094 * 5095 * @adapter: board private structure to calculate for 5096 * @pb: packet buffer to calculate 5097 */ 5098 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5099 { 5100 struct ixgbe_hw *hw = &adapter->hw; 5101 struct net_device *dev = adapter->netdev; 5102 int link, tc, kb, marker; 5103 u32 dv_id, rx_pba; 5104 5105 /* Calculate max LAN frame size */ 5106 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5107 5108 #ifdef IXGBE_FCOE 5109 /* FCoE traffic class uses FCOE jumbo frames */ 5110 if ((dev->features & NETIF_F_FCOE_MTU) && 5111 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5112 (pb == ixgbe_fcoe_get_tc(adapter))) 5113 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5114 #endif 5115 5116 /* Calculate delay value for device */ 5117 switch (hw->mac.type) { 5118 case ixgbe_mac_X540: 5119 case ixgbe_mac_X550: 5120 case ixgbe_mac_X550EM_x: 5121 case ixgbe_mac_x550em_a: 5122 dv_id = IXGBE_DV_X540(link, tc); 5123 break; 5124 default: 5125 dv_id = IXGBE_DV(link, tc); 5126 break; 5127 } 5128 5129 /* Loopback switch introduces additional latency */ 5130 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5131 dv_id += IXGBE_B2BT(tc); 5132 5133 /* Delay value is calculated in bit times convert to KB */ 5134 kb = IXGBE_BT2KB(dv_id); 5135 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5136 5137 marker = rx_pba - kb; 5138 5139 /* It is possible that the packet buffer is not large enough 5140 * to provide required headroom. In this case throw an error 5141 * to user and a do the best we can. 5142 */ 5143 if (marker < 0) { 5144 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5145 "headroom to support flow control." 5146 "Decrease MTU or number of traffic classes\n", pb); 5147 marker = tc + 1; 5148 } 5149 5150 return marker; 5151 } 5152 5153 /** 5154 * ixgbe_lpbthresh - calculate low water mark for for flow control 5155 * 5156 * @adapter: board private structure to calculate for 5157 * @pb: packet buffer to calculate 5158 */ 5159 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5160 { 5161 struct ixgbe_hw *hw = &adapter->hw; 5162 struct net_device *dev = adapter->netdev; 5163 int tc; 5164 u32 dv_id; 5165 5166 /* Calculate max LAN frame size */ 5167 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5168 5169 #ifdef IXGBE_FCOE 5170 /* FCoE traffic class uses FCOE jumbo frames */ 5171 if ((dev->features & NETIF_F_FCOE_MTU) && 5172 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5173 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5174 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5175 #endif 5176 5177 /* Calculate delay value for device */ 5178 switch (hw->mac.type) { 5179 case ixgbe_mac_X540: 5180 case ixgbe_mac_X550: 5181 case ixgbe_mac_X550EM_x: 5182 case ixgbe_mac_x550em_a: 5183 dv_id = IXGBE_LOW_DV_X540(tc); 5184 break; 5185 default: 5186 dv_id = IXGBE_LOW_DV(tc); 5187 break; 5188 } 5189 5190 /* Delay value is calculated in bit times convert to KB */ 5191 return IXGBE_BT2KB(dv_id); 5192 } 5193 5194 /* 5195 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5196 */ 5197 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5198 { 5199 struct ixgbe_hw *hw = &adapter->hw; 5200 int num_tc = netdev_get_num_tc(adapter->netdev); 5201 int i; 5202 5203 if (!num_tc) 5204 num_tc = 1; 5205 5206 for (i = 0; i < num_tc; i++) { 5207 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5208 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5209 5210 /* Low water marks must not be larger than high water marks */ 5211 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5212 hw->fc.low_water[i] = 0; 5213 } 5214 5215 for (; i < MAX_TRAFFIC_CLASS; i++) 5216 hw->fc.high_water[i] = 0; 5217 } 5218 5219 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5220 { 5221 struct ixgbe_hw *hw = &adapter->hw; 5222 int hdrm; 5223 u8 tc = netdev_get_num_tc(adapter->netdev); 5224 5225 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5226 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5227 hdrm = 32 << adapter->fdir_pballoc; 5228 else 5229 hdrm = 0; 5230 5231 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5232 ixgbe_pbthresh_setup(adapter); 5233 } 5234 5235 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5236 { 5237 struct ixgbe_hw *hw = &adapter->hw; 5238 struct hlist_node *node2; 5239 struct ixgbe_fdir_filter *filter; 5240 5241 spin_lock(&adapter->fdir_perfect_lock); 5242 5243 if (!hlist_empty(&adapter->fdir_filter_list)) 5244 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5245 5246 hlist_for_each_entry_safe(filter, node2, 5247 &adapter->fdir_filter_list, fdir_node) { 5248 ixgbe_fdir_write_perfect_filter_82599(hw, 5249 &filter->filter, 5250 filter->sw_idx, 5251 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5252 IXGBE_FDIR_DROP_QUEUE : 5253 adapter->rx_ring[filter->action]->reg_idx); 5254 } 5255 5256 spin_unlock(&adapter->fdir_perfect_lock); 5257 } 5258 5259 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 5260 struct ixgbe_adapter *adapter) 5261 { 5262 struct ixgbe_hw *hw = &adapter->hw; 5263 u32 vmolr; 5264 5265 /* No unicast promiscuous support for VMDQ devices. */ 5266 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 5267 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 5268 5269 /* clear the affected bit */ 5270 vmolr &= ~IXGBE_VMOLR_MPE; 5271 5272 if (dev->flags & IFF_ALLMULTI) { 5273 vmolr |= IXGBE_VMOLR_MPE; 5274 } else { 5275 vmolr |= IXGBE_VMOLR_ROMPE; 5276 hw->mac.ops.update_mc_addr_list(hw, dev); 5277 } 5278 ixgbe_write_uc_addr_list(adapter->netdev, pool); 5279 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 5280 } 5281 5282 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 5283 { 5284 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5285 int rss_i = adapter->num_rx_queues_per_pool; 5286 struct ixgbe_hw *hw = &adapter->hw; 5287 u16 pool = vadapter->pool; 5288 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 5289 IXGBE_PSRTYPE_UDPHDR | 5290 IXGBE_PSRTYPE_IPV4HDR | 5291 IXGBE_PSRTYPE_L2HDR | 5292 IXGBE_PSRTYPE_IPV6HDR; 5293 5294 if (hw->mac.type == ixgbe_mac_82598EB) 5295 return; 5296 5297 if (rss_i > 3) 5298 psrtype |= 2u << 29; 5299 else if (rss_i > 1) 5300 psrtype |= 1u << 29; 5301 5302 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 5303 } 5304 5305 /** 5306 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5307 * @rx_ring: ring to free buffers from 5308 **/ 5309 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5310 { 5311 u16 i = rx_ring->next_to_clean; 5312 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5313 5314 /* Free all the Rx ring sk_buffs */ 5315 while (i != rx_ring->next_to_alloc) { 5316 if (rx_buffer->skb) { 5317 struct sk_buff *skb = rx_buffer->skb; 5318 if (IXGBE_CB(skb)->page_released) 5319 dma_unmap_page_attrs(rx_ring->dev, 5320 IXGBE_CB(skb)->dma, 5321 ixgbe_rx_pg_size(rx_ring), 5322 DMA_FROM_DEVICE, 5323 IXGBE_RX_DMA_ATTR); 5324 dev_kfree_skb(skb); 5325 } 5326 5327 /* Invalidate cache lines that may have been written to by 5328 * device so that we avoid corrupting memory. 5329 */ 5330 dma_sync_single_range_for_cpu(rx_ring->dev, 5331 rx_buffer->dma, 5332 rx_buffer->page_offset, 5333 ixgbe_rx_bufsz(rx_ring), 5334 DMA_FROM_DEVICE); 5335 5336 /* free resources associated with mapping */ 5337 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5338 ixgbe_rx_pg_size(rx_ring), 5339 DMA_FROM_DEVICE, 5340 IXGBE_RX_DMA_ATTR); 5341 __page_frag_cache_drain(rx_buffer->page, 5342 rx_buffer->pagecnt_bias); 5343 5344 i++; 5345 rx_buffer++; 5346 if (i == rx_ring->count) { 5347 i = 0; 5348 rx_buffer = rx_ring->rx_buffer_info; 5349 } 5350 } 5351 5352 rx_ring->next_to_alloc = 0; 5353 rx_ring->next_to_clean = 0; 5354 rx_ring->next_to_use = 0; 5355 } 5356 5357 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 5358 struct ixgbe_ring *rx_ring) 5359 { 5360 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5361 int index = rx_ring->queue_index + vadapter->rx_base_queue; 5362 5363 /* shutdown specific queue receive and wait for dma to settle */ 5364 ixgbe_disable_rx_queue(adapter, rx_ring); 5365 usleep_range(10000, 20000); 5366 ixgbe_irq_disable_queues(adapter, BIT_ULL(index)); 5367 ixgbe_clean_rx_ring(rx_ring); 5368 rx_ring->l2_accel_priv = NULL; 5369 } 5370 5371 static int ixgbe_fwd_ring_down(struct net_device *vdev, 5372 struct ixgbe_fwd_adapter *accel) 5373 { 5374 struct ixgbe_adapter *adapter = accel->real_adapter; 5375 unsigned int rxbase = accel->rx_base_queue; 5376 unsigned int txbase = accel->tx_base_queue; 5377 int i; 5378 5379 netif_tx_stop_all_queues(vdev); 5380 5381 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5382 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5383 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 5384 } 5385 5386 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5387 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 5388 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 5389 } 5390 5391 5392 return 0; 5393 } 5394 5395 static int ixgbe_fwd_ring_up(struct net_device *vdev, 5396 struct ixgbe_fwd_adapter *accel) 5397 { 5398 struct ixgbe_adapter *adapter = accel->real_adapter; 5399 unsigned int rxbase, txbase, queues; 5400 int i, baseq, err = 0; 5401 5402 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 5403 return 0; 5404 5405 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5406 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 5407 accel->pool, adapter->num_rx_pools, 5408 baseq, baseq + adapter->num_rx_queues_per_pool, 5409 adapter->fwd_bitmask); 5410 5411 accel->netdev = vdev; 5412 accel->rx_base_queue = rxbase = baseq; 5413 accel->tx_base_queue = txbase = baseq; 5414 5415 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5416 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5417 5418 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5419 adapter->rx_ring[rxbase + i]->netdev = vdev; 5420 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 5421 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 5422 } 5423 5424 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5425 adapter->tx_ring[txbase + i]->netdev = vdev; 5426 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 5427 } 5428 5429 queues = min_t(unsigned int, 5430 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 5431 err = netif_set_real_num_tx_queues(vdev, queues); 5432 if (err) 5433 goto fwd_queue_err; 5434 5435 err = netif_set_real_num_rx_queues(vdev, queues); 5436 if (err) 5437 goto fwd_queue_err; 5438 5439 if (is_valid_ether_addr(vdev->dev_addr)) 5440 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 5441 5442 ixgbe_fwd_psrtype(accel); 5443 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 5444 return err; 5445 fwd_queue_err: 5446 ixgbe_fwd_ring_down(vdev, accel); 5447 return err; 5448 } 5449 5450 static int ixgbe_upper_dev_walk(struct net_device *upper, void *data) 5451 { 5452 if (netif_is_macvlan(upper)) { 5453 struct macvlan_dev *dfwd = netdev_priv(upper); 5454 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 5455 5456 if (dfwd->fwd_priv) 5457 ixgbe_fwd_ring_up(upper, vadapter); 5458 } 5459 5460 return 0; 5461 } 5462 5463 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5464 { 5465 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5466 ixgbe_upper_dev_walk, NULL); 5467 } 5468 5469 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5470 { 5471 struct ixgbe_hw *hw = &adapter->hw; 5472 5473 ixgbe_configure_pb(adapter); 5474 #ifdef CONFIG_IXGBE_DCB 5475 ixgbe_configure_dcb(adapter); 5476 #endif 5477 /* 5478 * We must restore virtualization before VLANs or else 5479 * the VLVF registers will not be populated 5480 */ 5481 ixgbe_configure_virtualization(adapter); 5482 5483 ixgbe_set_rx_mode(adapter->netdev); 5484 ixgbe_restore_vlan(adapter); 5485 5486 switch (hw->mac.type) { 5487 case ixgbe_mac_82599EB: 5488 case ixgbe_mac_X540: 5489 hw->mac.ops.disable_rx_buff(hw); 5490 break; 5491 default: 5492 break; 5493 } 5494 5495 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5496 ixgbe_init_fdir_signature_82599(&adapter->hw, 5497 adapter->fdir_pballoc); 5498 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5499 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5500 adapter->fdir_pballoc); 5501 ixgbe_fdir_filter_restore(adapter); 5502 } 5503 5504 switch (hw->mac.type) { 5505 case ixgbe_mac_82599EB: 5506 case ixgbe_mac_X540: 5507 hw->mac.ops.enable_rx_buff(hw); 5508 break; 5509 default: 5510 break; 5511 } 5512 5513 #ifdef CONFIG_IXGBE_DCA 5514 /* configure DCA */ 5515 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5516 ixgbe_setup_dca(adapter); 5517 #endif /* CONFIG_IXGBE_DCA */ 5518 5519 #ifdef IXGBE_FCOE 5520 /* configure FCoE L2 filters, redirection table, and Rx control */ 5521 ixgbe_configure_fcoe(adapter); 5522 5523 #endif /* IXGBE_FCOE */ 5524 ixgbe_configure_tx(adapter); 5525 ixgbe_configure_rx(adapter); 5526 ixgbe_configure_dfwd(adapter); 5527 } 5528 5529 /** 5530 * ixgbe_sfp_link_config - set up SFP+ link 5531 * @adapter: pointer to private adapter struct 5532 **/ 5533 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5534 { 5535 /* 5536 * We are assuming the worst case scenario here, and that 5537 * is that an SFP was inserted/removed after the reset 5538 * but before SFP detection was enabled. As such the best 5539 * solution is to just start searching as soon as we start 5540 */ 5541 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5542 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5543 5544 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5545 adapter->sfp_poll_time = 0; 5546 } 5547 5548 /** 5549 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5550 * @hw: pointer to private hardware struct 5551 * 5552 * Returns 0 on success, negative on failure 5553 **/ 5554 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5555 { 5556 u32 speed; 5557 bool autoneg, link_up = false; 5558 int ret = IXGBE_ERR_LINK_SETUP; 5559 5560 if (hw->mac.ops.check_link) 5561 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5562 5563 if (ret) 5564 return ret; 5565 5566 speed = hw->phy.autoneg_advertised; 5567 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5568 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5569 &autoneg); 5570 if (ret) 5571 return ret; 5572 5573 if (hw->mac.ops.setup_link) 5574 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5575 5576 return ret; 5577 } 5578 5579 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5580 { 5581 struct ixgbe_hw *hw = &adapter->hw; 5582 u32 gpie = 0; 5583 5584 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5585 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5586 IXGBE_GPIE_OCD; 5587 gpie |= IXGBE_GPIE_EIAME; 5588 /* 5589 * use EIAM to auto-mask when MSI-X interrupt is asserted 5590 * this saves a register write for every interrupt 5591 */ 5592 switch (hw->mac.type) { 5593 case ixgbe_mac_82598EB: 5594 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5595 break; 5596 case ixgbe_mac_82599EB: 5597 case ixgbe_mac_X540: 5598 case ixgbe_mac_X550: 5599 case ixgbe_mac_X550EM_x: 5600 case ixgbe_mac_x550em_a: 5601 default: 5602 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5603 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5604 break; 5605 } 5606 } else { 5607 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5608 * specifically only auto mask tx and rx interrupts */ 5609 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5610 } 5611 5612 /* XXX: to interrupt immediately for EICS writes, enable this */ 5613 /* gpie |= IXGBE_GPIE_EIMEN; */ 5614 5615 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5616 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5617 5618 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5619 case IXGBE_82599_VMDQ_8Q_MASK: 5620 gpie |= IXGBE_GPIE_VTMODE_16; 5621 break; 5622 case IXGBE_82599_VMDQ_4Q_MASK: 5623 gpie |= IXGBE_GPIE_VTMODE_32; 5624 break; 5625 default: 5626 gpie |= IXGBE_GPIE_VTMODE_64; 5627 break; 5628 } 5629 } 5630 5631 /* Enable Thermal over heat sensor interrupt */ 5632 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5633 switch (adapter->hw.mac.type) { 5634 case ixgbe_mac_82599EB: 5635 gpie |= IXGBE_SDP0_GPIEN_8259X; 5636 break; 5637 default: 5638 break; 5639 } 5640 } 5641 5642 /* Enable fan failure interrupt */ 5643 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5644 gpie |= IXGBE_SDP1_GPIEN(hw); 5645 5646 switch (hw->mac.type) { 5647 case ixgbe_mac_82599EB: 5648 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5649 break; 5650 case ixgbe_mac_X550EM_x: 5651 case ixgbe_mac_x550em_a: 5652 gpie |= IXGBE_SDP0_GPIEN_X540; 5653 break; 5654 default: 5655 break; 5656 } 5657 5658 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5659 } 5660 5661 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5662 { 5663 struct ixgbe_hw *hw = &adapter->hw; 5664 int err; 5665 u32 ctrl_ext; 5666 5667 ixgbe_get_hw_control(adapter); 5668 ixgbe_setup_gpie(adapter); 5669 5670 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5671 ixgbe_configure_msix(adapter); 5672 else 5673 ixgbe_configure_msi_and_legacy(adapter); 5674 5675 /* enable the optics for 82599 SFP+ fiber */ 5676 if (hw->mac.ops.enable_tx_laser) 5677 hw->mac.ops.enable_tx_laser(hw); 5678 5679 if (hw->phy.ops.set_phy_power) 5680 hw->phy.ops.set_phy_power(hw, true); 5681 5682 smp_mb__before_atomic(); 5683 clear_bit(__IXGBE_DOWN, &adapter->state); 5684 ixgbe_napi_enable_all(adapter); 5685 5686 if (ixgbe_is_sfp(hw)) { 5687 ixgbe_sfp_link_config(adapter); 5688 } else { 5689 err = ixgbe_non_sfp_link_config(hw); 5690 if (err) 5691 e_err(probe, "link_config FAILED %d\n", err); 5692 } 5693 5694 /* clear any pending interrupts, may auto mask */ 5695 IXGBE_READ_REG(hw, IXGBE_EICR); 5696 ixgbe_irq_enable(adapter, true, true); 5697 5698 /* 5699 * If this adapter has a fan, check to see if we had a failure 5700 * before we enabled the interrupt. 5701 */ 5702 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5703 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5704 if (esdp & IXGBE_ESDP_SDP1) 5705 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5706 } 5707 5708 /* bring the link up in the watchdog, this could race with our first 5709 * link up interrupt but shouldn't be a problem */ 5710 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5711 adapter->link_check_timeout = jiffies; 5712 mod_timer(&adapter->service_timer, jiffies); 5713 5714 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5715 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5716 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5717 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5718 } 5719 5720 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5721 { 5722 WARN_ON(in_interrupt()); 5723 /* put off any impending NetWatchDogTimeout */ 5724 netif_trans_update(adapter->netdev); 5725 5726 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5727 usleep_range(1000, 2000); 5728 if (adapter->hw.phy.type == ixgbe_phy_fw) 5729 ixgbe_watchdog_link_is_down(adapter); 5730 ixgbe_down(adapter); 5731 /* 5732 * If SR-IOV enabled then wait a bit before bringing the adapter 5733 * back up to give the VFs time to respond to the reset. The 5734 * two second wait is based upon the watchdog timer cycle in 5735 * the VF driver. 5736 */ 5737 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5738 msleep(2000); 5739 ixgbe_up(adapter); 5740 clear_bit(__IXGBE_RESETTING, &adapter->state); 5741 } 5742 5743 void ixgbe_up(struct ixgbe_adapter *adapter) 5744 { 5745 /* hardware has been reset, we need to reload some things */ 5746 ixgbe_configure(adapter); 5747 5748 ixgbe_up_complete(adapter); 5749 } 5750 5751 void ixgbe_reset(struct ixgbe_adapter *adapter) 5752 { 5753 struct ixgbe_hw *hw = &adapter->hw; 5754 struct net_device *netdev = adapter->netdev; 5755 int err; 5756 5757 if (ixgbe_removed(hw->hw_addr)) 5758 return; 5759 /* lock SFP init bit to prevent race conditions with the watchdog */ 5760 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5761 usleep_range(1000, 2000); 5762 5763 /* clear all SFP and link config related flags while holding SFP_INIT */ 5764 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5765 IXGBE_FLAG2_SFP_NEEDS_RESET); 5766 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5767 5768 err = hw->mac.ops.init_hw(hw); 5769 switch (err) { 5770 case 0: 5771 case IXGBE_ERR_SFP_NOT_PRESENT: 5772 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5773 break; 5774 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5775 e_dev_err("master disable timed out\n"); 5776 break; 5777 case IXGBE_ERR_EEPROM_VERSION: 5778 /* We are running on a pre-production device, log a warning */ 5779 e_dev_warn("This device is a pre-production adapter/LOM. " 5780 "Please be aware there may be issues associated with " 5781 "your hardware. If you are experiencing problems " 5782 "please contact your Intel or hardware " 5783 "representative who provided you with this " 5784 "hardware.\n"); 5785 break; 5786 default: 5787 e_dev_err("Hardware Error: %d\n", err); 5788 } 5789 5790 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5791 5792 /* flush entries out of MAC table */ 5793 ixgbe_flush_sw_mac_table(adapter); 5794 __dev_uc_unsync(netdev, NULL); 5795 5796 /* do not flush user set addresses */ 5797 ixgbe_mac_set_default_filter(adapter); 5798 5799 /* update SAN MAC vmdq pool selection */ 5800 if (hw->mac.san_mac_rar_index) 5801 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5802 5803 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5804 ixgbe_ptp_reset(adapter); 5805 5806 if (hw->phy.ops.set_phy_power) { 5807 if (!netif_running(adapter->netdev) && !adapter->wol) 5808 hw->phy.ops.set_phy_power(hw, false); 5809 else 5810 hw->phy.ops.set_phy_power(hw, true); 5811 } 5812 } 5813 5814 /** 5815 * ixgbe_clean_tx_ring - Free Tx Buffers 5816 * @tx_ring: ring to be cleaned 5817 **/ 5818 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5819 { 5820 u16 i = tx_ring->next_to_clean; 5821 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5822 5823 while (i != tx_ring->next_to_use) { 5824 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5825 5826 /* Free all the Tx ring sk_buffs */ 5827 if (ring_is_xdp(tx_ring)) 5828 page_frag_free(tx_buffer->data); 5829 else 5830 dev_kfree_skb_any(tx_buffer->skb); 5831 5832 /* unmap skb header data */ 5833 dma_unmap_single(tx_ring->dev, 5834 dma_unmap_addr(tx_buffer, dma), 5835 dma_unmap_len(tx_buffer, len), 5836 DMA_TO_DEVICE); 5837 5838 /* check for eop_desc to determine the end of the packet */ 5839 eop_desc = tx_buffer->next_to_watch; 5840 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5841 5842 /* unmap remaining buffers */ 5843 while (tx_desc != eop_desc) { 5844 tx_buffer++; 5845 tx_desc++; 5846 i++; 5847 if (unlikely(i == tx_ring->count)) { 5848 i = 0; 5849 tx_buffer = tx_ring->tx_buffer_info; 5850 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5851 } 5852 5853 /* unmap any remaining paged data */ 5854 if (dma_unmap_len(tx_buffer, len)) 5855 dma_unmap_page(tx_ring->dev, 5856 dma_unmap_addr(tx_buffer, dma), 5857 dma_unmap_len(tx_buffer, len), 5858 DMA_TO_DEVICE); 5859 } 5860 5861 /* move us one more past the eop_desc for start of next pkt */ 5862 tx_buffer++; 5863 i++; 5864 if (unlikely(i == tx_ring->count)) { 5865 i = 0; 5866 tx_buffer = tx_ring->tx_buffer_info; 5867 } 5868 } 5869 5870 /* reset BQL for queue */ 5871 if (!ring_is_xdp(tx_ring)) 5872 netdev_tx_reset_queue(txring_txq(tx_ring)); 5873 5874 /* reset next_to_use and next_to_clean */ 5875 tx_ring->next_to_use = 0; 5876 tx_ring->next_to_clean = 0; 5877 } 5878 5879 /** 5880 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5881 * @adapter: board private structure 5882 **/ 5883 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5884 { 5885 int i; 5886 5887 for (i = 0; i < adapter->num_rx_queues; i++) 5888 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5889 } 5890 5891 /** 5892 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5893 * @adapter: board private structure 5894 **/ 5895 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5896 { 5897 int i; 5898 5899 for (i = 0; i < adapter->num_tx_queues; i++) 5900 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5901 for (i = 0; i < adapter->num_xdp_queues; i++) 5902 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5903 } 5904 5905 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5906 { 5907 struct hlist_node *node2; 5908 struct ixgbe_fdir_filter *filter; 5909 5910 spin_lock(&adapter->fdir_perfect_lock); 5911 5912 hlist_for_each_entry_safe(filter, node2, 5913 &adapter->fdir_filter_list, fdir_node) { 5914 hlist_del(&filter->fdir_node); 5915 kfree(filter); 5916 } 5917 adapter->fdir_filter_count = 0; 5918 5919 spin_unlock(&adapter->fdir_perfect_lock); 5920 } 5921 5922 static int ixgbe_disable_macvlan(struct net_device *upper, void *data) 5923 { 5924 if (netif_is_macvlan(upper)) { 5925 struct macvlan_dev *vlan = netdev_priv(upper); 5926 5927 if (vlan->fwd_priv) { 5928 netif_tx_stop_all_queues(upper); 5929 netif_carrier_off(upper); 5930 netif_tx_disable(upper); 5931 } 5932 } 5933 5934 return 0; 5935 } 5936 5937 void ixgbe_down(struct ixgbe_adapter *adapter) 5938 { 5939 struct net_device *netdev = adapter->netdev; 5940 struct ixgbe_hw *hw = &adapter->hw; 5941 int i; 5942 5943 /* signal that we are down to the interrupt handler */ 5944 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5945 return; /* do nothing if already down */ 5946 5947 /* disable receives */ 5948 hw->mac.ops.disable_rx(hw); 5949 5950 /* disable all enabled rx queues */ 5951 for (i = 0; i < adapter->num_rx_queues; i++) 5952 /* this call also flushes the previous write */ 5953 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5954 5955 usleep_range(10000, 20000); 5956 5957 /* synchronize_sched() needed for pending XDP buffers to drain */ 5958 if (adapter->xdp_ring[0]) 5959 synchronize_sched(); 5960 netif_tx_stop_all_queues(netdev); 5961 5962 /* call carrier off first to avoid false dev_watchdog timeouts */ 5963 netif_carrier_off(netdev); 5964 netif_tx_disable(netdev); 5965 5966 /* disable any upper devices */ 5967 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5968 ixgbe_disable_macvlan, NULL); 5969 5970 ixgbe_irq_disable(adapter); 5971 5972 ixgbe_napi_disable_all(adapter); 5973 5974 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5975 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5976 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5977 5978 del_timer_sync(&adapter->service_timer); 5979 5980 if (adapter->num_vfs) { 5981 /* Clear EITR Select mapping */ 5982 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5983 5984 /* Mark all the VFs as inactive */ 5985 for (i = 0 ; i < adapter->num_vfs; i++) 5986 adapter->vfinfo[i].clear_to_send = false; 5987 5988 /* ping all the active vfs to let them know we are going down */ 5989 ixgbe_ping_all_vfs(adapter); 5990 5991 /* Disable all VFTE/VFRE TX/RX */ 5992 ixgbe_disable_tx_rx(adapter); 5993 } 5994 5995 /* disable transmits in the hardware now that interrupts are off */ 5996 for (i = 0; i < adapter->num_tx_queues; i++) { 5997 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5998 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5999 } 6000 for (i = 0; i < adapter->num_xdp_queues; i++) { 6001 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 6002 6003 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 6004 } 6005 6006 /* Disable the Tx DMA engine on 82599 and later MAC */ 6007 switch (hw->mac.type) { 6008 case ixgbe_mac_82599EB: 6009 case ixgbe_mac_X540: 6010 case ixgbe_mac_X550: 6011 case ixgbe_mac_X550EM_x: 6012 case ixgbe_mac_x550em_a: 6013 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 6014 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 6015 ~IXGBE_DMATXCTL_TE)); 6016 break; 6017 default: 6018 break; 6019 } 6020 6021 if (!pci_channel_offline(adapter->pdev)) 6022 ixgbe_reset(adapter); 6023 6024 /* power down the optics for 82599 SFP+ fiber */ 6025 if (hw->mac.ops.disable_tx_laser) 6026 hw->mac.ops.disable_tx_laser(hw); 6027 6028 ixgbe_clean_all_tx_rings(adapter); 6029 ixgbe_clean_all_rx_rings(adapter); 6030 } 6031 6032 /** 6033 * ixgbe_eee_capable - helper function to determine EEE support on X550 6034 * @adapter: board private structure 6035 */ 6036 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6037 { 6038 struct ixgbe_hw *hw = &adapter->hw; 6039 6040 switch (hw->device_id) { 6041 case IXGBE_DEV_ID_X550EM_A_1G_T: 6042 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6043 if (!hw->phy.eee_speeds_supported) 6044 break; 6045 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6046 if (!hw->phy.eee_speeds_advertised) 6047 break; 6048 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6049 break; 6050 default: 6051 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6052 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6053 break; 6054 } 6055 } 6056 6057 /** 6058 * ixgbe_tx_timeout - Respond to a Tx Hang 6059 * @netdev: network interface device structure 6060 **/ 6061 static void ixgbe_tx_timeout(struct net_device *netdev) 6062 { 6063 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6064 6065 /* Do the reset outside of interrupt context */ 6066 ixgbe_tx_timeout_reset(adapter); 6067 } 6068 6069 #ifdef CONFIG_IXGBE_DCB 6070 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6071 { 6072 struct ixgbe_hw *hw = &adapter->hw; 6073 struct tc_configuration *tc; 6074 int j; 6075 6076 switch (hw->mac.type) { 6077 case ixgbe_mac_82598EB: 6078 case ixgbe_mac_82599EB: 6079 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6080 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6081 break; 6082 case ixgbe_mac_X540: 6083 case ixgbe_mac_X550: 6084 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6085 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6086 break; 6087 case ixgbe_mac_X550EM_x: 6088 case ixgbe_mac_x550em_a: 6089 default: 6090 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6091 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6092 break; 6093 } 6094 6095 /* Configure DCB traffic classes */ 6096 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6097 tc = &adapter->dcb_cfg.tc_config[j]; 6098 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6099 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6100 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6101 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6102 tc->dcb_pfc = pfc_disabled; 6103 } 6104 6105 /* Initialize default user to priority mapping, UPx->TC0 */ 6106 tc = &adapter->dcb_cfg.tc_config[0]; 6107 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6108 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6109 6110 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6111 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6112 adapter->dcb_cfg.pfc_mode_enable = false; 6113 adapter->dcb_set_bitmap = 0x00; 6114 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6115 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6116 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6117 sizeof(adapter->temp_dcb_cfg)); 6118 } 6119 #endif 6120 6121 /** 6122 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6123 * @adapter: board private structure to initialize 6124 * 6125 * ixgbe_sw_init initializes the Adapter private data structure. 6126 * Fields are initialized based on PCI device information and 6127 * OS network device settings (MTU size). 6128 **/ 6129 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6130 const struct ixgbe_info *ii) 6131 { 6132 struct ixgbe_hw *hw = &adapter->hw; 6133 struct pci_dev *pdev = adapter->pdev; 6134 unsigned int rss, fdir; 6135 u32 fwsm; 6136 int i; 6137 6138 /* PCI config space info */ 6139 6140 hw->vendor_id = pdev->vendor; 6141 hw->device_id = pdev->device; 6142 hw->revision_id = pdev->revision; 6143 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6144 hw->subsystem_device_id = pdev->subsystem_device; 6145 6146 /* get_invariants needs the device IDs */ 6147 ii->get_invariants(hw); 6148 6149 /* Set common capability flags and settings */ 6150 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6151 adapter->ring_feature[RING_F_RSS].limit = rss; 6152 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6153 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6154 adapter->atr_sample_rate = 20; 6155 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6156 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6157 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6158 #ifdef CONFIG_IXGBE_DCA 6159 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6160 #endif 6161 #ifdef CONFIG_IXGBE_DCB 6162 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6163 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6164 #endif 6165 #ifdef IXGBE_FCOE 6166 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6167 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6168 #ifdef CONFIG_IXGBE_DCB 6169 /* Default traffic class to use for FCoE */ 6170 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6171 #endif /* CONFIG_IXGBE_DCB */ 6172 #endif /* IXGBE_FCOE */ 6173 6174 /* initialize static ixgbe jump table entries */ 6175 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6176 GFP_KERNEL); 6177 if (!adapter->jump_tables[0]) 6178 return -ENOMEM; 6179 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6180 6181 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6182 adapter->jump_tables[i] = NULL; 6183 6184 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6185 hw->mac.num_rar_entries, 6186 GFP_ATOMIC); 6187 if (!adapter->mac_table) 6188 return -ENOMEM; 6189 6190 if (ixgbe_init_rss_key(adapter)) 6191 return -ENOMEM; 6192 6193 /* Set MAC specific capability flags and exceptions */ 6194 switch (hw->mac.type) { 6195 case ixgbe_mac_82598EB: 6196 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6197 6198 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6199 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6200 6201 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6202 adapter->ring_feature[RING_F_FDIR].limit = 0; 6203 adapter->atr_sample_rate = 0; 6204 adapter->fdir_pballoc = 0; 6205 #ifdef IXGBE_FCOE 6206 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6207 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6208 #ifdef CONFIG_IXGBE_DCB 6209 adapter->fcoe.up = 0; 6210 #endif /* IXGBE_DCB */ 6211 #endif /* IXGBE_FCOE */ 6212 break; 6213 case ixgbe_mac_82599EB: 6214 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6215 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6216 break; 6217 case ixgbe_mac_X540: 6218 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6219 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6220 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6221 break; 6222 case ixgbe_mac_x550em_a: 6223 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6224 switch (hw->device_id) { 6225 case IXGBE_DEV_ID_X550EM_A_1G_T: 6226 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6227 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6228 break; 6229 default: 6230 break; 6231 } 6232 /* fall through */ 6233 case ixgbe_mac_X550EM_x: 6234 #ifdef CONFIG_IXGBE_DCB 6235 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6236 #endif 6237 #ifdef IXGBE_FCOE 6238 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6239 #ifdef CONFIG_IXGBE_DCB 6240 adapter->fcoe.up = 0; 6241 #endif /* IXGBE_DCB */ 6242 #endif /* IXGBE_FCOE */ 6243 /* Fall Through */ 6244 case ixgbe_mac_X550: 6245 if (hw->mac.type == ixgbe_mac_X550) 6246 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6247 #ifdef CONFIG_IXGBE_DCA 6248 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6249 #endif 6250 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6251 break; 6252 default: 6253 break; 6254 } 6255 6256 #ifdef IXGBE_FCOE 6257 /* FCoE support exists, always init the FCoE lock */ 6258 spin_lock_init(&adapter->fcoe.lock); 6259 6260 #endif 6261 /* n-tuple support exists, always init our spinlock */ 6262 spin_lock_init(&adapter->fdir_perfect_lock); 6263 6264 #ifdef CONFIG_IXGBE_DCB 6265 ixgbe_init_dcb(adapter); 6266 #endif 6267 6268 /* default flow control settings */ 6269 hw->fc.requested_mode = ixgbe_fc_full; 6270 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6271 ixgbe_pbthresh_setup(adapter); 6272 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6273 hw->fc.send_xon = true; 6274 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6275 6276 #ifdef CONFIG_PCI_IOV 6277 if (max_vfs > 0) 6278 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6279 6280 /* assign number of SR-IOV VFs */ 6281 if (hw->mac.type != ixgbe_mac_82598EB) { 6282 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6283 max_vfs = 0; 6284 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6285 } 6286 } 6287 #endif /* CONFIG_PCI_IOV */ 6288 6289 /* enable itr by default in dynamic mode */ 6290 adapter->rx_itr_setting = 1; 6291 adapter->tx_itr_setting = 1; 6292 6293 /* set default ring sizes */ 6294 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6295 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6296 6297 /* set default work limits */ 6298 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6299 6300 /* initialize eeprom parameters */ 6301 if (ixgbe_init_eeprom_params_generic(hw)) { 6302 e_dev_err("EEPROM initialization failed\n"); 6303 return -EIO; 6304 } 6305 6306 /* PF holds first pool slot */ 6307 set_bit(0, &adapter->fwd_bitmask); 6308 set_bit(__IXGBE_DOWN, &adapter->state); 6309 6310 return 0; 6311 } 6312 6313 /** 6314 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6315 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6316 * 6317 * Return 0 on success, negative on failure 6318 **/ 6319 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6320 { 6321 struct device *dev = tx_ring->dev; 6322 int orig_node = dev_to_node(dev); 6323 int ring_node = -1; 6324 int size; 6325 6326 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6327 6328 if (tx_ring->q_vector) 6329 ring_node = tx_ring->q_vector->numa_node; 6330 6331 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6332 if (!tx_ring->tx_buffer_info) 6333 tx_ring->tx_buffer_info = vmalloc(size); 6334 if (!tx_ring->tx_buffer_info) 6335 goto err; 6336 6337 /* round up to nearest 4K */ 6338 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6339 tx_ring->size = ALIGN(tx_ring->size, 4096); 6340 6341 set_dev_node(dev, ring_node); 6342 tx_ring->desc = dma_alloc_coherent(dev, 6343 tx_ring->size, 6344 &tx_ring->dma, 6345 GFP_KERNEL); 6346 set_dev_node(dev, orig_node); 6347 if (!tx_ring->desc) 6348 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6349 &tx_ring->dma, GFP_KERNEL); 6350 if (!tx_ring->desc) 6351 goto err; 6352 6353 tx_ring->next_to_use = 0; 6354 tx_ring->next_to_clean = 0; 6355 return 0; 6356 6357 err: 6358 vfree(tx_ring->tx_buffer_info); 6359 tx_ring->tx_buffer_info = NULL; 6360 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6361 return -ENOMEM; 6362 } 6363 6364 /** 6365 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6366 * @adapter: board private structure 6367 * 6368 * If this function returns with an error, then it's possible one or 6369 * more of the rings is populated (while the rest are not). It is the 6370 * callers duty to clean those orphaned rings. 6371 * 6372 * Return 0 on success, negative on failure 6373 **/ 6374 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6375 { 6376 int i, j = 0, err = 0; 6377 6378 for (i = 0; i < adapter->num_tx_queues; i++) { 6379 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6380 if (!err) 6381 continue; 6382 6383 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6384 goto err_setup_tx; 6385 } 6386 for (j = 0; j < adapter->num_xdp_queues; j++) { 6387 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6388 if (!err) 6389 continue; 6390 6391 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6392 goto err_setup_tx; 6393 } 6394 6395 return 0; 6396 err_setup_tx: 6397 /* rewind the index freeing the rings as we go */ 6398 while (j--) 6399 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6400 while (i--) 6401 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6402 return err; 6403 } 6404 6405 /** 6406 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6407 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6408 * 6409 * Returns 0 on success, negative on failure 6410 **/ 6411 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6412 struct ixgbe_ring *rx_ring) 6413 { 6414 struct device *dev = rx_ring->dev; 6415 int orig_node = dev_to_node(dev); 6416 int ring_node = -1; 6417 int size; 6418 6419 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6420 6421 if (rx_ring->q_vector) 6422 ring_node = rx_ring->q_vector->numa_node; 6423 6424 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6425 if (!rx_ring->rx_buffer_info) 6426 rx_ring->rx_buffer_info = vmalloc(size); 6427 if (!rx_ring->rx_buffer_info) 6428 goto err; 6429 6430 /* Round up to nearest 4K */ 6431 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6432 rx_ring->size = ALIGN(rx_ring->size, 4096); 6433 6434 set_dev_node(dev, ring_node); 6435 rx_ring->desc = dma_alloc_coherent(dev, 6436 rx_ring->size, 6437 &rx_ring->dma, 6438 GFP_KERNEL); 6439 set_dev_node(dev, orig_node); 6440 if (!rx_ring->desc) 6441 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6442 &rx_ring->dma, GFP_KERNEL); 6443 if (!rx_ring->desc) 6444 goto err; 6445 6446 rx_ring->next_to_clean = 0; 6447 rx_ring->next_to_use = 0; 6448 6449 /* XDP RX-queue info */ 6450 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6451 rx_ring->queue_index) < 0) 6452 goto err; 6453 6454 rx_ring->xdp_prog = adapter->xdp_prog; 6455 6456 return 0; 6457 err: 6458 vfree(rx_ring->rx_buffer_info); 6459 rx_ring->rx_buffer_info = NULL; 6460 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6461 return -ENOMEM; 6462 } 6463 6464 /** 6465 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6466 * @adapter: board private structure 6467 * 6468 * If this function returns with an error, then it's possible one or 6469 * more of the rings is populated (while the rest are not). It is the 6470 * callers duty to clean those orphaned rings. 6471 * 6472 * Return 0 on success, negative on failure 6473 **/ 6474 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6475 { 6476 int i, err = 0; 6477 6478 for (i = 0; i < adapter->num_rx_queues; i++) { 6479 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6480 if (!err) 6481 continue; 6482 6483 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6484 goto err_setup_rx; 6485 } 6486 6487 #ifdef IXGBE_FCOE 6488 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6489 if (!err) 6490 #endif 6491 return 0; 6492 err_setup_rx: 6493 /* rewind the index freeing the rings as we go */ 6494 while (i--) 6495 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6496 return err; 6497 } 6498 6499 /** 6500 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6501 * @tx_ring: Tx descriptor ring for a specific queue 6502 * 6503 * Free all transmit software resources 6504 **/ 6505 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6506 { 6507 ixgbe_clean_tx_ring(tx_ring); 6508 6509 vfree(tx_ring->tx_buffer_info); 6510 tx_ring->tx_buffer_info = NULL; 6511 6512 /* if not set, then don't free */ 6513 if (!tx_ring->desc) 6514 return; 6515 6516 dma_free_coherent(tx_ring->dev, tx_ring->size, 6517 tx_ring->desc, tx_ring->dma); 6518 6519 tx_ring->desc = NULL; 6520 } 6521 6522 /** 6523 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6524 * @adapter: board private structure 6525 * 6526 * Free all transmit software resources 6527 **/ 6528 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6529 { 6530 int i; 6531 6532 for (i = 0; i < adapter->num_tx_queues; i++) 6533 if (adapter->tx_ring[i]->desc) 6534 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6535 for (i = 0; i < adapter->num_xdp_queues; i++) 6536 if (adapter->xdp_ring[i]->desc) 6537 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6538 } 6539 6540 /** 6541 * ixgbe_free_rx_resources - Free Rx Resources 6542 * @rx_ring: ring to clean the resources from 6543 * 6544 * Free all receive software resources 6545 **/ 6546 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6547 { 6548 ixgbe_clean_rx_ring(rx_ring); 6549 6550 rx_ring->xdp_prog = NULL; 6551 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6552 vfree(rx_ring->rx_buffer_info); 6553 rx_ring->rx_buffer_info = NULL; 6554 6555 /* if not set, then don't free */ 6556 if (!rx_ring->desc) 6557 return; 6558 6559 dma_free_coherent(rx_ring->dev, rx_ring->size, 6560 rx_ring->desc, rx_ring->dma); 6561 6562 rx_ring->desc = NULL; 6563 } 6564 6565 /** 6566 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6567 * @adapter: board private structure 6568 * 6569 * Free all receive software resources 6570 **/ 6571 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6572 { 6573 int i; 6574 6575 #ifdef IXGBE_FCOE 6576 ixgbe_free_fcoe_ddp_resources(adapter); 6577 6578 #endif 6579 for (i = 0; i < adapter->num_rx_queues; i++) 6580 if (adapter->rx_ring[i]->desc) 6581 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6582 } 6583 6584 /** 6585 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6586 * @netdev: network interface device structure 6587 * @new_mtu: new value for maximum frame size 6588 * 6589 * Returns 0 on success, negative on failure 6590 **/ 6591 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6592 { 6593 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6594 6595 /* 6596 * For 82599EB we cannot allow legacy VFs to enable their receive 6597 * paths when MTU greater than 1500 is configured. So display a 6598 * warning that legacy VFs will be disabled. 6599 */ 6600 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6601 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6602 (new_mtu > ETH_DATA_LEN)) 6603 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6604 6605 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6606 6607 /* must set new MTU before calling down or up */ 6608 netdev->mtu = new_mtu; 6609 6610 if (netif_running(netdev)) 6611 ixgbe_reinit_locked(adapter); 6612 6613 return 0; 6614 } 6615 6616 /** 6617 * ixgbe_open - Called when a network interface is made active 6618 * @netdev: network interface device structure 6619 * 6620 * Returns 0 on success, negative value on failure 6621 * 6622 * The open entry point is called when a network interface is made 6623 * active by the system (IFF_UP). At this point all resources needed 6624 * for transmit and receive operations are allocated, the interrupt 6625 * handler is registered with the OS, the watchdog timer is started, 6626 * and the stack is notified that the interface is ready. 6627 **/ 6628 int ixgbe_open(struct net_device *netdev) 6629 { 6630 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6631 struct ixgbe_hw *hw = &adapter->hw; 6632 int err, queues; 6633 6634 /* disallow open during test */ 6635 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6636 return -EBUSY; 6637 6638 netif_carrier_off(netdev); 6639 6640 /* allocate transmit descriptors */ 6641 err = ixgbe_setup_all_tx_resources(adapter); 6642 if (err) 6643 goto err_setup_tx; 6644 6645 /* allocate receive descriptors */ 6646 err = ixgbe_setup_all_rx_resources(adapter); 6647 if (err) 6648 goto err_setup_rx; 6649 6650 ixgbe_configure(adapter); 6651 6652 err = ixgbe_request_irq(adapter); 6653 if (err) 6654 goto err_req_irq; 6655 6656 /* Notify the stack of the actual queue counts. */ 6657 if (adapter->num_rx_pools > 1) 6658 queues = adapter->num_rx_queues_per_pool; 6659 else 6660 queues = adapter->num_tx_queues; 6661 6662 err = netif_set_real_num_tx_queues(netdev, queues); 6663 if (err) 6664 goto err_set_queues; 6665 6666 if (adapter->num_rx_pools > 1 && 6667 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 6668 queues = IXGBE_MAX_L2A_QUEUES; 6669 else 6670 queues = adapter->num_rx_queues; 6671 err = netif_set_real_num_rx_queues(netdev, queues); 6672 if (err) 6673 goto err_set_queues; 6674 6675 ixgbe_ptp_init(adapter); 6676 6677 ixgbe_up_complete(adapter); 6678 6679 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6680 udp_tunnel_get_rx_info(netdev); 6681 6682 return 0; 6683 6684 err_set_queues: 6685 ixgbe_free_irq(adapter); 6686 err_req_irq: 6687 ixgbe_free_all_rx_resources(adapter); 6688 if (hw->phy.ops.set_phy_power && !adapter->wol) 6689 hw->phy.ops.set_phy_power(&adapter->hw, false); 6690 err_setup_rx: 6691 ixgbe_free_all_tx_resources(adapter); 6692 err_setup_tx: 6693 ixgbe_reset(adapter); 6694 6695 return err; 6696 } 6697 6698 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6699 { 6700 ixgbe_ptp_suspend(adapter); 6701 6702 if (adapter->hw.phy.ops.enter_lplu) { 6703 adapter->hw.phy.reset_disable = true; 6704 ixgbe_down(adapter); 6705 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6706 adapter->hw.phy.reset_disable = false; 6707 } else { 6708 ixgbe_down(adapter); 6709 } 6710 6711 ixgbe_free_irq(adapter); 6712 6713 ixgbe_free_all_tx_resources(adapter); 6714 ixgbe_free_all_rx_resources(adapter); 6715 } 6716 6717 /** 6718 * ixgbe_close - Disables a network interface 6719 * @netdev: network interface device structure 6720 * 6721 * Returns 0, this is not allowed to fail 6722 * 6723 * The close entry point is called when an interface is de-activated 6724 * by the OS. The hardware is still under the drivers control, but 6725 * needs to be disabled. A global MAC reset is issued to stop the 6726 * hardware, and all transmit and receive resources are freed. 6727 **/ 6728 int ixgbe_close(struct net_device *netdev) 6729 { 6730 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6731 6732 ixgbe_ptp_stop(adapter); 6733 6734 if (netif_device_present(netdev)) 6735 ixgbe_close_suspend(adapter); 6736 6737 ixgbe_fdir_filter_exit(adapter); 6738 6739 ixgbe_release_hw_control(adapter); 6740 6741 return 0; 6742 } 6743 6744 #ifdef CONFIG_PM 6745 static int ixgbe_resume(struct pci_dev *pdev) 6746 { 6747 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6748 struct net_device *netdev = adapter->netdev; 6749 u32 err; 6750 6751 adapter->hw.hw_addr = adapter->io_addr; 6752 pci_set_power_state(pdev, PCI_D0); 6753 pci_restore_state(pdev); 6754 /* 6755 * pci_restore_state clears dev->state_saved so call 6756 * pci_save_state to restore it. 6757 */ 6758 pci_save_state(pdev); 6759 6760 err = pci_enable_device_mem(pdev); 6761 if (err) { 6762 e_dev_err("Cannot enable PCI device from suspend\n"); 6763 return err; 6764 } 6765 smp_mb__before_atomic(); 6766 clear_bit(__IXGBE_DISABLED, &adapter->state); 6767 pci_set_master(pdev); 6768 6769 pci_wake_from_d3(pdev, false); 6770 6771 ixgbe_reset(adapter); 6772 6773 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6774 6775 rtnl_lock(); 6776 err = ixgbe_init_interrupt_scheme(adapter); 6777 if (!err && netif_running(netdev)) 6778 err = ixgbe_open(netdev); 6779 6780 6781 if (!err) 6782 netif_device_attach(netdev); 6783 rtnl_unlock(); 6784 6785 return err; 6786 } 6787 #endif /* CONFIG_PM */ 6788 6789 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6790 { 6791 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6792 struct net_device *netdev = adapter->netdev; 6793 struct ixgbe_hw *hw = &adapter->hw; 6794 u32 ctrl, fctrl; 6795 u32 wufc = adapter->wol; 6796 #ifdef CONFIG_PM 6797 int retval = 0; 6798 #endif 6799 6800 rtnl_lock(); 6801 netif_device_detach(netdev); 6802 6803 if (netif_running(netdev)) 6804 ixgbe_close_suspend(adapter); 6805 6806 ixgbe_clear_interrupt_scheme(adapter); 6807 rtnl_unlock(); 6808 6809 #ifdef CONFIG_PM 6810 retval = pci_save_state(pdev); 6811 if (retval) 6812 return retval; 6813 6814 #endif 6815 if (hw->mac.ops.stop_link_on_d3) 6816 hw->mac.ops.stop_link_on_d3(hw); 6817 6818 if (wufc) { 6819 ixgbe_set_rx_mode(netdev); 6820 6821 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6822 if (hw->mac.ops.enable_tx_laser) 6823 hw->mac.ops.enable_tx_laser(hw); 6824 6825 /* turn on all-multi mode if wake on multicast is enabled */ 6826 if (wufc & IXGBE_WUFC_MC) { 6827 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6828 fctrl |= IXGBE_FCTRL_MPE; 6829 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6830 } 6831 6832 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6833 ctrl |= IXGBE_CTRL_GIO_DIS; 6834 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6835 6836 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6837 } else { 6838 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6839 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6840 } 6841 6842 switch (hw->mac.type) { 6843 case ixgbe_mac_82598EB: 6844 pci_wake_from_d3(pdev, false); 6845 break; 6846 case ixgbe_mac_82599EB: 6847 case ixgbe_mac_X540: 6848 case ixgbe_mac_X550: 6849 case ixgbe_mac_X550EM_x: 6850 case ixgbe_mac_x550em_a: 6851 pci_wake_from_d3(pdev, !!wufc); 6852 break; 6853 default: 6854 break; 6855 } 6856 6857 *enable_wake = !!wufc; 6858 if (hw->phy.ops.set_phy_power && !*enable_wake) 6859 hw->phy.ops.set_phy_power(hw, false); 6860 6861 ixgbe_release_hw_control(adapter); 6862 6863 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6864 pci_disable_device(pdev); 6865 6866 return 0; 6867 } 6868 6869 #ifdef CONFIG_PM 6870 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6871 { 6872 int retval; 6873 bool wake; 6874 6875 retval = __ixgbe_shutdown(pdev, &wake); 6876 if (retval) 6877 return retval; 6878 6879 if (wake) { 6880 pci_prepare_to_sleep(pdev); 6881 } else { 6882 pci_wake_from_d3(pdev, false); 6883 pci_set_power_state(pdev, PCI_D3hot); 6884 } 6885 6886 return 0; 6887 } 6888 #endif /* CONFIG_PM */ 6889 6890 static void ixgbe_shutdown(struct pci_dev *pdev) 6891 { 6892 bool wake; 6893 6894 __ixgbe_shutdown(pdev, &wake); 6895 6896 if (system_state == SYSTEM_POWER_OFF) { 6897 pci_wake_from_d3(pdev, wake); 6898 pci_set_power_state(pdev, PCI_D3hot); 6899 } 6900 } 6901 6902 /** 6903 * ixgbe_update_stats - Update the board statistics counters. 6904 * @adapter: board private structure 6905 **/ 6906 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6907 { 6908 struct net_device *netdev = adapter->netdev; 6909 struct ixgbe_hw *hw = &adapter->hw; 6910 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6911 u64 total_mpc = 0; 6912 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6913 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6914 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6915 u64 alloc_rx_page = 0; 6916 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6917 6918 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6919 test_bit(__IXGBE_RESETTING, &adapter->state)) 6920 return; 6921 6922 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6923 u64 rsc_count = 0; 6924 u64 rsc_flush = 0; 6925 for (i = 0; i < adapter->num_rx_queues; i++) { 6926 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6927 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6928 } 6929 adapter->rsc_total_count = rsc_count; 6930 adapter->rsc_total_flush = rsc_flush; 6931 } 6932 6933 for (i = 0; i < adapter->num_rx_queues; i++) { 6934 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6935 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6936 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 6937 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6938 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6939 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6940 bytes += rx_ring->stats.bytes; 6941 packets += rx_ring->stats.packets; 6942 } 6943 adapter->non_eop_descs = non_eop_descs; 6944 adapter->alloc_rx_page = alloc_rx_page; 6945 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6946 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6947 adapter->hw_csum_rx_error = hw_csum_rx_error; 6948 netdev->stats.rx_bytes = bytes; 6949 netdev->stats.rx_packets = packets; 6950 6951 bytes = 0; 6952 packets = 0; 6953 /* gather some stats to the adapter struct that are per queue */ 6954 for (i = 0; i < adapter->num_tx_queues; i++) { 6955 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6956 restart_queue += tx_ring->tx_stats.restart_queue; 6957 tx_busy += tx_ring->tx_stats.tx_busy; 6958 bytes += tx_ring->stats.bytes; 6959 packets += tx_ring->stats.packets; 6960 } 6961 for (i = 0; i < adapter->num_xdp_queues; i++) { 6962 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6963 6964 restart_queue += xdp_ring->tx_stats.restart_queue; 6965 tx_busy += xdp_ring->tx_stats.tx_busy; 6966 bytes += xdp_ring->stats.bytes; 6967 packets += xdp_ring->stats.packets; 6968 } 6969 adapter->restart_queue = restart_queue; 6970 adapter->tx_busy = tx_busy; 6971 netdev->stats.tx_bytes = bytes; 6972 netdev->stats.tx_packets = packets; 6973 6974 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6975 6976 /* 8 register reads */ 6977 for (i = 0; i < 8; i++) { 6978 /* for packet buffers not used, the register should read 0 */ 6979 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6980 missed_rx += mpc; 6981 hwstats->mpc[i] += mpc; 6982 total_mpc += hwstats->mpc[i]; 6983 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6984 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6985 switch (hw->mac.type) { 6986 case ixgbe_mac_82598EB: 6987 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6988 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6989 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6990 hwstats->pxonrxc[i] += 6991 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6992 break; 6993 case ixgbe_mac_82599EB: 6994 case ixgbe_mac_X540: 6995 case ixgbe_mac_X550: 6996 case ixgbe_mac_X550EM_x: 6997 case ixgbe_mac_x550em_a: 6998 hwstats->pxonrxc[i] += 6999 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7000 break; 7001 default: 7002 break; 7003 } 7004 } 7005 7006 /*16 register reads */ 7007 for (i = 0; i < 16; i++) { 7008 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7009 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7010 if ((hw->mac.type == ixgbe_mac_82599EB) || 7011 (hw->mac.type == ixgbe_mac_X540) || 7012 (hw->mac.type == ixgbe_mac_X550) || 7013 (hw->mac.type == ixgbe_mac_X550EM_x) || 7014 (hw->mac.type == ixgbe_mac_x550em_a)) { 7015 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7016 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7017 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7018 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7019 } 7020 } 7021 7022 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7023 /* work around hardware counting issue */ 7024 hwstats->gprc -= missed_rx; 7025 7026 ixgbe_update_xoff_received(adapter); 7027 7028 /* 82598 hardware only has a 32 bit counter in the high register */ 7029 switch (hw->mac.type) { 7030 case ixgbe_mac_82598EB: 7031 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7032 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7033 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7034 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7035 break; 7036 case ixgbe_mac_X540: 7037 case ixgbe_mac_X550: 7038 case ixgbe_mac_X550EM_x: 7039 case ixgbe_mac_x550em_a: 7040 /* OS2BMC stats are X540 and later */ 7041 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7042 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7043 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7044 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7045 /* fall through */ 7046 case ixgbe_mac_82599EB: 7047 for (i = 0; i < 16; i++) 7048 adapter->hw_rx_no_dma_resources += 7049 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7050 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7051 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7052 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7053 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7054 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7055 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7056 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7057 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7058 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7059 #ifdef IXGBE_FCOE 7060 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7061 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7062 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7063 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7064 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7065 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7066 /* Add up per cpu counters for total ddp aloc fail */ 7067 if (adapter->fcoe.ddp_pool) { 7068 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7069 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7070 unsigned int cpu; 7071 u64 noddp = 0, noddp_ext_buff = 0; 7072 for_each_possible_cpu(cpu) { 7073 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7074 noddp += ddp_pool->noddp; 7075 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7076 } 7077 hwstats->fcoe_noddp = noddp; 7078 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7079 } 7080 #endif /* IXGBE_FCOE */ 7081 break; 7082 default: 7083 break; 7084 } 7085 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7086 hwstats->bprc += bprc; 7087 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7088 if (hw->mac.type == ixgbe_mac_82598EB) 7089 hwstats->mprc -= bprc; 7090 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7091 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7092 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7093 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7094 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7095 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7096 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7097 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7098 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7099 hwstats->lxontxc += lxon; 7100 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7101 hwstats->lxofftxc += lxoff; 7102 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7103 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7104 /* 7105 * 82598 errata - tx of flow control packets is included in tx counters 7106 */ 7107 xon_off_tot = lxon + lxoff; 7108 hwstats->gptc -= xon_off_tot; 7109 hwstats->mptc -= xon_off_tot; 7110 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7111 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7112 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7113 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7114 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7115 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7116 hwstats->ptc64 -= xon_off_tot; 7117 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7118 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7119 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7120 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7121 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7122 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7123 7124 /* Fill out the OS statistics structure */ 7125 netdev->stats.multicast = hwstats->mprc; 7126 7127 /* Rx Errors */ 7128 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7129 netdev->stats.rx_dropped = 0; 7130 netdev->stats.rx_length_errors = hwstats->rlec; 7131 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7132 netdev->stats.rx_missed_errors = total_mpc; 7133 } 7134 7135 /** 7136 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7137 * @adapter: pointer to the device adapter structure 7138 **/ 7139 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7140 { 7141 struct ixgbe_hw *hw = &adapter->hw; 7142 int i; 7143 7144 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7145 return; 7146 7147 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7148 7149 /* if interface is down do nothing */ 7150 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7151 return; 7152 7153 /* do nothing if we are not using signature filters */ 7154 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7155 return; 7156 7157 adapter->fdir_overflow++; 7158 7159 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7160 for (i = 0; i < adapter->num_tx_queues; i++) 7161 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7162 &(adapter->tx_ring[i]->state)); 7163 for (i = 0; i < adapter->num_xdp_queues; i++) 7164 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7165 &adapter->xdp_ring[i]->state); 7166 /* re-enable flow director interrupts */ 7167 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7168 } else { 7169 e_err(probe, "failed to finish FDIR re-initialization, " 7170 "ignored adding FDIR ATR filters\n"); 7171 } 7172 } 7173 7174 /** 7175 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7176 * @adapter: pointer to the device adapter structure 7177 * 7178 * This function serves two purposes. First it strobes the interrupt lines 7179 * in order to make certain interrupts are occurring. Secondly it sets the 7180 * bits needed to check for TX hangs. As a result we should immediately 7181 * determine if a hang has occurred. 7182 */ 7183 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7184 { 7185 struct ixgbe_hw *hw = &adapter->hw; 7186 u64 eics = 0; 7187 int i; 7188 7189 /* If we're down, removing or resetting, just bail */ 7190 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7191 test_bit(__IXGBE_REMOVING, &adapter->state) || 7192 test_bit(__IXGBE_RESETTING, &adapter->state)) 7193 return; 7194 7195 /* Force detection of hung controller */ 7196 if (netif_carrier_ok(adapter->netdev)) { 7197 for (i = 0; i < adapter->num_tx_queues; i++) 7198 set_check_for_tx_hang(adapter->tx_ring[i]); 7199 for (i = 0; i < adapter->num_xdp_queues; i++) 7200 set_check_for_tx_hang(adapter->xdp_ring[i]); 7201 } 7202 7203 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7204 /* 7205 * for legacy and MSI interrupts don't set any bits 7206 * that are enabled for EIAM, because this operation 7207 * would set *both* EIMS and EICS for any bit in EIAM 7208 */ 7209 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7210 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7211 } else { 7212 /* get one bit for every active tx/rx interrupt vector */ 7213 for (i = 0; i < adapter->num_q_vectors; i++) { 7214 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7215 if (qv->rx.ring || qv->tx.ring) 7216 eics |= BIT_ULL(i); 7217 } 7218 } 7219 7220 /* Cause software interrupt to ensure rings are cleaned */ 7221 ixgbe_irq_rearm_queues(adapter, eics); 7222 } 7223 7224 /** 7225 * ixgbe_watchdog_update_link - update the link status 7226 * @adapter: pointer to the device adapter structure 7227 * @link_speed: pointer to a u32 to store the link_speed 7228 **/ 7229 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7230 { 7231 struct ixgbe_hw *hw = &adapter->hw; 7232 u32 link_speed = adapter->link_speed; 7233 bool link_up = adapter->link_up; 7234 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7235 7236 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7237 return; 7238 7239 if (hw->mac.ops.check_link) { 7240 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7241 } else { 7242 /* always assume link is up, if no check link function */ 7243 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7244 link_up = true; 7245 } 7246 7247 if (adapter->ixgbe_ieee_pfc) 7248 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7249 7250 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7251 hw->mac.ops.fc_enable(hw); 7252 ixgbe_set_rx_drop_en(adapter); 7253 } 7254 7255 if (link_up || 7256 time_after(jiffies, (adapter->link_check_timeout + 7257 IXGBE_TRY_LINK_TIMEOUT))) { 7258 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7259 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7260 IXGBE_WRITE_FLUSH(hw); 7261 } 7262 7263 adapter->link_up = link_up; 7264 adapter->link_speed = link_speed; 7265 } 7266 7267 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7268 { 7269 #ifdef CONFIG_IXGBE_DCB 7270 struct net_device *netdev = adapter->netdev; 7271 struct dcb_app app = { 7272 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7273 .protocol = 0, 7274 }; 7275 u8 up = 0; 7276 7277 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7278 up = dcb_ieee_getapp_mask(netdev, &app); 7279 7280 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7281 #endif 7282 } 7283 7284 static int ixgbe_enable_macvlan(struct net_device *upper, void *data) 7285 { 7286 if (netif_is_macvlan(upper)) { 7287 struct macvlan_dev *vlan = netdev_priv(upper); 7288 7289 if (vlan->fwd_priv) 7290 netif_tx_wake_all_queues(upper); 7291 } 7292 7293 return 0; 7294 } 7295 7296 /** 7297 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7298 * print link up message 7299 * @adapter: pointer to the device adapter structure 7300 **/ 7301 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7302 { 7303 struct net_device *netdev = adapter->netdev; 7304 struct ixgbe_hw *hw = &adapter->hw; 7305 u32 link_speed = adapter->link_speed; 7306 const char *speed_str; 7307 bool flow_rx, flow_tx; 7308 7309 /* only continue if link was previously down */ 7310 if (netif_carrier_ok(netdev)) 7311 return; 7312 7313 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7314 7315 switch (hw->mac.type) { 7316 case ixgbe_mac_82598EB: { 7317 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7318 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7319 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7320 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7321 } 7322 break; 7323 case ixgbe_mac_X540: 7324 case ixgbe_mac_X550: 7325 case ixgbe_mac_X550EM_x: 7326 case ixgbe_mac_x550em_a: 7327 case ixgbe_mac_82599EB: { 7328 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7329 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7330 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7331 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7332 } 7333 break; 7334 default: 7335 flow_tx = false; 7336 flow_rx = false; 7337 break; 7338 } 7339 7340 adapter->last_rx_ptp_check = jiffies; 7341 7342 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7343 ixgbe_ptp_start_cyclecounter(adapter); 7344 7345 switch (link_speed) { 7346 case IXGBE_LINK_SPEED_10GB_FULL: 7347 speed_str = "10 Gbps"; 7348 break; 7349 case IXGBE_LINK_SPEED_2_5GB_FULL: 7350 speed_str = "2.5 Gbps"; 7351 break; 7352 case IXGBE_LINK_SPEED_1GB_FULL: 7353 speed_str = "1 Gbps"; 7354 break; 7355 case IXGBE_LINK_SPEED_100_FULL: 7356 speed_str = "100 Mbps"; 7357 break; 7358 case IXGBE_LINK_SPEED_10_FULL: 7359 speed_str = "10 Mbps"; 7360 break; 7361 default: 7362 speed_str = "unknown speed"; 7363 break; 7364 } 7365 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7366 ((flow_rx && flow_tx) ? "RX/TX" : 7367 (flow_rx ? "RX" : 7368 (flow_tx ? "TX" : "None")))); 7369 7370 netif_carrier_on(netdev); 7371 ixgbe_check_vf_rate_limit(adapter); 7372 7373 /* enable transmits */ 7374 netif_tx_wake_all_queues(adapter->netdev); 7375 7376 /* enable any upper devices */ 7377 rtnl_lock(); 7378 netdev_walk_all_upper_dev_rcu(adapter->netdev, 7379 ixgbe_enable_macvlan, NULL); 7380 rtnl_unlock(); 7381 7382 /* update the default user priority for VFs */ 7383 ixgbe_update_default_up(adapter); 7384 7385 /* ping all the active vfs to let them know link has changed */ 7386 ixgbe_ping_all_vfs(adapter); 7387 } 7388 7389 /** 7390 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7391 * print link down message 7392 * @adapter: pointer to the adapter structure 7393 **/ 7394 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7395 { 7396 struct net_device *netdev = adapter->netdev; 7397 struct ixgbe_hw *hw = &adapter->hw; 7398 7399 adapter->link_up = false; 7400 adapter->link_speed = 0; 7401 7402 /* only continue if link was up previously */ 7403 if (!netif_carrier_ok(netdev)) 7404 return; 7405 7406 /* poll for SFP+ cable when link is down */ 7407 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7408 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7409 7410 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7411 ixgbe_ptp_start_cyclecounter(adapter); 7412 7413 e_info(drv, "NIC Link is Down\n"); 7414 netif_carrier_off(netdev); 7415 7416 /* ping all the active vfs to let them know link has changed */ 7417 ixgbe_ping_all_vfs(adapter); 7418 } 7419 7420 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7421 { 7422 int i; 7423 7424 for (i = 0; i < adapter->num_tx_queues; i++) { 7425 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7426 7427 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7428 return true; 7429 } 7430 7431 for (i = 0; i < adapter->num_xdp_queues; i++) { 7432 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7433 7434 if (ring->next_to_use != ring->next_to_clean) 7435 return true; 7436 } 7437 7438 return false; 7439 } 7440 7441 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7442 { 7443 struct ixgbe_hw *hw = &adapter->hw; 7444 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7445 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7446 7447 int i, j; 7448 7449 if (!adapter->num_vfs) 7450 return false; 7451 7452 /* resetting the PF is only needed for MAC before X550 */ 7453 if (hw->mac.type >= ixgbe_mac_X550) 7454 return false; 7455 7456 for (i = 0; i < adapter->num_vfs; i++) { 7457 for (j = 0; j < q_per_pool; j++) { 7458 u32 h, t; 7459 7460 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7461 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7462 7463 if (h != t) 7464 return true; 7465 } 7466 } 7467 7468 return false; 7469 } 7470 7471 /** 7472 * ixgbe_watchdog_flush_tx - flush queues on link down 7473 * @adapter: pointer to the device adapter structure 7474 **/ 7475 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7476 { 7477 if (!netif_carrier_ok(adapter->netdev)) { 7478 if (ixgbe_ring_tx_pending(adapter) || 7479 ixgbe_vf_tx_pending(adapter)) { 7480 /* We've lost link, so the controller stops DMA, 7481 * but we've got queued Tx work that's never going 7482 * to get done, so reset controller to flush Tx. 7483 * (Do the reset outside of interrupt context). 7484 */ 7485 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7486 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7487 } 7488 } 7489 } 7490 7491 #ifdef CONFIG_PCI_IOV 7492 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7493 { 7494 struct ixgbe_hw *hw = &adapter->hw; 7495 struct pci_dev *pdev = adapter->pdev; 7496 unsigned int vf; 7497 u32 gpc; 7498 7499 if (!(netif_carrier_ok(adapter->netdev))) 7500 return; 7501 7502 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7503 if (gpc) /* If incrementing then no need for the check below */ 7504 return; 7505 /* Check to see if a bad DMA write target from an errant or 7506 * malicious VF has caused a PCIe error. If so then we can 7507 * issue a VFLR to the offending VF(s) and then resume without 7508 * requesting a full slot reset. 7509 */ 7510 7511 if (!pdev) 7512 return; 7513 7514 /* check status reg for all VFs owned by this PF */ 7515 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7516 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7517 u16 status_reg; 7518 7519 if (!vfdev) 7520 continue; 7521 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7522 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7523 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7524 pcie_flr(vfdev); 7525 } 7526 } 7527 7528 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7529 { 7530 u32 ssvpc; 7531 7532 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7533 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7534 adapter->num_vfs == 0) 7535 return; 7536 7537 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7538 7539 /* 7540 * ssvpc register is cleared on read, if zero then no 7541 * spoofed packets in the last interval. 7542 */ 7543 if (!ssvpc) 7544 return; 7545 7546 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7547 } 7548 #else 7549 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7550 { 7551 } 7552 7553 static void 7554 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7555 { 7556 } 7557 #endif /* CONFIG_PCI_IOV */ 7558 7559 7560 /** 7561 * ixgbe_watchdog_subtask - check and bring link up 7562 * @adapter: pointer to the device adapter structure 7563 **/ 7564 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7565 { 7566 /* if interface is down, removing or resetting, do nothing */ 7567 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7568 test_bit(__IXGBE_REMOVING, &adapter->state) || 7569 test_bit(__IXGBE_RESETTING, &adapter->state)) 7570 return; 7571 7572 ixgbe_watchdog_update_link(adapter); 7573 7574 if (adapter->link_up) 7575 ixgbe_watchdog_link_is_up(adapter); 7576 else 7577 ixgbe_watchdog_link_is_down(adapter); 7578 7579 ixgbe_check_for_bad_vf(adapter); 7580 ixgbe_spoof_check(adapter); 7581 ixgbe_update_stats(adapter); 7582 7583 ixgbe_watchdog_flush_tx(adapter); 7584 } 7585 7586 /** 7587 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7588 * @adapter: the ixgbe adapter structure 7589 **/ 7590 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7591 { 7592 struct ixgbe_hw *hw = &adapter->hw; 7593 s32 err; 7594 7595 /* not searching for SFP so there is nothing to do here */ 7596 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7597 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7598 return; 7599 7600 if (adapter->sfp_poll_time && 7601 time_after(adapter->sfp_poll_time, jiffies)) 7602 return; /* If not yet time to poll for SFP */ 7603 7604 /* someone else is in init, wait until next service event */ 7605 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7606 return; 7607 7608 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7609 7610 err = hw->phy.ops.identify_sfp(hw); 7611 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7612 goto sfp_out; 7613 7614 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7615 /* If no cable is present, then we need to reset 7616 * the next time we find a good cable. */ 7617 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7618 } 7619 7620 /* exit on error */ 7621 if (err) 7622 goto sfp_out; 7623 7624 /* exit if reset not needed */ 7625 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7626 goto sfp_out; 7627 7628 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7629 7630 /* 7631 * A module may be identified correctly, but the EEPROM may not have 7632 * support for that module. setup_sfp() will fail in that case, so 7633 * we should not allow that module to load. 7634 */ 7635 if (hw->mac.type == ixgbe_mac_82598EB) 7636 err = hw->phy.ops.reset(hw); 7637 else 7638 err = hw->mac.ops.setup_sfp(hw); 7639 7640 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7641 goto sfp_out; 7642 7643 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7644 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7645 7646 sfp_out: 7647 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7648 7649 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7650 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7651 e_dev_err("failed to initialize because an unsupported " 7652 "SFP+ module type was detected.\n"); 7653 e_dev_err("Reload the driver after installing a " 7654 "supported module.\n"); 7655 unregister_netdev(adapter->netdev); 7656 } 7657 } 7658 7659 /** 7660 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7661 * @adapter: the ixgbe adapter structure 7662 **/ 7663 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7664 { 7665 struct ixgbe_hw *hw = &adapter->hw; 7666 u32 speed; 7667 bool autoneg = false; 7668 7669 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7670 return; 7671 7672 /* someone else is in init, wait until next service event */ 7673 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7674 return; 7675 7676 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7677 7678 speed = hw->phy.autoneg_advertised; 7679 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 7680 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 7681 7682 /* setup the highest link when no autoneg */ 7683 if (!autoneg) { 7684 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 7685 speed = IXGBE_LINK_SPEED_10GB_FULL; 7686 } 7687 } 7688 7689 if (hw->mac.ops.setup_link) 7690 hw->mac.ops.setup_link(hw, speed, true); 7691 7692 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7693 adapter->link_check_timeout = jiffies; 7694 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7695 } 7696 7697 /** 7698 * ixgbe_service_timer - Timer Call-back 7699 * @data: pointer to adapter cast into an unsigned long 7700 **/ 7701 static void ixgbe_service_timer(struct timer_list *t) 7702 { 7703 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7704 unsigned long next_event_offset; 7705 7706 /* poll faster when waiting for link */ 7707 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7708 next_event_offset = HZ / 10; 7709 else 7710 next_event_offset = HZ * 2; 7711 7712 /* Reset the timer */ 7713 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7714 7715 ixgbe_service_event_schedule(adapter); 7716 } 7717 7718 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7719 { 7720 struct ixgbe_hw *hw = &adapter->hw; 7721 u32 status; 7722 7723 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7724 return; 7725 7726 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7727 7728 if (!hw->phy.ops.handle_lasi) 7729 return; 7730 7731 status = hw->phy.ops.handle_lasi(&adapter->hw); 7732 if (status != IXGBE_ERR_OVERTEMP) 7733 return; 7734 7735 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7736 } 7737 7738 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7739 { 7740 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7741 return; 7742 7743 /* If we're already down, removing or resetting, just bail */ 7744 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7745 test_bit(__IXGBE_REMOVING, &adapter->state) || 7746 test_bit(__IXGBE_RESETTING, &adapter->state)) 7747 return; 7748 7749 ixgbe_dump(adapter); 7750 netdev_err(adapter->netdev, "Reset adapter\n"); 7751 adapter->tx_timeout_count++; 7752 7753 rtnl_lock(); 7754 ixgbe_reinit_locked(adapter); 7755 rtnl_unlock(); 7756 } 7757 7758 /** 7759 * ixgbe_service_task - manages and runs subtasks 7760 * @work: pointer to work_struct containing our data 7761 **/ 7762 static void ixgbe_service_task(struct work_struct *work) 7763 { 7764 struct ixgbe_adapter *adapter = container_of(work, 7765 struct ixgbe_adapter, 7766 service_task); 7767 if (ixgbe_removed(adapter->hw.hw_addr)) { 7768 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7769 rtnl_lock(); 7770 ixgbe_down(adapter); 7771 rtnl_unlock(); 7772 } 7773 ixgbe_service_event_complete(adapter); 7774 return; 7775 } 7776 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7777 rtnl_lock(); 7778 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7779 udp_tunnel_get_rx_info(adapter->netdev); 7780 rtnl_unlock(); 7781 } 7782 ixgbe_reset_subtask(adapter); 7783 ixgbe_phy_interrupt_subtask(adapter); 7784 ixgbe_sfp_detection_subtask(adapter); 7785 ixgbe_sfp_link_config_subtask(adapter); 7786 ixgbe_check_overtemp_subtask(adapter); 7787 ixgbe_watchdog_subtask(adapter); 7788 ixgbe_fdir_reinit_subtask(adapter); 7789 ixgbe_check_hang_subtask(adapter); 7790 7791 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7792 ixgbe_ptp_overflow_check(adapter); 7793 ixgbe_ptp_rx_hang(adapter); 7794 ixgbe_ptp_tx_hang(adapter); 7795 } 7796 7797 ixgbe_service_event_complete(adapter); 7798 } 7799 7800 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7801 struct ixgbe_tx_buffer *first, 7802 u8 *hdr_len) 7803 { 7804 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7805 struct sk_buff *skb = first->skb; 7806 union { 7807 struct iphdr *v4; 7808 struct ipv6hdr *v6; 7809 unsigned char *hdr; 7810 } ip; 7811 union { 7812 struct tcphdr *tcp; 7813 unsigned char *hdr; 7814 } l4; 7815 u32 paylen, l4_offset; 7816 int err; 7817 7818 if (skb->ip_summed != CHECKSUM_PARTIAL) 7819 return 0; 7820 7821 if (!skb_is_gso(skb)) 7822 return 0; 7823 7824 err = skb_cow_head(skb, 0); 7825 if (err < 0) 7826 return err; 7827 7828 if (eth_p_mpls(first->protocol)) 7829 ip.hdr = skb_inner_network_header(skb); 7830 else 7831 ip.hdr = skb_network_header(skb); 7832 l4.hdr = skb_checksum_start(skb); 7833 7834 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7835 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7836 7837 /* initialize outer IP header fields */ 7838 if (ip.v4->version == 4) { 7839 unsigned char *csum_start = skb_checksum_start(skb); 7840 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7841 7842 /* IP header will have to cancel out any data that 7843 * is not a part of the outer IP header 7844 */ 7845 ip.v4->check = csum_fold(csum_partial(trans_start, 7846 csum_start - trans_start, 7847 0)); 7848 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7849 7850 ip.v4->tot_len = 0; 7851 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7852 IXGBE_TX_FLAGS_CSUM | 7853 IXGBE_TX_FLAGS_IPV4; 7854 } else { 7855 ip.v6->payload_len = 0; 7856 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7857 IXGBE_TX_FLAGS_CSUM; 7858 } 7859 7860 /* determine offset of inner transport header */ 7861 l4_offset = l4.hdr - skb->data; 7862 7863 /* compute length of segmentation header */ 7864 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7865 7866 /* remove payload length from inner checksum */ 7867 paylen = skb->len - l4_offset; 7868 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7869 7870 /* update gso size and bytecount with header size */ 7871 first->gso_segs = skb_shinfo(skb)->gso_segs; 7872 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7873 7874 /* mss_l4len_id: use 0 as index for TSO */ 7875 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7876 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7877 7878 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7879 vlan_macip_lens = l4.hdr - ip.hdr; 7880 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7881 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7882 7883 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 7884 mss_l4len_idx); 7885 7886 return 1; 7887 } 7888 7889 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7890 { 7891 unsigned int offset = 0; 7892 7893 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7894 7895 return offset == skb_checksum_start_offset(skb); 7896 } 7897 7898 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7899 struct ixgbe_tx_buffer *first) 7900 { 7901 struct sk_buff *skb = first->skb; 7902 u32 vlan_macip_lens = 0; 7903 u32 type_tucmd = 0; 7904 7905 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7906 csum_failed: 7907 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7908 IXGBE_TX_FLAGS_CC))) 7909 return; 7910 goto no_csum; 7911 } 7912 7913 switch (skb->csum_offset) { 7914 case offsetof(struct tcphdr, check): 7915 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7916 /* fall through */ 7917 case offsetof(struct udphdr, check): 7918 break; 7919 case offsetof(struct sctphdr, checksum): 7920 /* validate that this is actually an SCTP request */ 7921 if (((first->protocol == htons(ETH_P_IP)) && 7922 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7923 ((first->protocol == htons(ETH_P_IPV6)) && 7924 ixgbe_ipv6_csum_is_sctp(skb))) { 7925 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7926 break; 7927 } 7928 /* fall through */ 7929 default: 7930 skb_checksum_help(skb); 7931 goto csum_failed; 7932 } 7933 7934 /* update TX checksum flag */ 7935 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7936 vlan_macip_lens = skb_checksum_start_offset(skb) - 7937 skb_network_offset(skb); 7938 no_csum: 7939 /* vlan_macip_lens: MACLEN, VLAN tag */ 7940 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7941 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7942 7943 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0); 7944 } 7945 7946 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7947 ((_flag <= _result) ? \ 7948 ((u32)(_input & _flag) * (_result / _flag)) : \ 7949 ((u32)(_input & _flag) / (_flag / _result))) 7950 7951 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7952 { 7953 /* set type for advanced descriptor with frame checksum insertion */ 7954 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7955 IXGBE_ADVTXD_DCMD_DEXT | 7956 IXGBE_ADVTXD_DCMD_IFCS; 7957 7958 /* set HW vlan bit if vlan is present */ 7959 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7960 IXGBE_ADVTXD_DCMD_VLE); 7961 7962 /* set segmentation enable bits for TSO/FSO */ 7963 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7964 IXGBE_ADVTXD_DCMD_TSE); 7965 7966 /* set timestamp bit if present */ 7967 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7968 IXGBE_ADVTXD_MAC_TSTAMP); 7969 7970 /* insert frame checksum */ 7971 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7972 7973 return cmd_type; 7974 } 7975 7976 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7977 u32 tx_flags, unsigned int paylen) 7978 { 7979 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7980 7981 /* enable L4 checksum for TSO and TX checksum offload */ 7982 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7983 IXGBE_TX_FLAGS_CSUM, 7984 IXGBE_ADVTXD_POPTS_TXSM); 7985 7986 /* enble IPv4 checksum for TSO */ 7987 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7988 IXGBE_TX_FLAGS_IPV4, 7989 IXGBE_ADVTXD_POPTS_IXSM); 7990 7991 /* 7992 * Check Context must be set if Tx switch is enabled, which it 7993 * always is for case where virtual functions are running 7994 */ 7995 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7996 IXGBE_TX_FLAGS_CC, 7997 IXGBE_ADVTXD_CC); 7998 7999 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8000 } 8001 8002 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8003 { 8004 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8005 8006 /* Herbert's original patch had: 8007 * smp_mb__after_netif_stop_queue(); 8008 * but since that doesn't exist yet, just open code it. 8009 */ 8010 smp_mb(); 8011 8012 /* We need to check again in a case another CPU has just 8013 * made room available. 8014 */ 8015 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8016 return -EBUSY; 8017 8018 /* A reprieve! - use start_queue because it doesn't call schedule */ 8019 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8020 ++tx_ring->tx_stats.restart_queue; 8021 return 0; 8022 } 8023 8024 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8025 { 8026 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8027 return 0; 8028 8029 return __ixgbe_maybe_stop_tx(tx_ring, size); 8030 } 8031 8032 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 8033 IXGBE_TXD_CMD_RS) 8034 8035 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8036 struct ixgbe_tx_buffer *first, 8037 const u8 hdr_len) 8038 { 8039 struct sk_buff *skb = first->skb; 8040 struct ixgbe_tx_buffer *tx_buffer; 8041 union ixgbe_adv_tx_desc *tx_desc; 8042 struct skb_frag_struct *frag; 8043 dma_addr_t dma; 8044 unsigned int data_len, size; 8045 u32 tx_flags = first->tx_flags; 8046 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8047 u16 i = tx_ring->next_to_use; 8048 8049 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8050 8051 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8052 8053 size = skb_headlen(skb); 8054 data_len = skb->data_len; 8055 8056 #ifdef IXGBE_FCOE 8057 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8058 if (data_len < sizeof(struct fcoe_crc_eof)) { 8059 size -= sizeof(struct fcoe_crc_eof) - data_len; 8060 data_len = 0; 8061 } else { 8062 data_len -= sizeof(struct fcoe_crc_eof); 8063 } 8064 } 8065 8066 #endif 8067 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8068 8069 tx_buffer = first; 8070 8071 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8072 if (dma_mapping_error(tx_ring->dev, dma)) 8073 goto dma_error; 8074 8075 /* record length, and DMA address */ 8076 dma_unmap_len_set(tx_buffer, len, size); 8077 dma_unmap_addr_set(tx_buffer, dma, dma); 8078 8079 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8080 8081 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8082 tx_desc->read.cmd_type_len = 8083 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8084 8085 i++; 8086 tx_desc++; 8087 if (i == tx_ring->count) { 8088 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8089 i = 0; 8090 } 8091 tx_desc->read.olinfo_status = 0; 8092 8093 dma += IXGBE_MAX_DATA_PER_TXD; 8094 size -= IXGBE_MAX_DATA_PER_TXD; 8095 8096 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8097 } 8098 8099 if (likely(!data_len)) 8100 break; 8101 8102 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8103 8104 i++; 8105 tx_desc++; 8106 if (i == tx_ring->count) { 8107 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8108 i = 0; 8109 } 8110 tx_desc->read.olinfo_status = 0; 8111 8112 #ifdef IXGBE_FCOE 8113 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8114 #else 8115 size = skb_frag_size(frag); 8116 #endif 8117 data_len -= size; 8118 8119 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8120 DMA_TO_DEVICE); 8121 8122 tx_buffer = &tx_ring->tx_buffer_info[i]; 8123 } 8124 8125 /* write last descriptor with RS and EOP bits */ 8126 cmd_type |= size | IXGBE_TXD_CMD; 8127 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8128 8129 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8130 8131 /* set the timestamp */ 8132 first->time_stamp = jiffies; 8133 8134 /* 8135 * Force memory writes to complete before letting h/w know there 8136 * are new descriptors to fetch. (Only applicable for weak-ordered 8137 * memory model archs, such as IA-64). 8138 * 8139 * We also need this memory barrier to make certain all of the 8140 * status bits have been updated before next_to_watch is written. 8141 */ 8142 wmb(); 8143 8144 /* set next_to_watch value indicating a packet is present */ 8145 first->next_to_watch = tx_desc; 8146 8147 i++; 8148 if (i == tx_ring->count) 8149 i = 0; 8150 8151 tx_ring->next_to_use = i; 8152 8153 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8154 8155 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8156 writel(i, tx_ring->tail); 8157 8158 /* we need this if more than one processor can write to our tail 8159 * at a time, it synchronizes IO on IA64/Altix systems 8160 */ 8161 mmiowb(); 8162 } 8163 8164 return 0; 8165 dma_error: 8166 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8167 8168 /* clear dma mappings for failed tx_buffer_info map */ 8169 for (;;) { 8170 tx_buffer = &tx_ring->tx_buffer_info[i]; 8171 if (dma_unmap_len(tx_buffer, len)) 8172 dma_unmap_page(tx_ring->dev, 8173 dma_unmap_addr(tx_buffer, dma), 8174 dma_unmap_len(tx_buffer, len), 8175 DMA_TO_DEVICE); 8176 dma_unmap_len_set(tx_buffer, len, 0); 8177 if (tx_buffer == first) 8178 break; 8179 if (i == 0) 8180 i += tx_ring->count; 8181 i--; 8182 } 8183 8184 dev_kfree_skb_any(first->skb); 8185 first->skb = NULL; 8186 8187 tx_ring->next_to_use = i; 8188 8189 return -1; 8190 } 8191 8192 static void ixgbe_atr(struct ixgbe_ring *ring, 8193 struct ixgbe_tx_buffer *first) 8194 { 8195 struct ixgbe_q_vector *q_vector = ring->q_vector; 8196 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8197 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8198 union { 8199 unsigned char *network; 8200 struct iphdr *ipv4; 8201 struct ipv6hdr *ipv6; 8202 } hdr; 8203 struct tcphdr *th; 8204 unsigned int hlen; 8205 struct sk_buff *skb; 8206 __be16 vlan_id; 8207 int l4_proto; 8208 8209 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8210 if (!q_vector) 8211 return; 8212 8213 /* do nothing if sampling is disabled */ 8214 if (!ring->atr_sample_rate) 8215 return; 8216 8217 ring->atr_count++; 8218 8219 /* currently only IPv4/IPv6 with TCP is supported */ 8220 if ((first->protocol != htons(ETH_P_IP)) && 8221 (first->protocol != htons(ETH_P_IPV6))) 8222 return; 8223 8224 /* snag network header to get L4 type and address */ 8225 skb = first->skb; 8226 hdr.network = skb_network_header(skb); 8227 if (unlikely(hdr.network <= skb->data)) 8228 return; 8229 if (skb->encapsulation && 8230 first->protocol == htons(ETH_P_IP) && 8231 hdr.ipv4->protocol == IPPROTO_UDP) { 8232 struct ixgbe_adapter *adapter = q_vector->adapter; 8233 8234 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8235 VXLAN_HEADROOM)) 8236 return; 8237 8238 /* verify the port is recognized as VXLAN */ 8239 if (adapter->vxlan_port && 8240 udp_hdr(skb)->dest == adapter->vxlan_port) 8241 hdr.network = skb_inner_network_header(skb); 8242 8243 if (adapter->geneve_port && 8244 udp_hdr(skb)->dest == adapter->geneve_port) 8245 hdr.network = skb_inner_network_header(skb); 8246 } 8247 8248 /* Make sure we have at least [minimum IPv4 header + TCP] 8249 * or [IPv6 header] bytes 8250 */ 8251 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8252 return; 8253 8254 /* Currently only IPv4/IPv6 with TCP is supported */ 8255 switch (hdr.ipv4->version) { 8256 case IPVERSION: 8257 /* access ihl as u8 to avoid unaligned access on ia64 */ 8258 hlen = (hdr.network[0] & 0x0F) << 2; 8259 l4_proto = hdr.ipv4->protocol; 8260 break; 8261 case 6: 8262 hlen = hdr.network - skb->data; 8263 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8264 hlen -= hdr.network - skb->data; 8265 break; 8266 default: 8267 return; 8268 } 8269 8270 if (l4_proto != IPPROTO_TCP) 8271 return; 8272 8273 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8274 hlen + sizeof(struct tcphdr))) 8275 return; 8276 8277 th = (struct tcphdr *)(hdr.network + hlen); 8278 8279 /* skip this packet since the socket is closing */ 8280 if (th->fin) 8281 return; 8282 8283 /* sample on all syn packets or once every atr sample count */ 8284 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8285 return; 8286 8287 /* reset sample count */ 8288 ring->atr_count = 0; 8289 8290 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8291 8292 /* 8293 * src and dst are inverted, think how the receiver sees them 8294 * 8295 * The input is broken into two sections, a non-compressed section 8296 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8297 * is XORed together and stored in the compressed dword. 8298 */ 8299 input.formatted.vlan_id = vlan_id; 8300 8301 /* 8302 * since src port and flex bytes occupy the same word XOR them together 8303 * and write the value to source port portion of compressed dword 8304 */ 8305 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8306 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8307 else 8308 common.port.src ^= th->dest ^ first->protocol; 8309 common.port.dst ^= th->source; 8310 8311 switch (hdr.ipv4->version) { 8312 case IPVERSION: 8313 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8314 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8315 break; 8316 case 6: 8317 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8318 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8319 hdr.ipv6->saddr.s6_addr32[1] ^ 8320 hdr.ipv6->saddr.s6_addr32[2] ^ 8321 hdr.ipv6->saddr.s6_addr32[3] ^ 8322 hdr.ipv6->daddr.s6_addr32[0] ^ 8323 hdr.ipv6->daddr.s6_addr32[1] ^ 8324 hdr.ipv6->daddr.s6_addr32[2] ^ 8325 hdr.ipv6->daddr.s6_addr32[3]; 8326 break; 8327 default: 8328 break; 8329 } 8330 8331 if (hdr.network != skb_network_header(skb)) 8332 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8333 8334 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8335 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8336 input, common, ring->queue_index); 8337 } 8338 8339 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8340 void *accel_priv, select_queue_fallback_t fallback) 8341 { 8342 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8343 #ifdef IXGBE_FCOE 8344 struct ixgbe_adapter *adapter; 8345 struct ixgbe_ring_feature *f; 8346 int txq; 8347 #endif 8348 8349 if (fwd_adapter) 8350 return skb->queue_mapping + fwd_adapter->tx_base_queue; 8351 8352 #ifdef IXGBE_FCOE 8353 8354 /* 8355 * only execute the code below if protocol is FCoE 8356 * or FIP and we have FCoE enabled on the adapter 8357 */ 8358 switch (vlan_get_protocol(skb)) { 8359 case htons(ETH_P_FCOE): 8360 case htons(ETH_P_FIP): 8361 adapter = netdev_priv(dev); 8362 8363 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8364 break; 8365 /* fall through */ 8366 default: 8367 return fallback(dev, skb); 8368 } 8369 8370 f = &adapter->ring_feature[RING_F_FCOE]; 8371 8372 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8373 smp_processor_id(); 8374 8375 while (txq >= f->indices) 8376 txq -= f->indices; 8377 8378 return txq + f->offset; 8379 #else 8380 return fallback(dev, skb); 8381 #endif 8382 } 8383 8384 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8385 struct xdp_buff *xdp) 8386 { 8387 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8388 struct ixgbe_tx_buffer *tx_buffer; 8389 union ixgbe_adv_tx_desc *tx_desc; 8390 u32 len, cmd_type; 8391 dma_addr_t dma; 8392 u16 i; 8393 8394 len = xdp->data_end - xdp->data; 8395 8396 if (unlikely(!ixgbe_desc_unused(ring))) 8397 return IXGBE_XDP_CONSUMED; 8398 8399 dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE); 8400 if (dma_mapping_error(ring->dev, dma)) 8401 return IXGBE_XDP_CONSUMED; 8402 8403 /* record the location of the first descriptor for this packet */ 8404 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8405 tx_buffer->bytecount = len; 8406 tx_buffer->gso_segs = 1; 8407 tx_buffer->protocol = 0; 8408 8409 i = ring->next_to_use; 8410 tx_desc = IXGBE_TX_DESC(ring, i); 8411 8412 dma_unmap_len_set(tx_buffer, len, len); 8413 dma_unmap_addr_set(tx_buffer, dma, dma); 8414 tx_buffer->data = xdp->data; 8415 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8416 8417 /* put descriptor type bits */ 8418 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8419 IXGBE_ADVTXD_DCMD_DEXT | 8420 IXGBE_ADVTXD_DCMD_IFCS; 8421 cmd_type |= len | IXGBE_TXD_CMD; 8422 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8423 tx_desc->read.olinfo_status = 8424 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8425 8426 /* Avoid any potential race with xdp_xmit and cleanup */ 8427 smp_wmb(); 8428 8429 /* set next_to_watch value indicating a packet is present */ 8430 i++; 8431 if (i == ring->count) 8432 i = 0; 8433 8434 tx_buffer->next_to_watch = tx_desc; 8435 ring->next_to_use = i; 8436 8437 return IXGBE_XDP_TX; 8438 } 8439 8440 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8441 struct ixgbe_adapter *adapter, 8442 struct ixgbe_ring *tx_ring) 8443 { 8444 struct ixgbe_tx_buffer *first; 8445 int tso; 8446 u32 tx_flags = 0; 8447 unsigned short f; 8448 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8449 __be16 protocol = skb->protocol; 8450 u8 hdr_len = 0; 8451 8452 /* 8453 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8454 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8455 * + 2 desc gap to keep tail from touching head, 8456 * + 1 desc for context descriptor, 8457 * otherwise try next time 8458 */ 8459 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8460 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8461 8462 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8463 tx_ring->tx_stats.tx_busy++; 8464 return NETDEV_TX_BUSY; 8465 } 8466 8467 /* record the location of the first descriptor for this packet */ 8468 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8469 first->skb = skb; 8470 first->bytecount = skb->len; 8471 first->gso_segs = 1; 8472 8473 /* if we have a HW VLAN tag being added default to the HW one */ 8474 if (skb_vlan_tag_present(skb)) { 8475 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8476 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8477 /* else if it is a SW VLAN check the next protocol and store the tag */ 8478 } else if (protocol == htons(ETH_P_8021Q)) { 8479 struct vlan_hdr *vhdr, _vhdr; 8480 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8481 if (!vhdr) 8482 goto out_drop; 8483 8484 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8485 IXGBE_TX_FLAGS_VLAN_SHIFT; 8486 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8487 } 8488 protocol = vlan_get_protocol(skb); 8489 8490 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8491 adapter->ptp_clock) { 8492 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8493 &adapter->state)) { 8494 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8495 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8496 8497 /* schedule check for Tx timestamp */ 8498 adapter->ptp_tx_skb = skb_get(skb); 8499 adapter->ptp_tx_start = jiffies; 8500 schedule_work(&adapter->ptp_tx_work); 8501 } else { 8502 adapter->tx_hwtstamp_skipped++; 8503 } 8504 } 8505 8506 skb_tx_timestamp(skb); 8507 8508 #ifdef CONFIG_PCI_IOV 8509 /* 8510 * Use the l2switch_enable flag - would be false if the DMA 8511 * Tx switch had been disabled. 8512 */ 8513 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8514 tx_flags |= IXGBE_TX_FLAGS_CC; 8515 8516 #endif 8517 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8518 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8519 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8520 (skb->priority != TC_PRIO_CONTROL))) { 8521 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8522 tx_flags |= (skb->priority & 0x7) << 8523 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8524 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8525 struct vlan_ethhdr *vhdr; 8526 8527 if (skb_cow_head(skb, 0)) 8528 goto out_drop; 8529 vhdr = (struct vlan_ethhdr *)skb->data; 8530 vhdr->h_vlan_TCI = htons(tx_flags >> 8531 IXGBE_TX_FLAGS_VLAN_SHIFT); 8532 } else { 8533 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8534 } 8535 } 8536 8537 /* record initial flags and protocol */ 8538 first->tx_flags = tx_flags; 8539 first->protocol = protocol; 8540 8541 #ifdef IXGBE_FCOE 8542 /* setup tx offload for FCoE */ 8543 if ((protocol == htons(ETH_P_FCOE)) && 8544 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8545 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8546 if (tso < 0) 8547 goto out_drop; 8548 8549 goto xmit_fcoe; 8550 } 8551 8552 #endif /* IXGBE_FCOE */ 8553 tso = ixgbe_tso(tx_ring, first, &hdr_len); 8554 if (tso < 0) 8555 goto out_drop; 8556 else if (!tso) 8557 ixgbe_tx_csum(tx_ring, first); 8558 8559 /* add the ATR filter if ATR is on */ 8560 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8561 ixgbe_atr(tx_ring, first); 8562 8563 #ifdef IXGBE_FCOE 8564 xmit_fcoe: 8565 #endif /* IXGBE_FCOE */ 8566 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8567 goto cleanup_tx_timestamp; 8568 8569 return NETDEV_TX_OK; 8570 8571 out_drop: 8572 dev_kfree_skb_any(first->skb); 8573 first->skb = NULL; 8574 cleanup_tx_timestamp: 8575 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8576 dev_kfree_skb_any(adapter->ptp_tx_skb); 8577 adapter->ptp_tx_skb = NULL; 8578 cancel_work_sync(&adapter->ptp_tx_work); 8579 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8580 } 8581 8582 return NETDEV_TX_OK; 8583 } 8584 8585 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8586 struct net_device *netdev, 8587 struct ixgbe_ring *ring) 8588 { 8589 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8590 struct ixgbe_ring *tx_ring; 8591 8592 /* 8593 * The minimum packet size for olinfo paylen is 17 so pad the skb 8594 * in order to meet this minimum size requirement. 8595 */ 8596 if (skb_put_padto(skb, 17)) 8597 return NETDEV_TX_OK; 8598 8599 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8600 8601 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8602 } 8603 8604 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8605 struct net_device *netdev) 8606 { 8607 return __ixgbe_xmit_frame(skb, netdev, NULL); 8608 } 8609 8610 /** 8611 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8612 * @netdev: network interface device structure 8613 * @p: pointer to an address structure 8614 * 8615 * Returns 0 on success, negative on failure 8616 **/ 8617 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8618 { 8619 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8620 struct ixgbe_hw *hw = &adapter->hw; 8621 struct sockaddr *addr = p; 8622 8623 if (!is_valid_ether_addr(addr->sa_data)) 8624 return -EADDRNOTAVAIL; 8625 8626 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8627 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8628 8629 ixgbe_mac_set_default_filter(adapter); 8630 8631 return 0; 8632 } 8633 8634 static int 8635 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8636 { 8637 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8638 struct ixgbe_hw *hw = &adapter->hw; 8639 u16 value; 8640 int rc; 8641 8642 if (prtad != hw->phy.mdio.prtad) 8643 return -EINVAL; 8644 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8645 if (!rc) 8646 rc = value; 8647 return rc; 8648 } 8649 8650 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8651 u16 addr, u16 value) 8652 { 8653 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8654 struct ixgbe_hw *hw = &adapter->hw; 8655 8656 if (prtad != hw->phy.mdio.prtad) 8657 return -EINVAL; 8658 return hw->phy.ops.write_reg(hw, addr, devad, value); 8659 } 8660 8661 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8662 { 8663 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8664 8665 switch (cmd) { 8666 case SIOCSHWTSTAMP: 8667 return ixgbe_ptp_set_ts_config(adapter, req); 8668 case SIOCGHWTSTAMP: 8669 return ixgbe_ptp_get_ts_config(adapter, req); 8670 case SIOCGMIIPHY: 8671 if (!adapter->hw.phy.ops.read_reg) 8672 return -EOPNOTSUPP; 8673 /* fall through */ 8674 default: 8675 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8676 } 8677 } 8678 8679 /** 8680 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8681 * netdev->dev_addrs 8682 * @netdev: network interface device structure 8683 * 8684 * Returns non-zero on failure 8685 **/ 8686 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8687 { 8688 int err = 0; 8689 struct ixgbe_adapter *adapter = netdev_priv(dev); 8690 struct ixgbe_hw *hw = &adapter->hw; 8691 8692 if (is_valid_ether_addr(hw->mac.san_addr)) { 8693 rtnl_lock(); 8694 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8695 rtnl_unlock(); 8696 8697 /* update SAN MAC vmdq pool selection */ 8698 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8699 } 8700 return err; 8701 } 8702 8703 /** 8704 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8705 * netdev->dev_addrs 8706 * @netdev: network interface device structure 8707 * 8708 * Returns non-zero on failure 8709 **/ 8710 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8711 { 8712 int err = 0; 8713 struct ixgbe_adapter *adapter = netdev_priv(dev); 8714 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8715 8716 if (is_valid_ether_addr(mac->san_addr)) { 8717 rtnl_lock(); 8718 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8719 rtnl_unlock(); 8720 } 8721 return err; 8722 } 8723 8724 #ifdef CONFIG_NET_POLL_CONTROLLER 8725 /* 8726 * Polling 'interrupt' - used by things like netconsole to send skbs 8727 * without having to re-enable interrupts. It's not called while 8728 * the interrupt routine is executing. 8729 */ 8730 static void ixgbe_netpoll(struct net_device *netdev) 8731 { 8732 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8733 int i; 8734 8735 /* if interface is down do nothing */ 8736 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8737 return; 8738 8739 /* loop through and schedule all active queues */ 8740 for (i = 0; i < adapter->num_q_vectors; i++) 8741 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8742 } 8743 8744 #endif 8745 8746 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8747 struct ixgbe_ring *ring) 8748 { 8749 u64 bytes, packets; 8750 unsigned int start; 8751 8752 if (ring) { 8753 do { 8754 start = u64_stats_fetch_begin_irq(&ring->syncp); 8755 packets = ring->stats.packets; 8756 bytes = ring->stats.bytes; 8757 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8758 stats->tx_packets += packets; 8759 stats->tx_bytes += bytes; 8760 } 8761 } 8762 8763 static void ixgbe_get_stats64(struct net_device *netdev, 8764 struct rtnl_link_stats64 *stats) 8765 { 8766 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8767 int i; 8768 8769 rcu_read_lock(); 8770 for (i = 0; i < adapter->num_rx_queues; i++) { 8771 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8772 u64 bytes, packets; 8773 unsigned int start; 8774 8775 if (ring) { 8776 do { 8777 start = u64_stats_fetch_begin_irq(&ring->syncp); 8778 packets = ring->stats.packets; 8779 bytes = ring->stats.bytes; 8780 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8781 stats->rx_packets += packets; 8782 stats->rx_bytes += bytes; 8783 } 8784 } 8785 8786 for (i = 0; i < adapter->num_tx_queues; i++) { 8787 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8788 8789 ixgbe_get_ring_stats64(stats, ring); 8790 } 8791 for (i = 0; i < adapter->num_xdp_queues; i++) { 8792 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8793 8794 ixgbe_get_ring_stats64(stats, ring); 8795 } 8796 rcu_read_unlock(); 8797 8798 /* following stats updated by ixgbe_watchdog_task() */ 8799 stats->multicast = netdev->stats.multicast; 8800 stats->rx_errors = netdev->stats.rx_errors; 8801 stats->rx_length_errors = netdev->stats.rx_length_errors; 8802 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8803 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8804 } 8805 8806 #ifdef CONFIG_IXGBE_DCB 8807 /** 8808 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8809 * @adapter: pointer to ixgbe_adapter 8810 * @tc: number of traffic classes currently enabled 8811 * 8812 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8813 * 802.1Q priority maps to a packet buffer that exists. 8814 */ 8815 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8816 { 8817 struct ixgbe_hw *hw = &adapter->hw; 8818 u32 reg, rsave; 8819 int i; 8820 8821 /* 82598 have a static priority to TC mapping that can not 8822 * be changed so no validation is needed. 8823 */ 8824 if (hw->mac.type == ixgbe_mac_82598EB) 8825 return; 8826 8827 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8828 rsave = reg; 8829 8830 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8831 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8832 8833 /* If up2tc is out of bounds default to zero */ 8834 if (up2tc > tc) 8835 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8836 } 8837 8838 if (reg != rsave) 8839 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8840 8841 return; 8842 } 8843 8844 /** 8845 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8846 * @adapter: Pointer to adapter struct 8847 * 8848 * Populate the netdev user priority to tc map 8849 */ 8850 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8851 { 8852 struct net_device *dev = adapter->netdev; 8853 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8854 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8855 u8 prio; 8856 8857 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8858 u8 tc = 0; 8859 8860 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8861 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8862 else if (ets) 8863 tc = ets->prio_tc[prio]; 8864 8865 netdev_set_prio_tc_map(dev, prio, tc); 8866 } 8867 } 8868 8869 #endif /* CONFIG_IXGBE_DCB */ 8870 /** 8871 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8872 * 8873 * @netdev: net device to configure 8874 * @tc: number of traffic classes to enable 8875 */ 8876 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8877 { 8878 struct ixgbe_adapter *adapter = netdev_priv(dev); 8879 struct ixgbe_hw *hw = &adapter->hw; 8880 bool pools; 8881 8882 /* Hardware supports up to 8 traffic classes */ 8883 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8884 return -EINVAL; 8885 8886 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8887 return -EINVAL; 8888 8889 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 8890 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 8891 return -EBUSY; 8892 8893 /* Hardware has to reinitialize queues and interrupts to 8894 * match packet buffer alignment. Unfortunately, the 8895 * hardware is not flexible enough to do this dynamically. 8896 */ 8897 if (netif_running(dev)) 8898 ixgbe_close(dev); 8899 else 8900 ixgbe_reset(adapter); 8901 8902 ixgbe_clear_interrupt_scheme(adapter); 8903 8904 #ifdef CONFIG_IXGBE_DCB 8905 if (tc) { 8906 netdev_set_num_tc(dev, tc); 8907 ixgbe_set_prio_tc_map(adapter); 8908 8909 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8910 8911 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8912 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8913 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8914 } 8915 } else { 8916 netdev_reset_tc(dev); 8917 8918 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8919 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8920 8921 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8922 8923 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8924 adapter->dcb_cfg.pfc_mode_enable = false; 8925 } 8926 8927 ixgbe_validate_rtr(adapter, tc); 8928 8929 #endif /* CONFIG_IXGBE_DCB */ 8930 ixgbe_init_interrupt_scheme(adapter); 8931 8932 if (netif_running(dev)) 8933 return ixgbe_open(dev); 8934 8935 return 0; 8936 } 8937 8938 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8939 struct tc_cls_u32_offload *cls) 8940 { 8941 u32 hdl = cls->knode.handle; 8942 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8943 u32 loc = cls->knode.handle & 0xfffff; 8944 int err = 0, i, j; 8945 struct ixgbe_jump_table *jump = NULL; 8946 8947 if (loc > IXGBE_MAX_HW_ENTRIES) 8948 return -EINVAL; 8949 8950 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8951 return -EINVAL; 8952 8953 /* Clear this filter in the link data it is associated with */ 8954 if (uhtid != 0x800) { 8955 jump = adapter->jump_tables[uhtid]; 8956 if (!jump) 8957 return -EINVAL; 8958 if (!test_bit(loc - 1, jump->child_loc_map)) 8959 return -EINVAL; 8960 clear_bit(loc - 1, jump->child_loc_map); 8961 } 8962 8963 /* Check if the filter being deleted is a link */ 8964 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8965 jump = adapter->jump_tables[i]; 8966 if (jump && jump->link_hdl == hdl) { 8967 /* Delete filters in the hardware in the child hash 8968 * table associated with this link 8969 */ 8970 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8971 if (!test_bit(j, jump->child_loc_map)) 8972 continue; 8973 spin_lock(&adapter->fdir_perfect_lock); 8974 err = ixgbe_update_ethtool_fdir_entry(adapter, 8975 NULL, 8976 j + 1); 8977 spin_unlock(&adapter->fdir_perfect_lock); 8978 clear_bit(j, jump->child_loc_map); 8979 } 8980 /* Remove resources for this link */ 8981 kfree(jump->input); 8982 kfree(jump->mask); 8983 kfree(jump); 8984 adapter->jump_tables[i] = NULL; 8985 return err; 8986 } 8987 } 8988 8989 spin_lock(&adapter->fdir_perfect_lock); 8990 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8991 spin_unlock(&adapter->fdir_perfect_lock); 8992 return err; 8993 } 8994 8995 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8996 struct tc_cls_u32_offload *cls) 8997 { 8998 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8999 9000 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9001 return -EINVAL; 9002 9003 /* This ixgbe devices do not support hash tables at the moment 9004 * so abort when given hash tables. 9005 */ 9006 if (cls->hnode.divisor > 0) 9007 return -EINVAL; 9008 9009 set_bit(uhtid - 1, &adapter->tables); 9010 return 0; 9011 } 9012 9013 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9014 struct tc_cls_u32_offload *cls) 9015 { 9016 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9017 9018 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9019 return -EINVAL; 9020 9021 clear_bit(uhtid - 1, &adapter->tables); 9022 return 0; 9023 } 9024 9025 #ifdef CONFIG_NET_CLS_ACT 9026 struct upper_walk_data { 9027 struct ixgbe_adapter *adapter; 9028 u64 action; 9029 int ifindex; 9030 u8 queue; 9031 }; 9032 9033 static int get_macvlan_queue(struct net_device *upper, void *_data) 9034 { 9035 if (netif_is_macvlan(upper)) { 9036 struct macvlan_dev *dfwd = netdev_priv(upper); 9037 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 9038 struct upper_walk_data *data = _data; 9039 struct ixgbe_adapter *adapter = data->adapter; 9040 int ifindex = data->ifindex; 9041 9042 if (vadapter && vadapter->netdev->ifindex == ifindex) { 9043 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9044 data->action = data->queue; 9045 return 1; 9046 } 9047 } 9048 9049 return 0; 9050 } 9051 9052 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9053 u8 *queue, u64 *action) 9054 { 9055 unsigned int num_vfs = adapter->num_vfs, vf; 9056 struct upper_walk_data data; 9057 struct net_device *upper; 9058 9059 /* redirect to a SRIOV VF */ 9060 for (vf = 0; vf < num_vfs; ++vf) { 9061 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9062 if (upper->ifindex == ifindex) { 9063 if (adapter->num_rx_pools > 1) 9064 *queue = vf * 2; 9065 else 9066 *queue = vf * adapter->num_rx_queues_per_pool; 9067 9068 *action = vf + 1; 9069 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9070 return 0; 9071 } 9072 } 9073 9074 /* redirect to a offloaded macvlan netdev */ 9075 data.adapter = adapter; 9076 data.ifindex = ifindex; 9077 data.action = 0; 9078 data.queue = 0; 9079 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9080 get_macvlan_queue, &data)) { 9081 *action = data.action; 9082 *queue = data.queue; 9083 9084 return 0; 9085 } 9086 9087 return -EINVAL; 9088 } 9089 9090 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9091 struct tcf_exts *exts, u64 *action, u8 *queue) 9092 { 9093 const struct tc_action *a; 9094 LIST_HEAD(actions); 9095 int err; 9096 9097 if (!tcf_exts_has_actions(exts)) 9098 return -EINVAL; 9099 9100 tcf_exts_to_list(exts, &actions); 9101 list_for_each_entry(a, &actions, list) { 9102 9103 /* Drop action */ 9104 if (is_tcf_gact_shot(a)) { 9105 *action = IXGBE_FDIR_DROP_QUEUE; 9106 *queue = IXGBE_FDIR_DROP_QUEUE; 9107 return 0; 9108 } 9109 9110 /* Redirect to a VF or a offloaded macvlan */ 9111 if (is_tcf_mirred_egress_redirect(a)) { 9112 struct net_device *dev = tcf_mirred_dev(a); 9113 9114 if (!dev) 9115 return -EINVAL; 9116 err = handle_redirect_action(adapter, dev->ifindex, queue, 9117 action); 9118 if (err == 0) 9119 return err; 9120 } 9121 } 9122 9123 return -EINVAL; 9124 } 9125 #else 9126 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9127 struct tcf_exts *exts, u64 *action, u8 *queue) 9128 { 9129 return -EINVAL; 9130 } 9131 #endif /* CONFIG_NET_CLS_ACT */ 9132 9133 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9134 union ixgbe_atr_input *mask, 9135 struct tc_cls_u32_offload *cls, 9136 struct ixgbe_mat_field *field_ptr, 9137 struct ixgbe_nexthdr *nexthdr) 9138 { 9139 int i, j, off; 9140 __be32 val, m; 9141 bool found_entry = false, found_jump_field = false; 9142 9143 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9144 off = cls->knode.sel->keys[i].off; 9145 val = cls->knode.sel->keys[i].val; 9146 m = cls->knode.sel->keys[i].mask; 9147 9148 for (j = 0; field_ptr[j].val; j++) { 9149 if (field_ptr[j].off == off) { 9150 field_ptr[j].val(input, mask, val, m); 9151 input->filter.formatted.flow_type |= 9152 field_ptr[j].type; 9153 found_entry = true; 9154 break; 9155 } 9156 } 9157 if (nexthdr) { 9158 if (nexthdr->off == cls->knode.sel->keys[i].off && 9159 nexthdr->val == cls->knode.sel->keys[i].val && 9160 nexthdr->mask == cls->knode.sel->keys[i].mask) 9161 found_jump_field = true; 9162 else 9163 continue; 9164 } 9165 } 9166 9167 if (nexthdr && !found_jump_field) 9168 return -EINVAL; 9169 9170 if (!found_entry) 9171 return 0; 9172 9173 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9174 IXGBE_ATR_L4TYPE_MASK; 9175 9176 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9177 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9178 9179 return 0; 9180 } 9181 9182 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9183 struct tc_cls_u32_offload *cls) 9184 { 9185 __be16 protocol = cls->common.protocol; 9186 u32 loc = cls->knode.handle & 0xfffff; 9187 struct ixgbe_hw *hw = &adapter->hw; 9188 struct ixgbe_mat_field *field_ptr; 9189 struct ixgbe_fdir_filter *input = NULL; 9190 union ixgbe_atr_input *mask = NULL; 9191 struct ixgbe_jump_table *jump = NULL; 9192 int i, err = -EINVAL; 9193 u8 queue; 9194 u32 uhtid, link_uhtid; 9195 9196 uhtid = TC_U32_USERHTID(cls->knode.handle); 9197 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9198 9199 /* At the moment cls_u32 jumps to network layer and skips past 9200 * L2 headers. The canonical method to match L2 frames is to use 9201 * negative values. However this is error prone at best but really 9202 * just broken because there is no way to "know" what sort of hdr 9203 * is in front of the network layer. Fix cls_u32 to support L2 9204 * headers when needed. 9205 */ 9206 if (protocol != htons(ETH_P_IP)) 9207 return err; 9208 9209 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9210 e_err(drv, "Location out of range\n"); 9211 return err; 9212 } 9213 9214 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9215 * links and also the fields used to advance the parser across each 9216 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9217 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9218 * To add support for new nodes update ixgbe_model.h parse structures 9219 * this function _should_ be generic try not to hardcode values here. 9220 */ 9221 if (uhtid == 0x800) { 9222 field_ptr = (adapter->jump_tables[0])->mat; 9223 } else { 9224 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9225 return err; 9226 if (!adapter->jump_tables[uhtid]) 9227 return err; 9228 field_ptr = (adapter->jump_tables[uhtid])->mat; 9229 } 9230 9231 if (!field_ptr) 9232 return err; 9233 9234 /* At this point we know the field_ptr is valid and need to either 9235 * build cls_u32 link or attach filter. Because adding a link to 9236 * a handle that does not exist is invalid and the same for adding 9237 * rules to handles that don't exist. 9238 */ 9239 9240 if (link_uhtid) { 9241 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9242 9243 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9244 return err; 9245 9246 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9247 return err; 9248 9249 /* Multiple filters as links to the same hash table are not 9250 * supported. To add a new filter with the same next header 9251 * but different match/jump conditions, create a new hash table 9252 * and link to it. 9253 */ 9254 if (adapter->jump_tables[link_uhtid] && 9255 (adapter->jump_tables[link_uhtid])->link_hdl) { 9256 e_err(drv, "Link filter exists for link: %x\n", 9257 link_uhtid); 9258 return err; 9259 } 9260 9261 for (i = 0; nexthdr[i].jump; i++) { 9262 if (nexthdr[i].o != cls->knode.sel->offoff || 9263 nexthdr[i].s != cls->knode.sel->offshift || 9264 nexthdr[i].m != cls->knode.sel->offmask) 9265 return err; 9266 9267 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9268 if (!jump) 9269 return -ENOMEM; 9270 input = kzalloc(sizeof(*input), GFP_KERNEL); 9271 if (!input) { 9272 err = -ENOMEM; 9273 goto free_jump; 9274 } 9275 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9276 if (!mask) { 9277 err = -ENOMEM; 9278 goto free_input; 9279 } 9280 jump->input = input; 9281 jump->mask = mask; 9282 jump->link_hdl = cls->knode.handle; 9283 9284 err = ixgbe_clsu32_build_input(input, mask, cls, 9285 field_ptr, &nexthdr[i]); 9286 if (!err) { 9287 jump->mat = nexthdr[i].jump; 9288 adapter->jump_tables[link_uhtid] = jump; 9289 break; 9290 } 9291 } 9292 return 0; 9293 } 9294 9295 input = kzalloc(sizeof(*input), GFP_KERNEL); 9296 if (!input) 9297 return -ENOMEM; 9298 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9299 if (!mask) { 9300 err = -ENOMEM; 9301 goto free_input; 9302 } 9303 9304 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9305 if ((adapter->jump_tables[uhtid])->input) 9306 memcpy(input, (adapter->jump_tables[uhtid])->input, 9307 sizeof(*input)); 9308 if ((adapter->jump_tables[uhtid])->mask) 9309 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9310 sizeof(*mask)); 9311 9312 /* Lookup in all child hash tables if this location is already 9313 * filled with a filter 9314 */ 9315 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9316 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9317 9318 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9319 e_err(drv, "Filter exists in location: %x\n", 9320 loc); 9321 err = -EINVAL; 9322 goto err_out; 9323 } 9324 } 9325 } 9326 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9327 if (err) 9328 goto err_out; 9329 9330 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9331 &queue); 9332 if (err < 0) 9333 goto err_out; 9334 9335 input->sw_idx = loc; 9336 9337 spin_lock(&adapter->fdir_perfect_lock); 9338 9339 if (hlist_empty(&adapter->fdir_filter_list)) { 9340 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9341 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9342 if (err) 9343 goto err_out_w_lock; 9344 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9345 err = -EINVAL; 9346 goto err_out_w_lock; 9347 } 9348 9349 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9350 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9351 input->sw_idx, queue); 9352 if (!err) 9353 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9354 spin_unlock(&adapter->fdir_perfect_lock); 9355 9356 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9357 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9358 9359 kfree(mask); 9360 return err; 9361 err_out_w_lock: 9362 spin_unlock(&adapter->fdir_perfect_lock); 9363 err_out: 9364 kfree(mask); 9365 free_input: 9366 kfree(input); 9367 free_jump: 9368 kfree(jump); 9369 return err; 9370 } 9371 9372 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9373 struct tc_cls_u32_offload *cls_u32) 9374 { 9375 if (cls_u32->common.chain_index) 9376 return -EOPNOTSUPP; 9377 9378 switch (cls_u32->command) { 9379 case TC_CLSU32_NEW_KNODE: 9380 case TC_CLSU32_REPLACE_KNODE: 9381 return ixgbe_configure_clsu32(adapter, cls_u32); 9382 case TC_CLSU32_DELETE_KNODE: 9383 return ixgbe_delete_clsu32(adapter, cls_u32); 9384 case TC_CLSU32_NEW_HNODE: 9385 case TC_CLSU32_REPLACE_HNODE: 9386 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9387 case TC_CLSU32_DELETE_HNODE: 9388 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9389 default: 9390 return -EOPNOTSUPP; 9391 } 9392 } 9393 9394 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9395 void *cb_priv) 9396 { 9397 struct ixgbe_adapter *adapter = cb_priv; 9398 9399 if (!tc_can_offload(adapter->netdev)) 9400 return -EOPNOTSUPP; 9401 9402 switch (type) { 9403 case TC_SETUP_CLSU32: 9404 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9405 default: 9406 return -EOPNOTSUPP; 9407 } 9408 } 9409 9410 static int ixgbe_setup_tc_block(struct net_device *dev, 9411 struct tc_block_offload *f) 9412 { 9413 struct ixgbe_adapter *adapter = netdev_priv(dev); 9414 9415 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9416 return -EOPNOTSUPP; 9417 9418 switch (f->command) { 9419 case TC_BLOCK_BIND: 9420 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9421 adapter, adapter); 9422 case TC_BLOCK_UNBIND: 9423 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9424 adapter); 9425 return 0; 9426 default: 9427 return -EOPNOTSUPP; 9428 } 9429 } 9430 9431 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9432 struct tc_mqprio_qopt *mqprio) 9433 { 9434 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9435 return ixgbe_setup_tc(dev, mqprio->num_tc); 9436 } 9437 9438 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9439 void *type_data) 9440 { 9441 switch (type) { 9442 case TC_SETUP_BLOCK: 9443 return ixgbe_setup_tc_block(dev, type_data); 9444 case TC_SETUP_QDISC_MQPRIO: 9445 return ixgbe_setup_tc_mqprio(dev, type_data); 9446 default: 9447 return -EOPNOTSUPP; 9448 } 9449 } 9450 9451 #ifdef CONFIG_PCI_IOV 9452 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9453 { 9454 struct net_device *netdev = adapter->netdev; 9455 9456 rtnl_lock(); 9457 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 9458 rtnl_unlock(); 9459 } 9460 9461 #endif 9462 void ixgbe_do_reset(struct net_device *netdev) 9463 { 9464 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9465 9466 if (netif_running(netdev)) 9467 ixgbe_reinit_locked(adapter); 9468 else 9469 ixgbe_reset(adapter); 9470 } 9471 9472 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9473 netdev_features_t features) 9474 { 9475 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9476 9477 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9478 if (!(features & NETIF_F_RXCSUM)) 9479 features &= ~NETIF_F_LRO; 9480 9481 /* Turn off LRO if not RSC capable */ 9482 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9483 features &= ~NETIF_F_LRO; 9484 9485 return features; 9486 } 9487 9488 static int ixgbe_set_features(struct net_device *netdev, 9489 netdev_features_t features) 9490 { 9491 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9492 netdev_features_t changed = netdev->features ^ features; 9493 bool need_reset = false; 9494 9495 /* Make sure RSC matches LRO, reset if change */ 9496 if (!(features & NETIF_F_LRO)) { 9497 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9498 need_reset = true; 9499 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9500 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9501 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9502 if (adapter->rx_itr_setting == 1 || 9503 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9504 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9505 need_reset = true; 9506 } else if ((changed ^ features) & NETIF_F_LRO) { 9507 e_info(probe, "rx-usecs set too low, " 9508 "disabling RSC\n"); 9509 } 9510 } 9511 9512 /* 9513 * Check if Flow Director n-tuple support or hw_tc support was 9514 * enabled or disabled. If the state changed, we need to reset. 9515 */ 9516 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9517 /* turn off ATR, enable perfect filters and reset */ 9518 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9519 need_reset = true; 9520 9521 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9522 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9523 } else { 9524 /* turn off perfect filters, enable ATR and reset */ 9525 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9526 need_reset = true; 9527 9528 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9529 9530 /* We cannot enable ATR if SR-IOV is enabled */ 9531 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9532 /* We cannot enable ATR if we have 2 or more tcs */ 9533 (netdev_get_num_tc(netdev) > 1) || 9534 /* We cannot enable ATR if RSS is disabled */ 9535 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9536 /* A sample rate of 0 indicates ATR disabled */ 9537 (!adapter->atr_sample_rate)) 9538 ; /* do nothing not supported */ 9539 else /* otherwise supported and set the flag */ 9540 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9541 } 9542 9543 if (changed & NETIF_F_RXALL) 9544 need_reset = true; 9545 9546 netdev->features = features; 9547 9548 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9549 if (features & NETIF_F_RXCSUM) { 9550 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9551 } else { 9552 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9553 9554 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9555 } 9556 } 9557 9558 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9559 if (features & NETIF_F_RXCSUM) { 9560 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9561 } else { 9562 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9563 9564 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9565 } 9566 } 9567 9568 if (need_reset) 9569 ixgbe_do_reset(netdev); 9570 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9571 NETIF_F_HW_VLAN_CTAG_FILTER)) 9572 ixgbe_set_rx_mode(netdev); 9573 9574 return 0; 9575 } 9576 9577 /** 9578 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9579 * @dev: The port's netdev 9580 * @ti: Tunnel endpoint information 9581 **/ 9582 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9583 struct udp_tunnel_info *ti) 9584 { 9585 struct ixgbe_adapter *adapter = netdev_priv(dev); 9586 struct ixgbe_hw *hw = &adapter->hw; 9587 __be16 port = ti->port; 9588 u32 port_shift = 0; 9589 u32 reg; 9590 9591 if (ti->sa_family != AF_INET) 9592 return; 9593 9594 switch (ti->type) { 9595 case UDP_TUNNEL_TYPE_VXLAN: 9596 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9597 return; 9598 9599 if (adapter->vxlan_port == port) 9600 return; 9601 9602 if (adapter->vxlan_port) { 9603 netdev_info(dev, 9604 "VXLAN port %d set, not adding port %d\n", 9605 ntohs(adapter->vxlan_port), 9606 ntohs(port)); 9607 return; 9608 } 9609 9610 adapter->vxlan_port = port; 9611 break; 9612 case UDP_TUNNEL_TYPE_GENEVE: 9613 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9614 return; 9615 9616 if (adapter->geneve_port == port) 9617 return; 9618 9619 if (adapter->geneve_port) { 9620 netdev_info(dev, 9621 "GENEVE port %d set, not adding port %d\n", 9622 ntohs(adapter->geneve_port), 9623 ntohs(port)); 9624 return; 9625 } 9626 9627 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9628 adapter->geneve_port = port; 9629 break; 9630 default: 9631 return; 9632 } 9633 9634 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9635 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9636 } 9637 9638 /** 9639 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9640 * @dev: The port's netdev 9641 * @ti: Tunnel endpoint information 9642 **/ 9643 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9644 struct udp_tunnel_info *ti) 9645 { 9646 struct ixgbe_adapter *adapter = netdev_priv(dev); 9647 u32 port_mask; 9648 9649 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9650 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9651 return; 9652 9653 if (ti->sa_family != AF_INET) 9654 return; 9655 9656 switch (ti->type) { 9657 case UDP_TUNNEL_TYPE_VXLAN: 9658 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9659 return; 9660 9661 if (adapter->vxlan_port != ti->port) { 9662 netdev_info(dev, "VXLAN port %d not found\n", 9663 ntohs(ti->port)); 9664 return; 9665 } 9666 9667 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9668 break; 9669 case UDP_TUNNEL_TYPE_GENEVE: 9670 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9671 return; 9672 9673 if (adapter->geneve_port != ti->port) { 9674 netdev_info(dev, "GENEVE port %d not found\n", 9675 ntohs(ti->port)); 9676 return; 9677 } 9678 9679 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9680 break; 9681 default: 9682 return; 9683 } 9684 9685 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9686 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9687 } 9688 9689 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9690 struct net_device *dev, 9691 const unsigned char *addr, u16 vid, 9692 u16 flags) 9693 { 9694 /* guarantee we can provide a unique filter for the unicast address */ 9695 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9696 struct ixgbe_adapter *adapter = netdev_priv(dev); 9697 u16 pool = VMDQ_P(0); 9698 9699 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9700 return -ENOMEM; 9701 } 9702 9703 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9704 } 9705 9706 /** 9707 * ixgbe_configure_bridge_mode - set various bridge modes 9708 * @adapter - the private structure 9709 * @mode - requested bridge mode 9710 * 9711 * Configure some settings require for various bridge modes. 9712 **/ 9713 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9714 __u16 mode) 9715 { 9716 struct ixgbe_hw *hw = &adapter->hw; 9717 unsigned int p, num_pools; 9718 u32 vmdctl; 9719 9720 switch (mode) { 9721 case BRIDGE_MODE_VEPA: 9722 /* disable Tx loopback, rely on switch hairpin mode */ 9723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9724 9725 /* must enable Rx switching replication to allow multicast 9726 * packet reception on all VFs, and to enable source address 9727 * pruning. 9728 */ 9729 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9730 vmdctl |= IXGBE_VT_CTL_REPLEN; 9731 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9732 9733 /* enable Rx source address pruning. Note, this requires 9734 * replication to be enabled or else it does nothing. 9735 */ 9736 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9737 for (p = 0; p < num_pools; p++) { 9738 if (hw->mac.ops.set_source_address_pruning) 9739 hw->mac.ops.set_source_address_pruning(hw, 9740 true, 9741 p); 9742 } 9743 break; 9744 case BRIDGE_MODE_VEB: 9745 /* enable Tx loopback for internal VF/PF communication */ 9746 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9747 IXGBE_PFDTXGSWC_VT_LBEN); 9748 9749 /* disable Rx switching replication unless we have SR-IOV 9750 * virtual functions 9751 */ 9752 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9753 if (!adapter->num_vfs) 9754 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9755 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9756 9757 /* disable Rx source address pruning, since we don't expect to 9758 * be receiving external loopback of our transmitted frames. 9759 */ 9760 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9761 for (p = 0; p < num_pools; p++) { 9762 if (hw->mac.ops.set_source_address_pruning) 9763 hw->mac.ops.set_source_address_pruning(hw, 9764 false, 9765 p); 9766 } 9767 break; 9768 default: 9769 return -EINVAL; 9770 } 9771 9772 adapter->bridge_mode = mode; 9773 9774 e_info(drv, "enabling bridge mode: %s\n", 9775 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9776 9777 return 0; 9778 } 9779 9780 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9781 struct nlmsghdr *nlh, u16 flags) 9782 { 9783 struct ixgbe_adapter *adapter = netdev_priv(dev); 9784 struct nlattr *attr, *br_spec; 9785 int rem; 9786 9787 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9788 return -EOPNOTSUPP; 9789 9790 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9791 if (!br_spec) 9792 return -EINVAL; 9793 9794 nla_for_each_nested(attr, br_spec, rem) { 9795 int status; 9796 __u16 mode; 9797 9798 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9799 continue; 9800 9801 if (nla_len(attr) < sizeof(mode)) 9802 return -EINVAL; 9803 9804 mode = nla_get_u16(attr); 9805 status = ixgbe_configure_bridge_mode(adapter, mode); 9806 if (status) 9807 return status; 9808 9809 break; 9810 } 9811 9812 return 0; 9813 } 9814 9815 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9816 struct net_device *dev, 9817 u32 filter_mask, int nlflags) 9818 { 9819 struct ixgbe_adapter *adapter = netdev_priv(dev); 9820 9821 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9822 return 0; 9823 9824 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9825 adapter->bridge_mode, 0, 0, nlflags, 9826 filter_mask, NULL); 9827 } 9828 9829 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9830 { 9831 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 9832 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9833 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 9834 unsigned int limit; 9835 int pool, err; 9836 9837 /* Hardware has a limited number of available pools. Each VF, and the 9838 * PF require a pool. Check to ensure we don't attempt to use more 9839 * then the available number of pools. 9840 */ 9841 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9842 return ERR_PTR(-EINVAL); 9843 9844 #ifdef CONFIG_RPS 9845 if (vdev->num_rx_queues != vdev->num_tx_queues) { 9846 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 9847 vdev->name); 9848 return ERR_PTR(-EINVAL); 9849 } 9850 #endif 9851 /* Check for hardware restriction on number of rx/tx queues */ 9852 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 9853 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 9854 netdev_info(pdev, 9855 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 9856 pdev->name); 9857 return ERR_PTR(-EINVAL); 9858 } 9859 9860 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9861 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 9862 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 9863 return ERR_PTR(-EBUSY); 9864 9865 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 9866 if (!fwd_adapter) 9867 return ERR_PTR(-ENOMEM); 9868 9869 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 9870 adapter->num_rx_pools++; 9871 set_bit(pool, &adapter->fwd_bitmask); 9872 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9873 9874 /* Enable VMDq flag so device will be set in VM mode */ 9875 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 9876 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9877 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 9878 9879 /* Force reinit of ring allocation with VMDQ enabled */ 9880 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9881 if (err) 9882 goto fwd_add_err; 9883 fwd_adapter->pool = pool; 9884 fwd_adapter->real_adapter = adapter; 9885 9886 if (netif_running(pdev)) { 9887 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 9888 if (err) 9889 goto fwd_add_err; 9890 netif_tx_start_all_queues(vdev); 9891 } 9892 9893 return fwd_adapter; 9894 fwd_add_err: 9895 /* unwind counter and free adapter struct */ 9896 netdev_info(pdev, 9897 "%s: dfwd hardware acceleration failed\n", vdev->name); 9898 clear_bit(pool, &adapter->fwd_bitmask); 9899 adapter->num_rx_pools--; 9900 kfree(fwd_adapter); 9901 return ERR_PTR(err); 9902 } 9903 9904 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9905 { 9906 struct ixgbe_fwd_adapter *fwd_adapter = priv; 9907 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 9908 unsigned int limit; 9909 9910 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 9911 adapter->num_rx_pools--; 9912 9913 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9914 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9915 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 9916 9917 /* go back to full RSS if we're done with our VMQs */ 9918 if (adapter->ring_feature[RING_F_VMDQ].limit == 1) { 9919 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9920 num_online_cpus()); 9921 9922 adapter->flags &= ~IXGBE_FLAG_VMDQ_ENABLED; 9923 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; 9924 adapter->ring_feature[RING_F_RSS].limit = rss; 9925 } 9926 9927 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9928 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 9929 fwd_adapter->pool, adapter->num_rx_pools, 9930 fwd_adapter->rx_base_queue, 9931 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 9932 adapter->fwd_bitmask); 9933 kfree(fwd_adapter); 9934 } 9935 9936 #define IXGBE_MAX_MAC_HDR_LEN 127 9937 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9938 9939 static netdev_features_t 9940 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9941 netdev_features_t features) 9942 { 9943 unsigned int network_hdr_len, mac_hdr_len; 9944 9945 /* Make certain the headers can be described by a context descriptor */ 9946 mac_hdr_len = skb_network_header(skb) - skb->data; 9947 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9948 return features & ~(NETIF_F_HW_CSUM | 9949 NETIF_F_SCTP_CRC | 9950 NETIF_F_HW_VLAN_CTAG_TX | 9951 NETIF_F_TSO | 9952 NETIF_F_TSO6); 9953 9954 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9955 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9956 return features & ~(NETIF_F_HW_CSUM | 9957 NETIF_F_SCTP_CRC | 9958 NETIF_F_TSO | 9959 NETIF_F_TSO6); 9960 9961 /* We can only support IPV4 TSO in tunnels if we can mangle the 9962 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9963 */ 9964 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 9965 features &= ~NETIF_F_TSO; 9966 9967 return features; 9968 } 9969 9970 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9971 { 9972 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9973 struct ixgbe_adapter *adapter = netdev_priv(dev); 9974 struct bpf_prog *old_prog; 9975 9976 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9977 return -EINVAL; 9978 9979 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9980 return -EINVAL; 9981 9982 /* verify ixgbe ring attributes are sufficient for XDP */ 9983 for (i = 0; i < adapter->num_rx_queues; i++) { 9984 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9985 9986 if (ring_is_rsc_enabled(ring)) 9987 return -EINVAL; 9988 9989 if (frame_size > ixgbe_rx_bufsz(ring)) 9990 return -EINVAL; 9991 } 9992 9993 if (nr_cpu_ids > MAX_XDP_QUEUES) 9994 return -ENOMEM; 9995 9996 old_prog = xchg(&adapter->xdp_prog, prog); 9997 9998 /* If transitioning XDP modes reconfigure rings */ 9999 if (!!prog != !!old_prog) { 10000 int err = ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 10001 10002 if (err) { 10003 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10004 return -EINVAL; 10005 } 10006 } else { 10007 for (i = 0; i < adapter->num_rx_queues; i++) 10008 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); 10009 } 10010 10011 if (old_prog) 10012 bpf_prog_put(old_prog); 10013 10014 return 0; 10015 } 10016 10017 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10018 { 10019 struct ixgbe_adapter *adapter = netdev_priv(dev); 10020 10021 switch (xdp->command) { 10022 case XDP_SETUP_PROG: 10023 return ixgbe_xdp_setup(dev, xdp->prog); 10024 case XDP_QUERY_PROG: 10025 xdp->prog_attached = !!(adapter->xdp_prog); 10026 xdp->prog_id = adapter->xdp_prog ? 10027 adapter->xdp_prog->aux->id : 0; 10028 return 0; 10029 default: 10030 return -EINVAL; 10031 } 10032 } 10033 10034 static int ixgbe_xdp_xmit(struct net_device *dev, struct xdp_buff *xdp) 10035 { 10036 struct ixgbe_adapter *adapter = netdev_priv(dev); 10037 struct ixgbe_ring *ring; 10038 int err; 10039 10040 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10041 return -ENETDOWN; 10042 10043 /* During program transitions its possible adapter->xdp_prog is assigned 10044 * but ring has not been configured yet. In this case simply abort xmit. 10045 */ 10046 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10047 if (unlikely(!ring)) 10048 return -ENXIO; 10049 10050 err = ixgbe_xmit_xdp_ring(adapter, xdp); 10051 if (err != IXGBE_XDP_TX) 10052 return -ENOSPC; 10053 10054 return 0; 10055 } 10056 10057 static void ixgbe_xdp_flush(struct net_device *dev) 10058 { 10059 struct ixgbe_adapter *adapter = netdev_priv(dev); 10060 struct ixgbe_ring *ring; 10061 10062 /* Its possible the device went down between xdp xmit and flush so 10063 * we need to ensure device is still up. 10064 */ 10065 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10066 return; 10067 10068 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10069 if (unlikely(!ring)) 10070 return; 10071 10072 /* Force memory writes to complete before letting h/w know there 10073 * are new descriptors to fetch. 10074 */ 10075 wmb(); 10076 writel(ring->next_to_use, ring->tail); 10077 10078 return; 10079 } 10080 10081 static const struct net_device_ops ixgbe_netdev_ops = { 10082 .ndo_open = ixgbe_open, 10083 .ndo_stop = ixgbe_close, 10084 .ndo_start_xmit = ixgbe_xmit_frame, 10085 .ndo_select_queue = ixgbe_select_queue, 10086 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10087 .ndo_validate_addr = eth_validate_addr, 10088 .ndo_set_mac_address = ixgbe_set_mac, 10089 .ndo_change_mtu = ixgbe_change_mtu, 10090 .ndo_tx_timeout = ixgbe_tx_timeout, 10091 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10092 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10093 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10094 .ndo_do_ioctl = ixgbe_ioctl, 10095 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10096 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10097 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10098 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10099 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10100 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10101 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10102 .ndo_get_stats64 = ixgbe_get_stats64, 10103 .ndo_setup_tc = __ixgbe_setup_tc, 10104 #ifdef CONFIG_NET_POLL_CONTROLLER 10105 .ndo_poll_controller = ixgbe_netpoll, 10106 #endif 10107 #ifdef IXGBE_FCOE 10108 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10109 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10110 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10111 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10112 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10113 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10114 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10115 #endif /* IXGBE_FCOE */ 10116 .ndo_set_features = ixgbe_set_features, 10117 .ndo_fix_features = ixgbe_fix_features, 10118 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10119 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10120 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10121 .ndo_dfwd_add_station = ixgbe_fwd_add, 10122 .ndo_dfwd_del_station = ixgbe_fwd_del, 10123 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10124 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10125 .ndo_features_check = ixgbe_features_check, 10126 .ndo_bpf = ixgbe_xdp, 10127 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10128 .ndo_xdp_flush = ixgbe_xdp_flush, 10129 }; 10130 10131 /** 10132 * ixgbe_enumerate_functions - Get the number of ports this device has 10133 * @adapter: adapter structure 10134 * 10135 * This function enumerates the phsyical functions co-located on a single slot, 10136 * in order to determine how many ports a device has. This is most useful in 10137 * determining the required GT/s of PCIe bandwidth necessary for optimal 10138 * performance. 10139 **/ 10140 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10141 { 10142 struct pci_dev *entry, *pdev = adapter->pdev; 10143 int physfns = 0; 10144 10145 /* Some cards can not use the generic count PCIe functions method, 10146 * because they are behind a parent switch, so we hardcode these with 10147 * the correct number of functions. 10148 */ 10149 if (ixgbe_pcie_from_parent(&adapter->hw)) 10150 physfns = 4; 10151 10152 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10153 /* don't count virtual functions */ 10154 if (entry->is_virtfn) 10155 continue; 10156 10157 /* When the devices on the bus don't all match our device ID, 10158 * we can't reliably determine the correct number of 10159 * functions. This can occur if a function has been direct 10160 * attached to a virtual machine using VT-d, for example. In 10161 * this case, simply return -1 to indicate this. 10162 */ 10163 if ((entry->vendor != pdev->vendor) || 10164 (entry->device != pdev->device)) 10165 return -1; 10166 10167 physfns++; 10168 } 10169 10170 return physfns; 10171 } 10172 10173 /** 10174 * ixgbe_wol_supported - Check whether device supports WoL 10175 * @adapter: the adapter private structure 10176 * @device_id: the device ID 10177 * @subdev_id: the subsystem device ID 10178 * 10179 * This function is used by probe and ethtool to determine 10180 * which devices have WoL support 10181 * 10182 **/ 10183 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10184 u16 subdevice_id) 10185 { 10186 struct ixgbe_hw *hw = &adapter->hw; 10187 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10188 10189 /* WOL not supported on 82598 */ 10190 if (hw->mac.type == ixgbe_mac_82598EB) 10191 return false; 10192 10193 /* check eeprom to see if WOL is enabled for X540 and newer */ 10194 if (hw->mac.type >= ixgbe_mac_X540) { 10195 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10196 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10197 (hw->bus.func == 0))) 10198 return true; 10199 } 10200 10201 /* WOL is determined based on device IDs for 82599 MACs */ 10202 switch (device_id) { 10203 case IXGBE_DEV_ID_82599_SFP: 10204 /* Only these subdevices could supports WOL */ 10205 switch (subdevice_id) { 10206 case IXGBE_SUBDEV_ID_82599_560FLR: 10207 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10208 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10209 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10210 /* only support first port */ 10211 if (hw->bus.func != 0) 10212 break; 10213 /* fall through */ 10214 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10215 case IXGBE_SUBDEV_ID_82599_SFP: 10216 case IXGBE_SUBDEV_ID_82599_RNDC: 10217 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10218 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10219 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10220 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10221 return true; 10222 } 10223 break; 10224 case IXGBE_DEV_ID_82599EN_SFP: 10225 /* Only these subdevices support WOL */ 10226 switch (subdevice_id) { 10227 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10228 return true; 10229 } 10230 break; 10231 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10232 /* All except this subdevice support WOL */ 10233 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10234 return true; 10235 break; 10236 case IXGBE_DEV_ID_82599_KX4: 10237 return true; 10238 default: 10239 break; 10240 } 10241 10242 return false; 10243 } 10244 10245 /** 10246 * ixgbe_probe - Device Initialization Routine 10247 * @pdev: PCI device information struct 10248 * @ent: entry in ixgbe_pci_tbl 10249 * 10250 * Returns 0 on success, negative on failure 10251 * 10252 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10253 * The OS initialization, configuring of the adapter private structure, 10254 * and a hardware reset occur. 10255 **/ 10256 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10257 { 10258 struct net_device *netdev; 10259 struct ixgbe_adapter *adapter = NULL; 10260 struct ixgbe_hw *hw; 10261 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10262 int i, err, pci_using_dac, expected_gts; 10263 unsigned int indices = MAX_TX_QUEUES; 10264 u8 part_str[IXGBE_PBANUM_LENGTH]; 10265 bool disable_dev = false; 10266 #ifdef IXGBE_FCOE 10267 u16 device_caps; 10268 #endif 10269 u32 eec; 10270 10271 /* Catch broken hardware that put the wrong VF device ID in 10272 * the PCIe SR-IOV capability. 10273 */ 10274 if (pdev->is_virtfn) { 10275 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10276 pci_name(pdev), pdev->vendor, pdev->device); 10277 return -EINVAL; 10278 } 10279 10280 err = pci_enable_device_mem(pdev); 10281 if (err) 10282 return err; 10283 10284 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10285 pci_using_dac = 1; 10286 } else { 10287 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10288 if (err) { 10289 dev_err(&pdev->dev, 10290 "No usable DMA configuration, aborting\n"); 10291 goto err_dma; 10292 } 10293 pci_using_dac = 0; 10294 } 10295 10296 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10297 if (err) { 10298 dev_err(&pdev->dev, 10299 "pci_request_selected_regions failed 0x%x\n", err); 10300 goto err_pci_reg; 10301 } 10302 10303 pci_enable_pcie_error_reporting(pdev); 10304 10305 pci_set_master(pdev); 10306 pci_save_state(pdev); 10307 10308 if (ii->mac == ixgbe_mac_82598EB) { 10309 #ifdef CONFIG_IXGBE_DCB 10310 /* 8 TC w/ 4 queues per TC */ 10311 indices = 4 * MAX_TRAFFIC_CLASS; 10312 #else 10313 indices = IXGBE_MAX_RSS_INDICES; 10314 #endif 10315 } 10316 10317 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10318 if (!netdev) { 10319 err = -ENOMEM; 10320 goto err_alloc_etherdev; 10321 } 10322 10323 SET_NETDEV_DEV(netdev, &pdev->dev); 10324 10325 adapter = netdev_priv(netdev); 10326 10327 adapter->netdev = netdev; 10328 adapter->pdev = pdev; 10329 hw = &adapter->hw; 10330 hw->back = adapter; 10331 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10332 10333 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10334 pci_resource_len(pdev, 0)); 10335 adapter->io_addr = hw->hw_addr; 10336 if (!hw->hw_addr) { 10337 err = -EIO; 10338 goto err_ioremap; 10339 } 10340 10341 netdev->netdev_ops = &ixgbe_netdev_ops; 10342 ixgbe_set_ethtool_ops(netdev); 10343 netdev->watchdog_timeo = 5 * HZ; 10344 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10345 10346 /* Setup hw api */ 10347 hw->mac.ops = *ii->mac_ops; 10348 hw->mac.type = ii->mac; 10349 hw->mvals = ii->mvals; 10350 if (ii->link_ops) 10351 hw->link.ops = *ii->link_ops; 10352 10353 /* EEPROM */ 10354 hw->eeprom.ops = *ii->eeprom_ops; 10355 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10356 if (ixgbe_removed(hw->hw_addr)) { 10357 err = -EIO; 10358 goto err_ioremap; 10359 } 10360 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10361 if (!(eec & BIT(8))) 10362 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10363 10364 /* PHY */ 10365 hw->phy.ops = *ii->phy_ops; 10366 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10367 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10368 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10369 hw->phy.mdio.mmds = 0; 10370 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10371 hw->phy.mdio.dev = netdev; 10372 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10373 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10374 10375 /* setup the private structure */ 10376 err = ixgbe_sw_init(adapter, ii); 10377 if (err) 10378 goto err_sw_init; 10379 10380 /* Make sure the SWFW semaphore is in a valid state */ 10381 if (hw->mac.ops.init_swfw_sync) 10382 hw->mac.ops.init_swfw_sync(hw); 10383 10384 /* Make it possible the adapter to be woken up via WOL */ 10385 switch (adapter->hw.mac.type) { 10386 case ixgbe_mac_82599EB: 10387 case ixgbe_mac_X540: 10388 case ixgbe_mac_X550: 10389 case ixgbe_mac_X550EM_x: 10390 case ixgbe_mac_x550em_a: 10391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10392 break; 10393 default: 10394 break; 10395 } 10396 10397 /* 10398 * If there is a fan on this device and it has failed log the 10399 * failure. 10400 */ 10401 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10402 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10403 if (esdp & IXGBE_ESDP_SDP1) 10404 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10405 } 10406 10407 if (allow_unsupported_sfp) 10408 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10409 10410 /* reset_hw fills in the perm_addr as well */ 10411 hw->phy.reset_if_overtemp = true; 10412 err = hw->mac.ops.reset_hw(hw); 10413 hw->phy.reset_if_overtemp = false; 10414 ixgbe_set_eee_capable(adapter); 10415 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10416 err = 0; 10417 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10418 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10419 e_dev_err("Reload the driver after installing a supported module.\n"); 10420 goto err_sw_init; 10421 } else if (err) { 10422 e_dev_err("HW Init failed: %d\n", err); 10423 goto err_sw_init; 10424 } 10425 10426 #ifdef CONFIG_PCI_IOV 10427 /* SR-IOV not supported on the 82598 */ 10428 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10429 goto skip_sriov; 10430 /* Mailbox */ 10431 ixgbe_init_mbx_params_pf(hw); 10432 hw->mbx.ops = ii->mbx_ops; 10433 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10434 ixgbe_enable_sriov(adapter, max_vfs); 10435 skip_sriov: 10436 10437 #endif 10438 netdev->features = NETIF_F_SG | 10439 NETIF_F_TSO | 10440 NETIF_F_TSO6 | 10441 NETIF_F_RXHASH | 10442 NETIF_F_RXCSUM | 10443 NETIF_F_HW_CSUM; 10444 10445 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10446 NETIF_F_GSO_GRE_CSUM | \ 10447 NETIF_F_GSO_IPXIP4 | \ 10448 NETIF_F_GSO_IPXIP6 | \ 10449 NETIF_F_GSO_UDP_TUNNEL | \ 10450 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10451 10452 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10453 netdev->features |= NETIF_F_GSO_PARTIAL | 10454 IXGBE_GSO_PARTIAL_FEATURES; 10455 10456 if (hw->mac.type >= ixgbe_mac_82599EB) 10457 netdev->features |= NETIF_F_SCTP_CRC; 10458 10459 /* copy netdev features into list of user selectable features */ 10460 netdev->hw_features |= netdev->features | 10461 NETIF_F_HW_VLAN_CTAG_FILTER | 10462 NETIF_F_HW_VLAN_CTAG_RX | 10463 NETIF_F_HW_VLAN_CTAG_TX | 10464 NETIF_F_RXALL | 10465 NETIF_F_HW_L2FW_DOFFLOAD; 10466 10467 if (hw->mac.type >= ixgbe_mac_82599EB) 10468 netdev->hw_features |= NETIF_F_NTUPLE | 10469 NETIF_F_HW_TC; 10470 10471 if (pci_using_dac) 10472 netdev->features |= NETIF_F_HIGHDMA; 10473 10474 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10475 netdev->hw_enc_features |= netdev->vlan_features; 10476 netdev->mpls_features |= NETIF_F_SG | 10477 NETIF_F_TSO | 10478 NETIF_F_TSO6 | 10479 NETIF_F_HW_CSUM; 10480 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10481 10482 /* set this bit last since it cannot be part of vlan_features */ 10483 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10484 NETIF_F_HW_VLAN_CTAG_RX | 10485 NETIF_F_HW_VLAN_CTAG_TX; 10486 10487 netdev->priv_flags |= IFF_UNICAST_FLT; 10488 netdev->priv_flags |= IFF_SUPP_NOFCS; 10489 10490 /* MTU range: 68 - 9710 */ 10491 netdev->min_mtu = ETH_MIN_MTU; 10492 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10493 10494 #ifdef CONFIG_IXGBE_DCB 10495 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10496 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10497 #endif 10498 10499 #ifdef IXGBE_FCOE 10500 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10501 unsigned int fcoe_l; 10502 10503 if (hw->mac.ops.get_device_caps) { 10504 hw->mac.ops.get_device_caps(hw, &device_caps); 10505 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10506 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10507 } 10508 10509 10510 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10511 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10512 10513 netdev->features |= NETIF_F_FSO | 10514 NETIF_F_FCOE_CRC; 10515 10516 netdev->vlan_features |= NETIF_F_FSO | 10517 NETIF_F_FCOE_CRC | 10518 NETIF_F_FCOE_MTU; 10519 } 10520 #endif /* IXGBE_FCOE */ 10521 10522 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10523 netdev->hw_features |= NETIF_F_LRO; 10524 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10525 netdev->features |= NETIF_F_LRO; 10526 10527 /* make sure the EEPROM is good */ 10528 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10529 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10530 err = -EIO; 10531 goto err_sw_init; 10532 } 10533 10534 eth_platform_get_mac_address(&adapter->pdev->dev, 10535 adapter->hw.mac.perm_addr); 10536 10537 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10538 10539 if (!is_valid_ether_addr(netdev->dev_addr)) { 10540 e_dev_err("invalid MAC address\n"); 10541 err = -EIO; 10542 goto err_sw_init; 10543 } 10544 10545 /* Set hw->mac.addr to permanent MAC address */ 10546 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10547 ixgbe_mac_set_default_filter(adapter); 10548 10549 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10550 10551 if (ixgbe_removed(hw->hw_addr)) { 10552 err = -EIO; 10553 goto err_sw_init; 10554 } 10555 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10556 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10557 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10558 10559 err = ixgbe_init_interrupt_scheme(adapter); 10560 if (err) 10561 goto err_sw_init; 10562 10563 for (i = 0; i < adapter->num_rx_queues; i++) 10564 u64_stats_init(&adapter->rx_ring[i]->syncp); 10565 for (i = 0; i < adapter->num_tx_queues; i++) 10566 u64_stats_init(&adapter->tx_ring[i]->syncp); 10567 for (i = 0; i < adapter->num_xdp_queues; i++) 10568 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10569 10570 /* WOL not supported for all devices */ 10571 adapter->wol = 0; 10572 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10573 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10574 pdev->subsystem_device); 10575 if (hw->wol_enabled) 10576 adapter->wol = IXGBE_WUFC_MAG; 10577 10578 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10579 10580 /* save off EEPROM version number */ 10581 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 10582 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 10583 10584 /* pick up the PCI bus settings for reporting later */ 10585 if (ixgbe_pcie_from_parent(hw)) 10586 ixgbe_get_parent_bus_info(adapter); 10587 else 10588 hw->mac.ops.get_bus_info(hw); 10589 10590 /* calculate the expected PCIe bandwidth required for optimal 10591 * performance. Note that some older parts will never have enough 10592 * bandwidth due to being older generation PCIe parts. We clamp these 10593 * parts to ensure no warning is displayed if it can't be fixed. 10594 */ 10595 switch (hw->mac.type) { 10596 case ixgbe_mac_82598EB: 10597 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10598 break; 10599 default: 10600 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10601 break; 10602 } 10603 10604 /* don't check link if we failed to enumerate functions */ 10605 if (expected_gts > 0) 10606 ixgbe_check_minimum_link(adapter, expected_gts); 10607 10608 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10609 if (err) 10610 strlcpy(part_str, "Unknown", sizeof(part_str)); 10611 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10612 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10613 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10614 part_str); 10615 else 10616 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10617 hw->mac.type, hw->phy.type, part_str); 10618 10619 e_dev_info("%pM\n", netdev->dev_addr); 10620 10621 /* reset the hardware with the new settings */ 10622 err = hw->mac.ops.start_hw(hw); 10623 if (err == IXGBE_ERR_EEPROM_VERSION) { 10624 /* We are running on a pre-production device, log a warning */ 10625 e_dev_warn("This device is a pre-production adapter/LOM. " 10626 "Please be aware there may be issues associated " 10627 "with your hardware. If you are experiencing " 10628 "problems please contact your Intel or hardware " 10629 "representative who provided you with this " 10630 "hardware.\n"); 10631 } 10632 strcpy(netdev->name, "eth%d"); 10633 pci_set_drvdata(pdev, adapter); 10634 err = register_netdev(netdev); 10635 if (err) 10636 goto err_register; 10637 10638 10639 /* power down the optics for 82599 SFP+ fiber */ 10640 if (hw->mac.ops.disable_tx_laser) 10641 hw->mac.ops.disable_tx_laser(hw); 10642 10643 /* carrier off reporting is important to ethtool even BEFORE open */ 10644 netif_carrier_off(netdev); 10645 10646 #ifdef CONFIG_IXGBE_DCA 10647 if (dca_add_requester(&pdev->dev) == 0) { 10648 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10649 ixgbe_setup_dca(adapter); 10650 } 10651 #endif 10652 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10653 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10654 for (i = 0; i < adapter->num_vfs; i++) 10655 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10656 } 10657 10658 /* firmware requires driver version to be 0xFFFFFFFF 10659 * since os does not support feature 10660 */ 10661 if (hw->mac.ops.set_fw_drv_ver) 10662 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10663 sizeof(ixgbe_driver_version) - 1, 10664 ixgbe_driver_version); 10665 10666 /* add san mac addr to netdev */ 10667 ixgbe_add_sanmac_netdev(netdev); 10668 10669 e_dev_info("%s\n", ixgbe_default_device_descr); 10670 10671 #ifdef CONFIG_IXGBE_HWMON 10672 if (ixgbe_sysfs_init(adapter)) 10673 e_err(probe, "failed to allocate sysfs resources\n"); 10674 #endif /* CONFIG_IXGBE_HWMON */ 10675 10676 ixgbe_dbg_adapter_init(adapter); 10677 10678 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10679 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10680 hw->mac.ops.setup_link(hw, 10681 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10682 true); 10683 10684 return 0; 10685 10686 err_register: 10687 ixgbe_release_hw_control(adapter); 10688 ixgbe_clear_interrupt_scheme(adapter); 10689 err_sw_init: 10690 ixgbe_disable_sriov(adapter); 10691 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10692 iounmap(adapter->io_addr); 10693 kfree(adapter->jump_tables[0]); 10694 kfree(adapter->mac_table); 10695 kfree(adapter->rss_key); 10696 err_ioremap: 10697 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10698 free_netdev(netdev); 10699 err_alloc_etherdev: 10700 pci_release_mem_regions(pdev); 10701 err_pci_reg: 10702 err_dma: 10703 if (!adapter || disable_dev) 10704 pci_disable_device(pdev); 10705 return err; 10706 } 10707 10708 /** 10709 * ixgbe_remove - Device Removal Routine 10710 * @pdev: PCI device information struct 10711 * 10712 * ixgbe_remove is called by the PCI subsystem to alert the driver 10713 * that it should release a PCI device. The could be caused by a 10714 * Hot-Plug event, or because the driver is going to be removed from 10715 * memory. 10716 **/ 10717 static void ixgbe_remove(struct pci_dev *pdev) 10718 { 10719 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10720 struct net_device *netdev; 10721 bool disable_dev; 10722 int i; 10723 10724 /* if !adapter then we already cleaned up in probe */ 10725 if (!adapter) 10726 return; 10727 10728 netdev = adapter->netdev; 10729 ixgbe_dbg_adapter_exit(adapter); 10730 10731 set_bit(__IXGBE_REMOVING, &adapter->state); 10732 cancel_work_sync(&adapter->service_task); 10733 10734 10735 #ifdef CONFIG_IXGBE_DCA 10736 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10737 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10738 dca_remove_requester(&pdev->dev); 10739 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10740 IXGBE_DCA_CTRL_DCA_DISABLE); 10741 } 10742 10743 #endif 10744 #ifdef CONFIG_IXGBE_HWMON 10745 ixgbe_sysfs_exit(adapter); 10746 #endif /* CONFIG_IXGBE_HWMON */ 10747 10748 /* remove the added san mac */ 10749 ixgbe_del_sanmac_netdev(netdev); 10750 10751 #ifdef CONFIG_PCI_IOV 10752 ixgbe_disable_sriov(adapter); 10753 #endif 10754 if (netdev->reg_state == NETREG_REGISTERED) 10755 unregister_netdev(netdev); 10756 10757 ixgbe_clear_interrupt_scheme(adapter); 10758 10759 ixgbe_release_hw_control(adapter); 10760 10761 #ifdef CONFIG_DCB 10762 kfree(adapter->ixgbe_ieee_pfc); 10763 kfree(adapter->ixgbe_ieee_ets); 10764 10765 #endif 10766 iounmap(adapter->io_addr); 10767 pci_release_mem_regions(pdev); 10768 10769 e_dev_info("complete\n"); 10770 10771 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10772 if (adapter->jump_tables[i]) { 10773 kfree(adapter->jump_tables[i]->input); 10774 kfree(adapter->jump_tables[i]->mask); 10775 } 10776 kfree(adapter->jump_tables[i]); 10777 } 10778 10779 kfree(adapter->mac_table); 10780 kfree(adapter->rss_key); 10781 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10782 free_netdev(netdev); 10783 10784 pci_disable_pcie_error_reporting(pdev); 10785 10786 if (disable_dev) 10787 pci_disable_device(pdev); 10788 } 10789 10790 /** 10791 * ixgbe_io_error_detected - called when PCI error is detected 10792 * @pdev: Pointer to PCI device 10793 * @state: The current pci connection state 10794 * 10795 * This function is called after a PCI bus error affecting 10796 * this device has been detected. 10797 */ 10798 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10799 pci_channel_state_t state) 10800 { 10801 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10802 struct net_device *netdev = adapter->netdev; 10803 10804 #ifdef CONFIG_PCI_IOV 10805 struct ixgbe_hw *hw = &adapter->hw; 10806 struct pci_dev *bdev, *vfdev; 10807 u32 dw0, dw1, dw2, dw3; 10808 int vf, pos; 10809 u16 req_id, pf_func; 10810 10811 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10812 adapter->num_vfs == 0) 10813 goto skip_bad_vf_detection; 10814 10815 bdev = pdev->bus->self; 10816 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10817 bdev = bdev->bus->self; 10818 10819 if (!bdev) 10820 goto skip_bad_vf_detection; 10821 10822 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10823 if (!pos) 10824 goto skip_bad_vf_detection; 10825 10826 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10827 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10828 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10829 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10830 if (ixgbe_removed(hw->hw_addr)) 10831 goto skip_bad_vf_detection; 10832 10833 req_id = dw1 >> 16; 10834 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10835 if (!(req_id & 0x0080)) 10836 goto skip_bad_vf_detection; 10837 10838 pf_func = req_id & 0x01; 10839 if ((pf_func & 1) == (pdev->devfn & 1)) { 10840 unsigned int device_id; 10841 10842 vf = (req_id & 0x7F) >> 1; 10843 e_dev_err("VF %d has caused a PCIe error\n", vf); 10844 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10845 "%8.8x\tdw3: %8.8x\n", 10846 dw0, dw1, dw2, dw3); 10847 switch (adapter->hw.mac.type) { 10848 case ixgbe_mac_82599EB: 10849 device_id = IXGBE_82599_VF_DEVICE_ID; 10850 break; 10851 case ixgbe_mac_X540: 10852 device_id = IXGBE_X540_VF_DEVICE_ID; 10853 break; 10854 case ixgbe_mac_X550: 10855 device_id = IXGBE_DEV_ID_X550_VF; 10856 break; 10857 case ixgbe_mac_X550EM_x: 10858 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10859 break; 10860 case ixgbe_mac_x550em_a: 10861 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10862 break; 10863 default: 10864 device_id = 0; 10865 break; 10866 } 10867 10868 /* Find the pci device of the offending VF */ 10869 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10870 while (vfdev) { 10871 if (vfdev->devfn == (req_id & 0xFF)) 10872 break; 10873 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10874 device_id, vfdev); 10875 } 10876 /* 10877 * There's a slim chance the VF could have been hot plugged, 10878 * so if it is no longer present we don't need to issue the 10879 * VFLR. Just clean up the AER in that case. 10880 */ 10881 if (vfdev) { 10882 pcie_flr(vfdev); 10883 /* Free device reference count */ 10884 pci_dev_put(vfdev); 10885 } 10886 10887 pci_cleanup_aer_uncorrect_error_status(pdev); 10888 } 10889 10890 /* 10891 * Even though the error may have occurred on the other port 10892 * we still need to increment the vf error reference count for 10893 * both ports because the I/O resume function will be called 10894 * for both of them. 10895 */ 10896 adapter->vferr_refcount++; 10897 10898 return PCI_ERS_RESULT_RECOVERED; 10899 10900 skip_bad_vf_detection: 10901 #endif /* CONFIG_PCI_IOV */ 10902 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10903 return PCI_ERS_RESULT_DISCONNECT; 10904 10905 if (!netif_device_present(netdev)) 10906 return PCI_ERS_RESULT_DISCONNECT; 10907 10908 rtnl_lock(); 10909 netif_device_detach(netdev); 10910 10911 if (state == pci_channel_io_perm_failure) { 10912 rtnl_unlock(); 10913 return PCI_ERS_RESULT_DISCONNECT; 10914 } 10915 10916 if (netif_running(netdev)) 10917 ixgbe_close_suspend(adapter); 10918 10919 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10920 pci_disable_device(pdev); 10921 rtnl_unlock(); 10922 10923 /* Request a slot reset. */ 10924 return PCI_ERS_RESULT_NEED_RESET; 10925 } 10926 10927 /** 10928 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10929 * @pdev: Pointer to PCI device 10930 * 10931 * Restart the card from scratch, as if from a cold-boot. 10932 */ 10933 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10934 { 10935 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10936 pci_ers_result_t result; 10937 int err; 10938 10939 if (pci_enable_device_mem(pdev)) { 10940 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10941 result = PCI_ERS_RESULT_DISCONNECT; 10942 } else { 10943 smp_mb__before_atomic(); 10944 clear_bit(__IXGBE_DISABLED, &adapter->state); 10945 adapter->hw.hw_addr = adapter->io_addr; 10946 pci_set_master(pdev); 10947 pci_restore_state(pdev); 10948 pci_save_state(pdev); 10949 10950 pci_wake_from_d3(pdev, false); 10951 10952 ixgbe_reset(adapter); 10953 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10954 result = PCI_ERS_RESULT_RECOVERED; 10955 } 10956 10957 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10958 if (err) { 10959 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10960 "failed 0x%0x\n", err); 10961 /* non-fatal, continue */ 10962 } 10963 10964 return result; 10965 } 10966 10967 /** 10968 * ixgbe_io_resume - called when traffic can start flowing again. 10969 * @pdev: Pointer to PCI device 10970 * 10971 * This callback is called when the error recovery driver tells us that 10972 * its OK to resume normal operation. 10973 */ 10974 static void ixgbe_io_resume(struct pci_dev *pdev) 10975 { 10976 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10977 struct net_device *netdev = adapter->netdev; 10978 10979 #ifdef CONFIG_PCI_IOV 10980 if (adapter->vferr_refcount) { 10981 e_info(drv, "Resuming after VF err\n"); 10982 adapter->vferr_refcount--; 10983 return; 10984 } 10985 10986 #endif 10987 rtnl_lock(); 10988 if (netif_running(netdev)) 10989 ixgbe_open(netdev); 10990 10991 netif_device_attach(netdev); 10992 rtnl_unlock(); 10993 } 10994 10995 static const struct pci_error_handlers ixgbe_err_handler = { 10996 .error_detected = ixgbe_io_error_detected, 10997 .slot_reset = ixgbe_io_slot_reset, 10998 .resume = ixgbe_io_resume, 10999 }; 11000 11001 static struct pci_driver ixgbe_driver = { 11002 .name = ixgbe_driver_name, 11003 .id_table = ixgbe_pci_tbl, 11004 .probe = ixgbe_probe, 11005 .remove = ixgbe_remove, 11006 #ifdef CONFIG_PM 11007 .suspend = ixgbe_suspend, 11008 .resume = ixgbe_resume, 11009 #endif 11010 .shutdown = ixgbe_shutdown, 11011 .sriov_configure = ixgbe_pci_sriov_configure, 11012 .err_handler = &ixgbe_err_handler 11013 }; 11014 11015 /** 11016 * ixgbe_init_module - Driver Registration Routine 11017 * 11018 * ixgbe_init_module is the first routine called when the driver is 11019 * loaded. All it does is register with the PCI subsystem. 11020 **/ 11021 static int __init ixgbe_init_module(void) 11022 { 11023 int ret; 11024 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11025 pr_info("%s\n", ixgbe_copyright); 11026 11027 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11028 if (!ixgbe_wq) { 11029 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11030 return -ENOMEM; 11031 } 11032 11033 ixgbe_dbg_init(); 11034 11035 ret = pci_register_driver(&ixgbe_driver); 11036 if (ret) { 11037 destroy_workqueue(ixgbe_wq); 11038 ixgbe_dbg_exit(); 11039 return ret; 11040 } 11041 11042 #ifdef CONFIG_IXGBE_DCA 11043 dca_register_notify(&dca_notifier); 11044 #endif 11045 11046 return 0; 11047 } 11048 11049 module_init(ixgbe_init_module); 11050 11051 /** 11052 * ixgbe_exit_module - Driver Exit Cleanup Routine 11053 * 11054 * ixgbe_exit_module is called just before the driver is removed 11055 * from memory. 11056 **/ 11057 static void __exit ixgbe_exit_module(void) 11058 { 11059 #ifdef CONFIG_IXGBE_DCA 11060 dca_unregister_notify(&dca_notifier); 11061 #endif 11062 pci_unregister_driver(&ixgbe_driver); 11063 11064 ixgbe_dbg_exit(); 11065 if (ixgbe_wq) { 11066 destroy_workqueue(ixgbe_wq); 11067 ixgbe_wq = NULL; 11068 } 11069 } 11070 11071 #ifdef CONFIG_IXGBE_DCA 11072 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11073 void *p) 11074 { 11075 int ret_val; 11076 11077 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11078 __ixgbe_notify_dca); 11079 11080 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11081 } 11082 11083 #endif /* CONFIG_IXGBE_DCA */ 11084 11085 module_exit(ixgbe_exit_module); 11086 11087 /* ixgbe_main.c */ 11088