1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/vmalloc.h>
9 #include <linux/string.h>
10 #include <linux/in.h>
11 #include <linux/interrupt.h>
12 #include <linux/ip.h>
13 #include <linux/tcp.h>
14 #include <linux/sctp.h>
15 #include <linux/pkt_sched.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/etherdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/if_macvlan.h>
25 #include <linux/if_bridge.h>
26 #include <linux/prefetch.h>
27 #include <linux/bpf.h>
28 #include <linux/bpf_trace.h>
29 #include <linux/atomic.h>
30 #include <scsi/fc/fc_fcoe.h>
31 #include <net/udp_tunnel.h>
32 #include <net/pkt_cls.h>
33 #include <net/tc_act/tc_gact.h>
34 #include <net/tc_act/tc_mirred.h>
35 #include <net/vxlan.h>
36 #include <net/mpls.h>
37 
38 #include "ixgbe.h"
39 #include "ixgbe_common.h"
40 #include "ixgbe_dcb_82599.h"
41 #include "ixgbe_sriov.h"
42 #include "ixgbe_model.h"
43 
44 char ixgbe_driver_name[] = "ixgbe";
45 static const char ixgbe_driver_string[] =
46 			      "Intel(R) 10 Gigabit PCI Express Network Driver";
47 #ifdef IXGBE_FCOE
48 char ixgbe_default_device_descr[] =
49 			      "Intel(R) 10 Gigabit Network Connection";
50 #else
51 static char ixgbe_default_device_descr[] =
52 			      "Intel(R) 10 Gigabit Network Connection";
53 #endif
54 #define DRV_VERSION "5.1.0-k"
55 const char ixgbe_driver_version[] = DRV_VERSION;
56 static const char ixgbe_copyright[] =
57 				"Copyright (c) 1999-2016 Intel Corporation.";
58 
59 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
60 
61 static const struct ixgbe_info *ixgbe_info_tbl[] = {
62 	[board_82598]		= &ixgbe_82598_info,
63 	[board_82599]		= &ixgbe_82599_info,
64 	[board_X540]		= &ixgbe_X540_info,
65 	[board_X550]		= &ixgbe_X550_info,
66 	[board_X550EM_x]	= &ixgbe_X550EM_x_info,
67 	[board_x550em_x_fw]	= &ixgbe_x550em_x_fw_info,
68 	[board_x550em_a]	= &ixgbe_x550em_a_info,
69 	[board_x550em_a_fw]	= &ixgbe_x550em_a_fw_info,
70 };
71 
72 /* ixgbe_pci_tbl - PCI Device ID Table
73  *
74  * Wildcard entries (PCI_ANY_ID) should come last
75  * Last entry must be all 0s
76  *
77  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78  *   Class, Class Mask, private data (not used) }
79  */
80 static const struct pci_device_id ixgbe_pci_tbl[] = {
81 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
82 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
83 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
84 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
85 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
86 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
87 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
88 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
89 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
90 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
91 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
92 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
93 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
94 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
95 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
96 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
97 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
98 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
99 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
100 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
101 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
102 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
103 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
104 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
105 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
106 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
107 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
108 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
109 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
110 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
111 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
112 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
113 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
114 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
115 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
116 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
117 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
118 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
119 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
120 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
121 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
122 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
123 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
124 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
125 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
126 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
127 	{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
128 	/* required last entry */
129 	{0, }
130 };
131 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
132 
133 #ifdef CONFIG_IXGBE_DCA
134 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
135 			    void *p);
136 static struct notifier_block dca_notifier = {
137 	.notifier_call = ixgbe_notify_dca,
138 	.next          = NULL,
139 	.priority      = 0
140 };
141 #endif
142 
143 #ifdef CONFIG_PCI_IOV
144 static unsigned int max_vfs;
145 module_param(max_vfs, uint, 0);
146 MODULE_PARM_DESC(max_vfs,
147 		 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
148 #endif /* CONFIG_PCI_IOV */
149 
150 static unsigned int allow_unsupported_sfp;
151 module_param(allow_unsupported_sfp, uint, 0);
152 MODULE_PARM_DESC(allow_unsupported_sfp,
153 		 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
154 
155 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
156 static int debug = -1;
157 module_param(debug, int, 0);
158 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
159 
160 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
161 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
162 MODULE_LICENSE("GPL");
163 MODULE_VERSION(DRV_VERSION);
164 
165 static struct workqueue_struct *ixgbe_wq;
166 
167 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
168 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
169 
170 static const struct net_device_ops ixgbe_netdev_ops;
171 
172 static bool netif_is_ixgbe(struct net_device *dev)
173 {
174 	return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
175 }
176 
177 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
178 					  u32 reg, u16 *value)
179 {
180 	struct pci_dev *parent_dev;
181 	struct pci_bus *parent_bus;
182 
183 	parent_bus = adapter->pdev->bus->parent;
184 	if (!parent_bus)
185 		return -1;
186 
187 	parent_dev = parent_bus->self;
188 	if (!parent_dev)
189 		return -1;
190 
191 	if (!pci_is_pcie(parent_dev))
192 		return -1;
193 
194 	pcie_capability_read_word(parent_dev, reg, value);
195 	if (*value == IXGBE_FAILED_READ_CFG_WORD &&
196 	    ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
197 		return -1;
198 	return 0;
199 }
200 
201 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
202 {
203 	struct ixgbe_hw *hw = &adapter->hw;
204 	u16 link_status = 0;
205 	int err;
206 
207 	hw->bus.type = ixgbe_bus_type_pci_express;
208 
209 	/* Get the negotiated link width and speed from PCI config space of the
210 	 * parent, as this device is behind a switch
211 	 */
212 	err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
213 
214 	/* assume caller will handle error case */
215 	if (err)
216 		return err;
217 
218 	hw->bus.width = ixgbe_convert_bus_width(link_status);
219 	hw->bus.speed = ixgbe_convert_bus_speed(link_status);
220 
221 	return 0;
222 }
223 
224 /**
225  * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
226  * @hw: hw specific details
227  *
228  * This function is used by probe to determine whether a device's PCI-Express
229  * bandwidth details should be gathered from the parent bus instead of from the
230  * device. Used to ensure that various locations all have the correct device ID
231  * checks.
232  */
233 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
234 {
235 	switch (hw->device_id) {
236 	case IXGBE_DEV_ID_82599_SFP_SF_QP:
237 	case IXGBE_DEV_ID_82599_QSFP_SF_QP:
238 		return true;
239 	default:
240 		return false;
241 	}
242 }
243 
244 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
245 				     int expected_gts)
246 {
247 	struct ixgbe_hw *hw = &adapter->hw;
248 	struct pci_dev *pdev;
249 
250 	/* Some devices are not connected over PCIe and thus do not negotiate
251 	 * speed. These devices do not have valid bus info, and thus any report
252 	 * we generate may not be correct.
253 	 */
254 	if (hw->bus.type == ixgbe_bus_type_internal)
255 		return;
256 
257 	/* determine whether to use the parent device */
258 	if (ixgbe_pcie_from_parent(&adapter->hw))
259 		pdev = adapter->pdev->bus->parent->self;
260 	else
261 		pdev = adapter->pdev;
262 
263 	pcie_print_link_status(pdev);
264 }
265 
266 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
267 {
268 	if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
269 	    !test_bit(__IXGBE_REMOVING, &adapter->state) &&
270 	    !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
271 		queue_work(ixgbe_wq, &adapter->service_task);
272 }
273 
274 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
275 {
276 	struct ixgbe_adapter *adapter = hw->back;
277 
278 	if (!hw->hw_addr)
279 		return;
280 	hw->hw_addr = NULL;
281 	e_dev_err("Adapter removed\n");
282 	if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
283 		ixgbe_service_event_schedule(adapter);
284 }
285 
286 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
287 {
288 	u8 __iomem *reg_addr;
289 	u32 value;
290 	int i;
291 
292 	reg_addr = READ_ONCE(hw->hw_addr);
293 	if (ixgbe_removed(reg_addr))
294 		return IXGBE_FAILED_READ_REG;
295 
296 	/* Register read of 0xFFFFFFF can indicate the adapter has been removed,
297 	 * so perform several status register reads to determine if the adapter
298 	 * has been removed.
299 	 */
300 	for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
301 		value = readl(reg_addr + IXGBE_STATUS);
302 		if (value != IXGBE_FAILED_READ_REG)
303 			break;
304 		mdelay(3);
305 	}
306 
307 	if (value == IXGBE_FAILED_READ_REG)
308 		ixgbe_remove_adapter(hw);
309 	else
310 		value = readl(reg_addr + reg);
311 	return value;
312 }
313 
314 /**
315  * ixgbe_read_reg - Read from device register
316  * @hw: hw specific details
317  * @reg: offset of register to read
318  *
319  * Returns : value read or IXGBE_FAILED_READ_REG if removed
320  *
321  * This function is used to read device registers. It checks for device
322  * removal by confirming any read that returns all ones by checking the
323  * status register value for all ones. This function avoids reading from
324  * the hardware if a removal was previously detected in which case it
325  * returns IXGBE_FAILED_READ_REG (all ones).
326  */
327 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
328 {
329 	u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
330 	u32 value;
331 
332 	if (ixgbe_removed(reg_addr))
333 		return IXGBE_FAILED_READ_REG;
334 	if (unlikely(hw->phy.nw_mng_if_sel &
335 		     IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
336 		struct ixgbe_adapter *adapter;
337 		int i;
338 
339 		for (i = 0; i < 200; ++i) {
340 			value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
341 			if (likely(!value))
342 				goto writes_completed;
343 			if (value == IXGBE_FAILED_READ_REG) {
344 				ixgbe_remove_adapter(hw);
345 				return IXGBE_FAILED_READ_REG;
346 			}
347 			udelay(5);
348 		}
349 
350 		adapter = hw->back;
351 		e_warn(hw, "register writes incomplete %08x\n", value);
352 	}
353 
354 writes_completed:
355 	value = readl(reg_addr + reg);
356 	if (unlikely(value == IXGBE_FAILED_READ_REG))
357 		value = ixgbe_check_remove(hw, reg);
358 	return value;
359 }
360 
361 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
362 {
363 	u16 value;
364 
365 	pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
366 	if (value == IXGBE_FAILED_READ_CFG_WORD) {
367 		ixgbe_remove_adapter(hw);
368 		return true;
369 	}
370 	return false;
371 }
372 
373 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
374 {
375 	struct ixgbe_adapter *adapter = hw->back;
376 	u16 value;
377 
378 	if (ixgbe_removed(hw->hw_addr))
379 		return IXGBE_FAILED_READ_CFG_WORD;
380 	pci_read_config_word(adapter->pdev, reg, &value);
381 	if (value == IXGBE_FAILED_READ_CFG_WORD &&
382 	    ixgbe_check_cfg_remove(hw, adapter->pdev))
383 		return IXGBE_FAILED_READ_CFG_WORD;
384 	return value;
385 }
386 
387 #ifdef CONFIG_PCI_IOV
388 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
389 {
390 	struct ixgbe_adapter *adapter = hw->back;
391 	u32 value;
392 
393 	if (ixgbe_removed(hw->hw_addr))
394 		return IXGBE_FAILED_READ_CFG_DWORD;
395 	pci_read_config_dword(adapter->pdev, reg, &value);
396 	if (value == IXGBE_FAILED_READ_CFG_DWORD &&
397 	    ixgbe_check_cfg_remove(hw, adapter->pdev))
398 		return IXGBE_FAILED_READ_CFG_DWORD;
399 	return value;
400 }
401 #endif /* CONFIG_PCI_IOV */
402 
403 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
404 {
405 	struct ixgbe_adapter *adapter = hw->back;
406 
407 	if (ixgbe_removed(hw->hw_addr))
408 		return;
409 	pci_write_config_word(adapter->pdev, reg, value);
410 }
411 
412 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
413 {
414 	BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
415 
416 	/* flush memory to make sure state is correct before next watchdog */
417 	smp_mb__before_atomic();
418 	clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
419 }
420 
421 struct ixgbe_reg_info {
422 	u32 ofs;
423 	char *name;
424 };
425 
426 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
427 
428 	/* General Registers */
429 	{IXGBE_CTRL, "CTRL"},
430 	{IXGBE_STATUS, "STATUS"},
431 	{IXGBE_CTRL_EXT, "CTRL_EXT"},
432 
433 	/* Interrupt Registers */
434 	{IXGBE_EICR, "EICR"},
435 
436 	/* RX Registers */
437 	{IXGBE_SRRCTL(0), "SRRCTL"},
438 	{IXGBE_DCA_RXCTRL(0), "DRXCTL"},
439 	{IXGBE_RDLEN(0), "RDLEN"},
440 	{IXGBE_RDH(0), "RDH"},
441 	{IXGBE_RDT(0), "RDT"},
442 	{IXGBE_RXDCTL(0), "RXDCTL"},
443 	{IXGBE_RDBAL(0), "RDBAL"},
444 	{IXGBE_RDBAH(0), "RDBAH"},
445 
446 	/* TX Registers */
447 	{IXGBE_TDBAL(0), "TDBAL"},
448 	{IXGBE_TDBAH(0), "TDBAH"},
449 	{IXGBE_TDLEN(0), "TDLEN"},
450 	{IXGBE_TDH(0), "TDH"},
451 	{IXGBE_TDT(0), "TDT"},
452 	{IXGBE_TXDCTL(0), "TXDCTL"},
453 
454 	/* List Terminator */
455 	{ .name = NULL }
456 };
457 
458 
459 /*
460  * ixgbe_regdump - register printout routine
461  */
462 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
463 {
464 	int i;
465 	char rname[16];
466 	u32 regs[64];
467 
468 	switch (reginfo->ofs) {
469 	case IXGBE_SRRCTL(0):
470 		for (i = 0; i < 64; i++)
471 			regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
472 		break;
473 	case IXGBE_DCA_RXCTRL(0):
474 		for (i = 0; i < 64; i++)
475 			regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
476 		break;
477 	case IXGBE_RDLEN(0):
478 		for (i = 0; i < 64; i++)
479 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
480 		break;
481 	case IXGBE_RDH(0):
482 		for (i = 0; i < 64; i++)
483 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
484 		break;
485 	case IXGBE_RDT(0):
486 		for (i = 0; i < 64; i++)
487 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
488 		break;
489 	case IXGBE_RXDCTL(0):
490 		for (i = 0; i < 64; i++)
491 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
492 		break;
493 	case IXGBE_RDBAL(0):
494 		for (i = 0; i < 64; i++)
495 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
496 		break;
497 	case IXGBE_RDBAH(0):
498 		for (i = 0; i < 64; i++)
499 			regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
500 		break;
501 	case IXGBE_TDBAL(0):
502 		for (i = 0; i < 64; i++)
503 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
504 		break;
505 	case IXGBE_TDBAH(0):
506 		for (i = 0; i < 64; i++)
507 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
508 		break;
509 	case IXGBE_TDLEN(0):
510 		for (i = 0; i < 64; i++)
511 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
512 		break;
513 	case IXGBE_TDH(0):
514 		for (i = 0; i < 64; i++)
515 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
516 		break;
517 	case IXGBE_TDT(0):
518 		for (i = 0; i < 64; i++)
519 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
520 		break;
521 	case IXGBE_TXDCTL(0):
522 		for (i = 0; i < 64; i++)
523 			regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
524 		break;
525 	default:
526 		pr_info("%-15s %08x\n",
527 			reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
528 		return;
529 	}
530 
531 	i = 0;
532 	while (i < 64) {
533 		int j;
534 		char buf[9 * 8 + 1];
535 		char *p = buf;
536 
537 		snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
538 		for (j = 0; j < 8; j++)
539 			p += sprintf(p, " %08x", regs[i++]);
540 		pr_err("%-15s%s\n", rname, buf);
541 	}
542 
543 }
544 
545 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
546 {
547 	struct ixgbe_tx_buffer *tx_buffer;
548 
549 	tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
550 	pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
551 		n, ring->next_to_use, ring->next_to_clean,
552 		(u64)dma_unmap_addr(tx_buffer, dma),
553 		dma_unmap_len(tx_buffer, len),
554 		tx_buffer->next_to_watch,
555 		(u64)tx_buffer->time_stamp);
556 }
557 
558 /*
559  * ixgbe_dump - Print registers, tx-rings and rx-rings
560  */
561 static void ixgbe_dump(struct ixgbe_adapter *adapter)
562 {
563 	struct net_device *netdev = adapter->netdev;
564 	struct ixgbe_hw *hw = &adapter->hw;
565 	struct ixgbe_reg_info *reginfo;
566 	int n = 0;
567 	struct ixgbe_ring *ring;
568 	struct ixgbe_tx_buffer *tx_buffer;
569 	union ixgbe_adv_tx_desc *tx_desc;
570 	struct my_u0 { u64 a; u64 b; } *u0;
571 	struct ixgbe_ring *rx_ring;
572 	union ixgbe_adv_rx_desc *rx_desc;
573 	struct ixgbe_rx_buffer *rx_buffer_info;
574 	int i = 0;
575 
576 	if (!netif_msg_hw(adapter))
577 		return;
578 
579 	/* Print netdevice Info */
580 	if (netdev) {
581 		dev_info(&adapter->pdev->dev, "Net device Info\n");
582 		pr_info("Device Name     state            "
583 			"trans_start\n");
584 		pr_info("%-15s %016lX %016lX\n",
585 			netdev->name,
586 			netdev->state,
587 			dev_trans_start(netdev));
588 	}
589 
590 	/* Print Registers */
591 	dev_info(&adapter->pdev->dev, "Register Dump\n");
592 	pr_info(" Register Name   Value\n");
593 	for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
594 	     reginfo->name; reginfo++) {
595 		ixgbe_regdump(hw, reginfo);
596 	}
597 
598 	/* Print TX Ring Summary */
599 	if (!netdev || !netif_running(netdev))
600 		return;
601 
602 	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
603 	pr_info(" %s     %s              %s        %s\n",
604 		"Queue [NTU] [NTC] [bi(ntc)->dma  ]",
605 		"leng", "ntw", "timestamp");
606 	for (n = 0; n < adapter->num_tx_queues; n++) {
607 		ring = adapter->tx_ring[n];
608 		ixgbe_print_buffer(ring, n);
609 	}
610 
611 	for (n = 0; n < adapter->num_xdp_queues; n++) {
612 		ring = adapter->xdp_ring[n];
613 		ixgbe_print_buffer(ring, n);
614 	}
615 
616 	/* Print TX Rings */
617 	if (!netif_msg_tx_done(adapter))
618 		goto rx_ring_summary;
619 
620 	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
621 
622 	/* Transmit Descriptor Formats
623 	 *
624 	 * 82598 Advanced Transmit Descriptor
625 	 *   +--------------------------------------------------------------+
626 	 * 0 |         Buffer Address [63:0]                                |
627 	 *   +--------------------------------------------------------------+
628 	 * 8 |  PAYLEN  | POPTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
629 	 *   +--------------------------------------------------------------+
630 	 *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
631 	 *
632 	 * 82598 Advanced Transmit Descriptor (Write-Back Format)
633 	 *   +--------------------------------------------------------------+
634 	 * 0 |                          RSV [63:0]                          |
635 	 *   +--------------------------------------------------------------+
636 	 * 8 |            RSV           |  STA  |          NXTSEQ           |
637 	 *   +--------------------------------------------------------------+
638 	 *   63                       36 35   32 31                         0
639 	 *
640 	 * 82599+ Advanced Transmit Descriptor
641 	 *   +--------------------------------------------------------------+
642 	 * 0 |         Buffer Address [63:0]                                |
643 	 *   +--------------------------------------------------------------+
644 	 * 8 |PAYLEN  |POPTS|CC|IDX  |STA  |DCMD  |DTYP |MAC  |RSV  |DTALEN |
645 	 *   +--------------------------------------------------------------+
646 	 *   63     46 45 40 39 38 36 35 32 31  24 23 20 19 18 17 16 15     0
647 	 *
648 	 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
649 	 *   +--------------------------------------------------------------+
650 	 * 0 |                          RSV [63:0]                          |
651 	 *   +--------------------------------------------------------------+
652 	 * 8 |            RSV           |  STA  |           RSV             |
653 	 *   +--------------------------------------------------------------+
654 	 *   63                       36 35   32 31                         0
655 	 */
656 
657 	for (n = 0; n < adapter->num_tx_queues; n++) {
658 		ring = adapter->tx_ring[n];
659 		pr_info("------------------------------------\n");
660 		pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
661 		pr_info("------------------------------------\n");
662 		pr_info("%s%s    %s              %s        %s          %s\n",
663 			"T [desc]     [address 63:0  ] ",
664 			"[PlPOIdStDDt Ln] [bi->dma       ] ",
665 			"leng", "ntw", "timestamp", "bi->skb");
666 
667 		for (i = 0; ring->desc && (i < ring->count); i++) {
668 			tx_desc = IXGBE_TX_DESC(ring, i);
669 			tx_buffer = &ring->tx_buffer_info[i];
670 			u0 = (struct my_u0 *)tx_desc;
671 			if (dma_unmap_len(tx_buffer, len) > 0) {
672 				const char *ring_desc;
673 
674 				if (i == ring->next_to_use &&
675 				    i == ring->next_to_clean)
676 					ring_desc = " NTC/U";
677 				else if (i == ring->next_to_use)
678 					ring_desc = " NTU";
679 				else if (i == ring->next_to_clean)
680 					ring_desc = " NTC";
681 				else
682 					ring_desc = "";
683 				pr_info("T [0x%03X]    %016llX %016llX %016llX %08X %p %016llX %p%s",
684 					i,
685 					le64_to_cpu((__force __le64)u0->a),
686 					le64_to_cpu((__force __le64)u0->b),
687 					(u64)dma_unmap_addr(tx_buffer, dma),
688 					dma_unmap_len(tx_buffer, len),
689 					tx_buffer->next_to_watch,
690 					(u64)tx_buffer->time_stamp,
691 					tx_buffer->skb,
692 					ring_desc);
693 
694 				if (netif_msg_pktdata(adapter) &&
695 				    tx_buffer->skb)
696 					print_hex_dump(KERN_INFO, "",
697 						DUMP_PREFIX_ADDRESS, 16, 1,
698 						tx_buffer->skb->data,
699 						dma_unmap_len(tx_buffer, len),
700 						true);
701 			}
702 		}
703 	}
704 
705 	/* Print RX Rings Summary */
706 rx_ring_summary:
707 	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
708 	pr_info("Queue [NTU] [NTC]\n");
709 	for (n = 0; n < adapter->num_rx_queues; n++) {
710 		rx_ring = adapter->rx_ring[n];
711 		pr_info("%5d %5X %5X\n",
712 			n, rx_ring->next_to_use, rx_ring->next_to_clean);
713 	}
714 
715 	/* Print RX Rings */
716 	if (!netif_msg_rx_status(adapter))
717 		return;
718 
719 	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720 
721 	/* Receive Descriptor Formats
722 	 *
723 	 * 82598 Advanced Receive Descriptor (Read) Format
724 	 *    63                                           1        0
725 	 *    +-----------------------------------------------------+
726 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
727 	 *    +----------------------------------------------+------+
728 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
729 	 *    +-----------------------------------------------------+
730 	 *
731 	 *
732 	 * 82598 Advanced Receive Descriptor (Write-Back) Format
733 	 *
734 	 *   63       48 47    32 31  30      21 20 16 15   4 3     0
735 	 *   +------------------------------------------------------+
736 	 * 0 |       RSS Hash /  |SPH| HDR_LEN  | RSV |Packet|  RSS |
737 	 *   | Packet   | IP     |   |          |     | Type | Type |
738 	 *   | Checksum | Ident  |   |          |     |      |      |
739 	 *   +------------------------------------------------------+
740 	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 	 *   +------------------------------------------------------+
742 	 *   63       48 47    32 31            20 19               0
743 	 *
744 	 * 82599+ Advanced Receive Descriptor (Read) Format
745 	 *    63                                           1        0
746 	 *    +-----------------------------------------------------+
747 	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
748 	 *    +----------------------------------------------+------+
749 	 *  8 |       Header Buffer Address [63:1]           |  DD  |
750 	 *    +-----------------------------------------------------+
751 	 *
752 	 *
753 	 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 	 *
755 	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
756 	 *   +------------------------------------------------------+
757 	 * 0 |RSS / Frag Checksum|SPH| HDR_LEN  |RSC- |Packet|  RSS |
758 	 *   |/ RTT / PCoE_PARAM |   |          | CNT | Type | Type |
759 	 *   |/ Flow Dir Flt ID  |   |          |     |      |      |
760 	 *   +------------------------------------------------------+
761 	 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 	 *   +------------------------------------------------------+
763 	 *   63       48 47    32 31          20 19                 0
764 	 */
765 
766 	for (n = 0; n < adapter->num_rx_queues; n++) {
767 		rx_ring = adapter->rx_ring[n];
768 		pr_info("------------------------------------\n");
769 		pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 		pr_info("------------------------------------\n");
771 		pr_info("%s%s%s\n",
772 			"R  [desc]      [ PktBuf     A0] ",
773 			"[  HeadBuf   DD] [bi->dma       ] [bi->skb       ] ",
774 			"<-- Adv Rx Read format");
775 		pr_info("%s%s%s\n",
776 			"RWB[desc]      [PcsmIpSHl PtRs] ",
777 			"[vl er S cks ln] ---------------- [bi->skb       ] ",
778 			"<-- Adv Rx Write-Back format");
779 
780 		for (i = 0; i < rx_ring->count; i++) {
781 			const char *ring_desc;
782 
783 			if (i == rx_ring->next_to_use)
784 				ring_desc = " NTU";
785 			else if (i == rx_ring->next_to_clean)
786 				ring_desc = " NTC";
787 			else
788 				ring_desc = "";
789 
790 			rx_buffer_info = &rx_ring->rx_buffer_info[i];
791 			rx_desc = IXGBE_RX_DESC(rx_ring, i);
792 			u0 = (struct my_u0 *)rx_desc;
793 			if (rx_desc->wb.upper.length) {
794 				/* Descriptor Done */
795 				pr_info("RWB[0x%03X]     %016llX %016llX ---------------- %p%s\n",
796 					i,
797 					le64_to_cpu((__force __le64)u0->a),
798 					le64_to_cpu((__force __le64)u0->b),
799 					rx_buffer_info->skb,
800 					ring_desc);
801 			} else {
802 				pr_info("R  [0x%03X]     %016llX %016llX %016llX %p%s\n",
803 					i,
804 					le64_to_cpu((__force __le64)u0->a),
805 					le64_to_cpu((__force __le64)u0->b),
806 					(u64)rx_buffer_info->dma,
807 					rx_buffer_info->skb,
808 					ring_desc);
809 
810 				if (netif_msg_pktdata(adapter) &&
811 				    rx_buffer_info->dma) {
812 					print_hex_dump(KERN_INFO, "",
813 					   DUMP_PREFIX_ADDRESS, 16, 1,
814 					   page_address(rx_buffer_info->page) +
815 						    rx_buffer_info->page_offset,
816 					   ixgbe_rx_bufsz(rx_ring), true);
817 				}
818 			}
819 		}
820 	}
821 }
822 
823 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
824 {
825 	u32 ctrl_ext;
826 
827 	/* Let firmware take over control of h/w */
828 	ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
829 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
830 			ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
831 }
832 
833 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
834 {
835 	u32 ctrl_ext;
836 
837 	/* Let firmware know the driver has taken over */
838 	ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
839 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
840 			ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
841 }
842 
843 /**
844  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
845  * @adapter: pointer to adapter struct
846  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
847  * @queue: queue to map the corresponding interrupt to
848  * @msix_vector: the vector to map to the corresponding queue
849  *
850  */
851 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
852 			   u8 queue, u8 msix_vector)
853 {
854 	u32 ivar, index;
855 	struct ixgbe_hw *hw = &adapter->hw;
856 	switch (hw->mac.type) {
857 	case ixgbe_mac_82598EB:
858 		msix_vector |= IXGBE_IVAR_ALLOC_VAL;
859 		if (direction == -1)
860 			direction = 0;
861 		index = (((direction * 64) + queue) >> 2) & 0x1F;
862 		ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
863 		ivar &= ~(0xFF << (8 * (queue & 0x3)));
864 		ivar |= (msix_vector << (8 * (queue & 0x3)));
865 		IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
866 		break;
867 	case ixgbe_mac_82599EB:
868 	case ixgbe_mac_X540:
869 	case ixgbe_mac_X550:
870 	case ixgbe_mac_X550EM_x:
871 	case ixgbe_mac_x550em_a:
872 		if (direction == -1) {
873 			/* other causes */
874 			msix_vector |= IXGBE_IVAR_ALLOC_VAL;
875 			index = ((queue & 1) * 8);
876 			ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
877 			ivar &= ~(0xFF << index);
878 			ivar |= (msix_vector << index);
879 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
880 			break;
881 		} else {
882 			/* tx or rx causes */
883 			msix_vector |= IXGBE_IVAR_ALLOC_VAL;
884 			index = ((16 * (queue & 1)) + (8 * direction));
885 			ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
886 			ivar &= ~(0xFF << index);
887 			ivar |= (msix_vector << index);
888 			IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
889 			break;
890 		}
891 	default:
892 		break;
893 	}
894 }
895 
896 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
897 					  u64 qmask)
898 {
899 	u32 mask;
900 
901 	switch (adapter->hw.mac.type) {
902 	case ixgbe_mac_82598EB:
903 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
904 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
905 		break;
906 	case ixgbe_mac_82599EB:
907 	case ixgbe_mac_X540:
908 	case ixgbe_mac_X550:
909 	case ixgbe_mac_X550EM_x:
910 	case ixgbe_mac_x550em_a:
911 		mask = (qmask & 0xFFFFFFFF);
912 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
913 		mask = (qmask >> 32);
914 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
915 		break;
916 	default:
917 		break;
918 	}
919 }
920 
921 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
922 {
923 	struct ixgbe_hw *hw = &adapter->hw;
924 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
925 	int i;
926 	u32 data;
927 
928 	if ((hw->fc.current_mode != ixgbe_fc_full) &&
929 	    (hw->fc.current_mode != ixgbe_fc_rx_pause))
930 		return;
931 
932 	switch (hw->mac.type) {
933 	case ixgbe_mac_82598EB:
934 		data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
935 		break;
936 	default:
937 		data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
938 	}
939 	hwstats->lxoffrxc += data;
940 
941 	/* refill credits (no tx hang) if we received xoff */
942 	if (!data)
943 		return;
944 
945 	for (i = 0; i < adapter->num_tx_queues; i++)
946 		clear_bit(__IXGBE_HANG_CHECK_ARMED,
947 			  &adapter->tx_ring[i]->state);
948 
949 	for (i = 0; i < adapter->num_xdp_queues; i++)
950 		clear_bit(__IXGBE_HANG_CHECK_ARMED,
951 			  &adapter->xdp_ring[i]->state);
952 }
953 
954 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
955 {
956 	struct ixgbe_hw *hw = &adapter->hw;
957 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
958 	u32 xoff[8] = {0};
959 	u8 tc;
960 	int i;
961 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
962 
963 	if (adapter->ixgbe_ieee_pfc)
964 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
965 
966 	if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
967 		ixgbe_update_xoff_rx_lfc(adapter);
968 		return;
969 	}
970 
971 	/* update stats for each tc, only valid with PFC enabled */
972 	for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
973 		u32 pxoffrxc;
974 
975 		switch (hw->mac.type) {
976 		case ixgbe_mac_82598EB:
977 			pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
978 			break;
979 		default:
980 			pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
981 		}
982 		hwstats->pxoffrxc[i] += pxoffrxc;
983 		/* Get the TC for given UP */
984 		tc = netdev_get_prio_tc_map(adapter->netdev, i);
985 		xoff[tc] += pxoffrxc;
986 	}
987 
988 	/* disarm tx queues that have received xoff frames */
989 	for (i = 0; i < adapter->num_tx_queues; i++) {
990 		struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
991 
992 		tc = tx_ring->dcb_tc;
993 		if (xoff[tc])
994 			clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
995 	}
996 
997 	for (i = 0; i < adapter->num_xdp_queues; i++) {
998 		struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
999 
1000 		tc = xdp_ring->dcb_tc;
1001 		if (xoff[tc])
1002 			clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1003 	}
1004 }
1005 
1006 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1007 {
1008 	return ring->stats.packets;
1009 }
1010 
1011 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1012 {
1013 	unsigned int head, tail;
1014 
1015 	head = ring->next_to_clean;
1016 	tail = ring->next_to_use;
1017 
1018 	return ((head <= tail) ? tail : tail + ring->count) - head;
1019 }
1020 
1021 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1022 {
1023 	u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1024 	u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1025 	u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1026 
1027 	clear_check_for_tx_hang(tx_ring);
1028 
1029 	/*
1030 	 * Check for a hung queue, but be thorough. This verifies
1031 	 * that a transmit has been completed since the previous
1032 	 * check AND there is at least one packet pending. The
1033 	 * ARMED bit is set to indicate a potential hang. The
1034 	 * bit is cleared if a pause frame is received to remove
1035 	 * false hang detection due to PFC or 802.3x frames. By
1036 	 * requiring this to fail twice we avoid races with
1037 	 * pfc clearing the ARMED bit and conditions where we
1038 	 * run the check_tx_hang logic with a transmit completion
1039 	 * pending but without time to complete it yet.
1040 	 */
1041 	if (tx_done_old == tx_done && tx_pending)
1042 		/* make sure it is true for two checks in a row */
1043 		return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1044 					&tx_ring->state);
1045 	/* update completed stats and continue */
1046 	tx_ring->tx_stats.tx_done_old = tx_done;
1047 	/* reset the countdown */
1048 	clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1049 
1050 	return false;
1051 }
1052 
1053 /**
1054  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1055  * @adapter: driver private struct
1056  **/
1057 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1058 {
1059 
1060 	/* Do the reset outside of interrupt context */
1061 	if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1062 		set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
1063 		e_warn(drv, "initiating reset due to tx timeout\n");
1064 		ixgbe_service_event_schedule(adapter);
1065 	}
1066 }
1067 
1068 /**
1069  * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1070  * @netdev: network interface device structure
1071  * @queue_index: Tx queue to set
1072  * @maxrate: desired maximum transmit bitrate
1073  **/
1074 static int ixgbe_tx_maxrate(struct net_device *netdev,
1075 			    int queue_index, u32 maxrate)
1076 {
1077 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1078 	struct ixgbe_hw *hw = &adapter->hw;
1079 	u32 bcnrc_val = ixgbe_link_mbps(adapter);
1080 
1081 	if (!maxrate)
1082 		return 0;
1083 
1084 	/* Calculate the rate factor values to set */
1085 	bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1086 	bcnrc_val /= maxrate;
1087 
1088 	/* clear everything but the rate factor */
1089 	bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1090 	IXGBE_RTTBCNRC_RF_DEC_MASK;
1091 
1092 	/* enable the rate scheduler */
1093 	bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1094 
1095 	IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1096 	IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1097 
1098 	return 0;
1099 }
1100 
1101 /**
1102  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1103  * @q_vector: structure containing interrupt and ring information
1104  * @tx_ring: tx ring to clean
1105  * @napi_budget: Used to determine if we are in netpoll
1106  **/
1107 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1108 			       struct ixgbe_ring *tx_ring, int napi_budget)
1109 {
1110 	struct ixgbe_adapter *adapter = q_vector->adapter;
1111 	struct ixgbe_tx_buffer *tx_buffer;
1112 	union ixgbe_adv_tx_desc *tx_desc;
1113 	unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
1114 	unsigned int budget = q_vector->tx.work_limit;
1115 	unsigned int i = tx_ring->next_to_clean;
1116 
1117 	if (test_bit(__IXGBE_DOWN, &adapter->state))
1118 		return true;
1119 
1120 	tx_buffer = &tx_ring->tx_buffer_info[i];
1121 	tx_desc = IXGBE_TX_DESC(tx_ring, i);
1122 	i -= tx_ring->count;
1123 
1124 	do {
1125 		union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1126 
1127 		/* if next_to_watch is not set then there is no work pending */
1128 		if (!eop_desc)
1129 			break;
1130 
1131 		/* prevent any other reads prior to eop_desc */
1132 		smp_rmb();
1133 
1134 		/* if DD is not set pending work has not been completed */
1135 		if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1136 			break;
1137 
1138 		/* clear next_to_watch to prevent false hangs */
1139 		tx_buffer->next_to_watch = NULL;
1140 
1141 		/* update the statistics for this packet */
1142 		total_bytes += tx_buffer->bytecount;
1143 		total_packets += tx_buffer->gso_segs;
1144 		if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1145 			total_ipsec++;
1146 
1147 		/* free the skb */
1148 		if (ring_is_xdp(tx_ring))
1149 			xdp_return_frame(tx_buffer->xdpf);
1150 		else
1151 			napi_consume_skb(tx_buffer->skb, napi_budget);
1152 
1153 		/* unmap skb header data */
1154 		dma_unmap_single(tx_ring->dev,
1155 				 dma_unmap_addr(tx_buffer, dma),
1156 				 dma_unmap_len(tx_buffer, len),
1157 				 DMA_TO_DEVICE);
1158 
1159 		/* clear tx_buffer data */
1160 		dma_unmap_len_set(tx_buffer, len, 0);
1161 
1162 		/* unmap remaining buffers */
1163 		while (tx_desc != eop_desc) {
1164 			tx_buffer++;
1165 			tx_desc++;
1166 			i++;
1167 			if (unlikely(!i)) {
1168 				i -= tx_ring->count;
1169 				tx_buffer = tx_ring->tx_buffer_info;
1170 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 			}
1172 
1173 			/* unmap any remaining paged data */
1174 			if (dma_unmap_len(tx_buffer, len)) {
1175 				dma_unmap_page(tx_ring->dev,
1176 					       dma_unmap_addr(tx_buffer, dma),
1177 					       dma_unmap_len(tx_buffer, len),
1178 					       DMA_TO_DEVICE);
1179 				dma_unmap_len_set(tx_buffer, len, 0);
1180 			}
1181 		}
1182 
1183 		/* move us one more past the eop_desc for start of next pkt */
1184 		tx_buffer++;
1185 		tx_desc++;
1186 		i++;
1187 		if (unlikely(!i)) {
1188 			i -= tx_ring->count;
1189 			tx_buffer = tx_ring->tx_buffer_info;
1190 			tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1191 		}
1192 
1193 		/* issue prefetch for next Tx descriptor */
1194 		prefetch(tx_desc);
1195 
1196 		/* update budget accounting */
1197 		budget--;
1198 	} while (likely(budget));
1199 
1200 	i += tx_ring->count;
1201 	tx_ring->next_to_clean = i;
1202 	u64_stats_update_begin(&tx_ring->syncp);
1203 	tx_ring->stats.bytes += total_bytes;
1204 	tx_ring->stats.packets += total_packets;
1205 	u64_stats_update_end(&tx_ring->syncp);
1206 	q_vector->tx.total_bytes += total_bytes;
1207 	q_vector->tx.total_packets += total_packets;
1208 	adapter->tx_ipsec += total_ipsec;
1209 
1210 	if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1211 		/* schedule immediate reset if we believe we hung */
1212 		struct ixgbe_hw *hw = &adapter->hw;
1213 		e_err(drv, "Detected Tx Unit Hang %s\n"
1214 			"  Tx Queue             <%d>\n"
1215 			"  TDH, TDT             <%x>, <%x>\n"
1216 			"  next_to_use          <%x>\n"
1217 			"  next_to_clean        <%x>\n"
1218 			"tx_buffer_info[next_to_clean]\n"
1219 			"  time_stamp           <%lx>\n"
1220 			"  jiffies              <%lx>\n",
1221 			ring_is_xdp(tx_ring) ? "(XDP)" : "",
1222 			tx_ring->queue_index,
1223 			IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1224 			IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1225 			tx_ring->next_to_use, i,
1226 			tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1227 
1228 		if (!ring_is_xdp(tx_ring))
1229 			netif_stop_subqueue(tx_ring->netdev,
1230 					    tx_ring->queue_index);
1231 
1232 		e_info(probe,
1233 		       "tx hang %d detected on queue %d, resetting adapter\n",
1234 			adapter->tx_timeout_count + 1, tx_ring->queue_index);
1235 
1236 		/* schedule immediate reset if we believe we hung */
1237 		ixgbe_tx_timeout_reset(adapter);
1238 
1239 		/* the adapter is about to reset, no point in enabling stuff */
1240 		return true;
1241 	}
1242 
1243 	if (ring_is_xdp(tx_ring))
1244 		return !!budget;
1245 
1246 	netdev_tx_completed_queue(txring_txq(tx_ring),
1247 				  total_packets, total_bytes);
1248 
1249 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1250 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1251 		     (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1252 		/* Make sure that anybody stopping the queue after this
1253 		 * sees the new next_to_clean.
1254 		 */
1255 		smp_mb();
1256 		if (__netif_subqueue_stopped(tx_ring->netdev,
1257 					     tx_ring->queue_index)
1258 		    && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1259 			netif_wake_subqueue(tx_ring->netdev,
1260 					    tx_ring->queue_index);
1261 			++tx_ring->tx_stats.restart_queue;
1262 		}
1263 	}
1264 
1265 	return !!budget;
1266 }
1267 
1268 #ifdef CONFIG_IXGBE_DCA
1269 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1270 				struct ixgbe_ring *tx_ring,
1271 				int cpu)
1272 {
1273 	struct ixgbe_hw *hw = &adapter->hw;
1274 	u32 txctrl = 0;
1275 	u16 reg_offset;
1276 
1277 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1278 		txctrl = dca3_get_tag(tx_ring->dev, cpu);
1279 
1280 	switch (hw->mac.type) {
1281 	case ixgbe_mac_82598EB:
1282 		reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1283 		break;
1284 	case ixgbe_mac_82599EB:
1285 	case ixgbe_mac_X540:
1286 		reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1287 		txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1288 		break;
1289 	default:
1290 		/* for unknown hardware do not write register */
1291 		return;
1292 	}
1293 
1294 	/*
1295 	 * We can enable relaxed ordering for reads, but not writes when
1296 	 * DCA is enabled.  This is due to a known issue in some chipsets
1297 	 * which will cause the DCA tag to be cleared.
1298 	 */
1299 	txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1300 		  IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1301 		  IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1302 
1303 	IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1304 }
1305 
1306 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1307 				struct ixgbe_ring *rx_ring,
1308 				int cpu)
1309 {
1310 	struct ixgbe_hw *hw = &adapter->hw;
1311 	u32 rxctrl = 0;
1312 	u8 reg_idx = rx_ring->reg_idx;
1313 
1314 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1315 		rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1316 
1317 	switch (hw->mac.type) {
1318 	case ixgbe_mac_82599EB:
1319 	case ixgbe_mac_X540:
1320 		rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1321 		break;
1322 	default:
1323 		break;
1324 	}
1325 
1326 	/*
1327 	 * We can enable relaxed ordering for reads, but not writes when
1328 	 * DCA is enabled.  This is due to a known issue in some chipsets
1329 	 * which will cause the DCA tag to be cleared.
1330 	 */
1331 	rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1332 		  IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1333 		  IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1334 
1335 	IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1336 }
1337 
1338 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1339 {
1340 	struct ixgbe_adapter *adapter = q_vector->adapter;
1341 	struct ixgbe_ring *ring;
1342 	int cpu = get_cpu();
1343 
1344 	if (q_vector->cpu == cpu)
1345 		goto out_no_update;
1346 
1347 	ixgbe_for_each_ring(ring, q_vector->tx)
1348 		ixgbe_update_tx_dca(adapter, ring, cpu);
1349 
1350 	ixgbe_for_each_ring(ring, q_vector->rx)
1351 		ixgbe_update_rx_dca(adapter, ring, cpu);
1352 
1353 	q_vector->cpu = cpu;
1354 out_no_update:
1355 	put_cpu();
1356 }
1357 
1358 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1359 {
1360 	int i;
1361 
1362 	/* always use CB2 mode, difference is masked in the CB driver */
1363 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1364 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1365 				IXGBE_DCA_CTRL_DCA_MODE_CB2);
1366 	else
1367 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 				IXGBE_DCA_CTRL_DCA_DISABLE);
1369 
1370 	for (i = 0; i < adapter->num_q_vectors; i++) {
1371 		adapter->q_vector[i]->cpu = -1;
1372 		ixgbe_update_dca(adapter->q_vector[i]);
1373 	}
1374 }
1375 
1376 static int __ixgbe_notify_dca(struct device *dev, void *data)
1377 {
1378 	struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1379 	unsigned long event = *(unsigned long *)data;
1380 
1381 	if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1382 		return 0;
1383 
1384 	switch (event) {
1385 	case DCA_PROVIDER_ADD:
1386 		/* if we're already enabled, don't do it again */
1387 		if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1388 			break;
1389 		if (dca_add_requester(dev) == 0) {
1390 			adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1391 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1392 					IXGBE_DCA_CTRL_DCA_MODE_CB2);
1393 			break;
1394 		}
1395 		/* fall through - DCA is disabled. */
1396 	case DCA_PROVIDER_REMOVE:
1397 		if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1398 			dca_remove_requester(dev);
1399 			adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1400 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1401 					IXGBE_DCA_CTRL_DCA_DISABLE);
1402 		}
1403 		break;
1404 	}
1405 
1406 	return 0;
1407 }
1408 
1409 #endif /* CONFIG_IXGBE_DCA */
1410 
1411 #define IXGBE_RSS_L4_TYPES_MASK \
1412 	((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1413 	 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1414 	 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1415 	 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1416 
1417 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1418 				 union ixgbe_adv_rx_desc *rx_desc,
1419 				 struct sk_buff *skb)
1420 {
1421 	u16 rss_type;
1422 
1423 	if (!(ring->netdev->features & NETIF_F_RXHASH))
1424 		return;
1425 
1426 	rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1427 		   IXGBE_RXDADV_RSSTYPE_MASK;
1428 
1429 	if (!rss_type)
1430 		return;
1431 
1432 	skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1433 		     (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1434 		     PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1435 }
1436 
1437 #ifdef IXGBE_FCOE
1438 /**
1439  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1440  * @ring: structure containing ring specific data
1441  * @rx_desc: advanced rx descriptor
1442  *
1443  * Returns : true if it is FCoE pkt
1444  */
1445 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1446 				    union ixgbe_adv_rx_desc *rx_desc)
1447 {
1448 	__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1449 
1450 	return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1451 	       ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1452 		(cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1453 			     IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1454 }
1455 
1456 #endif /* IXGBE_FCOE */
1457 /**
1458  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1459  * @ring: structure containing ring specific data
1460  * @rx_desc: current Rx descriptor being processed
1461  * @skb: skb currently being received and modified
1462  **/
1463 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1464 				     union ixgbe_adv_rx_desc *rx_desc,
1465 				     struct sk_buff *skb)
1466 {
1467 	__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1468 	bool encap_pkt = false;
1469 
1470 	skb_checksum_none_assert(skb);
1471 
1472 	/* Rx csum disabled */
1473 	if (!(ring->netdev->features & NETIF_F_RXCSUM))
1474 		return;
1475 
1476 	/* check for VXLAN and Geneve packets */
1477 	if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
1478 		encap_pkt = true;
1479 		skb->encapsulation = 1;
1480 	}
1481 
1482 	/* if IP and error */
1483 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1484 	    ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1485 		ring->rx_stats.csum_err++;
1486 		return;
1487 	}
1488 
1489 	if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1490 		return;
1491 
1492 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1493 		/*
1494 		 * 82599 errata, UDP frames with a 0 checksum can be marked as
1495 		 * checksum errors.
1496 		 */
1497 		if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1498 		    test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1499 			return;
1500 
1501 		ring->rx_stats.csum_err++;
1502 		return;
1503 	}
1504 
1505 	/* It must be a TCP or UDP packet with a valid checksum */
1506 	skb->ip_summed = CHECKSUM_UNNECESSARY;
1507 	if (encap_pkt) {
1508 		if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1509 			return;
1510 
1511 		if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1512 			skb->ip_summed = CHECKSUM_NONE;
1513 			return;
1514 		}
1515 		/* If we checked the outer header let the stack know */
1516 		skb->csum_level = 1;
1517 	}
1518 }
1519 
1520 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1521 {
1522 	return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1523 }
1524 
1525 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1526 				    struct ixgbe_rx_buffer *bi)
1527 {
1528 	struct page *page = bi->page;
1529 	dma_addr_t dma;
1530 
1531 	/* since we are recycling buffers we should seldom need to alloc */
1532 	if (likely(page))
1533 		return true;
1534 
1535 	/* alloc new page for storage */
1536 	page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1537 	if (unlikely(!page)) {
1538 		rx_ring->rx_stats.alloc_rx_page_failed++;
1539 		return false;
1540 	}
1541 
1542 	/* map page for use */
1543 	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1544 				 ixgbe_rx_pg_size(rx_ring),
1545 				 DMA_FROM_DEVICE,
1546 				 IXGBE_RX_DMA_ATTR);
1547 
1548 	/*
1549 	 * if mapping failed free memory back to system since
1550 	 * there isn't much point in holding memory we can't use
1551 	 */
1552 	if (dma_mapping_error(rx_ring->dev, dma)) {
1553 		__free_pages(page, ixgbe_rx_pg_order(rx_ring));
1554 
1555 		rx_ring->rx_stats.alloc_rx_page_failed++;
1556 		return false;
1557 	}
1558 
1559 	bi->dma = dma;
1560 	bi->page = page;
1561 	bi->page_offset = ixgbe_rx_offset(rx_ring);
1562 	page_ref_add(page, USHRT_MAX - 1);
1563 	bi->pagecnt_bias = USHRT_MAX;
1564 	rx_ring->rx_stats.alloc_rx_page++;
1565 
1566 	return true;
1567 }
1568 
1569 /**
1570  * ixgbe_alloc_rx_buffers - Replace used receive buffers
1571  * @rx_ring: ring to place buffers on
1572  * @cleaned_count: number of buffers to replace
1573  **/
1574 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1575 {
1576 	union ixgbe_adv_rx_desc *rx_desc;
1577 	struct ixgbe_rx_buffer *bi;
1578 	u16 i = rx_ring->next_to_use;
1579 	u16 bufsz;
1580 
1581 	/* nothing to do */
1582 	if (!cleaned_count)
1583 		return;
1584 
1585 	rx_desc = IXGBE_RX_DESC(rx_ring, i);
1586 	bi = &rx_ring->rx_buffer_info[i];
1587 	i -= rx_ring->count;
1588 
1589 	bufsz = ixgbe_rx_bufsz(rx_ring);
1590 
1591 	do {
1592 		if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1593 			break;
1594 
1595 		/* sync the buffer for use by the device */
1596 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1597 						 bi->page_offset, bufsz,
1598 						 DMA_FROM_DEVICE);
1599 
1600 		/*
1601 		 * Refresh the desc even if buffer_addrs didn't change
1602 		 * because each write-back erases this info.
1603 		 */
1604 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1605 
1606 		rx_desc++;
1607 		bi++;
1608 		i++;
1609 		if (unlikely(!i)) {
1610 			rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1611 			bi = rx_ring->rx_buffer_info;
1612 			i -= rx_ring->count;
1613 		}
1614 
1615 		/* clear the length for the next_to_use descriptor */
1616 		rx_desc->wb.upper.length = 0;
1617 
1618 		cleaned_count--;
1619 	} while (cleaned_count);
1620 
1621 	i += rx_ring->count;
1622 
1623 	if (rx_ring->next_to_use != i) {
1624 		rx_ring->next_to_use = i;
1625 
1626 		/* update next to alloc since we have filled the ring */
1627 		rx_ring->next_to_alloc = i;
1628 
1629 		/* Force memory writes to complete before letting h/w
1630 		 * know there are new descriptors to fetch.  (Only
1631 		 * applicable for weak-ordered memory model archs,
1632 		 * such as IA-64).
1633 		 */
1634 		wmb();
1635 		writel(i, rx_ring->tail);
1636 	}
1637 }
1638 
1639 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1640 				   struct sk_buff *skb)
1641 {
1642 	u16 hdr_len = skb_headlen(skb);
1643 
1644 	/* set gso_size to avoid messing up TCP MSS */
1645 	skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1646 						 IXGBE_CB(skb)->append_cnt);
1647 	skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1648 }
1649 
1650 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1651 				   struct sk_buff *skb)
1652 {
1653 	/* if append_cnt is 0 then frame is not RSC */
1654 	if (!IXGBE_CB(skb)->append_cnt)
1655 		return;
1656 
1657 	rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1658 	rx_ring->rx_stats.rsc_flush++;
1659 
1660 	ixgbe_set_rsc_gso_size(rx_ring, skb);
1661 
1662 	/* gso_size is computed using append_cnt so always clear it last */
1663 	IXGBE_CB(skb)->append_cnt = 0;
1664 }
1665 
1666 /**
1667  * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1668  * @rx_ring: rx descriptor ring packet is being transacted on
1669  * @rx_desc: pointer to the EOP Rx descriptor
1670  * @skb: pointer to current skb being populated
1671  *
1672  * This function checks the ring, descriptor, and packet information in
1673  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1674  * other fields within the skb.
1675  **/
1676 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1677 				     union ixgbe_adv_rx_desc *rx_desc,
1678 				     struct sk_buff *skb)
1679 {
1680 	struct net_device *dev = rx_ring->netdev;
1681 	u32 flags = rx_ring->q_vector->adapter->flags;
1682 
1683 	ixgbe_update_rsc_stats(rx_ring, skb);
1684 
1685 	ixgbe_rx_hash(rx_ring, rx_desc, skb);
1686 
1687 	ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1688 
1689 	if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1690 		ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1691 
1692 	if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1693 	    ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1694 		u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1695 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1696 	}
1697 
1698 	if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1699 		ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1700 
1701 	/* record Rx queue, or update MACVLAN statistics */
1702 	if (netif_is_ixgbe(dev))
1703 		skb_record_rx_queue(skb, rx_ring->queue_index);
1704 	else
1705 		macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
1706 				 false);
1707 
1708 	skb->protocol = eth_type_trans(skb, dev);
1709 }
1710 
1711 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1712 			 struct sk_buff *skb)
1713 {
1714 	napi_gro_receive(&q_vector->napi, skb);
1715 }
1716 
1717 /**
1718  * ixgbe_is_non_eop - process handling of non-EOP buffers
1719  * @rx_ring: Rx ring being processed
1720  * @rx_desc: Rx descriptor for current buffer
1721  * @skb: Current socket buffer containing buffer in progress
1722  *
1723  * This function updates next to clean.  If the buffer is an EOP buffer
1724  * this function exits returning false, otherwise it will place the
1725  * sk_buff in the next buffer to be chained and return true indicating
1726  * that this is in fact a non-EOP buffer.
1727  **/
1728 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1729 			     union ixgbe_adv_rx_desc *rx_desc,
1730 			     struct sk_buff *skb)
1731 {
1732 	u32 ntc = rx_ring->next_to_clean + 1;
1733 
1734 	/* fetch, update, and store next to clean */
1735 	ntc = (ntc < rx_ring->count) ? ntc : 0;
1736 	rx_ring->next_to_clean = ntc;
1737 
1738 	prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1739 
1740 	/* update RSC append count if present */
1741 	if (ring_is_rsc_enabled(rx_ring)) {
1742 		__le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1743 				     cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1744 
1745 		if (unlikely(rsc_enabled)) {
1746 			u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1747 
1748 			rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1749 			IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1750 
1751 			/* update ntc based on RSC value */
1752 			ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1753 			ntc &= IXGBE_RXDADV_NEXTP_MASK;
1754 			ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1755 		}
1756 	}
1757 
1758 	/* if we are the last buffer then there is nothing else to do */
1759 	if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1760 		return false;
1761 
1762 	/* place skb in next buffer to be received */
1763 	rx_ring->rx_buffer_info[ntc].skb = skb;
1764 	rx_ring->rx_stats.non_eop_descs++;
1765 
1766 	return true;
1767 }
1768 
1769 /**
1770  * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1771  * @rx_ring: rx descriptor ring packet is being transacted on
1772  * @skb: pointer to current skb being adjusted
1773  *
1774  * This function is an ixgbe specific version of __pskb_pull_tail.  The
1775  * main difference between this version and the original function is that
1776  * this function can make several assumptions about the state of things
1777  * that allow for significant optimizations versus the standard function.
1778  * As a result we can do things like drop a frag and maintain an accurate
1779  * truesize for the skb.
1780  */
1781 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1782 			    struct sk_buff *skb)
1783 {
1784 	struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1785 	unsigned char *va;
1786 	unsigned int pull_len;
1787 
1788 	/*
1789 	 * it is valid to use page_address instead of kmap since we are
1790 	 * working with pages allocated out of the lomem pool per
1791 	 * alloc_page(GFP_ATOMIC)
1792 	 */
1793 	va = skb_frag_address(frag);
1794 
1795 	/*
1796 	 * we need the header to contain the greater of either ETH_HLEN or
1797 	 * 60 bytes if the skb->len is less than 60 for skb_pad.
1798 	 */
1799 	pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1800 
1801 	/* align pull length to size of long to optimize memcpy performance */
1802 	skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1803 
1804 	/* update all of the pointers */
1805 	skb_frag_size_sub(frag, pull_len);
1806 	frag->page_offset += pull_len;
1807 	skb->data_len -= pull_len;
1808 	skb->tail += pull_len;
1809 }
1810 
1811 /**
1812  * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1813  * @rx_ring: rx descriptor ring packet is being transacted on
1814  * @skb: pointer to current skb being updated
1815  *
1816  * This function provides a basic DMA sync up for the first fragment of an
1817  * skb.  The reason for doing this is that the first fragment cannot be
1818  * unmapped until we have reached the end of packet descriptor for a buffer
1819  * chain.
1820  */
1821 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1822 				struct sk_buff *skb)
1823 {
1824 	/* if the page was released unmap it, else just sync our portion */
1825 	if (unlikely(IXGBE_CB(skb)->page_released)) {
1826 		dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1827 				     ixgbe_rx_pg_size(rx_ring),
1828 				     DMA_FROM_DEVICE,
1829 				     IXGBE_RX_DMA_ATTR);
1830 	} else if (ring_uses_build_skb(rx_ring)) {
1831 		unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK;
1832 
1833 		dma_sync_single_range_for_cpu(rx_ring->dev,
1834 					      IXGBE_CB(skb)->dma,
1835 					      offset,
1836 					      skb_headlen(skb),
1837 					      DMA_FROM_DEVICE);
1838 	} else {
1839 		struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1840 
1841 		dma_sync_single_range_for_cpu(rx_ring->dev,
1842 					      IXGBE_CB(skb)->dma,
1843 					      frag->page_offset,
1844 					      skb_frag_size(frag),
1845 					      DMA_FROM_DEVICE);
1846 	}
1847 }
1848 
1849 /**
1850  * ixgbe_cleanup_headers - Correct corrupted or empty headers
1851  * @rx_ring: rx descriptor ring packet is being transacted on
1852  * @rx_desc: pointer to the EOP Rx descriptor
1853  * @skb: pointer to current skb being fixed
1854  *
1855  * Check if the skb is valid in the XDP case it will be an error pointer.
1856  * Return true in this case to abort processing and advance to next
1857  * descriptor.
1858  *
1859  * Check for corrupted packet headers caused by senders on the local L2
1860  * embedded NIC switch not setting up their Tx Descriptors right.  These
1861  * should be very rare.
1862  *
1863  * Also address the case where we are pulling data in on pages only
1864  * and as such no data is present in the skb header.
1865  *
1866  * In addition if skb is not at least 60 bytes we need to pad it so that
1867  * it is large enough to qualify as a valid Ethernet frame.
1868  *
1869  * Returns true if an error was encountered and skb was freed.
1870  **/
1871 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1872 				  union ixgbe_adv_rx_desc *rx_desc,
1873 				  struct sk_buff *skb)
1874 {
1875 	struct net_device *netdev = rx_ring->netdev;
1876 
1877 	/* XDP packets use error pointer so abort at this point */
1878 	if (IS_ERR(skb))
1879 		return true;
1880 
1881 	/* Verify netdev is present, and that packet does not have any
1882 	 * errors that would be unacceptable to the netdev.
1883 	 */
1884 	if (!netdev ||
1885 	    (unlikely(ixgbe_test_staterr(rx_desc,
1886 					 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1887 	     !(netdev->features & NETIF_F_RXALL)))) {
1888 		dev_kfree_skb_any(skb);
1889 		return true;
1890 	}
1891 
1892 	/* place header in linear portion of buffer */
1893 	if (!skb_headlen(skb))
1894 		ixgbe_pull_tail(rx_ring, skb);
1895 
1896 #ifdef IXGBE_FCOE
1897 	/* do not attempt to pad FCoE Frames as this will disrupt DDP */
1898 	if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1899 		return false;
1900 
1901 #endif
1902 	/* if eth_skb_pad returns an error the skb was freed */
1903 	if (eth_skb_pad(skb))
1904 		return true;
1905 
1906 	return false;
1907 }
1908 
1909 /**
1910  * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1911  * @rx_ring: rx descriptor ring to store buffers on
1912  * @old_buff: donor buffer to have page reused
1913  *
1914  * Synchronizes page for reuse by the adapter
1915  **/
1916 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1917 				struct ixgbe_rx_buffer *old_buff)
1918 {
1919 	struct ixgbe_rx_buffer *new_buff;
1920 	u16 nta = rx_ring->next_to_alloc;
1921 
1922 	new_buff = &rx_ring->rx_buffer_info[nta];
1923 
1924 	/* update, and store next to alloc */
1925 	nta++;
1926 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1927 
1928 	/* Transfer page from old buffer to new buffer.
1929 	 * Move each member individually to avoid possible store
1930 	 * forwarding stalls and unnecessary copy of skb.
1931 	 */
1932 	new_buff->dma		= old_buff->dma;
1933 	new_buff->page		= old_buff->page;
1934 	new_buff->page_offset	= old_buff->page_offset;
1935 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
1936 }
1937 
1938 static inline bool ixgbe_page_is_reserved(struct page *page)
1939 {
1940 	return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1941 }
1942 
1943 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer)
1944 {
1945 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1946 	struct page *page = rx_buffer->page;
1947 
1948 	/* avoid re-using remote pages */
1949 	if (unlikely(ixgbe_page_is_reserved(page)))
1950 		return false;
1951 
1952 #if (PAGE_SIZE < 8192)
1953 	/* if we are only owner of page we can reuse it */
1954 	if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
1955 		return false;
1956 #else
1957 	/* The last offset is a bit aggressive in that we assume the
1958 	 * worst case of FCoE being enabled and using a 3K buffer.
1959 	 * However this should have minimal impact as the 1K extra is
1960 	 * still less than one buffer in size.
1961 	 */
1962 #define IXGBE_LAST_OFFSET \
1963 	(SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1964 	if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
1965 		return false;
1966 #endif
1967 
1968 	/* If we have drained the page fragment pool we need to update
1969 	 * the pagecnt_bias and page count so that we fully restock the
1970 	 * number of references the driver holds.
1971 	 */
1972 	if (unlikely(pagecnt_bias == 1)) {
1973 		page_ref_add(page, USHRT_MAX - 1);
1974 		rx_buffer->pagecnt_bias = USHRT_MAX;
1975 	}
1976 
1977 	return true;
1978 }
1979 
1980 /**
1981  * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1982  * @rx_ring: rx descriptor ring to transact packets on
1983  * @rx_buffer: buffer containing page to add
1984  * @skb: sk_buff to place the data into
1985  * @size: size of data in rx_buffer
1986  *
1987  * This function will add the data contained in rx_buffer->page to the skb.
1988  * This is done either through a direct copy if the data in the buffer is
1989  * less than the skb header size, otherwise it will just attach the page as
1990  * a frag to the skb.
1991  *
1992  * The function will then update the page offset if necessary and return
1993  * true if the buffer can be reused by the adapter.
1994  **/
1995 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1996 			      struct ixgbe_rx_buffer *rx_buffer,
1997 			      struct sk_buff *skb,
1998 			      unsigned int size)
1999 {
2000 #if (PAGE_SIZE < 8192)
2001 	unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2002 #else
2003 	unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2004 				SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2005 				SKB_DATA_ALIGN(size);
2006 #endif
2007 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2008 			rx_buffer->page_offset, size, truesize);
2009 #if (PAGE_SIZE < 8192)
2010 	rx_buffer->page_offset ^= truesize;
2011 #else
2012 	rx_buffer->page_offset += truesize;
2013 #endif
2014 }
2015 
2016 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2017 						   union ixgbe_adv_rx_desc *rx_desc,
2018 						   struct sk_buff **skb,
2019 						   const unsigned int size)
2020 {
2021 	struct ixgbe_rx_buffer *rx_buffer;
2022 
2023 	rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2024 	prefetchw(rx_buffer->page);
2025 	*skb = rx_buffer->skb;
2026 
2027 	/* Delay unmapping of the first packet. It carries the header
2028 	 * information, HW may still access the header after the writeback.
2029 	 * Only unmap it when EOP is reached
2030 	 */
2031 	if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2032 		if (!*skb)
2033 			goto skip_sync;
2034 	} else {
2035 		if (*skb)
2036 			ixgbe_dma_sync_frag(rx_ring, *skb);
2037 	}
2038 
2039 	/* we are reusing so sync this buffer for CPU use */
2040 	dma_sync_single_range_for_cpu(rx_ring->dev,
2041 				      rx_buffer->dma,
2042 				      rx_buffer->page_offset,
2043 				      size,
2044 				      DMA_FROM_DEVICE);
2045 skip_sync:
2046 	rx_buffer->pagecnt_bias--;
2047 
2048 	return rx_buffer;
2049 }
2050 
2051 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2052 				struct ixgbe_rx_buffer *rx_buffer,
2053 				struct sk_buff *skb)
2054 {
2055 	if (ixgbe_can_reuse_rx_page(rx_buffer)) {
2056 		/* hand second half of page back to the ring */
2057 		ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2058 	} else {
2059 		if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
2060 			/* the page has been released from the ring */
2061 			IXGBE_CB(skb)->page_released = true;
2062 		} else {
2063 			/* we are not reusing the buffer so unmap it */
2064 			dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2065 					     ixgbe_rx_pg_size(rx_ring),
2066 					     DMA_FROM_DEVICE,
2067 					     IXGBE_RX_DMA_ATTR);
2068 		}
2069 		__page_frag_cache_drain(rx_buffer->page,
2070 					rx_buffer->pagecnt_bias);
2071 	}
2072 
2073 	/* clear contents of rx_buffer */
2074 	rx_buffer->page = NULL;
2075 	rx_buffer->skb = NULL;
2076 }
2077 
2078 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2079 					   struct ixgbe_rx_buffer *rx_buffer,
2080 					   struct xdp_buff *xdp,
2081 					   union ixgbe_adv_rx_desc *rx_desc)
2082 {
2083 	unsigned int size = xdp->data_end - xdp->data;
2084 #if (PAGE_SIZE < 8192)
2085 	unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2086 #else
2087 	unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2088 					       xdp->data_hard_start);
2089 #endif
2090 	struct sk_buff *skb;
2091 
2092 	/* prefetch first cache line of first page */
2093 	prefetch(xdp->data);
2094 #if L1_CACHE_BYTES < 128
2095 	prefetch(xdp->data + L1_CACHE_BYTES);
2096 #endif
2097 	/* Note, we get here by enabling legacy-rx via:
2098 	 *
2099 	 *    ethtool --set-priv-flags <dev> legacy-rx on
2100 	 *
2101 	 * In this mode, we currently get 0 extra XDP headroom as
2102 	 * opposed to having legacy-rx off, where we process XDP
2103 	 * packets going to stack via ixgbe_build_skb(). The latter
2104 	 * provides us currently with 192 bytes of headroom.
2105 	 *
2106 	 * For ixgbe_construct_skb() mode it means that the
2107 	 * xdp->data_meta will always point to xdp->data, since
2108 	 * the helper cannot expand the head. Should this ever
2109 	 * change in future for legacy-rx mode on, then lets also
2110 	 * add xdp->data_meta handling here.
2111 	 */
2112 
2113 	/* allocate a skb to store the frags */
2114 	skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2115 	if (unlikely(!skb))
2116 		return NULL;
2117 
2118 	if (size > IXGBE_RX_HDR_SIZE) {
2119 		if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2120 			IXGBE_CB(skb)->dma = rx_buffer->dma;
2121 
2122 		skb_add_rx_frag(skb, 0, rx_buffer->page,
2123 				xdp->data - page_address(rx_buffer->page),
2124 				size, truesize);
2125 #if (PAGE_SIZE < 8192)
2126 		rx_buffer->page_offset ^= truesize;
2127 #else
2128 		rx_buffer->page_offset += truesize;
2129 #endif
2130 	} else {
2131 		memcpy(__skb_put(skb, size),
2132 		       xdp->data, ALIGN(size, sizeof(long)));
2133 		rx_buffer->pagecnt_bias++;
2134 	}
2135 
2136 	return skb;
2137 }
2138 
2139 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2140 				       struct ixgbe_rx_buffer *rx_buffer,
2141 				       struct xdp_buff *xdp,
2142 				       union ixgbe_adv_rx_desc *rx_desc)
2143 {
2144 	unsigned int metasize = xdp->data - xdp->data_meta;
2145 #if (PAGE_SIZE < 8192)
2146 	unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2147 #else
2148 	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2149 				SKB_DATA_ALIGN(xdp->data_end -
2150 					       xdp->data_hard_start);
2151 #endif
2152 	struct sk_buff *skb;
2153 
2154 	/* Prefetch first cache line of first page. If xdp->data_meta
2155 	 * is unused, this points extactly as xdp->data, otherwise we
2156 	 * likely have a consumer accessing first few bytes of meta
2157 	 * data, and then actual data.
2158 	 */
2159 	prefetch(xdp->data_meta);
2160 #if L1_CACHE_BYTES < 128
2161 	prefetch(xdp->data_meta + L1_CACHE_BYTES);
2162 #endif
2163 
2164 	/* build an skb to around the page buffer */
2165 	skb = build_skb(xdp->data_hard_start, truesize);
2166 	if (unlikely(!skb))
2167 		return NULL;
2168 
2169 	/* update pointers within the skb to store the data */
2170 	skb_reserve(skb, xdp->data - xdp->data_hard_start);
2171 	__skb_put(skb, xdp->data_end - xdp->data);
2172 	if (metasize)
2173 		skb_metadata_set(skb, metasize);
2174 
2175 	/* record DMA address if this is the start of a chain of buffers */
2176 	if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2177 		IXGBE_CB(skb)->dma = rx_buffer->dma;
2178 
2179 	/* update buffer offset */
2180 #if (PAGE_SIZE < 8192)
2181 	rx_buffer->page_offset ^= truesize;
2182 #else
2183 	rx_buffer->page_offset += truesize;
2184 #endif
2185 
2186 	return skb;
2187 }
2188 
2189 #define IXGBE_XDP_PASS 0
2190 #define IXGBE_XDP_CONSUMED 1
2191 #define IXGBE_XDP_TX 2
2192 
2193 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
2194 			       struct xdp_frame *xdpf);
2195 
2196 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2197 				     struct ixgbe_ring *rx_ring,
2198 				     struct xdp_buff *xdp)
2199 {
2200 	int err, result = IXGBE_XDP_PASS;
2201 	struct bpf_prog *xdp_prog;
2202 	struct xdp_frame *xdpf;
2203 	u32 act;
2204 
2205 	rcu_read_lock();
2206 	xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2207 
2208 	if (!xdp_prog)
2209 		goto xdp_out;
2210 
2211 	prefetchw(xdp->data_hard_start); /* xdp_frame write */
2212 
2213 	act = bpf_prog_run_xdp(xdp_prog, xdp);
2214 	switch (act) {
2215 	case XDP_PASS:
2216 		break;
2217 	case XDP_TX:
2218 		xdpf = convert_to_xdp_frame(xdp);
2219 		if (unlikely(!xdpf)) {
2220 			result = IXGBE_XDP_CONSUMED;
2221 			break;
2222 		}
2223 		result = ixgbe_xmit_xdp_ring(adapter, xdpf);
2224 		break;
2225 	case XDP_REDIRECT:
2226 		err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
2227 		if (!err)
2228 			result = IXGBE_XDP_TX;
2229 		else
2230 			result = IXGBE_XDP_CONSUMED;
2231 		break;
2232 	default:
2233 		bpf_warn_invalid_xdp_action(act);
2234 		/* fallthrough */
2235 	case XDP_ABORTED:
2236 		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2237 		/* fallthrough -- handle aborts by dropping packet */
2238 	case XDP_DROP:
2239 		result = IXGBE_XDP_CONSUMED;
2240 		break;
2241 	}
2242 xdp_out:
2243 	rcu_read_unlock();
2244 	return ERR_PTR(-result);
2245 }
2246 
2247 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2248 				 struct ixgbe_rx_buffer *rx_buffer,
2249 				 unsigned int size)
2250 {
2251 #if (PAGE_SIZE < 8192)
2252 	unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2253 
2254 	rx_buffer->page_offset ^= truesize;
2255 #else
2256 	unsigned int truesize = ring_uses_build_skb(rx_ring) ?
2257 				SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) :
2258 				SKB_DATA_ALIGN(size);
2259 
2260 	rx_buffer->page_offset += truesize;
2261 #endif
2262 }
2263 
2264 /**
2265  * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2266  * @q_vector: structure containing interrupt and ring information
2267  * @rx_ring: rx descriptor ring to transact packets on
2268  * @budget: Total limit on number of packets to process
2269  *
2270  * This function provides a "bounce buffer" approach to Rx interrupt
2271  * processing.  The advantage to this is that on systems that have
2272  * expensive overhead for IOMMU access this provides a means of avoiding
2273  * it by maintaining the mapping of the page to the syste.
2274  *
2275  * Returns amount of work completed
2276  **/
2277 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2278 			       struct ixgbe_ring *rx_ring,
2279 			       const int budget)
2280 {
2281 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2282 	struct ixgbe_adapter *adapter = q_vector->adapter;
2283 #ifdef IXGBE_FCOE
2284 	int ddp_bytes;
2285 	unsigned int mss = 0;
2286 #endif /* IXGBE_FCOE */
2287 	u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2288 	bool xdp_xmit = false;
2289 	struct xdp_buff xdp;
2290 
2291 	xdp.rxq = &rx_ring->xdp_rxq;
2292 
2293 	while (likely(total_rx_packets < budget)) {
2294 		union ixgbe_adv_rx_desc *rx_desc;
2295 		struct ixgbe_rx_buffer *rx_buffer;
2296 		struct sk_buff *skb;
2297 		unsigned int size;
2298 
2299 		/* return some buffers to hardware, one at a time is too slow */
2300 		if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2301 			ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2302 			cleaned_count = 0;
2303 		}
2304 
2305 		rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2306 		size = le16_to_cpu(rx_desc->wb.upper.length);
2307 		if (!size)
2308 			break;
2309 
2310 		/* This memory barrier is needed to keep us from reading
2311 		 * any other fields out of the rx_desc until we know the
2312 		 * descriptor has been written back
2313 		 */
2314 		dma_rmb();
2315 
2316 		rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size);
2317 
2318 		/* retrieve a buffer from the ring */
2319 		if (!skb) {
2320 			xdp.data = page_address(rx_buffer->page) +
2321 				   rx_buffer->page_offset;
2322 			xdp.data_meta = xdp.data;
2323 			xdp.data_hard_start = xdp.data -
2324 					      ixgbe_rx_offset(rx_ring);
2325 			xdp.data_end = xdp.data + size;
2326 
2327 			skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
2328 		}
2329 
2330 		if (IS_ERR(skb)) {
2331 			if (PTR_ERR(skb) == -IXGBE_XDP_TX) {
2332 				xdp_xmit = true;
2333 				ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
2334 			} else {
2335 				rx_buffer->pagecnt_bias++;
2336 			}
2337 			total_rx_packets++;
2338 			total_rx_bytes += size;
2339 		} else if (skb) {
2340 			ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
2341 		} else if (ring_uses_build_skb(rx_ring)) {
2342 			skb = ixgbe_build_skb(rx_ring, rx_buffer,
2343 					      &xdp, rx_desc);
2344 		} else {
2345 			skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2346 						  &xdp, rx_desc);
2347 		}
2348 
2349 		/* exit if we failed to retrieve a buffer */
2350 		if (!skb) {
2351 			rx_ring->rx_stats.alloc_rx_buff_failed++;
2352 			rx_buffer->pagecnt_bias++;
2353 			break;
2354 		}
2355 
2356 		ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb);
2357 		cleaned_count++;
2358 
2359 		/* place incomplete frames back on ring for completion */
2360 		if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2361 			continue;
2362 
2363 		/* verify the packet layout is correct */
2364 		if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2365 			continue;
2366 
2367 		/* probably a little skewed due to removing CRC */
2368 		total_rx_bytes += skb->len;
2369 
2370 		/* populate checksum, timestamp, VLAN, and protocol */
2371 		ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2372 
2373 #ifdef IXGBE_FCOE
2374 		/* if ddp, not passing to ULD unless for FCP_RSP or error */
2375 		if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2376 			ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2377 			/* include DDPed FCoE data */
2378 			if (ddp_bytes > 0) {
2379 				if (!mss) {
2380 					mss = rx_ring->netdev->mtu -
2381 						sizeof(struct fcoe_hdr) -
2382 						sizeof(struct fc_frame_header) -
2383 						sizeof(struct fcoe_crc_eof);
2384 					if (mss > 512)
2385 						mss &= ~511;
2386 				}
2387 				total_rx_bytes += ddp_bytes;
2388 				total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2389 								 mss);
2390 			}
2391 			if (!ddp_bytes) {
2392 				dev_kfree_skb_any(skb);
2393 				continue;
2394 			}
2395 		}
2396 
2397 #endif /* IXGBE_FCOE */
2398 		ixgbe_rx_skb(q_vector, skb);
2399 
2400 		/* update budget accounting */
2401 		total_rx_packets++;
2402 	}
2403 
2404 	if (xdp_xmit) {
2405 		struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
2406 
2407 		/* Force memory writes to complete before letting h/w
2408 		 * know there are new descriptors to fetch.
2409 		 */
2410 		wmb();
2411 		writel(ring->next_to_use, ring->tail);
2412 
2413 		xdp_do_flush_map();
2414 	}
2415 
2416 	u64_stats_update_begin(&rx_ring->syncp);
2417 	rx_ring->stats.packets += total_rx_packets;
2418 	rx_ring->stats.bytes += total_rx_bytes;
2419 	u64_stats_update_end(&rx_ring->syncp);
2420 	q_vector->rx.total_packets += total_rx_packets;
2421 	q_vector->rx.total_bytes += total_rx_bytes;
2422 
2423 	return total_rx_packets;
2424 }
2425 
2426 /**
2427  * ixgbe_configure_msix - Configure MSI-X hardware
2428  * @adapter: board private structure
2429  *
2430  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2431  * interrupts.
2432  **/
2433 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2434 {
2435 	struct ixgbe_q_vector *q_vector;
2436 	int v_idx;
2437 	u32 mask;
2438 
2439 	/* Populate MSIX to EITR Select */
2440 	if (adapter->num_vfs > 32) {
2441 		u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2442 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2443 	}
2444 
2445 	/*
2446 	 * Populate the IVAR table and set the ITR values to the
2447 	 * corresponding register.
2448 	 */
2449 	for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2450 		struct ixgbe_ring *ring;
2451 		q_vector = adapter->q_vector[v_idx];
2452 
2453 		ixgbe_for_each_ring(ring, q_vector->rx)
2454 			ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2455 
2456 		ixgbe_for_each_ring(ring, q_vector->tx)
2457 			ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2458 
2459 		ixgbe_write_eitr(q_vector);
2460 	}
2461 
2462 	switch (adapter->hw.mac.type) {
2463 	case ixgbe_mac_82598EB:
2464 		ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2465 			       v_idx);
2466 		break;
2467 	case ixgbe_mac_82599EB:
2468 	case ixgbe_mac_X540:
2469 	case ixgbe_mac_X550:
2470 	case ixgbe_mac_X550EM_x:
2471 	case ixgbe_mac_x550em_a:
2472 		ixgbe_set_ivar(adapter, -1, 1, v_idx);
2473 		break;
2474 	default:
2475 		break;
2476 	}
2477 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2478 
2479 	/* set up to autoclear timer, and the vectors */
2480 	mask = IXGBE_EIMS_ENABLE_MASK;
2481 	mask &= ~(IXGBE_EIMS_OTHER |
2482 		  IXGBE_EIMS_MAILBOX |
2483 		  IXGBE_EIMS_LSC);
2484 
2485 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2486 }
2487 
2488 /**
2489  * ixgbe_update_itr - update the dynamic ITR value based on statistics
2490  * @q_vector: structure containing interrupt and ring information
2491  * @ring_container: structure containing ring performance data
2492  *
2493  *      Stores a new ITR value based on packets and byte
2494  *      counts during the last interrupt.  The advantage of per interrupt
2495  *      computation is faster updates and more accurate ITR for the current
2496  *      traffic pattern.  Constants in this function were computed
2497  *      based on theoretical maximum wire speed and thresholds were set based
2498  *      on testing data as well as attempting to minimize response time
2499  *      while increasing bulk throughput.
2500  **/
2501 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2502 			     struct ixgbe_ring_container *ring_container)
2503 {
2504 	unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2505 			   IXGBE_ITR_ADAPTIVE_LATENCY;
2506 	unsigned int avg_wire_size, packets, bytes;
2507 	unsigned long next_update = jiffies;
2508 
2509 	/* If we don't have any rings just leave ourselves set for maximum
2510 	 * possible latency so we take ourselves out of the equation.
2511 	 */
2512 	if (!ring_container->ring)
2513 		return;
2514 
2515 	/* If we didn't update within up to 1 - 2 jiffies we can assume
2516 	 * that either packets are coming in so slow there hasn't been
2517 	 * any work, or that there is so much work that NAPI is dealing
2518 	 * with interrupt moderation and we don't need to do anything.
2519 	 */
2520 	if (time_after(next_update, ring_container->next_update))
2521 		goto clear_counts;
2522 
2523 	packets = ring_container->total_packets;
2524 
2525 	/* We have no packets to actually measure against. This means
2526 	 * either one of the other queues on this vector is active or
2527 	 * we are a Tx queue doing TSO with too high of an interrupt rate.
2528 	 *
2529 	 * When this occurs just tick up our delay by the minimum value
2530 	 * and hope that this extra delay will prevent us from being called
2531 	 * without any work on our queue.
2532 	 */
2533 	if (!packets) {
2534 		itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2535 		if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2536 			itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2537 		itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2538 		goto clear_counts;
2539 	}
2540 
2541 	bytes = ring_container->total_bytes;
2542 
2543 	/* If packets are less than 4 or bytes are less than 9000 assume
2544 	 * insufficient data to use bulk rate limiting approach. We are
2545 	 * likely latency driven.
2546 	 */
2547 	if (packets < 4 && bytes < 9000) {
2548 		itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2549 		goto adjust_by_size;
2550 	}
2551 
2552 	/* Between 4 and 48 we can assume that our current interrupt delay
2553 	 * is only slightly too low. As such we should increase it by a small
2554 	 * fixed amount.
2555 	 */
2556 	if (packets < 48) {
2557 		itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2558 		if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2559 			itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2560 		goto clear_counts;
2561 	}
2562 
2563 	/* Between 48 and 96 is our "goldilocks" zone where we are working
2564 	 * out "just right". Just report that our current ITR is good for us.
2565 	 */
2566 	if (packets < 96) {
2567 		itr = q_vector->itr >> 2;
2568 		goto clear_counts;
2569 	}
2570 
2571 	/* If packet count is 96 or greater we are likely looking at a slight
2572 	 * overrun of the delay we want. Try halving our delay to see if that
2573 	 * will cut the number of packets in half per interrupt.
2574 	 */
2575 	if (packets < 256) {
2576 		itr = q_vector->itr >> 3;
2577 		if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2578 			itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2579 		goto clear_counts;
2580 	}
2581 
2582 	/* The paths below assume we are dealing with a bulk ITR since number
2583 	 * of packets is 256 or greater. We are just going to have to compute
2584 	 * a value and try to bring the count under control, though for smaller
2585 	 * packet sizes there isn't much we can do as NAPI polling will likely
2586 	 * be kicking in sooner rather than later.
2587 	 */
2588 	itr = IXGBE_ITR_ADAPTIVE_BULK;
2589 
2590 adjust_by_size:
2591 	/* If packet counts are 256 or greater we can assume we have a gross
2592 	 * overestimation of what the rate should be. Instead of trying to fine
2593 	 * tune it just use the formula below to try and dial in an exact value
2594 	 * give the current packet size of the frame.
2595 	 */
2596 	avg_wire_size = bytes / packets;
2597 
2598 	/* The following is a crude approximation of:
2599 	 *  wmem_default / (size + overhead) = desired_pkts_per_int
2600 	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2601 	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2602 	 *
2603 	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2604 	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2605 	 * formula down to
2606 	 *
2607 	 *  (170 * (size + 24)) / (size + 640) = ITR
2608 	 *
2609 	 * We first do some math on the packet size and then finally bitshift
2610 	 * by 8 after rounding up. We also have to account for PCIe link speed
2611 	 * difference as ITR scales based on this.
2612 	 */
2613 	if (avg_wire_size <= 60) {
2614 		/* Start at 50k ints/sec */
2615 		avg_wire_size = 5120;
2616 	} else if (avg_wire_size <= 316) {
2617 		/* 50K ints/sec to 16K ints/sec */
2618 		avg_wire_size *= 40;
2619 		avg_wire_size += 2720;
2620 	} else if (avg_wire_size <= 1084) {
2621 		/* 16K ints/sec to 9.2K ints/sec */
2622 		avg_wire_size *= 15;
2623 		avg_wire_size += 11452;
2624 	} else if (avg_wire_size <= 1980) {
2625 		/* 9.2K ints/sec to 8K ints/sec */
2626 		avg_wire_size *= 5;
2627 		avg_wire_size += 22420;
2628 	} else {
2629 		/* plateau at a limit of 8K ints/sec */
2630 		avg_wire_size = 32256;
2631 	}
2632 
2633 	/* If we are in low latency mode half our delay which doubles the rate
2634 	 * to somewhere between 100K to 16K ints/sec
2635 	 */
2636 	if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2637 		avg_wire_size >>= 1;
2638 
2639 	/* Resultant value is 256 times larger than it needs to be. This
2640 	 * gives us room to adjust the value as needed to either increase
2641 	 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2642 	 *
2643 	 * Use addition as we have already recorded the new latency flag
2644 	 * for the ITR value.
2645 	 */
2646 	switch (q_vector->adapter->link_speed) {
2647 	case IXGBE_LINK_SPEED_10GB_FULL:
2648 	case IXGBE_LINK_SPEED_100_FULL:
2649 	default:
2650 		itr += DIV_ROUND_UP(avg_wire_size,
2651 				    IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2652 		       IXGBE_ITR_ADAPTIVE_MIN_INC;
2653 		break;
2654 	case IXGBE_LINK_SPEED_2_5GB_FULL:
2655 	case IXGBE_LINK_SPEED_1GB_FULL:
2656 	case IXGBE_LINK_SPEED_10_FULL:
2657 		itr += DIV_ROUND_UP(avg_wire_size,
2658 				    IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2659 		       IXGBE_ITR_ADAPTIVE_MIN_INC;
2660 		break;
2661 	}
2662 
2663 clear_counts:
2664 	/* write back value */
2665 	ring_container->itr = itr;
2666 
2667 	/* next update should occur within next jiffy */
2668 	ring_container->next_update = next_update + 1;
2669 
2670 	ring_container->total_bytes = 0;
2671 	ring_container->total_packets = 0;
2672 }
2673 
2674 /**
2675  * ixgbe_write_eitr - write EITR register in hardware specific way
2676  * @q_vector: structure containing interrupt and ring information
2677  *
2678  * This function is made to be called by ethtool and by the driver
2679  * when it needs to update EITR registers at runtime.  Hardware
2680  * specific quirks/differences are taken care of here.
2681  */
2682 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2683 {
2684 	struct ixgbe_adapter *adapter = q_vector->adapter;
2685 	struct ixgbe_hw *hw = &adapter->hw;
2686 	int v_idx = q_vector->v_idx;
2687 	u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2688 
2689 	switch (adapter->hw.mac.type) {
2690 	case ixgbe_mac_82598EB:
2691 		/* must write high and low 16 bits to reset counter */
2692 		itr_reg |= (itr_reg << 16);
2693 		break;
2694 	case ixgbe_mac_82599EB:
2695 	case ixgbe_mac_X540:
2696 	case ixgbe_mac_X550:
2697 	case ixgbe_mac_X550EM_x:
2698 	case ixgbe_mac_x550em_a:
2699 		/*
2700 		 * set the WDIS bit to not clear the timer bits and cause an
2701 		 * immediate assertion of the interrupt
2702 		 */
2703 		itr_reg |= IXGBE_EITR_CNT_WDIS;
2704 		break;
2705 	default:
2706 		break;
2707 	}
2708 	IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2709 }
2710 
2711 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2712 {
2713 	u32 new_itr;
2714 
2715 	ixgbe_update_itr(q_vector, &q_vector->tx);
2716 	ixgbe_update_itr(q_vector, &q_vector->rx);
2717 
2718 	/* use the smallest value of new ITR delay calculations */
2719 	new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
2720 
2721 	/* Clear latency flag if set, shift into correct position */
2722 	new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2723 	new_itr <<= 2;
2724 
2725 	if (new_itr != q_vector->itr) {
2726 		/* save the algorithm value here */
2727 		q_vector->itr = new_itr;
2728 
2729 		ixgbe_write_eitr(q_vector);
2730 	}
2731 }
2732 
2733 /**
2734  * ixgbe_check_overtemp_subtask - check for over temperature
2735  * @adapter: pointer to adapter
2736  **/
2737 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2738 {
2739 	struct ixgbe_hw *hw = &adapter->hw;
2740 	u32 eicr = adapter->interrupt_event;
2741 	s32 rc;
2742 
2743 	if (test_bit(__IXGBE_DOWN, &adapter->state))
2744 		return;
2745 
2746 	if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2747 		return;
2748 
2749 	adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2750 
2751 	switch (hw->device_id) {
2752 	case IXGBE_DEV_ID_82599_T3_LOM:
2753 		/*
2754 		 * Since the warning interrupt is for both ports
2755 		 * we don't have to check if:
2756 		 *  - This interrupt wasn't for our port.
2757 		 *  - We may have missed the interrupt so always have to
2758 		 *    check if we  got a LSC
2759 		 */
2760 		if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2761 		    !(eicr & IXGBE_EICR_LSC))
2762 			return;
2763 
2764 		if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2765 			u32 speed;
2766 			bool link_up = false;
2767 
2768 			hw->mac.ops.check_link(hw, &speed, &link_up, false);
2769 
2770 			if (link_up)
2771 				return;
2772 		}
2773 
2774 		/* Check if this is not due to overtemp */
2775 		if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2776 			return;
2777 
2778 		break;
2779 	case IXGBE_DEV_ID_X550EM_A_1G_T:
2780 	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2781 		rc = hw->phy.ops.check_overtemp(hw);
2782 		if (rc != IXGBE_ERR_OVERTEMP)
2783 			return;
2784 		break;
2785 	default:
2786 		if (adapter->hw.mac.type >= ixgbe_mac_X540)
2787 			return;
2788 		if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2789 			return;
2790 		break;
2791 	}
2792 	e_crit(drv, "%s\n", ixgbe_overheat_msg);
2793 
2794 	adapter->interrupt_event = 0;
2795 }
2796 
2797 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2798 {
2799 	struct ixgbe_hw *hw = &adapter->hw;
2800 
2801 	if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2802 	    (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2803 		e_crit(probe, "Fan has stopped, replace the adapter\n");
2804 		/* write to clear the interrupt */
2805 		IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2806 	}
2807 }
2808 
2809 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2810 {
2811 	struct ixgbe_hw *hw = &adapter->hw;
2812 
2813 	if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2814 		return;
2815 
2816 	switch (adapter->hw.mac.type) {
2817 	case ixgbe_mac_82599EB:
2818 		/*
2819 		 * Need to check link state so complete overtemp check
2820 		 * on service task
2821 		 */
2822 		if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2823 		     (eicr & IXGBE_EICR_LSC)) &&
2824 		    (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2825 			adapter->interrupt_event = eicr;
2826 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2827 			ixgbe_service_event_schedule(adapter);
2828 			return;
2829 		}
2830 		return;
2831 	case ixgbe_mac_x550em_a:
2832 		if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2833 			adapter->interrupt_event = eicr;
2834 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2835 			ixgbe_service_event_schedule(adapter);
2836 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2837 					IXGBE_EICR_GPI_SDP0_X550EM_a);
2838 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2839 					IXGBE_EICR_GPI_SDP0_X550EM_a);
2840 		}
2841 		return;
2842 	case ixgbe_mac_X550:
2843 	case ixgbe_mac_X540:
2844 		if (!(eicr & IXGBE_EICR_TS))
2845 			return;
2846 		break;
2847 	default:
2848 		return;
2849 	}
2850 
2851 	e_crit(drv, "%s\n", ixgbe_overheat_msg);
2852 }
2853 
2854 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2855 {
2856 	switch (hw->mac.type) {
2857 	case ixgbe_mac_82598EB:
2858 		if (hw->phy.type == ixgbe_phy_nl)
2859 			return true;
2860 		return false;
2861 	case ixgbe_mac_82599EB:
2862 	case ixgbe_mac_X550EM_x:
2863 	case ixgbe_mac_x550em_a:
2864 		switch (hw->mac.ops.get_media_type(hw)) {
2865 		case ixgbe_media_type_fiber:
2866 		case ixgbe_media_type_fiber_qsfp:
2867 			return true;
2868 		default:
2869 			return false;
2870 		}
2871 	default:
2872 		return false;
2873 	}
2874 }
2875 
2876 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2877 {
2878 	struct ixgbe_hw *hw = &adapter->hw;
2879 	u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2880 
2881 	if (!ixgbe_is_sfp(hw))
2882 		return;
2883 
2884 	/* Later MAC's use different SDP */
2885 	if (hw->mac.type >= ixgbe_mac_X540)
2886 		eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2887 
2888 	if (eicr & eicr_mask) {
2889 		/* Clear the interrupt */
2890 		IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2891 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2892 			adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2893 			adapter->sfp_poll_time = 0;
2894 			ixgbe_service_event_schedule(adapter);
2895 		}
2896 	}
2897 
2898 	if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2899 	    (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2900 		/* Clear the interrupt */
2901 		IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2902 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2903 			adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2904 			ixgbe_service_event_schedule(adapter);
2905 		}
2906 	}
2907 }
2908 
2909 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2910 {
2911 	struct ixgbe_hw *hw = &adapter->hw;
2912 
2913 	adapter->lsc_int++;
2914 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2915 	adapter->link_check_timeout = jiffies;
2916 	if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2917 		IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2918 		IXGBE_WRITE_FLUSH(hw);
2919 		ixgbe_service_event_schedule(adapter);
2920 	}
2921 }
2922 
2923 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2924 					   u64 qmask)
2925 {
2926 	u32 mask;
2927 	struct ixgbe_hw *hw = &adapter->hw;
2928 
2929 	switch (hw->mac.type) {
2930 	case ixgbe_mac_82598EB:
2931 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2932 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2933 		break;
2934 	case ixgbe_mac_82599EB:
2935 	case ixgbe_mac_X540:
2936 	case ixgbe_mac_X550:
2937 	case ixgbe_mac_X550EM_x:
2938 	case ixgbe_mac_x550em_a:
2939 		mask = (qmask & 0xFFFFFFFF);
2940 		if (mask)
2941 			IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2942 		mask = (qmask >> 32);
2943 		if (mask)
2944 			IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2945 		break;
2946 	default:
2947 		break;
2948 	}
2949 	/* skip the flush */
2950 }
2951 
2952 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2953 					    u64 qmask)
2954 {
2955 	u32 mask;
2956 	struct ixgbe_hw *hw = &adapter->hw;
2957 
2958 	switch (hw->mac.type) {
2959 	case ixgbe_mac_82598EB:
2960 		mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2961 		IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2962 		break;
2963 	case ixgbe_mac_82599EB:
2964 	case ixgbe_mac_X540:
2965 	case ixgbe_mac_X550:
2966 	case ixgbe_mac_X550EM_x:
2967 	case ixgbe_mac_x550em_a:
2968 		mask = (qmask & 0xFFFFFFFF);
2969 		if (mask)
2970 			IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2971 		mask = (qmask >> 32);
2972 		if (mask)
2973 			IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2974 		break;
2975 	default:
2976 		break;
2977 	}
2978 	/* skip the flush */
2979 }
2980 
2981 /**
2982  * ixgbe_irq_enable - Enable default interrupt generation settings
2983  * @adapter: board private structure
2984  * @queues: enable irqs for queues
2985  * @flush: flush register write
2986  **/
2987 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2988 				    bool flush)
2989 {
2990 	struct ixgbe_hw *hw = &adapter->hw;
2991 	u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2992 
2993 	/* don't reenable LSC while waiting for link */
2994 	if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2995 		mask &= ~IXGBE_EIMS_LSC;
2996 
2997 	if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2998 		switch (adapter->hw.mac.type) {
2999 		case ixgbe_mac_82599EB:
3000 			mask |= IXGBE_EIMS_GPI_SDP0(hw);
3001 			break;
3002 		case ixgbe_mac_X540:
3003 		case ixgbe_mac_X550:
3004 		case ixgbe_mac_X550EM_x:
3005 		case ixgbe_mac_x550em_a:
3006 			mask |= IXGBE_EIMS_TS;
3007 			break;
3008 		default:
3009 			break;
3010 		}
3011 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3012 		mask |= IXGBE_EIMS_GPI_SDP1(hw);
3013 	switch (adapter->hw.mac.type) {
3014 	case ixgbe_mac_82599EB:
3015 		mask |= IXGBE_EIMS_GPI_SDP1(hw);
3016 		mask |= IXGBE_EIMS_GPI_SDP2(hw);
3017 		/* fall through */
3018 	case ixgbe_mac_X540:
3019 	case ixgbe_mac_X550:
3020 	case ixgbe_mac_X550EM_x:
3021 	case ixgbe_mac_x550em_a:
3022 		if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3023 		    adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
3024 		    adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
3025 			mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
3026 		if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3027 			mask |= IXGBE_EICR_GPI_SDP0_X540;
3028 		mask |= IXGBE_EIMS_ECC;
3029 		mask |= IXGBE_EIMS_MAILBOX;
3030 		break;
3031 	default:
3032 		break;
3033 	}
3034 
3035 	if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3036 	    !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3037 		mask |= IXGBE_EIMS_FLOW_DIR;
3038 
3039 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3040 	if (queues)
3041 		ixgbe_irq_enable_queues(adapter, ~0);
3042 	if (flush)
3043 		IXGBE_WRITE_FLUSH(&adapter->hw);
3044 }
3045 
3046 static irqreturn_t ixgbe_msix_other(int irq, void *data)
3047 {
3048 	struct ixgbe_adapter *adapter = data;
3049 	struct ixgbe_hw *hw = &adapter->hw;
3050 	u32 eicr;
3051 
3052 	/*
3053 	 * Workaround for Silicon errata.  Use clear-by-write instead
3054 	 * of clear-by-read.  Reading with EICS will return the
3055 	 * interrupt causes without clearing, which later be done
3056 	 * with the write to EICR.
3057 	 */
3058 	eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3059 
3060 	/* The lower 16bits of the EICR register are for the queue interrupts
3061 	 * which should be masked here in order to not accidentally clear them if
3062 	 * the bits are high when ixgbe_msix_other is called. There is a race
3063 	 * condition otherwise which results in possible performance loss
3064 	 * especially if the ixgbe_msix_other interrupt is triggering
3065 	 * consistently (as it would when PPS is turned on for the X540 device)
3066 	 */
3067 	eicr &= 0xFFFF0000;
3068 
3069 	IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3070 
3071 	if (eicr & IXGBE_EICR_LSC)
3072 		ixgbe_check_lsc(adapter);
3073 
3074 	if (eicr & IXGBE_EICR_MAILBOX)
3075 		ixgbe_msg_task(adapter);
3076 
3077 	switch (hw->mac.type) {
3078 	case ixgbe_mac_82599EB:
3079 	case ixgbe_mac_X540:
3080 	case ixgbe_mac_X550:
3081 	case ixgbe_mac_X550EM_x:
3082 	case ixgbe_mac_x550em_a:
3083 		if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3084 		    (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3085 			adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3086 			ixgbe_service_event_schedule(adapter);
3087 			IXGBE_WRITE_REG(hw, IXGBE_EICR,
3088 					IXGBE_EICR_GPI_SDP0_X540);
3089 		}
3090 		if (eicr & IXGBE_EICR_ECC) {
3091 			e_info(link, "Received ECC Err, initiating reset\n");
3092 			set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3093 			ixgbe_service_event_schedule(adapter);
3094 			IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3095 		}
3096 		/* Handle Flow Director Full threshold interrupt */
3097 		if (eicr & IXGBE_EICR_FLOW_DIR) {
3098 			int reinit_count = 0;
3099 			int i;
3100 			for (i = 0; i < adapter->num_tx_queues; i++) {
3101 				struct ixgbe_ring *ring = adapter->tx_ring[i];
3102 				if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
3103 						       &ring->state))
3104 					reinit_count++;
3105 			}
3106 			if (reinit_count) {
3107 				/* no more flow director interrupts until after init */
3108 				IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
3109 				adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3110 				ixgbe_service_event_schedule(adapter);
3111 			}
3112 		}
3113 		ixgbe_check_sfp_event(adapter, eicr);
3114 		ixgbe_check_overtemp_event(adapter, eicr);
3115 		break;
3116 	default:
3117 		break;
3118 	}
3119 
3120 	ixgbe_check_fan_failure(adapter, eicr);
3121 
3122 	if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3123 		ixgbe_ptp_check_pps_event(adapter);
3124 
3125 	/* re-enable the original interrupt state, no lsc, no queues */
3126 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
3127 		ixgbe_irq_enable(adapter, false, false);
3128 
3129 	return IRQ_HANDLED;
3130 }
3131 
3132 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
3133 {
3134 	struct ixgbe_q_vector *q_vector = data;
3135 
3136 	/* EIAM disabled interrupts (on this vector) for us */
3137 
3138 	if (q_vector->rx.ring || q_vector->tx.ring)
3139 		napi_schedule_irqoff(&q_vector->napi);
3140 
3141 	return IRQ_HANDLED;
3142 }
3143 
3144 /**
3145  * ixgbe_poll - NAPI Rx polling callback
3146  * @napi: structure for representing this polling device
3147  * @budget: how many packets driver is allowed to clean
3148  *
3149  * This function is used for legacy and MSI, NAPI mode
3150  **/
3151 int ixgbe_poll(struct napi_struct *napi, int budget)
3152 {
3153 	struct ixgbe_q_vector *q_vector =
3154 				container_of(napi, struct ixgbe_q_vector, napi);
3155 	struct ixgbe_adapter *adapter = q_vector->adapter;
3156 	struct ixgbe_ring *ring;
3157 	int per_ring_budget, work_done = 0;
3158 	bool clean_complete = true;
3159 
3160 #ifdef CONFIG_IXGBE_DCA
3161 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3162 		ixgbe_update_dca(q_vector);
3163 #endif
3164 
3165 	ixgbe_for_each_ring(ring, q_vector->tx) {
3166 		if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
3167 			clean_complete = false;
3168 	}
3169 
3170 	/* Exit if we are called by netpoll */
3171 	if (budget <= 0)
3172 		return budget;
3173 
3174 	/* attempt to distribute budget to each queue fairly, but don't allow
3175 	 * the budget to go below 1 because we'll exit polling */
3176 	if (q_vector->rx.count > 1)
3177 		per_ring_budget = max(budget/q_vector->rx.count, 1);
3178 	else
3179 		per_ring_budget = budget;
3180 
3181 	ixgbe_for_each_ring(ring, q_vector->rx) {
3182 		int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
3183 						 per_ring_budget);
3184 
3185 		work_done += cleaned;
3186 		if (cleaned >= per_ring_budget)
3187 			clean_complete = false;
3188 	}
3189 
3190 	/* If all work not completed, return budget and keep polling */
3191 	if (!clean_complete)
3192 		return budget;
3193 
3194 	/* all work done, exit the polling mode */
3195 	napi_complete_done(napi, work_done);
3196 	if (adapter->rx_itr_setting & 1)
3197 		ixgbe_set_itr(q_vector);
3198 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
3199 		ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx));
3200 
3201 	return min(work_done, budget - 1);
3202 }
3203 
3204 /**
3205  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3206  * @adapter: board private structure
3207  *
3208  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3209  * interrupts from the kernel.
3210  **/
3211 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3212 {
3213 	struct net_device *netdev = adapter->netdev;
3214 	unsigned int ri = 0, ti = 0;
3215 	int vector, err;
3216 
3217 	for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3218 		struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3219 		struct msix_entry *entry = &adapter->msix_entries[vector];
3220 
3221 		if (q_vector->tx.ring && q_vector->rx.ring) {
3222 			snprintf(q_vector->name, sizeof(q_vector->name),
3223 				 "%s-TxRx-%u", netdev->name, ri++);
3224 			ti++;
3225 		} else if (q_vector->rx.ring) {
3226 			snprintf(q_vector->name, sizeof(q_vector->name),
3227 				 "%s-rx-%u", netdev->name, ri++);
3228 		} else if (q_vector->tx.ring) {
3229 			snprintf(q_vector->name, sizeof(q_vector->name),
3230 				 "%s-tx-%u", netdev->name, ti++);
3231 		} else {
3232 			/* skip this unused q_vector */
3233 			continue;
3234 		}
3235 		err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3236 				  q_vector->name, q_vector);
3237 		if (err) {
3238 			e_err(probe, "request_irq failed for MSIX interrupt "
3239 			      "Error: %d\n", err);
3240 			goto free_queue_irqs;
3241 		}
3242 		/* If Flow Director is enabled, set interrupt affinity */
3243 		if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3244 			/* assign the mask for this irq */
3245 			irq_set_affinity_hint(entry->vector,
3246 					      &q_vector->affinity_mask);
3247 		}
3248 	}
3249 
3250 	err = request_irq(adapter->msix_entries[vector].vector,
3251 			  ixgbe_msix_other, 0, netdev->name, adapter);
3252 	if (err) {
3253 		e_err(probe, "request_irq for msix_other failed: %d\n", err);
3254 		goto free_queue_irqs;
3255 	}
3256 
3257 	return 0;
3258 
3259 free_queue_irqs:
3260 	while (vector) {
3261 		vector--;
3262 		irq_set_affinity_hint(adapter->msix_entries[vector].vector,
3263 				      NULL);
3264 		free_irq(adapter->msix_entries[vector].vector,
3265 			 adapter->q_vector[vector]);
3266 	}
3267 	adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3268 	pci_disable_msix(adapter->pdev);
3269 	kfree(adapter->msix_entries);
3270 	adapter->msix_entries = NULL;
3271 	return err;
3272 }
3273 
3274 /**
3275  * ixgbe_intr - legacy mode Interrupt Handler
3276  * @irq: interrupt number
3277  * @data: pointer to a network interface device structure
3278  **/
3279 static irqreturn_t ixgbe_intr(int irq, void *data)
3280 {
3281 	struct ixgbe_adapter *adapter = data;
3282 	struct ixgbe_hw *hw = &adapter->hw;
3283 	struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3284 	u32 eicr;
3285 
3286 	/*
3287 	 * Workaround for silicon errata #26 on 82598.  Mask the interrupt
3288 	 * before the read of EICR.
3289 	 */
3290 	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3291 
3292 	/* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
3293 	 * therefore no explicit interrupt disable is necessary */
3294 	eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3295 	if (!eicr) {
3296 		/*
3297 		 * shared interrupt alert!
3298 		 * make sure interrupts are enabled because the read will
3299 		 * have disabled interrupts due to EIAM
3300 		 * finish the workaround of silicon errata on 82598.  Unmask
3301 		 * the interrupt that we masked before the EICR read.
3302 		 */
3303 		if (!test_bit(__IXGBE_DOWN, &adapter->state))
3304 			ixgbe_irq_enable(adapter, true, true);
3305 		return IRQ_NONE;	/* Not our interrupt */
3306 	}
3307 
3308 	if (eicr & IXGBE_EICR_LSC)
3309 		ixgbe_check_lsc(adapter);
3310 
3311 	switch (hw->mac.type) {
3312 	case ixgbe_mac_82599EB:
3313 		ixgbe_check_sfp_event(adapter, eicr);
3314 		/* Fall through */
3315 	case ixgbe_mac_X540:
3316 	case ixgbe_mac_X550:
3317 	case ixgbe_mac_X550EM_x:
3318 	case ixgbe_mac_x550em_a:
3319 		if (eicr & IXGBE_EICR_ECC) {
3320 			e_info(link, "Received ECC Err, initiating reset\n");
3321 			set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3322 			ixgbe_service_event_schedule(adapter);
3323 			IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3324 		}
3325 		ixgbe_check_overtemp_event(adapter, eicr);
3326 		break;
3327 	default:
3328 		break;
3329 	}
3330 
3331 	ixgbe_check_fan_failure(adapter, eicr);
3332 	if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3333 		ixgbe_ptp_check_pps_event(adapter);
3334 
3335 	/* would disable interrupts here but EIAM disabled it */
3336 	napi_schedule_irqoff(&q_vector->napi);
3337 
3338 	/*
3339 	 * re-enable link(maybe) and non-queue interrupts, no flush.
3340 	 * ixgbe_poll will re-enable the queue interrupts
3341 	 */
3342 	if (!test_bit(__IXGBE_DOWN, &adapter->state))
3343 		ixgbe_irq_enable(adapter, false, false);
3344 
3345 	return IRQ_HANDLED;
3346 }
3347 
3348 /**
3349  * ixgbe_request_irq - initialize interrupts
3350  * @adapter: board private structure
3351  *
3352  * Attempts to configure interrupts using the best available
3353  * capabilities of the hardware and kernel.
3354  **/
3355 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3356 {
3357 	struct net_device *netdev = adapter->netdev;
3358 	int err;
3359 
3360 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3361 		err = ixgbe_request_msix_irqs(adapter);
3362 	else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3363 		err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3364 				  netdev->name, adapter);
3365 	else
3366 		err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3367 				  netdev->name, adapter);
3368 
3369 	if (err)
3370 		e_err(probe, "request_irq failed, Error %d\n", err);
3371 
3372 	return err;
3373 }
3374 
3375 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3376 {
3377 	int vector;
3378 
3379 	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3380 		free_irq(adapter->pdev->irq, adapter);
3381 		return;
3382 	}
3383 
3384 	if (!adapter->msix_entries)
3385 		return;
3386 
3387 	for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3388 		struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3389 		struct msix_entry *entry = &adapter->msix_entries[vector];
3390 
3391 		/* free only the irqs that were actually requested */
3392 		if (!q_vector->rx.ring && !q_vector->tx.ring)
3393 			continue;
3394 
3395 		/* clear the affinity_mask in the IRQ descriptor */
3396 		irq_set_affinity_hint(entry->vector, NULL);
3397 
3398 		free_irq(entry->vector, q_vector);
3399 	}
3400 
3401 	free_irq(adapter->msix_entries[vector].vector, adapter);
3402 }
3403 
3404 /**
3405  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3406  * @adapter: board private structure
3407  **/
3408 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3409 {
3410 	switch (adapter->hw.mac.type) {
3411 	case ixgbe_mac_82598EB:
3412 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3413 		break;
3414 	case ixgbe_mac_82599EB:
3415 	case ixgbe_mac_X540:
3416 	case ixgbe_mac_X550:
3417 	case ixgbe_mac_X550EM_x:
3418 	case ixgbe_mac_x550em_a:
3419 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3420 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3421 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3422 		break;
3423 	default:
3424 		break;
3425 	}
3426 	IXGBE_WRITE_FLUSH(&adapter->hw);
3427 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3428 		int vector;
3429 
3430 		for (vector = 0; vector < adapter->num_q_vectors; vector++)
3431 			synchronize_irq(adapter->msix_entries[vector].vector);
3432 
3433 		synchronize_irq(adapter->msix_entries[vector++].vector);
3434 	} else {
3435 		synchronize_irq(adapter->pdev->irq);
3436 	}
3437 }
3438 
3439 /**
3440  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3441  * @adapter: board private structure
3442  *
3443  **/
3444 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3445 {
3446 	struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3447 
3448 	ixgbe_write_eitr(q_vector);
3449 
3450 	ixgbe_set_ivar(adapter, 0, 0, 0);
3451 	ixgbe_set_ivar(adapter, 1, 0, 0);
3452 
3453 	e_info(hw, "Legacy interrupt IVAR setup done\n");
3454 }
3455 
3456 /**
3457  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3458  * @adapter: board private structure
3459  * @ring: structure containing ring specific data
3460  *
3461  * Configure the Tx descriptor ring after a reset.
3462  **/
3463 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3464 			     struct ixgbe_ring *ring)
3465 {
3466 	struct ixgbe_hw *hw = &adapter->hw;
3467 	u64 tdba = ring->dma;
3468 	int wait_loop = 10;
3469 	u32 txdctl = IXGBE_TXDCTL_ENABLE;
3470 	u8 reg_idx = ring->reg_idx;
3471 
3472 	/* disable queue to avoid issues while updating state */
3473 	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3474 	IXGBE_WRITE_FLUSH(hw);
3475 
3476 	IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3477 			(tdba & DMA_BIT_MASK(32)));
3478 	IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3479 	IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3480 			ring->count * sizeof(union ixgbe_adv_tx_desc));
3481 	IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3482 	IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3483 	ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3484 
3485 	/*
3486 	 * set WTHRESH to encourage burst writeback, it should not be set
3487 	 * higher than 1 when:
3488 	 * - ITR is 0 as it could cause false TX hangs
3489 	 * - ITR is set to > 100k int/sec and BQL is enabled
3490 	 *
3491 	 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3492 	 * to or less than the number of on chip descriptors, which is
3493 	 * currently 40.
3494 	 */
3495 	if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3496 		txdctl |= 1u << 16;	/* WTHRESH = 1 */
3497 	else
3498 		txdctl |= 8u << 16;	/* WTHRESH = 8 */
3499 
3500 	/*
3501 	 * Setting PTHRESH to 32 both improves performance
3502 	 * and avoids a TX hang with DFP enabled
3503 	 */
3504 	txdctl |= (1u << 8) |	/* HTHRESH = 1 */
3505 		   32;		/* PTHRESH = 32 */
3506 
3507 	/* reinitialize flowdirector state */
3508 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3509 		ring->atr_sample_rate = adapter->atr_sample_rate;
3510 		ring->atr_count = 0;
3511 		set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3512 	} else {
3513 		ring->atr_sample_rate = 0;
3514 	}
3515 
3516 	/* initialize XPS */
3517 	if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3518 		struct ixgbe_q_vector *q_vector = ring->q_vector;
3519 
3520 		if (q_vector)
3521 			netif_set_xps_queue(ring->netdev,
3522 					    &q_vector->affinity_mask,
3523 					    ring->queue_index);
3524 	}
3525 
3526 	clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3527 
3528 	/* reinitialize tx_buffer_info */
3529 	memset(ring->tx_buffer_info, 0,
3530 	       sizeof(struct ixgbe_tx_buffer) * ring->count);
3531 
3532 	/* enable queue */
3533 	IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3534 
3535 	/* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3536 	if (hw->mac.type == ixgbe_mac_82598EB &&
3537 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3538 		return;
3539 
3540 	/* poll to verify queue is enabled */
3541 	do {
3542 		usleep_range(1000, 2000);
3543 		txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3544 	} while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3545 	if (!wait_loop)
3546 		hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
3547 }
3548 
3549 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3550 {
3551 	struct ixgbe_hw *hw = &adapter->hw;
3552 	u32 rttdcs, mtqc;
3553 	u8 tcs = adapter->hw_tcs;
3554 
3555 	if (hw->mac.type == ixgbe_mac_82598EB)
3556 		return;
3557 
3558 	/* disable the arbiter while setting MTQC */
3559 	rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3560 	rttdcs |= IXGBE_RTTDCS_ARBDIS;
3561 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3562 
3563 	/* set transmit pool layout */
3564 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3565 		mtqc = IXGBE_MTQC_VT_ENA;
3566 		if (tcs > 4)
3567 			mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3568 		else if (tcs > 1)
3569 			mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3570 		else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3571 			 IXGBE_82599_VMDQ_4Q_MASK)
3572 			mtqc |= IXGBE_MTQC_32VF;
3573 		else
3574 			mtqc |= IXGBE_MTQC_64VF;
3575 	} else {
3576 		if (tcs > 4)
3577 			mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3578 		else if (tcs > 1)
3579 			mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3580 		else
3581 			mtqc = IXGBE_MTQC_64Q_1PB;
3582 	}
3583 
3584 	IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3585 
3586 	/* Enable Security TX Buffer IFG for multiple pb */
3587 	if (tcs) {
3588 		u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3589 		sectx |= IXGBE_SECTX_DCB;
3590 		IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3591 	}
3592 
3593 	/* re-enable the arbiter */
3594 	rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3595 	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3596 }
3597 
3598 /**
3599  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3600  * @adapter: board private structure
3601  *
3602  * Configure the Tx unit of the MAC after a reset.
3603  **/
3604 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3605 {
3606 	struct ixgbe_hw *hw = &adapter->hw;
3607 	u32 dmatxctl;
3608 	u32 i;
3609 
3610 	ixgbe_setup_mtqc(adapter);
3611 
3612 	if (hw->mac.type != ixgbe_mac_82598EB) {
3613 		/* DMATXCTL.EN must be before Tx queues are enabled */
3614 		dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3615 		dmatxctl |= IXGBE_DMATXCTL_TE;
3616 		IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3617 	}
3618 
3619 	/* Setup the HW Tx Head and Tail descriptor pointers */
3620 	for (i = 0; i < adapter->num_tx_queues; i++)
3621 		ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3622 	for (i = 0; i < adapter->num_xdp_queues; i++)
3623 		ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
3624 }
3625 
3626 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3627 				 struct ixgbe_ring *ring)
3628 {
3629 	struct ixgbe_hw *hw = &adapter->hw;
3630 	u8 reg_idx = ring->reg_idx;
3631 	u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3632 
3633 	srrctl |= IXGBE_SRRCTL_DROP_EN;
3634 
3635 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3636 }
3637 
3638 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3639 				  struct ixgbe_ring *ring)
3640 {
3641 	struct ixgbe_hw *hw = &adapter->hw;
3642 	u8 reg_idx = ring->reg_idx;
3643 	u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3644 
3645 	srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3646 
3647 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3648 }
3649 
3650 #ifdef CONFIG_IXGBE_DCB
3651 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3652 #else
3653 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3654 #endif
3655 {
3656 	int i;
3657 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3658 
3659 	if (adapter->ixgbe_ieee_pfc)
3660 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3661 
3662 	/*
3663 	 * We should set the drop enable bit if:
3664 	 *  SR-IOV is enabled
3665 	 *   or
3666 	 *  Number of Rx queues > 1 and flow control is disabled
3667 	 *
3668 	 *  This allows us to avoid head of line blocking for security
3669 	 *  and performance reasons.
3670 	 */
3671 	if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3672 	    !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3673 		for (i = 0; i < adapter->num_rx_queues; i++)
3674 			ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3675 	} else {
3676 		for (i = 0; i < adapter->num_rx_queues; i++)
3677 			ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3678 	}
3679 }
3680 
3681 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3682 
3683 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3684 				   struct ixgbe_ring *rx_ring)
3685 {
3686 	struct ixgbe_hw *hw = &adapter->hw;
3687 	u32 srrctl;
3688 	u8 reg_idx = rx_ring->reg_idx;
3689 
3690 	if (hw->mac.type == ixgbe_mac_82598EB) {
3691 		u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3692 
3693 		/*
3694 		 * if VMDq is not active we must program one srrctl register
3695 		 * per RSS queue since we have enabled RDRXCTL.MVMEN
3696 		 */
3697 		reg_idx &= mask;
3698 	}
3699 
3700 	/* configure header buffer length, needed for RSC */
3701 	srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3702 
3703 	/* configure the packet buffer length */
3704 	if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state))
3705 		srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3706 	else
3707 		srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3708 
3709 	/* configure descriptor type */
3710 	srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3711 
3712 	IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3713 }
3714 
3715 /**
3716  * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3717  * @adapter: device handle
3718  *
3719  *  - 82598/82599/X540:     128
3720  *  - X550(non-SRIOV mode): 512
3721  *  - X550(SRIOV mode):     64
3722  */
3723 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3724 {
3725 	if (adapter->hw.mac.type < ixgbe_mac_X550)
3726 		return 128;
3727 	else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3728 		return 64;
3729 	else
3730 		return 512;
3731 }
3732 
3733 /**
3734  * ixgbe_store_key - Write the RSS key to HW
3735  * @adapter: device handle
3736  *
3737  * Write the RSS key stored in adapter.rss_key to HW.
3738  */
3739 void ixgbe_store_key(struct ixgbe_adapter *adapter)
3740 {
3741 	struct ixgbe_hw *hw = &adapter->hw;
3742 	int i;
3743 
3744 	for (i = 0; i < 10; i++)
3745 		IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3746 }
3747 
3748 /**
3749  * ixgbe_init_rss_key - Initialize adapter RSS key
3750  * @adapter: device handle
3751  *
3752  * Allocates and initializes the RSS key if it is not allocated.
3753  **/
3754 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3755 {
3756 	u32 *rss_key;
3757 
3758 	if (!adapter->rss_key) {
3759 		rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3760 		if (unlikely(!rss_key))
3761 			return -ENOMEM;
3762 
3763 		netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3764 		adapter->rss_key = rss_key;
3765 	}
3766 
3767 	return 0;
3768 }
3769 
3770 /**
3771  * ixgbe_store_reta - Write the RETA table to HW
3772  * @adapter: device handle
3773  *
3774  * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3775  */
3776 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3777 {
3778 	u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3779 	struct ixgbe_hw *hw = &adapter->hw;
3780 	u32 reta = 0;
3781 	u32 indices_multi;
3782 	u8 *indir_tbl = adapter->rss_indir_tbl;
3783 
3784 	/* Fill out the redirection table as follows:
3785 	 *  - 82598:      8 bit wide entries containing pair of 4 bit RSS
3786 	 *    indices.
3787 	 *  - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3788 	 *  - X550:       8 bit wide entries containing 6 bit RSS index
3789 	 */
3790 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3791 		indices_multi = 0x11;
3792 	else
3793 		indices_multi = 0x1;
3794 
3795 	/* Write redirection table to HW */
3796 	for (i = 0; i < reta_entries; i++) {
3797 		reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3798 		if ((i & 3) == 3) {
3799 			if (i < 128)
3800 				IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3801 			else
3802 				IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3803 						reta);
3804 			reta = 0;
3805 		}
3806 	}
3807 }
3808 
3809 /**
3810  * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3811  * @adapter: device handle
3812  *
3813  * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3814  */
3815 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3816 {
3817 	u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3818 	struct ixgbe_hw *hw = &adapter->hw;
3819 	u32 vfreta = 0;
3820 
3821 	/* Write redirection table to HW */
3822 	for (i = 0; i < reta_entries; i++) {
3823 		u16 pool = adapter->num_rx_pools;
3824 
3825 		vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3826 		if ((i & 3) != 3)
3827 			continue;
3828 
3829 		while (pool--)
3830 			IXGBE_WRITE_REG(hw,
3831 					IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
3832 					vfreta);
3833 		vfreta = 0;
3834 	}
3835 }
3836 
3837 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3838 {
3839 	u32 i, j;
3840 	u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3841 	u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3842 
3843 	/* Program table for at least 4 queues w/ SR-IOV so that VFs can
3844 	 * make full use of any rings they may have.  We will use the
3845 	 * PSRTYPE register to control how many rings we use within the PF.
3846 	 */
3847 	if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3848 		rss_i = 4;
3849 
3850 	/* Fill out hash function seeds */
3851 	ixgbe_store_key(adapter);
3852 
3853 	/* Fill out redirection table */
3854 	memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3855 
3856 	for (i = 0, j = 0; i < reta_entries; i++, j++) {
3857 		if (j == rss_i)
3858 			j = 0;
3859 
3860 		adapter->rss_indir_tbl[i] = j;
3861 	}
3862 
3863 	ixgbe_store_reta(adapter);
3864 }
3865 
3866 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3867 {
3868 	struct ixgbe_hw *hw = &adapter->hw;
3869 	u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3870 	int i, j;
3871 
3872 	/* Fill out hash function seeds */
3873 	for (i = 0; i < 10; i++) {
3874 		u16 pool = adapter->num_rx_pools;
3875 
3876 		while (pool--)
3877 			IXGBE_WRITE_REG(hw,
3878 					IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3879 					*(adapter->rss_key + i));
3880 	}
3881 
3882 	/* Fill out the redirection table */
3883 	for (i = 0, j = 0; i < 64; i++, j++) {
3884 		if (j == rss_i)
3885 			j = 0;
3886 
3887 		adapter->rss_indir_tbl[i] = j;
3888 	}
3889 
3890 	ixgbe_store_vfreta(adapter);
3891 }
3892 
3893 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3894 {
3895 	struct ixgbe_hw *hw = &adapter->hw;
3896 	u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3897 	u32 rxcsum;
3898 
3899 	/* Disable indicating checksum in descriptor, enables RSS hash */
3900 	rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3901 	rxcsum |= IXGBE_RXCSUM_PCSD;
3902 	IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3903 
3904 	if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3905 		if (adapter->ring_feature[RING_F_RSS].mask)
3906 			mrqc = IXGBE_MRQC_RSSEN;
3907 	} else {
3908 		u8 tcs = adapter->hw_tcs;
3909 
3910 		if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3911 			if (tcs > 4)
3912 				mrqc = IXGBE_MRQC_VMDQRT8TCEN;	/* 8 TCs */
3913 			else if (tcs > 1)
3914 				mrqc = IXGBE_MRQC_VMDQRT4TCEN;	/* 4 TCs */
3915 			else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3916 				 IXGBE_82599_VMDQ_4Q_MASK)
3917 				mrqc = IXGBE_MRQC_VMDQRSS32EN;
3918 			else
3919 				mrqc = IXGBE_MRQC_VMDQRSS64EN;
3920 
3921 			/* Enable L3/L4 for Tx Switched packets */
3922 			mrqc |= IXGBE_MRQC_L3L4TXSWEN;
3923 		} else {
3924 			if (tcs > 4)
3925 				mrqc = IXGBE_MRQC_RTRSS8TCEN;
3926 			else if (tcs > 1)
3927 				mrqc = IXGBE_MRQC_RTRSS4TCEN;
3928 			else
3929 				mrqc = IXGBE_MRQC_RSSEN;
3930 		}
3931 	}
3932 
3933 	/* Perform hash on these packet types */
3934 	rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3935 		     IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3936 		     IXGBE_MRQC_RSS_FIELD_IPV6 |
3937 		     IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3938 
3939 	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3940 		rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3941 	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3942 		rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3943 
3944 	if ((hw->mac.type >= ixgbe_mac_X550) &&
3945 	    (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3946 		u16 pool = adapter->num_rx_pools;
3947 
3948 		/* Enable VF RSS mode */
3949 		mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3950 		IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3951 
3952 		/* Setup RSS through the VF registers */
3953 		ixgbe_setup_vfreta(adapter);
3954 		vfmrqc = IXGBE_MRQC_RSSEN;
3955 		vfmrqc |= rss_field;
3956 
3957 		while (pool--)
3958 			IXGBE_WRITE_REG(hw,
3959 					IXGBE_PFVFMRQC(VMDQ_P(pool)),
3960 					vfmrqc);
3961 	} else {
3962 		ixgbe_setup_reta(adapter);
3963 		mrqc |= rss_field;
3964 		IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3965 	}
3966 }
3967 
3968 /**
3969  * ixgbe_configure_rscctl - enable RSC for the indicated ring
3970  * @adapter: address of board private structure
3971  * @ring: structure containing ring specific data
3972  **/
3973 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3974 				   struct ixgbe_ring *ring)
3975 {
3976 	struct ixgbe_hw *hw = &adapter->hw;
3977 	u32 rscctrl;
3978 	u8 reg_idx = ring->reg_idx;
3979 
3980 	if (!ring_is_rsc_enabled(ring))
3981 		return;
3982 
3983 	rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3984 	rscctrl |= IXGBE_RSCCTL_RSCEN;
3985 	/*
3986 	 * we must limit the number of descriptors so that the
3987 	 * total size of max desc * buf_len is not greater
3988 	 * than 65536
3989 	 */
3990 	rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3991 	IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3992 }
3993 
3994 #define IXGBE_MAX_RX_DESC_POLL 10
3995 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3996 				       struct ixgbe_ring *ring)
3997 {
3998 	struct ixgbe_hw *hw = &adapter->hw;
3999 	int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4000 	u32 rxdctl;
4001 	u8 reg_idx = ring->reg_idx;
4002 
4003 	if (ixgbe_removed(hw->hw_addr))
4004 		return;
4005 	/* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4006 	if (hw->mac.type == ixgbe_mac_82598EB &&
4007 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4008 		return;
4009 
4010 	do {
4011 		usleep_range(1000, 2000);
4012 		rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4013 	} while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4014 
4015 	if (!wait_loop) {
4016 		e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4017 		      "the polling period\n", reg_idx);
4018 	}
4019 }
4020 
4021 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
4022 			    struct ixgbe_ring *ring)
4023 {
4024 	struct ixgbe_hw *hw = &adapter->hw;
4025 	int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4026 	u32 rxdctl;
4027 	u8 reg_idx = ring->reg_idx;
4028 
4029 	if (ixgbe_removed(hw->hw_addr))
4030 		return;
4031 	rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4032 	rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4033 
4034 	/* write value back with RXDCTL.ENABLE bit cleared */
4035 	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4036 
4037 	if (hw->mac.type == ixgbe_mac_82598EB &&
4038 	    !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4039 		return;
4040 
4041 	/* the hardware may take up to 100us to really disable the rx queue */
4042 	do {
4043 		udelay(10);
4044 		rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4045 	} while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
4046 
4047 	if (!wait_loop) {
4048 		e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
4049 		      "the polling period\n", reg_idx);
4050 	}
4051 }
4052 
4053 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4054 			     struct ixgbe_ring *ring)
4055 {
4056 	struct ixgbe_hw *hw = &adapter->hw;
4057 	union ixgbe_adv_rx_desc *rx_desc;
4058 	u64 rdba = ring->dma;
4059 	u32 rxdctl;
4060 	u8 reg_idx = ring->reg_idx;
4061 
4062 	/* disable queue to avoid issues while updating state */
4063 	rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4064 	ixgbe_disable_rx_queue(adapter, ring);
4065 
4066 	IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4067 	IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4068 	IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4069 			ring->count * sizeof(union ixgbe_adv_rx_desc));
4070 	/* Force flushing of IXGBE_RDLEN to prevent MDD */
4071 	IXGBE_WRITE_FLUSH(hw);
4072 
4073 	IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4074 	IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
4075 	ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
4076 
4077 	ixgbe_configure_srrctl(adapter, ring);
4078 	ixgbe_configure_rscctl(adapter, ring);
4079 
4080 	if (hw->mac.type == ixgbe_mac_82598EB) {
4081 		/*
4082 		 * enable cache line friendly hardware writes:
4083 		 * PTHRESH=32 descriptors (half the internal cache),
4084 		 * this also removes ugly rx_no_buffer_count increment
4085 		 * HTHRESH=4 descriptors (to minimize latency on fetch)
4086 		 * WTHRESH=8 burst writeback up to two cache lines
4087 		 */
4088 		rxdctl &= ~0x3FFFFF;
4089 		rxdctl |=  0x080420;
4090 #if (PAGE_SIZE < 8192)
4091 	/* RXDCTL.RLPML does not work on 82599 */
4092 	} else if (hw->mac.type != ixgbe_mac_82599EB) {
4093 		rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4094 			    IXGBE_RXDCTL_RLPML_EN);
4095 
4096 		/* Limit the maximum frame size so we don't overrun the skb.
4097 		 * This can happen in SRIOV mode when the MTU of the VF is
4098 		 * higher than the MTU of the PF.
4099 		 */
4100 		if (ring_uses_build_skb(ring) &&
4101 		    !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
4102 			rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
4103 				  IXGBE_RXDCTL_RLPML_EN;
4104 #endif
4105 	}
4106 
4107 	/* initialize rx_buffer_info */
4108 	memset(ring->rx_buffer_info, 0,
4109 	       sizeof(struct ixgbe_rx_buffer) * ring->count);
4110 
4111 	/* initialize Rx descriptor 0 */
4112 	rx_desc = IXGBE_RX_DESC(ring, 0);
4113 	rx_desc->wb.upper.length = 0;
4114 
4115 	/* enable receive descriptor ring */
4116 	rxdctl |= IXGBE_RXDCTL_ENABLE;
4117 	IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4118 
4119 	ixgbe_rx_desc_queue_enable(adapter, ring);
4120 	ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
4121 }
4122 
4123 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4124 {
4125 	struct ixgbe_hw *hw = &adapter->hw;
4126 	int rss_i = adapter->ring_feature[RING_F_RSS].indices;
4127 	u16 pool = adapter->num_rx_pools;
4128 
4129 	/* PSRTYPE must be initialized in non 82598 adapters */
4130 	u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4131 		      IXGBE_PSRTYPE_UDPHDR |
4132 		      IXGBE_PSRTYPE_IPV4HDR |
4133 		      IXGBE_PSRTYPE_L2HDR |
4134 		      IXGBE_PSRTYPE_IPV6HDR;
4135 
4136 	if (hw->mac.type == ixgbe_mac_82598EB)
4137 		return;
4138 
4139 	if (rss_i > 3)
4140 		psrtype |= 2u << 29;
4141 	else if (rss_i > 1)
4142 		psrtype |= 1u << 29;
4143 
4144 	while (pool--)
4145 		IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4146 }
4147 
4148 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4149 {
4150 	struct ixgbe_hw *hw = &adapter->hw;
4151 	u16 pool = adapter->num_rx_pools;
4152 	u32 reg_offset, vf_shift, vmolr;
4153 	u32 gcr_ext, vmdctl;
4154 	int i;
4155 
4156 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4157 		return;
4158 
4159 	vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4160 	vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4161 	vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
4162 	vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
4163 	vmdctl |= IXGBE_VT_CTL_REPLEN;
4164 	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
4165 
4166 	/* accept untagged packets until a vlan tag is
4167 	 * specifically set for the VMDQ queue/pool
4168 	 */
4169 	vmolr = IXGBE_VMOLR_AUPE;
4170 	while (pool--)
4171 		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4172 
4173 	vf_shift = VMDQ_P(0) % 32;
4174 	reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4175 
4176 	/* Enable only the PF's pool for Tx/Rx */
4177 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4178 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4179 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
4180 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
4181 	if (adapter->bridge_mode == BRIDGE_MODE_VEB)
4182 		IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4183 
4184 	/* Map PF MAC address in RAR Entry 0 to first pool following VFs */
4185 	hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
4186 
4187 	/* clear VLAN promisc flag so VFTA will be updated if necessary */
4188 	adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4189 
4190 	/*
4191 	 * Set up VF register offsets for selected VT Mode,
4192 	 * i.e. 32 or 64 VFs for SR-IOV
4193 	 */
4194 	switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4195 	case IXGBE_82599_VMDQ_8Q_MASK:
4196 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4197 		break;
4198 	case IXGBE_82599_VMDQ_4Q_MASK:
4199 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4200 		break;
4201 	default:
4202 		gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4203 		break;
4204 	}
4205 
4206 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4207 
4208 	for (i = 0; i < adapter->num_vfs; i++) {
4209 		/* configure spoof checking */
4210 		ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4211 					  adapter->vfinfo[i].spoofchk_enabled);
4212 
4213 		/* Enable/Disable RSS query feature  */
4214 		ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4215 					  adapter->vfinfo[i].rss_query_enabled);
4216 	}
4217 }
4218 
4219 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
4220 {
4221 	struct ixgbe_hw *hw = &adapter->hw;
4222 	struct net_device *netdev = adapter->netdev;
4223 	int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4224 	struct ixgbe_ring *rx_ring;
4225 	int i;
4226 	u32 mhadd, hlreg0;
4227 
4228 #ifdef IXGBE_FCOE
4229 	/* adjust max frame to be able to do baby jumbo for FCoE */
4230 	if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4231 	    (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4232 		max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4233 
4234 #endif /* IXGBE_FCOE */
4235 
4236 	/* adjust max frame to be at least the size of a standard frame */
4237 	if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4238 		max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4239 
4240 	mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4241 	if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4242 		mhadd &= ~IXGBE_MHADD_MFS_MASK;
4243 		mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4244 
4245 		IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4246 	}
4247 
4248 	hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4249 	/* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4250 	hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4251 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4252 
4253 	/*
4254 	 * Setup the HW Rx Head and Tail Descriptor Pointers and
4255 	 * the Base and Length of the Rx Descriptor Ring
4256 	 */
4257 	for (i = 0; i < adapter->num_rx_queues; i++) {
4258 		rx_ring = adapter->rx_ring[i];
4259 
4260 		clear_ring_rsc_enabled(rx_ring);
4261 		clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4262 		clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4263 
4264 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4265 			set_ring_rsc_enabled(rx_ring);
4266 
4267 		if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4268 			set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4269 
4270 		clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4271 		if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4272 			continue;
4273 
4274 		set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4275 
4276 #if (PAGE_SIZE < 8192)
4277 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4278 			set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4279 
4280 		if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4281 		    (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4282 			set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4283 #endif
4284 	}
4285 }
4286 
4287 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4288 {
4289 	struct ixgbe_hw *hw = &adapter->hw;
4290 	u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4291 
4292 	switch (hw->mac.type) {
4293 	case ixgbe_mac_82598EB:
4294 		/*
4295 		 * For VMDq support of different descriptor types or
4296 		 * buffer sizes through the use of multiple SRRCTL
4297 		 * registers, RDRXCTL.MVMEN must be set to 1
4298 		 *
4299 		 * also, the manual doesn't mention it clearly but DCA hints
4300 		 * will only use queue 0's tags unless this bit is set.  Side
4301 		 * effects of setting this bit are only that SRRCTL must be
4302 		 * fully programmed [0..15]
4303 		 */
4304 		rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4305 		break;
4306 	case ixgbe_mac_X550:
4307 	case ixgbe_mac_X550EM_x:
4308 	case ixgbe_mac_x550em_a:
4309 		if (adapter->num_vfs)
4310 			rdrxctl |= IXGBE_RDRXCTL_PSP;
4311 		/* fall through */
4312 	case ixgbe_mac_82599EB:
4313 	case ixgbe_mac_X540:
4314 		/* Disable RSC for ACK packets */
4315 		IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4316 		   (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4317 		rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4318 		/* hardware requires some bits to be set by default */
4319 		rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4320 		rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4321 		break;
4322 	default:
4323 		/* We should do nothing since we don't know this hardware */
4324 		return;
4325 	}
4326 
4327 	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4328 }
4329 
4330 /**
4331  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4332  * @adapter: board private structure
4333  *
4334  * Configure the Rx unit of the MAC after a reset.
4335  **/
4336 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4337 {
4338 	struct ixgbe_hw *hw = &adapter->hw;
4339 	int i;
4340 	u32 rxctrl, rfctl;
4341 
4342 	/* disable receives while setting up the descriptors */
4343 	hw->mac.ops.disable_rx(hw);
4344 
4345 	ixgbe_setup_psrtype(adapter);
4346 	ixgbe_setup_rdrxctl(adapter);
4347 
4348 	/* RSC Setup */
4349 	rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4350 	rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4351 	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4352 		rfctl |= IXGBE_RFCTL_RSC_DIS;
4353 
4354 	/* disable NFS filtering */
4355 	rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
4356 	IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4357 
4358 	/* Program registers for the distribution of queues */
4359 	ixgbe_setup_mrqc(adapter);
4360 
4361 	/* set_rx_buffer_len must be called before ring initialization */
4362 	ixgbe_set_rx_buffer_len(adapter);
4363 
4364 	/*
4365 	 * Setup the HW Rx Head and Tail Descriptor Pointers and
4366 	 * the Base and Length of the Rx Descriptor Ring
4367 	 */
4368 	for (i = 0; i < adapter->num_rx_queues; i++)
4369 		ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
4370 
4371 	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4372 	/* disable drop enable for 82598 parts */
4373 	if (hw->mac.type == ixgbe_mac_82598EB)
4374 		rxctrl |= IXGBE_RXCTRL_DMBYPS;
4375 
4376 	/* enable all receives */
4377 	rxctrl |= IXGBE_RXCTRL_RXEN;
4378 	hw->mac.ops.enable_rx_dma(hw, rxctrl);
4379 }
4380 
4381 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4382 				 __be16 proto, u16 vid)
4383 {
4384 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4385 	struct ixgbe_hw *hw = &adapter->hw;
4386 
4387 	/* add VID to filter table */
4388 	if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4389 		hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4390 
4391 	set_bit(vid, adapter->active_vlans);
4392 
4393 	return 0;
4394 }
4395 
4396 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4397 {
4398 	u32 vlvf;
4399 	int idx;
4400 
4401 	/* short cut the special case */
4402 	if (vlan == 0)
4403 		return 0;
4404 
4405 	/* Search for the vlan id in the VLVF entries */
4406 	for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4407 		vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4408 		if ((vlvf & VLAN_VID_MASK) == vlan)
4409 			break;
4410 	}
4411 
4412 	return idx;
4413 }
4414 
4415 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4416 {
4417 	struct ixgbe_hw *hw = &adapter->hw;
4418 	u32 bits, word;
4419 	int idx;
4420 
4421 	idx = ixgbe_find_vlvf_entry(hw, vid);
4422 	if (!idx)
4423 		return;
4424 
4425 	/* See if any other pools are set for this VLAN filter
4426 	 * entry other than the PF.
4427 	 */
4428 	word = idx * 2 + (VMDQ_P(0) / 32);
4429 	bits = ~BIT(VMDQ_P(0) % 32);
4430 	bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4431 
4432 	/* Disable the filter so this falls into the default pool. */
4433 	if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4434 		if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4435 			IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4436 		IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4437 	}
4438 }
4439 
4440 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4441 				  __be16 proto, u16 vid)
4442 {
4443 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4444 	struct ixgbe_hw *hw = &adapter->hw;
4445 
4446 	/* remove VID from filter table */
4447 	if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4448 		hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4449 
4450 	clear_bit(vid, adapter->active_vlans);
4451 
4452 	return 0;
4453 }
4454 
4455 /**
4456  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4457  * @adapter: driver data
4458  */
4459 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4460 {
4461 	struct ixgbe_hw *hw = &adapter->hw;
4462 	u32 vlnctrl;
4463 	int i, j;
4464 
4465 	switch (hw->mac.type) {
4466 	case ixgbe_mac_82598EB:
4467 		vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4468 		vlnctrl &= ~IXGBE_VLNCTRL_VME;
4469 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4470 		break;
4471 	case ixgbe_mac_82599EB:
4472 	case ixgbe_mac_X540:
4473 	case ixgbe_mac_X550:
4474 	case ixgbe_mac_X550EM_x:
4475 	case ixgbe_mac_x550em_a:
4476 		for (i = 0; i < adapter->num_rx_queues; i++) {
4477 			struct ixgbe_ring *ring = adapter->rx_ring[i];
4478 
4479 			if (!netif_is_ixgbe(ring->netdev))
4480 				continue;
4481 
4482 			j = ring->reg_idx;
4483 			vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4484 			vlnctrl &= ~IXGBE_RXDCTL_VME;
4485 			IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4486 		}
4487 		break;
4488 	default:
4489 		break;
4490 	}
4491 }
4492 
4493 /**
4494  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4495  * @adapter: driver data
4496  */
4497 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4498 {
4499 	struct ixgbe_hw *hw = &adapter->hw;
4500 	u32 vlnctrl;
4501 	int i, j;
4502 
4503 	switch (hw->mac.type) {
4504 	case ixgbe_mac_82598EB:
4505 		vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4506 		vlnctrl |= IXGBE_VLNCTRL_VME;
4507 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4508 		break;
4509 	case ixgbe_mac_82599EB:
4510 	case ixgbe_mac_X540:
4511 	case ixgbe_mac_X550:
4512 	case ixgbe_mac_X550EM_x:
4513 	case ixgbe_mac_x550em_a:
4514 		for (i = 0; i < adapter->num_rx_queues; i++) {
4515 			struct ixgbe_ring *ring = adapter->rx_ring[i];
4516 
4517 			if (!netif_is_ixgbe(ring->netdev))
4518 				continue;
4519 
4520 			j = ring->reg_idx;
4521 			vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4522 			vlnctrl |= IXGBE_RXDCTL_VME;
4523 			IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4524 		}
4525 		break;
4526 	default:
4527 		break;
4528 	}
4529 }
4530 
4531 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4532 {
4533 	struct ixgbe_hw *hw = &adapter->hw;
4534 	u32 vlnctrl, i;
4535 
4536 	vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4537 
4538 	if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4539 	/* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4540 		vlnctrl |= IXGBE_VLNCTRL_VFE;
4541 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4542 	} else {
4543 		vlnctrl &= ~IXGBE_VLNCTRL_VFE;
4544 		IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4545 		return;
4546 	}
4547 
4548 	/* Nothing to do for 82598 */
4549 	if (hw->mac.type == ixgbe_mac_82598EB)
4550 		return;
4551 
4552 	/* We are already in VLAN promisc, nothing to do */
4553 	if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4554 		return;
4555 
4556 	/* Set flag so we don't redo unnecessary work */
4557 	adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4558 
4559 	/* Add PF to all active pools */
4560 	for (i = IXGBE_VLVF_ENTRIES; --i;) {
4561 		u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4562 		u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4563 
4564 		vlvfb |= BIT(VMDQ_P(0) % 32);
4565 		IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4566 	}
4567 
4568 	/* Set all bits in the VLAN filter table array */
4569 	for (i = hw->mac.vft_size; i--;)
4570 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4571 }
4572 
4573 #define VFTA_BLOCK_SIZE 8
4574 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4575 {
4576 	struct ixgbe_hw *hw = &adapter->hw;
4577 	u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4578 	u32 vid_start = vfta_offset * 32;
4579 	u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4580 	u32 i, vid, word, bits;
4581 
4582 	for (i = IXGBE_VLVF_ENTRIES; --i;) {
4583 		u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4584 
4585 		/* pull VLAN ID from VLVF */
4586 		vid = vlvf & VLAN_VID_MASK;
4587 
4588 		/* only concern outselves with a certain range */
4589 		if (vid < vid_start || vid >= vid_end)
4590 			continue;
4591 
4592 		if (vlvf) {
4593 			/* record VLAN ID in VFTA */
4594 			vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4595 
4596 			/* if PF is part of this then continue */
4597 			if (test_bit(vid, adapter->active_vlans))
4598 				continue;
4599 		}
4600 
4601 		/* remove PF from the pool */
4602 		word = i * 2 + VMDQ_P(0) / 32;
4603 		bits = ~BIT(VMDQ_P(0) % 32);
4604 		bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4605 		IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4606 	}
4607 
4608 	/* extract values from active_vlans and write back to VFTA */
4609 	for (i = VFTA_BLOCK_SIZE; i--;) {
4610 		vid = (vfta_offset + i) * 32;
4611 		word = vid / BITS_PER_LONG;
4612 		bits = vid % BITS_PER_LONG;
4613 
4614 		vfta[i] |= adapter->active_vlans[word] >> bits;
4615 
4616 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4617 	}
4618 }
4619 
4620 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4621 {
4622 	struct ixgbe_hw *hw = &adapter->hw;
4623 	u32 vlnctrl, i;
4624 
4625 	/* Set VLAN filtering to enabled */
4626 	vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4627 	vlnctrl |= IXGBE_VLNCTRL_VFE;
4628 	IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4629 
4630 	if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4631 	    hw->mac.type == ixgbe_mac_82598EB)
4632 		return;
4633 
4634 	/* We are not in VLAN promisc, nothing to do */
4635 	if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4636 		return;
4637 
4638 	/* Set flag so we don't redo unnecessary work */
4639 	adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4640 
4641 	for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4642 		ixgbe_scrub_vfta(adapter, i);
4643 }
4644 
4645 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4646 {
4647 	u16 vid = 1;
4648 
4649 	ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4650 
4651 	for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4652 		ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4653 }
4654 
4655 /**
4656  * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4657  * @netdev: network interface device structure
4658  *
4659  * Writes multicast address list to the MTA hash table.
4660  * Returns: -ENOMEM on failure
4661  *                0 on no addresses written
4662  *                X on writing X addresses to MTA
4663  **/
4664 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4665 {
4666 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4667 	struct ixgbe_hw *hw = &adapter->hw;
4668 
4669 	if (!netif_running(netdev))
4670 		return 0;
4671 
4672 	if (hw->mac.ops.update_mc_addr_list)
4673 		hw->mac.ops.update_mc_addr_list(hw, netdev);
4674 	else
4675 		return -ENOMEM;
4676 
4677 #ifdef CONFIG_PCI_IOV
4678 	ixgbe_restore_vf_multicasts(adapter);
4679 #endif
4680 
4681 	return netdev_mc_count(netdev);
4682 }
4683 
4684 #ifdef CONFIG_PCI_IOV
4685 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4686 {
4687 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4688 	struct ixgbe_hw *hw = &adapter->hw;
4689 	int i;
4690 
4691 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4692 		mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4693 
4694 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4695 			hw->mac.ops.set_rar(hw, i,
4696 					    mac_table->addr,
4697 					    mac_table->pool,
4698 					    IXGBE_RAH_AV);
4699 		else
4700 			hw->mac.ops.clear_rar(hw, i);
4701 	}
4702 }
4703 
4704 #endif
4705 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4706 {
4707 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4708 	struct ixgbe_hw *hw = &adapter->hw;
4709 	int i;
4710 
4711 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4712 		if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4713 			continue;
4714 
4715 		mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4716 
4717 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4718 			hw->mac.ops.set_rar(hw, i,
4719 					    mac_table->addr,
4720 					    mac_table->pool,
4721 					    IXGBE_RAH_AV);
4722 		else
4723 			hw->mac.ops.clear_rar(hw, i);
4724 	}
4725 }
4726 
4727 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4728 {
4729 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4730 	struct ixgbe_hw *hw = &adapter->hw;
4731 	int i;
4732 
4733 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4734 		mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4735 		mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4736 	}
4737 
4738 	ixgbe_sync_mac_table(adapter);
4739 }
4740 
4741 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4742 {
4743 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4744 	struct ixgbe_hw *hw = &adapter->hw;
4745 	int i, count = 0;
4746 
4747 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4748 		/* do not count default RAR as available */
4749 		if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4750 			continue;
4751 
4752 		/* only count unused and addresses that belong to us */
4753 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4754 			if (mac_table->pool != pool)
4755 				continue;
4756 		}
4757 
4758 		count++;
4759 	}
4760 
4761 	return count;
4762 }
4763 
4764 /* this function destroys the first RAR entry */
4765 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4766 {
4767 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4768 	struct ixgbe_hw *hw = &adapter->hw;
4769 
4770 	memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4771 	mac_table->pool = VMDQ_P(0);
4772 
4773 	mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4774 
4775 	hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4776 			    IXGBE_RAH_AV);
4777 }
4778 
4779 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4780 			 const u8 *addr, u16 pool)
4781 {
4782 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4783 	struct ixgbe_hw *hw = &adapter->hw;
4784 	int i;
4785 
4786 	if (is_zero_ether_addr(addr))
4787 		return -EINVAL;
4788 
4789 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4790 		if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4791 			continue;
4792 
4793 		ether_addr_copy(mac_table->addr, addr);
4794 		mac_table->pool = pool;
4795 
4796 		mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4797 				    IXGBE_MAC_STATE_IN_USE;
4798 
4799 		ixgbe_sync_mac_table(adapter);
4800 
4801 		return i;
4802 	}
4803 
4804 	return -ENOMEM;
4805 }
4806 
4807 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4808 			 const u8 *addr, u16 pool)
4809 {
4810 	struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4811 	struct ixgbe_hw *hw = &adapter->hw;
4812 	int i;
4813 
4814 	if (is_zero_ether_addr(addr))
4815 		return -EINVAL;
4816 
4817 	/* search table for addr, if found clear IN_USE flag and sync */
4818 	for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4819 		/* we can only delete an entry if it is in use */
4820 		if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4821 			continue;
4822 		/* we only care about entries that belong to the given pool */
4823 		if (mac_table->pool != pool)
4824 			continue;
4825 		/* we only care about a specific MAC address */
4826 		if (!ether_addr_equal(addr, mac_table->addr))
4827 			continue;
4828 
4829 		mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4830 		mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4831 
4832 		ixgbe_sync_mac_table(adapter);
4833 
4834 		return 0;
4835 	}
4836 
4837 	return -ENOMEM;
4838 }
4839 
4840 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4841 {
4842 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4843 	int ret;
4844 
4845 	ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4846 
4847 	return min_t(int, ret, 0);
4848 }
4849 
4850 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4851 {
4852 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4853 
4854 	ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4855 
4856 	return 0;
4857 }
4858 
4859 /**
4860  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4861  * @netdev: network interface device structure
4862  *
4863  * The set_rx_method entry point is called whenever the unicast/multicast
4864  * address list or the network interface flags are updated.  This routine is
4865  * responsible for configuring the hardware for proper unicast, multicast and
4866  * promiscuous mode.
4867  **/
4868 void ixgbe_set_rx_mode(struct net_device *netdev)
4869 {
4870 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
4871 	struct ixgbe_hw *hw = &adapter->hw;
4872 	u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4873 	netdev_features_t features = netdev->features;
4874 	int count;
4875 
4876 	/* Check for Promiscuous and All Multicast modes */
4877 	fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4878 
4879 	/* set all bits that we expect to always be set */
4880 	fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4881 	fctrl |= IXGBE_FCTRL_BAM;
4882 	fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4883 	fctrl |= IXGBE_FCTRL_PMCF;
4884 
4885 	/* clear the bits we are changing the status of */
4886 	fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4887 	if (netdev->flags & IFF_PROMISC) {
4888 		hw->addr_ctrl.user_set_promisc = true;
4889 		fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4890 		vmolr |= IXGBE_VMOLR_MPE;
4891 		features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4892 	} else {
4893 		if (netdev->flags & IFF_ALLMULTI) {
4894 			fctrl |= IXGBE_FCTRL_MPE;
4895 			vmolr |= IXGBE_VMOLR_MPE;
4896 		}
4897 		hw->addr_ctrl.user_set_promisc = false;
4898 	}
4899 
4900 	/*
4901 	 * Write addresses to available RAR registers, if there is not
4902 	 * sufficient space to store all the addresses then enable
4903 	 * unicast promiscuous mode
4904 	 */
4905 	if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4906 		fctrl |= IXGBE_FCTRL_UPE;
4907 		vmolr |= IXGBE_VMOLR_ROPE;
4908 	}
4909 
4910 	/* Write addresses to the MTA, if the attempt fails
4911 	 * then we should just turn on promiscuous mode so
4912 	 * that we can at least receive multicast traffic
4913 	 */
4914 	count = ixgbe_write_mc_addr_list(netdev);
4915 	if (count < 0) {
4916 		fctrl |= IXGBE_FCTRL_MPE;
4917 		vmolr |= IXGBE_VMOLR_MPE;
4918 	} else if (count) {
4919 		vmolr |= IXGBE_VMOLR_ROMPE;
4920 	}
4921 
4922 	if (hw->mac.type != ixgbe_mac_82598EB) {
4923 		vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4924 			 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4925 			   IXGBE_VMOLR_ROPE);
4926 		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4927 	}
4928 
4929 	/* This is useful for sniffing bad packets. */
4930 	if (features & NETIF_F_RXALL) {
4931 		/* UPE and MPE will be handled by normal PROMISC logic
4932 		 * in e1000e_set_rx_mode */
4933 		fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4934 			  IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4935 			  IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4936 
4937 		fctrl &= ~(IXGBE_FCTRL_DPF);
4938 		/* NOTE:  VLAN filtering is disabled by setting PROMISC */
4939 	}
4940 
4941 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4942 
4943 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
4944 		ixgbe_vlan_strip_enable(adapter);
4945 	else
4946 		ixgbe_vlan_strip_disable(adapter);
4947 
4948 	if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4949 		ixgbe_vlan_promisc_disable(adapter);
4950 	else
4951 		ixgbe_vlan_promisc_enable(adapter);
4952 }
4953 
4954 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4955 {
4956 	int q_idx;
4957 
4958 	for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4959 		napi_enable(&adapter->q_vector[q_idx]->napi);
4960 }
4961 
4962 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4963 {
4964 	int q_idx;
4965 
4966 	for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
4967 		napi_disable(&adapter->q_vector[q_idx]->napi);
4968 }
4969 
4970 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask)
4971 {
4972 	struct ixgbe_hw *hw = &adapter->hw;
4973 	u32 vxlanctrl;
4974 
4975 	if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE |
4976 				IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)))
4977 		return;
4978 
4979 	vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask;
4980 	IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl);
4981 
4982 	if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK)
4983 		adapter->vxlan_port = 0;
4984 
4985 	if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK)
4986 		adapter->geneve_port = 0;
4987 }
4988 
4989 #ifdef CONFIG_IXGBE_DCB
4990 /**
4991  * ixgbe_configure_dcb - Configure DCB hardware
4992  * @adapter: ixgbe adapter struct
4993  *
4994  * This is called by the driver on open to configure the DCB hardware.
4995  * This is also called by the gennetlink interface when reconfiguring
4996  * the DCB state.
4997  */
4998 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4999 {
5000 	struct ixgbe_hw *hw = &adapter->hw;
5001 	int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5002 
5003 	if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
5004 		if (hw->mac.type == ixgbe_mac_82598EB)
5005 			netif_set_gso_max_size(adapter->netdev, 65536);
5006 		return;
5007 	}
5008 
5009 	if (hw->mac.type == ixgbe_mac_82598EB)
5010 		netif_set_gso_max_size(adapter->netdev, 32768);
5011 
5012 #ifdef IXGBE_FCOE
5013 	if (adapter->netdev->features & NETIF_F_FCOE_MTU)
5014 		max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
5015 #endif
5016 
5017 	/* reconfigure the hardware */
5018 	if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
5019 		ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5020 						DCB_TX_CONFIG);
5021 		ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5022 						DCB_RX_CONFIG);
5023 		ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
5024 	} else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5025 		ixgbe_dcb_hw_ets(&adapter->hw,
5026 				 adapter->ixgbe_ieee_ets,
5027 				 max_frame);
5028 		ixgbe_dcb_hw_pfc_config(&adapter->hw,
5029 					adapter->ixgbe_ieee_pfc->pfc_en,
5030 					adapter->ixgbe_ieee_ets->prio_tc);
5031 	}
5032 
5033 	/* Enable RSS Hash per TC */
5034 	if (hw->mac.type != ixgbe_mac_82598EB) {
5035 		u32 msb = 0;
5036 		u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
5037 
5038 		while (rss_i) {
5039 			msb++;
5040 			rss_i >>= 1;
5041 		}
5042 
5043 		/* write msb to all 8 TCs in one write */
5044 		IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
5045 	}
5046 }
5047 #endif
5048 
5049 /* Additional bittime to account for IXGBE framing */
5050 #define IXGBE_ETH_FRAMING 20
5051 
5052 /**
5053  * ixgbe_hpbthresh - calculate high water mark for flow control
5054  *
5055  * @adapter: board private structure to calculate for
5056  * @pb: packet buffer to calculate
5057  */
5058 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5059 {
5060 	struct ixgbe_hw *hw = &adapter->hw;
5061 	struct net_device *dev = adapter->netdev;
5062 	int link, tc, kb, marker;
5063 	u32 dv_id, rx_pba;
5064 
5065 	/* Calculate max LAN frame size */
5066 	tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5067 
5068 #ifdef IXGBE_FCOE
5069 	/* FCoE traffic class uses FCOE jumbo frames */
5070 	if ((dev->features & NETIF_F_FCOE_MTU) &&
5071 	    (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5072 	    (pb == ixgbe_fcoe_get_tc(adapter)))
5073 		tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5074 #endif
5075 
5076 	/* Calculate delay value for device */
5077 	switch (hw->mac.type) {
5078 	case ixgbe_mac_X540:
5079 	case ixgbe_mac_X550:
5080 	case ixgbe_mac_X550EM_x:
5081 	case ixgbe_mac_x550em_a:
5082 		dv_id = IXGBE_DV_X540(link, tc);
5083 		break;
5084 	default:
5085 		dv_id = IXGBE_DV(link, tc);
5086 		break;
5087 	}
5088 
5089 	/* Loopback switch introduces additional latency */
5090 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5091 		dv_id += IXGBE_B2BT(tc);
5092 
5093 	/* Delay value is calculated in bit times convert to KB */
5094 	kb = IXGBE_BT2KB(dv_id);
5095 	rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5096 
5097 	marker = rx_pba - kb;
5098 
5099 	/* It is possible that the packet buffer is not large enough
5100 	 * to provide required headroom. In this case throw an error
5101 	 * to user and a do the best we can.
5102 	 */
5103 	if (marker < 0) {
5104 		e_warn(drv, "Packet Buffer(%i) can not provide enough"
5105 			    "headroom to support flow control."
5106 			    "Decrease MTU or number of traffic classes\n", pb);
5107 		marker = tc + 1;
5108 	}
5109 
5110 	return marker;
5111 }
5112 
5113 /**
5114  * ixgbe_lpbthresh - calculate low water mark for for flow control
5115  *
5116  * @adapter: board private structure to calculate for
5117  * @pb: packet buffer to calculate
5118  */
5119 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
5120 {
5121 	struct ixgbe_hw *hw = &adapter->hw;
5122 	struct net_device *dev = adapter->netdev;
5123 	int tc;
5124 	u32 dv_id;
5125 
5126 	/* Calculate max LAN frame size */
5127 	tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5128 
5129 #ifdef IXGBE_FCOE
5130 	/* FCoE traffic class uses FCOE jumbo frames */
5131 	if ((dev->features & NETIF_F_FCOE_MTU) &&
5132 	    (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
5133 	    (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5134 		tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5135 #endif
5136 
5137 	/* Calculate delay value for device */
5138 	switch (hw->mac.type) {
5139 	case ixgbe_mac_X540:
5140 	case ixgbe_mac_X550:
5141 	case ixgbe_mac_X550EM_x:
5142 	case ixgbe_mac_x550em_a:
5143 		dv_id = IXGBE_LOW_DV_X540(tc);
5144 		break;
5145 	default:
5146 		dv_id = IXGBE_LOW_DV(tc);
5147 		break;
5148 	}
5149 
5150 	/* Delay value is calculated in bit times convert to KB */
5151 	return IXGBE_BT2KB(dv_id);
5152 }
5153 
5154 /*
5155  * ixgbe_pbthresh_setup - calculate and setup high low water marks
5156  */
5157 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5158 {
5159 	struct ixgbe_hw *hw = &adapter->hw;
5160 	int num_tc = adapter->hw_tcs;
5161 	int i;
5162 
5163 	if (!num_tc)
5164 		num_tc = 1;
5165 
5166 	for (i = 0; i < num_tc; i++) {
5167 		hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
5168 		hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
5169 
5170 		/* Low water marks must not be larger than high water marks */
5171 		if (hw->fc.low_water[i] > hw->fc.high_water[i])
5172 			hw->fc.low_water[i] = 0;
5173 	}
5174 
5175 	for (; i < MAX_TRAFFIC_CLASS; i++)
5176 		hw->fc.high_water[i] = 0;
5177 }
5178 
5179 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5180 {
5181 	struct ixgbe_hw *hw = &adapter->hw;
5182 	int hdrm;
5183 	u8 tc = adapter->hw_tcs;
5184 
5185 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5186 	    adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5187 		hdrm = 32 << adapter->fdir_pballoc;
5188 	else
5189 		hdrm = 0;
5190 
5191 	hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
5192 	ixgbe_pbthresh_setup(adapter);
5193 }
5194 
5195 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5196 {
5197 	struct ixgbe_hw *hw = &adapter->hw;
5198 	struct hlist_node *node2;
5199 	struct ixgbe_fdir_filter *filter;
5200 
5201 	spin_lock(&adapter->fdir_perfect_lock);
5202 
5203 	if (!hlist_empty(&adapter->fdir_filter_list))
5204 		ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5205 
5206 	hlist_for_each_entry_safe(filter, node2,
5207 				  &adapter->fdir_filter_list, fdir_node) {
5208 		ixgbe_fdir_write_perfect_filter_82599(hw,
5209 				&filter->filter,
5210 				filter->sw_idx,
5211 				(filter->action == IXGBE_FDIR_DROP_QUEUE) ?
5212 				IXGBE_FDIR_DROP_QUEUE :
5213 				adapter->rx_ring[filter->action]->reg_idx);
5214 	}
5215 
5216 	spin_unlock(&adapter->fdir_perfect_lock);
5217 }
5218 
5219 /**
5220  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5221  * @rx_ring: ring to free buffers from
5222  **/
5223 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5224 {
5225 	u16 i = rx_ring->next_to_clean;
5226 	struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
5227 
5228 	/* Free all the Rx ring sk_buffs */
5229 	while (i != rx_ring->next_to_alloc) {
5230 		if (rx_buffer->skb) {
5231 			struct sk_buff *skb = rx_buffer->skb;
5232 			if (IXGBE_CB(skb)->page_released)
5233 				dma_unmap_page_attrs(rx_ring->dev,
5234 						     IXGBE_CB(skb)->dma,
5235 						     ixgbe_rx_pg_size(rx_ring),
5236 						     DMA_FROM_DEVICE,
5237 						     IXGBE_RX_DMA_ATTR);
5238 			dev_kfree_skb(skb);
5239 		}
5240 
5241 		/* Invalidate cache lines that may have been written to by
5242 		 * device so that we avoid corrupting memory.
5243 		 */
5244 		dma_sync_single_range_for_cpu(rx_ring->dev,
5245 					      rx_buffer->dma,
5246 					      rx_buffer->page_offset,
5247 					      ixgbe_rx_bufsz(rx_ring),
5248 					      DMA_FROM_DEVICE);
5249 
5250 		/* free resources associated with mapping */
5251 		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
5252 				     ixgbe_rx_pg_size(rx_ring),
5253 				     DMA_FROM_DEVICE,
5254 				     IXGBE_RX_DMA_ATTR);
5255 		__page_frag_cache_drain(rx_buffer->page,
5256 					rx_buffer->pagecnt_bias);
5257 
5258 		i++;
5259 		rx_buffer++;
5260 		if (i == rx_ring->count) {
5261 			i = 0;
5262 			rx_buffer = rx_ring->rx_buffer_info;
5263 		}
5264 	}
5265 
5266 	rx_ring->next_to_alloc = 0;
5267 	rx_ring->next_to_clean = 0;
5268 	rx_ring->next_to_use = 0;
5269 }
5270 
5271 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
5272 			     struct ixgbe_fwd_adapter *accel)
5273 {
5274 	struct net_device *vdev = accel->netdev;
5275 	int i, baseq, err;
5276 
5277 	baseq = accel->pool * adapter->num_rx_queues_per_pool;
5278 	netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
5279 		   accel->pool, adapter->num_rx_pools,
5280 		   baseq, baseq + adapter->num_rx_queues_per_pool);
5281 
5282 	accel->rx_base_queue = baseq;
5283 	accel->tx_base_queue = baseq;
5284 
5285 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5286 		adapter->rx_ring[baseq + i]->netdev = vdev;
5287 
5288 	/* Guarantee all rings are updated before we update the
5289 	 * MAC address filter.
5290 	 */
5291 	wmb();
5292 
5293 	/* ixgbe_add_mac_filter will return an index if it succeeds, so we
5294 	 * need to only treat it as an error value if it is negative.
5295 	 */
5296 	err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5297 				   VMDQ_P(accel->pool));
5298 	if (err >= 0)
5299 		return 0;
5300 
5301 	/* if we cannot add the MAC rule then disable the offload */
5302 	macvlan_release_l2fw_offload(vdev);
5303 
5304 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5305 		adapter->rx_ring[baseq + i]->netdev = NULL;
5306 
5307 	netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5308 
5309 	clear_bit(accel->pool, adapter->fwd_bitmask);
5310 	kfree(accel);
5311 
5312 	return err;
5313 }
5314 
5315 static int ixgbe_macvlan_up(struct net_device *vdev, void *data)
5316 {
5317 	struct ixgbe_adapter *adapter = data;
5318 	struct ixgbe_fwd_adapter *accel;
5319 
5320 	if (!netif_is_macvlan(vdev))
5321 		return 0;
5322 
5323 	accel = macvlan_accel_priv(vdev);
5324 	if (!accel)
5325 		return 0;
5326 
5327 	ixgbe_fwd_ring_up(adapter, accel);
5328 
5329 	return 0;
5330 }
5331 
5332 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5333 {
5334 	netdev_walk_all_upper_dev_rcu(adapter->netdev,
5335 				      ixgbe_macvlan_up, adapter);
5336 }
5337 
5338 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5339 {
5340 	struct ixgbe_hw *hw = &adapter->hw;
5341 
5342 	ixgbe_configure_pb(adapter);
5343 #ifdef CONFIG_IXGBE_DCB
5344 	ixgbe_configure_dcb(adapter);
5345 #endif
5346 	/*
5347 	 * We must restore virtualization before VLANs or else
5348 	 * the VLVF registers will not be populated
5349 	 */
5350 	ixgbe_configure_virtualization(adapter);
5351 
5352 	ixgbe_set_rx_mode(adapter->netdev);
5353 	ixgbe_restore_vlan(adapter);
5354 	ixgbe_ipsec_restore(adapter);
5355 
5356 	switch (hw->mac.type) {
5357 	case ixgbe_mac_82599EB:
5358 	case ixgbe_mac_X540:
5359 		hw->mac.ops.disable_rx_buff(hw);
5360 		break;
5361 	default:
5362 		break;
5363 	}
5364 
5365 	if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5366 		ixgbe_init_fdir_signature_82599(&adapter->hw,
5367 						adapter->fdir_pballoc);
5368 	} else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5369 		ixgbe_init_fdir_perfect_82599(&adapter->hw,
5370 					      adapter->fdir_pballoc);
5371 		ixgbe_fdir_filter_restore(adapter);
5372 	}
5373 
5374 	switch (hw->mac.type) {
5375 	case ixgbe_mac_82599EB:
5376 	case ixgbe_mac_X540:
5377 		hw->mac.ops.enable_rx_buff(hw);
5378 		break;
5379 	default:
5380 		break;
5381 	}
5382 
5383 #ifdef CONFIG_IXGBE_DCA
5384 	/* configure DCA */
5385 	if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5386 		ixgbe_setup_dca(adapter);
5387 #endif /* CONFIG_IXGBE_DCA */
5388 
5389 #ifdef IXGBE_FCOE
5390 	/* configure FCoE L2 filters, redirection table, and Rx control */
5391 	ixgbe_configure_fcoe(adapter);
5392 
5393 #endif /* IXGBE_FCOE */
5394 	ixgbe_configure_tx(adapter);
5395 	ixgbe_configure_rx(adapter);
5396 	ixgbe_configure_dfwd(adapter);
5397 }
5398 
5399 /**
5400  * ixgbe_sfp_link_config - set up SFP+ link
5401  * @adapter: pointer to private adapter struct
5402  **/
5403 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5404 {
5405 	/*
5406 	 * We are assuming the worst case scenario here, and that
5407 	 * is that an SFP was inserted/removed after the reset
5408 	 * but before SFP detection was enabled.  As such the best
5409 	 * solution is to just start searching as soon as we start
5410 	 */
5411 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5412 		adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5413 
5414 	adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5415 	adapter->sfp_poll_time = 0;
5416 }
5417 
5418 /**
5419  * ixgbe_non_sfp_link_config - set up non-SFP+ link
5420  * @hw: pointer to private hardware struct
5421  *
5422  * Returns 0 on success, negative on failure
5423  **/
5424 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5425 {
5426 	u32 speed;
5427 	bool autoneg, link_up = false;
5428 	int ret = IXGBE_ERR_LINK_SETUP;
5429 
5430 	if (hw->mac.ops.check_link)
5431 		ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5432 
5433 	if (ret)
5434 		return ret;
5435 
5436 	speed = hw->phy.autoneg_advertised;
5437 	if ((!speed) && (hw->mac.ops.get_link_capabilities))
5438 		ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5439 							&autoneg);
5440 	if (ret)
5441 		return ret;
5442 
5443 	if (hw->mac.ops.setup_link)
5444 		ret = hw->mac.ops.setup_link(hw, speed, link_up);
5445 
5446 	return ret;
5447 }
5448 
5449 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5450 {
5451 	struct ixgbe_hw *hw = &adapter->hw;
5452 	u32 gpie = 0;
5453 
5454 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5455 		gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5456 		       IXGBE_GPIE_OCD;
5457 		gpie |= IXGBE_GPIE_EIAME;
5458 		/*
5459 		 * use EIAM to auto-mask when MSI-X interrupt is asserted
5460 		 * this saves a register write for every interrupt
5461 		 */
5462 		switch (hw->mac.type) {
5463 		case ixgbe_mac_82598EB:
5464 			IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5465 			break;
5466 		case ixgbe_mac_82599EB:
5467 		case ixgbe_mac_X540:
5468 		case ixgbe_mac_X550:
5469 		case ixgbe_mac_X550EM_x:
5470 		case ixgbe_mac_x550em_a:
5471 		default:
5472 			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5473 			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5474 			break;
5475 		}
5476 	} else {
5477 		/* legacy interrupts, use EIAM to auto-mask when reading EICR,
5478 		 * specifically only auto mask tx and rx interrupts */
5479 		IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5480 	}
5481 
5482 	/* XXX: to interrupt immediately for EICS writes, enable this */
5483 	/* gpie |= IXGBE_GPIE_EIMEN; */
5484 
5485 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5486 		gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5487 
5488 		switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5489 		case IXGBE_82599_VMDQ_8Q_MASK:
5490 			gpie |= IXGBE_GPIE_VTMODE_16;
5491 			break;
5492 		case IXGBE_82599_VMDQ_4Q_MASK:
5493 			gpie |= IXGBE_GPIE_VTMODE_32;
5494 			break;
5495 		default:
5496 			gpie |= IXGBE_GPIE_VTMODE_64;
5497 			break;
5498 		}
5499 	}
5500 
5501 	/* Enable Thermal over heat sensor interrupt */
5502 	if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5503 		switch (adapter->hw.mac.type) {
5504 		case ixgbe_mac_82599EB:
5505 			gpie |= IXGBE_SDP0_GPIEN_8259X;
5506 			break;
5507 		default:
5508 			break;
5509 		}
5510 	}
5511 
5512 	/* Enable fan failure interrupt */
5513 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5514 		gpie |= IXGBE_SDP1_GPIEN(hw);
5515 
5516 	switch (hw->mac.type) {
5517 	case ixgbe_mac_82599EB:
5518 		gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5519 		break;
5520 	case ixgbe_mac_X550EM_x:
5521 	case ixgbe_mac_x550em_a:
5522 		gpie |= IXGBE_SDP0_GPIEN_X540;
5523 		break;
5524 	default:
5525 		break;
5526 	}
5527 
5528 	IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5529 }
5530 
5531 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5532 {
5533 	struct ixgbe_hw *hw = &adapter->hw;
5534 	int err;
5535 	u32 ctrl_ext;
5536 
5537 	ixgbe_get_hw_control(adapter);
5538 	ixgbe_setup_gpie(adapter);
5539 
5540 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5541 		ixgbe_configure_msix(adapter);
5542 	else
5543 		ixgbe_configure_msi_and_legacy(adapter);
5544 
5545 	/* enable the optics for 82599 SFP+ fiber */
5546 	if (hw->mac.ops.enable_tx_laser)
5547 		hw->mac.ops.enable_tx_laser(hw);
5548 
5549 	if (hw->phy.ops.set_phy_power)
5550 		hw->phy.ops.set_phy_power(hw, true);
5551 
5552 	smp_mb__before_atomic();
5553 	clear_bit(__IXGBE_DOWN, &adapter->state);
5554 	ixgbe_napi_enable_all(adapter);
5555 
5556 	if (ixgbe_is_sfp(hw)) {
5557 		ixgbe_sfp_link_config(adapter);
5558 	} else {
5559 		err = ixgbe_non_sfp_link_config(hw);
5560 		if (err)
5561 			e_err(probe, "link_config FAILED %d\n", err);
5562 	}
5563 
5564 	/* clear any pending interrupts, may auto mask */
5565 	IXGBE_READ_REG(hw, IXGBE_EICR);
5566 	ixgbe_irq_enable(adapter, true, true);
5567 
5568 	/*
5569 	 * If this adapter has a fan, check to see if we had a failure
5570 	 * before we enabled the interrupt.
5571 	 */
5572 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5573 		u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5574 		if (esdp & IXGBE_ESDP_SDP1)
5575 			e_crit(drv, "Fan has stopped, replace the adapter\n");
5576 	}
5577 
5578 	/* bring the link up in the watchdog, this could race with our first
5579 	 * link up interrupt but shouldn't be a problem */
5580 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5581 	adapter->link_check_timeout = jiffies;
5582 	mod_timer(&adapter->service_timer, jiffies);
5583 
5584 	/* Set PF Reset Done bit so PF/VF Mail Ops can work */
5585 	ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5586 	ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5587 	IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5588 }
5589 
5590 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5591 {
5592 	WARN_ON(in_interrupt());
5593 	/* put off any impending NetWatchDogTimeout */
5594 	netif_trans_update(adapter->netdev);
5595 
5596 	while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5597 		usleep_range(1000, 2000);
5598 	if (adapter->hw.phy.type == ixgbe_phy_fw)
5599 		ixgbe_watchdog_link_is_down(adapter);
5600 	ixgbe_down(adapter);
5601 	/*
5602 	 * If SR-IOV enabled then wait a bit before bringing the adapter
5603 	 * back up to give the VFs time to respond to the reset.  The
5604 	 * two second wait is based upon the watchdog timer cycle in
5605 	 * the VF driver.
5606 	 */
5607 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5608 		msleep(2000);
5609 	ixgbe_up(adapter);
5610 	clear_bit(__IXGBE_RESETTING, &adapter->state);
5611 }
5612 
5613 void ixgbe_up(struct ixgbe_adapter *adapter)
5614 {
5615 	/* hardware has been reset, we need to reload some things */
5616 	ixgbe_configure(adapter);
5617 
5618 	ixgbe_up_complete(adapter);
5619 }
5620 
5621 void ixgbe_reset(struct ixgbe_adapter *adapter)
5622 {
5623 	struct ixgbe_hw *hw = &adapter->hw;
5624 	struct net_device *netdev = adapter->netdev;
5625 	int err;
5626 
5627 	if (ixgbe_removed(hw->hw_addr))
5628 		return;
5629 	/* lock SFP init bit to prevent race conditions with the watchdog */
5630 	while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5631 		usleep_range(1000, 2000);
5632 
5633 	/* clear all SFP and link config related flags while holding SFP_INIT */
5634 	adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5635 			     IXGBE_FLAG2_SFP_NEEDS_RESET);
5636 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5637 
5638 	err = hw->mac.ops.init_hw(hw);
5639 	switch (err) {
5640 	case 0:
5641 	case IXGBE_ERR_SFP_NOT_PRESENT:
5642 	case IXGBE_ERR_SFP_NOT_SUPPORTED:
5643 		break;
5644 	case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5645 		e_dev_err("master disable timed out\n");
5646 		break;
5647 	case IXGBE_ERR_EEPROM_VERSION:
5648 		/* We are running on a pre-production device, log a warning */
5649 		e_dev_warn("This device is a pre-production adapter/LOM. "
5650 			   "Please be aware there may be issues associated with "
5651 			   "your hardware.  If you are experiencing problems "
5652 			   "please contact your Intel or hardware "
5653 			   "representative who provided you with this "
5654 			   "hardware.\n");
5655 		break;
5656 	default:
5657 		e_dev_err("Hardware Error: %d\n", err);
5658 	}
5659 
5660 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5661 
5662 	/* flush entries out of MAC table */
5663 	ixgbe_flush_sw_mac_table(adapter);
5664 	__dev_uc_unsync(netdev, NULL);
5665 
5666 	/* do not flush user set addresses */
5667 	ixgbe_mac_set_default_filter(adapter);
5668 
5669 	/* update SAN MAC vmdq pool selection */
5670 	if (hw->mac.san_mac_rar_index)
5671 		hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5672 
5673 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5674 		ixgbe_ptp_reset(adapter);
5675 
5676 	if (hw->phy.ops.set_phy_power) {
5677 		if (!netif_running(adapter->netdev) && !adapter->wol)
5678 			hw->phy.ops.set_phy_power(hw, false);
5679 		else
5680 			hw->phy.ops.set_phy_power(hw, true);
5681 	}
5682 }
5683 
5684 /**
5685  * ixgbe_clean_tx_ring - Free Tx Buffers
5686  * @tx_ring: ring to be cleaned
5687  **/
5688 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5689 {
5690 	u16 i = tx_ring->next_to_clean;
5691 	struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
5692 
5693 	while (i != tx_ring->next_to_use) {
5694 		union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
5695 
5696 		/* Free all the Tx ring sk_buffs */
5697 		if (ring_is_xdp(tx_ring))
5698 			xdp_return_frame(tx_buffer->xdpf);
5699 		else
5700 			dev_kfree_skb_any(tx_buffer->skb);
5701 
5702 		/* unmap skb header data */
5703 		dma_unmap_single(tx_ring->dev,
5704 				 dma_unmap_addr(tx_buffer, dma),
5705 				 dma_unmap_len(tx_buffer, len),
5706 				 DMA_TO_DEVICE);
5707 
5708 		/* check for eop_desc to determine the end of the packet */
5709 		eop_desc = tx_buffer->next_to_watch;
5710 		tx_desc = IXGBE_TX_DESC(tx_ring, i);
5711 
5712 		/* unmap remaining buffers */
5713 		while (tx_desc != eop_desc) {
5714 			tx_buffer++;
5715 			tx_desc++;
5716 			i++;
5717 			if (unlikely(i == tx_ring->count)) {
5718 				i = 0;
5719 				tx_buffer = tx_ring->tx_buffer_info;
5720 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5721 			}
5722 
5723 			/* unmap any remaining paged data */
5724 			if (dma_unmap_len(tx_buffer, len))
5725 				dma_unmap_page(tx_ring->dev,
5726 					       dma_unmap_addr(tx_buffer, dma),
5727 					       dma_unmap_len(tx_buffer, len),
5728 					       DMA_TO_DEVICE);
5729 		}
5730 
5731 		/* move us one more past the eop_desc for start of next pkt */
5732 		tx_buffer++;
5733 		i++;
5734 		if (unlikely(i == tx_ring->count)) {
5735 			i = 0;
5736 			tx_buffer = tx_ring->tx_buffer_info;
5737 		}
5738 	}
5739 
5740 	/* reset BQL for queue */
5741 	if (!ring_is_xdp(tx_ring))
5742 		netdev_tx_reset_queue(txring_txq(tx_ring));
5743 
5744 	/* reset next_to_use and next_to_clean */
5745 	tx_ring->next_to_use = 0;
5746 	tx_ring->next_to_clean = 0;
5747 }
5748 
5749 /**
5750  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5751  * @adapter: board private structure
5752  **/
5753 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5754 {
5755 	int i;
5756 
5757 	for (i = 0; i < adapter->num_rx_queues; i++)
5758 		ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5759 }
5760 
5761 /**
5762  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5763  * @adapter: board private structure
5764  **/
5765 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5766 {
5767 	int i;
5768 
5769 	for (i = 0; i < adapter->num_tx_queues; i++)
5770 		ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5771 	for (i = 0; i < adapter->num_xdp_queues; i++)
5772 		ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
5773 }
5774 
5775 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5776 {
5777 	struct hlist_node *node2;
5778 	struct ixgbe_fdir_filter *filter;
5779 
5780 	spin_lock(&adapter->fdir_perfect_lock);
5781 
5782 	hlist_for_each_entry_safe(filter, node2,
5783 				  &adapter->fdir_filter_list, fdir_node) {
5784 		hlist_del(&filter->fdir_node);
5785 		kfree(filter);
5786 	}
5787 	adapter->fdir_filter_count = 0;
5788 
5789 	spin_unlock(&adapter->fdir_perfect_lock);
5790 }
5791 
5792 void ixgbe_down(struct ixgbe_adapter *adapter)
5793 {
5794 	struct net_device *netdev = adapter->netdev;
5795 	struct ixgbe_hw *hw = &adapter->hw;
5796 	int i;
5797 
5798 	/* signal that we are down to the interrupt handler */
5799 	if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5800 		return; /* do nothing if already down */
5801 
5802 	/* disable receives */
5803 	hw->mac.ops.disable_rx(hw);
5804 
5805 	/* disable all enabled rx queues */
5806 	for (i = 0; i < adapter->num_rx_queues; i++)
5807 		/* this call also flushes the previous write */
5808 		ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5809 
5810 	usleep_range(10000, 20000);
5811 
5812 	/* synchronize_sched() needed for pending XDP buffers to drain */
5813 	if (adapter->xdp_ring[0])
5814 		synchronize_sched();
5815 	netif_tx_stop_all_queues(netdev);
5816 
5817 	/* call carrier off first to avoid false dev_watchdog timeouts */
5818 	netif_carrier_off(netdev);
5819 	netif_tx_disable(netdev);
5820 
5821 	ixgbe_irq_disable(adapter);
5822 
5823 	ixgbe_napi_disable_all(adapter);
5824 
5825 	clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
5826 	adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5827 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5828 
5829 	del_timer_sync(&adapter->service_timer);
5830 
5831 	if (adapter->num_vfs) {
5832 		/* Clear EITR Select mapping */
5833 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5834 
5835 		/* Mark all the VFs as inactive */
5836 		for (i = 0 ; i < adapter->num_vfs; i++)
5837 			adapter->vfinfo[i].clear_to_send = false;
5838 
5839 		/* ping all the active vfs to let them know we are going down */
5840 		ixgbe_ping_all_vfs(adapter);
5841 
5842 		/* Disable all VFTE/VFRE TX/RX */
5843 		ixgbe_disable_tx_rx(adapter);
5844 	}
5845 
5846 	/* disable transmits in the hardware now that interrupts are off */
5847 	for (i = 0; i < adapter->num_tx_queues; i++) {
5848 		u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5849 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5850 	}
5851 	for (i = 0; i < adapter->num_xdp_queues; i++) {
5852 		u8 reg_idx = adapter->xdp_ring[i]->reg_idx;
5853 
5854 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5855 	}
5856 
5857 	/* Disable the Tx DMA engine on 82599 and later MAC */
5858 	switch (hw->mac.type) {
5859 	case ixgbe_mac_82599EB:
5860 	case ixgbe_mac_X540:
5861 	case ixgbe_mac_X550:
5862 	case ixgbe_mac_X550EM_x:
5863 	case ixgbe_mac_x550em_a:
5864 		IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5865 				(IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5866 				 ~IXGBE_DMATXCTL_TE));
5867 		break;
5868 	default:
5869 		break;
5870 	}
5871 
5872 	if (!pci_channel_offline(adapter->pdev))
5873 		ixgbe_reset(adapter);
5874 
5875 	/* power down the optics for 82599 SFP+ fiber */
5876 	if (hw->mac.ops.disable_tx_laser)
5877 		hw->mac.ops.disable_tx_laser(hw);
5878 
5879 	ixgbe_clean_all_tx_rings(adapter);
5880 	ixgbe_clean_all_rx_rings(adapter);
5881 }
5882 
5883 /**
5884  * ixgbe_eee_capable - helper function to determine EEE support on X550
5885  * @adapter: board private structure
5886  */
5887 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
5888 {
5889 	struct ixgbe_hw *hw = &adapter->hw;
5890 
5891 	switch (hw->device_id) {
5892 	case IXGBE_DEV_ID_X550EM_A_1G_T:
5893 	case IXGBE_DEV_ID_X550EM_A_1G_T_L:
5894 		if (!hw->phy.eee_speeds_supported)
5895 			break;
5896 		adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
5897 		if (!hw->phy.eee_speeds_advertised)
5898 			break;
5899 		adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
5900 		break;
5901 	default:
5902 		adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
5903 		adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
5904 		break;
5905 	}
5906 }
5907 
5908 /**
5909  * ixgbe_tx_timeout - Respond to a Tx Hang
5910  * @netdev: network interface device structure
5911  **/
5912 static void ixgbe_tx_timeout(struct net_device *netdev)
5913 {
5914 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
5915 
5916 	/* Do the reset outside of interrupt context */
5917 	ixgbe_tx_timeout_reset(adapter);
5918 }
5919 
5920 #ifdef CONFIG_IXGBE_DCB
5921 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
5922 {
5923 	struct ixgbe_hw *hw = &adapter->hw;
5924 	struct tc_configuration *tc;
5925 	int j;
5926 
5927 	switch (hw->mac.type) {
5928 	case ixgbe_mac_82598EB:
5929 	case ixgbe_mac_82599EB:
5930 		adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5931 		adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5932 		break;
5933 	case ixgbe_mac_X540:
5934 	case ixgbe_mac_X550:
5935 		adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5936 		adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5937 		break;
5938 	case ixgbe_mac_X550EM_x:
5939 	case ixgbe_mac_x550em_a:
5940 	default:
5941 		adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
5942 		adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
5943 		break;
5944 	}
5945 
5946 	/* Configure DCB traffic classes */
5947 	for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5948 		tc = &adapter->dcb_cfg.tc_config[j];
5949 		tc->path[DCB_TX_CONFIG].bwg_id = 0;
5950 		tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5951 		tc->path[DCB_RX_CONFIG].bwg_id = 0;
5952 		tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5953 		tc->dcb_pfc = pfc_disabled;
5954 	}
5955 
5956 	/* Initialize default user to priority mapping, UPx->TC0 */
5957 	tc = &adapter->dcb_cfg.tc_config[0];
5958 	tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5959 	tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5960 
5961 	adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5962 	adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5963 	adapter->dcb_cfg.pfc_mode_enable = false;
5964 	adapter->dcb_set_bitmap = 0x00;
5965 	if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
5966 		adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5967 	memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5968 	       sizeof(adapter->temp_dcb_cfg));
5969 }
5970 #endif
5971 
5972 /**
5973  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5974  * @adapter: board private structure to initialize
5975  * @ii: pointer to ixgbe_info for device
5976  *
5977  * ixgbe_sw_init initializes the Adapter private data structure.
5978  * Fields are initialized based on PCI device information and
5979  * OS network device settings (MTU size).
5980  **/
5981 static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
5982 			 const struct ixgbe_info *ii)
5983 {
5984 	struct ixgbe_hw *hw = &adapter->hw;
5985 	struct pci_dev *pdev = adapter->pdev;
5986 	unsigned int rss, fdir;
5987 	u32 fwsm;
5988 	int i;
5989 
5990 	/* PCI config space info */
5991 
5992 	hw->vendor_id = pdev->vendor;
5993 	hw->device_id = pdev->device;
5994 	hw->revision_id = pdev->revision;
5995 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
5996 	hw->subsystem_device_id = pdev->subsystem_device;
5997 
5998 	/* get_invariants needs the device IDs */
5999 	ii->get_invariants(hw);
6000 
6001 	/* Set common capability flags and settings */
6002 	rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
6003 	adapter->ring_feature[RING_F_RSS].limit = rss;
6004 	adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
6005 	adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6006 	adapter->atr_sample_rate = 20;
6007 	fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6008 	adapter->ring_feature[RING_F_FDIR].limit = fdir;
6009 	adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6010 	adapter->ring_feature[RING_F_VMDQ].limit = 1;
6011 #ifdef CONFIG_IXGBE_DCA
6012 	adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6013 #endif
6014 #ifdef CONFIG_IXGBE_DCB
6015 	adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6016 	adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6017 #endif
6018 #ifdef IXGBE_FCOE
6019 	adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6020 	adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6021 #ifdef CONFIG_IXGBE_DCB
6022 	/* Default traffic class to use for FCoE */
6023 	adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6024 #endif /* CONFIG_IXGBE_DCB */
6025 #endif /* IXGBE_FCOE */
6026 
6027 	/* initialize static ixgbe jump table entries */
6028 	adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6029 					  GFP_KERNEL);
6030 	if (!adapter->jump_tables[0])
6031 		return -ENOMEM;
6032 	adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6033 
6034 	for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6035 		adapter->jump_tables[i] = NULL;
6036 
6037 	adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6038 				     sizeof(struct ixgbe_mac_addr),
6039 				     GFP_ATOMIC);
6040 	if (!adapter->mac_table)
6041 		return -ENOMEM;
6042 
6043 	if (ixgbe_init_rss_key(adapter))
6044 		return -ENOMEM;
6045 
6046 	/* Set MAC specific capability flags and exceptions */
6047 	switch (hw->mac.type) {
6048 	case ixgbe_mac_82598EB:
6049 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
6050 
6051 		if (hw->device_id == IXGBE_DEV_ID_82598AT)
6052 			adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
6053 
6054 		adapter->max_q_vectors = MAX_Q_VECTORS_82598;
6055 		adapter->ring_feature[RING_F_FDIR].limit = 0;
6056 		adapter->atr_sample_rate = 0;
6057 		adapter->fdir_pballoc = 0;
6058 #ifdef IXGBE_FCOE
6059 		adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6060 		adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6061 #ifdef CONFIG_IXGBE_DCB
6062 		adapter->fcoe.up = 0;
6063 #endif /* IXGBE_DCB */
6064 #endif /* IXGBE_FCOE */
6065 		break;
6066 	case ixgbe_mac_82599EB:
6067 		if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6068 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6069 		break;
6070 	case ixgbe_mac_X540:
6071 		fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
6072 		if (fwsm & IXGBE_FWSM_TS_ENABLED)
6073 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6074 		break;
6075 	case ixgbe_mac_x550em_a:
6076 		adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE;
6077 		switch (hw->device_id) {
6078 		case IXGBE_DEV_ID_X550EM_A_1G_T:
6079 		case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6080 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6081 			break;
6082 		default:
6083 			break;
6084 		}
6085 	/* fall through */
6086 	case ixgbe_mac_X550EM_x:
6087 #ifdef CONFIG_IXGBE_DCB
6088 		adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6089 #endif
6090 #ifdef IXGBE_FCOE
6091 		adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6092 #ifdef CONFIG_IXGBE_DCB
6093 		adapter->fcoe.up = 0;
6094 #endif /* IXGBE_DCB */
6095 #endif /* IXGBE_FCOE */
6096 	/* Fall Through */
6097 	case ixgbe_mac_X550:
6098 		if (hw->mac.type == ixgbe_mac_X550)
6099 			adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6100 #ifdef CONFIG_IXGBE_DCA
6101 		adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
6102 #endif
6103 		adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
6104 		break;
6105 	default:
6106 		break;
6107 	}
6108 
6109 #ifdef IXGBE_FCOE
6110 	/* FCoE support exists, always init the FCoE lock */
6111 	spin_lock_init(&adapter->fcoe.lock);
6112 
6113 #endif
6114 	/* n-tuple support exists, always init our spinlock */
6115 	spin_lock_init(&adapter->fdir_perfect_lock);
6116 
6117 #ifdef CONFIG_IXGBE_DCB
6118 	ixgbe_init_dcb(adapter);
6119 #endif
6120 	ixgbe_init_ipsec_offload(adapter);
6121 
6122 	/* default flow control settings */
6123 	hw->fc.requested_mode = ixgbe_fc_full;
6124 	hw->fc.current_mode = ixgbe_fc_full;	/* init for ethtool output */
6125 	ixgbe_pbthresh_setup(adapter);
6126 	hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6127 	hw->fc.send_xon = true;
6128 	hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
6129 
6130 #ifdef CONFIG_PCI_IOV
6131 	if (max_vfs > 0)
6132 		e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6133 
6134 	/* assign number of SR-IOV VFs */
6135 	if (hw->mac.type != ixgbe_mac_82598EB) {
6136 		if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
6137 			max_vfs = 0;
6138 			e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
6139 		}
6140 	}
6141 #endif /* CONFIG_PCI_IOV */
6142 
6143 	/* enable itr by default in dynamic mode */
6144 	adapter->rx_itr_setting = 1;
6145 	adapter->tx_itr_setting = 1;
6146 
6147 	/* set default ring sizes */
6148 	adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6149 	adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6150 
6151 	/* set default work limits */
6152 	adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
6153 
6154 	/* initialize eeprom parameters */
6155 	if (ixgbe_init_eeprom_params_generic(hw)) {
6156 		e_dev_err("EEPROM initialization failed\n");
6157 		return -EIO;
6158 	}
6159 
6160 	/* PF holds first pool slot */
6161 	set_bit(0, adapter->fwd_bitmask);
6162 	set_bit(__IXGBE_DOWN, &adapter->state);
6163 
6164 	return 0;
6165 }
6166 
6167 /**
6168  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
6169  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
6170  *
6171  * Return 0 on success, negative on failure
6172  **/
6173 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
6174 {
6175 	struct device *dev = tx_ring->dev;
6176 	int orig_node = dev_to_node(dev);
6177 	int ring_node = -1;
6178 	int size;
6179 
6180 	size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
6181 
6182 	if (tx_ring->q_vector)
6183 		ring_node = tx_ring->q_vector->numa_node;
6184 
6185 	tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
6186 	if (!tx_ring->tx_buffer_info)
6187 		tx_ring->tx_buffer_info = vmalloc(size);
6188 	if (!tx_ring->tx_buffer_info)
6189 		goto err;
6190 
6191 	/* round up to nearest 4K */
6192 	tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
6193 	tx_ring->size = ALIGN(tx_ring->size, 4096);
6194 
6195 	set_dev_node(dev, ring_node);
6196 	tx_ring->desc = dma_alloc_coherent(dev,
6197 					   tx_ring->size,
6198 					   &tx_ring->dma,
6199 					   GFP_KERNEL);
6200 	set_dev_node(dev, orig_node);
6201 	if (!tx_ring->desc)
6202 		tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6203 						   &tx_ring->dma, GFP_KERNEL);
6204 	if (!tx_ring->desc)
6205 		goto err;
6206 
6207 	tx_ring->next_to_use = 0;
6208 	tx_ring->next_to_clean = 0;
6209 	return 0;
6210 
6211 err:
6212 	vfree(tx_ring->tx_buffer_info);
6213 	tx_ring->tx_buffer_info = NULL;
6214 	dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
6215 	return -ENOMEM;
6216 }
6217 
6218 /**
6219  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6220  * @adapter: board private structure
6221  *
6222  * If this function returns with an error, then it's possible one or
6223  * more of the rings is populated (while the rest are not).  It is the
6224  * callers duty to clean those orphaned rings.
6225  *
6226  * Return 0 on success, negative on failure
6227  **/
6228 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6229 {
6230 	int i, j = 0, err = 0;
6231 
6232 	for (i = 0; i < adapter->num_tx_queues; i++) {
6233 		err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
6234 		if (!err)
6235 			continue;
6236 
6237 		e_err(probe, "Allocation for Tx Queue %u failed\n", i);
6238 		goto err_setup_tx;
6239 	}
6240 	for (j = 0; j < adapter->num_xdp_queues; j++) {
6241 		err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6242 		if (!err)
6243 			continue;
6244 
6245 		e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6246 		goto err_setup_tx;
6247 	}
6248 
6249 	return 0;
6250 err_setup_tx:
6251 	/* rewind the index freeing the rings as we go */
6252 	while (j--)
6253 		ixgbe_free_tx_resources(adapter->xdp_ring[j]);
6254 	while (i--)
6255 		ixgbe_free_tx_resources(adapter->tx_ring[i]);
6256 	return err;
6257 }
6258 
6259 /**
6260  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
6261  * @adapter: pointer to ixgbe_adapter
6262  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
6263  *
6264  * Returns 0 on success, negative on failure
6265  **/
6266 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6267 			     struct ixgbe_ring *rx_ring)
6268 {
6269 	struct device *dev = rx_ring->dev;
6270 	int orig_node = dev_to_node(dev);
6271 	int ring_node = -1;
6272 	int size, err;
6273 
6274 	size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
6275 
6276 	if (rx_ring->q_vector)
6277 		ring_node = rx_ring->q_vector->numa_node;
6278 
6279 	rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
6280 	if (!rx_ring->rx_buffer_info)
6281 		rx_ring->rx_buffer_info = vmalloc(size);
6282 	if (!rx_ring->rx_buffer_info)
6283 		goto err;
6284 
6285 	/* Round up to nearest 4K */
6286 	rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6287 	rx_ring->size = ALIGN(rx_ring->size, 4096);
6288 
6289 	set_dev_node(dev, ring_node);
6290 	rx_ring->desc = dma_alloc_coherent(dev,
6291 					   rx_ring->size,
6292 					   &rx_ring->dma,
6293 					   GFP_KERNEL);
6294 	set_dev_node(dev, orig_node);
6295 	if (!rx_ring->desc)
6296 		rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6297 						   &rx_ring->dma, GFP_KERNEL);
6298 	if (!rx_ring->desc)
6299 		goto err;
6300 
6301 	rx_ring->next_to_clean = 0;
6302 	rx_ring->next_to_use = 0;
6303 
6304 	/* XDP RX-queue info */
6305 	if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
6306 			     rx_ring->queue_index) < 0)
6307 		goto err;
6308 
6309 	err = xdp_rxq_info_reg_mem_model(&rx_ring->xdp_rxq,
6310 					 MEM_TYPE_PAGE_SHARED, NULL);
6311 	if (err) {
6312 		xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6313 		goto err;
6314 	}
6315 
6316 	rx_ring->xdp_prog = adapter->xdp_prog;
6317 
6318 	return 0;
6319 err:
6320 	vfree(rx_ring->rx_buffer_info);
6321 	rx_ring->rx_buffer_info = NULL;
6322 	dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
6323 	return -ENOMEM;
6324 }
6325 
6326 /**
6327  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6328  * @adapter: board private structure
6329  *
6330  * If this function returns with an error, then it's possible one or
6331  * more of the rings is populated (while the rest are not).  It is the
6332  * callers duty to clean those orphaned rings.
6333  *
6334  * Return 0 on success, negative on failure
6335  **/
6336 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6337 {
6338 	int i, err = 0;
6339 
6340 	for (i = 0; i < adapter->num_rx_queues; i++) {
6341 		err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
6342 		if (!err)
6343 			continue;
6344 
6345 		e_err(probe, "Allocation for Rx Queue %u failed\n", i);
6346 		goto err_setup_rx;
6347 	}
6348 
6349 #ifdef IXGBE_FCOE
6350 	err = ixgbe_setup_fcoe_ddp_resources(adapter);
6351 	if (!err)
6352 #endif
6353 		return 0;
6354 err_setup_rx:
6355 	/* rewind the index freeing the rings as we go */
6356 	while (i--)
6357 		ixgbe_free_rx_resources(adapter->rx_ring[i]);
6358 	return err;
6359 }
6360 
6361 /**
6362  * ixgbe_free_tx_resources - Free Tx Resources per Queue
6363  * @tx_ring: Tx descriptor ring for a specific queue
6364  *
6365  * Free all transmit software resources
6366  **/
6367 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
6368 {
6369 	ixgbe_clean_tx_ring(tx_ring);
6370 
6371 	vfree(tx_ring->tx_buffer_info);
6372 	tx_ring->tx_buffer_info = NULL;
6373 
6374 	/* if not set, then don't free */
6375 	if (!tx_ring->desc)
6376 		return;
6377 
6378 	dma_free_coherent(tx_ring->dev, tx_ring->size,
6379 			  tx_ring->desc, tx_ring->dma);
6380 
6381 	tx_ring->desc = NULL;
6382 }
6383 
6384 /**
6385  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6386  * @adapter: board private structure
6387  *
6388  * Free all transmit software resources
6389  **/
6390 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6391 {
6392 	int i;
6393 
6394 	for (i = 0; i < adapter->num_tx_queues; i++)
6395 		if (adapter->tx_ring[i]->desc)
6396 			ixgbe_free_tx_resources(adapter->tx_ring[i]);
6397 	for (i = 0; i < adapter->num_xdp_queues; i++)
6398 		if (adapter->xdp_ring[i]->desc)
6399 			ixgbe_free_tx_resources(adapter->xdp_ring[i]);
6400 }
6401 
6402 /**
6403  * ixgbe_free_rx_resources - Free Rx Resources
6404  * @rx_ring: ring to clean the resources from
6405  *
6406  * Free all receive software resources
6407  **/
6408 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
6409 {
6410 	ixgbe_clean_rx_ring(rx_ring);
6411 
6412 	rx_ring->xdp_prog = NULL;
6413 	xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6414 	vfree(rx_ring->rx_buffer_info);
6415 	rx_ring->rx_buffer_info = NULL;
6416 
6417 	/* if not set, then don't free */
6418 	if (!rx_ring->desc)
6419 		return;
6420 
6421 	dma_free_coherent(rx_ring->dev, rx_ring->size,
6422 			  rx_ring->desc, rx_ring->dma);
6423 
6424 	rx_ring->desc = NULL;
6425 }
6426 
6427 /**
6428  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6429  * @adapter: board private structure
6430  *
6431  * Free all receive software resources
6432  **/
6433 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6434 {
6435 	int i;
6436 
6437 #ifdef IXGBE_FCOE
6438 	ixgbe_free_fcoe_ddp_resources(adapter);
6439 
6440 #endif
6441 	for (i = 0; i < adapter->num_rx_queues; i++)
6442 		if (adapter->rx_ring[i]->desc)
6443 			ixgbe_free_rx_resources(adapter->rx_ring[i]);
6444 }
6445 
6446 /**
6447  * ixgbe_change_mtu - Change the Maximum Transfer Unit
6448  * @netdev: network interface device structure
6449  * @new_mtu: new value for maximum frame size
6450  *
6451  * Returns 0 on success, negative on failure
6452  **/
6453 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6454 {
6455 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
6456 
6457 	/*
6458 	 * For 82599EB we cannot allow legacy VFs to enable their receive
6459 	 * paths when MTU greater than 1500 is configured.  So display a
6460 	 * warning that legacy VFs will be disabled.
6461 	 */
6462 	if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6463 	    (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6464 	    (new_mtu > ETH_DATA_LEN))
6465 		e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6466 
6467 	e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6468 
6469 	/* must set new MTU before calling down or up */
6470 	netdev->mtu = new_mtu;
6471 
6472 	if (netif_running(netdev))
6473 		ixgbe_reinit_locked(adapter);
6474 
6475 	return 0;
6476 }
6477 
6478 /**
6479  * ixgbe_open - Called when a network interface is made active
6480  * @netdev: network interface device structure
6481  *
6482  * Returns 0 on success, negative value on failure
6483  *
6484  * The open entry point is called when a network interface is made
6485  * active by the system (IFF_UP).  At this point all resources needed
6486  * for transmit and receive operations are allocated, the interrupt
6487  * handler is registered with the OS, the watchdog timer is started,
6488  * and the stack is notified that the interface is ready.
6489  **/
6490 int ixgbe_open(struct net_device *netdev)
6491 {
6492 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
6493 	struct ixgbe_hw *hw = &adapter->hw;
6494 	int err, queues;
6495 
6496 	/* disallow open during test */
6497 	if (test_bit(__IXGBE_TESTING, &adapter->state))
6498 		return -EBUSY;
6499 
6500 	netif_carrier_off(netdev);
6501 
6502 	/* allocate transmit descriptors */
6503 	err = ixgbe_setup_all_tx_resources(adapter);
6504 	if (err)
6505 		goto err_setup_tx;
6506 
6507 	/* allocate receive descriptors */
6508 	err = ixgbe_setup_all_rx_resources(adapter);
6509 	if (err)
6510 		goto err_setup_rx;
6511 
6512 	ixgbe_configure(adapter);
6513 
6514 	err = ixgbe_request_irq(adapter);
6515 	if (err)
6516 		goto err_req_irq;
6517 
6518 	/* Notify the stack of the actual queue counts. */
6519 	queues = adapter->num_tx_queues;
6520 	err = netif_set_real_num_tx_queues(netdev, queues);
6521 	if (err)
6522 		goto err_set_queues;
6523 
6524 	queues = adapter->num_rx_queues;
6525 	err = netif_set_real_num_rx_queues(netdev, queues);
6526 	if (err)
6527 		goto err_set_queues;
6528 
6529 	ixgbe_ptp_init(adapter);
6530 
6531 	ixgbe_up_complete(adapter);
6532 
6533 	ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK);
6534 	udp_tunnel_get_rx_info(netdev);
6535 
6536 	return 0;
6537 
6538 err_set_queues:
6539 	ixgbe_free_irq(adapter);
6540 err_req_irq:
6541 	ixgbe_free_all_rx_resources(adapter);
6542 	if (hw->phy.ops.set_phy_power && !adapter->wol)
6543 		hw->phy.ops.set_phy_power(&adapter->hw, false);
6544 err_setup_rx:
6545 	ixgbe_free_all_tx_resources(adapter);
6546 err_setup_tx:
6547 	ixgbe_reset(adapter);
6548 
6549 	return err;
6550 }
6551 
6552 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6553 {
6554 	ixgbe_ptp_suspend(adapter);
6555 
6556 	if (adapter->hw.phy.ops.enter_lplu) {
6557 		adapter->hw.phy.reset_disable = true;
6558 		ixgbe_down(adapter);
6559 		adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6560 		adapter->hw.phy.reset_disable = false;
6561 	} else {
6562 		ixgbe_down(adapter);
6563 	}
6564 
6565 	ixgbe_free_irq(adapter);
6566 
6567 	ixgbe_free_all_tx_resources(adapter);
6568 	ixgbe_free_all_rx_resources(adapter);
6569 }
6570 
6571 /**
6572  * ixgbe_close - Disables a network interface
6573  * @netdev: network interface device structure
6574  *
6575  * Returns 0, this is not allowed to fail
6576  *
6577  * The close entry point is called when an interface is de-activated
6578  * by the OS.  The hardware is still under the drivers control, but
6579  * needs to be disabled.  A global MAC reset is issued to stop the
6580  * hardware, and all transmit and receive resources are freed.
6581  **/
6582 int ixgbe_close(struct net_device *netdev)
6583 {
6584 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
6585 
6586 	ixgbe_ptp_stop(adapter);
6587 
6588 	if (netif_device_present(netdev))
6589 		ixgbe_close_suspend(adapter);
6590 
6591 	ixgbe_fdir_filter_exit(adapter);
6592 
6593 	ixgbe_release_hw_control(adapter);
6594 
6595 	return 0;
6596 }
6597 
6598 #ifdef CONFIG_PM
6599 static int ixgbe_resume(struct pci_dev *pdev)
6600 {
6601 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6602 	struct net_device *netdev = adapter->netdev;
6603 	u32 err;
6604 
6605 	adapter->hw.hw_addr = adapter->io_addr;
6606 	pci_set_power_state(pdev, PCI_D0);
6607 	pci_restore_state(pdev);
6608 	/*
6609 	 * pci_restore_state clears dev->state_saved so call
6610 	 * pci_save_state to restore it.
6611 	 */
6612 	pci_save_state(pdev);
6613 
6614 	err = pci_enable_device_mem(pdev);
6615 	if (err) {
6616 		e_dev_err("Cannot enable PCI device from suspend\n");
6617 		return err;
6618 	}
6619 	smp_mb__before_atomic();
6620 	clear_bit(__IXGBE_DISABLED, &adapter->state);
6621 	pci_set_master(pdev);
6622 
6623 	pci_wake_from_d3(pdev, false);
6624 
6625 	ixgbe_reset(adapter);
6626 
6627 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6628 
6629 	rtnl_lock();
6630 	err = ixgbe_init_interrupt_scheme(adapter);
6631 	if (!err && netif_running(netdev))
6632 		err = ixgbe_open(netdev);
6633 
6634 
6635 	if (!err)
6636 		netif_device_attach(netdev);
6637 	rtnl_unlock();
6638 
6639 	return err;
6640 }
6641 #endif /* CONFIG_PM */
6642 
6643 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
6644 {
6645 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6646 	struct net_device *netdev = adapter->netdev;
6647 	struct ixgbe_hw *hw = &adapter->hw;
6648 	u32 ctrl;
6649 	u32 wufc = adapter->wol;
6650 #ifdef CONFIG_PM
6651 	int retval = 0;
6652 #endif
6653 
6654 	rtnl_lock();
6655 	netif_device_detach(netdev);
6656 
6657 	if (netif_running(netdev))
6658 		ixgbe_close_suspend(adapter);
6659 
6660 	ixgbe_clear_interrupt_scheme(adapter);
6661 	rtnl_unlock();
6662 
6663 #ifdef CONFIG_PM
6664 	retval = pci_save_state(pdev);
6665 	if (retval)
6666 		return retval;
6667 
6668 #endif
6669 	if (hw->mac.ops.stop_link_on_d3)
6670 		hw->mac.ops.stop_link_on_d3(hw);
6671 
6672 	if (wufc) {
6673 		u32 fctrl;
6674 
6675 		ixgbe_set_rx_mode(netdev);
6676 
6677 		/* enable the optics for 82599 SFP+ fiber as we can WoL */
6678 		if (hw->mac.ops.enable_tx_laser)
6679 			hw->mac.ops.enable_tx_laser(hw);
6680 
6681 		/* enable the reception of multicast packets */
6682 		fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6683 		fctrl |= IXGBE_FCTRL_MPE;
6684 		IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6685 
6686 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6687 		ctrl |= IXGBE_CTRL_GIO_DIS;
6688 		IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6689 
6690 		IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6691 	} else {
6692 		IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6693 		IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6694 	}
6695 
6696 	switch (hw->mac.type) {
6697 	case ixgbe_mac_82598EB:
6698 		pci_wake_from_d3(pdev, false);
6699 		break;
6700 	case ixgbe_mac_82599EB:
6701 	case ixgbe_mac_X540:
6702 	case ixgbe_mac_X550:
6703 	case ixgbe_mac_X550EM_x:
6704 	case ixgbe_mac_x550em_a:
6705 		pci_wake_from_d3(pdev, !!wufc);
6706 		break;
6707 	default:
6708 		break;
6709 	}
6710 
6711 	*enable_wake = !!wufc;
6712 	if (hw->phy.ops.set_phy_power && !*enable_wake)
6713 		hw->phy.ops.set_phy_power(hw, false);
6714 
6715 	ixgbe_release_hw_control(adapter);
6716 
6717 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6718 		pci_disable_device(pdev);
6719 
6720 	return 0;
6721 }
6722 
6723 #ifdef CONFIG_PM
6724 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6725 {
6726 	int retval;
6727 	bool wake;
6728 
6729 	retval = __ixgbe_shutdown(pdev, &wake);
6730 	if (retval)
6731 		return retval;
6732 
6733 	if (wake) {
6734 		pci_prepare_to_sleep(pdev);
6735 	} else {
6736 		pci_wake_from_d3(pdev, false);
6737 		pci_set_power_state(pdev, PCI_D3hot);
6738 	}
6739 
6740 	return 0;
6741 }
6742 #endif /* CONFIG_PM */
6743 
6744 static void ixgbe_shutdown(struct pci_dev *pdev)
6745 {
6746 	bool wake;
6747 
6748 	__ixgbe_shutdown(pdev, &wake);
6749 
6750 	if (system_state == SYSTEM_POWER_OFF) {
6751 		pci_wake_from_d3(pdev, wake);
6752 		pci_set_power_state(pdev, PCI_D3hot);
6753 	}
6754 }
6755 
6756 /**
6757  * ixgbe_update_stats - Update the board statistics counters.
6758  * @adapter: board private structure
6759  **/
6760 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6761 {
6762 	struct net_device *netdev = adapter->netdev;
6763 	struct ixgbe_hw *hw = &adapter->hw;
6764 	struct ixgbe_hw_stats *hwstats = &adapter->stats;
6765 	u64 total_mpc = 0;
6766 	u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6767 	u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6768 	u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6769 	u64 alloc_rx_page = 0;
6770 	u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6771 
6772 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6773 	    test_bit(__IXGBE_RESETTING, &adapter->state))
6774 		return;
6775 
6776 	if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6777 		u64 rsc_count = 0;
6778 		u64 rsc_flush = 0;
6779 		for (i = 0; i < adapter->num_rx_queues; i++) {
6780 			rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6781 			rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6782 		}
6783 		adapter->rsc_total_count = rsc_count;
6784 		adapter->rsc_total_flush = rsc_flush;
6785 	}
6786 
6787 	for (i = 0; i < adapter->num_rx_queues; i++) {
6788 		struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6789 		non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6790 		alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
6791 		alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6792 		alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6793 		hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6794 		bytes += rx_ring->stats.bytes;
6795 		packets += rx_ring->stats.packets;
6796 	}
6797 	adapter->non_eop_descs = non_eop_descs;
6798 	adapter->alloc_rx_page = alloc_rx_page;
6799 	adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6800 	adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6801 	adapter->hw_csum_rx_error = hw_csum_rx_error;
6802 	netdev->stats.rx_bytes = bytes;
6803 	netdev->stats.rx_packets = packets;
6804 
6805 	bytes = 0;
6806 	packets = 0;
6807 	/* gather some stats to the adapter struct that are per queue */
6808 	for (i = 0; i < adapter->num_tx_queues; i++) {
6809 		struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6810 		restart_queue += tx_ring->tx_stats.restart_queue;
6811 		tx_busy += tx_ring->tx_stats.tx_busy;
6812 		bytes += tx_ring->stats.bytes;
6813 		packets += tx_ring->stats.packets;
6814 	}
6815 	for (i = 0; i < adapter->num_xdp_queues; i++) {
6816 		struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
6817 
6818 		restart_queue += xdp_ring->tx_stats.restart_queue;
6819 		tx_busy += xdp_ring->tx_stats.tx_busy;
6820 		bytes += xdp_ring->stats.bytes;
6821 		packets += xdp_ring->stats.packets;
6822 	}
6823 	adapter->restart_queue = restart_queue;
6824 	adapter->tx_busy = tx_busy;
6825 	netdev->stats.tx_bytes = bytes;
6826 	netdev->stats.tx_packets = packets;
6827 
6828 	hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6829 
6830 	/* 8 register reads */
6831 	for (i = 0; i < 8; i++) {
6832 		/* for packet buffers not used, the register should read 0 */
6833 		mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6834 		missed_rx += mpc;
6835 		hwstats->mpc[i] += mpc;
6836 		total_mpc += hwstats->mpc[i];
6837 		hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6838 		hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6839 		switch (hw->mac.type) {
6840 		case ixgbe_mac_82598EB:
6841 			hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6842 			hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6843 			hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6844 			hwstats->pxonrxc[i] +=
6845 				IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6846 			break;
6847 		case ixgbe_mac_82599EB:
6848 		case ixgbe_mac_X540:
6849 		case ixgbe_mac_X550:
6850 		case ixgbe_mac_X550EM_x:
6851 		case ixgbe_mac_x550em_a:
6852 			hwstats->pxonrxc[i] +=
6853 				IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6854 			break;
6855 		default:
6856 			break;
6857 		}
6858 	}
6859 
6860 	/*16 register reads */
6861 	for (i = 0; i < 16; i++) {
6862 		hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6863 		hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6864 		if ((hw->mac.type == ixgbe_mac_82599EB) ||
6865 		    (hw->mac.type == ixgbe_mac_X540) ||
6866 		    (hw->mac.type == ixgbe_mac_X550) ||
6867 		    (hw->mac.type == ixgbe_mac_X550EM_x) ||
6868 		    (hw->mac.type == ixgbe_mac_x550em_a)) {
6869 			hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6870 			IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6871 			hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6872 			IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6873 		}
6874 	}
6875 
6876 	hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6877 	/* work around hardware counting issue */
6878 	hwstats->gprc -= missed_rx;
6879 
6880 	ixgbe_update_xoff_received(adapter);
6881 
6882 	/* 82598 hardware only has a 32 bit counter in the high register */
6883 	switch (hw->mac.type) {
6884 	case ixgbe_mac_82598EB:
6885 		hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6886 		hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6887 		hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6888 		hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6889 		break;
6890 	case ixgbe_mac_X540:
6891 	case ixgbe_mac_X550:
6892 	case ixgbe_mac_X550EM_x:
6893 	case ixgbe_mac_x550em_a:
6894 		/* OS2BMC stats are X540 and later */
6895 		hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6896 		hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6897 		hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6898 		hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6899 		/* fall through */
6900 	case ixgbe_mac_82599EB:
6901 		for (i = 0; i < 16; i++)
6902 			adapter->hw_rx_no_dma_resources +=
6903 					     IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6904 		hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6905 		IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6906 		hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6907 		IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6908 		hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6909 		IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6910 		hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6911 		hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6912 		hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6913 #ifdef IXGBE_FCOE
6914 		hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6915 		hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6916 		hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6917 		hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6918 		hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6919 		hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6920 		/* Add up per cpu counters for total ddp aloc fail */
6921 		if (adapter->fcoe.ddp_pool) {
6922 			struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6923 			struct ixgbe_fcoe_ddp_pool *ddp_pool;
6924 			unsigned int cpu;
6925 			u64 noddp = 0, noddp_ext_buff = 0;
6926 			for_each_possible_cpu(cpu) {
6927 				ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6928 				noddp += ddp_pool->noddp;
6929 				noddp_ext_buff += ddp_pool->noddp_ext_buff;
6930 			}
6931 			hwstats->fcoe_noddp = noddp;
6932 			hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6933 		}
6934 #endif /* IXGBE_FCOE */
6935 		break;
6936 	default:
6937 		break;
6938 	}
6939 	bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6940 	hwstats->bprc += bprc;
6941 	hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6942 	if (hw->mac.type == ixgbe_mac_82598EB)
6943 		hwstats->mprc -= bprc;
6944 	hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6945 	hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6946 	hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6947 	hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6948 	hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6949 	hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6950 	hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6951 	hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6952 	lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6953 	hwstats->lxontxc += lxon;
6954 	lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6955 	hwstats->lxofftxc += lxoff;
6956 	hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6957 	hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6958 	/*
6959 	 * 82598 errata - tx of flow control packets is included in tx counters
6960 	 */
6961 	xon_off_tot = lxon + lxoff;
6962 	hwstats->gptc -= xon_off_tot;
6963 	hwstats->mptc -= xon_off_tot;
6964 	hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6965 	hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6966 	hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6967 	hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6968 	hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6969 	hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6970 	hwstats->ptc64 -= xon_off_tot;
6971 	hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6972 	hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6973 	hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6974 	hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6975 	hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6976 	hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6977 
6978 	/* Fill out the OS statistics structure */
6979 	netdev->stats.multicast = hwstats->mprc;
6980 
6981 	/* Rx Errors */
6982 	netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6983 	netdev->stats.rx_dropped = 0;
6984 	netdev->stats.rx_length_errors = hwstats->rlec;
6985 	netdev->stats.rx_crc_errors = hwstats->crcerrs;
6986 	netdev->stats.rx_missed_errors = total_mpc;
6987 }
6988 
6989 /**
6990  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6991  * @adapter: pointer to the device adapter structure
6992  **/
6993 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6994 {
6995 	struct ixgbe_hw *hw = &adapter->hw;
6996 	int i;
6997 
6998 	if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6999 		return;
7000 
7001 	adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7002 
7003 	/* if interface is down do nothing */
7004 	if (test_bit(__IXGBE_DOWN, &adapter->state))
7005 		return;
7006 
7007 	/* do nothing if we are not using signature filters */
7008 	if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7009 		return;
7010 
7011 	adapter->fdir_overflow++;
7012 
7013 	if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7014 		for (i = 0; i < adapter->num_tx_queues; i++)
7015 			set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7016 				&(adapter->tx_ring[i]->state));
7017 		for (i = 0; i < adapter->num_xdp_queues; i++)
7018 			set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7019 				&adapter->xdp_ring[i]->state);
7020 		/* re-enable flow director interrupts */
7021 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
7022 	} else {
7023 		e_err(probe, "failed to finish FDIR re-initialization, "
7024 		      "ignored adding FDIR ATR filters\n");
7025 	}
7026 }
7027 
7028 /**
7029  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
7030  * @adapter: pointer to the device adapter structure
7031  *
7032  * This function serves two purposes.  First it strobes the interrupt lines
7033  * in order to make certain interrupts are occurring.  Secondly it sets the
7034  * bits needed to check for TX hangs.  As a result we should immediately
7035  * determine if a hang has occurred.
7036  */
7037 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
7038 {
7039 	struct ixgbe_hw *hw = &adapter->hw;
7040 	u64 eics = 0;
7041 	int i;
7042 
7043 	/* If we're down, removing or resetting, just bail */
7044 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7045 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
7046 	    test_bit(__IXGBE_RESETTING, &adapter->state))
7047 		return;
7048 
7049 	/* Force detection of hung controller */
7050 	if (netif_carrier_ok(adapter->netdev)) {
7051 		for (i = 0; i < adapter->num_tx_queues; i++)
7052 			set_check_for_tx_hang(adapter->tx_ring[i]);
7053 		for (i = 0; i < adapter->num_xdp_queues; i++)
7054 			set_check_for_tx_hang(adapter->xdp_ring[i]);
7055 	}
7056 
7057 	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7058 		/*
7059 		 * for legacy and MSI interrupts don't set any bits
7060 		 * that are enabled for EIAM, because this operation
7061 		 * would set *both* EIMS and EICS for any bit in EIAM
7062 		 */
7063 		IXGBE_WRITE_REG(hw, IXGBE_EICS,
7064 			(IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
7065 	} else {
7066 		/* get one bit for every active tx/rx interrupt vector */
7067 		for (i = 0; i < adapter->num_q_vectors; i++) {
7068 			struct ixgbe_q_vector *qv = adapter->q_vector[i];
7069 			if (qv->rx.ring || qv->tx.ring)
7070 				eics |= BIT_ULL(i);
7071 		}
7072 	}
7073 
7074 	/* Cause software interrupt to ensure rings are cleaned */
7075 	ixgbe_irq_rearm_queues(adapter, eics);
7076 }
7077 
7078 /**
7079  * ixgbe_watchdog_update_link - update the link status
7080  * @adapter: pointer to the device adapter structure
7081  **/
7082 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
7083 {
7084 	struct ixgbe_hw *hw = &adapter->hw;
7085 	u32 link_speed = adapter->link_speed;
7086 	bool link_up = adapter->link_up;
7087 	bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
7088 
7089 	if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7090 		return;
7091 
7092 	if (hw->mac.ops.check_link) {
7093 		hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
7094 	} else {
7095 		/* always assume link is up, if no check link function */
7096 		link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7097 		link_up = true;
7098 	}
7099 
7100 	if (adapter->ixgbe_ieee_pfc)
7101 		pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7102 
7103 	if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
7104 		hw->mac.ops.fc_enable(hw);
7105 		ixgbe_set_rx_drop_en(adapter);
7106 	}
7107 
7108 	if (link_up ||
7109 	    time_after(jiffies, (adapter->link_check_timeout +
7110 				 IXGBE_TRY_LINK_TIMEOUT))) {
7111 		adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7112 		IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7113 		IXGBE_WRITE_FLUSH(hw);
7114 	}
7115 
7116 	adapter->link_up = link_up;
7117 	adapter->link_speed = link_speed;
7118 }
7119 
7120 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7121 {
7122 #ifdef CONFIG_IXGBE_DCB
7123 	struct net_device *netdev = adapter->netdev;
7124 	struct dcb_app app = {
7125 			      .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7126 			      .protocol = 0,
7127 			     };
7128 	u8 up = 0;
7129 
7130 	if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7131 		up = dcb_ieee_getapp_mask(netdev, &app);
7132 
7133 	adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7134 #endif
7135 }
7136 
7137 /**
7138  * ixgbe_watchdog_link_is_up - update netif_carrier status and
7139  *                             print link up message
7140  * @adapter: pointer to the device adapter structure
7141  **/
7142 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
7143 {
7144 	struct net_device *netdev = adapter->netdev;
7145 	struct ixgbe_hw *hw = &adapter->hw;
7146 	u32 link_speed = adapter->link_speed;
7147 	const char *speed_str;
7148 	bool flow_rx, flow_tx;
7149 
7150 	/* only continue if link was previously down */
7151 	if (netif_carrier_ok(netdev))
7152 		return;
7153 
7154 	adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7155 
7156 	switch (hw->mac.type) {
7157 	case ixgbe_mac_82598EB: {
7158 		u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7159 		u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7160 		flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7161 		flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7162 	}
7163 		break;
7164 	case ixgbe_mac_X540:
7165 	case ixgbe_mac_X550:
7166 	case ixgbe_mac_X550EM_x:
7167 	case ixgbe_mac_x550em_a:
7168 	case ixgbe_mac_82599EB: {
7169 		u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7170 		u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7171 		flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7172 		flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7173 	}
7174 		break;
7175 	default:
7176 		flow_tx = false;
7177 		flow_rx = false;
7178 		break;
7179 	}
7180 
7181 	adapter->last_rx_ptp_check = jiffies;
7182 
7183 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7184 		ixgbe_ptp_start_cyclecounter(adapter);
7185 
7186 	switch (link_speed) {
7187 	case IXGBE_LINK_SPEED_10GB_FULL:
7188 		speed_str = "10 Gbps";
7189 		break;
7190 	case IXGBE_LINK_SPEED_5GB_FULL:
7191 		speed_str = "5 Gbps";
7192 		break;
7193 	case IXGBE_LINK_SPEED_2_5GB_FULL:
7194 		speed_str = "2.5 Gbps";
7195 		break;
7196 	case IXGBE_LINK_SPEED_1GB_FULL:
7197 		speed_str = "1 Gbps";
7198 		break;
7199 	case IXGBE_LINK_SPEED_100_FULL:
7200 		speed_str = "100 Mbps";
7201 		break;
7202 	case IXGBE_LINK_SPEED_10_FULL:
7203 		speed_str = "10 Mbps";
7204 		break;
7205 	default:
7206 		speed_str = "unknown speed";
7207 		break;
7208 	}
7209 	e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
7210 	       ((flow_rx && flow_tx) ? "RX/TX" :
7211 	       (flow_rx ? "RX" :
7212 	       (flow_tx ? "TX" : "None"))));
7213 
7214 	netif_carrier_on(netdev);
7215 	ixgbe_check_vf_rate_limit(adapter);
7216 
7217 	/* enable transmits */
7218 	netif_tx_wake_all_queues(adapter->netdev);
7219 
7220 	/* update the default user priority for VFs */
7221 	ixgbe_update_default_up(adapter);
7222 
7223 	/* ping all the active vfs to let them know link has changed */
7224 	ixgbe_ping_all_vfs(adapter);
7225 }
7226 
7227 /**
7228  * ixgbe_watchdog_link_is_down - update netif_carrier status and
7229  *                               print link down message
7230  * @adapter: pointer to the adapter structure
7231  **/
7232 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
7233 {
7234 	struct net_device *netdev = adapter->netdev;
7235 	struct ixgbe_hw *hw = &adapter->hw;
7236 
7237 	adapter->link_up = false;
7238 	adapter->link_speed = 0;
7239 
7240 	/* only continue if link was up previously */
7241 	if (!netif_carrier_ok(netdev))
7242 		return;
7243 
7244 	/* poll for SFP+ cable when link is down */
7245 	if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7246 		adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
7247 
7248 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7249 		ixgbe_ptp_start_cyclecounter(adapter);
7250 
7251 	e_info(drv, "NIC Link is Down\n");
7252 	netif_carrier_off(netdev);
7253 
7254 	/* ping all the active vfs to let them know link has changed */
7255 	ixgbe_ping_all_vfs(adapter);
7256 }
7257 
7258 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7259 {
7260 	int i;
7261 
7262 	for (i = 0; i < adapter->num_tx_queues; i++) {
7263 		struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7264 
7265 		if (tx_ring->next_to_use != tx_ring->next_to_clean)
7266 			return true;
7267 	}
7268 
7269 	for (i = 0; i < adapter->num_xdp_queues; i++) {
7270 		struct ixgbe_ring *ring = adapter->xdp_ring[i];
7271 
7272 		if (ring->next_to_use != ring->next_to_clean)
7273 			return true;
7274 	}
7275 
7276 	return false;
7277 }
7278 
7279 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7280 {
7281 	struct ixgbe_hw *hw = &adapter->hw;
7282 	struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7283 	u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7284 
7285 	int i, j;
7286 
7287 	if (!adapter->num_vfs)
7288 		return false;
7289 
7290 	/* resetting the PF is only needed for MAC before X550 */
7291 	if (hw->mac.type >= ixgbe_mac_X550)
7292 		return false;
7293 
7294 	for (i = 0; i < adapter->num_vfs; i++) {
7295 		for (j = 0; j < q_per_pool; j++) {
7296 			u32 h, t;
7297 
7298 			h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7299 			t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7300 
7301 			if (h != t)
7302 				return true;
7303 		}
7304 	}
7305 
7306 	return false;
7307 }
7308 
7309 /**
7310  * ixgbe_watchdog_flush_tx - flush queues on link down
7311  * @adapter: pointer to the device adapter structure
7312  **/
7313 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7314 {
7315 	if (!netif_carrier_ok(adapter->netdev)) {
7316 		if (ixgbe_ring_tx_pending(adapter) ||
7317 		    ixgbe_vf_tx_pending(adapter)) {
7318 			/* We've lost link, so the controller stops DMA,
7319 			 * but we've got queued Tx work that's never going
7320 			 * to get done, so reset controller to flush Tx.
7321 			 * (Do the reset outside of interrupt context).
7322 			 */
7323 			e_warn(drv, "initiating reset to clear Tx work after link loss\n");
7324 			set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
7325 		}
7326 	}
7327 }
7328 
7329 #ifdef CONFIG_PCI_IOV
7330 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7331 {
7332 	struct ixgbe_hw *hw = &adapter->hw;
7333 	struct pci_dev *pdev = adapter->pdev;
7334 	unsigned int vf;
7335 	u32 gpc;
7336 
7337 	if (!(netif_carrier_ok(adapter->netdev)))
7338 		return;
7339 
7340 	gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7341 	if (gpc) /* If incrementing then no need for the check below */
7342 		return;
7343 	/* Check to see if a bad DMA write target from an errant or
7344 	 * malicious VF has caused a PCIe error.  If so then we can
7345 	 * issue a VFLR to the offending VF(s) and then resume without
7346 	 * requesting a full slot reset.
7347 	 */
7348 
7349 	if (!pdev)
7350 		return;
7351 
7352 	/* check status reg for all VFs owned by this PF */
7353 	for (vf = 0; vf < adapter->num_vfs; ++vf) {
7354 		struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7355 		u16 status_reg;
7356 
7357 		if (!vfdev)
7358 			continue;
7359 		pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7360 		if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7361 		    status_reg & PCI_STATUS_REC_MASTER_ABORT)
7362 			pcie_flr(vfdev);
7363 	}
7364 }
7365 
7366 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7367 {
7368 	u32 ssvpc;
7369 
7370 	/* Do not perform spoof check for 82598 or if not in IOV mode */
7371 	if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7372 	    adapter->num_vfs == 0)
7373 		return;
7374 
7375 	ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7376 
7377 	/*
7378 	 * ssvpc register is cleared on read, if zero then no
7379 	 * spoofed packets in the last interval.
7380 	 */
7381 	if (!ssvpc)
7382 		return;
7383 
7384 	e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
7385 }
7386 #else
7387 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7388 {
7389 }
7390 
7391 static void
7392 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7393 {
7394 }
7395 #endif /* CONFIG_PCI_IOV */
7396 
7397 
7398 /**
7399  * ixgbe_watchdog_subtask - check and bring link up
7400  * @adapter: pointer to the device adapter structure
7401  **/
7402 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7403 {
7404 	/* if interface is down, removing or resetting, do nothing */
7405 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7406 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
7407 	    test_bit(__IXGBE_RESETTING, &adapter->state))
7408 		return;
7409 
7410 	ixgbe_watchdog_update_link(adapter);
7411 
7412 	if (adapter->link_up)
7413 		ixgbe_watchdog_link_is_up(adapter);
7414 	else
7415 		ixgbe_watchdog_link_is_down(adapter);
7416 
7417 	ixgbe_check_for_bad_vf(adapter);
7418 	ixgbe_spoof_check(adapter);
7419 	ixgbe_update_stats(adapter);
7420 
7421 	ixgbe_watchdog_flush_tx(adapter);
7422 }
7423 
7424 /**
7425  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7426  * @adapter: the ixgbe adapter structure
7427  **/
7428 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7429 {
7430 	struct ixgbe_hw *hw = &adapter->hw;
7431 	s32 err;
7432 
7433 	/* not searching for SFP so there is nothing to do here */
7434 	if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7435 	    !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7436 		return;
7437 
7438 	if (adapter->sfp_poll_time &&
7439 	    time_after(adapter->sfp_poll_time, jiffies))
7440 		return; /* If not yet time to poll for SFP */
7441 
7442 	/* someone else is in init, wait until next service event */
7443 	if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7444 		return;
7445 
7446 	adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7447 
7448 	err = hw->phy.ops.identify_sfp(hw);
7449 	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7450 		goto sfp_out;
7451 
7452 	if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7453 		/* If no cable is present, then we need to reset
7454 		 * the next time we find a good cable. */
7455 		adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7456 	}
7457 
7458 	/* exit on error */
7459 	if (err)
7460 		goto sfp_out;
7461 
7462 	/* exit if reset not needed */
7463 	if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7464 		goto sfp_out;
7465 
7466 	adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7467 
7468 	/*
7469 	 * A module may be identified correctly, but the EEPROM may not have
7470 	 * support for that module.  setup_sfp() will fail in that case, so
7471 	 * we should not allow that module to load.
7472 	 */
7473 	if (hw->mac.type == ixgbe_mac_82598EB)
7474 		err = hw->phy.ops.reset(hw);
7475 	else
7476 		err = hw->mac.ops.setup_sfp(hw);
7477 
7478 	if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7479 		goto sfp_out;
7480 
7481 	adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7482 	e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7483 
7484 sfp_out:
7485 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7486 
7487 	if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7488 	    (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7489 		e_dev_err("failed to initialize because an unsupported "
7490 			  "SFP+ module type was detected.\n");
7491 		e_dev_err("Reload the driver after installing a "
7492 			  "supported module.\n");
7493 		unregister_netdev(adapter->netdev);
7494 	}
7495 }
7496 
7497 /**
7498  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7499  * @adapter: the ixgbe adapter structure
7500  **/
7501 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7502 {
7503 	struct ixgbe_hw *hw = &adapter->hw;
7504 	u32 cap_speed;
7505 	u32 speed;
7506 	bool autoneg = false;
7507 
7508 	if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7509 		return;
7510 
7511 	/* someone else is in init, wait until next service event */
7512 	if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7513 		return;
7514 
7515 	adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7516 
7517 	hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
7518 
7519 	/* advertise highest capable link speed */
7520 	if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7521 		speed = IXGBE_LINK_SPEED_10GB_FULL;
7522 	else
7523 		speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7524 				     IXGBE_LINK_SPEED_1GB_FULL);
7525 
7526 	if (hw->mac.ops.setup_link)
7527 		hw->mac.ops.setup_link(hw, speed, true);
7528 
7529 	adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7530 	adapter->link_check_timeout = jiffies;
7531 	clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7532 }
7533 
7534 /**
7535  * ixgbe_service_timer - Timer Call-back
7536  * @t: pointer to timer_list structure
7537  **/
7538 static void ixgbe_service_timer(struct timer_list *t)
7539 {
7540 	struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7541 	unsigned long next_event_offset;
7542 
7543 	/* poll faster when waiting for link */
7544 	if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7545 		next_event_offset = HZ / 10;
7546 	else
7547 		next_event_offset = HZ * 2;
7548 
7549 	/* Reset the timer */
7550 	mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7551 
7552 	ixgbe_service_event_schedule(adapter);
7553 }
7554 
7555 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7556 {
7557 	struct ixgbe_hw *hw = &adapter->hw;
7558 	u32 status;
7559 
7560 	if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7561 		return;
7562 
7563 	adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7564 
7565 	if (!hw->phy.ops.handle_lasi)
7566 		return;
7567 
7568 	status = hw->phy.ops.handle_lasi(&adapter->hw);
7569 	if (status != IXGBE_ERR_OVERTEMP)
7570 		return;
7571 
7572 	e_crit(drv, "%s\n", ixgbe_overheat_msg);
7573 }
7574 
7575 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7576 {
7577 	if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
7578 		return;
7579 
7580 	rtnl_lock();
7581 	/* If we're already down, removing or resetting, just bail */
7582 	if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7583 	    test_bit(__IXGBE_REMOVING, &adapter->state) ||
7584 	    test_bit(__IXGBE_RESETTING, &adapter->state)) {
7585 		rtnl_unlock();
7586 		return;
7587 	}
7588 
7589 	ixgbe_dump(adapter);
7590 	netdev_err(adapter->netdev, "Reset adapter\n");
7591 	adapter->tx_timeout_count++;
7592 
7593 	ixgbe_reinit_locked(adapter);
7594 	rtnl_unlock();
7595 }
7596 
7597 /**
7598  * ixgbe_service_task - manages and runs subtasks
7599  * @work: pointer to work_struct containing our data
7600  **/
7601 static void ixgbe_service_task(struct work_struct *work)
7602 {
7603 	struct ixgbe_adapter *adapter = container_of(work,
7604 						     struct ixgbe_adapter,
7605 						     service_task);
7606 	if (ixgbe_removed(adapter->hw.hw_addr)) {
7607 		if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7608 			rtnl_lock();
7609 			ixgbe_down(adapter);
7610 			rtnl_unlock();
7611 		}
7612 		ixgbe_service_event_complete(adapter);
7613 		return;
7614 	}
7615 	if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) {
7616 		rtnl_lock();
7617 		adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
7618 		udp_tunnel_get_rx_info(adapter->netdev);
7619 		rtnl_unlock();
7620 	}
7621 	ixgbe_reset_subtask(adapter);
7622 	ixgbe_phy_interrupt_subtask(adapter);
7623 	ixgbe_sfp_detection_subtask(adapter);
7624 	ixgbe_sfp_link_config_subtask(adapter);
7625 	ixgbe_check_overtemp_subtask(adapter);
7626 	ixgbe_watchdog_subtask(adapter);
7627 	ixgbe_fdir_reinit_subtask(adapter);
7628 	ixgbe_check_hang_subtask(adapter);
7629 
7630 	if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
7631 		ixgbe_ptp_overflow_check(adapter);
7632 		if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
7633 			ixgbe_ptp_rx_hang(adapter);
7634 		ixgbe_ptp_tx_hang(adapter);
7635 	}
7636 
7637 	ixgbe_service_event_complete(adapter);
7638 }
7639 
7640 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7641 		     struct ixgbe_tx_buffer *first,
7642 		     u8 *hdr_len,
7643 		     struct ixgbe_ipsec_tx_data *itd)
7644 {
7645 	u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7646 	struct sk_buff *skb = first->skb;
7647 	union {
7648 		struct iphdr *v4;
7649 		struct ipv6hdr *v6;
7650 		unsigned char *hdr;
7651 	} ip;
7652 	union {
7653 		struct tcphdr *tcp;
7654 		unsigned char *hdr;
7655 	} l4;
7656 	u32 paylen, l4_offset;
7657 	u32 fceof_saidx = 0;
7658 	int err;
7659 
7660 	if (skb->ip_summed != CHECKSUM_PARTIAL)
7661 		return 0;
7662 
7663 	if (!skb_is_gso(skb))
7664 		return 0;
7665 
7666 	err = skb_cow_head(skb, 0);
7667 	if (err < 0)
7668 		return err;
7669 
7670 	if (eth_p_mpls(first->protocol))
7671 		ip.hdr = skb_inner_network_header(skb);
7672 	else
7673 		ip.hdr = skb_network_header(skb);
7674 	l4.hdr = skb_checksum_start(skb);
7675 
7676 	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7677 	type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7678 
7679 	/* initialize outer IP header fields */
7680 	if (ip.v4->version == 4) {
7681 		unsigned char *csum_start = skb_checksum_start(skb);
7682 		unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
7683 		int len = csum_start - trans_start;
7684 
7685 		/* IP header will have to cancel out any data that
7686 		 * is not a part of the outer IP header, so set to
7687 		 * a reverse csum if needed, else init check to 0.
7688 		 */
7689 		ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
7690 					   csum_fold(csum_partial(trans_start,
7691 								  len, 0)) : 0;
7692 		type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7693 
7694 		ip.v4->tot_len = 0;
7695 		first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7696 				   IXGBE_TX_FLAGS_CSUM |
7697 				   IXGBE_TX_FLAGS_IPV4;
7698 	} else {
7699 		ip.v6->payload_len = 0;
7700 		first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7701 				   IXGBE_TX_FLAGS_CSUM;
7702 	}
7703 
7704 	/* determine offset of inner transport header */
7705 	l4_offset = l4.hdr - skb->data;
7706 
7707 	/* compute length of segmentation header */
7708 	*hdr_len = (l4.tcp->doff * 4) + l4_offset;
7709 
7710 	/* remove payload length from inner checksum */
7711 	paylen = skb->len - l4_offset;
7712 	csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
7713 
7714 	/* update gso size and bytecount with header size */
7715 	first->gso_segs = skb_shinfo(skb)->gso_segs;
7716 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
7717 
7718 	/* mss_l4len_id: use 0 as index for TSO */
7719 	mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
7720 	mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
7721 
7722 	fceof_saidx |= itd->sa_idx;
7723 	type_tucmd |= itd->flags | itd->trailer_len;
7724 
7725 	/* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7726 	vlan_macip_lens = l4.hdr - ip.hdr;
7727 	vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
7728 	vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7729 
7730 	ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
7731 			  mss_l4len_idx);
7732 
7733 	return 1;
7734 }
7735 
7736 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7737 {
7738 	unsigned int offset = 0;
7739 
7740 	ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7741 
7742 	return offset == skb_checksum_start_offset(skb);
7743 }
7744 
7745 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7746 			  struct ixgbe_tx_buffer *first,
7747 			  struct ixgbe_ipsec_tx_data *itd)
7748 {
7749 	struct sk_buff *skb = first->skb;
7750 	u32 vlan_macip_lens = 0;
7751 	u32 fceof_saidx = 0;
7752 	u32 type_tucmd = 0;
7753 
7754 	if (skb->ip_summed != CHECKSUM_PARTIAL) {
7755 csum_failed:
7756 		if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7757 					 IXGBE_TX_FLAGS_CC)))
7758 			return;
7759 		goto no_csum;
7760 	}
7761 
7762 	switch (skb->csum_offset) {
7763 	case offsetof(struct tcphdr, check):
7764 		type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7765 		/* fall through */
7766 	case offsetof(struct udphdr, check):
7767 		break;
7768 	case offsetof(struct sctphdr, checksum):
7769 		/* validate that this is actually an SCTP request */
7770 		if (((first->protocol == htons(ETH_P_IP)) &&
7771 		     (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7772 		    ((first->protocol == htons(ETH_P_IPV6)) &&
7773 		     ixgbe_ipv6_csum_is_sctp(skb))) {
7774 			type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7775 			break;
7776 		}
7777 		/* fall through */
7778 	default:
7779 		skb_checksum_help(skb);
7780 		goto csum_failed;
7781 	}
7782 
7783 	/* update TX checksum flag */
7784 	first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7785 	vlan_macip_lens = skb_checksum_start_offset(skb) -
7786 			  skb_network_offset(skb);
7787 no_csum:
7788 	/* vlan_macip_lens: MACLEN, VLAN tag */
7789 	vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
7790 	vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7791 
7792 	fceof_saidx |= itd->sa_idx;
7793 	type_tucmd |= itd->flags | itd->trailer_len;
7794 
7795 	ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
7796 }
7797 
7798 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7799 	((_flag <= _result) ? \
7800 	 ((u32)(_input & _flag) * (_result / _flag)) : \
7801 	 ((u32)(_input & _flag) / (_flag / _result)))
7802 
7803 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7804 {
7805 	/* set type for advanced descriptor with frame checksum insertion */
7806 	u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7807 		       IXGBE_ADVTXD_DCMD_DEXT |
7808 		       IXGBE_ADVTXD_DCMD_IFCS;
7809 
7810 	/* set HW vlan bit if vlan is present */
7811 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7812 				   IXGBE_ADVTXD_DCMD_VLE);
7813 
7814 	/* set segmentation enable bits for TSO/FSO */
7815 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7816 				   IXGBE_ADVTXD_DCMD_TSE);
7817 
7818 	/* set timestamp bit if present */
7819 	cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7820 				   IXGBE_ADVTXD_MAC_TSTAMP);
7821 
7822 	/* insert frame checksum */
7823 	cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7824 
7825 	return cmd_type;
7826 }
7827 
7828 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7829 				   u32 tx_flags, unsigned int paylen)
7830 {
7831 	u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7832 
7833 	/* enable L4 checksum for TSO and TX checksum offload */
7834 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7835 					IXGBE_TX_FLAGS_CSUM,
7836 					IXGBE_ADVTXD_POPTS_TXSM);
7837 
7838 	/* enable IPv4 checksum for TSO */
7839 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7840 					IXGBE_TX_FLAGS_IPV4,
7841 					IXGBE_ADVTXD_POPTS_IXSM);
7842 
7843 	/* enable IPsec */
7844 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7845 					IXGBE_TX_FLAGS_IPSEC,
7846 					IXGBE_ADVTXD_POPTS_IPSEC);
7847 
7848 	/*
7849 	 * Check Context must be set if Tx switch is enabled, which it
7850 	 * always is for case where virtual functions are running
7851 	 */
7852 	olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7853 					IXGBE_TX_FLAGS_CC,
7854 					IXGBE_ADVTXD_CC);
7855 
7856 	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7857 }
7858 
7859 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7860 {
7861 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7862 
7863 	/* Herbert's original patch had:
7864 	 *  smp_mb__after_netif_stop_queue();
7865 	 * but since that doesn't exist yet, just open code it.
7866 	 */
7867 	smp_mb();
7868 
7869 	/* We need to check again in a case another CPU has just
7870 	 * made room available.
7871 	 */
7872 	if (likely(ixgbe_desc_unused(tx_ring) < size))
7873 		return -EBUSY;
7874 
7875 	/* A reprieve! - use start_queue because it doesn't call schedule */
7876 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7877 	++tx_ring->tx_stats.restart_queue;
7878 	return 0;
7879 }
7880 
7881 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7882 {
7883 	if (likely(ixgbe_desc_unused(tx_ring) >= size))
7884 		return 0;
7885 
7886 	return __ixgbe_maybe_stop_tx(tx_ring, size);
7887 }
7888 
7889 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7890 		       IXGBE_TXD_CMD_RS)
7891 
7892 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7893 			struct ixgbe_tx_buffer *first,
7894 			const u8 hdr_len)
7895 {
7896 	struct sk_buff *skb = first->skb;
7897 	struct ixgbe_tx_buffer *tx_buffer;
7898 	union ixgbe_adv_tx_desc *tx_desc;
7899 	struct skb_frag_struct *frag;
7900 	dma_addr_t dma;
7901 	unsigned int data_len, size;
7902 	u32 tx_flags = first->tx_flags;
7903 	u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7904 	u16 i = tx_ring->next_to_use;
7905 
7906 	tx_desc = IXGBE_TX_DESC(tx_ring, i);
7907 
7908 	ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7909 
7910 	size = skb_headlen(skb);
7911 	data_len = skb->data_len;
7912 
7913 #ifdef IXGBE_FCOE
7914 	if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7915 		if (data_len < sizeof(struct fcoe_crc_eof)) {
7916 			size -= sizeof(struct fcoe_crc_eof) - data_len;
7917 			data_len = 0;
7918 		} else {
7919 			data_len -= sizeof(struct fcoe_crc_eof);
7920 		}
7921 	}
7922 
7923 #endif
7924 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7925 
7926 	tx_buffer = first;
7927 
7928 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7929 		if (dma_mapping_error(tx_ring->dev, dma))
7930 			goto dma_error;
7931 
7932 		/* record length, and DMA address */
7933 		dma_unmap_len_set(tx_buffer, len, size);
7934 		dma_unmap_addr_set(tx_buffer, dma, dma);
7935 
7936 		tx_desc->read.buffer_addr = cpu_to_le64(dma);
7937 
7938 		while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7939 			tx_desc->read.cmd_type_len =
7940 				cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7941 
7942 			i++;
7943 			tx_desc++;
7944 			if (i == tx_ring->count) {
7945 				tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7946 				i = 0;
7947 			}
7948 			tx_desc->read.olinfo_status = 0;
7949 
7950 			dma += IXGBE_MAX_DATA_PER_TXD;
7951 			size -= IXGBE_MAX_DATA_PER_TXD;
7952 
7953 			tx_desc->read.buffer_addr = cpu_to_le64(dma);
7954 		}
7955 
7956 		if (likely(!data_len))
7957 			break;
7958 
7959 		tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7960 
7961 		i++;
7962 		tx_desc++;
7963 		if (i == tx_ring->count) {
7964 			tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7965 			i = 0;
7966 		}
7967 		tx_desc->read.olinfo_status = 0;
7968 
7969 #ifdef IXGBE_FCOE
7970 		size = min_t(unsigned int, data_len, skb_frag_size(frag));
7971 #else
7972 		size = skb_frag_size(frag);
7973 #endif
7974 		data_len -= size;
7975 
7976 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7977 				       DMA_TO_DEVICE);
7978 
7979 		tx_buffer = &tx_ring->tx_buffer_info[i];
7980 	}
7981 
7982 	/* write last descriptor with RS and EOP bits */
7983 	cmd_type |= size | IXGBE_TXD_CMD;
7984 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7985 
7986 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7987 
7988 	/* set the timestamp */
7989 	first->time_stamp = jiffies;
7990 
7991 	/*
7992 	 * Force memory writes to complete before letting h/w know there
7993 	 * are new descriptors to fetch.  (Only applicable for weak-ordered
7994 	 * memory model archs, such as IA-64).
7995 	 *
7996 	 * We also need this memory barrier to make certain all of the
7997 	 * status bits have been updated before next_to_watch is written.
7998 	 */
7999 	wmb();
8000 
8001 	/* set next_to_watch value indicating a packet is present */
8002 	first->next_to_watch = tx_desc;
8003 
8004 	i++;
8005 	if (i == tx_ring->count)
8006 		i = 0;
8007 
8008 	tx_ring->next_to_use = i;
8009 
8010 	ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8011 
8012 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
8013 		writel(i, tx_ring->tail);
8014 
8015 		/* we need this if more than one processor can write to our tail
8016 		 * at a time, it synchronizes IO on IA64/Altix systems
8017 		 */
8018 		mmiowb();
8019 	}
8020 
8021 	return 0;
8022 dma_error:
8023 	dev_err(tx_ring->dev, "TX DMA map failed\n");
8024 
8025 	/* clear dma mappings for failed tx_buffer_info map */
8026 	for (;;) {
8027 		tx_buffer = &tx_ring->tx_buffer_info[i];
8028 		if (dma_unmap_len(tx_buffer, len))
8029 			dma_unmap_page(tx_ring->dev,
8030 				       dma_unmap_addr(tx_buffer, dma),
8031 				       dma_unmap_len(tx_buffer, len),
8032 				       DMA_TO_DEVICE);
8033 		dma_unmap_len_set(tx_buffer, len, 0);
8034 		if (tx_buffer == first)
8035 			break;
8036 		if (i == 0)
8037 			i += tx_ring->count;
8038 		i--;
8039 	}
8040 
8041 	dev_kfree_skb_any(first->skb);
8042 	first->skb = NULL;
8043 
8044 	tx_ring->next_to_use = i;
8045 
8046 	return -1;
8047 }
8048 
8049 static void ixgbe_atr(struct ixgbe_ring *ring,
8050 		      struct ixgbe_tx_buffer *first)
8051 {
8052 	struct ixgbe_q_vector *q_vector = ring->q_vector;
8053 	union ixgbe_atr_hash_dword input = { .dword = 0 };
8054 	union ixgbe_atr_hash_dword common = { .dword = 0 };
8055 	union {
8056 		unsigned char *network;
8057 		struct iphdr *ipv4;
8058 		struct ipv6hdr *ipv6;
8059 	} hdr;
8060 	struct tcphdr *th;
8061 	unsigned int hlen;
8062 	struct sk_buff *skb;
8063 	__be16 vlan_id;
8064 	int l4_proto;
8065 
8066 	/* if ring doesn't have a interrupt vector, cannot perform ATR */
8067 	if (!q_vector)
8068 		return;
8069 
8070 	/* do nothing if sampling is disabled */
8071 	if (!ring->atr_sample_rate)
8072 		return;
8073 
8074 	ring->atr_count++;
8075 
8076 	/* currently only IPv4/IPv6 with TCP is supported */
8077 	if ((first->protocol != htons(ETH_P_IP)) &&
8078 	    (first->protocol != htons(ETH_P_IPV6)))
8079 		return;
8080 
8081 	/* snag network header to get L4 type and address */
8082 	skb = first->skb;
8083 	hdr.network = skb_network_header(skb);
8084 	if (unlikely(hdr.network <= skb->data))
8085 		return;
8086 	if (skb->encapsulation &&
8087 	    first->protocol == htons(ETH_P_IP) &&
8088 	    hdr.ipv4->protocol == IPPROTO_UDP) {
8089 		struct ixgbe_adapter *adapter = q_vector->adapter;
8090 
8091 		if (unlikely(skb_tail_pointer(skb) < hdr.network +
8092 			     VXLAN_HEADROOM))
8093 			return;
8094 
8095 		/* verify the port is recognized as VXLAN */
8096 		if (adapter->vxlan_port &&
8097 		    udp_hdr(skb)->dest == adapter->vxlan_port)
8098 			hdr.network = skb_inner_network_header(skb);
8099 
8100 		if (adapter->geneve_port &&
8101 		    udp_hdr(skb)->dest == adapter->geneve_port)
8102 			hdr.network = skb_inner_network_header(skb);
8103 	}
8104 
8105 	/* Make sure we have at least [minimum IPv4 header + TCP]
8106 	 * or [IPv6 header] bytes
8107 	 */
8108 	if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8109 		return;
8110 
8111 	/* Currently only IPv4/IPv6 with TCP is supported */
8112 	switch (hdr.ipv4->version) {
8113 	case IPVERSION:
8114 		/* access ihl as u8 to avoid unaligned access on ia64 */
8115 		hlen = (hdr.network[0] & 0x0F) << 2;
8116 		l4_proto = hdr.ipv4->protocol;
8117 		break;
8118 	case 6:
8119 		hlen = hdr.network - skb->data;
8120 		l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8121 		hlen -= hdr.network - skb->data;
8122 		break;
8123 	default:
8124 		return;
8125 	}
8126 
8127 	if (l4_proto != IPPROTO_TCP)
8128 		return;
8129 
8130 	if (unlikely(skb_tail_pointer(skb) < hdr.network +
8131 		     hlen + sizeof(struct tcphdr)))
8132 		return;
8133 
8134 	th = (struct tcphdr *)(hdr.network + hlen);
8135 
8136 	/* skip this packet since the socket is closing */
8137 	if (th->fin)
8138 		return;
8139 
8140 	/* sample on all syn packets or once every atr sample count */
8141 	if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8142 		return;
8143 
8144 	/* reset sample count */
8145 	ring->atr_count = 0;
8146 
8147 	vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
8148 
8149 	/*
8150 	 * src and dst are inverted, think how the receiver sees them
8151 	 *
8152 	 * The input is broken into two sections, a non-compressed section
8153 	 * containing vm_pool, vlan_id, and flow_type.  The rest of the data
8154 	 * is XORed together and stored in the compressed dword.
8155 	 */
8156 	input.formatted.vlan_id = vlan_id;
8157 
8158 	/*
8159 	 * since src port and flex bytes occupy the same word XOR them together
8160 	 * and write the value to source port portion of compressed dword
8161 	 */
8162 	if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
8163 		common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
8164 	else
8165 		common.port.src ^= th->dest ^ first->protocol;
8166 	common.port.dst ^= th->source;
8167 
8168 	switch (hdr.ipv4->version) {
8169 	case IPVERSION:
8170 		input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8171 		common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
8172 		break;
8173 	case 6:
8174 		input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8175 		common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8176 			     hdr.ipv6->saddr.s6_addr32[1] ^
8177 			     hdr.ipv6->saddr.s6_addr32[2] ^
8178 			     hdr.ipv6->saddr.s6_addr32[3] ^
8179 			     hdr.ipv6->daddr.s6_addr32[0] ^
8180 			     hdr.ipv6->daddr.s6_addr32[1] ^
8181 			     hdr.ipv6->daddr.s6_addr32[2] ^
8182 			     hdr.ipv6->daddr.s6_addr32[3];
8183 		break;
8184 	default:
8185 		break;
8186 	}
8187 
8188 	if (hdr.network != skb_network_header(skb))
8189 		input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
8190 
8191 	/* This assumes the Rx queue and Tx queue are bound to the same CPU */
8192 	ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8193 					      input, common, ring->queue_index);
8194 }
8195 
8196 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
8197 			      void *accel_priv, select_queue_fallback_t fallback)
8198 {
8199 	struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
8200 	struct ixgbe_adapter *adapter;
8201 	int txq;
8202 #ifdef IXGBE_FCOE
8203 	struct ixgbe_ring_feature *f;
8204 #endif
8205 
8206 	if (fwd_adapter) {
8207 		adapter = netdev_priv(dev);
8208 		txq = reciprocal_scale(skb_get_hash(skb),
8209 				       adapter->num_rx_queues_per_pool);
8210 
8211 		return txq + fwd_adapter->tx_base_queue;
8212 	}
8213 
8214 #ifdef IXGBE_FCOE
8215 
8216 	/*
8217 	 * only execute the code below if protocol is FCoE
8218 	 * or FIP and we have FCoE enabled on the adapter
8219 	 */
8220 	switch (vlan_get_protocol(skb)) {
8221 	case htons(ETH_P_FCOE):
8222 	case htons(ETH_P_FIP):
8223 		adapter = netdev_priv(dev);
8224 
8225 		if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
8226 			break;
8227 		/* fall through */
8228 	default:
8229 		return fallback(dev, skb);
8230 	}
8231 
8232 	f = &adapter->ring_feature[RING_F_FCOE];
8233 
8234 	txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8235 					   smp_processor_id();
8236 
8237 	while (txq >= f->indices)
8238 		txq -= f->indices;
8239 
8240 	return txq + f->offset;
8241 #else
8242 	return fallback(dev, skb);
8243 #endif
8244 }
8245 
8246 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter,
8247 			       struct xdp_frame *xdpf)
8248 {
8249 	struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()];
8250 	struct ixgbe_tx_buffer *tx_buffer;
8251 	union ixgbe_adv_tx_desc *tx_desc;
8252 	u32 len, cmd_type;
8253 	dma_addr_t dma;
8254 	u16 i;
8255 
8256 	len = xdpf->len;
8257 
8258 	if (unlikely(!ixgbe_desc_unused(ring)))
8259 		return IXGBE_XDP_CONSUMED;
8260 
8261 	dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE);
8262 	if (dma_mapping_error(ring->dev, dma))
8263 		return IXGBE_XDP_CONSUMED;
8264 
8265 	/* record the location of the first descriptor for this packet */
8266 	tx_buffer = &ring->tx_buffer_info[ring->next_to_use];
8267 	tx_buffer->bytecount = len;
8268 	tx_buffer->gso_segs = 1;
8269 	tx_buffer->protocol = 0;
8270 
8271 	i = ring->next_to_use;
8272 	tx_desc = IXGBE_TX_DESC(ring, i);
8273 
8274 	dma_unmap_len_set(tx_buffer, len, len);
8275 	dma_unmap_addr_set(tx_buffer, dma, dma);
8276 	tx_buffer->xdpf = xdpf;
8277 
8278 	tx_desc->read.buffer_addr = cpu_to_le64(dma);
8279 
8280 	/* put descriptor type bits */
8281 	cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8282 		   IXGBE_ADVTXD_DCMD_DEXT |
8283 		   IXGBE_ADVTXD_DCMD_IFCS;
8284 	cmd_type |= len | IXGBE_TXD_CMD;
8285 	tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8286 	tx_desc->read.olinfo_status =
8287 		cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT);
8288 
8289 	/* Avoid any potential race with xdp_xmit and cleanup */
8290 	smp_wmb();
8291 
8292 	/* set next_to_watch value indicating a packet is present */
8293 	i++;
8294 	if (i == ring->count)
8295 		i = 0;
8296 
8297 	tx_buffer->next_to_watch = tx_desc;
8298 	ring->next_to_use = i;
8299 
8300 	return IXGBE_XDP_TX;
8301 }
8302 
8303 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
8304 			  struct ixgbe_adapter *adapter,
8305 			  struct ixgbe_ring *tx_ring)
8306 {
8307 	struct ixgbe_tx_buffer *first;
8308 	int tso;
8309 	u32 tx_flags = 0;
8310 	unsigned short f;
8311 	u16 count = TXD_USE_COUNT(skb_headlen(skb));
8312 	struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
8313 	__be16 protocol = skb->protocol;
8314 	u8 hdr_len = 0;
8315 
8316 	/*
8317 	 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
8318 	 *       + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
8319 	 *       + 2 desc gap to keep tail from touching head,
8320 	 *       + 1 desc for context descriptor,
8321 	 * otherwise try next time
8322 	 */
8323 	for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8324 		count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
8325 
8326 	if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8327 		tx_ring->tx_stats.tx_busy++;
8328 		return NETDEV_TX_BUSY;
8329 	}
8330 
8331 	/* record the location of the first descriptor for this packet */
8332 	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8333 	first->skb = skb;
8334 	first->bytecount = skb->len;
8335 	first->gso_segs = 1;
8336 
8337 	/* if we have a HW VLAN tag being added default to the HW one */
8338 	if (skb_vlan_tag_present(skb)) {
8339 		tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
8340 		tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8341 	/* else if it is a SW VLAN check the next protocol and store the tag */
8342 	} else if (protocol == htons(ETH_P_8021Q)) {
8343 		struct vlan_hdr *vhdr, _vhdr;
8344 		vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8345 		if (!vhdr)
8346 			goto out_drop;
8347 
8348 		tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8349 				  IXGBE_TX_FLAGS_VLAN_SHIFT;
8350 		tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8351 	}
8352 	protocol = vlan_get_protocol(skb);
8353 
8354 	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8355 	    adapter->ptp_clock) {
8356 		if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8357 					   &adapter->state)) {
8358 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8359 			tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8360 
8361 			/* schedule check for Tx timestamp */
8362 			adapter->ptp_tx_skb = skb_get(skb);
8363 			adapter->ptp_tx_start = jiffies;
8364 			schedule_work(&adapter->ptp_tx_work);
8365 		} else {
8366 			adapter->tx_hwtstamp_skipped++;
8367 		}
8368 	}
8369 
8370 	skb_tx_timestamp(skb);
8371 
8372 #ifdef CONFIG_PCI_IOV
8373 	/*
8374 	 * Use the l2switch_enable flag - would be false if the DMA
8375 	 * Tx switch had been disabled.
8376 	 */
8377 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8378 		tx_flags |= IXGBE_TX_FLAGS_CC;
8379 
8380 #endif
8381 	/* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
8382 	if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8383 	    ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8384 	     (skb->priority != TC_PRIO_CONTROL))) {
8385 		tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
8386 		tx_flags |= (skb->priority & 0x7) <<
8387 					IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
8388 		if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8389 			struct vlan_ethhdr *vhdr;
8390 
8391 			if (skb_cow_head(skb, 0))
8392 				goto out_drop;
8393 			vhdr = (struct vlan_ethhdr *)skb->data;
8394 			vhdr->h_vlan_TCI = htons(tx_flags >>
8395 						 IXGBE_TX_FLAGS_VLAN_SHIFT);
8396 		} else {
8397 			tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8398 		}
8399 	}
8400 
8401 	/* record initial flags and protocol */
8402 	first->tx_flags = tx_flags;
8403 	first->protocol = protocol;
8404 
8405 #ifdef IXGBE_FCOE
8406 	/* setup tx offload for FCoE */
8407 	if ((protocol == htons(ETH_P_FCOE)) &&
8408 	    (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
8409 		tso = ixgbe_fso(tx_ring, first, &hdr_len);
8410 		if (tso < 0)
8411 			goto out_drop;
8412 
8413 		goto xmit_fcoe;
8414 	}
8415 
8416 #endif /* IXGBE_FCOE */
8417 
8418 #ifdef CONFIG_XFRM_OFFLOAD
8419 	if (skb->sp && !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
8420 		goto out_drop;
8421 #endif
8422 	tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
8423 	if (tso < 0)
8424 		goto out_drop;
8425 	else if (!tso)
8426 		ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
8427 
8428 	/* add the ATR filter if ATR is on */
8429 	if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
8430 		ixgbe_atr(tx_ring, first);
8431 
8432 #ifdef IXGBE_FCOE
8433 xmit_fcoe:
8434 #endif /* IXGBE_FCOE */
8435 	if (ixgbe_tx_map(tx_ring, first, hdr_len))
8436 		goto cleanup_tx_timestamp;
8437 
8438 	return NETDEV_TX_OK;
8439 
8440 out_drop:
8441 	dev_kfree_skb_any(first->skb);
8442 	first->skb = NULL;
8443 cleanup_tx_timestamp:
8444 	if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8445 		dev_kfree_skb_any(adapter->ptp_tx_skb);
8446 		adapter->ptp_tx_skb = NULL;
8447 		cancel_work_sync(&adapter->ptp_tx_work);
8448 		clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8449 	}
8450 
8451 	return NETDEV_TX_OK;
8452 }
8453 
8454 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8455 				      struct net_device *netdev,
8456 				      struct ixgbe_ring *ring)
8457 {
8458 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8459 	struct ixgbe_ring *tx_ring;
8460 
8461 	/*
8462 	 * The minimum packet size for olinfo paylen is 17 so pad the skb
8463 	 * in order to meet this minimum size requirement.
8464 	 */
8465 	if (skb_put_padto(skb, 17))
8466 		return NETDEV_TX_OK;
8467 
8468 	tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
8469 
8470 	return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
8471 }
8472 
8473 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8474 				    struct net_device *netdev)
8475 {
8476 	return __ixgbe_xmit_frame(skb, netdev, NULL);
8477 }
8478 
8479 /**
8480  * ixgbe_set_mac - Change the Ethernet Address of the NIC
8481  * @netdev: network interface device structure
8482  * @p: pointer to an address structure
8483  *
8484  * Returns 0 on success, negative on failure
8485  **/
8486 static int ixgbe_set_mac(struct net_device *netdev, void *p)
8487 {
8488 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8489 	struct ixgbe_hw *hw = &adapter->hw;
8490 	struct sockaddr *addr = p;
8491 
8492 	if (!is_valid_ether_addr(addr->sa_data))
8493 		return -EADDRNOTAVAIL;
8494 
8495 	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
8496 	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
8497 
8498 	ixgbe_mac_set_default_filter(adapter);
8499 
8500 	return 0;
8501 }
8502 
8503 static int
8504 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8505 {
8506 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8507 	struct ixgbe_hw *hw = &adapter->hw;
8508 	u16 value;
8509 	int rc;
8510 
8511 	if (prtad != hw->phy.mdio.prtad)
8512 		return -EINVAL;
8513 	rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8514 	if (!rc)
8515 		rc = value;
8516 	return rc;
8517 }
8518 
8519 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8520 			    u16 addr, u16 value)
8521 {
8522 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8523 	struct ixgbe_hw *hw = &adapter->hw;
8524 
8525 	if (prtad != hw->phy.mdio.prtad)
8526 		return -EINVAL;
8527 	return hw->phy.ops.write_reg(hw, addr, devad, value);
8528 }
8529 
8530 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8531 {
8532 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8533 
8534 	switch (cmd) {
8535 	case SIOCSHWTSTAMP:
8536 		return ixgbe_ptp_set_ts_config(adapter, req);
8537 	case SIOCGHWTSTAMP:
8538 		return ixgbe_ptp_get_ts_config(adapter, req);
8539 	case SIOCGMIIPHY:
8540 		if (!adapter->hw.phy.ops.read_reg)
8541 			return -EOPNOTSUPP;
8542 		/* fall through */
8543 	default:
8544 		return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8545 	}
8546 }
8547 
8548 /**
8549  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
8550  * netdev->dev_addrs
8551  * @dev: network interface device structure
8552  *
8553  * Returns non-zero on failure
8554  **/
8555 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8556 {
8557 	int err = 0;
8558 	struct ixgbe_adapter *adapter = netdev_priv(dev);
8559 	struct ixgbe_hw *hw = &adapter->hw;
8560 
8561 	if (is_valid_ether_addr(hw->mac.san_addr)) {
8562 		rtnl_lock();
8563 		err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
8564 		rtnl_unlock();
8565 
8566 		/* update SAN MAC vmdq pool selection */
8567 		hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
8568 	}
8569 	return err;
8570 }
8571 
8572 /**
8573  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
8574  * netdev->dev_addrs
8575  * @dev: network interface device structure
8576  *
8577  * Returns non-zero on failure
8578  **/
8579 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8580 {
8581 	int err = 0;
8582 	struct ixgbe_adapter *adapter = netdev_priv(dev);
8583 	struct ixgbe_mac_info *mac = &adapter->hw.mac;
8584 
8585 	if (is_valid_ether_addr(mac->san_addr)) {
8586 		rtnl_lock();
8587 		err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8588 		rtnl_unlock();
8589 	}
8590 	return err;
8591 }
8592 
8593 #ifdef CONFIG_NET_POLL_CONTROLLER
8594 /*
8595  * Polling 'interrupt' - used by things like netconsole to send skbs
8596  * without having to re-enable interrupts. It's not called while
8597  * the interrupt routine is executing.
8598  */
8599 static void ixgbe_netpoll(struct net_device *netdev)
8600 {
8601 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8602 	int i;
8603 
8604 	/* if interface is down do nothing */
8605 	if (test_bit(__IXGBE_DOWN, &adapter->state))
8606 		return;
8607 
8608 	/* loop through and schedule all active queues */
8609 	for (i = 0; i < adapter->num_q_vectors; i++)
8610 		ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8611 }
8612 
8613 #endif
8614 
8615 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
8616 				   struct ixgbe_ring *ring)
8617 {
8618 	u64 bytes, packets;
8619 	unsigned int start;
8620 
8621 	if (ring) {
8622 		do {
8623 			start = u64_stats_fetch_begin_irq(&ring->syncp);
8624 			packets = ring->stats.packets;
8625 			bytes   = ring->stats.bytes;
8626 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8627 		stats->tx_packets += packets;
8628 		stats->tx_bytes   += bytes;
8629 	}
8630 }
8631 
8632 static void ixgbe_get_stats64(struct net_device *netdev,
8633 			      struct rtnl_link_stats64 *stats)
8634 {
8635 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
8636 	int i;
8637 
8638 	rcu_read_lock();
8639 	for (i = 0; i < adapter->num_rx_queues; i++) {
8640 		struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
8641 		u64 bytes, packets;
8642 		unsigned int start;
8643 
8644 		if (ring) {
8645 			do {
8646 				start = u64_stats_fetch_begin_irq(&ring->syncp);
8647 				packets = ring->stats.packets;
8648 				bytes   = ring->stats.bytes;
8649 			} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
8650 			stats->rx_packets += packets;
8651 			stats->rx_bytes   += bytes;
8652 		}
8653 	}
8654 
8655 	for (i = 0; i < adapter->num_tx_queues; i++) {
8656 		struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
8657 
8658 		ixgbe_get_ring_stats64(stats, ring);
8659 	}
8660 	for (i = 0; i < adapter->num_xdp_queues; i++) {
8661 		struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
8662 
8663 		ixgbe_get_ring_stats64(stats, ring);
8664 	}
8665 	rcu_read_unlock();
8666 
8667 	/* following stats updated by ixgbe_watchdog_task() */
8668 	stats->multicast	= netdev->stats.multicast;
8669 	stats->rx_errors	= netdev->stats.rx_errors;
8670 	stats->rx_length_errors	= netdev->stats.rx_length_errors;
8671 	stats->rx_crc_errors	= netdev->stats.rx_crc_errors;
8672 	stats->rx_missed_errors	= netdev->stats.rx_missed_errors;
8673 }
8674 
8675 #ifdef CONFIG_IXGBE_DCB
8676 /**
8677  * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8678  * @adapter: pointer to ixgbe_adapter
8679  * @tc: number of traffic classes currently enabled
8680  *
8681  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8682  * 802.1Q priority maps to a packet buffer that exists.
8683  */
8684 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8685 {
8686 	struct ixgbe_hw *hw = &adapter->hw;
8687 	u32 reg, rsave;
8688 	int i;
8689 
8690 	/* 82598 have a static priority to TC mapping that can not
8691 	 * be changed so no validation is needed.
8692 	 */
8693 	if (hw->mac.type == ixgbe_mac_82598EB)
8694 		return;
8695 
8696 	reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8697 	rsave = reg;
8698 
8699 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8700 		u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8701 
8702 		/* If up2tc is out of bounds default to zero */
8703 		if (up2tc > tc)
8704 			reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8705 	}
8706 
8707 	if (reg != rsave)
8708 		IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8709 
8710 	return;
8711 }
8712 
8713 /**
8714  * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8715  * @adapter: Pointer to adapter struct
8716  *
8717  * Populate the netdev user priority to tc map
8718  */
8719 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8720 {
8721 	struct net_device *dev = adapter->netdev;
8722 	struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8723 	struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8724 	u8 prio;
8725 
8726 	for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8727 		u8 tc = 0;
8728 
8729 		if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8730 			tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8731 		else if (ets)
8732 			tc = ets->prio_tc[prio];
8733 
8734 		netdev_set_prio_tc_map(dev, prio, tc);
8735 	}
8736 }
8737 
8738 #endif /* CONFIG_IXGBE_DCB */
8739 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data)
8740 {
8741 	struct ixgbe_adapter *adapter = data;
8742 	struct ixgbe_fwd_adapter *accel;
8743 	int pool;
8744 
8745 	/* we only care about macvlans... */
8746 	if (!netif_is_macvlan(vdev))
8747 		return 0;
8748 
8749 	/* that have hardware offload enabled... */
8750 	accel = macvlan_accel_priv(vdev);
8751 	if (!accel)
8752 		return 0;
8753 
8754 	/* If we can relocate to a different bit do so */
8755 	pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
8756 	if (pool < adapter->num_rx_pools) {
8757 		set_bit(pool, adapter->fwd_bitmask);
8758 		accel->pool = pool;
8759 		return 0;
8760 	}
8761 
8762 	/* if we cannot find a free pool then disable the offload */
8763 	netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
8764 	macvlan_release_l2fw_offload(vdev);
8765 	kfree(accel);
8766 
8767 	return 0;
8768 }
8769 
8770 static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
8771 {
8772 	struct ixgbe_adapter *adapter = netdev_priv(dev);
8773 
8774 	/* flush any stale bits out of the fwd bitmask */
8775 	bitmap_clear(adapter->fwd_bitmask, 1, 63);
8776 
8777 	/* walk through upper devices reassigning pools */
8778 	netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
8779 				      adapter);
8780 }
8781 
8782 /**
8783  * ixgbe_setup_tc - configure net_device for multiple traffic classes
8784  *
8785  * @dev: net device to configure
8786  * @tc: number of traffic classes to enable
8787  */
8788 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8789 {
8790 	struct ixgbe_adapter *adapter = netdev_priv(dev);
8791 	struct ixgbe_hw *hw = &adapter->hw;
8792 
8793 	/* Hardware supports up to 8 traffic classes */
8794 	if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8795 		return -EINVAL;
8796 
8797 	if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8798 		return -EINVAL;
8799 
8800 	/* Hardware has to reinitialize queues and interrupts to
8801 	 * match packet buffer alignment. Unfortunately, the
8802 	 * hardware is not flexible enough to do this dynamically.
8803 	 */
8804 	if (netif_running(dev))
8805 		ixgbe_close(dev);
8806 	else
8807 		ixgbe_reset(adapter);
8808 
8809 	ixgbe_clear_interrupt_scheme(adapter);
8810 
8811 #ifdef CONFIG_IXGBE_DCB
8812 	if (tc) {
8813 		netdev_set_num_tc(dev, tc);
8814 		ixgbe_set_prio_tc_map(adapter);
8815 
8816 		adapter->hw_tcs = tc;
8817 		adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
8818 
8819 		if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8820 			adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
8821 			adapter->hw.fc.requested_mode = ixgbe_fc_none;
8822 		}
8823 	} else {
8824 		netdev_reset_tc(dev);
8825 
8826 		if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8827 			adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
8828 
8829 		adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
8830 		adapter->hw_tcs = tc;
8831 
8832 		adapter->temp_dcb_cfg.pfc_mode_enable = false;
8833 		adapter->dcb_cfg.pfc_mode_enable = false;
8834 	}
8835 
8836 	ixgbe_validate_rtr(adapter, tc);
8837 
8838 #endif /* CONFIG_IXGBE_DCB */
8839 	ixgbe_init_interrupt_scheme(adapter);
8840 
8841 	ixgbe_defrag_macvlan_pools(dev);
8842 
8843 	if (netif_running(dev))
8844 		return ixgbe_open(dev);
8845 
8846 	return 0;
8847 }
8848 
8849 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8850 			       struct tc_cls_u32_offload *cls)
8851 {
8852 	u32 hdl = cls->knode.handle;
8853 	u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
8854 	u32 loc = cls->knode.handle & 0xfffff;
8855 	int err = 0, i, j;
8856 	struct ixgbe_jump_table *jump = NULL;
8857 
8858 	if (loc > IXGBE_MAX_HW_ENTRIES)
8859 		return -EINVAL;
8860 
8861 	if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8862 		return -EINVAL;
8863 
8864 	/* Clear this filter in the link data it is associated with */
8865 	if (uhtid != 0x800) {
8866 		jump = adapter->jump_tables[uhtid];
8867 		if (!jump)
8868 			return -EINVAL;
8869 		if (!test_bit(loc - 1, jump->child_loc_map))
8870 			return -EINVAL;
8871 		clear_bit(loc - 1, jump->child_loc_map);
8872 	}
8873 
8874 	/* Check if the filter being deleted is a link */
8875 	for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
8876 		jump = adapter->jump_tables[i];
8877 		if (jump && jump->link_hdl == hdl) {
8878 			/* Delete filters in the hardware in the child hash
8879 			 * table associated with this link
8880 			 */
8881 			for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
8882 				if (!test_bit(j, jump->child_loc_map))
8883 					continue;
8884 				spin_lock(&adapter->fdir_perfect_lock);
8885 				err = ixgbe_update_ethtool_fdir_entry(adapter,
8886 								      NULL,
8887 								      j + 1);
8888 				spin_unlock(&adapter->fdir_perfect_lock);
8889 				clear_bit(j, jump->child_loc_map);
8890 			}
8891 			/* Remove resources for this link */
8892 			kfree(jump->input);
8893 			kfree(jump->mask);
8894 			kfree(jump);
8895 			adapter->jump_tables[i] = NULL;
8896 			return err;
8897 		}
8898 	}
8899 
8900 	spin_lock(&adapter->fdir_perfect_lock);
8901 	err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
8902 	spin_unlock(&adapter->fdir_perfect_lock);
8903 	return err;
8904 }
8905 
8906 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8907 					    struct tc_cls_u32_offload *cls)
8908 {
8909 	u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8910 
8911 	if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8912 		return -EINVAL;
8913 
8914 	/* This ixgbe devices do not support hash tables at the moment
8915 	 * so abort when given hash tables.
8916 	 */
8917 	if (cls->hnode.divisor > 0)
8918 		return -EINVAL;
8919 
8920 	set_bit(uhtid - 1, &adapter->tables);
8921 	return 0;
8922 }
8923 
8924 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8925 					    struct tc_cls_u32_offload *cls)
8926 {
8927 	u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8928 
8929 	if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8930 		return -EINVAL;
8931 
8932 	clear_bit(uhtid - 1, &adapter->tables);
8933 	return 0;
8934 }
8935 
8936 #ifdef CONFIG_NET_CLS_ACT
8937 struct upper_walk_data {
8938 	struct ixgbe_adapter *adapter;
8939 	u64 action;
8940 	int ifindex;
8941 	u8 queue;
8942 };
8943 
8944 static int get_macvlan_queue(struct net_device *upper, void *_data)
8945 {
8946 	if (netif_is_macvlan(upper)) {
8947 		struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
8948 		struct upper_walk_data *data = _data;
8949 		struct ixgbe_adapter *adapter = data->adapter;
8950 		int ifindex = data->ifindex;
8951 
8952 		if (vadapter && upper->ifindex == ifindex) {
8953 			data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
8954 			data->action = data->queue;
8955 			return 1;
8956 		}
8957 	}
8958 
8959 	return 0;
8960 }
8961 
8962 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
8963 				  u8 *queue, u64 *action)
8964 {
8965 	struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
8966 	unsigned int num_vfs = adapter->num_vfs, vf;
8967 	struct upper_walk_data data;
8968 	struct net_device *upper;
8969 
8970 	/* redirect to a SRIOV VF */
8971 	for (vf = 0; vf < num_vfs; ++vf) {
8972 		upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
8973 		if (upper->ifindex == ifindex) {
8974 			*queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
8975 			*action = vf + 1;
8976 			*action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
8977 			return 0;
8978 		}
8979 	}
8980 
8981 	/* redirect to a offloaded macvlan netdev */
8982 	data.adapter = adapter;
8983 	data.ifindex = ifindex;
8984 	data.action = 0;
8985 	data.queue = 0;
8986 	if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
8987 					  get_macvlan_queue, &data)) {
8988 		*action = data.action;
8989 		*queue = data.queue;
8990 
8991 		return 0;
8992 	}
8993 
8994 	return -EINVAL;
8995 }
8996 
8997 static int parse_tc_actions(struct ixgbe_adapter *adapter,
8998 			    struct tcf_exts *exts, u64 *action, u8 *queue)
8999 {
9000 	const struct tc_action *a;
9001 	LIST_HEAD(actions);
9002 
9003 	if (!tcf_exts_has_actions(exts))
9004 		return -EINVAL;
9005 
9006 	tcf_exts_to_list(exts, &actions);
9007 	list_for_each_entry(a, &actions, list) {
9008 
9009 		/* Drop action */
9010 		if (is_tcf_gact_shot(a)) {
9011 			*action = IXGBE_FDIR_DROP_QUEUE;
9012 			*queue = IXGBE_FDIR_DROP_QUEUE;
9013 			return 0;
9014 		}
9015 
9016 		/* Redirect to a VF or a offloaded macvlan */
9017 		if (is_tcf_mirred_egress_redirect(a)) {
9018 			struct net_device *dev = tcf_mirred_dev(a);
9019 
9020 			if (!dev)
9021 				return -EINVAL;
9022 			return handle_redirect_action(adapter, dev->ifindex,
9023 						      queue, action);
9024 		}
9025 
9026 		return -EINVAL;
9027 	}
9028 
9029 	return -EINVAL;
9030 }
9031 #else
9032 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9033 			    struct tcf_exts *exts, u64 *action, u8 *queue)
9034 {
9035 	return -EINVAL;
9036 }
9037 #endif /* CONFIG_NET_CLS_ACT */
9038 
9039 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9040 				    union ixgbe_atr_input *mask,
9041 				    struct tc_cls_u32_offload *cls,
9042 				    struct ixgbe_mat_field *field_ptr,
9043 				    struct ixgbe_nexthdr *nexthdr)
9044 {
9045 	int i, j, off;
9046 	__be32 val, m;
9047 	bool found_entry = false, found_jump_field = false;
9048 
9049 	for (i = 0; i < cls->knode.sel->nkeys; i++) {
9050 		off = cls->knode.sel->keys[i].off;
9051 		val = cls->knode.sel->keys[i].val;
9052 		m = cls->knode.sel->keys[i].mask;
9053 
9054 		for (j = 0; field_ptr[j].val; j++) {
9055 			if (field_ptr[j].off == off) {
9056 				field_ptr[j].val(input, mask, (__force u32)val,
9057 						 (__force u32)m);
9058 				input->filter.formatted.flow_type |=
9059 					field_ptr[j].type;
9060 				found_entry = true;
9061 				break;
9062 			}
9063 		}
9064 		if (nexthdr) {
9065 			if (nexthdr->off == cls->knode.sel->keys[i].off &&
9066 			    nexthdr->val ==
9067 			    (__force u32)cls->knode.sel->keys[i].val &&
9068 			    nexthdr->mask ==
9069 			    (__force u32)cls->knode.sel->keys[i].mask)
9070 				found_jump_field = true;
9071 			else
9072 				continue;
9073 		}
9074 	}
9075 
9076 	if (nexthdr && !found_jump_field)
9077 		return -EINVAL;
9078 
9079 	if (!found_entry)
9080 		return 0;
9081 
9082 	mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9083 				    IXGBE_ATR_L4TYPE_MASK;
9084 
9085 	if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9086 		mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9087 
9088 	return 0;
9089 }
9090 
9091 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
9092 				  struct tc_cls_u32_offload *cls)
9093 {
9094 	__be16 protocol = cls->common.protocol;
9095 	u32 loc = cls->knode.handle & 0xfffff;
9096 	struct ixgbe_hw *hw = &adapter->hw;
9097 	struct ixgbe_mat_field *field_ptr;
9098 	struct ixgbe_fdir_filter *input = NULL;
9099 	union ixgbe_atr_input *mask = NULL;
9100 	struct ixgbe_jump_table *jump = NULL;
9101 	int i, err = -EINVAL;
9102 	u8 queue;
9103 	u32 uhtid, link_uhtid;
9104 
9105 	uhtid = TC_U32_USERHTID(cls->knode.handle);
9106 	link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
9107 
9108 	/* At the moment cls_u32 jumps to network layer and skips past
9109 	 * L2 headers. The canonical method to match L2 frames is to use
9110 	 * negative values. However this is error prone at best but really
9111 	 * just broken because there is no way to "know" what sort of hdr
9112 	 * is in front of the network layer. Fix cls_u32 to support L2
9113 	 * headers when needed.
9114 	 */
9115 	if (protocol != htons(ETH_P_IP))
9116 		return err;
9117 
9118 	if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9119 		e_err(drv, "Location out of range\n");
9120 		return err;
9121 	}
9122 
9123 	/* cls u32 is a graph starting at root node 0x800. The driver tracks
9124 	 * links and also the fields used to advance the parser across each
9125 	 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9126 	 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9127 	 * To add support for new nodes update ixgbe_model.h parse structures
9128 	 * this function _should_ be generic try not to hardcode values here.
9129 	 */
9130 	if (uhtid == 0x800) {
9131 		field_ptr = (adapter->jump_tables[0])->mat;
9132 	} else {
9133 		if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9134 			return err;
9135 		if (!adapter->jump_tables[uhtid])
9136 			return err;
9137 		field_ptr = (adapter->jump_tables[uhtid])->mat;
9138 	}
9139 
9140 	if (!field_ptr)
9141 		return err;
9142 
9143 	/* At this point we know the field_ptr is valid and need to either
9144 	 * build cls_u32 link or attach filter. Because adding a link to
9145 	 * a handle that does not exist is invalid and the same for adding
9146 	 * rules to handles that don't exist.
9147 	 */
9148 
9149 	if (link_uhtid) {
9150 		struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
9151 
9152 		if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9153 			return err;
9154 
9155 		if (!test_bit(link_uhtid - 1, &adapter->tables))
9156 			return err;
9157 
9158 		/* Multiple filters as links to the same hash table are not
9159 		 * supported. To add a new filter with the same next header
9160 		 * but different match/jump conditions, create a new hash table
9161 		 * and link to it.
9162 		 */
9163 		if (adapter->jump_tables[link_uhtid] &&
9164 		    (adapter->jump_tables[link_uhtid])->link_hdl) {
9165 			e_err(drv, "Link filter exists for link: %x\n",
9166 			      link_uhtid);
9167 			return err;
9168 		}
9169 
9170 		for (i = 0; nexthdr[i].jump; i++) {
9171 			if (nexthdr[i].o != cls->knode.sel->offoff ||
9172 			    nexthdr[i].s != cls->knode.sel->offshift ||
9173 			    nexthdr[i].m !=
9174 			    (__force u32)cls->knode.sel->offmask)
9175 				return err;
9176 
9177 			jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9178 			if (!jump)
9179 				return -ENOMEM;
9180 			input = kzalloc(sizeof(*input), GFP_KERNEL);
9181 			if (!input) {
9182 				err = -ENOMEM;
9183 				goto free_jump;
9184 			}
9185 			mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9186 			if (!mask) {
9187 				err = -ENOMEM;
9188 				goto free_input;
9189 			}
9190 			jump->input = input;
9191 			jump->mask = mask;
9192 			jump->link_hdl = cls->knode.handle;
9193 
9194 			err = ixgbe_clsu32_build_input(input, mask, cls,
9195 						       field_ptr, &nexthdr[i]);
9196 			if (!err) {
9197 				jump->mat = nexthdr[i].jump;
9198 				adapter->jump_tables[link_uhtid] = jump;
9199 				break;
9200 			}
9201 		}
9202 		return 0;
9203 	}
9204 
9205 	input = kzalloc(sizeof(*input), GFP_KERNEL);
9206 	if (!input)
9207 		return -ENOMEM;
9208 	mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9209 	if (!mask) {
9210 		err = -ENOMEM;
9211 		goto free_input;
9212 	}
9213 
9214 	if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9215 		if ((adapter->jump_tables[uhtid])->input)
9216 			memcpy(input, (adapter->jump_tables[uhtid])->input,
9217 			       sizeof(*input));
9218 		if ((adapter->jump_tables[uhtid])->mask)
9219 			memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9220 			       sizeof(*mask));
9221 
9222 		/* Lookup in all child hash tables if this location is already
9223 		 * filled with a filter
9224 		 */
9225 		for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9226 			struct ixgbe_jump_table *link = adapter->jump_tables[i];
9227 
9228 			if (link && (test_bit(loc - 1, link->child_loc_map))) {
9229 				e_err(drv, "Filter exists in location: %x\n",
9230 				      loc);
9231 				err = -EINVAL;
9232 				goto err_out;
9233 			}
9234 		}
9235 	}
9236 	err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9237 	if (err)
9238 		goto err_out;
9239 
9240 	err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9241 			       &queue);
9242 	if (err < 0)
9243 		goto err_out;
9244 
9245 	input->sw_idx = loc;
9246 
9247 	spin_lock(&adapter->fdir_perfect_lock);
9248 
9249 	if (hlist_empty(&adapter->fdir_filter_list)) {
9250 		memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9251 		err = ixgbe_fdir_set_input_mask_82599(hw, mask);
9252 		if (err)
9253 			goto err_out_w_lock;
9254 	} else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
9255 		err = -EINVAL;
9256 		goto err_out_w_lock;
9257 	}
9258 
9259 	ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
9260 	err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9261 						    input->sw_idx, queue);
9262 	if (!err)
9263 		ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9264 	spin_unlock(&adapter->fdir_perfect_lock);
9265 
9266 	if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9267 		set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
9268 
9269 	kfree(mask);
9270 	return err;
9271 err_out_w_lock:
9272 	spin_unlock(&adapter->fdir_perfect_lock);
9273 err_out:
9274 	kfree(mask);
9275 free_input:
9276 	kfree(input);
9277 free_jump:
9278 	kfree(jump);
9279 	return err;
9280 }
9281 
9282 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
9283 				  struct tc_cls_u32_offload *cls_u32)
9284 {
9285 	switch (cls_u32->command) {
9286 	case TC_CLSU32_NEW_KNODE:
9287 	case TC_CLSU32_REPLACE_KNODE:
9288 		return ixgbe_configure_clsu32(adapter, cls_u32);
9289 	case TC_CLSU32_DELETE_KNODE:
9290 		return ixgbe_delete_clsu32(adapter, cls_u32);
9291 	case TC_CLSU32_NEW_HNODE:
9292 	case TC_CLSU32_REPLACE_HNODE:
9293 		return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
9294 	case TC_CLSU32_DELETE_HNODE:
9295 		return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9296 	default:
9297 		return -EOPNOTSUPP;
9298 	}
9299 }
9300 
9301 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9302 				   void *cb_priv)
9303 {
9304 	struct ixgbe_adapter *adapter = cb_priv;
9305 
9306 	if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
9307 		return -EOPNOTSUPP;
9308 
9309 	switch (type) {
9310 	case TC_SETUP_CLSU32:
9311 		return ixgbe_setup_tc_cls_u32(adapter, type_data);
9312 	default:
9313 		return -EOPNOTSUPP;
9314 	}
9315 }
9316 
9317 static int ixgbe_setup_tc_block(struct net_device *dev,
9318 				struct tc_block_offload *f)
9319 {
9320 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9321 
9322 	if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9323 		return -EOPNOTSUPP;
9324 
9325 	switch (f->command) {
9326 	case TC_BLOCK_BIND:
9327 		return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb,
9328 					     adapter, adapter);
9329 	case TC_BLOCK_UNBIND:
9330 		tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb,
9331 					adapter);
9332 		return 0;
9333 	default:
9334 		return -EOPNOTSUPP;
9335 	}
9336 }
9337 
9338 static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9339 				 struct tc_mqprio_qopt *mqprio)
9340 {
9341 	mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9342 	return ixgbe_setup_tc(dev, mqprio->num_tc);
9343 }
9344 
9345 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
9346 			    void *type_data)
9347 {
9348 	switch (type) {
9349 	case TC_SETUP_BLOCK:
9350 		return ixgbe_setup_tc_block(dev, type_data);
9351 	case TC_SETUP_QDISC_MQPRIO:
9352 		return ixgbe_setup_tc_mqprio(dev, type_data);
9353 	default:
9354 		return -EOPNOTSUPP;
9355 	}
9356 }
9357 
9358 #ifdef CONFIG_PCI_IOV
9359 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9360 {
9361 	struct net_device *netdev = adapter->netdev;
9362 
9363 	rtnl_lock();
9364 	ixgbe_setup_tc(netdev, adapter->hw_tcs);
9365 	rtnl_unlock();
9366 }
9367 
9368 #endif
9369 void ixgbe_do_reset(struct net_device *netdev)
9370 {
9371 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
9372 
9373 	if (netif_running(netdev))
9374 		ixgbe_reinit_locked(adapter);
9375 	else
9376 		ixgbe_reset(adapter);
9377 }
9378 
9379 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
9380 					    netdev_features_t features)
9381 {
9382 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
9383 
9384 	/* If Rx checksum is disabled, then RSC/LRO should also be disabled */
9385 	if (!(features & NETIF_F_RXCSUM))
9386 		features &= ~NETIF_F_LRO;
9387 
9388 	/* Turn off LRO if not RSC capable */
9389 	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9390 		features &= ~NETIF_F_LRO;
9391 
9392 	return features;
9393 }
9394 
9395 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9396 {
9397 	int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9398 			num_online_cpus());
9399 
9400 	/* go back to full RSS if we're not running SR-IOV */
9401 	if (!adapter->ring_feature[RING_F_VMDQ].offset)
9402 		adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9403 				    IXGBE_FLAG_SRIOV_ENABLED);
9404 
9405 	adapter->ring_feature[RING_F_RSS].limit = rss;
9406 	adapter->ring_feature[RING_F_VMDQ].limit = 1;
9407 
9408 	ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9409 }
9410 
9411 static int ixgbe_set_features(struct net_device *netdev,
9412 			      netdev_features_t features)
9413 {
9414 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
9415 	netdev_features_t changed = netdev->features ^ features;
9416 	bool need_reset = false;
9417 
9418 	/* Make sure RSC matches LRO, reset if change */
9419 	if (!(features & NETIF_F_LRO)) {
9420 		if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9421 			need_reset = true;
9422 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9423 	} else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9424 		   !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9425 		if (adapter->rx_itr_setting == 1 ||
9426 		    adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9427 			adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9428 			need_reset = true;
9429 		} else if ((changed ^ features) & NETIF_F_LRO) {
9430 			e_info(probe, "rx-usecs set too low, "
9431 			       "disabling RSC\n");
9432 		}
9433 	}
9434 
9435 	/*
9436 	 * Check if Flow Director n-tuple support or hw_tc support was
9437 	 * enabled or disabled.  If the state changed, we need to reset.
9438 	 */
9439 	if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
9440 		/* turn off ATR, enable perfect filters and reset */
9441 		if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9442 			need_reset = true;
9443 
9444 		adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9445 		adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9446 	} else {
9447 		/* turn off perfect filters, enable ATR and reset */
9448 		if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9449 			need_reset = true;
9450 
9451 		adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9452 
9453 		/* We cannot enable ATR if SR-IOV is enabled */
9454 		if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9455 		    /* We cannot enable ATR if we have 2 or more tcs */
9456 		    (adapter->hw_tcs > 1) ||
9457 		    /* We cannot enable ATR if RSS is disabled */
9458 		    (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9459 		    /* A sample rate of 0 indicates ATR disabled */
9460 		    (!adapter->atr_sample_rate))
9461 			; /* do nothing not supported */
9462 		else /* otherwise supported and set the flag */
9463 			adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9464 	}
9465 
9466 	if (changed & NETIF_F_RXALL)
9467 		need_reset = true;
9468 
9469 	netdev->features = features;
9470 
9471 	if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
9472 		if (features & NETIF_F_RXCSUM) {
9473 			adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9474 		} else {
9475 			u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9476 
9477 			ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9478 		}
9479 	}
9480 
9481 	if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) {
9482 		if (features & NETIF_F_RXCSUM) {
9483 			adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9484 		} else {
9485 			u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9486 
9487 			ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9488 		}
9489 	}
9490 
9491 	if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9492 		ixgbe_reset_l2fw_offload(adapter);
9493 	else if (need_reset)
9494 		ixgbe_do_reset(netdev);
9495 	else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9496 			    NETIF_F_HW_VLAN_CTAG_FILTER))
9497 		ixgbe_set_rx_mode(netdev);
9498 
9499 	return 0;
9500 }
9501 
9502 /**
9503  * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports
9504  * @dev: The port's netdev
9505  * @ti: Tunnel endpoint information
9506  **/
9507 static void ixgbe_add_udp_tunnel_port(struct net_device *dev,
9508 				      struct udp_tunnel_info *ti)
9509 {
9510 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9511 	struct ixgbe_hw *hw = &adapter->hw;
9512 	__be16 port = ti->port;
9513 	u32 port_shift = 0;
9514 	u32 reg;
9515 
9516 	if (ti->sa_family != AF_INET)
9517 		return;
9518 
9519 	switch (ti->type) {
9520 	case UDP_TUNNEL_TYPE_VXLAN:
9521 		if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9522 			return;
9523 
9524 		if (adapter->vxlan_port == port)
9525 			return;
9526 
9527 		if (adapter->vxlan_port) {
9528 			netdev_info(dev,
9529 				    "VXLAN port %d set, not adding port %d\n",
9530 				    ntohs(adapter->vxlan_port),
9531 				    ntohs(port));
9532 			return;
9533 		}
9534 
9535 		adapter->vxlan_port = port;
9536 		break;
9537 	case UDP_TUNNEL_TYPE_GENEVE:
9538 		if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9539 			return;
9540 
9541 		if (adapter->geneve_port == port)
9542 			return;
9543 
9544 		if (adapter->geneve_port) {
9545 			netdev_info(dev,
9546 				    "GENEVE port %d set, not adding port %d\n",
9547 				    ntohs(adapter->geneve_port),
9548 				    ntohs(port));
9549 			return;
9550 		}
9551 
9552 		port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT;
9553 		adapter->geneve_port = port;
9554 		break;
9555 	default:
9556 		return;
9557 	}
9558 
9559 	reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift;
9560 	IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg);
9561 }
9562 
9563 /**
9564  * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports
9565  * @dev: The port's netdev
9566  * @ti: Tunnel endpoint information
9567  **/
9568 static void ixgbe_del_udp_tunnel_port(struct net_device *dev,
9569 				      struct udp_tunnel_info *ti)
9570 {
9571 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9572 	u32 port_mask;
9573 
9574 	if (ti->type != UDP_TUNNEL_TYPE_VXLAN &&
9575 	    ti->type != UDP_TUNNEL_TYPE_GENEVE)
9576 		return;
9577 
9578 	if (ti->sa_family != AF_INET)
9579 		return;
9580 
9581 	switch (ti->type) {
9582 	case UDP_TUNNEL_TYPE_VXLAN:
9583 		if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
9584 			return;
9585 
9586 		if (adapter->vxlan_port != ti->port) {
9587 			netdev_info(dev, "VXLAN port %d not found\n",
9588 				    ntohs(ti->port));
9589 			return;
9590 		}
9591 
9592 		port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK;
9593 		break;
9594 	case UDP_TUNNEL_TYPE_GENEVE:
9595 		if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))
9596 			return;
9597 
9598 		if (adapter->geneve_port != ti->port) {
9599 			netdev_info(dev, "GENEVE port %d not found\n",
9600 				    ntohs(ti->port));
9601 			return;
9602 		}
9603 
9604 		port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK;
9605 		break;
9606 	default:
9607 		return;
9608 	}
9609 
9610 	ixgbe_clear_udp_tunnel_port(adapter, port_mask);
9611 	adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED;
9612 }
9613 
9614 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
9615 			     struct net_device *dev,
9616 			     const unsigned char *addr, u16 vid,
9617 			     u16 flags)
9618 {
9619 	/* guarantee we can provide a unique filter for the unicast address */
9620 	if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
9621 		struct ixgbe_adapter *adapter = netdev_priv(dev);
9622 		u16 pool = VMDQ_P(0);
9623 
9624 		if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
9625 			return -ENOMEM;
9626 	}
9627 
9628 	return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
9629 }
9630 
9631 /**
9632  * ixgbe_configure_bridge_mode - set various bridge modes
9633  * @adapter: the private structure
9634  * @mode: requested bridge mode
9635  *
9636  * Configure some settings require for various bridge modes.
9637  **/
9638 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9639 				       __u16 mode)
9640 {
9641 	struct ixgbe_hw *hw = &adapter->hw;
9642 	unsigned int p, num_pools;
9643 	u32 vmdctl;
9644 
9645 	switch (mode) {
9646 	case BRIDGE_MODE_VEPA:
9647 		/* disable Tx loopback, rely on switch hairpin mode */
9648 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
9649 
9650 		/* must enable Rx switching replication to allow multicast
9651 		 * packet reception on all VFs, and to enable source address
9652 		 * pruning.
9653 		 */
9654 		vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9655 		vmdctl |= IXGBE_VT_CTL_REPLEN;
9656 		IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9657 
9658 		/* enable Rx source address pruning. Note, this requires
9659 		 * replication to be enabled or else it does nothing.
9660 		 */
9661 		num_pools = adapter->num_vfs + adapter->num_rx_pools;
9662 		for (p = 0; p < num_pools; p++) {
9663 			if (hw->mac.ops.set_source_address_pruning)
9664 				hw->mac.ops.set_source_address_pruning(hw,
9665 								       true,
9666 								       p);
9667 		}
9668 		break;
9669 	case BRIDGE_MODE_VEB:
9670 		/* enable Tx loopback for internal VF/PF communication */
9671 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
9672 				IXGBE_PFDTXGSWC_VT_LBEN);
9673 
9674 		/* disable Rx switching replication unless we have SR-IOV
9675 		 * virtual functions
9676 		 */
9677 		vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9678 		if (!adapter->num_vfs)
9679 			vmdctl &= ~IXGBE_VT_CTL_REPLEN;
9680 		IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9681 
9682 		/* disable Rx source address pruning, since we don't expect to
9683 		 * be receiving external loopback of our transmitted frames.
9684 		 */
9685 		num_pools = adapter->num_vfs + adapter->num_rx_pools;
9686 		for (p = 0; p < num_pools; p++) {
9687 			if (hw->mac.ops.set_source_address_pruning)
9688 				hw->mac.ops.set_source_address_pruning(hw,
9689 								       false,
9690 								       p);
9691 		}
9692 		break;
9693 	default:
9694 		return -EINVAL;
9695 	}
9696 
9697 	adapter->bridge_mode = mode;
9698 
9699 	e_info(drv, "enabling bridge mode: %s\n",
9700 	       mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
9701 
9702 	return 0;
9703 }
9704 
9705 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
9706 				    struct nlmsghdr *nlh, u16 flags)
9707 {
9708 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9709 	struct nlattr *attr, *br_spec;
9710 	int rem;
9711 
9712 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9713 		return -EOPNOTSUPP;
9714 
9715 	br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
9716 	if (!br_spec)
9717 		return -EINVAL;
9718 
9719 	nla_for_each_nested(attr, br_spec, rem) {
9720 		int status;
9721 		__u16 mode;
9722 
9723 		if (nla_type(attr) != IFLA_BRIDGE_MODE)
9724 			continue;
9725 
9726 		if (nla_len(attr) < sizeof(mode))
9727 			return -EINVAL;
9728 
9729 		mode = nla_get_u16(attr);
9730 		status = ixgbe_configure_bridge_mode(adapter, mode);
9731 		if (status)
9732 			return status;
9733 
9734 		break;
9735 	}
9736 
9737 	return 0;
9738 }
9739 
9740 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
9741 				    struct net_device *dev,
9742 				    u32 filter_mask, int nlflags)
9743 {
9744 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9745 
9746 	if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
9747 		return 0;
9748 
9749 	return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
9750 				       adapter->bridge_mode, 0, 0, nlflags,
9751 				       filter_mask, NULL);
9752 }
9753 
9754 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
9755 {
9756 	struct ixgbe_adapter *adapter = netdev_priv(pdev);
9757 	struct ixgbe_fwd_adapter *accel;
9758 	int tcs = adapter->hw_tcs ? : 1;
9759 	int pool, err;
9760 
9761 	/* The hardware supported by ixgbe only filters on the destination MAC
9762 	 * address. In order to avoid issues we only support offloading modes
9763 	 * where the hardware can actually provide the functionality.
9764 	 */
9765 	if (!macvlan_supports_dest_filter(vdev))
9766 		return ERR_PTR(-EMEDIUMTYPE);
9767 
9768 	pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9769 	if (pool == adapter->num_rx_pools) {
9770 		u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
9771 		u16 reserved_pools;
9772 
9773 		if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
9774 		     adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
9775 		    adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
9776 			return ERR_PTR(-EBUSY);
9777 
9778 		/* Hardware has a limited number of available pools. Each VF,
9779 		 * and the PF require a pool. Check to ensure we don't
9780 		 * attempt to use more then the available number of pools.
9781 		 */
9782 		if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
9783 			return ERR_PTR(-EBUSY);
9784 
9785 		/* Enable VMDq flag so device will be set in VM mode */
9786 		adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
9787 				  IXGBE_FLAG_SRIOV_ENABLED;
9788 
9789 		/* Try to reserve as many queues per pool as possible,
9790 		 * we start with the configurations that support 4 queues
9791 		 * per pools, followed by 2, and then by just 1 per pool.
9792 		 */
9793 		if (used_pools < 32 && adapter->num_rx_pools < 16)
9794 			reserved_pools = min_t(u16,
9795 					       32 - used_pools,
9796 					       16 - adapter->num_rx_pools);
9797 		else if (adapter->num_rx_pools < 32)
9798 			reserved_pools = min_t(u16,
9799 					       64 - used_pools,
9800 					       32 - adapter->num_rx_pools);
9801 		else
9802 			reserved_pools = 64 - used_pools;
9803 
9804 
9805 		if (!reserved_pools)
9806 			return ERR_PTR(-EBUSY);
9807 
9808 		adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
9809 
9810 		/* Force reinit of ring allocation with VMDQ enabled */
9811 		err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
9812 		if (err)
9813 			return ERR_PTR(err);
9814 
9815 		if (pool >= adapter->num_rx_pools)
9816 			return ERR_PTR(-ENOMEM);
9817 	}
9818 
9819 	accel = kzalloc(sizeof(*accel), GFP_KERNEL);
9820 	if (!accel)
9821 		return ERR_PTR(-ENOMEM);
9822 
9823 	set_bit(pool, adapter->fwd_bitmask);
9824 	accel->pool = pool;
9825 	accel->netdev = vdev;
9826 
9827 	if (!netif_running(pdev))
9828 		return accel;
9829 
9830 	err = ixgbe_fwd_ring_up(adapter, accel);
9831 	if (err)
9832 		return ERR_PTR(err);
9833 
9834 	return accel;
9835 }
9836 
9837 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
9838 {
9839 	struct ixgbe_fwd_adapter *accel = priv;
9840 	struct ixgbe_adapter *adapter = netdev_priv(pdev);
9841 	unsigned int rxbase = accel->rx_base_queue;
9842 	unsigned int i;
9843 
9844 	/* delete unicast filter associated with offloaded interface */
9845 	ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
9846 			     VMDQ_P(accel->pool));
9847 
9848 	/* Allow remaining Rx packets to get flushed out of the
9849 	 * Rx FIFO before we drop the netdev for the ring.
9850 	 */
9851 	usleep_range(10000, 20000);
9852 
9853 	for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
9854 		struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
9855 		struct ixgbe_q_vector *qv = ring->q_vector;
9856 
9857 		/* Make sure we aren't processing any packets and clear
9858 		 * netdev to shut down the ring.
9859 		 */
9860 		if (netif_running(adapter->netdev))
9861 			napi_synchronize(&qv->napi);
9862 		ring->netdev = NULL;
9863 	}
9864 
9865 	clear_bit(accel->pool, adapter->fwd_bitmask);
9866 	kfree(accel);
9867 }
9868 
9869 #define IXGBE_MAX_MAC_HDR_LEN		127
9870 #define IXGBE_MAX_NETWORK_HDR_LEN	511
9871 
9872 static netdev_features_t
9873 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
9874 		     netdev_features_t features)
9875 {
9876 	unsigned int network_hdr_len, mac_hdr_len;
9877 
9878 	/* Make certain the headers can be described by a context descriptor */
9879 	mac_hdr_len = skb_network_header(skb) - skb->data;
9880 	if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
9881 		return features & ~(NETIF_F_HW_CSUM |
9882 				    NETIF_F_SCTP_CRC |
9883 				    NETIF_F_HW_VLAN_CTAG_TX |
9884 				    NETIF_F_TSO |
9885 				    NETIF_F_TSO6);
9886 
9887 	network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
9888 	if (unlikely(network_hdr_len >  IXGBE_MAX_NETWORK_HDR_LEN))
9889 		return features & ~(NETIF_F_HW_CSUM |
9890 				    NETIF_F_SCTP_CRC |
9891 				    NETIF_F_TSO |
9892 				    NETIF_F_TSO6);
9893 
9894 	/* We can only support IPV4 TSO in tunnels if we can mangle the
9895 	 * inner IP ID field, so strip TSO if MANGLEID is not supported.
9896 	 * IPsec offoad sets skb->encapsulation but still can handle
9897 	 * the TSO, so it's the exception.
9898 	 */
9899 	if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
9900 #ifdef CONFIG_XFRM_OFFLOAD
9901 		if (!skb->sp)
9902 #endif
9903 			features &= ~NETIF_F_TSO;
9904 	}
9905 
9906 	return features;
9907 }
9908 
9909 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
9910 {
9911 	int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9912 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9913 	struct bpf_prog *old_prog;
9914 
9915 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
9916 		return -EINVAL;
9917 
9918 	if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
9919 		return -EINVAL;
9920 
9921 	/* verify ixgbe ring attributes are sufficient for XDP */
9922 	for (i = 0; i < adapter->num_rx_queues; i++) {
9923 		struct ixgbe_ring *ring = adapter->rx_ring[i];
9924 
9925 		if (ring_is_rsc_enabled(ring))
9926 			return -EINVAL;
9927 
9928 		if (frame_size > ixgbe_rx_bufsz(ring))
9929 			return -EINVAL;
9930 	}
9931 
9932 	if (nr_cpu_ids > MAX_XDP_QUEUES)
9933 		return -ENOMEM;
9934 
9935 	old_prog = xchg(&adapter->xdp_prog, prog);
9936 
9937 	/* If transitioning XDP modes reconfigure rings */
9938 	if (!!prog != !!old_prog) {
9939 		int err = ixgbe_setup_tc(dev, adapter->hw_tcs);
9940 
9941 		if (err) {
9942 			rcu_assign_pointer(adapter->xdp_prog, old_prog);
9943 			return -EINVAL;
9944 		}
9945 	} else {
9946 		for (i = 0; i < adapter->num_rx_queues; i++)
9947 			(void)xchg(&adapter->rx_ring[i]->xdp_prog,
9948 			    adapter->xdp_prog);
9949 	}
9950 
9951 	if (old_prog)
9952 		bpf_prog_put(old_prog);
9953 
9954 	return 0;
9955 }
9956 
9957 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
9958 {
9959 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9960 
9961 	switch (xdp->command) {
9962 	case XDP_SETUP_PROG:
9963 		return ixgbe_xdp_setup(dev, xdp->prog);
9964 	case XDP_QUERY_PROG:
9965 		xdp->prog_attached = !!(adapter->xdp_prog);
9966 		xdp->prog_id = adapter->xdp_prog ?
9967 			adapter->xdp_prog->aux->id : 0;
9968 		return 0;
9969 	default:
9970 		return -EINVAL;
9971 	}
9972 }
9973 
9974 static void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
9975 {
9976 	/* Force memory writes to complete before letting h/w know there
9977 	 * are new descriptors to fetch.
9978 	 */
9979 	wmb();
9980 	writel(ring->next_to_use, ring->tail);
9981 }
9982 
9983 static int ixgbe_xdp_xmit(struct net_device *dev, int n,
9984 			  struct xdp_frame **frames, u32 flags)
9985 {
9986 	struct ixgbe_adapter *adapter = netdev_priv(dev);
9987 	struct ixgbe_ring *ring;
9988 	int drops = 0;
9989 	int i;
9990 
9991 	if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
9992 		return -ENETDOWN;
9993 
9994 	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
9995 		return -EINVAL;
9996 
9997 	/* During program transitions its possible adapter->xdp_prog is assigned
9998 	 * but ring has not been configured yet. In this case simply abort xmit.
9999 	 */
10000 	ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL;
10001 	if (unlikely(!ring))
10002 		return -ENXIO;
10003 
10004 	for (i = 0; i < n; i++) {
10005 		struct xdp_frame *xdpf = frames[i];
10006 		int err;
10007 
10008 		err = ixgbe_xmit_xdp_ring(adapter, xdpf);
10009 		if (err != IXGBE_XDP_TX) {
10010 			xdp_return_frame_rx_napi(xdpf);
10011 			drops++;
10012 		}
10013 	}
10014 
10015 	if (unlikely(flags & XDP_XMIT_FLUSH))
10016 		ixgbe_xdp_ring_update_tail(ring);
10017 
10018 	return n - drops;
10019 }
10020 
10021 static const struct net_device_ops ixgbe_netdev_ops = {
10022 	.ndo_open		= ixgbe_open,
10023 	.ndo_stop		= ixgbe_close,
10024 	.ndo_start_xmit		= ixgbe_xmit_frame,
10025 	.ndo_select_queue	= ixgbe_select_queue,
10026 	.ndo_set_rx_mode	= ixgbe_set_rx_mode,
10027 	.ndo_validate_addr	= eth_validate_addr,
10028 	.ndo_set_mac_address	= ixgbe_set_mac,
10029 	.ndo_change_mtu		= ixgbe_change_mtu,
10030 	.ndo_tx_timeout		= ixgbe_tx_timeout,
10031 	.ndo_set_tx_maxrate	= ixgbe_tx_maxrate,
10032 	.ndo_vlan_rx_add_vid	= ixgbe_vlan_rx_add_vid,
10033 	.ndo_vlan_rx_kill_vid	= ixgbe_vlan_rx_kill_vid,
10034 	.ndo_do_ioctl		= ixgbe_ioctl,
10035 	.ndo_set_vf_mac		= ixgbe_ndo_set_vf_mac,
10036 	.ndo_set_vf_vlan	= ixgbe_ndo_set_vf_vlan,
10037 	.ndo_set_vf_rate	= ixgbe_ndo_set_vf_bw,
10038 	.ndo_set_vf_spoofchk	= ixgbe_ndo_set_vf_spoofchk,
10039 	.ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
10040 	.ndo_set_vf_trust	= ixgbe_ndo_set_vf_trust,
10041 	.ndo_get_vf_config	= ixgbe_ndo_get_vf_config,
10042 	.ndo_get_stats64	= ixgbe_get_stats64,
10043 	.ndo_setup_tc		= __ixgbe_setup_tc,
10044 #ifdef CONFIG_NET_POLL_CONTROLLER
10045 	.ndo_poll_controller	= ixgbe_netpoll,
10046 #endif
10047 #ifdef IXGBE_FCOE
10048 	.ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
10049 	.ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
10050 	.ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
10051 	.ndo_fcoe_enable = ixgbe_fcoe_enable,
10052 	.ndo_fcoe_disable = ixgbe_fcoe_disable,
10053 	.ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
10054 	.ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
10055 #endif /* IXGBE_FCOE */
10056 	.ndo_set_features = ixgbe_set_features,
10057 	.ndo_fix_features = ixgbe_fix_features,
10058 	.ndo_fdb_add		= ixgbe_ndo_fdb_add,
10059 	.ndo_bridge_setlink	= ixgbe_ndo_bridge_setlink,
10060 	.ndo_bridge_getlink	= ixgbe_ndo_bridge_getlink,
10061 	.ndo_dfwd_add_station	= ixgbe_fwd_add,
10062 	.ndo_dfwd_del_station	= ixgbe_fwd_del,
10063 	.ndo_udp_tunnel_add	= ixgbe_add_udp_tunnel_port,
10064 	.ndo_udp_tunnel_del	= ixgbe_del_udp_tunnel_port,
10065 	.ndo_features_check	= ixgbe_features_check,
10066 	.ndo_bpf		= ixgbe_xdp,
10067 	.ndo_xdp_xmit		= ixgbe_xdp_xmit,
10068 };
10069 
10070 /**
10071  * ixgbe_enumerate_functions - Get the number of ports this device has
10072  * @adapter: adapter structure
10073  *
10074  * This function enumerates the phsyical functions co-located on a single slot,
10075  * in order to determine how many ports a device has. This is most useful in
10076  * determining the required GT/s of PCIe bandwidth necessary for optimal
10077  * performance.
10078  **/
10079 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10080 {
10081 	struct pci_dev *entry, *pdev = adapter->pdev;
10082 	int physfns = 0;
10083 
10084 	/* Some cards can not use the generic count PCIe functions method,
10085 	 * because they are behind a parent switch, so we hardcode these with
10086 	 * the correct number of functions.
10087 	 */
10088 	if (ixgbe_pcie_from_parent(&adapter->hw))
10089 		physfns = 4;
10090 
10091 	list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10092 		/* don't count virtual functions */
10093 		if (entry->is_virtfn)
10094 			continue;
10095 
10096 		/* When the devices on the bus don't all match our device ID,
10097 		 * we can't reliably determine the correct number of
10098 		 * functions. This can occur if a function has been direct
10099 		 * attached to a virtual machine using VT-d, for example. In
10100 		 * this case, simply return -1 to indicate this.
10101 		 */
10102 		if ((entry->vendor != pdev->vendor) ||
10103 		    (entry->device != pdev->device))
10104 			return -1;
10105 
10106 		physfns++;
10107 	}
10108 
10109 	return physfns;
10110 }
10111 
10112 /**
10113  * ixgbe_wol_supported - Check whether device supports WoL
10114  * @adapter: the adapter private structure
10115  * @device_id: the device ID
10116  * @subdevice_id: the subsystem device ID
10117  *
10118  * This function is used by probe and ethtool to determine
10119  * which devices have WoL support
10120  *
10121  **/
10122 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10123 			 u16 subdevice_id)
10124 {
10125 	struct ixgbe_hw *hw = &adapter->hw;
10126 	u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
10127 
10128 	/* WOL not supported on 82598 */
10129 	if (hw->mac.type == ixgbe_mac_82598EB)
10130 		return false;
10131 
10132 	/* check eeprom to see if WOL is enabled for X540 and newer */
10133 	if (hw->mac.type >= ixgbe_mac_X540) {
10134 		if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10135 		    ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10136 		     (hw->bus.func == 0)))
10137 			return true;
10138 	}
10139 
10140 	/* WOL is determined based on device IDs for 82599 MACs */
10141 	switch (device_id) {
10142 	case IXGBE_DEV_ID_82599_SFP:
10143 		/* Only these subdevices could supports WOL */
10144 		switch (subdevice_id) {
10145 		case IXGBE_SUBDEV_ID_82599_560FLR:
10146 		case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10147 		case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10148 		case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
10149 			/* only support first port */
10150 			if (hw->bus.func != 0)
10151 				break;
10152 			/* fall through */
10153 		case IXGBE_SUBDEV_ID_82599_SP_560FLR:
10154 		case IXGBE_SUBDEV_ID_82599_SFP:
10155 		case IXGBE_SUBDEV_ID_82599_RNDC:
10156 		case IXGBE_SUBDEV_ID_82599_ECNA_DP:
10157 		case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10158 		case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10159 		case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
10160 			return true;
10161 		}
10162 		break;
10163 	case IXGBE_DEV_ID_82599EN_SFP:
10164 		/* Only these subdevices support WOL */
10165 		switch (subdevice_id) {
10166 		case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
10167 			return true;
10168 		}
10169 		break;
10170 	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10171 		/* All except this subdevice support WOL */
10172 		if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
10173 			return true;
10174 		break;
10175 	case IXGBE_DEV_ID_82599_KX4:
10176 		return  true;
10177 	default:
10178 		break;
10179 	}
10180 
10181 	return false;
10182 }
10183 
10184 /**
10185  * ixgbe_set_fw_version - Set FW version
10186  * @adapter: the adapter private structure
10187  *
10188  * This function is used by probe and ethtool to determine the FW version to
10189  * format to display. The FW version is taken from the EEPROM/NVM.
10190  */
10191 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10192 {
10193 	struct ixgbe_hw *hw = &adapter->hw;
10194 	struct ixgbe_nvm_version nvm_ver;
10195 
10196 	ixgbe_get_oem_prod_version(hw, &nvm_ver);
10197 	if (nvm_ver.oem_valid) {
10198 		snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10199 			 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10200 			 nvm_ver.oem_release);
10201 		return;
10202 	}
10203 
10204 	ixgbe_get_etk_id(hw, &nvm_ver);
10205 	ixgbe_get_orom_version(hw, &nvm_ver);
10206 
10207 	if (nvm_ver.or_valid) {
10208 		snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10209 			 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10210 			 nvm_ver.or_build, nvm_ver.or_patch);
10211 		return;
10212 	}
10213 
10214 	/* Set ETrack ID format */
10215 	snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10216 		 "0x%08x", nvm_ver.etk_id);
10217 }
10218 
10219 /**
10220  * ixgbe_probe - Device Initialization Routine
10221  * @pdev: PCI device information struct
10222  * @ent: entry in ixgbe_pci_tbl
10223  *
10224  * Returns 0 on success, negative on failure
10225  *
10226  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10227  * The OS initialization, configuring of the adapter private structure,
10228  * and a hardware reset occur.
10229  **/
10230 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10231 {
10232 	struct net_device *netdev;
10233 	struct ixgbe_adapter *adapter = NULL;
10234 	struct ixgbe_hw *hw;
10235 	const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
10236 	int i, err, pci_using_dac, expected_gts;
10237 	unsigned int indices = MAX_TX_QUEUES;
10238 	u8 part_str[IXGBE_PBANUM_LENGTH];
10239 	bool disable_dev = false;
10240 #ifdef IXGBE_FCOE
10241 	u16 device_caps;
10242 #endif
10243 	u32 eec;
10244 
10245 	/* Catch broken hardware that put the wrong VF device ID in
10246 	 * the PCIe SR-IOV capability.
10247 	 */
10248 	if (pdev->is_virtfn) {
10249 		WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10250 		     pci_name(pdev), pdev->vendor, pdev->device);
10251 		return -EINVAL;
10252 	}
10253 
10254 	err = pci_enable_device_mem(pdev);
10255 	if (err)
10256 		return err;
10257 
10258 	if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
10259 		pci_using_dac = 1;
10260 	} else {
10261 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10262 		if (err) {
10263 			dev_err(&pdev->dev,
10264 				"No usable DMA configuration, aborting\n");
10265 			goto err_dma;
10266 		}
10267 		pci_using_dac = 0;
10268 	}
10269 
10270 	err = pci_request_mem_regions(pdev, ixgbe_driver_name);
10271 	if (err) {
10272 		dev_err(&pdev->dev,
10273 			"pci_request_selected_regions failed 0x%x\n", err);
10274 		goto err_pci_reg;
10275 	}
10276 
10277 	pci_enable_pcie_error_reporting(pdev);
10278 
10279 	pci_set_master(pdev);
10280 	pci_save_state(pdev);
10281 
10282 	if (ii->mac == ixgbe_mac_82598EB) {
10283 #ifdef CONFIG_IXGBE_DCB
10284 		/* 8 TC w/ 4 queues per TC */
10285 		indices = 4 * MAX_TRAFFIC_CLASS;
10286 #else
10287 		indices = IXGBE_MAX_RSS_INDICES;
10288 #endif
10289 	}
10290 
10291 	netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
10292 	if (!netdev) {
10293 		err = -ENOMEM;
10294 		goto err_alloc_etherdev;
10295 	}
10296 
10297 	SET_NETDEV_DEV(netdev, &pdev->dev);
10298 
10299 	adapter = netdev_priv(netdev);
10300 
10301 	adapter->netdev = netdev;
10302 	adapter->pdev = pdev;
10303 	hw = &adapter->hw;
10304 	hw->back = adapter;
10305 	adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
10306 
10307 	hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
10308 			      pci_resource_len(pdev, 0));
10309 	adapter->io_addr = hw->hw_addr;
10310 	if (!hw->hw_addr) {
10311 		err = -EIO;
10312 		goto err_ioremap;
10313 	}
10314 
10315 	netdev->netdev_ops = &ixgbe_netdev_ops;
10316 	ixgbe_set_ethtool_ops(netdev);
10317 	netdev->watchdog_timeo = 5 * HZ;
10318 	strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
10319 
10320 	/* Setup hw api */
10321 	hw->mac.ops   = *ii->mac_ops;
10322 	hw->mac.type  = ii->mac;
10323 	hw->mvals     = ii->mvals;
10324 	if (ii->link_ops)
10325 		hw->link.ops  = *ii->link_ops;
10326 
10327 	/* EEPROM */
10328 	hw->eeprom.ops = *ii->eeprom_ops;
10329 	eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
10330 	if (ixgbe_removed(hw->hw_addr)) {
10331 		err = -EIO;
10332 		goto err_ioremap;
10333 	}
10334 	/* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
10335 	if (!(eec & BIT(8)))
10336 		hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10337 
10338 	/* PHY */
10339 	hw->phy.ops = *ii->phy_ops;
10340 	hw->phy.sfp_type = ixgbe_sfp_type_unknown;
10341 	/* ixgbe_identify_phy_generic will set prtad and mmds properly */
10342 	hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10343 	hw->phy.mdio.mmds = 0;
10344 	hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10345 	hw->phy.mdio.dev = netdev;
10346 	hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10347 	hw->phy.mdio.mdio_write = ixgbe_mdio_write;
10348 
10349 	/* setup the private structure */
10350 	err = ixgbe_sw_init(adapter, ii);
10351 	if (err)
10352 		goto err_sw_init;
10353 
10354 	/* Make sure the SWFW semaphore is in a valid state */
10355 	if (hw->mac.ops.init_swfw_sync)
10356 		hw->mac.ops.init_swfw_sync(hw);
10357 
10358 	/* Make it possible the adapter to be woken up via WOL */
10359 	switch (adapter->hw.mac.type) {
10360 	case ixgbe_mac_82599EB:
10361 	case ixgbe_mac_X540:
10362 	case ixgbe_mac_X550:
10363 	case ixgbe_mac_X550EM_x:
10364 	case ixgbe_mac_x550em_a:
10365 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10366 		break;
10367 	default:
10368 		break;
10369 	}
10370 
10371 	/*
10372 	 * If there is a fan on this device and it has failed log the
10373 	 * failure.
10374 	 */
10375 	if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10376 		u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10377 		if (esdp & IXGBE_ESDP_SDP1)
10378 			e_crit(probe, "Fan has stopped, replace the adapter\n");
10379 	}
10380 
10381 	if (allow_unsupported_sfp)
10382 		hw->allow_unsupported_sfp = allow_unsupported_sfp;
10383 
10384 	/* reset_hw fills in the perm_addr as well */
10385 	hw->phy.reset_if_overtemp = true;
10386 	err = hw->mac.ops.reset_hw(hw);
10387 	hw->phy.reset_if_overtemp = false;
10388 	ixgbe_set_eee_capable(adapter);
10389 	if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
10390 		err = 0;
10391 	} else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
10392 		e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10393 		e_dev_err("Reload the driver after installing a supported module.\n");
10394 		goto err_sw_init;
10395 	} else if (err) {
10396 		e_dev_err("HW Init failed: %d\n", err);
10397 		goto err_sw_init;
10398 	}
10399 
10400 #ifdef CONFIG_PCI_IOV
10401 	/* SR-IOV not supported on the 82598 */
10402 	if (adapter->hw.mac.type == ixgbe_mac_82598EB)
10403 		goto skip_sriov;
10404 	/* Mailbox */
10405 	ixgbe_init_mbx_params_pf(hw);
10406 	hw->mbx.ops = ii->mbx_ops;
10407 	pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
10408 	ixgbe_enable_sriov(adapter, max_vfs);
10409 skip_sriov:
10410 
10411 #endif
10412 	netdev->features = NETIF_F_SG |
10413 			   NETIF_F_TSO |
10414 			   NETIF_F_TSO6 |
10415 			   NETIF_F_RXHASH |
10416 			   NETIF_F_RXCSUM |
10417 			   NETIF_F_HW_CSUM;
10418 
10419 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
10420 				    NETIF_F_GSO_GRE_CSUM | \
10421 				    NETIF_F_GSO_IPXIP4 | \
10422 				    NETIF_F_GSO_IPXIP6 | \
10423 				    NETIF_F_GSO_UDP_TUNNEL | \
10424 				    NETIF_F_GSO_UDP_TUNNEL_CSUM)
10425 
10426 	netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
10427 	netdev->features |= NETIF_F_GSO_PARTIAL |
10428 			    IXGBE_GSO_PARTIAL_FEATURES;
10429 
10430 	if (hw->mac.type >= ixgbe_mac_82599EB)
10431 		netdev->features |= NETIF_F_SCTP_CRC;
10432 
10433 #ifdef CONFIG_XFRM_OFFLOAD
10434 #define IXGBE_ESP_FEATURES	(NETIF_F_HW_ESP | \
10435 				 NETIF_F_HW_ESP_TX_CSUM | \
10436 				 NETIF_F_GSO_ESP)
10437 
10438 	if (adapter->ipsec)
10439 		netdev->features |= IXGBE_ESP_FEATURES;
10440 #endif
10441 	/* copy netdev features into list of user selectable features */
10442 	netdev->hw_features |= netdev->features |
10443 			       NETIF_F_HW_VLAN_CTAG_FILTER |
10444 			       NETIF_F_HW_VLAN_CTAG_RX |
10445 			       NETIF_F_HW_VLAN_CTAG_TX |
10446 			       NETIF_F_RXALL |
10447 			       NETIF_F_HW_L2FW_DOFFLOAD;
10448 
10449 	if (hw->mac.type >= ixgbe_mac_82599EB)
10450 		netdev->hw_features |= NETIF_F_NTUPLE |
10451 				       NETIF_F_HW_TC;
10452 
10453 	if (pci_using_dac)
10454 		netdev->features |= NETIF_F_HIGHDMA;
10455 
10456 	netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
10457 	netdev->hw_enc_features |= netdev->vlan_features;
10458 	netdev->mpls_features |= NETIF_F_SG |
10459 				 NETIF_F_TSO |
10460 				 NETIF_F_TSO6 |
10461 				 NETIF_F_HW_CSUM;
10462 	netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
10463 
10464 	/* set this bit last since it cannot be part of vlan_features */
10465 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
10466 			    NETIF_F_HW_VLAN_CTAG_RX |
10467 			    NETIF_F_HW_VLAN_CTAG_TX;
10468 
10469 	netdev->priv_flags |= IFF_UNICAST_FLT;
10470 	netdev->priv_flags |= IFF_SUPP_NOFCS;
10471 
10472 	/* MTU range: 68 - 9710 */
10473 	netdev->min_mtu = ETH_MIN_MTU;
10474 	netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
10475 
10476 #ifdef CONFIG_IXGBE_DCB
10477 	if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
10478 		netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
10479 #endif
10480 
10481 #ifdef IXGBE_FCOE
10482 	if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
10483 		unsigned int fcoe_l;
10484 
10485 		if (hw->mac.ops.get_device_caps) {
10486 			hw->mac.ops.get_device_caps(hw, &device_caps);
10487 			if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
10488 				adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
10489 		}
10490 
10491 
10492 		fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
10493 		adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
10494 
10495 		netdev->features |= NETIF_F_FSO |
10496 				    NETIF_F_FCOE_CRC;
10497 
10498 		netdev->vlan_features |= NETIF_F_FSO |
10499 					 NETIF_F_FCOE_CRC |
10500 					 NETIF_F_FCOE_MTU;
10501 	}
10502 #endif /* IXGBE_FCOE */
10503 	if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
10504 		netdev->hw_features |= NETIF_F_LRO;
10505 	if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
10506 		netdev->features |= NETIF_F_LRO;
10507 
10508 	/* make sure the EEPROM is good */
10509 	if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
10510 		e_dev_err("The EEPROM Checksum Is Not Valid\n");
10511 		err = -EIO;
10512 		goto err_sw_init;
10513 	}
10514 
10515 	eth_platform_get_mac_address(&adapter->pdev->dev,
10516 				     adapter->hw.mac.perm_addr);
10517 
10518 	memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
10519 
10520 	if (!is_valid_ether_addr(netdev->dev_addr)) {
10521 		e_dev_err("invalid MAC address\n");
10522 		err = -EIO;
10523 		goto err_sw_init;
10524 	}
10525 
10526 	/* Set hw->mac.addr to permanent MAC address */
10527 	ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
10528 	ixgbe_mac_set_default_filter(adapter);
10529 
10530 	timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
10531 
10532 	if (ixgbe_removed(hw->hw_addr)) {
10533 		err = -EIO;
10534 		goto err_sw_init;
10535 	}
10536 	INIT_WORK(&adapter->service_task, ixgbe_service_task);
10537 	set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
10538 	clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
10539 
10540 	err = ixgbe_init_interrupt_scheme(adapter);
10541 	if (err)
10542 		goto err_sw_init;
10543 
10544 	for (i = 0; i < adapter->num_rx_queues; i++)
10545 		u64_stats_init(&adapter->rx_ring[i]->syncp);
10546 	for (i = 0; i < adapter->num_tx_queues; i++)
10547 		u64_stats_init(&adapter->tx_ring[i]->syncp);
10548 	for (i = 0; i < adapter->num_xdp_queues; i++)
10549 		u64_stats_init(&adapter->xdp_ring[i]->syncp);
10550 
10551 	/* WOL not supported for all devices */
10552 	adapter->wol = 0;
10553 	hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
10554 	hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
10555 						pdev->subsystem_device);
10556 	if (hw->wol_enabled)
10557 		adapter->wol = IXGBE_WUFC_MAG;
10558 
10559 	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
10560 
10561 	/* save off EEPROM version number */
10562 	ixgbe_set_fw_version(adapter);
10563 
10564 	/* pick up the PCI bus settings for reporting later */
10565 	if (ixgbe_pcie_from_parent(hw))
10566 		ixgbe_get_parent_bus_info(adapter);
10567 	else
10568 		 hw->mac.ops.get_bus_info(hw);
10569 
10570 	/* calculate the expected PCIe bandwidth required for optimal
10571 	 * performance. Note that some older parts will never have enough
10572 	 * bandwidth due to being older generation PCIe parts. We clamp these
10573 	 * parts to ensure no warning is displayed if it can't be fixed.
10574 	 */
10575 	switch (hw->mac.type) {
10576 	case ixgbe_mac_82598EB:
10577 		expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
10578 		break;
10579 	default:
10580 		expected_gts = ixgbe_enumerate_functions(adapter) * 10;
10581 		break;
10582 	}
10583 
10584 	/* don't check link if we failed to enumerate functions */
10585 	if (expected_gts > 0)
10586 		ixgbe_check_minimum_link(adapter, expected_gts);
10587 
10588 	err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
10589 	if (err)
10590 		strlcpy(part_str, "Unknown", sizeof(part_str));
10591 	if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
10592 		e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
10593 			   hw->mac.type, hw->phy.type, hw->phy.sfp_type,
10594 			   part_str);
10595 	else
10596 		e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
10597 			   hw->mac.type, hw->phy.type, part_str);
10598 
10599 	e_dev_info("%pM\n", netdev->dev_addr);
10600 
10601 	/* reset the hardware with the new settings */
10602 	err = hw->mac.ops.start_hw(hw);
10603 	if (err == IXGBE_ERR_EEPROM_VERSION) {
10604 		/* We are running on a pre-production device, log a warning */
10605 		e_dev_warn("This device is a pre-production adapter/LOM. "
10606 			   "Please be aware there may be issues associated "
10607 			   "with your hardware.  If you are experiencing "
10608 			   "problems please contact your Intel or hardware "
10609 			   "representative who provided you with this "
10610 			   "hardware.\n");
10611 	}
10612 	strcpy(netdev->name, "eth%d");
10613 	pci_set_drvdata(pdev, adapter);
10614 	err = register_netdev(netdev);
10615 	if (err)
10616 		goto err_register;
10617 
10618 
10619 	/* power down the optics for 82599 SFP+ fiber */
10620 	if (hw->mac.ops.disable_tx_laser)
10621 		hw->mac.ops.disable_tx_laser(hw);
10622 
10623 	/* carrier off reporting is important to ethtool even BEFORE open */
10624 	netif_carrier_off(netdev);
10625 
10626 #ifdef CONFIG_IXGBE_DCA
10627 	if (dca_add_requester(&pdev->dev) == 0) {
10628 		adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
10629 		ixgbe_setup_dca(adapter);
10630 	}
10631 #endif
10632 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
10633 		e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
10634 		for (i = 0; i < adapter->num_vfs; i++)
10635 			ixgbe_vf_configuration(pdev, (i | 0x10000000));
10636 	}
10637 
10638 	/* firmware requires driver version to be 0xFFFFFFFF
10639 	 * since os does not support feature
10640 	 */
10641 	if (hw->mac.ops.set_fw_drv_ver)
10642 		hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
10643 					   sizeof(ixgbe_driver_version) - 1,
10644 					   ixgbe_driver_version);
10645 
10646 	/* add san mac addr to netdev */
10647 	ixgbe_add_sanmac_netdev(netdev);
10648 
10649 	e_dev_info("%s\n", ixgbe_default_device_descr);
10650 
10651 #ifdef CONFIG_IXGBE_HWMON
10652 	if (ixgbe_sysfs_init(adapter))
10653 		e_err(probe, "failed to allocate sysfs resources\n");
10654 #endif /* CONFIG_IXGBE_HWMON */
10655 
10656 	ixgbe_dbg_adapter_init(adapter);
10657 
10658 	/* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
10659 	if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
10660 		hw->mac.ops.setup_link(hw,
10661 			IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
10662 			true);
10663 
10664 	return 0;
10665 
10666 err_register:
10667 	ixgbe_release_hw_control(adapter);
10668 	ixgbe_clear_interrupt_scheme(adapter);
10669 err_sw_init:
10670 	ixgbe_disable_sriov(adapter);
10671 	adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
10672 	iounmap(adapter->io_addr);
10673 	kfree(adapter->jump_tables[0]);
10674 	kfree(adapter->mac_table);
10675 	kfree(adapter->rss_key);
10676 err_ioremap:
10677 	disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
10678 	free_netdev(netdev);
10679 err_alloc_etherdev:
10680 	pci_release_mem_regions(pdev);
10681 err_pci_reg:
10682 err_dma:
10683 	if (!adapter || disable_dev)
10684 		pci_disable_device(pdev);
10685 	return err;
10686 }
10687 
10688 /**
10689  * ixgbe_remove - Device Removal Routine
10690  * @pdev: PCI device information struct
10691  *
10692  * ixgbe_remove is called by the PCI subsystem to alert the driver
10693  * that it should release a PCI device.  The could be caused by a
10694  * Hot-Plug event, or because the driver is going to be removed from
10695  * memory.
10696  **/
10697 static void ixgbe_remove(struct pci_dev *pdev)
10698 {
10699 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10700 	struct net_device *netdev;
10701 	bool disable_dev;
10702 	int i;
10703 
10704 	/* if !adapter then we already cleaned up in probe */
10705 	if (!adapter)
10706 		return;
10707 
10708 	netdev  = adapter->netdev;
10709 	ixgbe_dbg_adapter_exit(adapter);
10710 
10711 	set_bit(__IXGBE_REMOVING, &adapter->state);
10712 	cancel_work_sync(&adapter->service_task);
10713 
10714 
10715 #ifdef CONFIG_IXGBE_DCA
10716 	if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
10717 		adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
10718 		dca_remove_requester(&pdev->dev);
10719 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
10720 				IXGBE_DCA_CTRL_DCA_DISABLE);
10721 	}
10722 
10723 #endif
10724 #ifdef CONFIG_IXGBE_HWMON
10725 	ixgbe_sysfs_exit(adapter);
10726 #endif /* CONFIG_IXGBE_HWMON */
10727 
10728 	/* remove the added san mac */
10729 	ixgbe_del_sanmac_netdev(netdev);
10730 
10731 #ifdef CONFIG_PCI_IOV
10732 	ixgbe_disable_sriov(adapter);
10733 #endif
10734 	if (netdev->reg_state == NETREG_REGISTERED)
10735 		unregister_netdev(netdev);
10736 
10737 	ixgbe_stop_ipsec_offload(adapter);
10738 	ixgbe_clear_interrupt_scheme(adapter);
10739 
10740 	ixgbe_release_hw_control(adapter);
10741 
10742 #ifdef CONFIG_DCB
10743 	kfree(adapter->ixgbe_ieee_pfc);
10744 	kfree(adapter->ixgbe_ieee_ets);
10745 
10746 #endif
10747 	iounmap(adapter->io_addr);
10748 	pci_release_mem_regions(pdev);
10749 
10750 	e_dev_info("complete\n");
10751 
10752 	for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
10753 		if (adapter->jump_tables[i]) {
10754 			kfree(adapter->jump_tables[i]->input);
10755 			kfree(adapter->jump_tables[i]->mask);
10756 		}
10757 		kfree(adapter->jump_tables[i]);
10758 	}
10759 
10760 	kfree(adapter->mac_table);
10761 	kfree(adapter->rss_key);
10762 	disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
10763 	free_netdev(netdev);
10764 
10765 	pci_disable_pcie_error_reporting(pdev);
10766 
10767 	if (disable_dev)
10768 		pci_disable_device(pdev);
10769 }
10770 
10771 /**
10772  * ixgbe_io_error_detected - called when PCI error is detected
10773  * @pdev: Pointer to PCI device
10774  * @state: The current pci connection state
10775  *
10776  * This function is called after a PCI bus error affecting
10777  * this device has been detected.
10778  */
10779 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
10780 						pci_channel_state_t state)
10781 {
10782 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10783 	struct net_device *netdev = adapter->netdev;
10784 
10785 #ifdef CONFIG_PCI_IOV
10786 	struct ixgbe_hw *hw = &adapter->hw;
10787 	struct pci_dev *bdev, *vfdev;
10788 	u32 dw0, dw1, dw2, dw3;
10789 	int vf, pos;
10790 	u16 req_id, pf_func;
10791 
10792 	if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
10793 	    adapter->num_vfs == 0)
10794 		goto skip_bad_vf_detection;
10795 
10796 	bdev = pdev->bus->self;
10797 	while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
10798 		bdev = bdev->bus->self;
10799 
10800 	if (!bdev)
10801 		goto skip_bad_vf_detection;
10802 
10803 	pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
10804 	if (!pos)
10805 		goto skip_bad_vf_detection;
10806 
10807 	dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
10808 	dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
10809 	dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
10810 	dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
10811 	if (ixgbe_removed(hw->hw_addr))
10812 		goto skip_bad_vf_detection;
10813 
10814 	req_id = dw1 >> 16;
10815 	/* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
10816 	if (!(req_id & 0x0080))
10817 		goto skip_bad_vf_detection;
10818 
10819 	pf_func = req_id & 0x01;
10820 	if ((pf_func & 1) == (pdev->devfn & 1)) {
10821 		unsigned int device_id;
10822 
10823 		vf = (req_id & 0x7F) >> 1;
10824 		e_dev_err("VF %d has caused a PCIe error\n", vf);
10825 		e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
10826 				"%8.8x\tdw3: %8.8x\n",
10827 		dw0, dw1, dw2, dw3);
10828 		switch (adapter->hw.mac.type) {
10829 		case ixgbe_mac_82599EB:
10830 			device_id = IXGBE_82599_VF_DEVICE_ID;
10831 			break;
10832 		case ixgbe_mac_X540:
10833 			device_id = IXGBE_X540_VF_DEVICE_ID;
10834 			break;
10835 		case ixgbe_mac_X550:
10836 			device_id = IXGBE_DEV_ID_X550_VF;
10837 			break;
10838 		case ixgbe_mac_X550EM_x:
10839 			device_id = IXGBE_DEV_ID_X550EM_X_VF;
10840 			break;
10841 		case ixgbe_mac_x550em_a:
10842 			device_id = IXGBE_DEV_ID_X550EM_A_VF;
10843 			break;
10844 		default:
10845 			device_id = 0;
10846 			break;
10847 		}
10848 
10849 		/* Find the pci device of the offending VF */
10850 		vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
10851 		while (vfdev) {
10852 			if (vfdev->devfn == (req_id & 0xFF))
10853 				break;
10854 			vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
10855 					       device_id, vfdev);
10856 		}
10857 		/*
10858 		 * There's a slim chance the VF could have been hot plugged,
10859 		 * so if it is no longer present we don't need to issue the
10860 		 * VFLR.  Just clean up the AER in that case.
10861 		 */
10862 		if (vfdev) {
10863 			pcie_flr(vfdev);
10864 			/* Free device reference count */
10865 			pci_dev_put(vfdev);
10866 		}
10867 
10868 		pci_cleanup_aer_uncorrect_error_status(pdev);
10869 	}
10870 
10871 	/*
10872 	 * Even though the error may have occurred on the other port
10873 	 * we still need to increment the vf error reference count for
10874 	 * both ports because the I/O resume function will be called
10875 	 * for both of them.
10876 	 */
10877 	adapter->vferr_refcount++;
10878 
10879 	return PCI_ERS_RESULT_RECOVERED;
10880 
10881 skip_bad_vf_detection:
10882 #endif /* CONFIG_PCI_IOV */
10883 	if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
10884 		return PCI_ERS_RESULT_DISCONNECT;
10885 
10886 	if (!netif_device_present(netdev))
10887 		return PCI_ERS_RESULT_DISCONNECT;
10888 
10889 	rtnl_lock();
10890 	netif_device_detach(netdev);
10891 
10892 	if (netif_running(netdev))
10893 		ixgbe_close_suspend(adapter);
10894 
10895 	if (state == pci_channel_io_perm_failure) {
10896 		rtnl_unlock();
10897 		return PCI_ERS_RESULT_DISCONNECT;
10898 	}
10899 
10900 	if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
10901 		pci_disable_device(pdev);
10902 	rtnl_unlock();
10903 
10904 	/* Request a slot reset. */
10905 	return PCI_ERS_RESULT_NEED_RESET;
10906 }
10907 
10908 /**
10909  * ixgbe_io_slot_reset - called after the pci bus has been reset.
10910  * @pdev: Pointer to PCI device
10911  *
10912  * Restart the card from scratch, as if from a cold-boot.
10913  */
10914 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
10915 {
10916 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10917 	pci_ers_result_t result;
10918 	int err;
10919 
10920 	if (pci_enable_device_mem(pdev)) {
10921 		e_err(probe, "Cannot re-enable PCI device after reset.\n");
10922 		result = PCI_ERS_RESULT_DISCONNECT;
10923 	} else {
10924 		smp_mb__before_atomic();
10925 		clear_bit(__IXGBE_DISABLED, &adapter->state);
10926 		adapter->hw.hw_addr = adapter->io_addr;
10927 		pci_set_master(pdev);
10928 		pci_restore_state(pdev);
10929 		pci_save_state(pdev);
10930 
10931 		pci_wake_from_d3(pdev, false);
10932 
10933 		ixgbe_reset(adapter);
10934 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10935 		result = PCI_ERS_RESULT_RECOVERED;
10936 	}
10937 
10938 	err = pci_cleanup_aer_uncorrect_error_status(pdev);
10939 	if (err) {
10940 		e_dev_err("pci_cleanup_aer_uncorrect_error_status "
10941 			  "failed 0x%0x\n", err);
10942 		/* non-fatal, continue */
10943 	}
10944 
10945 	return result;
10946 }
10947 
10948 /**
10949  * ixgbe_io_resume - called when traffic can start flowing again.
10950  * @pdev: Pointer to PCI device
10951  *
10952  * This callback is called when the error recovery driver tells us that
10953  * its OK to resume normal operation.
10954  */
10955 static void ixgbe_io_resume(struct pci_dev *pdev)
10956 {
10957 	struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
10958 	struct net_device *netdev = adapter->netdev;
10959 
10960 #ifdef CONFIG_PCI_IOV
10961 	if (adapter->vferr_refcount) {
10962 		e_info(drv, "Resuming after VF err\n");
10963 		adapter->vferr_refcount--;
10964 		return;
10965 	}
10966 
10967 #endif
10968 	rtnl_lock();
10969 	if (netif_running(netdev))
10970 		ixgbe_open(netdev);
10971 
10972 	netif_device_attach(netdev);
10973 	rtnl_unlock();
10974 }
10975 
10976 static const struct pci_error_handlers ixgbe_err_handler = {
10977 	.error_detected = ixgbe_io_error_detected,
10978 	.slot_reset = ixgbe_io_slot_reset,
10979 	.resume = ixgbe_io_resume,
10980 };
10981 
10982 static struct pci_driver ixgbe_driver = {
10983 	.name     = ixgbe_driver_name,
10984 	.id_table = ixgbe_pci_tbl,
10985 	.probe    = ixgbe_probe,
10986 	.remove   = ixgbe_remove,
10987 #ifdef CONFIG_PM
10988 	.suspend  = ixgbe_suspend,
10989 	.resume   = ixgbe_resume,
10990 #endif
10991 	.shutdown = ixgbe_shutdown,
10992 	.sriov_configure = ixgbe_pci_sriov_configure,
10993 	.err_handler = &ixgbe_err_handler
10994 };
10995 
10996 /**
10997  * ixgbe_init_module - Driver Registration Routine
10998  *
10999  * ixgbe_init_module is the first routine called when the driver is
11000  * loaded. All it does is register with the PCI subsystem.
11001  **/
11002 static int __init ixgbe_init_module(void)
11003 {
11004 	int ret;
11005 	pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
11006 	pr_info("%s\n", ixgbe_copyright);
11007 
11008 	ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11009 	if (!ixgbe_wq) {
11010 		pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11011 		return -ENOMEM;
11012 	}
11013 
11014 	ixgbe_dbg_init();
11015 
11016 	ret = pci_register_driver(&ixgbe_driver);
11017 	if (ret) {
11018 		destroy_workqueue(ixgbe_wq);
11019 		ixgbe_dbg_exit();
11020 		return ret;
11021 	}
11022 
11023 #ifdef CONFIG_IXGBE_DCA
11024 	dca_register_notify(&dca_notifier);
11025 #endif
11026 
11027 	return 0;
11028 }
11029 
11030 module_init(ixgbe_init_module);
11031 
11032 /**
11033  * ixgbe_exit_module - Driver Exit Cleanup Routine
11034  *
11035  * ixgbe_exit_module is called just before the driver is removed
11036  * from memory.
11037  **/
11038 static void __exit ixgbe_exit_module(void)
11039 {
11040 #ifdef CONFIG_IXGBE_DCA
11041 	dca_unregister_notify(&dca_notifier);
11042 #endif
11043 	pci_unregister_driver(&ixgbe_driver);
11044 
11045 	ixgbe_dbg_exit();
11046 	if (ixgbe_wq) {
11047 		destroy_workqueue(ixgbe_wq);
11048 		ixgbe_wq = NULL;
11049 	}
11050 }
11051 
11052 #ifdef CONFIG_IXGBE_DCA
11053 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
11054 			    void *p)
11055 {
11056 	int ret_val;
11057 
11058 	ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
11059 					 __ixgbe_notify_dca);
11060 
11061 	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11062 }
11063 
11064 #endif /* CONFIG_IXGBE_DCA */
11065 
11066 module_exit(ixgbe_exit_module);
11067 
11068 /* ixgbe_main.c */
11069