1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <linux/bpf.h> 53 #include <linux/bpf_trace.h> 54 #include <linux/atomic.h> 55 #include <scsi/fc/fc_fcoe.h> 56 #include <net/udp_tunnel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/vxlan.h> 61 #include <net/mpls.h> 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 #include "ixgbe_model.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "5.1.0-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2016 Intel Corporation."; 83 84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 85 86 static const struct ixgbe_info *ixgbe_info_tbl[] = { 87 [board_82598] = &ixgbe_82598_info, 88 [board_82599] = &ixgbe_82599_info, 89 [board_X540] = &ixgbe_X540_info, 90 [board_X550] = &ixgbe_X550_info, 91 [board_X550EM_x] = &ixgbe_X550EM_x_info, 92 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 93 [board_x550em_a] = &ixgbe_x550em_a_info, 94 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 152 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 153 /* required last entry */ 154 {0, } 155 }; 156 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 157 158 #ifdef CONFIG_IXGBE_DCA 159 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 160 void *p); 161 static struct notifier_block dca_notifier = { 162 .notifier_call = ixgbe_notify_dca, 163 .next = NULL, 164 .priority = 0 165 }; 166 #endif 167 168 #ifdef CONFIG_PCI_IOV 169 static unsigned int max_vfs; 170 module_param(max_vfs, uint, 0); 171 MODULE_PARM_DESC(max_vfs, 172 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 173 #endif /* CONFIG_PCI_IOV */ 174 175 static unsigned int allow_unsupported_sfp; 176 module_param(allow_unsupported_sfp, uint, 0); 177 MODULE_PARM_DESC(allow_unsupported_sfp, 178 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 179 180 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 181 static int debug = -1; 182 module_param(debug, int, 0); 183 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 184 185 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 186 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 187 MODULE_LICENSE("GPL"); 188 MODULE_VERSION(DRV_VERSION); 189 190 static struct workqueue_struct *ixgbe_wq; 191 192 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 193 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 194 195 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 196 u32 reg, u16 *value) 197 { 198 struct pci_dev *parent_dev; 199 struct pci_bus *parent_bus; 200 201 parent_bus = adapter->pdev->bus->parent; 202 if (!parent_bus) 203 return -1; 204 205 parent_dev = parent_bus->self; 206 if (!parent_dev) 207 return -1; 208 209 if (!pci_is_pcie(parent_dev)) 210 return -1; 211 212 pcie_capability_read_word(parent_dev, reg, value); 213 if (*value == IXGBE_FAILED_READ_CFG_WORD && 214 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 215 return -1; 216 return 0; 217 } 218 219 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 220 { 221 struct ixgbe_hw *hw = &adapter->hw; 222 u16 link_status = 0; 223 int err; 224 225 hw->bus.type = ixgbe_bus_type_pci_express; 226 227 /* Get the negotiated link width and speed from PCI config space of the 228 * parent, as this device is behind a switch 229 */ 230 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 231 232 /* assume caller will handle error case */ 233 if (err) 234 return err; 235 236 hw->bus.width = ixgbe_convert_bus_width(link_status); 237 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 238 239 return 0; 240 } 241 242 /** 243 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 244 * @hw: hw specific details 245 * 246 * This function is used by probe to determine whether a device's PCI-Express 247 * bandwidth details should be gathered from the parent bus instead of from the 248 * device. Used to ensure that various locations all have the correct device ID 249 * checks. 250 */ 251 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 252 { 253 switch (hw->device_id) { 254 case IXGBE_DEV_ID_82599_SFP_SF_QP: 255 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 256 return true; 257 default: 258 return false; 259 } 260 } 261 262 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 263 int expected_gts) 264 { 265 struct ixgbe_hw *hw = &adapter->hw; 266 int max_gts = 0; 267 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 268 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 269 struct pci_dev *pdev; 270 271 /* Some devices are not connected over PCIe and thus do not negotiate 272 * speed. These devices do not have valid bus info, and thus any report 273 * we generate may not be correct. 274 */ 275 if (hw->bus.type == ixgbe_bus_type_internal) 276 return; 277 278 /* determine whether to use the parent device */ 279 if (ixgbe_pcie_from_parent(&adapter->hw)) 280 pdev = adapter->pdev->bus->parent->self; 281 else 282 pdev = adapter->pdev; 283 284 if (pcie_get_minimum_link(pdev, &speed, &width) || 285 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 286 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 287 return; 288 } 289 290 switch (speed) { 291 case PCIE_SPEED_2_5GT: 292 /* 8b/10b encoding reduces max throughput by 20% */ 293 max_gts = 2 * width; 294 break; 295 case PCIE_SPEED_5_0GT: 296 /* 8b/10b encoding reduces max throughput by 20% */ 297 max_gts = 4 * width; 298 break; 299 case PCIE_SPEED_8_0GT: 300 /* 128b/130b encoding reduces throughput by less than 2% */ 301 max_gts = 8 * width; 302 break; 303 default: 304 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 305 return; 306 } 307 308 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 309 max_gts); 310 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 311 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 312 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 313 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 314 "Unknown"), 315 width, 316 (speed == PCIE_SPEED_2_5GT ? "20%" : 317 speed == PCIE_SPEED_5_0GT ? "20%" : 318 speed == PCIE_SPEED_8_0GT ? "<2%" : 319 "Unknown")); 320 321 if (max_gts < expected_gts) { 322 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 323 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 324 expected_gts); 325 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 326 } 327 } 328 329 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 330 { 331 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 332 !test_bit(__IXGBE_REMOVING, &adapter->state) && 333 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 334 queue_work(ixgbe_wq, &adapter->service_task); 335 } 336 337 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 338 { 339 struct ixgbe_adapter *adapter = hw->back; 340 341 if (!hw->hw_addr) 342 return; 343 hw->hw_addr = NULL; 344 e_dev_err("Adapter removed\n"); 345 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 346 ixgbe_service_event_schedule(adapter); 347 } 348 349 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 350 { 351 u32 value; 352 353 /* The following check not only optimizes a bit by not 354 * performing a read on the status register when the 355 * register just read was a status register read that 356 * returned IXGBE_FAILED_READ_REG. It also blocks any 357 * potential recursion. 358 */ 359 if (reg == IXGBE_STATUS) { 360 ixgbe_remove_adapter(hw); 361 return; 362 } 363 value = ixgbe_read_reg(hw, IXGBE_STATUS); 364 if (value == IXGBE_FAILED_READ_REG) 365 ixgbe_remove_adapter(hw); 366 } 367 368 /** 369 * ixgbe_read_reg - Read from device register 370 * @hw: hw specific details 371 * @reg: offset of register to read 372 * 373 * Returns : value read or IXGBE_FAILED_READ_REG if removed 374 * 375 * This function is used to read device registers. It checks for device 376 * removal by confirming any read that returns all ones by checking the 377 * status register value for all ones. This function avoids reading from 378 * the hardware if a removal was previously detected in which case it 379 * returns IXGBE_FAILED_READ_REG (all ones). 380 */ 381 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 382 { 383 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 384 u32 value; 385 386 if (ixgbe_removed(reg_addr)) 387 return IXGBE_FAILED_READ_REG; 388 if (unlikely(hw->phy.nw_mng_if_sel & 389 IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) { 390 struct ixgbe_adapter *adapter; 391 int i; 392 393 for (i = 0; i < 200; ++i) { 394 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 395 if (likely(!value)) 396 goto writes_completed; 397 if (value == IXGBE_FAILED_READ_REG) { 398 ixgbe_remove_adapter(hw); 399 return IXGBE_FAILED_READ_REG; 400 } 401 udelay(5); 402 } 403 404 adapter = hw->back; 405 e_warn(hw, "register writes incomplete %08x\n", value); 406 } 407 408 writes_completed: 409 value = readl(reg_addr + reg); 410 if (unlikely(value == IXGBE_FAILED_READ_REG)) 411 ixgbe_check_remove(hw, reg); 412 return value; 413 } 414 415 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 416 { 417 u16 value; 418 419 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 420 if (value == IXGBE_FAILED_READ_CFG_WORD) { 421 ixgbe_remove_adapter(hw); 422 return true; 423 } 424 return false; 425 } 426 427 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 428 { 429 struct ixgbe_adapter *adapter = hw->back; 430 u16 value; 431 432 if (ixgbe_removed(hw->hw_addr)) 433 return IXGBE_FAILED_READ_CFG_WORD; 434 pci_read_config_word(adapter->pdev, reg, &value); 435 if (value == IXGBE_FAILED_READ_CFG_WORD && 436 ixgbe_check_cfg_remove(hw, adapter->pdev)) 437 return IXGBE_FAILED_READ_CFG_WORD; 438 return value; 439 } 440 441 #ifdef CONFIG_PCI_IOV 442 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 443 { 444 struct ixgbe_adapter *adapter = hw->back; 445 u32 value; 446 447 if (ixgbe_removed(hw->hw_addr)) 448 return IXGBE_FAILED_READ_CFG_DWORD; 449 pci_read_config_dword(adapter->pdev, reg, &value); 450 if (value == IXGBE_FAILED_READ_CFG_DWORD && 451 ixgbe_check_cfg_remove(hw, adapter->pdev)) 452 return IXGBE_FAILED_READ_CFG_DWORD; 453 return value; 454 } 455 #endif /* CONFIG_PCI_IOV */ 456 457 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 458 { 459 struct ixgbe_adapter *adapter = hw->back; 460 461 if (ixgbe_removed(hw->hw_addr)) 462 return; 463 pci_write_config_word(adapter->pdev, reg, value); 464 } 465 466 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 467 { 468 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 469 470 /* flush memory to make sure state is correct before next watchdog */ 471 smp_mb__before_atomic(); 472 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 473 } 474 475 struct ixgbe_reg_info { 476 u32 ofs; 477 char *name; 478 }; 479 480 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 481 482 /* General Registers */ 483 {IXGBE_CTRL, "CTRL"}, 484 {IXGBE_STATUS, "STATUS"}, 485 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 486 487 /* Interrupt Registers */ 488 {IXGBE_EICR, "EICR"}, 489 490 /* RX Registers */ 491 {IXGBE_SRRCTL(0), "SRRCTL"}, 492 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 493 {IXGBE_RDLEN(0), "RDLEN"}, 494 {IXGBE_RDH(0), "RDH"}, 495 {IXGBE_RDT(0), "RDT"}, 496 {IXGBE_RXDCTL(0), "RXDCTL"}, 497 {IXGBE_RDBAL(0), "RDBAL"}, 498 {IXGBE_RDBAH(0), "RDBAH"}, 499 500 /* TX Registers */ 501 {IXGBE_TDBAL(0), "TDBAL"}, 502 {IXGBE_TDBAH(0), "TDBAH"}, 503 {IXGBE_TDLEN(0), "TDLEN"}, 504 {IXGBE_TDH(0), "TDH"}, 505 {IXGBE_TDT(0), "TDT"}, 506 {IXGBE_TXDCTL(0), "TXDCTL"}, 507 508 /* List Terminator */ 509 { .name = NULL } 510 }; 511 512 513 /* 514 * ixgbe_regdump - register printout routine 515 */ 516 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 517 { 518 int i; 519 char rname[16]; 520 u32 regs[64]; 521 522 switch (reginfo->ofs) { 523 case IXGBE_SRRCTL(0): 524 for (i = 0; i < 64; i++) 525 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 526 break; 527 case IXGBE_DCA_RXCTRL(0): 528 for (i = 0; i < 64; i++) 529 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 530 break; 531 case IXGBE_RDLEN(0): 532 for (i = 0; i < 64; i++) 533 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 534 break; 535 case IXGBE_RDH(0): 536 for (i = 0; i < 64; i++) 537 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 538 break; 539 case IXGBE_RDT(0): 540 for (i = 0; i < 64; i++) 541 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 542 break; 543 case IXGBE_RXDCTL(0): 544 for (i = 0; i < 64; i++) 545 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 546 break; 547 case IXGBE_RDBAL(0): 548 for (i = 0; i < 64; i++) 549 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 550 break; 551 case IXGBE_RDBAH(0): 552 for (i = 0; i < 64; i++) 553 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 554 break; 555 case IXGBE_TDBAL(0): 556 for (i = 0; i < 64; i++) 557 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 558 break; 559 case IXGBE_TDBAH(0): 560 for (i = 0; i < 64; i++) 561 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 562 break; 563 case IXGBE_TDLEN(0): 564 for (i = 0; i < 64; i++) 565 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 566 break; 567 case IXGBE_TDH(0): 568 for (i = 0; i < 64; i++) 569 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 570 break; 571 case IXGBE_TDT(0): 572 for (i = 0; i < 64; i++) 573 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 574 break; 575 case IXGBE_TXDCTL(0): 576 for (i = 0; i < 64; i++) 577 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 578 break; 579 default: 580 pr_info("%-15s %08x\n", 581 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 582 return; 583 } 584 585 i = 0; 586 while (i < 64) { 587 int j; 588 char buf[9 * 8 + 1]; 589 char *p = buf; 590 591 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 592 for (j = 0; j < 8; j++) 593 p += sprintf(p, " %08x", regs[i++]); 594 pr_err("%-15s%s\n", rname, buf); 595 } 596 597 } 598 599 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 600 { 601 struct ixgbe_tx_buffer *tx_buffer; 602 603 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 604 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 605 n, ring->next_to_use, ring->next_to_clean, 606 (u64)dma_unmap_addr(tx_buffer, dma), 607 dma_unmap_len(tx_buffer, len), 608 tx_buffer->next_to_watch, 609 (u64)tx_buffer->time_stamp); 610 } 611 612 /* 613 * ixgbe_dump - Print registers, tx-rings and rx-rings 614 */ 615 static void ixgbe_dump(struct ixgbe_adapter *adapter) 616 { 617 struct net_device *netdev = adapter->netdev; 618 struct ixgbe_hw *hw = &adapter->hw; 619 struct ixgbe_reg_info *reginfo; 620 int n = 0; 621 struct ixgbe_ring *ring; 622 struct ixgbe_tx_buffer *tx_buffer; 623 union ixgbe_adv_tx_desc *tx_desc; 624 struct my_u0 { u64 a; u64 b; } *u0; 625 struct ixgbe_ring *rx_ring; 626 union ixgbe_adv_rx_desc *rx_desc; 627 struct ixgbe_rx_buffer *rx_buffer_info; 628 int i = 0; 629 630 if (!netif_msg_hw(adapter)) 631 return; 632 633 /* Print netdevice Info */ 634 if (netdev) { 635 dev_info(&adapter->pdev->dev, "Net device Info\n"); 636 pr_info("Device Name state " 637 "trans_start\n"); 638 pr_info("%-15s %016lX %016lX\n", 639 netdev->name, 640 netdev->state, 641 dev_trans_start(netdev)); 642 } 643 644 /* Print Registers */ 645 dev_info(&adapter->pdev->dev, "Register Dump\n"); 646 pr_info(" Register Name Value\n"); 647 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 648 reginfo->name; reginfo++) { 649 ixgbe_regdump(hw, reginfo); 650 } 651 652 /* Print TX Ring Summary */ 653 if (!netdev || !netif_running(netdev)) 654 return; 655 656 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 657 pr_info(" %s %s %s %s\n", 658 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 659 "leng", "ntw", "timestamp"); 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 ring = adapter->tx_ring[n]; 662 ixgbe_print_buffer(ring, n); 663 } 664 665 for (n = 0; n < adapter->num_xdp_queues; n++) { 666 ring = adapter->xdp_ring[n]; 667 ixgbe_print_buffer(ring, n); 668 } 669 670 /* Print TX Rings */ 671 if (!netif_msg_tx_done(adapter)) 672 goto rx_ring_summary; 673 674 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 675 676 /* Transmit Descriptor Formats 677 * 678 * 82598 Advanced Transmit Descriptor 679 * +--------------------------------------------------------------+ 680 * 0 | Buffer Address [63:0] | 681 * +--------------------------------------------------------------+ 682 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 683 * +--------------------------------------------------------------+ 684 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 685 * 686 * 82598 Advanced Transmit Descriptor (Write-Back Format) 687 * +--------------------------------------------------------------+ 688 * 0 | RSV [63:0] | 689 * +--------------------------------------------------------------+ 690 * 8 | RSV | STA | NXTSEQ | 691 * +--------------------------------------------------------------+ 692 * 63 36 35 32 31 0 693 * 694 * 82599+ Advanced Transmit Descriptor 695 * +--------------------------------------------------------------+ 696 * 0 | Buffer Address [63:0] | 697 * +--------------------------------------------------------------+ 698 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 699 * +--------------------------------------------------------------+ 700 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 701 * 702 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 703 * +--------------------------------------------------------------+ 704 * 0 | RSV [63:0] | 705 * +--------------------------------------------------------------+ 706 * 8 | RSV | STA | RSV | 707 * +--------------------------------------------------------------+ 708 * 63 36 35 32 31 0 709 */ 710 711 for (n = 0; n < adapter->num_tx_queues; n++) { 712 ring = adapter->tx_ring[n]; 713 pr_info("------------------------------------\n"); 714 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 715 pr_info("------------------------------------\n"); 716 pr_info("%s%s %s %s %s %s\n", 717 "T [desc] [address 63:0 ] ", 718 "[PlPOIdStDDt Ln] [bi->dma ] ", 719 "leng", "ntw", "timestamp", "bi->skb"); 720 721 for (i = 0; ring->desc && (i < ring->count); i++) { 722 tx_desc = IXGBE_TX_DESC(ring, i); 723 tx_buffer = &ring->tx_buffer_info[i]; 724 u0 = (struct my_u0 *)tx_desc; 725 if (dma_unmap_len(tx_buffer, len) > 0) { 726 const char *ring_desc; 727 728 if (i == ring->next_to_use && 729 i == ring->next_to_clean) 730 ring_desc = " NTC/U"; 731 else if (i == ring->next_to_use) 732 ring_desc = " NTU"; 733 else if (i == ring->next_to_clean) 734 ring_desc = " NTC"; 735 else 736 ring_desc = ""; 737 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 738 i, 739 le64_to_cpu(u0->a), 740 le64_to_cpu(u0->b), 741 (u64)dma_unmap_addr(tx_buffer, dma), 742 dma_unmap_len(tx_buffer, len), 743 tx_buffer->next_to_watch, 744 (u64)tx_buffer->time_stamp, 745 tx_buffer->skb, 746 ring_desc); 747 748 if (netif_msg_pktdata(adapter) && 749 tx_buffer->skb) 750 print_hex_dump(KERN_INFO, "", 751 DUMP_PREFIX_ADDRESS, 16, 1, 752 tx_buffer->skb->data, 753 dma_unmap_len(tx_buffer, len), 754 true); 755 } 756 } 757 } 758 759 /* Print RX Rings Summary */ 760 rx_ring_summary: 761 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 762 pr_info("Queue [NTU] [NTC]\n"); 763 for (n = 0; n < adapter->num_rx_queues; n++) { 764 rx_ring = adapter->rx_ring[n]; 765 pr_info("%5d %5X %5X\n", 766 n, rx_ring->next_to_use, rx_ring->next_to_clean); 767 } 768 769 /* Print RX Rings */ 770 if (!netif_msg_rx_status(adapter)) 771 return; 772 773 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 774 775 /* Receive Descriptor Formats 776 * 777 * 82598 Advanced Receive Descriptor (Read) Format 778 * 63 1 0 779 * +-----------------------------------------------------+ 780 * 0 | Packet Buffer Address [63:1] |A0/NSE| 781 * +----------------------------------------------+------+ 782 * 8 | Header Buffer Address [63:1] | DD | 783 * +-----------------------------------------------------+ 784 * 785 * 786 * 82598 Advanced Receive Descriptor (Write-Back) Format 787 * 788 * 63 48 47 32 31 30 21 20 16 15 4 3 0 789 * +------------------------------------------------------+ 790 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 791 * | Packet | IP | | | | Type | Type | 792 * | Checksum | Ident | | | | | | 793 * +------------------------------------------------------+ 794 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 795 * +------------------------------------------------------+ 796 * 63 48 47 32 31 20 19 0 797 * 798 * 82599+ Advanced Receive Descriptor (Read) Format 799 * 63 1 0 800 * +-----------------------------------------------------+ 801 * 0 | Packet Buffer Address [63:1] |A0/NSE| 802 * +----------------------------------------------+------+ 803 * 8 | Header Buffer Address [63:1] | DD | 804 * +-----------------------------------------------------+ 805 * 806 * 807 * 82599+ Advanced Receive Descriptor (Write-Back) Format 808 * 809 * 63 48 47 32 31 30 21 20 17 16 4 3 0 810 * +------------------------------------------------------+ 811 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 812 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 813 * |/ Flow Dir Flt ID | | | | | | 814 * +------------------------------------------------------+ 815 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 816 * +------------------------------------------------------+ 817 * 63 48 47 32 31 20 19 0 818 */ 819 820 for (n = 0; n < adapter->num_rx_queues; n++) { 821 rx_ring = adapter->rx_ring[n]; 822 pr_info("------------------------------------\n"); 823 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 824 pr_info("------------------------------------\n"); 825 pr_info("%s%s%s\n", 826 "R [desc] [ PktBuf A0] ", 827 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 828 "<-- Adv Rx Read format"); 829 pr_info("%s%s%s\n", 830 "RWB[desc] [PcsmIpSHl PtRs] ", 831 "[vl er S cks ln] ---------------- [bi->skb ] ", 832 "<-- Adv Rx Write-Back format"); 833 834 for (i = 0; i < rx_ring->count; i++) { 835 const char *ring_desc; 836 837 if (i == rx_ring->next_to_use) 838 ring_desc = " NTU"; 839 else if (i == rx_ring->next_to_clean) 840 ring_desc = " NTC"; 841 else 842 ring_desc = ""; 843 844 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 845 rx_desc = IXGBE_RX_DESC(rx_ring, i); 846 u0 = (struct my_u0 *)rx_desc; 847 if (rx_desc->wb.upper.length) { 848 /* Descriptor Done */ 849 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 850 i, 851 le64_to_cpu(u0->a), 852 le64_to_cpu(u0->b), 853 rx_buffer_info->skb, 854 ring_desc); 855 } else { 856 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 857 i, 858 le64_to_cpu(u0->a), 859 le64_to_cpu(u0->b), 860 (u64)rx_buffer_info->dma, 861 rx_buffer_info->skb, 862 ring_desc); 863 864 if (netif_msg_pktdata(adapter) && 865 rx_buffer_info->dma) { 866 print_hex_dump(KERN_INFO, "", 867 DUMP_PREFIX_ADDRESS, 16, 1, 868 page_address(rx_buffer_info->page) + 869 rx_buffer_info->page_offset, 870 ixgbe_rx_bufsz(rx_ring), true); 871 } 872 } 873 } 874 } 875 } 876 877 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 878 { 879 u32 ctrl_ext; 880 881 /* Let firmware take over control of h/w */ 882 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 884 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 885 } 886 887 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 888 { 889 u32 ctrl_ext; 890 891 /* Let firmware know the driver has taken over */ 892 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 894 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 895 } 896 897 /** 898 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 899 * @adapter: pointer to adapter struct 900 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 901 * @queue: queue to map the corresponding interrupt to 902 * @msix_vector: the vector to map to the corresponding queue 903 * 904 */ 905 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 906 u8 queue, u8 msix_vector) 907 { 908 u32 ivar, index; 909 struct ixgbe_hw *hw = &adapter->hw; 910 switch (hw->mac.type) { 911 case ixgbe_mac_82598EB: 912 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 913 if (direction == -1) 914 direction = 0; 915 index = (((direction * 64) + queue) >> 2) & 0x1F; 916 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 917 ivar &= ~(0xFF << (8 * (queue & 0x3))); 918 ivar |= (msix_vector << (8 * (queue & 0x3))); 919 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 920 break; 921 case ixgbe_mac_82599EB: 922 case ixgbe_mac_X540: 923 case ixgbe_mac_X550: 924 case ixgbe_mac_X550EM_x: 925 case ixgbe_mac_x550em_a: 926 if (direction == -1) { 927 /* other causes */ 928 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 929 index = ((queue & 1) * 8); 930 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 931 ivar &= ~(0xFF << index); 932 ivar |= (msix_vector << index); 933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 934 break; 935 } else { 936 /* tx or rx causes */ 937 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 938 index = ((16 * (queue & 1)) + (8 * direction)); 939 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 940 ivar &= ~(0xFF << index); 941 ivar |= (msix_vector << index); 942 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 943 break; 944 } 945 default: 946 break; 947 } 948 } 949 950 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 951 u64 qmask) 952 { 953 u32 mask; 954 955 switch (adapter->hw.mac.type) { 956 case ixgbe_mac_82598EB: 957 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 959 break; 960 case ixgbe_mac_82599EB: 961 case ixgbe_mac_X540: 962 case ixgbe_mac_X550: 963 case ixgbe_mac_X550EM_x: 964 case ixgbe_mac_x550em_a: 965 mask = (qmask & 0xFFFFFFFF); 966 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 967 mask = (qmask >> 32); 968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 969 break; 970 default: 971 break; 972 } 973 } 974 975 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 976 { 977 struct ixgbe_hw *hw = &adapter->hw; 978 struct ixgbe_hw_stats *hwstats = &adapter->stats; 979 int i; 980 u32 data; 981 982 if ((hw->fc.current_mode != ixgbe_fc_full) && 983 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 984 return; 985 986 switch (hw->mac.type) { 987 case ixgbe_mac_82598EB: 988 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 989 break; 990 default: 991 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 992 } 993 hwstats->lxoffrxc += data; 994 995 /* refill credits (no tx hang) if we received xoff */ 996 if (!data) 997 return; 998 999 for (i = 0; i < adapter->num_tx_queues; i++) 1000 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1001 &adapter->tx_ring[i]->state); 1002 1003 for (i = 0; i < adapter->num_xdp_queues; i++) 1004 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1005 &adapter->xdp_ring[i]->state); 1006 } 1007 1008 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1009 { 1010 struct ixgbe_hw *hw = &adapter->hw; 1011 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1012 u32 xoff[8] = {0}; 1013 u8 tc; 1014 int i; 1015 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1016 1017 if (adapter->ixgbe_ieee_pfc) 1018 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1019 1020 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1021 ixgbe_update_xoff_rx_lfc(adapter); 1022 return; 1023 } 1024 1025 /* update stats for each tc, only valid with PFC enabled */ 1026 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1027 u32 pxoffrxc; 1028 1029 switch (hw->mac.type) { 1030 case ixgbe_mac_82598EB: 1031 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1032 break; 1033 default: 1034 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1035 } 1036 hwstats->pxoffrxc[i] += pxoffrxc; 1037 /* Get the TC for given UP */ 1038 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1039 xoff[tc] += pxoffrxc; 1040 } 1041 1042 /* disarm tx queues that have received xoff frames */ 1043 for (i = 0; i < adapter->num_tx_queues; i++) { 1044 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1045 1046 tc = tx_ring->dcb_tc; 1047 if (xoff[tc]) 1048 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1049 } 1050 1051 for (i = 0; i < adapter->num_xdp_queues; i++) { 1052 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1053 1054 tc = xdp_ring->dcb_tc; 1055 if (xoff[tc]) 1056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1057 } 1058 } 1059 1060 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1061 { 1062 return ring->stats.packets; 1063 } 1064 1065 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1066 { 1067 struct ixgbe_adapter *adapter; 1068 struct ixgbe_hw *hw; 1069 u32 head, tail; 1070 1071 if (ring->l2_accel_priv) 1072 adapter = ring->l2_accel_priv->real_adapter; 1073 else 1074 adapter = netdev_priv(ring->netdev); 1075 1076 hw = &adapter->hw; 1077 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1078 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1079 1080 if (head != tail) 1081 return (head < tail) ? 1082 tail - head : (tail + ring->count - head); 1083 1084 return 0; 1085 } 1086 1087 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1088 { 1089 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1090 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1091 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1092 1093 clear_check_for_tx_hang(tx_ring); 1094 1095 /* 1096 * Check for a hung queue, but be thorough. This verifies 1097 * that a transmit has been completed since the previous 1098 * check AND there is at least one packet pending. The 1099 * ARMED bit is set to indicate a potential hang. The 1100 * bit is cleared if a pause frame is received to remove 1101 * false hang detection due to PFC or 802.3x frames. By 1102 * requiring this to fail twice we avoid races with 1103 * pfc clearing the ARMED bit and conditions where we 1104 * run the check_tx_hang logic with a transmit completion 1105 * pending but without time to complete it yet. 1106 */ 1107 if (tx_done_old == tx_done && tx_pending) 1108 /* make sure it is true for two checks in a row */ 1109 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1110 &tx_ring->state); 1111 /* update completed stats and continue */ 1112 tx_ring->tx_stats.tx_done_old = tx_done; 1113 /* reset the countdown */ 1114 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1115 1116 return false; 1117 } 1118 1119 /** 1120 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1121 * @adapter: driver private struct 1122 **/ 1123 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1124 { 1125 1126 /* Do the reset outside of interrupt context */ 1127 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1128 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1129 e_warn(drv, "initiating reset due to tx timeout\n"); 1130 ixgbe_service_event_schedule(adapter); 1131 } 1132 } 1133 1134 /** 1135 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1136 **/ 1137 static int ixgbe_tx_maxrate(struct net_device *netdev, 1138 int queue_index, u32 maxrate) 1139 { 1140 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1141 struct ixgbe_hw *hw = &adapter->hw; 1142 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1143 1144 if (!maxrate) 1145 return 0; 1146 1147 /* Calculate the rate factor values to set */ 1148 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1149 bcnrc_val /= maxrate; 1150 1151 /* clear everything but the rate factor */ 1152 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1153 IXGBE_RTTBCNRC_RF_DEC_MASK; 1154 1155 /* enable the rate scheduler */ 1156 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1157 1158 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1159 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1160 1161 return 0; 1162 } 1163 1164 /** 1165 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1166 * @q_vector: structure containing interrupt and ring information 1167 * @tx_ring: tx ring to clean 1168 * @napi_budget: Used to determine if we are in netpoll 1169 **/ 1170 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1171 struct ixgbe_ring *tx_ring, int napi_budget) 1172 { 1173 struct ixgbe_adapter *adapter = q_vector->adapter; 1174 struct ixgbe_tx_buffer *tx_buffer; 1175 union ixgbe_adv_tx_desc *tx_desc; 1176 unsigned int total_bytes = 0, total_packets = 0; 1177 unsigned int budget = q_vector->tx.work_limit; 1178 unsigned int i = tx_ring->next_to_clean; 1179 1180 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1181 return true; 1182 1183 tx_buffer = &tx_ring->tx_buffer_info[i]; 1184 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1185 i -= tx_ring->count; 1186 1187 do { 1188 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1189 1190 /* if next_to_watch is not set then there is no work pending */ 1191 if (!eop_desc) 1192 break; 1193 1194 /* prevent any other reads prior to eop_desc */ 1195 read_barrier_depends(); 1196 1197 /* if DD is not set pending work has not been completed */ 1198 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1199 break; 1200 1201 /* clear next_to_watch to prevent false hangs */ 1202 tx_buffer->next_to_watch = NULL; 1203 1204 /* update the statistics for this packet */ 1205 total_bytes += tx_buffer->bytecount; 1206 total_packets += tx_buffer->gso_segs; 1207 1208 /* free the skb */ 1209 if (ring_is_xdp(tx_ring)) 1210 page_frag_free(tx_buffer->data); 1211 else 1212 napi_consume_skb(tx_buffer->skb, napi_budget); 1213 1214 /* unmap skb header data */ 1215 dma_unmap_single(tx_ring->dev, 1216 dma_unmap_addr(tx_buffer, dma), 1217 dma_unmap_len(tx_buffer, len), 1218 DMA_TO_DEVICE); 1219 1220 /* clear tx_buffer data */ 1221 dma_unmap_len_set(tx_buffer, len, 0); 1222 1223 /* unmap remaining buffers */ 1224 while (tx_desc != eop_desc) { 1225 tx_buffer++; 1226 tx_desc++; 1227 i++; 1228 if (unlikely(!i)) { 1229 i -= tx_ring->count; 1230 tx_buffer = tx_ring->tx_buffer_info; 1231 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1232 } 1233 1234 /* unmap any remaining paged data */ 1235 if (dma_unmap_len(tx_buffer, len)) { 1236 dma_unmap_page(tx_ring->dev, 1237 dma_unmap_addr(tx_buffer, dma), 1238 dma_unmap_len(tx_buffer, len), 1239 DMA_TO_DEVICE); 1240 dma_unmap_len_set(tx_buffer, len, 0); 1241 } 1242 } 1243 1244 /* move us one more past the eop_desc for start of next pkt */ 1245 tx_buffer++; 1246 tx_desc++; 1247 i++; 1248 if (unlikely(!i)) { 1249 i -= tx_ring->count; 1250 tx_buffer = tx_ring->tx_buffer_info; 1251 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1252 } 1253 1254 /* issue prefetch for next Tx descriptor */ 1255 prefetch(tx_desc); 1256 1257 /* update budget accounting */ 1258 budget--; 1259 } while (likely(budget)); 1260 1261 i += tx_ring->count; 1262 tx_ring->next_to_clean = i; 1263 u64_stats_update_begin(&tx_ring->syncp); 1264 tx_ring->stats.bytes += total_bytes; 1265 tx_ring->stats.packets += total_packets; 1266 u64_stats_update_end(&tx_ring->syncp); 1267 q_vector->tx.total_bytes += total_bytes; 1268 q_vector->tx.total_packets += total_packets; 1269 1270 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1271 /* schedule immediate reset if we believe we hung */ 1272 struct ixgbe_hw *hw = &adapter->hw; 1273 e_err(drv, "Detected Tx Unit Hang %s\n" 1274 " Tx Queue <%d>\n" 1275 " TDH, TDT <%x>, <%x>\n" 1276 " next_to_use <%x>\n" 1277 " next_to_clean <%x>\n" 1278 "tx_buffer_info[next_to_clean]\n" 1279 " time_stamp <%lx>\n" 1280 " jiffies <%lx>\n", 1281 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1282 tx_ring->queue_index, 1283 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1284 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1285 tx_ring->next_to_use, i, 1286 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1287 1288 if (!ring_is_xdp(tx_ring)) 1289 netif_stop_subqueue(tx_ring->netdev, 1290 tx_ring->queue_index); 1291 1292 e_info(probe, 1293 "tx hang %d detected on queue %d, resetting adapter\n", 1294 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1295 1296 /* schedule immediate reset if we believe we hung */ 1297 ixgbe_tx_timeout_reset(adapter); 1298 1299 /* the adapter is about to reset, no point in enabling stuff */ 1300 return true; 1301 } 1302 1303 if (ring_is_xdp(tx_ring)) 1304 return !!budget; 1305 1306 netdev_tx_completed_queue(txring_txq(tx_ring), 1307 total_packets, total_bytes); 1308 1309 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1310 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1311 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1312 /* Make sure that anybody stopping the queue after this 1313 * sees the new next_to_clean. 1314 */ 1315 smp_mb(); 1316 if (__netif_subqueue_stopped(tx_ring->netdev, 1317 tx_ring->queue_index) 1318 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1319 netif_wake_subqueue(tx_ring->netdev, 1320 tx_ring->queue_index); 1321 ++tx_ring->tx_stats.restart_queue; 1322 } 1323 } 1324 1325 return !!budget; 1326 } 1327 1328 #ifdef CONFIG_IXGBE_DCA 1329 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1330 struct ixgbe_ring *tx_ring, 1331 int cpu) 1332 { 1333 struct ixgbe_hw *hw = &adapter->hw; 1334 u32 txctrl = 0; 1335 u16 reg_offset; 1336 1337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1338 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1339 1340 switch (hw->mac.type) { 1341 case ixgbe_mac_82598EB: 1342 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1343 break; 1344 case ixgbe_mac_82599EB: 1345 case ixgbe_mac_X540: 1346 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1347 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1348 break; 1349 default: 1350 /* for unknown hardware do not write register */ 1351 return; 1352 } 1353 1354 /* 1355 * We can enable relaxed ordering for reads, but not writes when 1356 * DCA is enabled. This is due to a known issue in some chipsets 1357 * which will cause the DCA tag to be cleared. 1358 */ 1359 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1360 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1361 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1362 1363 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1364 } 1365 1366 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1367 struct ixgbe_ring *rx_ring, 1368 int cpu) 1369 { 1370 struct ixgbe_hw *hw = &adapter->hw; 1371 u32 rxctrl = 0; 1372 u8 reg_idx = rx_ring->reg_idx; 1373 1374 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1375 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1376 1377 switch (hw->mac.type) { 1378 case ixgbe_mac_82599EB: 1379 case ixgbe_mac_X540: 1380 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1381 break; 1382 default: 1383 break; 1384 } 1385 1386 /* 1387 * We can enable relaxed ordering for reads, but not writes when 1388 * DCA is enabled. This is due to a known issue in some chipsets 1389 * which will cause the DCA tag to be cleared. 1390 */ 1391 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1392 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1393 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1394 1395 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1396 } 1397 1398 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1399 { 1400 struct ixgbe_adapter *adapter = q_vector->adapter; 1401 struct ixgbe_ring *ring; 1402 int cpu = get_cpu(); 1403 1404 if (q_vector->cpu == cpu) 1405 goto out_no_update; 1406 1407 ixgbe_for_each_ring(ring, q_vector->tx) 1408 ixgbe_update_tx_dca(adapter, ring, cpu); 1409 1410 ixgbe_for_each_ring(ring, q_vector->rx) 1411 ixgbe_update_rx_dca(adapter, ring, cpu); 1412 1413 q_vector->cpu = cpu; 1414 out_no_update: 1415 put_cpu(); 1416 } 1417 1418 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1419 { 1420 int i; 1421 1422 /* always use CB2 mode, difference is masked in the CB driver */ 1423 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1425 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1426 else 1427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1428 IXGBE_DCA_CTRL_DCA_DISABLE); 1429 1430 for (i = 0; i < adapter->num_q_vectors; i++) { 1431 adapter->q_vector[i]->cpu = -1; 1432 ixgbe_update_dca(adapter->q_vector[i]); 1433 } 1434 } 1435 1436 static int __ixgbe_notify_dca(struct device *dev, void *data) 1437 { 1438 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1439 unsigned long event = *(unsigned long *)data; 1440 1441 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1442 return 0; 1443 1444 switch (event) { 1445 case DCA_PROVIDER_ADD: 1446 /* if we're already enabled, don't do it again */ 1447 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1448 break; 1449 if (dca_add_requester(dev) == 0) { 1450 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1452 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1453 break; 1454 } 1455 /* fall through - DCA is disabled. */ 1456 case DCA_PROVIDER_REMOVE: 1457 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1458 dca_remove_requester(dev); 1459 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1461 IXGBE_DCA_CTRL_DCA_DISABLE); 1462 } 1463 break; 1464 } 1465 1466 return 0; 1467 } 1468 1469 #endif /* CONFIG_IXGBE_DCA */ 1470 1471 #define IXGBE_RSS_L4_TYPES_MASK \ 1472 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1473 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1474 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1475 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1476 1477 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1478 union ixgbe_adv_rx_desc *rx_desc, 1479 struct sk_buff *skb) 1480 { 1481 u16 rss_type; 1482 1483 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1484 return; 1485 1486 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1487 IXGBE_RXDADV_RSSTYPE_MASK; 1488 1489 if (!rss_type) 1490 return; 1491 1492 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1493 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1494 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1495 } 1496 1497 #ifdef IXGBE_FCOE 1498 /** 1499 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1500 * @ring: structure containing ring specific data 1501 * @rx_desc: advanced rx descriptor 1502 * 1503 * Returns : true if it is FCoE pkt 1504 */ 1505 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1506 union ixgbe_adv_rx_desc *rx_desc) 1507 { 1508 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1509 1510 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1511 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1512 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1513 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1514 } 1515 1516 #endif /* IXGBE_FCOE */ 1517 /** 1518 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1519 * @ring: structure containing ring specific data 1520 * @rx_desc: current Rx descriptor being processed 1521 * @skb: skb currently being received and modified 1522 **/ 1523 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1524 union ixgbe_adv_rx_desc *rx_desc, 1525 struct sk_buff *skb) 1526 { 1527 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1528 bool encap_pkt = false; 1529 1530 skb_checksum_none_assert(skb); 1531 1532 /* Rx csum disabled */ 1533 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1534 return; 1535 1536 /* check for VXLAN and Geneve packets */ 1537 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1538 encap_pkt = true; 1539 skb->encapsulation = 1; 1540 } 1541 1542 /* if IP and error */ 1543 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1544 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1545 ring->rx_stats.csum_err++; 1546 return; 1547 } 1548 1549 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1550 return; 1551 1552 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1553 /* 1554 * 82599 errata, UDP frames with a 0 checksum can be marked as 1555 * checksum errors. 1556 */ 1557 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1558 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1559 return; 1560 1561 ring->rx_stats.csum_err++; 1562 return; 1563 } 1564 1565 /* It must be a TCP or UDP packet with a valid checksum */ 1566 skb->ip_summed = CHECKSUM_UNNECESSARY; 1567 if (encap_pkt) { 1568 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1569 return; 1570 1571 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1572 skb->ip_summed = CHECKSUM_NONE; 1573 return; 1574 } 1575 /* If we checked the outer header let the stack know */ 1576 skb->csum_level = 1; 1577 } 1578 } 1579 1580 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1581 { 1582 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1583 } 1584 1585 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1586 struct ixgbe_rx_buffer *bi) 1587 { 1588 struct page *page = bi->page; 1589 dma_addr_t dma; 1590 1591 /* since we are recycling buffers we should seldom need to alloc */ 1592 if (likely(page)) 1593 return true; 1594 1595 /* alloc new page for storage */ 1596 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1597 if (unlikely(!page)) { 1598 rx_ring->rx_stats.alloc_rx_page_failed++; 1599 return false; 1600 } 1601 1602 /* map page for use */ 1603 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1604 ixgbe_rx_pg_size(rx_ring), 1605 DMA_FROM_DEVICE, 1606 IXGBE_RX_DMA_ATTR); 1607 1608 /* 1609 * if mapping failed free memory back to system since 1610 * there isn't much point in holding memory we can't use 1611 */ 1612 if (dma_mapping_error(rx_ring->dev, dma)) { 1613 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1614 1615 rx_ring->rx_stats.alloc_rx_page_failed++; 1616 return false; 1617 } 1618 1619 bi->dma = dma; 1620 bi->page = page; 1621 bi->page_offset = ixgbe_rx_offset(rx_ring); 1622 bi->pagecnt_bias = 1; 1623 1624 return true; 1625 } 1626 1627 /** 1628 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1629 * @rx_ring: ring to place buffers on 1630 * @cleaned_count: number of buffers to replace 1631 **/ 1632 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1633 { 1634 union ixgbe_adv_rx_desc *rx_desc; 1635 struct ixgbe_rx_buffer *bi; 1636 u16 i = rx_ring->next_to_use; 1637 u16 bufsz; 1638 1639 /* nothing to do */ 1640 if (!cleaned_count) 1641 return; 1642 1643 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1644 bi = &rx_ring->rx_buffer_info[i]; 1645 i -= rx_ring->count; 1646 1647 bufsz = ixgbe_rx_bufsz(rx_ring); 1648 1649 do { 1650 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1651 break; 1652 1653 /* sync the buffer for use by the device */ 1654 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1655 bi->page_offset, bufsz, 1656 DMA_FROM_DEVICE); 1657 1658 /* 1659 * Refresh the desc even if buffer_addrs didn't change 1660 * because each write-back erases this info. 1661 */ 1662 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1663 1664 rx_desc++; 1665 bi++; 1666 i++; 1667 if (unlikely(!i)) { 1668 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1669 bi = rx_ring->rx_buffer_info; 1670 i -= rx_ring->count; 1671 } 1672 1673 /* clear the length for the next_to_use descriptor */ 1674 rx_desc->wb.upper.length = 0; 1675 1676 cleaned_count--; 1677 } while (cleaned_count); 1678 1679 i += rx_ring->count; 1680 1681 if (rx_ring->next_to_use != i) { 1682 rx_ring->next_to_use = i; 1683 1684 /* update next to alloc since we have filled the ring */ 1685 rx_ring->next_to_alloc = i; 1686 1687 /* Force memory writes to complete before letting h/w 1688 * know there are new descriptors to fetch. (Only 1689 * applicable for weak-ordered memory model archs, 1690 * such as IA-64). 1691 */ 1692 wmb(); 1693 writel(i, rx_ring->tail); 1694 } 1695 } 1696 1697 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1698 struct sk_buff *skb) 1699 { 1700 u16 hdr_len = skb_headlen(skb); 1701 1702 /* set gso_size to avoid messing up TCP MSS */ 1703 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1704 IXGBE_CB(skb)->append_cnt); 1705 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1706 } 1707 1708 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1709 struct sk_buff *skb) 1710 { 1711 /* if append_cnt is 0 then frame is not RSC */ 1712 if (!IXGBE_CB(skb)->append_cnt) 1713 return; 1714 1715 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1716 rx_ring->rx_stats.rsc_flush++; 1717 1718 ixgbe_set_rsc_gso_size(rx_ring, skb); 1719 1720 /* gso_size is computed using append_cnt so always clear it last */ 1721 IXGBE_CB(skb)->append_cnt = 0; 1722 } 1723 1724 /** 1725 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1726 * @rx_ring: rx descriptor ring packet is being transacted on 1727 * @rx_desc: pointer to the EOP Rx descriptor 1728 * @skb: pointer to current skb being populated 1729 * 1730 * This function checks the ring, descriptor, and packet information in 1731 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1732 * other fields within the skb. 1733 **/ 1734 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1735 union ixgbe_adv_rx_desc *rx_desc, 1736 struct sk_buff *skb) 1737 { 1738 struct net_device *dev = rx_ring->netdev; 1739 u32 flags = rx_ring->q_vector->adapter->flags; 1740 1741 ixgbe_update_rsc_stats(rx_ring, skb); 1742 1743 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1744 1745 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1746 1747 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1748 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1749 1750 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1751 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1752 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1753 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1754 } 1755 1756 skb_record_rx_queue(skb, rx_ring->queue_index); 1757 1758 skb->protocol = eth_type_trans(skb, dev); 1759 } 1760 1761 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1762 struct sk_buff *skb) 1763 { 1764 napi_gro_receive(&q_vector->napi, skb); 1765 } 1766 1767 /** 1768 * ixgbe_is_non_eop - process handling of non-EOP buffers 1769 * @rx_ring: Rx ring being processed 1770 * @rx_desc: Rx descriptor for current buffer 1771 * @skb: Current socket buffer containing buffer in progress 1772 * 1773 * This function updates next to clean. If the buffer is an EOP buffer 1774 * this function exits returning false, otherwise it will place the 1775 * sk_buff in the next buffer to be chained and return true indicating 1776 * that this is in fact a non-EOP buffer. 1777 **/ 1778 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1779 union ixgbe_adv_rx_desc *rx_desc, 1780 struct sk_buff *skb) 1781 { 1782 u32 ntc = rx_ring->next_to_clean + 1; 1783 1784 /* fetch, update, and store next to clean */ 1785 ntc = (ntc < rx_ring->count) ? ntc : 0; 1786 rx_ring->next_to_clean = ntc; 1787 1788 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1789 1790 /* update RSC append count if present */ 1791 if (ring_is_rsc_enabled(rx_ring)) { 1792 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1793 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1794 1795 if (unlikely(rsc_enabled)) { 1796 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1797 1798 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1799 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1800 1801 /* update ntc based on RSC value */ 1802 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1803 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1804 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1805 } 1806 } 1807 1808 /* if we are the last buffer then there is nothing else to do */ 1809 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1810 return false; 1811 1812 /* place skb in next buffer to be received */ 1813 rx_ring->rx_buffer_info[ntc].skb = skb; 1814 rx_ring->rx_stats.non_eop_descs++; 1815 1816 return true; 1817 } 1818 1819 /** 1820 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1821 * @rx_ring: rx descriptor ring packet is being transacted on 1822 * @skb: pointer to current skb being adjusted 1823 * 1824 * This function is an ixgbe specific version of __pskb_pull_tail. The 1825 * main difference between this version and the original function is that 1826 * this function can make several assumptions about the state of things 1827 * that allow for significant optimizations versus the standard function. 1828 * As a result we can do things like drop a frag and maintain an accurate 1829 * truesize for the skb. 1830 */ 1831 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1832 struct sk_buff *skb) 1833 { 1834 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1835 unsigned char *va; 1836 unsigned int pull_len; 1837 1838 /* 1839 * it is valid to use page_address instead of kmap since we are 1840 * working with pages allocated out of the lomem pool per 1841 * alloc_page(GFP_ATOMIC) 1842 */ 1843 va = skb_frag_address(frag); 1844 1845 /* 1846 * we need the header to contain the greater of either ETH_HLEN or 1847 * 60 bytes if the skb->len is less than 60 for skb_pad. 1848 */ 1849 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1850 1851 /* align pull length to size of long to optimize memcpy performance */ 1852 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1853 1854 /* update all of the pointers */ 1855 skb_frag_size_sub(frag, pull_len); 1856 frag->page_offset += pull_len; 1857 skb->data_len -= pull_len; 1858 skb->tail += pull_len; 1859 } 1860 1861 /** 1862 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1863 * @rx_ring: rx descriptor ring packet is being transacted on 1864 * @skb: pointer to current skb being updated 1865 * 1866 * This function provides a basic DMA sync up for the first fragment of an 1867 * skb. The reason for doing this is that the first fragment cannot be 1868 * unmapped until we have reached the end of packet descriptor for a buffer 1869 * chain. 1870 */ 1871 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1872 struct sk_buff *skb) 1873 { 1874 /* if the page was released unmap it, else just sync our portion */ 1875 if (unlikely(IXGBE_CB(skb)->page_released)) { 1876 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1877 ixgbe_rx_pg_size(rx_ring), 1878 DMA_FROM_DEVICE, 1879 IXGBE_RX_DMA_ATTR); 1880 } else { 1881 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1882 1883 dma_sync_single_range_for_cpu(rx_ring->dev, 1884 IXGBE_CB(skb)->dma, 1885 frag->page_offset, 1886 skb_frag_size(frag), 1887 DMA_FROM_DEVICE); 1888 } 1889 } 1890 1891 /** 1892 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1893 * @rx_ring: rx descriptor ring packet is being transacted on 1894 * @rx_desc: pointer to the EOP Rx descriptor 1895 * @skb: pointer to current skb being fixed 1896 * 1897 * Check if the skb is valid in the XDP case it will be an error pointer. 1898 * Return true in this case to abort processing and advance to next 1899 * descriptor. 1900 * 1901 * Check for corrupted packet headers caused by senders on the local L2 1902 * embedded NIC switch not setting up their Tx Descriptors right. These 1903 * should be very rare. 1904 * 1905 * Also address the case where we are pulling data in on pages only 1906 * and as such no data is present in the skb header. 1907 * 1908 * In addition if skb is not at least 60 bytes we need to pad it so that 1909 * it is large enough to qualify as a valid Ethernet frame. 1910 * 1911 * Returns true if an error was encountered and skb was freed. 1912 **/ 1913 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1914 union ixgbe_adv_rx_desc *rx_desc, 1915 struct sk_buff *skb) 1916 { 1917 struct net_device *netdev = rx_ring->netdev; 1918 1919 /* XDP packets use error pointer so abort at this point */ 1920 if (IS_ERR(skb)) 1921 return true; 1922 1923 /* verify that the packet does not have any known errors */ 1924 if (unlikely(ixgbe_test_staterr(rx_desc, 1925 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1926 !(netdev->features & NETIF_F_RXALL))) { 1927 dev_kfree_skb_any(skb); 1928 return true; 1929 } 1930 1931 /* place header in linear portion of buffer */ 1932 if (!skb_headlen(skb)) 1933 ixgbe_pull_tail(rx_ring, skb); 1934 1935 #ifdef IXGBE_FCOE 1936 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1937 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1938 return false; 1939 1940 #endif 1941 /* if eth_skb_pad returns an error the skb was freed */ 1942 if (eth_skb_pad(skb)) 1943 return true; 1944 1945 return false; 1946 } 1947 1948 /** 1949 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1950 * @rx_ring: rx descriptor ring to store buffers on 1951 * @old_buff: donor buffer to have page reused 1952 * 1953 * Synchronizes page for reuse by the adapter 1954 **/ 1955 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1956 struct ixgbe_rx_buffer *old_buff) 1957 { 1958 struct ixgbe_rx_buffer *new_buff; 1959 u16 nta = rx_ring->next_to_alloc; 1960 1961 new_buff = &rx_ring->rx_buffer_info[nta]; 1962 1963 /* update, and store next to alloc */ 1964 nta++; 1965 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1966 1967 /* Transfer page from old buffer to new buffer. 1968 * Move each member individually to avoid possible store 1969 * forwarding stalls and unnecessary copy of skb. 1970 */ 1971 new_buff->dma = old_buff->dma; 1972 new_buff->page = old_buff->page; 1973 new_buff->page_offset = old_buff->page_offset; 1974 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1975 } 1976 1977 static inline bool ixgbe_page_is_reserved(struct page *page) 1978 { 1979 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1980 } 1981 1982 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1983 { 1984 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1985 struct page *page = rx_buffer->page; 1986 1987 /* avoid re-using remote pages */ 1988 if (unlikely(ixgbe_page_is_reserved(page))) 1989 return false; 1990 1991 #if (PAGE_SIZE < 8192) 1992 /* if we are only owner of page we can reuse it */ 1993 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1994 return false; 1995 #else 1996 /* The last offset is a bit aggressive in that we assume the 1997 * worst case of FCoE being enabled and using a 3K buffer. 1998 * However this should have minimal impact as the 1K extra is 1999 * still less than one buffer in size. 2000 */ 2001 #define IXGBE_LAST_OFFSET \ 2002 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2003 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2004 return false; 2005 #endif 2006 2007 /* If we have drained the page fragment pool we need to update 2008 * the pagecnt_bias and page count so that we fully restock the 2009 * number of references the driver holds. 2010 */ 2011 if (unlikely(!pagecnt_bias)) { 2012 page_ref_add(page, USHRT_MAX); 2013 rx_buffer->pagecnt_bias = USHRT_MAX; 2014 } 2015 2016 return true; 2017 } 2018 2019 /** 2020 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2021 * @rx_ring: rx descriptor ring to transact packets on 2022 * @rx_buffer: buffer containing page to add 2023 * @rx_desc: descriptor containing length of buffer written by hardware 2024 * @skb: sk_buff to place the data into 2025 * 2026 * This function will add the data contained in rx_buffer->page to the skb. 2027 * This is done either through a direct copy if the data in the buffer is 2028 * less than the skb header size, otherwise it will just attach the page as 2029 * a frag to the skb. 2030 * 2031 * The function will then update the page offset if necessary and return 2032 * true if the buffer can be reused by the adapter. 2033 **/ 2034 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2035 struct ixgbe_rx_buffer *rx_buffer, 2036 struct sk_buff *skb, 2037 unsigned int size) 2038 { 2039 #if (PAGE_SIZE < 8192) 2040 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2041 #else 2042 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2043 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2044 SKB_DATA_ALIGN(size); 2045 #endif 2046 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2047 rx_buffer->page_offset, size, truesize); 2048 #if (PAGE_SIZE < 8192) 2049 rx_buffer->page_offset ^= truesize; 2050 #else 2051 rx_buffer->page_offset += truesize; 2052 #endif 2053 } 2054 2055 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2056 union ixgbe_adv_rx_desc *rx_desc, 2057 struct sk_buff **skb, 2058 const unsigned int size) 2059 { 2060 struct ixgbe_rx_buffer *rx_buffer; 2061 2062 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2063 prefetchw(rx_buffer->page); 2064 *skb = rx_buffer->skb; 2065 2066 /* Delay unmapping of the first packet. It carries the header 2067 * information, HW may still access the header after the writeback. 2068 * Only unmap it when EOP is reached 2069 */ 2070 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2071 if (!*skb) 2072 goto skip_sync; 2073 } else { 2074 if (*skb) 2075 ixgbe_dma_sync_frag(rx_ring, *skb); 2076 } 2077 2078 /* we are reusing so sync this buffer for CPU use */ 2079 dma_sync_single_range_for_cpu(rx_ring->dev, 2080 rx_buffer->dma, 2081 rx_buffer->page_offset, 2082 size, 2083 DMA_FROM_DEVICE); 2084 skip_sync: 2085 rx_buffer->pagecnt_bias--; 2086 2087 return rx_buffer; 2088 } 2089 2090 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2091 struct ixgbe_rx_buffer *rx_buffer, 2092 struct sk_buff *skb) 2093 { 2094 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2095 /* hand second half of page back to the ring */ 2096 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2097 } else { 2098 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2099 /* the page has been released from the ring */ 2100 IXGBE_CB(skb)->page_released = true; 2101 } else { 2102 /* we are not reusing the buffer so unmap it */ 2103 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2104 ixgbe_rx_pg_size(rx_ring), 2105 DMA_FROM_DEVICE, 2106 IXGBE_RX_DMA_ATTR); 2107 } 2108 __page_frag_cache_drain(rx_buffer->page, 2109 rx_buffer->pagecnt_bias); 2110 } 2111 2112 /* clear contents of rx_buffer */ 2113 rx_buffer->page = NULL; 2114 rx_buffer->skb = NULL; 2115 } 2116 2117 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2118 struct ixgbe_rx_buffer *rx_buffer, 2119 struct xdp_buff *xdp, 2120 union ixgbe_adv_rx_desc *rx_desc) 2121 { 2122 unsigned int size = xdp->data_end - xdp->data; 2123 #if (PAGE_SIZE < 8192) 2124 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2125 #else 2126 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2127 xdp->data_hard_start); 2128 #endif 2129 struct sk_buff *skb; 2130 2131 /* prefetch first cache line of first page */ 2132 prefetch(xdp->data); 2133 #if L1_CACHE_BYTES < 128 2134 prefetch(xdp->data + L1_CACHE_BYTES); 2135 #endif 2136 2137 /* allocate a skb to store the frags */ 2138 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2139 if (unlikely(!skb)) 2140 return NULL; 2141 2142 if (size > IXGBE_RX_HDR_SIZE) { 2143 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2144 IXGBE_CB(skb)->dma = rx_buffer->dma; 2145 2146 skb_add_rx_frag(skb, 0, rx_buffer->page, 2147 xdp->data - page_address(rx_buffer->page), 2148 size, truesize); 2149 #if (PAGE_SIZE < 8192) 2150 rx_buffer->page_offset ^= truesize; 2151 #else 2152 rx_buffer->page_offset += truesize; 2153 #endif 2154 } else { 2155 memcpy(__skb_put(skb, size), 2156 xdp->data, ALIGN(size, sizeof(long))); 2157 rx_buffer->pagecnt_bias++; 2158 } 2159 2160 return skb; 2161 } 2162 2163 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2164 struct ixgbe_rx_buffer *rx_buffer, 2165 struct xdp_buff *xdp, 2166 union ixgbe_adv_rx_desc *rx_desc) 2167 { 2168 #if (PAGE_SIZE < 8192) 2169 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2170 #else 2171 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2172 SKB_DATA_ALIGN(xdp->data_end - 2173 xdp->data_hard_start); 2174 #endif 2175 struct sk_buff *skb; 2176 2177 /* prefetch first cache line of first page */ 2178 prefetch(xdp->data); 2179 #if L1_CACHE_BYTES < 128 2180 prefetch(xdp->data + L1_CACHE_BYTES); 2181 #endif 2182 2183 /* build an skb to around the page buffer */ 2184 skb = build_skb(xdp->data_hard_start, truesize); 2185 if (unlikely(!skb)) 2186 return NULL; 2187 2188 /* update pointers within the skb to store the data */ 2189 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2190 __skb_put(skb, xdp->data_end - xdp->data); 2191 2192 /* record DMA address if this is the start of a chain of buffers */ 2193 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2194 IXGBE_CB(skb)->dma = rx_buffer->dma; 2195 2196 /* update buffer offset */ 2197 #if (PAGE_SIZE < 8192) 2198 rx_buffer->page_offset ^= truesize; 2199 #else 2200 rx_buffer->page_offset += truesize; 2201 #endif 2202 2203 return skb; 2204 } 2205 2206 #define IXGBE_XDP_PASS 0 2207 #define IXGBE_XDP_CONSUMED 1 2208 #define IXGBE_XDP_TX 2 2209 2210 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2211 struct xdp_buff *xdp); 2212 2213 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2214 struct ixgbe_ring *rx_ring, 2215 struct xdp_buff *xdp) 2216 { 2217 int result = IXGBE_XDP_PASS; 2218 struct bpf_prog *xdp_prog; 2219 u32 act; 2220 2221 rcu_read_lock(); 2222 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2223 2224 if (!xdp_prog) 2225 goto xdp_out; 2226 2227 act = bpf_prog_run_xdp(xdp_prog, xdp); 2228 switch (act) { 2229 case XDP_PASS: 2230 break; 2231 case XDP_TX: 2232 result = ixgbe_xmit_xdp_ring(adapter, xdp); 2233 break; 2234 default: 2235 bpf_warn_invalid_xdp_action(act); 2236 /* fallthrough */ 2237 case XDP_ABORTED: 2238 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2239 /* fallthrough -- handle aborts by dropping packet */ 2240 case XDP_DROP: 2241 result = IXGBE_XDP_CONSUMED; 2242 break; 2243 } 2244 xdp_out: 2245 rcu_read_unlock(); 2246 return ERR_PTR(-result); 2247 } 2248 2249 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2250 struct ixgbe_rx_buffer *rx_buffer, 2251 unsigned int size) 2252 { 2253 #if (PAGE_SIZE < 8192) 2254 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2255 2256 rx_buffer->page_offset ^= truesize; 2257 #else 2258 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2259 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2260 SKB_DATA_ALIGN(size); 2261 2262 rx_buffer->page_offset += truesize; 2263 #endif 2264 } 2265 2266 /** 2267 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2268 * @q_vector: structure containing interrupt and ring information 2269 * @rx_ring: rx descriptor ring to transact packets on 2270 * @budget: Total limit on number of packets to process 2271 * 2272 * This function provides a "bounce buffer" approach to Rx interrupt 2273 * processing. The advantage to this is that on systems that have 2274 * expensive overhead for IOMMU access this provides a means of avoiding 2275 * it by maintaining the mapping of the page to the syste. 2276 * 2277 * Returns amount of work completed 2278 **/ 2279 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2280 struct ixgbe_ring *rx_ring, 2281 const int budget) 2282 { 2283 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2284 struct ixgbe_adapter *adapter = q_vector->adapter; 2285 #ifdef IXGBE_FCOE 2286 int ddp_bytes; 2287 unsigned int mss = 0; 2288 #endif /* IXGBE_FCOE */ 2289 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2290 bool xdp_xmit = false; 2291 2292 while (likely(total_rx_packets < budget)) { 2293 union ixgbe_adv_rx_desc *rx_desc; 2294 struct ixgbe_rx_buffer *rx_buffer; 2295 struct sk_buff *skb; 2296 struct xdp_buff xdp; 2297 unsigned int size; 2298 2299 /* return some buffers to hardware, one at a time is too slow */ 2300 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2301 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2302 cleaned_count = 0; 2303 } 2304 2305 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2306 size = le16_to_cpu(rx_desc->wb.upper.length); 2307 if (!size) 2308 break; 2309 2310 /* This memory barrier is needed to keep us from reading 2311 * any other fields out of the rx_desc until we know the 2312 * descriptor has been written back 2313 */ 2314 dma_rmb(); 2315 2316 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2317 2318 /* retrieve a buffer from the ring */ 2319 if (!skb) { 2320 xdp.data = page_address(rx_buffer->page) + 2321 rx_buffer->page_offset; 2322 xdp.data_hard_start = xdp.data - 2323 ixgbe_rx_offset(rx_ring); 2324 xdp.data_end = xdp.data + size; 2325 2326 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2327 } 2328 2329 if (IS_ERR(skb)) { 2330 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2331 xdp_xmit = true; 2332 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2333 } else { 2334 rx_buffer->pagecnt_bias++; 2335 } 2336 total_rx_packets++; 2337 total_rx_bytes += size; 2338 } else if (skb) { 2339 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2340 } else if (ring_uses_build_skb(rx_ring)) { 2341 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2342 &xdp, rx_desc); 2343 } else { 2344 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2345 &xdp, rx_desc); 2346 } 2347 2348 /* exit if we failed to retrieve a buffer */ 2349 if (!skb) { 2350 rx_ring->rx_stats.alloc_rx_buff_failed++; 2351 rx_buffer->pagecnt_bias++; 2352 break; 2353 } 2354 2355 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2356 cleaned_count++; 2357 2358 /* place incomplete frames back on ring for completion */ 2359 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2360 continue; 2361 2362 /* verify the packet layout is correct */ 2363 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2364 continue; 2365 2366 /* probably a little skewed due to removing CRC */ 2367 total_rx_bytes += skb->len; 2368 2369 /* populate checksum, timestamp, VLAN, and protocol */ 2370 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2371 2372 #ifdef IXGBE_FCOE 2373 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2374 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2375 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2376 /* include DDPed FCoE data */ 2377 if (ddp_bytes > 0) { 2378 if (!mss) { 2379 mss = rx_ring->netdev->mtu - 2380 sizeof(struct fcoe_hdr) - 2381 sizeof(struct fc_frame_header) - 2382 sizeof(struct fcoe_crc_eof); 2383 if (mss > 512) 2384 mss &= ~511; 2385 } 2386 total_rx_bytes += ddp_bytes; 2387 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2388 mss); 2389 } 2390 if (!ddp_bytes) { 2391 dev_kfree_skb_any(skb); 2392 continue; 2393 } 2394 } 2395 2396 #endif /* IXGBE_FCOE */ 2397 ixgbe_rx_skb(q_vector, skb); 2398 2399 /* update budget accounting */ 2400 total_rx_packets++; 2401 } 2402 2403 if (xdp_xmit) { 2404 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2405 2406 /* Force memory writes to complete before letting h/w 2407 * know there are new descriptors to fetch. 2408 */ 2409 wmb(); 2410 writel(ring->next_to_use, ring->tail); 2411 } 2412 2413 u64_stats_update_begin(&rx_ring->syncp); 2414 rx_ring->stats.packets += total_rx_packets; 2415 rx_ring->stats.bytes += total_rx_bytes; 2416 u64_stats_update_end(&rx_ring->syncp); 2417 q_vector->rx.total_packets += total_rx_packets; 2418 q_vector->rx.total_bytes += total_rx_bytes; 2419 2420 return total_rx_packets; 2421 } 2422 2423 /** 2424 * ixgbe_configure_msix - Configure MSI-X hardware 2425 * @adapter: board private structure 2426 * 2427 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2428 * interrupts. 2429 **/ 2430 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2431 { 2432 struct ixgbe_q_vector *q_vector; 2433 int v_idx; 2434 u32 mask; 2435 2436 /* Populate MSIX to EITR Select */ 2437 if (adapter->num_vfs > 32) { 2438 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2440 } 2441 2442 /* 2443 * Populate the IVAR table and set the ITR values to the 2444 * corresponding register. 2445 */ 2446 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2447 struct ixgbe_ring *ring; 2448 q_vector = adapter->q_vector[v_idx]; 2449 2450 ixgbe_for_each_ring(ring, q_vector->rx) 2451 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2452 2453 ixgbe_for_each_ring(ring, q_vector->tx) 2454 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2455 2456 ixgbe_write_eitr(q_vector); 2457 } 2458 2459 switch (adapter->hw.mac.type) { 2460 case ixgbe_mac_82598EB: 2461 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2462 v_idx); 2463 break; 2464 case ixgbe_mac_82599EB: 2465 case ixgbe_mac_X540: 2466 case ixgbe_mac_X550: 2467 case ixgbe_mac_X550EM_x: 2468 case ixgbe_mac_x550em_a: 2469 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2470 break; 2471 default: 2472 break; 2473 } 2474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2475 2476 /* set up to autoclear timer, and the vectors */ 2477 mask = IXGBE_EIMS_ENABLE_MASK; 2478 mask &= ~(IXGBE_EIMS_OTHER | 2479 IXGBE_EIMS_MAILBOX | 2480 IXGBE_EIMS_LSC); 2481 2482 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2483 } 2484 2485 enum latency_range { 2486 lowest_latency = 0, 2487 low_latency = 1, 2488 bulk_latency = 2, 2489 latency_invalid = 255 2490 }; 2491 2492 /** 2493 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2494 * @q_vector: structure containing interrupt and ring information 2495 * @ring_container: structure containing ring performance data 2496 * 2497 * Stores a new ITR value based on packets and byte 2498 * counts during the last interrupt. The advantage of per interrupt 2499 * computation is faster updates and more accurate ITR for the current 2500 * traffic pattern. Constants in this function were computed 2501 * based on theoretical maximum wire speed and thresholds were set based 2502 * on testing data as well as attempting to minimize response time 2503 * while increasing bulk throughput. 2504 * this functionality is controlled by the InterruptThrottleRate module 2505 * parameter (see ixgbe_param.c) 2506 **/ 2507 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2508 struct ixgbe_ring_container *ring_container) 2509 { 2510 int bytes = ring_container->total_bytes; 2511 int packets = ring_container->total_packets; 2512 u32 timepassed_us; 2513 u64 bytes_perint; 2514 u8 itr_setting = ring_container->itr; 2515 2516 if (packets == 0) 2517 return; 2518 2519 /* simple throttlerate management 2520 * 0-10MB/s lowest (100000 ints/s) 2521 * 10-20MB/s low (20000 ints/s) 2522 * 20-1249MB/s bulk (12000 ints/s) 2523 */ 2524 /* what was last interrupt timeslice? */ 2525 timepassed_us = q_vector->itr >> 2; 2526 if (timepassed_us == 0) 2527 return; 2528 2529 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2530 2531 switch (itr_setting) { 2532 case lowest_latency: 2533 if (bytes_perint > 10) 2534 itr_setting = low_latency; 2535 break; 2536 case low_latency: 2537 if (bytes_perint > 20) 2538 itr_setting = bulk_latency; 2539 else if (bytes_perint <= 10) 2540 itr_setting = lowest_latency; 2541 break; 2542 case bulk_latency: 2543 if (bytes_perint <= 20) 2544 itr_setting = low_latency; 2545 break; 2546 } 2547 2548 /* clear work counters since we have the values we need */ 2549 ring_container->total_bytes = 0; 2550 ring_container->total_packets = 0; 2551 2552 /* write updated itr to ring container */ 2553 ring_container->itr = itr_setting; 2554 } 2555 2556 /** 2557 * ixgbe_write_eitr - write EITR register in hardware specific way 2558 * @q_vector: structure containing interrupt and ring information 2559 * 2560 * This function is made to be called by ethtool and by the driver 2561 * when it needs to update EITR registers at runtime. Hardware 2562 * specific quirks/differences are taken care of here. 2563 */ 2564 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2565 { 2566 struct ixgbe_adapter *adapter = q_vector->adapter; 2567 struct ixgbe_hw *hw = &adapter->hw; 2568 int v_idx = q_vector->v_idx; 2569 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2570 2571 switch (adapter->hw.mac.type) { 2572 case ixgbe_mac_82598EB: 2573 /* must write high and low 16 bits to reset counter */ 2574 itr_reg |= (itr_reg << 16); 2575 break; 2576 case ixgbe_mac_82599EB: 2577 case ixgbe_mac_X540: 2578 case ixgbe_mac_X550: 2579 case ixgbe_mac_X550EM_x: 2580 case ixgbe_mac_x550em_a: 2581 /* 2582 * set the WDIS bit to not clear the timer bits and cause an 2583 * immediate assertion of the interrupt 2584 */ 2585 itr_reg |= IXGBE_EITR_CNT_WDIS; 2586 break; 2587 default: 2588 break; 2589 } 2590 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2591 } 2592 2593 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2594 { 2595 u32 new_itr = q_vector->itr; 2596 u8 current_itr; 2597 2598 ixgbe_update_itr(q_vector, &q_vector->tx); 2599 ixgbe_update_itr(q_vector, &q_vector->rx); 2600 2601 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2602 2603 switch (current_itr) { 2604 /* counts and packets in update_itr are dependent on these numbers */ 2605 case lowest_latency: 2606 new_itr = IXGBE_100K_ITR; 2607 break; 2608 case low_latency: 2609 new_itr = IXGBE_20K_ITR; 2610 break; 2611 case bulk_latency: 2612 new_itr = IXGBE_12K_ITR; 2613 break; 2614 default: 2615 break; 2616 } 2617 2618 if (new_itr != q_vector->itr) { 2619 /* do an exponential smoothing */ 2620 new_itr = (10 * new_itr * q_vector->itr) / 2621 ((9 * new_itr) + q_vector->itr); 2622 2623 /* save the algorithm value here */ 2624 q_vector->itr = new_itr; 2625 2626 ixgbe_write_eitr(q_vector); 2627 } 2628 } 2629 2630 /** 2631 * ixgbe_check_overtemp_subtask - check for over temperature 2632 * @adapter: pointer to adapter 2633 **/ 2634 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2635 { 2636 struct ixgbe_hw *hw = &adapter->hw; 2637 u32 eicr = adapter->interrupt_event; 2638 s32 rc; 2639 2640 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2641 return; 2642 2643 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2644 return; 2645 2646 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2647 2648 switch (hw->device_id) { 2649 case IXGBE_DEV_ID_82599_T3_LOM: 2650 /* 2651 * Since the warning interrupt is for both ports 2652 * we don't have to check if: 2653 * - This interrupt wasn't for our port. 2654 * - We may have missed the interrupt so always have to 2655 * check if we got a LSC 2656 */ 2657 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2658 !(eicr & IXGBE_EICR_LSC)) 2659 return; 2660 2661 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2662 u32 speed; 2663 bool link_up = false; 2664 2665 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2666 2667 if (link_up) 2668 return; 2669 } 2670 2671 /* Check if this is not due to overtemp */ 2672 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2673 return; 2674 2675 break; 2676 case IXGBE_DEV_ID_X550EM_A_1G_T: 2677 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2678 rc = hw->phy.ops.check_overtemp(hw); 2679 if (rc != IXGBE_ERR_OVERTEMP) 2680 return; 2681 break; 2682 default: 2683 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2684 return; 2685 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2686 return; 2687 break; 2688 } 2689 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2690 2691 adapter->interrupt_event = 0; 2692 } 2693 2694 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2695 { 2696 struct ixgbe_hw *hw = &adapter->hw; 2697 2698 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2699 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2700 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2701 /* write to clear the interrupt */ 2702 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2703 } 2704 } 2705 2706 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2707 { 2708 struct ixgbe_hw *hw = &adapter->hw; 2709 2710 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2711 return; 2712 2713 switch (adapter->hw.mac.type) { 2714 case ixgbe_mac_82599EB: 2715 /* 2716 * Need to check link state so complete overtemp check 2717 * on service task 2718 */ 2719 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2720 (eicr & IXGBE_EICR_LSC)) && 2721 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2722 adapter->interrupt_event = eicr; 2723 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2724 ixgbe_service_event_schedule(adapter); 2725 return; 2726 } 2727 return; 2728 case ixgbe_mac_x550em_a: 2729 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2730 adapter->interrupt_event = eicr; 2731 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2732 ixgbe_service_event_schedule(adapter); 2733 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2734 IXGBE_EICR_GPI_SDP0_X550EM_a); 2735 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2736 IXGBE_EICR_GPI_SDP0_X550EM_a); 2737 } 2738 return; 2739 case ixgbe_mac_X550: 2740 case ixgbe_mac_X540: 2741 if (!(eicr & IXGBE_EICR_TS)) 2742 return; 2743 break; 2744 default: 2745 return; 2746 } 2747 2748 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2749 } 2750 2751 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2752 { 2753 switch (hw->mac.type) { 2754 case ixgbe_mac_82598EB: 2755 if (hw->phy.type == ixgbe_phy_nl) 2756 return true; 2757 return false; 2758 case ixgbe_mac_82599EB: 2759 case ixgbe_mac_X550EM_x: 2760 case ixgbe_mac_x550em_a: 2761 switch (hw->mac.ops.get_media_type(hw)) { 2762 case ixgbe_media_type_fiber: 2763 case ixgbe_media_type_fiber_qsfp: 2764 return true; 2765 default: 2766 return false; 2767 } 2768 default: 2769 return false; 2770 } 2771 } 2772 2773 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2774 { 2775 struct ixgbe_hw *hw = &adapter->hw; 2776 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2777 2778 if (!ixgbe_is_sfp(hw)) 2779 return; 2780 2781 /* Later MAC's use different SDP */ 2782 if (hw->mac.type >= ixgbe_mac_X540) 2783 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2784 2785 if (eicr & eicr_mask) { 2786 /* Clear the interrupt */ 2787 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2788 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2789 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2790 adapter->sfp_poll_time = 0; 2791 ixgbe_service_event_schedule(adapter); 2792 } 2793 } 2794 2795 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2796 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2797 /* Clear the interrupt */ 2798 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2799 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2800 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2801 ixgbe_service_event_schedule(adapter); 2802 } 2803 } 2804 } 2805 2806 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2807 { 2808 struct ixgbe_hw *hw = &adapter->hw; 2809 2810 adapter->lsc_int++; 2811 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2812 adapter->link_check_timeout = jiffies; 2813 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2814 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2815 IXGBE_WRITE_FLUSH(hw); 2816 ixgbe_service_event_schedule(adapter); 2817 } 2818 } 2819 2820 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2821 u64 qmask) 2822 { 2823 u32 mask; 2824 struct ixgbe_hw *hw = &adapter->hw; 2825 2826 switch (hw->mac.type) { 2827 case ixgbe_mac_82598EB: 2828 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2829 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2830 break; 2831 case ixgbe_mac_82599EB: 2832 case ixgbe_mac_X540: 2833 case ixgbe_mac_X550: 2834 case ixgbe_mac_X550EM_x: 2835 case ixgbe_mac_x550em_a: 2836 mask = (qmask & 0xFFFFFFFF); 2837 if (mask) 2838 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2839 mask = (qmask >> 32); 2840 if (mask) 2841 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2842 break; 2843 default: 2844 break; 2845 } 2846 /* skip the flush */ 2847 } 2848 2849 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2850 u64 qmask) 2851 { 2852 u32 mask; 2853 struct ixgbe_hw *hw = &adapter->hw; 2854 2855 switch (hw->mac.type) { 2856 case ixgbe_mac_82598EB: 2857 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2858 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2859 break; 2860 case ixgbe_mac_82599EB: 2861 case ixgbe_mac_X540: 2862 case ixgbe_mac_X550: 2863 case ixgbe_mac_X550EM_x: 2864 case ixgbe_mac_x550em_a: 2865 mask = (qmask & 0xFFFFFFFF); 2866 if (mask) 2867 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2868 mask = (qmask >> 32); 2869 if (mask) 2870 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2871 break; 2872 default: 2873 break; 2874 } 2875 /* skip the flush */ 2876 } 2877 2878 /** 2879 * ixgbe_irq_enable - Enable default interrupt generation settings 2880 * @adapter: board private structure 2881 **/ 2882 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2883 bool flush) 2884 { 2885 struct ixgbe_hw *hw = &adapter->hw; 2886 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2887 2888 /* don't reenable LSC while waiting for link */ 2889 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2890 mask &= ~IXGBE_EIMS_LSC; 2891 2892 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2893 switch (adapter->hw.mac.type) { 2894 case ixgbe_mac_82599EB: 2895 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2896 break; 2897 case ixgbe_mac_X540: 2898 case ixgbe_mac_X550: 2899 case ixgbe_mac_X550EM_x: 2900 case ixgbe_mac_x550em_a: 2901 mask |= IXGBE_EIMS_TS; 2902 break; 2903 default: 2904 break; 2905 } 2906 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2907 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2908 switch (adapter->hw.mac.type) { 2909 case ixgbe_mac_82599EB: 2910 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2911 mask |= IXGBE_EIMS_GPI_SDP2(hw); 2912 /* fall through */ 2913 case ixgbe_mac_X540: 2914 case ixgbe_mac_X550: 2915 case ixgbe_mac_X550EM_x: 2916 case ixgbe_mac_x550em_a: 2917 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 2918 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 2919 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 2920 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 2921 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 2922 mask |= IXGBE_EICR_GPI_SDP0_X540; 2923 mask |= IXGBE_EIMS_ECC; 2924 mask |= IXGBE_EIMS_MAILBOX; 2925 break; 2926 default: 2927 break; 2928 } 2929 2930 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2931 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2932 mask |= IXGBE_EIMS_FLOW_DIR; 2933 2934 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2935 if (queues) 2936 ixgbe_irq_enable_queues(adapter, ~0); 2937 if (flush) 2938 IXGBE_WRITE_FLUSH(&adapter->hw); 2939 } 2940 2941 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2942 { 2943 struct ixgbe_adapter *adapter = data; 2944 struct ixgbe_hw *hw = &adapter->hw; 2945 u32 eicr; 2946 2947 /* 2948 * Workaround for Silicon errata. Use clear-by-write instead 2949 * of clear-by-read. Reading with EICS will return the 2950 * interrupt causes without clearing, which later be done 2951 * with the write to EICR. 2952 */ 2953 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2954 2955 /* The lower 16bits of the EICR register are for the queue interrupts 2956 * which should be masked here in order to not accidentally clear them if 2957 * the bits are high when ixgbe_msix_other is called. There is a race 2958 * condition otherwise which results in possible performance loss 2959 * especially if the ixgbe_msix_other interrupt is triggering 2960 * consistently (as it would when PPS is turned on for the X540 device) 2961 */ 2962 eicr &= 0xFFFF0000; 2963 2964 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2965 2966 if (eicr & IXGBE_EICR_LSC) 2967 ixgbe_check_lsc(adapter); 2968 2969 if (eicr & IXGBE_EICR_MAILBOX) 2970 ixgbe_msg_task(adapter); 2971 2972 switch (hw->mac.type) { 2973 case ixgbe_mac_82599EB: 2974 case ixgbe_mac_X540: 2975 case ixgbe_mac_X550: 2976 case ixgbe_mac_X550EM_x: 2977 case ixgbe_mac_x550em_a: 2978 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 2979 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2980 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 2981 ixgbe_service_event_schedule(adapter); 2982 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2983 IXGBE_EICR_GPI_SDP0_X540); 2984 } 2985 if (eicr & IXGBE_EICR_ECC) { 2986 e_info(link, "Received ECC Err, initiating reset\n"); 2987 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 2988 ixgbe_service_event_schedule(adapter); 2989 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2990 } 2991 /* Handle Flow Director Full threshold interrupt */ 2992 if (eicr & IXGBE_EICR_FLOW_DIR) { 2993 int reinit_count = 0; 2994 int i; 2995 for (i = 0; i < adapter->num_tx_queues; i++) { 2996 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2997 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2998 &ring->state)) 2999 reinit_count++; 3000 } 3001 if (reinit_count) { 3002 /* no more flow director interrupts until after init */ 3003 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3004 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3005 ixgbe_service_event_schedule(adapter); 3006 } 3007 } 3008 ixgbe_check_sfp_event(adapter, eicr); 3009 ixgbe_check_overtemp_event(adapter, eicr); 3010 break; 3011 default: 3012 break; 3013 } 3014 3015 ixgbe_check_fan_failure(adapter, eicr); 3016 3017 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3018 ixgbe_ptp_check_pps_event(adapter); 3019 3020 /* re-enable the original interrupt state, no lsc, no queues */ 3021 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3022 ixgbe_irq_enable(adapter, false, false); 3023 3024 return IRQ_HANDLED; 3025 } 3026 3027 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3028 { 3029 struct ixgbe_q_vector *q_vector = data; 3030 3031 /* EIAM disabled interrupts (on this vector) for us */ 3032 3033 if (q_vector->rx.ring || q_vector->tx.ring) 3034 napi_schedule_irqoff(&q_vector->napi); 3035 3036 return IRQ_HANDLED; 3037 } 3038 3039 /** 3040 * ixgbe_poll - NAPI Rx polling callback 3041 * @napi: structure for representing this polling device 3042 * @budget: how many packets driver is allowed to clean 3043 * 3044 * This function is used for legacy and MSI, NAPI mode 3045 **/ 3046 int ixgbe_poll(struct napi_struct *napi, int budget) 3047 { 3048 struct ixgbe_q_vector *q_vector = 3049 container_of(napi, struct ixgbe_q_vector, napi); 3050 struct ixgbe_adapter *adapter = q_vector->adapter; 3051 struct ixgbe_ring *ring; 3052 int per_ring_budget, work_done = 0; 3053 bool clean_complete = true; 3054 3055 #ifdef CONFIG_IXGBE_DCA 3056 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3057 ixgbe_update_dca(q_vector); 3058 #endif 3059 3060 ixgbe_for_each_ring(ring, q_vector->tx) { 3061 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3062 clean_complete = false; 3063 } 3064 3065 /* Exit if we are called by netpoll */ 3066 if (budget <= 0) 3067 return budget; 3068 3069 /* attempt to distribute budget to each queue fairly, but don't allow 3070 * the budget to go below 1 because we'll exit polling */ 3071 if (q_vector->rx.count > 1) 3072 per_ring_budget = max(budget/q_vector->rx.count, 1); 3073 else 3074 per_ring_budget = budget; 3075 3076 ixgbe_for_each_ring(ring, q_vector->rx) { 3077 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3078 per_ring_budget); 3079 3080 work_done += cleaned; 3081 if (cleaned >= per_ring_budget) 3082 clean_complete = false; 3083 } 3084 3085 /* If all work not completed, return budget and keep polling */ 3086 if (!clean_complete) 3087 return budget; 3088 3089 /* all work done, exit the polling mode */ 3090 napi_complete_done(napi, work_done); 3091 if (adapter->rx_itr_setting & 1) 3092 ixgbe_set_itr(q_vector); 3093 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3094 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3095 3096 return min(work_done, budget - 1); 3097 } 3098 3099 /** 3100 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3101 * @adapter: board private structure 3102 * 3103 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3104 * interrupts from the kernel. 3105 **/ 3106 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3107 { 3108 struct net_device *netdev = adapter->netdev; 3109 unsigned int ri = 0, ti = 0; 3110 int vector, err; 3111 3112 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3113 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3114 struct msix_entry *entry = &adapter->msix_entries[vector]; 3115 3116 if (q_vector->tx.ring && q_vector->rx.ring) { 3117 snprintf(q_vector->name, sizeof(q_vector->name), 3118 "%s-TxRx-%u", netdev->name, ri++); 3119 ti++; 3120 } else if (q_vector->rx.ring) { 3121 snprintf(q_vector->name, sizeof(q_vector->name), 3122 "%s-rx-%u", netdev->name, ri++); 3123 } else if (q_vector->tx.ring) { 3124 snprintf(q_vector->name, sizeof(q_vector->name), 3125 "%s-tx-%u", netdev->name, ti++); 3126 } else { 3127 /* skip this unused q_vector */ 3128 continue; 3129 } 3130 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3131 q_vector->name, q_vector); 3132 if (err) { 3133 e_err(probe, "request_irq failed for MSIX interrupt " 3134 "Error: %d\n", err); 3135 goto free_queue_irqs; 3136 } 3137 /* If Flow Director is enabled, set interrupt affinity */ 3138 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3139 /* assign the mask for this irq */ 3140 irq_set_affinity_hint(entry->vector, 3141 &q_vector->affinity_mask); 3142 } 3143 } 3144 3145 err = request_irq(adapter->msix_entries[vector].vector, 3146 ixgbe_msix_other, 0, netdev->name, adapter); 3147 if (err) { 3148 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3149 goto free_queue_irqs; 3150 } 3151 3152 return 0; 3153 3154 free_queue_irqs: 3155 while (vector) { 3156 vector--; 3157 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3158 NULL); 3159 free_irq(adapter->msix_entries[vector].vector, 3160 adapter->q_vector[vector]); 3161 } 3162 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3163 pci_disable_msix(adapter->pdev); 3164 kfree(adapter->msix_entries); 3165 adapter->msix_entries = NULL; 3166 return err; 3167 } 3168 3169 /** 3170 * ixgbe_intr - legacy mode Interrupt Handler 3171 * @irq: interrupt number 3172 * @data: pointer to a network interface device structure 3173 **/ 3174 static irqreturn_t ixgbe_intr(int irq, void *data) 3175 { 3176 struct ixgbe_adapter *adapter = data; 3177 struct ixgbe_hw *hw = &adapter->hw; 3178 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3179 u32 eicr; 3180 3181 /* 3182 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3183 * before the read of EICR. 3184 */ 3185 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3186 3187 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3188 * therefore no explicit interrupt disable is necessary */ 3189 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3190 if (!eicr) { 3191 /* 3192 * shared interrupt alert! 3193 * make sure interrupts are enabled because the read will 3194 * have disabled interrupts due to EIAM 3195 * finish the workaround of silicon errata on 82598. Unmask 3196 * the interrupt that we masked before the EICR read. 3197 */ 3198 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3199 ixgbe_irq_enable(adapter, true, true); 3200 return IRQ_NONE; /* Not our interrupt */ 3201 } 3202 3203 if (eicr & IXGBE_EICR_LSC) 3204 ixgbe_check_lsc(adapter); 3205 3206 switch (hw->mac.type) { 3207 case ixgbe_mac_82599EB: 3208 ixgbe_check_sfp_event(adapter, eicr); 3209 /* Fall through */ 3210 case ixgbe_mac_X540: 3211 case ixgbe_mac_X550: 3212 case ixgbe_mac_X550EM_x: 3213 case ixgbe_mac_x550em_a: 3214 if (eicr & IXGBE_EICR_ECC) { 3215 e_info(link, "Received ECC Err, initiating reset\n"); 3216 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3217 ixgbe_service_event_schedule(adapter); 3218 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3219 } 3220 ixgbe_check_overtemp_event(adapter, eicr); 3221 break; 3222 default: 3223 break; 3224 } 3225 3226 ixgbe_check_fan_failure(adapter, eicr); 3227 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3228 ixgbe_ptp_check_pps_event(adapter); 3229 3230 /* would disable interrupts here but EIAM disabled it */ 3231 napi_schedule_irqoff(&q_vector->napi); 3232 3233 /* 3234 * re-enable link(maybe) and non-queue interrupts, no flush. 3235 * ixgbe_poll will re-enable the queue interrupts 3236 */ 3237 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3238 ixgbe_irq_enable(adapter, false, false); 3239 3240 return IRQ_HANDLED; 3241 } 3242 3243 /** 3244 * ixgbe_request_irq - initialize interrupts 3245 * @adapter: board private structure 3246 * 3247 * Attempts to configure interrupts using the best available 3248 * capabilities of the hardware and kernel. 3249 **/ 3250 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3251 { 3252 struct net_device *netdev = adapter->netdev; 3253 int err; 3254 3255 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3256 err = ixgbe_request_msix_irqs(adapter); 3257 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3258 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3259 netdev->name, adapter); 3260 else 3261 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3262 netdev->name, adapter); 3263 3264 if (err) 3265 e_err(probe, "request_irq failed, Error %d\n", err); 3266 3267 return err; 3268 } 3269 3270 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3271 { 3272 int vector; 3273 3274 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3275 free_irq(adapter->pdev->irq, adapter); 3276 return; 3277 } 3278 3279 if (!adapter->msix_entries) 3280 return; 3281 3282 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3283 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3284 struct msix_entry *entry = &adapter->msix_entries[vector]; 3285 3286 /* free only the irqs that were actually requested */ 3287 if (!q_vector->rx.ring && !q_vector->tx.ring) 3288 continue; 3289 3290 /* clear the affinity_mask in the IRQ descriptor */ 3291 irq_set_affinity_hint(entry->vector, NULL); 3292 3293 free_irq(entry->vector, q_vector); 3294 } 3295 3296 free_irq(adapter->msix_entries[vector].vector, adapter); 3297 } 3298 3299 /** 3300 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3301 * @adapter: board private structure 3302 **/ 3303 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3304 { 3305 switch (adapter->hw.mac.type) { 3306 case ixgbe_mac_82598EB: 3307 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3308 break; 3309 case ixgbe_mac_82599EB: 3310 case ixgbe_mac_X540: 3311 case ixgbe_mac_X550: 3312 case ixgbe_mac_X550EM_x: 3313 case ixgbe_mac_x550em_a: 3314 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3316 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3317 break; 3318 default: 3319 break; 3320 } 3321 IXGBE_WRITE_FLUSH(&adapter->hw); 3322 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3323 int vector; 3324 3325 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3326 synchronize_irq(adapter->msix_entries[vector].vector); 3327 3328 synchronize_irq(adapter->msix_entries[vector++].vector); 3329 } else { 3330 synchronize_irq(adapter->pdev->irq); 3331 } 3332 } 3333 3334 /** 3335 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3336 * 3337 **/ 3338 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3339 { 3340 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3341 3342 ixgbe_write_eitr(q_vector); 3343 3344 ixgbe_set_ivar(adapter, 0, 0, 0); 3345 ixgbe_set_ivar(adapter, 1, 0, 0); 3346 3347 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3348 } 3349 3350 /** 3351 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3352 * @adapter: board private structure 3353 * @ring: structure containing ring specific data 3354 * 3355 * Configure the Tx descriptor ring after a reset. 3356 **/ 3357 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3358 struct ixgbe_ring *ring) 3359 { 3360 struct ixgbe_hw *hw = &adapter->hw; 3361 u64 tdba = ring->dma; 3362 int wait_loop = 10; 3363 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3364 u8 reg_idx = ring->reg_idx; 3365 3366 /* disable queue to avoid issues while updating state */ 3367 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3368 IXGBE_WRITE_FLUSH(hw); 3369 3370 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3371 (tdba & DMA_BIT_MASK(32))); 3372 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3373 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3374 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3375 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3376 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3377 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3378 3379 /* 3380 * set WTHRESH to encourage burst writeback, it should not be set 3381 * higher than 1 when: 3382 * - ITR is 0 as it could cause false TX hangs 3383 * - ITR is set to > 100k int/sec and BQL is enabled 3384 * 3385 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3386 * to or less than the number of on chip descriptors, which is 3387 * currently 40. 3388 */ 3389 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3390 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3391 else 3392 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3393 3394 /* 3395 * Setting PTHRESH to 32 both improves performance 3396 * and avoids a TX hang with DFP enabled 3397 */ 3398 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3399 32; /* PTHRESH = 32 */ 3400 3401 /* reinitialize flowdirector state */ 3402 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3403 ring->atr_sample_rate = adapter->atr_sample_rate; 3404 ring->atr_count = 0; 3405 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3406 } else { 3407 ring->atr_sample_rate = 0; 3408 } 3409 3410 /* initialize XPS */ 3411 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3412 struct ixgbe_q_vector *q_vector = ring->q_vector; 3413 3414 if (q_vector) 3415 netif_set_xps_queue(ring->netdev, 3416 &q_vector->affinity_mask, 3417 ring->queue_index); 3418 } 3419 3420 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3421 3422 /* reinitialize tx_buffer_info */ 3423 memset(ring->tx_buffer_info, 0, 3424 sizeof(struct ixgbe_tx_buffer) * ring->count); 3425 3426 /* enable queue */ 3427 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3428 3429 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3430 if (hw->mac.type == ixgbe_mac_82598EB && 3431 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3432 return; 3433 3434 /* poll to verify queue is enabled */ 3435 do { 3436 usleep_range(1000, 2000); 3437 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3438 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3439 if (!wait_loop) 3440 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3441 } 3442 3443 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3444 { 3445 struct ixgbe_hw *hw = &adapter->hw; 3446 u32 rttdcs, mtqc; 3447 u8 tcs = netdev_get_num_tc(adapter->netdev); 3448 3449 if (hw->mac.type == ixgbe_mac_82598EB) 3450 return; 3451 3452 /* disable the arbiter while setting MTQC */ 3453 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3454 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3455 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3456 3457 /* set transmit pool layout */ 3458 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3459 mtqc = IXGBE_MTQC_VT_ENA; 3460 if (tcs > 4) 3461 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3462 else if (tcs > 1) 3463 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3464 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3465 IXGBE_82599_VMDQ_4Q_MASK) 3466 mtqc |= IXGBE_MTQC_32VF; 3467 else 3468 mtqc |= IXGBE_MTQC_64VF; 3469 } else { 3470 if (tcs > 4) 3471 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3472 else if (tcs > 1) 3473 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3474 else 3475 mtqc = IXGBE_MTQC_64Q_1PB; 3476 } 3477 3478 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3479 3480 /* Enable Security TX Buffer IFG for multiple pb */ 3481 if (tcs) { 3482 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3483 sectx |= IXGBE_SECTX_DCB; 3484 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3485 } 3486 3487 /* re-enable the arbiter */ 3488 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3489 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3490 } 3491 3492 /** 3493 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3494 * @adapter: board private structure 3495 * 3496 * Configure the Tx unit of the MAC after a reset. 3497 **/ 3498 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3499 { 3500 struct ixgbe_hw *hw = &adapter->hw; 3501 u32 dmatxctl; 3502 u32 i; 3503 3504 ixgbe_setup_mtqc(adapter); 3505 3506 if (hw->mac.type != ixgbe_mac_82598EB) { 3507 /* DMATXCTL.EN must be before Tx queues are enabled */ 3508 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3509 dmatxctl |= IXGBE_DMATXCTL_TE; 3510 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3511 } 3512 3513 /* Setup the HW Tx Head and Tail descriptor pointers */ 3514 for (i = 0; i < adapter->num_tx_queues; i++) 3515 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3516 for (i = 0; i < adapter->num_xdp_queues; i++) 3517 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3518 } 3519 3520 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3521 struct ixgbe_ring *ring) 3522 { 3523 struct ixgbe_hw *hw = &adapter->hw; 3524 u8 reg_idx = ring->reg_idx; 3525 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3526 3527 srrctl |= IXGBE_SRRCTL_DROP_EN; 3528 3529 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3530 } 3531 3532 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3533 struct ixgbe_ring *ring) 3534 { 3535 struct ixgbe_hw *hw = &adapter->hw; 3536 u8 reg_idx = ring->reg_idx; 3537 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3538 3539 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3540 3541 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3542 } 3543 3544 #ifdef CONFIG_IXGBE_DCB 3545 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3546 #else 3547 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3548 #endif 3549 { 3550 int i; 3551 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3552 3553 if (adapter->ixgbe_ieee_pfc) 3554 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3555 3556 /* 3557 * We should set the drop enable bit if: 3558 * SR-IOV is enabled 3559 * or 3560 * Number of Rx queues > 1 and flow control is disabled 3561 * 3562 * This allows us to avoid head of line blocking for security 3563 * and performance reasons. 3564 */ 3565 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3566 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3567 for (i = 0; i < adapter->num_rx_queues; i++) 3568 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3569 } else { 3570 for (i = 0; i < adapter->num_rx_queues; i++) 3571 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3572 } 3573 } 3574 3575 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3576 3577 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3578 struct ixgbe_ring *rx_ring) 3579 { 3580 struct ixgbe_hw *hw = &adapter->hw; 3581 u32 srrctl; 3582 u8 reg_idx = rx_ring->reg_idx; 3583 3584 if (hw->mac.type == ixgbe_mac_82598EB) { 3585 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3586 3587 /* 3588 * if VMDq is not active we must program one srrctl register 3589 * per RSS queue since we have enabled RDRXCTL.MVMEN 3590 */ 3591 reg_idx &= mask; 3592 } 3593 3594 /* configure header buffer length, needed for RSC */ 3595 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3596 3597 /* configure the packet buffer length */ 3598 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3599 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3600 else 3601 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3602 3603 /* configure descriptor type */ 3604 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3605 3606 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3607 } 3608 3609 /** 3610 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3611 * @adapter: device handle 3612 * 3613 * - 82598/82599/X540: 128 3614 * - X550(non-SRIOV mode): 512 3615 * - X550(SRIOV mode): 64 3616 */ 3617 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3618 { 3619 if (adapter->hw.mac.type < ixgbe_mac_X550) 3620 return 128; 3621 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3622 return 64; 3623 else 3624 return 512; 3625 } 3626 3627 /** 3628 * ixgbe_store_key - Write the RSS key to HW 3629 * @adapter: device handle 3630 * 3631 * Write the RSS key stored in adapter.rss_key to HW. 3632 */ 3633 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3634 { 3635 struct ixgbe_hw *hw = &adapter->hw; 3636 int i; 3637 3638 for (i = 0; i < 10; i++) 3639 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3640 } 3641 3642 /** 3643 * ixgbe_init_rss_key - Initialize adapter RSS key 3644 * @adapter: device handle 3645 * 3646 * Allocates and initializes the RSS key if it is not allocated. 3647 **/ 3648 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3649 { 3650 u32 *rss_key; 3651 3652 if (!adapter->rss_key) { 3653 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3654 if (unlikely(!rss_key)) 3655 return -ENOMEM; 3656 3657 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3658 adapter->rss_key = rss_key; 3659 } 3660 3661 return 0; 3662 } 3663 3664 /** 3665 * ixgbe_store_reta - Write the RETA table to HW 3666 * @adapter: device handle 3667 * 3668 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3669 */ 3670 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3671 { 3672 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3673 struct ixgbe_hw *hw = &adapter->hw; 3674 u32 reta = 0; 3675 u32 indices_multi; 3676 u8 *indir_tbl = adapter->rss_indir_tbl; 3677 3678 /* Fill out the redirection table as follows: 3679 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3680 * indices. 3681 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3682 * - X550: 8 bit wide entries containing 6 bit RSS index 3683 */ 3684 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3685 indices_multi = 0x11; 3686 else 3687 indices_multi = 0x1; 3688 3689 /* Write redirection table to HW */ 3690 for (i = 0; i < reta_entries; i++) { 3691 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3692 if ((i & 3) == 3) { 3693 if (i < 128) 3694 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3695 else 3696 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3697 reta); 3698 reta = 0; 3699 } 3700 } 3701 } 3702 3703 /** 3704 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3705 * @adapter: device handle 3706 * 3707 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3708 */ 3709 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3710 { 3711 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3712 struct ixgbe_hw *hw = &adapter->hw; 3713 u32 vfreta = 0; 3714 unsigned int pf_pool = adapter->num_vfs; 3715 3716 /* Write redirection table to HW */ 3717 for (i = 0; i < reta_entries; i++) { 3718 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3719 if ((i & 3) == 3) { 3720 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3721 vfreta); 3722 vfreta = 0; 3723 } 3724 } 3725 } 3726 3727 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3728 { 3729 u32 i, j; 3730 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3731 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3732 3733 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3734 * make full use of any rings they may have. We will use the 3735 * PSRTYPE register to control how many rings we use within the PF. 3736 */ 3737 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3738 rss_i = 4; 3739 3740 /* Fill out hash function seeds */ 3741 ixgbe_store_key(adapter); 3742 3743 /* Fill out redirection table */ 3744 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3745 3746 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3747 if (j == rss_i) 3748 j = 0; 3749 3750 adapter->rss_indir_tbl[i] = j; 3751 } 3752 3753 ixgbe_store_reta(adapter); 3754 } 3755 3756 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3757 { 3758 struct ixgbe_hw *hw = &adapter->hw; 3759 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3760 unsigned int pf_pool = adapter->num_vfs; 3761 int i, j; 3762 3763 /* Fill out hash function seeds */ 3764 for (i = 0; i < 10; i++) 3765 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), 3766 *(adapter->rss_key + i)); 3767 3768 /* Fill out the redirection table */ 3769 for (i = 0, j = 0; i < 64; i++, j++) { 3770 if (j == rss_i) 3771 j = 0; 3772 3773 adapter->rss_indir_tbl[i] = j; 3774 } 3775 3776 ixgbe_store_vfreta(adapter); 3777 } 3778 3779 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3780 { 3781 struct ixgbe_hw *hw = &adapter->hw; 3782 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3783 u32 rxcsum; 3784 3785 /* Disable indicating checksum in descriptor, enables RSS hash */ 3786 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3787 rxcsum |= IXGBE_RXCSUM_PCSD; 3788 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3789 3790 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3791 if (adapter->ring_feature[RING_F_RSS].mask) 3792 mrqc = IXGBE_MRQC_RSSEN; 3793 } else { 3794 u8 tcs = netdev_get_num_tc(adapter->netdev); 3795 3796 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3797 if (tcs > 4) 3798 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3799 else if (tcs > 1) 3800 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3801 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3802 IXGBE_82599_VMDQ_4Q_MASK) 3803 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3804 else 3805 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3806 3807 /* Enable L3/L4 for Tx Switched packets */ 3808 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3809 } else { 3810 if (tcs > 4) 3811 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3812 else if (tcs > 1) 3813 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3814 else 3815 mrqc = IXGBE_MRQC_RSSEN; 3816 } 3817 } 3818 3819 /* Perform hash on these packet types */ 3820 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3821 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3822 IXGBE_MRQC_RSS_FIELD_IPV6 | 3823 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3824 3825 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3826 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3827 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3828 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3829 3830 if ((hw->mac.type >= ixgbe_mac_X550) && 3831 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3832 unsigned int pf_pool = adapter->num_vfs; 3833 3834 /* Enable VF RSS mode */ 3835 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3836 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3837 3838 /* Setup RSS through the VF registers */ 3839 ixgbe_setup_vfreta(adapter); 3840 vfmrqc = IXGBE_MRQC_RSSEN; 3841 vfmrqc |= rss_field; 3842 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3843 } else { 3844 ixgbe_setup_reta(adapter); 3845 mrqc |= rss_field; 3846 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3847 } 3848 } 3849 3850 /** 3851 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3852 * @adapter: address of board private structure 3853 * @index: index of ring to set 3854 **/ 3855 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3856 struct ixgbe_ring *ring) 3857 { 3858 struct ixgbe_hw *hw = &adapter->hw; 3859 u32 rscctrl; 3860 u8 reg_idx = ring->reg_idx; 3861 3862 if (!ring_is_rsc_enabled(ring)) 3863 return; 3864 3865 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3866 rscctrl |= IXGBE_RSCCTL_RSCEN; 3867 /* 3868 * we must limit the number of descriptors so that the 3869 * total size of max desc * buf_len is not greater 3870 * than 65536 3871 */ 3872 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3873 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3874 } 3875 3876 #define IXGBE_MAX_RX_DESC_POLL 10 3877 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3878 struct ixgbe_ring *ring) 3879 { 3880 struct ixgbe_hw *hw = &adapter->hw; 3881 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3882 u32 rxdctl; 3883 u8 reg_idx = ring->reg_idx; 3884 3885 if (ixgbe_removed(hw->hw_addr)) 3886 return; 3887 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3888 if (hw->mac.type == ixgbe_mac_82598EB && 3889 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3890 return; 3891 3892 do { 3893 usleep_range(1000, 2000); 3894 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3895 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3896 3897 if (!wait_loop) { 3898 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3899 "the polling period\n", reg_idx); 3900 } 3901 } 3902 3903 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3904 struct ixgbe_ring *ring) 3905 { 3906 struct ixgbe_hw *hw = &adapter->hw; 3907 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3908 u32 rxdctl; 3909 u8 reg_idx = ring->reg_idx; 3910 3911 if (ixgbe_removed(hw->hw_addr)) 3912 return; 3913 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3914 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3915 3916 /* write value back with RXDCTL.ENABLE bit cleared */ 3917 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3918 3919 if (hw->mac.type == ixgbe_mac_82598EB && 3920 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3921 return; 3922 3923 /* the hardware may take up to 100us to really disable the rx queue */ 3924 do { 3925 udelay(10); 3926 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3927 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3928 3929 if (!wait_loop) { 3930 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3931 "the polling period\n", reg_idx); 3932 } 3933 } 3934 3935 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3936 struct ixgbe_ring *ring) 3937 { 3938 struct ixgbe_hw *hw = &adapter->hw; 3939 union ixgbe_adv_rx_desc *rx_desc; 3940 u64 rdba = ring->dma; 3941 u32 rxdctl; 3942 u8 reg_idx = ring->reg_idx; 3943 3944 /* disable queue to avoid issues while updating state */ 3945 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3946 ixgbe_disable_rx_queue(adapter, ring); 3947 3948 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3949 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3950 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3951 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3952 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 3953 IXGBE_WRITE_FLUSH(hw); 3954 3955 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3956 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3957 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3958 3959 ixgbe_configure_srrctl(adapter, ring); 3960 ixgbe_configure_rscctl(adapter, ring); 3961 3962 if (hw->mac.type == ixgbe_mac_82598EB) { 3963 /* 3964 * enable cache line friendly hardware writes: 3965 * PTHRESH=32 descriptors (half the internal cache), 3966 * this also removes ugly rx_no_buffer_count increment 3967 * HTHRESH=4 descriptors (to minimize latency on fetch) 3968 * WTHRESH=8 burst writeback up to two cache lines 3969 */ 3970 rxdctl &= ~0x3FFFFF; 3971 rxdctl |= 0x080420; 3972 #if (PAGE_SIZE < 8192) 3973 } else { 3974 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 3975 IXGBE_RXDCTL_RLPML_EN); 3976 3977 /* Limit the maximum frame size so we don't overrun the skb */ 3978 if (ring_uses_build_skb(ring) && 3979 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 3980 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 3981 IXGBE_RXDCTL_RLPML_EN; 3982 #endif 3983 } 3984 3985 /* initialize rx_buffer_info */ 3986 memset(ring->rx_buffer_info, 0, 3987 sizeof(struct ixgbe_rx_buffer) * ring->count); 3988 3989 /* initialize Rx descriptor 0 */ 3990 rx_desc = IXGBE_RX_DESC(ring, 0); 3991 rx_desc->wb.upper.length = 0; 3992 3993 /* enable receive descriptor ring */ 3994 rxdctl |= IXGBE_RXDCTL_ENABLE; 3995 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3996 3997 ixgbe_rx_desc_queue_enable(adapter, ring); 3998 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3999 } 4000 4001 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4002 { 4003 struct ixgbe_hw *hw = &adapter->hw; 4004 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4005 u16 pool; 4006 4007 /* PSRTYPE must be initialized in non 82598 adapters */ 4008 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4009 IXGBE_PSRTYPE_UDPHDR | 4010 IXGBE_PSRTYPE_IPV4HDR | 4011 IXGBE_PSRTYPE_L2HDR | 4012 IXGBE_PSRTYPE_IPV6HDR; 4013 4014 if (hw->mac.type == ixgbe_mac_82598EB) 4015 return; 4016 4017 if (rss_i > 3) 4018 psrtype |= 2u << 29; 4019 else if (rss_i > 1) 4020 psrtype |= 1u << 29; 4021 4022 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 4023 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4024 } 4025 4026 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4027 { 4028 struct ixgbe_hw *hw = &adapter->hw; 4029 u32 reg_offset, vf_shift; 4030 u32 gcr_ext, vmdctl; 4031 int i; 4032 4033 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4034 return; 4035 4036 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4037 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4038 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4039 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4040 vmdctl |= IXGBE_VT_CTL_REPLEN; 4041 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4042 4043 vf_shift = VMDQ_P(0) % 32; 4044 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4045 4046 /* Enable only the PF's pool for Tx/Rx */ 4047 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4048 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4049 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4050 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4051 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4052 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4053 4054 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4055 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4056 4057 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4058 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4059 4060 /* 4061 * Set up VF register offsets for selected VT Mode, 4062 * i.e. 32 or 64 VFs for SR-IOV 4063 */ 4064 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4065 case IXGBE_82599_VMDQ_8Q_MASK: 4066 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4067 break; 4068 case IXGBE_82599_VMDQ_4Q_MASK: 4069 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4070 break; 4071 default: 4072 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4073 break; 4074 } 4075 4076 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4077 4078 for (i = 0; i < adapter->num_vfs; i++) { 4079 /* configure spoof checking */ 4080 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4081 adapter->vfinfo[i].spoofchk_enabled); 4082 4083 /* Enable/Disable RSS query feature */ 4084 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4085 adapter->vfinfo[i].rss_query_enabled); 4086 } 4087 } 4088 4089 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4090 { 4091 struct ixgbe_hw *hw = &adapter->hw; 4092 struct net_device *netdev = adapter->netdev; 4093 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4094 struct ixgbe_ring *rx_ring; 4095 int i; 4096 u32 mhadd, hlreg0; 4097 4098 #ifdef IXGBE_FCOE 4099 /* adjust max frame to be able to do baby jumbo for FCoE */ 4100 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4101 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4102 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4103 4104 #endif /* IXGBE_FCOE */ 4105 4106 /* adjust max frame to be at least the size of a standard frame */ 4107 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4108 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4109 4110 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4111 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4112 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4113 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4114 4115 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4116 } 4117 4118 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4119 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4120 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4121 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4122 4123 /* 4124 * Setup the HW Rx Head and Tail Descriptor Pointers and 4125 * the Base and Length of the Rx Descriptor Ring 4126 */ 4127 for (i = 0; i < adapter->num_rx_queues; i++) { 4128 rx_ring = adapter->rx_ring[i]; 4129 4130 clear_ring_rsc_enabled(rx_ring); 4131 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4132 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4133 4134 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4135 set_ring_rsc_enabled(rx_ring); 4136 4137 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4138 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4139 4140 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4141 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4142 continue; 4143 4144 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4145 4146 #if (PAGE_SIZE < 8192) 4147 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4148 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4149 4150 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4151 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4152 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4153 #endif 4154 } 4155 } 4156 4157 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4158 { 4159 struct ixgbe_hw *hw = &adapter->hw; 4160 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4161 4162 switch (hw->mac.type) { 4163 case ixgbe_mac_82598EB: 4164 /* 4165 * For VMDq support of different descriptor types or 4166 * buffer sizes through the use of multiple SRRCTL 4167 * registers, RDRXCTL.MVMEN must be set to 1 4168 * 4169 * also, the manual doesn't mention it clearly but DCA hints 4170 * will only use queue 0's tags unless this bit is set. Side 4171 * effects of setting this bit are only that SRRCTL must be 4172 * fully programmed [0..15] 4173 */ 4174 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4175 break; 4176 case ixgbe_mac_X550: 4177 case ixgbe_mac_X550EM_x: 4178 case ixgbe_mac_x550em_a: 4179 if (adapter->num_vfs) 4180 rdrxctl |= IXGBE_RDRXCTL_PSP; 4181 /* fall through */ 4182 case ixgbe_mac_82599EB: 4183 case ixgbe_mac_X540: 4184 /* Disable RSC for ACK packets */ 4185 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4186 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4187 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4188 /* hardware requires some bits to be set by default */ 4189 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4190 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4191 break; 4192 default: 4193 /* We should do nothing since we don't know this hardware */ 4194 return; 4195 } 4196 4197 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4198 } 4199 4200 /** 4201 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4202 * @adapter: board private structure 4203 * 4204 * Configure the Rx unit of the MAC after a reset. 4205 **/ 4206 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4207 { 4208 struct ixgbe_hw *hw = &adapter->hw; 4209 int i; 4210 u32 rxctrl, rfctl; 4211 4212 /* disable receives while setting up the descriptors */ 4213 hw->mac.ops.disable_rx(hw); 4214 4215 ixgbe_setup_psrtype(adapter); 4216 ixgbe_setup_rdrxctl(adapter); 4217 4218 /* RSC Setup */ 4219 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4220 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4221 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4222 rfctl |= IXGBE_RFCTL_RSC_DIS; 4223 4224 /* disable NFS filtering */ 4225 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4226 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4227 4228 /* Program registers for the distribution of queues */ 4229 ixgbe_setup_mrqc(adapter); 4230 4231 /* set_rx_buffer_len must be called before ring initialization */ 4232 ixgbe_set_rx_buffer_len(adapter); 4233 4234 /* 4235 * Setup the HW Rx Head and Tail Descriptor Pointers and 4236 * the Base and Length of the Rx Descriptor Ring 4237 */ 4238 for (i = 0; i < adapter->num_rx_queues; i++) 4239 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4240 4241 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4242 /* disable drop enable for 82598 parts */ 4243 if (hw->mac.type == ixgbe_mac_82598EB) 4244 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4245 4246 /* enable all receives */ 4247 rxctrl |= IXGBE_RXCTRL_RXEN; 4248 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4249 } 4250 4251 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4252 __be16 proto, u16 vid) 4253 { 4254 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4255 struct ixgbe_hw *hw = &adapter->hw; 4256 4257 /* add VID to filter table */ 4258 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4259 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4260 4261 set_bit(vid, adapter->active_vlans); 4262 4263 return 0; 4264 } 4265 4266 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4267 { 4268 u32 vlvf; 4269 int idx; 4270 4271 /* short cut the special case */ 4272 if (vlan == 0) 4273 return 0; 4274 4275 /* Search for the vlan id in the VLVF entries */ 4276 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4277 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4278 if ((vlvf & VLAN_VID_MASK) == vlan) 4279 break; 4280 } 4281 4282 return idx; 4283 } 4284 4285 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4286 { 4287 struct ixgbe_hw *hw = &adapter->hw; 4288 u32 bits, word; 4289 int idx; 4290 4291 idx = ixgbe_find_vlvf_entry(hw, vid); 4292 if (!idx) 4293 return; 4294 4295 /* See if any other pools are set for this VLAN filter 4296 * entry other than the PF. 4297 */ 4298 word = idx * 2 + (VMDQ_P(0) / 32); 4299 bits = ~BIT(VMDQ_P(0) % 32); 4300 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4301 4302 /* Disable the filter so this falls into the default pool. */ 4303 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4304 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4305 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4306 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4307 } 4308 } 4309 4310 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4311 __be16 proto, u16 vid) 4312 { 4313 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4314 struct ixgbe_hw *hw = &adapter->hw; 4315 4316 /* remove VID from filter table */ 4317 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4318 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4319 4320 clear_bit(vid, adapter->active_vlans); 4321 4322 return 0; 4323 } 4324 4325 /** 4326 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4327 * @adapter: driver data 4328 */ 4329 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4330 { 4331 struct ixgbe_hw *hw = &adapter->hw; 4332 u32 vlnctrl; 4333 int i, j; 4334 4335 switch (hw->mac.type) { 4336 case ixgbe_mac_82598EB: 4337 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4338 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4339 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4340 break; 4341 case ixgbe_mac_82599EB: 4342 case ixgbe_mac_X540: 4343 case ixgbe_mac_X550: 4344 case ixgbe_mac_X550EM_x: 4345 case ixgbe_mac_x550em_a: 4346 for (i = 0; i < adapter->num_rx_queues; i++) { 4347 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4348 4349 if (ring->l2_accel_priv) 4350 continue; 4351 j = ring->reg_idx; 4352 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4353 vlnctrl &= ~IXGBE_RXDCTL_VME; 4354 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4355 } 4356 break; 4357 default: 4358 break; 4359 } 4360 } 4361 4362 /** 4363 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4364 * @adapter: driver data 4365 */ 4366 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4367 { 4368 struct ixgbe_hw *hw = &adapter->hw; 4369 u32 vlnctrl; 4370 int i, j; 4371 4372 switch (hw->mac.type) { 4373 case ixgbe_mac_82598EB: 4374 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4375 vlnctrl |= IXGBE_VLNCTRL_VME; 4376 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4377 break; 4378 case ixgbe_mac_82599EB: 4379 case ixgbe_mac_X540: 4380 case ixgbe_mac_X550: 4381 case ixgbe_mac_X550EM_x: 4382 case ixgbe_mac_x550em_a: 4383 for (i = 0; i < adapter->num_rx_queues; i++) { 4384 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4385 4386 if (ring->l2_accel_priv) 4387 continue; 4388 j = ring->reg_idx; 4389 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4390 vlnctrl |= IXGBE_RXDCTL_VME; 4391 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4392 } 4393 break; 4394 default: 4395 break; 4396 } 4397 } 4398 4399 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4400 { 4401 struct ixgbe_hw *hw = &adapter->hw; 4402 u32 vlnctrl, i; 4403 4404 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4405 4406 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4407 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4408 vlnctrl |= IXGBE_VLNCTRL_VFE; 4409 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4410 } else { 4411 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4412 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4413 return; 4414 } 4415 4416 /* Nothing to do for 82598 */ 4417 if (hw->mac.type == ixgbe_mac_82598EB) 4418 return; 4419 4420 /* We are already in VLAN promisc, nothing to do */ 4421 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4422 return; 4423 4424 /* Set flag so we don't redo unnecessary work */ 4425 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4426 4427 /* Add PF to all active pools */ 4428 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4429 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4430 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4431 4432 vlvfb |= BIT(VMDQ_P(0) % 32); 4433 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4434 } 4435 4436 /* Set all bits in the VLAN filter table array */ 4437 for (i = hw->mac.vft_size; i--;) 4438 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4439 } 4440 4441 #define VFTA_BLOCK_SIZE 8 4442 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4443 { 4444 struct ixgbe_hw *hw = &adapter->hw; 4445 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4446 u32 vid_start = vfta_offset * 32; 4447 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4448 u32 i, vid, word, bits; 4449 4450 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4451 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4452 4453 /* pull VLAN ID from VLVF */ 4454 vid = vlvf & VLAN_VID_MASK; 4455 4456 /* only concern outselves with a certain range */ 4457 if (vid < vid_start || vid >= vid_end) 4458 continue; 4459 4460 if (vlvf) { 4461 /* record VLAN ID in VFTA */ 4462 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4463 4464 /* if PF is part of this then continue */ 4465 if (test_bit(vid, adapter->active_vlans)) 4466 continue; 4467 } 4468 4469 /* remove PF from the pool */ 4470 word = i * 2 + VMDQ_P(0) / 32; 4471 bits = ~BIT(VMDQ_P(0) % 32); 4472 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4473 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4474 } 4475 4476 /* extract values from active_vlans and write back to VFTA */ 4477 for (i = VFTA_BLOCK_SIZE; i--;) { 4478 vid = (vfta_offset + i) * 32; 4479 word = vid / BITS_PER_LONG; 4480 bits = vid % BITS_PER_LONG; 4481 4482 vfta[i] |= adapter->active_vlans[word] >> bits; 4483 4484 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4485 } 4486 } 4487 4488 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4489 { 4490 struct ixgbe_hw *hw = &adapter->hw; 4491 u32 vlnctrl, i; 4492 4493 /* Set VLAN filtering to enabled */ 4494 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4495 vlnctrl |= IXGBE_VLNCTRL_VFE; 4496 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4497 4498 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4499 hw->mac.type == ixgbe_mac_82598EB) 4500 return; 4501 4502 /* We are not in VLAN promisc, nothing to do */ 4503 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4504 return; 4505 4506 /* Set flag so we don't redo unnecessary work */ 4507 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4508 4509 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4510 ixgbe_scrub_vfta(adapter, i); 4511 } 4512 4513 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4514 { 4515 u16 vid = 1; 4516 4517 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4518 4519 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4520 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4521 } 4522 4523 /** 4524 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4525 * @netdev: network interface device structure 4526 * 4527 * Writes multicast address list to the MTA hash table. 4528 * Returns: -ENOMEM on failure 4529 * 0 on no addresses written 4530 * X on writing X addresses to MTA 4531 **/ 4532 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4533 { 4534 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4535 struct ixgbe_hw *hw = &adapter->hw; 4536 4537 if (!netif_running(netdev)) 4538 return 0; 4539 4540 if (hw->mac.ops.update_mc_addr_list) 4541 hw->mac.ops.update_mc_addr_list(hw, netdev); 4542 else 4543 return -ENOMEM; 4544 4545 #ifdef CONFIG_PCI_IOV 4546 ixgbe_restore_vf_multicasts(adapter); 4547 #endif 4548 4549 return netdev_mc_count(netdev); 4550 } 4551 4552 #ifdef CONFIG_PCI_IOV 4553 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4554 { 4555 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4556 struct ixgbe_hw *hw = &adapter->hw; 4557 int i; 4558 4559 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4560 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4561 4562 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4563 hw->mac.ops.set_rar(hw, i, 4564 mac_table->addr, 4565 mac_table->pool, 4566 IXGBE_RAH_AV); 4567 else 4568 hw->mac.ops.clear_rar(hw, i); 4569 } 4570 } 4571 4572 #endif 4573 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4574 { 4575 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4576 struct ixgbe_hw *hw = &adapter->hw; 4577 int i; 4578 4579 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4580 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4581 continue; 4582 4583 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4584 4585 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4586 hw->mac.ops.set_rar(hw, i, 4587 mac_table->addr, 4588 mac_table->pool, 4589 IXGBE_RAH_AV); 4590 else 4591 hw->mac.ops.clear_rar(hw, i); 4592 } 4593 } 4594 4595 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4596 { 4597 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4598 struct ixgbe_hw *hw = &adapter->hw; 4599 int i; 4600 4601 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4602 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4603 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4604 } 4605 4606 ixgbe_sync_mac_table(adapter); 4607 } 4608 4609 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4610 { 4611 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4612 struct ixgbe_hw *hw = &adapter->hw; 4613 int i, count = 0; 4614 4615 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4616 /* do not count default RAR as available */ 4617 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4618 continue; 4619 4620 /* only count unused and addresses that belong to us */ 4621 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4622 if (mac_table->pool != pool) 4623 continue; 4624 } 4625 4626 count++; 4627 } 4628 4629 return count; 4630 } 4631 4632 /* this function destroys the first RAR entry */ 4633 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4634 { 4635 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4636 struct ixgbe_hw *hw = &adapter->hw; 4637 4638 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4639 mac_table->pool = VMDQ_P(0); 4640 4641 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4642 4643 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4644 IXGBE_RAH_AV); 4645 } 4646 4647 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4648 const u8 *addr, u16 pool) 4649 { 4650 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4651 struct ixgbe_hw *hw = &adapter->hw; 4652 int i; 4653 4654 if (is_zero_ether_addr(addr)) 4655 return -EINVAL; 4656 4657 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4658 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4659 continue; 4660 4661 ether_addr_copy(mac_table->addr, addr); 4662 mac_table->pool = pool; 4663 4664 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4665 IXGBE_MAC_STATE_IN_USE; 4666 4667 ixgbe_sync_mac_table(adapter); 4668 4669 return i; 4670 } 4671 4672 return -ENOMEM; 4673 } 4674 4675 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4676 const u8 *addr, u16 pool) 4677 { 4678 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4679 struct ixgbe_hw *hw = &adapter->hw; 4680 int i; 4681 4682 if (is_zero_ether_addr(addr)) 4683 return -EINVAL; 4684 4685 /* search table for addr, if found clear IN_USE flag and sync */ 4686 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4687 /* we can only delete an entry if it is in use */ 4688 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4689 continue; 4690 /* we only care about entries that belong to the given pool */ 4691 if (mac_table->pool != pool) 4692 continue; 4693 /* we only care about a specific MAC address */ 4694 if (!ether_addr_equal(addr, mac_table->addr)) 4695 continue; 4696 4697 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4698 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4699 4700 ixgbe_sync_mac_table(adapter); 4701 4702 return 0; 4703 } 4704 4705 return -ENOMEM; 4706 } 4707 /** 4708 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4709 * @netdev: network interface device structure 4710 * 4711 * Writes unicast address list to the RAR table. 4712 * Returns: -ENOMEM on failure/insufficient address space 4713 * 0 on no addresses written 4714 * X on writing X addresses to the RAR table 4715 **/ 4716 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4717 { 4718 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4719 int count = 0; 4720 4721 /* return ENOMEM indicating insufficient memory for addresses */ 4722 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) 4723 return -ENOMEM; 4724 4725 if (!netdev_uc_empty(netdev)) { 4726 struct netdev_hw_addr *ha; 4727 netdev_for_each_uc_addr(ha, netdev) { 4728 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4729 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4730 count++; 4731 } 4732 } 4733 return count; 4734 } 4735 4736 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4737 { 4738 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4739 int ret; 4740 4741 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4742 4743 return min_t(int, ret, 0); 4744 } 4745 4746 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4747 { 4748 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4749 4750 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4751 4752 return 0; 4753 } 4754 4755 /** 4756 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4757 * @netdev: network interface device structure 4758 * 4759 * The set_rx_method entry point is called whenever the unicast/multicast 4760 * address list or the network interface flags are updated. This routine is 4761 * responsible for configuring the hardware for proper unicast, multicast and 4762 * promiscuous mode. 4763 **/ 4764 void ixgbe_set_rx_mode(struct net_device *netdev) 4765 { 4766 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4767 struct ixgbe_hw *hw = &adapter->hw; 4768 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4769 netdev_features_t features = netdev->features; 4770 int count; 4771 4772 /* Check for Promiscuous and All Multicast modes */ 4773 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4774 4775 /* set all bits that we expect to always be set */ 4776 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4777 fctrl |= IXGBE_FCTRL_BAM; 4778 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4779 fctrl |= IXGBE_FCTRL_PMCF; 4780 4781 /* clear the bits we are changing the status of */ 4782 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4783 if (netdev->flags & IFF_PROMISC) { 4784 hw->addr_ctrl.user_set_promisc = true; 4785 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4786 vmolr |= IXGBE_VMOLR_MPE; 4787 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4788 } else { 4789 if (netdev->flags & IFF_ALLMULTI) { 4790 fctrl |= IXGBE_FCTRL_MPE; 4791 vmolr |= IXGBE_VMOLR_MPE; 4792 } 4793 hw->addr_ctrl.user_set_promisc = false; 4794 } 4795 4796 /* 4797 * Write addresses to available RAR registers, if there is not 4798 * sufficient space to store all the addresses then enable 4799 * unicast promiscuous mode 4800 */ 4801 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4802 fctrl |= IXGBE_FCTRL_UPE; 4803 vmolr |= IXGBE_VMOLR_ROPE; 4804 } 4805 4806 /* Write addresses to the MTA, if the attempt fails 4807 * then we should just turn on promiscuous mode so 4808 * that we can at least receive multicast traffic 4809 */ 4810 count = ixgbe_write_mc_addr_list(netdev); 4811 if (count < 0) { 4812 fctrl |= IXGBE_FCTRL_MPE; 4813 vmolr |= IXGBE_VMOLR_MPE; 4814 } else if (count) { 4815 vmolr |= IXGBE_VMOLR_ROMPE; 4816 } 4817 4818 if (hw->mac.type != ixgbe_mac_82598EB) { 4819 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4820 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4821 IXGBE_VMOLR_ROPE); 4822 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4823 } 4824 4825 /* This is useful for sniffing bad packets. */ 4826 if (features & NETIF_F_RXALL) { 4827 /* UPE and MPE will be handled by normal PROMISC logic 4828 * in e1000e_set_rx_mode */ 4829 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4830 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4831 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4832 4833 fctrl &= ~(IXGBE_FCTRL_DPF); 4834 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4835 } 4836 4837 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4838 4839 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4840 ixgbe_vlan_strip_enable(adapter); 4841 else 4842 ixgbe_vlan_strip_disable(adapter); 4843 4844 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4845 ixgbe_vlan_promisc_disable(adapter); 4846 else 4847 ixgbe_vlan_promisc_enable(adapter); 4848 } 4849 4850 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4851 { 4852 int q_idx; 4853 4854 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4855 napi_enable(&adapter->q_vector[q_idx]->napi); 4856 } 4857 4858 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4859 { 4860 int q_idx; 4861 4862 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4863 napi_disable(&adapter->q_vector[q_idx]->napi); 4864 } 4865 4866 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 4867 { 4868 struct ixgbe_hw *hw = &adapter->hw; 4869 u32 vxlanctrl; 4870 4871 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 4872 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 4873 return; 4874 4875 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask; 4876 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 4877 4878 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 4879 adapter->vxlan_port = 0; 4880 4881 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 4882 adapter->geneve_port = 0; 4883 } 4884 4885 #ifdef CONFIG_IXGBE_DCB 4886 /** 4887 * ixgbe_configure_dcb - Configure DCB hardware 4888 * @adapter: ixgbe adapter struct 4889 * 4890 * This is called by the driver on open to configure the DCB hardware. 4891 * This is also called by the gennetlink interface when reconfiguring 4892 * the DCB state. 4893 */ 4894 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4895 { 4896 struct ixgbe_hw *hw = &adapter->hw; 4897 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4898 4899 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4900 if (hw->mac.type == ixgbe_mac_82598EB) 4901 netif_set_gso_max_size(adapter->netdev, 65536); 4902 return; 4903 } 4904 4905 if (hw->mac.type == ixgbe_mac_82598EB) 4906 netif_set_gso_max_size(adapter->netdev, 32768); 4907 4908 #ifdef IXGBE_FCOE 4909 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4910 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4911 #endif 4912 4913 /* reconfigure the hardware */ 4914 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4915 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4916 DCB_TX_CONFIG); 4917 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4918 DCB_RX_CONFIG); 4919 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4920 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4921 ixgbe_dcb_hw_ets(&adapter->hw, 4922 adapter->ixgbe_ieee_ets, 4923 max_frame); 4924 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4925 adapter->ixgbe_ieee_pfc->pfc_en, 4926 adapter->ixgbe_ieee_ets->prio_tc); 4927 } 4928 4929 /* Enable RSS Hash per TC */ 4930 if (hw->mac.type != ixgbe_mac_82598EB) { 4931 u32 msb = 0; 4932 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4933 4934 while (rss_i) { 4935 msb++; 4936 rss_i >>= 1; 4937 } 4938 4939 /* write msb to all 8 TCs in one write */ 4940 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4941 } 4942 } 4943 #endif 4944 4945 /* Additional bittime to account for IXGBE framing */ 4946 #define IXGBE_ETH_FRAMING 20 4947 4948 /** 4949 * ixgbe_hpbthresh - calculate high water mark for flow control 4950 * 4951 * @adapter: board private structure to calculate for 4952 * @pb: packet buffer to calculate 4953 */ 4954 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4955 { 4956 struct ixgbe_hw *hw = &adapter->hw; 4957 struct net_device *dev = adapter->netdev; 4958 int link, tc, kb, marker; 4959 u32 dv_id, rx_pba; 4960 4961 /* Calculate max LAN frame size */ 4962 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4963 4964 #ifdef IXGBE_FCOE 4965 /* FCoE traffic class uses FCOE jumbo frames */ 4966 if ((dev->features & NETIF_F_FCOE_MTU) && 4967 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4968 (pb == ixgbe_fcoe_get_tc(adapter))) 4969 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4970 #endif 4971 4972 /* Calculate delay value for device */ 4973 switch (hw->mac.type) { 4974 case ixgbe_mac_X540: 4975 case ixgbe_mac_X550: 4976 case ixgbe_mac_X550EM_x: 4977 case ixgbe_mac_x550em_a: 4978 dv_id = IXGBE_DV_X540(link, tc); 4979 break; 4980 default: 4981 dv_id = IXGBE_DV(link, tc); 4982 break; 4983 } 4984 4985 /* Loopback switch introduces additional latency */ 4986 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4987 dv_id += IXGBE_B2BT(tc); 4988 4989 /* Delay value is calculated in bit times convert to KB */ 4990 kb = IXGBE_BT2KB(dv_id); 4991 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4992 4993 marker = rx_pba - kb; 4994 4995 /* It is possible that the packet buffer is not large enough 4996 * to provide required headroom. In this case throw an error 4997 * to user and a do the best we can. 4998 */ 4999 if (marker < 0) { 5000 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5001 "headroom to support flow control." 5002 "Decrease MTU or number of traffic classes\n", pb); 5003 marker = tc + 1; 5004 } 5005 5006 return marker; 5007 } 5008 5009 /** 5010 * ixgbe_lpbthresh - calculate low water mark for for flow control 5011 * 5012 * @adapter: board private structure to calculate for 5013 * @pb: packet buffer to calculate 5014 */ 5015 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5016 { 5017 struct ixgbe_hw *hw = &adapter->hw; 5018 struct net_device *dev = adapter->netdev; 5019 int tc; 5020 u32 dv_id; 5021 5022 /* Calculate max LAN frame size */ 5023 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5024 5025 #ifdef IXGBE_FCOE 5026 /* FCoE traffic class uses FCOE jumbo frames */ 5027 if ((dev->features & NETIF_F_FCOE_MTU) && 5028 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5029 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5030 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5031 #endif 5032 5033 /* Calculate delay value for device */ 5034 switch (hw->mac.type) { 5035 case ixgbe_mac_X540: 5036 case ixgbe_mac_X550: 5037 case ixgbe_mac_X550EM_x: 5038 case ixgbe_mac_x550em_a: 5039 dv_id = IXGBE_LOW_DV_X540(tc); 5040 break; 5041 default: 5042 dv_id = IXGBE_LOW_DV(tc); 5043 break; 5044 } 5045 5046 /* Delay value is calculated in bit times convert to KB */ 5047 return IXGBE_BT2KB(dv_id); 5048 } 5049 5050 /* 5051 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5052 */ 5053 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5054 { 5055 struct ixgbe_hw *hw = &adapter->hw; 5056 int num_tc = netdev_get_num_tc(adapter->netdev); 5057 int i; 5058 5059 if (!num_tc) 5060 num_tc = 1; 5061 5062 for (i = 0; i < num_tc; i++) { 5063 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5064 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5065 5066 /* Low water marks must not be larger than high water marks */ 5067 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5068 hw->fc.low_water[i] = 0; 5069 } 5070 5071 for (; i < MAX_TRAFFIC_CLASS; i++) 5072 hw->fc.high_water[i] = 0; 5073 } 5074 5075 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5076 { 5077 struct ixgbe_hw *hw = &adapter->hw; 5078 int hdrm; 5079 u8 tc = netdev_get_num_tc(adapter->netdev); 5080 5081 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5082 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5083 hdrm = 32 << adapter->fdir_pballoc; 5084 else 5085 hdrm = 0; 5086 5087 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5088 ixgbe_pbthresh_setup(adapter); 5089 } 5090 5091 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5092 { 5093 struct ixgbe_hw *hw = &adapter->hw; 5094 struct hlist_node *node2; 5095 struct ixgbe_fdir_filter *filter; 5096 5097 spin_lock(&adapter->fdir_perfect_lock); 5098 5099 if (!hlist_empty(&adapter->fdir_filter_list)) 5100 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5101 5102 hlist_for_each_entry_safe(filter, node2, 5103 &adapter->fdir_filter_list, fdir_node) { 5104 ixgbe_fdir_write_perfect_filter_82599(hw, 5105 &filter->filter, 5106 filter->sw_idx, 5107 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5108 IXGBE_FDIR_DROP_QUEUE : 5109 adapter->rx_ring[filter->action]->reg_idx); 5110 } 5111 5112 spin_unlock(&adapter->fdir_perfect_lock); 5113 } 5114 5115 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 5116 struct ixgbe_adapter *adapter) 5117 { 5118 struct ixgbe_hw *hw = &adapter->hw; 5119 u32 vmolr; 5120 5121 /* No unicast promiscuous support for VMDQ devices. */ 5122 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 5123 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 5124 5125 /* clear the affected bit */ 5126 vmolr &= ~IXGBE_VMOLR_MPE; 5127 5128 if (dev->flags & IFF_ALLMULTI) { 5129 vmolr |= IXGBE_VMOLR_MPE; 5130 } else { 5131 vmolr |= IXGBE_VMOLR_ROMPE; 5132 hw->mac.ops.update_mc_addr_list(hw, dev); 5133 } 5134 ixgbe_write_uc_addr_list(adapter->netdev, pool); 5135 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 5136 } 5137 5138 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 5139 { 5140 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5141 int rss_i = adapter->num_rx_queues_per_pool; 5142 struct ixgbe_hw *hw = &adapter->hw; 5143 u16 pool = vadapter->pool; 5144 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 5145 IXGBE_PSRTYPE_UDPHDR | 5146 IXGBE_PSRTYPE_IPV4HDR | 5147 IXGBE_PSRTYPE_L2HDR | 5148 IXGBE_PSRTYPE_IPV6HDR; 5149 5150 if (hw->mac.type == ixgbe_mac_82598EB) 5151 return; 5152 5153 if (rss_i > 3) 5154 psrtype |= 2u << 29; 5155 else if (rss_i > 1) 5156 psrtype |= 1u << 29; 5157 5158 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 5159 } 5160 5161 /** 5162 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5163 * @rx_ring: ring to free buffers from 5164 **/ 5165 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5166 { 5167 u16 i = rx_ring->next_to_clean; 5168 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5169 5170 /* Free all the Rx ring sk_buffs */ 5171 while (i != rx_ring->next_to_alloc) { 5172 if (rx_buffer->skb) { 5173 struct sk_buff *skb = rx_buffer->skb; 5174 if (IXGBE_CB(skb)->page_released) 5175 dma_unmap_page_attrs(rx_ring->dev, 5176 IXGBE_CB(skb)->dma, 5177 ixgbe_rx_pg_size(rx_ring), 5178 DMA_FROM_DEVICE, 5179 IXGBE_RX_DMA_ATTR); 5180 dev_kfree_skb(skb); 5181 } 5182 5183 /* Invalidate cache lines that may have been written to by 5184 * device so that we avoid corrupting memory. 5185 */ 5186 dma_sync_single_range_for_cpu(rx_ring->dev, 5187 rx_buffer->dma, 5188 rx_buffer->page_offset, 5189 ixgbe_rx_bufsz(rx_ring), 5190 DMA_FROM_DEVICE); 5191 5192 /* free resources associated with mapping */ 5193 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5194 ixgbe_rx_pg_size(rx_ring), 5195 DMA_FROM_DEVICE, 5196 IXGBE_RX_DMA_ATTR); 5197 __page_frag_cache_drain(rx_buffer->page, 5198 rx_buffer->pagecnt_bias); 5199 5200 i++; 5201 rx_buffer++; 5202 if (i == rx_ring->count) { 5203 i = 0; 5204 rx_buffer = rx_ring->rx_buffer_info; 5205 } 5206 } 5207 5208 rx_ring->next_to_alloc = 0; 5209 rx_ring->next_to_clean = 0; 5210 rx_ring->next_to_use = 0; 5211 } 5212 5213 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 5214 struct ixgbe_ring *rx_ring) 5215 { 5216 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5217 int index = rx_ring->queue_index + vadapter->rx_base_queue; 5218 5219 /* shutdown specific queue receive and wait for dma to settle */ 5220 ixgbe_disable_rx_queue(adapter, rx_ring); 5221 usleep_range(10000, 20000); 5222 ixgbe_irq_disable_queues(adapter, BIT_ULL(index)); 5223 ixgbe_clean_rx_ring(rx_ring); 5224 rx_ring->l2_accel_priv = NULL; 5225 } 5226 5227 static int ixgbe_fwd_ring_down(struct net_device *vdev, 5228 struct ixgbe_fwd_adapter *accel) 5229 { 5230 struct ixgbe_adapter *adapter = accel->real_adapter; 5231 unsigned int rxbase = accel->rx_base_queue; 5232 unsigned int txbase = accel->tx_base_queue; 5233 int i; 5234 5235 netif_tx_stop_all_queues(vdev); 5236 5237 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5238 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5239 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 5240 } 5241 5242 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5243 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 5244 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 5245 } 5246 5247 5248 return 0; 5249 } 5250 5251 static int ixgbe_fwd_ring_up(struct net_device *vdev, 5252 struct ixgbe_fwd_adapter *accel) 5253 { 5254 struct ixgbe_adapter *adapter = accel->real_adapter; 5255 unsigned int rxbase, txbase, queues; 5256 int i, baseq, err = 0; 5257 5258 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 5259 return 0; 5260 5261 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5262 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 5263 accel->pool, adapter->num_rx_pools, 5264 baseq, baseq + adapter->num_rx_queues_per_pool, 5265 adapter->fwd_bitmask); 5266 5267 accel->netdev = vdev; 5268 accel->rx_base_queue = rxbase = baseq; 5269 accel->tx_base_queue = txbase = baseq; 5270 5271 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5272 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5273 5274 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5275 adapter->rx_ring[rxbase + i]->netdev = vdev; 5276 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 5277 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 5278 } 5279 5280 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5281 adapter->tx_ring[txbase + i]->netdev = vdev; 5282 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 5283 } 5284 5285 queues = min_t(unsigned int, 5286 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 5287 err = netif_set_real_num_tx_queues(vdev, queues); 5288 if (err) 5289 goto fwd_queue_err; 5290 5291 err = netif_set_real_num_rx_queues(vdev, queues); 5292 if (err) 5293 goto fwd_queue_err; 5294 5295 if (is_valid_ether_addr(vdev->dev_addr)) 5296 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 5297 5298 ixgbe_fwd_psrtype(accel); 5299 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 5300 return err; 5301 fwd_queue_err: 5302 ixgbe_fwd_ring_down(vdev, accel); 5303 return err; 5304 } 5305 5306 static int ixgbe_upper_dev_walk(struct net_device *upper, void *data) 5307 { 5308 if (netif_is_macvlan(upper)) { 5309 struct macvlan_dev *dfwd = netdev_priv(upper); 5310 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 5311 5312 if (dfwd->fwd_priv) 5313 ixgbe_fwd_ring_up(upper, vadapter); 5314 } 5315 5316 return 0; 5317 } 5318 5319 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5320 { 5321 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5322 ixgbe_upper_dev_walk, NULL); 5323 } 5324 5325 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5326 { 5327 struct ixgbe_hw *hw = &adapter->hw; 5328 5329 ixgbe_configure_pb(adapter); 5330 #ifdef CONFIG_IXGBE_DCB 5331 ixgbe_configure_dcb(adapter); 5332 #endif 5333 /* 5334 * We must restore virtualization before VLANs or else 5335 * the VLVF registers will not be populated 5336 */ 5337 ixgbe_configure_virtualization(adapter); 5338 5339 ixgbe_set_rx_mode(adapter->netdev); 5340 ixgbe_restore_vlan(adapter); 5341 5342 switch (hw->mac.type) { 5343 case ixgbe_mac_82599EB: 5344 case ixgbe_mac_X540: 5345 hw->mac.ops.disable_rx_buff(hw); 5346 break; 5347 default: 5348 break; 5349 } 5350 5351 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5352 ixgbe_init_fdir_signature_82599(&adapter->hw, 5353 adapter->fdir_pballoc); 5354 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5355 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5356 adapter->fdir_pballoc); 5357 ixgbe_fdir_filter_restore(adapter); 5358 } 5359 5360 switch (hw->mac.type) { 5361 case ixgbe_mac_82599EB: 5362 case ixgbe_mac_X540: 5363 hw->mac.ops.enable_rx_buff(hw); 5364 break; 5365 default: 5366 break; 5367 } 5368 5369 #ifdef CONFIG_IXGBE_DCA 5370 /* configure DCA */ 5371 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5372 ixgbe_setup_dca(adapter); 5373 #endif /* CONFIG_IXGBE_DCA */ 5374 5375 #ifdef IXGBE_FCOE 5376 /* configure FCoE L2 filters, redirection table, and Rx control */ 5377 ixgbe_configure_fcoe(adapter); 5378 5379 #endif /* IXGBE_FCOE */ 5380 ixgbe_configure_tx(adapter); 5381 ixgbe_configure_rx(adapter); 5382 ixgbe_configure_dfwd(adapter); 5383 } 5384 5385 /** 5386 * ixgbe_sfp_link_config - set up SFP+ link 5387 * @adapter: pointer to private adapter struct 5388 **/ 5389 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5390 { 5391 /* 5392 * We are assuming the worst case scenario here, and that 5393 * is that an SFP was inserted/removed after the reset 5394 * but before SFP detection was enabled. As such the best 5395 * solution is to just start searching as soon as we start 5396 */ 5397 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5398 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5399 5400 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5401 adapter->sfp_poll_time = 0; 5402 } 5403 5404 /** 5405 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5406 * @hw: pointer to private hardware struct 5407 * 5408 * Returns 0 on success, negative on failure 5409 **/ 5410 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5411 { 5412 u32 speed; 5413 bool autoneg, link_up = false; 5414 int ret = IXGBE_ERR_LINK_SETUP; 5415 5416 if (hw->mac.ops.check_link) 5417 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5418 5419 if (ret) 5420 return ret; 5421 5422 speed = hw->phy.autoneg_advertised; 5423 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5424 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5425 &autoneg); 5426 if (ret) 5427 return ret; 5428 5429 if (hw->mac.ops.setup_link) 5430 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5431 5432 return ret; 5433 } 5434 5435 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5436 { 5437 struct ixgbe_hw *hw = &adapter->hw; 5438 u32 gpie = 0; 5439 5440 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5441 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5442 IXGBE_GPIE_OCD; 5443 gpie |= IXGBE_GPIE_EIAME; 5444 /* 5445 * use EIAM to auto-mask when MSI-X interrupt is asserted 5446 * this saves a register write for every interrupt 5447 */ 5448 switch (hw->mac.type) { 5449 case ixgbe_mac_82598EB: 5450 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5451 break; 5452 case ixgbe_mac_82599EB: 5453 case ixgbe_mac_X540: 5454 case ixgbe_mac_X550: 5455 case ixgbe_mac_X550EM_x: 5456 case ixgbe_mac_x550em_a: 5457 default: 5458 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5459 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5460 break; 5461 } 5462 } else { 5463 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5464 * specifically only auto mask tx and rx interrupts */ 5465 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5466 } 5467 5468 /* XXX: to interrupt immediately for EICS writes, enable this */ 5469 /* gpie |= IXGBE_GPIE_EIMEN; */ 5470 5471 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5472 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5473 5474 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5475 case IXGBE_82599_VMDQ_8Q_MASK: 5476 gpie |= IXGBE_GPIE_VTMODE_16; 5477 break; 5478 case IXGBE_82599_VMDQ_4Q_MASK: 5479 gpie |= IXGBE_GPIE_VTMODE_32; 5480 break; 5481 default: 5482 gpie |= IXGBE_GPIE_VTMODE_64; 5483 break; 5484 } 5485 } 5486 5487 /* Enable Thermal over heat sensor interrupt */ 5488 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5489 switch (adapter->hw.mac.type) { 5490 case ixgbe_mac_82599EB: 5491 gpie |= IXGBE_SDP0_GPIEN_8259X; 5492 break; 5493 default: 5494 break; 5495 } 5496 } 5497 5498 /* Enable fan failure interrupt */ 5499 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5500 gpie |= IXGBE_SDP1_GPIEN(hw); 5501 5502 switch (hw->mac.type) { 5503 case ixgbe_mac_82599EB: 5504 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5505 break; 5506 case ixgbe_mac_X550EM_x: 5507 case ixgbe_mac_x550em_a: 5508 gpie |= IXGBE_SDP0_GPIEN_X540; 5509 break; 5510 default: 5511 break; 5512 } 5513 5514 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5515 } 5516 5517 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5518 { 5519 struct ixgbe_hw *hw = &adapter->hw; 5520 int err; 5521 u32 ctrl_ext; 5522 5523 ixgbe_get_hw_control(adapter); 5524 ixgbe_setup_gpie(adapter); 5525 5526 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5527 ixgbe_configure_msix(adapter); 5528 else 5529 ixgbe_configure_msi_and_legacy(adapter); 5530 5531 /* enable the optics for 82599 SFP+ fiber */ 5532 if (hw->mac.ops.enable_tx_laser) 5533 hw->mac.ops.enable_tx_laser(hw); 5534 5535 if (hw->phy.ops.set_phy_power) 5536 hw->phy.ops.set_phy_power(hw, true); 5537 5538 smp_mb__before_atomic(); 5539 clear_bit(__IXGBE_DOWN, &adapter->state); 5540 ixgbe_napi_enable_all(adapter); 5541 5542 if (ixgbe_is_sfp(hw)) { 5543 ixgbe_sfp_link_config(adapter); 5544 } else { 5545 err = ixgbe_non_sfp_link_config(hw); 5546 if (err) 5547 e_err(probe, "link_config FAILED %d\n", err); 5548 } 5549 5550 /* clear any pending interrupts, may auto mask */ 5551 IXGBE_READ_REG(hw, IXGBE_EICR); 5552 ixgbe_irq_enable(adapter, true, true); 5553 5554 /* 5555 * If this adapter has a fan, check to see if we had a failure 5556 * before we enabled the interrupt. 5557 */ 5558 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5559 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5560 if (esdp & IXGBE_ESDP_SDP1) 5561 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5562 } 5563 5564 /* bring the link up in the watchdog, this could race with our first 5565 * link up interrupt but shouldn't be a problem */ 5566 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5567 adapter->link_check_timeout = jiffies; 5568 mod_timer(&adapter->service_timer, jiffies); 5569 5570 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5571 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5572 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5573 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5574 } 5575 5576 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5577 { 5578 WARN_ON(in_interrupt()); 5579 /* put off any impending NetWatchDogTimeout */ 5580 netif_trans_update(adapter->netdev); 5581 5582 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5583 usleep_range(1000, 2000); 5584 if (adapter->hw.phy.type == ixgbe_phy_fw) 5585 ixgbe_watchdog_link_is_down(adapter); 5586 ixgbe_down(adapter); 5587 /* 5588 * If SR-IOV enabled then wait a bit before bringing the adapter 5589 * back up to give the VFs time to respond to the reset. The 5590 * two second wait is based upon the watchdog timer cycle in 5591 * the VF driver. 5592 */ 5593 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5594 msleep(2000); 5595 ixgbe_up(adapter); 5596 clear_bit(__IXGBE_RESETTING, &adapter->state); 5597 } 5598 5599 void ixgbe_up(struct ixgbe_adapter *adapter) 5600 { 5601 /* hardware has been reset, we need to reload some things */ 5602 ixgbe_configure(adapter); 5603 5604 ixgbe_up_complete(adapter); 5605 } 5606 5607 void ixgbe_reset(struct ixgbe_adapter *adapter) 5608 { 5609 struct ixgbe_hw *hw = &adapter->hw; 5610 struct net_device *netdev = adapter->netdev; 5611 int err; 5612 5613 if (ixgbe_removed(hw->hw_addr)) 5614 return; 5615 /* lock SFP init bit to prevent race conditions with the watchdog */ 5616 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5617 usleep_range(1000, 2000); 5618 5619 /* clear all SFP and link config related flags while holding SFP_INIT */ 5620 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5621 IXGBE_FLAG2_SFP_NEEDS_RESET); 5622 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5623 5624 err = hw->mac.ops.init_hw(hw); 5625 switch (err) { 5626 case 0: 5627 case IXGBE_ERR_SFP_NOT_PRESENT: 5628 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5629 break; 5630 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5631 e_dev_err("master disable timed out\n"); 5632 break; 5633 case IXGBE_ERR_EEPROM_VERSION: 5634 /* We are running on a pre-production device, log a warning */ 5635 e_dev_warn("This device is a pre-production adapter/LOM. " 5636 "Please be aware there may be issues associated with " 5637 "your hardware. If you are experiencing problems " 5638 "please contact your Intel or hardware " 5639 "representative who provided you with this " 5640 "hardware.\n"); 5641 break; 5642 default: 5643 e_dev_err("Hardware Error: %d\n", err); 5644 } 5645 5646 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5647 5648 /* flush entries out of MAC table */ 5649 ixgbe_flush_sw_mac_table(adapter); 5650 __dev_uc_unsync(netdev, NULL); 5651 5652 /* do not flush user set addresses */ 5653 ixgbe_mac_set_default_filter(adapter); 5654 5655 /* update SAN MAC vmdq pool selection */ 5656 if (hw->mac.san_mac_rar_index) 5657 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5658 5659 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5660 ixgbe_ptp_reset(adapter); 5661 5662 if (hw->phy.ops.set_phy_power) { 5663 if (!netif_running(adapter->netdev) && !adapter->wol) 5664 hw->phy.ops.set_phy_power(hw, false); 5665 else 5666 hw->phy.ops.set_phy_power(hw, true); 5667 } 5668 } 5669 5670 /** 5671 * ixgbe_clean_tx_ring - Free Tx Buffers 5672 * @tx_ring: ring to be cleaned 5673 **/ 5674 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5675 { 5676 u16 i = tx_ring->next_to_clean; 5677 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5678 5679 while (i != tx_ring->next_to_use) { 5680 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5681 5682 /* Free all the Tx ring sk_buffs */ 5683 if (ring_is_xdp(tx_ring)) 5684 page_frag_free(tx_buffer->data); 5685 else 5686 dev_kfree_skb_any(tx_buffer->skb); 5687 5688 /* unmap skb header data */ 5689 dma_unmap_single(tx_ring->dev, 5690 dma_unmap_addr(tx_buffer, dma), 5691 dma_unmap_len(tx_buffer, len), 5692 DMA_TO_DEVICE); 5693 5694 /* check for eop_desc to determine the end of the packet */ 5695 eop_desc = tx_buffer->next_to_watch; 5696 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5697 5698 /* unmap remaining buffers */ 5699 while (tx_desc != eop_desc) { 5700 tx_buffer++; 5701 tx_desc++; 5702 i++; 5703 if (unlikely(i == tx_ring->count)) { 5704 i = 0; 5705 tx_buffer = tx_ring->tx_buffer_info; 5706 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5707 } 5708 5709 /* unmap any remaining paged data */ 5710 if (dma_unmap_len(tx_buffer, len)) 5711 dma_unmap_page(tx_ring->dev, 5712 dma_unmap_addr(tx_buffer, dma), 5713 dma_unmap_len(tx_buffer, len), 5714 DMA_TO_DEVICE); 5715 } 5716 5717 /* move us one more past the eop_desc for start of next pkt */ 5718 tx_buffer++; 5719 i++; 5720 if (unlikely(i == tx_ring->count)) { 5721 i = 0; 5722 tx_buffer = tx_ring->tx_buffer_info; 5723 } 5724 } 5725 5726 /* reset BQL for queue */ 5727 if (!ring_is_xdp(tx_ring)) 5728 netdev_tx_reset_queue(txring_txq(tx_ring)); 5729 5730 /* reset next_to_use and next_to_clean */ 5731 tx_ring->next_to_use = 0; 5732 tx_ring->next_to_clean = 0; 5733 } 5734 5735 /** 5736 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5737 * @adapter: board private structure 5738 **/ 5739 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5740 { 5741 int i; 5742 5743 for (i = 0; i < adapter->num_rx_queues; i++) 5744 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5745 } 5746 5747 /** 5748 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5749 * @adapter: board private structure 5750 **/ 5751 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5752 { 5753 int i; 5754 5755 for (i = 0; i < adapter->num_tx_queues; i++) 5756 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5757 for (i = 0; i < adapter->num_xdp_queues; i++) 5758 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5759 } 5760 5761 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5762 { 5763 struct hlist_node *node2; 5764 struct ixgbe_fdir_filter *filter; 5765 5766 spin_lock(&adapter->fdir_perfect_lock); 5767 5768 hlist_for_each_entry_safe(filter, node2, 5769 &adapter->fdir_filter_list, fdir_node) { 5770 hlist_del(&filter->fdir_node); 5771 kfree(filter); 5772 } 5773 adapter->fdir_filter_count = 0; 5774 5775 spin_unlock(&adapter->fdir_perfect_lock); 5776 } 5777 5778 static int ixgbe_disable_macvlan(struct net_device *upper, void *data) 5779 { 5780 if (netif_is_macvlan(upper)) { 5781 struct macvlan_dev *vlan = netdev_priv(upper); 5782 5783 if (vlan->fwd_priv) { 5784 netif_tx_stop_all_queues(upper); 5785 netif_carrier_off(upper); 5786 netif_tx_disable(upper); 5787 } 5788 } 5789 5790 return 0; 5791 } 5792 5793 void ixgbe_down(struct ixgbe_adapter *adapter) 5794 { 5795 struct net_device *netdev = adapter->netdev; 5796 struct ixgbe_hw *hw = &adapter->hw; 5797 int i; 5798 5799 /* signal that we are down to the interrupt handler */ 5800 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5801 return; /* do nothing if already down */ 5802 5803 /* disable receives */ 5804 hw->mac.ops.disable_rx(hw); 5805 5806 /* disable all enabled rx queues */ 5807 for (i = 0; i < adapter->num_rx_queues; i++) 5808 /* this call also flushes the previous write */ 5809 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5810 5811 usleep_range(10000, 20000); 5812 5813 netif_tx_stop_all_queues(netdev); 5814 5815 /* call carrier off first to avoid false dev_watchdog timeouts */ 5816 netif_carrier_off(netdev); 5817 netif_tx_disable(netdev); 5818 5819 /* disable any upper devices */ 5820 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5821 ixgbe_disable_macvlan, NULL); 5822 5823 ixgbe_irq_disable(adapter); 5824 5825 ixgbe_napi_disable_all(adapter); 5826 5827 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5828 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5829 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5830 5831 del_timer_sync(&adapter->service_timer); 5832 5833 if (adapter->num_vfs) { 5834 /* Clear EITR Select mapping */ 5835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5836 5837 /* Mark all the VFs as inactive */ 5838 for (i = 0 ; i < adapter->num_vfs; i++) 5839 adapter->vfinfo[i].clear_to_send = false; 5840 5841 /* ping all the active vfs to let them know we are going down */ 5842 ixgbe_ping_all_vfs(adapter); 5843 5844 /* Disable all VFTE/VFRE TX/RX */ 5845 ixgbe_disable_tx_rx(adapter); 5846 } 5847 5848 /* disable transmits in the hardware now that interrupts are off */ 5849 for (i = 0; i < adapter->num_tx_queues; i++) { 5850 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5851 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5852 } 5853 for (i = 0; i < adapter->num_xdp_queues; i++) { 5854 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5855 5856 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5857 } 5858 5859 /* Disable the Tx DMA engine on 82599 and later MAC */ 5860 switch (hw->mac.type) { 5861 case ixgbe_mac_82599EB: 5862 case ixgbe_mac_X540: 5863 case ixgbe_mac_X550: 5864 case ixgbe_mac_X550EM_x: 5865 case ixgbe_mac_x550em_a: 5866 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5867 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5868 ~IXGBE_DMATXCTL_TE)); 5869 break; 5870 default: 5871 break; 5872 } 5873 5874 if (!pci_channel_offline(adapter->pdev)) 5875 ixgbe_reset(adapter); 5876 5877 /* power down the optics for 82599 SFP+ fiber */ 5878 if (hw->mac.ops.disable_tx_laser) 5879 hw->mac.ops.disable_tx_laser(hw); 5880 5881 ixgbe_clean_all_tx_rings(adapter); 5882 ixgbe_clean_all_rx_rings(adapter); 5883 } 5884 5885 /** 5886 * ixgbe_eee_capable - helper function to determine EEE support on X550 5887 * @adapter: board private structure 5888 */ 5889 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5890 { 5891 struct ixgbe_hw *hw = &adapter->hw; 5892 5893 switch (hw->device_id) { 5894 case IXGBE_DEV_ID_X550EM_A_1G_T: 5895 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 5896 if (!hw->phy.eee_speeds_supported) 5897 break; 5898 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 5899 if (!hw->phy.eee_speeds_advertised) 5900 break; 5901 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 5902 break; 5903 default: 5904 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 5905 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 5906 break; 5907 } 5908 } 5909 5910 /** 5911 * ixgbe_tx_timeout - Respond to a Tx Hang 5912 * @netdev: network interface device structure 5913 **/ 5914 static void ixgbe_tx_timeout(struct net_device *netdev) 5915 { 5916 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5917 5918 /* Do the reset outside of interrupt context */ 5919 ixgbe_tx_timeout_reset(adapter); 5920 } 5921 5922 #ifdef CONFIG_IXGBE_DCB 5923 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 5924 { 5925 struct ixgbe_hw *hw = &adapter->hw; 5926 struct tc_configuration *tc; 5927 int j; 5928 5929 switch (hw->mac.type) { 5930 case ixgbe_mac_82598EB: 5931 case ixgbe_mac_82599EB: 5932 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5933 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5934 break; 5935 case ixgbe_mac_X540: 5936 case ixgbe_mac_X550: 5937 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5938 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5939 break; 5940 case ixgbe_mac_X550EM_x: 5941 case ixgbe_mac_x550em_a: 5942 default: 5943 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 5944 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 5945 break; 5946 } 5947 5948 /* Configure DCB traffic classes */ 5949 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5950 tc = &adapter->dcb_cfg.tc_config[j]; 5951 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5952 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5953 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5954 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5955 tc->dcb_pfc = pfc_disabled; 5956 } 5957 5958 /* Initialize default user to priority mapping, UPx->TC0 */ 5959 tc = &adapter->dcb_cfg.tc_config[0]; 5960 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5961 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5962 5963 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5964 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5965 adapter->dcb_cfg.pfc_mode_enable = false; 5966 adapter->dcb_set_bitmap = 0x00; 5967 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 5968 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5969 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5970 sizeof(adapter->temp_dcb_cfg)); 5971 } 5972 #endif 5973 5974 /** 5975 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5976 * @adapter: board private structure to initialize 5977 * 5978 * ixgbe_sw_init initializes the Adapter private data structure. 5979 * Fields are initialized based on PCI device information and 5980 * OS network device settings (MTU size). 5981 **/ 5982 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 5983 const struct ixgbe_info *ii) 5984 { 5985 struct ixgbe_hw *hw = &adapter->hw; 5986 struct pci_dev *pdev = adapter->pdev; 5987 unsigned int rss, fdir; 5988 u32 fwsm; 5989 int i; 5990 5991 /* PCI config space info */ 5992 5993 hw->vendor_id = pdev->vendor; 5994 hw->device_id = pdev->device; 5995 hw->revision_id = pdev->revision; 5996 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5997 hw->subsystem_device_id = pdev->subsystem_device; 5998 5999 /* get_invariants needs the device IDs */ 6000 ii->get_invariants(hw); 6001 6002 /* Set common capability flags and settings */ 6003 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6004 adapter->ring_feature[RING_F_RSS].limit = rss; 6005 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6006 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6007 adapter->atr_sample_rate = 20; 6008 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6009 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6010 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6011 #ifdef CONFIG_IXGBE_DCA 6012 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6013 #endif 6014 #ifdef CONFIG_IXGBE_DCB 6015 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6016 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6017 #endif 6018 #ifdef IXGBE_FCOE 6019 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6020 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6021 #ifdef CONFIG_IXGBE_DCB 6022 /* Default traffic class to use for FCoE */ 6023 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6024 #endif /* CONFIG_IXGBE_DCB */ 6025 #endif /* IXGBE_FCOE */ 6026 6027 /* initialize static ixgbe jump table entries */ 6028 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6029 GFP_KERNEL); 6030 if (!adapter->jump_tables[0]) 6031 return -ENOMEM; 6032 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6033 6034 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6035 adapter->jump_tables[i] = NULL; 6036 6037 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6038 hw->mac.num_rar_entries, 6039 GFP_ATOMIC); 6040 if (!adapter->mac_table) 6041 return -ENOMEM; 6042 6043 if (ixgbe_init_rss_key(adapter)) 6044 return -ENOMEM; 6045 6046 /* Set MAC specific capability flags and exceptions */ 6047 switch (hw->mac.type) { 6048 case ixgbe_mac_82598EB: 6049 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6050 6051 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6052 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6053 6054 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6055 adapter->ring_feature[RING_F_FDIR].limit = 0; 6056 adapter->atr_sample_rate = 0; 6057 adapter->fdir_pballoc = 0; 6058 #ifdef IXGBE_FCOE 6059 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6060 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6061 #ifdef CONFIG_IXGBE_DCB 6062 adapter->fcoe.up = 0; 6063 #endif /* IXGBE_DCB */ 6064 #endif /* IXGBE_FCOE */ 6065 break; 6066 case ixgbe_mac_82599EB: 6067 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6068 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6069 break; 6070 case ixgbe_mac_X540: 6071 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6072 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6073 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6074 break; 6075 case ixgbe_mac_x550em_a: 6076 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6077 switch (hw->device_id) { 6078 case IXGBE_DEV_ID_X550EM_A_1G_T: 6079 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6080 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6081 break; 6082 default: 6083 break; 6084 } 6085 /* fall through */ 6086 case ixgbe_mac_X550EM_x: 6087 #ifdef CONFIG_IXGBE_DCB 6088 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6089 #endif 6090 #ifdef IXGBE_FCOE 6091 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6092 #ifdef CONFIG_IXGBE_DCB 6093 adapter->fcoe.up = 0; 6094 #endif /* IXGBE_DCB */ 6095 #endif /* IXGBE_FCOE */ 6096 /* Fall Through */ 6097 case ixgbe_mac_X550: 6098 if (hw->mac.type == ixgbe_mac_X550) 6099 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6100 #ifdef CONFIG_IXGBE_DCA 6101 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6102 #endif 6103 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6104 break; 6105 default: 6106 break; 6107 } 6108 6109 #ifdef IXGBE_FCOE 6110 /* FCoE support exists, always init the FCoE lock */ 6111 spin_lock_init(&adapter->fcoe.lock); 6112 6113 #endif 6114 /* n-tuple support exists, always init our spinlock */ 6115 spin_lock_init(&adapter->fdir_perfect_lock); 6116 6117 #ifdef CONFIG_IXGBE_DCB 6118 ixgbe_init_dcb(adapter); 6119 #endif 6120 6121 /* default flow control settings */ 6122 hw->fc.requested_mode = ixgbe_fc_full; 6123 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6124 ixgbe_pbthresh_setup(adapter); 6125 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6126 hw->fc.send_xon = true; 6127 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6128 6129 #ifdef CONFIG_PCI_IOV 6130 if (max_vfs > 0) 6131 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6132 6133 /* assign number of SR-IOV VFs */ 6134 if (hw->mac.type != ixgbe_mac_82598EB) { 6135 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6136 max_vfs = 0; 6137 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6138 } 6139 } 6140 #endif /* CONFIG_PCI_IOV */ 6141 6142 /* enable itr by default in dynamic mode */ 6143 adapter->rx_itr_setting = 1; 6144 adapter->tx_itr_setting = 1; 6145 6146 /* set default ring sizes */ 6147 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6148 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6149 6150 /* set default work limits */ 6151 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6152 6153 /* initialize eeprom parameters */ 6154 if (ixgbe_init_eeprom_params_generic(hw)) { 6155 e_dev_err("EEPROM initialization failed\n"); 6156 return -EIO; 6157 } 6158 6159 /* PF holds first pool slot */ 6160 set_bit(0, &adapter->fwd_bitmask); 6161 set_bit(__IXGBE_DOWN, &adapter->state); 6162 6163 return 0; 6164 } 6165 6166 /** 6167 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6168 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6169 * 6170 * Return 0 on success, negative on failure 6171 **/ 6172 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6173 { 6174 struct device *dev = tx_ring->dev; 6175 int orig_node = dev_to_node(dev); 6176 int ring_node = -1; 6177 int size; 6178 6179 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6180 6181 if (tx_ring->q_vector) 6182 ring_node = tx_ring->q_vector->numa_node; 6183 6184 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6185 if (!tx_ring->tx_buffer_info) 6186 tx_ring->tx_buffer_info = vmalloc(size); 6187 if (!tx_ring->tx_buffer_info) 6188 goto err; 6189 6190 /* round up to nearest 4K */ 6191 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6192 tx_ring->size = ALIGN(tx_ring->size, 4096); 6193 6194 set_dev_node(dev, ring_node); 6195 tx_ring->desc = dma_alloc_coherent(dev, 6196 tx_ring->size, 6197 &tx_ring->dma, 6198 GFP_KERNEL); 6199 set_dev_node(dev, orig_node); 6200 if (!tx_ring->desc) 6201 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6202 &tx_ring->dma, GFP_KERNEL); 6203 if (!tx_ring->desc) 6204 goto err; 6205 6206 tx_ring->next_to_use = 0; 6207 tx_ring->next_to_clean = 0; 6208 return 0; 6209 6210 err: 6211 vfree(tx_ring->tx_buffer_info); 6212 tx_ring->tx_buffer_info = NULL; 6213 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6214 return -ENOMEM; 6215 } 6216 6217 /** 6218 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6219 * @adapter: board private structure 6220 * 6221 * If this function returns with an error, then it's possible one or 6222 * more of the rings is populated (while the rest are not). It is the 6223 * callers duty to clean those orphaned rings. 6224 * 6225 * Return 0 on success, negative on failure 6226 **/ 6227 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6228 { 6229 int i, j = 0, err = 0; 6230 6231 for (i = 0; i < adapter->num_tx_queues; i++) { 6232 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6233 if (!err) 6234 continue; 6235 6236 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6237 goto err_setup_tx; 6238 } 6239 for (j = 0; j < adapter->num_xdp_queues; j++) { 6240 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6241 if (!err) 6242 continue; 6243 6244 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6245 goto err_setup_tx; 6246 } 6247 6248 return 0; 6249 err_setup_tx: 6250 /* rewind the index freeing the rings as we go */ 6251 while (j--) 6252 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6253 while (i--) 6254 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6255 return err; 6256 } 6257 6258 /** 6259 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6260 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6261 * 6262 * Returns 0 on success, negative on failure 6263 **/ 6264 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6265 struct ixgbe_ring *rx_ring) 6266 { 6267 struct device *dev = rx_ring->dev; 6268 int orig_node = dev_to_node(dev); 6269 int ring_node = -1; 6270 int size; 6271 6272 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6273 6274 if (rx_ring->q_vector) 6275 ring_node = rx_ring->q_vector->numa_node; 6276 6277 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6278 if (!rx_ring->rx_buffer_info) 6279 rx_ring->rx_buffer_info = vmalloc(size); 6280 if (!rx_ring->rx_buffer_info) 6281 goto err; 6282 6283 /* Round up to nearest 4K */ 6284 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6285 rx_ring->size = ALIGN(rx_ring->size, 4096); 6286 6287 set_dev_node(dev, ring_node); 6288 rx_ring->desc = dma_alloc_coherent(dev, 6289 rx_ring->size, 6290 &rx_ring->dma, 6291 GFP_KERNEL); 6292 set_dev_node(dev, orig_node); 6293 if (!rx_ring->desc) 6294 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6295 &rx_ring->dma, GFP_KERNEL); 6296 if (!rx_ring->desc) 6297 goto err; 6298 6299 rx_ring->next_to_clean = 0; 6300 rx_ring->next_to_use = 0; 6301 6302 rx_ring->xdp_prog = adapter->xdp_prog; 6303 6304 return 0; 6305 err: 6306 vfree(rx_ring->rx_buffer_info); 6307 rx_ring->rx_buffer_info = NULL; 6308 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6309 return -ENOMEM; 6310 } 6311 6312 /** 6313 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6314 * @adapter: board private structure 6315 * 6316 * If this function returns with an error, then it's possible one or 6317 * more of the rings is populated (while the rest are not). It is the 6318 * callers duty to clean those orphaned rings. 6319 * 6320 * Return 0 on success, negative on failure 6321 **/ 6322 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6323 { 6324 int i, err = 0; 6325 6326 for (i = 0; i < adapter->num_rx_queues; i++) { 6327 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6328 if (!err) 6329 continue; 6330 6331 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6332 goto err_setup_rx; 6333 } 6334 6335 #ifdef IXGBE_FCOE 6336 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6337 if (!err) 6338 #endif 6339 return 0; 6340 err_setup_rx: 6341 /* rewind the index freeing the rings as we go */ 6342 while (i--) 6343 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6344 return err; 6345 } 6346 6347 /** 6348 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6349 * @tx_ring: Tx descriptor ring for a specific queue 6350 * 6351 * Free all transmit software resources 6352 **/ 6353 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6354 { 6355 ixgbe_clean_tx_ring(tx_ring); 6356 6357 vfree(tx_ring->tx_buffer_info); 6358 tx_ring->tx_buffer_info = NULL; 6359 6360 /* if not set, then don't free */ 6361 if (!tx_ring->desc) 6362 return; 6363 6364 dma_free_coherent(tx_ring->dev, tx_ring->size, 6365 tx_ring->desc, tx_ring->dma); 6366 6367 tx_ring->desc = NULL; 6368 } 6369 6370 /** 6371 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6372 * @adapter: board private structure 6373 * 6374 * Free all transmit software resources 6375 **/ 6376 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6377 { 6378 int i; 6379 6380 for (i = 0; i < adapter->num_tx_queues; i++) 6381 if (adapter->tx_ring[i]->desc) 6382 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6383 for (i = 0; i < adapter->num_xdp_queues; i++) 6384 if (adapter->xdp_ring[i]->desc) 6385 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6386 } 6387 6388 /** 6389 * ixgbe_free_rx_resources - Free Rx Resources 6390 * @rx_ring: ring to clean the resources from 6391 * 6392 * Free all receive software resources 6393 **/ 6394 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6395 { 6396 ixgbe_clean_rx_ring(rx_ring); 6397 6398 rx_ring->xdp_prog = NULL; 6399 vfree(rx_ring->rx_buffer_info); 6400 rx_ring->rx_buffer_info = NULL; 6401 6402 /* if not set, then don't free */ 6403 if (!rx_ring->desc) 6404 return; 6405 6406 dma_free_coherent(rx_ring->dev, rx_ring->size, 6407 rx_ring->desc, rx_ring->dma); 6408 6409 rx_ring->desc = NULL; 6410 } 6411 6412 /** 6413 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6414 * @adapter: board private structure 6415 * 6416 * Free all receive software resources 6417 **/ 6418 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6419 { 6420 int i; 6421 6422 #ifdef IXGBE_FCOE 6423 ixgbe_free_fcoe_ddp_resources(adapter); 6424 6425 #endif 6426 for (i = 0; i < adapter->num_rx_queues; i++) 6427 if (adapter->rx_ring[i]->desc) 6428 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6429 } 6430 6431 /** 6432 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6433 * @netdev: network interface device structure 6434 * @new_mtu: new value for maximum frame size 6435 * 6436 * Returns 0 on success, negative on failure 6437 **/ 6438 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6439 { 6440 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6441 6442 /* 6443 * For 82599EB we cannot allow legacy VFs to enable their receive 6444 * paths when MTU greater than 1500 is configured. So display a 6445 * warning that legacy VFs will be disabled. 6446 */ 6447 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6448 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6449 (new_mtu > ETH_DATA_LEN)) 6450 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6451 6452 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6453 6454 /* must set new MTU before calling down or up */ 6455 netdev->mtu = new_mtu; 6456 6457 if (netif_running(netdev)) 6458 ixgbe_reinit_locked(adapter); 6459 6460 return 0; 6461 } 6462 6463 /** 6464 * ixgbe_open - Called when a network interface is made active 6465 * @netdev: network interface device structure 6466 * 6467 * Returns 0 on success, negative value on failure 6468 * 6469 * The open entry point is called when a network interface is made 6470 * active by the system (IFF_UP). At this point all resources needed 6471 * for transmit and receive operations are allocated, the interrupt 6472 * handler is registered with the OS, the watchdog timer is started, 6473 * and the stack is notified that the interface is ready. 6474 **/ 6475 int ixgbe_open(struct net_device *netdev) 6476 { 6477 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6478 struct ixgbe_hw *hw = &adapter->hw; 6479 int err, queues; 6480 6481 /* disallow open during test */ 6482 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6483 return -EBUSY; 6484 6485 netif_carrier_off(netdev); 6486 6487 /* allocate transmit descriptors */ 6488 err = ixgbe_setup_all_tx_resources(adapter); 6489 if (err) 6490 goto err_setup_tx; 6491 6492 /* allocate receive descriptors */ 6493 err = ixgbe_setup_all_rx_resources(adapter); 6494 if (err) 6495 goto err_setup_rx; 6496 6497 ixgbe_configure(adapter); 6498 6499 err = ixgbe_request_irq(adapter); 6500 if (err) 6501 goto err_req_irq; 6502 6503 /* Notify the stack of the actual queue counts. */ 6504 if (adapter->num_rx_pools > 1) 6505 queues = adapter->num_rx_queues_per_pool; 6506 else 6507 queues = adapter->num_tx_queues; 6508 6509 err = netif_set_real_num_tx_queues(netdev, queues); 6510 if (err) 6511 goto err_set_queues; 6512 6513 if (adapter->num_rx_pools > 1 && 6514 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 6515 queues = IXGBE_MAX_L2A_QUEUES; 6516 else 6517 queues = adapter->num_rx_queues; 6518 err = netif_set_real_num_rx_queues(netdev, queues); 6519 if (err) 6520 goto err_set_queues; 6521 6522 ixgbe_ptp_init(adapter); 6523 6524 ixgbe_up_complete(adapter); 6525 6526 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6527 udp_tunnel_get_rx_info(netdev); 6528 6529 return 0; 6530 6531 err_set_queues: 6532 ixgbe_free_irq(adapter); 6533 err_req_irq: 6534 ixgbe_free_all_rx_resources(adapter); 6535 if (hw->phy.ops.set_phy_power && !adapter->wol) 6536 hw->phy.ops.set_phy_power(&adapter->hw, false); 6537 err_setup_rx: 6538 ixgbe_free_all_tx_resources(adapter); 6539 err_setup_tx: 6540 ixgbe_reset(adapter); 6541 6542 return err; 6543 } 6544 6545 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6546 { 6547 ixgbe_ptp_suspend(adapter); 6548 6549 if (adapter->hw.phy.ops.enter_lplu) { 6550 adapter->hw.phy.reset_disable = true; 6551 ixgbe_down(adapter); 6552 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6553 adapter->hw.phy.reset_disable = false; 6554 } else { 6555 ixgbe_down(adapter); 6556 } 6557 6558 ixgbe_free_irq(adapter); 6559 6560 ixgbe_free_all_tx_resources(adapter); 6561 ixgbe_free_all_rx_resources(adapter); 6562 } 6563 6564 /** 6565 * ixgbe_close - Disables a network interface 6566 * @netdev: network interface device structure 6567 * 6568 * Returns 0, this is not allowed to fail 6569 * 6570 * The close entry point is called when an interface is de-activated 6571 * by the OS. The hardware is still under the drivers control, but 6572 * needs to be disabled. A global MAC reset is issued to stop the 6573 * hardware, and all transmit and receive resources are freed. 6574 **/ 6575 int ixgbe_close(struct net_device *netdev) 6576 { 6577 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6578 6579 ixgbe_ptp_stop(adapter); 6580 6581 if (netif_device_present(netdev)) 6582 ixgbe_close_suspend(adapter); 6583 6584 ixgbe_fdir_filter_exit(adapter); 6585 6586 ixgbe_release_hw_control(adapter); 6587 6588 return 0; 6589 } 6590 6591 #ifdef CONFIG_PM 6592 static int ixgbe_resume(struct pci_dev *pdev) 6593 { 6594 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6595 struct net_device *netdev = adapter->netdev; 6596 u32 err; 6597 6598 adapter->hw.hw_addr = adapter->io_addr; 6599 pci_set_power_state(pdev, PCI_D0); 6600 pci_restore_state(pdev); 6601 /* 6602 * pci_restore_state clears dev->state_saved so call 6603 * pci_save_state to restore it. 6604 */ 6605 pci_save_state(pdev); 6606 6607 err = pci_enable_device_mem(pdev); 6608 if (err) { 6609 e_dev_err("Cannot enable PCI device from suspend\n"); 6610 return err; 6611 } 6612 smp_mb__before_atomic(); 6613 clear_bit(__IXGBE_DISABLED, &adapter->state); 6614 pci_set_master(pdev); 6615 6616 pci_wake_from_d3(pdev, false); 6617 6618 ixgbe_reset(adapter); 6619 6620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6621 6622 rtnl_lock(); 6623 err = ixgbe_init_interrupt_scheme(adapter); 6624 if (!err && netif_running(netdev)) 6625 err = ixgbe_open(netdev); 6626 6627 6628 if (!err) 6629 netif_device_attach(netdev); 6630 rtnl_unlock(); 6631 6632 return err; 6633 } 6634 #endif /* CONFIG_PM */ 6635 6636 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6637 { 6638 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6639 struct net_device *netdev = adapter->netdev; 6640 struct ixgbe_hw *hw = &adapter->hw; 6641 u32 ctrl, fctrl; 6642 u32 wufc = adapter->wol; 6643 #ifdef CONFIG_PM 6644 int retval = 0; 6645 #endif 6646 6647 rtnl_lock(); 6648 netif_device_detach(netdev); 6649 6650 if (netif_running(netdev)) 6651 ixgbe_close_suspend(adapter); 6652 6653 ixgbe_clear_interrupt_scheme(adapter); 6654 rtnl_unlock(); 6655 6656 #ifdef CONFIG_PM 6657 retval = pci_save_state(pdev); 6658 if (retval) 6659 return retval; 6660 6661 #endif 6662 if (hw->mac.ops.stop_link_on_d3) 6663 hw->mac.ops.stop_link_on_d3(hw); 6664 6665 if (wufc) { 6666 ixgbe_set_rx_mode(netdev); 6667 6668 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6669 if (hw->mac.ops.enable_tx_laser) 6670 hw->mac.ops.enable_tx_laser(hw); 6671 6672 /* turn on all-multi mode if wake on multicast is enabled */ 6673 if (wufc & IXGBE_WUFC_MC) { 6674 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6675 fctrl |= IXGBE_FCTRL_MPE; 6676 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6677 } 6678 6679 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6680 ctrl |= IXGBE_CTRL_GIO_DIS; 6681 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6682 6683 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6684 } else { 6685 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6686 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6687 } 6688 6689 switch (hw->mac.type) { 6690 case ixgbe_mac_82598EB: 6691 pci_wake_from_d3(pdev, false); 6692 break; 6693 case ixgbe_mac_82599EB: 6694 case ixgbe_mac_X540: 6695 case ixgbe_mac_X550: 6696 case ixgbe_mac_X550EM_x: 6697 case ixgbe_mac_x550em_a: 6698 pci_wake_from_d3(pdev, !!wufc); 6699 break; 6700 default: 6701 break; 6702 } 6703 6704 *enable_wake = !!wufc; 6705 if (hw->phy.ops.set_phy_power && !*enable_wake) 6706 hw->phy.ops.set_phy_power(hw, false); 6707 6708 ixgbe_release_hw_control(adapter); 6709 6710 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6711 pci_disable_device(pdev); 6712 6713 return 0; 6714 } 6715 6716 #ifdef CONFIG_PM 6717 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6718 { 6719 int retval; 6720 bool wake; 6721 6722 retval = __ixgbe_shutdown(pdev, &wake); 6723 if (retval) 6724 return retval; 6725 6726 if (wake) { 6727 pci_prepare_to_sleep(pdev); 6728 } else { 6729 pci_wake_from_d3(pdev, false); 6730 pci_set_power_state(pdev, PCI_D3hot); 6731 } 6732 6733 return 0; 6734 } 6735 #endif /* CONFIG_PM */ 6736 6737 static void ixgbe_shutdown(struct pci_dev *pdev) 6738 { 6739 bool wake; 6740 6741 __ixgbe_shutdown(pdev, &wake); 6742 6743 if (system_state == SYSTEM_POWER_OFF) { 6744 pci_wake_from_d3(pdev, wake); 6745 pci_set_power_state(pdev, PCI_D3hot); 6746 } 6747 } 6748 6749 /** 6750 * ixgbe_update_stats - Update the board statistics counters. 6751 * @adapter: board private structure 6752 **/ 6753 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6754 { 6755 struct net_device *netdev = adapter->netdev; 6756 struct ixgbe_hw *hw = &adapter->hw; 6757 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6758 u64 total_mpc = 0; 6759 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6760 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6761 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6762 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6763 6764 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6765 test_bit(__IXGBE_RESETTING, &adapter->state)) 6766 return; 6767 6768 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6769 u64 rsc_count = 0; 6770 u64 rsc_flush = 0; 6771 for (i = 0; i < adapter->num_rx_queues; i++) { 6772 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6773 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6774 } 6775 adapter->rsc_total_count = rsc_count; 6776 adapter->rsc_total_flush = rsc_flush; 6777 } 6778 6779 for (i = 0; i < adapter->num_rx_queues; i++) { 6780 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6781 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6782 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6783 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6784 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6785 bytes += rx_ring->stats.bytes; 6786 packets += rx_ring->stats.packets; 6787 } 6788 adapter->non_eop_descs = non_eop_descs; 6789 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6790 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6791 adapter->hw_csum_rx_error = hw_csum_rx_error; 6792 netdev->stats.rx_bytes = bytes; 6793 netdev->stats.rx_packets = packets; 6794 6795 bytes = 0; 6796 packets = 0; 6797 /* gather some stats to the adapter struct that are per queue */ 6798 for (i = 0; i < adapter->num_tx_queues; i++) { 6799 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6800 restart_queue += tx_ring->tx_stats.restart_queue; 6801 tx_busy += tx_ring->tx_stats.tx_busy; 6802 bytes += tx_ring->stats.bytes; 6803 packets += tx_ring->stats.packets; 6804 } 6805 for (i = 0; i < adapter->num_xdp_queues; i++) { 6806 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6807 6808 restart_queue += xdp_ring->tx_stats.restart_queue; 6809 tx_busy += xdp_ring->tx_stats.tx_busy; 6810 bytes += xdp_ring->stats.bytes; 6811 packets += xdp_ring->stats.packets; 6812 } 6813 adapter->restart_queue = restart_queue; 6814 adapter->tx_busy = tx_busy; 6815 netdev->stats.tx_bytes = bytes; 6816 netdev->stats.tx_packets = packets; 6817 6818 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6819 6820 /* 8 register reads */ 6821 for (i = 0; i < 8; i++) { 6822 /* for packet buffers not used, the register should read 0 */ 6823 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6824 missed_rx += mpc; 6825 hwstats->mpc[i] += mpc; 6826 total_mpc += hwstats->mpc[i]; 6827 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6828 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6829 switch (hw->mac.type) { 6830 case ixgbe_mac_82598EB: 6831 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6832 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6833 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6834 hwstats->pxonrxc[i] += 6835 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6836 break; 6837 case ixgbe_mac_82599EB: 6838 case ixgbe_mac_X540: 6839 case ixgbe_mac_X550: 6840 case ixgbe_mac_X550EM_x: 6841 case ixgbe_mac_x550em_a: 6842 hwstats->pxonrxc[i] += 6843 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6844 break; 6845 default: 6846 break; 6847 } 6848 } 6849 6850 /*16 register reads */ 6851 for (i = 0; i < 16; i++) { 6852 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6853 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6854 if ((hw->mac.type == ixgbe_mac_82599EB) || 6855 (hw->mac.type == ixgbe_mac_X540) || 6856 (hw->mac.type == ixgbe_mac_X550) || 6857 (hw->mac.type == ixgbe_mac_X550EM_x) || 6858 (hw->mac.type == ixgbe_mac_x550em_a)) { 6859 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6860 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6861 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6862 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6863 } 6864 } 6865 6866 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6867 /* work around hardware counting issue */ 6868 hwstats->gprc -= missed_rx; 6869 6870 ixgbe_update_xoff_received(adapter); 6871 6872 /* 82598 hardware only has a 32 bit counter in the high register */ 6873 switch (hw->mac.type) { 6874 case ixgbe_mac_82598EB: 6875 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6876 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6877 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6878 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6879 break; 6880 case ixgbe_mac_X540: 6881 case ixgbe_mac_X550: 6882 case ixgbe_mac_X550EM_x: 6883 case ixgbe_mac_x550em_a: 6884 /* OS2BMC stats are X540 and later */ 6885 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6886 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6887 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6888 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6889 /* fall through */ 6890 case ixgbe_mac_82599EB: 6891 for (i = 0; i < 16; i++) 6892 adapter->hw_rx_no_dma_resources += 6893 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6894 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6895 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6896 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6897 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6898 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6899 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6900 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6901 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6902 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6903 #ifdef IXGBE_FCOE 6904 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6905 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6906 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6907 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6908 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6909 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6910 /* Add up per cpu counters for total ddp aloc fail */ 6911 if (adapter->fcoe.ddp_pool) { 6912 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6913 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6914 unsigned int cpu; 6915 u64 noddp = 0, noddp_ext_buff = 0; 6916 for_each_possible_cpu(cpu) { 6917 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6918 noddp += ddp_pool->noddp; 6919 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6920 } 6921 hwstats->fcoe_noddp = noddp; 6922 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6923 } 6924 #endif /* IXGBE_FCOE */ 6925 break; 6926 default: 6927 break; 6928 } 6929 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6930 hwstats->bprc += bprc; 6931 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6932 if (hw->mac.type == ixgbe_mac_82598EB) 6933 hwstats->mprc -= bprc; 6934 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6935 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6936 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6937 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6938 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6939 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6940 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6941 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6942 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6943 hwstats->lxontxc += lxon; 6944 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6945 hwstats->lxofftxc += lxoff; 6946 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6947 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6948 /* 6949 * 82598 errata - tx of flow control packets is included in tx counters 6950 */ 6951 xon_off_tot = lxon + lxoff; 6952 hwstats->gptc -= xon_off_tot; 6953 hwstats->mptc -= xon_off_tot; 6954 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6955 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6956 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6957 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6958 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6959 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6960 hwstats->ptc64 -= xon_off_tot; 6961 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6962 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6963 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6964 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6965 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6966 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6967 6968 /* Fill out the OS statistics structure */ 6969 netdev->stats.multicast = hwstats->mprc; 6970 6971 /* Rx Errors */ 6972 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6973 netdev->stats.rx_dropped = 0; 6974 netdev->stats.rx_length_errors = hwstats->rlec; 6975 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6976 netdev->stats.rx_missed_errors = total_mpc; 6977 } 6978 6979 /** 6980 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6981 * @adapter: pointer to the device adapter structure 6982 **/ 6983 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6984 { 6985 struct ixgbe_hw *hw = &adapter->hw; 6986 int i; 6987 6988 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6989 return; 6990 6991 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6992 6993 /* if interface is down do nothing */ 6994 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6995 return; 6996 6997 /* do nothing if we are not using signature filters */ 6998 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6999 return; 7000 7001 adapter->fdir_overflow++; 7002 7003 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7004 for (i = 0; i < adapter->num_tx_queues; i++) 7005 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7006 &(adapter->tx_ring[i]->state)); 7007 for (i = 0; i < adapter->num_xdp_queues; i++) 7008 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7009 &adapter->xdp_ring[i]->state); 7010 /* re-enable flow director interrupts */ 7011 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7012 } else { 7013 e_err(probe, "failed to finish FDIR re-initialization, " 7014 "ignored adding FDIR ATR filters\n"); 7015 } 7016 } 7017 7018 /** 7019 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7020 * @adapter: pointer to the device adapter structure 7021 * 7022 * This function serves two purposes. First it strobes the interrupt lines 7023 * in order to make certain interrupts are occurring. Secondly it sets the 7024 * bits needed to check for TX hangs. As a result we should immediately 7025 * determine if a hang has occurred. 7026 */ 7027 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7028 { 7029 struct ixgbe_hw *hw = &adapter->hw; 7030 u64 eics = 0; 7031 int i; 7032 7033 /* If we're down, removing or resetting, just bail */ 7034 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7035 test_bit(__IXGBE_REMOVING, &adapter->state) || 7036 test_bit(__IXGBE_RESETTING, &adapter->state)) 7037 return; 7038 7039 /* Force detection of hung controller */ 7040 if (netif_carrier_ok(adapter->netdev)) { 7041 for (i = 0; i < adapter->num_tx_queues; i++) 7042 set_check_for_tx_hang(adapter->tx_ring[i]); 7043 for (i = 0; i < adapter->num_xdp_queues; i++) 7044 set_check_for_tx_hang(adapter->xdp_ring[i]); 7045 } 7046 7047 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7048 /* 7049 * for legacy and MSI interrupts don't set any bits 7050 * that are enabled for EIAM, because this operation 7051 * would set *both* EIMS and EICS for any bit in EIAM 7052 */ 7053 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7054 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7055 } else { 7056 /* get one bit for every active tx/rx interrupt vector */ 7057 for (i = 0; i < adapter->num_q_vectors; i++) { 7058 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7059 if (qv->rx.ring || qv->tx.ring) 7060 eics |= BIT_ULL(i); 7061 } 7062 } 7063 7064 /* Cause software interrupt to ensure rings are cleaned */ 7065 ixgbe_irq_rearm_queues(adapter, eics); 7066 } 7067 7068 /** 7069 * ixgbe_watchdog_update_link - update the link status 7070 * @adapter: pointer to the device adapter structure 7071 * @link_speed: pointer to a u32 to store the link_speed 7072 **/ 7073 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7074 { 7075 struct ixgbe_hw *hw = &adapter->hw; 7076 u32 link_speed = adapter->link_speed; 7077 bool link_up = adapter->link_up; 7078 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7079 7080 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7081 return; 7082 7083 if (hw->mac.ops.check_link) { 7084 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7085 } else { 7086 /* always assume link is up, if no check link function */ 7087 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7088 link_up = true; 7089 } 7090 7091 if (adapter->ixgbe_ieee_pfc) 7092 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7093 7094 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7095 hw->mac.ops.fc_enable(hw); 7096 ixgbe_set_rx_drop_en(adapter); 7097 } 7098 7099 if (link_up || 7100 time_after(jiffies, (adapter->link_check_timeout + 7101 IXGBE_TRY_LINK_TIMEOUT))) { 7102 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7103 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7104 IXGBE_WRITE_FLUSH(hw); 7105 } 7106 7107 adapter->link_up = link_up; 7108 adapter->link_speed = link_speed; 7109 } 7110 7111 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7112 { 7113 #ifdef CONFIG_IXGBE_DCB 7114 struct net_device *netdev = adapter->netdev; 7115 struct dcb_app app = { 7116 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7117 .protocol = 0, 7118 }; 7119 u8 up = 0; 7120 7121 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7122 up = dcb_ieee_getapp_mask(netdev, &app); 7123 7124 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7125 #endif 7126 } 7127 7128 static int ixgbe_enable_macvlan(struct net_device *upper, void *data) 7129 { 7130 if (netif_is_macvlan(upper)) { 7131 struct macvlan_dev *vlan = netdev_priv(upper); 7132 7133 if (vlan->fwd_priv) 7134 netif_tx_wake_all_queues(upper); 7135 } 7136 7137 return 0; 7138 } 7139 7140 /** 7141 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7142 * print link up message 7143 * @adapter: pointer to the device adapter structure 7144 **/ 7145 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7146 { 7147 struct net_device *netdev = adapter->netdev; 7148 struct ixgbe_hw *hw = &adapter->hw; 7149 u32 link_speed = adapter->link_speed; 7150 const char *speed_str; 7151 bool flow_rx, flow_tx; 7152 7153 /* only continue if link was previously down */ 7154 if (netif_carrier_ok(netdev)) 7155 return; 7156 7157 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7158 7159 switch (hw->mac.type) { 7160 case ixgbe_mac_82598EB: { 7161 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7162 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7163 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7164 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7165 } 7166 break; 7167 case ixgbe_mac_X540: 7168 case ixgbe_mac_X550: 7169 case ixgbe_mac_X550EM_x: 7170 case ixgbe_mac_x550em_a: 7171 case ixgbe_mac_82599EB: { 7172 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7173 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7174 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7175 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7176 } 7177 break; 7178 default: 7179 flow_tx = false; 7180 flow_rx = false; 7181 break; 7182 } 7183 7184 adapter->last_rx_ptp_check = jiffies; 7185 7186 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7187 ixgbe_ptp_start_cyclecounter(adapter); 7188 7189 switch (link_speed) { 7190 case IXGBE_LINK_SPEED_10GB_FULL: 7191 speed_str = "10 Gbps"; 7192 break; 7193 case IXGBE_LINK_SPEED_2_5GB_FULL: 7194 speed_str = "2.5 Gbps"; 7195 break; 7196 case IXGBE_LINK_SPEED_1GB_FULL: 7197 speed_str = "1 Gbps"; 7198 break; 7199 case IXGBE_LINK_SPEED_100_FULL: 7200 speed_str = "100 Mbps"; 7201 break; 7202 case IXGBE_LINK_SPEED_10_FULL: 7203 speed_str = "10 Mbps"; 7204 break; 7205 default: 7206 speed_str = "unknown speed"; 7207 break; 7208 } 7209 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7210 ((flow_rx && flow_tx) ? "RX/TX" : 7211 (flow_rx ? "RX" : 7212 (flow_tx ? "TX" : "None")))); 7213 7214 netif_carrier_on(netdev); 7215 ixgbe_check_vf_rate_limit(adapter); 7216 7217 /* enable transmits */ 7218 netif_tx_wake_all_queues(adapter->netdev); 7219 7220 /* enable any upper devices */ 7221 rtnl_lock(); 7222 netdev_walk_all_upper_dev_rcu(adapter->netdev, 7223 ixgbe_enable_macvlan, NULL); 7224 rtnl_unlock(); 7225 7226 /* update the default user priority for VFs */ 7227 ixgbe_update_default_up(adapter); 7228 7229 /* ping all the active vfs to let them know link has changed */ 7230 ixgbe_ping_all_vfs(adapter); 7231 } 7232 7233 /** 7234 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7235 * print link down message 7236 * @adapter: pointer to the adapter structure 7237 **/ 7238 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7239 { 7240 struct net_device *netdev = adapter->netdev; 7241 struct ixgbe_hw *hw = &adapter->hw; 7242 7243 adapter->link_up = false; 7244 adapter->link_speed = 0; 7245 7246 /* only continue if link was up previously */ 7247 if (!netif_carrier_ok(netdev)) 7248 return; 7249 7250 /* poll for SFP+ cable when link is down */ 7251 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7252 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7253 7254 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7255 ixgbe_ptp_start_cyclecounter(adapter); 7256 7257 e_info(drv, "NIC Link is Down\n"); 7258 netif_carrier_off(netdev); 7259 7260 /* ping all the active vfs to let them know link has changed */ 7261 ixgbe_ping_all_vfs(adapter); 7262 } 7263 7264 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7265 { 7266 int i; 7267 7268 for (i = 0; i < adapter->num_tx_queues; i++) { 7269 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7270 7271 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7272 return true; 7273 } 7274 7275 for (i = 0; i < adapter->num_xdp_queues; i++) { 7276 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7277 7278 if (ring->next_to_use != ring->next_to_clean) 7279 return true; 7280 } 7281 7282 return false; 7283 } 7284 7285 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7286 { 7287 struct ixgbe_hw *hw = &adapter->hw; 7288 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7289 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7290 7291 int i, j; 7292 7293 if (!adapter->num_vfs) 7294 return false; 7295 7296 /* resetting the PF is only needed for MAC before X550 */ 7297 if (hw->mac.type >= ixgbe_mac_X550) 7298 return false; 7299 7300 for (i = 0; i < adapter->num_vfs; i++) { 7301 for (j = 0; j < q_per_pool; j++) { 7302 u32 h, t; 7303 7304 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7305 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7306 7307 if (h != t) 7308 return true; 7309 } 7310 } 7311 7312 return false; 7313 } 7314 7315 /** 7316 * ixgbe_watchdog_flush_tx - flush queues on link down 7317 * @adapter: pointer to the device adapter structure 7318 **/ 7319 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7320 { 7321 if (!netif_carrier_ok(adapter->netdev)) { 7322 if (ixgbe_ring_tx_pending(adapter) || 7323 ixgbe_vf_tx_pending(adapter)) { 7324 /* We've lost link, so the controller stops DMA, 7325 * but we've got queued Tx work that's never going 7326 * to get done, so reset controller to flush Tx. 7327 * (Do the reset outside of interrupt context). 7328 */ 7329 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7330 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7331 } 7332 } 7333 } 7334 7335 #ifdef CONFIG_PCI_IOV 7336 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7337 { 7338 struct ixgbe_hw *hw = &adapter->hw; 7339 struct pci_dev *pdev = adapter->pdev; 7340 unsigned int vf; 7341 u32 gpc; 7342 7343 if (!(netif_carrier_ok(adapter->netdev))) 7344 return; 7345 7346 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7347 if (gpc) /* If incrementing then no need for the check below */ 7348 return; 7349 /* Check to see if a bad DMA write target from an errant or 7350 * malicious VF has caused a PCIe error. If so then we can 7351 * issue a VFLR to the offending VF(s) and then resume without 7352 * requesting a full slot reset. 7353 */ 7354 7355 if (!pdev) 7356 return; 7357 7358 /* check status reg for all VFs owned by this PF */ 7359 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7360 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7361 u16 status_reg; 7362 7363 if (!vfdev) 7364 continue; 7365 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7366 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7367 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7368 pcie_flr(vfdev); 7369 } 7370 } 7371 7372 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7373 { 7374 u32 ssvpc; 7375 7376 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7377 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7378 adapter->num_vfs == 0) 7379 return; 7380 7381 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7382 7383 /* 7384 * ssvpc register is cleared on read, if zero then no 7385 * spoofed packets in the last interval. 7386 */ 7387 if (!ssvpc) 7388 return; 7389 7390 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7391 } 7392 #else 7393 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7394 { 7395 } 7396 7397 static void 7398 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7399 { 7400 } 7401 #endif /* CONFIG_PCI_IOV */ 7402 7403 7404 /** 7405 * ixgbe_watchdog_subtask - check and bring link up 7406 * @adapter: pointer to the device adapter structure 7407 **/ 7408 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7409 { 7410 /* if interface is down, removing or resetting, do nothing */ 7411 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7412 test_bit(__IXGBE_REMOVING, &adapter->state) || 7413 test_bit(__IXGBE_RESETTING, &adapter->state)) 7414 return; 7415 7416 ixgbe_watchdog_update_link(adapter); 7417 7418 if (adapter->link_up) 7419 ixgbe_watchdog_link_is_up(adapter); 7420 else 7421 ixgbe_watchdog_link_is_down(adapter); 7422 7423 ixgbe_check_for_bad_vf(adapter); 7424 ixgbe_spoof_check(adapter); 7425 ixgbe_update_stats(adapter); 7426 7427 ixgbe_watchdog_flush_tx(adapter); 7428 } 7429 7430 /** 7431 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7432 * @adapter: the ixgbe adapter structure 7433 **/ 7434 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7435 { 7436 struct ixgbe_hw *hw = &adapter->hw; 7437 s32 err; 7438 7439 /* not searching for SFP so there is nothing to do here */ 7440 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7441 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7442 return; 7443 7444 if (adapter->sfp_poll_time && 7445 time_after(adapter->sfp_poll_time, jiffies)) 7446 return; /* If not yet time to poll for SFP */ 7447 7448 /* someone else is in init, wait until next service event */ 7449 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7450 return; 7451 7452 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7453 7454 err = hw->phy.ops.identify_sfp(hw); 7455 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7456 goto sfp_out; 7457 7458 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7459 /* If no cable is present, then we need to reset 7460 * the next time we find a good cable. */ 7461 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7462 } 7463 7464 /* exit on error */ 7465 if (err) 7466 goto sfp_out; 7467 7468 /* exit if reset not needed */ 7469 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7470 goto sfp_out; 7471 7472 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7473 7474 /* 7475 * A module may be identified correctly, but the EEPROM may not have 7476 * support for that module. setup_sfp() will fail in that case, so 7477 * we should not allow that module to load. 7478 */ 7479 if (hw->mac.type == ixgbe_mac_82598EB) 7480 err = hw->phy.ops.reset(hw); 7481 else 7482 err = hw->mac.ops.setup_sfp(hw); 7483 7484 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7485 goto sfp_out; 7486 7487 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7488 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7489 7490 sfp_out: 7491 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7492 7493 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7494 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7495 e_dev_err("failed to initialize because an unsupported " 7496 "SFP+ module type was detected.\n"); 7497 e_dev_err("Reload the driver after installing a " 7498 "supported module.\n"); 7499 unregister_netdev(adapter->netdev); 7500 } 7501 } 7502 7503 /** 7504 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7505 * @adapter: the ixgbe adapter structure 7506 **/ 7507 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7508 { 7509 struct ixgbe_hw *hw = &adapter->hw; 7510 u32 speed; 7511 bool autoneg = false; 7512 7513 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7514 return; 7515 7516 /* someone else is in init, wait until next service event */ 7517 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7518 return; 7519 7520 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7521 7522 speed = hw->phy.autoneg_advertised; 7523 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 7524 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 7525 7526 /* setup the highest link when no autoneg */ 7527 if (!autoneg) { 7528 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 7529 speed = IXGBE_LINK_SPEED_10GB_FULL; 7530 } 7531 } 7532 7533 if (hw->mac.ops.setup_link) 7534 hw->mac.ops.setup_link(hw, speed, true); 7535 7536 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7537 adapter->link_check_timeout = jiffies; 7538 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7539 } 7540 7541 /** 7542 * ixgbe_service_timer - Timer Call-back 7543 * @data: pointer to adapter cast into an unsigned long 7544 **/ 7545 static void ixgbe_service_timer(unsigned long data) 7546 { 7547 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 7548 unsigned long next_event_offset; 7549 7550 /* poll faster when waiting for link */ 7551 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7552 next_event_offset = HZ / 10; 7553 else 7554 next_event_offset = HZ * 2; 7555 7556 /* Reset the timer */ 7557 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7558 7559 ixgbe_service_event_schedule(adapter); 7560 } 7561 7562 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7563 { 7564 struct ixgbe_hw *hw = &adapter->hw; 7565 u32 status; 7566 7567 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7568 return; 7569 7570 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7571 7572 if (!hw->phy.ops.handle_lasi) 7573 return; 7574 7575 status = hw->phy.ops.handle_lasi(&adapter->hw); 7576 if (status != IXGBE_ERR_OVERTEMP) 7577 return; 7578 7579 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7580 } 7581 7582 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7583 { 7584 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7585 return; 7586 7587 /* If we're already down, removing or resetting, just bail */ 7588 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7589 test_bit(__IXGBE_REMOVING, &adapter->state) || 7590 test_bit(__IXGBE_RESETTING, &adapter->state)) 7591 return; 7592 7593 ixgbe_dump(adapter); 7594 netdev_err(adapter->netdev, "Reset adapter\n"); 7595 adapter->tx_timeout_count++; 7596 7597 rtnl_lock(); 7598 ixgbe_reinit_locked(adapter); 7599 rtnl_unlock(); 7600 } 7601 7602 /** 7603 * ixgbe_service_task - manages and runs subtasks 7604 * @work: pointer to work_struct containing our data 7605 **/ 7606 static void ixgbe_service_task(struct work_struct *work) 7607 { 7608 struct ixgbe_adapter *adapter = container_of(work, 7609 struct ixgbe_adapter, 7610 service_task); 7611 if (ixgbe_removed(adapter->hw.hw_addr)) { 7612 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7613 rtnl_lock(); 7614 ixgbe_down(adapter); 7615 rtnl_unlock(); 7616 } 7617 ixgbe_service_event_complete(adapter); 7618 return; 7619 } 7620 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7621 rtnl_lock(); 7622 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7623 udp_tunnel_get_rx_info(adapter->netdev); 7624 rtnl_unlock(); 7625 } 7626 ixgbe_reset_subtask(adapter); 7627 ixgbe_phy_interrupt_subtask(adapter); 7628 ixgbe_sfp_detection_subtask(adapter); 7629 ixgbe_sfp_link_config_subtask(adapter); 7630 ixgbe_check_overtemp_subtask(adapter); 7631 ixgbe_watchdog_subtask(adapter); 7632 ixgbe_fdir_reinit_subtask(adapter); 7633 ixgbe_check_hang_subtask(adapter); 7634 7635 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7636 ixgbe_ptp_overflow_check(adapter); 7637 ixgbe_ptp_rx_hang(adapter); 7638 ixgbe_ptp_tx_hang(adapter); 7639 } 7640 7641 ixgbe_service_event_complete(adapter); 7642 } 7643 7644 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7645 struct ixgbe_tx_buffer *first, 7646 u8 *hdr_len) 7647 { 7648 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7649 struct sk_buff *skb = first->skb; 7650 union { 7651 struct iphdr *v4; 7652 struct ipv6hdr *v6; 7653 unsigned char *hdr; 7654 } ip; 7655 union { 7656 struct tcphdr *tcp; 7657 unsigned char *hdr; 7658 } l4; 7659 u32 paylen, l4_offset; 7660 int err; 7661 7662 if (skb->ip_summed != CHECKSUM_PARTIAL) 7663 return 0; 7664 7665 if (!skb_is_gso(skb)) 7666 return 0; 7667 7668 err = skb_cow_head(skb, 0); 7669 if (err < 0) 7670 return err; 7671 7672 if (eth_p_mpls(first->protocol)) 7673 ip.hdr = skb_inner_network_header(skb); 7674 else 7675 ip.hdr = skb_network_header(skb); 7676 l4.hdr = skb_checksum_start(skb); 7677 7678 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7679 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7680 7681 /* initialize outer IP header fields */ 7682 if (ip.v4->version == 4) { 7683 unsigned char *csum_start = skb_checksum_start(skb); 7684 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7685 7686 /* IP header will have to cancel out any data that 7687 * is not a part of the outer IP header 7688 */ 7689 ip.v4->check = csum_fold(csum_partial(trans_start, 7690 csum_start - trans_start, 7691 0)); 7692 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7693 7694 ip.v4->tot_len = 0; 7695 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7696 IXGBE_TX_FLAGS_CSUM | 7697 IXGBE_TX_FLAGS_IPV4; 7698 } else { 7699 ip.v6->payload_len = 0; 7700 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7701 IXGBE_TX_FLAGS_CSUM; 7702 } 7703 7704 /* determine offset of inner transport header */ 7705 l4_offset = l4.hdr - skb->data; 7706 7707 /* compute length of segmentation header */ 7708 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7709 7710 /* remove payload length from inner checksum */ 7711 paylen = skb->len - l4_offset; 7712 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7713 7714 /* update gso size and bytecount with header size */ 7715 first->gso_segs = skb_shinfo(skb)->gso_segs; 7716 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7717 7718 /* mss_l4len_id: use 0 as index for TSO */ 7719 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7720 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7721 7722 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7723 vlan_macip_lens = l4.hdr - ip.hdr; 7724 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7725 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7726 7727 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 7728 mss_l4len_idx); 7729 7730 return 1; 7731 } 7732 7733 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7734 { 7735 unsigned int offset = 0; 7736 7737 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7738 7739 return offset == skb_checksum_start_offset(skb); 7740 } 7741 7742 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7743 struct ixgbe_tx_buffer *first) 7744 { 7745 struct sk_buff *skb = first->skb; 7746 u32 vlan_macip_lens = 0; 7747 u32 type_tucmd = 0; 7748 7749 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7750 csum_failed: 7751 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7752 IXGBE_TX_FLAGS_CC))) 7753 return; 7754 goto no_csum; 7755 } 7756 7757 switch (skb->csum_offset) { 7758 case offsetof(struct tcphdr, check): 7759 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7760 /* fall through */ 7761 case offsetof(struct udphdr, check): 7762 break; 7763 case offsetof(struct sctphdr, checksum): 7764 /* validate that this is actually an SCTP request */ 7765 if (((first->protocol == htons(ETH_P_IP)) && 7766 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7767 ((first->protocol == htons(ETH_P_IPV6)) && 7768 ixgbe_ipv6_csum_is_sctp(skb))) { 7769 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7770 break; 7771 } 7772 /* fall through */ 7773 default: 7774 skb_checksum_help(skb); 7775 goto csum_failed; 7776 } 7777 7778 /* update TX checksum flag */ 7779 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7780 vlan_macip_lens = skb_checksum_start_offset(skb) - 7781 skb_network_offset(skb); 7782 no_csum: 7783 /* vlan_macip_lens: MACLEN, VLAN tag */ 7784 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7785 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7786 7787 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0); 7788 } 7789 7790 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7791 ((_flag <= _result) ? \ 7792 ((u32)(_input & _flag) * (_result / _flag)) : \ 7793 ((u32)(_input & _flag) / (_flag / _result))) 7794 7795 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7796 { 7797 /* set type for advanced descriptor with frame checksum insertion */ 7798 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7799 IXGBE_ADVTXD_DCMD_DEXT | 7800 IXGBE_ADVTXD_DCMD_IFCS; 7801 7802 /* set HW vlan bit if vlan is present */ 7803 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7804 IXGBE_ADVTXD_DCMD_VLE); 7805 7806 /* set segmentation enable bits for TSO/FSO */ 7807 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7808 IXGBE_ADVTXD_DCMD_TSE); 7809 7810 /* set timestamp bit if present */ 7811 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7812 IXGBE_ADVTXD_MAC_TSTAMP); 7813 7814 /* insert frame checksum */ 7815 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7816 7817 return cmd_type; 7818 } 7819 7820 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7821 u32 tx_flags, unsigned int paylen) 7822 { 7823 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7824 7825 /* enable L4 checksum for TSO and TX checksum offload */ 7826 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7827 IXGBE_TX_FLAGS_CSUM, 7828 IXGBE_ADVTXD_POPTS_TXSM); 7829 7830 /* enble IPv4 checksum for TSO */ 7831 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7832 IXGBE_TX_FLAGS_IPV4, 7833 IXGBE_ADVTXD_POPTS_IXSM); 7834 7835 /* 7836 * Check Context must be set if Tx switch is enabled, which it 7837 * always is for case where virtual functions are running 7838 */ 7839 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7840 IXGBE_TX_FLAGS_CC, 7841 IXGBE_ADVTXD_CC); 7842 7843 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7844 } 7845 7846 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7847 { 7848 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7849 7850 /* Herbert's original patch had: 7851 * smp_mb__after_netif_stop_queue(); 7852 * but since that doesn't exist yet, just open code it. 7853 */ 7854 smp_mb(); 7855 7856 /* We need to check again in a case another CPU has just 7857 * made room available. 7858 */ 7859 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7860 return -EBUSY; 7861 7862 /* A reprieve! - use start_queue because it doesn't call schedule */ 7863 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7864 ++tx_ring->tx_stats.restart_queue; 7865 return 0; 7866 } 7867 7868 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7869 { 7870 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7871 return 0; 7872 7873 return __ixgbe_maybe_stop_tx(tx_ring, size); 7874 } 7875 7876 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7877 IXGBE_TXD_CMD_RS) 7878 7879 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7880 struct ixgbe_tx_buffer *first, 7881 const u8 hdr_len) 7882 { 7883 struct sk_buff *skb = first->skb; 7884 struct ixgbe_tx_buffer *tx_buffer; 7885 union ixgbe_adv_tx_desc *tx_desc; 7886 struct skb_frag_struct *frag; 7887 dma_addr_t dma; 7888 unsigned int data_len, size; 7889 u32 tx_flags = first->tx_flags; 7890 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7891 u16 i = tx_ring->next_to_use; 7892 7893 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7894 7895 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7896 7897 size = skb_headlen(skb); 7898 data_len = skb->data_len; 7899 7900 #ifdef IXGBE_FCOE 7901 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7902 if (data_len < sizeof(struct fcoe_crc_eof)) { 7903 size -= sizeof(struct fcoe_crc_eof) - data_len; 7904 data_len = 0; 7905 } else { 7906 data_len -= sizeof(struct fcoe_crc_eof); 7907 } 7908 } 7909 7910 #endif 7911 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7912 7913 tx_buffer = first; 7914 7915 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7916 if (dma_mapping_error(tx_ring->dev, dma)) 7917 goto dma_error; 7918 7919 /* record length, and DMA address */ 7920 dma_unmap_len_set(tx_buffer, len, size); 7921 dma_unmap_addr_set(tx_buffer, dma, dma); 7922 7923 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7924 7925 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7926 tx_desc->read.cmd_type_len = 7927 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7928 7929 i++; 7930 tx_desc++; 7931 if (i == tx_ring->count) { 7932 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7933 i = 0; 7934 } 7935 tx_desc->read.olinfo_status = 0; 7936 7937 dma += IXGBE_MAX_DATA_PER_TXD; 7938 size -= IXGBE_MAX_DATA_PER_TXD; 7939 7940 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7941 } 7942 7943 if (likely(!data_len)) 7944 break; 7945 7946 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7947 7948 i++; 7949 tx_desc++; 7950 if (i == tx_ring->count) { 7951 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7952 i = 0; 7953 } 7954 tx_desc->read.olinfo_status = 0; 7955 7956 #ifdef IXGBE_FCOE 7957 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7958 #else 7959 size = skb_frag_size(frag); 7960 #endif 7961 data_len -= size; 7962 7963 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7964 DMA_TO_DEVICE); 7965 7966 tx_buffer = &tx_ring->tx_buffer_info[i]; 7967 } 7968 7969 /* write last descriptor with RS and EOP bits */ 7970 cmd_type |= size | IXGBE_TXD_CMD; 7971 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7972 7973 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7974 7975 /* set the timestamp */ 7976 first->time_stamp = jiffies; 7977 7978 /* 7979 * Force memory writes to complete before letting h/w know there 7980 * are new descriptors to fetch. (Only applicable for weak-ordered 7981 * memory model archs, such as IA-64). 7982 * 7983 * We also need this memory barrier to make certain all of the 7984 * status bits have been updated before next_to_watch is written. 7985 */ 7986 wmb(); 7987 7988 /* set next_to_watch value indicating a packet is present */ 7989 first->next_to_watch = tx_desc; 7990 7991 i++; 7992 if (i == tx_ring->count) 7993 i = 0; 7994 7995 tx_ring->next_to_use = i; 7996 7997 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7998 7999 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8000 writel(i, tx_ring->tail); 8001 8002 /* we need this if more than one processor can write to our tail 8003 * at a time, it synchronizes IO on IA64/Altix systems 8004 */ 8005 mmiowb(); 8006 } 8007 8008 return 0; 8009 dma_error: 8010 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8011 tx_buffer = &tx_ring->tx_buffer_info[i]; 8012 8013 /* clear dma mappings for failed tx_buffer_info map */ 8014 while (tx_buffer != first) { 8015 if (dma_unmap_len(tx_buffer, len)) 8016 dma_unmap_page(tx_ring->dev, 8017 dma_unmap_addr(tx_buffer, dma), 8018 dma_unmap_len(tx_buffer, len), 8019 DMA_TO_DEVICE); 8020 dma_unmap_len_set(tx_buffer, len, 0); 8021 8022 if (i--) 8023 i += tx_ring->count; 8024 tx_buffer = &tx_ring->tx_buffer_info[i]; 8025 } 8026 8027 if (dma_unmap_len(tx_buffer, len)) 8028 dma_unmap_single(tx_ring->dev, 8029 dma_unmap_addr(tx_buffer, dma), 8030 dma_unmap_len(tx_buffer, len), 8031 DMA_TO_DEVICE); 8032 dma_unmap_len_set(tx_buffer, len, 0); 8033 8034 dev_kfree_skb_any(first->skb); 8035 first->skb = NULL; 8036 8037 tx_ring->next_to_use = i; 8038 8039 return -1; 8040 } 8041 8042 static void ixgbe_atr(struct ixgbe_ring *ring, 8043 struct ixgbe_tx_buffer *first) 8044 { 8045 struct ixgbe_q_vector *q_vector = ring->q_vector; 8046 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8047 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8048 union { 8049 unsigned char *network; 8050 struct iphdr *ipv4; 8051 struct ipv6hdr *ipv6; 8052 } hdr; 8053 struct tcphdr *th; 8054 unsigned int hlen; 8055 struct sk_buff *skb; 8056 __be16 vlan_id; 8057 int l4_proto; 8058 8059 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8060 if (!q_vector) 8061 return; 8062 8063 /* do nothing if sampling is disabled */ 8064 if (!ring->atr_sample_rate) 8065 return; 8066 8067 ring->atr_count++; 8068 8069 /* currently only IPv4/IPv6 with TCP is supported */ 8070 if ((first->protocol != htons(ETH_P_IP)) && 8071 (first->protocol != htons(ETH_P_IPV6))) 8072 return; 8073 8074 /* snag network header to get L4 type and address */ 8075 skb = first->skb; 8076 hdr.network = skb_network_header(skb); 8077 if (unlikely(hdr.network <= skb->data)) 8078 return; 8079 if (skb->encapsulation && 8080 first->protocol == htons(ETH_P_IP) && 8081 hdr.ipv4->protocol == IPPROTO_UDP) { 8082 struct ixgbe_adapter *adapter = q_vector->adapter; 8083 8084 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8085 VXLAN_HEADROOM)) 8086 return; 8087 8088 /* verify the port is recognized as VXLAN */ 8089 if (adapter->vxlan_port && 8090 udp_hdr(skb)->dest == adapter->vxlan_port) 8091 hdr.network = skb_inner_network_header(skb); 8092 8093 if (adapter->geneve_port && 8094 udp_hdr(skb)->dest == adapter->geneve_port) 8095 hdr.network = skb_inner_network_header(skb); 8096 } 8097 8098 /* Make sure we have at least [minimum IPv4 header + TCP] 8099 * or [IPv6 header] bytes 8100 */ 8101 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8102 return; 8103 8104 /* Currently only IPv4/IPv6 with TCP is supported */ 8105 switch (hdr.ipv4->version) { 8106 case IPVERSION: 8107 /* access ihl as u8 to avoid unaligned access on ia64 */ 8108 hlen = (hdr.network[0] & 0x0F) << 2; 8109 l4_proto = hdr.ipv4->protocol; 8110 break; 8111 case 6: 8112 hlen = hdr.network - skb->data; 8113 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8114 hlen -= hdr.network - skb->data; 8115 break; 8116 default: 8117 return; 8118 } 8119 8120 if (l4_proto != IPPROTO_TCP) 8121 return; 8122 8123 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8124 hlen + sizeof(struct tcphdr))) 8125 return; 8126 8127 th = (struct tcphdr *)(hdr.network + hlen); 8128 8129 /* skip this packet since the socket is closing */ 8130 if (th->fin) 8131 return; 8132 8133 /* sample on all syn packets or once every atr sample count */ 8134 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8135 return; 8136 8137 /* reset sample count */ 8138 ring->atr_count = 0; 8139 8140 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8141 8142 /* 8143 * src and dst are inverted, think how the receiver sees them 8144 * 8145 * The input is broken into two sections, a non-compressed section 8146 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8147 * is XORed together and stored in the compressed dword. 8148 */ 8149 input.formatted.vlan_id = vlan_id; 8150 8151 /* 8152 * since src port and flex bytes occupy the same word XOR them together 8153 * and write the value to source port portion of compressed dword 8154 */ 8155 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8156 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8157 else 8158 common.port.src ^= th->dest ^ first->protocol; 8159 common.port.dst ^= th->source; 8160 8161 switch (hdr.ipv4->version) { 8162 case IPVERSION: 8163 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8164 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8165 break; 8166 case 6: 8167 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8168 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8169 hdr.ipv6->saddr.s6_addr32[1] ^ 8170 hdr.ipv6->saddr.s6_addr32[2] ^ 8171 hdr.ipv6->saddr.s6_addr32[3] ^ 8172 hdr.ipv6->daddr.s6_addr32[0] ^ 8173 hdr.ipv6->daddr.s6_addr32[1] ^ 8174 hdr.ipv6->daddr.s6_addr32[2] ^ 8175 hdr.ipv6->daddr.s6_addr32[3]; 8176 break; 8177 default: 8178 break; 8179 } 8180 8181 if (hdr.network != skb_network_header(skb)) 8182 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8183 8184 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8185 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8186 input, common, ring->queue_index); 8187 } 8188 8189 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8190 void *accel_priv, select_queue_fallback_t fallback) 8191 { 8192 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8193 #ifdef IXGBE_FCOE 8194 struct ixgbe_adapter *adapter; 8195 struct ixgbe_ring_feature *f; 8196 int txq; 8197 #endif 8198 8199 if (fwd_adapter) 8200 return skb->queue_mapping + fwd_adapter->tx_base_queue; 8201 8202 #ifdef IXGBE_FCOE 8203 8204 /* 8205 * only execute the code below if protocol is FCoE 8206 * or FIP and we have FCoE enabled on the adapter 8207 */ 8208 switch (vlan_get_protocol(skb)) { 8209 case htons(ETH_P_FCOE): 8210 case htons(ETH_P_FIP): 8211 adapter = netdev_priv(dev); 8212 8213 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8214 break; 8215 /* fall through */ 8216 default: 8217 return fallback(dev, skb); 8218 } 8219 8220 f = &adapter->ring_feature[RING_F_FCOE]; 8221 8222 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8223 smp_processor_id(); 8224 8225 while (txq >= f->indices) 8226 txq -= f->indices; 8227 8228 return txq + f->offset; 8229 #else 8230 return fallback(dev, skb); 8231 #endif 8232 } 8233 8234 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8235 struct xdp_buff *xdp) 8236 { 8237 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8238 struct ixgbe_tx_buffer *tx_buffer; 8239 union ixgbe_adv_tx_desc *tx_desc; 8240 u32 len, cmd_type; 8241 dma_addr_t dma; 8242 u16 i; 8243 8244 len = xdp->data_end - xdp->data; 8245 8246 if (unlikely(!ixgbe_desc_unused(ring))) 8247 return IXGBE_XDP_CONSUMED; 8248 8249 dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE); 8250 if (dma_mapping_error(ring->dev, dma)) 8251 return IXGBE_XDP_CONSUMED; 8252 8253 /* record the location of the first descriptor for this packet */ 8254 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8255 tx_buffer->bytecount = len; 8256 tx_buffer->gso_segs = 1; 8257 tx_buffer->protocol = 0; 8258 8259 i = ring->next_to_use; 8260 tx_desc = IXGBE_TX_DESC(ring, i); 8261 8262 dma_unmap_len_set(tx_buffer, len, len); 8263 dma_unmap_addr_set(tx_buffer, dma, dma); 8264 tx_buffer->data = xdp->data; 8265 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8266 8267 /* put descriptor type bits */ 8268 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8269 IXGBE_ADVTXD_DCMD_DEXT | 8270 IXGBE_ADVTXD_DCMD_IFCS; 8271 cmd_type |= len | IXGBE_TXD_CMD; 8272 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8273 tx_desc->read.olinfo_status = 8274 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8275 8276 /* Avoid any potential race with xdp_xmit and cleanup */ 8277 smp_wmb(); 8278 8279 /* set next_to_watch value indicating a packet is present */ 8280 i++; 8281 if (i == ring->count) 8282 i = 0; 8283 8284 tx_buffer->next_to_watch = tx_desc; 8285 ring->next_to_use = i; 8286 8287 return IXGBE_XDP_TX; 8288 } 8289 8290 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8291 struct ixgbe_adapter *adapter, 8292 struct ixgbe_ring *tx_ring) 8293 { 8294 struct ixgbe_tx_buffer *first; 8295 int tso; 8296 u32 tx_flags = 0; 8297 unsigned short f; 8298 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8299 __be16 protocol = skb->protocol; 8300 u8 hdr_len = 0; 8301 8302 /* 8303 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8304 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8305 * + 2 desc gap to keep tail from touching head, 8306 * + 1 desc for context descriptor, 8307 * otherwise try next time 8308 */ 8309 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8310 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8311 8312 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8313 tx_ring->tx_stats.tx_busy++; 8314 return NETDEV_TX_BUSY; 8315 } 8316 8317 /* record the location of the first descriptor for this packet */ 8318 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8319 first->skb = skb; 8320 first->bytecount = skb->len; 8321 first->gso_segs = 1; 8322 8323 /* if we have a HW VLAN tag being added default to the HW one */ 8324 if (skb_vlan_tag_present(skb)) { 8325 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8326 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8327 /* else if it is a SW VLAN check the next protocol and store the tag */ 8328 } else if (protocol == htons(ETH_P_8021Q)) { 8329 struct vlan_hdr *vhdr, _vhdr; 8330 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8331 if (!vhdr) 8332 goto out_drop; 8333 8334 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8335 IXGBE_TX_FLAGS_VLAN_SHIFT; 8336 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8337 } 8338 protocol = vlan_get_protocol(skb); 8339 8340 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8341 adapter->ptp_clock) { 8342 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8343 &adapter->state)) { 8344 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8345 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8346 8347 /* schedule check for Tx timestamp */ 8348 adapter->ptp_tx_skb = skb_get(skb); 8349 adapter->ptp_tx_start = jiffies; 8350 schedule_work(&adapter->ptp_tx_work); 8351 } else { 8352 adapter->tx_hwtstamp_skipped++; 8353 } 8354 } 8355 8356 skb_tx_timestamp(skb); 8357 8358 #ifdef CONFIG_PCI_IOV 8359 /* 8360 * Use the l2switch_enable flag - would be false if the DMA 8361 * Tx switch had been disabled. 8362 */ 8363 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8364 tx_flags |= IXGBE_TX_FLAGS_CC; 8365 8366 #endif 8367 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8368 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8369 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8370 (skb->priority != TC_PRIO_CONTROL))) { 8371 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8372 tx_flags |= (skb->priority & 0x7) << 8373 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8374 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8375 struct vlan_ethhdr *vhdr; 8376 8377 if (skb_cow_head(skb, 0)) 8378 goto out_drop; 8379 vhdr = (struct vlan_ethhdr *)skb->data; 8380 vhdr->h_vlan_TCI = htons(tx_flags >> 8381 IXGBE_TX_FLAGS_VLAN_SHIFT); 8382 } else { 8383 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8384 } 8385 } 8386 8387 /* record initial flags and protocol */ 8388 first->tx_flags = tx_flags; 8389 first->protocol = protocol; 8390 8391 #ifdef IXGBE_FCOE 8392 /* setup tx offload for FCoE */ 8393 if ((protocol == htons(ETH_P_FCOE)) && 8394 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8395 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8396 if (tso < 0) 8397 goto out_drop; 8398 8399 goto xmit_fcoe; 8400 } 8401 8402 #endif /* IXGBE_FCOE */ 8403 tso = ixgbe_tso(tx_ring, first, &hdr_len); 8404 if (tso < 0) 8405 goto out_drop; 8406 else if (!tso) 8407 ixgbe_tx_csum(tx_ring, first); 8408 8409 /* add the ATR filter if ATR is on */ 8410 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8411 ixgbe_atr(tx_ring, first); 8412 8413 #ifdef IXGBE_FCOE 8414 xmit_fcoe: 8415 #endif /* IXGBE_FCOE */ 8416 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8417 goto cleanup_tx_timestamp; 8418 8419 return NETDEV_TX_OK; 8420 8421 out_drop: 8422 dev_kfree_skb_any(first->skb); 8423 first->skb = NULL; 8424 cleanup_tx_timestamp: 8425 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8426 dev_kfree_skb_any(adapter->ptp_tx_skb); 8427 adapter->ptp_tx_skb = NULL; 8428 cancel_work_sync(&adapter->ptp_tx_work); 8429 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8430 } 8431 8432 return NETDEV_TX_OK; 8433 } 8434 8435 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8436 struct net_device *netdev, 8437 struct ixgbe_ring *ring) 8438 { 8439 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8440 struct ixgbe_ring *tx_ring; 8441 8442 /* 8443 * The minimum packet size for olinfo paylen is 17 so pad the skb 8444 * in order to meet this minimum size requirement. 8445 */ 8446 if (skb_put_padto(skb, 17)) 8447 return NETDEV_TX_OK; 8448 8449 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8450 8451 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8452 } 8453 8454 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8455 struct net_device *netdev) 8456 { 8457 return __ixgbe_xmit_frame(skb, netdev, NULL); 8458 } 8459 8460 /** 8461 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8462 * @netdev: network interface device structure 8463 * @p: pointer to an address structure 8464 * 8465 * Returns 0 on success, negative on failure 8466 **/ 8467 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8468 { 8469 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8470 struct ixgbe_hw *hw = &adapter->hw; 8471 struct sockaddr *addr = p; 8472 8473 if (!is_valid_ether_addr(addr->sa_data)) 8474 return -EADDRNOTAVAIL; 8475 8476 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8477 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8478 8479 ixgbe_mac_set_default_filter(adapter); 8480 8481 return 0; 8482 } 8483 8484 static int 8485 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8486 { 8487 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8488 struct ixgbe_hw *hw = &adapter->hw; 8489 u16 value; 8490 int rc; 8491 8492 if (prtad != hw->phy.mdio.prtad) 8493 return -EINVAL; 8494 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8495 if (!rc) 8496 rc = value; 8497 return rc; 8498 } 8499 8500 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8501 u16 addr, u16 value) 8502 { 8503 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8504 struct ixgbe_hw *hw = &adapter->hw; 8505 8506 if (prtad != hw->phy.mdio.prtad) 8507 return -EINVAL; 8508 return hw->phy.ops.write_reg(hw, addr, devad, value); 8509 } 8510 8511 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8512 { 8513 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8514 8515 switch (cmd) { 8516 case SIOCSHWTSTAMP: 8517 return ixgbe_ptp_set_ts_config(adapter, req); 8518 case SIOCGHWTSTAMP: 8519 return ixgbe_ptp_get_ts_config(adapter, req); 8520 default: 8521 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8522 } 8523 } 8524 8525 /** 8526 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8527 * netdev->dev_addrs 8528 * @netdev: network interface device structure 8529 * 8530 * Returns non-zero on failure 8531 **/ 8532 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8533 { 8534 int err = 0; 8535 struct ixgbe_adapter *adapter = netdev_priv(dev); 8536 struct ixgbe_hw *hw = &adapter->hw; 8537 8538 if (is_valid_ether_addr(hw->mac.san_addr)) { 8539 rtnl_lock(); 8540 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8541 rtnl_unlock(); 8542 8543 /* update SAN MAC vmdq pool selection */ 8544 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8545 } 8546 return err; 8547 } 8548 8549 /** 8550 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8551 * netdev->dev_addrs 8552 * @netdev: network interface device structure 8553 * 8554 * Returns non-zero on failure 8555 **/ 8556 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8557 { 8558 int err = 0; 8559 struct ixgbe_adapter *adapter = netdev_priv(dev); 8560 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8561 8562 if (is_valid_ether_addr(mac->san_addr)) { 8563 rtnl_lock(); 8564 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8565 rtnl_unlock(); 8566 } 8567 return err; 8568 } 8569 8570 #ifdef CONFIG_NET_POLL_CONTROLLER 8571 /* 8572 * Polling 'interrupt' - used by things like netconsole to send skbs 8573 * without having to re-enable interrupts. It's not called while 8574 * the interrupt routine is executing. 8575 */ 8576 static void ixgbe_netpoll(struct net_device *netdev) 8577 { 8578 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8579 int i; 8580 8581 /* if interface is down do nothing */ 8582 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8583 return; 8584 8585 /* loop through and schedule all active queues */ 8586 for (i = 0; i < adapter->num_q_vectors; i++) 8587 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8588 } 8589 8590 #endif 8591 8592 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8593 struct ixgbe_ring *ring) 8594 { 8595 u64 bytes, packets; 8596 unsigned int start; 8597 8598 if (ring) { 8599 do { 8600 start = u64_stats_fetch_begin_irq(&ring->syncp); 8601 packets = ring->stats.packets; 8602 bytes = ring->stats.bytes; 8603 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8604 stats->tx_packets += packets; 8605 stats->tx_bytes += bytes; 8606 } 8607 } 8608 8609 static void ixgbe_get_stats64(struct net_device *netdev, 8610 struct rtnl_link_stats64 *stats) 8611 { 8612 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8613 int i; 8614 8615 rcu_read_lock(); 8616 for (i = 0; i < adapter->num_rx_queues; i++) { 8617 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 8618 u64 bytes, packets; 8619 unsigned int start; 8620 8621 if (ring) { 8622 do { 8623 start = u64_stats_fetch_begin_irq(&ring->syncp); 8624 packets = ring->stats.packets; 8625 bytes = ring->stats.bytes; 8626 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8627 stats->rx_packets += packets; 8628 stats->rx_bytes += bytes; 8629 } 8630 } 8631 8632 for (i = 0; i < adapter->num_tx_queues; i++) { 8633 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 8634 8635 ixgbe_get_ring_stats64(stats, ring); 8636 } 8637 for (i = 0; i < adapter->num_xdp_queues; i++) { 8638 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->xdp_ring[i]); 8639 8640 ixgbe_get_ring_stats64(stats, ring); 8641 } 8642 rcu_read_unlock(); 8643 8644 /* following stats updated by ixgbe_watchdog_task() */ 8645 stats->multicast = netdev->stats.multicast; 8646 stats->rx_errors = netdev->stats.rx_errors; 8647 stats->rx_length_errors = netdev->stats.rx_length_errors; 8648 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8649 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8650 } 8651 8652 #ifdef CONFIG_IXGBE_DCB 8653 /** 8654 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8655 * @adapter: pointer to ixgbe_adapter 8656 * @tc: number of traffic classes currently enabled 8657 * 8658 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8659 * 802.1Q priority maps to a packet buffer that exists. 8660 */ 8661 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8662 { 8663 struct ixgbe_hw *hw = &adapter->hw; 8664 u32 reg, rsave; 8665 int i; 8666 8667 /* 82598 have a static priority to TC mapping that can not 8668 * be changed so no validation is needed. 8669 */ 8670 if (hw->mac.type == ixgbe_mac_82598EB) 8671 return; 8672 8673 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8674 rsave = reg; 8675 8676 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8677 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8678 8679 /* If up2tc is out of bounds default to zero */ 8680 if (up2tc > tc) 8681 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8682 } 8683 8684 if (reg != rsave) 8685 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8686 8687 return; 8688 } 8689 8690 /** 8691 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8692 * @adapter: Pointer to adapter struct 8693 * 8694 * Populate the netdev user priority to tc map 8695 */ 8696 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8697 { 8698 struct net_device *dev = adapter->netdev; 8699 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8700 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8701 u8 prio; 8702 8703 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8704 u8 tc = 0; 8705 8706 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8707 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8708 else if (ets) 8709 tc = ets->prio_tc[prio]; 8710 8711 netdev_set_prio_tc_map(dev, prio, tc); 8712 } 8713 } 8714 8715 #endif /* CONFIG_IXGBE_DCB */ 8716 /** 8717 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8718 * 8719 * @netdev: net device to configure 8720 * @tc: number of traffic classes to enable 8721 */ 8722 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8723 { 8724 struct ixgbe_adapter *adapter = netdev_priv(dev); 8725 struct ixgbe_hw *hw = &adapter->hw; 8726 bool pools; 8727 8728 /* Hardware supports up to 8 traffic classes */ 8729 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8730 return -EINVAL; 8731 8732 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8733 return -EINVAL; 8734 8735 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 8736 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 8737 return -EBUSY; 8738 8739 /* Hardware has to reinitialize queues and interrupts to 8740 * match packet buffer alignment. Unfortunately, the 8741 * hardware is not flexible enough to do this dynamically. 8742 */ 8743 if (netif_running(dev)) 8744 ixgbe_close(dev); 8745 else 8746 ixgbe_reset(adapter); 8747 8748 ixgbe_clear_interrupt_scheme(adapter); 8749 8750 #ifdef CONFIG_IXGBE_DCB 8751 if (tc) { 8752 netdev_set_num_tc(dev, tc); 8753 ixgbe_set_prio_tc_map(adapter); 8754 8755 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8756 8757 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8758 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8759 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8760 } 8761 } else { 8762 netdev_reset_tc(dev); 8763 8764 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8765 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8766 8767 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8768 8769 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8770 adapter->dcb_cfg.pfc_mode_enable = false; 8771 } 8772 8773 ixgbe_validate_rtr(adapter, tc); 8774 8775 #endif /* CONFIG_IXGBE_DCB */ 8776 ixgbe_init_interrupt_scheme(adapter); 8777 8778 if (netif_running(dev)) 8779 return ixgbe_open(dev); 8780 8781 return 0; 8782 } 8783 8784 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8785 struct tc_cls_u32_offload *cls) 8786 { 8787 u32 hdl = cls->knode.handle; 8788 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8789 u32 loc = cls->knode.handle & 0xfffff; 8790 int err = 0, i, j; 8791 struct ixgbe_jump_table *jump = NULL; 8792 8793 if (loc > IXGBE_MAX_HW_ENTRIES) 8794 return -EINVAL; 8795 8796 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8797 return -EINVAL; 8798 8799 /* Clear this filter in the link data it is associated with */ 8800 if (uhtid != 0x800) { 8801 jump = adapter->jump_tables[uhtid]; 8802 if (!jump) 8803 return -EINVAL; 8804 if (!test_bit(loc - 1, jump->child_loc_map)) 8805 return -EINVAL; 8806 clear_bit(loc - 1, jump->child_loc_map); 8807 } 8808 8809 /* Check if the filter being deleted is a link */ 8810 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8811 jump = adapter->jump_tables[i]; 8812 if (jump && jump->link_hdl == hdl) { 8813 /* Delete filters in the hardware in the child hash 8814 * table associated with this link 8815 */ 8816 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8817 if (!test_bit(j, jump->child_loc_map)) 8818 continue; 8819 spin_lock(&adapter->fdir_perfect_lock); 8820 err = ixgbe_update_ethtool_fdir_entry(adapter, 8821 NULL, 8822 j + 1); 8823 spin_unlock(&adapter->fdir_perfect_lock); 8824 clear_bit(j, jump->child_loc_map); 8825 } 8826 /* Remove resources for this link */ 8827 kfree(jump->input); 8828 kfree(jump->mask); 8829 kfree(jump); 8830 adapter->jump_tables[i] = NULL; 8831 return err; 8832 } 8833 } 8834 8835 spin_lock(&adapter->fdir_perfect_lock); 8836 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8837 spin_unlock(&adapter->fdir_perfect_lock); 8838 return err; 8839 } 8840 8841 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8842 __be16 protocol, 8843 struct tc_cls_u32_offload *cls) 8844 { 8845 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8846 8847 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8848 return -EINVAL; 8849 8850 /* This ixgbe devices do not support hash tables at the moment 8851 * so abort when given hash tables. 8852 */ 8853 if (cls->hnode.divisor > 0) 8854 return -EINVAL; 8855 8856 set_bit(uhtid - 1, &adapter->tables); 8857 return 0; 8858 } 8859 8860 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8861 struct tc_cls_u32_offload *cls) 8862 { 8863 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8864 8865 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8866 return -EINVAL; 8867 8868 clear_bit(uhtid - 1, &adapter->tables); 8869 return 0; 8870 } 8871 8872 #ifdef CONFIG_NET_CLS_ACT 8873 struct upper_walk_data { 8874 struct ixgbe_adapter *adapter; 8875 u64 action; 8876 int ifindex; 8877 u8 queue; 8878 }; 8879 8880 static int get_macvlan_queue(struct net_device *upper, void *_data) 8881 { 8882 if (netif_is_macvlan(upper)) { 8883 struct macvlan_dev *dfwd = netdev_priv(upper); 8884 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 8885 struct upper_walk_data *data = _data; 8886 struct ixgbe_adapter *adapter = data->adapter; 8887 int ifindex = data->ifindex; 8888 8889 if (vadapter && vadapter->netdev->ifindex == ifindex) { 8890 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 8891 data->action = data->queue; 8892 return 1; 8893 } 8894 } 8895 8896 return 0; 8897 } 8898 8899 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 8900 u8 *queue, u64 *action) 8901 { 8902 unsigned int num_vfs = adapter->num_vfs, vf; 8903 struct upper_walk_data data; 8904 struct net_device *upper; 8905 8906 /* redirect to a SRIOV VF */ 8907 for (vf = 0; vf < num_vfs; ++vf) { 8908 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 8909 if (upper->ifindex == ifindex) { 8910 if (adapter->num_rx_pools > 1) 8911 *queue = vf * 2; 8912 else 8913 *queue = vf * adapter->num_rx_queues_per_pool; 8914 8915 *action = vf + 1; 8916 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 8917 return 0; 8918 } 8919 } 8920 8921 /* redirect to a offloaded macvlan netdev */ 8922 data.adapter = adapter; 8923 data.ifindex = ifindex; 8924 data.action = 0; 8925 data.queue = 0; 8926 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 8927 get_macvlan_queue, &data)) { 8928 *action = data.action; 8929 *queue = data.queue; 8930 8931 return 0; 8932 } 8933 8934 return -EINVAL; 8935 } 8936 8937 static int parse_tc_actions(struct ixgbe_adapter *adapter, 8938 struct tcf_exts *exts, u64 *action, u8 *queue) 8939 { 8940 const struct tc_action *a; 8941 LIST_HEAD(actions); 8942 int err; 8943 8944 if (tc_no_actions(exts)) 8945 return -EINVAL; 8946 8947 tcf_exts_to_list(exts, &actions); 8948 list_for_each_entry(a, &actions, list) { 8949 8950 /* Drop action */ 8951 if (is_tcf_gact_shot(a)) { 8952 *action = IXGBE_FDIR_DROP_QUEUE; 8953 *queue = IXGBE_FDIR_DROP_QUEUE; 8954 return 0; 8955 } 8956 8957 /* Redirect to a VF or a offloaded macvlan */ 8958 if (is_tcf_mirred_egress_redirect(a)) { 8959 int ifindex = tcf_mirred_ifindex(a); 8960 8961 err = handle_redirect_action(adapter, ifindex, queue, 8962 action); 8963 if (err == 0) 8964 return err; 8965 } 8966 } 8967 8968 return -EINVAL; 8969 } 8970 #else 8971 static int parse_tc_actions(struct ixgbe_adapter *adapter, 8972 struct tcf_exts *exts, u64 *action, u8 *queue) 8973 { 8974 return -EINVAL; 8975 } 8976 #endif /* CONFIG_NET_CLS_ACT */ 8977 8978 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 8979 union ixgbe_atr_input *mask, 8980 struct tc_cls_u32_offload *cls, 8981 struct ixgbe_mat_field *field_ptr, 8982 struct ixgbe_nexthdr *nexthdr) 8983 { 8984 int i, j, off; 8985 __be32 val, m; 8986 bool found_entry = false, found_jump_field = false; 8987 8988 for (i = 0; i < cls->knode.sel->nkeys; i++) { 8989 off = cls->knode.sel->keys[i].off; 8990 val = cls->knode.sel->keys[i].val; 8991 m = cls->knode.sel->keys[i].mask; 8992 8993 for (j = 0; field_ptr[j].val; j++) { 8994 if (field_ptr[j].off == off) { 8995 field_ptr[j].val(input, mask, val, m); 8996 input->filter.formatted.flow_type |= 8997 field_ptr[j].type; 8998 found_entry = true; 8999 break; 9000 } 9001 } 9002 if (nexthdr) { 9003 if (nexthdr->off == cls->knode.sel->keys[i].off && 9004 nexthdr->val == cls->knode.sel->keys[i].val && 9005 nexthdr->mask == cls->knode.sel->keys[i].mask) 9006 found_jump_field = true; 9007 else 9008 continue; 9009 } 9010 } 9011 9012 if (nexthdr && !found_jump_field) 9013 return -EINVAL; 9014 9015 if (!found_entry) 9016 return 0; 9017 9018 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9019 IXGBE_ATR_L4TYPE_MASK; 9020 9021 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9022 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9023 9024 return 0; 9025 } 9026 9027 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9028 __be16 protocol, 9029 struct tc_cls_u32_offload *cls) 9030 { 9031 u32 loc = cls->knode.handle & 0xfffff; 9032 struct ixgbe_hw *hw = &adapter->hw; 9033 struct ixgbe_mat_field *field_ptr; 9034 struct ixgbe_fdir_filter *input = NULL; 9035 union ixgbe_atr_input *mask = NULL; 9036 struct ixgbe_jump_table *jump = NULL; 9037 int i, err = -EINVAL; 9038 u8 queue; 9039 u32 uhtid, link_uhtid; 9040 9041 uhtid = TC_U32_USERHTID(cls->knode.handle); 9042 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9043 9044 /* At the moment cls_u32 jumps to network layer and skips past 9045 * L2 headers. The canonical method to match L2 frames is to use 9046 * negative values. However this is error prone at best but really 9047 * just broken because there is no way to "know" what sort of hdr 9048 * is in front of the network layer. Fix cls_u32 to support L2 9049 * headers when needed. 9050 */ 9051 if (protocol != htons(ETH_P_IP)) 9052 return err; 9053 9054 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9055 e_err(drv, "Location out of range\n"); 9056 return err; 9057 } 9058 9059 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9060 * links and also the fields used to advance the parser across each 9061 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9062 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9063 * To add support for new nodes update ixgbe_model.h parse structures 9064 * this function _should_ be generic try not to hardcode values here. 9065 */ 9066 if (uhtid == 0x800) { 9067 field_ptr = (adapter->jump_tables[0])->mat; 9068 } else { 9069 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9070 return err; 9071 if (!adapter->jump_tables[uhtid]) 9072 return err; 9073 field_ptr = (adapter->jump_tables[uhtid])->mat; 9074 } 9075 9076 if (!field_ptr) 9077 return err; 9078 9079 /* At this point we know the field_ptr is valid and need to either 9080 * build cls_u32 link or attach filter. Because adding a link to 9081 * a handle that does not exist is invalid and the same for adding 9082 * rules to handles that don't exist. 9083 */ 9084 9085 if (link_uhtid) { 9086 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9087 9088 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9089 return err; 9090 9091 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9092 return err; 9093 9094 /* Multiple filters as links to the same hash table are not 9095 * supported. To add a new filter with the same next header 9096 * but different match/jump conditions, create a new hash table 9097 * and link to it. 9098 */ 9099 if (adapter->jump_tables[link_uhtid] && 9100 (adapter->jump_tables[link_uhtid])->link_hdl) { 9101 e_err(drv, "Link filter exists for link: %x\n", 9102 link_uhtid); 9103 return err; 9104 } 9105 9106 for (i = 0; nexthdr[i].jump; i++) { 9107 if (nexthdr[i].o != cls->knode.sel->offoff || 9108 nexthdr[i].s != cls->knode.sel->offshift || 9109 nexthdr[i].m != cls->knode.sel->offmask) 9110 return err; 9111 9112 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9113 if (!jump) 9114 return -ENOMEM; 9115 input = kzalloc(sizeof(*input), GFP_KERNEL); 9116 if (!input) { 9117 err = -ENOMEM; 9118 goto free_jump; 9119 } 9120 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9121 if (!mask) { 9122 err = -ENOMEM; 9123 goto free_input; 9124 } 9125 jump->input = input; 9126 jump->mask = mask; 9127 jump->link_hdl = cls->knode.handle; 9128 9129 err = ixgbe_clsu32_build_input(input, mask, cls, 9130 field_ptr, &nexthdr[i]); 9131 if (!err) { 9132 jump->mat = nexthdr[i].jump; 9133 adapter->jump_tables[link_uhtid] = jump; 9134 break; 9135 } 9136 } 9137 return 0; 9138 } 9139 9140 input = kzalloc(sizeof(*input), GFP_KERNEL); 9141 if (!input) 9142 return -ENOMEM; 9143 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9144 if (!mask) { 9145 err = -ENOMEM; 9146 goto free_input; 9147 } 9148 9149 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9150 if ((adapter->jump_tables[uhtid])->input) 9151 memcpy(input, (adapter->jump_tables[uhtid])->input, 9152 sizeof(*input)); 9153 if ((adapter->jump_tables[uhtid])->mask) 9154 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9155 sizeof(*mask)); 9156 9157 /* Lookup in all child hash tables if this location is already 9158 * filled with a filter 9159 */ 9160 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9161 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9162 9163 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9164 e_err(drv, "Filter exists in location: %x\n", 9165 loc); 9166 err = -EINVAL; 9167 goto err_out; 9168 } 9169 } 9170 } 9171 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9172 if (err) 9173 goto err_out; 9174 9175 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9176 &queue); 9177 if (err < 0) 9178 goto err_out; 9179 9180 input->sw_idx = loc; 9181 9182 spin_lock(&adapter->fdir_perfect_lock); 9183 9184 if (hlist_empty(&adapter->fdir_filter_list)) { 9185 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9186 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9187 if (err) 9188 goto err_out_w_lock; 9189 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9190 err = -EINVAL; 9191 goto err_out_w_lock; 9192 } 9193 9194 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9195 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9196 input->sw_idx, queue); 9197 if (!err) 9198 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9199 spin_unlock(&adapter->fdir_perfect_lock); 9200 9201 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9202 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9203 9204 kfree(mask); 9205 return err; 9206 err_out_w_lock: 9207 spin_unlock(&adapter->fdir_perfect_lock); 9208 err_out: 9209 kfree(mask); 9210 free_input: 9211 kfree(input); 9212 free_jump: 9213 kfree(jump); 9214 return err; 9215 } 9216 9217 static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, u32 chain_index, 9218 __be16 proto, struct tc_to_netdev *tc) 9219 { 9220 struct ixgbe_adapter *adapter = netdev_priv(dev); 9221 9222 if (chain_index) 9223 return -EOPNOTSUPP; 9224 9225 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) && 9226 tc->type == TC_SETUP_CLSU32) { 9227 switch (tc->cls_u32->command) { 9228 case TC_CLSU32_NEW_KNODE: 9229 case TC_CLSU32_REPLACE_KNODE: 9230 return ixgbe_configure_clsu32(adapter, 9231 proto, tc->cls_u32); 9232 case TC_CLSU32_DELETE_KNODE: 9233 return ixgbe_delete_clsu32(adapter, tc->cls_u32); 9234 case TC_CLSU32_NEW_HNODE: 9235 case TC_CLSU32_REPLACE_HNODE: 9236 return ixgbe_configure_clsu32_add_hnode(adapter, proto, 9237 tc->cls_u32); 9238 case TC_CLSU32_DELETE_HNODE: 9239 return ixgbe_configure_clsu32_del_hnode(adapter, 9240 tc->cls_u32); 9241 default: 9242 return -EINVAL; 9243 } 9244 } 9245 9246 if (tc->type != TC_SETUP_MQPRIO) 9247 return -EINVAL; 9248 9249 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9250 9251 return ixgbe_setup_tc(dev, tc->mqprio->num_tc); 9252 } 9253 9254 #ifdef CONFIG_PCI_IOV 9255 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9256 { 9257 struct net_device *netdev = adapter->netdev; 9258 9259 rtnl_lock(); 9260 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 9261 rtnl_unlock(); 9262 } 9263 9264 #endif 9265 void ixgbe_do_reset(struct net_device *netdev) 9266 { 9267 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9268 9269 if (netif_running(netdev)) 9270 ixgbe_reinit_locked(adapter); 9271 else 9272 ixgbe_reset(adapter); 9273 } 9274 9275 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9276 netdev_features_t features) 9277 { 9278 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9279 9280 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9281 if (!(features & NETIF_F_RXCSUM)) 9282 features &= ~NETIF_F_LRO; 9283 9284 /* Turn off LRO if not RSC capable */ 9285 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9286 features &= ~NETIF_F_LRO; 9287 9288 return features; 9289 } 9290 9291 static int ixgbe_set_features(struct net_device *netdev, 9292 netdev_features_t features) 9293 { 9294 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9295 netdev_features_t changed = netdev->features ^ features; 9296 bool need_reset = false; 9297 9298 /* Make sure RSC matches LRO, reset if change */ 9299 if (!(features & NETIF_F_LRO)) { 9300 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9301 need_reset = true; 9302 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9303 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9304 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9305 if (adapter->rx_itr_setting == 1 || 9306 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9307 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9308 need_reset = true; 9309 } else if ((changed ^ features) & NETIF_F_LRO) { 9310 e_info(probe, "rx-usecs set too low, " 9311 "disabling RSC\n"); 9312 } 9313 } 9314 9315 /* 9316 * Check if Flow Director n-tuple support or hw_tc support was 9317 * enabled or disabled. If the state changed, we need to reset. 9318 */ 9319 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9320 /* turn off ATR, enable perfect filters and reset */ 9321 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9322 need_reset = true; 9323 9324 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9325 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9326 } else { 9327 /* turn off perfect filters, enable ATR and reset */ 9328 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9329 need_reset = true; 9330 9331 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9332 9333 /* We cannot enable ATR if SR-IOV is enabled */ 9334 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9335 /* We cannot enable ATR if we have 2 or more tcs */ 9336 (netdev_get_num_tc(netdev) > 1) || 9337 /* We cannot enable ATR if RSS is disabled */ 9338 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9339 /* A sample rate of 0 indicates ATR disabled */ 9340 (!adapter->atr_sample_rate)) 9341 ; /* do nothing not supported */ 9342 else /* otherwise supported and set the flag */ 9343 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9344 } 9345 9346 if (changed & NETIF_F_RXALL) 9347 need_reset = true; 9348 9349 netdev->features = features; 9350 9351 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9352 if (features & NETIF_F_RXCSUM) { 9353 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9354 } else { 9355 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9356 9357 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9358 } 9359 } 9360 9361 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9362 if (features & NETIF_F_RXCSUM) { 9363 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9364 } else { 9365 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9366 9367 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9368 } 9369 } 9370 9371 if (need_reset) 9372 ixgbe_do_reset(netdev); 9373 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9374 NETIF_F_HW_VLAN_CTAG_FILTER)) 9375 ixgbe_set_rx_mode(netdev); 9376 9377 return 0; 9378 } 9379 9380 /** 9381 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9382 * @dev: The port's netdev 9383 * @ti: Tunnel endpoint information 9384 **/ 9385 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9386 struct udp_tunnel_info *ti) 9387 { 9388 struct ixgbe_adapter *adapter = netdev_priv(dev); 9389 struct ixgbe_hw *hw = &adapter->hw; 9390 __be16 port = ti->port; 9391 u32 port_shift = 0; 9392 u32 reg; 9393 9394 if (ti->sa_family != AF_INET) 9395 return; 9396 9397 switch (ti->type) { 9398 case UDP_TUNNEL_TYPE_VXLAN: 9399 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9400 return; 9401 9402 if (adapter->vxlan_port == port) 9403 return; 9404 9405 if (adapter->vxlan_port) { 9406 netdev_info(dev, 9407 "VXLAN port %d set, not adding port %d\n", 9408 ntohs(adapter->vxlan_port), 9409 ntohs(port)); 9410 return; 9411 } 9412 9413 adapter->vxlan_port = port; 9414 break; 9415 case UDP_TUNNEL_TYPE_GENEVE: 9416 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9417 return; 9418 9419 if (adapter->geneve_port == port) 9420 return; 9421 9422 if (adapter->geneve_port) { 9423 netdev_info(dev, 9424 "GENEVE port %d set, not adding port %d\n", 9425 ntohs(adapter->geneve_port), 9426 ntohs(port)); 9427 return; 9428 } 9429 9430 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9431 adapter->geneve_port = port; 9432 break; 9433 default: 9434 return; 9435 } 9436 9437 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9438 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9439 } 9440 9441 /** 9442 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9443 * @dev: The port's netdev 9444 * @ti: Tunnel endpoint information 9445 **/ 9446 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9447 struct udp_tunnel_info *ti) 9448 { 9449 struct ixgbe_adapter *adapter = netdev_priv(dev); 9450 u32 port_mask; 9451 9452 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9453 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9454 return; 9455 9456 if (ti->sa_family != AF_INET) 9457 return; 9458 9459 switch (ti->type) { 9460 case UDP_TUNNEL_TYPE_VXLAN: 9461 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9462 return; 9463 9464 if (adapter->vxlan_port != ti->port) { 9465 netdev_info(dev, "VXLAN port %d not found\n", 9466 ntohs(ti->port)); 9467 return; 9468 } 9469 9470 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9471 break; 9472 case UDP_TUNNEL_TYPE_GENEVE: 9473 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9474 return; 9475 9476 if (adapter->geneve_port != ti->port) { 9477 netdev_info(dev, "GENEVE port %d not found\n", 9478 ntohs(ti->port)); 9479 return; 9480 } 9481 9482 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9483 break; 9484 default: 9485 return; 9486 } 9487 9488 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9489 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9490 } 9491 9492 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9493 struct net_device *dev, 9494 const unsigned char *addr, u16 vid, 9495 u16 flags) 9496 { 9497 /* guarantee we can provide a unique filter for the unicast address */ 9498 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9499 struct ixgbe_adapter *adapter = netdev_priv(dev); 9500 u16 pool = VMDQ_P(0); 9501 9502 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9503 return -ENOMEM; 9504 } 9505 9506 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9507 } 9508 9509 /** 9510 * ixgbe_configure_bridge_mode - set various bridge modes 9511 * @adapter - the private structure 9512 * @mode - requested bridge mode 9513 * 9514 * Configure some settings require for various bridge modes. 9515 **/ 9516 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9517 __u16 mode) 9518 { 9519 struct ixgbe_hw *hw = &adapter->hw; 9520 unsigned int p, num_pools; 9521 u32 vmdctl; 9522 9523 switch (mode) { 9524 case BRIDGE_MODE_VEPA: 9525 /* disable Tx loopback, rely on switch hairpin mode */ 9526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9527 9528 /* must enable Rx switching replication to allow multicast 9529 * packet reception on all VFs, and to enable source address 9530 * pruning. 9531 */ 9532 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9533 vmdctl |= IXGBE_VT_CTL_REPLEN; 9534 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9535 9536 /* enable Rx source address pruning. Note, this requires 9537 * replication to be enabled or else it does nothing. 9538 */ 9539 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9540 for (p = 0; p < num_pools; p++) { 9541 if (hw->mac.ops.set_source_address_pruning) 9542 hw->mac.ops.set_source_address_pruning(hw, 9543 true, 9544 p); 9545 } 9546 break; 9547 case BRIDGE_MODE_VEB: 9548 /* enable Tx loopback for internal VF/PF communication */ 9549 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9550 IXGBE_PFDTXGSWC_VT_LBEN); 9551 9552 /* disable Rx switching replication unless we have SR-IOV 9553 * virtual functions 9554 */ 9555 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9556 if (!adapter->num_vfs) 9557 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9558 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9559 9560 /* disable Rx source address pruning, since we don't expect to 9561 * be receiving external loopback of our transmitted frames. 9562 */ 9563 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9564 for (p = 0; p < num_pools; p++) { 9565 if (hw->mac.ops.set_source_address_pruning) 9566 hw->mac.ops.set_source_address_pruning(hw, 9567 false, 9568 p); 9569 } 9570 break; 9571 default: 9572 return -EINVAL; 9573 } 9574 9575 adapter->bridge_mode = mode; 9576 9577 e_info(drv, "enabling bridge mode: %s\n", 9578 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9579 9580 return 0; 9581 } 9582 9583 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9584 struct nlmsghdr *nlh, u16 flags) 9585 { 9586 struct ixgbe_adapter *adapter = netdev_priv(dev); 9587 struct nlattr *attr, *br_spec; 9588 int rem; 9589 9590 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9591 return -EOPNOTSUPP; 9592 9593 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9594 if (!br_spec) 9595 return -EINVAL; 9596 9597 nla_for_each_nested(attr, br_spec, rem) { 9598 int status; 9599 __u16 mode; 9600 9601 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9602 continue; 9603 9604 if (nla_len(attr) < sizeof(mode)) 9605 return -EINVAL; 9606 9607 mode = nla_get_u16(attr); 9608 status = ixgbe_configure_bridge_mode(adapter, mode); 9609 if (status) 9610 return status; 9611 9612 break; 9613 } 9614 9615 return 0; 9616 } 9617 9618 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9619 struct net_device *dev, 9620 u32 filter_mask, int nlflags) 9621 { 9622 struct ixgbe_adapter *adapter = netdev_priv(dev); 9623 9624 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9625 return 0; 9626 9627 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9628 adapter->bridge_mode, 0, 0, nlflags, 9629 filter_mask, NULL); 9630 } 9631 9632 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9633 { 9634 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 9635 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9636 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 9637 unsigned int limit; 9638 int pool, err; 9639 9640 /* Hardware has a limited number of available pools. Each VF, and the 9641 * PF require a pool. Check to ensure we don't attempt to use more 9642 * then the available number of pools. 9643 */ 9644 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9645 return ERR_PTR(-EINVAL); 9646 9647 #ifdef CONFIG_RPS 9648 if (vdev->num_rx_queues != vdev->num_tx_queues) { 9649 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 9650 vdev->name); 9651 return ERR_PTR(-EINVAL); 9652 } 9653 #endif 9654 /* Check for hardware restriction on number of rx/tx queues */ 9655 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 9656 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 9657 netdev_info(pdev, 9658 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 9659 pdev->name); 9660 return ERR_PTR(-EINVAL); 9661 } 9662 9663 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9664 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 9665 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 9666 return ERR_PTR(-EBUSY); 9667 9668 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 9669 if (!fwd_adapter) 9670 return ERR_PTR(-ENOMEM); 9671 9672 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 9673 adapter->num_rx_pools++; 9674 set_bit(pool, &adapter->fwd_bitmask); 9675 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9676 9677 /* Enable VMDq flag so device will be set in VM mode */ 9678 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 9679 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9680 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 9681 9682 /* Force reinit of ring allocation with VMDQ enabled */ 9683 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9684 if (err) 9685 goto fwd_add_err; 9686 fwd_adapter->pool = pool; 9687 fwd_adapter->real_adapter = adapter; 9688 9689 if (netif_running(pdev)) { 9690 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 9691 if (err) 9692 goto fwd_add_err; 9693 netif_tx_start_all_queues(vdev); 9694 } 9695 9696 return fwd_adapter; 9697 fwd_add_err: 9698 /* unwind counter and free adapter struct */ 9699 netdev_info(pdev, 9700 "%s: dfwd hardware acceleration failed\n", vdev->name); 9701 clear_bit(pool, &adapter->fwd_bitmask); 9702 adapter->num_rx_pools--; 9703 kfree(fwd_adapter); 9704 return ERR_PTR(err); 9705 } 9706 9707 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9708 { 9709 struct ixgbe_fwd_adapter *fwd_adapter = priv; 9710 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 9711 unsigned int limit; 9712 9713 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 9714 adapter->num_rx_pools--; 9715 9716 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9717 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9718 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 9719 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9720 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 9721 fwd_adapter->pool, adapter->num_rx_pools, 9722 fwd_adapter->rx_base_queue, 9723 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 9724 adapter->fwd_bitmask); 9725 kfree(fwd_adapter); 9726 } 9727 9728 #define IXGBE_MAX_MAC_HDR_LEN 127 9729 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9730 9731 static netdev_features_t 9732 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9733 netdev_features_t features) 9734 { 9735 unsigned int network_hdr_len, mac_hdr_len; 9736 9737 /* Make certain the headers can be described by a context descriptor */ 9738 mac_hdr_len = skb_network_header(skb) - skb->data; 9739 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9740 return features & ~(NETIF_F_HW_CSUM | 9741 NETIF_F_SCTP_CRC | 9742 NETIF_F_HW_VLAN_CTAG_TX | 9743 NETIF_F_TSO | 9744 NETIF_F_TSO6); 9745 9746 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9747 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9748 return features & ~(NETIF_F_HW_CSUM | 9749 NETIF_F_SCTP_CRC | 9750 NETIF_F_TSO | 9751 NETIF_F_TSO6); 9752 9753 /* We can only support IPV4 TSO in tunnels if we can mangle the 9754 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9755 */ 9756 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 9757 features &= ~NETIF_F_TSO; 9758 9759 return features; 9760 } 9761 9762 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9763 { 9764 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9765 struct ixgbe_adapter *adapter = netdev_priv(dev); 9766 struct bpf_prog *old_prog; 9767 9768 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9769 return -EINVAL; 9770 9771 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9772 return -EINVAL; 9773 9774 /* verify ixgbe ring attributes are sufficient for XDP */ 9775 for (i = 0; i < adapter->num_rx_queues; i++) { 9776 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9777 9778 if (ring_is_rsc_enabled(ring)) 9779 return -EINVAL; 9780 9781 if (frame_size > ixgbe_rx_bufsz(ring)) 9782 return -EINVAL; 9783 } 9784 9785 if (nr_cpu_ids > MAX_XDP_QUEUES) 9786 return -ENOMEM; 9787 9788 old_prog = xchg(&adapter->xdp_prog, prog); 9789 9790 /* If transitioning XDP modes reconfigure rings */ 9791 if (!!prog != !!old_prog) { 9792 int err = ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 9793 9794 if (err) { 9795 rcu_assign_pointer(adapter->xdp_prog, old_prog); 9796 return -EINVAL; 9797 } 9798 } else { 9799 for (i = 0; i < adapter->num_rx_queues; i++) 9800 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); 9801 } 9802 9803 if (old_prog) 9804 bpf_prog_put(old_prog); 9805 9806 return 0; 9807 } 9808 9809 static int ixgbe_xdp(struct net_device *dev, struct netdev_xdp *xdp) 9810 { 9811 struct ixgbe_adapter *adapter = netdev_priv(dev); 9812 9813 switch (xdp->command) { 9814 case XDP_SETUP_PROG: 9815 return ixgbe_xdp_setup(dev, xdp->prog); 9816 case XDP_QUERY_PROG: 9817 xdp->prog_attached = !!(adapter->xdp_prog); 9818 xdp->prog_id = adapter->xdp_prog ? 9819 adapter->xdp_prog->aux->id : 0; 9820 return 0; 9821 default: 9822 return -EINVAL; 9823 } 9824 } 9825 9826 static const struct net_device_ops ixgbe_netdev_ops = { 9827 .ndo_open = ixgbe_open, 9828 .ndo_stop = ixgbe_close, 9829 .ndo_start_xmit = ixgbe_xmit_frame, 9830 .ndo_select_queue = ixgbe_select_queue, 9831 .ndo_set_rx_mode = ixgbe_set_rx_mode, 9832 .ndo_validate_addr = eth_validate_addr, 9833 .ndo_set_mac_address = ixgbe_set_mac, 9834 .ndo_change_mtu = ixgbe_change_mtu, 9835 .ndo_tx_timeout = ixgbe_tx_timeout, 9836 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 9837 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 9838 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 9839 .ndo_do_ioctl = ixgbe_ioctl, 9840 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 9841 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 9842 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 9843 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 9844 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 9845 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 9846 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 9847 .ndo_get_stats64 = ixgbe_get_stats64, 9848 .ndo_setup_tc = __ixgbe_setup_tc, 9849 #ifdef CONFIG_NET_POLL_CONTROLLER 9850 .ndo_poll_controller = ixgbe_netpoll, 9851 #endif 9852 #ifdef IXGBE_FCOE 9853 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 9854 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 9855 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 9856 .ndo_fcoe_enable = ixgbe_fcoe_enable, 9857 .ndo_fcoe_disable = ixgbe_fcoe_disable, 9858 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 9859 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 9860 #endif /* IXGBE_FCOE */ 9861 .ndo_set_features = ixgbe_set_features, 9862 .ndo_fix_features = ixgbe_fix_features, 9863 .ndo_fdb_add = ixgbe_ndo_fdb_add, 9864 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 9865 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 9866 .ndo_dfwd_add_station = ixgbe_fwd_add, 9867 .ndo_dfwd_del_station = ixgbe_fwd_del, 9868 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 9869 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 9870 .ndo_features_check = ixgbe_features_check, 9871 .ndo_xdp = ixgbe_xdp, 9872 }; 9873 9874 /** 9875 * ixgbe_enumerate_functions - Get the number of ports this device has 9876 * @adapter: adapter structure 9877 * 9878 * This function enumerates the phsyical functions co-located on a single slot, 9879 * in order to determine how many ports a device has. This is most useful in 9880 * determining the required GT/s of PCIe bandwidth necessary for optimal 9881 * performance. 9882 **/ 9883 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 9884 { 9885 struct pci_dev *entry, *pdev = adapter->pdev; 9886 int physfns = 0; 9887 9888 /* Some cards can not use the generic count PCIe functions method, 9889 * because they are behind a parent switch, so we hardcode these with 9890 * the correct number of functions. 9891 */ 9892 if (ixgbe_pcie_from_parent(&adapter->hw)) 9893 physfns = 4; 9894 9895 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 9896 /* don't count virtual functions */ 9897 if (entry->is_virtfn) 9898 continue; 9899 9900 /* When the devices on the bus don't all match our device ID, 9901 * we can't reliably determine the correct number of 9902 * functions. This can occur if a function has been direct 9903 * attached to a virtual machine using VT-d, for example. In 9904 * this case, simply return -1 to indicate this. 9905 */ 9906 if ((entry->vendor != pdev->vendor) || 9907 (entry->device != pdev->device)) 9908 return -1; 9909 9910 physfns++; 9911 } 9912 9913 return physfns; 9914 } 9915 9916 /** 9917 * ixgbe_wol_supported - Check whether device supports WoL 9918 * @adapter: the adapter private structure 9919 * @device_id: the device ID 9920 * @subdev_id: the subsystem device ID 9921 * 9922 * This function is used by probe and ethtool to determine 9923 * which devices have WoL support 9924 * 9925 **/ 9926 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 9927 u16 subdevice_id) 9928 { 9929 struct ixgbe_hw *hw = &adapter->hw; 9930 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 9931 9932 /* WOL not supported on 82598 */ 9933 if (hw->mac.type == ixgbe_mac_82598EB) 9934 return false; 9935 9936 /* check eeprom to see if WOL is enabled for X540 and newer */ 9937 if (hw->mac.type >= ixgbe_mac_X540) { 9938 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 9939 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 9940 (hw->bus.func == 0))) 9941 return true; 9942 } 9943 9944 /* WOL is determined based on device IDs for 82599 MACs */ 9945 switch (device_id) { 9946 case IXGBE_DEV_ID_82599_SFP: 9947 /* Only these subdevices could supports WOL */ 9948 switch (subdevice_id) { 9949 case IXGBE_SUBDEV_ID_82599_560FLR: 9950 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 9951 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 9952 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 9953 /* only support first port */ 9954 if (hw->bus.func != 0) 9955 break; 9956 /* fall through */ 9957 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 9958 case IXGBE_SUBDEV_ID_82599_SFP: 9959 case IXGBE_SUBDEV_ID_82599_RNDC: 9960 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 9961 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 9962 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 9963 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 9964 return true; 9965 } 9966 break; 9967 case IXGBE_DEV_ID_82599EN_SFP: 9968 /* Only these subdevices support WOL */ 9969 switch (subdevice_id) { 9970 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 9971 return true; 9972 } 9973 break; 9974 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 9975 /* All except this subdevice support WOL */ 9976 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 9977 return true; 9978 break; 9979 case IXGBE_DEV_ID_82599_KX4: 9980 return true; 9981 default: 9982 break; 9983 } 9984 9985 return false; 9986 } 9987 9988 /** 9989 * ixgbe_probe - Device Initialization Routine 9990 * @pdev: PCI device information struct 9991 * @ent: entry in ixgbe_pci_tbl 9992 * 9993 * Returns 0 on success, negative on failure 9994 * 9995 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 9996 * The OS initialization, configuring of the adapter private structure, 9997 * and a hardware reset occur. 9998 **/ 9999 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10000 { 10001 struct net_device *netdev; 10002 struct ixgbe_adapter *adapter = NULL; 10003 struct ixgbe_hw *hw; 10004 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10005 int i, err, pci_using_dac, expected_gts; 10006 unsigned int indices = MAX_TX_QUEUES; 10007 u8 part_str[IXGBE_PBANUM_LENGTH]; 10008 bool disable_dev = false; 10009 #ifdef IXGBE_FCOE 10010 u16 device_caps; 10011 #endif 10012 u32 eec; 10013 10014 /* Catch broken hardware that put the wrong VF device ID in 10015 * the PCIe SR-IOV capability. 10016 */ 10017 if (pdev->is_virtfn) { 10018 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10019 pci_name(pdev), pdev->vendor, pdev->device); 10020 return -EINVAL; 10021 } 10022 10023 err = pci_enable_device_mem(pdev); 10024 if (err) 10025 return err; 10026 10027 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10028 pci_using_dac = 1; 10029 } else { 10030 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10031 if (err) { 10032 dev_err(&pdev->dev, 10033 "No usable DMA configuration, aborting\n"); 10034 goto err_dma; 10035 } 10036 pci_using_dac = 0; 10037 } 10038 10039 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10040 if (err) { 10041 dev_err(&pdev->dev, 10042 "pci_request_selected_regions failed 0x%x\n", err); 10043 goto err_pci_reg; 10044 } 10045 10046 pci_enable_pcie_error_reporting(pdev); 10047 10048 pci_set_master(pdev); 10049 pci_save_state(pdev); 10050 10051 if (ii->mac == ixgbe_mac_82598EB) { 10052 #ifdef CONFIG_IXGBE_DCB 10053 /* 8 TC w/ 4 queues per TC */ 10054 indices = 4 * MAX_TRAFFIC_CLASS; 10055 #else 10056 indices = IXGBE_MAX_RSS_INDICES; 10057 #endif 10058 } 10059 10060 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10061 if (!netdev) { 10062 err = -ENOMEM; 10063 goto err_alloc_etherdev; 10064 } 10065 10066 SET_NETDEV_DEV(netdev, &pdev->dev); 10067 10068 adapter = netdev_priv(netdev); 10069 10070 adapter->netdev = netdev; 10071 adapter->pdev = pdev; 10072 hw = &adapter->hw; 10073 hw->back = adapter; 10074 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10075 10076 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10077 pci_resource_len(pdev, 0)); 10078 adapter->io_addr = hw->hw_addr; 10079 if (!hw->hw_addr) { 10080 err = -EIO; 10081 goto err_ioremap; 10082 } 10083 10084 netdev->netdev_ops = &ixgbe_netdev_ops; 10085 ixgbe_set_ethtool_ops(netdev); 10086 netdev->watchdog_timeo = 5 * HZ; 10087 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10088 10089 /* Setup hw api */ 10090 hw->mac.ops = *ii->mac_ops; 10091 hw->mac.type = ii->mac; 10092 hw->mvals = ii->mvals; 10093 if (ii->link_ops) 10094 hw->link.ops = *ii->link_ops; 10095 10096 /* EEPROM */ 10097 hw->eeprom.ops = *ii->eeprom_ops; 10098 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10099 if (ixgbe_removed(hw->hw_addr)) { 10100 err = -EIO; 10101 goto err_ioremap; 10102 } 10103 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10104 if (!(eec & BIT(8))) 10105 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10106 10107 /* PHY */ 10108 hw->phy.ops = *ii->phy_ops; 10109 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10110 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10111 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10112 hw->phy.mdio.mmds = 0; 10113 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10114 hw->phy.mdio.dev = netdev; 10115 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10116 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10117 10118 /* setup the private structure */ 10119 err = ixgbe_sw_init(adapter, ii); 10120 if (err) 10121 goto err_sw_init; 10122 10123 /* Make sure the SWFW semaphore is in a valid state */ 10124 if (hw->mac.ops.init_swfw_sync) 10125 hw->mac.ops.init_swfw_sync(hw); 10126 10127 /* Make it possible the adapter to be woken up via WOL */ 10128 switch (adapter->hw.mac.type) { 10129 case ixgbe_mac_82599EB: 10130 case ixgbe_mac_X540: 10131 case ixgbe_mac_X550: 10132 case ixgbe_mac_X550EM_x: 10133 case ixgbe_mac_x550em_a: 10134 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10135 break; 10136 default: 10137 break; 10138 } 10139 10140 /* 10141 * If there is a fan on this device and it has failed log the 10142 * failure. 10143 */ 10144 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10145 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10146 if (esdp & IXGBE_ESDP_SDP1) 10147 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10148 } 10149 10150 if (allow_unsupported_sfp) 10151 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10152 10153 /* reset_hw fills in the perm_addr as well */ 10154 hw->phy.reset_if_overtemp = true; 10155 err = hw->mac.ops.reset_hw(hw); 10156 hw->phy.reset_if_overtemp = false; 10157 ixgbe_set_eee_capable(adapter); 10158 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10159 err = 0; 10160 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10161 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10162 e_dev_err("Reload the driver after installing a supported module.\n"); 10163 goto err_sw_init; 10164 } else if (err) { 10165 e_dev_err("HW Init failed: %d\n", err); 10166 goto err_sw_init; 10167 } 10168 10169 #ifdef CONFIG_PCI_IOV 10170 /* SR-IOV not supported on the 82598 */ 10171 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10172 goto skip_sriov; 10173 /* Mailbox */ 10174 ixgbe_init_mbx_params_pf(hw); 10175 hw->mbx.ops = ii->mbx_ops; 10176 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10177 ixgbe_enable_sriov(adapter, max_vfs); 10178 skip_sriov: 10179 10180 #endif 10181 netdev->features = NETIF_F_SG | 10182 NETIF_F_TSO | 10183 NETIF_F_TSO6 | 10184 NETIF_F_RXHASH | 10185 NETIF_F_RXCSUM | 10186 NETIF_F_HW_CSUM; 10187 10188 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10189 NETIF_F_GSO_GRE_CSUM | \ 10190 NETIF_F_GSO_IPXIP4 | \ 10191 NETIF_F_GSO_IPXIP6 | \ 10192 NETIF_F_GSO_UDP_TUNNEL | \ 10193 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10194 10195 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10196 netdev->features |= NETIF_F_GSO_PARTIAL | 10197 IXGBE_GSO_PARTIAL_FEATURES; 10198 10199 if (hw->mac.type >= ixgbe_mac_82599EB) 10200 netdev->features |= NETIF_F_SCTP_CRC; 10201 10202 /* copy netdev features into list of user selectable features */ 10203 netdev->hw_features |= netdev->features | 10204 NETIF_F_HW_VLAN_CTAG_FILTER | 10205 NETIF_F_HW_VLAN_CTAG_RX | 10206 NETIF_F_HW_VLAN_CTAG_TX | 10207 NETIF_F_RXALL | 10208 NETIF_F_HW_L2FW_DOFFLOAD; 10209 10210 if (hw->mac.type >= ixgbe_mac_82599EB) 10211 netdev->hw_features |= NETIF_F_NTUPLE | 10212 NETIF_F_HW_TC; 10213 10214 if (pci_using_dac) 10215 netdev->features |= NETIF_F_HIGHDMA; 10216 10217 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10218 netdev->hw_enc_features |= netdev->vlan_features; 10219 netdev->mpls_features |= NETIF_F_SG | 10220 NETIF_F_TSO | 10221 NETIF_F_TSO6 | 10222 NETIF_F_HW_CSUM; 10223 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10224 10225 /* set this bit last since it cannot be part of vlan_features */ 10226 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10227 NETIF_F_HW_VLAN_CTAG_RX | 10228 NETIF_F_HW_VLAN_CTAG_TX; 10229 10230 netdev->priv_flags |= IFF_UNICAST_FLT; 10231 netdev->priv_flags |= IFF_SUPP_NOFCS; 10232 10233 /* MTU range: 68 - 9710 */ 10234 netdev->min_mtu = ETH_MIN_MTU; 10235 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10236 10237 #ifdef CONFIG_IXGBE_DCB 10238 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10239 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10240 #endif 10241 10242 #ifdef IXGBE_FCOE 10243 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10244 unsigned int fcoe_l; 10245 10246 if (hw->mac.ops.get_device_caps) { 10247 hw->mac.ops.get_device_caps(hw, &device_caps); 10248 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10249 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10250 } 10251 10252 10253 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10254 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10255 10256 netdev->features |= NETIF_F_FSO | 10257 NETIF_F_FCOE_CRC; 10258 10259 netdev->vlan_features |= NETIF_F_FSO | 10260 NETIF_F_FCOE_CRC | 10261 NETIF_F_FCOE_MTU; 10262 } 10263 #endif /* IXGBE_FCOE */ 10264 10265 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10266 netdev->hw_features |= NETIF_F_LRO; 10267 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10268 netdev->features |= NETIF_F_LRO; 10269 10270 /* make sure the EEPROM is good */ 10271 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10272 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10273 err = -EIO; 10274 goto err_sw_init; 10275 } 10276 10277 eth_platform_get_mac_address(&adapter->pdev->dev, 10278 adapter->hw.mac.perm_addr); 10279 10280 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10281 10282 if (!is_valid_ether_addr(netdev->dev_addr)) { 10283 e_dev_err("invalid MAC address\n"); 10284 err = -EIO; 10285 goto err_sw_init; 10286 } 10287 10288 /* Set hw->mac.addr to permanent MAC address */ 10289 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10290 ixgbe_mac_set_default_filter(adapter); 10291 10292 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 10293 (unsigned long) adapter); 10294 10295 if (ixgbe_removed(hw->hw_addr)) { 10296 err = -EIO; 10297 goto err_sw_init; 10298 } 10299 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10300 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10301 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10302 10303 err = ixgbe_init_interrupt_scheme(adapter); 10304 if (err) 10305 goto err_sw_init; 10306 10307 for (i = 0; i < adapter->num_rx_queues; i++) 10308 u64_stats_init(&adapter->rx_ring[i]->syncp); 10309 for (i = 0; i < adapter->num_tx_queues; i++) 10310 u64_stats_init(&adapter->tx_ring[i]->syncp); 10311 for (i = 0; i < adapter->num_xdp_queues; i++) 10312 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10313 10314 /* WOL not supported for all devices */ 10315 adapter->wol = 0; 10316 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10317 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10318 pdev->subsystem_device); 10319 if (hw->wol_enabled) 10320 adapter->wol = IXGBE_WUFC_MAG; 10321 10322 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10323 10324 /* save off EEPROM version number */ 10325 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 10326 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 10327 10328 /* pick up the PCI bus settings for reporting later */ 10329 if (ixgbe_pcie_from_parent(hw)) 10330 ixgbe_get_parent_bus_info(adapter); 10331 else 10332 hw->mac.ops.get_bus_info(hw); 10333 10334 /* calculate the expected PCIe bandwidth required for optimal 10335 * performance. Note that some older parts will never have enough 10336 * bandwidth due to being older generation PCIe parts. We clamp these 10337 * parts to ensure no warning is displayed if it can't be fixed. 10338 */ 10339 switch (hw->mac.type) { 10340 case ixgbe_mac_82598EB: 10341 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10342 break; 10343 default: 10344 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10345 break; 10346 } 10347 10348 /* don't check link if we failed to enumerate functions */ 10349 if (expected_gts > 0) 10350 ixgbe_check_minimum_link(adapter, expected_gts); 10351 10352 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10353 if (err) 10354 strlcpy(part_str, "Unknown", sizeof(part_str)); 10355 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10356 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10357 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10358 part_str); 10359 else 10360 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10361 hw->mac.type, hw->phy.type, part_str); 10362 10363 e_dev_info("%pM\n", netdev->dev_addr); 10364 10365 /* reset the hardware with the new settings */ 10366 err = hw->mac.ops.start_hw(hw); 10367 if (err == IXGBE_ERR_EEPROM_VERSION) { 10368 /* We are running on a pre-production device, log a warning */ 10369 e_dev_warn("This device is a pre-production adapter/LOM. " 10370 "Please be aware there may be issues associated " 10371 "with your hardware. If you are experiencing " 10372 "problems please contact your Intel or hardware " 10373 "representative who provided you with this " 10374 "hardware.\n"); 10375 } 10376 strcpy(netdev->name, "eth%d"); 10377 pci_set_drvdata(pdev, adapter); 10378 err = register_netdev(netdev); 10379 if (err) 10380 goto err_register; 10381 10382 10383 /* power down the optics for 82599 SFP+ fiber */ 10384 if (hw->mac.ops.disable_tx_laser) 10385 hw->mac.ops.disable_tx_laser(hw); 10386 10387 /* carrier off reporting is important to ethtool even BEFORE open */ 10388 netif_carrier_off(netdev); 10389 10390 #ifdef CONFIG_IXGBE_DCA 10391 if (dca_add_requester(&pdev->dev) == 0) { 10392 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10393 ixgbe_setup_dca(adapter); 10394 } 10395 #endif 10396 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10397 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10398 for (i = 0; i < adapter->num_vfs; i++) 10399 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10400 } 10401 10402 /* firmware requires driver version to be 0xFFFFFFFF 10403 * since os does not support feature 10404 */ 10405 if (hw->mac.ops.set_fw_drv_ver) 10406 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10407 sizeof(ixgbe_driver_version) - 1, 10408 ixgbe_driver_version); 10409 10410 /* add san mac addr to netdev */ 10411 ixgbe_add_sanmac_netdev(netdev); 10412 10413 e_dev_info("%s\n", ixgbe_default_device_descr); 10414 10415 #ifdef CONFIG_IXGBE_HWMON 10416 if (ixgbe_sysfs_init(adapter)) 10417 e_err(probe, "failed to allocate sysfs resources\n"); 10418 #endif /* CONFIG_IXGBE_HWMON */ 10419 10420 ixgbe_dbg_adapter_init(adapter); 10421 10422 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10423 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10424 hw->mac.ops.setup_link(hw, 10425 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10426 true); 10427 10428 return 0; 10429 10430 err_register: 10431 ixgbe_release_hw_control(adapter); 10432 ixgbe_clear_interrupt_scheme(adapter); 10433 err_sw_init: 10434 ixgbe_disable_sriov(adapter); 10435 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10436 iounmap(adapter->io_addr); 10437 kfree(adapter->jump_tables[0]); 10438 kfree(adapter->mac_table); 10439 kfree(adapter->rss_key); 10440 err_ioremap: 10441 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10442 free_netdev(netdev); 10443 err_alloc_etherdev: 10444 pci_release_mem_regions(pdev); 10445 err_pci_reg: 10446 err_dma: 10447 if (!adapter || disable_dev) 10448 pci_disable_device(pdev); 10449 return err; 10450 } 10451 10452 /** 10453 * ixgbe_remove - Device Removal Routine 10454 * @pdev: PCI device information struct 10455 * 10456 * ixgbe_remove is called by the PCI subsystem to alert the driver 10457 * that it should release a PCI device. The could be caused by a 10458 * Hot-Plug event, or because the driver is going to be removed from 10459 * memory. 10460 **/ 10461 static void ixgbe_remove(struct pci_dev *pdev) 10462 { 10463 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10464 struct net_device *netdev; 10465 bool disable_dev; 10466 int i; 10467 10468 /* if !adapter then we already cleaned up in probe */ 10469 if (!adapter) 10470 return; 10471 10472 netdev = adapter->netdev; 10473 ixgbe_dbg_adapter_exit(adapter); 10474 10475 set_bit(__IXGBE_REMOVING, &adapter->state); 10476 cancel_work_sync(&adapter->service_task); 10477 10478 10479 #ifdef CONFIG_IXGBE_DCA 10480 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10481 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10482 dca_remove_requester(&pdev->dev); 10483 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10484 IXGBE_DCA_CTRL_DCA_DISABLE); 10485 } 10486 10487 #endif 10488 #ifdef CONFIG_IXGBE_HWMON 10489 ixgbe_sysfs_exit(adapter); 10490 #endif /* CONFIG_IXGBE_HWMON */ 10491 10492 /* remove the added san mac */ 10493 ixgbe_del_sanmac_netdev(netdev); 10494 10495 #ifdef CONFIG_PCI_IOV 10496 ixgbe_disable_sriov(adapter); 10497 #endif 10498 if (netdev->reg_state == NETREG_REGISTERED) 10499 unregister_netdev(netdev); 10500 10501 ixgbe_clear_interrupt_scheme(adapter); 10502 10503 ixgbe_release_hw_control(adapter); 10504 10505 #ifdef CONFIG_DCB 10506 kfree(adapter->ixgbe_ieee_pfc); 10507 kfree(adapter->ixgbe_ieee_ets); 10508 10509 #endif 10510 iounmap(adapter->io_addr); 10511 pci_release_mem_regions(pdev); 10512 10513 e_dev_info("complete\n"); 10514 10515 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10516 if (adapter->jump_tables[i]) { 10517 kfree(adapter->jump_tables[i]->input); 10518 kfree(adapter->jump_tables[i]->mask); 10519 } 10520 kfree(adapter->jump_tables[i]); 10521 } 10522 10523 kfree(adapter->mac_table); 10524 kfree(adapter->rss_key); 10525 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10526 free_netdev(netdev); 10527 10528 pci_disable_pcie_error_reporting(pdev); 10529 10530 if (disable_dev) 10531 pci_disable_device(pdev); 10532 } 10533 10534 /** 10535 * ixgbe_io_error_detected - called when PCI error is detected 10536 * @pdev: Pointer to PCI device 10537 * @state: The current pci connection state 10538 * 10539 * This function is called after a PCI bus error affecting 10540 * this device has been detected. 10541 */ 10542 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10543 pci_channel_state_t state) 10544 { 10545 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10546 struct net_device *netdev = adapter->netdev; 10547 10548 #ifdef CONFIG_PCI_IOV 10549 struct ixgbe_hw *hw = &adapter->hw; 10550 struct pci_dev *bdev, *vfdev; 10551 u32 dw0, dw1, dw2, dw3; 10552 int vf, pos; 10553 u16 req_id, pf_func; 10554 10555 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10556 adapter->num_vfs == 0) 10557 goto skip_bad_vf_detection; 10558 10559 bdev = pdev->bus->self; 10560 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10561 bdev = bdev->bus->self; 10562 10563 if (!bdev) 10564 goto skip_bad_vf_detection; 10565 10566 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10567 if (!pos) 10568 goto skip_bad_vf_detection; 10569 10570 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10571 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10572 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10573 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10574 if (ixgbe_removed(hw->hw_addr)) 10575 goto skip_bad_vf_detection; 10576 10577 req_id = dw1 >> 16; 10578 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10579 if (!(req_id & 0x0080)) 10580 goto skip_bad_vf_detection; 10581 10582 pf_func = req_id & 0x01; 10583 if ((pf_func & 1) == (pdev->devfn & 1)) { 10584 unsigned int device_id; 10585 10586 vf = (req_id & 0x7F) >> 1; 10587 e_dev_err("VF %d has caused a PCIe error\n", vf); 10588 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10589 "%8.8x\tdw3: %8.8x\n", 10590 dw0, dw1, dw2, dw3); 10591 switch (adapter->hw.mac.type) { 10592 case ixgbe_mac_82599EB: 10593 device_id = IXGBE_82599_VF_DEVICE_ID; 10594 break; 10595 case ixgbe_mac_X540: 10596 device_id = IXGBE_X540_VF_DEVICE_ID; 10597 break; 10598 case ixgbe_mac_X550: 10599 device_id = IXGBE_DEV_ID_X550_VF; 10600 break; 10601 case ixgbe_mac_X550EM_x: 10602 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10603 break; 10604 case ixgbe_mac_x550em_a: 10605 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10606 break; 10607 default: 10608 device_id = 0; 10609 break; 10610 } 10611 10612 /* Find the pci device of the offending VF */ 10613 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10614 while (vfdev) { 10615 if (vfdev->devfn == (req_id & 0xFF)) 10616 break; 10617 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10618 device_id, vfdev); 10619 } 10620 /* 10621 * There's a slim chance the VF could have been hot plugged, 10622 * so if it is no longer present we don't need to issue the 10623 * VFLR. Just clean up the AER in that case. 10624 */ 10625 if (vfdev) { 10626 pcie_flr(vfdev); 10627 /* Free device reference count */ 10628 pci_dev_put(vfdev); 10629 } 10630 10631 pci_cleanup_aer_uncorrect_error_status(pdev); 10632 } 10633 10634 /* 10635 * Even though the error may have occurred on the other port 10636 * we still need to increment the vf error reference count for 10637 * both ports because the I/O resume function will be called 10638 * for both of them. 10639 */ 10640 adapter->vferr_refcount++; 10641 10642 return PCI_ERS_RESULT_RECOVERED; 10643 10644 skip_bad_vf_detection: 10645 #endif /* CONFIG_PCI_IOV */ 10646 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10647 return PCI_ERS_RESULT_DISCONNECT; 10648 10649 rtnl_lock(); 10650 netif_device_detach(netdev); 10651 10652 if (state == pci_channel_io_perm_failure) { 10653 rtnl_unlock(); 10654 return PCI_ERS_RESULT_DISCONNECT; 10655 } 10656 10657 if (netif_running(netdev)) 10658 ixgbe_close_suspend(adapter); 10659 10660 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10661 pci_disable_device(pdev); 10662 rtnl_unlock(); 10663 10664 /* Request a slot reset. */ 10665 return PCI_ERS_RESULT_NEED_RESET; 10666 } 10667 10668 /** 10669 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10670 * @pdev: Pointer to PCI device 10671 * 10672 * Restart the card from scratch, as if from a cold-boot. 10673 */ 10674 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10675 { 10676 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10677 pci_ers_result_t result; 10678 int err; 10679 10680 if (pci_enable_device_mem(pdev)) { 10681 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10682 result = PCI_ERS_RESULT_DISCONNECT; 10683 } else { 10684 smp_mb__before_atomic(); 10685 clear_bit(__IXGBE_DISABLED, &adapter->state); 10686 adapter->hw.hw_addr = adapter->io_addr; 10687 pci_set_master(pdev); 10688 pci_restore_state(pdev); 10689 pci_save_state(pdev); 10690 10691 pci_wake_from_d3(pdev, false); 10692 10693 ixgbe_reset(adapter); 10694 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10695 result = PCI_ERS_RESULT_RECOVERED; 10696 } 10697 10698 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10699 if (err) { 10700 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10701 "failed 0x%0x\n", err); 10702 /* non-fatal, continue */ 10703 } 10704 10705 return result; 10706 } 10707 10708 /** 10709 * ixgbe_io_resume - called when traffic can start flowing again. 10710 * @pdev: Pointer to PCI device 10711 * 10712 * This callback is called when the error recovery driver tells us that 10713 * its OK to resume normal operation. 10714 */ 10715 static void ixgbe_io_resume(struct pci_dev *pdev) 10716 { 10717 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10718 struct net_device *netdev = adapter->netdev; 10719 10720 #ifdef CONFIG_PCI_IOV 10721 if (adapter->vferr_refcount) { 10722 e_info(drv, "Resuming after VF err\n"); 10723 adapter->vferr_refcount--; 10724 return; 10725 } 10726 10727 #endif 10728 rtnl_lock(); 10729 if (netif_running(netdev)) 10730 ixgbe_open(netdev); 10731 10732 netif_device_attach(netdev); 10733 rtnl_unlock(); 10734 } 10735 10736 static const struct pci_error_handlers ixgbe_err_handler = { 10737 .error_detected = ixgbe_io_error_detected, 10738 .slot_reset = ixgbe_io_slot_reset, 10739 .resume = ixgbe_io_resume, 10740 }; 10741 10742 static struct pci_driver ixgbe_driver = { 10743 .name = ixgbe_driver_name, 10744 .id_table = ixgbe_pci_tbl, 10745 .probe = ixgbe_probe, 10746 .remove = ixgbe_remove, 10747 #ifdef CONFIG_PM 10748 .suspend = ixgbe_suspend, 10749 .resume = ixgbe_resume, 10750 #endif 10751 .shutdown = ixgbe_shutdown, 10752 .sriov_configure = ixgbe_pci_sriov_configure, 10753 .err_handler = &ixgbe_err_handler 10754 }; 10755 10756 /** 10757 * ixgbe_init_module - Driver Registration Routine 10758 * 10759 * ixgbe_init_module is the first routine called when the driver is 10760 * loaded. All it does is register with the PCI subsystem. 10761 **/ 10762 static int __init ixgbe_init_module(void) 10763 { 10764 int ret; 10765 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 10766 pr_info("%s\n", ixgbe_copyright); 10767 10768 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 10769 if (!ixgbe_wq) { 10770 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 10771 return -ENOMEM; 10772 } 10773 10774 ixgbe_dbg_init(); 10775 10776 ret = pci_register_driver(&ixgbe_driver); 10777 if (ret) { 10778 destroy_workqueue(ixgbe_wq); 10779 ixgbe_dbg_exit(); 10780 return ret; 10781 } 10782 10783 #ifdef CONFIG_IXGBE_DCA 10784 dca_register_notify(&dca_notifier); 10785 #endif 10786 10787 return 0; 10788 } 10789 10790 module_init(ixgbe_init_module); 10791 10792 /** 10793 * ixgbe_exit_module - Driver Exit Cleanup Routine 10794 * 10795 * ixgbe_exit_module is called just before the driver is removed 10796 * from memory. 10797 **/ 10798 static void __exit ixgbe_exit_module(void) 10799 { 10800 #ifdef CONFIG_IXGBE_DCA 10801 dca_unregister_notify(&dca_notifier); 10802 #endif 10803 pci_unregister_driver(&ixgbe_driver); 10804 10805 ixgbe_dbg_exit(); 10806 if (ixgbe_wq) { 10807 destroy_workqueue(ixgbe_wq); 10808 ixgbe_wq = NULL; 10809 } 10810 } 10811 10812 #ifdef CONFIG_IXGBE_DCA 10813 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 10814 void *p) 10815 { 10816 int ret_val; 10817 10818 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 10819 __ixgbe_notify_dca); 10820 10821 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 10822 } 10823 10824 #endif /* CONFIG_IXGBE_DCA */ 10825 10826 module_exit(ixgbe_exit_module); 10827 10828 /* ixgbe_main.c */ 10829