1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <scsi/fc/fc_fcoe.h> 31 #include <net/udp_tunnel.h> 32 #include <net/pkt_cls.h> 33 #include <net/tc_act/tc_gact.h> 34 #include <net/tc_act/tc_mirred.h> 35 #include <net/vxlan.h> 36 #include <net/mpls.h> 37 38 #include "ixgbe.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_dcb_82599.h" 41 #include "ixgbe_sriov.h" 42 #include "ixgbe_model.h" 43 44 char ixgbe_driver_name[] = "ixgbe"; 45 static const char ixgbe_driver_string[] = 46 "Intel(R) 10 Gigabit PCI Express Network Driver"; 47 #ifdef IXGBE_FCOE 48 char ixgbe_default_device_descr[] = 49 "Intel(R) 10 Gigabit Network Connection"; 50 #else 51 static char ixgbe_default_device_descr[] = 52 "Intel(R) 10 Gigabit Network Connection"; 53 #endif 54 #define DRV_VERSION "5.1.0-k" 55 const char ixgbe_driver_version[] = DRV_VERSION; 56 static const char ixgbe_copyright[] = 57 "Copyright (c) 1999-2016 Intel Corporation."; 58 59 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 60 61 static const struct ixgbe_info *ixgbe_info_tbl[] = { 62 [board_82598] = &ixgbe_82598_info, 63 [board_82599] = &ixgbe_82599_info, 64 [board_X540] = &ixgbe_X540_info, 65 [board_X550] = &ixgbe_X550_info, 66 [board_X550EM_x] = &ixgbe_X550EM_x_info, 67 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 68 [board_x550em_a] = &ixgbe_x550em_a_info, 69 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 70 }; 71 72 /* ixgbe_pci_tbl - PCI Device ID Table 73 * 74 * Wildcard entries (PCI_ANY_ID) should come last 75 * Last entry must be all 0s 76 * 77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 78 * Class, Class Mask, private data (not used) } 79 */ 80 static const struct pci_device_id ixgbe_pci_tbl[] = { 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 128 /* required last entry */ 129 {0, } 130 }; 131 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 132 133 #ifdef CONFIG_IXGBE_DCA 134 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 135 void *p); 136 static struct notifier_block dca_notifier = { 137 .notifier_call = ixgbe_notify_dca, 138 .next = NULL, 139 .priority = 0 140 }; 141 #endif 142 143 #ifdef CONFIG_PCI_IOV 144 static unsigned int max_vfs; 145 module_param(max_vfs, uint, 0); 146 MODULE_PARM_DESC(max_vfs, 147 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 148 #endif /* CONFIG_PCI_IOV */ 149 150 static unsigned int allow_unsupported_sfp; 151 module_param(allow_unsupported_sfp, uint, 0); 152 MODULE_PARM_DESC(allow_unsupported_sfp, 153 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 154 155 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 156 static int debug = -1; 157 module_param(debug, int, 0); 158 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 159 160 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 161 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 162 MODULE_LICENSE("GPL"); 163 MODULE_VERSION(DRV_VERSION); 164 165 static struct workqueue_struct *ixgbe_wq; 166 167 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 168 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 169 170 static const struct net_device_ops ixgbe_netdev_ops; 171 172 static bool netif_is_ixgbe(struct net_device *dev) 173 { 174 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 175 } 176 177 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 178 u32 reg, u16 *value) 179 { 180 struct pci_dev *parent_dev; 181 struct pci_bus *parent_bus; 182 183 parent_bus = adapter->pdev->bus->parent; 184 if (!parent_bus) 185 return -1; 186 187 parent_dev = parent_bus->self; 188 if (!parent_dev) 189 return -1; 190 191 if (!pci_is_pcie(parent_dev)) 192 return -1; 193 194 pcie_capability_read_word(parent_dev, reg, value); 195 if (*value == IXGBE_FAILED_READ_CFG_WORD && 196 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 197 return -1; 198 return 0; 199 } 200 201 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 202 { 203 struct ixgbe_hw *hw = &adapter->hw; 204 u16 link_status = 0; 205 int err; 206 207 hw->bus.type = ixgbe_bus_type_pci_express; 208 209 /* Get the negotiated link width and speed from PCI config space of the 210 * parent, as this device is behind a switch 211 */ 212 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 213 214 /* assume caller will handle error case */ 215 if (err) 216 return err; 217 218 hw->bus.width = ixgbe_convert_bus_width(link_status); 219 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 220 221 return 0; 222 } 223 224 /** 225 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 226 * @hw: hw specific details 227 * 228 * This function is used by probe to determine whether a device's PCI-Express 229 * bandwidth details should be gathered from the parent bus instead of from the 230 * device. Used to ensure that various locations all have the correct device ID 231 * checks. 232 */ 233 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 234 { 235 switch (hw->device_id) { 236 case IXGBE_DEV_ID_82599_SFP_SF_QP: 237 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 238 return true; 239 default: 240 return false; 241 } 242 } 243 244 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 245 int expected_gts) 246 { 247 struct ixgbe_hw *hw = &adapter->hw; 248 struct pci_dev *pdev; 249 250 /* Some devices are not connected over PCIe and thus do not negotiate 251 * speed. These devices do not have valid bus info, and thus any report 252 * we generate may not be correct. 253 */ 254 if (hw->bus.type == ixgbe_bus_type_internal) 255 return; 256 257 /* determine whether to use the parent device */ 258 if (ixgbe_pcie_from_parent(&adapter->hw)) 259 pdev = adapter->pdev->bus->parent->self; 260 else 261 pdev = adapter->pdev; 262 263 pcie_print_link_status(pdev); 264 } 265 266 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 267 { 268 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 269 !test_bit(__IXGBE_REMOVING, &adapter->state) && 270 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 271 queue_work(ixgbe_wq, &adapter->service_task); 272 } 273 274 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 275 { 276 struct ixgbe_adapter *adapter = hw->back; 277 278 if (!hw->hw_addr) 279 return; 280 hw->hw_addr = NULL; 281 e_dev_err("Adapter removed\n"); 282 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 283 ixgbe_service_event_schedule(adapter); 284 } 285 286 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 287 { 288 u8 __iomem *reg_addr; 289 u32 value; 290 int i; 291 292 reg_addr = READ_ONCE(hw->hw_addr); 293 if (ixgbe_removed(reg_addr)) 294 return IXGBE_FAILED_READ_REG; 295 296 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 297 * so perform several status register reads to determine if the adapter 298 * has been removed. 299 */ 300 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 301 value = readl(reg_addr + IXGBE_STATUS); 302 if (value != IXGBE_FAILED_READ_REG) 303 break; 304 mdelay(3); 305 } 306 307 if (value == IXGBE_FAILED_READ_REG) 308 ixgbe_remove_adapter(hw); 309 else 310 value = readl(reg_addr + reg); 311 return value; 312 } 313 314 /** 315 * ixgbe_read_reg - Read from device register 316 * @hw: hw specific details 317 * @reg: offset of register to read 318 * 319 * Returns : value read or IXGBE_FAILED_READ_REG if removed 320 * 321 * This function is used to read device registers. It checks for device 322 * removal by confirming any read that returns all ones by checking the 323 * status register value for all ones. This function avoids reading from 324 * the hardware if a removal was previously detected in which case it 325 * returns IXGBE_FAILED_READ_REG (all ones). 326 */ 327 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 328 { 329 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 330 u32 value; 331 332 if (ixgbe_removed(reg_addr)) 333 return IXGBE_FAILED_READ_REG; 334 if (unlikely(hw->phy.nw_mng_if_sel & 335 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 336 struct ixgbe_adapter *adapter; 337 int i; 338 339 for (i = 0; i < 200; ++i) { 340 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 341 if (likely(!value)) 342 goto writes_completed; 343 if (value == IXGBE_FAILED_READ_REG) { 344 ixgbe_remove_adapter(hw); 345 return IXGBE_FAILED_READ_REG; 346 } 347 udelay(5); 348 } 349 350 adapter = hw->back; 351 e_warn(hw, "register writes incomplete %08x\n", value); 352 } 353 354 writes_completed: 355 value = readl(reg_addr + reg); 356 if (unlikely(value == IXGBE_FAILED_READ_REG)) 357 value = ixgbe_check_remove(hw, reg); 358 return value; 359 } 360 361 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 362 { 363 u16 value; 364 365 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 366 if (value == IXGBE_FAILED_READ_CFG_WORD) { 367 ixgbe_remove_adapter(hw); 368 return true; 369 } 370 return false; 371 } 372 373 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 374 { 375 struct ixgbe_adapter *adapter = hw->back; 376 u16 value; 377 378 if (ixgbe_removed(hw->hw_addr)) 379 return IXGBE_FAILED_READ_CFG_WORD; 380 pci_read_config_word(adapter->pdev, reg, &value); 381 if (value == IXGBE_FAILED_READ_CFG_WORD && 382 ixgbe_check_cfg_remove(hw, adapter->pdev)) 383 return IXGBE_FAILED_READ_CFG_WORD; 384 return value; 385 } 386 387 #ifdef CONFIG_PCI_IOV 388 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 389 { 390 struct ixgbe_adapter *adapter = hw->back; 391 u32 value; 392 393 if (ixgbe_removed(hw->hw_addr)) 394 return IXGBE_FAILED_READ_CFG_DWORD; 395 pci_read_config_dword(adapter->pdev, reg, &value); 396 if (value == IXGBE_FAILED_READ_CFG_DWORD && 397 ixgbe_check_cfg_remove(hw, adapter->pdev)) 398 return IXGBE_FAILED_READ_CFG_DWORD; 399 return value; 400 } 401 #endif /* CONFIG_PCI_IOV */ 402 403 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 404 { 405 struct ixgbe_adapter *adapter = hw->back; 406 407 if (ixgbe_removed(hw->hw_addr)) 408 return; 409 pci_write_config_word(adapter->pdev, reg, value); 410 } 411 412 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 413 { 414 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 415 416 /* flush memory to make sure state is correct before next watchdog */ 417 smp_mb__before_atomic(); 418 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 419 } 420 421 struct ixgbe_reg_info { 422 u32 ofs; 423 char *name; 424 }; 425 426 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 427 428 /* General Registers */ 429 {IXGBE_CTRL, "CTRL"}, 430 {IXGBE_STATUS, "STATUS"}, 431 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 432 433 /* Interrupt Registers */ 434 {IXGBE_EICR, "EICR"}, 435 436 /* RX Registers */ 437 {IXGBE_SRRCTL(0), "SRRCTL"}, 438 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 439 {IXGBE_RDLEN(0), "RDLEN"}, 440 {IXGBE_RDH(0), "RDH"}, 441 {IXGBE_RDT(0), "RDT"}, 442 {IXGBE_RXDCTL(0), "RXDCTL"}, 443 {IXGBE_RDBAL(0), "RDBAL"}, 444 {IXGBE_RDBAH(0), "RDBAH"}, 445 446 /* TX Registers */ 447 {IXGBE_TDBAL(0), "TDBAL"}, 448 {IXGBE_TDBAH(0), "TDBAH"}, 449 {IXGBE_TDLEN(0), "TDLEN"}, 450 {IXGBE_TDH(0), "TDH"}, 451 {IXGBE_TDT(0), "TDT"}, 452 {IXGBE_TXDCTL(0), "TXDCTL"}, 453 454 /* List Terminator */ 455 { .name = NULL } 456 }; 457 458 459 /* 460 * ixgbe_regdump - register printout routine 461 */ 462 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 463 { 464 int i; 465 char rname[16]; 466 u32 regs[64]; 467 468 switch (reginfo->ofs) { 469 case IXGBE_SRRCTL(0): 470 for (i = 0; i < 64; i++) 471 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 472 break; 473 case IXGBE_DCA_RXCTRL(0): 474 for (i = 0; i < 64; i++) 475 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 476 break; 477 case IXGBE_RDLEN(0): 478 for (i = 0; i < 64; i++) 479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 480 break; 481 case IXGBE_RDH(0): 482 for (i = 0; i < 64; i++) 483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 484 break; 485 case IXGBE_RDT(0): 486 for (i = 0; i < 64; i++) 487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 488 break; 489 case IXGBE_RXDCTL(0): 490 for (i = 0; i < 64; i++) 491 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 492 break; 493 case IXGBE_RDBAL(0): 494 for (i = 0; i < 64; i++) 495 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 496 break; 497 case IXGBE_RDBAH(0): 498 for (i = 0; i < 64; i++) 499 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 500 break; 501 case IXGBE_TDBAL(0): 502 for (i = 0; i < 64; i++) 503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 504 break; 505 case IXGBE_TDBAH(0): 506 for (i = 0; i < 64; i++) 507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 508 break; 509 case IXGBE_TDLEN(0): 510 for (i = 0; i < 64; i++) 511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 512 break; 513 case IXGBE_TDH(0): 514 for (i = 0; i < 64; i++) 515 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 516 break; 517 case IXGBE_TDT(0): 518 for (i = 0; i < 64; i++) 519 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 520 break; 521 case IXGBE_TXDCTL(0): 522 for (i = 0; i < 64; i++) 523 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 524 break; 525 default: 526 pr_info("%-15s %08x\n", 527 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 528 return; 529 } 530 531 i = 0; 532 while (i < 64) { 533 int j; 534 char buf[9 * 8 + 1]; 535 char *p = buf; 536 537 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 538 for (j = 0; j < 8; j++) 539 p += sprintf(p, " %08x", regs[i++]); 540 pr_err("%-15s%s\n", rname, buf); 541 } 542 543 } 544 545 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 546 { 547 struct ixgbe_tx_buffer *tx_buffer; 548 549 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 550 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 551 n, ring->next_to_use, ring->next_to_clean, 552 (u64)dma_unmap_addr(tx_buffer, dma), 553 dma_unmap_len(tx_buffer, len), 554 tx_buffer->next_to_watch, 555 (u64)tx_buffer->time_stamp); 556 } 557 558 /* 559 * ixgbe_dump - Print registers, tx-rings and rx-rings 560 */ 561 static void ixgbe_dump(struct ixgbe_adapter *adapter) 562 { 563 struct net_device *netdev = adapter->netdev; 564 struct ixgbe_hw *hw = &adapter->hw; 565 struct ixgbe_reg_info *reginfo; 566 int n = 0; 567 struct ixgbe_ring *ring; 568 struct ixgbe_tx_buffer *tx_buffer; 569 union ixgbe_adv_tx_desc *tx_desc; 570 struct my_u0 { u64 a; u64 b; } *u0; 571 struct ixgbe_ring *rx_ring; 572 union ixgbe_adv_rx_desc *rx_desc; 573 struct ixgbe_rx_buffer *rx_buffer_info; 574 int i = 0; 575 576 if (!netif_msg_hw(adapter)) 577 return; 578 579 /* Print netdevice Info */ 580 if (netdev) { 581 dev_info(&adapter->pdev->dev, "Net device Info\n"); 582 pr_info("Device Name state " 583 "trans_start\n"); 584 pr_info("%-15s %016lX %016lX\n", 585 netdev->name, 586 netdev->state, 587 dev_trans_start(netdev)); 588 } 589 590 /* Print Registers */ 591 dev_info(&adapter->pdev->dev, "Register Dump\n"); 592 pr_info(" Register Name Value\n"); 593 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 594 reginfo->name; reginfo++) { 595 ixgbe_regdump(hw, reginfo); 596 } 597 598 /* Print TX Ring Summary */ 599 if (!netdev || !netif_running(netdev)) 600 return; 601 602 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 603 pr_info(" %s %s %s %s\n", 604 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 605 "leng", "ntw", "timestamp"); 606 for (n = 0; n < adapter->num_tx_queues; n++) { 607 ring = adapter->tx_ring[n]; 608 ixgbe_print_buffer(ring, n); 609 } 610 611 for (n = 0; n < adapter->num_xdp_queues; n++) { 612 ring = adapter->xdp_ring[n]; 613 ixgbe_print_buffer(ring, n); 614 } 615 616 /* Print TX Rings */ 617 if (!netif_msg_tx_done(adapter)) 618 goto rx_ring_summary; 619 620 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 621 622 /* Transmit Descriptor Formats 623 * 624 * 82598 Advanced Transmit Descriptor 625 * +--------------------------------------------------------------+ 626 * 0 | Buffer Address [63:0] | 627 * +--------------------------------------------------------------+ 628 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 629 * +--------------------------------------------------------------+ 630 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 631 * 632 * 82598 Advanced Transmit Descriptor (Write-Back Format) 633 * +--------------------------------------------------------------+ 634 * 0 | RSV [63:0] | 635 * +--------------------------------------------------------------+ 636 * 8 | RSV | STA | NXTSEQ | 637 * +--------------------------------------------------------------+ 638 * 63 36 35 32 31 0 639 * 640 * 82599+ Advanced Transmit Descriptor 641 * +--------------------------------------------------------------+ 642 * 0 | Buffer Address [63:0] | 643 * +--------------------------------------------------------------+ 644 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 645 * +--------------------------------------------------------------+ 646 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 647 * 648 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 649 * +--------------------------------------------------------------+ 650 * 0 | RSV [63:0] | 651 * +--------------------------------------------------------------+ 652 * 8 | RSV | STA | RSV | 653 * +--------------------------------------------------------------+ 654 * 63 36 35 32 31 0 655 */ 656 657 for (n = 0; n < adapter->num_tx_queues; n++) { 658 ring = adapter->tx_ring[n]; 659 pr_info("------------------------------------\n"); 660 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 661 pr_info("------------------------------------\n"); 662 pr_info("%s%s %s %s %s %s\n", 663 "T [desc] [address 63:0 ] ", 664 "[PlPOIdStDDt Ln] [bi->dma ] ", 665 "leng", "ntw", "timestamp", "bi->skb"); 666 667 for (i = 0; ring->desc && (i < ring->count); i++) { 668 tx_desc = IXGBE_TX_DESC(ring, i); 669 tx_buffer = &ring->tx_buffer_info[i]; 670 u0 = (struct my_u0 *)tx_desc; 671 if (dma_unmap_len(tx_buffer, len) > 0) { 672 const char *ring_desc; 673 674 if (i == ring->next_to_use && 675 i == ring->next_to_clean) 676 ring_desc = " NTC/U"; 677 else if (i == ring->next_to_use) 678 ring_desc = " NTU"; 679 else if (i == ring->next_to_clean) 680 ring_desc = " NTC"; 681 else 682 ring_desc = ""; 683 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 684 i, 685 le64_to_cpu((__force __le64)u0->a), 686 le64_to_cpu((__force __le64)u0->b), 687 (u64)dma_unmap_addr(tx_buffer, dma), 688 dma_unmap_len(tx_buffer, len), 689 tx_buffer->next_to_watch, 690 (u64)tx_buffer->time_stamp, 691 tx_buffer->skb, 692 ring_desc); 693 694 if (netif_msg_pktdata(adapter) && 695 tx_buffer->skb) 696 print_hex_dump(KERN_INFO, "", 697 DUMP_PREFIX_ADDRESS, 16, 1, 698 tx_buffer->skb->data, 699 dma_unmap_len(tx_buffer, len), 700 true); 701 } 702 } 703 } 704 705 /* Print RX Rings Summary */ 706 rx_ring_summary: 707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 708 pr_info("Queue [NTU] [NTC]\n"); 709 for (n = 0; n < adapter->num_rx_queues; n++) { 710 rx_ring = adapter->rx_ring[n]; 711 pr_info("%5d %5X %5X\n", 712 n, rx_ring->next_to_use, rx_ring->next_to_clean); 713 } 714 715 /* Print RX Rings */ 716 if (!netif_msg_rx_status(adapter)) 717 return; 718 719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 720 721 /* Receive Descriptor Formats 722 * 723 * 82598 Advanced Receive Descriptor (Read) Format 724 * 63 1 0 725 * +-----------------------------------------------------+ 726 * 0 | Packet Buffer Address [63:1] |A0/NSE| 727 * +----------------------------------------------+------+ 728 * 8 | Header Buffer Address [63:1] | DD | 729 * +-----------------------------------------------------+ 730 * 731 * 732 * 82598 Advanced Receive Descriptor (Write-Back) Format 733 * 734 * 63 48 47 32 31 30 21 20 16 15 4 3 0 735 * +------------------------------------------------------+ 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 737 * | Packet | IP | | | | Type | Type | 738 * | Checksum | Ident | | | | | | 739 * +------------------------------------------------------+ 740 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 741 * +------------------------------------------------------+ 742 * 63 48 47 32 31 20 19 0 743 * 744 * 82599+ Advanced Receive Descriptor (Read) Format 745 * 63 1 0 746 * +-----------------------------------------------------+ 747 * 0 | Packet Buffer Address [63:1] |A0/NSE| 748 * +----------------------------------------------+------+ 749 * 8 | Header Buffer Address [63:1] | DD | 750 * +-----------------------------------------------------+ 751 * 752 * 753 * 82599+ Advanced Receive Descriptor (Write-Back) Format 754 * 755 * 63 48 47 32 31 30 21 20 17 16 4 3 0 756 * +------------------------------------------------------+ 757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 759 * |/ Flow Dir Flt ID | | | | | | 760 * +------------------------------------------------------+ 761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 762 * +------------------------------------------------------+ 763 * 63 48 47 32 31 20 19 0 764 */ 765 766 for (n = 0; n < adapter->num_rx_queues; n++) { 767 rx_ring = adapter->rx_ring[n]; 768 pr_info("------------------------------------\n"); 769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 770 pr_info("------------------------------------\n"); 771 pr_info("%s%s%s\n", 772 "R [desc] [ PktBuf A0] ", 773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 774 "<-- Adv Rx Read format"); 775 pr_info("%s%s%s\n", 776 "RWB[desc] [PcsmIpSHl PtRs] ", 777 "[vl er S cks ln] ---------------- [bi->skb ] ", 778 "<-- Adv Rx Write-Back format"); 779 780 for (i = 0; i < rx_ring->count; i++) { 781 const char *ring_desc; 782 783 if (i == rx_ring->next_to_use) 784 ring_desc = " NTU"; 785 else if (i == rx_ring->next_to_clean) 786 ring_desc = " NTC"; 787 else 788 ring_desc = ""; 789 790 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 791 rx_desc = IXGBE_RX_DESC(rx_ring, i); 792 u0 = (struct my_u0 *)rx_desc; 793 if (rx_desc->wb.upper.length) { 794 /* Descriptor Done */ 795 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 796 i, 797 le64_to_cpu((__force __le64)u0->a), 798 le64_to_cpu((__force __le64)u0->b), 799 rx_buffer_info->skb, 800 ring_desc); 801 } else { 802 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 803 i, 804 le64_to_cpu((__force __le64)u0->a), 805 le64_to_cpu((__force __le64)u0->b), 806 (u64)rx_buffer_info->dma, 807 rx_buffer_info->skb, 808 ring_desc); 809 810 if (netif_msg_pktdata(adapter) && 811 rx_buffer_info->dma) { 812 print_hex_dump(KERN_INFO, "", 813 DUMP_PREFIX_ADDRESS, 16, 1, 814 page_address(rx_buffer_info->page) + 815 rx_buffer_info->page_offset, 816 ixgbe_rx_bufsz(rx_ring), true); 817 } 818 } 819 } 820 } 821 } 822 823 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 824 { 825 u32 ctrl_ext; 826 827 /* Let firmware take over control of h/w */ 828 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 829 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 830 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 831 } 832 833 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 834 { 835 u32 ctrl_ext; 836 837 /* Let firmware know the driver has taken over */ 838 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 839 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 840 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 841 } 842 843 /** 844 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 845 * @adapter: pointer to adapter struct 846 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 847 * @queue: queue to map the corresponding interrupt to 848 * @msix_vector: the vector to map to the corresponding queue 849 * 850 */ 851 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 852 u8 queue, u8 msix_vector) 853 { 854 u32 ivar, index; 855 struct ixgbe_hw *hw = &adapter->hw; 856 switch (hw->mac.type) { 857 case ixgbe_mac_82598EB: 858 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 859 if (direction == -1) 860 direction = 0; 861 index = (((direction * 64) + queue) >> 2) & 0x1F; 862 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 863 ivar &= ~(0xFF << (8 * (queue & 0x3))); 864 ivar |= (msix_vector << (8 * (queue & 0x3))); 865 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 866 break; 867 case ixgbe_mac_82599EB: 868 case ixgbe_mac_X540: 869 case ixgbe_mac_X550: 870 case ixgbe_mac_X550EM_x: 871 case ixgbe_mac_x550em_a: 872 if (direction == -1) { 873 /* other causes */ 874 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 875 index = ((queue & 1) * 8); 876 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 877 ivar &= ~(0xFF << index); 878 ivar |= (msix_vector << index); 879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 880 break; 881 } else { 882 /* tx or rx causes */ 883 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 884 index = ((16 * (queue & 1)) + (8 * direction)); 885 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 886 ivar &= ~(0xFF << index); 887 ivar |= (msix_vector << index); 888 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 889 break; 890 } 891 default: 892 break; 893 } 894 } 895 896 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 897 u64 qmask) 898 { 899 u32 mask; 900 901 switch (adapter->hw.mac.type) { 902 case ixgbe_mac_82598EB: 903 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 905 break; 906 case ixgbe_mac_82599EB: 907 case ixgbe_mac_X540: 908 case ixgbe_mac_X550: 909 case ixgbe_mac_X550EM_x: 910 case ixgbe_mac_x550em_a: 911 mask = (qmask & 0xFFFFFFFF); 912 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 913 mask = (qmask >> 32); 914 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 915 break; 916 default: 917 break; 918 } 919 } 920 921 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 922 { 923 struct ixgbe_hw *hw = &adapter->hw; 924 struct ixgbe_hw_stats *hwstats = &adapter->stats; 925 int i; 926 u32 data; 927 928 if ((hw->fc.current_mode != ixgbe_fc_full) && 929 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 930 return; 931 932 switch (hw->mac.type) { 933 case ixgbe_mac_82598EB: 934 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 935 break; 936 default: 937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 938 } 939 hwstats->lxoffrxc += data; 940 941 /* refill credits (no tx hang) if we received xoff */ 942 if (!data) 943 return; 944 945 for (i = 0; i < adapter->num_tx_queues; i++) 946 clear_bit(__IXGBE_HANG_CHECK_ARMED, 947 &adapter->tx_ring[i]->state); 948 949 for (i = 0; i < adapter->num_xdp_queues; i++) 950 clear_bit(__IXGBE_HANG_CHECK_ARMED, 951 &adapter->xdp_ring[i]->state); 952 } 953 954 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 955 { 956 struct ixgbe_hw *hw = &adapter->hw; 957 struct ixgbe_hw_stats *hwstats = &adapter->stats; 958 u32 xoff[8] = {0}; 959 u8 tc; 960 int i; 961 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 962 963 if (adapter->ixgbe_ieee_pfc) 964 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 965 966 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 967 ixgbe_update_xoff_rx_lfc(adapter); 968 return; 969 } 970 971 /* update stats for each tc, only valid with PFC enabled */ 972 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 973 u32 pxoffrxc; 974 975 switch (hw->mac.type) { 976 case ixgbe_mac_82598EB: 977 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 978 break; 979 default: 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 981 } 982 hwstats->pxoffrxc[i] += pxoffrxc; 983 /* Get the TC for given UP */ 984 tc = netdev_get_prio_tc_map(adapter->netdev, i); 985 xoff[tc] += pxoffrxc; 986 } 987 988 /* disarm tx queues that have received xoff frames */ 989 for (i = 0; i < adapter->num_tx_queues; i++) { 990 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 991 992 tc = tx_ring->dcb_tc; 993 if (xoff[tc]) 994 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 995 } 996 997 for (i = 0; i < adapter->num_xdp_queues; i++) { 998 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 999 1000 tc = xdp_ring->dcb_tc; 1001 if (xoff[tc]) 1002 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1003 } 1004 } 1005 1006 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1007 { 1008 return ring->stats.packets; 1009 } 1010 1011 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1012 { 1013 unsigned int head, tail; 1014 1015 head = ring->next_to_clean; 1016 tail = ring->next_to_use; 1017 1018 return ((head <= tail) ? tail : tail + ring->count) - head; 1019 } 1020 1021 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1022 { 1023 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1024 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1025 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1026 1027 clear_check_for_tx_hang(tx_ring); 1028 1029 /* 1030 * Check for a hung queue, but be thorough. This verifies 1031 * that a transmit has been completed since the previous 1032 * check AND there is at least one packet pending. The 1033 * ARMED bit is set to indicate a potential hang. The 1034 * bit is cleared if a pause frame is received to remove 1035 * false hang detection due to PFC or 802.3x frames. By 1036 * requiring this to fail twice we avoid races with 1037 * pfc clearing the ARMED bit and conditions where we 1038 * run the check_tx_hang logic with a transmit completion 1039 * pending but without time to complete it yet. 1040 */ 1041 if (tx_done_old == tx_done && tx_pending) 1042 /* make sure it is true for two checks in a row */ 1043 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1044 &tx_ring->state); 1045 /* update completed stats and continue */ 1046 tx_ring->tx_stats.tx_done_old = tx_done; 1047 /* reset the countdown */ 1048 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1049 1050 return false; 1051 } 1052 1053 /** 1054 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1055 * @adapter: driver private struct 1056 **/ 1057 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1058 { 1059 1060 /* Do the reset outside of interrupt context */ 1061 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1062 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1063 e_warn(drv, "initiating reset due to tx timeout\n"); 1064 ixgbe_service_event_schedule(adapter); 1065 } 1066 } 1067 1068 /** 1069 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1070 * @netdev: network interface device structure 1071 * @queue_index: Tx queue to set 1072 * @maxrate: desired maximum transmit bitrate 1073 **/ 1074 static int ixgbe_tx_maxrate(struct net_device *netdev, 1075 int queue_index, u32 maxrate) 1076 { 1077 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1078 struct ixgbe_hw *hw = &adapter->hw; 1079 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1080 1081 if (!maxrate) 1082 return 0; 1083 1084 /* Calculate the rate factor values to set */ 1085 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1086 bcnrc_val /= maxrate; 1087 1088 /* clear everything but the rate factor */ 1089 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1090 IXGBE_RTTBCNRC_RF_DEC_MASK; 1091 1092 /* enable the rate scheduler */ 1093 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1094 1095 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1096 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1097 1098 return 0; 1099 } 1100 1101 /** 1102 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1103 * @q_vector: structure containing interrupt and ring information 1104 * @tx_ring: tx ring to clean 1105 * @napi_budget: Used to determine if we are in netpoll 1106 **/ 1107 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1108 struct ixgbe_ring *tx_ring, int napi_budget) 1109 { 1110 struct ixgbe_adapter *adapter = q_vector->adapter; 1111 struct ixgbe_tx_buffer *tx_buffer; 1112 union ixgbe_adv_tx_desc *tx_desc; 1113 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1114 unsigned int budget = q_vector->tx.work_limit; 1115 unsigned int i = tx_ring->next_to_clean; 1116 1117 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1118 return true; 1119 1120 tx_buffer = &tx_ring->tx_buffer_info[i]; 1121 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1122 i -= tx_ring->count; 1123 1124 do { 1125 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1126 1127 /* if next_to_watch is not set then there is no work pending */ 1128 if (!eop_desc) 1129 break; 1130 1131 /* prevent any other reads prior to eop_desc */ 1132 smp_rmb(); 1133 1134 /* if DD is not set pending work has not been completed */ 1135 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1136 break; 1137 1138 /* clear next_to_watch to prevent false hangs */ 1139 tx_buffer->next_to_watch = NULL; 1140 1141 /* update the statistics for this packet */ 1142 total_bytes += tx_buffer->bytecount; 1143 total_packets += tx_buffer->gso_segs; 1144 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1145 total_ipsec++; 1146 1147 /* free the skb */ 1148 if (ring_is_xdp(tx_ring)) 1149 xdp_return_frame(tx_buffer->xdpf); 1150 else 1151 napi_consume_skb(tx_buffer->skb, napi_budget); 1152 1153 /* unmap skb header data */ 1154 dma_unmap_single(tx_ring->dev, 1155 dma_unmap_addr(tx_buffer, dma), 1156 dma_unmap_len(tx_buffer, len), 1157 DMA_TO_DEVICE); 1158 1159 /* clear tx_buffer data */ 1160 dma_unmap_len_set(tx_buffer, len, 0); 1161 1162 /* unmap remaining buffers */ 1163 while (tx_desc != eop_desc) { 1164 tx_buffer++; 1165 tx_desc++; 1166 i++; 1167 if (unlikely(!i)) { 1168 i -= tx_ring->count; 1169 tx_buffer = tx_ring->tx_buffer_info; 1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1171 } 1172 1173 /* unmap any remaining paged data */ 1174 if (dma_unmap_len(tx_buffer, len)) { 1175 dma_unmap_page(tx_ring->dev, 1176 dma_unmap_addr(tx_buffer, dma), 1177 dma_unmap_len(tx_buffer, len), 1178 DMA_TO_DEVICE); 1179 dma_unmap_len_set(tx_buffer, len, 0); 1180 } 1181 } 1182 1183 /* move us one more past the eop_desc for start of next pkt */ 1184 tx_buffer++; 1185 tx_desc++; 1186 i++; 1187 if (unlikely(!i)) { 1188 i -= tx_ring->count; 1189 tx_buffer = tx_ring->tx_buffer_info; 1190 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1191 } 1192 1193 /* issue prefetch for next Tx descriptor */ 1194 prefetch(tx_desc); 1195 1196 /* update budget accounting */ 1197 budget--; 1198 } while (likely(budget)); 1199 1200 i += tx_ring->count; 1201 tx_ring->next_to_clean = i; 1202 u64_stats_update_begin(&tx_ring->syncp); 1203 tx_ring->stats.bytes += total_bytes; 1204 tx_ring->stats.packets += total_packets; 1205 u64_stats_update_end(&tx_ring->syncp); 1206 q_vector->tx.total_bytes += total_bytes; 1207 q_vector->tx.total_packets += total_packets; 1208 adapter->tx_ipsec += total_ipsec; 1209 1210 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1211 /* schedule immediate reset if we believe we hung */ 1212 struct ixgbe_hw *hw = &adapter->hw; 1213 e_err(drv, "Detected Tx Unit Hang %s\n" 1214 " Tx Queue <%d>\n" 1215 " TDH, TDT <%x>, <%x>\n" 1216 " next_to_use <%x>\n" 1217 " next_to_clean <%x>\n" 1218 "tx_buffer_info[next_to_clean]\n" 1219 " time_stamp <%lx>\n" 1220 " jiffies <%lx>\n", 1221 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1222 tx_ring->queue_index, 1223 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1224 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1225 tx_ring->next_to_use, i, 1226 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1227 1228 if (!ring_is_xdp(tx_ring)) 1229 netif_stop_subqueue(tx_ring->netdev, 1230 tx_ring->queue_index); 1231 1232 e_info(probe, 1233 "tx hang %d detected on queue %d, resetting adapter\n", 1234 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1235 1236 /* schedule immediate reset if we believe we hung */ 1237 ixgbe_tx_timeout_reset(adapter); 1238 1239 /* the adapter is about to reset, no point in enabling stuff */ 1240 return true; 1241 } 1242 1243 if (ring_is_xdp(tx_ring)) 1244 return !!budget; 1245 1246 netdev_tx_completed_queue(txring_txq(tx_ring), 1247 total_packets, total_bytes); 1248 1249 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1250 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1251 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1252 /* Make sure that anybody stopping the queue after this 1253 * sees the new next_to_clean. 1254 */ 1255 smp_mb(); 1256 if (__netif_subqueue_stopped(tx_ring->netdev, 1257 tx_ring->queue_index) 1258 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1259 netif_wake_subqueue(tx_ring->netdev, 1260 tx_ring->queue_index); 1261 ++tx_ring->tx_stats.restart_queue; 1262 } 1263 } 1264 1265 return !!budget; 1266 } 1267 1268 #ifdef CONFIG_IXGBE_DCA 1269 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1270 struct ixgbe_ring *tx_ring, 1271 int cpu) 1272 { 1273 struct ixgbe_hw *hw = &adapter->hw; 1274 u32 txctrl = 0; 1275 u16 reg_offset; 1276 1277 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1278 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1279 1280 switch (hw->mac.type) { 1281 case ixgbe_mac_82598EB: 1282 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1283 break; 1284 case ixgbe_mac_82599EB: 1285 case ixgbe_mac_X540: 1286 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1287 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1288 break; 1289 default: 1290 /* for unknown hardware do not write register */ 1291 return; 1292 } 1293 1294 /* 1295 * We can enable relaxed ordering for reads, but not writes when 1296 * DCA is enabled. This is due to a known issue in some chipsets 1297 * which will cause the DCA tag to be cleared. 1298 */ 1299 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1300 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1301 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1302 1303 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1304 } 1305 1306 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1307 struct ixgbe_ring *rx_ring, 1308 int cpu) 1309 { 1310 struct ixgbe_hw *hw = &adapter->hw; 1311 u32 rxctrl = 0; 1312 u8 reg_idx = rx_ring->reg_idx; 1313 1314 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1315 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1316 1317 switch (hw->mac.type) { 1318 case ixgbe_mac_82599EB: 1319 case ixgbe_mac_X540: 1320 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1321 break; 1322 default: 1323 break; 1324 } 1325 1326 /* 1327 * We can enable relaxed ordering for reads, but not writes when 1328 * DCA is enabled. This is due to a known issue in some chipsets 1329 * which will cause the DCA tag to be cleared. 1330 */ 1331 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1332 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1333 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1334 1335 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1336 } 1337 1338 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1339 { 1340 struct ixgbe_adapter *adapter = q_vector->adapter; 1341 struct ixgbe_ring *ring; 1342 int cpu = get_cpu(); 1343 1344 if (q_vector->cpu == cpu) 1345 goto out_no_update; 1346 1347 ixgbe_for_each_ring(ring, q_vector->tx) 1348 ixgbe_update_tx_dca(adapter, ring, cpu); 1349 1350 ixgbe_for_each_ring(ring, q_vector->rx) 1351 ixgbe_update_rx_dca(adapter, ring, cpu); 1352 1353 q_vector->cpu = cpu; 1354 out_no_update: 1355 put_cpu(); 1356 } 1357 1358 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1359 { 1360 int i; 1361 1362 /* always use CB2 mode, difference is masked in the CB driver */ 1363 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1365 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1366 else 1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1368 IXGBE_DCA_CTRL_DCA_DISABLE); 1369 1370 for (i = 0; i < adapter->num_q_vectors; i++) { 1371 adapter->q_vector[i]->cpu = -1; 1372 ixgbe_update_dca(adapter->q_vector[i]); 1373 } 1374 } 1375 1376 static int __ixgbe_notify_dca(struct device *dev, void *data) 1377 { 1378 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1379 unsigned long event = *(unsigned long *)data; 1380 1381 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1382 return 0; 1383 1384 switch (event) { 1385 case DCA_PROVIDER_ADD: 1386 /* if we're already enabled, don't do it again */ 1387 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1388 break; 1389 if (dca_add_requester(dev) == 0) { 1390 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1392 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1393 break; 1394 } 1395 /* fall through - DCA is disabled. */ 1396 case DCA_PROVIDER_REMOVE: 1397 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1398 dca_remove_requester(dev); 1399 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1400 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1401 IXGBE_DCA_CTRL_DCA_DISABLE); 1402 } 1403 break; 1404 } 1405 1406 return 0; 1407 } 1408 1409 #endif /* CONFIG_IXGBE_DCA */ 1410 1411 #define IXGBE_RSS_L4_TYPES_MASK \ 1412 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1413 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1414 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1415 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1416 1417 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1418 union ixgbe_adv_rx_desc *rx_desc, 1419 struct sk_buff *skb) 1420 { 1421 u16 rss_type; 1422 1423 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1424 return; 1425 1426 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1427 IXGBE_RXDADV_RSSTYPE_MASK; 1428 1429 if (!rss_type) 1430 return; 1431 1432 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1433 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1434 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1435 } 1436 1437 #ifdef IXGBE_FCOE 1438 /** 1439 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1440 * @ring: structure containing ring specific data 1441 * @rx_desc: advanced rx descriptor 1442 * 1443 * Returns : true if it is FCoE pkt 1444 */ 1445 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1446 union ixgbe_adv_rx_desc *rx_desc) 1447 { 1448 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1449 1450 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1451 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1452 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1453 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1454 } 1455 1456 #endif /* IXGBE_FCOE */ 1457 /** 1458 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1459 * @ring: structure containing ring specific data 1460 * @rx_desc: current Rx descriptor being processed 1461 * @skb: skb currently being received and modified 1462 **/ 1463 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1464 union ixgbe_adv_rx_desc *rx_desc, 1465 struct sk_buff *skb) 1466 { 1467 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1468 bool encap_pkt = false; 1469 1470 skb_checksum_none_assert(skb); 1471 1472 /* Rx csum disabled */ 1473 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1474 return; 1475 1476 /* check for VXLAN and Geneve packets */ 1477 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1478 encap_pkt = true; 1479 skb->encapsulation = 1; 1480 } 1481 1482 /* if IP and error */ 1483 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1484 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1485 ring->rx_stats.csum_err++; 1486 return; 1487 } 1488 1489 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1490 return; 1491 1492 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1493 /* 1494 * 82599 errata, UDP frames with a 0 checksum can be marked as 1495 * checksum errors. 1496 */ 1497 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1498 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1499 return; 1500 1501 ring->rx_stats.csum_err++; 1502 return; 1503 } 1504 1505 /* It must be a TCP or UDP packet with a valid checksum */ 1506 skb->ip_summed = CHECKSUM_UNNECESSARY; 1507 if (encap_pkt) { 1508 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1509 return; 1510 1511 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1512 skb->ip_summed = CHECKSUM_NONE; 1513 return; 1514 } 1515 /* If we checked the outer header let the stack know */ 1516 skb->csum_level = 1; 1517 } 1518 } 1519 1520 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1521 { 1522 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1523 } 1524 1525 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1526 struct ixgbe_rx_buffer *bi) 1527 { 1528 struct page *page = bi->page; 1529 dma_addr_t dma; 1530 1531 /* since we are recycling buffers we should seldom need to alloc */ 1532 if (likely(page)) 1533 return true; 1534 1535 /* alloc new page for storage */ 1536 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1537 if (unlikely(!page)) { 1538 rx_ring->rx_stats.alloc_rx_page_failed++; 1539 return false; 1540 } 1541 1542 /* map page for use */ 1543 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1544 ixgbe_rx_pg_size(rx_ring), 1545 DMA_FROM_DEVICE, 1546 IXGBE_RX_DMA_ATTR); 1547 1548 /* 1549 * if mapping failed free memory back to system since 1550 * there isn't much point in holding memory we can't use 1551 */ 1552 if (dma_mapping_error(rx_ring->dev, dma)) { 1553 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1554 1555 rx_ring->rx_stats.alloc_rx_page_failed++; 1556 return false; 1557 } 1558 1559 bi->dma = dma; 1560 bi->page = page; 1561 bi->page_offset = ixgbe_rx_offset(rx_ring); 1562 page_ref_add(page, USHRT_MAX - 1); 1563 bi->pagecnt_bias = USHRT_MAX; 1564 rx_ring->rx_stats.alloc_rx_page++; 1565 1566 return true; 1567 } 1568 1569 /** 1570 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1571 * @rx_ring: ring to place buffers on 1572 * @cleaned_count: number of buffers to replace 1573 **/ 1574 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1575 { 1576 union ixgbe_adv_rx_desc *rx_desc; 1577 struct ixgbe_rx_buffer *bi; 1578 u16 i = rx_ring->next_to_use; 1579 u16 bufsz; 1580 1581 /* nothing to do */ 1582 if (!cleaned_count) 1583 return; 1584 1585 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1586 bi = &rx_ring->rx_buffer_info[i]; 1587 i -= rx_ring->count; 1588 1589 bufsz = ixgbe_rx_bufsz(rx_ring); 1590 1591 do { 1592 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1593 break; 1594 1595 /* sync the buffer for use by the device */ 1596 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1597 bi->page_offset, bufsz, 1598 DMA_FROM_DEVICE); 1599 1600 /* 1601 * Refresh the desc even if buffer_addrs didn't change 1602 * because each write-back erases this info. 1603 */ 1604 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1605 1606 rx_desc++; 1607 bi++; 1608 i++; 1609 if (unlikely(!i)) { 1610 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1611 bi = rx_ring->rx_buffer_info; 1612 i -= rx_ring->count; 1613 } 1614 1615 /* clear the length for the next_to_use descriptor */ 1616 rx_desc->wb.upper.length = 0; 1617 1618 cleaned_count--; 1619 } while (cleaned_count); 1620 1621 i += rx_ring->count; 1622 1623 if (rx_ring->next_to_use != i) { 1624 rx_ring->next_to_use = i; 1625 1626 /* update next to alloc since we have filled the ring */ 1627 rx_ring->next_to_alloc = i; 1628 1629 /* Force memory writes to complete before letting h/w 1630 * know there are new descriptors to fetch. (Only 1631 * applicable for weak-ordered memory model archs, 1632 * such as IA-64). 1633 */ 1634 wmb(); 1635 writel(i, rx_ring->tail); 1636 } 1637 } 1638 1639 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1640 struct sk_buff *skb) 1641 { 1642 u16 hdr_len = skb_headlen(skb); 1643 1644 /* set gso_size to avoid messing up TCP MSS */ 1645 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1646 IXGBE_CB(skb)->append_cnt); 1647 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1648 } 1649 1650 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1651 struct sk_buff *skb) 1652 { 1653 /* if append_cnt is 0 then frame is not RSC */ 1654 if (!IXGBE_CB(skb)->append_cnt) 1655 return; 1656 1657 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1658 rx_ring->rx_stats.rsc_flush++; 1659 1660 ixgbe_set_rsc_gso_size(rx_ring, skb); 1661 1662 /* gso_size is computed using append_cnt so always clear it last */ 1663 IXGBE_CB(skb)->append_cnt = 0; 1664 } 1665 1666 /** 1667 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1668 * @rx_ring: rx descriptor ring packet is being transacted on 1669 * @rx_desc: pointer to the EOP Rx descriptor 1670 * @skb: pointer to current skb being populated 1671 * 1672 * This function checks the ring, descriptor, and packet information in 1673 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1674 * other fields within the skb. 1675 **/ 1676 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1677 union ixgbe_adv_rx_desc *rx_desc, 1678 struct sk_buff *skb) 1679 { 1680 struct net_device *dev = rx_ring->netdev; 1681 u32 flags = rx_ring->q_vector->adapter->flags; 1682 1683 ixgbe_update_rsc_stats(rx_ring, skb); 1684 1685 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1686 1687 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1688 1689 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1690 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1691 1692 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1693 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1694 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1695 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1696 } 1697 1698 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1699 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1700 1701 /* record Rx queue, or update MACVLAN statistics */ 1702 if (netif_is_ixgbe(dev)) 1703 skb_record_rx_queue(skb, rx_ring->queue_index); 1704 else 1705 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1706 false); 1707 1708 skb->protocol = eth_type_trans(skb, dev); 1709 } 1710 1711 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1712 struct sk_buff *skb) 1713 { 1714 napi_gro_receive(&q_vector->napi, skb); 1715 } 1716 1717 /** 1718 * ixgbe_is_non_eop - process handling of non-EOP buffers 1719 * @rx_ring: Rx ring being processed 1720 * @rx_desc: Rx descriptor for current buffer 1721 * @skb: Current socket buffer containing buffer in progress 1722 * 1723 * This function updates next to clean. If the buffer is an EOP buffer 1724 * this function exits returning false, otherwise it will place the 1725 * sk_buff in the next buffer to be chained and return true indicating 1726 * that this is in fact a non-EOP buffer. 1727 **/ 1728 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1729 union ixgbe_adv_rx_desc *rx_desc, 1730 struct sk_buff *skb) 1731 { 1732 u32 ntc = rx_ring->next_to_clean + 1; 1733 1734 /* fetch, update, and store next to clean */ 1735 ntc = (ntc < rx_ring->count) ? ntc : 0; 1736 rx_ring->next_to_clean = ntc; 1737 1738 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1739 1740 /* update RSC append count if present */ 1741 if (ring_is_rsc_enabled(rx_ring)) { 1742 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1743 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1744 1745 if (unlikely(rsc_enabled)) { 1746 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1747 1748 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1749 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1750 1751 /* update ntc based on RSC value */ 1752 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1753 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1754 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1755 } 1756 } 1757 1758 /* if we are the last buffer then there is nothing else to do */ 1759 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1760 return false; 1761 1762 /* place skb in next buffer to be received */ 1763 rx_ring->rx_buffer_info[ntc].skb = skb; 1764 rx_ring->rx_stats.non_eop_descs++; 1765 1766 return true; 1767 } 1768 1769 /** 1770 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1771 * @rx_ring: rx descriptor ring packet is being transacted on 1772 * @skb: pointer to current skb being adjusted 1773 * 1774 * This function is an ixgbe specific version of __pskb_pull_tail. The 1775 * main difference between this version and the original function is that 1776 * this function can make several assumptions about the state of things 1777 * that allow for significant optimizations versus the standard function. 1778 * As a result we can do things like drop a frag and maintain an accurate 1779 * truesize for the skb. 1780 */ 1781 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1782 struct sk_buff *skb) 1783 { 1784 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1785 unsigned char *va; 1786 unsigned int pull_len; 1787 1788 /* 1789 * it is valid to use page_address instead of kmap since we are 1790 * working with pages allocated out of the lomem pool per 1791 * alloc_page(GFP_ATOMIC) 1792 */ 1793 va = skb_frag_address(frag); 1794 1795 /* 1796 * we need the header to contain the greater of either ETH_HLEN or 1797 * 60 bytes if the skb->len is less than 60 for skb_pad. 1798 */ 1799 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1800 1801 /* align pull length to size of long to optimize memcpy performance */ 1802 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1803 1804 /* update all of the pointers */ 1805 skb_frag_size_sub(frag, pull_len); 1806 frag->page_offset += pull_len; 1807 skb->data_len -= pull_len; 1808 skb->tail += pull_len; 1809 } 1810 1811 /** 1812 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1813 * @rx_ring: rx descriptor ring packet is being transacted on 1814 * @skb: pointer to current skb being updated 1815 * 1816 * This function provides a basic DMA sync up for the first fragment of an 1817 * skb. The reason for doing this is that the first fragment cannot be 1818 * unmapped until we have reached the end of packet descriptor for a buffer 1819 * chain. 1820 */ 1821 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1822 struct sk_buff *skb) 1823 { 1824 /* if the page was released unmap it, else just sync our portion */ 1825 if (unlikely(IXGBE_CB(skb)->page_released)) { 1826 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1827 ixgbe_rx_pg_size(rx_ring), 1828 DMA_FROM_DEVICE, 1829 IXGBE_RX_DMA_ATTR); 1830 } else if (ring_uses_build_skb(rx_ring)) { 1831 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1832 1833 dma_sync_single_range_for_cpu(rx_ring->dev, 1834 IXGBE_CB(skb)->dma, 1835 offset, 1836 skb_headlen(skb), 1837 DMA_FROM_DEVICE); 1838 } else { 1839 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1840 1841 dma_sync_single_range_for_cpu(rx_ring->dev, 1842 IXGBE_CB(skb)->dma, 1843 frag->page_offset, 1844 skb_frag_size(frag), 1845 DMA_FROM_DEVICE); 1846 } 1847 } 1848 1849 /** 1850 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1851 * @rx_ring: rx descriptor ring packet is being transacted on 1852 * @rx_desc: pointer to the EOP Rx descriptor 1853 * @skb: pointer to current skb being fixed 1854 * 1855 * Check if the skb is valid in the XDP case it will be an error pointer. 1856 * Return true in this case to abort processing and advance to next 1857 * descriptor. 1858 * 1859 * Check for corrupted packet headers caused by senders on the local L2 1860 * embedded NIC switch not setting up their Tx Descriptors right. These 1861 * should be very rare. 1862 * 1863 * Also address the case where we are pulling data in on pages only 1864 * and as such no data is present in the skb header. 1865 * 1866 * In addition if skb is not at least 60 bytes we need to pad it so that 1867 * it is large enough to qualify as a valid Ethernet frame. 1868 * 1869 * Returns true if an error was encountered and skb was freed. 1870 **/ 1871 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1872 union ixgbe_adv_rx_desc *rx_desc, 1873 struct sk_buff *skb) 1874 { 1875 struct net_device *netdev = rx_ring->netdev; 1876 1877 /* XDP packets use error pointer so abort at this point */ 1878 if (IS_ERR(skb)) 1879 return true; 1880 1881 /* Verify netdev is present, and that packet does not have any 1882 * errors that would be unacceptable to the netdev. 1883 */ 1884 if (!netdev || 1885 (unlikely(ixgbe_test_staterr(rx_desc, 1886 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1887 !(netdev->features & NETIF_F_RXALL)))) { 1888 dev_kfree_skb_any(skb); 1889 return true; 1890 } 1891 1892 /* place header in linear portion of buffer */ 1893 if (!skb_headlen(skb)) 1894 ixgbe_pull_tail(rx_ring, skb); 1895 1896 #ifdef IXGBE_FCOE 1897 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1898 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1899 return false; 1900 1901 #endif 1902 /* if eth_skb_pad returns an error the skb was freed */ 1903 if (eth_skb_pad(skb)) 1904 return true; 1905 1906 return false; 1907 } 1908 1909 /** 1910 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1911 * @rx_ring: rx descriptor ring to store buffers on 1912 * @old_buff: donor buffer to have page reused 1913 * 1914 * Synchronizes page for reuse by the adapter 1915 **/ 1916 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1917 struct ixgbe_rx_buffer *old_buff) 1918 { 1919 struct ixgbe_rx_buffer *new_buff; 1920 u16 nta = rx_ring->next_to_alloc; 1921 1922 new_buff = &rx_ring->rx_buffer_info[nta]; 1923 1924 /* update, and store next to alloc */ 1925 nta++; 1926 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1927 1928 /* Transfer page from old buffer to new buffer. 1929 * Move each member individually to avoid possible store 1930 * forwarding stalls and unnecessary copy of skb. 1931 */ 1932 new_buff->dma = old_buff->dma; 1933 new_buff->page = old_buff->page; 1934 new_buff->page_offset = old_buff->page_offset; 1935 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1936 } 1937 1938 static inline bool ixgbe_page_is_reserved(struct page *page) 1939 { 1940 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1941 } 1942 1943 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1944 { 1945 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1946 struct page *page = rx_buffer->page; 1947 1948 /* avoid re-using remote pages */ 1949 if (unlikely(ixgbe_page_is_reserved(page))) 1950 return false; 1951 1952 #if (PAGE_SIZE < 8192) 1953 /* if we are only owner of page we can reuse it */ 1954 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1955 return false; 1956 #else 1957 /* The last offset is a bit aggressive in that we assume the 1958 * worst case of FCoE being enabled and using a 3K buffer. 1959 * However this should have minimal impact as the 1K extra is 1960 * still less than one buffer in size. 1961 */ 1962 #define IXGBE_LAST_OFFSET \ 1963 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1964 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1965 return false; 1966 #endif 1967 1968 /* If we have drained the page fragment pool we need to update 1969 * the pagecnt_bias and page count so that we fully restock the 1970 * number of references the driver holds. 1971 */ 1972 if (unlikely(pagecnt_bias == 1)) { 1973 page_ref_add(page, USHRT_MAX - 1); 1974 rx_buffer->pagecnt_bias = USHRT_MAX; 1975 } 1976 1977 return true; 1978 } 1979 1980 /** 1981 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1982 * @rx_ring: rx descriptor ring to transact packets on 1983 * @rx_buffer: buffer containing page to add 1984 * @skb: sk_buff to place the data into 1985 * @size: size of data in rx_buffer 1986 * 1987 * This function will add the data contained in rx_buffer->page to the skb. 1988 * This is done either through a direct copy if the data in the buffer is 1989 * less than the skb header size, otherwise it will just attach the page as 1990 * a frag to the skb. 1991 * 1992 * The function will then update the page offset if necessary and return 1993 * true if the buffer can be reused by the adapter. 1994 **/ 1995 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1996 struct ixgbe_rx_buffer *rx_buffer, 1997 struct sk_buff *skb, 1998 unsigned int size) 1999 { 2000 #if (PAGE_SIZE < 8192) 2001 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2002 #else 2003 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2004 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2005 SKB_DATA_ALIGN(size); 2006 #endif 2007 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2008 rx_buffer->page_offset, size, truesize); 2009 #if (PAGE_SIZE < 8192) 2010 rx_buffer->page_offset ^= truesize; 2011 #else 2012 rx_buffer->page_offset += truesize; 2013 #endif 2014 } 2015 2016 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2017 union ixgbe_adv_rx_desc *rx_desc, 2018 struct sk_buff **skb, 2019 const unsigned int size) 2020 { 2021 struct ixgbe_rx_buffer *rx_buffer; 2022 2023 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2024 prefetchw(rx_buffer->page); 2025 *skb = rx_buffer->skb; 2026 2027 /* Delay unmapping of the first packet. It carries the header 2028 * information, HW may still access the header after the writeback. 2029 * Only unmap it when EOP is reached 2030 */ 2031 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2032 if (!*skb) 2033 goto skip_sync; 2034 } else { 2035 if (*skb) 2036 ixgbe_dma_sync_frag(rx_ring, *skb); 2037 } 2038 2039 /* we are reusing so sync this buffer for CPU use */ 2040 dma_sync_single_range_for_cpu(rx_ring->dev, 2041 rx_buffer->dma, 2042 rx_buffer->page_offset, 2043 size, 2044 DMA_FROM_DEVICE); 2045 skip_sync: 2046 rx_buffer->pagecnt_bias--; 2047 2048 return rx_buffer; 2049 } 2050 2051 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2052 struct ixgbe_rx_buffer *rx_buffer, 2053 struct sk_buff *skb) 2054 { 2055 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2056 /* hand second half of page back to the ring */ 2057 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2058 } else { 2059 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2060 /* the page has been released from the ring */ 2061 IXGBE_CB(skb)->page_released = true; 2062 } else { 2063 /* we are not reusing the buffer so unmap it */ 2064 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2065 ixgbe_rx_pg_size(rx_ring), 2066 DMA_FROM_DEVICE, 2067 IXGBE_RX_DMA_ATTR); 2068 } 2069 __page_frag_cache_drain(rx_buffer->page, 2070 rx_buffer->pagecnt_bias); 2071 } 2072 2073 /* clear contents of rx_buffer */ 2074 rx_buffer->page = NULL; 2075 rx_buffer->skb = NULL; 2076 } 2077 2078 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2079 struct ixgbe_rx_buffer *rx_buffer, 2080 struct xdp_buff *xdp, 2081 union ixgbe_adv_rx_desc *rx_desc) 2082 { 2083 unsigned int size = xdp->data_end - xdp->data; 2084 #if (PAGE_SIZE < 8192) 2085 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2086 #else 2087 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2088 xdp->data_hard_start); 2089 #endif 2090 struct sk_buff *skb; 2091 2092 /* prefetch first cache line of first page */ 2093 prefetch(xdp->data); 2094 #if L1_CACHE_BYTES < 128 2095 prefetch(xdp->data + L1_CACHE_BYTES); 2096 #endif 2097 /* Note, we get here by enabling legacy-rx via: 2098 * 2099 * ethtool --set-priv-flags <dev> legacy-rx on 2100 * 2101 * In this mode, we currently get 0 extra XDP headroom as 2102 * opposed to having legacy-rx off, where we process XDP 2103 * packets going to stack via ixgbe_build_skb(). The latter 2104 * provides us currently with 192 bytes of headroom. 2105 * 2106 * For ixgbe_construct_skb() mode it means that the 2107 * xdp->data_meta will always point to xdp->data, since 2108 * the helper cannot expand the head. Should this ever 2109 * change in future for legacy-rx mode on, then lets also 2110 * add xdp->data_meta handling here. 2111 */ 2112 2113 /* allocate a skb to store the frags */ 2114 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2115 if (unlikely(!skb)) 2116 return NULL; 2117 2118 if (size > IXGBE_RX_HDR_SIZE) { 2119 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2120 IXGBE_CB(skb)->dma = rx_buffer->dma; 2121 2122 skb_add_rx_frag(skb, 0, rx_buffer->page, 2123 xdp->data - page_address(rx_buffer->page), 2124 size, truesize); 2125 #if (PAGE_SIZE < 8192) 2126 rx_buffer->page_offset ^= truesize; 2127 #else 2128 rx_buffer->page_offset += truesize; 2129 #endif 2130 } else { 2131 memcpy(__skb_put(skb, size), 2132 xdp->data, ALIGN(size, sizeof(long))); 2133 rx_buffer->pagecnt_bias++; 2134 } 2135 2136 return skb; 2137 } 2138 2139 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2140 struct ixgbe_rx_buffer *rx_buffer, 2141 struct xdp_buff *xdp, 2142 union ixgbe_adv_rx_desc *rx_desc) 2143 { 2144 unsigned int metasize = xdp->data - xdp->data_meta; 2145 #if (PAGE_SIZE < 8192) 2146 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2147 #else 2148 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2149 SKB_DATA_ALIGN(xdp->data_end - 2150 xdp->data_hard_start); 2151 #endif 2152 struct sk_buff *skb; 2153 2154 /* Prefetch first cache line of first page. If xdp->data_meta 2155 * is unused, this points extactly as xdp->data, otherwise we 2156 * likely have a consumer accessing first few bytes of meta 2157 * data, and then actual data. 2158 */ 2159 prefetch(xdp->data_meta); 2160 #if L1_CACHE_BYTES < 128 2161 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2162 #endif 2163 2164 /* build an skb to around the page buffer */ 2165 skb = build_skb(xdp->data_hard_start, truesize); 2166 if (unlikely(!skb)) 2167 return NULL; 2168 2169 /* update pointers within the skb to store the data */ 2170 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2171 __skb_put(skb, xdp->data_end - xdp->data); 2172 if (metasize) 2173 skb_metadata_set(skb, metasize); 2174 2175 /* record DMA address if this is the start of a chain of buffers */ 2176 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2177 IXGBE_CB(skb)->dma = rx_buffer->dma; 2178 2179 /* update buffer offset */ 2180 #if (PAGE_SIZE < 8192) 2181 rx_buffer->page_offset ^= truesize; 2182 #else 2183 rx_buffer->page_offset += truesize; 2184 #endif 2185 2186 return skb; 2187 } 2188 2189 #define IXGBE_XDP_PASS 0 2190 #define IXGBE_XDP_CONSUMED BIT(0) 2191 #define IXGBE_XDP_TX BIT(1) 2192 #define IXGBE_XDP_REDIR BIT(2) 2193 2194 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2195 struct xdp_frame *xdpf); 2196 2197 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2198 struct ixgbe_ring *rx_ring, 2199 struct xdp_buff *xdp) 2200 { 2201 int err, result = IXGBE_XDP_PASS; 2202 struct bpf_prog *xdp_prog; 2203 struct xdp_frame *xdpf; 2204 u32 act; 2205 2206 rcu_read_lock(); 2207 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2208 2209 if (!xdp_prog) 2210 goto xdp_out; 2211 2212 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2213 2214 act = bpf_prog_run_xdp(xdp_prog, xdp); 2215 switch (act) { 2216 case XDP_PASS: 2217 break; 2218 case XDP_TX: 2219 xdpf = convert_to_xdp_frame(xdp); 2220 if (unlikely(!xdpf)) { 2221 result = IXGBE_XDP_CONSUMED; 2222 break; 2223 } 2224 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2225 break; 2226 case XDP_REDIRECT: 2227 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2228 if (!err) 2229 result = IXGBE_XDP_REDIR; 2230 else 2231 result = IXGBE_XDP_CONSUMED; 2232 break; 2233 default: 2234 bpf_warn_invalid_xdp_action(act); 2235 /* fallthrough */ 2236 case XDP_ABORTED: 2237 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2238 /* fallthrough -- handle aborts by dropping packet */ 2239 case XDP_DROP: 2240 result = IXGBE_XDP_CONSUMED; 2241 break; 2242 } 2243 xdp_out: 2244 rcu_read_unlock(); 2245 return ERR_PTR(-result); 2246 } 2247 2248 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2249 struct ixgbe_rx_buffer *rx_buffer, 2250 unsigned int size) 2251 { 2252 #if (PAGE_SIZE < 8192) 2253 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2254 2255 rx_buffer->page_offset ^= truesize; 2256 #else 2257 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2258 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2259 SKB_DATA_ALIGN(size); 2260 2261 rx_buffer->page_offset += truesize; 2262 #endif 2263 } 2264 2265 /** 2266 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2267 * @q_vector: structure containing interrupt and ring information 2268 * @rx_ring: rx descriptor ring to transact packets on 2269 * @budget: Total limit on number of packets to process 2270 * 2271 * This function provides a "bounce buffer" approach to Rx interrupt 2272 * processing. The advantage to this is that on systems that have 2273 * expensive overhead for IOMMU access this provides a means of avoiding 2274 * it by maintaining the mapping of the page to the syste. 2275 * 2276 * Returns amount of work completed 2277 **/ 2278 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2279 struct ixgbe_ring *rx_ring, 2280 const int budget) 2281 { 2282 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2283 struct ixgbe_adapter *adapter = q_vector->adapter; 2284 #ifdef IXGBE_FCOE 2285 int ddp_bytes; 2286 unsigned int mss = 0; 2287 #endif /* IXGBE_FCOE */ 2288 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2289 unsigned int xdp_xmit = 0; 2290 struct xdp_buff xdp; 2291 2292 xdp.rxq = &rx_ring->xdp_rxq; 2293 2294 while (likely(total_rx_packets < budget)) { 2295 union ixgbe_adv_rx_desc *rx_desc; 2296 struct ixgbe_rx_buffer *rx_buffer; 2297 struct sk_buff *skb; 2298 unsigned int size; 2299 2300 /* return some buffers to hardware, one at a time is too slow */ 2301 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2302 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2303 cleaned_count = 0; 2304 } 2305 2306 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2307 size = le16_to_cpu(rx_desc->wb.upper.length); 2308 if (!size) 2309 break; 2310 2311 /* This memory barrier is needed to keep us from reading 2312 * any other fields out of the rx_desc until we know the 2313 * descriptor has been written back 2314 */ 2315 dma_rmb(); 2316 2317 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2318 2319 /* retrieve a buffer from the ring */ 2320 if (!skb) { 2321 xdp.data = page_address(rx_buffer->page) + 2322 rx_buffer->page_offset; 2323 xdp.data_meta = xdp.data; 2324 xdp.data_hard_start = xdp.data - 2325 ixgbe_rx_offset(rx_ring); 2326 xdp.data_end = xdp.data + size; 2327 2328 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2329 } 2330 2331 if (IS_ERR(skb)) { 2332 unsigned int xdp_res = -PTR_ERR(skb); 2333 2334 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2335 xdp_xmit |= xdp_res; 2336 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2337 } else { 2338 rx_buffer->pagecnt_bias++; 2339 } 2340 total_rx_packets++; 2341 total_rx_bytes += size; 2342 } else if (skb) { 2343 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2344 } else if (ring_uses_build_skb(rx_ring)) { 2345 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2346 &xdp, rx_desc); 2347 } else { 2348 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2349 &xdp, rx_desc); 2350 } 2351 2352 /* exit if we failed to retrieve a buffer */ 2353 if (!skb) { 2354 rx_ring->rx_stats.alloc_rx_buff_failed++; 2355 rx_buffer->pagecnt_bias++; 2356 break; 2357 } 2358 2359 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2360 cleaned_count++; 2361 2362 /* place incomplete frames back on ring for completion */ 2363 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2364 continue; 2365 2366 /* verify the packet layout is correct */ 2367 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2368 continue; 2369 2370 /* probably a little skewed due to removing CRC */ 2371 total_rx_bytes += skb->len; 2372 2373 /* populate checksum, timestamp, VLAN, and protocol */ 2374 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2375 2376 #ifdef IXGBE_FCOE 2377 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2378 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2379 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2380 /* include DDPed FCoE data */ 2381 if (ddp_bytes > 0) { 2382 if (!mss) { 2383 mss = rx_ring->netdev->mtu - 2384 sizeof(struct fcoe_hdr) - 2385 sizeof(struct fc_frame_header) - 2386 sizeof(struct fcoe_crc_eof); 2387 if (mss > 512) 2388 mss &= ~511; 2389 } 2390 total_rx_bytes += ddp_bytes; 2391 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2392 mss); 2393 } 2394 if (!ddp_bytes) { 2395 dev_kfree_skb_any(skb); 2396 continue; 2397 } 2398 } 2399 2400 #endif /* IXGBE_FCOE */ 2401 ixgbe_rx_skb(q_vector, skb); 2402 2403 /* update budget accounting */ 2404 total_rx_packets++; 2405 } 2406 2407 if (xdp_xmit & IXGBE_XDP_REDIR) 2408 xdp_do_flush_map(); 2409 2410 if (xdp_xmit & IXGBE_XDP_TX) { 2411 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2412 2413 /* Force memory writes to complete before letting h/w 2414 * know there are new descriptors to fetch. 2415 */ 2416 wmb(); 2417 writel(ring->next_to_use, ring->tail); 2418 } 2419 2420 u64_stats_update_begin(&rx_ring->syncp); 2421 rx_ring->stats.packets += total_rx_packets; 2422 rx_ring->stats.bytes += total_rx_bytes; 2423 u64_stats_update_end(&rx_ring->syncp); 2424 q_vector->rx.total_packets += total_rx_packets; 2425 q_vector->rx.total_bytes += total_rx_bytes; 2426 2427 return total_rx_packets; 2428 } 2429 2430 /** 2431 * ixgbe_configure_msix - Configure MSI-X hardware 2432 * @adapter: board private structure 2433 * 2434 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2435 * interrupts. 2436 **/ 2437 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2438 { 2439 struct ixgbe_q_vector *q_vector; 2440 int v_idx; 2441 u32 mask; 2442 2443 /* Populate MSIX to EITR Select */ 2444 if (adapter->num_vfs > 32) { 2445 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2446 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2447 } 2448 2449 /* 2450 * Populate the IVAR table and set the ITR values to the 2451 * corresponding register. 2452 */ 2453 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2454 struct ixgbe_ring *ring; 2455 q_vector = adapter->q_vector[v_idx]; 2456 2457 ixgbe_for_each_ring(ring, q_vector->rx) 2458 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2459 2460 ixgbe_for_each_ring(ring, q_vector->tx) 2461 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2462 2463 ixgbe_write_eitr(q_vector); 2464 } 2465 2466 switch (adapter->hw.mac.type) { 2467 case ixgbe_mac_82598EB: 2468 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2469 v_idx); 2470 break; 2471 case ixgbe_mac_82599EB: 2472 case ixgbe_mac_X540: 2473 case ixgbe_mac_X550: 2474 case ixgbe_mac_X550EM_x: 2475 case ixgbe_mac_x550em_a: 2476 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2477 break; 2478 default: 2479 break; 2480 } 2481 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2482 2483 /* set up to autoclear timer, and the vectors */ 2484 mask = IXGBE_EIMS_ENABLE_MASK; 2485 mask &= ~(IXGBE_EIMS_OTHER | 2486 IXGBE_EIMS_MAILBOX | 2487 IXGBE_EIMS_LSC); 2488 2489 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2490 } 2491 2492 /** 2493 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2494 * @q_vector: structure containing interrupt and ring information 2495 * @ring_container: structure containing ring performance data 2496 * 2497 * Stores a new ITR value based on packets and byte 2498 * counts during the last interrupt. The advantage of per interrupt 2499 * computation is faster updates and more accurate ITR for the current 2500 * traffic pattern. Constants in this function were computed 2501 * based on theoretical maximum wire speed and thresholds were set based 2502 * on testing data as well as attempting to minimize response time 2503 * while increasing bulk throughput. 2504 **/ 2505 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2506 struct ixgbe_ring_container *ring_container) 2507 { 2508 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2509 IXGBE_ITR_ADAPTIVE_LATENCY; 2510 unsigned int avg_wire_size, packets, bytes; 2511 unsigned long next_update = jiffies; 2512 2513 /* If we don't have any rings just leave ourselves set for maximum 2514 * possible latency so we take ourselves out of the equation. 2515 */ 2516 if (!ring_container->ring) 2517 return; 2518 2519 /* If we didn't update within up to 1 - 2 jiffies we can assume 2520 * that either packets are coming in so slow there hasn't been 2521 * any work, or that there is so much work that NAPI is dealing 2522 * with interrupt moderation and we don't need to do anything. 2523 */ 2524 if (time_after(next_update, ring_container->next_update)) 2525 goto clear_counts; 2526 2527 packets = ring_container->total_packets; 2528 2529 /* We have no packets to actually measure against. This means 2530 * either one of the other queues on this vector is active or 2531 * we are a Tx queue doing TSO with too high of an interrupt rate. 2532 * 2533 * When this occurs just tick up our delay by the minimum value 2534 * and hope that this extra delay will prevent us from being called 2535 * without any work on our queue. 2536 */ 2537 if (!packets) { 2538 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2539 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2540 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2541 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2542 goto clear_counts; 2543 } 2544 2545 bytes = ring_container->total_bytes; 2546 2547 /* If packets are less than 4 or bytes are less than 9000 assume 2548 * insufficient data to use bulk rate limiting approach. We are 2549 * likely latency driven. 2550 */ 2551 if (packets < 4 && bytes < 9000) { 2552 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2553 goto adjust_by_size; 2554 } 2555 2556 /* Between 4 and 48 we can assume that our current interrupt delay 2557 * is only slightly too low. As such we should increase it by a small 2558 * fixed amount. 2559 */ 2560 if (packets < 48) { 2561 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2562 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2563 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2564 goto clear_counts; 2565 } 2566 2567 /* Between 48 and 96 is our "goldilocks" zone where we are working 2568 * out "just right". Just report that our current ITR is good for us. 2569 */ 2570 if (packets < 96) { 2571 itr = q_vector->itr >> 2; 2572 goto clear_counts; 2573 } 2574 2575 /* If packet count is 96 or greater we are likely looking at a slight 2576 * overrun of the delay we want. Try halving our delay to see if that 2577 * will cut the number of packets in half per interrupt. 2578 */ 2579 if (packets < 256) { 2580 itr = q_vector->itr >> 3; 2581 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2582 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2583 goto clear_counts; 2584 } 2585 2586 /* The paths below assume we are dealing with a bulk ITR since number 2587 * of packets is 256 or greater. We are just going to have to compute 2588 * a value and try to bring the count under control, though for smaller 2589 * packet sizes there isn't much we can do as NAPI polling will likely 2590 * be kicking in sooner rather than later. 2591 */ 2592 itr = IXGBE_ITR_ADAPTIVE_BULK; 2593 2594 adjust_by_size: 2595 /* If packet counts are 256 or greater we can assume we have a gross 2596 * overestimation of what the rate should be. Instead of trying to fine 2597 * tune it just use the formula below to try and dial in an exact value 2598 * give the current packet size of the frame. 2599 */ 2600 avg_wire_size = bytes / packets; 2601 2602 /* The following is a crude approximation of: 2603 * wmem_default / (size + overhead) = desired_pkts_per_int 2604 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2605 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2606 * 2607 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2608 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2609 * formula down to 2610 * 2611 * (170 * (size + 24)) / (size + 640) = ITR 2612 * 2613 * We first do some math on the packet size and then finally bitshift 2614 * by 8 after rounding up. We also have to account for PCIe link speed 2615 * difference as ITR scales based on this. 2616 */ 2617 if (avg_wire_size <= 60) { 2618 /* Start at 50k ints/sec */ 2619 avg_wire_size = 5120; 2620 } else if (avg_wire_size <= 316) { 2621 /* 50K ints/sec to 16K ints/sec */ 2622 avg_wire_size *= 40; 2623 avg_wire_size += 2720; 2624 } else if (avg_wire_size <= 1084) { 2625 /* 16K ints/sec to 9.2K ints/sec */ 2626 avg_wire_size *= 15; 2627 avg_wire_size += 11452; 2628 } else if (avg_wire_size <= 1980) { 2629 /* 9.2K ints/sec to 8K ints/sec */ 2630 avg_wire_size *= 5; 2631 avg_wire_size += 22420; 2632 } else { 2633 /* plateau at a limit of 8K ints/sec */ 2634 avg_wire_size = 32256; 2635 } 2636 2637 /* If we are in low latency mode half our delay which doubles the rate 2638 * to somewhere between 100K to 16K ints/sec 2639 */ 2640 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2641 avg_wire_size >>= 1; 2642 2643 /* Resultant value is 256 times larger than it needs to be. This 2644 * gives us room to adjust the value as needed to either increase 2645 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2646 * 2647 * Use addition as we have already recorded the new latency flag 2648 * for the ITR value. 2649 */ 2650 switch (q_vector->adapter->link_speed) { 2651 case IXGBE_LINK_SPEED_10GB_FULL: 2652 case IXGBE_LINK_SPEED_100_FULL: 2653 default: 2654 itr += DIV_ROUND_UP(avg_wire_size, 2655 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2656 IXGBE_ITR_ADAPTIVE_MIN_INC; 2657 break; 2658 case IXGBE_LINK_SPEED_2_5GB_FULL: 2659 case IXGBE_LINK_SPEED_1GB_FULL: 2660 case IXGBE_LINK_SPEED_10_FULL: 2661 itr += DIV_ROUND_UP(avg_wire_size, 2662 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2663 IXGBE_ITR_ADAPTIVE_MIN_INC; 2664 break; 2665 } 2666 2667 clear_counts: 2668 /* write back value */ 2669 ring_container->itr = itr; 2670 2671 /* next update should occur within next jiffy */ 2672 ring_container->next_update = next_update + 1; 2673 2674 ring_container->total_bytes = 0; 2675 ring_container->total_packets = 0; 2676 } 2677 2678 /** 2679 * ixgbe_write_eitr - write EITR register in hardware specific way 2680 * @q_vector: structure containing interrupt and ring information 2681 * 2682 * This function is made to be called by ethtool and by the driver 2683 * when it needs to update EITR registers at runtime. Hardware 2684 * specific quirks/differences are taken care of here. 2685 */ 2686 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2687 { 2688 struct ixgbe_adapter *adapter = q_vector->adapter; 2689 struct ixgbe_hw *hw = &adapter->hw; 2690 int v_idx = q_vector->v_idx; 2691 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2692 2693 switch (adapter->hw.mac.type) { 2694 case ixgbe_mac_82598EB: 2695 /* must write high and low 16 bits to reset counter */ 2696 itr_reg |= (itr_reg << 16); 2697 break; 2698 case ixgbe_mac_82599EB: 2699 case ixgbe_mac_X540: 2700 case ixgbe_mac_X550: 2701 case ixgbe_mac_X550EM_x: 2702 case ixgbe_mac_x550em_a: 2703 /* 2704 * set the WDIS bit to not clear the timer bits and cause an 2705 * immediate assertion of the interrupt 2706 */ 2707 itr_reg |= IXGBE_EITR_CNT_WDIS; 2708 break; 2709 default: 2710 break; 2711 } 2712 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2713 } 2714 2715 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2716 { 2717 u32 new_itr; 2718 2719 ixgbe_update_itr(q_vector, &q_vector->tx); 2720 ixgbe_update_itr(q_vector, &q_vector->rx); 2721 2722 /* use the smallest value of new ITR delay calculations */ 2723 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2724 2725 /* Clear latency flag if set, shift into correct position */ 2726 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2727 new_itr <<= 2; 2728 2729 if (new_itr != q_vector->itr) { 2730 /* save the algorithm value here */ 2731 q_vector->itr = new_itr; 2732 2733 ixgbe_write_eitr(q_vector); 2734 } 2735 } 2736 2737 /** 2738 * ixgbe_check_overtemp_subtask - check for over temperature 2739 * @adapter: pointer to adapter 2740 **/ 2741 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2742 { 2743 struct ixgbe_hw *hw = &adapter->hw; 2744 u32 eicr = adapter->interrupt_event; 2745 s32 rc; 2746 2747 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2748 return; 2749 2750 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2751 return; 2752 2753 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2754 2755 switch (hw->device_id) { 2756 case IXGBE_DEV_ID_82599_T3_LOM: 2757 /* 2758 * Since the warning interrupt is for both ports 2759 * we don't have to check if: 2760 * - This interrupt wasn't for our port. 2761 * - We may have missed the interrupt so always have to 2762 * check if we got a LSC 2763 */ 2764 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2765 !(eicr & IXGBE_EICR_LSC)) 2766 return; 2767 2768 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2769 u32 speed; 2770 bool link_up = false; 2771 2772 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2773 2774 if (link_up) 2775 return; 2776 } 2777 2778 /* Check if this is not due to overtemp */ 2779 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2780 return; 2781 2782 break; 2783 case IXGBE_DEV_ID_X550EM_A_1G_T: 2784 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2785 rc = hw->phy.ops.check_overtemp(hw); 2786 if (rc != IXGBE_ERR_OVERTEMP) 2787 return; 2788 break; 2789 default: 2790 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2791 return; 2792 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2793 return; 2794 break; 2795 } 2796 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2797 2798 adapter->interrupt_event = 0; 2799 } 2800 2801 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2802 { 2803 struct ixgbe_hw *hw = &adapter->hw; 2804 2805 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2806 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2807 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2808 /* write to clear the interrupt */ 2809 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2810 } 2811 } 2812 2813 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2814 { 2815 struct ixgbe_hw *hw = &adapter->hw; 2816 2817 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2818 return; 2819 2820 switch (adapter->hw.mac.type) { 2821 case ixgbe_mac_82599EB: 2822 /* 2823 * Need to check link state so complete overtemp check 2824 * on service task 2825 */ 2826 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2827 (eicr & IXGBE_EICR_LSC)) && 2828 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2829 adapter->interrupt_event = eicr; 2830 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2831 ixgbe_service_event_schedule(adapter); 2832 return; 2833 } 2834 return; 2835 case ixgbe_mac_x550em_a: 2836 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2837 adapter->interrupt_event = eicr; 2838 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2839 ixgbe_service_event_schedule(adapter); 2840 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2841 IXGBE_EICR_GPI_SDP0_X550EM_a); 2842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2843 IXGBE_EICR_GPI_SDP0_X550EM_a); 2844 } 2845 return; 2846 case ixgbe_mac_X550: 2847 case ixgbe_mac_X540: 2848 if (!(eicr & IXGBE_EICR_TS)) 2849 return; 2850 break; 2851 default: 2852 return; 2853 } 2854 2855 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2856 } 2857 2858 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2859 { 2860 switch (hw->mac.type) { 2861 case ixgbe_mac_82598EB: 2862 if (hw->phy.type == ixgbe_phy_nl) 2863 return true; 2864 return false; 2865 case ixgbe_mac_82599EB: 2866 case ixgbe_mac_X550EM_x: 2867 case ixgbe_mac_x550em_a: 2868 switch (hw->mac.ops.get_media_type(hw)) { 2869 case ixgbe_media_type_fiber: 2870 case ixgbe_media_type_fiber_qsfp: 2871 return true; 2872 default: 2873 return false; 2874 } 2875 default: 2876 return false; 2877 } 2878 } 2879 2880 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2881 { 2882 struct ixgbe_hw *hw = &adapter->hw; 2883 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2884 2885 if (!ixgbe_is_sfp(hw)) 2886 return; 2887 2888 /* Later MAC's use different SDP */ 2889 if (hw->mac.type >= ixgbe_mac_X540) 2890 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2891 2892 if (eicr & eicr_mask) { 2893 /* Clear the interrupt */ 2894 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2895 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2896 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2897 adapter->sfp_poll_time = 0; 2898 ixgbe_service_event_schedule(adapter); 2899 } 2900 } 2901 2902 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2903 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2904 /* Clear the interrupt */ 2905 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2906 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2907 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2908 ixgbe_service_event_schedule(adapter); 2909 } 2910 } 2911 } 2912 2913 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2914 { 2915 struct ixgbe_hw *hw = &adapter->hw; 2916 2917 adapter->lsc_int++; 2918 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2919 adapter->link_check_timeout = jiffies; 2920 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2921 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2922 IXGBE_WRITE_FLUSH(hw); 2923 ixgbe_service_event_schedule(adapter); 2924 } 2925 } 2926 2927 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2928 u64 qmask) 2929 { 2930 u32 mask; 2931 struct ixgbe_hw *hw = &adapter->hw; 2932 2933 switch (hw->mac.type) { 2934 case ixgbe_mac_82598EB: 2935 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2936 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2937 break; 2938 case ixgbe_mac_82599EB: 2939 case ixgbe_mac_X540: 2940 case ixgbe_mac_X550: 2941 case ixgbe_mac_X550EM_x: 2942 case ixgbe_mac_x550em_a: 2943 mask = (qmask & 0xFFFFFFFF); 2944 if (mask) 2945 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2946 mask = (qmask >> 32); 2947 if (mask) 2948 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2949 break; 2950 default: 2951 break; 2952 } 2953 /* skip the flush */ 2954 } 2955 2956 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2957 u64 qmask) 2958 { 2959 u32 mask; 2960 struct ixgbe_hw *hw = &adapter->hw; 2961 2962 switch (hw->mac.type) { 2963 case ixgbe_mac_82598EB: 2964 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2965 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2966 break; 2967 case ixgbe_mac_82599EB: 2968 case ixgbe_mac_X540: 2969 case ixgbe_mac_X550: 2970 case ixgbe_mac_X550EM_x: 2971 case ixgbe_mac_x550em_a: 2972 mask = (qmask & 0xFFFFFFFF); 2973 if (mask) 2974 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2975 mask = (qmask >> 32); 2976 if (mask) 2977 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2978 break; 2979 default: 2980 break; 2981 } 2982 /* skip the flush */ 2983 } 2984 2985 /** 2986 * ixgbe_irq_enable - Enable default interrupt generation settings 2987 * @adapter: board private structure 2988 * @queues: enable irqs for queues 2989 * @flush: flush register write 2990 **/ 2991 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2992 bool flush) 2993 { 2994 struct ixgbe_hw *hw = &adapter->hw; 2995 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2996 2997 /* don't reenable LSC while waiting for link */ 2998 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2999 mask &= ~IXGBE_EIMS_LSC; 3000 3001 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3002 switch (adapter->hw.mac.type) { 3003 case ixgbe_mac_82599EB: 3004 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3005 break; 3006 case ixgbe_mac_X540: 3007 case ixgbe_mac_X550: 3008 case ixgbe_mac_X550EM_x: 3009 case ixgbe_mac_x550em_a: 3010 mask |= IXGBE_EIMS_TS; 3011 break; 3012 default: 3013 break; 3014 } 3015 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3016 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3017 switch (adapter->hw.mac.type) { 3018 case ixgbe_mac_82599EB: 3019 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3020 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3021 /* fall through */ 3022 case ixgbe_mac_X540: 3023 case ixgbe_mac_X550: 3024 case ixgbe_mac_X550EM_x: 3025 case ixgbe_mac_x550em_a: 3026 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3027 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3028 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3029 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3030 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3031 mask |= IXGBE_EICR_GPI_SDP0_X540; 3032 mask |= IXGBE_EIMS_ECC; 3033 mask |= IXGBE_EIMS_MAILBOX; 3034 break; 3035 default: 3036 break; 3037 } 3038 3039 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3040 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3041 mask |= IXGBE_EIMS_FLOW_DIR; 3042 3043 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3044 if (queues) 3045 ixgbe_irq_enable_queues(adapter, ~0); 3046 if (flush) 3047 IXGBE_WRITE_FLUSH(&adapter->hw); 3048 } 3049 3050 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3051 { 3052 struct ixgbe_adapter *adapter = data; 3053 struct ixgbe_hw *hw = &adapter->hw; 3054 u32 eicr; 3055 3056 /* 3057 * Workaround for Silicon errata. Use clear-by-write instead 3058 * of clear-by-read. Reading with EICS will return the 3059 * interrupt causes without clearing, which later be done 3060 * with the write to EICR. 3061 */ 3062 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3063 3064 /* The lower 16bits of the EICR register are for the queue interrupts 3065 * which should be masked here in order to not accidentally clear them if 3066 * the bits are high when ixgbe_msix_other is called. There is a race 3067 * condition otherwise which results in possible performance loss 3068 * especially if the ixgbe_msix_other interrupt is triggering 3069 * consistently (as it would when PPS is turned on for the X540 device) 3070 */ 3071 eicr &= 0xFFFF0000; 3072 3073 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3074 3075 if (eicr & IXGBE_EICR_LSC) 3076 ixgbe_check_lsc(adapter); 3077 3078 if (eicr & IXGBE_EICR_MAILBOX) 3079 ixgbe_msg_task(adapter); 3080 3081 switch (hw->mac.type) { 3082 case ixgbe_mac_82599EB: 3083 case ixgbe_mac_X540: 3084 case ixgbe_mac_X550: 3085 case ixgbe_mac_X550EM_x: 3086 case ixgbe_mac_x550em_a: 3087 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3088 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3089 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3090 ixgbe_service_event_schedule(adapter); 3091 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3092 IXGBE_EICR_GPI_SDP0_X540); 3093 } 3094 if (eicr & IXGBE_EICR_ECC) { 3095 e_info(link, "Received ECC Err, initiating reset\n"); 3096 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3097 ixgbe_service_event_schedule(adapter); 3098 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3099 } 3100 /* Handle Flow Director Full threshold interrupt */ 3101 if (eicr & IXGBE_EICR_FLOW_DIR) { 3102 int reinit_count = 0; 3103 int i; 3104 for (i = 0; i < adapter->num_tx_queues; i++) { 3105 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3106 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3107 &ring->state)) 3108 reinit_count++; 3109 } 3110 if (reinit_count) { 3111 /* no more flow director interrupts until after init */ 3112 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3113 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3114 ixgbe_service_event_schedule(adapter); 3115 } 3116 } 3117 ixgbe_check_sfp_event(adapter, eicr); 3118 ixgbe_check_overtemp_event(adapter, eicr); 3119 break; 3120 default: 3121 break; 3122 } 3123 3124 ixgbe_check_fan_failure(adapter, eicr); 3125 3126 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3127 ixgbe_ptp_check_pps_event(adapter); 3128 3129 /* re-enable the original interrupt state, no lsc, no queues */ 3130 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3131 ixgbe_irq_enable(adapter, false, false); 3132 3133 return IRQ_HANDLED; 3134 } 3135 3136 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3137 { 3138 struct ixgbe_q_vector *q_vector = data; 3139 3140 /* EIAM disabled interrupts (on this vector) for us */ 3141 3142 if (q_vector->rx.ring || q_vector->tx.ring) 3143 napi_schedule_irqoff(&q_vector->napi); 3144 3145 return IRQ_HANDLED; 3146 } 3147 3148 /** 3149 * ixgbe_poll - NAPI Rx polling callback 3150 * @napi: structure for representing this polling device 3151 * @budget: how many packets driver is allowed to clean 3152 * 3153 * This function is used for legacy and MSI, NAPI mode 3154 **/ 3155 int ixgbe_poll(struct napi_struct *napi, int budget) 3156 { 3157 struct ixgbe_q_vector *q_vector = 3158 container_of(napi, struct ixgbe_q_vector, napi); 3159 struct ixgbe_adapter *adapter = q_vector->adapter; 3160 struct ixgbe_ring *ring; 3161 int per_ring_budget, work_done = 0; 3162 bool clean_complete = true; 3163 3164 #ifdef CONFIG_IXGBE_DCA 3165 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3166 ixgbe_update_dca(q_vector); 3167 #endif 3168 3169 ixgbe_for_each_ring(ring, q_vector->tx) { 3170 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3171 clean_complete = false; 3172 } 3173 3174 /* Exit if we are called by netpoll */ 3175 if (budget <= 0) 3176 return budget; 3177 3178 /* attempt to distribute budget to each queue fairly, but don't allow 3179 * the budget to go below 1 because we'll exit polling */ 3180 if (q_vector->rx.count > 1) 3181 per_ring_budget = max(budget/q_vector->rx.count, 1); 3182 else 3183 per_ring_budget = budget; 3184 3185 ixgbe_for_each_ring(ring, q_vector->rx) { 3186 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3187 per_ring_budget); 3188 3189 work_done += cleaned; 3190 if (cleaned >= per_ring_budget) 3191 clean_complete = false; 3192 } 3193 3194 /* If all work not completed, return budget and keep polling */ 3195 if (!clean_complete) 3196 return budget; 3197 3198 /* all work done, exit the polling mode */ 3199 napi_complete_done(napi, work_done); 3200 if (adapter->rx_itr_setting & 1) 3201 ixgbe_set_itr(q_vector); 3202 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3203 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3204 3205 return min(work_done, budget - 1); 3206 } 3207 3208 /** 3209 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3210 * @adapter: board private structure 3211 * 3212 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3213 * interrupts from the kernel. 3214 **/ 3215 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3216 { 3217 struct net_device *netdev = adapter->netdev; 3218 unsigned int ri = 0, ti = 0; 3219 int vector, err; 3220 3221 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3222 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3223 struct msix_entry *entry = &adapter->msix_entries[vector]; 3224 3225 if (q_vector->tx.ring && q_vector->rx.ring) { 3226 snprintf(q_vector->name, sizeof(q_vector->name), 3227 "%s-TxRx-%u", netdev->name, ri++); 3228 ti++; 3229 } else if (q_vector->rx.ring) { 3230 snprintf(q_vector->name, sizeof(q_vector->name), 3231 "%s-rx-%u", netdev->name, ri++); 3232 } else if (q_vector->tx.ring) { 3233 snprintf(q_vector->name, sizeof(q_vector->name), 3234 "%s-tx-%u", netdev->name, ti++); 3235 } else { 3236 /* skip this unused q_vector */ 3237 continue; 3238 } 3239 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3240 q_vector->name, q_vector); 3241 if (err) { 3242 e_err(probe, "request_irq failed for MSIX interrupt " 3243 "Error: %d\n", err); 3244 goto free_queue_irqs; 3245 } 3246 /* If Flow Director is enabled, set interrupt affinity */ 3247 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3248 /* assign the mask for this irq */ 3249 irq_set_affinity_hint(entry->vector, 3250 &q_vector->affinity_mask); 3251 } 3252 } 3253 3254 err = request_irq(adapter->msix_entries[vector].vector, 3255 ixgbe_msix_other, 0, netdev->name, adapter); 3256 if (err) { 3257 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3258 goto free_queue_irqs; 3259 } 3260 3261 return 0; 3262 3263 free_queue_irqs: 3264 while (vector) { 3265 vector--; 3266 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3267 NULL); 3268 free_irq(adapter->msix_entries[vector].vector, 3269 adapter->q_vector[vector]); 3270 } 3271 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3272 pci_disable_msix(adapter->pdev); 3273 kfree(adapter->msix_entries); 3274 adapter->msix_entries = NULL; 3275 return err; 3276 } 3277 3278 /** 3279 * ixgbe_intr - legacy mode Interrupt Handler 3280 * @irq: interrupt number 3281 * @data: pointer to a network interface device structure 3282 **/ 3283 static irqreturn_t ixgbe_intr(int irq, void *data) 3284 { 3285 struct ixgbe_adapter *adapter = data; 3286 struct ixgbe_hw *hw = &adapter->hw; 3287 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3288 u32 eicr; 3289 3290 /* 3291 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3292 * before the read of EICR. 3293 */ 3294 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3295 3296 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3297 * therefore no explicit interrupt disable is necessary */ 3298 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3299 if (!eicr) { 3300 /* 3301 * shared interrupt alert! 3302 * make sure interrupts are enabled because the read will 3303 * have disabled interrupts due to EIAM 3304 * finish the workaround of silicon errata on 82598. Unmask 3305 * the interrupt that we masked before the EICR read. 3306 */ 3307 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3308 ixgbe_irq_enable(adapter, true, true); 3309 return IRQ_NONE; /* Not our interrupt */ 3310 } 3311 3312 if (eicr & IXGBE_EICR_LSC) 3313 ixgbe_check_lsc(adapter); 3314 3315 switch (hw->mac.type) { 3316 case ixgbe_mac_82599EB: 3317 ixgbe_check_sfp_event(adapter, eicr); 3318 /* Fall through */ 3319 case ixgbe_mac_X540: 3320 case ixgbe_mac_X550: 3321 case ixgbe_mac_X550EM_x: 3322 case ixgbe_mac_x550em_a: 3323 if (eicr & IXGBE_EICR_ECC) { 3324 e_info(link, "Received ECC Err, initiating reset\n"); 3325 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3326 ixgbe_service_event_schedule(adapter); 3327 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3328 } 3329 ixgbe_check_overtemp_event(adapter, eicr); 3330 break; 3331 default: 3332 break; 3333 } 3334 3335 ixgbe_check_fan_failure(adapter, eicr); 3336 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3337 ixgbe_ptp_check_pps_event(adapter); 3338 3339 /* would disable interrupts here but EIAM disabled it */ 3340 napi_schedule_irqoff(&q_vector->napi); 3341 3342 /* 3343 * re-enable link(maybe) and non-queue interrupts, no flush. 3344 * ixgbe_poll will re-enable the queue interrupts 3345 */ 3346 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3347 ixgbe_irq_enable(adapter, false, false); 3348 3349 return IRQ_HANDLED; 3350 } 3351 3352 /** 3353 * ixgbe_request_irq - initialize interrupts 3354 * @adapter: board private structure 3355 * 3356 * Attempts to configure interrupts using the best available 3357 * capabilities of the hardware and kernel. 3358 **/ 3359 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3360 { 3361 struct net_device *netdev = adapter->netdev; 3362 int err; 3363 3364 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3365 err = ixgbe_request_msix_irqs(adapter); 3366 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3367 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3368 netdev->name, adapter); 3369 else 3370 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3371 netdev->name, adapter); 3372 3373 if (err) 3374 e_err(probe, "request_irq failed, Error %d\n", err); 3375 3376 return err; 3377 } 3378 3379 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3380 { 3381 int vector; 3382 3383 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3384 free_irq(adapter->pdev->irq, adapter); 3385 return; 3386 } 3387 3388 if (!adapter->msix_entries) 3389 return; 3390 3391 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3392 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3393 struct msix_entry *entry = &adapter->msix_entries[vector]; 3394 3395 /* free only the irqs that were actually requested */ 3396 if (!q_vector->rx.ring && !q_vector->tx.ring) 3397 continue; 3398 3399 /* clear the affinity_mask in the IRQ descriptor */ 3400 irq_set_affinity_hint(entry->vector, NULL); 3401 3402 free_irq(entry->vector, q_vector); 3403 } 3404 3405 free_irq(adapter->msix_entries[vector].vector, adapter); 3406 } 3407 3408 /** 3409 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3410 * @adapter: board private structure 3411 **/ 3412 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3413 { 3414 switch (adapter->hw.mac.type) { 3415 case ixgbe_mac_82598EB: 3416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3417 break; 3418 case ixgbe_mac_82599EB: 3419 case ixgbe_mac_X540: 3420 case ixgbe_mac_X550: 3421 case ixgbe_mac_X550EM_x: 3422 case ixgbe_mac_x550em_a: 3423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3426 break; 3427 default: 3428 break; 3429 } 3430 IXGBE_WRITE_FLUSH(&adapter->hw); 3431 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3432 int vector; 3433 3434 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3435 synchronize_irq(adapter->msix_entries[vector].vector); 3436 3437 synchronize_irq(adapter->msix_entries[vector++].vector); 3438 } else { 3439 synchronize_irq(adapter->pdev->irq); 3440 } 3441 } 3442 3443 /** 3444 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3445 * @adapter: board private structure 3446 * 3447 **/ 3448 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3449 { 3450 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3451 3452 ixgbe_write_eitr(q_vector); 3453 3454 ixgbe_set_ivar(adapter, 0, 0, 0); 3455 ixgbe_set_ivar(adapter, 1, 0, 0); 3456 3457 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3458 } 3459 3460 /** 3461 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3462 * @adapter: board private structure 3463 * @ring: structure containing ring specific data 3464 * 3465 * Configure the Tx descriptor ring after a reset. 3466 **/ 3467 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3468 struct ixgbe_ring *ring) 3469 { 3470 struct ixgbe_hw *hw = &adapter->hw; 3471 u64 tdba = ring->dma; 3472 int wait_loop = 10; 3473 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3474 u8 reg_idx = ring->reg_idx; 3475 3476 /* disable queue to avoid issues while updating state */ 3477 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3478 IXGBE_WRITE_FLUSH(hw); 3479 3480 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3481 (tdba & DMA_BIT_MASK(32))); 3482 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3483 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3484 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3485 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3486 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3487 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3488 3489 /* 3490 * set WTHRESH to encourage burst writeback, it should not be set 3491 * higher than 1 when: 3492 * - ITR is 0 as it could cause false TX hangs 3493 * - ITR is set to > 100k int/sec and BQL is enabled 3494 * 3495 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3496 * to or less than the number of on chip descriptors, which is 3497 * currently 40. 3498 */ 3499 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3500 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3501 else 3502 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3503 3504 /* 3505 * Setting PTHRESH to 32 both improves performance 3506 * and avoids a TX hang with DFP enabled 3507 */ 3508 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3509 32; /* PTHRESH = 32 */ 3510 3511 /* reinitialize flowdirector state */ 3512 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3513 ring->atr_sample_rate = adapter->atr_sample_rate; 3514 ring->atr_count = 0; 3515 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3516 } else { 3517 ring->atr_sample_rate = 0; 3518 } 3519 3520 /* initialize XPS */ 3521 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3522 struct ixgbe_q_vector *q_vector = ring->q_vector; 3523 3524 if (q_vector) 3525 netif_set_xps_queue(ring->netdev, 3526 &q_vector->affinity_mask, 3527 ring->queue_index); 3528 } 3529 3530 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3531 3532 /* reinitialize tx_buffer_info */ 3533 memset(ring->tx_buffer_info, 0, 3534 sizeof(struct ixgbe_tx_buffer) * ring->count); 3535 3536 /* enable queue */ 3537 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3538 3539 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3540 if (hw->mac.type == ixgbe_mac_82598EB && 3541 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3542 return; 3543 3544 /* poll to verify queue is enabled */ 3545 do { 3546 usleep_range(1000, 2000); 3547 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3548 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3549 if (!wait_loop) 3550 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3551 } 3552 3553 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3554 { 3555 struct ixgbe_hw *hw = &adapter->hw; 3556 u32 rttdcs, mtqc; 3557 u8 tcs = adapter->hw_tcs; 3558 3559 if (hw->mac.type == ixgbe_mac_82598EB) 3560 return; 3561 3562 /* disable the arbiter while setting MTQC */ 3563 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3564 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3565 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3566 3567 /* set transmit pool layout */ 3568 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3569 mtqc = IXGBE_MTQC_VT_ENA; 3570 if (tcs > 4) 3571 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3572 else if (tcs > 1) 3573 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3574 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3575 IXGBE_82599_VMDQ_4Q_MASK) 3576 mtqc |= IXGBE_MTQC_32VF; 3577 else 3578 mtqc |= IXGBE_MTQC_64VF; 3579 } else { 3580 if (tcs > 4) 3581 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3582 else if (tcs > 1) 3583 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3584 else 3585 mtqc = IXGBE_MTQC_64Q_1PB; 3586 } 3587 3588 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3589 3590 /* Enable Security TX Buffer IFG for multiple pb */ 3591 if (tcs) { 3592 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3593 sectx |= IXGBE_SECTX_DCB; 3594 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3595 } 3596 3597 /* re-enable the arbiter */ 3598 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3599 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3600 } 3601 3602 /** 3603 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3604 * @adapter: board private structure 3605 * 3606 * Configure the Tx unit of the MAC after a reset. 3607 **/ 3608 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3609 { 3610 struct ixgbe_hw *hw = &adapter->hw; 3611 u32 dmatxctl; 3612 u32 i; 3613 3614 ixgbe_setup_mtqc(adapter); 3615 3616 if (hw->mac.type != ixgbe_mac_82598EB) { 3617 /* DMATXCTL.EN must be before Tx queues are enabled */ 3618 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3619 dmatxctl |= IXGBE_DMATXCTL_TE; 3620 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3621 } 3622 3623 /* Setup the HW Tx Head and Tail descriptor pointers */ 3624 for (i = 0; i < adapter->num_tx_queues; i++) 3625 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3626 for (i = 0; i < adapter->num_xdp_queues; i++) 3627 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3628 } 3629 3630 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3631 struct ixgbe_ring *ring) 3632 { 3633 struct ixgbe_hw *hw = &adapter->hw; 3634 u8 reg_idx = ring->reg_idx; 3635 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3636 3637 srrctl |= IXGBE_SRRCTL_DROP_EN; 3638 3639 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3640 } 3641 3642 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3643 struct ixgbe_ring *ring) 3644 { 3645 struct ixgbe_hw *hw = &adapter->hw; 3646 u8 reg_idx = ring->reg_idx; 3647 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3648 3649 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3650 3651 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3652 } 3653 3654 #ifdef CONFIG_IXGBE_DCB 3655 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3656 #else 3657 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3658 #endif 3659 { 3660 int i; 3661 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3662 3663 if (adapter->ixgbe_ieee_pfc) 3664 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3665 3666 /* 3667 * We should set the drop enable bit if: 3668 * SR-IOV is enabled 3669 * or 3670 * Number of Rx queues > 1 and flow control is disabled 3671 * 3672 * This allows us to avoid head of line blocking for security 3673 * and performance reasons. 3674 */ 3675 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3676 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3677 for (i = 0; i < adapter->num_rx_queues; i++) 3678 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3679 } else { 3680 for (i = 0; i < adapter->num_rx_queues; i++) 3681 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3682 } 3683 } 3684 3685 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3686 3687 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3688 struct ixgbe_ring *rx_ring) 3689 { 3690 struct ixgbe_hw *hw = &adapter->hw; 3691 u32 srrctl; 3692 u8 reg_idx = rx_ring->reg_idx; 3693 3694 if (hw->mac.type == ixgbe_mac_82598EB) { 3695 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3696 3697 /* 3698 * if VMDq is not active we must program one srrctl register 3699 * per RSS queue since we have enabled RDRXCTL.MVMEN 3700 */ 3701 reg_idx &= mask; 3702 } 3703 3704 /* configure header buffer length, needed for RSC */ 3705 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3706 3707 /* configure the packet buffer length */ 3708 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3709 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3710 else 3711 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3712 3713 /* configure descriptor type */ 3714 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3715 3716 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3717 } 3718 3719 /** 3720 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3721 * @adapter: device handle 3722 * 3723 * - 82598/82599/X540: 128 3724 * - X550(non-SRIOV mode): 512 3725 * - X550(SRIOV mode): 64 3726 */ 3727 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3728 { 3729 if (adapter->hw.mac.type < ixgbe_mac_X550) 3730 return 128; 3731 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3732 return 64; 3733 else 3734 return 512; 3735 } 3736 3737 /** 3738 * ixgbe_store_key - Write the RSS key to HW 3739 * @adapter: device handle 3740 * 3741 * Write the RSS key stored in adapter.rss_key to HW. 3742 */ 3743 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3744 { 3745 struct ixgbe_hw *hw = &adapter->hw; 3746 int i; 3747 3748 for (i = 0; i < 10; i++) 3749 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3750 } 3751 3752 /** 3753 * ixgbe_init_rss_key - Initialize adapter RSS key 3754 * @adapter: device handle 3755 * 3756 * Allocates and initializes the RSS key if it is not allocated. 3757 **/ 3758 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3759 { 3760 u32 *rss_key; 3761 3762 if (!adapter->rss_key) { 3763 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3764 if (unlikely(!rss_key)) 3765 return -ENOMEM; 3766 3767 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3768 adapter->rss_key = rss_key; 3769 } 3770 3771 return 0; 3772 } 3773 3774 /** 3775 * ixgbe_store_reta - Write the RETA table to HW 3776 * @adapter: device handle 3777 * 3778 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3779 */ 3780 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3781 { 3782 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3783 struct ixgbe_hw *hw = &adapter->hw; 3784 u32 reta = 0; 3785 u32 indices_multi; 3786 u8 *indir_tbl = adapter->rss_indir_tbl; 3787 3788 /* Fill out the redirection table as follows: 3789 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3790 * indices. 3791 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3792 * - X550: 8 bit wide entries containing 6 bit RSS index 3793 */ 3794 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3795 indices_multi = 0x11; 3796 else 3797 indices_multi = 0x1; 3798 3799 /* Write redirection table to HW */ 3800 for (i = 0; i < reta_entries; i++) { 3801 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3802 if ((i & 3) == 3) { 3803 if (i < 128) 3804 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3805 else 3806 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3807 reta); 3808 reta = 0; 3809 } 3810 } 3811 } 3812 3813 /** 3814 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3815 * @adapter: device handle 3816 * 3817 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3818 */ 3819 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3820 { 3821 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3822 struct ixgbe_hw *hw = &adapter->hw; 3823 u32 vfreta = 0; 3824 3825 /* Write redirection table to HW */ 3826 for (i = 0; i < reta_entries; i++) { 3827 u16 pool = adapter->num_rx_pools; 3828 3829 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3830 if ((i & 3) != 3) 3831 continue; 3832 3833 while (pool--) 3834 IXGBE_WRITE_REG(hw, 3835 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3836 vfreta); 3837 vfreta = 0; 3838 } 3839 } 3840 3841 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3842 { 3843 u32 i, j; 3844 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3845 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3846 3847 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3848 * make full use of any rings they may have. We will use the 3849 * PSRTYPE register to control how many rings we use within the PF. 3850 */ 3851 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3852 rss_i = 4; 3853 3854 /* Fill out hash function seeds */ 3855 ixgbe_store_key(adapter); 3856 3857 /* Fill out redirection table */ 3858 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3859 3860 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3861 if (j == rss_i) 3862 j = 0; 3863 3864 adapter->rss_indir_tbl[i] = j; 3865 } 3866 3867 ixgbe_store_reta(adapter); 3868 } 3869 3870 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3871 { 3872 struct ixgbe_hw *hw = &adapter->hw; 3873 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3874 int i, j; 3875 3876 /* Fill out hash function seeds */ 3877 for (i = 0; i < 10; i++) { 3878 u16 pool = adapter->num_rx_pools; 3879 3880 while (pool--) 3881 IXGBE_WRITE_REG(hw, 3882 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3883 *(adapter->rss_key + i)); 3884 } 3885 3886 /* Fill out the redirection table */ 3887 for (i = 0, j = 0; i < 64; i++, j++) { 3888 if (j == rss_i) 3889 j = 0; 3890 3891 adapter->rss_indir_tbl[i] = j; 3892 } 3893 3894 ixgbe_store_vfreta(adapter); 3895 } 3896 3897 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3898 { 3899 struct ixgbe_hw *hw = &adapter->hw; 3900 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3901 u32 rxcsum; 3902 3903 /* Disable indicating checksum in descriptor, enables RSS hash */ 3904 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3905 rxcsum |= IXGBE_RXCSUM_PCSD; 3906 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3907 3908 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3909 if (adapter->ring_feature[RING_F_RSS].mask) 3910 mrqc = IXGBE_MRQC_RSSEN; 3911 } else { 3912 u8 tcs = adapter->hw_tcs; 3913 3914 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3915 if (tcs > 4) 3916 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3917 else if (tcs > 1) 3918 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3919 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3920 IXGBE_82599_VMDQ_4Q_MASK) 3921 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3922 else 3923 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3924 3925 /* Enable L3/L4 for Tx Switched packets */ 3926 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3927 } else { 3928 if (tcs > 4) 3929 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3930 else if (tcs > 1) 3931 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3932 else 3933 mrqc = IXGBE_MRQC_RSSEN; 3934 } 3935 } 3936 3937 /* Perform hash on these packet types */ 3938 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3939 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3940 IXGBE_MRQC_RSS_FIELD_IPV6 | 3941 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3942 3943 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3944 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3945 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3946 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3947 3948 if ((hw->mac.type >= ixgbe_mac_X550) && 3949 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3950 u16 pool = adapter->num_rx_pools; 3951 3952 /* Enable VF RSS mode */ 3953 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3954 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3955 3956 /* Setup RSS through the VF registers */ 3957 ixgbe_setup_vfreta(adapter); 3958 vfmrqc = IXGBE_MRQC_RSSEN; 3959 vfmrqc |= rss_field; 3960 3961 while (pool--) 3962 IXGBE_WRITE_REG(hw, 3963 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3964 vfmrqc); 3965 } else { 3966 ixgbe_setup_reta(adapter); 3967 mrqc |= rss_field; 3968 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3969 } 3970 } 3971 3972 /** 3973 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3974 * @adapter: address of board private structure 3975 * @ring: structure containing ring specific data 3976 **/ 3977 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3978 struct ixgbe_ring *ring) 3979 { 3980 struct ixgbe_hw *hw = &adapter->hw; 3981 u32 rscctrl; 3982 u8 reg_idx = ring->reg_idx; 3983 3984 if (!ring_is_rsc_enabled(ring)) 3985 return; 3986 3987 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3988 rscctrl |= IXGBE_RSCCTL_RSCEN; 3989 /* 3990 * we must limit the number of descriptors so that the 3991 * total size of max desc * buf_len is not greater 3992 * than 65536 3993 */ 3994 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3995 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3996 } 3997 3998 #define IXGBE_MAX_RX_DESC_POLL 10 3999 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4000 struct ixgbe_ring *ring) 4001 { 4002 struct ixgbe_hw *hw = &adapter->hw; 4003 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4004 u32 rxdctl; 4005 u8 reg_idx = ring->reg_idx; 4006 4007 if (ixgbe_removed(hw->hw_addr)) 4008 return; 4009 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4010 if (hw->mac.type == ixgbe_mac_82598EB && 4011 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4012 return; 4013 4014 do { 4015 usleep_range(1000, 2000); 4016 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4017 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4018 4019 if (!wait_loop) { 4020 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4021 "the polling period\n", reg_idx); 4022 } 4023 } 4024 4025 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 4026 struct ixgbe_ring *ring) 4027 { 4028 struct ixgbe_hw *hw = &adapter->hw; 4029 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4030 u32 rxdctl; 4031 u8 reg_idx = ring->reg_idx; 4032 4033 if (ixgbe_removed(hw->hw_addr)) 4034 return; 4035 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4036 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4037 4038 /* write value back with RXDCTL.ENABLE bit cleared */ 4039 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4040 4041 if (hw->mac.type == ixgbe_mac_82598EB && 4042 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4043 return; 4044 4045 /* the hardware may take up to 100us to really disable the rx queue */ 4046 do { 4047 udelay(10); 4048 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4049 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 4050 4051 if (!wait_loop) { 4052 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 4053 "the polling period\n", reg_idx); 4054 } 4055 } 4056 4057 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4058 struct ixgbe_ring *ring) 4059 { 4060 struct ixgbe_hw *hw = &adapter->hw; 4061 union ixgbe_adv_rx_desc *rx_desc; 4062 u64 rdba = ring->dma; 4063 u32 rxdctl; 4064 u8 reg_idx = ring->reg_idx; 4065 4066 /* disable queue to avoid issues while updating state */ 4067 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4068 ixgbe_disable_rx_queue(adapter, ring); 4069 4070 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4071 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4072 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4073 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4074 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4075 IXGBE_WRITE_FLUSH(hw); 4076 4077 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4078 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4079 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4080 4081 ixgbe_configure_srrctl(adapter, ring); 4082 ixgbe_configure_rscctl(adapter, ring); 4083 4084 if (hw->mac.type == ixgbe_mac_82598EB) { 4085 /* 4086 * enable cache line friendly hardware writes: 4087 * PTHRESH=32 descriptors (half the internal cache), 4088 * this also removes ugly rx_no_buffer_count increment 4089 * HTHRESH=4 descriptors (to minimize latency on fetch) 4090 * WTHRESH=8 burst writeback up to two cache lines 4091 */ 4092 rxdctl &= ~0x3FFFFF; 4093 rxdctl |= 0x080420; 4094 #if (PAGE_SIZE < 8192) 4095 /* RXDCTL.RLPML does not work on 82599 */ 4096 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4097 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4098 IXGBE_RXDCTL_RLPML_EN); 4099 4100 /* Limit the maximum frame size so we don't overrun the skb. 4101 * This can happen in SRIOV mode when the MTU of the VF is 4102 * higher than the MTU of the PF. 4103 */ 4104 if (ring_uses_build_skb(ring) && 4105 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4106 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4107 IXGBE_RXDCTL_RLPML_EN; 4108 #endif 4109 } 4110 4111 /* initialize rx_buffer_info */ 4112 memset(ring->rx_buffer_info, 0, 4113 sizeof(struct ixgbe_rx_buffer) * ring->count); 4114 4115 /* initialize Rx descriptor 0 */ 4116 rx_desc = IXGBE_RX_DESC(ring, 0); 4117 rx_desc->wb.upper.length = 0; 4118 4119 /* enable receive descriptor ring */ 4120 rxdctl |= IXGBE_RXDCTL_ENABLE; 4121 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4122 4123 ixgbe_rx_desc_queue_enable(adapter, ring); 4124 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4125 } 4126 4127 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4128 { 4129 struct ixgbe_hw *hw = &adapter->hw; 4130 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4131 u16 pool = adapter->num_rx_pools; 4132 4133 /* PSRTYPE must be initialized in non 82598 adapters */ 4134 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4135 IXGBE_PSRTYPE_UDPHDR | 4136 IXGBE_PSRTYPE_IPV4HDR | 4137 IXGBE_PSRTYPE_L2HDR | 4138 IXGBE_PSRTYPE_IPV6HDR; 4139 4140 if (hw->mac.type == ixgbe_mac_82598EB) 4141 return; 4142 4143 if (rss_i > 3) 4144 psrtype |= 2u << 29; 4145 else if (rss_i > 1) 4146 psrtype |= 1u << 29; 4147 4148 while (pool--) 4149 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4150 } 4151 4152 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4153 { 4154 struct ixgbe_hw *hw = &adapter->hw; 4155 u16 pool = adapter->num_rx_pools; 4156 u32 reg_offset, vf_shift, vmolr; 4157 u32 gcr_ext, vmdctl; 4158 int i; 4159 4160 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4161 return; 4162 4163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4164 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4165 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4166 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4167 vmdctl |= IXGBE_VT_CTL_REPLEN; 4168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4169 4170 /* accept untagged packets until a vlan tag is 4171 * specifically set for the VMDQ queue/pool 4172 */ 4173 vmolr = IXGBE_VMOLR_AUPE; 4174 while (pool--) 4175 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4176 4177 vf_shift = VMDQ_P(0) % 32; 4178 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4179 4180 /* Enable only the PF's pool for Tx/Rx */ 4181 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4182 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4183 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4184 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4185 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4186 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4187 4188 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4189 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4190 4191 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4192 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4193 4194 /* 4195 * Set up VF register offsets for selected VT Mode, 4196 * i.e. 32 or 64 VFs for SR-IOV 4197 */ 4198 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4199 case IXGBE_82599_VMDQ_8Q_MASK: 4200 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4201 break; 4202 case IXGBE_82599_VMDQ_4Q_MASK: 4203 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4204 break; 4205 default: 4206 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4207 break; 4208 } 4209 4210 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4211 4212 for (i = 0; i < adapter->num_vfs; i++) { 4213 /* configure spoof checking */ 4214 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4215 adapter->vfinfo[i].spoofchk_enabled); 4216 4217 /* Enable/Disable RSS query feature */ 4218 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4219 adapter->vfinfo[i].rss_query_enabled); 4220 } 4221 } 4222 4223 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4224 { 4225 struct ixgbe_hw *hw = &adapter->hw; 4226 struct net_device *netdev = adapter->netdev; 4227 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4228 struct ixgbe_ring *rx_ring; 4229 int i; 4230 u32 mhadd, hlreg0; 4231 4232 #ifdef IXGBE_FCOE 4233 /* adjust max frame to be able to do baby jumbo for FCoE */ 4234 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4235 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4236 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4237 4238 #endif /* IXGBE_FCOE */ 4239 4240 /* adjust max frame to be at least the size of a standard frame */ 4241 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4242 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4243 4244 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4245 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4246 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4247 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4248 4249 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4250 } 4251 4252 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4253 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4254 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4255 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4256 4257 /* 4258 * Setup the HW Rx Head and Tail Descriptor Pointers and 4259 * the Base and Length of the Rx Descriptor Ring 4260 */ 4261 for (i = 0; i < adapter->num_rx_queues; i++) { 4262 rx_ring = adapter->rx_ring[i]; 4263 4264 clear_ring_rsc_enabled(rx_ring); 4265 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4266 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4267 4268 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4269 set_ring_rsc_enabled(rx_ring); 4270 4271 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4272 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4273 4274 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4275 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4276 continue; 4277 4278 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4279 4280 #if (PAGE_SIZE < 8192) 4281 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4282 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4283 4284 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4285 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4286 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4287 #endif 4288 } 4289 } 4290 4291 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4292 { 4293 struct ixgbe_hw *hw = &adapter->hw; 4294 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4295 4296 switch (hw->mac.type) { 4297 case ixgbe_mac_82598EB: 4298 /* 4299 * For VMDq support of different descriptor types or 4300 * buffer sizes through the use of multiple SRRCTL 4301 * registers, RDRXCTL.MVMEN must be set to 1 4302 * 4303 * also, the manual doesn't mention it clearly but DCA hints 4304 * will only use queue 0's tags unless this bit is set. Side 4305 * effects of setting this bit are only that SRRCTL must be 4306 * fully programmed [0..15] 4307 */ 4308 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4309 break; 4310 case ixgbe_mac_X550: 4311 case ixgbe_mac_X550EM_x: 4312 case ixgbe_mac_x550em_a: 4313 if (adapter->num_vfs) 4314 rdrxctl |= IXGBE_RDRXCTL_PSP; 4315 /* fall through */ 4316 case ixgbe_mac_82599EB: 4317 case ixgbe_mac_X540: 4318 /* Disable RSC for ACK packets */ 4319 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4320 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4321 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4322 /* hardware requires some bits to be set by default */ 4323 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4324 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4325 break; 4326 default: 4327 /* We should do nothing since we don't know this hardware */ 4328 return; 4329 } 4330 4331 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4332 } 4333 4334 /** 4335 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4336 * @adapter: board private structure 4337 * 4338 * Configure the Rx unit of the MAC after a reset. 4339 **/ 4340 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4341 { 4342 struct ixgbe_hw *hw = &adapter->hw; 4343 int i; 4344 u32 rxctrl, rfctl; 4345 4346 /* disable receives while setting up the descriptors */ 4347 hw->mac.ops.disable_rx(hw); 4348 4349 ixgbe_setup_psrtype(adapter); 4350 ixgbe_setup_rdrxctl(adapter); 4351 4352 /* RSC Setup */ 4353 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4354 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4355 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4356 rfctl |= IXGBE_RFCTL_RSC_DIS; 4357 4358 /* disable NFS filtering */ 4359 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4360 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4361 4362 /* Program registers for the distribution of queues */ 4363 ixgbe_setup_mrqc(adapter); 4364 4365 /* set_rx_buffer_len must be called before ring initialization */ 4366 ixgbe_set_rx_buffer_len(adapter); 4367 4368 /* 4369 * Setup the HW Rx Head and Tail Descriptor Pointers and 4370 * the Base and Length of the Rx Descriptor Ring 4371 */ 4372 for (i = 0; i < adapter->num_rx_queues; i++) 4373 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4374 4375 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4376 /* disable drop enable for 82598 parts */ 4377 if (hw->mac.type == ixgbe_mac_82598EB) 4378 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4379 4380 /* enable all receives */ 4381 rxctrl |= IXGBE_RXCTRL_RXEN; 4382 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4383 } 4384 4385 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4386 __be16 proto, u16 vid) 4387 { 4388 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4389 struct ixgbe_hw *hw = &adapter->hw; 4390 4391 /* add VID to filter table */ 4392 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4393 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4394 4395 set_bit(vid, adapter->active_vlans); 4396 4397 return 0; 4398 } 4399 4400 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4401 { 4402 u32 vlvf; 4403 int idx; 4404 4405 /* short cut the special case */ 4406 if (vlan == 0) 4407 return 0; 4408 4409 /* Search for the vlan id in the VLVF entries */ 4410 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4411 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4412 if ((vlvf & VLAN_VID_MASK) == vlan) 4413 break; 4414 } 4415 4416 return idx; 4417 } 4418 4419 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4420 { 4421 struct ixgbe_hw *hw = &adapter->hw; 4422 u32 bits, word; 4423 int idx; 4424 4425 idx = ixgbe_find_vlvf_entry(hw, vid); 4426 if (!idx) 4427 return; 4428 4429 /* See if any other pools are set for this VLAN filter 4430 * entry other than the PF. 4431 */ 4432 word = idx * 2 + (VMDQ_P(0) / 32); 4433 bits = ~BIT(VMDQ_P(0) % 32); 4434 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4435 4436 /* Disable the filter so this falls into the default pool. */ 4437 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4438 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4439 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4440 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4441 } 4442 } 4443 4444 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4445 __be16 proto, u16 vid) 4446 { 4447 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4448 struct ixgbe_hw *hw = &adapter->hw; 4449 4450 /* remove VID from filter table */ 4451 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4452 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4453 4454 clear_bit(vid, adapter->active_vlans); 4455 4456 return 0; 4457 } 4458 4459 /** 4460 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4461 * @adapter: driver data 4462 */ 4463 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4464 { 4465 struct ixgbe_hw *hw = &adapter->hw; 4466 u32 vlnctrl; 4467 int i, j; 4468 4469 switch (hw->mac.type) { 4470 case ixgbe_mac_82598EB: 4471 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4472 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4473 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4474 break; 4475 case ixgbe_mac_82599EB: 4476 case ixgbe_mac_X540: 4477 case ixgbe_mac_X550: 4478 case ixgbe_mac_X550EM_x: 4479 case ixgbe_mac_x550em_a: 4480 for (i = 0; i < adapter->num_rx_queues; i++) { 4481 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4482 4483 if (!netif_is_ixgbe(ring->netdev)) 4484 continue; 4485 4486 j = ring->reg_idx; 4487 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4488 vlnctrl &= ~IXGBE_RXDCTL_VME; 4489 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4490 } 4491 break; 4492 default: 4493 break; 4494 } 4495 } 4496 4497 /** 4498 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4499 * @adapter: driver data 4500 */ 4501 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4502 { 4503 struct ixgbe_hw *hw = &adapter->hw; 4504 u32 vlnctrl; 4505 int i, j; 4506 4507 switch (hw->mac.type) { 4508 case ixgbe_mac_82598EB: 4509 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4510 vlnctrl |= IXGBE_VLNCTRL_VME; 4511 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4512 break; 4513 case ixgbe_mac_82599EB: 4514 case ixgbe_mac_X540: 4515 case ixgbe_mac_X550: 4516 case ixgbe_mac_X550EM_x: 4517 case ixgbe_mac_x550em_a: 4518 for (i = 0; i < adapter->num_rx_queues; i++) { 4519 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4520 4521 if (!netif_is_ixgbe(ring->netdev)) 4522 continue; 4523 4524 j = ring->reg_idx; 4525 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4526 vlnctrl |= IXGBE_RXDCTL_VME; 4527 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4528 } 4529 break; 4530 default: 4531 break; 4532 } 4533 } 4534 4535 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4536 { 4537 struct ixgbe_hw *hw = &adapter->hw; 4538 u32 vlnctrl, i; 4539 4540 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4541 4542 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4543 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4544 vlnctrl |= IXGBE_VLNCTRL_VFE; 4545 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4546 } else { 4547 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4548 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4549 return; 4550 } 4551 4552 /* Nothing to do for 82598 */ 4553 if (hw->mac.type == ixgbe_mac_82598EB) 4554 return; 4555 4556 /* We are already in VLAN promisc, nothing to do */ 4557 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4558 return; 4559 4560 /* Set flag so we don't redo unnecessary work */ 4561 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4562 4563 /* Add PF to all active pools */ 4564 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4565 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4566 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4567 4568 vlvfb |= BIT(VMDQ_P(0) % 32); 4569 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4570 } 4571 4572 /* Set all bits in the VLAN filter table array */ 4573 for (i = hw->mac.vft_size; i--;) 4574 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4575 } 4576 4577 #define VFTA_BLOCK_SIZE 8 4578 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4579 { 4580 struct ixgbe_hw *hw = &adapter->hw; 4581 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4582 u32 vid_start = vfta_offset * 32; 4583 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4584 u32 i, vid, word, bits; 4585 4586 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4587 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4588 4589 /* pull VLAN ID from VLVF */ 4590 vid = vlvf & VLAN_VID_MASK; 4591 4592 /* only concern outselves with a certain range */ 4593 if (vid < vid_start || vid >= vid_end) 4594 continue; 4595 4596 if (vlvf) { 4597 /* record VLAN ID in VFTA */ 4598 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4599 4600 /* if PF is part of this then continue */ 4601 if (test_bit(vid, adapter->active_vlans)) 4602 continue; 4603 } 4604 4605 /* remove PF from the pool */ 4606 word = i * 2 + VMDQ_P(0) / 32; 4607 bits = ~BIT(VMDQ_P(0) % 32); 4608 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4609 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4610 } 4611 4612 /* extract values from active_vlans and write back to VFTA */ 4613 for (i = VFTA_BLOCK_SIZE; i--;) { 4614 vid = (vfta_offset + i) * 32; 4615 word = vid / BITS_PER_LONG; 4616 bits = vid % BITS_PER_LONG; 4617 4618 vfta[i] |= adapter->active_vlans[word] >> bits; 4619 4620 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4621 } 4622 } 4623 4624 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4625 { 4626 struct ixgbe_hw *hw = &adapter->hw; 4627 u32 vlnctrl, i; 4628 4629 /* Set VLAN filtering to enabled */ 4630 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4631 vlnctrl |= IXGBE_VLNCTRL_VFE; 4632 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4633 4634 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4635 hw->mac.type == ixgbe_mac_82598EB) 4636 return; 4637 4638 /* We are not in VLAN promisc, nothing to do */ 4639 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4640 return; 4641 4642 /* Set flag so we don't redo unnecessary work */ 4643 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4644 4645 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4646 ixgbe_scrub_vfta(adapter, i); 4647 } 4648 4649 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4650 { 4651 u16 vid = 1; 4652 4653 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4654 4655 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4656 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4657 } 4658 4659 /** 4660 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4661 * @netdev: network interface device structure 4662 * 4663 * Writes multicast address list to the MTA hash table. 4664 * Returns: -ENOMEM on failure 4665 * 0 on no addresses written 4666 * X on writing X addresses to MTA 4667 **/ 4668 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4669 { 4670 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4671 struct ixgbe_hw *hw = &adapter->hw; 4672 4673 if (!netif_running(netdev)) 4674 return 0; 4675 4676 if (hw->mac.ops.update_mc_addr_list) 4677 hw->mac.ops.update_mc_addr_list(hw, netdev); 4678 else 4679 return -ENOMEM; 4680 4681 #ifdef CONFIG_PCI_IOV 4682 ixgbe_restore_vf_multicasts(adapter); 4683 #endif 4684 4685 return netdev_mc_count(netdev); 4686 } 4687 4688 #ifdef CONFIG_PCI_IOV 4689 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4690 { 4691 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4692 struct ixgbe_hw *hw = &adapter->hw; 4693 int i; 4694 4695 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4696 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4697 4698 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4699 hw->mac.ops.set_rar(hw, i, 4700 mac_table->addr, 4701 mac_table->pool, 4702 IXGBE_RAH_AV); 4703 else 4704 hw->mac.ops.clear_rar(hw, i); 4705 } 4706 } 4707 4708 #endif 4709 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4710 { 4711 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4712 struct ixgbe_hw *hw = &adapter->hw; 4713 int i; 4714 4715 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4716 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4717 continue; 4718 4719 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4720 4721 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4722 hw->mac.ops.set_rar(hw, i, 4723 mac_table->addr, 4724 mac_table->pool, 4725 IXGBE_RAH_AV); 4726 else 4727 hw->mac.ops.clear_rar(hw, i); 4728 } 4729 } 4730 4731 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4732 { 4733 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4734 struct ixgbe_hw *hw = &adapter->hw; 4735 int i; 4736 4737 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4738 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4739 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4740 } 4741 4742 ixgbe_sync_mac_table(adapter); 4743 } 4744 4745 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4746 { 4747 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4748 struct ixgbe_hw *hw = &adapter->hw; 4749 int i, count = 0; 4750 4751 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4752 /* do not count default RAR as available */ 4753 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4754 continue; 4755 4756 /* only count unused and addresses that belong to us */ 4757 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4758 if (mac_table->pool != pool) 4759 continue; 4760 } 4761 4762 count++; 4763 } 4764 4765 return count; 4766 } 4767 4768 /* this function destroys the first RAR entry */ 4769 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4770 { 4771 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4772 struct ixgbe_hw *hw = &adapter->hw; 4773 4774 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4775 mac_table->pool = VMDQ_P(0); 4776 4777 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4778 4779 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4780 IXGBE_RAH_AV); 4781 } 4782 4783 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4784 const u8 *addr, u16 pool) 4785 { 4786 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4787 struct ixgbe_hw *hw = &adapter->hw; 4788 int i; 4789 4790 if (is_zero_ether_addr(addr)) 4791 return -EINVAL; 4792 4793 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4794 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4795 continue; 4796 4797 ether_addr_copy(mac_table->addr, addr); 4798 mac_table->pool = pool; 4799 4800 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4801 IXGBE_MAC_STATE_IN_USE; 4802 4803 ixgbe_sync_mac_table(adapter); 4804 4805 return i; 4806 } 4807 4808 return -ENOMEM; 4809 } 4810 4811 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4812 const u8 *addr, u16 pool) 4813 { 4814 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4815 struct ixgbe_hw *hw = &adapter->hw; 4816 int i; 4817 4818 if (is_zero_ether_addr(addr)) 4819 return -EINVAL; 4820 4821 /* search table for addr, if found clear IN_USE flag and sync */ 4822 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4823 /* we can only delete an entry if it is in use */ 4824 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4825 continue; 4826 /* we only care about entries that belong to the given pool */ 4827 if (mac_table->pool != pool) 4828 continue; 4829 /* we only care about a specific MAC address */ 4830 if (!ether_addr_equal(addr, mac_table->addr)) 4831 continue; 4832 4833 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4834 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4835 4836 ixgbe_sync_mac_table(adapter); 4837 4838 return 0; 4839 } 4840 4841 return -ENOMEM; 4842 } 4843 4844 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4845 { 4846 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4847 int ret; 4848 4849 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4850 4851 return min_t(int, ret, 0); 4852 } 4853 4854 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4855 { 4856 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4857 4858 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4859 4860 return 0; 4861 } 4862 4863 /** 4864 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4865 * @netdev: network interface device structure 4866 * 4867 * The set_rx_method entry point is called whenever the unicast/multicast 4868 * address list or the network interface flags are updated. This routine is 4869 * responsible for configuring the hardware for proper unicast, multicast and 4870 * promiscuous mode. 4871 **/ 4872 void ixgbe_set_rx_mode(struct net_device *netdev) 4873 { 4874 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4875 struct ixgbe_hw *hw = &adapter->hw; 4876 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4877 netdev_features_t features = netdev->features; 4878 int count; 4879 4880 /* Check for Promiscuous and All Multicast modes */ 4881 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4882 4883 /* set all bits that we expect to always be set */ 4884 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4885 fctrl |= IXGBE_FCTRL_BAM; 4886 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4887 fctrl |= IXGBE_FCTRL_PMCF; 4888 4889 /* clear the bits we are changing the status of */ 4890 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4891 if (netdev->flags & IFF_PROMISC) { 4892 hw->addr_ctrl.user_set_promisc = true; 4893 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4894 vmolr |= IXGBE_VMOLR_MPE; 4895 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4896 } else { 4897 if (netdev->flags & IFF_ALLMULTI) { 4898 fctrl |= IXGBE_FCTRL_MPE; 4899 vmolr |= IXGBE_VMOLR_MPE; 4900 } 4901 hw->addr_ctrl.user_set_promisc = false; 4902 } 4903 4904 /* 4905 * Write addresses to available RAR registers, if there is not 4906 * sufficient space to store all the addresses then enable 4907 * unicast promiscuous mode 4908 */ 4909 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4910 fctrl |= IXGBE_FCTRL_UPE; 4911 vmolr |= IXGBE_VMOLR_ROPE; 4912 } 4913 4914 /* Write addresses to the MTA, if the attempt fails 4915 * then we should just turn on promiscuous mode so 4916 * that we can at least receive multicast traffic 4917 */ 4918 count = ixgbe_write_mc_addr_list(netdev); 4919 if (count < 0) { 4920 fctrl |= IXGBE_FCTRL_MPE; 4921 vmolr |= IXGBE_VMOLR_MPE; 4922 } else if (count) { 4923 vmolr |= IXGBE_VMOLR_ROMPE; 4924 } 4925 4926 if (hw->mac.type != ixgbe_mac_82598EB) { 4927 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4928 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4929 IXGBE_VMOLR_ROPE); 4930 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4931 } 4932 4933 /* This is useful for sniffing bad packets. */ 4934 if (features & NETIF_F_RXALL) { 4935 /* UPE and MPE will be handled by normal PROMISC logic 4936 * in e1000e_set_rx_mode */ 4937 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4938 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4939 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4940 4941 fctrl &= ~(IXGBE_FCTRL_DPF); 4942 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4943 } 4944 4945 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4946 4947 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4948 ixgbe_vlan_strip_enable(adapter); 4949 else 4950 ixgbe_vlan_strip_disable(adapter); 4951 4952 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4953 ixgbe_vlan_promisc_disable(adapter); 4954 else 4955 ixgbe_vlan_promisc_enable(adapter); 4956 } 4957 4958 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4959 { 4960 int q_idx; 4961 4962 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4963 napi_enable(&adapter->q_vector[q_idx]->napi); 4964 } 4965 4966 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4967 { 4968 int q_idx; 4969 4970 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4971 napi_disable(&adapter->q_vector[q_idx]->napi); 4972 } 4973 4974 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 4975 { 4976 struct ixgbe_hw *hw = &adapter->hw; 4977 u32 vxlanctrl; 4978 4979 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 4980 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 4981 return; 4982 4983 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 4984 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 4985 4986 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 4987 adapter->vxlan_port = 0; 4988 4989 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 4990 adapter->geneve_port = 0; 4991 } 4992 4993 #ifdef CONFIG_IXGBE_DCB 4994 /** 4995 * ixgbe_configure_dcb - Configure DCB hardware 4996 * @adapter: ixgbe adapter struct 4997 * 4998 * This is called by the driver on open to configure the DCB hardware. 4999 * This is also called by the gennetlink interface when reconfiguring 5000 * the DCB state. 5001 */ 5002 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5003 { 5004 struct ixgbe_hw *hw = &adapter->hw; 5005 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5006 5007 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5008 if (hw->mac.type == ixgbe_mac_82598EB) 5009 netif_set_gso_max_size(adapter->netdev, 65536); 5010 return; 5011 } 5012 5013 if (hw->mac.type == ixgbe_mac_82598EB) 5014 netif_set_gso_max_size(adapter->netdev, 32768); 5015 5016 #ifdef IXGBE_FCOE 5017 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5018 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5019 #endif 5020 5021 /* reconfigure the hardware */ 5022 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5023 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5024 DCB_TX_CONFIG); 5025 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5026 DCB_RX_CONFIG); 5027 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5028 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5029 ixgbe_dcb_hw_ets(&adapter->hw, 5030 adapter->ixgbe_ieee_ets, 5031 max_frame); 5032 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5033 adapter->ixgbe_ieee_pfc->pfc_en, 5034 adapter->ixgbe_ieee_ets->prio_tc); 5035 } 5036 5037 /* Enable RSS Hash per TC */ 5038 if (hw->mac.type != ixgbe_mac_82598EB) { 5039 u32 msb = 0; 5040 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5041 5042 while (rss_i) { 5043 msb++; 5044 rss_i >>= 1; 5045 } 5046 5047 /* write msb to all 8 TCs in one write */ 5048 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5049 } 5050 } 5051 #endif 5052 5053 /* Additional bittime to account for IXGBE framing */ 5054 #define IXGBE_ETH_FRAMING 20 5055 5056 /** 5057 * ixgbe_hpbthresh - calculate high water mark for flow control 5058 * 5059 * @adapter: board private structure to calculate for 5060 * @pb: packet buffer to calculate 5061 */ 5062 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5063 { 5064 struct ixgbe_hw *hw = &adapter->hw; 5065 struct net_device *dev = adapter->netdev; 5066 int link, tc, kb, marker; 5067 u32 dv_id, rx_pba; 5068 5069 /* Calculate max LAN frame size */ 5070 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5071 5072 #ifdef IXGBE_FCOE 5073 /* FCoE traffic class uses FCOE jumbo frames */ 5074 if ((dev->features & NETIF_F_FCOE_MTU) && 5075 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5076 (pb == ixgbe_fcoe_get_tc(adapter))) 5077 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5078 #endif 5079 5080 /* Calculate delay value for device */ 5081 switch (hw->mac.type) { 5082 case ixgbe_mac_X540: 5083 case ixgbe_mac_X550: 5084 case ixgbe_mac_X550EM_x: 5085 case ixgbe_mac_x550em_a: 5086 dv_id = IXGBE_DV_X540(link, tc); 5087 break; 5088 default: 5089 dv_id = IXGBE_DV(link, tc); 5090 break; 5091 } 5092 5093 /* Loopback switch introduces additional latency */ 5094 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5095 dv_id += IXGBE_B2BT(tc); 5096 5097 /* Delay value is calculated in bit times convert to KB */ 5098 kb = IXGBE_BT2KB(dv_id); 5099 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5100 5101 marker = rx_pba - kb; 5102 5103 /* It is possible that the packet buffer is not large enough 5104 * to provide required headroom. In this case throw an error 5105 * to user and a do the best we can. 5106 */ 5107 if (marker < 0) { 5108 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5109 "headroom to support flow control." 5110 "Decrease MTU or number of traffic classes\n", pb); 5111 marker = tc + 1; 5112 } 5113 5114 return marker; 5115 } 5116 5117 /** 5118 * ixgbe_lpbthresh - calculate low water mark for for flow control 5119 * 5120 * @adapter: board private structure to calculate for 5121 * @pb: packet buffer to calculate 5122 */ 5123 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5124 { 5125 struct ixgbe_hw *hw = &adapter->hw; 5126 struct net_device *dev = adapter->netdev; 5127 int tc; 5128 u32 dv_id; 5129 5130 /* Calculate max LAN frame size */ 5131 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5132 5133 #ifdef IXGBE_FCOE 5134 /* FCoE traffic class uses FCOE jumbo frames */ 5135 if ((dev->features & NETIF_F_FCOE_MTU) && 5136 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5137 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5138 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5139 #endif 5140 5141 /* Calculate delay value for device */ 5142 switch (hw->mac.type) { 5143 case ixgbe_mac_X540: 5144 case ixgbe_mac_X550: 5145 case ixgbe_mac_X550EM_x: 5146 case ixgbe_mac_x550em_a: 5147 dv_id = IXGBE_LOW_DV_X540(tc); 5148 break; 5149 default: 5150 dv_id = IXGBE_LOW_DV(tc); 5151 break; 5152 } 5153 5154 /* Delay value is calculated in bit times convert to KB */ 5155 return IXGBE_BT2KB(dv_id); 5156 } 5157 5158 /* 5159 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5160 */ 5161 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5162 { 5163 struct ixgbe_hw *hw = &adapter->hw; 5164 int num_tc = adapter->hw_tcs; 5165 int i; 5166 5167 if (!num_tc) 5168 num_tc = 1; 5169 5170 for (i = 0; i < num_tc; i++) { 5171 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5172 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5173 5174 /* Low water marks must not be larger than high water marks */ 5175 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5176 hw->fc.low_water[i] = 0; 5177 } 5178 5179 for (; i < MAX_TRAFFIC_CLASS; i++) 5180 hw->fc.high_water[i] = 0; 5181 } 5182 5183 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5184 { 5185 struct ixgbe_hw *hw = &adapter->hw; 5186 int hdrm; 5187 u8 tc = adapter->hw_tcs; 5188 5189 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5190 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5191 hdrm = 32 << adapter->fdir_pballoc; 5192 else 5193 hdrm = 0; 5194 5195 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5196 ixgbe_pbthresh_setup(adapter); 5197 } 5198 5199 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5200 { 5201 struct ixgbe_hw *hw = &adapter->hw; 5202 struct hlist_node *node2; 5203 struct ixgbe_fdir_filter *filter; 5204 5205 spin_lock(&adapter->fdir_perfect_lock); 5206 5207 if (!hlist_empty(&adapter->fdir_filter_list)) 5208 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5209 5210 hlist_for_each_entry_safe(filter, node2, 5211 &adapter->fdir_filter_list, fdir_node) { 5212 ixgbe_fdir_write_perfect_filter_82599(hw, 5213 &filter->filter, 5214 filter->sw_idx, 5215 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5216 IXGBE_FDIR_DROP_QUEUE : 5217 adapter->rx_ring[filter->action]->reg_idx); 5218 } 5219 5220 spin_unlock(&adapter->fdir_perfect_lock); 5221 } 5222 5223 /** 5224 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5225 * @rx_ring: ring to free buffers from 5226 **/ 5227 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5228 { 5229 u16 i = rx_ring->next_to_clean; 5230 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5231 5232 /* Free all the Rx ring sk_buffs */ 5233 while (i != rx_ring->next_to_alloc) { 5234 if (rx_buffer->skb) { 5235 struct sk_buff *skb = rx_buffer->skb; 5236 if (IXGBE_CB(skb)->page_released) 5237 dma_unmap_page_attrs(rx_ring->dev, 5238 IXGBE_CB(skb)->dma, 5239 ixgbe_rx_pg_size(rx_ring), 5240 DMA_FROM_DEVICE, 5241 IXGBE_RX_DMA_ATTR); 5242 dev_kfree_skb(skb); 5243 } 5244 5245 /* Invalidate cache lines that may have been written to by 5246 * device so that we avoid corrupting memory. 5247 */ 5248 dma_sync_single_range_for_cpu(rx_ring->dev, 5249 rx_buffer->dma, 5250 rx_buffer->page_offset, 5251 ixgbe_rx_bufsz(rx_ring), 5252 DMA_FROM_DEVICE); 5253 5254 /* free resources associated with mapping */ 5255 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5256 ixgbe_rx_pg_size(rx_ring), 5257 DMA_FROM_DEVICE, 5258 IXGBE_RX_DMA_ATTR); 5259 __page_frag_cache_drain(rx_buffer->page, 5260 rx_buffer->pagecnt_bias); 5261 5262 i++; 5263 rx_buffer++; 5264 if (i == rx_ring->count) { 5265 i = 0; 5266 rx_buffer = rx_ring->rx_buffer_info; 5267 } 5268 } 5269 5270 rx_ring->next_to_alloc = 0; 5271 rx_ring->next_to_clean = 0; 5272 rx_ring->next_to_use = 0; 5273 } 5274 5275 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5276 struct ixgbe_fwd_adapter *accel) 5277 { 5278 struct net_device *vdev = accel->netdev; 5279 int i, baseq, err; 5280 5281 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5282 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5283 accel->pool, adapter->num_rx_pools, 5284 baseq, baseq + adapter->num_rx_queues_per_pool); 5285 5286 accel->rx_base_queue = baseq; 5287 accel->tx_base_queue = baseq; 5288 5289 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5290 adapter->rx_ring[baseq + i]->netdev = vdev; 5291 5292 /* Guarantee all rings are updated before we update the 5293 * MAC address filter. 5294 */ 5295 wmb(); 5296 5297 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5298 * need to only treat it as an error value if it is negative. 5299 */ 5300 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5301 VMDQ_P(accel->pool)); 5302 if (err >= 0) 5303 return 0; 5304 5305 /* if we cannot add the MAC rule then disable the offload */ 5306 macvlan_release_l2fw_offload(vdev); 5307 5308 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5309 adapter->rx_ring[baseq + i]->netdev = NULL; 5310 5311 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5312 5313 clear_bit(accel->pool, adapter->fwd_bitmask); 5314 kfree(accel); 5315 5316 return err; 5317 } 5318 5319 static int ixgbe_macvlan_up(struct net_device *vdev, void *data) 5320 { 5321 struct ixgbe_adapter *adapter = data; 5322 struct ixgbe_fwd_adapter *accel; 5323 5324 if (!netif_is_macvlan(vdev)) 5325 return 0; 5326 5327 accel = macvlan_accel_priv(vdev); 5328 if (!accel) 5329 return 0; 5330 5331 ixgbe_fwd_ring_up(adapter, accel); 5332 5333 return 0; 5334 } 5335 5336 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5337 { 5338 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5339 ixgbe_macvlan_up, adapter); 5340 } 5341 5342 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5343 { 5344 struct ixgbe_hw *hw = &adapter->hw; 5345 5346 ixgbe_configure_pb(adapter); 5347 #ifdef CONFIG_IXGBE_DCB 5348 ixgbe_configure_dcb(adapter); 5349 #endif 5350 /* 5351 * We must restore virtualization before VLANs or else 5352 * the VLVF registers will not be populated 5353 */ 5354 ixgbe_configure_virtualization(adapter); 5355 5356 ixgbe_set_rx_mode(adapter->netdev); 5357 ixgbe_restore_vlan(adapter); 5358 ixgbe_ipsec_restore(adapter); 5359 5360 switch (hw->mac.type) { 5361 case ixgbe_mac_82599EB: 5362 case ixgbe_mac_X540: 5363 hw->mac.ops.disable_rx_buff(hw); 5364 break; 5365 default: 5366 break; 5367 } 5368 5369 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5370 ixgbe_init_fdir_signature_82599(&adapter->hw, 5371 adapter->fdir_pballoc); 5372 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5373 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5374 adapter->fdir_pballoc); 5375 ixgbe_fdir_filter_restore(adapter); 5376 } 5377 5378 switch (hw->mac.type) { 5379 case ixgbe_mac_82599EB: 5380 case ixgbe_mac_X540: 5381 hw->mac.ops.enable_rx_buff(hw); 5382 break; 5383 default: 5384 break; 5385 } 5386 5387 #ifdef CONFIG_IXGBE_DCA 5388 /* configure DCA */ 5389 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5390 ixgbe_setup_dca(adapter); 5391 #endif /* CONFIG_IXGBE_DCA */ 5392 5393 #ifdef IXGBE_FCOE 5394 /* configure FCoE L2 filters, redirection table, and Rx control */ 5395 ixgbe_configure_fcoe(adapter); 5396 5397 #endif /* IXGBE_FCOE */ 5398 ixgbe_configure_tx(adapter); 5399 ixgbe_configure_rx(adapter); 5400 ixgbe_configure_dfwd(adapter); 5401 } 5402 5403 /** 5404 * ixgbe_sfp_link_config - set up SFP+ link 5405 * @adapter: pointer to private adapter struct 5406 **/ 5407 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5408 { 5409 /* 5410 * We are assuming the worst case scenario here, and that 5411 * is that an SFP was inserted/removed after the reset 5412 * but before SFP detection was enabled. As such the best 5413 * solution is to just start searching as soon as we start 5414 */ 5415 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5416 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5417 5418 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5419 adapter->sfp_poll_time = 0; 5420 } 5421 5422 /** 5423 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5424 * @hw: pointer to private hardware struct 5425 * 5426 * Returns 0 on success, negative on failure 5427 **/ 5428 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5429 { 5430 u32 speed; 5431 bool autoneg, link_up = false; 5432 int ret = IXGBE_ERR_LINK_SETUP; 5433 5434 if (hw->mac.ops.check_link) 5435 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5436 5437 if (ret) 5438 return ret; 5439 5440 speed = hw->phy.autoneg_advertised; 5441 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5442 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5443 &autoneg); 5444 if (ret) 5445 return ret; 5446 5447 if (hw->mac.ops.setup_link) 5448 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5449 5450 return ret; 5451 } 5452 5453 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5454 { 5455 struct ixgbe_hw *hw = &adapter->hw; 5456 u32 gpie = 0; 5457 5458 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5459 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5460 IXGBE_GPIE_OCD; 5461 gpie |= IXGBE_GPIE_EIAME; 5462 /* 5463 * use EIAM to auto-mask when MSI-X interrupt is asserted 5464 * this saves a register write for every interrupt 5465 */ 5466 switch (hw->mac.type) { 5467 case ixgbe_mac_82598EB: 5468 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5469 break; 5470 case ixgbe_mac_82599EB: 5471 case ixgbe_mac_X540: 5472 case ixgbe_mac_X550: 5473 case ixgbe_mac_X550EM_x: 5474 case ixgbe_mac_x550em_a: 5475 default: 5476 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5477 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5478 break; 5479 } 5480 } else { 5481 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5482 * specifically only auto mask tx and rx interrupts */ 5483 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5484 } 5485 5486 /* XXX: to interrupt immediately for EICS writes, enable this */ 5487 /* gpie |= IXGBE_GPIE_EIMEN; */ 5488 5489 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5490 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5491 5492 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5493 case IXGBE_82599_VMDQ_8Q_MASK: 5494 gpie |= IXGBE_GPIE_VTMODE_16; 5495 break; 5496 case IXGBE_82599_VMDQ_4Q_MASK: 5497 gpie |= IXGBE_GPIE_VTMODE_32; 5498 break; 5499 default: 5500 gpie |= IXGBE_GPIE_VTMODE_64; 5501 break; 5502 } 5503 } 5504 5505 /* Enable Thermal over heat sensor interrupt */ 5506 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5507 switch (adapter->hw.mac.type) { 5508 case ixgbe_mac_82599EB: 5509 gpie |= IXGBE_SDP0_GPIEN_8259X; 5510 break; 5511 default: 5512 break; 5513 } 5514 } 5515 5516 /* Enable fan failure interrupt */ 5517 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5518 gpie |= IXGBE_SDP1_GPIEN(hw); 5519 5520 switch (hw->mac.type) { 5521 case ixgbe_mac_82599EB: 5522 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5523 break; 5524 case ixgbe_mac_X550EM_x: 5525 case ixgbe_mac_x550em_a: 5526 gpie |= IXGBE_SDP0_GPIEN_X540; 5527 break; 5528 default: 5529 break; 5530 } 5531 5532 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5533 } 5534 5535 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5536 { 5537 struct ixgbe_hw *hw = &adapter->hw; 5538 int err; 5539 u32 ctrl_ext; 5540 5541 ixgbe_get_hw_control(adapter); 5542 ixgbe_setup_gpie(adapter); 5543 5544 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5545 ixgbe_configure_msix(adapter); 5546 else 5547 ixgbe_configure_msi_and_legacy(adapter); 5548 5549 /* enable the optics for 82599 SFP+ fiber */ 5550 if (hw->mac.ops.enable_tx_laser) 5551 hw->mac.ops.enable_tx_laser(hw); 5552 5553 if (hw->phy.ops.set_phy_power) 5554 hw->phy.ops.set_phy_power(hw, true); 5555 5556 smp_mb__before_atomic(); 5557 clear_bit(__IXGBE_DOWN, &adapter->state); 5558 ixgbe_napi_enable_all(adapter); 5559 5560 if (ixgbe_is_sfp(hw)) { 5561 ixgbe_sfp_link_config(adapter); 5562 } else { 5563 err = ixgbe_non_sfp_link_config(hw); 5564 if (err) 5565 e_err(probe, "link_config FAILED %d\n", err); 5566 } 5567 5568 /* clear any pending interrupts, may auto mask */ 5569 IXGBE_READ_REG(hw, IXGBE_EICR); 5570 ixgbe_irq_enable(adapter, true, true); 5571 5572 /* 5573 * If this adapter has a fan, check to see if we had a failure 5574 * before we enabled the interrupt. 5575 */ 5576 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5577 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5578 if (esdp & IXGBE_ESDP_SDP1) 5579 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5580 } 5581 5582 /* bring the link up in the watchdog, this could race with our first 5583 * link up interrupt but shouldn't be a problem */ 5584 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5585 adapter->link_check_timeout = jiffies; 5586 mod_timer(&adapter->service_timer, jiffies); 5587 5588 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5589 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5590 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5591 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5592 } 5593 5594 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5595 { 5596 WARN_ON(in_interrupt()); 5597 /* put off any impending NetWatchDogTimeout */ 5598 netif_trans_update(adapter->netdev); 5599 5600 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5601 usleep_range(1000, 2000); 5602 if (adapter->hw.phy.type == ixgbe_phy_fw) 5603 ixgbe_watchdog_link_is_down(adapter); 5604 ixgbe_down(adapter); 5605 /* 5606 * If SR-IOV enabled then wait a bit before bringing the adapter 5607 * back up to give the VFs time to respond to the reset. The 5608 * two second wait is based upon the watchdog timer cycle in 5609 * the VF driver. 5610 */ 5611 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5612 msleep(2000); 5613 ixgbe_up(adapter); 5614 clear_bit(__IXGBE_RESETTING, &adapter->state); 5615 } 5616 5617 void ixgbe_up(struct ixgbe_adapter *adapter) 5618 { 5619 /* hardware has been reset, we need to reload some things */ 5620 ixgbe_configure(adapter); 5621 5622 ixgbe_up_complete(adapter); 5623 } 5624 5625 void ixgbe_reset(struct ixgbe_adapter *adapter) 5626 { 5627 struct ixgbe_hw *hw = &adapter->hw; 5628 struct net_device *netdev = adapter->netdev; 5629 int err; 5630 5631 if (ixgbe_removed(hw->hw_addr)) 5632 return; 5633 /* lock SFP init bit to prevent race conditions with the watchdog */ 5634 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5635 usleep_range(1000, 2000); 5636 5637 /* clear all SFP and link config related flags while holding SFP_INIT */ 5638 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5639 IXGBE_FLAG2_SFP_NEEDS_RESET); 5640 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5641 5642 err = hw->mac.ops.init_hw(hw); 5643 switch (err) { 5644 case 0: 5645 case IXGBE_ERR_SFP_NOT_PRESENT: 5646 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5647 break; 5648 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5649 e_dev_err("master disable timed out\n"); 5650 break; 5651 case IXGBE_ERR_EEPROM_VERSION: 5652 /* We are running on a pre-production device, log a warning */ 5653 e_dev_warn("This device is a pre-production adapter/LOM. " 5654 "Please be aware there may be issues associated with " 5655 "your hardware. If you are experiencing problems " 5656 "please contact your Intel or hardware " 5657 "representative who provided you with this " 5658 "hardware.\n"); 5659 break; 5660 default: 5661 e_dev_err("Hardware Error: %d\n", err); 5662 } 5663 5664 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5665 5666 /* flush entries out of MAC table */ 5667 ixgbe_flush_sw_mac_table(adapter); 5668 __dev_uc_unsync(netdev, NULL); 5669 5670 /* do not flush user set addresses */ 5671 ixgbe_mac_set_default_filter(adapter); 5672 5673 /* update SAN MAC vmdq pool selection */ 5674 if (hw->mac.san_mac_rar_index) 5675 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5676 5677 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5678 ixgbe_ptp_reset(adapter); 5679 5680 if (hw->phy.ops.set_phy_power) { 5681 if (!netif_running(adapter->netdev) && !adapter->wol) 5682 hw->phy.ops.set_phy_power(hw, false); 5683 else 5684 hw->phy.ops.set_phy_power(hw, true); 5685 } 5686 } 5687 5688 /** 5689 * ixgbe_clean_tx_ring - Free Tx Buffers 5690 * @tx_ring: ring to be cleaned 5691 **/ 5692 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5693 { 5694 u16 i = tx_ring->next_to_clean; 5695 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5696 5697 while (i != tx_ring->next_to_use) { 5698 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5699 5700 /* Free all the Tx ring sk_buffs */ 5701 if (ring_is_xdp(tx_ring)) 5702 xdp_return_frame(tx_buffer->xdpf); 5703 else 5704 dev_kfree_skb_any(tx_buffer->skb); 5705 5706 /* unmap skb header data */ 5707 dma_unmap_single(tx_ring->dev, 5708 dma_unmap_addr(tx_buffer, dma), 5709 dma_unmap_len(tx_buffer, len), 5710 DMA_TO_DEVICE); 5711 5712 /* check for eop_desc to determine the end of the packet */ 5713 eop_desc = tx_buffer->next_to_watch; 5714 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5715 5716 /* unmap remaining buffers */ 5717 while (tx_desc != eop_desc) { 5718 tx_buffer++; 5719 tx_desc++; 5720 i++; 5721 if (unlikely(i == tx_ring->count)) { 5722 i = 0; 5723 tx_buffer = tx_ring->tx_buffer_info; 5724 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5725 } 5726 5727 /* unmap any remaining paged data */ 5728 if (dma_unmap_len(tx_buffer, len)) 5729 dma_unmap_page(tx_ring->dev, 5730 dma_unmap_addr(tx_buffer, dma), 5731 dma_unmap_len(tx_buffer, len), 5732 DMA_TO_DEVICE); 5733 } 5734 5735 /* move us one more past the eop_desc for start of next pkt */ 5736 tx_buffer++; 5737 i++; 5738 if (unlikely(i == tx_ring->count)) { 5739 i = 0; 5740 tx_buffer = tx_ring->tx_buffer_info; 5741 } 5742 } 5743 5744 /* reset BQL for queue */ 5745 if (!ring_is_xdp(tx_ring)) 5746 netdev_tx_reset_queue(txring_txq(tx_ring)); 5747 5748 /* reset next_to_use and next_to_clean */ 5749 tx_ring->next_to_use = 0; 5750 tx_ring->next_to_clean = 0; 5751 } 5752 5753 /** 5754 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5755 * @adapter: board private structure 5756 **/ 5757 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5758 { 5759 int i; 5760 5761 for (i = 0; i < adapter->num_rx_queues; i++) 5762 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5763 } 5764 5765 /** 5766 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5767 * @adapter: board private structure 5768 **/ 5769 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5770 { 5771 int i; 5772 5773 for (i = 0; i < adapter->num_tx_queues; i++) 5774 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5775 for (i = 0; i < adapter->num_xdp_queues; i++) 5776 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5777 } 5778 5779 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5780 { 5781 struct hlist_node *node2; 5782 struct ixgbe_fdir_filter *filter; 5783 5784 spin_lock(&adapter->fdir_perfect_lock); 5785 5786 hlist_for_each_entry_safe(filter, node2, 5787 &adapter->fdir_filter_list, fdir_node) { 5788 hlist_del(&filter->fdir_node); 5789 kfree(filter); 5790 } 5791 adapter->fdir_filter_count = 0; 5792 5793 spin_unlock(&adapter->fdir_perfect_lock); 5794 } 5795 5796 void ixgbe_down(struct ixgbe_adapter *adapter) 5797 { 5798 struct net_device *netdev = adapter->netdev; 5799 struct ixgbe_hw *hw = &adapter->hw; 5800 int i; 5801 5802 /* signal that we are down to the interrupt handler */ 5803 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5804 return; /* do nothing if already down */ 5805 5806 /* disable receives */ 5807 hw->mac.ops.disable_rx(hw); 5808 5809 /* disable all enabled rx queues */ 5810 for (i = 0; i < adapter->num_rx_queues; i++) 5811 /* this call also flushes the previous write */ 5812 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5813 5814 usleep_range(10000, 20000); 5815 5816 /* synchronize_sched() needed for pending XDP buffers to drain */ 5817 if (adapter->xdp_ring[0]) 5818 synchronize_sched(); 5819 netif_tx_stop_all_queues(netdev); 5820 5821 /* call carrier off first to avoid false dev_watchdog timeouts */ 5822 netif_carrier_off(netdev); 5823 netif_tx_disable(netdev); 5824 5825 ixgbe_irq_disable(adapter); 5826 5827 ixgbe_napi_disable_all(adapter); 5828 5829 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5830 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5831 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5832 5833 del_timer_sync(&adapter->service_timer); 5834 5835 if (adapter->num_vfs) { 5836 /* Clear EITR Select mapping */ 5837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5838 5839 /* Mark all the VFs as inactive */ 5840 for (i = 0 ; i < adapter->num_vfs; i++) 5841 adapter->vfinfo[i].clear_to_send = false; 5842 5843 /* ping all the active vfs to let them know we are going down */ 5844 ixgbe_ping_all_vfs(adapter); 5845 5846 /* Disable all VFTE/VFRE TX/RX */ 5847 ixgbe_disable_tx_rx(adapter); 5848 } 5849 5850 /* disable transmits in the hardware now that interrupts are off */ 5851 for (i = 0; i < adapter->num_tx_queues; i++) { 5852 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5853 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5854 } 5855 for (i = 0; i < adapter->num_xdp_queues; i++) { 5856 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5857 5858 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5859 } 5860 5861 /* Disable the Tx DMA engine on 82599 and later MAC */ 5862 switch (hw->mac.type) { 5863 case ixgbe_mac_82599EB: 5864 case ixgbe_mac_X540: 5865 case ixgbe_mac_X550: 5866 case ixgbe_mac_X550EM_x: 5867 case ixgbe_mac_x550em_a: 5868 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5869 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5870 ~IXGBE_DMATXCTL_TE)); 5871 break; 5872 default: 5873 break; 5874 } 5875 5876 if (!pci_channel_offline(adapter->pdev)) 5877 ixgbe_reset(adapter); 5878 5879 /* power down the optics for 82599 SFP+ fiber */ 5880 if (hw->mac.ops.disable_tx_laser) 5881 hw->mac.ops.disable_tx_laser(hw); 5882 5883 ixgbe_clean_all_tx_rings(adapter); 5884 ixgbe_clean_all_rx_rings(adapter); 5885 } 5886 5887 /** 5888 * ixgbe_eee_capable - helper function to determine EEE support on X550 5889 * @adapter: board private structure 5890 */ 5891 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5892 { 5893 struct ixgbe_hw *hw = &adapter->hw; 5894 5895 switch (hw->device_id) { 5896 case IXGBE_DEV_ID_X550EM_A_1G_T: 5897 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 5898 if (!hw->phy.eee_speeds_supported) 5899 break; 5900 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 5901 if (!hw->phy.eee_speeds_advertised) 5902 break; 5903 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 5904 break; 5905 default: 5906 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 5907 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 5908 break; 5909 } 5910 } 5911 5912 /** 5913 * ixgbe_tx_timeout - Respond to a Tx Hang 5914 * @netdev: network interface device structure 5915 **/ 5916 static void ixgbe_tx_timeout(struct net_device *netdev) 5917 { 5918 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5919 5920 /* Do the reset outside of interrupt context */ 5921 ixgbe_tx_timeout_reset(adapter); 5922 } 5923 5924 #ifdef CONFIG_IXGBE_DCB 5925 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 5926 { 5927 struct ixgbe_hw *hw = &adapter->hw; 5928 struct tc_configuration *tc; 5929 int j; 5930 5931 switch (hw->mac.type) { 5932 case ixgbe_mac_82598EB: 5933 case ixgbe_mac_82599EB: 5934 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5935 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5936 break; 5937 case ixgbe_mac_X540: 5938 case ixgbe_mac_X550: 5939 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5940 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5941 break; 5942 case ixgbe_mac_X550EM_x: 5943 case ixgbe_mac_x550em_a: 5944 default: 5945 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 5946 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 5947 break; 5948 } 5949 5950 /* Configure DCB traffic classes */ 5951 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5952 tc = &adapter->dcb_cfg.tc_config[j]; 5953 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5954 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5955 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5956 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5957 tc->dcb_pfc = pfc_disabled; 5958 } 5959 5960 /* Initialize default user to priority mapping, UPx->TC0 */ 5961 tc = &adapter->dcb_cfg.tc_config[0]; 5962 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5963 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5964 5965 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5966 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5967 adapter->dcb_cfg.pfc_mode_enable = false; 5968 adapter->dcb_set_bitmap = 0x00; 5969 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 5970 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5971 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5972 sizeof(adapter->temp_dcb_cfg)); 5973 } 5974 #endif 5975 5976 /** 5977 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5978 * @adapter: board private structure to initialize 5979 * @ii: pointer to ixgbe_info for device 5980 * 5981 * ixgbe_sw_init initializes the Adapter private data structure. 5982 * Fields are initialized based on PCI device information and 5983 * OS network device settings (MTU size). 5984 **/ 5985 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 5986 const struct ixgbe_info *ii) 5987 { 5988 struct ixgbe_hw *hw = &adapter->hw; 5989 struct pci_dev *pdev = adapter->pdev; 5990 unsigned int rss, fdir; 5991 u32 fwsm; 5992 int i; 5993 5994 /* PCI config space info */ 5995 5996 hw->vendor_id = pdev->vendor; 5997 hw->device_id = pdev->device; 5998 hw->revision_id = pdev->revision; 5999 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6000 hw->subsystem_device_id = pdev->subsystem_device; 6001 6002 /* get_invariants needs the device IDs */ 6003 ii->get_invariants(hw); 6004 6005 /* Set common capability flags and settings */ 6006 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6007 adapter->ring_feature[RING_F_RSS].limit = rss; 6008 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6009 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6010 adapter->atr_sample_rate = 20; 6011 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6012 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6013 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6014 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6015 #ifdef CONFIG_IXGBE_DCA 6016 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6017 #endif 6018 #ifdef CONFIG_IXGBE_DCB 6019 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6020 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6021 #endif 6022 #ifdef IXGBE_FCOE 6023 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6024 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6025 #ifdef CONFIG_IXGBE_DCB 6026 /* Default traffic class to use for FCoE */ 6027 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6028 #endif /* CONFIG_IXGBE_DCB */ 6029 #endif /* IXGBE_FCOE */ 6030 6031 /* initialize static ixgbe jump table entries */ 6032 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6033 GFP_KERNEL); 6034 if (!adapter->jump_tables[0]) 6035 return -ENOMEM; 6036 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6037 6038 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6039 adapter->jump_tables[i] = NULL; 6040 6041 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6042 sizeof(struct ixgbe_mac_addr), 6043 GFP_ATOMIC); 6044 if (!adapter->mac_table) 6045 return -ENOMEM; 6046 6047 if (ixgbe_init_rss_key(adapter)) 6048 return -ENOMEM; 6049 6050 /* Set MAC specific capability flags and exceptions */ 6051 switch (hw->mac.type) { 6052 case ixgbe_mac_82598EB: 6053 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6054 6055 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6056 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6057 6058 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6059 adapter->ring_feature[RING_F_FDIR].limit = 0; 6060 adapter->atr_sample_rate = 0; 6061 adapter->fdir_pballoc = 0; 6062 #ifdef IXGBE_FCOE 6063 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6064 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6065 #ifdef CONFIG_IXGBE_DCB 6066 adapter->fcoe.up = 0; 6067 #endif /* IXGBE_DCB */ 6068 #endif /* IXGBE_FCOE */ 6069 break; 6070 case ixgbe_mac_82599EB: 6071 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6072 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6073 break; 6074 case ixgbe_mac_X540: 6075 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6076 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6077 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6078 break; 6079 case ixgbe_mac_x550em_a: 6080 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6081 switch (hw->device_id) { 6082 case IXGBE_DEV_ID_X550EM_A_1G_T: 6083 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6084 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6085 break; 6086 default: 6087 break; 6088 } 6089 /* fall through */ 6090 case ixgbe_mac_X550EM_x: 6091 #ifdef CONFIG_IXGBE_DCB 6092 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6093 #endif 6094 #ifdef IXGBE_FCOE 6095 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6096 #ifdef CONFIG_IXGBE_DCB 6097 adapter->fcoe.up = 0; 6098 #endif /* IXGBE_DCB */ 6099 #endif /* IXGBE_FCOE */ 6100 /* Fall Through */ 6101 case ixgbe_mac_X550: 6102 if (hw->mac.type == ixgbe_mac_X550) 6103 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6104 #ifdef CONFIG_IXGBE_DCA 6105 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6106 #endif 6107 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6108 break; 6109 default: 6110 break; 6111 } 6112 6113 #ifdef IXGBE_FCOE 6114 /* FCoE support exists, always init the FCoE lock */ 6115 spin_lock_init(&adapter->fcoe.lock); 6116 6117 #endif 6118 /* n-tuple support exists, always init our spinlock */ 6119 spin_lock_init(&adapter->fdir_perfect_lock); 6120 6121 #ifdef CONFIG_IXGBE_DCB 6122 ixgbe_init_dcb(adapter); 6123 #endif 6124 ixgbe_init_ipsec_offload(adapter); 6125 6126 /* default flow control settings */ 6127 hw->fc.requested_mode = ixgbe_fc_full; 6128 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6129 ixgbe_pbthresh_setup(adapter); 6130 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6131 hw->fc.send_xon = true; 6132 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6133 6134 #ifdef CONFIG_PCI_IOV 6135 if (max_vfs > 0) 6136 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6137 6138 /* assign number of SR-IOV VFs */ 6139 if (hw->mac.type != ixgbe_mac_82598EB) { 6140 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6141 max_vfs = 0; 6142 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6143 } 6144 } 6145 #endif /* CONFIG_PCI_IOV */ 6146 6147 /* enable itr by default in dynamic mode */ 6148 adapter->rx_itr_setting = 1; 6149 adapter->tx_itr_setting = 1; 6150 6151 /* set default ring sizes */ 6152 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6153 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6154 6155 /* set default work limits */ 6156 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6157 6158 /* initialize eeprom parameters */ 6159 if (ixgbe_init_eeprom_params_generic(hw)) { 6160 e_dev_err("EEPROM initialization failed\n"); 6161 return -EIO; 6162 } 6163 6164 /* PF holds first pool slot */ 6165 set_bit(0, adapter->fwd_bitmask); 6166 set_bit(__IXGBE_DOWN, &adapter->state); 6167 6168 return 0; 6169 } 6170 6171 /** 6172 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6173 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6174 * 6175 * Return 0 on success, negative on failure 6176 **/ 6177 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6178 { 6179 struct device *dev = tx_ring->dev; 6180 int orig_node = dev_to_node(dev); 6181 int ring_node = -1; 6182 int size; 6183 6184 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6185 6186 if (tx_ring->q_vector) 6187 ring_node = tx_ring->q_vector->numa_node; 6188 6189 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6190 if (!tx_ring->tx_buffer_info) 6191 tx_ring->tx_buffer_info = vmalloc(size); 6192 if (!tx_ring->tx_buffer_info) 6193 goto err; 6194 6195 /* round up to nearest 4K */ 6196 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6197 tx_ring->size = ALIGN(tx_ring->size, 4096); 6198 6199 set_dev_node(dev, ring_node); 6200 tx_ring->desc = dma_alloc_coherent(dev, 6201 tx_ring->size, 6202 &tx_ring->dma, 6203 GFP_KERNEL); 6204 set_dev_node(dev, orig_node); 6205 if (!tx_ring->desc) 6206 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6207 &tx_ring->dma, GFP_KERNEL); 6208 if (!tx_ring->desc) 6209 goto err; 6210 6211 tx_ring->next_to_use = 0; 6212 tx_ring->next_to_clean = 0; 6213 return 0; 6214 6215 err: 6216 vfree(tx_ring->tx_buffer_info); 6217 tx_ring->tx_buffer_info = NULL; 6218 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6219 return -ENOMEM; 6220 } 6221 6222 /** 6223 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6224 * @adapter: board private structure 6225 * 6226 * If this function returns with an error, then it's possible one or 6227 * more of the rings is populated (while the rest are not). It is the 6228 * callers duty to clean those orphaned rings. 6229 * 6230 * Return 0 on success, negative on failure 6231 **/ 6232 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6233 { 6234 int i, j = 0, err = 0; 6235 6236 for (i = 0; i < adapter->num_tx_queues; i++) { 6237 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6238 if (!err) 6239 continue; 6240 6241 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6242 goto err_setup_tx; 6243 } 6244 for (j = 0; j < adapter->num_xdp_queues; j++) { 6245 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6246 if (!err) 6247 continue; 6248 6249 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6250 goto err_setup_tx; 6251 } 6252 6253 return 0; 6254 err_setup_tx: 6255 /* rewind the index freeing the rings as we go */ 6256 while (j--) 6257 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6258 while (i--) 6259 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6260 return err; 6261 } 6262 6263 /** 6264 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6265 * @adapter: pointer to ixgbe_adapter 6266 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6267 * 6268 * Returns 0 on success, negative on failure 6269 **/ 6270 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6271 struct ixgbe_ring *rx_ring) 6272 { 6273 struct device *dev = rx_ring->dev; 6274 int orig_node = dev_to_node(dev); 6275 int ring_node = -1; 6276 int size, err; 6277 6278 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6279 6280 if (rx_ring->q_vector) 6281 ring_node = rx_ring->q_vector->numa_node; 6282 6283 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6284 if (!rx_ring->rx_buffer_info) 6285 rx_ring->rx_buffer_info = vmalloc(size); 6286 if (!rx_ring->rx_buffer_info) 6287 goto err; 6288 6289 /* Round up to nearest 4K */ 6290 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6291 rx_ring->size = ALIGN(rx_ring->size, 4096); 6292 6293 set_dev_node(dev, ring_node); 6294 rx_ring->desc = dma_alloc_coherent(dev, 6295 rx_ring->size, 6296 &rx_ring->dma, 6297 GFP_KERNEL); 6298 set_dev_node(dev, orig_node); 6299 if (!rx_ring->desc) 6300 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6301 &rx_ring->dma, GFP_KERNEL); 6302 if (!rx_ring->desc) 6303 goto err; 6304 6305 rx_ring->next_to_clean = 0; 6306 rx_ring->next_to_use = 0; 6307 6308 /* XDP RX-queue info */ 6309 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6310 rx_ring->queue_index) < 0) 6311 goto err; 6312 6313 err = xdp_rxq_info_reg_mem_model(&rx_ring->xdp_rxq, 6314 MEM_TYPE_PAGE_SHARED, NULL); 6315 if (err) { 6316 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6317 goto err; 6318 } 6319 6320 rx_ring->xdp_prog = adapter->xdp_prog; 6321 6322 return 0; 6323 err: 6324 vfree(rx_ring->rx_buffer_info); 6325 rx_ring->rx_buffer_info = NULL; 6326 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6327 return -ENOMEM; 6328 } 6329 6330 /** 6331 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6332 * @adapter: board private structure 6333 * 6334 * If this function returns with an error, then it's possible one or 6335 * more of the rings is populated (while the rest are not). It is the 6336 * callers duty to clean those orphaned rings. 6337 * 6338 * Return 0 on success, negative on failure 6339 **/ 6340 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6341 { 6342 int i, err = 0; 6343 6344 for (i = 0; i < adapter->num_rx_queues; i++) { 6345 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6346 if (!err) 6347 continue; 6348 6349 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6350 goto err_setup_rx; 6351 } 6352 6353 #ifdef IXGBE_FCOE 6354 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6355 if (!err) 6356 #endif 6357 return 0; 6358 err_setup_rx: 6359 /* rewind the index freeing the rings as we go */ 6360 while (i--) 6361 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6362 return err; 6363 } 6364 6365 /** 6366 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6367 * @tx_ring: Tx descriptor ring for a specific queue 6368 * 6369 * Free all transmit software resources 6370 **/ 6371 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6372 { 6373 ixgbe_clean_tx_ring(tx_ring); 6374 6375 vfree(tx_ring->tx_buffer_info); 6376 tx_ring->tx_buffer_info = NULL; 6377 6378 /* if not set, then don't free */ 6379 if (!tx_ring->desc) 6380 return; 6381 6382 dma_free_coherent(tx_ring->dev, tx_ring->size, 6383 tx_ring->desc, tx_ring->dma); 6384 6385 tx_ring->desc = NULL; 6386 } 6387 6388 /** 6389 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6390 * @adapter: board private structure 6391 * 6392 * Free all transmit software resources 6393 **/ 6394 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6395 { 6396 int i; 6397 6398 for (i = 0; i < adapter->num_tx_queues; i++) 6399 if (adapter->tx_ring[i]->desc) 6400 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6401 for (i = 0; i < adapter->num_xdp_queues; i++) 6402 if (adapter->xdp_ring[i]->desc) 6403 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6404 } 6405 6406 /** 6407 * ixgbe_free_rx_resources - Free Rx Resources 6408 * @rx_ring: ring to clean the resources from 6409 * 6410 * Free all receive software resources 6411 **/ 6412 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6413 { 6414 ixgbe_clean_rx_ring(rx_ring); 6415 6416 rx_ring->xdp_prog = NULL; 6417 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6418 vfree(rx_ring->rx_buffer_info); 6419 rx_ring->rx_buffer_info = NULL; 6420 6421 /* if not set, then don't free */ 6422 if (!rx_ring->desc) 6423 return; 6424 6425 dma_free_coherent(rx_ring->dev, rx_ring->size, 6426 rx_ring->desc, rx_ring->dma); 6427 6428 rx_ring->desc = NULL; 6429 } 6430 6431 /** 6432 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6433 * @adapter: board private structure 6434 * 6435 * Free all receive software resources 6436 **/ 6437 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6438 { 6439 int i; 6440 6441 #ifdef IXGBE_FCOE 6442 ixgbe_free_fcoe_ddp_resources(adapter); 6443 6444 #endif 6445 for (i = 0; i < adapter->num_rx_queues; i++) 6446 if (adapter->rx_ring[i]->desc) 6447 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6448 } 6449 6450 /** 6451 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6452 * @netdev: network interface device structure 6453 * @new_mtu: new value for maximum frame size 6454 * 6455 * Returns 0 on success, negative on failure 6456 **/ 6457 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6458 { 6459 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6460 6461 /* 6462 * For 82599EB we cannot allow legacy VFs to enable their receive 6463 * paths when MTU greater than 1500 is configured. So display a 6464 * warning that legacy VFs will be disabled. 6465 */ 6466 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6467 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6468 (new_mtu > ETH_DATA_LEN)) 6469 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6470 6471 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6472 6473 /* must set new MTU before calling down or up */ 6474 netdev->mtu = new_mtu; 6475 6476 if (netif_running(netdev)) 6477 ixgbe_reinit_locked(adapter); 6478 6479 return 0; 6480 } 6481 6482 /** 6483 * ixgbe_open - Called when a network interface is made active 6484 * @netdev: network interface device structure 6485 * 6486 * Returns 0 on success, negative value on failure 6487 * 6488 * The open entry point is called when a network interface is made 6489 * active by the system (IFF_UP). At this point all resources needed 6490 * for transmit and receive operations are allocated, the interrupt 6491 * handler is registered with the OS, the watchdog timer is started, 6492 * and the stack is notified that the interface is ready. 6493 **/ 6494 int ixgbe_open(struct net_device *netdev) 6495 { 6496 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6497 struct ixgbe_hw *hw = &adapter->hw; 6498 int err, queues; 6499 6500 /* disallow open during test */ 6501 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6502 return -EBUSY; 6503 6504 netif_carrier_off(netdev); 6505 6506 /* allocate transmit descriptors */ 6507 err = ixgbe_setup_all_tx_resources(adapter); 6508 if (err) 6509 goto err_setup_tx; 6510 6511 /* allocate receive descriptors */ 6512 err = ixgbe_setup_all_rx_resources(adapter); 6513 if (err) 6514 goto err_setup_rx; 6515 6516 ixgbe_configure(adapter); 6517 6518 err = ixgbe_request_irq(adapter); 6519 if (err) 6520 goto err_req_irq; 6521 6522 /* Notify the stack of the actual queue counts. */ 6523 queues = adapter->num_tx_queues; 6524 err = netif_set_real_num_tx_queues(netdev, queues); 6525 if (err) 6526 goto err_set_queues; 6527 6528 queues = adapter->num_rx_queues; 6529 err = netif_set_real_num_rx_queues(netdev, queues); 6530 if (err) 6531 goto err_set_queues; 6532 6533 ixgbe_ptp_init(adapter); 6534 6535 ixgbe_up_complete(adapter); 6536 6537 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6538 udp_tunnel_get_rx_info(netdev); 6539 6540 return 0; 6541 6542 err_set_queues: 6543 ixgbe_free_irq(adapter); 6544 err_req_irq: 6545 ixgbe_free_all_rx_resources(adapter); 6546 if (hw->phy.ops.set_phy_power && !adapter->wol) 6547 hw->phy.ops.set_phy_power(&adapter->hw, false); 6548 err_setup_rx: 6549 ixgbe_free_all_tx_resources(adapter); 6550 err_setup_tx: 6551 ixgbe_reset(adapter); 6552 6553 return err; 6554 } 6555 6556 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6557 { 6558 ixgbe_ptp_suspend(adapter); 6559 6560 if (adapter->hw.phy.ops.enter_lplu) { 6561 adapter->hw.phy.reset_disable = true; 6562 ixgbe_down(adapter); 6563 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6564 adapter->hw.phy.reset_disable = false; 6565 } else { 6566 ixgbe_down(adapter); 6567 } 6568 6569 ixgbe_free_irq(adapter); 6570 6571 ixgbe_free_all_tx_resources(adapter); 6572 ixgbe_free_all_rx_resources(adapter); 6573 } 6574 6575 /** 6576 * ixgbe_close - Disables a network interface 6577 * @netdev: network interface device structure 6578 * 6579 * Returns 0, this is not allowed to fail 6580 * 6581 * The close entry point is called when an interface is de-activated 6582 * by the OS. The hardware is still under the drivers control, but 6583 * needs to be disabled. A global MAC reset is issued to stop the 6584 * hardware, and all transmit and receive resources are freed. 6585 **/ 6586 int ixgbe_close(struct net_device *netdev) 6587 { 6588 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6589 6590 ixgbe_ptp_stop(adapter); 6591 6592 if (netif_device_present(netdev)) 6593 ixgbe_close_suspend(adapter); 6594 6595 ixgbe_fdir_filter_exit(adapter); 6596 6597 ixgbe_release_hw_control(adapter); 6598 6599 return 0; 6600 } 6601 6602 #ifdef CONFIG_PM 6603 static int ixgbe_resume(struct pci_dev *pdev) 6604 { 6605 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6606 struct net_device *netdev = adapter->netdev; 6607 u32 err; 6608 6609 adapter->hw.hw_addr = adapter->io_addr; 6610 pci_set_power_state(pdev, PCI_D0); 6611 pci_restore_state(pdev); 6612 /* 6613 * pci_restore_state clears dev->state_saved so call 6614 * pci_save_state to restore it. 6615 */ 6616 pci_save_state(pdev); 6617 6618 err = pci_enable_device_mem(pdev); 6619 if (err) { 6620 e_dev_err("Cannot enable PCI device from suspend\n"); 6621 return err; 6622 } 6623 smp_mb__before_atomic(); 6624 clear_bit(__IXGBE_DISABLED, &adapter->state); 6625 pci_set_master(pdev); 6626 6627 pci_wake_from_d3(pdev, false); 6628 6629 ixgbe_reset(adapter); 6630 6631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6632 6633 rtnl_lock(); 6634 err = ixgbe_init_interrupt_scheme(adapter); 6635 if (!err && netif_running(netdev)) 6636 err = ixgbe_open(netdev); 6637 6638 6639 if (!err) 6640 netif_device_attach(netdev); 6641 rtnl_unlock(); 6642 6643 return err; 6644 } 6645 #endif /* CONFIG_PM */ 6646 6647 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6648 { 6649 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6650 struct net_device *netdev = adapter->netdev; 6651 struct ixgbe_hw *hw = &adapter->hw; 6652 u32 ctrl; 6653 u32 wufc = adapter->wol; 6654 #ifdef CONFIG_PM 6655 int retval = 0; 6656 #endif 6657 6658 rtnl_lock(); 6659 netif_device_detach(netdev); 6660 6661 if (netif_running(netdev)) 6662 ixgbe_close_suspend(adapter); 6663 6664 ixgbe_clear_interrupt_scheme(adapter); 6665 rtnl_unlock(); 6666 6667 #ifdef CONFIG_PM 6668 retval = pci_save_state(pdev); 6669 if (retval) 6670 return retval; 6671 6672 #endif 6673 if (hw->mac.ops.stop_link_on_d3) 6674 hw->mac.ops.stop_link_on_d3(hw); 6675 6676 if (wufc) { 6677 u32 fctrl; 6678 6679 ixgbe_set_rx_mode(netdev); 6680 6681 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6682 if (hw->mac.ops.enable_tx_laser) 6683 hw->mac.ops.enable_tx_laser(hw); 6684 6685 /* enable the reception of multicast packets */ 6686 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6687 fctrl |= IXGBE_FCTRL_MPE; 6688 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6689 6690 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6691 ctrl |= IXGBE_CTRL_GIO_DIS; 6692 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6693 6694 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6695 } else { 6696 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6697 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6698 } 6699 6700 switch (hw->mac.type) { 6701 case ixgbe_mac_82598EB: 6702 pci_wake_from_d3(pdev, false); 6703 break; 6704 case ixgbe_mac_82599EB: 6705 case ixgbe_mac_X540: 6706 case ixgbe_mac_X550: 6707 case ixgbe_mac_X550EM_x: 6708 case ixgbe_mac_x550em_a: 6709 pci_wake_from_d3(pdev, !!wufc); 6710 break; 6711 default: 6712 break; 6713 } 6714 6715 *enable_wake = !!wufc; 6716 if (hw->phy.ops.set_phy_power && !*enable_wake) 6717 hw->phy.ops.set_phy_power(hw, false); 6718 6719 ixgbe_release_hw_control(adapter); 6720 6721 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6722 pci_disable_device(pdev); 6723 6724 return 0; 6725 } 6726 6727 #ifdef CONFIG_PM 6728 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6729 { 6730 int retval; 6731 bool wake; 6732 6733 retval = __ixgbe_shutdown(pdev, &wake); 6734 if (retval) 6735 return retval; 6736 6737 if (wake) { 6738 pci_prepare_to_sleep(pdev); 6739 } else { 6740 pci_wake_from_d3(pdev, false); 6741 pci_set_power_state(pdev, PCI_D3hot); 6742 } 6743 6744 return 0; 6745 } 6746 #endif /* CONFIG_PM */ 6747 6748 static void ixgbe_shutdown(struct pci_dev *pdev) 6749 { 6750 bool wake; 6751 6752 __ixgbe_shutdown(pdev, &wake); 6753 6754 if (system_state == SYSTEM_POWER_OFF) { 6755 pci_wake_from_d3(pdev, wake); 6756 pci_set_power_state(pdev, PCI_D3hot); 6757 } 6758 } 6759 6760 /** 6761 * ixgbe_update_stats - Update the board statistics counters. 6762 * @adapter: board private structure 6763 **/ 6764 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6765 { 6766 struct net_device *netdev = adapter->netdev; 6767 struct ixgbe_hw *hw = &adapter->hw; 6768 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6769 u64 total_mpc = 0; 6770 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6771 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6772 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6773 u64 alloc_rx_page = 0; 6774 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6775 6776 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6777 test_bit(__IXGBE_RESETTING, &adapter->state)) 6778 return; 6779 6780 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6781 u64 rsc_count = 0; 6782 u64 rsc_flush = 0; 6783 for (i = 0; i < adapter->num_rx_queues; i++) { 6784 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6785 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6786 } 6787 adapter->rsc_total_count = rsc_count; 6788 adapter->rsc_total_flush = rsc_flush; 6789 } 6790 6791 for (i = 0; i < adapter->num_rx_queues; i++) { 6792 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6793 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6794 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 6795 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6796 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6797 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6798 bytes += rx_ring->stats.bytes; 6799 packets += rx_ring->stats.packets; 6800 } 6801 adapter->non_eop_descs = non_eop_descs; 6802 adapter->alloc_rx_page = alloc_rx_page; 6803 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6804 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6805 adapter->hw_csum_rx_error = hw_csum_rx_error; 6806 netdev->stats.rx_bytes = bytes; 6807 netdev->stats.rx_packets = packets; 6808 6809 bytes = 0; 6810 packets = 0; 6811 /* gather some stats to the adapter struct that are per queue */ 6812 for (i = 0; i < adapter->num_tx_queues; i++) { 6813 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6814 restart_queue += tx_ring->tx_stats.restart_queue; 6815 tx_busy += tx_ring->tx_stats.tx_busy; 6816 bytes += tx_ring->stats.bytes; 6817 packets += tx_ring->stats.packets; 6818 } 6819 for (i = 0; i < adapter->num_xdp_queues; i++) { 6820 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6821 6822 restart_queue += xdp_ring->tx_stats.restart_queue; 6823 tx_busy += xdp_ring->tx_stats.tx_busy; 6824 bytes += xdp_ring->stats.bytes; 6825 packets += xdp_ring->stats.packets; 6826 } 6827 adapter->restart_queue = restart_queue; 6828 adapter->tx_busy = tx_busy; 6829 netdev->stats.tx_bytes = bytes; 6830 netdev->stats.tx_packets = packets; 6831 6832 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6833 6834 /* 8 register reads */ 6835 for (i = 0; i < 8; i++) { 6836 /* for packet buffers not used, the register should read 0 */ 6837 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6838 missed_rx += mpc; 6839 hwstats->mpc[i] += mpc; 6840 total_mpc += hwstats->mpc[i]; 6841 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6842 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6843 switch (hw->mac.type) { 6844 case ixgbe_mac_82598EB: 6845 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6846 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6847 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6848 hwstats->pxonrxc[i] += 6849 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6850 break; 6851 case ixgbe_mac_82599EB: 6852 case ixgbe_mac_X540: 6853 case ixgbe_mac_X550: 6854 case ixgbe_mac_X550EM_x: 6855 case ixgbe_mac_x550em_a: 6856 hwstats->pxonrxc[i] += 6857 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6858 break; 6859 default: 6860 break; 6861 } 6862 } 6863 6864 /*16 register reads */ 6865 for (i = 0; i < 16; i++) { 6866 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6867 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6868 if ((hw->mac.type == ixgbe_mac_82599EB) || 6869 (hw->mac.type == ixgbe_mac_X540) || 6870 (hw->mac.type == ixgbe_mac_X550) || 6871 (hw->mac.type == ixgbe_mac_X550EM_x) || 6872 (hw->mac.type == ixgbe_mac_x550em_a)) { 6873 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6874 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6875 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6876 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6877 } 6878 } 6879 6880 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6881 /* work around hardware counting issue */ 6882 hwstats->gprc -= missed_rx; 6883 6884 ixgbe_update_xoff_received(adapter); 6885 6886 /* 82598 hardware only has a 32 bit counter in the high register */ 6887 switch (hw->mac.type) { 6888 case ixgbe_mac_82598EB: 6889 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6890 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6891 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6892 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6893 break; 6894 case ixgbe_mac_X540: 6895 case ixgbe_mac_X550: 6896 case ixgbe_mac_X550EM_x: 6897 case ixgbe_mac_x550em_a: 6898 /* OS2BMC stats are X540 and later */ 6899 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6900 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6901 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6902 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6903 /* fall through */ 6904 case ixgbe_mac_82599EB: 6905 for (i = 0; i < 16; i++) 6906 adapter->hw_rx_no_dma_resources += 6907 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6908 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6909 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6910 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6911 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6912 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6913 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6914 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6915 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6916 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6917 #ifdef IXGBE_FCOE 6918 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6919 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6920 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6921 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6922 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6923 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6924 /* Add up per cpu counters for total ddp aloc fail */ 6925 if (adapter->fcoe.ddp_pool) { 6926 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6927 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6928 unsigned int cpu; 6929 u64 noddp = 0, noddp_ext_buff = 0; 6930 for_each_possible_cpu(cpu) { 6931 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6932 noddp += ddp_pool->noddp; 6933 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6934 } 6935 hwstats->fcoe_noddp = noddp; 6936 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6937 } 6938 #endif /* IXGBE_FCOE */ 6939 break; 6940 default: 6941 break; 6942 } 6943 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6944 hwstats->bprc += bprc; 6945 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6946 if (hw->mac.type == ixgbe_mac_82598EB) 6947 hwstats->mprc -= bprc; 6948 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6949 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6950 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6951 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6952 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6953 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6954 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6955 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6956 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6957 hwstats->lxontxc += lxon; 6958 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6959 hwstats->lxofftxc += lxoff; 6960 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6961 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6962 /* 6963 * 82598 errata - tx of flow control packets is included in tx counters 6964 */ 6965 xon_off_tot = lxon + lxoff; 6966 hwstats->gptc -= xon_off_tot; 6967 hwstats->mptc -= xon_off_tot; 6968 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6969 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6970 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6971 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6972 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6973 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6974 hwstats->ptc64 -= xon_off_tot; 6975 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6976 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6977 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6978 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6979 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6980 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6981 6982 /* Fill out the OS statistics structure */ 6983 netdev->stats.multicast = hwstats->mprc; 6984 6985 /* Rx Errors */ 6986 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6987 netdev->stats.rx_dropped = 0; 6988 netdev->stats.rx_length_errors = hwstats->rlec; 6989 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6990 netdev->stats.rx_missed_errors = total_mpc; 6991 } 6992 6993 /** 6994 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6995 * @adapter: pointer to the device adapter structure 6996 **/ 6997 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6998 { 6999 struct ixgbe_hw *hw = &adapter->hw; 7000 int i; 7001 7002 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7003 return; 7004 7005 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7006 7007 /* if interface is down do nothing */ 7008 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7009 return; 7010 7011 /* do nothing if we are not using signature filters */ 7012 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7013 return; 7014 7015 adapter->fdir_overflow++; 7016 7017 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7018 for (i = 0; i < adapter->num_tx_queues; i++) 7019 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7020 &(adapter->tx_ring[i]->state)); 7021 for (i = 0; i < adapter->num_xdp_queues; i++) 7022 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7023 &adapter->xdp_ring[i]->state); 7024 /* re-enable flow director interrupts */ 7025 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7026 } else { 7027 e_err(probe, "failed to finish FDIR re-initialization, " 7028 "ignored adding FDIR ATR filters\n"); 7029 } 7030 } 7031 7032 /** 7033 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7034 * @adapter: pointer to the device adapter structure 7035 * 7036 * This function serves two purposes. First it strobes the interrupt lines 7037 * in order to make certain interrupts are occurring. Secondly it sets the 7038 * bits needed to check for TX hangs. As a result we should immediately 7039 * determine if a hang has occurred. 7040 */ 7041 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7042 { 7043 struct ixgbe_hw *hw = &adapter->hw; 7044 u64 eics = 0; 7045 int i; 7046 7047 /* If we're down, removing or resetting, just bail */ 7048 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7049 test_bit(__IXGBE_REMOVING, &adapter->state) || 7050 test_bit(__IXGBE_RESETTING, &adapter->state)) 7051 return; 7052 7053 /* Force detection of hung controller */ 7054 if (netif_carrier_ok(adapter->netdev)) { 7055 for (i = 0; i < adapter->num_tx_queues; i++) 7056 set_check_for_tx_hang(adapter->tx_ring[i]); 7057 for (i = 0; i < adapter->num_xdp_queues; i++) 7058 set_check_for_tx_hang(adapter->xdp_ring[i]); 7059 } 7060 7061 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7062 /* 7063 * for legacy and MSI interrupts don't set any bits 7064 * that are enabled for EIAM, because this operation 7065 * would set *both* EIMS and EICS for any bit in EIAM 7066 */ 7067 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7068 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7069 } else { 7070 /* get one bit for every active tx/rx interrupt vector */ 7071 for (i = 0; i < adapter->num_q_vectors; i++) { 7072 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7073 if (qv->rx.ring || qv->tx.ring) 7074 eics |= BIT_ULL(i); 7075 } 7076 } 7077 7078 /* Cause software interrupt to ensure rings are cleaned */ 7079 ixgbe_irq_rearm_queues(adapter, eics); 7080 } 7081 7082 /** 7083 * ixgbe_watchdog_update_link - update the link status 7084 * @adapter: pointer to the device adapter structure 7085 **/ 7086 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7087 { 7088 struct ixgbe_hw *hw = &adapter->hw; 7089 u32 link_speed = adapter->link_speed; 7090 bool link_up = adapter->link_up; 7091 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7092 7093 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7094 return; 7095 7096 if (hw->mac.ops.check_link) { 7097 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7098 } else { 7099 /* always assume link is up, if no check link function */ 7100 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7101 link_up = true; 7102 } 7103 7104 if (adapter->ixgbe_ieee_pfc) 7105 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7106 7107 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7108 hw->mac.ops.fc_enable(hw); 7109 ixgbe_set_rx_drop_en(adapter); 7110 } 7111 7112 if (link_up || 7113 time_after(jiffies, (adapter->link_check_timeout + 7114 IXGBE_TRY_LINK_TIMEOUT))) { 7115 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7116 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7117 IXGBE_WRITE_FLUSH(hw); 7118 } 7119 7120 adapter->link_up = link_up; 7121 adapter->link_speed = link_speed; 7122 } 7123 7124 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7125 { 7126 #ifdef CONFIG_IXGBE_DCB 7127 struct net_device *netdev = adapter->netdev; 7128 struct dcb_app app = { 7129 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7130 .protocol = 0, 7131 }; 7132 u8 up = 0; 7133 7134 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7135 up = dcb_ieee_getapp_mask(netdev, &app); 7136 7137 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7138 #endif 7139 } 7140 7141 /** 7142 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7143 * print link up message 7144 * @adapter: pointer to the device adapter structure 7145 **/ 7146 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7147 { 7148 struct net_device *netdev = adapter->netdev; 7149 struct ixgbe_hw *hw = &adapter->hw; 7150 u32 link_speed = adapter->link_speed; 7151 const char *speed_str; 7152 bool flow_rx, flow_tx; 7153 7154 /* only continue if link was previously down */ 7155 if (netif_carrier_ok(netdev)) 7156 return; 7157 7158 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7159 7160 switch (hw->mac.type) { 7161 case ixgbe_mac_82598EB: { 7162 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7163 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7164 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7165 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7166 } 7167 break; 7168 case ixgbe_mac_X540: 7169 case ixgbe_mac_X550: 7170 case ixgbe_mac_X550EM_x: 7171 case ixgbe_mac_x550em_a: 7172 case ixgbe_mac_82599EB: { 7173 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7174 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7175 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7176 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7177 } 7178 break; 7179 default: 7180 flow_tx = false; 7181 flow_rx = false; 7182 break; 7183 } 7184 7185 adapter->last_rx_ptp_check = jiffies; 7186 7187 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7188 ixgbe_ptp_start_cyclecounter(adapter); 7189 7190 switch (link_speed) { 7191 case IXGBE_LINK_SPEED_10GB_FULL: 7192 speed_str = "10 Gbps"; 7193 break; 7194 case IXGBE_LINK_SPEED_5GB_FULL: 7195 speed_str = "5 Gbps"; 7196 break; 7197 case IXGBE_LINK_SPEED_2_5GB_FULL: 7198 speed_str = "2.5 Gbps"; 7199 break; 7200 case IXGBE_LINK_SPEED_1GB_FULL: 7201 speed_str = "1 Gbps"; 7202 break; 7203 case IXGBE_LINK_SPEED_100_FULL: 7204 speed_str = "100 Mbps"; 7205 break; 7206 case IXGBE_LINK_SPEED_10_FULL: 7207 speed_str = "10 Mbps"; 7208 break; 7209 default: 7210 speed_str = "unknown speed"; 7211 break; 7212 } 7213 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7214 ((flow_rx && flow_tx) ? "RX/TX" : 7215 (flow_rx ? "RX" : 7216 (flow_tx ? "TX" : "None")))); 7217 7218 netif_carrier_on(netdev); 7219 ixgbe_check_vf_rate_limit(adapter); 7220 7221 /* enable transmits */ 7222 netif_tx_wake_all_queues(adapter->netdev); 7223 7224 /* update the default user priority for VFs */ 7225 ixgbe_update_default_up(adapter); 7226 7227 /* ping all the active vfs to let them know link has changed */ 7228 ixgbe_ping_all_vfs(adapter); 7229 } 7230 7231 /** 7232 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7233 * print link down message 7234 * @adapter: pointer to the adapter structure 7235 **/ 7236 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7237 { 7238 struct net_device *netdev = adapter->netdev; 7239 struct ixgbe_hw *hw = &adapter->hw; 7240 7241 adapter->link_up = false; 7242 adapter->link_speed = 0; 7243 7244 /* only continue if link was up previously */ 7245 if (!netif_carrier_ok(netdev)) 7246 return; 7247 7248 /* poll for SFP+ cable when link is down */ 7249 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7250 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7251 7252 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7253 ixgbe_ptp_start_cyclecounter(adapter); 7254 7255 e_info(drv, "NIC Link is Down\n"); 7256 netif_carrier_off(netdev); 7257 7258 /* ping all the active vfs to let them know link has changed */ 7259 ixgbe_ping_all_vfs(adapter); 7260 } 7261 7262 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7263 { 7264 int i; 7265 7266 for (i = 0; i < adapter->num_tx_queues; i++) { 7267 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7268 7269 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7270 return true; 7271 } 7272 7273 for (i = 0; i < adapter->num_xdp_queues; i++) { 7274 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7275 7276 if (ring->next_to_use != ring->next_to_clean) 7277 return true; 7278 } 7279 7280 return false; 7281 } 7282 7283 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7284 { 7285 struct ixgbe_hw *hw = &adapter->hw; 7286 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7287 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7288 7289 int i, j; 7290 7291 if (!adapter->num_vfs) 7292 return false; 7293 7294 /* resetting the PF is only needed for MAC before X550 */ 7295 if (hw->mac.type >= ixgbe_mac_X550) 7296 return false; 7297 7298 for (i = 0; i < adapter->num_vfs; i++) { 7299 for (j = 0; j < q_per_pool; j++) { 7300 u32 h, t; 7301 7302 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7303 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7304 7305 if (h != t) 7306 return true; 7307 } 7308 } 7309 7310 return false; 7311 } 7312 7313 /** 7314 * ixgbe_watchdog_flush_tx - flush queues on link down 7315 * @adapter: pointer to the device adapter structure 7316 **/ 7317 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7318 { 7319 if (!netif_carrier_ok(adapter->netdev)) { 7320 if (ixgbe_ring_tx_pending(adapter) || 7321 ixgbe_vf_tx_pending(adapter)) { 7322 /* We've lost link, so the controller stops DMA, 7323 * but we've got queued Tx work that's never going 7324 * to get done, so reset controller to flush Tx. 7325 * (Do the reset outside of interrupt context). 7326 */ 7327 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7328 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7329 } 7330 } 7331 } 7332 7333 #ifdef CONFIG_PCI_IOV 7334 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7335 { 7336 struct ixgbe_hw *hw = &adapter->hw; 7337 struct pci_dev *pdev = adapter->pdev; 7338 unsigned int vf; 7339 u32 gpc; 7340 7341 if (!(netif_carrier_ok(adapter->netdev))) 7342 return; 7343 7344 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7345 if (gpc) /* If incrementing then no need for the check below */ 7346 return; 7347 /* Check to see if a bad DMA write target from an errant or 7348 * malicious VF has caused a PCIe error. If so then we can 7349 * issue a VFLR to the offending VF(s) and then resume without 7350 * requesting a full slot reset. 7351 */ 7352 7353 if (!pdev) 7354 return; 7355 7356 /* check status reg for all VFs owned by this PF */ 7357 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7358 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7359 u16 status_reg; 7360 7361 if (!vfdev) 7362 continue; 7363 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7364 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7365 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7366 pcie_flr(vfdev); 7367 } 7368 } 7369 7370 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7371 { 7372 u32 ssvpc; 7373 7374 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7375 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7376 adapter->num_vfs == 0) 7377 return; 7378 7379 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7380 7381 /* 7382 * ssvpc register is cleared on read, if zero then no 7383 * spoofed packets in the last interval. 7384 */ 7385 if (!ssvpc) 7386 return; 7387 7388 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7389 } 7390 #else 7391 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7392 { 7393 } 7394 7395 static void 7396 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7397 { 7398 } 7399 #endif /* CONFIG_PCI_IOV */ 7400 7401 7402 /** 7403 * ixgbe_watchdog_subtask - check and bring link up 7404 * @adapter: pointer to the device adapter structure 7405 **/ 7406 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7407 { 7408 /* if interface is down, removing or resetting, do nothing */ 7409 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7410 test_bit(__IXGBE_REMOVING, &adapter->state) || 7411 test_bit(__IXGBE_RESETTING, &adapter->state)) 7412 return; 7413 7414 ixgbe_watchdog_update_link(adapter); 7415 7416 if (adapter->link_up) 7417 ixgbe_watchdog_link_is_up(adapter); 7418 else 7419 ixgbe_watchdog_link_is_down(adapter); 7420 7421 ixgbe_check_for_bad_vf(adapter); 7422 ixgbe_spoof_check(adapter); 7423 ixgbe_update_stats(adapter); 7424 7425 ixgbe_watchdog_flush_tx(adapter); 7426 } 7427 7428 /** 7429 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7430 * @adapter: the ixgbe adapter structure 7431 **/ 7432 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7433 { 7434 struct ixgbe_hw *hw = &adapter->hw; 7435 s32 err; 7436 7437 /* not searching for SFP so there is nothing to do here */ 7438 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7439 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7440 return; 7441 7442 if (adapter->sfp_poll_time && 7443 time_after(adapter->sfp_poll_time, jiffies)) 7444 return; /* If not yet time to poll for SFP */ 7445 7446 /* someone else is in init, wait until next service event */ 7447 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7448 return; 7449 7450 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7451 7452 err = hw->phy.ops.identify_sfp(hw); 7453 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7454 goto sfp_out; 7455 7456 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7457 /* If no cable is present, then we need to reset 7458 * the next time we find a good cable. */ 7459 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7460 } 7461 7462 /* exit on error */ 7463 if (err) 7464 goto sfp_out; 7465 7466 /* exit if reset not needed */ 7467 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7468 goto sfp_out; 7469 7470 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7471 7472 /* 7473 * A module may be identified correctly, but the EEPROM may not have 7474 * support for that module. setup_sfp() will fail in that case, so 7475 * we should not allow that module to load. 7476 */ 7477 if (hw->mac.type == ixgbe_mac_82598EB) 7478 err = hw->phy.ops.reset(hw); 7479 else 7480 err = hw->mac.ops.setup_sfp(hw); 7481 7482 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7483 goto sfp_out; 7484 7485 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7486 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7487 7488 sfp_out: 7489 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7490 7491 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7492 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7493 e_dev_err("failed to initialize because an unsupported " 7494 "SFP+ module type was detected.\n"); 7495 e_dev_err("Reload the driver after installing a " 7496 "supported module.\n"); 7497 unregister_netdev(adapter->netdev); 7498 } 7499 } 7500 7501 /** 7502 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7503 * @adapter: the ixgbe adapter structure 7504 **/ 7505 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7506 { 7507 struct ixgbe_hw *hw = &adapter->hw; 7508 u32 cap_speed; 7509 u32 speed; 7510 bool autoneg = false; 7511 7512 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7513 return; 7514 7515 /* someone else is in init, wait until next service event */ 7516 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7517 return; 7518 7519 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7520 7521 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7522 7523 /* advertise highest capable link speed */ 7524 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7525 speed = IXGBE_LINK_SPEED_10GB_FULL; 7526 else 7527 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7528 IXGBE_LINK_SPEED_1GB_FULL); 7529 7530 if (hw->mac.ops.setup_link) 7531 hw->mac.ops.setup_link(hw, speed, true); 7532 7533 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7534 adapter->link_check_timeout = jiffies; 7535 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7536 } 7537 7538 /** 7539 * ixgbe_service_timer - Timer Call-back 7540 * @t: pointer to timer_list structure 7541 **/ 7542 static void ixgbe_service_timer(struct timer_list *t) 7543 { 7544 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7545 unsigned long next_event_offset; 7546 7547 /* poll faster when waiting for link */ 7548 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7549 next_event_offset = HZ / 10; 7550 else 7551 next_event_offset = HZ * 2; 7552 7553 /* Reset the timer */ 7554 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7555 7556 ixgbe_service_event_schedule(adapter); 7557 } 7558 7559 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7560 { 7561 struct ixgbe_hw *hw = &adapter->hw; 7562 u32 status; 7563 7564 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7565 return; 7566 7567 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7568 7569 if (!hw->phy.ops.handle_lasi) 7570 return; 7571 7572 status = hw->phy.ops.handle_lasi(&adapter->hw); 7573 if (status != IXGBE_ERR_OVERTEMP) 7574 return; 7575 7576 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7577 } 7578 7579 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7580 { 7581 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7582 return; 7583 7584 rtnl_lock(); 7585 /* If we're already down, removing or resetting, just bail */ 7586 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7587 test_bit(__IXGBE_REMOVING, &adapter->state) || 7588 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7589 rtnl_unlock(); 7590 return; 7591 } 7592 7593 ixgbe_dump(adapter); 7594 netdev_err(adapter->netdev, "Reset adapter\n"); 7595 adapter->tx_timeout_count++; 7596 7597 ixgbe_reinit_locked(adapter); 7598 rtnl_unlock(); 7599 } 7600 7601 /** 7602 * ixgbe_service_task - manages and runs subtasks 7603 * @work: pointer to work_struct containing our data 7604 **/ 7605 static void ixgbe_service_task(struct work_struct *work) 7606 { 7607 struct ixgbe_adapter *adapter = container_of(work, 7608 struct ixgbe_adapter, 7609 service_task); 7610 if (ixgbe_removed(adapter->hw.hw_addr)) { 7611 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7612 rtnl_lock(); 7613 ixgbe_down(adapter); 7614 rtnl_unlock(); 7615 } 7616 ixgbe_service_event_complete(adapter); 7617 return; 7618 } 7619 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7620 rtnl_lock(); 7621 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7622 udp_tunnel_get_rx_info(adapter->netdev); 7623 rtnl_unlock(); 7624 } 7625 ixgbe_reset_subtask(adapter); 7626 ixgbe_phy_interrupt_subtask(adapter); 7627 ixgbe_sfp_detection_subtask(adapter); 7628 ixgbe_sfp_link_config_subtask(adapter); 7629 ixgbe_check_overtemp_subtask(adapter); 7630 ixgbe_watchdog_subtask(adapter); 7631 ixgbe_fdir_reinit_subtask(adapter); 7632 ixgbe_check_hang_subtask(adapter); 7633 7634 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7635 ixgbe_ptp_overflow_check(adapter); 7636 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7637 ixgbe_ptp_rx_hang(adapter); 7638 ixgbe_ptp_tx_hang(adapter); 7639 } 7640 7641 ixgbe_service_event_complete(adapter); 7642 } 7643 7644 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7645 struct ixgbe_tx_buffer *first, 7646 u8 *hdr_len, 7647 struct ixgbe_ipsec_tx_data *itd) 7648 { 7649 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7650 struct sk_buff *skb = first->skb; 7651 union { 7652 struct iphdr *v4; 7653 struct ipv6hdr *v6; 7654 unsigned char *hdr; 7655 } ip; 7656 union { 7657 struct tcphdr *tcp; 7658 unsigned char *hdr; 7659 } l4; 7660 u32 paylen, l4_offset; 7661 u32 fceof_saidx = 0; 7662 int err; 7663 7664 if (skb->ip_summed != CHECKSUM_PARTIAL) 7665 return 0; 7666 7667 if (!skb_is_gso(skb)) 7668 return 0; 7669 7670 err = skb_cow_head(skb, 0); 7671 if (err < 0) 7672 return err; 7673 7674 if (eth_p_mpls(first->protocol)) 7675 ip.hdr = skb_inner_network_header(skb); 7676 else 7677 ip.hdr = skb_network_header(skb); 7678 l4.hdr = skb_checksum_start(skb); 7679 7680 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7681 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7682 7683 /* initialize outer IP header fields */ 7684 if (ip.v4->version == 4) { 7685 unsigned char *csum_start = skb_checksum_start(skb); 7686 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7687 int len = csum_start - trans_start; 7688 7689 /* IP header will have to cancel out any data that 7690 * is not a part of the outer IP header, so set to 7691 * a reverse csum if needed, else init check to 0. 7692 */ 7693 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7694 csum_fold(csum_partial(trans_start, 7695 len, 0)) : 0; 7696 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7697 7698 ip.v4->tot_len = 0; 7699 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7700 IXGBE_TX_FLAGS_CSUM | 7701 IXGBE_TX_FLAGS_IPV4; 7702 } else { 7703 ip.v6->payload_len = 0; 7704 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7705 IXGBE_TX_FLAGS_CSUM; 7706 } 7707 7708 /* determine offset of inner transport header */ 7709 l4_offset = l4.hdr - skb->data; 7710 7711 /* compute length of segmentation header */ 7712 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7713 7714 /* remove payload length from inner checksum */ 7715 paylen = skb->len - l4_offset; 7716 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 7717 7718 /* update gso size and bytecount with header size */ 7719 first->gso_segs = skb_shinfo(skb)->gso_segs; 7720 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7721 7722 /* mss_l4len_id: use 0 as index for TSO */ 7723 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7724 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7725 7726 fceof_saidx |= itd->sa_idx; 7727 type_tucmd |= itd->flags | itd->trailer_len; 7728 7729 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7730 vlan_macip_lens = l4.hdr - ip.hdr; 7731 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7732 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7733 7734 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 7735 mss_l4len_idx); 7736 7737 return 1; 7738 } 7739 7740 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7741 { 7742 unsigned int offset = 0; 7743 7744 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7745 7746 return offset == skb_checksum_start_offset(skb); 7747 } 7748 7749 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7750 struct ixgbe_tx_buffer *first, 7751 struct ixgbe_ipsec_tx_data *itd) 7752 { 7753 struct sk_buff *skb = first->skb; 7754 u32 vlan_macip_lens = 0; 7755 u32 fceof_saidx = 0; 7756 u32 type_tucmd = 0; 7757 7758 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7759 csum_failed: 7760 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7761 IXGBE_TX_FLAGS_CC))) 7762 return; 7763 goto no_csum; 7764 } 7765 7766 switch (skb->csum_offset) { 7767 case offsetof(struct tcphdr, check): 7768 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7769 /* fall through */ 7770 case offsetof(struct udphdr, check): 7771 break; 7772 case offsetof(struct sctphdr, checksum): 7773 /* validate that this is actually an SCTP request */ 7774 if (((first->protocol == htons(ETH_P_IP)) && 7775 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7776 ((first->protocol == htons(ETH_P_IPV6)) && 7777 ixgbe_ipv6_csum_is_sctp(skb))) { 7778 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7779 break; 7780 } 7781 /* fall through */ 7782 default: 7783 skb_checksum_help(skb); 7784 goto csum_failed; 7785 } 7786 7787 /* update TX checksum flag */ 7788 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7789 vlan_macip_lens = skb_checksum_start_offset(skb) - 7790 skb_network_offset(skb); 7791 no_csum: 7792 /* vlan_macip_lens: MACLEN, VLAN tag */ 7793 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7794 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7795 7796 fceof_saidx |= itd->sa_idx; 7797 type_tucmd |= itd->flags | itd->trailer_len; 7798 7799 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 7800 } 7801 7802 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7803 ((_flag <= _result) ? \ 7804 ((u32)(_input & _flag) * (_result / _flag)) : \ 7805 ((u32)(_input & _flag) / (_flag / _result))) 7806 7807 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7808 { 7809 /* set type for advanced descriptor with frame checksum insertion */ 7810 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7811 IXGBE_ADVTXD_DCMD_DEXT | 7812 IXGBE_ADVTXD_DCMD_IFCS; 7813 7814 /* set HW vlan bit if vlan is present */ 7815 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7816 IXGBE_ADVTXD_DCMD_VLE); 7817 7818 /* set segmentation enable bits for TSO/FSO */ 7819 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7820 IXGBE_ADVTXD_DCMD_TSE); 7821 7822 /* set timestamp bit if present */ 7823 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7824 IXGBE_ADVTXD_MAC_TSTAMP); 7825 7826 /* insert frame checksum */ 7827 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7828 7829 return cmd_type; 7830 } 7831 7832 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7833 u32 tx_flags, unsigned int paylen) 7834 { 7835 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7836 7837 /* enable L4 checksum for TSO and TX checksum offload */ 7838 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7839 IXGBE_TX_FLAGS_CSUM, 7840 IXGBE_ADVTXD_POPTS_TXSM); 7841 7842 /* enable IPv4 checksum for TSO */ 7843 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7844 IXGBE_TX_FLAGS_IPV4, 7845 IXGBE_ADVTXD_POPTS_IXSM); 7846 7847 /* enable IPsec */ 7848 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7849 IXGBE_TX_FLAGS_IPSEC, 7850 IXGBE_ADVTXD_POPTS_IPSEC); 7851 7852 /* 7853 * Check Context must be set if Tx switch is enabled, which it 7854 * always is for case where virtual functions are running 7855 */ 7856 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7857 IXGBE_TX_FLAGS_CC, 7858 IXGBE_ADVTXD_CC); 7859 7860 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7861 } 7862 7863 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7864 { 7865 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7866 7867 /* Herbert's original patch had: 7868 * smp_mb__after_netif_stop_queue(); 7869 * but since that doesn't exist yet, just open code it. 7870 */ 7871 smp_mb(); 7872 7873 /* We need to check again in a case another CPU has just 7874 * made room available. 7875 */ 7876 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7877 return -EBUSY; 7878 7879 /* A reprieve! - use start_queue because it doesn't call schedule */ 7880 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7881 ++tx_ring->tx_stats.restart_queue; 7882 return 0; 7883 } 7884 7885 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7886 { 7887 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7888 return 0; 7889 7890 return __ixgbe_maybe_stop_tx(tx_ring, size); 7891 } 7892 7893 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7894 IXGBE_TXD_CMD_RS) 7895 7896 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7897 struct ixgbe_tx_buffer *first, 7898 const u8 hdr_len) 7899 { 7900 struct sk_buff *skb = first->skb; 7901 struct ixgbe_tx_buffer *tx_buffer; 7902 union ixgbe_adv_tx_desc *tx_desc; 7903 struct skb_frag_struct *frag; 7904 dma_addr_t dma; 7905 unsigned int data_len, size; 7906 u32 tx_flags = first->tx_flags; 7907 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7908 u16 i = tx_ring->next_to_use; 7909 7910 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7911 7912 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7913 7914 size = skb_headlen(skb); 7915 data_len = skb->data_len; 7916 7917 #ifdef IXGBE_FCOE 7918 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7919 if (data_len < sizeof(struct fcoe_crc_eof)) { 7920 size -= sizeof(struct fcoe_crc_eof) - data_len; 7921 data_len = 0; 7922 } else { 7923 data_len -= sizeof(struct fcoe_crc_eof); 7924 } 7925 } 7926 7927 #endif 7928 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7929 7930 tx_buffer = first; 7931 7932 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7933 if (dma_mapping_error(tx_ring->dev, dma)) 7934 goto dma_error; 7935 7936 /* record length, and DMA address */ 7937 dma_unmap_len_set(tx_buffer, len, size); 7938 dma_unmap_addr_set(tx_buffer, dma, dma); 7939 7940 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7941 7942 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7943 tx_desc->read.cmd_type_len = 7944 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7945 7946 i++; 7947 tx_desc++; 7948 if (i == tx_ring->count) { 7949 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7950 i = 0; 7951 } 7952 tx_desc->read.olinfo_status = 0; 7953 7954 dma += IXGBE_MAX_DATA_PER_TXD; 7955 size -= IXGBE_MAX_DATA_PER_TXD; 7956 7957 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7958 } 7959 7960 if (likely(!data_len)) 7961 break; 7962 7963 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7964 7965 i++; 7966 tx_desc++; 7967 if (i == tx_ring->count) { 7968 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7969 i = 0; 7970 } 7971 tx_desc->read.olinfo_status = 0; 7972 7973 #ifdef IXGBE_FCOE 7974 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7975 #else 7976 size = skb_frag_size(frag); 7977 #endif 7978 data_len -= size; 7979 7980 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7981 DMA_TO_DEVICE); 7982 7983 tx_buffer = &tx_ring->tx_buffer_info[i]; 7984 } 7985 7986 /* write last descriptor with RS and EOP bits */ 7987 cmd_type |= size | IXGBE_TXD_CMD; 7988 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7989 7990 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7991 7992 /* set the timestamp */ 7993 first->time_stamp = jiffies; 7994 7995 /* 7996 * Force memory writes to complete before letting h/w know there 7997 * are new descriptors to fetch. (Only applicable for weak-ordered 7998 * memory model archs, such as IA-64). 7999 * 8000 * We also need this memory barrier to make certain all of the 8001 * status bits have been updated before next_to_watch is written. 8002 */ 8003 wmb(); 8004 8005 /* set next_to_watch value indicating a packet is present */ 8006 first->next_to_watch = tx_desc; 8007 8008 i++; 8009 if (i == tx_ring->count) 8010 i = 0; 8011 8012 tx_ring->next_to_use = i; 8013 8014 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8015 8016 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8017 writel(i, tx_ring->tail); 8018 8019 /* we need this if more than one processor can write to our tail 8020 * at a time, it synchronizes IO on IA64/Altix systems 8021 */ 8022 mmiowb(); 8023 } 8024 8025 return 0; 8026 dma_error: 8027 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8028 8029 /* clear dma mappings for failed tx_buffer_info map */ 8030 for (;;) { 8031 tx_buffer = &tx_ring->tx_buffer_info[i]; 8032 if (dma_unmap_len(tx_buffer, len)) 8033 dma_unmap_page(tx_ring->dev, 8034 dma_unmap_addr(tx_buffer, dma), 8035 dma_unmap_len(tx_buffer, len), 8036 DMA_TO_DEVICE); 8037 dma_unmap_len_set(tx_buffer, len, 0); 8038 if (tx_buffer == first) 8039 break; 8040 if (i == 0) 8041 i += tx_ring->count; 8042 i--; 8043 } 8044 8045 dev_kfree_skb_any(first->skb); 8046 first->skb = NULL; 8047 8048 tx_ring->next_to_use = i; 8049 8050 return -1; 8051 } 8052 8053 static void ixgbe_atr(struct ixgbe_ring *ring, 8054 struct ixgbe_tx_buffer *first) 8055 { 8056 struct ixgbe_q_vector *q_vector = ring->q_vector; 8057 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8058 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8059 union { 8060 unsigned char *network; 8061 struct iphdr *ipv4; 8062 struct ipv6hdr *ipv6; 8063 } hdr; 8064 struct tcphdr *th; 8065 unsigned int hlen; 8066 struct sk_buff *skb; 8067 __be16 vlan_id; 8068 int l4_proto; 8069 8070 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8071 if (!q_vector) 8072 return; 8073 8074 /* do nothing if sampling is disabled */ 8075 if (!ring->atr_sample_rate) 8076 return; 8077 8078 ring->atr_count++; 8079 8080 /* currently only IPv4/IPv6 with TCP is supported */ 8081 if ((first->protocol != htons(ETH_P_IP)) && 8082 (first->protocol != htons(ETH_P_IPV6))) 8083 return; 8084 8085 /* snag network header to get L4 type and address */ 8086 skb = first->skb; 8087 hdr.network = skb_network_header(skb); 8088 if (unlikely(hdr.network <= skb->data)) 8089 return; 8090 if (skb->encapsulation && 8091 first->protocol == htons(ETH_P_IP) && 8092 hdr.ipv4->protocol == IPPROTO_UDP) { 8093 struct ixgbe_adapter *adapter = q_vector->adapter; 8094 8095 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8096 VXLAN_HEADROOM)) 8097 return; 8098 8099 /* verify the port is recognized as VXLAN */ 8100 if (adapter->vxlan_port && 8101 udp_hdr(skb)->dest == adapter->vxlan_port) 8102 hdr.network = skb_inner_network_header(skb); 8103 8104 if (adapter->geneve_port && 8105 udp_hdr(skb)->dest == adapter->geneve_port) 8106 hdr.network = skb_inner_network_header(skb); 8107 } 8108 8109 /* Make sure we have at least [minimum IPv4 header + TCP] 8110 * or [IPv6 header] bytes 8111 */ 8112 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8113 return; 8114 8115 /* Currently only IPv4/IPv6 with TCP is supported */ 8116 switch (hdr.ipv4->version) { 8117 case IPVERSION: 8118 /* access ihl as u8 to avoid unaligned access on ia64 */ 8119 hlen = (hdr.network[0] & 0x0F) << 2; 8120 l4_proto = hdr.ipv4->protocol; 8121 break; 8122 case 6: 8123 hlen = hdr.network - skb->data; 8124 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8125 hlen -= hdr.network - skb->data; 8126 break; 8127 default: 8128 return; 8129 } 8130 8131 if (l4_proto != IPPROTO_TCP) 8132 return; 8133 8134 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8135 hlen + sizeof(struct tcphdr))) 8136 return; 8137 8138 th = (struct tcphdr *)(hdr.network + hlen); 8139 8140 /* skip this packet since the socket is closing */ 8141 if (th->fin) 8142 return; 8143 8144 /* sample on all syn packets or once every atr sample count */ 8145 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8146 return; 8147 8148 /* reset sample count */ 8149 ring->atr_count = 0; 8150 8151 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8152 8153 /* 8154 * src and dst are inverted, think how the receiver sees them 8155 * 8156 * The input is broken into two sections, a non-compressed section 8157 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8158 * is XORed together and stored in the compressed dword. 8159 */ 8160 input.formatted.vlan_id = vlan_id; 8161 8162 /* 8163 * since src port and flex bytes occupy the same word XOR them together 8164 * and write the value to source port portion of compressed dword 8165 */ 8166 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8167 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8168 else 8169 common.port.src ^= th->dest ^ first->protocol; 8170 common.port.dst ^= th->source; 8171 8172 switch (hdr.ipv4->version) { 8173 case IPVERSION: 8174 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8175 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8176 break; 8177 case 6: 8178 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8179 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8180 hdr.ipv6->saddr.s6_addr32[1] ^ 8181 hdr.ipv6->saddr.s6_addr32[2] ^ 8182 hdr.ipv6->saddr.s6_addr32[3] ^ 8183 hdr.ipv6->daddr.s6_addr32[0] ^ 8184 hdr.ipv6->daddr.s6_addr32[1] ^ 8185 hdr.ipv6->daddr.s6_addr32[2] ^ 8186 hdr.ipv6->daddr.s6_addr32[3]; 8187 break; 8188 default: 8189 break; 8190 } 8191 8192 if (hdr.network != skb_network_header(skb)) 8193 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8194 8195 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8196 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8197 input, common, ring->queue_index); 8198 } 8199 8200 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8201 void *accel_priv, select_queue_fallback_t fallback) 8202 { 8203 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8204 struct ixgbe_adapter *adapter; 8205 int txq; 8206 #ifdef IXGBE_FCOE 8207 struct ixgbe_ring_feature *f; 8208 #endif 8209 8210 if (fwd_adapter) { 8211 adapter = netdev_priv(dev); 8212 txq = reciprocal_scale(skb_get_hash(skb), 8213 adapter->num_rx_queues_per_pool); 8214 8215 return txq + fwd_adapter->tx_base_queue; 8216 } 8217 8218 #ifdef IXGBE_FCOE 8219 8220 /* 8221 * only execute the code below if protocol is FCoE 8222 * or FIP and we have FCoE enabled on the adapter 8223 */ 8224 switch (vlan_get_protocol(skb)) { 8225 case htons(ETH_P_FCOE): 8226 case htons(ETH_P_FIP): 8227 adapter = netdev_priv(dev); 8228 8229 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8230 break; 8231 /* fall through */ 8232 default: 8233 return fallback(dev, skb); 8234 } 8235 8236 f = &adapter->ring_feature[RING_F_FCOE]; 8237 8238 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8239 smp_processor_id(); 8240 8241 while (txq >= f->indices) 8242 txq -= f->indices; 8243 8244 return txq + f->offset; 8245 #else 8246 return fallback(dev, skb); 8247 #endif 8248 } 8249 8250 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8251 struct xdp_frame *xdpf) 8252 { 8253 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8254 struct ixgbe_tx_buffer *tx_buffer; 8255 union ixgbe_adv_tx_desc *tx_desc; 8256 u32 len, cmd_type; 8257 dma_addr_t dma; 8258 u16 i; 8259 8260 len = xdpf->len; 8261 8262 if (unlikely(!ixgbe_desc_unused(ring))) 8263 return IXGBE_XDP_CONSUMED; 8264 8265 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8266 if (dma_mapping_error(ring->dev, dma)) 8267 return IXGBE_XDP_CONSUMED; 8268 8269 /* record the location of the first descriptor for this packet */ 8270 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8271 tx_buffer->bytecount = len; 8272 tx_buffer->gso_segs = 1; 8273 tx_buffer->protocol = 0; 8274 8275 i = ring->next_to_use; 8276 tx_desc = IXGBE_TX_DESC(ring, i); 8277 8278 dma_unmap_len_set(tx_buffer, len, len); 8279 dma_unmap_addr_set(tx_buffer, dma, dma); 8280 tx_buffer->xdpf = xdpf; 8281 8282 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8283 8284 /* put descriptor type bits */ 8285 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8286 IXGBE_ADVTXD_DCMD_DEXT | 8287 IXGBE_ADVTXD_DCMD_IFCS; 8288 cmd_type |= len | IXGBE_TXD_CMD; 8289 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8290 tx_desc->read.olinfo_status = 8291 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8292 8293 /* Avoid any potential race with xdp_xmit and cleanup */ 8294 smp_wmb(); 8295 8296 /* set next_to_watch value indicating a packet is present */ 8297 i++; 8298 if (i == ring->count) 8299 i = 0; 8300 8301 tx_buffer->next_to_watch = tx_desc; 8302 ring->next_to_use = i; 8303 8304 return IXGBE_XDP_TX; 8305 } 8306 8307 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8308 struct ixgbe_adapter *adapter, 8309 struct ixgbe_ring *tx_ring) 8310 { 8311 struct ixgbe_tx_buffer *first; 8312 int tso; 8313 u32 tx_flags = 0; 8314 unsigned short f; 8315 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8316 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8317 __be16 protocol = skb->protocol; 8318 u8 hdr_len = 0; 8319 8320 /* 8321 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8322 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8323 * + 2 desc gap to keep tail from touching head, 8324 * + 1 desc for context descriptor, 8325 * otherwise try next time 8326 */ 8327 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8328 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8329 8330 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8331 tx_ring->tx_stats.tx_busy++; 8332 return NETDEV_TX_BUSY; 8333 } 8334 8335 /* record the location of the first descriptor for this packet */ 8336 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8337 first->skb = skb; 8338 first->bytecount = skb->len; 8339 first->gso_segs = 1; 8340 8341 /* if we have a HW VLAN tag being added default to the HW one */ 8342 if (skb_vlan_tag_present(skb)) { 8343 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8344 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8345 /* else if it is a SW VLAN check the next protocol and store the tag */ 8346 } else if (protocol == htons(ETH_P_8021Q)) { 8347 struct vlan_hdr *vhdr, _vhdr; 8348 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8349 if (!vhdr) 8350 goto out_drop; 8351 8352 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8353 IXGBE_TX_FLAGS_VLAN_SHIFT; 8354 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8355 } 8356 protocol = vlan_get_protocol(skb); 8357 8358 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8359 adapter->ptp_clock) { 8360 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8361 &adapter->state)) { 8362 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8363 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8364 8365 /* schedule check for Tx timestamp */ 8366 adapter->ptp_tx_skb = skb_get(skb); 8367 adapter->ptp_tx_start = jiffies; 8368 schedule_work(&adapter->ptp_tx_work); 8369 } else { 8370 adapter->tx_hwtstamp_skipped++; 8371 } 8372 } 8373 8374 skb_tx_timestamp(skb); 8375 8376 #ifdef CONFIG_PCI_IOV 8377 /* 8378 * Use the l2switch_enable flag - would be false if the DMA 8379 * Tx switch had been disabled. 8380 */ 8381 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8382 tx_flags |= IXGBE_TX_FLAGS_CC; 8383 8384 #endif 8385 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8386 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8387 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8388 (skb->priority != TC_PRIO_CONTROL))) { 8389 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8390 tx_flags |= (skb->priority & 0x7) << 8391 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8392 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8393 struct vlan_ethhdr *vhdr; 8394 8395 if (skb_cow_head(skb, 0)) 8396 goto out_drop; 8397 vhdr = (struct vlan_ethhdr *)skb->data; 8398 vhdr->h_vlan_TCI = htons(tx_flags >> 8399 IXGBE_TX_FLAGS_VLAN_SHIFT); 8400 } else { 8401 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8402 } 8403 } 8404 8405 /* record initial flags and protocol */ 8406 first->tx_flags = tx_flags; 8407 first->protocol = protocol; 8408 8409 #ifdef IXGBE_FCOE 8410 /* setup tx offload for FCoE */ 8411 if ((protocol == htons(ETH_P_FCOE)) && 8412 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8413 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8414 if (tso < 0) 8415 goto out_drop; 8416 8417 goto xmit_fcoe; 8418 } 8419 8420 #endif /* IXGBE_FCOE */ 8421 8422 #ifdef CONFIG_XFRM_OFFLOAD 8423 if (skb->sp && !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8424 goto out_drop; 8425 #endif 8426 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8427 if (tso < 0) 8428 goto out_drop; 8429 else if (!tso) 8430 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8431 8432 /* add the ATR filter if ATR is on */ 8433 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8434 ixgbe_atr(tx_ring, first); 8435 8436 #ifdef IXGBE_FCOE 8437 xmit_fcoe: 8438 #endif /* IXGBE_FCOE */ 8439 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8440 goto cleanup_tx_timestamp; 8441 8442 return NETDEV_TX_OK; 8443 8444 out_drop: 8445 dev_kfree_skb_any(first->skb); 8446 first->skb = NULL; 8447 cleanup_tx_timestamp: 8448 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8449 dev_kfree_skb_any(adapter->ptp_tx_skb); 8450 adapter->ptp_tx_skb = NULL; 8451 cancel_work_sync(&adapter->ptp_tx_work); 8452 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8453 } 8454 8455 return NETDEV_TX_OK; 8456 } 8457 8458 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8459 struct net_device *netdev, 8460 struct ixgbe_ring *ring) 8461 { 8462 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8463 struct ixgbe_ring *tx_ring; 8464 8465 /* 8466 * The minimum packet size for olinfo paylen is 17 so pad the skb 8467 * in order to meet this minimum size requirement. 8468 */ 8469 if (skb_put_padto(skb, 17)) 8470 return NETDEV_TX_OK; 8471 8472 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8473 8474 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8475 } 8476 8477 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8478 struct net_device *netdev) 8479 { 8480 return __ixgbe_xmit_frame(skb, netdev, NULL); 8481 } 8482 8483 /** 8484 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8485 * @netdev: network interface device structure 8486 * @p: pointer to an address structure 8487 * 8488 * Returns 0 on success, negative on failure 8489 **/ 8490 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8491 { 8492 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8493 struct ixgbe_hw *hw = &adapter->hw; 8494 struct sockaddr *addr = p; 8495 8496 if (!is_valid_ether_addr(addr->sa_data)) 8497 return -EADDRNOTAVAIL; 8498 8499 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8500 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8501 8502 ixgbe_mac_set_default_filter(adapter); 8503 8504 return 0; 8505 } 8506 8507 static int 8508 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8509 { 8510 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8511 struct ixgbe_hw *hw = &adapter->hw; 8512 u16 value; 8513 int rc; 8514 8515 if (prtad != hw->phy.mdio.prtad) 8516 return -EINVAL; 8517 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8518 if (!rc) 8519 rc = value; 8520 return rc; 8521 } 8522 8523 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8524 u16 addr, u16 value) 8525 { 8526 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8527 struct ixgbe_hw *hw = &adapter->hw; 8528 8529 if (prtad != hw->phy.mdio.prtad) 8530 return -EINVAL; 8531 return hw->phy.ops.write_reg(hw, addr, devad, value); 8532 } 8533 8534 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8535 { 8536 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8537 8538 switch (cmd) { 8539 case SIOCSHWTSTAMP: 8540 return ixgbe_ptp_set_ts_config(adapter, req); 8541 case SIOCGHWTSTAMP: 8542 return ixgbe_ptp_get_ts_config(adapter, req); 8543 case SIOCGMIIPHY: 8544 if (!adapter->hw.phy.ops.read_reg) 8545 return -EOPNOTSUPP; 8546 /* fall through */ 8547 default: 8548 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8549 } 8550 } 8551 8552 /** 8553 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8554 * netdev->dev_addrs 8555 * @dev: network interface device structure 8556 * 8557 * Returns non-zero on failure 8558 **/ 8559 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8560 { 8561 int err = 0; 8562 struct ixgbe_adapter *adapter = netdev_priv(dev); 8563 struct ixgbe_hw *hw = &adapter->hw; 8564 8565 if (is_valid_ether_addr(hw->mac.san_addr)) { 8566 rtnl_lock(); 8567 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8568 rtnl_unlock(); 8569 8570 /* update SAN MAC vmdq pool selection */ 8571 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8572 } 8573 return err; 8574 } 8575 8576 /** 8577 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8578 * netdev->dev_addrs 8579 * @dev: network interface device structure 8580 * 8581 * Returns non-zero on failure 8582 **/ 8583 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8584 { 8585 int err = 0; 8586 struct ixgbe_adapter *adapter = netdev_priv(dev); 8587 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8588 8589 if (is_valid_ether_addr(mac->san_addr)) { 8590 rtnl_lock(); 8591 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8592 rtnl_unlock(); 8593 } 8594 return err; 8595 } 8596 8597 #ifdef CONFIG_NET_POLL_CONTROLLER 8598 /* 8599 * Polling 'interrupt' - used by things like netconsole to send skbs 8600 * without having to re-enable interrupts. It's not called while 8601 * the interrupt routine is executing. 8602 */ 8603 static void ixgbe_netpoll(struct net_device *netdev) 8604 { 8605 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8606 int i; 8607 8608 /* if interface is down do nothing */ 8609 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8610 return; 8611 8612 /* loop through and schedule all active queues */ 8613 for (i = 0; i < adapter->num_q_vectors; i++) 8614 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8615 } 8616 8617 #endif 8618 8619 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8620 struct ixgbe_ring *ring) 8621 { 8622 u64 bytes, packets; 8623 unsigned int start; 8624 8625 if (ring) { 8626 do { 8627 start = u64_stats_fetch_begin_irq(&ring->syncp); 8628 packets = ring->stats.packets; 8629 bytes = ring->stats.bytes; 8630 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8631 stats->tx_packets += packets; 8632 stats->tx_bytes += bytes; 8633 } 8634 } 8635 8636 static void ixgbe_get_stats64(struct net_device *netdev, 8637 struct rtnl_link_stats64 *stats) 8638 { 8639 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8640 int i; 8641 8642 rcu_read_lock(); 8643 for (i = 0; i < adapter->num_rx_queues; i++) { 8644 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8645 u64 bytes, packets; 8646 unsigned int start; 8647 8648 if (ring) { 8649 do { 8650 start = u64_stats_fetch_begin_irq(&ring->syncp); 8651 packets = ring->stats.packets; 8652 bytes = ring->stats.bytes; 8653 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8654 stats->rx_packets += packets; 8655 stats->rx_bytes += bytes; 8656 } 8657 } 8658 8659 for (i = 0; i < adapter->num_tx_queues; i++) { 8660 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8661 8662 ixgbe_get_ring_stats64(stats, ring); 8663 } 8664 for (i = 0; i < adapter->num_xdp_queues; i++) { 8665 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8666 8667 ixgbe_get_ring_stats64(stats, ring); 8668 } 8669 rcu_read_unlock(); 8670 8671 /* following stats updated by ixgbe_watchdog_task() */ 8672 stats->multicast = netdev->stats.multicast; 8673 stats->rx_errors = netdev->stats.rx_errors; 8674 stats->rx_length_errors = netdev->stats.rx_length_errors; 8675 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8676 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8677 } 8678 8679 #ifdef CONFIG_IXGBE_DCB 8680 /** 8681 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8682 * @adapter: pointer to ixgbe_adapter 8683 * @tc: number of traffic classes currently enabled 8684 * 8685 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8686 * 802.1Q priority maps to a packet buffer that exists. 8687 */ 8688 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8689 { 8690 struct ixgbe_hw *hw = &adapter->hw; 8691 u32 reg, rsave; 8692 int i; 8693 8694 /* 82598 have a static priority to TC mapping that can not 8695 * be changed so no validation is needed. 8696 */ 8697 if (hw->mac.type == ixgbe_mac_82598EB) 8698 return; 8699 8700 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8701 rsave = reg; 8702 8703 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8704 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8705 8706 /* If up2tc is out of bounds default to zero */ 8707 if (up2tc > tc) 8708 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8709 } 8710 8711 if (reg != rsave) 8712 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8713 8714 return; 8715 } 8716 8717 /** 8718 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8719 * @adapter: Pointer to adapter struct 8720 * 8721 * Populate the netdev user priority to tc map 8722 */ 8723 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8724 { 8725 struct net_device *dev = adapter->netdev; 8726 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8727 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8728 u8 prio; 8729 8730 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8731 u8 tc = 0; 8732 8733 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8734 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8735 else if (ets) 8736 tc = ets->prio_tc[prio]; 8737 8738 netdev_set_prio_tc_map(dev, prio, tc); 8739 } 8740 } 8741 8742 #endif /* CONFIG_IXGBE_DCB */ 8743 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data) 8744 { 8745 struct ixgbe_adapter *adapter = data; 8746 struct ixgbe_fwd_adapter *accel; 8747 int pool; 8748 8749 /* we only care about macvlans... */ 8750 if (!netif_is_macvlan(vdev)) 8751 return 0; 8752 8753 /* that have hardware offload enabled... */ 8754 accel = macvlan_accel_priv(vdev); 8755 if (!accel) 8756 return 0; 8757 8758 /* If we can relocate to a different bit do so */ 8759 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 8760 if (pool < adapter->num_rx_pools) { 8761 set_bit(pool, adapter->fwd_bitmask); 8762 accel->pool = pool; 8763 return 0; 8764 } 8765 8766 /* if we cannot find a free pool then disable the offload */ 8767 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 8768 macvlan_release_l2fw_offload(vdev); 8769 kfree(accel); 8770 8771 return 0; 8772 } 8773 8774 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 8775 { 8776 struct ixgbe_adapter *adapter = netdev_priv(dev); 8777 8778 /* flush any stale bits out of the fwd bitmask */ 8779 bitmap_clear(adapter->fwd_bitmask, 1, 63); 8780 8781 /* walk through upper devices reassigning pools */ 8782 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 8783 adapter); 8784 } 8785 8786 /** 8787 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8788 * 8789 * @dev: net device to configure 8790 * @tc: number of traffic classes to enable 8791 */ 8792 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8793 { 8794 struct ixgbe_adapter *adapter = netdev_priv(dev); 8795 struct ixgbe_hw *hw = &adapter->hw; 8796 8797 /* Hardware supports up to 8 traffic classes */ 8798 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8799 return -EINVAL; 8800 8801 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8802 return -EINVAL; 8803 8804 /* Hardware has to reinitialize queues and interrupts to 8805 * match packet buffer alignment. Unfortunately, the 8806 * hardware is not flexible enough to do this dynamically. 8807 */ 8808 if (netif_running(dev)) 8809 ixgbe_close(dev); 8810 else 8811 ixgbe_reset(adapter); 8812 8813 ixgbe_clear_interrupt_scheme(adapter); 8814 8815 #ifdef CONFIG_IXGBE_DCB 8816 if (tc) { 8817 netdev_set_num_tc(dev, tc); 8818 ixgbe_set_prio_tc_map(adapter); 8819 8820 adapter->hw_tcs = tc; 8821 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8822 8823 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8824 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8825 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8826 } 8827 } else { 8828 netdev_reset_tc(dev); 8829 8830 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8831 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8832 8833 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8834 adapter->hw_tcs = tc; 8835 8836 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8837 adapter->dcb_cfg.pfc_mode_enable = false; 8838 } 8839 8840 ixgbe_validate_rtr(adapter, tc); 8841 8842 #endif /* CONFIG_IXGBE_DCB */ 8843 ixgbe_init_interrupt_scheme(adapter); 8844 8845 ixgbe_defrag_macvlan_pools(dev); 8846 8847 if (netif_running(dev)) 8848 return ixgbe_open(dev); 8849 8850 return 0; 8851 } 8852 8853 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8854 struct tc_cls_u32_offload *cls) 8855 { 8856 u32 hdl = cls->knode.handle; 8857 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8858 u32 loc = cls->knode.handle & 0xfffff; 8859 int err = 0, i, j; 8860 struct ixgbe_jump_table *jump = NULL; 8861 8862 if (loc > IXGBE_MAX_HW_ENTRIES) 8863 return -EINVAL; 8864 8865 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8866 return -EINVAL; 8867 8868 /* Clear this filter in the link data it is associated with */ 8869 if (uhtid != 0x800) { 8870 jump = adapter->jump_tables[uhtid]; 8871 if (!jump) 8872 return -EINVAL; 8873 if (!test_bit(loc - 1, jump->child_loc_map)) 8874 return -EINVAL; 8875 clear_bit(loc - 1, jump->child_loc_map); 8876 } 8877 8878 /* Check if the filter being deleted is a link */ 8879 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8880 jump = adapter->jump_tables[i]; 8881 if (jump && jump->link_hdl == hdl) { 8882 /* Delete filters in the hardware in the child hash 8883 * table associated with this link 8884 */ 8885 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8886 if (!test_bit(j, jump->child_loc_map)) 8887 continue; 8888 spin_lock(&adapter->fdir_perfect_lock); 8889 err = ixgbe_update_ethtool_fdir_entry(adapter, 8890 NULL, 8891 j + 1); 8892 spin_unlock(&adapter->fdir_perfect_lock); 8893 clear_bit(j, jump->child_loc_map); 8894 } 8895 /* Remove resources for this link */ 8896 kfree(jump->input); 8897 kfree(jump->mask); 8898 kfree(jump); 8899 adapter->jump_tables[i] = NULL; 8900 return err; 8901 } 8902 } 8903 8904 spin_lock(&adapter->fdir_perfect_lock); 8905 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8906 spin_unlock(&adapter->fdir_perfect_lock); 8907 return err; 8908 } 8909 8910 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8911 struct tc_cls_u32_offload *cls) 8912 { 8913 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8914 8915 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8916 return -EINVAL; 8917 8918 /* This ixgbe devices do not support hash tables at the moment 8919 * so abort when given hash tables. 8920 */ 8921 if (cls->hnode.divisor > 0) 8922 return -EINVAL; 8923 8924 set_bit(uhtid - 1, &adapter->tables); 8925 return 0; 8926 } 8927 8928 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8929 struct tc_cls_u32_offload *cls) 8930 { 8931 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8932 8933 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8934 return -EINVAL; 8935 8936 clear_bit(uhtid - 1, &adapter->tables); 8937 return 0; 8938 } 8939 8940 #ifdef CONFIG_NET_CLS_ACT 8941 struct upper_walk_data { 8942 struct ixgbe_adapter *adapter; 8943 u64 action; 8944 int ifindex; 8945 u8 queue; 8946 }; 8947 8948 static int get_macvlan_queue(struct net_device *upper, void *_data) 8949 { 8950 if (netif_is_macvlan(upper)) { 8951 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 8952 struct upper_walk_data *data = _data; 8953 struct ixgbe_adapter *adapter = data->adapter; 8954 int ifindex = data->ifindex; 8955 8956 if (vadapter && upper->ifindex == ifindex) { 8957 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 8958 data->action = data->queue; 8959 return 1; 8960 } 8961 } 8962 8963 return 0; 8964 } 8965 8966 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 8967 u8 *queue, u64 *action) 8968 { 8969 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 8970 unsigned int num_vfs = adapter->num_vfs, vf; 8971 struct upper_walk_data data; 8972 struct net_device *upper; 8973 8974 /* redirect to a SRIOV VF */ 8975 for (vf = 0; vf < num_vfs; ++vf) { 8976 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 8977 if (upper->ifindex == ifindex) { 8978 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 8979 *action = vf + 1; 8980 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 8981 return 0; 8982 } 8983 } 8984 8985 /* redirect to a offloaded macvlan netdev */ 8986 data.adapter = adapter; 8987 data.ifindex = ifindex; 8988 data.action = 0; 8989 data.queue = 0; 8990 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 8991 get_macvlan_queue, &data)) { 8992 *action = data.action; 8993 *queue = data.queue; 8994 8995 return 0; 8996 } 8997 8998 return -EINVAL; 8999 } 9000 9001 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9002 struct tcf_exts *exts, u64 *action, u8 *queue) 9003 { 9004 const struct tc_action *a; 9005 LIST_HEAD(actions); 9006 9007 if (!tcf_exts_has_actions(exts)) 9008 return -EINVAL; 9009 9010 tcf_exts_to_list(exts, &actions); 9011 list_for_each_entry(a, &actions, list) { 9012 9013 /* Drop action */ 9014 if (is_tcf_gact_shot(a)) { 9015 *action = IXGBE_FDIR_DROP_QUEUE; 9016 *queue = IXGBE_FDIR_DROP_QUEUE; 9017 return 0; 9018 } 9019 9020 /* Redirect to a VF or a offloaded macvlan */ 9021 if (is_tcf_mirred_egress_redirect(a)) { 9022 struct net_device *dev = tcf_mirred_dev(a); 9023 9024 if (!dev) 9025 return -EINVAL; 9026 return handle_redirect_action(adapter, dev->ifindex, 9027 queue, action); 9028 } 9029 9030 return -EINVAL; 9031 } 9032 9033 return -EINVAL; 9034 } 9035 #else 9036 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9037 struct tcf_exts *exts, u64 *action, u8 *queue) 9038 { 9039 return -EINVAL; 9040 } 9041 #endif /* CONFIG_NET_CLS_ACT */ 9042 9043 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9044 union ixgbe_atr_input *mask, 9045 struct tc_cls_u32_offload *cls, 9046 struct ixgbe_mat_field *field_ptr, 9047 struct ixgbe_nexthdr *nexthdr) 9048 { 9049 int i, j, off; 9050 __be32 val, m; 9051 bool found_entry = false, found_jump_field = false; 9052 9053 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9054 off = cls->knode.sel->keys[i].off; 9055 val = cls->knode.sel->keys[i].val; 9056 m = cls->knode.sel->keys[i].mask; 9057 9058 for (j = 0; field_ptr[j].val; j++) { 9059 if (field_ptr[j].off == off) { 9060 field_ptr[j].val(input, mask, (__force u32)val, 9061 (__force u32)m); 9062 input->filter.formatted.flow_type |= 9063 field_ptr[j].type; 9064 found_entry = true; 9065 break; 9066 } 9067 } 9068 if (nexthdr) { 9069 if (nexthdr->off == cls->knode.sel->keys[i].off && 9070 nexthdr->val == 9071 (__force u32)cls->knode.sel->keys[i].val && 9072 nexthdr->mask == 9073 (__force u32)cls->knode.sel->keys[i].mask) 9074 found_jump_field = true; 9075 else 9076 continue; 9077 } 9078 } 9079 9080 if (nexthdr && !found_jump_field) 9081 return -EINVAL; 9082 9083 if (!found_entry) 9084 return 0; 9085 9086 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9087 IXGBE_ATR_L4TYPE_MASK; 9088 9089 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9090 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9091 9092 return 0; 9093 } 9094 9095 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9096 struct tc_cls_u32_offload *cls) 9097 { 9098 __be16 protocol = cls->common.protocol; 9099 u32 loc = cls->knode.handle & 0xfffff; 9100 struct ixgbe_hw *hw = &adapter->hw; 9101 struct ixgbe_mat_field *field_ptr; 9102 struct ixgbe_fdir_filter *input = NULL; 9103 union ixgbe_atr_input *mask = NULL; 9104 struct ixgbe_jump_table *jump = NULL; 9105 int i, err = -EINVAL; 9106 u8 queue; 9107 u32 uhtid, link_uhtid; 9108 9109 uhtid = TC_U32_USERHTID(cls->knode.handle); 9110 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9111 9112 /* At the moment cls_u32 jumps to network layer and skips past 9113 * L2 headers. The canonical method to match L2 frames is to use 9114 * negative values. However this is error prone at best but really 9115 * just broken because there is no way to "know" what sort of hdr 9116 * is in front of the network layer. Fix cls_u32 to support L2 9117 * headers when needed. 9118 */ 9119 if (protocol != htons(ETH_P_IP)) 9120 return err; 9121 9122 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9123 e_err(drv, "Location out of range\n"); 9124 return err; 9125 } 9126 9127 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9128 * links and also the fields used to advance the parser across each 9129 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9130 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9131 * To add support for new nodes update ixgbe_model.h parse structures 9132 * this function _should_ be generic try not to hardcode values here. 9133 */ 9134 if (uhtid == 0x800) { 9135 field_ptr = (adapter->jump_tables[0])->mat; 9136 } else { 9137 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9138 return err; 9139 if (!adapter->jump_tables[uhtid]) 9140 return err; 9141 field_ptr = (adapter->jump_tables[uhtid])->mat; 9142 } 9143 9144 if (!field_ptr) 9145 return err; 9146 9147 /* At this point we know the field_ptr is valid and need to either 9148 * build cls_u32 link or attach filter. Because adding a link to 9149 * a handle that does not exist is invalid and the same for adding 9150 * rules to handles that don't exist. 9151 */ 9152 9153 if (link_uhtid) { 9154 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9155 9156 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9157 return err; 9158 9159 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9160 return err; 9161 9162 /* Multiple filters as links to the same hash table are not 9163 * supported. To add a new filter with the same next header 9164 * but different match/jump conditions, create a new hash table 9165 * and link to it. 9166 */ 9167 if (adapter->jump_tables[link_uhtid] && 9168 (adapter->jump_tables[link_uhtid])->link_hdl) { 9169 e_err(drv, "Link filter exists for link: %x\n", 9170 link_uhtid); 9171 return err; 9172 } 9173 9174 for (i = 0; nexthdr[i].jump; i++) { 9175 if (nexthdr[i].o != cls->knode.sel->offoff || 9176 nexthdr[i].s != cls->knode.sel->offshift || 9177 nexthdr[i].m != 9178 (__force u32)cls->knode.sel->offmask) 9179 return err; 9180 9181 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9182 if (!jump) 9183 return -ENOMEM; 9184 input = kzalloc(sizeof(*input), GFP_KERNEL); 9185 if (!input) { 9186 err = -ENOMEM; 9187 goto free_jump; 9188 } 9189 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9190 if (!mask) { 9191 err = -ENOMEM; 9192 goto free_input; 9193 } 9194 jump->input = input; 9195 jump->mask = mask; 9196 jump->link_hdl = cls->knode.handle; 9197 9198 err = ixgbe_clsu32_build_input(input, mask, cls, 9199 field_ptr, &nexthdr[i]); 9200 if (!err) { 9201 jump->mat = nexthdr[i].jump; 9202 adapter->jump_tables[link_uhtid] = jump; 9203 break; 9204 } 9205 } 9206 return 0; 9207 } 9208 9209 input = kzalloc(sizeof(*input), GFP_KERNEL); 9210 if (!input) 9211 return -ENOMEM; 9212 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9213 if (!mask) { 9214 err = -ENOMEM; 9215 goto free_input; 9216 } 9217 9218 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9219 if ((adapter->jump_tables[uhtid])->input) 9220 memcpy(input, (adapter->jump_tables[uhtid])->input, 9221 sizeof(*input)); 9222 if ((adapter->jump_tables[uhtid])->mask) 9223 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9224 sizeof(*mask)); 9225 9226 /* Lookup in all child hash tables if this location is already 9227 * filled with a filter 9228 */ 9229 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9230 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9231 9232 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9233 e_err(drv, "Filter exists in location: %x\n", 9234 loc); 9235 err = -EINVAL; 9236 goto err_out; 9237 } 9238 } 9239 } 9240 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9241 if (err) 9242 goto err_out; 9243 9244 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9245 &queue); 9246 if (err < 0) 9247 goto err_out; 9248 9249 input->sw_idx = loc; 9250 9251 spin_lock(&adapter->fdir_perfect_lock); 9252 9253 if (hlist_empty(&adapter->fdir_filter_list)) { 9254 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9255 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9256 if (err) 9257 goto err_out_w_lock; 9258 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9259 err = -EINVAL; 9260 goto err_out_w_lock; 9261 } 9262 9263 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9264 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9265 input->sw_idx, queue); 9266 if (!err) 9267 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9268 spin_unlock(&adapter->fdir_perfect_lock); 9269 9270 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9271 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9272 9273 kfree(mask); 9274 return err; 9275 err_out_w_lock: 9276 spin_unlock(&adapter->fdir_perfect_lock); 9277 err_out: 9278 kfree(mask); 9279 free_input: 9280 kfree(input); 9281 free_jump: 9282 kfree(jump); 9283 return err; 9284 } 9285 9286 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9287 struct tc_cls_u32_offload *cls_u32) 9288 { 9289 switch (cls_u32->command) { 9290 case TC_CLSU32_NEW_KNODE: 9291 case TC_CLSU32_REPLACE_KNODE: 9292 return ixgbe_configure_clsu32(adapter, cls_u32); 9293 case TC_CLSU32_DELETE_KNODE: 9294 return ixgbe_delete_clsu32(adapter, cls_u32); 9295 case TC_CLSU32_NEW_HNODE: 9296 case TC_CLSU32_REPLACE_HNODE: 9297 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9298 case TC_CLSU32_DELETE_HNODE: 9299 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9300 default: 9301 return -EOPNOTSUPP; 9302 } 9303 } 9304 9305 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9306 void *cb_priv) 9307 { 9308 struct ixgbe_adapter *adapter = cb_priv; 9309 9310 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9311 return -EOPNOTSUPP; 9312 9313 switch (type) { 9314 case TC_SETUP_CLSU32: 9315 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9316 default: 9317 return -EOPNOTSUPP; 9318 } 9319 } 9320 9321 static int ixgbe_setup_tc_block(struct net_device *dev, 9322 struct tc_block_offload *f) 9323 { 9324 struct ixgbe_adapter *adapter = netdev_priv(dev); 9325 9326 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9327 return -EOPNOTSUPP; 9328 9329 switch (f->command) { 9330 case TC_BLOCK_BIND: 9331 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9332 adapter, adapter); 9333 case TC_BLOCK_UNBIND: 9334 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9335 adapter); 9336 return 0; 9337 default: 9338 return -EOPNOTSUPP; 9339 } 9340 } 9341 9342 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9343 struct tc_mqprio_qopt *mqprio) 9344 { 9345 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9346 return ixgbe_setup_tc(dev, mqprio->num_tc); 9347 } 9348 9349 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9350 void *type_data) 9351 { 9352 switch (type) { 9353 case TC_SETUP_BLOCK: 9354 return ixgbe_setup_tc_block(dev, type_data); 9355 case TC_SETUP_QDISC_MQPRIO: 9356 return ixgbe_setup_tc_mqprio(dev, type_data); 9357 default: 9358 return -EOPNOTSUPP; 9359 } 9360 } 9361 9362 #ifdef CONFIG_PCI_IOV 9363 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9364 { 9365 struct net_device *netdev = adapter->netdev; 9366 9367 rtnl_lock(); 9368 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9369 rtnl_unlock(); 9370 } 9371 9372 #endif 9373 void ixgbe_do_reset(struct net_device *netdev) 9374 { 9375 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9376 9377 if (netif_running(netdev)) 9378 ixgbe_reinit_locked(adapter); 9379 else 9380 ixgbe_reset(adapter); 9381 } 9382 9383 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9384 netdev_features_t features) 9385 { 9386 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9387 9388 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9389 if (!(features & NETIF_F_RXCSUM)) 9390 features &= ~NETIF_F_LRO; 9391 9392 /* Turn off LRO if not RSC capable */ 9393 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9394 features &= ~NETIF_F_LRO; 9395 9396 return features; 9397 } 9398 9399 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9400 { 9401 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9402 num_online_cpus()); 9403 9404 /* go back to full RSS if we're not running SR-IOV */ 9405 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9406 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9407 IXGBE_FLAG_SRIOV_ENABLED); 9408 9409 adapter->ring_feature[RING_F_RSS].limit = rss; 9410 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9411 9412 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9413 } 9414 9415 static int ixgbe_set_features(struct net_device *netdev, 9416 netdev_features_t features) 9417 { 9418 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9419 netdev_features_t changed = netdev->features ^ features; 9420 bool need_reset = false; 9421 9422 /* Make sure RSC matches LRO, reset if change */ 9423 if (!(features & NETIF_F_LRO)) { 9424 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9425 need_reset = true; 9426 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9427 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9428 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9429 if (adapter->rx_itr_setting == 1 || 9430 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9431 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9432 need_reset = true; 9433 } else if ((changed ^ features) & NETIF_F_LRO) { 9434 e_info(probe, "rx-usecs set too low, " 9435 "disabling RSC\n"); 9436 } 9437 } 9438 9439 /* 9440 * Check if Flow Director n-tuple support or hw_tc support was 9441 * enabled or disabled. If the state changed, we need to reset. 9442 */ 9443 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9444 /* turn off ATR, enable perfect filters and reset */ 9445 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9446 need_reset = true; 9447 9448 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9449 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9450 } else { 9451 /* turn off perfect filters, enable ATR and reset */ 9452 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9453 need_reset = true; 9454 9455 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9456 9457 /* We cannot enable ATR if SR-IOV is enabled */ 9458 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9459 /* We cannot enable ATR if we have 2 or more tcs */ 9460 (adapter->hw_tcs > 1) || 9461 /* We cannot enable ATR if RSS is disabled */ 9462 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9463 /* A sample rate of 0 indicates ATR disabled */ 9464 (!adapter->atr_sample_rate)) 9465 ; /* do nothing not supported */ 9466 else /* otherwise supported and set the flag */ 9467 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9468 } 9469 9470 if (changed & NETIF_F_RXALL) 9471 need_reset = true; 9472 9473 netdev->features = features; 9474 9475 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9476 if (features & NETIF_F_RXCSUM) { 9477 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9478 } else { 9479 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9480 9481 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9482 } 9483 } 9484 9485 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9486 if (features & NETIF_F_RXCSUM) { 9487 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9488 } else { 9489 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9490 9491 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9492 } 9493 } 9494 9495 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9496 ixgbe_reset_l2fw_offload(adapter); 9497 else if (need_reset) 9498 ixgbe_do_reset(netdev); 9499 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9500 NETIF_F_HW_VLAN_CTAG_FILTER)) 9501 ixgbe_set_rx_mode(netdev); 9502 9503 return 0; 9504 } 9505 9506 /** 9507 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9508 * @dev: The port's netdev 9509 * @ti: Tunnel endpoint information 9510 **/ 9511 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9512 struct udp_tunnel_info *ti) 9513 { 9514 struct ixgbe_adapter *adapter = netdev_priv(dev); 9515 struct ixgbe_hw *hw = &adapter->hw; 9516 __be16 port = ti->port; 9517 u32 port_shift = 0; 9518 u32 reg; 9519 9520 if (ti->sa_family != AF_INET) 9521 return; 9522 9523 switch (ti->type) { 9524 case UDP_TUNNEL_TYPE_VXLAN: 9525 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9526 return; 9527 9528 if (adapter->vxlan_port == port) 9529 return; 9530 9531 if (adapter->vxlan_port) { 9532 netdev_info(dev, 9533 "VXLAN port %d set, not adding port %d\n", 9534 ntohs(adapter->vxlan_port), 9535 ntohs(port)); 9536 return; 9537 } 9538 9539 adapter->vxlan_port = port; 9540 break; 9541 case UDP_TUNNEL_TYPE_GENEVE: 9542 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9543 return; 9544 9545 if (adapter->geneve_port == port) 9546 return; 9547 9548 if (adapter->geneve_port) { 9549 netdev_info(dev, 9550 "GENEVE port %d set, not adding port %d\n", 9551 ntohs(adapter->geneve_port), 9552 ntohs(port)); 9553 return; 9554 } 9555 9556 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9557 adapter->geneve_port = port; 9558 break; 9559 default: 9560 return; 9561 } 9562 9563 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9564 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9565 } 9566 9567 /** 9568 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9569 * @dev: The port's netdev 9570 * @ti: Tunnel endpoint information 9571 **/ 9572 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9573 struct udp_tunnel_info *ti) 9574 { 9575 struct ixgbe_adapter *adapter = netdev_priv(dev); 9576 u32 port_mask; 9577 9578 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9579 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9580 return; 9581 9582 if (ti->sa_family != AF_INET) 9583 return; 9584 9585 switch (ti->type) { 9586 case UDP_TUNNEL_TYPE_VXLAN: 9587 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9588 return; 9589 9590 if (adapter->vxlan_port != ti->port) { 9591 netdev_info(dev, "VXLAN port %d not found\n", 9592 ntohs(ti->port)); 9593 return; 9594 } 9595 9596 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9597 break; 9598 case UDP_TUNNEL_TYPE_GENEVE: 9599 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9600 return; 9601 9602 if (adapter->geneve_port != ti->port) { 9603 netdev_info(dev, "GENEVE port %d not found\n", 9604 ntohs(ti->port)); 9605 return; 9606 } 9607 9608 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9609 break; 9610 default: 9611 return; 9612 } 9613 9614 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9615 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9616 } 9617 9618 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9619 struct net_device *dev, 9620 const unsigned char *addr, u16 vid, 9621 u16 flags) 9622 { 9623 /* guarantee we can provide a unique filter for the unicast address */ 9624 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9625 struct ixgbe_adapter *adapter = netdev_priv(dev); 9626 u16 pool = VMDQ_P(0); 9627 9628 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9629 return -ENOMEM; 9630 } 9631 9632 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9633 } 9634 9635 /** 9636 * ixgbe_configure_bridge_mode - set various bridge modes 9637 * @adapter: the private structure 9638 * @mode: requested bridge mode 9639 * 9640 * Configure some settings require for various bridge modes. 9641 **/ 9642 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9643 __u16 mode) 9644 { 9645 struct ixgbe_hw *hw = &adapter->hw; 9646 unsigned int p, num_pools; 9647 u32 vmdctl; 9648 9649 switch (mode) { 9650 case BRIDGE_MODE_VEPA: 9651 /* disable Tx loopback, rely on switch hairpin mode */ 9652 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9653 9654 /* must enable Rx switching replication to allow multicast 9655 * packet reception on all VFs, and to enable source address 9656 * pruning. 9657 */ 9658 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9659 vmdctl |= IXGBE_VT_CTL_REPLEN; 9660 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9661 9662 /* enable Rx source address pruning. Note, this requires 9663 * replication to be enabled or else it does nothing. 9664 */ 9665 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9666 for (p = 0; p < num_pools; p++) { 9667 if (hw->mac.ops.set_source_address_pruning) 9668 hw->mac.ops.set_source_address_pruning(hw, 9669 true, 9670 p); 9671 } 9672 break; 9673 case BRIDGE_MODE_VEB: 9674 /* enable Tx loopback for internal VF/PF communication */ 9675 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9676 IXGBE_PFDTXGSWC_VT_LBEN); 9677 9678 /* disable Rx switching replication unless we have SR-IOV 9679 * virtual functions 9680 */ 9681 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9682 if (!adapter->num_vfs) 9683 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9684 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9685 9686 /* disable Rx source address pruning, since we don't expect to 9687 * be receiving external loopback of our transmitted frames. 9688 */ 9689 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9690 for (p = 0; p < num_pools; p++) { 9691 if (hw->mac.ops.set_source_address_pruning) 9692 hw->mac.ops.set_source_address_pruning(hw, 9693 false, 9694 p); 9695 } 9696 break; 9697 default: 9698 return -EINVAL; 9699 } 9700 9701 adapter->bridge_mode = mode; 9702 9703 e_info(drv, "enabling bridge mode: %s\n", 9704 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9705 9706 return 0; 9707 } 9708 9709 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9710 struct nlmsghdr *nlh, u16 flags) 9711 { 9712 struct ixgbe_adapter *adapter = netdev_priv(dev); 9713 struct nlattr *attr, *br_spec; 9714 int rem; 9715 9716 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9717 return -EOPNOTSUPP; 9718 9719 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9720 if (!br_spec) 9721 return -EINVAL; 9722 9723 nla_for_each_nested(attr, br_spec, rem) { 9724 int status; 9725 __u16 mode; 9726 9727 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9728 continue; 9729 9730 if (nla_len(attr) < sizeof(mode)) 9731 return -EINVAL; 9732 9733 mode = nla_get_u16(attr); 9734 status = ixgbe_configure_bridge_mode(adapter, mode); 9735 if (status) 9736 return status; 9737 9738 break; 9739 } 9740 9741 return 0; 9742 } 9743 9744 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9745 struct net_device *dev, 9746 u32 filter_mask, int nlflags) 9747 { 9748 struct ixgbe_adapter *adapter = netdev_priv(dev); 9749 9750 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9751 return 0; 9752 9753 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9754 adapter->bridge_mode, 0, 0, nlflags, 9755 filter_mask, NULL); 9756 } 9757 9758 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9759 { 9760 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9761 struct ixgbe_fwd_adapter *accel; 9762 int tcs = adapter->hw_tcs ? : 1; 9763 int pool, err; 9764 9765 /* The hardware supported by ixgbe only filters on the destination MAC 9766 * address. In order to avoid issues we only support offloading modes 9767 * where the hardware can actually provide the functionality. 9768 */ 9769 if (!macvlan_supports_dest_filter(vdev)) 9770 return ERR_PTR(-EMEDIUMTYPE); 9771 9772 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9773 if (pool == adapter->num_rx_pools) { 9774 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 9775 u16 reserved_pools; 9776 9777 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9778 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 9779 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 9780 return ERR_PTR(-EBUSY); 9781 9782 /* Hardware has a limited number of available pools. Each VF, 9783 * and the PF require a pool. Check to ensure we don't 9784 * attempt to use more then the available number of pools. 9785 */ 9786 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9787 return ERR_PTR(-EBUSY); 9788 9789 /* Enable VMDq flag so device will be set in VM mode */ 9790 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 9791 IXGBE_FLAG_SRIOV_ENABLED; 9792 9793 /* Try to reserve as many queues per pool as possible, 9794 * we start with the configurations that support 4 queues 9795 * per pools, followed by 2, and then by just 1 per pool. 9796 */ 9797 if (used_pools < 32 && adapter->num_rx_pools < 16) 9798 reserved_pools = min_t(u16, 9799 32 - used_pools, 9800 16 - adapter->num_rx_pools); 9801 else if (adapter->num_rx_pools < 32) 9802 reserved_pools = min_t(u16, 9803 64 - used_pools, 9804 32 - adapter->num_rx_pools); 9805 else 9806 reserved_pools = 64 - used_pools; 9807 9808 9809 if (!reserved_pools) 9810 return ERR_PTR(-EBUSY); 9811 9812 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 9813 9814 /* Force reinit of ring allocation with VMDQ enabled */ 9815 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 9816 if (err) 9817 return ERR_PTR(err); 9818 9819 if (pool >= adapter->num_rx_pools) 9820 return ERR_PTR(-ENOMEM); 9821 } 9822 9823 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 9824 if (!accel) 9825 return ERR_PTR(-ENOMEM); 9826 9827 set_bit(pool, adapter->fwd_bitmask); 9828 accel->pool = pool; 9829 accel->netdev = vdev; 9830 9831 if (!netif_running(pdev)) 9832 return accel; 9833 9834 err = ixgbe_fwd_ring_up(adapter, accel); 9835 if (err) 9836 return ERR_PTR(err); 9837 9838 return accel; 9839 } 9840 9841 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9842 { 9843 struct ixgbe_fwd_adapter *accel = priv; 9844 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9845 unsigned int rxbase = accel->rx_base_queue; 9846 unsigned int i; 9847 9848 /* delete unicast filter associated with offloaded interface */ 9849 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 9850 VMDQ_P(accel->pool)); 9851 9852 /* Allow remaining Rx packets to get flushed out of the 9853 * Rx FIFO before we drop the netdev for the ring. 9854 */ 9855 usleep_range(10000, 20000); 9856 9857 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 9858 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 9859 struct ixgbe_q_vector *qv = ring->q_vector; 9860 9861 /* Make sure we aren't processing any packets and clear 9862 * netdev to shut down the ring. 9863 */ 9864 if (netif_running(adapter->netdev)) 9865 napi_synchronize(&qv->napi); 9866 ring->netdev = NULL; 9867 } 9868 9869 clear_bit(accel->pool, adapter->fwd_bitmask); 9870 kfree(accel); 9871 } 9872 9873 #define IXGBE_MAX_MAC_HDR_LEN 127 9874 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9875 9876 static netdev_features_t 9877 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9878 netdev_features_t features) 9879 { 9880 unsigned int network_hdr_len, mac_hdr_len; 9881 9882 /* Make certain the headers can be described by a context descriptor */ 9883 mac_hdr_len = skb_network_header(skb) - skb->data; 9884 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9885 return features & ~(NETIF_F_HW_CSUM | 9886 NETIF_F_SCTP_CRC | 9887 NETIF_F_HW_VLAN_CTAG_TX | 9888 NETIF_F_TSO | 9889 NETIF_F_TSO6); 9890 9891 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9892 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9893 return features & ~(NETIF_F_HW_CSUM | 9894 NETIF_F_SCTP_CRC | 9895 NETIF_F_TSO | 9896 NETIF_F_TSO6); 9897 9898 /* We can only support IPV4 TSO in tunnels if we can mangle the 9899 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9900 * IPsec offoad sets skb->encapsulation but still can handle 9901 * the TSO, so it's the exception. 9902 */ 9903 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 9904 #ifdef CONFIG_XFRM_OFFLOAD 9905 if (!skb->sp) 9906 #endif 9907 features &= ~NETIF_F_TSO; 9908 } 9909 9910 return features; 9911 } 9912 9913 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9914 { 9915 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9916 struct ixgbe_adapter *adapter = netdev_priv(dev); 9917 struct bpf_prog *old_prog; 9918 9919 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9920 return -EINVAL; 9921 9922 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9923 return -EINVAL; 9924 9925 /* verify ixgbe ring attributes are sufficient for XDP */ 9926 for (i = 0; i < adapter->num_rx_queues; i++) { 9927 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9928 9929 if (ring_is_rsc_enabled(ring)) 9930 return -EINVAL; 9931 9932 if (frame_size > ixgbe_rx_bufsz(ring)) 9933 return -EINVAL; 9934 } 9935 9936 if (nr_cpu_ids > MAX_XDP_QUEUES) 9937 return -ENOMEM; 9938 9939 old_prog = xchg(&adapter->xdp_prog, prog); 9940 9941 /* If transitioning XDP modes reconfigure rings */ 9942 if (!!prog != !!old_prog) { 9943 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 9944 9945 if (err) { 9946 rcu_assign_pointer(adapter->xdp_prog, old_prog); 9947 return -EINVAL; 9948 } 9949 } else { 9950 for (i = 0; i < adapter->num_rx_queues; i++) 9951 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 9952 adapter->xdp_prog); 9953 } 9954 9955 if (old_prog) 9956 bpf_prog_put(old_prog); 9957 9958 return 0; 9959 } 9960 9961 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 9962 { 9963 struct ixgbe_adapter *adapter = netdev_priv(dev); 9964 9965 switch (xdp->command) { 9966 case XDP_SETUP_PROG: 9967 return ixgbe_xdp_setup(dev, xdp->prog); 9968 case XDP_QUERY_PROG: 9969 xdp->prog_attached = !!(adapter->xdp_prog); 9970 xdp->prog_id = adapter->xdp_prog ? 9971 adapter->xdp_prog->aux->id : 0; 9972 return 0; 9973 default: 9974 return -EINVAL; 9975 } 9976 } 9977 9978 static void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 9979 { 9980 /* Force memory writes to complete before letting h/w know there 9981 * are new descriptors to fetch. 9982 */ 9983 wmb(); 9984 writel(ring->next_to_use, ring->tail); 9985 } 9986 9987 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 9988 struct xdp_frame **frames, u32 flags) 9989 { 9990 struct ixgbe_adapter *adapter = netdev_priv(dev); 9991 struct ixgbe_ring *ring; 9992 int drops = 0; 9993 int i; 9994 9995 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 9996 return -ENETDOWN; 9997 9998 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 9999 return -EINVAL; 10000 10001 /* During program transitions its possible adapter->xdp_prog is assigned 10002 * but ring has not been configured yet. In this case simply abort xmit. 10003 */ 10004 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10005 if (unlikely(!ring)) 10006 return -ENXIO; 10007 10008 for (i = 0; i < n; i++) { 10009 struct xdp_frame *xdpf = frames[i]; 10010 int err; 10011 10012 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10013 if (err != IXGBE_XDP_TX) { 10014 xdp_return_frame_rx_napi(xdpf); 10015 drops++; 10016 } 10017 } 10018 10019 if (unlikely(flags & XDP_XMIT_FLUSH)) 10020 ixgbe_xdp_ring_update_tail(ring); 10021 10022 return n - drops; 10023 } 10024 10025 static const struct net_device_ops ixgbe_netdev_ops = { 10026 .ndo_open = ixgbe_open, 10027 .ndo_stop = ixgbe_close, 10028 .ndo_start_xmit = ixgbe_xmit_frame, 10029 .ndo_select_queue = ixgbe_select_queue, 10030 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10031 .ndo_validate_addr = eth_validate_addr, 10032 .ndo_set_mac_address = ixgbe_set_mac, 10033 .ndo_change_mtu = ixgbe_change_mtu, 10034 .ndo_tx_timeout = ixgbe_tx_timeout, 10035 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10036 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10037 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10038 .ndo_do_ioctl = ixgbe_ioctl, 10039 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10040 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10041 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10042 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10043 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10044 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10045 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10046 .ndo_get_stats64 = ixgbe_get_stats64, 10047 .ndo_setup_tc = __ixgbe_setup_tc, 10048 #ifdef CONFIG_NET_POLL_CONTROLLER 10049 .ndo_poll_controller = ixgbe_netpoll, 10050 #endif 10051 #ifdef IXGBE_FCOE 10052 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10053 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10054 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10055 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10056 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10057 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10058 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10059 #endif /* IXGBE_FCOE */ 10060 .ndo_set_features = ixgbe_set_features, 10061 .ndo_fix_features = ixgbe_fix_features, 10062 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10063 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10064 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10065 .ndo_dfwd_add_station = ixgbe_fwd_add, 10066 .ndo_dfwd_del_station = ixgbe_fwd_del, 10067 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10068 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10069 .ndo_features_check = ixgbe_features_check, 10070 .ndo_bpf = ixgbe_xdp, 10071 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10072 }; 10073 10074 /** 10075 * ixgbe_enumerate_functions - Get the number of ports this device has 10076 * @adapter: adapter structure 10077 * 10078 * This function enumerates the phsyical functions co-located on a single slot, 10079 * in order to determine how many ports a device has. This is most useful in 10080 * determining the required GT/s of PCIe bandwidth necessary for optimal 10081 * performance. 10082 **/ 10083 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10084 { 10085 struct pci_dev *entry, *pdev = adapter->pdev; 10086 int physfns = 0; 10087 10088 /* Some cards can not use the generic count PCIe functions method, 10089 * because they are behind a parent switch, so we hardcode these with 10090 * the correct number of functions. 10091 */ 10092 if (ixgbe_pcie_from_parent(&adapter->hw)) 10093 physfns = 4; 10094 10095 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10096 /* don't count virtual functions */ 10097 if (entry->is_virtfn) 10098 continue; 10099 10100 /* When the devices on the bus don't all match our device ID, 10101 * we can't reliably determine the correct number of 10102 * functions. This can occur if a function has been direct 10103 * attached to a virtual machine using VT-d, for example. In 10104 * this case, simply return -1 to indicate this. 10105 */ 10106 if ((entry->vendor != pdev->vendor) || 10107 (entry->device != pdev->device)) 10108 return -1; 10109 10110 physfns++; 10111 } 10112 10113 return physfns; 10114 } 10115 10116 /** 10117 * ixgbe_wol_supported - Check whether device supports WoL 10118 * @adapter: the adapter private structure 10119 * @device_id: the device ID 10120 * @subdevice_id: the subsystem device ID 10121 * 10122 * This function is used by probe and ethtool to determine 10123 * which devices have WoL support 10124 * 10125 **/ 10126 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10127 u16 subdevice_id) 10128 { 10129 struct ixgbe_hw *hw = &adapter->hw; 10130 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10131 10132 /* WOL not supported on 82598 */ 10133 if (hw->mac.type == ixgbe_mac_82598EB) 10134 return false; 10135 10136 /* check eeprom to see if WOL is enabled for X540 and newer */ 10137 if (hw->mac.type >= ixgbe_mac_X540) { 10138 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10139 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10140 (hw->bus.func == 0))) 10141 return true; 10142 } 10143 10144 /* WOL is determined based on device IDs for 82599 MACs */ 10145 switch (device_id) { 10146 case IXGBE_DEV_ID_82599_SFP: 10147 /* Only these subdevices could supports WOL */ 10148 switch (subdevice_id) { 10149 case IXGBE_SUBDEV_ID_82599_560FLR: 10150 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10151 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10152 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10153 /* only support first port */ 10154 if (hw->bus.func != 0) 10155 break; 10156 /* fall through */ 10157 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10158 case IXGBE_SUBDEV_ID_82599_SFP: 10159 case IXGBE_SUBDEV_ID_82599_RNDC: 10160 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10161 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10162 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10163 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10164 return true; 10165 } 10166 break; 10167 case IXGBE_DEV_ID_82599EN_SFP: 10168 /* Only these subdevices support WOL */ 10169 switch (subdevice_id) { 10170 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10171 return true; 10172 } 10173 break; 10174 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10175 /* All except this subdevice support WOL */ 10176 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10177 return true; 10178 break; 10179 case IXGBE_DEV_ID_82599_KX4: 10180 return true; 10181 default: 10182 break; 10183 } 10184 10185 return false; 10186 } 10187 10188 /** 10189 * ixgbe_set_fw_version - Set FW version 10190 * @adapter: the adapter private structure 10191 * 10192 * This function is used by probe and ethtool to determine the FW version to 10193 * format to display. The FW version is taken from the EEPROM/NVM. 10194 */ 10195 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10196 { 10197 struct ixgbe_hw *hw = &adapter->hw; 10198 struct ixgbe_nvm_version nvm_ver; 10199 10200 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10201 if (nvm_ver.oem_valid) { 10202 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10203 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10204 nvm_ver.oem_release); 10205 return; 10206 } 10207 10208 ixgbe_get_etk_id(hw, &nvm_ver); 10209 ixgbe_get_orom_version(hw, &nvm_ver); 10210 10211 if (nvm_ver.or_valid) { 10212 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10213 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10214 nvm_ver.or_build, nvm_ver.or_patch); 10215 return; 10216 } 10217 10218 /* Set ETrack ID format */ 10219 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10220 "0x%08x", nvm_ver.etk_id); 10221 } 10222 10223 /** 10224 * ixgbe_probe - Device Initialization Routine 10225 * @pdev: PCI device information struct 10226 * @ent: entry in ixgbe_pci_tbl 10227 * 10228 * Returns 0 on success, negative on failure 10229 * 10230 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10231 * The OS initialization, configuring of the adapter private structure, 10232 * and a hardware reset occur. 10233 **/ 10234 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10235 { 10236 struct net_device *netdev; 10237 struct ixgbe_adapter *adapter = NULL; 10238 struct ixgbe_hw *hw; 10239 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10240 int i, err, pci_using_dac, expected_gts; 10241 unsigned int indices = MAX_TX_QUEUES; 10242 u8 part_str[IXGBE_PBANUM_LENGTH]; 10243 bool disable_dev = false; 10244 #ifdef IXGBE_FCOE 10245 u16 device_caps; 10246 #endif 10247 u32 eec; 10248 10249 /* Catch broken hardware that put the wrong VF device ID in 10250 * the PCIe SR-IOV capability. 10251 */ 10252 if (pdev->is_virtfn) { 10253 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10254 pci_name(pdev), pdev->vendor, pdev->device); 10255 return -EINVAL; 10256 } 10257 10258 err = pci_enable_device_mem(pdev); 10259 if (err) 10260 return err; 10261 10262 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10263 pci_using_dac = 1; 10264 } else { 10265 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10266 if (err) { 10267 dev_err(&pdev->dev, 10268 "No usable DMA configuration, aborting\n"); 10269 goto err_dma; 10270 } 10271 pci_using_dac = 0; 10272 } 10273 10274 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10275 if (err) { 10276 dev_err(&pdev->dev, 10277 "pci_request_selected_regions failed 0x%x\n", err); 10278 goto err_pci_reg; 10279 } 10280 10281 pci_enable_pcie_error_reporting(pdev); 10282 10283 pci_set_master(pdev); 10284 pci_save_state(pdev); 10285 10286 if (ii->mac == ixgbe_mac_82598EB) { 10287 #ifdef CONFIG_IXGBE_DCB 10288 /* 8 TC w/ 4 queues per TC */ 10289 indices = 4 * MAX_TRAFFIC_CLASS; 10290 #else 10291 indices = IXGBE_MAX_RSS_INDICES; 10292 #endif 10293 } 10294 10295 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10296 if (!netdev) { 10297 err = -ENOMEM; 10298 goto err_alloc_etherdev; 10299 } 10300 10301 SET_NETDEV_DEV(netdev, &pdev->dev); 10302 10303 adapter = netdev_priv(netdev); 10304 10305 adapter->netdev = netdev; 10306 adapter->pdev = pdev; 10307 hw = &adapter->hw; 10308 hw->back = adapter; 10309 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10310 10311 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10312 pci_resource_len(pdev, 0)); 10313 adapter->io_addr = hw->hw_addr; 10314 if (!hw->hw_addr) { 10315 err = -EIO; 10316 goto err_ioremap; 10317 } 10318 10319 netdev->netdev_ops = &ixgbe_netdev_ops; 10320 ixgbe_set_ethtool_ops(netdev); 10321 netdev->watchdog_timeo = 5 * HZ; 10322 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10323 10324 /* Setup hw api */ 10325 hw->mac.ops = *ii->mac_ops; 10326 hw->mac.type = ii->mac; 10327 hw->mvals = ii->mvals; 10328 if (ii->link_ops) 10329 hw->link.ops = *ii->link_ops; 10330 10331 /* EEPROM */ 10332 hw->eeprom.ops = *ii->eeprom_ops; 10333 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10334 if (ixgbe_removed(hw->hw_addr)) { 10335 err = -EIO; 10336 goto err_ioremap; 10337 } 10338 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10339 if (!(eec & BIT(8))) 10340 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10341 10342 /* PHY */ 10343 hw->phy.ops = *ii->phy_ops; 10344 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10345 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10346 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10347 hw->phy.mdio.mmds = 0; 10348 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10349 hw->phy.mdio.dev = netdev; 10350 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10351 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10352 10353 /* setup the private structure */ 10354 err = ixgbe_sw_init(adapter, ii); 10355 if (err) 10356 goto err_sw_init; 10357 10358 /* Make sure the SWFW semaphore is in a valid state */ 10359 if (hw->mac.ops.init_swfw_sync) 10360 hw->mac.ops.init_swfw_sync(hw); 10361 10362 /* Make it possible the adapter to be woken up via WOL */ 10363 switch (adapter->hw.mac.type) { 10364 case ixgbe_mac_82599EB: 10365 case ixgbe_mac_X540: 10366 case ixgbe_mac_X550: 10367 case ixgbe_mac_X550EM_x: 10368 case ixgbe_mac_x550em_a: 10369 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10370 break; 10371 default: 10372 break; 10373 } 10374 10375 /* 10376 * If there is a fan on this device and it has failed log the 10377 * failure. 10378 */ 10379 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10380 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10381 if (esdp & IXGBE_ESDP_SDP1) 10382 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10383 } 10384 10385 if (allow_unsupported_sfp) 10386 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10387 10388 /* reset_hw fills in the perm_addr as well */ 10389 hw->phy.reset_if_overtemp = true; 10390 err = hw->mac.ops.reset_hw(hw); 10391 hw->phy.reset_if_overtemp = false; 10392 ixgbe_set_eee_capable(adapter); 10393 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10394 err = 0; 10395 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10396 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10397 e_dev_err("Reload the driver after installing a supported module.\n"); 10398 goto err_sw_init; 10399 } else if (err) { 10400 e_dev_err("HW Init failed: %d\n", err); 10401 goto err_sw_init; 10402 } 10403 10404 #ifdef CONFIG_PCI_IOV 10405 /* SR-IOV not supported on the 82598 */ 10406 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10407 goto skip_sriov; 10408 /* Mailbox */ 10409 ixgbe_init_mbx_params_pf(hw); 10410 hw->mbx.ops = ii->mbx_ops; 10411 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10412 ixgbe_enable_sriov(adapter, max_vfs); 10413 skip_sriov: 10414 10415 #endif 10416 netdev->features = NETIF_F_SG | 10417 NETIF_F_TSO | 10418 NETIF_F_TSO6 | 10419 NETIF_F_RXHASH | 10420 NETIF_F_RXCSUM | 10421 NETIF_F_HW_CSUM; 10422 10423 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10424 NETIF_F_GSO_GRE_CSUM | \ 10425 NETIF_F_GSO_IPXIP4 | \ 10426 NETIF_F_GSO_IPXIP6 | \ 10427 NETIF_F_GSO_UDP_TUNNEL | \ 10428 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10429 10430 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10431 netdev->features |= NETIF_F_GSO_PARTIAL | 10432 IXGBE_GSO_PARTIAL_FEATURES; 10433 10434 if (hw->mac.type >= ixgbe_mac_82599EB) 10435 netdev->features |= NETIF_F_SCTP_CRC; 10436 10437 #ifdef CONFIG_XFRM_OFFLOAD 10438 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10439 NETIF_F_HW_ESP_TX_CSUM | \ 10440 NETIF_F_GSO_ESP) 10441 10442 if (adapter->ipsec) 10443 netdev->features |= IXGBE_ESP_FEATURES; 10444 #endif 10445 /* copy netdev features into list of user selectable features */ 10446 netdev->hw_features |= netdev->features | 10447 NETIF_F_HW_VLAN_CTAG_FILTER | 10448 NETIF_F_HW_VLAN_CTAG_RX | 10449 NETIF_F_HW_VLAN_CTAG_TX | 10450 NETIF_F_RXALL | 10451 NETIF_F_HW_L2FW_DOFFLOAD; 10452 10453 if (hw->mac.type >= ixgbe_mac_82599EB) 10454 netdev->hw_features |= NETIF_F_NTUPLE | 10455 NETIF_F_HW_TC; 10456 10457 if (pci_using_dac) 10458 netdev->features |= NETIF_F_HIGHDMA; 10459 10460 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10461 netdev->hw_enc_features |= netdev->vlan_features; 10462 netdev->mpls_features |= NETIF_F_SG | 10463 NETIF_F_TSO | 10464 NETIF_F_TSO6 | 10465 NETIF_F_HW_CSUM; 10466 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10467 10468 /* set this bit last since it cannot be part of vlan_features */ 10469 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10470 NETIF_F_HW_VLAN_CTAG_RX | 10471 NETIF_F_HW_VLAN_CTAG_TX; 10472 10473 netdev->priv_flags |= IFF_UNICAST_FLT; 10474 netdev->priv_flags |= IFF_SUPP_NOFCS; 10475 10476 /* MTU range: 68 - 9710 */ 10477 netdev->min_mtu = ETH_MIN_MTU; 10478 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10479 10480 #ifdef CONFIG_IXGBE_DCB 10481 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10482 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10483 #endif 10484 10485 #ifdef IXGBE_FCOE 10486 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10487 unsigned int fcoe_l; 10488 10489 if (hw->mac.ops.get_device_caps) { 10490 hw->mac.ops.get_device_caps(hw, &device_caps); 10491 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10492 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10493 } 10494 10495 10496 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10497 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10498 10499 netdev->features |= NETIF_F_FSO | 10500 NETIF_F_FCOE_CRC; 10501 10502 netdev->vlan_features |= NETIF_F_FSO | 10503 NETIF_F_FCOE_CRC | 10504 NETIF_F_FCOE_MTU; 10505 } 10506 #endif /* IXGBE_FCOE */ 10507 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10508 netdev->hw_features |= NETIF_F_LRO; 10509 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10510 netdev->features |= NETIF_F_LRO; 10511 10512 /* make sure the EEPROM is good */ 10513 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10514 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10515 err = -EIO; 10516 goto err_sw_init; 10517 } 10518 10519 eth_platform_get_mac_address(&adapter->pdev->dev, 10520 adapter->hw.mac.perm_addr); 10521 10522 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10523 10524 if (!is_valid_ether_addr(netdev->dev_addr)) { 10525 e_dev_err("invalid MAC address\n"); 10526 err = -EIO; 10527 goto err_sw_init; 10528 } 10529 10530 /* Set hw->mac.addr to permanent MAC address */ 10531 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10532 ixgbe_mac_set_default_filter(adapter); 10533 10534 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10535 10536 if (ixgbe_removed(hw->hw_addr)) { 10537 err = -EIO; 10538 goto err_sw_init; 10539 } 10540 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10541 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10542 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10543 10544 err = ixgbe_init_interrupt_scheme(adapter); 10545 if (err) 10546 goto err_sw_init; 10547 10548 for (i = 0; i < adapter->num_rx_queues; i++) 10549 u64_stats_init(&adapter->rx_ring[i]->syncp); 10550 for (i = 0; i < adapter->num_tx_queues; i++) 10551 u64_stats_init(&adapter->tx_ring[i]->syncp); 10552 for (i = 0; i < adapter->num_xdp_queues; i++) 10553 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10554 10555 /* WOL not supported for all devices */ 10556 adapter->wol = 0; 10557 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10558 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10559 pdev->subsystem_device); 10560 if (hw->wol_enabled) 10561 adapter->wol = IXGBE_WUFC_MAG; 10562 10563 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10564 10565 /* save off EEPROM version number */ 10566 ixgbe_set_fw_version(adapter); 10567 10568 /* pick up the PCI bus settings for reporting later */ 10569 if (ixgbe_pcie_from_parent(hw)) 10570 ixgbe_get_parent_bus_info(adapter); 10571 else 10572 hw->mac.ops.get_bus_info(hw); 10573 10574 /* calculate the expected PCIe bandwidth required for optimal 10575 * performance. Note that some older parts will never have enough 10576 * bandwidth due to being older generation PCIe parts. We clamp these 10577 * parts to ensure no warning is displayed if it can't be fixed. 10578 */ 10579 switch (hw->mac.type) { 10580 case ixgbe_mac_82598EB: 10581 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10582 break; 10583 default: 10584 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10585 break; 10586 } 10587 10588 /* don't check link if we failed to enumerate functions */ 10589 if (expected_gts > 0) 10590 ixgbe_check_minimum_link(adapter, expected_gts); 10591 10592 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10593 if (err) 10594 strlcpy(part_str, "Unknown", sizeof(part_str)); 10595 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10596 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10597 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10598 part_str); 10599 else 10600 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10601 hw->mac.type, hw->phy.type, part_str); 10602 10603 e_dev_info("%pM\n", netdev->dev_addr); 10604 10605 /* reset the hardware with the new settings */ 10606 err = hw->mac.ops.start_hw(hw); 10607 if (err == IXGBE_ERR_EEPROM_VERSION) { 10608 /* We are running on a pre-production device, log a warning */ 10609 e_dev_warn("This device is a pre-production adapter/LOM. " 10610 "Please be aware there may be issues associated " 10611 "with your hardware. If you are experiencing " 10612 "problems please contact your Intel or hardware " 10613 "representative who provided you with this " 10614 "hardware.\n"); 10615 } 10616 strcpy(netdev->name, "eth%d"); 10617 pci_set_drvdata(pdev, adapter); 10618 err = register_netdev(netdev); 10619 if (err) 10620 goto err_register; 10621 10622 10623 /* power down the optics for 82599 SFP+ fiber */ 10624 if (hw->mac.ops.disable_tx_laser) 10625 hw->mac.ops.disable_tx_laser(hw); 10626 10627 /* carrier off reporting is important to ethtool even BEFORE open */ 10628 netif_carrier_off(netdev); 10629 10630 #ifdef CONFIG_IXGBE_DCA 10631 if (dca_add_requester(&pdev->dev) == 0) { 10632 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10633 ixgbe_setup_dca(adapter); 10634 } 10635 #endif 10636 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10637 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10638 for (i = 0; i < adapter->num_vfs; i++) 10639 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10640 } 10641 10642 /* firmware requires driver version to be 0xFFFFFFFF 10643 * since os does not support feature 10644 */ 10645 if (hw->mac.ops.set_fw_drv_ver) 10646 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10647 sizeof(ixgbe_driver_version) - 1, 10648 ixgbe_driver_version); 10649 10650 /* add san mac addr to netdev */ 10651 ixgbe_add_sanmac_netdev(netdev); 10652 10653 e_dev_info("%s\n", ixgbe_default_device_descr); 10654 10655 #ifdef CONFIG_IXGBE_HWMON 10656 if (ixgbe_sysfs_init(adapter)) 10657 e_err(probe, "failed to allocate sysfs resources\n"); 10658 #endif /* CONFIG_IXGBE_HWMON */ 10659 10660 ixgbe_dbg_adapter_init(adapter); 10661 10662 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10663 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10664 hw->mac.ops.setup_link(hw, 10665 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10666 true); 10667 10668 return 0; 10669 10670 err_register: 10671 ixgbe_release_hw_control(adapter); 10672 ixgbe_clear_interrupt_scheme(adapter); 10673 err_sw_init: 10674 ixgbe_disable_sriov(adapter); 10675 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10676 iounmap(adapter->io_addr); 10677 kfree(adapter->jump_tables[0]); 10678 kfree(adapter->mac_table); 10679 kfree(adapter->rss_key); 10680 err_ioremap: 10681 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10682 free_netdev(netdev); 10683 err_alloc_etherdev: 10684 pci_release_mem_regions(pdev); 10685 err_pci_reg: 10686 err_dma: 10687 if (!adapter || disable_dev) 10688 pci_disable_device(pdev); 10689 return err; 10690 } 10691 10692 /** 10693 * ixgbe_remove - Device Removal Routine 10694 * @pdev: PCI device information struct 10695 * 10696 * ixgbe_remove is called by the PCI subsystem to alert the driver 10697 * that it should release a PCI device. The could be caused by a 10698 * Hot-Plug event, or because the driver is going to be removed from 10699 * memory. 10700 **/ 10701 static void ixgbe_remove(struct pci_dev *pdev) 10702 { 10703 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10704 struct net_device *netdev; 10705 bool disable_dev; 10706 int i; 10707 10708 /* if !adapter then we already cleaned up in probe */ 10709 if (!adapter) 10710 return; 10711 10712 netdev = adapter->netdev; 10713 ixgbe_dbg_adapter_exit(adapter); 10714 10715 set_bit(__IXGBE_REMOVING, &adapter->state); 10716 cancel_work_sync(&adapter->service_task); 10717 10718 10719 #ifdef CONFIG_IXGBE_DCA 10720 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10721 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10722 dca_remove_requester(&pdev->dev); 10723 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10724 IXGBE_DCA_CTRL_DCA_DISABLE); 10725 } 10726 10727 #endif 10728 #ifdef CONFIG_IXGBE_HWMON 10729 ixgbe_sysfs_exit(adapter); 10730 #endif /* CONFIG_IXGBE_HWMON */ 10731 10732 /* remove the added san mac */ 10733 ixgbe_del_sanmac_netdev(netdev); 10734 10735 #ifdef CONFIG_PCI_IOV 10736 ixgbe_disable_sriov(adapter); 10737 #endif 10738 if (netdev->reg_state == NETREG_REGISTERED) 10739 unregister_netdev(netdev); 10740 10741 ixgbe_stop_ipsec_offload(adapter); 10742 ixgbe_clear_interrupt_scheme(adapter); 10743 10744 ixgbe_release_hw_control(adapter); 10745 10746 #ifdef CONFIG_DCB 10747 kfree(adapter->ixgbe_ieee_pfc); 10748 kfree(adapter->ixgbe_ieee_ets); 10749 10750 #endif 10751 iounmap(adapter->io_addr); 10752 pci_release_mem_regions(pdev); 10753 10754 e_dev_info("complete\n"); 10755 10756 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10757 if (adapter->jump_tables[i]) { 10758 kfree(adapter->jump_tables[i]->input); 10759 kfree(adapter->jump_tables[i]->mask); 10760 } 10761 kfree(adapter->jump_tables[i]); 10762 } 10763 10764 kfree(adapter->mac_table); 10765 kfree(adapter->rss_key); 10766 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10767 free_netdev(netdev); 10768 10769 pci_disable_pcie_error_reporting(pdev); 10770 10771 if (disable_dev) 10772 pci_disable_device(pdev); 10773 } 10774 10775 /** 10776 * ixgbe_io_error_detected - called when PCI error is detected 10777 * @pdev: Pointer to PCI device 10778 * @state: The current pci connection state 10779 * 10780 * This function is called after a PCI bus error affecting 10781 * this device has been detected. 10782 */ 10783 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10784 pci_channel_state_t state) 10785 { 10786 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10787 struct net_device *netdev = adapter->netdev; 10788 10789 #ifdef CONFIG_PCI_IOV 10790 struct ixgbe_hw *hw = &adapter->hw; 10791 struct pci_dev *bdev, *vfdev; 10792 u32 dw0, dw1, dw2, dw3; 10793 int vf, pos; 10794 u16 req_id, pf_func; 10795 10796 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10797 adapter->num_vfs == 0) 10798 goto skip_bad_vf_detection; 10799 10800 bdev = pdev->bus->self; 10801 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10802 bdev = bdev->bus->self; 10803 10804 if (!bdev) 10805 goto skip_bad_vf_detection; 10806 10807 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10808 if (!pos) 10809 goto skip_bad_vf_detection; 10810 10811 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10812 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10813 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10814 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10815 if (ixgbe_removed(hw->hw_addr)) 10816 goto skip_bad_vf_detection; 10817 10818 req_id = dw1 >> 16; 10819 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10820 if (!(req_id & 0x0080)) 10821 goto skip_bad_vf_detection; 10822 10823 pf_func = req_id & 0x01; 10824 if ((pf_func & 1) == (pdev->devfn & 1)) { 10825 unsigned int device_id; 10826 10827 vf = (req_id & 0x7F) >> 1; 10828 e_dev_err("VF %d has caused a PCIe error\n", vf); 10829 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10830 "%8.8x\tdw3: %8.8x\n", 10831 dw0, dw1, dw2, dw3); 10832 switch (adapter->hw.mac.type) { 10833 case ixgbe_mac_82599EB: 10834 device_id = IXGBE_82599_VF_DEVICE_ID; 10835 break; 10836 case ixgbe_mac_X540: 10837 device_id = IXGBE_X540_VF_DEVICE_ID; 10838 break; 10839 case ixgbe_mac_X550: 10840 device_id = IXGBE_DEV_ID_X550_VF; 10841 break; 10842 case ixgbe_mac_X550EM_x: 10843 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10844 break; 10845 case ixgbe_mac_x550em_a: 10846 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10847 break; 10848 default: 10849 device_id = 0; 10850 break; 10851 } 10852 10853 /* Find the pci device of the offending VF */ 10854 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10855 while (vfdev) { 10856 if (vfdev->devfn == (req_id & 0xFF)) 10857 break; 10858 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10859 device_id, vfdev); 10860 } 10861 /* 10862 * There's a slim chance the VF could have been hot plugged, 10863 * so if it is no longer present we don't need to issue the 10864 * VFLR. Just clean up the AER in that case. 10865 */ 10866 if (vfdev) { 10867 pcie_flr(vfdev); 10868 /* Free device reference count */ 10869 pci_dev_put(vfdev); 10870 } 10871 10872 pci_cleanup_aer_uncorrect_error_status(pdev); 10873 } 10874 10875 /* 10876 * Even though the error may have occurred on the other port 10877 * we still need to increment the vf error reference count for 10878 * both ports because the I/O resume function will be called 10879 * for both of them. 10880 */ 10881 adapter->vferr_refcount++; 10882 10883 return PCI_ERS_RESULT_RECOVERED; 10884 10885 skip_bad_vf_detection: 10886 #endif /* CONFIG_PCI_IOV */ 10887 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10888 return PCI_ERS_RESULT_DISCONNECT; 10889 10890 if (!netif_device_present(netdev)) 10891 return PCI_ERS_RESULT_DISCONNECT; 10892 10893 rtnl_lock(); 10894 netif_device_detach(netdev); 10895 10896 if (netif_running(netdev)) 10897 ixgbe_close_suspend(adapter); 10898 10899 if (state == pci_channel_io_perm_failure) { 10900 rtnl_unlock(); 10901 return PCI_ERS_RESULT_DISCONNECT; 10902 } 10903 10904 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10905 pci_disable_device(pdev); 10906 rtnl_unlock(); 10907 10908 /* Request a slot reset. */ 10909 return PCI_ERS_RESULT_NEED_RESET; 10910 } 10911 10912 /** 10913 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10914 * @pdev: Pointer to PCI device 10915 * 10916 * Restart the card from scratch, as if from a cold-boot. 10917 */ 10918 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10919 { 10920 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10921 pci_ers_result_t result; 10922 int err; 10923 10924 if (pci_enable_device_mem(pdev)) { 10925 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10926 result = PCI_ERS_RESULT_DISCONNECT; 10927 } else { 10928 smp_mb__before_atomic(); 10929 clear_bit(__IXGBE_DISABLED, &adapter->state); 10930 adapter->hw.hw_addr = adapter->io_addr; 10931 pci_set_master(pdev); 10932 pci_restore_state(pdev); 10933 pci_save_state(pdev); 10934 10935 pci_wake_from_d3(pdev, false); 10936 10937 ixgbe_reset(adapter); 10938 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10939 result = PCI_ERS_RESULT_RECOVERED; 10940 } 10941 10942 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10943 if (err) { 10944 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10945 "failed 0x%0x\n", err); 10946 /* non-fatal, continue */ 10947 } 10948 10949 return result; 10950 } 10951 10952 /** 10953 * ixgbe_io_resume - called when traffic can start flowing again. 10954 * @pdev: Pointer to PCI device 10955 * 10956 * This callback is called when the error recovery driver tells us that 10957 * its OK to resume normal operation. 10958 */ 10959 static void ixgbe_io_resume(struct pci_dev *pdev) 10960 { 10961 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10962 struct net_device *netdev = adapter->netdev; 10963 10964 #ifdef CONFIG_PCI_IOV 10965 if (adapter->vferr_refcount) { 10966 e_info(drv, "Resuming after VF err\n"); 10967 adapter->vferr_refcount--; 10968 return; 10969 } 10970 10971 #endif 10972 rtnl_lock(); 10973 if (netif_running(netdev)) 10974 ixgbe_open(netdev); 10975 10976 netif_device_attach(netdev); 10977 rtnl_unlock(); 10978 } 10979 10980 static const struct pci_error_handlers ixgbe_err_handler = { 10981 .error_detected = ixgbe_io_error_detected, 10982 .slot_reset = ixgbe_io_slot_reset, 10983 .resume = ixgbe_io_resume, 10984 }; 10985 10986 static struct pci_driver ixgbe_driver = { 10987 .name = ixgbe_driver_name, 10988 .id_table = ixgbe_pci_tbl, 10989 .probe = ixgbe_probe, 10990 .remove = ixgbe_remove, 10991 #ifdef CONFIG_PM 10992 .suspend = ixgbe_suspend, 10993 .resume = ixgbe_resume, 10994 #endif 10995 .shutdown = ixgbe_shutdown, 10996 .sriov_configure = ixgbe_pci_sriov_configure, 10997 .err_handler = &ixgbe_err_handler 10998 }; 10999 11000 /** 11001 * ixgbe_init_module - Driver Registration Routine 11002 * 11003 * ixgbe_init_module is the first routine called when the driver is 11004 * loaded. All it does is register with the PCI subsystem. 11005 **/ 11006 static int __init ixgbe_init_module(void) 11007 { 11008 int ret; 11009 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11010 pr_info("%s\n", ixgbe_copyright); 11011 11012 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11013 if (!ixgbe_wq) { 11014 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11015 return -ENOMEM; 11016 } 11017 11018 ixgbe_dbg_init(); 11019 11020 ret = pci_register_driver(&ixgbe_driver); 11021 if (ret) { 11022 destroy_workqueue(ixgbe_wq); 11023 ixgbe_dbg_exit(); 11024 return ret; 11025 } 11026 11027 #ifdef CONFIG_IXGBE_DCA 11028 dca_register_notify(&dca_notifier); 11029 #endif 11030 11031 return 0; 11032 } 11033 11034 module_init(ixgbe_init_module); 11035 11036 /** 11037 * ixgbe_exit_module - Driver Exit Cleanup Routine 11038 * 11039 * ixgbe_exit_module is called just before the driver is removed 11040 * from memory. 11041 **/ 11042 static void __exit ixgbe_exit_module(void) 11043 { 11044 #ifdef CONFIG_IXGBE_DCA 11045 dca_unregister_notify(&dca_notifier); 11046 #endif 11047 pci_unregister_driver(&ixgbe_driver); 11048 11049 ixgbe_dbg_exit(); 11050 if (ixgbe_wq) { 11051 destroy_workqueue(ixgbe_wq); 11052 ixgbe_wq = NULL; 11053 } 11054 } 11055 11056 #ifdef CONFIG_IXGBE_DCA 11057 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11058 void *p) 11059 { 11060 int ret_val; 11061 11062 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11063 __ixgbe_notify_dca); 11064 11065 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11066 } 11067 11068 #endif /* CONFIG_IXGBE_DCA */ 11069 11070 module_exit(ixgbe_exit_module); 11071 11072 /* ixgbe_main.c */ 11073