1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <scsi/fc/fc_fcoe.h> 31 #include <net/udp_tunnel.h> 32 #include <net/pkt_cls.h> 33 #include <net/tc_act/tc_gact.h> 34 #include <net/tc_act/tc_mirred.h> 35 #include <net/vxlan.h> 36 #include <net/mpls.h> 37 #include <net/xdp_sock.h> 38 39 #include "ixgbe.h" 40 #include "ixgbe_common.h" 41 #include "ixgbe_dcb_82599.h" 42 #include "ixgbe_phy.h" 43 #include "ixgbe_sriov.h" 44 #include "ixgbe_model.h" 45 #include "ixgbe_txrx_common.h" 46 47 char ixgbe_driver_name[] = "ixgbe"; 48 static const char ixgbe_driver_string[] = 49 "Intel(R) 10 Gigabit PCI Express Network Driver"; 50 #ifdef IXGBE_FCOE 51 char ixgbe_default_device_descr[] = 52 "Intel(R) 10 Gigabit Network Connection"; 53 #else 54 static char ixgbe_default_device_descr[] = 55 "Intel(R) 10 Gigabit Network Connection"; 56 #endif 57 #define DRV_VERSION "5.1.0-k" 58 const char ixgbe_driver_version[] = DRV_VERSION; 59 static const char ixgbe_copyright[] = 60 "Copyright (c) 1999-2016 Intel Corporation."; 61 62 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 63 64 static const struct ixgbe_info *ixgbe_info_tbl[] = { 65 [board_82598] = &ixgbe_82598_info, 66 [board_82599] = &ixgbe_82599_info, 67 [board_X540] = &ixgbe_X540_info, 68 [board_X550] = &ixgbe_X550_info, 69 [board_X550EM_x] = &ixgbe_X550EM_x_info, 70 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 71 [board_x550em_a] = &ixgbe_x550em_a_info, 72 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 73 }; 74 75 /* ixgbe_pci_tbl - PCI Device ID Table 76 * 77 * Wildcard entries (PCI_ANY_ID) should come last 78 * Last entry must be all 0s 79 * 80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 81 * Class, Class Mask, private data (not used) } 82 */ 83 static const struct pci_device_id ixgbe_pci_tbl[] = { 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 131 /* required last entry */ 132 {0, } 133 }; 134 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 135 136 #ifdef CONFIG_IXGBE_DCA 137 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 138 void *p); 139 static struct notifier_block dca_notifier = { 140 .notifier_call = ixgbe_notify_dca, 141 .next = NULL, 142 .priority = 0 143 }; 144 #endif 145 146 #ifdef CONFIG_PCI_IOV 147 static unsigned int max_vfs; 148 module_param(max_vfs, uint, 0); 149 MODULE_PARM_DESC(max_vfs, 150 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 151 #endif /* CONFIG_PCI_IOV */ 152 153 static unsigned int allow_unsupported_sfp; 154 module_param(allow_unsupported_sfp, uint, 0); 155 MODULE_PARM_DESC(allow_unsupported_sfp, 156 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 157 158 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 159 static int debug = -1; 160 module_param(debug, int, 0); 161 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 162 163 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 164 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 165 MODULE_LICENSE("GPL v2"); 166 MODULE_VERSION(DRV_VERSION); 167 168 static struct workqueue_struct *ixgbe_wq; 169 170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 171 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 172 173 static const struct net_device_ops ixgbe_netdev_ops; 174 175 static bool netif_is_ixgbe(struct net_device *dev) 176 { 177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 178 } 179 180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 181 u32 reg, u16 *value) 182 { 183 struct pci_dev *parent_dev; 184 struct pci_bus *parent_bus; 185 186 parent_bus = adapter->pdev->bus->parent; 187 if (!parent_bus) 188 return -1; 189 190 parent_dev = parent_bus->self; 191 if (!parent_dev) 192 return -1; 193 194 if (!pci_is_pcie(parent_dev)) 195 return -1; 196 197 pcie_capability_read_word(parent_dev, reg, value); 198 if (*value == IXGBE_FAILED_READ_CFG_WORD && 199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 200 return -1; 201 return 0; 202 } 203 204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 205 { 206 struct ixgbe_hw *hw = &adapter->hw; 207 u16 link_status = 0; 208 int err; 209 210 hw->bus.type = ixgbe_bus_type_pci_express; 211 212 /* Get the negotiated link width and speed from PCI config space of the 213 * parent, as this device is behind a switch 214 */ 215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 216 217 /* assume caller will handle error case */ 218 if (err) 219 return err; 220 221 hw->bus.width = ixgbe_convert_bus_width(link_status); 222 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 223 224 return 0; 225 } 226 227 /** 228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 229 * @hw: hw specific details 230 * 231 * This function is used by probe to determine whether a device's PCI-Express 232 * bandwidth details should be gathered from the parent bus instead of from the 233 * device. Used to ensure that various locations all have the correct device ID 234 * checks. 235 */ 236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 237 { 238 switch (hw->device_id) { 239 case IXGBE_DEV_ID_82599_SFP_SF_QP: 240 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 241 return true; 242 default: 243 return false; 244 } 245 } 246 247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 248 int expected_gts) 249 { 250 struct ixgbe_hw *hw = &adapter->hw; 251 struct pci_dev *pdev; 252 253 /* Some devices are not connected over PCIe and thus do not negotiate 254 * speed. These devices do not have valid bus info, and thus any report 255 * we generate may not be correct. 256 */ 257 if (hw->bus.type == ixgbe_bus_type_internal) 258 return; 259 260 /* determine whether to use the parent device */ 261 if (ixgbe_pcie_from_parent(&adapter->hw)) 262 pdev = adapter->pdev->bus->parent->self; 263 else 264 pdev = adapter->pdev; 265 266 pcie_print_link_status(pdev); 267 } 268 269 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 270 { 271 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 272 !test_bit(__IXGBE_REMOVING, &adapter->state) && 273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 274 queue_work(ixgbe_wq, &adapter->service_task); 275 } 276 277 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 278 { 279 struct ixgbe_adapter *adapter = hw->back; 280 281 if (!hw->hw_addr) 282 return; 283 hw->hw_addr = NULL; 284 e_dev_err("Adapter removed\n"); 285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 286 ixgbe_service_event_schedule(adapter); 287 } 288 289 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 290 { 291 u8 __iomem *reg_addr; 292 u32 value; 293 int i; 294 295 reg_addr = READ_ONCE(hw->hw_addr); 296 if (ixgbe_removed(reg_addr)) 297 return IXGBE_FAILED_READ_REG; 298 299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 300 * so perform several status register reads to determine if the adapter 301 * has been removed. 302 */ 303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 304 value = readl(reg_addr + IXGBE_STATUS); 305 if (value != IXGBE_FAILED_READ_REG) 306 break; 307 mdelay(3); 308 } 309 310 if (value == IXGBE_FAILED_READ_REG) 311 ixgbe_remove_adapter(hw); 312 else 313 value = readl(reg_addr + reg); 314 return value; 315 } 316 317 /** 318 * ixgbe_read_reg - Read from device register 319 * @hw: hw specific details 320 * @reg: offset of register to read 321 * 322 * Returns : value read or IXGBE_FAILED_READ_REG if removed 323 * 324 * This function is used to read device registers. It checks for device 325 * removal by confirming any read that returns all ones by checking the 326 * status register value for all ones. This function avoids reading from 327 * the hardware if a removal was previously detected in which case it 328 * returns IXGBE_FAILED_READ_REG (all ones). 329 */ 330 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 331 { 332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 333 u32 value; 334 335 if (ixgbe_removed(reg_addr)) 336 return IXGBE_FAILED_READ_REG; 337 if (unlikely(hw->phy.nw_mng_if_sel & 338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 339 struct ixgbe_adapter *adapter; 340 int i; 341 342 for (i = 0; i < 200; ++i) { 343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 344 if (likely(!value)) 345 goto writes_completed; 346 if (value == IXGBE_FAILED_READ_REG) { 347 ixgbe_remove_adapter(hw); 348 return IXGBE_FAILED_READ_REG; 349 } 350 udelay(5); 351 } 352 353 adapter = hw->back; 354 e_warn(hw, "register writes incomplete %08x\n", value); 355 } 356 357 writes_completed: 358 value = readl(reg_addr + reg); 359 if (unlikely(value == IXGBE_FAILED_READ_REG)) 360 value = ixgbe_check_remove(hw, reg); 361 return value; 362 } 363 364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 365 { 366 u16 value; 367 368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 369 if (value == IXGBE_FAILED_READ_CFG_WORD) { 370 ixgbe_remove_adapter(hw); 371 return true; 372 } 373 return false; 374 } 375 376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 377 { 378 struct ixgbe_adapter *adapter = hw->back; 379 u16 value; 380 381 if (ixgbe_removed(hw->hw_addr)) 382 return IXGBE_FAILED_READ_CFG_WORD; 383 pci_read_config_word(adapter->pdev, reg, &value); 384 if (value == IXGBE_FAILED_READ_CFG_WORD && 385 ixgbe_check_cfg_remove(hw, adapter->pdev)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 return value; 388 } 389 390 #ifdef CONFIG_PCI_IOV 391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 392 { 393 struct ixgbe_adapter *adapter = hw->back; 394 u32 value; 395 396 if (ixgbe_removed(hw->hw_addr)) 397 return IXGBE_FAILED_READ_CFG_DWORD; 398 pci_read_config_dword(adapter->pdev, reg, &value); 399 if (value == IXGBE_FAILED_READ_CFG_DWORD && 400 ixgbe_check_cfg_remove(hw, adapter->pdev)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 return value; 403 } 404 #endif /* CONFIG_PCI_IOV */ 405 406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 407 { 408 struct ixgbe_adapter *adapter = hw->back; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return; 412 pci_write_config_word(adapter->pdev, reg, value); 413 } 414 415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 416 { 417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 418 419 /* flush memory to make sure state is correct before next watchdog */ 420 smp_mb__before_atomic(); 421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 422 } 423 424 struct ixgbe_reg_info { 425 u32 ofs; 426 char *name; 427 }; 428 429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 430 431 /* General Registers */ 432 {IXGBE_CTRL, "CTRL"}, 433 {IXGBE_STATUS, "STATUS"}, 434 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 435 436 /* Interrupt Registers */ 437 {IXGBE_EICR, "EICR"}, 438 439 /* RX Registers */ 440 {IXGBE_SRRCTL(0), "SRRCTL"}, 441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 442 {IXGBE_RDLEN(0), "RDLEN"}, 443 {IXGBE_RDH(0), "RDH"}, 444 {IXGBE_RDT(0), "RDT"}, 445 {IXGBE_RXDCTL(0), "RXDCTL"}, 446 {IXGBE_RDBAL(0), "RDBAL"}, 447 {IXGBE_RDBAH(0), "RDBAH"}, 448 449 /* TX Registers */ 450 {IXGBE_TDBAL(0), "TDBAL"}, 451 {IXGBE_TDBAH(0), "TDBAH"}, 452 {IXGBE_TDLEN(0), "TDLEN"}, 453 {IXGBE_TDH(0), "TDH"}, 454 {IXGBE_TDT(0), "TDT"}, 455 {IXGBE_TXDCTL(0), "TXDCTL"}, 456 457 /* List Terminator */ 458 { .name = NULL } 459 }; 460 461 462 /* 463 * ixgbe_regdump - register printout routine 464 */ 465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 466 { 467 int i; 468 char rname[16]; 469 u32 regs[64]; 470 471 switch (reginfo->ofs) { 472 case IXGBE_SRRCTL(0): 473 for (i = 0; i < 64; i++) 474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 475 break; 476 case IXGBE_DCA_RXCTRL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 479 break; 480 case IXGBE_RDLEN(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 483 break; 484 case IXGBE_RDH(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 487 break; 488 case IXGBE_RDT(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 491 break; 492 case IXGBE_RXDCTL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 495 break; 496 case IXGBE_RDBAL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 499 break; 500 case IXGBE_RDBAH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 503 break; 504 case IXGBE_TDBAL(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 507 break; 508 case IXGBE_TDBAH(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 511 break; 512 case IXGBE_TDLEN(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 515 break; 516 case IXGBE_TDH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 519 break; 520 case IXGBE_TDT(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 523 break; 524 case IXGBE_TXDCTL(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 527 break; 528 default: 529 pr_info("%-15s %08x\n", 530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 531 return; 532 } 533 534 i = 0; 535 while (i < 64) { 536 int j; 537 char buf[9 * 8 + 1]; 538 char *p = buf; 539 540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 541 for (j = 0; j < 8; j++) 542 p += sprintf(p, " %08x", regs[i++]); 543 pr_err("%-15s%s\n", rname, buf); 544 } 545 546 } 547 548 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 549 { 550 struct ixgbe_tx_buffer *tx_buffer; 551 552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 554 n, ring->next_to_use, ring->next_to_clean, 555 (u64)dma_unmap_addr(tx_buffer, dma), 556 dma_unmap_len(tx_buffer, len), 557 tx_buffer->next_to_watch, 558 (u64)tx_buffer->time_stamp); 559 } 560 561 /* 562 * ixgbe_dump - Print registers, tx-rings and rx-rings 563 */ 564 static void ixgbe_dump(struct ixgbe_adapter *adapter) 565 { 566 struct net_device *netdev = adapter->netdev; 567 struct ixgbe_hw *hw = &adapter->hw; 568 struct ixgbe_reg_info *reginfo; 569 int n = 0; 570 struct ixgbe_ring *ring; 571 struct ixgbe_tx_buffer *tx_buffer; 572 union ixgbe_adv_tx_desc *tx_desc; 573 struct my_u0 { u64 a; u64 b; } *u0; 574 struct ixgbe_ring *rx_ring; 575 union ixgbe_adv_rx_desc *rx_desc; 576 struct ixgbe_rx_buffer *rx_buffer_info; 577 int i = 0; 578 579 if (!netif_msg_hw(adapter)) 580 return; 581 582 /* Print netdevice Info */ 583 if (netdev) { 584 dev_info(&adapter->pdev->dev, "Net device Info\n"); 585 pr_info("Device Name state " 586 "trans_start\n"); 587 pr_info("%-15s %016lX %016lX\n", 588 netdev->name, 589 netdev->state, 590 dev_trans_start(netdev)); 591 } 592 593 /* Print Registers */ 594 dev_info(&adapter->pdev->dev, "Register Dump\n"); 595 pr_info(" Register Name Value\n"); 596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 597 reginfo->name; reginfo++) { 598 ixgbe_regdump(hw, reginfo); 599 } 600 601 /* Print TX Ring Summary */ 602 if (!netdev || !netif_running(netdev)) 603 return; 604 605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 606 pr_info(" %s %s %s %s\n", 607 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 608 "leng", "ntw", "timestamp"); 609 for (n = 0; n < adapter->num_tx_queues; n++) { 610 ring = adapter->tx_ring[n]; 611 ixgbe_print_buffer(ring, n); 612 } 613 614 for (n = 0; n < adapter->num_xdp_queues; n++) { 615 ring = adapter->xdp_ring[n]; 616 ixgbe_print_buffer(ring, n); 617 } 618 619 /* Print TX Rings */ 620 if (!netif_msg_tx_done(adapter)) 621 goto rx_ring_summary; 622 623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 624 625 /* Transmit Descriptor Formats 626 * 627 * 82598 Advanced Transmit Descriptor 628 * +--------------------------------------------------------------+ 629 * 0 | Buffer Address [63:0] | 630 * +--------------------------------------------------------------+ 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 632 * +--------------------------------------------------------------+ 633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 634 * 635 * 82598 Advanced Transmit Descriptor (Write-Back Format) 636 * +--------------------------------------------------------------+ 637 * 0 | RSV [63:0] | 638 * +--------------------------------------------------------------+ 639 * 8 | RSV | STA | NXTSEQ | 640 * +--------------------------------------------------------------+ 641 * 63 36 35 32 31 0 642 * 643 * 82599+ Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 650 * 651 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | RSV | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 */ 659 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 ring = adapter->tx_ring[n]; 662 pr_info("------------------------------------\n"); 663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 664 pr_info("------------------------------------\n"); 665 pr_info("%s%s %s %s %s %s\n", 666 "T [desc] [address 63:0 ] ", 667 "[PlPOIdStDDt Ln] [bi->dma ] ", 668 "leng", "ntw", "timestamp", "bi->skb"); 669 670 for (i = 0; ring->desc && (i < ring->count); i++) { 671 tx_desc = IXGBE_TX_DESC(ring, i); 672 tx_buffer = &ring->tx_buffer_info[i]; 673 u0 = (struct my_u0 *)tx_desc; 674 if (dma_unmap_len(tx_buffer, len) > 0) { 675 const char *ring_desc; 676 677 if (i == ring->next_to_use && 678 i == ring->next_to_clean) 679 ring_desc = " NTC/U"; 680 else if (i == ring->next_to_use) 681 ring_desc = " NTU"; 682 else if (i == ring->next_to_clean) 683 ring_desc = " NTC"; 684 else 685 ring_desc = ""; 686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 687 i, 688 le64_to_cpu((__force __le64)u0->a), 689 le64_to_cpu((__force __le64)u0->b), 690 (u64)dma_unmap_addr(tx_buffer, dma), 691 dma_unmap_len(tx_buffer, len), 692 tx_buffer->next_to_watch, 693 (u64)tx_buffer->time_stamp, 694 tx_buffer->skb, 695 ring_desc); 696 697 if (netif_msg_pktdata(adapter) && 698 tx_buffer->skb) 699 print_hex_dump(KERN_INFO, "", 700 DUMP_PREFIX_ADDRESS, 16, 1, 701 tx_buffer->skb->data, 702 dma_unmap_len(tx_buffer, len), 703 true); 704 } 705 } 706 } 707 708 /* Print RX Rings Summary */ 709 rx_ring_summary: 710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 711 pr_info("Queue [NTU] [NTC]\n"); 712 for (n = 0; n < adapter->num_rx_queues; n++) { 713 rx_ring = adapter->rx_ring[n]; 714 pr_info("%5d %5X %5X\n", 715 n, rx_ring->next_to_use, rx_ring->next_to_clean); 716 } 717 718 /* Print RX Rings */ 719 if (!netif_msg_rx_status(adapter)) 720 return; 721 722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 723 724 /* Receive Descriptor Formats 725 * 726 * 82598 Advanced Receive Descriptor (Read) Format 727 * 63 1 0 728 * +-----------------------------------------------------+ 729 * 0 | Packet Buffer Address [63:1] |A0/NSE| 730 * +----------------------------------------------+------+ 731 * 8 | Header Buffer Address [63:1] | DD | 732 * +-----------------------------------------------------+ 733 * 734 * 735 * 82598 Advanced Receive Descriptor (Write-Back) Format 736 * 737 * 63 48 47 32 31 30 21 20 16 15 4 3 0 738 * +------------------------------------------------------+ 739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 740 * | Packet | IP | | | | Type | Type | 741 * | Checksum | Ident | | | | | | 742 * +------------------------------------------------------+ 743 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 744 * +------------------------------------------------------+ 745 * 63 48 47 32 31 20 19 0 746 * 747 * 82599+ Advanced Receive Descriptor (Read) Format 748 * 63 1 0 749 * +-----------------------------------------------------+ 750 * 0 | Packet Buffer Address [63:1] |A0/NSE| 751 * +----------------------------------------------+------+ 752 * 8 | Header Buffer Address [63:1] | DD | 753 * +-----------------------------------------------------+ 754 * 755 * 756 * 82599+ Advanced Receive Descriptor (Write-Back) Format 757 * 758 * 63 48 47 32 31 30 21 20 17 16 4 3 0 759 * +------------------------------------------------------+ 760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 762 * |/ Flow Dir Flt ID | | | | | | 763 * +------------------------------------------------------+ 764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 765 * +------------------------------------------------------+ 766 * 63 48 47 32 31 20 19 0 767 */ 768 769 for (n = 0; n < adapter->num_rx_queues; n++) { 770 rx_ring = adapter->rx_ring[n]; 771 pr_info("------------------------------------\n"); 772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 773 pr_info("------------------------------------\n"); 774 pr_info("%s%s%s\n", 775 "R [desc] [ PktBuf A0] ", 776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 777 "<-- Adv Rx Read format"); 778 pr_info("%s%s%s\n", 779 "RWB[desc] [PcsmIpSHl PtRs] ", 780 "[vl er S cks ln] ---------------- [bi->skb ] ", 781 "<-- Adv Rx Write-Back format"); 782 783 for (i = 0; i < rx_ring->count; i++) { 784 const char *ring_desc; 785 786 if (i == rx_ring->next_to_use) 787 ring_desc = " NTU"; 788 else if (i == rx_ring->next_to_clean) 789 ring_desc = " NTC"; 790 else 791 ring_desc = ""; 792 793 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 794 rx_desc = IXGBE_RX_DESC(rx_ring, i); 795 u0 = (struct my_u0 *)rx_desc; 796 if (rx_desc->wb.upper.length) { 797 /* Descriptor Done */ 798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 799 i, 800 le64_to_cpu((__force __le64)u0->a), 801 le64_to_cpu((__force __le64)u0->b), 802 rx_buffer_info->skb, 803 ring_desc); 804 } else { 805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 806 i, 807 le64_to_cpu((__force __le64)u0->a), 808 le64_to_cpu((__force __le64)u0->b), 809 (u64)rx_buffer_info->dma, 810 rx_buffer_info->skb, 811 ring_desc); 812 813 if (netif_msg_pktdata(adapter) && 814 rx_buffer_info->dma) { 815 print_hex_dump(KERN_INFO, "", 816 DUMP_PREFIX_ADDRESS, 16, 1, 817 page_address(rx_buffer_info->page) + 818 rx_buffer_info->page_offset, 819 ixgbe_rx_bufsz(rx_ring), true); 820 } 821 } 822 } 823 } 824 } 825 826 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 827 { 828 u32 ctrl_ext; 829 830 /* Let firmware take over control of h/w */ 831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 834 } 835 836 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 837 { 838 u32 ctrl_ext; 839 840 /* Let firmware know the driver has taken over */ 841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 844 } 845 846 /** 847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 848 * @adapter: pointer to adapter struct 849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 850 * @queue: queue to map the corresponding interrupt to 851 * @msix_vector: the vector to map to the corresponding queue 852 * 853 */ 854 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 855 u8 queue, u8 msix_vector) 856 { 857 u32 ivar, index; 858 struct ixgbe_hw *hw = &adapter->hw; 859 switch (hw->mac.type) { 860 case ixgbe_mac_82598EB: 861 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 862 if (direction == -1) 863 direction = 0; 864 index = (((direction * 64) + queue) >> 2) & 0x1F; 865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 866 ivar &= ~(0xFF << (8 * (queue & 0x3))); 867 ivar |= (msix_vector << (8 * (queue & 0x3))); 868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 869 break; 870 case ixgbe_mac_82599EB: 871 case ixgbe_mac_X540: 872 case ixgbe_mac_X550: 873 case ixgbe_mac_X550EM_x: 874 case ixgbe_mac_x550em_a: 875 if (direction == -1) { 876 /* other causes */ 877 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 878 index = ((queue & 1) * 8); 879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 880 ivar &= ~(0xFF << index); 881 ivar |= (msix_vector << index); 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 883 break; 884 } else { 885 /* tx or rx causes */ 886 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 887 index = ((16 * (queue & 1)) + (8 * direction)); 888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 889 ivar &= ~(0xFF << index); 890 ivar |= (msix_vector << index); 891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 892 break; 893 } 894 default: 895 break; 896 } 897 } 898 899 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 900 u64 qmask) 901 { 902 u32 mask; 903 904 switch (adapter->hw.mac.type) { 905 case ixgbe_mac_82598EB: 906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 908 break; 909 case ixgbe_mac_82599EB: 910 case ixgbe_mac_X540: 911 case ixgbe_mac_X550: 912 case ixgbe_mac_X550EM_x: 913 case ixgbe_mac_x550em_a: 914 mask = (qmask & 0xFFFFFFFF); 915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 916 mask = (qmask >> 32); 917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 918 break; 919 default: 920 break; 921 } 922 } 923 924 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 925 { 926 struct ixgbe_hw *hw = &adapter->hw; 927 struct ixgbe_hw_stats *hwstats = &adapter->stats; 928 int i; 929 u32 data; 930 931 if ((hw->fc.current_mode != ixgbe_fc_full) && 932 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 933 return; 934 935 switch (hw->mac.type) { 936 case ixgbe_mac_82598EB: 937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 938 break; 939 default: 940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 941 } 942 hwstats->lxoffrxc += data; 943 944 /* refill credits (no tx hang) if we received xoff */ 945 if (!data) 946 return; 947 948 for (i = 0; i < adapter->num_tx_queues; i++) 949 clear_bit(__IXGBE_HANG_CHECK_ARMED, 950 &adapter->tx_ring[i]->state); 951 952 for (i = 0; i < adapter->num_xdp_queues; i++) 953 clear_bit(__IXGBE_HANG_CHECK_ARMED, 954 &adapter->xdp_ring[i]->state); 955 } 956 957 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 958 { 959 struct ixgbe_hw *hw = &adapter->hw; 960 struct ixgbe_hw_stats *hwstats = &adapter->stats; 961 u32 xoff[8] = {0}; 962 u8 tc; 963 int i; 964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 965 966 if (adapter->ixgbe_ieee_pfc) 967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 968 969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 970 ixgbe_update_xoff_rx_lfc(adapter); 971 return; 972 } 973 974 /* update stats for each tc, only valid with PFC enabled */ 975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 976 u32 pxoffrxc; 977 978 switch (hw->mac.type) { 979 case ixgbe_mac_82598EB: 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 981 break; 982 default: 983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 984 } 985 hwstats->pxoffrxc[i] += pxoffrxc; 986 /* Get the TC for given UP */ 987 tc = netdev_get_prio_tc_map(adapter->netdev, i); 988 xoff[tc] += pxoffrxc; 989 } 990 991 /* disarm tx queues that have received xoff frames */ 992 for (i = 0; i < adapter->num_tx_queues; i++) { 993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 994 995 tc = tx_ring->dcb_tc; 996 if (xoff[tc]) 997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 998 } 999 1000 for (i = 0; i < adapter->num_xdp_queues; i++) { 1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1002 1003 tc = xdp_ring->dcb_tc; 1004 if (xoff[tc]) 1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1006 } 1007 } 1008 1009 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1010 { 1011 return ring->stats.packets; 1012 } 1013 1014 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1015 { 1016 unsigned int head, tail; 1017 1018 head = ring->next_to_clean; 1019 tail = ring->next_to_use; 1020 1021 return ((head <= tail) ? tail : tail + ring->count) - head; 1022 } 1023 1024 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1025 { 1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1029 1030 clear_check_for_tx_hang(tx_ring); 1031 1032 /* 1033 * Check for a hung queue, but be thorough. This verifies 1034 * that a transmit has been completed since the previous 1035 * check AND there is at least one packet pending. The 1036 * ARMED bit is set to indicate a potential hang. The 1037 * bit is cleared if a pause frame is received to remove 1038 * false hang detection due to PFC or 802.3x frames. By 1039 * requiring this to fail twice we avoid races with 1040 * pfc clearing the ARMED bit and conditions where we 1041 * run the check_tx_hang logic with a transmit completion 1042 * pending but without time to complete it yet. 1043 */ 1044 if (tx_done_old == tx_done && tx_pending) 1045 /* make sure it is true for two checks in a row */ 1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1047 &tx_ring->state); 1048 /* update completed stats and continue */ 1049 tx_ring->tx_stats.tx_done_old = tx_done; 1050 /* reset the countdown */ 1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1052 1053 return false; 1054 } 1055 1056 /** 1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1058 * @adapter: driver private struct 1059 **/ 1060 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1061 { 1062 1063 /* Do the reset outside of interrupt context */ 1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1066 e_warn(drv, "initiating reset due to tx timeout\n"); 1067 ixgbe_service_event_schedule(adapter); 1068 } 1069 } 1070 1071 /** 1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1073 * @netdev: network interface device structure 1074 * @queue_index: Tx queue to set 1075 * @maxrate: desired maximum transmit bitrate 1076 **/ 1077 static int ixgbe_tx_maxrate(struct net_device *netdev, 1078 int queue_index, u32 maxrate) 1079 { 1080 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1081 struct ixgbe_hw *hw = &adapter->hw; 1082 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1083 1084 if (!maxrate) 1085 return 0; 1086 1087 /* Calculate the rate factor values to set */ 1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1089 bcnrc_val /= maxrate; 1090 1091 /* clear everything but the rate factor */ 1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1093 IXGBE_RTTBCNRC_RF_DEC_MASK; 1094 1095 /* enable the rate scheduler */ 1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1097 1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1100 1101 return 0; 1102 } 1103 1104 /** 1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1106 * @q_vector: structure containing interrupt and ring information 1107 * @tx_ring: tx ring to clean 1108 * @napi_budget: Used to determine if we are in netpoll 1109 **/ 1110 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1111 struct ixgbe_ring *tx_ring, int napi_budget) 1112 { 1113 struct ixgbe_adapter *adapter = q_vector->adapter; 1114 struct ixgbe_tx_buffer *tx_buffer; 1115 union ixgbe_adv_tx_desc *tx_desc; 1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1117 unsigned int budget = q_vector->tx.work_limit; 1118 unsigned int i = tx_ring->next_to_clean; 1119 1120 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1121 return true; 1122 1123 tx_buffer = &tx_ring->tx_buffer_info[i]; 1124 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1125 i -= tx_ring->count; 1126 1127 do { 1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1129 1130 /* if next_to_watch is not set then there is no work pending */ 1131 if (!eop_desc) 1132 break; 1133 1134 /* prevent any other reads prior to eop_desc */ 1135 smp_rmb(); 1136 1137 /* if DD is not set pending work has not been completed */ 1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1139 break; 1140 1141 /* clear next_to_watch to prevent false hangs */ 1142 tx_buffer->next_to_watch = NULL; 1143 1144 /* update the statistics for this packet */ 1145 total_bytes += tx_buffer->bytecount; 1146 total_packets += tx_buffer->gso_segs; 1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1148 total_ipsec++; 1149 1150 /* free the skb */ 1151 if (ring_is_xdp(tx_ring)) 1152 xdp_return_frame(tx_buffer->xdpf); 1153 else 1154 napi_consume_skb(tx_buffer->skb, napi_budget); 1155 1156 /* unmap skb header data */ 1157 dma_unmap_single(tx_ring->dev, 1158 dma_unmap_addr(tx_buffer, dma), 1159 dma_unmap_len(tx_buffer, len), 1160 DMA_TO_DEVICE); 1161 1162 /* clear tx_buffer data */ 1163 dma_unmap_len_set(tx_buffer, len, 0); 1164 1165 /* unmap remaining buffers */ 1166 while (tx_desc != eop_desc) { 1167 tx_buffer++; 1168 tx_desc++; 1169 i++; 1170 if (unlikely(!i)) { 1171 i -= tx_ring->count; 1172 tx_buffer = tx_ring->tx_buffer_info; 1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1174 } 1175 1176 /* unmap any remaining paged data */ 1177 if (dma_unmap_len(tx_buffer, len)) { 1178 dma_unmap_page(tx_ring->dev, 1179 dma_unmap_addr(tx_buffer, dma), 1180 dma_unmap_len(tx_buffer, len), 1181 DMA_TO_DEVICE); 1182 dma_unmap_len_set(tx_buffer, len, 0); 1183 } 1184 } 1185 1186 /* move us one more past the eop_desc for start of next pkt */ 1187 tx_buffer++; 1188 tx_desc++; 1189 i++; 1190 if (unlikely(!i)) { 1191 i -= tx_ring->count; 1192 tx_buffer = tx_ring->tx_buffer_info; 1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1194 } 1195 1196 /* issue prefetch for next Tx descriptor */ 1197 prefetch(tx_desc); 1198 1199 /* update budget accounting */ 1200 budget--; 1201 } while (likely(budget)); 1202 1203 i += tx_ring->count; 1204 tx_ring->next_to_clean = i; 1205 u64_stats_update_begin(&tx_ring->syncp); 1206 tx_ring->stats.bytes += total_bytes; 1207 tx_ring->stats.packets += total_packets; 1208 u64_stats_update_end(&tx_ring->syncp); 1209 q_vector->tx.total_bytes += total_bytes; 1210 q_vector->tx.total_packets += total_packets; 1211 adapter->tx_ipsec += total_ipsec; 1212 1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1214 /* schedule immediate reset if we believe we hung */ 1215 struct ixgbe_hw *hw = &adapter->hw; 1216 e_err(drv, "Detected Tx Unit Hang %s\n" 1217 " Tx Queue <%d>\n" 1218 " TDH, TDT <%x>, <%x>\n" 1219 " next_to_use <%x>\n" 1220 " next_to_clean <%x>\n" 1221 "tx_buffer_info[next_to_clean]\n" 1222 " time_stamp <%lx>\n" 1223 " jiffies <%lx>\n", 1224 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1225 tx_ring->queue_index, 1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1228 tx_ring->next_to_use, i, 1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1230 1231 if (!ring_is_xdp(tx_ring)) 1232 netif_stop_subqueue(tx_ring->netdev, 1233 tx_ring->queue_index); 1234 1235 e_info(probe, 1236 "tx hang %d detected on queue %d, resetting adapter\n", 1237 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1238 1239 /* schedule immediate reset if we believe we hung */ 1240 ixgbe_tx_timeout_reset(adapter); 1241 1242 /* the adapter is about to reset, no point in enabling stuff */ 1243 return true; 1244 } 1245 1246 if (ring_is_xdp(tx_ring)) 1247 return !!budget; 1248 1249 netdev_tx_completed_queue(txring_txq(tx_ring), 1250 total_packets, total_bytes); 1251 1252 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1255 /* Make sure that anybody stopping the queue after this 1256 * sees the new next_to_clean. 1257 */ 1258 smp_mb(); 1259 if (__netif_subqueue_stopped(tx_ring->netdev, 1260 tx_ring->queue_index) 1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1262 netif_wake_subqueue(tx_ring->netdev, 1263 tx_ring->queue_index); 1264 ++tx_ring->tx_stats.restart_queue; 1265 } 1266 } 1267 1268 return !!budget; 1269 } 1270 1271 #ifdef CONFIG_IXGBE_DCA 1272 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1273 struct ixgbe_ring *tx_ring, 1274 int cpu) 1275 { 1276 struct ixgbe_hw *hw = &adapter->hw; 1277 u32 txctrl = 0; 1278 u16 reg_offset; 1279 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1281 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1282 1283 switch (hw->mac.type) { 1284 case ixgbe_mac_82598EB: 1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1286 break; 1287 case ixgbe_mac_82599EB: 1288 case ixgbe_mac_X540: 1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1291 break; 1292 default: 1293 /* for unknown hardware do not write register */ 1294 return; 1295 } 1296 1297 /* 1298 * We can enable relaxed ordering for reads, but not writes when 1299 * DCA is enabled. This is due to a known issue in some chipsets 1300 * which will cause the DCA tag to be cleared. 1301 */ 1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1305 1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1307 } 1308 1309 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1310 struct ixgbe_ring *rx_ring, 1311 int cpu) 1312 { 1313 struct ixgbe_hw *hw = &adapter->hw; 1314 u32 rxctrl = 0; 1315 u8 reg_idx = rx_ring->reg_idx; 1316 1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1319 1320 switch (hw->mac.type) { 1321 case ixgbe_mac_82599EB: 1322 case ixgbe_mac_X540: 1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1324 break; 1325 default: 1326 break; 1327 } 1328 1329 /* 1330 * We can enable relaxed ordering for reads, but not writes when 1331 * DCA is enabled. This is due to a known issue in some chipsets 1332 * which will cause the DCA tag to be cleared. 1333 */ 1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1337 1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1339 } 1340 1341 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1342 { 1343 struct ixgbe_adapter *adapter = q_vector->adapter; 1344 struct ixgbe_ring *ring; 1345 int cpu = get_cpu(); 1346 1347 if (q_vector->cpu == cpu) 1348 goto out_no_update; 1349 1350 ixgbe_for_each_ring(ring, q_vector->tx) 1351 ixgbe_update_tx_dca(adapter, ring, cpu); 1352 1353 ixgbe_for_each_ring(ring, q_vector->rx) 1354 ixgbe_update_rx_dca(adapter, ring, cpu); 1355 1356 q_vector->cpu = cpu; 1357 out_no_update: 1358 put_cpu(); 1359 } 1360 1361 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1362 { 1363 int i; 1364 1365 /* always use CB2 mode, difference is masked in the CB driver */ 1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1368 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1369 else 1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1371 IXGBE_DCA_CTRL_DCA_DISABLE); 1372 1373 for (i = 0; i < adapter->num_q_vectors; i++) { 1374 adapter->q_vector[i]->cpu = -1; 1375 ixgbe_update_dca(adapter->q_vector[i]); 1376 } 1377 } 1378 1379 static int __ixgbe_notify_dca(struct device *dev, void *data) 1380 { 1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1382 unsigned long event = *(unsigned long *)data; 1383 1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1385 return 0; 1386 1387 switch (event) { 1388 case DCA_PROVIDER_ADD: 1389 /* if we're already enabled, don't do it again */ 1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1391 break; 1392 if (dca_add_requester(dev) == 0) { 1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1395 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1396 break; 1397 } 1398 /* fall through - DCA is disabled. */ 1399 case DCA_PROVIDER_REMOVE: 1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1401 dca_remove_requester(dev); 1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1404 IXGBE_DCA_CTRL_DCA_DISABLE); 1405 } 1406 break; 1407 } 1408 1409 return 0; 1410 } 1411 1412 #endif /* CONFIG_IXGBE_DCA */ 1413 1414 #define IXGBE_RSS_L4_TYPES_MASK \ 1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1419 1420 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1421 union ixgbe_adv_rx_desc *rx_desc, 1422 struct sk_buff *skb) 1423 { 1424 u16 rss_type; 1425 1426 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1427 return; 1428 1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1430 IXGBE_RXDADV_RSSTYPE_MASK; 1431 1432 if (!rss_type) 1433 return; 1434 1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1438 } 1439 1440 #ifdef IXGBE_FCOE 1441 /** 1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1443 * @ring: structure containing ring specific data 1444 * @rx_desc: advanced rx descriptor 1445 * 1446 * Returns : true if it is FCoE pkt 1447 */ 1448 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1449 union ixgbe_adv_rx_desc *rx_desc) 1450 { 1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1452 1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1457 } 1458 1459 #endif /* IXGBE_FCOE */ 1460 /** 1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1462 * @ring: structure containing ring specific data 1463 * @rx_desc: current Rx descriptor being processed 1464 * @skb: skb currently being received and modified 1465 **/ 1466 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1467 union ixgbe_adv_rx_desc *rx_desc, 1468 struct sk_buff *skb) 1469 { 1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1471 bool encap_pkt = false; 1472 1473 skb_checksum_none_assert(skb); 1474 1475 /* Rx csum disabled */ 1476 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1477 return; 1478 1479 /* check for VXLAN and Geneve packets */ 1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1481 encap_pkt = true; 1482 skb->encapsulation = 1; 1483 } 1484 1485 /* if IP and error */ 1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1488 ring->rx_stats.csum_err++; 1489 return; 1490 } 1491 1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1493 return; 1494 1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1496 /* 1497 * 82599 errata, UDP frames with a 0 checksum can be marked as 1498 * checksum errors. 1499 */ 1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1502 return; 1503 1504 ring->rx_stats.csum_err++; 1505 return; 1506 } 1507 1508 /* It must be a TCP or UDP packet with a valid checksum */ 1509 skb->ip_summed = CHECKSUM_UNNECESSARY; 1510 if (encap_pkt) { 1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1512 return; 1513 1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1515 skb->ip_summed = CHECKSUM_NONE; 1516 return; 1517 } 1518 /* If we checked the outer header let the stack know */ 1519 skb->csum_level = 1; 1520 } 1521 } 1522 1523 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1524 { 1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1526 } 1527 1528 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1529 struct ixgbe_rx_buffer *bi) 1530 { 1531 struct page *page = bi->page; 1532 dma_addr_t dma; 1533 1534 /* since we are recycling buffers we should seldom need to alloc */ 1535 if (likely(page)) 1536 return true; 1537 1538 /* alloc new page for storage */ 1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1540 if (unlikely(!page)) { 1541 rx_ring->rx_stats.alloc_rx_page_failed++; 1542 return false; 1543 } 1544 1545 /* map page for use */ 1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1547 ixgbe_rx_pg_size(rx_ring), 1548 DMA_FROM_DEVICE, 1549 IXGBE_RX_DMA_ATTR); 1550 1551 /* 1552 * if mapping failed free memory back to system since 1553 * there isn't much point in holding memory we can't use 1554 */ 1555 if (dma_mapping_error(rx_ring->dev, dma)) { 1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1557 1558 rx_ring->rx_stats.alloc_rx_page_failed++; 1559 return false; 1560 } 1561 1562 bi->dma = dma; 1563 bi->page = page; 1564 bi->page_offset = ixgbe_rx_offset(rx_ring); 1565 page_ref_add(page, USHRT_MAX - 1); 1566 bi->pagecnt_bias = USHRT_MAX; 1567 rx_ring->rx_stats.alloc_rx_page++; 1568 1569 return true; 1570 } 1571 1572 /** 1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1574 * @rx_ring: ring to place buffers on 1575 * @cleaned_count: number of buffers to replace 1576 **/ 1577 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1578 { 1579 union ixgbe_adv_rx_desc *rx_desc; 1580 struct ixgbe_rx_buffer *bi; 1581 u16 i = rx_ring->next_to_use; 1582 u16 bufsz; 1583 1584 /* nothing to do */ 1585 if (!cleaned_count) 1586 return; 1587 1588 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1589 bi = &rx_ring->rx_buffer_info[i]; 1590 i -= rx_ring->count; 1591 1592 bufsz = ixgbe_rx_bufsz(rx_ring); 1593 1594 do { 1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1596 break; 1597 1598 /* sync the buffer for use by the device */ 1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1600 bi->page_offset, bufsz, 1601 DMA_FROM_DEVICE); 1602 1603 /* 1604 * Refresh the desc even if buffer_addrs didn't change 1605 * because each write-back erases this info. 1606 */ 1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1608 1609 rx_desc++; 1610 bi++; 1611 i++; 1612 if (unlikely(!i)) { 1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1614 bi = rx_ring->rx_buffer_info; 1615 i -= rx_ring->count; 1616 } 1617 1618 /* clear the length for the next_to_use descriptor */ 1619 rx_desc->wb.upper.length = 0; 1620 1621 cleaned_count--; 1622 } while (cleaned_count); 1623 1624 i += rx_ring->count; 1625 1626 if (rx_ring->next_to_use != i) { 1627 rx_ring->next_to_use = i; 1628 1629 /* update next to alloc since we have filled the ring */ 1630 rx_ring->next_to_alloc = i; 1631 1632 /* Force memory writes to complete before letting h/w 1633 * know there are new descriptors to fetch. (Only 1634 * applicable for weak-ordered memory model archs, 1635 * such as IA-64). 1636 */ 1637 wmb(); 1638 writel(i, rx_ring->tail); 1639 } 1640 } 1641 1642 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1643 struct sk_buff *skb) 1644 { 1645 u16 hdr_len = skb_headlen(skb); 1646 1647 /* set gso_size to avoid messing up TCP MSS */ 1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1649 IXGBE_CB(skb)->append_cnt); 1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1651 } 1652 1653 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1654 struct sk_buff *skb) 1655 { 1656 /* if append_cnt is 0 then frame is not RSC */ 1657 if (!IXGBE_CB(skb)->append_cnt) 1658 return; 1659 1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1661 rx_ring->rx_stats.rsc_flush++; 1662 1663 ixgbe_set_rsc_gso_size(rx_ring, skb); 1664 1665 /* gso_size is computed using append_cnt so always clear it last */ 1666 IXGBE_CB(skb)->append_cnt = 0; 1667 } 1668 1669 /** 1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1671 * @rx_ring: rx descriptor ring packet is being transacted on 1672 * @rx_desc: pointer to the EOP Rx descriptor 1673 * @skb: pointer to current skb being populated 1674 * 1675 * This function checks the ring, descriptor, and packet information in 1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1677 * other fields within the skb. 1678 **/ 1679 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1680 union ixgbe_adv_rx_desc *rx_desc, 1681 struct sk_buff *skb) 1682 { 1683 struct net_device *dev = rx_ring->netdev; 1684 u32 flags = rx_ring->q_vector->adapter->flags; 1685 1686 ixgbe_update_rsc_stats(rx_ring, skb); 1687 1688 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1689 1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1691 1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1694 1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1699 } 1700 1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1703 1704 /* record Rx queue, or update MACVLAN statistics */ 1705 if (netif_is_ixgbe(dev)) 1706 skb_record_rx_queue(skb, rx_ring->queue_index); 1707 else 1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1709 false); 1710 1711 skb->protocol = eth_type_trans(skb, dev); 1712 } 1713 1714 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1715 struct sk_buff *skb) 1716 { 1717 napi_gro_receive(&q_vector->napi, skb); 1718 } 1719 1720 /** 1721 * ixgbe_is_non_eop - process handling of non-EOP buffers 1722 * @rx_ring: Rx ring being processed 1723 * @rx_desc: Rx descriptor for current buffer 1724 * @skb: Current socket buffer containing buffer in progress 1725 * 1726 * This function updates next to clean. If the buffer is an EOP buffer 1727 * this function exits returning false, otherwise it will place the 1728 * sk_buff in the next buffer to be chained and return true indicating 1729 * that this is in fact a non-EOP buffer. 1730 **/ 1731 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1732 union ixgbe_adv_rx_desc *rx_desc, 1733 struct sk_buff *skb) 1734 { 1735 u32 ntc = rx_ring->next_to_clean + 1; 1736 1737 /* fetch, update, and store next to clean */ 1738 ntc = (ntc < rx_ring->count) ? ntc : 0; 1739 rx_ring->next_to_clean = ntc; 1740 1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1742 1743 /* update RSC append count if present */ 1744 if (ring_is_rsc_enabled(rx_ring)) { 1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1747 1748 if (unlikely(rsc_enabled)) { 1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1750 1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1753 1754 /* update ntc based on RSC value */ 1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1756 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1758 } 1759 } 1760 1761 /* if we are the last buffer then there is nothing else to do */ 1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1763 return false; 1764 1765 /* place skb in next buffer to be received */ 1766 rx_ring->rx_buffer_info[ntc].skb = skb; 1767 rx_ring->rx_stats.non_eop_descs++; 1768 1769 return true; 1770 } 1771 1772 /** 1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1774 * @rx_ring: rx descriptor ring packet is being transacted on 1775 * @skb: pointer to current skb being adjusted 1776 * 1777 * This function is an ixgbe specific version of __pskb_pull_tail. The 1778 * main difference between this version and the original function is that 1779 * this function can make several assumptions about the state of things 1780 * that allow for significant optimizations versus the standard function. 1781 * As a result we can do things like drop a frag and maintain an accurate 1782 * truesize for the skb. 1783 */ 1784 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1785 struct sk_buff *skb) 1786 { 1787 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1788 unsigned char *va; 1789 unsigned int pull_len; 1790 1791 /* 1792 * it is valid to use page_address instead of kmap since we are 1793 * working with pages allocated out of the lomem pool per 1794 * alloc_page(GFP_ATOMIC) 1795 */ 1796 va = skb_frag_address(frag); 1797 1798 /* 1799 * we need the header to contain the greater of either ETH_HLEN or 1800 * 60 bytes if the skb->len is less than 60 for skb_pad. 1801 */ 1802 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1803 1804 /* align pull length to size of long to optimize memcpy performance */ 1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1806 1807 /* update all of the pointers */ 1808 skb_frag_size_sub(frag, pull_len); 1809 frag->page_offset += pull_len; 1810 skb->data_len -= pull_len; 1811 skb->tail += pull_len; 1812 } 1813 1814 /** 1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1816 * @rx_ring: rx descriptor ring packet is being transacted on 1817 * @skb: pointer to current skb being updated 1818 * 1819 * This function provides a basic DMA sync up for the first fragment of an 1820 * skb. The reason for doing this is that the first fragment cannot be 1821 * unmapped until we have reached the end of packet descriptor for a buffer 1822 * chain. 1823 */ 1824 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1825 struct sk_buff *skb) 1826 { 1827 /* if the page was released unmap it, else just sync our portion */ 1828 if (unlikely(IXGBE_CB(skb)->page_released)) { 1829 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1830 ixgbe_rx_pg_size(rx_ring), 1831 DMA_FROM_DEVICE, 1832 IXGBE_RX_DMA_ATTR); 1833 } else if (ring_uses_build_skb(rx_ring)) { 1834 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1835 1836 dma_sync_single_range_for_cpu(rx_ring->dev, 1837 IXGBE_CB(skb)->dma, 1838 offset, 1839 skb_headlen(skb), 1840 DMA_FROM_DEVICE); 1841 } else { 1842 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1843 1844 dma_sync_single_range_for_cpu(rx_ring->dev, 1845 IXGBE_CB(skb)->dma, 1846 frag->page_offset, 1847 skb_frag_size(frag), 1848 DMA_FROM_DEVICE); 1849 } 1850 } 1851 1852 /** 1853 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1854 * @rx_ring: rx descriptor ring packet is being transacted on 1855 * @rx_desc: pointer to the EOP Rx descriptor 1856 * @skb: pointer to current skb being fixed 1857 * 1858 * Check if the skb is valid in the XDP case it will be an error pointer. 1859 * Return true in this case to abort processing and advance to next 1860 * descriptor. 1861 * 1862 * Check for corrupted packet headers caused by senders on the local L2 1863 * embedded NIC switch not setting up their Tx Descriptors right. These 1864 * should be very rare. 1865 * 1866 * Also address the case where we are pulling data in on pages only 1867 * and as such no data is present in the skb header. 1868 * 1869 * In addition if skb is not at least 60 bytes we need to pad it so that 1870 * it is large enough to qualify as a valid Ethernet frame. 1871 * 1872 * Returns true if an error was encountered and skb was freed. 1873 **/ 1874 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1875 union ixgbe_adv_rx_desc *rx_desc, 1876 struct sk_buff *skb) 1877 { 1878 struct net_device *netdev = rx_ring->netdev; 1879 1880 /* XDP packets use error pointer so abort at this point */ 1881 if (IS_ERR(skb)) 1882 return true; 1883 1884 /* Verify netdev is present, and that packet does not have any 1885 * errors that would be unacceptable to the netdev. 1886 */ 1887 if (!netdev || 1888 (unlikely(ixgbe_test_staterr(rx_desc, 1889 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1890 !(netdev->features & NETIF_F_RXALL)))) { 1891 dev_kfree_skb_any(skb); 1892 return true; 1893 } 1894 1895 /* place header in linear portion of buffer */ 1896 if (!skb_headlen(skb)) 1897 ixgbe_pull_tail(rx_ring, skb); 1898 1899 #ifdef IXGBE_FCOE 1900 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1901 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1902 return false; 1903 1904 #endif 1905 /* if eth_skb_pad returns an error the skb was freed */ 1906 if (eth_skb_pad(skb)) 1907 return true; 1908 1909 return false; 1910 } 1911 1912 /** 1913 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1914 * @rx_ring: rx descriptor ring to store buffers on 1915 * @old_buff: donor buffer to have page reused 1916 * 1917 * Synchronizes page for reuse by the adapter 1918 **/ 1919 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1920 struct ixgbe_rx_buffer *old_buff) 1921 { 1922 struct ixgbe_rx_buffer *new_buff; 1923 u16 nta = rx_ring->next_to_alloc; 1924 1925 new_buff = &rx_ring->rx_buffer_info[nta]; 1926 1927 /* update, and store next to alloc */ 1928 nta++; 1929 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1930 1931 /* Transfer page from old buffer to new buffer. 1932 * Move each member individually to avoid possible store 1933 * forwarding stalls and unnecessary copy of skb. 1934 */ 1935 new_buff->dma = old_buff->dma; 1936 new_buff->page = old_buff->page; 1937 new_buff->page_offset = old_buff->page_offset; 1938 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1939 } 1940 1941 static inline bool ixgbe_page_is_reserved(struct page *page) 1942 { 1943 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1944 } 1945 1946 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1947 { 1948 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1949 struct page *page = rx_buffer->page; 1950 1951 /* avoid re-using remote pages */ 1952 if (unlikely(ixgbe_page_is_reserved(page))) 1953 return false; 1954 1955 #if (PAGE_SIZE < 8192) 1956 /* if we are only owner of page we can reuse it */ 1957 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1958 return false; 1959 #else 1960 /* The last offset is a bit aggressive in that we assume the 1961 * worst case of FCoE being enabled and using a 3K buffer. 1962 * However this should have minimal impact as the 1K extra is 1963 * still less than one buffer in size. 1964 */ 1965 #define IXGBE_LAST_OFFSET \ 1966 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1967 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1968 return false; 1969 #endif 1970 1971 /* If we have drained the page fragment pool we need to update 1972 * the pagecnt_bias and page count so that we fully restock the 1973 * number of references the driver holds. 1974 */ 1975 if (unlikely(pagecnt_bias == 1)) { 1976 page_ref_add(page, USHRT_MAX - 1); 1977 rx_buffer->pagecnt_bias = USHRT_MAX; 1978 } 1979 1980 return true; 1981 } 1982 1983 /** 1984 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1985 * @rx_ring: rx descriptor ring to transact packets on 1986 * @rx_buffer: buffer containing page to add 1987 * @skb: sk_buff to place the data into 1988 * @size: size of data in rx_buffer 1989 * 1990 * This function will add the data contained in rx_buffer->page to the skb. 1991 * This is done either through a direct copy if the data in the buffer is 1992 * less than the skb header size, otherwise it will just attach the page as 1993 * a frag to the skb. 1994 * 1995 * The function will then update the page offset if necessary and return 1996 * true if the buffer can be reused by the adapter. 1997 **/ 1998 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1999 struct ixgbe_rx_buffer *rx_buffer, 2000 struct sk_buff *skb, 2001 unsigned int size) 2002 { 2003 #if (PAGE_SIZE < 8192) 2004 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2005 #else 2006 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2007 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2008 SKB_DATA_ALIGN(size); 2009 #endif 2010 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2011 rx_buffer->page_offset, size, truesize); 2012 #if (PAGE_SIZE < 8192) 2013 rx_buffer->page_offset ^= truesize; 2014 #else 2015 rx_buffer->page_offset += truesize; 2016 #endif 2017 } 2018 2019 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2020 union ixgbe_adv_rx_desc *rx_desc, 2021 struct sk_buff **skb, 2022 const unsigned int size) 2023 { 2024 struct ixgbe_rx_buffer *rx_buffer; 2025 2026 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2027 prefetchw(rx_buffer->page); 2028 *skb = rx_buffer->skb; 2029 2030 /* Delay unmapping of the first packet. It carries the header 2031 * information, HW may still access the header after the writeback. 2032 * Only unmap it when EOP is reached 2033 */ 2034 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2035 if (!*skb) 2036 goto skip_sync; 2037 } else { 2038 if (*skb) 2039 ixgbe_dma_sync_frag(rx_ring, *skb); 2040 } 2041 2042 /* we are reusing so sync this buffer for CPU use */ 2043 dma_sync_single_range_for_cpu(rx_ring->dev, 2044 rx_buffer->dma, 2045 rx_buffer->page_offset, 2046 size, 2047 DMA_FROM_DEVICE); 2048 skip_sync: 2049 rx_buffer->pagecnt_bias--; 2050 2051 return rx_buffer; 2052 } 2053 2054 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2055 struct ixgbe_rx_buffer *rx_buffer, 2056 struct sk_buff *skb) 2057 { 2058 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2059 /* hand second half of page back to the ring */ 2060 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2061 } else { 2062 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2063 /* the page has been released from the ring */ 2064 IXGBE_CB(skb)->page_released = true; 2065 } else { 2066 /* we are not reusing the buffer so unmap it */ 2067 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2068 ixgbe_rx_pg_size(rx_ring), 2069 DMA_FROM_DEVICE, 2070 IXGBE_RX_DMA_ATTR); 2071 } 2072 __page_frag_cache_drain(rx_buffer->page, 2073 rx_buffer->pagecnt_bias); 2074 } 2075 2076 /* clear contents of rx_buffer */ 2077 rx_buffer->page = NULL; 2078 rx_buffer->skb = NULL; 2079 } 2080 2081 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2082 struct ixgbe_rx_buffer *rx_buffer, 2083 struct xdp_buff *xdp, 2084 union ixgbe_adv_rx_desc *rx_desc) 2085 { 2086 unsigned int size = xdp->data_end - xdp->data; 2087 #if (PAGE_SIZE < 8192) 2088 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2089 #else 2090 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2091 xdp->data_hard_start); 2092 #endif 2093 struct sk_buff *skb; 2094 2095 /* prefetch first cache line of first page */ 2096 prefetch(xdp->data); 2097 #if L1_CACHE_BYTES < 128 2098 prefetch(xdp->data + L1_CACHE_BYTES); 2099 #endif 2100 /* Note, we get here by enabling legacy-rx via: 2101 * 2102 * ethtool --set-priv-flags <dev> legacy-rx on 2103 * 2104 * In this mode, we currently get 0 extra XDP headroom as 2105 * opposed to having legacy-rx off, where we process XDP 2106 * packets going to stack via ixgbe_build_skb(). The latter 2107 * provides us currently with 192 bytes of headroom. 2108 * 2109 * For ixgbe_construct_skb() mode it means that the 2110 * xdp->data_meta will always point to xdp->data, since 2111 * the helper cannot expand the head. Should this ever 2112 * change in future for legacy-rx mode on, then lets also 2113 * add xdp->data_meta handling here. 2114 */ 2115 2116 /* allocate a skb to store the frags */ 2117 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2118 if (unlikely(!skb)) 2119 return NULL; 2120 2121 if (size > IXGBE_RX_HDR_SIZE) { 2122 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2123 IXGBE_CB(skb)->dma = rx_buffer->dma; 2124 2125 skb_add_rx_frag(skb, 0, rx_buffer->page, 2126 xdp->data - page_address(rx_buffer->page), 2127 size, truesize); 2128 #if (PAGE_SIZE < 8192) 2129 rx_buffer->page_offset ^= truesize; 2130 #else 2131 rx_buffer->page_offset += truesize; 2132 #endif 2133 } else { 2134 memcpy(__skb_put(skb, size), 2135 xdp->data, ALIGN(size, sizeof(long))); 2136 rx_buffer->pagecnt_bias++; 2137 } 2138 2139 return skb; 2140 } 2141 2142 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2143 struct ixgbe_rx_buffer *rx_buffer, 2144 struct xdp_buff *xdp, 2145 union ixgbe_adv_rx_desc *rx_desc) 2146 { 2147 unsigned int metasize = xdp->data - xdp->data_meta; 2148 #if (PAGE_SIZE < 8192) 2149 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2150 #else 2151 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2152 SKB_DATA_ALIGN(xdp->data_end - 2153 xdp->data_hard_start); 2154 #endif 2155 struct sk_buff *skb; 2156 2157 /* Prefetch first cache line of first page. If xdp->data_meta 2158 * is unused, this points extactly as xdp->data, otherwise we 2159 * likely have a consumer accessing first few bytes of meta 2160 * data, and then actual data. 2161 */ 2162 prefetch(xdp->data_meta); 2163 #if L1_CACHE_BYTES < 128 2164 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2165 #endif 2166 2167 /* build an skb to around the page buffer */ 2168 skb = build_skb(xdp->data_hard_start, truesize); 2169 if (unlikely(!skb)) 2170 return NULL; 2171 2172 /* update pointers within the skb to store the data */ 2173 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2174 __skb_put(skb, xdp->data_end - xdp->data); 2175 if (metasize) 2176 skb_metadata_set(skb, metasize); 2177 2178 /* record DMA address if this is the start of a chain of buffers */ 2179 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2180 IXGBE_CB(skb)->dma = rx_buffer->dma; 2181 2182 /* update buffer offset */ 2183 #if (PAGE_SIZE < 8192) 2184 rx_buffer->page_offset ^= truesize; 2185 #else 2186 rx_buffer->page_offset += truesize; 2187 #endif 2188 2189 return skb; 2190 } 2191 2192 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2193 struct ixgbe_ring *rx_ring, 2194 struct xdp_buff *xdp) 2195 { 2196 int err, result = IXGBE_XDP_PASS; 2197 struct bpf_prog *xdp_prog; 2198 struct xdp_frame *xdpf; 2199 u32 act; 2200 2201 rcu_read_lock(); 2202 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2203 2204 if (!xdp_prog) 2205 goto xdp_out; 2206 2207 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2208 2209 act = bpf_prog_run_xdp(xdp_prog, xdp); 2210 switch (act) { 2211 case XDP_PASS: 2212 break; 2213 case XDP_TX: 2214 xdpf = convert_to_xdp_frame(xdp); 2215 if (unlikely(!xdpf)) { 2216 result = IXGBE_XDP_CONSUMED; 2217 break; 2218 } 2219 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2220 break; 2221 case XDP_REDIRECT: 2222 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2223 if (!err) 2224 result = IXGBE_XDP_REDIR; 2225 else 2226 result = IXGBE_XDP_CONSUMED; 2227 break; 2228 default: 2229 bpf_warn_invalid_xdp_action(act); 2230 /* fallthrough */ 2231 case XDP_ABORTED: 2232 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2233 /* fallthrough -- handle aborts by dropping packet */ 2234 case XDP_DROP: 2235 result = IXGBE_XDP_CONSUMED; 2236 break; 2237 } 2238 xdp_out: 2239 rcu_read_unlock(); 2240 return ERR_PTR(-result); 2241 } 2242 2243 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2244 struct ixgbe_rx_buffer *rx_buffer, 2245 unsigned int size) 2246 { 2247 #if (PAGE_SIZE < 8192) 2248 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2249 2250 rx_buffer->page_offset ^= truesize; 2251 #else 2252 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2253 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2254 SKB_DATA_ALIGN(size); 2255 2256 rx_buffer->page_offset += truesize; 2257 #endif 2258 } 2259 2260 /** 2261 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2262 * @q_vector: structure containing interrupt and ring information 2263 * @rx_ring: rx descriptor ring to transact packets on 2264 * @budget: Total limit on number of packets to process 2265 * 2266 * This function provides a "bounce buffer" approach to Rx interrupt 2267 * processing. The advantage to this is that on systems that have 2268 * expensive overhead for IOMMU access this provides a means of avoiding 2269 * it by maintaining the mapping of the page to the syste. 2270 * 2271 * Returns amount of work completed 2272 **/ 2273 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2274 struct ixgbe_ring *rx_ring, 2275 const int budget) 2276 { 2277 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2278 struct ixgbe_adapter *adapter = q_vector->adapter; 2279 #ifdef IXGBE_FCOE 2280 int ddp_bytes; 2281 unsigned int mss = 0; 2282 #endif /* IXGBE_FCOE */ 2283 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2284 unsigned int xdp_xmit = 0; 2285 struct xdp_buff xdp; 2286 2287 xdp.rxq = &rx_ring->xdp_rxq; 2288 2289 while (likely(total_rx_packets < budget)) { 2290 union ixgbe_adv_rx_desc *rx_desc; 2291 struct ixgbe_rx_buffer *rx_buffer; 2292 struct sk_buff *skb; 2293 unsigned int size; 2294 2295 /* return some buffers to hardware, one at a time is too slow */ 2296 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2297 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2298 cleaned_count = 0; 2299 } 2300 2301 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2302 size = le16_to_cpu(rx_desc->wb.upper.length); 2303 if (!size) 2304 break; 2305 2306 /* This memory barrier is needed to keep us from reading 2307 * any other fields out of the rx_desc until we know the 2308 * descriptor has been written back 2309 */ 2310 dma_rmb(); 2311 2312 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2313 2314 /* retrieve a buffer from the ring */ 2315 if (!skb) { 2316 xdp.data = page_address(rx_buffer->page) + 2317 rx_buffer->page_offset; 2318 xdp.data_meta = xdp.data; 2319 xdp.data_hard_start = xdp.data - 2320 ixgbe_rx_offset(rx_ring); 2321 xdp.data_end = xdp.data + size; 2322 2323 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2324 } 2325 2326 if (IS_ERR(skb)) { 2327 unsigned int xdp_res = -PTR_ERR(skb); 2328 2329 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2330 xdp_xmit |= xdp_res; 2331 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2332 } else { 2333 rx_buffer->pagecnt_bias++; 2334 } 2335 total_rx_packets++; 2336 total_rx_bytes += size; 2337 } else if (skb) { 2338 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2339 } else if (ring_uses_build_skb(rx_ring)) { 2340 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2341 &xdp, rx_desc); 2342 } else { 2343 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2344 &xdp, rx_desc); 2345 } 2346 2347 /* exit if we failed to retrieve a buffer */ 2348 if (!skb) { 2349 rx_ring->rx_stats.alloc_rx_buff_failed++; 2350 rx_buffer->pagecnt_bias++; 2351 break; 2352 } 2353 2354 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2355 cleaned_count++; 2356 2357 /* place incomplete frames back on ring for completion */ 2358 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2359 continue; 2360 2361 /* verify the packet layout is correct */ 2362 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2363 continue; 2364 2365 /* probably a little skewed due to removing CRC */ 2366 total_rx_bytes += skb->len; 2367 2368 /* populate checksum, timestamp, VLAN, and protocol */ 2369 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2370 2371 #ifdef IXGBE_FCOE 2372 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2373 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2374 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2375 /* include DDPed FCoE data */ 2376 if (ddp_bytes > 0) { 2377 if (!mss) { 2378 mss = rx_ring->netdev->mtu - 2379 sizeof(struct fcoe_hdr) - 2380 sizeof(struct fc_frame_header) - 2381 sizeof(struct fcoe_crc_eof); 2382 if (mss > 512) 2383 mss &= ~511; 2384 } 2385 total_rx_bytes += ddp_bytes; 2386 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2387 mss); 2388 } 2389 if (!ddp_bytes) { 2390 dev_kfree_skb_any(skb); 2391 continue; 2392 } 2393 } 2394 2395 #endif /* IXGBE_FCOE */ 2396 ixgbe_rx_skb(q_vector, skb); 2397 2398 /* update budget accounting */ 2399 total_rx_packets++; 2400 } 2401 2402 if (xdp_xmit & IXGBE_XDP_REDIR) 2403 xdp_do_flush_map(); 2404 2405 if (xdp_xmit & IXGBE_XDP_TX) { 2406 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2407 2408 /* Force memory writes to complete before letting h/w 2409 * know there are new descriptors to fetch. 2410 */ 2411 wmb(); 2412 writel(ring->next_to_use, ring->tail); 2413 } 2414 2415 u64_stats_update_begin(&rx_ring->syncp); 2416 rx_ring->stats.packets += total_rx_packets; 2417 rx_ring->stats.bytes += total_rx_bytes; 2418 u64_stats_update_end(&rx_ring->syncp); 2419 q_vector->rx.total_packets += total_rx_packets; 2420 q_vector->rx.total_bytes += total_rx_bytes; 2421 2422 return total_rx_packets; 2423 } 2424 2425 /** 2426 * ixgbe_configure_msix - Configure MSI-X hardware 2427 * @adapter: board private structure 2428 * 2429 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2430 * interrupts. 2431 **/ 2432 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2433 { 2434 struct ixgbe_q_vector *q_vector; 2435 int v_idx; 2436 u32 mask; 2437 2438 /* Populate MSIX to EITR Select */ 2439 if (adapter->num_vfs > 32) { 2440 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2442 } 2443 2444 /* 2445 * Populate the IVAR table and set the ITR values to the 2446 * corresponding register. 2447 */ 2448 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2449 struct ixgbe_ring *ring; 2450 q_vector = adapter->q_vector[v_idx]; 2451 2452 ixgbe_for_each_ring(ring, q_vector->rx) 2453 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2454 2455 ixgbe_for_each_ring(ring, q_vector->tx) 2456 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2457 2458 ixgbe_write_eitr(q_vector); 2459 } 2460 2461 switch (adapter->hw.mac.type) { 2462 case ixgbe_mac_82598EB: 2463 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2464 v_idx); 2465 break; 2466 case ixgbe_mac_82599EB: 2467 case ixgbe_mac_X540: 2468 case ixgbe_mac_X550: 2469 case ixgbe_mac_X550EM_x: 2470 case ixgbe_mac_x550em_a: 2471 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2472 break; 2473 default: 2474 break; 2475 } 2476 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2477 2478 /* set up to autoclear timer, and the vectors */ 2479 mask = IXGBE_EIMS_ENABLE_MASK; 2480 mask &= ~(IXGBE_EIMS_OTHER | 2481 IXGBE_EIMS_MAILBOX | 2482 IXGBE_EIMS_LSC); 2483 2484 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2485 } 2486 2487 /** 2488 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2489 * @q_vector: structure containing interrupt and ring information 2490 * @ring_container: structure containing ring performance data 2491 * 2492 * Stores a new ITR value based on packets and byte 2493 * counts during the last interrupt. The advantage of per interrupt 2494 * computation is faster updates and more accurate ITR for the current 2495 * traffic pattern. Constants in this function were computed 2496 * based on theoretical maximum wire speed and thresholds were set based 2497 * on testing data as well as attempting to minimize response time 2498 * while increasing bulk throughput. 2499 **/ 2500 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2501 struct ixgbe_ring_container *ring_container) 2502 { 2503 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2504 IXGBE_ITR_ADAPTIVE_LATENCY; 2505 unsigned int avg_wire_size, packets, bytes; 2506 unsigned long next_update = jiffies; 2507 2508 /* If we don't have any rings just leave ourselves set for maximum 2509 * possible latency so we take ourselves out of the equation. 2510 */ 2511 if (!ring_container->ring) 2512 return; 2513 2514 /* If we didn't update within up to 1 - 2 jiffies we can assume 2515 * that either packets are coming in so slow there hasn't been 2516 * any work, or that there is so much work that NAPI is dealing 2517 * with interrupt moderation and we don't need to do anything. 2518 */ 2519 if (time_after(next_update, ring_container->next_update)) 2520 goto clear_counts; 2521 2522 packets = ring_container->total_packets; 2523 2524 /* We have no packets to actually measure against. This means 2525 * either one of the other queues on this vector is active or 2526 * we are a Tx queue doing TSO with too high of an interrupt rate. 2527 * 2528 * When this occurs just tick up our delay by the minimum value 2529 * and hope that this extra delay will prevent us from being called 2530 * without any work on our queue. 2531 */ 2532 if (!packets) { 2533 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2534 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2535 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2536 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2537 goto clear_counts; 2538 } 2539 2540 bytes = ring_container->total_bytes; 2541 2542 /* If packets are less than 4 or bytes are less than 9000 assume 2543 * insufficient data to use bulk rate limiting approach. We are 2544 * likely latency driven. 2545 */ 2546 if (packets < 4 && bytes < 9000) { 2547 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2548 goto adjust_by_size; 2549 } 2550 2551 /* Between 4 and 48 we can assume that our current interrupt delay 2552 * is only slightly too low. As such we should increase it by a small 2553 * fixed amount. 2554 */ 2555 if (packets < 48) { 2556 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2557 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2558 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2559 goto clear_counts; 2560 } 2561 2562 /* Between 48 and 96 is our "goldilocks" zone where we are working 2563 * out "just right". Just report that our current ITR is good for us. 2564 */ 2565 if (packets < 96) { 2566 itr = q_vector->itr >> 2; 2567 goto clear_counts; 2568 } 2569 2570 /* If packet count is 96 or greater we are likely looking at a slight 2571 * overrun of the delay we want. Try halving our delay to see if that 2572 * will cut the number of packets in half per interrupt. 2573 */ 2574 if (packets < 256) { 2575 itr = q_vector->itr >> 3; 2576 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2577 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2578 goto clear_counts; 2579 } 2580 2581 /* The paths below assume we are dealing with a bulk ITR since number 2582 * of packets is 256 or greater. We are just going to have to compute 2583 * a value and try to bring the count under control, though for smaller 2584 * packet sizes there isn't much we can do as NAPI polling will likely 2585 * be kicking in sooner rather than later. 2586 */ 2587 itr = IXGBE_ITR_ADAPTIVE_BULK; 2588 2589 adjust_by_size: 2590 /* If packet counts are 256 or greater we can assume we have a gross 2591 * overestimation of what the rate should be. Instead of trying to fine 2592 * tune it just use the formula below to try and dial in an exact value 2593 * give the current packet size of the frame. 2594 */ 2595 avg_wire_size = bytes / packets; 2596 2597 /* The following is a crude approximation of: 2598 * wmem_default / (size + overhead) = desired_pkts_per_int 2599 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2600 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2601 * 2602 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2603 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2604 * formula down to 2605 * 2606 * (170 * (size + 24)) / (size + 640) = ITR 2607 * 2608 * We first do some math on the packet size and then finally bitshift 2609 * by 8 after rounding up. We also have to account for PCIe link speed 2610 * difference as ITR scales based on this. 2611 */ 2612 if (avg_wire_size <= 60) { 2613 /* Start at 50k ints/sec */ 2614 avg_wire_size = 5120; 2615 } else if (avg_wire_size <= 316) { 2616 /* 50K ints/sec to 16K ints/sec */ 2617 avg_wire_size *= 40; 2618 avg_wire_size += 2720; 2619 } else if (avg_wire_size <= 1084) { 2620 /* 16K ints/sec to 9.2K ints/sec */ 2621 avg_wire_size *= 15; 2622 avg_wire_size += 11452; 2623 } else if (avg_wire_size <= 1980) { 2624 /* 9.2K ints/sec to 8K ints/sec */ 2625 avg_wire_size *= 5; 2626 avg_wire_size += 22420; 2627 } else { 2628 /* plateau at a limit of 8K ints/sec */ 2629 avg_wire_size = 32256; 2630 } 2631 2632 /* If we are in low latency mode half our delay which doubles the rate 2633 * to somewhere between 100K to 16K ints/sec 2634 */ 2635 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2636 avg_wire_size >>= 1; 2637 2638 /* Resultant value is 256 times larger than it needs to be. This 2639 * gives us room to adjust the value as needed to either increase 2640 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2641 * 2642 * Use addition as we have already recorded the new latency flag 2643 * for the ITR value. 2644 */ 2645 switch (q_vector->adapter->link_speed) { 2646 case IXGBE_LINK_SPEED_10GB_FULL: 2647 case IXGBE_LINK_SPEED_100_FULL: 2648 default: 2649 itr += DIV_ROUND_UP(avg_wire_size, 2650 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2651 IXGBE_ITR_ADAPTIVE_MIN_INC; 2652 break; 2653 case IXGBE_LINK_SPEED_2_5GB_FULL: 2654 case IXGBE_LINK_SPEED_1GB_FULL: 2655 case IXGBE_LINK_SPEED_10_FULL: 2656 itr += DIV_ROUND_UP(avg_wire_size, 2657 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2658 IXGBE_ITR_ADAPTIVE_MIN_INC; 2659 break; 2660 } 2661 2662 clear_counts: 2663 /* write back value */ 2664 ring_container->itr = itr; 2665 2666 /* next update should occur within next jiffy */ 2667 ring_container->next_update = next_update + 1; 2668 2669 ring_container->total_bytes = 0; 2670 ring_container->total_packets = 0; 2671 } 2672 2673 /** 2674 * ixgbe_write_eitr - write EITR register in hardware specific way 2675 * @q_vector: structure containing interrupt and ring information 2676 * 2677 * This function is made to be called by ethtool and by the driver 2678 * when it needs to update EITR registers at runtime. Hardware 2679 * specific quirks/differences are taken care of here. 2680 */ 2681 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2682 { 2683 struct ixgbe_adapter *adapter = q_vector->adapter; 2684 struct ixgbe_hw *hw = &adapter->hw; 2685 int v_idx = q_vector->v_idx; 2686 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2687 2688 switch (adapter->hw.mac.type) { 2689 case ixgbe_mac_82598EB: 2690 /* must write high and low 16 bits to reset counter */ 2691 itr_reg |= (itr_reg << 16); 2692 break; 2693 case ixgbe_mac_82599EB: 2694 case ixgbe_mac_X540: 2695 case ixgbe_mac_X550: 2696 case ixgbe_mac_X550EM_x: 2697 case ixgbe_mac_x550em_a: 2698 /* 2699 * set the WDIS bit to not clear the timer bits and cause an 2700 * immediate assertion of the interrupt 2701 */ 2702 itr_reg |= IXGBE_EITR_CNT_WDIS; 2703 break; 2704 default: 2705 break; 2706 } 2707 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2708 } 2709 2710 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2711 { 2712 u32 new_itr; 2713 2714 ixgbe_update_itr(q_vector, &q_vector->tx); 2715 ixgbe_update_itr(q_vector, &q_vector->rx); 2716 2717 /* use the smallest value of new ITR delay calculations */ 2718 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2719 2720 /* Clear latency flag if set, shift into correct position */ 2721 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2722 new_itr <<= 2; 2723 2724 if (new_itr != q_vector->itr) { 2725 /* save the algorithm value here */ 2726 q_vector->itr = new_itr; 2727 2728 ixgbe_write_eitr(q_vector); 2729 } 2730 } 2731 2732 /** 2733 * ixgbe_check_overtemp_subtask - check for over temperature 2734 * @adapter: pointer to adapter 2735 **/ 2736 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2737 { 2738 struct ixgbe_hw *hw = &adapter->hw; 2739 u32 eicr = adapter->interrupt_event; 2740 s32 rc; 2741 2742 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2743 return; 2744 2745 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2746 return; 2747 2748 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2749 2750 switch (hw->device_id) { 2751 case IXGBE_DEV_ID_82599_T3_LOM: 2752 /* 2753 * Since the warning interrupt is for both ports 2754 * we don't have to check if: 2755 * - This interrupt wasn't for our port. 2756 * - We may have missed the interrupt so always have to 2757 * check if we got a LSC 2758 */ 2759 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2760 !(eicr & IXGBE_EICR_LSC)) 2761 return; 2762 2763 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2764 u32 speed; 2765 bool link_up = false; 2766 2767 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2768 2769 if (link_up) 2770 return; 2771 } 2772 2773 /* Check if this is not due to overtemp */ 2774 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2775 return; 2776 2777 break; 2778 case IXGBE_DEV_ID_X550EM_A_1G_T: 2779 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2780 rc = hw->phy.ops.check_overtemp(hw); 2781 if (rc != IXGBE_ERR_OVERTEMP) 2782 return; 2783 break; 2784 default: 2785 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2786 return; 2787 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2788 return; 2789 break; 2790 } 2791 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2792 2793 adapter->interrupt_event = 0; 2794 } 2795 2796 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2797 { 2798 struct ixgbe_hw *hw = &adapter->hw; 2799 2800 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2801 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2802 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2803 /* write to clear the interrupt */ 2804 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2805 } 2806 } 2807 2808 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2809 { 2810 struct ixgbe_hw *hw = &adapter->hw; 2811 2812 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2813 return; 2814 2815 switch (adapter->hw.mac.type) { 2816 case ixgbe_mac_82599EB: 2817 /* 2818 * Need to check link state so complete overtemp check 2819 * on service task 2820 */ 2821 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2822 (eicr & IXGBE_EICR_LSC)) && 2823 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2824 adapter->interrupt_event = eicr; 2825 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2826 ixgbe_service_event_schedule(adapter); 2827 return; 2828 } 2829 return; 2830 case ixgbe_mac_x550em_a: 2831 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2832 adapter->interrupt_event = eicr; 2833 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2834 ixgbe_service_event_schedule(adapter); 2835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2836 IXGBE_EICR_GPI_SDP0_X550EM_a); 2837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2838 IXGBE_EICR_GPI_SDP0_X550EM_a); 2839 } 2840 return; 2841 case ixgbe_mac_X550: 2842 case ixgbe_mac_X540: 2843 if (!(eicr & IXGBE_EICR_TS)) 2844 return; 2845 break; 2846 default: 2847 return; 2848 } 2849 2850 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2851 } 2852 2853 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2854 { 2855 switch (hw->mac.type) { 2856 case ixgbe_mac_82598EB: 2857 if (hw->phy.type == ixgbe_phy_nl) 2858 return true; 2859 return false; 2860 case ixgbe_mac_82599EB: 2861 case ixgbe_mac_X550EM_x: 2862 case ixgbe_mac_x550em_a: 2863 switch (hw->mac.ops.get_media_type(hw)) { 2864 case ixgbe_media_type_fiber: 2865 case ixgbe_media_type_fiber_qsfp: 2866 return true; 2867 default: 2868 return false; 2869 } 2870 default: 2871 return false; 2872 } 2873 } 2874 2875 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2876 { 2877 struct ixgbe_hw *hw = &adapter->hw; 2878 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2879 2880 if (!ixgbe_is_sfp(hw)) 2881 return; 2882 2883 /* Later MAC's use different SDP */ 2884 if (hw->mac.type >= ixgbe_mac_X540) 2885 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2886 2887 if (eicr & eicr_mask) { 2888 /* Clear the interrupt */ 2889 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2890 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2891 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2892 adapter->sfp_poll_time = 0; 2893 ixgbe_service_event_schedule(adapter); 2894 } 2895 } 2896 2897 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2898 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2899 /* Clear the interrupt */ 2900 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2901 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2902 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2903 ixgbe_service_event_schedule(adapter); 2904 } 2905 } 2906 } 2907 2908 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2909 { 2910 struct ixgbe_hw *hw = &adapter->hw; 2911 2912 adapter->lsc_int++; 2913 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2914 adapter->link_check_timeout = jiffies; 2915 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2916 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2917 IXGBE_WRITE_FLUSH(hw); 2918 ixgbe_service_event_schedule(adapter); 2919 } 2920 } 2921 2922 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2923 u64 qmask) 2924 { 2925 u32 mask; 2926 struct ixgbe_hw *hw = &adapter->hw; 2927 2928 switch (hw->mac.type) { 2929 case ixgbe_mac_82598EB: 2930 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2931 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2932 break; 2933 case ixgbe_mac_82599EB: 2934 case ixgbe_mac_X540: 2935 case ixgbe_mac_X550: 2936 case ixgbe_mac_X550EM_x: 2937 case ixgbe_mac_x550em_a: 2938 mask = (qmask & 0xFFFFFFFF); 2939 if (mask) 2940 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2941 mask = (qmask >> 32); 2942 if (mask) 2943 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2944 break; 2945 default: 2946 break; 2947 } 2948 /* skip the flush */ 2949 } 2950 2951 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2952 u64 qmask) 2953 { 2954 u32 mask; 2955 struct ixgbe_hw *hw = &adapter->hw; 2956 2957 switch (hw->mac.type) { 2958 case ixgbe_mac_82598EB: 2959 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2960 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2961 break; 2962 case ixgbe_mac_82599EB: 2963 case ixgbe_mac_X540: 2964 case ixgbe_mac_X550: 2965 case ixgbe_mac_X550EM_x: 2966 case ixgbe_mac_x550em_a: 2967 mask = (qmask & 0xFFFFFFFF); 2968 if (mask) 2969 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2970 mask = (qmask >> 32); 2971 if (mask) 2972 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2973 break; 2974 default: 2975 break; 2976 } 2977 /* skip the flush */ 2978 } 2979 2980 /** 2981 * ixgbe_irq_enable - Enable default interrupt generation settings 2982 * @adapter: board private structure 2983 * @queues: enable irqs for queues 2984 * @flush: flush register write 2985 **/ 2986 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2987 bool flush) 2988 { 2989 struct ixgbe_hw *hw = &adapter->hw; 2990 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2991 2992 /* don't reenable LSC while waiting for link */ 2993 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2994 mask &= ~IXGBE_EIMS_LSC; 2995 2996 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2997 switch (adapter->hw.mac.type) { 2998 case ixgbe_mac_82599EB: 2999 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3000 break; 3001 case ixgbe_mac_X540: 3002 case ixgbe_mac_X550: 3003 case ixgbe_mac_X550EM_x: 3004 case ixgbe_mac_x550em_a: 3005 mask |= IXGBE_EIMS_TS; 3006 break; 3007 default: 3008 break; 3009 } 3010 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3011 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3012 switch (adapter->hw.mac.type) { 3013 case ixgbe_mac_82599EB: 3014 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3015 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3016 /* fall through */ 3017 case ixgbe_mac_X540: 3018 case ixgbe_mac_X550: 3019 case ixgbe_mac_X550EM_x: 3020 case ixgbe_mac_x550em_a: 3021 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3022 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3023 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3024 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3025 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3026 mask |= IXGBE_EICR_GPI_SDP0_X540; 3027 mask |= IXGBE_EIMS_ECC; 3028 mask |= IXGBE_EIMS_MAILBOX; 3029 break; 3030 default: 3031 break; 3032 } 3033 3034 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3035 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3036 mask |= IXGBE_EIMS_FLOW_DIR; 3037 3038 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3039 if (queues) 3040 ixgbe_irq_enable_queues(adapter, ~0); 3041 if (flush) 3042 IXGBE_WRITE_FLUSH(&adapter->hw); 3043 } 3044 3045 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3046 { 3047 struct ixgbe_adapter *adapter = data; 3048 struct ixgbe_hw *hw = &adapter->hw; 3049 u32 eicr; 3050 3051 /* 3052 * Workaround for Silicon errata. Use clear-by-write instead 3053 * of clear-by-read. Reading with EICS will return the 3054 * interrupt causes without clearing, which later be done 3055 * with the write to EICR. 3056 */ 3057 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3058 3059 /* The lower 16bits of the EICR register are for the queue interrupts 3060 * which should be masked here in order to not accidentally clear them if 3061 * the bits are high when ixgbe_msix_other is called. There is a race 3062 * condition otherwise which results in possible performance loss 3063 * especially if the ixgbe_msix_other interrupt is triggering 3064 * consistently (as it would when PPS is turned on for the X540 device) 3065 */ 3066 eicr &= 0xFFFF0000; 3067 3068 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3069 3070 if (eicr & IXGBE_EICR_LSC) 3071 ixgbe_check_lsc(adapter); 3072 3073 if (eicr & IXGBE_EICR_MAILBOX) 3074 ixgbe_msg_task(adapter); 3075 3076 switch (hw->mac.type) { 3077 case ixgbe_mac_82599EB: 3078 case ixgbe_mac_X540: 3079 case ixgbe_mac_X550: 3080 case ixgbe_mac_X550EM_x: 3081 case ixgbe_mac_x550em_a: 3082 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3083 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3084 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3085 ixgbe_service_event_schedule(adapter); 3086 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3087 IXGBE_EICR_GPI_SDP0_X540); 3088 } 3089 if (eicr & IXGBE_EICR_ECC) { 3090 e_info(link, "Received ECC Err, initiating reset\n"); 3091 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3092 ixgbe_service_event_schedule(adapter); 3093 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3094 } 3095 /* Handle Flow Director Full threshold interrupt */ 3096 if (eicr & IXGBE_EICR_FLOW_DIR) { 3097 int reinit_count = 0; 3098 int i; 3099 for (i = 0; i < adapter->num_tx_queues; i++) { 3100 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3101 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3102 &ring->state)) 3103 reinit_count++; 3104 } 3105 if (reinit_count) { 3106 /* no more flow director interrupts until after init */ 3107 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3108 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3109 ixgbe_service_event_schedule(adapter); 3110 } 3111 } 3112 ixgbe_check_sfp_event(adapter, eicr); 3113 ixgbe_check_overtemp_event(adapter, eicr); 3114 break; 3115 default: 3116 break; 3117 } 3118 3119 ixgbe_check_fan_failure(adapter, eicr); 3120 3121 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3122 ixgbe_ptp_check_pps_event(adapter); 3123 3124 /* re-enable the original interrupt state, no lsc, no queues */ 3125 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3126 ixgbe_irq_enable(adapter, false, false); 3127 3128 return IRQ_HANDLED; 3129 } 3130 3131 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3132 { 3133 struct ixgbe_q_vector *q_vector = data; 3134 3135 /* EIAM disabled interrupts (on this vector) for us */ 3136 3137 if (q_vector->rx.ring || q_vector->tx.ring) 3138 napi_schedule_irqoff(&q_vector->napi); 3139 3140 return IRQ_HANDLED; 3141 } 3142 3143 /** 3144 * ixgbe_poll - NAPI Rx polling callback 3145 * @napi: structure for representing this polling device 3146 * @budget: how many packets driver is allowed to clean 3147 * 3148 * This function is used for legacy and MSI, NAPI mode 3149 **/ 3150 int ixgbe_poll(struct napi_struct *napi, int budget) 3151 { 3152 struct ixgbe_q_vector *q_vector = 3153 container_of(napi, struct ixgbe_q_vector, napi); 3154 struct ixgbe_adapter *adapter = q_vector->adapter; 3155 struct ixgbe_ring *ring; 3156 int per_ring_budget, work_done = 0; 3157 bool clean_complete = true; 3158 3159 #ifdef CONFIG_IXGBE_DCA 3160 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3161 ixgbe_update_dca(q_vector); 3162 #endif 3163 3164 ixgbe_for_each_ring(ring, q_vector->tx) { 3165 bool wd = ring->xsk_umem ? 3166 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3167 ixgbe_clean_tx_irq(q_vector, ring, budget); 3168 3169 if (!wd) 3170 clean_complete = false; 3171 } 3172 3173 /* Exit if we are called by netpoll */ 3174 if (budget <= 0) 3175 return budget; 3176 3177 /* attempt to distribute budget to each queue fairly, but don't allow 3178 * the budget to go below 1 because we'll exit polling */ 3179 if (q_vector->rx.count > 1) 3180 per_ring_budget = max(budget/q_vector->rx.count, 1); 3181 else 3182 per_ring_budget = budget; 3183 3184 ixgbe_for_each_ring(ring, q_vector->rx) { 3185 int cleaned = ring->xsk_umem ? 3186 ixgbe_clean_rx_irq_zc(q_vector, ring, 3187 per_ring_budget) : 3188 ixgbe_clean_rx_irq(q_vector, ring, 3189 per_ring_budget); 3190 3191 work_done += cleaned; 3192 if (cleaned >= per_ring_budget) 3193 clean_complete = false; 3194 } 3195 3196 /* If all work not completed, return budget and keep polling */ 3197 if (!clean_complete) 3198 return budget; 3199 3200 /* all work done, exit the polling mode */ 3201 if (likely(napi_complete_done(napi, work_done))) { 3202 if (adapter->rx_itr_setting & 1) 3203 ixgbe_set_itr(q_vector); 3204 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3205 ixgbe_irq_enable_queues(adapter, 3206 BIT_ULL(q_vector->v_idx)); 3207 } 3208 3209 return min(work_done, budget - 1); 3210 } 3211 3212 /** 3213 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3214 * @adapter: board private structure 3215 * 3216 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3217 * interrupts from the kernel. 3218 **/ 3219 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3220 { 3221 struct net_device *netdev = adapter->netdev; 3222 unsigned int ri = 0, ti = 0; 3223 int vector, err; 3224 3225 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3226 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3227 struct msix_entry *entry = &adapter->msix_entries[vector]; 3228 3229 if (q_vector->tx.ring && q_vector->rx.ring) { 3230 snprintf(q_vector->name, sizeof(q_vector->name), 3231 "%s-TxRx-%u", netdev->name, ri++); 3232 ti++; 3233 } else if (q_vector->rx.ring) { 3234 snprintf(q_vector->name, sizeof(q_vector->name), 3235 "%s-rx-%u", netdev->name, ri++); 3236 } else if (q_vector->tx.ring) { 3237 snprintf(q_vector->name, sizeof(q_vector->name), 3238 "%s-tx-%u", netdev->name, ti++); 3239 } else { 3240 /* skip this unused q_vector */ 3241 continue; 3242 } 3243 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3244 q_vector->name, q_vector); 3245 if (err) { 3246 e_err(probe, "request_irq failed for MSIX interrupt " 3247 "Error: %d\n", err); 3248 goto free_queue_irqs; 3249 } 3250 /* If Flow Director is enabled, set interrupt affinity */ 3251 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3252 /* assign the mask for this irq */ 3253 irq_set_affinity_hint(entry->vector, 3254 &q_vector->affinity_mask); 3255 } 3256 } 3257 3258 err = request_irq(adapter->msix_entries[vector].vector, 3259 ixgbe_msix_other, 0, netdev->name, adapter); 3260 if (err) { 3261 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3262 goto free_queue_irqs; 3263 } 3264 3265 return 0; 3266 3267 free_queue_irqs: 3268 while (vector) { 3269 vector--; 3270 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3271 NULL); 3272 free_irq(adapter->msix_entries[vector].vector, 3273 adapter->q_vector[vector]); 3274 } 3275 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3276 pci_disable_msix(adapter->pdev); 3277 kfree(adapter->msix_entries); 3278 adapter->msix_entries = NULL; 3279 return err; 3280 } 3281 3282 /** 3283 * ixgbe_intr - legacy mode Interrupt Handler 3284 * @irq: interrupt number 3285 * @data: pointer to a network interface device structure 3286 **/ 3287 static irqreturn_t ixgbe_intr(int irq, void *data) 3288 { 3289 struct ixgbe_adapter *adapter = data; 3290 struct ixgbe_hw *hw = &adapter->hw; 3291 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3292 u32 eicr; 3293 3294 /* 3295 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3296 * before the read of EICR. 3297 */ 3298 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3299 3300 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3301 * therefore no explicit interrupt disable is necessary */ 3302 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3303 if (!eicr) { 3304 /* 3305 * shared interrupt alert! 3306 * make sure interrupts are enabled because the read will 3307 * have disabled interrupts due to EIAM 3308 * finish the workaround of silicon errata on 82598. Unmask 3309 * the interrupt that we masked before the EICR read. 3310 */ 3311 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3312 ixgbe_irq_enable(adapter, true, true); 3313 return IRQ_NONE; /* Not our interrupt */ 3314 } 3315 3316 if (eicr & IXGBE_EICR_LSC) 3317 ixgbe_check_lsc(adapter); 3318 3319 switch (hw->mac.type) { 3320 case ixgbe_mac_82599EB: 3321 ixgbe_check_sfp_event(adapter, eicr); 3322 /* Fall through */ 3323 case ixgbe_mac_X540: 3324 case ixgbe_mac_X550: 3325 case ixgbe_mac_X550EM_x: 3326 case ixgbe_mac_x550em_a: 3327 if (eicr & IXGBE_EICR_ECC) { 3328 e_info(link, "Received ECC Err, initiating reset\n"); 3329 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3330 ixgbe_service_event_schedule(adapter); 3331 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3332 } 3333 ixgbe_check_overtemp_event(adapter, eicr); 3334 break; 3335 default: 3336 break; 3337 } 3338 3339 ixgbe_check_fan_failure(adapter, eicr); 3340 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3341 ixgbe_ptp_check_pps_event(adapter); 3342 3343 /* would disable interrupts here but EIAM disabled it */ 3344 napi_schedule_irqoff(&q_vector->napi); 3345 3346 /* 3347 * re-enable link(maybe) and non-queue interrupts, no flush. 3348 * ixgbe_poll will re-enable the queue interrupts 3349 */ 3350 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3351 ixgbe_irq_enable(adapter, false, false); 3352 3353 return IRQ_HANDLED; 3354 } 3355 3356 /** 3357 * ixgbe_request_irq - initialize interrupts 3358 * @adapter: board private structure 3359 * 3360 * Attempts to configure interrupts using the best available 3361 * capabilities of the hardware and kernel. 3362 **/ 3363 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3364 { 3365 struct net_device *netdev = adapter->netdev; 3366 int err; 3367 3368 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3369 err = ixgbe_request_msix_irqs(adapter); 3370 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3371 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3372 netdev->name, adapter); 3373 else 3374 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3375 netdev->name, adapter); 3376 3377 if (err) 3378 e_err(probe, "request_irq failed, Error %d\n", err); 3379 3380 return err; 3381 } 3382 3383 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3384 { 3385 int vector; 3386 3387 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3388 free_irq(adapter->pdev->irq, adapter); 3389 return; 3390 } 3391 3392 if (!adapter->msix_entries) 3393 return; 3394 3395 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3396 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3397 struct msix_entry *entry = &adapter->msix_entries[vector]; 3398 3399 /* free only the irqs that were actually requested */ 3400 if (!q_vector->rx.ring && !q_vector->tx.ring) 3401 continue; 3402 3403 /* clear the affinity_mask in the IRQ descriptor */ 3404 irq_set_affinity_hint(entry->vector, NULL); 3405 3406 free_irq(entry->vector, q_vector); 3407 } 3408 3409 free_irq(adapter->msix_entries[vector].vector, adapter); 3410 } 3411 3412 /** 3413 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3414 * @adapter: board private structure 3415 **/ 3416 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3417 { 3418 switch (adapter->hw.mac.type) { 3419 case ixgbe_mac_82598EB: 3420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3421 break; 3422 case ixgbe_mac_82599EB: 3423 case ixgbe_mac_X540: 3424 case ixgbe_mac_X550: 3425 case ixgbe_mac_X550EM_x: 3426 case ixgbe_mac_x550em_a: 3427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3429 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3430 break; 3431 default: 3432 break; 3433 } 3434 IXGBE_WRITE_FLUSH(&adapter->hw); 3435 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3436 int vector; 3437 3438 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3439 synchronize_irq(adapter->msix_entries[vector].vector); 3440 3441 synchronize_irq(adapter->msix_entries[vector++].vector); 3442 } else { 3443 synchronize_irq(adapter->pdev->irq); 3444 } 3445 } 3446 3447 /** 3448 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3449 * @adapter: board private structure 3450 * 3451 **/ 3452 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3453 { 3454 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3455 3456 ixgbe_write_eitr(q_vector); 3457 3458 ixgbe_set_ivar(adapter, 0, 0, 0); 3459 ixgbe_set_ivar(adapter, 1, 0, 0); 3460 3461 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3462 } 3463 3464 /** 3465 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3466 * @adapter: board private structure 3467 * @ring: structure containing ring specific data 3468 * 3469 * Configure the Tx descriptor ring after a reset. 3470 **/ 3471 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3472 struct ixgbe_ring *ring) 3473 { 3474 struct ixgbe_hw *hw = &adapter->hw; 3475 u64 tdba = ring->dma; 3476 int wait_loop = 10; 3477 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3478 u8 reg_idx = ring->reg_idx; 3479 3480 ring->xsk_umem = NULL; 3481 if (ring_is_xdp(ring)) 3482 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 3483 3484 /* disable queue to avoid issues while updating state */ 3485 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3486 IXGBE_WRITE_FLUSH(hw); 3487 3488 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3489 (tdba & DMA_BIT_MASK(32))); 3490 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3491 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3492 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3493 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3494 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3495 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3496 3497 /* 3498 * set WTHRESH to encourage burst writeback, it should not be set 3499 * higher than 1 when: 3500 * - ITR is 0 as it could cause false TX hangs 3501 * - ITR is set to > 100k int/sec and BQL is enabled 3502 * 3503 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3504 * to or less than the number of on chip descriptors, which is 3505 * currently 40. 3506 */ 3507 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3508 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3509 else 3510 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3511 3512 /* 3513 * Setting PTHRESH to 32 both improves performance 3514 * and avoids a TX hang with DFP enabled 3515 */ 3516 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3517 32; /* PTHRESH = 32 */ 3518 3519 /* reinitialize flowdirector state */ 3520 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3521 ring->atr_sample_rate = adapter->atr_sample_rate; 3522 ring->atr_count = 0; 3523 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3524 } else { 3525 ring->atr_sample_rate = 0; 3526 } 3527 3528 /* initialize XPS */ 3529 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3530 struct ixgbe_q_vector *q_vector = ring->q_vector; 3531 3532 if (q_vector) 3533 netif_set_xps_queue(ring->netdev, 3534 &q_vector->affinity_mask, 3535 ring->queue_index); 3536 } 3537 3538 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3539 3540 /* reinitialize tx_buffer_info */ 3541 memset(ring->tx_buffer_info, 0, 3542 sizeof(struct ixgbe_tx_buffer) * ring->count); 3543 3544 /* enable queue */ 3545 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3546 3547 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3548 if (hw->mac.type == ixgbe_mac_82598EB && 3549 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3550 return; 3551 3552 /* poll to verify queue is enabled */ 3553 do { 3554 usleep_range(1000, 2000); 3555 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3556 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3557 if (!wait_loop) 3558 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3559 } 3560 3561 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3562 { 3563 struct ixgbe_hw *hw = &adapter->hw; 3564 u32 rttdcs, mtqc; 3565 u8 tcs = adapter->hw_tcs; 3566 3567 if (hw->mac.type == ixgbe_mac_82598EB) 3568 return; 3569 3570 /* disable the arbiter while setting MTQC */ 3571 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3572 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3573 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3574 3575 /* set transmit pool layout */ 3576 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3577 mtqc = IXGBE_MTQC_VT_ENA; 3578 if (tcs > 4) 3579 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3580 else if (tcs > 1) 3581 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3582 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3583 IXGBE_82599_VMDQ_4Q_MASK) 3584 mtqc |= IXGBE_MTQC_32VF; 3585 else 3586 mtqc |= IXGBE_MTQC_64VF; 3587 } else { 3588 if (tcs > 4) { 3589 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3590 } else if (tcs > 1) { 3591 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3592 } else { 3593 u8 max_txq = adapter->num_tx_queues + 3594 adapter->num_xdp_queues; 3595 if (max_txq > 63) 3596 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3597 else 3598 mtqc = IXGBE_MTQC_64Q_1PB; 3599 } 3600 } 3601 3602 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3603 3604 /* Enable Security TX Buffer IFG for multiple pb */ 3605 if (tcs) { 3606 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3607 sectx |= IXGBE_SECTX_DCB; 3608 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3609 } 3610 3611 /* re-enable the arbiter */ 3612 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3613 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3614 } 3615 3616 /** 3617 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3618 * @adapter: board private structure 3619 * 3620 * Configure the Tx unit of the MAC after a reset. 3621 **/ 3622 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3623 { 3624 struct ixgbe_hw *hw = &adapter->hw; 3625 u32 dmatxctl; 3626 u32 i; 3627 3628 ixgbe_setup_mtqc(adapter); 3629 3630 if (hw->mac.type != ixgbe_mac_82598EB) { 3631 /* DMATXCTL.EN must be before Tx queues are enabled */ 3632 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3633 dmatxctl |= IXGBE_DMATXCTL_TE; 3634 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3635 } 3636 3637 /* Setup the HW Tx Head and Tail descriptor pointers */ 3638 for (i = 0; i < adapter->num_tx_queues; i++) 3639 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3640 for (i = 0; i < adapter->num_xdp_queues; i++) 3641 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3642 } 3643 3644 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3645 struct ixgbe_ring *ring) 3646 { 3647 struct ixgbe_hw *hw = &adapter->hw; 3648 u8 reg_idx = ring->reg_idx; 3649 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3650 3651 srrctl |= IXGBE_SRRCTL_DROP_EN; 3652 3653 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3654 } 3655 3656 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3657 struct ixgbe_ring *ring) 3658 { 3659 struct ixgbe_hw *hw = &adapter->hw; 3660 u8 reg_idx = ring->reg_idx; 3661 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3662 3663 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3664 3665 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3666 } 3667 3668 #ifdef CONFIG_IXGBE_DCB 3669 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3670 #else 3671 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3672 #endif 3673 { 3674 int i; 3675 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3676 3677 if (adapter->ixgbe_ieee_pfc) 3678 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3679 3680 /* 3681 * We should set the drop enable bit if: 3682 * SR-IOV is enabled 3683 * or 3684 * Number of Rx queues > 1 and flow control is disabled 3685 * 3686 * This allows us to avoid head of line blocking for security 3687 * and performance reasons. 3688 */ 3689 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3690 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3691 for (i = 0; i < adapter->num_rx_queues; i++) 3692 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3693 } else { 3694 for (i = 0; i < adapter->num_rx_queues; i++) 3695 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3696 } 3697 } 3698 3699 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3700 3701 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3702 struct ixgbe_ring *rx_ring) 3703 { 3704 struct ixgbe_hw *hw = &adapter->hw; 3705 u32 srrctl; 3706 u8 reg_idx = rx_ring->reg_idx; 3707 3708 if (hw->mac.type == ixgbe_mac_82598EB) { 3709 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3710 3711 /* 3712 * if VMDq is not active we must program one srrctl register 3713 * per RSS queue since we have enabled RDRXCTL.MVMEN 3714 */ 3715 reg_idx &= mask; 3716 } 3717 3718 /* configure header buffer length, needed for RSC */ 3719 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3720 3721 /* configure the packet buffer length */ 3722 if (rx_ring->xsk_umem) { 3723 u32 xsk_buf_len = rx_ring->xsk_umem->chunk_size_nohr - 3724 XDP_PACKET_HEADROOM; 3725 3726 /* If the MAC support setting RXDCTL.RLPML, the 3727 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3728 * RXDCTL.RLPML is set to the actual UMEM buffer 3729 * size. If not, then we are stuck with a 1k buffer 3730 * size resolution. In this case frames larger than 3731 * the UMEM buffer size viewed in a 1k resolution will 3732 * be dropped. 3733 */ 3734 if (hw->mac.type != ixgbe_mac_82599EB) 3735 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3736 else 3737 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3738 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3739 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3740 } else { 3741 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3742 } 3743 3744 /* configure descriptor type */ 3745 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3746 3747 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3748 } 3749 3750 /** 3751 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3752 * @adapter: device handle 3753 * 3754 * - 82598/82599/X540: 128 3755 * - X550(non-SRIOV mode): 512 3756 * - X550(SRIOV mode): 64 3757 */ 3758 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3759 { 3760 if (adapter->hw.mac.type < ixgbe_mac_X550) 3761 return 128; 3762 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3763 return 64; 3764 else 3765 return 512; 3766 } 3767 3768 /** 3769 * ixgbe_store_key - Write the RSS key to HW 3770 * @adapter: device handle 3771 * 3772 * Write the RSS key stored in adapter.rss_key to HW. 3773 */ 3774 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3775 { 3776 struct ixgbe_hw *hw = &adapter->hw; 3777 int i; 3778 3779 for (i = 0; i < 10; i++) 3780 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3781 } 3782 3783 /** 3784 * ixgbe_init_rss_key - Initialize adapter RSS key 3785 * @adapter: device handle 3786 * 3787 * Allocates and initializes the RSS key if it is not allocated. 3788 **/ 3789 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3790 { 3791 u32 *rss_key; 3792 3793 if (!adapter->rss_key) { 3794 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3795 if (unlikely(!rss_key)) 3796 return -ENOMEM; 3797 3798 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3799 adapter->rss_key = rss_key; 3800 } 3801 3802 return 0; 3803 } 3804 3805 /** 3806 * ixgbe_store_reta - Write the RETA table to HW 3807 * @adapter: device handle 3808 * 3809 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3810 */ 3811 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3812 { 3813 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3814 struct ixgbe_hw *hw = &adapter->hw; 3815 u32 reta = 0; 3816 u32 indices_multi; 3817 u8 *indir_tbl = adapter->rss_indir_tbl; 3818 3819 /* Fill out the redirection table as follows: 3820 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3821 * indices. 3822 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3823 * - X550: 8 bit wide entries containing 6 bit RSS index 3824 */ 3825 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3826 indices_multi = 0x11; 3827 else 3828 indices_multi = 0x1; 3829 3830 /* Write redirection table to HW */ 3831 for (i = 0; i < reta_entries; i++) { 3832 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3833 if ((i & 3) == 3) { 3834 if (i < 128) 3835 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3836 else 3837 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3838 reta); 3839 reta = 0; 3840 } 3841 } 3842 } 3843 3844 /** 3845 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3846 * @adapter: device handle 3847 * 3848 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3849 */ 3850 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3851 { 3852 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3853 struct ixgbe_hw *hw = &adapter->hw; 3854 u32 vfreta = 0; 3855 3856 /* Write redirection table to HW */ 3857 for (i = 0; i < reta_entries; i++) { 3858 u16 pool = adapter->num_rx_pools; 3859 3860 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3861 if ((i & 3) != 3) 3862 continue; 3863 3864 while (pool--) 3865 IXGBE_WRITE_REG(hw, 3866 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3867 vfreta); 3868 vfreta = 0; 3869 } 3870 } 3871 3872 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3873 { 3874 u32 i, j; 3875 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3876 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3877 3878 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3879 * make full use of any rings they may have. We will use the 3880 * PSRTYPE register to control how many rings we use within the PF. 3881 */ 3882 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3883 rss_i = 4; 3884 3885 /* Fill out hash function seeds */ 3886 ixgbe_store_key(adapter); 3887 3888 /* Fill out redirection table */ 3889 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3890 3891 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3892 if (j == rss_i) 3893 j = 0; 3894 3895 adapter->rss_indir_tbl[i] = j; 3896 } 3897 3898 ixgbe_store_reta(adapter); 3899 } 3900 3901 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3902 { 3903 struct ixgbe_hw *hw = &adapter->hw; 3904 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3905 int i, j; 3906 3907 /* Fill out hash function seeds */ 3908 for (i = 0; i < 10; i++) { 3909 u16 pool = adapter->num_rx_pools; 3910 3911 while (pool--) 3912 IXGBE_WRITE_REG(hw, 3913 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3914 *(adapter->rss_key + i)); 3915 } 3916 3917 /* Fill out the redirection table */ 3918 for (i = 0, j = 0; i < 64; i++, j++) { 3919 if (j == rss_i) 3920 j = 0; 3921 3922 adapter->rss_indir_tbl[i] = j; 3923 } 3924 3925 ixgbe_store_vfreta(adapter); 3926 } 3927 3928 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3929 { 3930 struct ixgbe_hw *hw = &adapter->hw; 3931 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3932 u32 rxcsum; 3933 3934 /* Disable indicating checksum in descriptor, enables RSS hash */ 3935 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3936 rxcsum |= IXGBE_RXCSUM_PCSD; 3937 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3938 3939 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3940 if (adapter->ring_feature[RING_F_RSS].mask) 3941 mrqc = IXGBE_MRQC_RSSEN; 3942 } else { 3943 u8 tcs = adapter->hw_tcs; 3944 3945 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3946 if (tcs > 4) 3947 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3948 else if (tcs > 1) 3949 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3950 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3951 IXGBE_82599_VMDQ_4Q_MASK) 3952 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3953 else 3954 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3955 3956 /* Enable L3/L4 for Tx Switched packets only for X550, 3957 * older devices do not support this feature 3958 */ 3959 if (hw->mac.type >= ixgbe_mac_X550) 3960 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3961 } else { 3962 if (tcs > 4) 3963 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3964 else if (tcs > 1) 3965 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3966 else 3967 mrqc = IXGBE_MRQC_RSSEN; 3968 } 3969 } 3970 3971 /* Perform hash on these packet types */ 3972 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3973 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3974 IXGBE_MRQC_RSS_FIELD_IPV6 | 3975 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3976 3977 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3978 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3979 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3980 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3981 3982 if ((hw->mac.type >= ixgbe_mac_X550) && 3983 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3984 u16 pool = adapter->num_rx_pools; 3985 3986 /* Enable VF RSS mode */ 3987 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3988 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3989 3990 /* Setup RSS through the VF registers */ 3991 ixgbe_setup_vfreta(adapter); 3992 vfmrqc = IXGBE_MRQC_RSSEN; 3993 vfmrqc |= rss_field; 3994 3995 while (pool--) 3996 IXGBE_WRITE_REG(hw, 3997 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3998 vfmrqc); 3999 } else { 4000 ixgbe_setup_reta(adapter); 4001 mrqc |= rss_field; 4002 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4003 } 4004 } 4005 4006 /** 4007 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4008 * @adapter: address of board private structure 4009 * @ring: structure containing ring specific data 4010 **/ 4011 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4012 struct ixgbe_ring *ring) 4013 { 4014 struct ixgbe_hw *hw = &adapter->hw; 4015 u32 rscctrl; 4016 u8 reg_idx = ring->reg_idx; 4017 4018 if (!ring_is_rsc_enabled(ring)) 4019 return; 4020 4021 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4022 rscctrl |= IXGBE_RSCCTL_RSCEN; 4023 /* 4024 * we must limit the number of descriptors so that the 4025 * total size of max desc * buf_len is not greater 4026 * than 65536 4027 */ 4028 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4029 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4030 } 4031 4032 #define IXGBE_MAX_RX_DESC_POLL 10 4033 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4034 struct ixgbe_ring *ring) 4035 { 4036 struct ixgbe_hw *hw = &adapter->hw; 4037 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4038 u32 rxdctl; 4039 u8 reg_idx = ring->reg_idx; 4040 4041 if (ixgbe_removed(hw->hw_addr)) 4042 return; 4043 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4044 if (hw->mac.type == ixgbe_mac_82598EB && 4045 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4046 return; 4047 4048 do { 4049 usleep_range(1000, 2000); 4050 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4051 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4052 4053 if (!wait_loop) { 4054 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4055 "the polling period\n", reg_idx); 4056 } 4057 } 4058 4059 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4060 struct ixgbe_ring *ring) 4061 { 4062 struct ixgbe_hw *hw = &adapter->hw; 4063 union ixgbe_adv_rx_desc *rx_desc; 4064 u64 rdba = ring->dma; 4065 u32 rxdctl; 4066 u8 reg_idx = ring->reg_idx; 4067 4068 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4069 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 4070 if (ring->xsk_umem) { 4071 ring->zca.free = ixgbe_zca_free; 4072 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4073 MEM_TYPE_ZERO_COPY, 4074 &ring->zca)); 4075 4076 } else { 4077 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4078 MEM_TYPE_PAGE_SHARED, NULL)); 4079 } 4080 4081 /* disable queue to avoid use of these values while updating state */ 4082 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4083 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4084 4085 /* write value back with RXDCTL.ENABLE bit cleared */ 4086 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4087 IXGBE_WRITE_FLUSH(hw); 4088 4089 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4090 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4091 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4092 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4093 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4094 IXGBE_WRITE_FLUSH(hw); 4095 4096 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4097 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4098 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4099 4100 ixgbe_configure_srrctl(adapter, ring); 4101 ixgbe_configure_rscctl(adapter, ring); 4102 4103 if (hw->mac.type == ixgbe_mac_82598EB) { 4104 /* 4105 * enable cache line friendly hardware writes: 4106 * PTHRESH=32 descriptors (half the internal cache), 4107 * this also removes ugly rx_no_buffer_count increment 4108 * HTHRESH=4 descriptors (to minimize latency on fetch) 4109 * WTHRESH=8 burst writeback up to two cache lines 4110 */ 4111 rxdctl &= ~0x3FFFFF; 4112 rxdctl |= 0x080420; 4113 #if (PAGE_SIZE < 8192) 4114 /* RXDCTL.RLPML does not work on 82599 */ 4115 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4116 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4117 IXGBE_RXDCTL_RLPML_EN); 4118 4119 /* Limit the maximum frame size so we don't overrun the skb. 4120 * This can happen in SRIOV mode when the MTU of the VF is 4121 * higher than the MTU of the PF. 4122 */ 4123 if (ring_uses_build_skb(ring) && 4124 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4125 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4126 IXGBE_RXDCTL_RLPML_EN; 4127 #endif 4128 } 4129 4130 if (ring->xsk_umem && hw->mac.type != ixgbe_mac_82599EB) { 4131 u32 xsk_buf_len = ring->xsk_umem->chunk_size_nohr - 4132 XDP_PACKET_HEADROOM; 4133 4134 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4135 IXGBE_RXDCTL_RLPML_EN); 4136 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4137 4138 ring->rx_buf_len = xsk_buf_len; 4139 } 4140 4141 /* initialize rx_buffer_info */ 4142 memset(ring->rx_buffer_info, 0, 4143 sizeof(struct ixgbe_rx_buffer) * ring->count); 4144 4145 /* initialize Rx descriptor 0 */ 4146 rx_desc = IXGBE_RX_DESC(ring, 0); 4147 rx_desc->wb.upper.length = 0; 4148 4149 /* enable receive descriptor ring */ 4150 rxdctl |= IXGBE_RXDCTL_ENABLE; 4151 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4152 4153 ixgbe_rx_desc_queue_enable(adapter, ring); 4154 if (ring->xsk_umem) 4155 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4156 else 4157 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4158 } 4159 4160 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4161 { 4162 struct ixgbe_hw *hw = &adapter->hw; 4163 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4164 u16 pool = adapter->num_rx_pools; 4165 4166 /* PSRTYPE must be initialized in non 82598 adapters */ 4167 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4168 IXGBE_PSRTYPE_UDPHDR | 4169 IXGBE_PSRTYPE_IPV4HDR | 4170 IXGBE_PSRTYPE_L2HDR | 4171 IXGBE_PSRTYPE_IPV6HDR; 4172 4173 if (hw->mac.type == ixgbe_mac_82598EB) 4174 return; 4175 4176 if (rss_i > 3) 4177 psrtype |= 2u << 29; 4178 else if (rss_i > 1) 4179 psrtype |= 1u << 29; 4180 4181 while (pool--) 4182 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4183 } 4184 4185 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4186 { 4187 struct ixgbe_hw *hw = &adapter->hw; 4188 u16 pool = adapter->num_rx_pools; 4189 u32 reg_offset, vf_shift, vmolr; 4190 u32 gcr_ext, vmdctl; 4191 int i; 4192 4193 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4194 return; 4195 4196 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4197 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4198 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4199 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4200 vmdctl |= IXGBE_VT_CTL_REPLEN; 4201 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4202 4203 /* accept untagged packets until a vlan tag is 4204 * specifically set for the VMDQ queue/pool 4205 */ 4206 vmolr = IXGBE_VMOLR_AUPE; 4207 while (pool--) 4208 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4209 4210 vf_shift = VMDQ_P(0) % 32; 4211 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4212 4213 /* Enable only the PF's pool for Tx/Rx */ 4214 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4215 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4216 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4217 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4218 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4219 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4220 4221 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4222 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4223 4224 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4225 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4226 4227 /* 4228 * Set up VF register offsets for selected VT Mode, 4229 * i.e. 32 or 64 VFs for SR-IOV 4230 */ 4231 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4232 case IXGBE_82599_VMDQ_8Q_MASK: 4233 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4234 break; 4235 case IXGBE_82599_VMDQ_4Q_MASK: 4236 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4237 break; 4238 default: 4239 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4240 break; 4241 } 4242 4243 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4244 4245 for (i = 0; i < adapter->num_vfs; i++) { 4246 /* configure spoof checking */ 4247 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4248 adapter->vfinfo[i].spoofchk_enabled); 4249 4250 /* Enable/Disable RSS query feature */ 4251 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4252 adapter->vfinfo[i].rss_query_enabled); 4253 } 4254 } 4255 4256 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4257 { 4258 struct ixgbe_hw *hw = &adapter->hw; 4259 struct net_device *netdev = adapter->netdev; 4260 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4261 struct ixgbe_ring *rx_ring; 4262 int i; 4263 u32 mhadd, hlreg0; 4264 4265 #ifdef IXGBE_FCOE 4266 /* adjust max frame to be able to do baby jumbo for FCoE */ 4267 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4268 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4269 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4270 4271 #endif /* IXGBE_FCOE */ 4272 4273 /* adjust max frame to be at least the size of a standard frame */ 4274 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4275 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4276 4277 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4278 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4279 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4280 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4281 4282 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4283 } 4284 4285 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4286 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4287 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4288 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4289 4290 /* 4291 * Setup the HW Rx Head and Tail Descriptor Pointers and 4292 * the Base and Length of the Rx Descriptor Ring 4293 */ 4294 for (i = 0; i < adapter->num_rx_queues; i++) { 4295 rx_ring = adapter->rx_ring[i]; 4296 4297 clear_ring_rsc_enabled(rx_ring); 4298 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4299 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4300 4301 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4302 set_ring_rsc_enabled(rx_ring); 4303 4304 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4305 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4306 4307 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4308 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4309 continue; 4310 4311 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4312 4313 #if (PAGE_SIZE < 8192) 4314 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4315 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4316 4317 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4318 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4319 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4320 #endif 4321 } 4322 } 4323 4324 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4325 { 4326 struct ixgbe_hw *hw = &adapter->hw; 4327 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4328 4329 switch (hw->mac.type) { 4330 case ixgbe_mac_82598EB: 4331 /* 4332 * For VMDq support of different descriptor types or 4333 * buffer sizes through the use of multiple SRRCTL 4334 * registers, RDRXCTL.MVMEN must be set to 1 4335 * 4336 * also, the manual doesn't mention it clearly but DCA hints 4337 * will only use queue 0's tags unless this bit is set. Side 4338 * effects of setting this bit are only that SRRCTL must be 4339 * fully programmed [0..15] 4340 */ 4341 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4342 break; 4343 case ixgbe_mac_X550: 4344 case ixgbe_mac_X550EM_x: 4345 case ixgbe_mac_x550em_a: 4346 if (adapter->num_vfs) 4347 rdrxctl |= IXGBE_RDRXCTL_PSP; 4348 /* fall through */ 4349 case ixgbe_mac_82599EB: 4350 case ixgbe_mac_X540: 4351 /* Disable RSC for ACK packets */ 4352 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4353 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4354 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4355 /* hardware requires some bits to be set by default */ 4356 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4357 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4358 break; 4359 default: 4360 /* We should do nothing since we don't know this hardware */ 4361 return; 4362 } 4363 4364 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4365 } 4366 4367 /** 4368 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4369 * @adapter: board private structure 4370 * 4371 * Configure the Rx unit of the MAC after a reset. 4372 **/ 4373 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4374 { 4375 struct ixgbe_hw *hw = &adapter->hw; 4376 int i; 4377 u32 rxctrl, rfctl; 4378 4379 /* disable receives while setting up the descriptors */ 4380 hw->mac.ops.disable_rx(hw); 4381 4382 ixgbe_setup_psrtype(adapter); 4383 ixgbe_setup_rdrxctl(adapter); 4384 4385 /* RSC Setup */ 4386 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4387 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4388 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4389 rfctl |= IXGBE_RFCTL_RSC_DIS; 4390 4391 /* disable NFS filtering */ 4392 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4393 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4394 4395 /* Program registers for the distribution of queues */ 4396 ixgbe_setup_mrqc(adapter); 4397 4398 /* set_rx_buffer_len must be called before ring initialization */ 4399 ixgbe_set_rx_buffer_len(adapter); 4400 4401 /* 4402 * Setup the HW Rx Head and Tail Descriptor Pointers and 4403 * the Base and Length of the Rx Descriptor Ring 4404 */ 4405 for (i = 0; i < adapter->num_rx_queues; i++) 4406 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4407 4408 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4409 /* disable drop enable for 82598 parts */ 4410 if (hw->mac.type == ixgbe_mac_82598EB) 4411 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4412 4413 /* enable all receives */ 4414 rxctrl |= IXGBE_RXCTRL_RXEN; 4415 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4416 } 4417 4418 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4419 __be16 proto, u16 vid) 4420 { 4421 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4422 struct ixgbe_hw *hw = &adapter->hw; 4423 4424 /* add VID to filter table */ 4425 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4426 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4427 4428 set_bit(vid, adapter->active_vlans); 4429 4430 return 0; 4431 } 4432 4433 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4434 { 4435 u32 vlvf; 4436 int idx; 4437 4438 /* short cut the special case */ 4439 if (vlan == 0) 4440 return 0; 4441 4442 /* Search for the vlan id in the VLVF entries */ 4443 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4444 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4445 if ((vlvf & VLAN_VID_MASK) == vlan) 4446 break; 4447 } 4448 4449 return idx; 4450 } 4451 4452 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4453 { 4454 struct ixgbe_hw *hw = &adapter->hw; 4455 u32 bits, word; 4456 int idx; 4457 4458 idx = ixgbe_find_vlvf_entry(hw, vid); 4459 if (!idx) 4460 return; 4461 4462 /* See if any other pools are set for this VLAN filter 4463 * entry other than the PF. 4464 */ 4465 word = idx * 2 + (VMDQ_P(0) / 32); 4466 bits = ~BIT(VMDQ_P(0) % 32); 4467 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4468 4469 /* Disable the filter so this falls into the default pool. */ 4470 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4471 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4472 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4473 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4474 } 4475 } 4476 4477 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4478 __be16 proto, u16 vid) 4479 { 4480 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4481 struct ixgbe_hw *hw = &adapter->hw; 4482 4483 /* remove VID from filter table */ 4484 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4485 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4486 4487 clear_bit(vid, adapter->active_vlans); 4488 4489 return 0; 4490 } 4491 4492 /** 4493 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4494 * @adapter: driver data 4495 */ 4496 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4497 { 4498 struct ixgbe_hw *hw = &adapter->hw; 4499 u32 vlnctrl; 4500 int i, j; 4501 4502 switch (hw->mac.type) { 4503 case ixgbe_mac_82598EB: 4504 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4505 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4506 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4507 break; 4508 case ixgbe_mac_82599EB: 4509 case ixgbe_mac_X540: 4510 case ixgbe_mac_X550: 4511 case ixgbe_mac_X550EM_x: 4512 case ixgbe_mac_x550em_a: 4513 for (i = 0; i < adapter->num_rx_queues; i++) { 4514 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4515 4516 if (!netif_is_ixgbe(ring->netdev)) 4517 continue; 4518 4519 j = ring->reg_idx; 4520 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4521 vlnctrl &= ~IXGBE_RXDCTL_VME; 4522 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4523 } 4524 break; 4525 default: 4526 break; 4527 } 4528 } 4529 4530 /** 4531 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4532 * @adapter: driver data 4533 */ 4534 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4535 { 4536 struct ixgbe_hw *hw = &adapter->hw; 4537 u32 vlnctrl; 4538 int i, j; 4539 4540 switch (hw->mac.type) { 4541 case ixgbe_mac_82598EB: 4542 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4543 vlnctrl |= IXGBE_VLNCTRL_VME; 4544 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4545 break; 4546 case ixgbe_mac_82599EB: 4547 case ixgbe_mac_X540: 4548 case ixgbe_mac_X550: 4549 case ixgbe_mac_X550EM_x: 4550 case ixgbe_mac_x550em_a: 4551 for (i = 0; i < adapter->num_rx_queues; i++) { 4552 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4553 4554 if (!netif_is_ixgbe(ring->netdev)) 4555 continue; 4556 4557 j = ring->reg_idx; 4558 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4559 vlnctrl |= IXGBE_RXDCTL_VME; 4560 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4561 } 4562 break; 4563 default: 4564 break; 4565 } 4566 } 4567 4568 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4569 { 4570 struct ixgbe_hw *hw = &adapter->hw; 4571 u32 vlnctrl, i; 4572 4573 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4574 4575 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4576 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4577 vlnctrl |= IXGBE_VLNCTRL_VFE; 4578 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4579 } else { 4580 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4581 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4582 return; 4583 } 4584 4585 /* Nothing to do for 82598 */ 4586 if (hw->mac.type == ixgbe_mac_82598EB) 4587 return; 4588 4589 /* We are already in VLAN promisc, nothing to do */ 4590 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4591 return; 4592 4593 /* Set flag so we don't redo unnecessary work */ 4594 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4595 4596 /* Add PF to all active pools */ 4597 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4598 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4599 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4600 4601 vlvfb |= BIT(VMDQ_P(0) % 32); 4602 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4603 } 4604 4605 /* Set all bits in the VLAN filter table array */ 4606 for (i = hw->mac.vft_size; i--;) 4607 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4608 } 4609 4610 #define VFTA_BLOCK_SIZE 8 4611 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4612 { 4613 struct ixgbe_hw *hw = &adapter->hw; 4614 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4615 u32 vid_start = vfta_offset * 32; 4616 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4617 u32 i, vid, word, bits; 4618 4619 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4620 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4621 4622 /* pull VLAN ID from VLVF */ 4623 vid = vlvf & VLAN_VID_MASK; 4624 4625 /* only concern outselves with a certain range */ 4626 if (vid < vid_start || vid >= vid_end) 4627 continue; 4628 4629 if (vlvf) { 4630 /* record VLAN ID in VFTA */ 4631 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4632 4633 /* if PF is part of this then continue */ 4634 if (test_bit(vid, adapter->active_vlans)) 4635 continue; 4636 } 4637 4638 /* remove PF from the pool */ 4639 word = i * 2 + VMDQ_P(0) / 32; 4640 bits = ~BIT(VMDQ_P(0) % 32); 4641 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4642 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4643 } 4644 4645 /* extract values from active_vlans and write back to VFTA */ 4646 for (i = VFTA_BLOCK_SIZE; i--;) { 4647 vid = (vfta_offset + i) * 32; 4648 word = vid / BITS_PER_LONG; 4649 bits = vid % BITS_PER_LONG; 4650 4651 vfta[i] |= adapter->active_vlans[word] >> bits; 4652 4653 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4654 } 4655 } 4656 4657 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4658 { 4659 struct ixgbe_hw *hw = &adapter->hw; 4660 u32 vlnctrl, i; 4661 4662 /* Set VLAN filtering to enabled */ 4663 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4664 vlnctrl |= IXGBE_VLNCTRL_VFE; 4665 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4666 4667 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4668 hw->mac.type == ixgbe_mac_82598EB) 4669 return; 4670 4671 /* We are not in VLAN promisc, nothing to do */ 4672 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4673 return; 4674 4675 /* Set flag so we don't redo unnecessary work */ 4676 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4677 4678 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4679 ixgbe_scrub_vfta(adapter, i); 4680 } 4681 4682 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4683 { 4684 u16 vid = 1; 4685 4686 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4687 4688 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4689 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4690 } 4691 4692 /** 4693 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4694 * @netdev: network interface device structure 4695 * 4696 * Writes multicast address list to the MTA hash table. 4697 * Returns: -ENOMEM on failure 4698 * 0 on no addresses written 4699 * X on writing X addresses to MTA 4700 **/ 4701 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4702 { 4703 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4704 struct ixgbe_hw *hw = &adapter->hw; 4705 4706 if (!netif_running(netdev)) 4707 return 0; 4708 4709 if (hw->mac.ops.update_mc_addr_list) 4710 hw->mac.ops.update_mc_addr_list(hw, netdev); 4711 else 4712 return -ENOMEM; 4713 4714 #ifdef CONFIG_PCI_IOV 4715 ixgbe_restore_vf_multicasts(adapter); 4716 #endif 4717 4718 return netdev_mc_count(netdev); 4719 } 4720 4721 #ifdef CONFIG_PCI_IOV 4722 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4723 { 4724 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4725 struct ixgbe_hw *hw = &adapter->hw; 4726 int i; 4727 4728 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4729 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4730 4731 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4732 hw->mac.ops.set_rar(hw, i, 4733 mac_table->addr, 4734 mac_table->pool, 4735 IXGBE_RAH_AV); 4736 else 4737 hw->mac.ops.clear_rar(hw, i); 4738 } 4739 } 4740 4741 #endif 4742 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4743 { 4744 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4745 struct ixgbe_hw *hw = &adapter->hw; 4746 int i; 4747 4748 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4749 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4750 continue; 4751 4752 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4753 4754 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4755 hw->mac.ops.set_rar(hw, i, 4756 mac_table->addr, 4757 mac_table->pool, 4758 IXGBE_RAH_AV); 4759 else 4760 hw->mac.ops.clear_rar(hw, i); 4761 } 4762 } 4763 4764 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4765 { 4766 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4767 struct ixgbe_hw *hw = &adapter->hw; 4768 int i; 4769 4770 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4771 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4772 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4773 } 4774 4775 ixgbe_sync_mac_table(adapter); 4776 } 4777 4778 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4779 { 4780 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4781 struct ixgbe_hw *hw = &adapter->hw; 4782 int i, count = 0; 4783 4784 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4785 /* do not count default RAR as available */ 4786 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4787 continue; 4788 4789 /* only count unused and addresses that belong to us */ 4790 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4791 if (mac_table->pool != pool) 4792 continue; 4793 } 4794 4795 count++; 4796 } 4797 4798 return count; 4799 } 4800 4801 /* this function destroys the first RAR entry */ 4802 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4803 { 4804 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4805 struct ixgbe_hw *hw = &adapter->hw; 4806 4807 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4808 mac_table->pool = VMDQ_P(0); 4809 4810 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4811 4812 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4813 IXGBE_RAH_AV); 4814 } 4815 4816 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4817 const u8 *addr, u16 pool) 4818 { 4819 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4820 struct ixgbe_hw *hw = &adapter->hw; 4821 int i; 4822 4823 if (is_zero_ether_addr(addr)) 4824 return -EINVAL; 4825 4826 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4827 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4828 continue; 4829 4830 ether_addr_copy(mac_table->addr, addr); 4831 mac_table->pool = pool; 4832 4833 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4834 IXGBE_MAC_STATE_IN_USE; 4835 4836 ixgbe_sync_mac_table(adapter); 4837 4838 return i; 4839 } 4840 4841 return -ENOMEM; 4842 } 4843 4844 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4845 const u8 *addr, u16 pool) 4846 { 4847 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4848 struct ixgbe_hw *hw = &adapter->hw; 4849 int i; 4850 4851 if (is_zero_ether_addr(addr)) 4852 return -EINVAL; 4853 4854 /* search table for addr, if found clear IN_USE flag and sync */ 4855 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4856 /* we can only delete an entry if it is in use */ 4857 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4858 continue; 4859 /* we only care about entries that belong to the given pool */ 4860 if (mac_table->pool != pool) 4861 continue; 4862 /* we only care about a specific MAC address */ 4863 if (!ether_addr_equal(addr, mac_table->addr)) 4864 continue; 4865 4866 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4867 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4868 4869 ixgbe_sync_mac_table(adapter); 4870 4871 return 0; 4872 } 4873 4874 return -ENOMEM; 4875 } 4876 4877 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4878 { 4879 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4880 int ret; 4881 4882 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4883 4884 return min_t(int, ret, 0); 4885 } 4886 4887 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4888 { 4889 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4890 4891 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4892 4893 return 0; 4894 } 4895 4896 /** 4897 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4898 * @netdev: network interface device structure 4899 * 4900 * The set_rx_method entry point is called whenever the unicast/multicast 4901 * address list or the network interface flags are updated. This routine is 4902 * responsible for configuring the hardware for proper unicast, multicast and 4903 * promiscuous mode. 4904 **/ 4905 void ixgbe_set_rx_mode(struct net_device *netdev) 4906 { 4907 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4908 struct ixgbe_hw *hw = &adapter->hw; 4909 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4910 netdev_features_t features = netdev->features; 4911 int count; 4912 4913 /* Check for Promiscuous and All Multicast modes */ 4914 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4915 4916 /* set all bits that we expect to always be set */ 4917 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4918 fctrl |= IXGBE_FCTRL_BAM; 4919 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4920 fctrl |= IXGBE_FCTRL_PMCF; 4921 4922 /* clear the bits we are changing the status of */ 4923 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4924 if (netdev->flags & IFF_PROMISC) { 4925 hw->addr_ctrl.user_set_promisc = true; 4926 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4927 vmolr |= IXGBE_VMOLR_MPE; 4928 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4929 } else { 4930 if (netdev->flags & IFF_ALLMULTI) { 4931 fctrl |= IXGBE_FCTRL_MPE; 4932 vmolr |= IXGBE_VMOLR_MPE; 4933 } 4934 hw->addr_ctrl.user_set_promisc = false; 4935 } 4936 4937 /* 4938 * Write addresses to available RAR registers, if there is not 4939 * sufficient space to store all the addresses then enable 4940 * unicast promiscuous mode 4941 */ 4942 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4943 fctrl |= IXGBE_FCTRL_UPE; 4944 vmolr |= IXGBE_VMOLR_ROPE; 4945 } 4946 4947 /* Write addresses to the MTA, if the attempt fails 4948 * then we should just turn on promiscuous mode so 4949 * that we can at least receive multicast traffic 4950 */ 4951 count = ixgbe_write_mc_addr_list(netdev); 4952 if (count < 0) { 4953 fctrl |= IXGBE_FCTRL_MPE; 4954 vmolr |= IXGBE_VMOLR_MPE; 4955 } else if (count) { 4956 vmolr |= IXGBE_VMOLR_ROMPE; 4957 } 4958 4959 if (hw->mac.type != ixgbe_mac_82598EB) { 4960 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4961 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4962 IXGBE_VMOLR_ROPE); 4963 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4964 } 4965 4966 /* This is useful for sniffing bad packets. */ 4967 if (features & NETIF_F_RXALL) { 4968 /* UPE and MPE will be handled by normal PROMISC logic 4969 * in e1000e_set_rx_mode */ 4970 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4971 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4972 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4973 4974 fctrl &= ~(IXGBE_FCTRL_DPF); 4975 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4976 } 4977 4978 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4979 4980 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4981 ixgbe_vlan_strip_enable(adapter); 4982 else 4983 ixgbe_vlan_strip_disable(adapter); 4984 4985 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4986 ixgbe_vlan_promisc_disable(adapter); 4987 else 4988 ixgbe_vlan_promisc_enable(adapter); 4989 } 4990 4991 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4992 { 4993 int q_idx; 4994 4995 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4996 napi_enable(&adapter->q_vector[q_idx]->napi); 4997 } 4998 4999 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5000 { 5001 int q_idx; 5002 5003 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5004 napi_disable(&adapter->q_vector[q_idx]->napi); 5005 } 5006 5007 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5008 { 5009 struct ixgbe_hw *hw = &adapter->hw; 5010 u32 vxlanctrl; 5011 5012 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5013 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5014 return; 5015 5016 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5017 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5018 5019 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5020 adapter->vxlan_port = 0; 5021 5022 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5023 adapter->geneve_port = 0; 5024 } 5025 5026 #ifdef CONFIG_IXGBE_DCB 5027 /** 5028 * ixgbe_configure_dcb - Configure DCB hardware 5029 * @adapter: ixgbe adapter struct 5030 * 5031 * This is called by the driver on open to configure the DCB hardware. 5032 * This is also called by the gennetlink interface when reconfiguring 5033 * the DCB state. 5034 */ 5035 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5036 { 5037 struct ixgbe_hw *hw = &adapter->hw; 5038 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5039 5040 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5041 if (hw->mac.type == ixgbe_mac_82598EB) 5042 netif_set_gso_max_size(adapter->netdev, 65536); 5043 return; 5044 } 5045 5046 if (hw->mac.type == ixgbe_mac_82598EB) 5047 netif_set_gso_max_size(adapter->netdev, 32768); 5048 5049 #ifdef IXGBE_FCOE 5050 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5051 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5052 #endif 5053 5054 /* reconfigure the hardware */ 5055 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5056 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5057 DCB_TX_CONFIG); 5058 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5059 DCB_RX_CONFIG); 5060 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5061 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5062 ixgbe_dcb_hw_ets(&adapter->hw, 5063 adapter->ixgbe_ieee_ets, 5064 max_frame); 5065 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5066 adapter->ixgbe_ieee_pfc->pfc_en, 5067 adapter->ixgbe_ieee_ets->prio_tc); 5068 } 5069 5070 /* Enable RSS Hash per TC */ 5071 if (hw->mac.type != ixgbe_mac_82598EB) { 5072 u32 msb = 0; 5073 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5074 5075 while (rss_i) { 5076 msb++; 5077 rss_i >>= 1; 5078 } 5079 5080 /* write msb to all 8 TCs in one write */ 5081 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5082 } 5083 } 5084 #endif 5085 5086 /* Additional bittime to account for IXGBE framing */ 5087 #define IXGBE_ETH_FRAMING 20 5088 5089 /** 5090 * ixgbe_hpbthresh - calculate high water mark for flow control 5091 * 5092 * @adapter: board private structure to calculate for 5093 * @pb: packet buffer to calculate 5094 */ 5095 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5096 { 5097 struct ixgbe_hw *hw = &adapter->hw; 5098 struct net_device *dev = adapter->netdev; 5099 int link, tc, kb, marker; 5100 u32 dv_id, rx_pba; 5101 5102 /* Calculate max LAN frame size */ 5103 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5104 5105 #ifdef IXGBE_FCOE 5106 /* FCoE traffic class uses FCOE jumbo frames */ 5107 if ((dev->features & NETIF_F_FCOE_MTU) && 5108 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5109 (pb == ixgbe_fcoe_get_tc(adapter))) 5110 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5111 #endif 5112 5113 /* Calculate delay value for device */ 5114 switch (hw->mac.type) { 5115 case ixgbe_mac_X540: 5116 case ixgbe_mac_X550: 5117 case ixgbe_mac_X550EM_x: 5118 case ixgbe_mac_x550em_a: 5119 dv_id = IXGBE_DV_X540(link, tc); 5120 break; 5121 default: 5122 dv_id = IXGBE_DV(link, tc); 5123 break; 5124 } 5125 5126 /* Loopback switch introduces additional latency */ 5127 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5128 dv_id += IXGBE_B2BT(tc); 5129 5130 /* Delay value is calculated in bit times convert to KB */ 5131 kb = IXGBE_BT2KB(dv_id); 5132 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5133 5134 marker = rx_pba - kb; 5135 5136 /* It is possible that the packet buffer is not large enough 5137 * to provide required headroom. In this case throw an error 5138 * to user and a do the best we can. 5139 */ 5140 if (marker < 0) { 5141 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5142 "headroom to support flow control." 5143 "Decrease MTU or number of traffic classes\n", pb); 5144 marker = tc + 1; 5145 } 5146 5147 return marker; 5148 } 5149 5150 /** 5151 * ixgbe_lpbthresh - calculate low water mark for for flow control 5152 * 5153 * @adapter: board private structure to calculate for 5154 * @pb: packet buffer to calculate 5155 */ 5156 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5157 { 5158 struct ixgbe_hw *hw = &adapter->hw; 5159 struct net_device *dev = adapter->netdev; 5160 int tc; 5161 u32 dv_id; 5162 5163 /* Calculate max LAN frame size */ 5164 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5165 5166 #ifdef IXGBE_FCOE 5167 /* FCoE traffic class uses FCOE jumbo frames */ 5168 if ((dev->features & NETIF_F_FCOE_MTU) && 5169 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5170 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5171 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5172 #endif 5173 5174 /* Calculate delay value for device */ 5175 switch (hw->mac.type) { 5176 case ixgbe_mac_X540: 5177 case ixgbe_mac_X550: 5178 case ixgbe_mac_X550EM_x: 5179 case ixgbe_mac_x550em_a: 5180 dv_id = IXGBE_LOW_DV_X540(tc); 5181 break; 5182 default: 5183 dv_id = IXGBE_LOW_DV(tc); 5184 break; 5185 } 5186 5187 /* Delay value is calculated in bit times convert to KB */ 5188 return IXGBE_BT2KB(dv_id); 5189 } 5190 5191 /* 5192 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5193 */ 5194 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5195 { 5196 struct ixgbe_hw *hw = &adapter->hw; 5197 int num_tc = adapter->hw_tcs; 5198 int i; 5199 5200 if (!num_tc) 5201 num_tc = 1; 5202 5203 for (i = 0; i < num_tc; i++) { 5204 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5205 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5206 5207 /* Low water marks must not be larger than high water marks */ 5208 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5209 hw->fc.low_water[i] = 0; 5210 } 5211 5212 for (; i < MAX_TRAFFIC_CLASS; i++) 5213 hw->fc.high_water[i] = 0; 5214 } 5215 5216 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5217 { 5218 struct ixgbe_hw *hw = &adapter->hw; 5219 int hdrm; 5220 u8 tc = adapter->hw_tcs; 5221 5222 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5223 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5224 hdrm = 32 << adapter->fdir_pballoc; 5225 else 5226 hdrm = 0; 5227 5228 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5229 ixgbe_pbthresh_setup(adapter); 5230 } 5231 5232 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5233 { 5234 struct ixgbe_hw *hw = &adapter->hw; 5235 struct hlist_node *node2; 5236 struct ixgbe_fdir_filter *filter; 5237 u64 action; 5238 5239 spin_lock(&adapter->fdir_perfect_lock); 5240 5241 if (!hlist_empty(&adapter->fdir_filter_list)) 5242 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5243 5244 hlist_for_each_entry_safe(filter, node2, 5245 &adapter->fdir_filter_list, fdir_node) { 5246 action = filter->action; 5247 if (action != IXGBE_FDIR_DROP_QUEUE && action != 0) 5248 action = 5249 (action >> ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF) - 1; 5250 5251 ixgbe_fdir_write_perfect_filter_82599(hw, 5252 &filter->filter, 5253 filter->sw_idx, 5254 (action == IXGBE_FDIR_DROP_QUEUE) ? 5255 IXGBE_FDIR_DROP_QUEUE : 5256 adapter->rx_ring[action]->reg_idx); 5257 } 5258 5259 spin_unlock(&adapter->fdir_perfect_lock); 5260 } 5261 5262 /** 5263 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5264 * @rx_ring: ring to free buffers from 5265 **/ 5266 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5267 { 5268 u16 i = rx_ring->next_to_clean; 5269 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5270 5271 if (rx_ring->xsk_umem) { 5272 ixgbe_xsk_clean_rx_ring(rx_ring); 5273 goto skip_free; 5274 } 5275 5276 /* Free all the Rx ring sk_buffs */ 5277 while (i != rx_ring->next_to_alloc) { 5278 if (rx_buffer->skb) { 5279 struct sk_buff *skb = rx_buffer->skb; 5280 if (IXGBE_CB(skb)->page_released) 5281 dma_unmap_page_attrs(rx_ring->dev, 5282 IXGBE_CB(skb)->dma, 5283 ixgbe_rx_pg_size(rx_ring), 5284 DMA_FROM_DEVICE, 5285 IXGBE_RX_DMA_ATTR); 5286 dev_kfree_skb(skb); 5287 } 5288 5289 /* Invalidate cache lines that may have been written to by 5290 * device so that we avoid corrupting memory. 5291 */ 5292 dma_sync_single_range_for_cpu(rx_ring->dev, 5293 rx_buffer->dma, 5294 rx_buffer->page_offset, 5295 ixgbe_rx_bufsz(rx_ring), 5296 DMA_FROM_DEVICE); 5297 5298 /* free resources associated with mapping */ 5299 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5300 ixgbe_rx_pg_size(rx_ring), 5301 DMA_FROM_DEVICE, 5302 IXGBE_RX_DMA_ATTR); 5303 __page_frag_cache_drain(rx_buffer->page, 5304 rx_buffer->pagecnt_bias); 5305 5306 i++; 5307 rx_buffer++; 5308 if (i == rx_ring->count) { 5309 i = 0; 5310 rx_buffer = rx_ring->rx_buffer_info; 5311 } 5312 } 5313 5314 skip_free: 5315 rx_ring->next_to_alloc = 0; 5316 rx_ring->next_to_clean = 0; 5317 rx_ring->next_to_use = 0; 5318 } 5319 5320 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5321 struct ixgbe_fwd_adapter *accel) 5322 { 5323 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5324 int num_tc = netdev_get_num_tc(adapter->netdev); 5325 struct net_device *vdev = accel->netdev; 5326 int i, baseq, err; 5327 5328 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5329 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5330 accel->pool, adapter->num_rx_pools, 5331 baseq, baseq + adapter->num_rx_queues_per_pool); 5332 5333 accel->rx_base_queue = baseq; 5334 accel->tx_base_queue = baseq; 5335 5336 /* record configuration for macvlan interface in vdev */ 5337 for (i = 0; i < num_tc; i++) 5338 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5339 i, rss_i, baseq + (rss_i * i)); 5340 5341 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5342 adapter->rx_ring[baseq + i]->netdev = vdev; 5343 5344 /* Guarantee all rings are updated before we update the 5345 * MAC address filter. 5346 */ 5347 wmb(); 5348 5349 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5350 * need to only treat it as an error value if it is negative. 5351 */ 5352 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5353 VMDQ_P(accel->pool)); 5354 if (err >= 0) 5355 return 0; 5356 5357 /* if we cannot add the MAC rule then disable the offload */ 5358 macvlan_release_l2fw_offload(vdev); 5359 5360 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5361 adapter->rx_ring[baseq + i]->netdev = NULL; 5362 5363 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5364 5365 /* unbind the queues and drop the subordinate channel config */ 5366 netdev_unbind_sb_channel(adapter->netdev, vdev); 5367 netdev_set_sb_channel(vdev, 0); 5368 5369 clear_bit(accel->pool, adapter->fwd_bitmask); 5370 kfree(accel); 5371 5372 return err; 5373 } 5374 5375 static int ixgbe_macvlan_up(struct net_device *vdev, void *data) 5376 { 5377 struct ixgbe_adapter *adapter = data; 5378 struct ixgbe_fwd_adapter *accel; 5379 5380 if (!netif_is_macvlan(vdev)) 5381 return 0; 5382 5383 accel = macvlan_accel_priv(vdev); 5384 if (!accel) 5385 return 0; 5386 5387 ixgbe_fwd_ring_up(adapter, accel); 5388 5389 return 0; 5390 } 5391 5392 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5393 { 5394 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5395 ixgbe_macvlan_up, adapter); 5396 } 5397 5398 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5399 { 5400 struct ixgbe_hw *hw = &adapter->hw; 5401 5402 ixgbe_configure_pb(adapter); 5403 #ifdef CONFIG_IXGBE_DCB 5404 ixgbe_configure_dcb(adapter); 5405 #endif 5406 /* 5407 * We must restore virtualization before VLANs or else 5408 * the VLVF registers will not be populated 5409 */ 5410 ixgbe_configure_virtualization(adapter); 5411 5412 ixgbe_set_rx_mode(adapter->netdev); 5413 ixgbe_restore_vlan(adapter); 5414 ixgbe_ipsec_restore(adapter); 5415 5416 switch (hw->mac.type) { 5417 case ixgbe_mac_82599EB: 5418 case ixgbe_mac_X540: 5419 hw->mac.ops.disable_rx_buff(hw); 5420 break; 5421 default: 5422 break; 5423 } 5424 5425 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5426 ixgbe_init_fdir_signature_82599(&adapter->hw, 5427 adapter->fdir_pballoc); 5428 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5429 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5430 adapter->fdir_pballoc); 5431 ixgbe_fdir_filter_restore(adapter); 5432 } 5433 5434 switch (hw->mac.type) { 5435 case ixgbe_mac_82599EB: 5436 case ixgbe_mac_X540: 5437 hw->mac.ops.enable_rx_buff(hw); 5438 break; 5439 default: 5440 break; 5441 } 5442 5443 #ifdef CONFIG_IXGBE_DCA 5444 /* configure DCA */ 5445 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5446 ixgbe_setup_dca(adapter); 5447 #endif /* CONFIG_IXGBE_DCA */ 5448 5449 #ifdef IXGBE_FCOE 5450 /* configure FCoE L2 filters, redirection table, and Rx control */ 5451 ixgbe_configure_fcoe(adapter); 5452 5453 #endif /* IXGBE_FCOE */ 5454 ixgbe_configure_tx(adapter); 5455 ixgbe_configure_rx(adapter); 5456 ixgbe_configure_dfwd(adapter); 5457 } 5458 5459 /** 5460 * ixgbe_sfp_link_config - set up SFP+ link 5461 * @adapter: pointer to private adapter struct 5462 **/ 5463 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5464 { 5465 /* 5466 * We are assuming the worst case scenario here, and that 5467 * is that an SFP was inserted/removed after the reset 5468 * but before SFP detection was enabled. As such the best 5469 * solution is to just start searching as soon as we start 5470 */ 5471 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5472 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5473 5474 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5475 adapter->sfp_poll_time = 0; 5476 } 5477 5478 /** 5479 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5480 * @hw: pointer to private hardware struct 5481 * 5482 * Returns 0 on success, negative on failure 5483 **/ 5484 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5485 { 5486 u32 speed; 5487 bool autoneg, link_up = false; 5488 int ret = IXGBE_ERR_LINK_SETUP; 5489 5490 if (hw->mac.ops.check_link) 5491 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5492 5493 if (ret) 5494 return ret; 5495 5496 speed = hw->phy.autoneg_advertised; 5497 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5498 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5499 &autoneg); 5500 if (ret) 5501 return ret; 5502 5503 if (hw->mac.ops.setup_link) 5504 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5505 5506 return ret; 5507 } 5508 5509 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5510 { 5511 struct ixgbe_hw *hw = &adapter->hw; 5512 u32 gpie = 0; 5513 5514 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5515 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5516 IXGBE_GPIE_OCD; 5517 gpie |= IXGBE_GPIE_EIAME; 5518 /* 5519 * use EIAM to auto-mask when MSI-X interrupt is asserted 5520 * this saves a register write for every interrupt 5521 */ 5522 switch (hw->mac.type) { 5523 case ixgbe_mac_82598EB: 5524 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5525 break; 5526 case ixgbe_mac_82599EB: 5527 case ixgbe_mac_X540: 5528 case ixgbe_mac_X550: 5529 case ixgbe_mac_X550EM_x: 5530 case ixgbe_mac_x550em_a: 5531 default: 5532 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5533 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5534 break; 5535 } 5536 } else { 5537 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5538 * specifically only auto mask tx and rx interrupts */ 5539 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5540 } 5541 5542 /* XXX: to interrupt immediately for EICS writes, enable this */ 5543 /* gpie |= IXGBE_GPIE_EIMEN; */ 5544 5545 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5546 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5547 5548 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5549 case IXGBE_82599_VMDQ_8Q_MASK: 5550 gpie |= IXGBE_GPIE_VTMODE_16; 5551 break; 5552 case IXGBE_82599_VMDQ_4Q_MASK: 5553 gpie |= IXGBE_GPIE_VTMODE_32; 5554 break; 5555 default: 5556 gpie |= IXGBE_GPIE_VTMODE_64; 5557 break; 5558 } 5559 } 5560 5561 /* Enable Thermal over heat sensor interrupt */ 5562 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5563 switch (adapter->hw.mac.type) { 5564 case ixgbe_mac_82599EB: 5565 gpie |= IXGBE_SDP0_GPIEN_8259X; 5566 break; 5567 default: 5568 break; 5569 } 5570 } 5571 5572 /* Enable fan failure interrupt */ 5573 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5574 gpie |= IXGBE_SDP1_GPIEN(hw); 5575 5576 switch (hw->mac.type) { 5577 case ixgbe_mac_82599EB: 5578 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5579 break; 5580 case ixgbe_mac_X550EM_x: 5581 case ixgbe_mac_x550em_a: 5582 gpie |= IXGBE_SDP0_GPIEN_X540; 5583 break; 5584 default: 5585 break; 5586 } 5587 5588 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5589 } 5590 5591 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5592 { 5593 struct ixgbe_hw *hw = &adapter->hw; 5594 int err; 5595 u32 ctrl_ext; 5596 5597 ixgbe_get_hw_control(adapter); 5598 ixgbe_setup_gpie(adapter); 5599 5600 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5601 ixgbe_configure_msix(adapter); 5602 else 5603 ixgbe_configure_msi_and_legacy(adapter); 5604 5605 /* enable the optics for 82599 SFP+ fiber */ 5606 if (hw->mac.ops.enable_tx_laser) 5607 hw->mac.ops.enable_tx_laser(hw); 5608 5609 if (hw->phy.ops.set_phy_power) 5610 hw->phy.ops.set_phy_power(hw, true); 5611 5612 smp_mb__before_atomic(); 5613 clear_bit(__IXGBE_DOWN, &adapter->state); 5614 ixgbe_napi_enable_all(adapter); 5615 5616 if (ixgbe_is_sfp(hw)) { 5617 ixgbe_sfp_link_config(adapter); 5618 } else { 5619 err = ixgbe_non_sfp_link_config(hw); 5620 if (err) 5621 e_err(probe, "link_config FAILED %d\n", err); 5622 } 5623 5624 /* clear any pending interrupts, may auto mask */ 5625 IXGBE_READ_REG(hw, IXGBE_EICR); 5626 ixgbe_irq_enable(adapter, true, true); 5627 5628 /* 5629 * If this adapter has a fan, check to see if we had a failure 5630 * before we enabled the interrupt. 5631 */ 5632 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5633 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5634 if (esdp & IXGBE_ESDP_SDP1) 5635 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5636 } 5637 5638 /* bring the link up in the watchdog, this could race with our first 5639 * link up interrupt but shouldn't be a problem */ 5640 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5641 adapter->link_check_timeout = jiffies; 5642 mod_timer(&adapter->service_timer, jiffies); 5643 5644 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5645 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5646 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5647 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5648 } 5649 5650 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5651 { 5652 WARN_ON(in_interrupt()); 5653 /* put off any impending NetWatchDogTimeout */ 5654 netif_trans_update(adapter->netdev); 5655 5656 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5657 usleep_range(1000, 2000); 5658 if (adapter->hw.phy.type == ixgbe_phy_fw) 5659 ixgbe_watchdog_link_is_down(adapter); 5660 ixgbe_down(adapter); 5661 /* 5662 * If SR-IOV enabled then wait a bit before bringing the adapter 5663 * back up to give the VFs time to respond to the reset. The 5664 * two second wait is based upon the watchdog timer cycle in 5665 * the VF driver. 5666 */ 5667 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5668 msleep(2000); 5669 ixgbe_up(adapter); 5670 clear_bit(__IXGBE_RESETTING, &adapter->state); 5671 } 5672 5673 void ixgbe_up(struct ixgbe_adapter *adapter) 5674 { 5675 /* hardware has been reset, we need to reload some things */ 5676 ixgbe_configure(adapter); 5677 5678 ixgbe_up_complete(adapter); 5679 } 5680 5681 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5682 { 5683 u16 devctl2; 5684 5685 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5686 5687 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5688 case IXGBE_PCIDEVCTRL2_17_34s: 5689 case IXGBE_PCIDEVCTRL2_4_8s: 5690 /* For now we cap the upper limit on delay to 2 seconds 5691 * as we end up going up to 34 seconds of delay in worst 5692 * case timeout value. 5693 */ 5694 case IXGBE_PCIDEVCTRL2_1_2s: 5695 return 2000000ul; /* 2.0 s */ 5696 case IXGBE_PCIDEVCTRL2_260_520ms: 5697 return 520000ul; /* 520 ms */ 5698 case IXGBE_PCIDEVCTRL2_65_130ms: 5699 return 130000ul; /* 130 ms */ 5700 case IXGBE_PCIDEVCTRL2_16_32ms: 5701 return 32000ul; /* 32 ms */ 5702 case IXGBE_PCIDEVCTRL2_1_2ms: 5703 return 2000ul; /* 2 ms */ 5704 case IXGBE_PCIDEVCTRL2_50_100us: 5705 return 100ul; /* 100 us */ 5706 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5707 return 32000ul; /* 32 ms */ 5708 default: 5709 break; 5710 } 5711 5712 /* We shouldn't need to hit this path, but just in case default as 5713 * though completion timeout is not supported and support 32ms. 5714 */ 5715 return 32000ul; 5716 } 5717 5718 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5719 { 5720 unsigned long wait_delay, delay_interval; 5721 struct ixgbe_hw *hw = &adapter->hw; 5722 int i, wait_loop; 5723 u32 rxdctl; 5724 5725 /* disable receives */ 5726 hw->mac.ops.disable_rx(hw); 5727 5728 if (ixgbe_removed(hw->hw_addr)) 5729 return; 5730 5731 /* disable all enabled Rx queues */ 5732 for (i = 0; i < adapter->num_rx_queues; i++) { 5733 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5734 u8 reg_idx = ring->reg_idx; 5735 5736 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5737 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5738 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5739 5740 /* write value back with RXDCTL.ENABLE bit cleared */ 5741 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5742 } 5743 5744 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5745 if (hw->mac.type == ixgbe_mac_82598EB && 5746 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5747 return; 5748 5749 /* Determine our minimum delay interval. We will increase this value 5750 * with each subsequent test. This way if the device returns quickly 5751 * we should spend as little time as possible waiting, however as 5752 * the time increases we will wait for larger periods of time. 5753 * 5754 * The trick here is that we increase the interval using the 5755 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5756 * of that wait is that it totals up to 100x whatever interval we 5757 * choose. Since our minimum wait is 100us we can just divide the 5758 * total timeout by 100 to get our minimum delay interval. 5759 */ 5760 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5761 5762 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5763 wait_delay = delay_interval; 5764 5765 while (wait_loop--) { 5766 usleep_range(wait_delay, wait_delay + 10); 5767 wait_delay += delay_interval * 2; 5768 rxdctl = 0; 5769 5770 /* OR together the reading of all the active RXDCTL registers, 5771 * and then test the result. We need the disable to complete 5772 * before we start freeing the memory and invalidating the 5773 * DMA mappings. 5774 */ 5775 for (i = 0; i < adapter->num_rx_queues; i++) { 5776 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5777 u8 reg_idx = ring->reg_idx; 5778 5779 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5780 } 5781 5782 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5783 return; 5784 } 5785 5786 e_err(drv, 5787 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5788 } 5789 5790 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5791 { 5792 unsigned long wait_delay, delay_interval; 5793 struct ixgbe_hw *hw = &adapter->hw; 5794 int i, wait_loop; 5795 u32 txdctl; 5796 5797 if (ixgbe_removed(hw->hw_addr)) 5798 return; 5799 5800 /* disable all enabled Tx queues */ 5801 for (i = 0; i < adapter->num_tx_queues; i++) { 5802 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5803 u8 reg_idx = ring->reg_idx; 5804 5805 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5806 } 5807 5808 /* disable all enabled XDP Tx queues */ 5809 for (i = 0; i < adapter->num_xdp_queues; i++) { 5810 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5811 u8 reg_idx = ring->reg_idx; 5812 5813 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5814 } 5815 5816 /* If the link is not up there shouldn't be much in the way of 5817 * pending transactions. Those that are left will be flushed out 5818 * when the reset logic goes through the flush sequence to clean out 5819 * the pending Tx transactions. 5820 */ 5821 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5822 goto dma_engine_disable; 5823 5824 /* Determine our minimum delay interval. We will increase this value 5825 * with each subsequent test. This way if the device returns quickly 5826 * we should spend as little time as possible waiting, however as 5827 * the time increases we will wait for larger periods of time. 5828 * 5829 * The trick here is that we increase the interval using the 5830 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5831 * of that wait is that it totals up to 100x whatever interval we 5832 * choose. Since our minimum wait is 100us we can just divide the 5833 * total timeout by 100 to get our minimum delay interval. 5834 */ 5835 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5836 5837 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5838 wait_delay = delay_interval; 5839 5840 while (wait_loop--) { 5841 usleep_range(wait_delay, wait_delay + 10); 5842 wait_delay += delay_interval * 2; 5843 txdctl = 0; 5844 5845 /* OR together the reading of all the active TXDCTL registers, 5846 * and then test the result. We need the disable to complete 5847 * before we start freeing the memory and invalidating the 5848 * DMA mappings. 5849 */ 5850 for (i = 0; i < adapter->num_tx_queues; i++) { 5851 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5852 u8 reg_idx = ring->reg_idx; 5853 5854 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5855 } 5856 for (i = 0; i < adapter->num_xdp_queues; i++) { 5857 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5858 u8 reg_idx = ring->reg_idx; 5859 5860 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5861 } 5862 5863 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5864 goto dma_engine_disable; 5865 } 5866 5867 e_err(drv, 5868 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5869 5870 dma_engine_disable: 5871 /* Disable the Tx DMA engine on 82599 and later MAC */ 5872 switch (hw->mac.type) { 5873 case ixgbe_mac_82599EB: 5874 case ixgbe_mac_X540: 5875 case ixgbe_mac_X550: 5876 case ixgbe_mac_X550EM_x: 5877 case ixgbe_mac_x550em_a: 5878 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5879 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5880 ~IXGBE_DMATXCTL_TE)); 5881 /* fall through */ 5882 default: 5883 break; 5884 } 5885 } 5886 5887 void ixgbe_reset(struct ixgbe_adapter *adapter) 5888 { 5889 struct ixgbe_hw *hw = &adapter->hw; 5890 struct net_device *netdev = adapter->netdev; 5891 int err; 5892 5893 if (ixgbe_removed(hw->hw_addr)) 5894 return; 5895 /* lock SFP init bit to prevent race conditions with the watchdog */ 5896 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5897 usleep_range(1000, 2000); 5898 5899 /* clear all SFP and link config related flags while holding SFP_INIT */ 5900 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5901 IXGBE_FLAG2_SFP_NEEDS_RESET); 5902 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5903 5904 err = hw->mac.ops.init_hw(hw); 5905 switch (err) { 5906 case 0: 5907 case IXGBE_ERR_SFP_NOT_PRESENT: 5908 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5909 break; 5910 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5911 e_dev_err("master disable timed out\n"); 5912 break; 5913 case IXGBE_ERR_EEPROM_VERSION: 5914 /* We are running on a pre-production device, log a warning */ 5915 e_dev_warn("This device is a pre-production adapter/LOM. " 5916 "Please be aware there may be issues associated with " 5917 "your hardware. If you are experiencing problems " 5918 "please contact your Intel or hardware " 5919 "representative who provided you with this " 5920 "hardware.\n"); 5921 break; 5922 default: 5923 e_dev_err("Hardware Error: %d\n", err); 5924 } 5925 5926 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5927 5928 /* flush entries out of MAC table */ 5929 ixgbe_flush_sw_mac_table(adapter); 5930 __dev_uc_unsync(netdev, NULL); 5931 5932 /* do not flush user set addresses */ 5933 ixgbe_mac_set_default_filter(adapter); 5934 5935 /* update SAN MAC vmdq pool selection */ 5936 if (hw->mac.san_mac_rar_index) 5937 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5938 5939 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5940 ixgbe_ptp_reset(adapter); 5941 5942 if (hw->phy.ops.set_phy_power) { 5943 if (!netif_running(adapter->netdev) && !adapter->wol) 5944 hw->phy.ops.set_phy_power(hw, false); 5945 else 5946 hw->phy.ops.set_phy_power(hw, true); 5947 } 5948 } 5949 5950 /** 5951 * ixgbe_clean_tx_ring - Free Tx Buffers 5952 * @tx_ring: ring to be cleaned 5953 **/ 5954 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5955 { 5956 u16 i = tx_ring->next_to_clean; 5957 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5958 5959 if (tx_ring->xsk_umem) { 5960 ixgbe_xsk_clean_tx_ring(tx_ring); 5961 goto out; 5962 } 5963 5964 while (i != tx_ring->next_to_use) { 5965 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5966 5967 /* Free all the Tx ring sk_buffs */ 5968 if (ring_is_xdp(tx_ring)) 5969 xdp_return_frame(tx_buffer->xdpf); 5970 else 5971 dev_kfree_skb_any(tx_buffer->skb); 5972 5973 /* unmap skb header data */ 5974 dma_unmap_single(tx_ring->dev, 5975 dma_unmap_addr(tx_buffer, dma), 5976 dma_unmap_len(tx_buffer, len), 5977 DMA_TO_DEVICE); 5978 5979 /* check for eop_desc to determine the end of the packet */ 5980 eop_desc = tx_buffer->next_to_watch; 5981 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5982 5983 /* unmap remaining buffers */ 5984 while (tx_desc != eop_desc) { 5985 tx_buffer++; 5986 tx_desc++; 5987 i++; 5988 if (unlikely(i == tx_ring->count)) { 5989 i = 0; 5990 tx_buffer = tx_ring->tx_buffer_info; 5991 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5992 } 5993 5994 /* unmap any remaining paged data */ 5995 if (dma_unmap_len(tx_buffer, len)) 5996 dma_unmap_page(tx_ring->dev, 5997 dma_unmap_addr(tx_buffer, dma), 5998 dma_unmap_len(tx_buffer, len), 5999 DMA_TO_DEVICE); 6000 } 6001 6002 /* move us one more past the eop_desc for start of next pkt */ 6003 tx_buffer++; 6004 i++; 6005 if (unlikely(i == tx_ring->count)) { 6006 i = 0; 6007 tx_buffer = tx_ring->tx_buffer_info; 6008 } 6009 } 6010 6011 /* reset BQL for queue */ 6012 if (!ring_is_xdp(tx_ring)) 6013 netdev_tx_reset_queue(txring_txq(tx_ring)); 6014 6015 out: 6016 /* reset next_to_use and next_to_clean */ 6017 tx_ring->next_to_use = 0; 6018 tx_ring->next_to_clean = 0; 6019 } 6020 6021 /** 6022 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6023 * @adapter: board private structure 6024 **/ 6025 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6026 { 6027 int i; 6028 6029 for (i = 0; i < adapter->num_rx_queues; i++) 6030 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6031 } 6032 6033 /** 6034 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6035 * @adapter: board private structure 6036 **/ 6037 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6038 { 6039 int i; 6040 6041 for (i = 0; i < adapter->num_tx_queues; i++) 6042 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6043 for (i = 0; i < adapter->num_xdp_queues; i++) 6044 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6045 } 6046 6047 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6048 { 6049 struct hlist_node *node2; 6050 struct ixgbe_fdir_filter *filter; 6051 6052 spin_lock(&adapter->fdir_perfect_lock); 6053 6054 hlist_for_each_entry_safe(filter, node2, 6055 &adapter->fdir_filter_list, fdir_node) { 6056 hlist_del(&filter->fdir_node); 6057 kfree(filter); 6058 } 6059 adapter->fdir_filter_count = 0; 6060 6061 spin_unlock(&adapter->fdir_perfect_lock); 6062 } 6063 6064 void ixgbe_down(struct ixgbe_adapter *adapter) 6065 { 6066 struct net_device *netdev = adapter->netdev; 6067 struct ixgbe_hw *hw = &adapter->hw; 6068 int i; 6069 6070 /* signal that we are down to the interrupt handler */ 6071 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6072 return; /* do nothing if already down */ 6073 6074 /* Shut off incoming Tx traffic */ 6075 netif_tx_stop_all_queues(netdev); 6076 6077 /* call carrier off first to avoid false dev_watchdog timeouts */ 6078 netif_carrier_off(netdev); 6079 netif_tx_disable(netdev); 6080 6081 /* Disable Rx */ 6082 ixgbe_disable_rx(adapter); 6083 6084 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6085 if (adapter->xdp_ring[0]) 6086 synchronize_rcu(); 6087 6088 ixgbe_irq_disable(adapter); 6089 6090 ixgbe_napi_disable_all(adapter); 6091 6092 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6093 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6094 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6095 6096 del_timer_sync(&adapter->service_timer); 6097 6098 if (adapter->num_vfs) { 6099 /* Clear EITR Select mapping */ 6100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6101 6102 /* Mark all the VFs as inactive */ 6103 for (i = 0 ; i < adapter->num_vfs; i++) 6104 adapter->vfinfo[i].clear_to_send = false; 6105 6106 /* ping all the active vfs to let them know we are going down */ 6107 ixgbe_ping_all_vfs(adapter); 6108 6109 /* Disable all VFTE/VFRE TX/RX */ 6110 ixgbe_disable_tx_rx(adapter); 6111 } 6112 6113 /* disable transmits in the hardware now that interrupts are off */ 6114 ixgbe_disable_tx(adapter); 6115 6116 if (!pci_channel_offline(adapter->pdev)) 6117 ixgbe_reset(adapter); 6118 6119 /* power down the optics for 82599 SFP+ fiber */ 6120 if (hw->mac.ops.disable_tx_laser) 6121 hw->mac.ops.disable_tx_laser(hw); 6122 6123 ixgbe_clean_all_tx_rings(adapter); 6124 ixgbe_clean_all_rx_rings(adapter); 6125 } 6126 6127 /** 6128 * ixgbe_eee_capable - helper function to determine EEE support on X550 6129 * @adapter: board private structure 6130 */ 6131 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6132 { 6133 struct ixgbe_hw *hw = &adapter->hw; 6134 6135 switch (hw->device_id) { 6136 case IXGBE_DEV_ID_X550EM_A_1G_T: 6137 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6138 if (!hw->phy.eee_speeds_supported) 6139 break; 6140 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6141 if (!hw->phy.eee_speeds_advertised) 6142 break; 6143 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6144 break; 6145 default: 6146 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6147 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6148 break; 6149 } 6150 } 6151 6152 /** 6153 * ixgbe_tx_timeout - Respond to a Tx Hang 6154 * @netdev: network interface device structure 6155 **/ 6156 static void ixgbe_tx_timeout(struct net_device *netdev) 6157 { 6158 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6159 6160 /* Do the reset outside of interrupt context */ 6161 ixgbe_tx_timeout_reset(adapter); 6162 } 6163 6164 #ifdef CONFIG_IXGBE_DCB 6165 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6166 { 6167 struct ixgbe_hw *hw = &adapter->hw; 6168 struct tc_configuration *tc; 6169 int j; 6170 6171 switch (hw->mac.type) { 6172 case ixgbe_mac_82598EB: 6173 case ixgbe_mac_82599EB: 6174 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6175 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6176 break; 6177 case ixgbe_mac_X540: 6178 case ixgbe_mac_X550: 6179 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6180 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6181 break; 6182 case ixgbe_mac_X550EM_x: 6183 case ixgbe_mac_x550em_a: 6184 default: 6185 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6186 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6187 break; 6188 } 6189 6190 /* Configure DCB traffic classes */ 6191 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6192 tc = &adapter->dcb_cfg.tc_config[j]; 6193 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6194 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6195 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6196 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6197 tc->dcb_pfc = pfc_disabled; 6198 } 6199 6200 /* Initialize default user to priority mapping, UPx->TC0 */ 6201 tc = &adapter->dcb_cfg.tc_config[0]; 6202 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6203 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6204 6205 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6206 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6207 adapter->dcb_cfg.pfc_mode_enable = false; 6208 adapter->dcb_set_bitmap = 0x00; 6209 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6210 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6211 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6212 sizeof(adapter->temp_dcb_cfg)); 6213 } 6214 #endif 6215 6216 /** 6217 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6218 * @adapter: board private structure to initialize 6219 * @ii: pointer to ixgbe_info for device 6220 * 6221 * ixgbe_sw_init initializes the Adapter private data structure. 6222 * Fields are initialized based on PCI device information and 6223 * OS network device settings (MTU size). 6224 **/ 6225 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6226 const struct ixgbe_info *ii) 6227 { 6228 struct ixgbe_hw *hw = &adapter->hw; 6229 struct pci_dev *pdev = adapter->pdev; 6230 unsigned int rss, fdir; 6231 u32 fwsm; 6232 int i; 6233 6234 /* PCI config space info */ 6235 6236 hw->vendor_id = pdev->vendor; 6237 hw->device_id = pdev->device; 6238 hw->revision_id = pdev->revision; 6239 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6240 hw->subsystem_device_id = pdev->subsystem_device; 6241 6242 /* get_invariants needs the device IDs */ 6243 ii->get_invariants(hw); 6244 6245 /* Set common capability flags and settings */ 6246 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6247 adapter->ring_feature[RING_F_RSS].limit = rss; 6248 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6249 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6250 adapter->atr_sample_rate = 20; 6251 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6252 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6253 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6254 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6255 #ifdef CONFIG_IXGBE_DCA 6256 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6257 #endif 6258 #ifdef CONFIG_IXGBE_DCB 6259 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6260 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6261 #endif 6262 #ifdef IXGBE_FCOE 6263 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6264 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6265 #ifdef CONFIG_IXGBE_DCB 6266 /* Default traffic class to use for FCoE */ 6267 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6268 #endif /* CONFIG_IXGBE_DCB */ 6269 #endif /* IXGBE_FCOE */ 6270 6271 /* initialize static ixgbe jump table entries */ 6272 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6273 GFP_KERNEL); 6274 if (!adapter->jump_tables[0]) 6275 return -ENOMEM; 6276 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6277 6278 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6279 adapter->jump_tables[i] = NULL; 6280 6281 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6282 sizeof(struct ixgbe_mac_addr), 6283 GFP_KERNEL); 6284 if (!adapter->mac_table) 6285 return -ENOMEM; 6286 6287 if (ixgbe_init_rss_key(adapter)) 6288 return -ENOMEM; 6289 6290 /* Set MAC specific capability flags and exceptions */ 6291 switch (hw->mac.type) { 6292 case ixgbe_mac_82598EB: 6293 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6294 6295 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6296 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6297 6298 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6299 adapter->ring_feature[RING_F_FDIR].limit = 0; 6300 adapter->atr_sample_rate = 0; 6301 adapter->fdir_pballoc = 0; 6302 #ifdef IXGBE_FCOE 6303 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6304 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6305 #ifdef CONFIG_IXGBE_DCB 6306 adapter->fcoe.up = 0; 6307 #endif /* IXGBE_DCB */ 6308 #endif /* IXGBE_FCOE */ 6309 break; 6310 case ixgbe_mac_82599EB: 6311 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6312 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6313 break; 6314 case ixgbe_mac_X540: 6315 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6316 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6317 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6318 break; 6319 case ixgbe_mac_x550em_a: 6320 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6321 switch (hw->device_id) { 6322 case IXGBE_DEV_ID_X550EM_A_1G_T: 6323 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6324 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6325 break; 6326 default: 6327 break; 6328 } 6329 /* fall through */ 6330 case ixgbe_mac_X550EM_x: 6331 #ifdef CONFIG_IXGBE_DCB 6332 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6333 #endif 6334 #ifdef IXGBE_FCOE 6335 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6336 #ifdef CONFIG_IXGBE_DCB 6337 adapter->fcoe.up = 0; 6338 #endif /* IXGBE_DCB */ 6339 #endif /* IXGBE_FCOE */ 6340 /* Fall Through */ 6341 case ixgbe_mac_X550: 6342 if (hw->mac.type == ixgbe_mac_X550) 6343 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6344 #ifdef CONFIG_IXGBE_DCA 6345 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6346 #endif 6347 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6348 break; 6349 default: 6350 break; 6351 } 6352 6353 #ifdef IXGBE_FCOE 6354 /* FCoE support exists, always init the FCoE lock */ 6355 spin_lock_init(&adapter->fcoe.lock); 6356 6357 #endif 6358 /* n-tuple support exists, always init our spinlock */ 6359 spin_lock_init(&adapter->fdir_perfect_lock); 6360 6361 #ifdef CONFIG_IXGBE_DCB 6362 ixgbe_init_dcb(adapter); 6363 #endif 6364 ixgbe_init_ipsec_offload(adapter); 6365 6366 /* default flow control settings */ 6367 hw->fc.requested_mode = ixgbe_fc_full; 6368 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6369 ixgbe_pbthresh_setup(adapter); 6370 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6371 hw->fc.send_xon = true; 6372 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6373 6374 #ifdef CONFIG_PCI_IOV 6375 if (max_vfs > 0) 6376 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6377 6378 /* assign number of SR-IOV VFs */ 6379 if (hw->mac.type != ixgbe_mac_82598EB) { 6380 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6381 max_vfs = 0; 6382 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6383 } 6384 } 6385 #endif /* CONFIG_PCI_IOV */ 6386 6387 /* enable itr by default in dynamic mode */ 6388 adapter->rx_itr_setting = 1; 6389 adapter->tx_itr_setting = 1; 6390 6391 /* set default ring sizes */ 6392 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6393 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6394 6395 /* set default work limits */ 6396 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6397 6398 /* initialize eeprom parameters */ 6399 if (ixgbe_init_eeprom_params_generic(hw)) { 6400 e_dev_err("EEPROM initialization failed\n"); 6401 return -EIO; 6402 } 6403 6404 /* PF holds first pool slot */ 6405 set_bit(0, adapter->fwd_bitmask); 6406 set_bit(__IXGBE_DOWN, &adapter->state); 6407 6408 return 0; 6409 } 6410 6411 /** 6412 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6413 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6414 * 6415 * Return 0 on success, negative on failure 6416 **/ 6417 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6418 { 6419 struct device *dev = tx_ring->dev; 6420 int orig_node = dev_to_node(dev); 6421 int ring_node = -1; 6422 int size; 6423 6424 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6425 6426 if (tx_ring->q_vector) 6427 ring_node = tx_ring->q_vector->numa_node; 6428 6429 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6430 if (!tx_ring->tx_buffer_info) 6431 tx_ring->tx_buffer_info = vmalloc(size); 6432 if (!tx_ring->tx_buffer_info) 6433 goto err; 6434 6435 /* round up to nearest 4K */ 6436 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6437 tx_ring->size = ALIGN(tx_ring->size, 4096); 6438 6439 set_dev_node(dev, ring_node); 6440 tx_ring->desc = dma_alloc_coherent(dev, 6441 tx_ring->size, 6442 &tx_ring->dma, 6443 GFP_KERNEL); 6444 set_dev_node(dev, orig_node); 6445 if (!tx_ring->desc) 6446 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6447 &tx_ring->dma, GFP_KERNEL); 6448 if (!tx_ring->desc) 6449 goto err; 6450 6451 tx_ring->next_to_use = 0; 6452 tx_ring->next_to_clean = 0; 6453 return 0; 6454 6455 err: 6456 vfree(tx_ring->tx_buffer_info); 6457 tx_ring->tx_buffer_info = NULL; 6458 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6459 return -ENOMEM; 6460 } 6461 6462 /** 6463 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6464 * @adapter: board private structure 6465 * 6466 * If this function returns with an error, then it's possible one or 6467 * more of the rings is populated (while the rest are not). It is the 6468 * callers duty to clean those orphaned rings. 6469 * 6470 * Return 0 on success, negative on failure 6471 **/ 6472 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6473 { 6474 int i, j = 0, err = 0; 6475 6476 for (i = 0; i < adapter->num_tx_queues; i++) { 6477 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6478 if (!err) 6479 continue; 6480 6481 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6482 goto err_setup_tx; 6483 } 6484 for (j = 0; j < adapter->num_xdp_queues; j++) { 6485 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6486 if (!err) 6487 continue; 6488 6489 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6490 goto err_setup_tx; 6491 } 6492 6493 return 0; 6494 err_setup_tx: 6495 /* rewind the index freeing the rings as we go */ 6496 while (j--) 6497 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6498 while (i--) 6499 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6500 return err; 6501 } 6502 6503 /** 6504 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6505 * @adapter: pointer to ixgbe_adapter 6506 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6507 * 6508 * Returns 0 on success, negative on failure 6509 **/ 6510 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6511 struct ixgbe_ring *rx_ring) 6512 { 6513 struct device *dev = rx_ring->dev; 6514 int orig_node = dev_to_node(dev); 6515 int ring_node = -1; 6516 int size; 6517 6518 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6519 6520 if (rx_ring->q_vector) 6521 ring_node = rx_ring->q_vector->numa_node; 6522 6523 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6524 if (!rx_ring->rx_buffer_info) 6525 rx_ring->rx_buffer_info = vmalloc(size); 6526 if (!rx_ring->rx_buffer_info) 6527 goto err; 6528 6529 /* Round up to nearest 4K */ 6530 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6531 rx_ring->size = ALIGN(rx_ring->size, 4096); 6532 6533 set_dev_node(dev, ring_node); 6534 rx_ring->desc = dma_alloc_coherent(dev, 6535 rx_ring->size, 6536 &rx_ring->dma, 6537 GFP_KERNEL); 6538 set_dev_node(dev, orig_node); 6539 if (!rx_ring->desc) 6540 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6541 &rx_ring->dma, GFP_KERNEL); 6542 if (!rx_ring->desc) 6543 goto err; 6544 6545 rx_ring->next_to_clean = 0; 6546 rx_ring->next_to_use = 0; 6547 6548 /* XDP RX-queue info */ 6549 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6550 rx_ring->queue_index) < 0) 6551 goto err; 6552 6553 rx_ring->xdp_prog = adapter->xdp_prog; 6554 6555 return 0; 6556 err: 6557 vfree(rx_ring->rx_buffer_info); 6558 rx_ring->rx_buffer_info = NULL; 6559 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6560 return -ENOMEM; 6561 } 6562 6563 /** 6564 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6565 * @adapter: board private structure 6566 * 6567 * If this function returns with an error, then it's possible one or 6568 * more of the rings is populated (while the rest are not). It is the 6569 * callers duty to clean those orphaned rings. 6570 * 6571 * Return 0 on success, negative on failure 6572 **/ 6573 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6574 { 6575 int i, err = 0; 6576 6577 for (i = 0; i < adapter->num_rx_queues; i++) { 6578 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6579 if (!err) 6580 continue; 6581 6582 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6583 goto err_setup_rx; 6584 } 6585 6586 #ifdef IXGBE_FCOE 6587 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6588 if (!err) 6589 #endif 6590 return 0; 6591 err_setup_rx: 6592 /* rewind the index freeing the rings as we go */ 6593 while (i--) 6594 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6595 return err; 6596 } 6597 6598 /** 6599 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6600 * @tx_ring: Tx descriptor ring for a specific queue 6601 * 6602 * Free all transmit software resources 6603 **/ 6604 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6605 { 6606 ixgbe_clean_tx_ring(tx_ring); 6607 6608 vfree(tx_ring->tx_buffer_info); 6609 tx_ring->tx_buffer_info = NULL; 6610 6611 /* if not set, then don't free */ 6612 if (!tx_ring->desc) 6613 return; 6614 6615 dma_free_coherent(tx_ring->dev, tx_ring->size, 6616 tx_ring->desc, tx_ring->dma); 6617 6618 tx_ring->desc = NULL; 6619 } 6620 6621 /** 6622 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6623 * @adapter: board private structure 6624 * 6625 * Free all transmit software resources 6626 **/ 6627 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6628 { 6629 int i; 6630 6631 for (i = 0; i < adapter->num_tx_queues; i++) 6632 if (adapter->tx_ring[i]->desc) 6633 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6634 for (i = 0; i < adapter->num_xdp_queues; i++) 6635 if (adapter->xdp_ring[i]->desc) 6636 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6637 } 6638 6639 /** 6640 * ixgbe_free_rx_resources - Free Rx Resources 6641 * @rx_ring: ring to clean the resources from 6642 * 6643 * Free all receive software resources 6644 **/ 6645 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6646 { 6647 ixgbe_clean_rx_ring(rx_ring); 6648 6649 rx_ring->xdp_prog = NULL; 6650 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6651 vfree(rx_ring->rx_buffer_info); 6652 rx_ring->rx_buffer_info = NULL; 6653 6654 /* if not set, then don't free */ 6655 if (!rx_ring->desc) 6656 return; 6657 6658 dma_free_coherent(rx_ring->dev, rx_ring->size, 6659 rx_ring->desc, rx_ring->dma); 6660 6661 rx_ring->desc = NULL; 6662 } 6663 6664 /** 6665 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6666 * @adapter: board private structure 6667 * 6668 * Free all receive software resources 6669 **/ 6670 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6671 { 6672 int i; 6673 6674 #ifdef IXGBE_FCOE 6675 ixgbe_free_fcoe_ddp_resources(adapter); 6676 6677 #endif 6678 for (i = 0; i < adapter->num_rx_queues; i++) 6679 if (adapter->rx_ring[i]->desc) 6680 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6681 } 6682 6683 /** 6684 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6685 * @netdev: network interface device structure 6686 * @new_mtu: new value for maximum frame size 6687 * 6688 * Returns 0 on success, negative on failure 6689 **/ 6690 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6691 { 6692 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6693 6694 if (adapter->xdp_prog) { 6695 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 6696 VLAN_HLEN; 6697 int i; 6698 6699 for (i = 0; i < adapter->num_rx_queues; i++) { 6700 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6701 6702 if (new_frame_size > ixgbe_rx_bufsz(ring)) { 6703 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6704 return -EINVAL; 6705 } 6706 } 6707 } 6708 6709 /* 6710 * For 82599EB we cannot allow legacy VFs to enable their receive 6711 * paths when MTU greater than 1500 is configured. So display a 6712 * warning that legacy VFs will be disabled. 6713 */ 6714 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6715 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6716 (new_mtu > ETH_DATA_LEN)) 6717 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6718 6719 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6720 6721 /* must set new MTU before calling down or up */ 6722 netdev->mtu = new_mtu; 6723 6724 if (netif_running(netdev)) 6725 ixgbe_reinit_locked(adapter); 6726 6727 return 0; 6728 } 6729 6730 /** 6731 * ixgbe_open - Called when a network interface is made active 6732 * @netdev: network interface device structure 6733 * 6734 * Returns 0 on success, negative value on failure 6735 * 6736 * The open entry point is called when a network interface is made 6737 * active by the system (IFF_UP). At this point all resources needed 6738 * for transmit and receive operations are allocated, the interrupt 6739 * handler is registered with the OS, the watchdog timer is started, 6740 * and the stack is notified that the interface is ready. 6741 **/ 6742 int ixgbe_open(struct net_device *netdev) 6743 { 6744 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6745 struct ixgbe_hw *hw = &adapter->hw; 6746 int err, queues; 6747 6748 /* disallow open during test */ 6749 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6750 return -EBUSY; 6751 6752 netif_carrier_off(netdev); 6753 6754 /* allocate transmit descriptors */ 6755 err = ixgbe_setup_all_tx_resources(adapter); 6756 if (err) 6757 goto err_setup_tx; 6758 6759 /* allocate receive descriptors */ 6760 err = ixgbe_setup_all_rx_resources(adapter); 6761 if (err) 6762 goto err_setup_rx; 6763 6764 ixgbe_configure(adapter); 6765 6766 err = ixgbe_request_irq(adapter); 6767 if (err) 6768 goto err_req_irq; 6769 6770 /* Notify the stack of the actual queue counts. */ 6771 queues = adapter->num_tx_queues; 6772 err = netif_set_real_num_tx_queues(netdev, queues); 6773 if (err) 6774 goto err_set_queues; 6775 6776 queues = adapter->num_rx_queues; 6777 err = netif_set_real_num_rx_queues(netdev, queues); 6778 if (err) 6779 goto err_set_queues; 6780 6781 ixgbe_ptp_init(adapter); 6782 6783 ixgbe_up_complete(adapter); 6784 6785 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6786 udp_tunnel_get_rx_info(netdev); 6787 6788 return 0; 6789 6790 err_set_queues: 6791 ixgbe_free_irq(adapter); 6792 err_req_irq: 6793 ixgbe_free_all_rx_resources(adapter); 6794 if (hw->phy.ops.set_phy_power && !adapter->wol) 6795 hw->phy.ops.set_phy_power(&adapter->hw, false); 6796 err_setup_rx: 6797 ixgbe_free_all_tx_resources(adapter); 6798 err_setup_tx: 6799 ixgbe_reset(adapter); 6800 6801 return err; 6802 } 6803 6804 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6805 { 6806 ixgbe_ptp_suspend(adapter); 6807 6808 if (adapter->hw.phy.ops.enter_lplu) { 6809 adapter->hw.phy.reset_disable = true; 6810 ixgbe_down(adapter); 6811 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6812 adapter->hw.phy.reset_disable = false; 6813 } else { 6814 ixgbe_down(adapter); 6815 } 6816 6817 ixgbe_free_irq(adapter); 6818 6819 ixgbe_free_all_tx_resources(adapter); 6820 ixgbe_free_all_rx_resources(adapter); 6821 } 6822 6823 /** 6824 * ixgbe_close - Disables a network interface 6825 * @netdev: network interface device structure 6826 * 6827 * Returns 0, this is not allowed to fail 6828 * 6829 * The close entry point is called when an interface is de-activated 6830 * by the OS. The hardware is still under the drivers control, but 6831 * needs to be disabled. A global MAC reset is issued to stop the 6832 * hardware, and all transmit and receive resources are freed. 6833 **/ 6834 int ixgbe_close(struct net_device *netdev) 6835 { 6836 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6837 6838 ixgbe_ptp_stop(adapter); 6839 6840 if (netif_device_present(netdev)) 6841 ixgbe_close_suspend(adapter); 6842 6843 ixgbe_fdir_filter_exit(adapter); 6844 6845 ixgbe_release_hw_control(adapter); 6846 6847 return 0; 6848 } 6849 6850 #ifdef CONFIG_PM 6851 static int ixgbe_resume(struct pci_dev *pdev) 6852 { 6853 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6854 struct net_device *netdev = adapter->netdev; 6855 u32 err; 6856 6857 adapter->hw.hw_addr = adapter->io_addr; 6858 pci_set_power_state(pdev, PCI_D0); 6859 pci_restore_state(pdev); 6860 /* 6861 * pci_restore_state clears dev->state_saved so call 6862 * pci_save_state to restore it. 6863 */ 6864 pci_save_state(pdev); 6865 6866 err = pci_enable_device_mem(pdev); 6867 if (err) { 6868 e_dev_err("Cannot enable PCI device from suspend\n"); 6869 return err; 6870 } 6871 smp_mb__before_atomic(); 6872 clear_bit(__IXGBE_DISABLED, &adapter->state); 6873 pci_set_master(pdev); 6874 6875 pci_wake_from_d3(pdev, false); 6876 6877 ixgbe_reset(adapter); 6878 6879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6880 6881 rtnl_lock(); 6882 err = ixgbe_init_interrupt_scheme(adapter); 6883 if (!err && netif_running(netdev)) 6884 err = ixgbe_open(netdev); 6885 6886 6887 if (!err) 6888 netif_device_attach(netdev); 6889 rtnl_unlock(); 6890 6891 return err; 6892 } 6893 #endif /* CONFIG_PM */ 6894 6895 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6896 { 6897 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6898 struct net_device *netdev = adapter->netdev; 6899 struct ixgbe_hw *hw = &adapter->hw; 6900 u32 ctrl; 6901 u32 wufc = adapter->wol; 6902 #ifdef CONFIG_PM 6903 int retval = 0; 6904 #endif 6905 6906 rtnl_lock(); 6907 netif_device_detach(netdev); 6908 6909 if (netif_running(netdev)) 6910 ixgbe_close_suspend(adapter); 6911 6912 ixgbe_clear_interrupt_scheme(adapter); 6913 rtnl_unlock(); 6914 6915 #ifdef CONFIG_PM 6916 retval = pci_save_state(pdev); 6917 if (retval) 6918 return retval; 6919 6920 #endif 6921 if (hw->mac.ops.stop_link_on_d3) 6922 hw->mac.ops.stop_link_on_d3(hw); 6923 6924 if (wufc) { 6925 u32 fctrl; 6926 6927 ixgbe_set_rx_mode(netdev); 6928 6929 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6930 if (hw->mac.ops.enable_tx_laser) 6931 hw->mac.ops.enable_tx_laser(hw); 6932 6933 /* enable the reception of multicast packets */ 6934 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6935 fctrl |= IXGBE_FCTRL_MPE; 6936 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6937 6938 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6939 ctrl |= IXGBE_CTRL_GIO_DIS; 6940 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6941 6942 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6943 } else { 6944 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6945 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6946 } 6947 6948 switch (hw->mac.type) { 6949 case ixgbe_mac_82598EB: 6950 pci_wake_from_d3(pdev, false); 6951 break; 6952 case ixgbe_mac_82599EB: 6953 case ixgbe_mac_X540: 6954 case ixgbe_mac_X550: 6955 case ixgbe_mac_X550EM_x: 6956 case ixgbe_mac_x550em_a: 6957 pci_wake_from_d3(pdev, !!wufc); 6958 break; 6959 default: 6960 break; 6961 } 6962 6963 *enable_wake = !!wufc; 6964 if (hw->phy.ops.set_phy_power && !*enable_wake) 6965 hw->phy.ops.set_phy_power(hw, false); 6966 6967 ixgbe_release_hw_control(adapter); 6968 6969 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6970 pci_disable_device(pdev); 6971 6972 return 0; 6973 } 6974 6975 #ifdef CONFIG_PM 6976 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6977 { 6978 int retval; 6979 bool wake; 6980 6981 retval = __ixgbe_shutdown(pdev, &wake); 6982 if (retval) 6983 return retval; 6984 6985 if (wake) { 6986 pci_prepare_to_sleep(pdev); 6987 } else { 6988 pci_wake_from_d3(pdev, false); 6989 pci_set_power_state(pdev, PCI_D3hot); 6990 } 6991 6992 return 0; 6993 } 6994 #endif /* CONFIG_PM */ 6995 6996 static void ixgbe_shutdown(struct pci_dev *pdev) 6997 { 6998 bool wake; 6999 7000 __ixgbe_shutdown(pdev, &wake); 7001 7002 if (system_state == SYSTEM_POWER_OFF) { 7003 pci_wake_from_d3(pdev, wake); 7004 pci_set_power_state(pdev, PCI_D3hot); 7005 } 7006 } 7007 7008 /** 7009 * ixgbe_update_stats - Update the board statistics counters. 7010 * @adapter: board private structure 7011 **/ 7012 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7013 { 7014 struct net_device *netdev = adapter->netdev; 7015 struct ixgbe_hw *hw = &adapter->hw; 7016 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7017 u64 total_mpc = 0; 7018 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7019 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7020 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7021 u64 alloc_rx_page = 0; 7022 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7023 7024 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7025 test_bit(__IXGBE_RESETTING, &adapter->state)) 7026 return; 7027 7028 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7029 u64 rsc_count = 0; 7030 u64 rsc_flush = 0; 7031 for (i = 0; i < adapter->num_rx_queues; i++) { 7032 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7033 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7034 } 7035 adapter->rsc_total_count = rsc_count; 7036 adapter->rsc_total_flush = rsc_flush; 7037 } 7038 7039 for (i = 0; i < adapter->num_rx_queues; i++) { 7040 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 7041 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7042 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7043 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7044 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7045 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7046 bytes += rx_ring->stats.bytes; 7047 packets += rx_ring->stats.packets; 7048 } 7049 adapter->non_eop_descs = non_eop_descs; 7050 adapter->alloc_rx_page = alloc_rx_page; 7051 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7052 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7053 adapter->hw_csum_rx_error = hw_csum_rx_error; 7054 netdev->stats.rx_bytes = bytes; 7055 netdev->stats.rx_packets = packets; 7056 7057 bytes = 0; 7058 packets = 0; 7059 /* gather some stats to the adapter struct that are per queue */ 7060 for (i = 0; i < adapter->num_tx_queues; i++) { 7061 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7062 restart_queue += tx_ring->tx_stats.restart_queue; 7063 tx_busy += tx_ring->tx_stats.tx_busy; 7064 bytes += tx_ring->stats.bytes; 7065 packets += tx_ring->stats.packets; 7066 } 7067 for (i = 0; i < adapter->num_xdp_queues; i++) { 7068 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 7069 7070 restart_queue += xdp_ring->tx_stats.restart_queue; 7071 tx_busy += xdp_ring->tx_stats.tx_busy; 7072 bytes += xdp_ring->stats.bytes; 7073 packets += xdp_ring->stats.packets; 7074 } 7075 adapter->restart_queue = restart_queue; 7076 adapter->tx_busy = tx_busy; 7077 netdev->stats.tx_bytes = bytes; 7078 netdev->stats.tx_packets = packets; 7079 7080 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7081 7082 /* 8 register reads */ 7083 for (i = 0; i < 8; i++) { 7084 /* for packet buffers not used, the register should read 0 */ 7085 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7086 missed_rx += mpc; 7087 hwstats->mpc[i] += mpc; 7088 total_mpc += hwstats->mpc[i]; 7089 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7090 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7091 switch (hw->mac.type) { 7092 case ixgbe_mac_82598EB: 7093 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7094 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7095 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7096 hwstats->pxonrxc[i] += 7097 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7098 break; 7099 case ixgbe_mac_82599EB: 7100 case ixgbe_mac_X540: 7101 case ixgbe_mac_X550: 7102 case ixgbe_mac_X550EM_x: 7103 case ixgbe_mac_x550em_a: 7104 hwstats->pxonrxc[i] += 7105 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7106 break; 7107 default: 7108 break; 7109 } 7110 } 7111 7112 /*16 register reads */ 7113 for (i = 0; i < 16; i++) { 7114 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7115 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7116 if ((hw->mac.type == ixgbe_mac_82599EB) || 7117 (hw->mac.type == ixgbe_mac_X540) || 7118 (hw->mac.type == ixgbe_mac_X550) || 7119 (hw->mac.type == ixgbe_mac_X550EM_x) || 7120 (hw->mac.type == ixgbe_mac_x550em_a)) { 7121 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7122 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7123 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7124 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7125 } 7126 } 7127 7128 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7129 /* work around hardware counting issue */ 7130 hwstats->gprc -= missed_rx; 7131 7132 ixgbe_update_xoff_received(adapter); 7133 7134 /* 82598 hardware only has a 32 bit counter in the high register */ 7135 switch (hw->mac.type) { 7136 case ixgbe_mac_82598EB: 7137 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7138 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7139 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7140 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7141 break; 7142 case ixgbe_mac_X540: 7143 case ixgbe_mac_X550: 7144 case ixgbe_mac_X550EM_x: 7145 case ixgbe_mac_x550em_a: 7146 /* OS2BMC stats are X540 and later */ 7147 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7148 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7149 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7150 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7151 /* fall through */ 7152 case ixgbe_mac_82599EB: 7153 for (i = 0; i < 16; i++) 7154 adapter->hw_rx_no_dma_resources += 7155 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7156 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7157 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7158 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7159 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7160 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7161 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7162 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7163 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7164 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7165 #ifdef IXGBE_FCOE 7166 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7167 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7168 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7169 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7170 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7171 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7172 /* Add up per cpu counters for total ddp aloc fail */ 7173 if (adapter->fcoe.ddp_pool) { 7174 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7175 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7176 unsigned int cpu; 7177 u64 noddp = 0, noddp_ext_buff = 0; 7178 for_each_possible_cpu(cpu) { 7179 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7180 noddp += ddp_pool->noddp; 7181 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7182 } 7183 hwstats->fcoe_noddp = noddp; 7184 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7185 } 7186 #endif /* IXGBE_FCOE */ 7187 break; 7188 default: 7189 break; 7190 } 7191 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7192 hwstats->bprc += bprc; 7193 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7194 if (hw->mac.type == ixgbe_mac_82598EB) 7195 hwstats->mprc -= bprc; 7196 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7197 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7198 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7199 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7200 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7201 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7202 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7203 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7204 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7205 hwstats->lxontxc += lxon; 7206 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7207 hwstats->lxofftxc += lxoff; 7208 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7209 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7210 /* 7211 * 82598 errata - tx of flow control packets is included in tx counters 7212 */ 7213 xon_off_tot = lxon + lxoff; 7214 hwstats->gptc -= xon_off_tot; 7215 hwstats->mptc -= xon_off_tot; 7216 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7217 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7218 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7219 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7220 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7221 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7222 hwstats->ptc64 -= xon_off_tot; 7223 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7224 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7225 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7226 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7227 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7228 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7229 7230 /* Fill out the OS statistics structure */ 7231 netdev->stats.multicast = hwstats->mprc; 7232 7233 /* Rx Errors */ 7234 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7235 netdev->stats.rx_dropped = 0; 7236 netdev->stats.rx_length_errors = hwstats->rlec; 7237 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7238 netdev->stats.rx_missed_errors = total_mpc; 7239 } 7240 7241 /** 7242 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7243 * @adapter: pointer to the device adapter structure 7244 **/ 7245 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7246 { 7247 struct ixgbe_hw *hw = &adapter->hw; 7248 int i; 7249 7250 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7251 return; 7252 7253 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7254 7255 /* if interface is down do nothing */ 7256 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7257 return; 7258 7259 /* do nothing if we are not using signature filters */ 7260 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7261 return; 7262 7263 adapter->fdir_overflow++; 7264 7265 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7266 for (i = 0; i < adapter->num_tx_queues; i++) 7267 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7268 &(adapter->tx_ring[i]->state)); 7269 for (i = 0; i < adapter->num_xdp_queues; i++) 7270 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7271 &adapter->xdp_ring[i]->state); 7272 /* re-enable flow director interrupts */ 7273 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7274 } else { 7275 e_err(probe, "failed to finish FDIR re-initialization, " 7276 "ignored adding FDIR ATR filters\n"); 7277 } 7278 } 7279 7280 /** 7281 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7282 * @adapter: pointer to the device adapter structure 7283 * 7284 * This function serves two purposes. First it strobes the interrupt lines 7285 * in order to make certain interrupts are occurring. Secondly it sets the 7286 * bits needed to check for TX hangs. As a result we should immediately 7287 * determine if a hang has occurred. 7288 */ 7289 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7290 { 7291 struct ixgbe_hw *hw = &adapter->hw; 7292 u64 eics = 0; 7293 int i; 7294 7295 /* If we're down, removing or resetting, just bail */ 7296 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7297 test_bit(__IXGBE_REMOVING, &adapter->state) || 7298 test_bit(__IXGBE_RESETTING, &adapter->state)) 7299 return; 7300 7301 /* Force detection of hung controller */ 7302 if (netif_carrier_ok(adapter->netdev)) { 7303 for (i = 0; i < adapter->num_tx_queues; i++) 7304 set_check_for_tx_hang(adapter->tx_ring[i]); 7305 for (i = 0; i < adapter->num_xdp_queues; i++) 7306 set_check_for_tx_hang(adapter->xdp_ring[i]); 7307 } 7308 7309 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7310 /* 7311 * for legacy and MSI interrupts don't set any bits 7312 * that are enabled for EIAM, because this operation 7313 * would set *both* EIMS and EICS for any bit in EIAM 7314 */ 7315 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7316 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7317 } else { 7318 /* get one bit for every active tx/rx interrupt vector */ 7319 for (i = 0; i < adapter->num_q_vectors; i++) { 7320 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7321 if (qv->rx.ring || qv->tx.ring) 7322 eics |= BIT_ULL(i); 7323 } 7324 } 7325 7326 /* Cause software interrupt to ensure rings are cleaned */ 7327 ixgbe_irq_rearm_queues(adapter, eics); 7328 } 7329 7330 /** 7331 * ixgbe_watchdog_update_link - update the link status 7332 * @adapter: pointer to the device adapter structure 7333 **/ 7334 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7335 { 7336 struct ixgbe_hw *hw = &adapter->hw; 7337 u32 link_speed = adapter->link_speed; 7338 bool link_up = adapter->link_up; 7339 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7340 7341 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7342 return; 7343 7344 if (hw->mac.ops.check_link) { 7345 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7346 } else { 7347 /* always assume link is up, if no check link function */ 7348 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7349 link_up = true; 7350 } 7351 7352 if (adapter->ixgbe_ieee_pfc) 7353 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7354 7355 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7356 hw->mac.ops.fc_enable(hw); 7357 ixgbe_set_rx_drop_en(adapter); 7358 } 7359 7360 if (link_up || 7361 time_after(jiffies, (adapter->link_check_timeout + 7362 IXGBE_TRY_LINK_TIMEOUT))) { 7363 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7364 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7365 IXGBE_WRITE_FLUSH(hw); 7366 } 7367 7368 adapter->link_up = link_up; 7369 adapter->link_speed = link_speed; 7370 } 7371 7372 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7373 { 7374 #ifdef CONFIG_IXGBE_DCB 7375 struct net_device *netdev = adapter->netdev; 7376 struct dcb_app app = { 7377 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7378 .protocol = 0, 7379 }; 7380 u8 up = 0; 7381 7382 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7383 up = dcb_ieee_getapp_mask(netdev, &app); 7384 7385 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7386 #endif 7387 } 7388 7389 /** 7390 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7391 * print link up message 7392 * @adapter: pointer to the device adapter structure 7393 **/ 7394 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7395 { 7396 struct net_device *netdev = adapter->netdev; 7397 struct ixgbe_hw *hw = &adapter->hw; 7398 u32 link_speed = adapter->link_speed; 7399 const char *speed_str; 7400 bool flow_rx, flow_tx; 7401 7402 /* only continue if link was previously down */ 7403 if (netif_carrier_ok(netdev)) 7404 return; 7405 7406 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7407 7408 switch (hw->mac.type) { 7409 case ixgbe_mac_82598EB: { 7410 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7411 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7412 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7413 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7414 } 7415 break; 7416 case ixgbe_mac_X540: 7417 case ixgbe_mac_X550: 7418 case ixgbe_mac_X550EM_x: 7419 case ixgbe_mac_x550em_a: 7420 case ixgbe_mac_82599EB: { 7421 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7422 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7423 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7424 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7425 } 7426 break; 7427 default: 7428 flow_tx = false; 7429 flow_rx = false; 7430 break; 7431 } 7432 7433 adapter->last_rx_ptp_check = jiffies; 7434 7435 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7436 ixgbe_ptp_start_cyclecounter(adapter); 7437 7438 switch (link_speed) { 7439 case IXGBE_LINK_SPEED_10GB_FULL: 7440 speed_str = "10 Gbps"; 7441 break; 7442 case IXGBE_LINK_SPEED_5GB_FULL: 7443 speed_str = "5 Gbps"; 7444 break; 7445 case IXGBE_LINK_SPEED_2_5GB_FULL: 7446 speed_str = "2.5 Gbps"; 7447 break; 7448 case IXGBE_LINK_SPEED_1GB_FULL: 7449 speed_str = "1 Gbps"; 7450 break; 7451 case IXGBE_LINK_SPEED_100_FULL: 7452 speed_str = "100 Mbps"; 7453 break; 7454 case IXGBE_LINK_SPEED_10_FULL: 7455 speed_str = "10 Mbps"; 7456 break; 7457 default: 7458 speed_str = "unknown speed"; 7459 break; 7460 } 7461 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7462 ((flow_rx && flow_tx) ? "RX/TX" : 7463 (flow_rx ? "RX" : 7464 (flow_tx ? "TX" : "None")))); 7465 7466 netif_carrier_on(netdev); 7467 ixgbe_check_vf_rate_limit(adapter); 7468 7469 /* enable transmits */ 7470 netif_tx_wake_all_queues(adapter->netdev); 7471 7472 /* update the default user priority for VFs */ 7473 ixgbe_update_default_up(adapter); 7474 7475 /* ping all the active vfs to let them know link has changed */ 7476 ixgbe_ping_all_vfs(adapter); 7477 } 7478 7479 /** 7480 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7481 * print link down message 7482 * @adapter: pointer to the adapter structure 7483 **/ 7484 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7485 { 7486 struct net_device *netdev = adapter->netdev; 7487 struct ixgbe_hw *hw = &adapter->hw; 7488 7489 adapter->link_up = false; 7490 adapter->link_speed = 0; 7491 7492 /* only continue if link was up previously */ 7493 if (!netif_carrier_ok(netdev)) 7494 return; 7495 7496 /* poll for SFP+ cable when link is down */ 7497 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7498 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7499 7500 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7501 ixgbe_ptp_start_cyclecounter(adapter); 7502 7503 e_info(drv, "NIC Link is Down\n"); 7504 netif_carrier_off(netdev); 7505 7506 /* ping all the active vfs to let them know link has changed */ 7507 ixgbe_ping_all_vfs(adapter); 7508 } 7509 7510 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7511 { 7512 int i; 7513 7514 for (i = 0; i < adapter->num_tx_queues; i++) { 7515 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7516 7517 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7518 return true; 7519 } 7520 7521 for (i = 0; i < adapter->num_xdp_queues; i++) { 7522 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7523 7524 if (ring->next_to_use != ring->next_to_clean) 7525 return true; 7526 } 7527 7528 return false; 7529 } 7530 7531 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7532 { 7533 struct ixgbe_hw *hw = &adapter->hw; 7534 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7535 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7536 7537 int i, j; 7538 7539 if (!adapter->num_vfs) 7540 return false; 7541 7542 /* resetting the PF is only needed for MAC before X550 */ 7543 if (hw->mac.type >= ixgbe_mac_X550) 7544 return false; 7545 7546 for (i = 0; i < adapter->num_vfs; i++) { 7547 for (j = 0; j < q_per_pool; j++) { 7548 u32 h, t; 7549 7550 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7551 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7552 7553 if (h != t) 7554 return true; 7555 } 7556 } 7557 7558 return false; 7559 } 7560 7561 /** 7562 * ixgbe_watchdog_flush_tx - flush queues on link down 7563 * @adapter: pointer to the device adapter structure 7564 **/ 7565 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7566 { 7567 if (!netif_carrier_ok(adapter->netdev)) { 7568 if (ixgbe_ring_tx_pending(adapter) || 7569 ixgbe_vf_tx_pending(adapter)) { 7570 /* We've lost link, so the controller stops DMA, 7571 * but we've got queued Tx work that's never going 7572 * to get done, so reset controller to flush Tx. 7573 * (Do the reset outside of interrupt context). 7574 */ 7575 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7576 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7577 } 7578 } 7579 } 7580 7581 #ifdef CONFIG_PCI_IOV 7582 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7583 { 7584 struct ixgbe_hw *hw = &adapter->hw; 7585 struct pci_dev *pdev = adapter->pdev; 7586 unsigned int vf; 7587 u32 gpc; 7588 7589 if (!(netif_carrier_ok(adapter->netdev))) 7590 return; 7591 7592 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7593 if (gpc) /* If incrementing then no need for the check below */ 7594 return; 7595 /* Check to see if a bad DMA write target from an errant or 7596 * malicious VF has caused a PCIe error. If so then we can 7597 * issue a VFLR to the offending VF(s) and then resume without 7598 * requesting a full slot reset. 7599 */ 7600 7601 if (!pdev) 7602 return; 7603 7604 /* check status reg for all VFs owned by this PF */ 7605 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7606 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7607 u16 status_reg; 7608 7609 if (!vfdev) 7610 continue; 7611 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7612 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7613 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7614 pcie_flr(vfdev); 7615 } 7616 } 7617 7618 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7619 { 7620 u32 ssvpc; 7621 7622 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7623 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7624 adapter->num_vfs == 0) 7625 return; 7626 7627 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7628 7629 /* 7630 * ssvpc register is cleared on read, if zero then no 7631 * spoofed packets in the last interval. 7632 */ 7633 if (!ssvpc) 7634 return; 7635 7636 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7637 } 7638 #else 7639 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7640 { 7641 } 7642 7643 static void 7644 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7645 { 7646 } 7647 #endif /* CONFIG_PCI_IOV */ 7648 7649 7650 /** 7651 * ixgbe_watchdog_subtask - check and bring link up 7652 * @adapter: pointer to the device adapter structure 7653 **/ 7654 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7655 { 7656 /* if interface is down, removing or resetting, do nothing */ 7657 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7658 test_bit(__IXGBE_REMOVING, &adapter->state) || 7659 test_bit(__IXGBE_RESETTING, &adapter->state)) 7660 return; 7661 7662 ixgbe_watchdog_update_link(adapter); 7663 7664 if (adapter->link_up) 7665 ixgbe_watchdog_link_is_up(adapter); 7666 else 7667 ixgbe_watchdog_link_is_down(adapter); 7668 7669 ixgbe_check_for_bad_vf(adapter); 7670 ixgbe_spoof_check(adapter); 7671 ixgbe_update_stats(adapter); 7672 7673 ixgbe_watchdog_flush_tx(adapter); 7674 } 7675 7676 /** 7677 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7678 * @adapter: the ixgbe adapter structure 7679 **/ 7680 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7681 { 7682 struct ixgbe_hw *hw = &adapter->hw; 7683 s32 err; 7684 7685 /* not searching for SFP so there is nothing to do here */ 7686 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7687 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7688 return; 7689 7690 if (adapter->sfp_poll_time && 7691 time_after(adapter->sfp_poll_time, jiffies)) 7692 return; /* If not yet time to poll for SFP */ 7693 7694 /* someone else is in init, wait until next service event */ 7695 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7696 return; 7697 7698 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7699 7700 err = hw->phy.ops.identify_sfp(hw); 7701 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7702 goto sfp_out; 7703 7704 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7705 /* If no cable is present, then we need to reset 7706 * the next time we find a good cable. */ 7707 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7708 } 7709 7710 /* exit on error */ 7711 if (err) 7712 goto sfp_out; 7713 7714 /* exit if reset not needed */ 7715 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7716 goto sfp_out; 7717 7718 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7719 7720 /* 7721 * A module may be identified correctly, but the EEPROM may not have 7722 * support for that module. setup_sfp() will fail in that case, so 7723 * we should not allow that module to load. 7724 */ 7725 if (hw->mac.type == ixgbe_mac_82598EB) 7726 err = hw->phy.ops.reset(hw); 7727 else 7728 err = hw->mac.ops.setup_sfp(hw); 7729 7730 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7731 goto sfp_out; 7732 7733 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7734 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7735 7736 sfp_out: 7737 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7738 7739 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7740 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7741 e_dev_err("failed to initialize because an unsupported " 7742 "SFP+ module type was detected.\n"); 7743 e_dev_err("Reload the driver after installing a " 7744 "supported module.\n"); 7745 unregister_netdev(adapter->netdev); 7746 } 7747 } 7748 7749 /** 7750 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7751 * @adapter: the ixgbe adapter structure 7752 **/ 7753 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7754 { 7755 struct ixgbe_hw *hw = &adapter->hw; 7756 u32 cap_speed; 7757 u32 speed; 7758 bool autoneg = false; 7759 7760 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7761 return; 7762 7763 /* someone else is in init, wait until next service event */ 7764 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7765 return; 7766 7767 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7768 7769 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7770 7771 /* advertise highest capable link speed */ 7772 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7773 speed = IXGBE_LINK_SPEED_10GB_FULL; 7774 else 7775 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7776 IXGBE_LINK_SPEED_1GB_FULL); 7777 7778 if (hw->mac.ops.setup_link) 7779 hw->mac.ops.setup_link(hw, speed, true); 7780 7781 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7782 adapter->link_check_timeout = jiffies; 7783 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7784 } 7785 7786 /** 7787 * ixgbe_service_timer - Timer Call-back 7788 * @t: pointer to timer_list structure 7789 **/ 7790 static void ixgbe_service_timer(struct timer_list *t) 7791 { 7792 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7793 unsigned long next_event_offset; 7794 7795 /* poll faster when waiting for link */ 7796 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7797 next_event_offset = HZ / 10; 7798 else 7799 next_event_offset = HZ * 2; 7800 7801 /* Reset the timer */ 7802 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7803 7804 ixgbe_service_event_schedule(adapter); 7805 } 7806 7807 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7808 { 7809 struct ixgbe_hw *hw = &adapter->hw; 7810 u32 status; 7811 7812 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7813 return; 7814 7815 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7816 7817 if (!hw->phy.ops.handle_lasi) 7818 return; 7819 7820 status = hw->phy.ops.handle_lasi(&adapter->hw); 7821 if (status != IXGBE_ERR_OVERTEMP) 7822 return; 7823 7824 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7825 } 7826 7827 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7828 { 7829 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7830 return; 7831 7832 rtnl_lock(); 7833 /* If we're already down, removing or resetting, just bail */ 7834 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7835 test_bit(__IXGBE_REMOVING, &adapter->state) || 7836 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7837 rtnl_unlock(); 7838 return; 7839 } 7840 7841 ixgbe_dump(adapter); 7842 netdev_err(adapter->netdev, "Reset adapter\n"); 7843 adapter->tx_timeout_count++; 7844 7845 ixgbe_reinit_locked(adapter); 7846 rtnl_unlock(); 7847 } 7848 7849 /** 7850 * ixgbe_check_fw_error - Check firmware for errors 7851 * @adapter: the adapter private structure 7852 * 7853 * Check firmware errors in register FWSM 7854 */ 7855 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7856 { 7857 struct ixgbe_hw *hw = &adapter->hw; 7858 u32 fwsm; 7859 7860 /* read fwsm.ext_err_ind register and log errors */ 7861 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7862 7863 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7864 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7865 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7866 fwsm); 7867 7868 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7869 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7870 return true; 7871 } 7872 7873 return false; 7874 } 7875 7876 /** 7877 * ixgbe_service_task - manages and runs subtasks 7878 * @work: pointer to work_struct containing our data 7879 **/ 7880 static void ixgbe_service_task(struct work_struct *work) 7881 { 7882 struct ixgbe_adapter *adapter = container_of(work, 7883 struct ixgbe_adapter, 7884 service_task); 7885 if (ixgbe_removed(adapter->hw.hw_addr)) { 7886 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7887 rtnl_lock(); 7888 ixgbe_down(adapter); 7889 rtnl_unlock(); 7890 } 7891 ixgbe_service_event_complete(adapter); 7892 return; 7893 } 7894 if (ixgbe_check_fw_error(adapter)) { 7895 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7896 rtnl_lock(); 7897 unregister_netdev(adapter->netdev); 7898 rtnl_unlock(); 7899 } 7900 ixgbe_service_event_complete(adapter); 7901 return; 7902 } 7903 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7904 rtnl_lock(); 7905 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7906 udp_tunnel_get_rx_info(adapter->netdev); 7907 rtnl_unlock(); 7908 } 7909 ixgbe_reset_subtask(adapter); 7910 ixgbe_phy_interrupt_subtask(adapter); 7911 ixgbe_sfp_detection_subtask(adapter); 7912 ixgbe_sfp_link_config_subtask(adapter); 7913 ixgbe_check_overtemp_subtask(adapter); 7914 ixgbe_watchdog_subtask(adapter); 7915 ixgbe_fdir_reinit_subtask(adapter); 7916 ixgbe_check_hang_subtask(adapter); 7917 7918 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7919 ixgbe_ptp_overflow_check(adapter); 7920 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7921 ixgbe_ptp_rx_hang(adapter); 7922 ixgbe_ptp_tx_hang(adapter); 7923 } 7924 7925 ixgbe_service_event_complete(adapter); 7926 } 7927 7928 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7929 struct ixgbe_tx_buffer *first, 7930 u8 *hdr_len, 7931 struct ixgbe_ipsec_tx_data *itd) 7932 { 7933 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7934 struct sk_buff *skb = first->skb; 7935 union { 7936 struct iphdr *v4; 7937 struct ipv6hdr *v6; 7938 unsigned char *hdr; 7939 } ip; 7940 union { 7941 struct tcphdr *tcp; 7942 unsigned char *hdr; 7943 } l4; 7944 u32 paylen, l4_offset; 7945 u32 fceof_saidx = 0; 7946 int err; 7947 7948 if (skb->ip_summed != CHECKSUM_PARTIAL) 7949 return 0; 7950 7951 if (!skb_is_gso(skb)) 7952 return 0; 7953 7954 err = skb_cow_head(skb, 0); 7955 if (err < 0) 7956 return err; 7957 7958 if (eth_p_mpls(first->protocol)) 7959 ip.hdr = skb_inner_network_header(skb); 7960 else 7961 ip.hdr = skb_network_header(skb); 7962 l4.hdr = skb_checksum_start(skb); 7963 7964 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7965 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7966 7967 /* initialize outer IP header fields */ 7968 if (ip.v4->version == 4) { 7969 unsigned char *csum_start = skb_checksum_start(skb); 7970 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7971 int len = csum_start - trans_start; 7972 7973 /* IP header will have to cancel out any data that 7974 * is not a part of the outer IP header, so set to 7975 * a reverse csum if needed, else init check to 0. 7976 */ 7977 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7978 csum_fold(csum_partial(trans_start, 7979 len, 0)) : 0; 7980 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7981 7982 ip.v4->tot_len = 0; 7983 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7984 IXGBE_TX_FLAGS_CSUM | 7985 IXGBE_TX_FLAGS_IPV4; 7986 } else { 7987 ip.v6->payload_len = 0; 7988 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7989 IXGBE_TX_FLAGS_CSUM; 7990 } 7991 7992 /* determine offset of inner transport header */ 7993 l4_offset = l4.hdr - skb->data; 7994 7995 /* compute length of segmentation header */ 7996 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7997 7998 /* remove payload length from inner checksum */ 7999 paylen = skb->len - l4_offset; 8000 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 8001 8002 /* update gso size and bytecount with header size */ 8003 first->gso_segs = skb_shinfo(skb)->gso_segs; 8004 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8005 8006 /* mss_l4len_id: use 0 as index for TSO */ 8007 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8008 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8009 8010 fceof_saidx |= itd->sa_idx; 8011 type_tucmd |= itd->flags | itd->trailer_len; 8012 8013 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8014 vlan_macip_lens = l4.hdr - ip.hdr; 8015 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8016 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8017 8018 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8019 mss_l4len_idx); 8020 8021 return 1; 8022 } 8023 8024 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 8025 { 8026 unsigned int offset = 0; 8027 8028 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 8029 8030 return offset == skb_checksum_start_offset(skb); 8031 } 8032 8033 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8034 struct ixgbe_tx_buffer *first, 8035 struct ixgbe_ipsec_tx_data *itd) 8036 { 8037 struct sk_buff *skb = first->skb; 8038 u32 vlan_macip_lens = 0; 8039 u32 fceof_saidx = 0; 8040 u32 type_tucmd = 0; 8041 8042 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8043 csum_failed: 8044 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8045 IXGBE_TX_FLAGS_CC))) 8046 return; 8047 goto no_csum; 8048 } 8049 8050 switch (skb->csum_offset) { 8051 case offsetof(struct tcphdr, check): 8052 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8053 /* fall through */ 8054 case offsetof(struct udphdr, check): 8055 break; 8056 case offsetof(struct sctphdr, checksum): 8057 /* validate that this is actually an SCTP request */ 8058 if (((first->protocol == htons(ETH_P_IP)) && 8059 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 8060 ((first->protocol == htons(ETH_P_IPV6)) && 8061 ixgbe_ipv6_csum_is_sctp(skb))) { 8062 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8063 break; 8064 } 8065 /* fall through */ 8066 default: 8067 skb_checksum_help(skb); 8068 goto csum_failed; 8069 } 8070 8071 /* update TX checksum flag */ 8072 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8073 vlan_macip_lens = skb_checksum_start_offset(skb) - 8074 skb_network_offset(skb); 8075 no_csum: 8076 /* vlan_macip_lens: MACLEN, VLAN tag */ 8077 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8078 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8079 8080 fceof_saidx |= itd->sa_idx; 8081 type_tucmd |= itd->flags | itd->trailer_len; 8082 8083 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8084 } 8085 8086 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8087 ((_flag <= _result) ? \ 8088 ((u32)(_input & _flag) * (_result / _flag)) : \ 8089 ((u32)(_input & _flag) / (_flag / _result))) 8090 8091 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8092 { 8093 /* set type for advanced descriptor with frame checksum insertion */ 8094 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8095 IXGBE_ADVTXD_DCMD_DEXT | 8096 IXGBE_ADVTXD_DCMD_IFCS; 8097 8098 /* set HW vlan bit if vlan is present */ 8099 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8100 IXGBE_ADVTXD_DCMD_VLE); 8101 8102 /* set segmentation enable bits for TSO/FSO */ 8103 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8104 IXGBE_ADVTXD_DCMD_TSE); 8105 8106 /* set timestamp bit if present */ 8107 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8108 IXGBE_ADVTXD_MAC_TSTAMP); 8109 8110 /* insert frame checksum */ 8111 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8112 8113 return cmd_type; 8114 } 8115 8116 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8117 u32 tx_flags, unsigned int paylen) 8118 { 8119 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8120 8121 /* enable L4 checksum for TSO and TX checksum offload */ 8122 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8123 IXGBE_TX_FLAGS_CSUM, 8124 IXGBE_ADVTXD_POPTS_TXSM); 8125 8126 /* enable IPv4 checksum for TSO */ 8127 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8128 IXGBE_TX_FLAGS_IPV4, 8129 IXGBE_ADVTXD_POPTS_IXSM); 8130 8131 /* enable IPsec */ 8132 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8133 IXGBE_TX_FLAGS_IPSEC, 8134 IXGBE_ADVTXD_POPTS_IPSEC); 8135 8136 /* 8137 * Check Context must be set if Tx switch is enabled, which it 8138 * always is for case where virtual functions are running 8139 */ 8140 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8141 IXGBE_TX_FLAGS_CC, 8142 IXGBE_ADVTXD_CC); 8143 8144 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8145 } 8146 8147 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8148 { 8149 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8150 8151 /* Herbert's original patch had: 8152 * smp_mb__after_netif_stop_queue(); 8153 * but since that doesn't exist yet, just open code it. 8154 */ 8155 smp_mb(); 8156 8157 /* We need to check again in a case another CPU has just 8158 * made room available. 8159 */ 8160 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8161 return -EBUSY; 8162 8163 /* A reprieve! - use start_queue because it doesn't call schedule */ 8164 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8165 ++tx_ring->tx_stats.restart_queue; 8166 return 0; 8167 } 8168 8169 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8170 { 8171 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8172 return 0; 8173 8174 return __ixgbe_maybe_stop_tx(tx_ring, size); 8175 } 8176 8177 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8178 struct ixgbe_tx_buffer *first, 8179 const u8 hdr_len) 8180 { 8181 struct sk_buff *skb = first->skb; 8182 struct ixgbe_tx_buffer *tx_buffer; 8183 union ixgbe_adv_tx_desc *tx_desc; 8184 struct skb_frag_struct *frag; 8185 dma_addr_t dma; 8186 unsigned int data_len, size; 8187 u32 tx_flags = first->tx_flags; 8188 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8189 u16 i = tx_ring->next_to_use; 8190 8191 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8192 8193 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8194 8195 size = skb_headlen(skb); 8196 data_len = skb->data_len; 8197 8198 #ifdef IXGBE_FCOE 8199 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8200 if (data_len < sizeof(struct fcoe_crc_eof)) { 8201 size -= sizeof(struct fcoe_crc_eof) - data_len; 8202 data_len = 0; 8203 } else { 8204 data_len -= sizeof(struct fcoe_crc_eof); 8205 } 8206 } 8207 8208 #endif 8209 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8210 8211 tx_buffer = first; 8212 8213 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8214 if (dma_mapping_error(tx_ring->dev, dma)) 8215 goto dma_error; 8216 8217 /* record length, and DMA address */ 8218 dma_unmap_len_set(tx_buffer, len, size); 8219 dma_unmap_addr_set(tx_buffer, dma, dma); 8220 8221 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8222 8223 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8224 tx_desc->read.cmd_type_len = 8225 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8226 8227 i++; 8228 tx_desc++; 8229 if (i == tx_ring->count) { 8230 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8231 i = 0; 8232 } 8233 tx_desc->read.olinfo_status = 0; 8234 8235 dma += IXGBE_MAX_DATA_PER_TXD; 8236 size -= IXGBE_MAX_DATA_PER_TXD; 8237 8238 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8239 } 8240 8241 if (likely(!data_len)) 8242 break; 8243 8244 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8245 8246 i++; 8247 tx_desc++; 8248 if (i == tx_ring->count) { 8249 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8250 i = 0; 8251 } 8252 tx_desc->read.olinfo_status = 0; 8253 8254 #ifdef IXGBE_FCOE 8255 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8256 #else 8257 size = skb_frag_size(frag); 8258 #endif 8259 data_len -= size; 8260 8261 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8262 DMA_TO_DEVICE); 8263 8264 tx_buffer = &tx_ring->tx_buffer_info[i]; 8265 } 8266 8267 /* write last descriptor with RS and EOP bits */ 8268 cmd_type |= size | IXGBE_TXD_CMD; 8269 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8270 8271 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8272 8273 /* set the timestamp */ 8274 first->time_stamp = jiffies; 8275 8276 skb_tx_timestamp(skb); 8277 8278 /* 8279 * Force memory writes to complete before letting h/w know there 8280 * are new descriptors to fetch. (Only applicable for weak-ordered 8281 * memory model archs, such as IA-64). 8282 * 8283 * We also need this memory barrier to make certain all of the 8284 * status bits have been updated before next_to_watch is written. 8285 */ 8286 wmb(); 8287 8288 /* set next_to_watch value indicating a packet is present */ 8289 first->next_to_watch = tx_desc; 8290 8291 i++; 8292 if (i == tx_ring->count) 8293 i = 0; 8294 8295 tx_ring->next_to_use = i; 8296 8297 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8298 8299 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8300 writel(i, tx_ring->tail); 8301 8302 /* we need this if more than one processor can write to our tail 8303 * at a time, it synchronizes IO on IA64/Altix systems 8304 */ 8305 mmiowb(); 8306 } 8307 8308 return 0; 8309 dma_error: 8310 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8311 8312 /* clear dma mappings for failed tx_buffer_info map */ 8313 for (;;) { 8314 tx_buffer = &tx_ring->tx_buffer_info[i]; 8315 if (dma_unmap_len(tx_buffer, len)) 8316 dma_unmap_page(tx_ring->dev, 8317 dma_unmap_addr(tx_buffer, dma), 8318 dma_unmap_len(tx_buffer, len), 8319 DMA_TO_DEVICE); 8320 dma_unmap_len_set(tx_buffer, len, 0); 8321 if (tx_buffer == first) 8322 break; 8323 if (i == 0) 8324 i += tx_ring->count; 8325 i--; 8326 } 8327 8328 dev_kfree_skb_any(first->skb); 8329 first->skb = NULL; 8330 8331 tx_ring->next_to_use = i; 8332 8333 return -1; 8334 } 8335 8336 static void ixgbe_atr(struct ixgbe_ring *ring, 8337 struct ixgbe_tx_buffer *first) 8338 { 8339 struct ixgbe_q_vector *q_vector = ring->q_vector; 8340 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8341 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8342 union { 8343 unsigned char *network; 8344 struct iphdr *ipv4; 8345 struct ipv6hdr *ipv6; 8346 } hdr; 8347 struct tcphdr *th; 8348 unsigned int hlen; 8349 struct sk_buff *skb; 8350 __be16 vlan_id; 8351 int l4_proto; 8352 8353 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8354 if (!q_vector) 8355 return; 8356 8357 /* do nothing if sampling is disabled */ 8358 if (!ring->atr_sample_rate) 8359 return; 8360 8361 ring->atr_count++; 8362 8363 /* currently only IPv4/IPv6 with TCP is supported */ 8364 if ((first->protocol != htons(ETH_P_IP)) && 8365 (first->protocol != htons(ETH_P_IPV6))) 8366 return; 8367 8368 /* snag network header to get L4 type and address */ 8369 skb = first->skb; 8370 hdr.network = skb_network_header(skb); 8371 if (unlikely(hdr.network <= skb->data)) 8372 return; 8373 if (skb->encapsulation && 8374 first->protocol == htons(ETH_P_IP) && 8375 hdr.ipv4->protocol == IPPROTO_UDP) { 8376 struct ixgbe_adapter *adapter = q_vector->adapter; 8377 8378 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8379 VXLAN_HEADROOM)) 8380 return; 8381 8382 /* verify the port is recognized as VXLAN */ 8383 if (adapter->vxlan_port && 8384 udp_hdr(skb)->dest == adapter->vxlan_port) 8385 hdr.network = skb_inner_network_header(skb); 8386 8387 if (adapter->geneve_port && 8388 udp_hdr(skb)->dest == adapter->geneve_port) 8389 hdr.network = skb_inner_network_header(skb); 8390 } 8391 8392 /* Make sure we have at least [minimum IPv4 header + TCP] 8393 * or [IPv6 header] bytes 8394 */ 8395 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8396 return; 8397 8398 /* Currently only IPv4/IPv6 with TCP is supported */ 8399 switch (hdr.ipv4->version) { 8400 case IPVERSION: 8401 /* access ihl as u8 to avoid unaligned access on ia64 */ 8402 hlen = (hdr.network[0] & 0x0F) << 2; 8403 l4_proto = hdr.ipv4->protocol; 8404 break; 8405 case 6: 8406 hlen = hdr.network - skb->data; 8407 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8408 hlen -= hdr.network - skb->data; 8409 break; 8410 default: 8411 return; 8412 } 8413 8414 if (l4_proto != IPPROTO_TCP) 8415 return; 8416 8417 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8418 hlen + sizeof(struct tcphdr))) 8419 return; 8420 8421 th = (struct tcphdr *)(hdr.network + hlen); 8422 8423 /* skip this packet since the socket is closing */ 8424 if (th->fin) 8425 return; 8426 8427 /* sample on all syn packets or once every atr sample count */ 8428 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8429 return; 8430 8431 /* reset sample count */ 8432 ring->atr_count = 0; 8433 8434 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8435 8436 /* 8437 * src and dst are inverted, think how the receiver sees them 8438 * 8439 * The input is broken into two sections, a non-compressed section 8440 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8441 * is XORed together and stored in the compressed dword. 8442 */ 8443 input.formatted.vlan_id = vlan_id; 8444 8445 /* 8446 * since src port and flex bytes occupy the same word XOR them together 8447 * and write the value to source port portion of compressed dword 8448 */ 8449 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8450 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8451 else 8452 common.port.src ^= th->dest ^ first->protocol; 8453 common.port.dst ^= th->source; 8454 8455 switch (hdr.ipv4->version) { 8456 case IPVERSION: 8457 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8458 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8459 break; 8460 case 6: 8461 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8462 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8463 hdr.ipv6->saddr.s6_addr32[1] ^ 8464 hdr.ipv6->saddr.s6_addr32[2] ^ 8465 hdr.ipv6->saddr.s6_addr32[3] ^ 8466 hdr.ipv6->daddr.s6_addr32[0] ^ 8467 hdr.ipv6->daddr.s6_addr32[1] ^ 8468 hdr.ipv6->daddr.s6_addr32[2] ^ 8469 hdr.ipv6->daddr.s6_addr32[3]; 8470 break; 8471 default: 8472 break; 8473 } 8474 8475 if (hdr.network != skb_network_header(skb)) 8476 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8477 8478 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8479 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8480 input, common, ring->queue_index); 8481 } 8482 8483 #ifdef IXGBE_FCOE 8484 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8485 struct net_device *sb_dev, 8486 select_queue_fallback_t fallback) 8487 { 8488 struct ixgbe_adapter *adapter; 8489 struct ixgbe_ring_feature *f; 8490 int txq; 8491 8492 if (sb_dev) { 8493 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8494 struct net_device *vdev = sb_dev; 8495 8496 txq = vdev->tc_to_txq[tc].offset; 8497 txq += reciprocal_scale(skb_get_hash(skb), 8498 vdev->tc_to_txq[tc].count); 8499 8500 return txq; 8501 } 8502 8503 /* 8504 * only execute the code below if protocol is FCoE 8505 * or FIP and we have FCoE enabled on the adapter 8506 */ 8507 switch (vlan_get_protocol(skb)) { 8508 case htons(ETH_P_FCOE): 8509 case htons(ETH_P_FIP): 8510 adapter = netdev_priv(dev); 8511 8512 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8513 break; 8514 /* fall through */ 8515 default: 8516 return fallback(dev, skb, sb_dev); 8517 } 8518 8519 f = &adapter->ring_feature[RING_F_FCOE]; 8520 8521 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8522 smp_processor_id(); 8523 8524 while (txq >= f->indices) 8525 txq -= f->indices; 8526 8527 return txq + f->offset; 8528 } 8529 8530 #endif 8531 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8532 struct xdp_frame *xdpf) 8533 { 8534 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8535 struct ixgbe_tx_buffer *tx_buffer; 8536 union ixgbe_adv_tx_desc *tx_desc; 8537 u32 len, cmd_type; 8538 dma_addr_t dma; 8539 u16 i; 8540 8541 len = xdpf->len; 8542 8543 if (unlikely(!ixgbe_desc_unused(ring))) 8544 return IXGBE_XDP_CONSUMED; 8545 8546 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8547 if (dma_mapping_error(ring->dev, dma)) 8548 return IXGBE_XDP_CONSUMED; 8549 8550 /* record the location of the first descriptor for this packet */ 8551 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8552 tx_buffer->bytecount = len; 8553 tx_buffer->gso_segs = 1; 8554 tx_buffer->protocol = 0; 8555 8556 i = ring->next_to_use; 8557 tx_desc = IXGBE_TX_DESC(ring, i); 8558 8559 dma_unmap_len_set(tx_buffer, len, len); 8560 dma_unmap_addr_set(tx_buffer, dma, dma); 8561 tx_buffer->xdpf = xdpf; 8562 8563 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8564 8565 /* put descriptor type bits */ 8566 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8567 IXGBE_ADVTXD_DCMD_DEXT | 8568 IXGBE_ADVTXD_DCMD_IFCS; 8569 cmd_type |= len | IXGBE_TXD_CMD; 8570 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8571 tx_desc->read.olinfo_status = 8572 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8573 8574 /* Avoid any potential race with xdp_xmit and cleanup */ 8575 smp_wmb(); 8576 8577 /* set next_to_watch value indicating a packet is present */ 8578 i++; 8579 if (i == ring->count) 8580 i = 0; 8581 8582 tx_buffer->next_to_watch = tx_desc; 8583 ring->next_to_use = i; 8584 8585 return IXGBE_XDP_TX; 8586 } 8587 8588 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8589 struct ixgbe_adapter *adapter, 8590 struct ixgbe_ring *tx_ring) 8591 { 8592 struct ixgbe_tx_buffer *first; 8593 int tso; 8594 u32 tx_flags = 0; 8595 unsigned short f; 8596 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8597 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8598 __be16 protocol = skb->protocol; 8599 u8 hdr_len = 0; 8600 8601 /* 8602 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8603 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8604 * + 2 desc gap to keep tail from touching head, 8605 * + 1 desc for context descriptor, 8606 * otherwise try next time 8607 */ 8608 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8609 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8610 8611 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8612 tx_ring->tx_stats.tx_busy++; 8613 return NETDEV_TX_BUSY; 8614 } 8615 8616 /* record the location of the first descriptor for this packet */ 8617 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8618 first->skb = skb; 8619 first->bytecount = skb->len; 8620 first->gso_segs = 1; 8621 8622 /* if we have a HW VLAN tag being added default to the HW one */ 8623 if (skb_vlan_tag_present(skb)) { 8624 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8625 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8626 /* else if it is a SW VLAN check the next protocol and store the tag */ 8627 } else if (protocol == htons(ETH_P_8021Q)) { 8628 struct vlan_hdr *vhdr, _vhdr; 8629 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8630 if (!vhdr) 8631 goto out_drop; 8632 8633 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8634 IXGBE_TX_FLAGS_VLAN_SHIFT; 8635 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8636 } 8637 protocol = vlan_get_protocol(skb); 8638 8639 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8640 adapter->ptp_clock) { 8641 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8642 &adapter->state)) { 8643 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8644 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8645 8646 /* schedule check for Tx timestamp */ 8647 adapter->ptp_tx_skb = skb_get(skb); 8648 adapter->ptp_tx_start = jiffies; 8649 schedule_work(&adapter->ptp_tx_work); 8650 } else { 8651 adapter->tx_hwtstamp_skipped++; 8652 } 8653 } 8654 8655 #ifdef CONFIG_PCI_IOV 8656 /* 8657 * Use the l2switch_enable flag - would be false if the DMA 8658 * Tx switch had been disabled. 8659 */ 8660 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8661 tx_flags |= IXGBE_TX_FLAGS_CC; 8662 8663 #endif 8664 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8665 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8666 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8667 (skb->priority != TC_PRIO_CONTROL))) { 8668 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8669 tx_flags |= (skb->priority & 0x7) << 8670 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8671 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8672 struct vlan_ethhdr *vhdr; 8673 8674 if (skb_cow_head(skb, 0)) 8675 goto out_drop; 8676 vhdr = (struct vlan_ethhdr *)skb->data; 8677 vhdr->h_vlan_TCI = htons(tx_flags >> 8678 IXGBE_TX_FLAGS_VLAN_SHIFT); 8679 } else { 8680 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8681 } 8682 } 8683 8684 /* record initial flags and protocol */ 8685 first->tx_flags = tx_flags; 8686 first->protocol = protocol; 8687 8688 #ifdef IXGBE_FCOE 8689 /* setup tx offload for FCoE */ 8690 if ((protocol == htons(ETH_P_FCOE)) && 8691 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8692 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8693 if (tso < 0) 8694 goto out_drop; 8695 8696 goto xmit_fcoe; 8697 } 8698 8699 #endif /* IXGBE_FCOE */ 8700 8701 #ifdef CONFIG_IXGBE_IPSEC 8702 if (secpath_exists(skb) && 8703 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8704 goto out_drop; 8705 #endif 8706 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8707 if (tso < 0) 8708 goto out_drop; 8709 else if (!tso) 8710 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8711 8712 /* add the ATR filter if ATR is on */ 8713 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8714 ixgbe_atr(tx_ring, first); 8715 8716 #ifdef IXGBE_FCOE 8717 xmit_fcoe: 8718 #endif /* IXGBE_FCOE */ 8719 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8720 goto cleanup_tx_timestamp; 8721 8722 return NETDEV_TX_OK; 8723 8724 out_drop: 8725 dev_kfree_skb_any(first->skb); 8726 first->skb = NULL; 8727 cleanup_tx_timestamp: 8728 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8729 dev_kfree_skb_any(adapter->ptp_tx_skb); 8730 adapter->ptp_tx_skb = NULL; 8731 cancel_work_sync(&adapter->ptp_tx_work); 8732 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8733 } 8734 8735 return NETDEV_TX_OK; 8736 } 8737 8738 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8739 struct net_device *netdev, 8740 struct ixgbe_ring *ring) 8741 { 8742 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8743 struct ixgbe_ring *tx_ring; 8744 8745 /* 8746 * The minimum packet size for olinfo paylen is 17 so pad the skb 8747 * in order to meet this minimum size requirement. 8748 */ 8749 if (skb_put_padto(skb, 17)) 8750 return NETDEV_TX_OK; 8751 8752 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8753 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8754 return NETDEV_TX_BUSY; 8755 8756 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8757 } 8758 8759 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8760 struct net_device *netdev) 8761 { 8762 return __ixgbe_xmit_frame(skb, netdev, NULL); 8763 } 8764 8765 /** 8766 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8767 * @netdev: network interface device structure 8768 * @p: pointer to an address structure 8769 * 8770 * Returns 0 on success, negative on failure 8771 **/ 8772 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8773 { 8774 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8775 struct ixgbe_hw *hw = &adapter->hw; 8776 struct sockaddr *addr = p; 8777 8778 if (!is_valid_ether_addr(addr->sa_data)) 8779 return -EADDRNOTAVAIL; 8780 8781 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8782 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8783 8784 ixgbe_mac_set_default_filter(adapter); 8785 8786 return 0; 8787 } 8788 8789 static int 8790 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8791 { 8792 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8793 struct ixgbe_hw *hw = &adapter->hw; 8794 u16 value; 8795 int rc; 8796 8797 if (adapter->mii_bus) { 8798 int regnum = addr; 8799 8800 if (devad != MDIO_DEVAD_NONE) 8801 regnum |= (devad << 16) | MII_ADDR_C45; 8802 8803 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8804 } 8805 8806 if (prtad != hw->phy.mdio.prtad) 8807 return -EINVAL; 8808 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8809 if (!rc) 8810 rc = value; 8811 return rc; 8812 } 8813 8814 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8815 u16 addr, u16 value) 8816 { 8817 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8818 struct ixgbe_hw *hw = &adapter->hw; 8819 8820 if (adapter->mii_bus) { 8821 int regnum = addr; 8822 8823 if (devad != MDIO_DEVAD_NONE) 8824 regnum |= (devad << 16) | MII_ADDR_C45; 8825 8826 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8827 } 8828 8829 if (prtad != hw->phy.mdio.prtad) 8830 return -EINVAL; 8831 return hw->phy.ops.write_reg(hw, addr, devad, value); 8832 } 8833 8834 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8835 { 8836 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8837 8838 switch (cmd) { 8839 case SIOCSHWTSTAMP: 8840 return ixgbe_ptp_set_ts_config(adapter, req); 8841 case SIOCGHWTSTAMP: 8842 return ixgbe_ptp_get_ts_config(adapter, req); 8843 case SIOCGMIIPHY: 8844 if (!adapter->hw.phy.ops.read_reg) 8845 return -EOPNOTSUPP; 8846 /* fall through */ 8847 default: 8848 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8849 } 8850 } 8851 8852 /** 8853 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8854 * netdev->dev_addrs 8855 * @dev: network interface device structure 8856 * 8857 * Returns non-zero on failure 8858 **/ 8859 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8860 { 8861 int err = 0; 8862 struct ixgbe_adapter *adapter = netdev_priv(dev); 8863 struct ixgbe_hw *hw = &adapter->hw; 8864 8865 if (is_valid_ether_addr(hw->mac.san_addr)) { 8866 rtnl_lock(); 8867 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8868 rtnl_unlock(); 8869 8870 /* update SAN MAC vmdq pool selection */ 8871 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8872 } 8873 return err; 8874 } 8875 8876 /** 8877 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8878 * netdev->dev_addrs 8879 * @dev: network interface device structure 8880 * 8881 * Returns non-zero on failure 8882 **/ 8883 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8884 { 8885 int err = 0; 8886 struct ixgbe_adapter *adapter = netdev_priv(dev); 8887 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8888 8889 if (is_valid_ether_addr(mac->san_addr)) { 8890 rtnl_lock(); 8891 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8892 rtnl_unlock(); 8893 } 8894 return err; 8895 } 8896 8897 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8898 struct ixgbe_ring *ring) 8899 { 8900 u64 bytes, packets; 8901 unsigned int start; 8902 8903 if (ring) { 8904 do { 8905 start = u64_stats_fetch_begin_irq(&ring->syncp); 8906 packets = ring->stats.packets; 8907 bytes = ring->stats.bytes; 8908 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8909 stats->tx_packets += packets; 8910 stats->tx_bytes += bytes; 8911 } 8912 } 8913 8914 static void ixgbe_get_stats64(struct net_device *netdev, 8915 struct rtnl_link_stats64 *stats) 8916 { 8917 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8918 int i; 8919 8920 rcu_read_lock(); 8921 for (i = 0; i < adapter->num_rx_queues; i++) { 8922 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8923 u64 bytes, packets; 8924 unsigned int start; 8925 8926 if (ring) { 8927 do { 8928 start = u64_stats_fetch_begin_irq(&ring->syncp); 8929 packets = ring->stats.packets; 8930 bytes = ring->stats.bytes; 8931 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8932 stats->rx_packets += packets; 8933 stats->rx_bytes += bytes; 8934 } 8935 } 8936 8937 for (i = 0; i < adapter->num_tx_queues; i++) { 8938 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8939 8940 ixgbe_get_ring_stats64(stats, ring); 8941 } 8942 for (i = 0; i < adapter->num_xdp_queues; i++) { 8943 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8944 8945 ixgbe_get_ring_stats64(stats, ring); 8946 } 8947 rcu_read_unlock(); 8948 8949 /* following stats updated by ixgbe_watchdog_task() */ 8950 stats->multicast = netdev->stats.multicast; 8951 stats->rx_errors = netdev->stats.rx_errors; 8952 stats->rx_length_errors = netdev->stats.rx_length_errors; 8953 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8954 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8955 } 8956 8957 #ifdef CONFIG_IXGBE_DCB 8958 /** 8959 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8960 * @adapter: pointer to ixgbe_adapter 8961 * @tc: number of traffic classes currently enabled 8962 * 8963 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8964 * 802.1Q priority maps to a packet buffer that exists. 8965 */ 8966 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8967 { 8968 struct ixgbe_hw *hw = &adapter->hw; 8969 u32 reg, rsave; 8970 int i; 8971 8972 /* 82598 have a static priority to TC mapping that can not 8973 * be changed so no validation is needed. 8974 */ 8975 if (hw->mac.type == ixgbe_mac_82598EB) 8976 return; 8977 8978 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8979 rsave = reg; 8980 8981 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8982 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8983 8984 /* If up2tc is out of bounds default to zero */ 8985 if (up2tc > tc) 8986 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8987 } 8988 8989 if (reg != rsave) 8990 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8991 8992 return; 8993 } 8994 8995 /** 8996 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8997 * @adapter: Pointer to adapter struct 8998 * 8999 * Populate the netdev user priority to tc map 9000 */ 9001 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9002 { 9003 struct net_device *dev = adapter->netdev; 9004 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9005 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9006 u8 prio; 9007 9008 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9009 u8 tc = 0; 9010 9011 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9012 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9013 else if (ets) 9014 tc = ets->prio_tc[prio]; 9015 9016 netdev_set_prio_tc_map(dev, prio, tc); 9017 } 9018 } 9019 9020 #endif /* CONFIG_IXGBE_DCB */ 9021 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data) 9022 { 9023 struct ixgbe_adapter *adapter = data; 9024 struct ixgbe_fwd_adapter *accel; 9025 int pool; 9026 9027 /* we only care about macvlans... */ 9028 if (!netif_is_macvlan(vdev)) 9029 return 0; 9030 9031 /* that have hardware offload enabled... */ 9032 accel = macvlan_accel_priv(vdev); 9033 if (!accel) 9034 return 0; 9035 9036 /* If we can relocate to a different bit do so */ 9037 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9038 if (pool < adapter->num_rx_pools) { 9039 set_bit(pool, adapter->fwd_bitmask); 9040 accel->pool = pool; 9041 return 0; 9042 } 9043 9044 /* if we cannot find a free pool then disable the offload */ 9045 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9046 macvlan_release_l2fw_offload(vdev); 9047 9048 /* unbind the queues and drop the subordinate channel config */ 9049 netdev_unbind_sb_channel(adapter->netdev, vdev); 9050 netdev_set_sb_channel(vdev, 0); 9051 9052 kfree(accel); 9053 9054 return 0; 9055 } 9056 9057 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9058 { 9059 struct ixgbe_adapter *adapter = netdev_priv(dev); 9060 9061 /* flush any stale bits out of the fwd bitmask */ 9062 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9063 9064 /* walk through upper devices reassigning pools */ 9065 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9066 adapter); 9067 } 9068 9069 /** 9070 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9071 * 9072 * @dev: net device to configure 9073 * @tc: number of traffic classes to enable 9074 */ 9075 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9076 { 9077 struct ixgbe_adapter *adapter = netdev_priv(dev); 9078 struct ixgbe_hw *hw = &adapter->hw; 9079 9080 /* Hardware supports up to 8 traffic classes */ 9081 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9082 return -EINVAL; 9083 9084 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9085 return -EINVAL; 9086 9087 /* Hardware has to reinitialize queues and interrupts to 9088 * match packet buffer alignment. Unfortunately, the 9089 * hardware is not flexible enough to do this dynamically. 9090 */ 9091 if (netif_running(dev)) 9092 ixgbe_close(dev); 9093 else 9094 ixgbe_reset(adapter); 9095 9096 ixgbe_clear_interrupt_scheme(adapter); 9097 9098 #ifdef CONFIG_IXGBE_DCB 9099 if (tc) { 9100 if (adapter->xdp_prog) { 9101 e_warn(probe, "DCB is not supported with XDP\n"); 9102 9103 ixgbe_init_interrupt_scheme(adapter); 9104 if (netif_running(dev)) 9105 ixgbe_open(dev); 9106 return -EINVAL; 9107 } 9108 9109 netdev_set_num_tc(dev, tc); 9110 ixgbe_set_prio_tc_map(adapter); 9111 9112 adapter->hw_tcs = tc; 9113 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9114 9115 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9116 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9117 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9118 } 9119 } else { 9120 netdev_reset_tc(dev); 9121 9122 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9123 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9124 9125 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9126 adapter->hw_tcs = tc; 9127 9128 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9129 adapter->dcb_cfg.pfc_mode_enable = false; 9130 } 9131 9132 ixgbe_validate_rtr(adapter, tc); 9133 9134 #endif /* CONFIG_IXGBE_DCB */ 9135 ixgbe_init_interrupt_scheme(adapter); 9136 9137 ixgbe_defrag_macvlan_pools(dev); 9138 9139 if (netif_running(dev)) 9140 return ixgbe_open(dev); 9141 9142 return 0; 9143 } 9144 9145 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9146 struct tc_cls_u32_offload *cls) 9147 { 9148 u32 hdl = cls->knode.handle; 9149 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9150 u32 loc = cls->knode.handle & 0xfffff; 9151 int err = 0, i, j; 9152 struct ixgbe_jump_table *jump = NULL; 9153 9154 if (loc > IXGBE_MAX_HW_ENTRIES) 9155 return -EINVAL; 9156 9157 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9158 return -EINVAL; 9159 9160 /* Clear this filter in the link data it is associated with */ 9161 if (uhtid != 0x800) { 9162 jump = adapter->jump_tables[uhtid]; 9163 if (!jump) 9164 return -EINVAL; 9165 if (!test_bit(loc - 1, jump->child_loc_map)) 9166 return -EINVAL; 9167 clear_bit(loc - 1, jump->child_loc_map); 9168 } 9169 9170 /* Check if the filter being deleted is a link */ 9171 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9172 jump = adapter->jump_tables[i]; 9173 if (jump && jump->link_hdl == hdl) { 9174 /* Delete filters in the hardware in the child hash 9175 * table associated with this link 9176 */ 9177 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9178 if (!test_bit(j, jump->child_loc_map)) 9179 continue; 9180 spin_lock(&adapter->fdir_perfect_lock); 9181 err = ixgbe_update_ethtool_fdir_entry(adapter, 9182 NULL, 9183 j + 1); 9184 spin_unlock(&adapter->fdir_perfect_lock); 9185 clear_bit(j, jump->child_loc_map); 9186 } 9187 /* Remove resources for this link */ 9188 kfree(jump->input); 9189 kfree(jump->mask); 9190 kfree(jump); 9191 adapter->jump_tables[i] = NULL; 9192 return err; 9193 } 9194 } 9195 9196 spin_lock(&adapter->fdir_perfect_lock); 9197 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9198 spin_unlock(&adapter->fdir_perfect_lock); 9199 return err; 9200 } 9201 9202 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9203 struct tc_cls_u32_offload *cls) 9204 { 9205 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9206 9207 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9208 return -EINVAL; 9209 9210 /* This ixgbe devices do not support hash tables at the moment 9211 * so abort when given hash tables. 9212 */ 9213 if (cls->hnode.divisor > 0) 9214 return -EINVAL; 9215 9216 set_bit(uhtid - 1, &adapter->tables); 9217 return 0; 9218 } 9219 9220 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9221 struct tc_cls_u32_offload *cls) 9222 { 9223 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9224 9225 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9226 return -EINVAL; 9227 9228 clear_bit(uhtid - 1, &adapter->tables); 9229 return 0; 9230 } 9231 9232 #ifdef CONFIG_NET_CLS_ACT 9233 struct upper_walk_data { 9234 struct ixgbe_adapter *adapter; 9235 u64 action; 9236 int ifindex; 9237 u8 queue; 9238 }; 9239 9240 static int get_macvlan_queue(struct net_device *upper, void *_data) 9241 { 9242 if (netif_is_macvlan(upper)) { 9243 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9244 struct upper_walk_data *data = _data; 9245 struct ixgbe_adapter *adapter = data->adapter; 9246 int ifindex = data->ifindex; 9247 9248 if (vadapter && upper->ifindex == ifindex) { 9249 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9250 data->action = data->queue; 9251 return 1; 9252 } 9253 } 9254 9255 return 0; 9256 } 9257 9258 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9259 u8 *queue, u64 *action) 9260 { 9261 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9262 unsigned int num_vfs = adapter->num_vfs, vf; 9263 struct upper_walk_data data; 9264 struct net_device *upper; 9265 9266 /* redirect to a SRIOV VF */ 9267 for (vf = 0; vf < num_vfs; ++vf) { 9268 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9269 if (upper->ifindex == ifindex) { 9270 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9271 *action = vf + 1; 9272 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9273 return 0; 9274 } 9275 } 9276 9277 /* redirect to a offloaded macvlan netdev */ 9278 data.adapter = adapter; 9279 data.ifindex = ifindex; 9280 data.action = 0; 9281 data.queue = 0; 9282 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9283 get_macvlan_queue, &data)) { 9284 *action = data.action; 9285 *queue = data.queue; 9286 9287 return 0; 9288 } 9289 9290 return -EINVAL; 9291 } 9292 9293 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9294 struct tcf_exts *exts, u64 *action, u8 *queue) 9295 { 9296 const struct tc_action *a; 9297 int i; 9298 9299 if (!tcf_exts_has_actions(exts)) 9300 return -EINVAL; 9301 9302 tcf_exts_for_each_action(i, a, exts) { 9303 /* Drop action */ 9304 if (is_tcf_gact_shot(a)) { 9305 *action = IXGBE_FDIR_DROP_QUEUE; 9306 *queue = IXGBE_FDIR_DROP_QUEUE; 9307 return 0; 9308 } 9309 9310 /* Redirect to a VF or a offloaded macvlan */ 9311 if (is_tcf_mirred_egress_redirect(a)) { 9312 struct net_device *dev = tcf_mirred_dev(a); 9313 9314 if (!dev) 9315 return -EINVAL; 9316 return handle_redirect_action(adapter, dev->ifindex, 9317 queue, action); 9318 } 9319 9320 return -EINVAL; 9321 } 9322 9323 return -EINVAL; 9324 } 9325 #else 9326 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9327 struct tcf_exts *exts, u64 *action, u8 *queue) 9328 { 9329 return -EINVAL; 9330 } 9331 #endif /* CONFIG_NET_CLS_ACT */ 9332 9333 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9334 union ixgbe_atr_input *mask, 9335 struct tc_cls_u32_offload *cls, 9336 struct ixgbe_mat_field *field_ptr, 9337 struct ixgbe_nexthdr *nexthdr) 9338 { 9339 int i, j, off; 9340 __be32 val, m; 9341 bool found_entry = false, found_jump_field = false; 9342 9343 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9344 off = cls->knode.sel->keys[i].off; 9345 val = cls->knode.sel->keys[i].val; 9346 m = cls->knode.sel->keys[i].mask; 9347 9348 for (j = 0; field_ptr[j].val; j++) { 9349 if (field_ptr[j].off == off) { 9350 field_ptr[j].val(input, mask, (__force u32)val, 9351 (__force u32)m); 9352 input->filter.formatted.flow_type |= 9353 field_ptr[j].type; 9354 found_entry = true; 9355 break; 9356 } 9357 } 9358 if (nexthdr) { 9359 if (nexthdr->off == cls->knode.sel->keys[i].off && 9360 nexthdr->val == 9361 (__force u32)cls->knode.sel->keys[i].val && 9362 nexthdr->mask == 9363 (__force u32)cls->knode.sel->keys[i].mask) 9364 found_jump_field = true; 9365 else 9366 continue; 9367 } 9368 } 9369 9370 if (nexthdr && !found_jump_field) 9371 return -EINVAL; 9372 9373 if (!found_entry) 9374 return 0; 9375 9376 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9377 IXGBE_ATR_L4TYPE_MASK; 9378 9379 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9380 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9381 9382 return 0; 9383 } 9384 9385 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9386 struct tc_cls_u32_offload *cls) 9387 { 9388 __be16 protocol = cls->common.protocol; 9389 u32 loc = cls->knode.handle & 0xfffff; 9390 struct ixgbe_hw *hw = &adapter->hw; 9391 struct ixgbe_mat_field *field_ptr; 9392 struct ixgbe_fdir_filter *input = NULL; 9393 union ixgbe_atr_input *mask = NULL; 9394 struct ixgbe_jump_table *jump = NULL; 9395 int i, err = -EINVAL; 9396 u8 queue; 9397 u32 uhtid, link_uhtid; 9398 9399 uhtid = TC_U32_USERHTID(cls->knode.handle); 9400 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9401 9402 /* At the moment cls_u32 jumps to network layer and skips past 9403 * L2 headers. The canonical method to match L2 frames is to use 9404 * negative values. However this is error prone at best but really 9405 * just broken because there is no way to "know" what sort of hdr 9406 * is in front of the network layer. Fix cls_u32 to support L2 9407 * headers when needed. 9408 */ 9409 if (protocol != htons(ETH_P_IP)) 9410 return err; 9411 9412 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9413 e_err(drv, "Location out of range\n"); 9414 return err; 9415 } 9416 9417 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9418 * links and also the fields used to advance the parser across each 9419 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9420 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9421 * To add support for new nodes update ixgbe_model.h parse structures 9422 * this function _should_ be generic try not to hardcode values here. 9423 */ 9424 if (uhtid == 0x800) { 9425 field_ptr = (adapter->jump_tables[0])->mat; 9426 } else { 9427 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9428 return err; 9429 if (!adapter->jump_tables[uhtid]) 9430 return err; 9431 field_ptr = (adapter->jump_tables[uhtid])->mat; 9432 } 9433 9434 if (!field_ptr) 9435 return err; 9436 9437 /* At this point we know the field_ptr is valid and need to either 9438 * build cls_u32 link or attach filter. Because adding a link to 9439 * a handle that does not exist is invalid and the same for adding 9440 * rules to handles that don't exist. 9441 */ 9442 9443 if (link_uhtid) { 9444 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9445 9446 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9447 return err; 9448 9449 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9450 return err; 9451 9452 /* Multiple filters as links to the same hash table are not 9453 * supported. To add a new filter with the same next header 9454 * but different match/jump conditions, create a new hash table 9455 * and link to it. 9456 */ 9457 if (adapter->jump_tables[link_uhtid] && 9458 (adapter->jump_tables[link_uhtid])->link_hdl) { 9459 e_err(drv, "Link filter exists for link: %x\n", 9460 link_uhtid); 9461 return err; 9462 } 9463 9464 for (i = 0; nexthdr[i].jump; i++) { 9465 if (nexthdr[i].o != cls->knode.sel->offoff || 9466 nexthdr[i].s != cls->knode.sel->offshift || 9467 nexthdr[i].m != 9468 (__force u32)cls->knode.sel->offmask) 9469 return err; 9470 9471 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9472 if (!jump) 9473 return -ENOMEM; 9474 input = kzalloc(sizeof(*input), GFP_KERNEL); 9475 if (!input) { 9476 err = -ENOMEM; 9477 goto free_jump; 9478 } 9479 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9480 if (!mask) { 9481 err = -ENOMEM; 9482 goto free_input; 9483 } 9484 jump->input = input; 9485 jump->mask = mask; 9486 jump->link_hdl = cls->knode.handle; 9487 9488 err = ixgbe_clsu32_build_input(input, mask, cls, 9489 field_ptr, &nexthdr[i]); 9490 if (!err) { 9491 jump->mat = nexthdr[i].jump; 9492 adapter->jump_tables[link_uhtid] = jump; 9493 break; 9494 } 9495 } 9496 return 0; 9497 } 9498 9499 input = kzalloc(sizeof(*input), GFP_KERNEL); 9500 if (!input) 9501 return -ENOMEM; 9502 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9503 if (!mask) { 9504 err = -ENOMEM; 9505 goto free_input; 9506 } 9507 9508 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9509 if ((adapter->jump_tables[uhtid])->input) 9510 memcpy(input, (adapter->jump_tables[uhtid])->input, 9511 sizeof(*input)); 9512 if ((adapter->jump_tables[uhtid])->mask) 9513 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9514 sizeof(*mask)); 9515 9516 /* Lookup in all child hash tables if this location is already 9517 * filled with a filter 9518 */ 9519 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9520 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9521 9522 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9523 e_err(drv, "Filter exists in location: %x\n", 9524 loc); 9525 err = -EINVAL; 9526 goto err_out; 9527 } 9528 } 9529 } 9530 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9531 if (err) 9532 goto err_out; 9533 9534 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9535 &queue); 9536 if (err < 0) 9537 goto err_out; 9538 9539 input->sw_idx = loc; 9540 9541 spin_lock(&adapter->fdir_perfect_lock); 9542 9543 if (hlist_empty(&adapter->fdir_filter_list)) { 9544 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9545 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9546 if (err) 9547 goto err_out_w_lock; 9548 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9549 err = -EINVAL; 9550 goto err_out_w_lock; 9551 } 9552 9553 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9554 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9555 input->sw_idx, queue); 9556 if (!err) 9557 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9558 spin_unlock(&adapter->fdir_perfect_lock); 9559 9560 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9561 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9562 9563 kfree(mask); 9564 return err; 9565 err_out_w_lock: 9566 spin_unlock(&adapter->fdir_perfect_lock); 9567 err_out: 9568 kfree(mask); 9569 free_input: 9570 kfree(input); 9571 free_jump: 9572 kfree(jump); 9573 return err; 9574 } 9575 9576 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9577 struct tc_cls_u32_offload *cls_u32) 9578 { 9579 switch (cls_u32->command) { 9580 case TC_CLSU32_NEW_KNODE: 9581 case TC_CLSU32_REPLACE_KNODE: 9582 return ixgbe_configure_clsu32(adapter, cls_u32); 9583 case TC_CLSU32_DELETE_KNODE: 9584 return ixgbe_delete_clsu32(adapter, cls_u32); 9585 case TC_CLSU32_NEW_HNODE: 9586 case TC_CLSU32_REPLACE_HNODE: 9587 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9588 case TC_CLSU32_DELETE_HNODE: 9589 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9590 default: 9591 return -EOPNOTSUPP; 9592 } 9593 } 9594 9595 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9596 void *cb_priv) 9597 { 9598 struct ixgbe_adapter *adapter = cb_priv; 9599 9600 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9601 return -EOPNOTSUPP; 9602 9603 switch (type) { 9604 case TC_SETUP_CLSU32: 9605 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9606 default: 9607 return -EOPNOTSUPP; 9608 } 9609 } 9610 9611 static int ixgbe_setup_tc_block(struct net_device *dev, 9612 struct tc_block_offload *f) 9613 { 9614 struct ixgbe_adapter *adapter = netdev_priv(dev); 9615 9616 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9617 return -EOPNOTSUPP; 9618 9619 switch (f->command) { 9620 case TC_BLOCK_BIND: 9621 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9622 adapter, adapter, f->extack); 9623 case TC_BLOCK_UNBIND: 9624 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9625 adapter); 9626 return 0; 9627 default: 9628 return -EOPNOTSUPP; 9629 } 9630 } 9631 9632 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9633 struct tc_mqprio_qopt *mqprio) 9634 { 9635 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9636 return ixgbe_setup_tc(dev, mqprio->num_tc); 9637 } 9638 9639 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9640 void *type_data) 9641 { 9642 switch (type) { 9643 case TC_SETUP_BLOCK: 9644 return ixgbe_setup_tc_block(dev, type_data); 9645 case TC_SETUP_QDISC_MQPRIO: 9646 return ixgbe_setup_tc_mqprio(dev, type_data); 9647 default: 9648 return -EOPNOTSUPP; 9649 } 9650 } 9651 9652 #ifdef CONFIG_PCI_IOV 9653 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9654 { 9655 struct net_device *netdev = adapter->netdev; 9656 9657 rtnl_lock(); 9658 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9659 rtnl_unlock(); 9660 } 9661 9662 #endif 9663 void ixgbe_do_reset(struct net_device *netdev) 9664 { 9665 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9666 9667 if (netif_running(netdev)) 9668 ixgbe_reinit_locked(adapter); 9669 else 9670 ixgbe_reset(adapter); 9671 } 9672 9673 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9674 netdev_features_t features) 9675 { 9676 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9677 9678 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9679 if (!(features & NETIF_F_RXCSUM)) 9680 features &= ~NETIF_F_LRO; 9681 9682 /* Turn off LRO if not RSC capable */ 9683 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9684 features &= ~NETIF_F_LRO; 9685 9686 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9687 e_dev_err("LRO is not supported with XDP\n"); 9688 features &= ~NETIF_F_LRO; 9689 } 9690 9691 return features; 9692 } 9693 9694 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9695 { 9696 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9697 num_online_cpus()); 9698 9699 /* go back to full RSS if we're not running SR-IOV */ 9700 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9701 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9702 IXGBE_FLAG_SRIOV_ENABLED); 9703 9704 adapter->ring_feature[RING_F_RSS].limit = rss; 9705 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9706 9707 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9708 } 9709 9710 static int ixgbe_set_features(struct net_device *netdev, 9711 netdev_features_t features) 9712 { 9713 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9714 netdev_features_t changed = netdev->features ^ features; 9715 bool need_reset = false; 9716 9717 /* Make sure RSC matches LRO, reset if change */ 9718 if (!(features & NETIF_F_LRO)) { 9719 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9720 need_reset = true; 9721 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9722 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9723 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9724 if (adapter->rx_itr_setting == 1 || 9725 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9726 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9727 need_reset = true; 9728 } else if ((changed ^ features) & NETIF_F_LRO) { 9729 e_info(probe, "rx-usecs set too low, " 9730 "disabling RSC\n"); 9731 } 9732 } 9733 9734 /* 9735 * Check if Flow Director n-tuple support or hw_tc support was 9736 * enabled or disabled. If the state changed, we need to reset. 9737 */ 9738 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9739 /* turn off ATR, enable perfect filters and reset */ 9740 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9741 need_reset = true; 9742 9743 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9744 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9745 } else { 9746 /* turn off perfect filters, enable ATR and reset */ 9747 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9748 need_reset = true; 9749 9750 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9751 9752 /* We cannot enable ATR if SR-IOV is enabled */ 9753 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9754 /* We cannot enable ATR if we have 2 or more tcs */ 9755 (adapter->hw_tcs > 1) || 9756 /* We cannot enable ATR if RSS is disabled */ 9757 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9758 /* A sample rate of 0 indicates ATR disabled */ 9759 (!adapter->atr_sample_rate)) 9760 ; /* do nothing not supported */ 9761 else /* otherwise supported and set the flag */ 9762 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9763 } 9764 9765 if (changed & NETIF_F_RXALL) 9766 need_reset = true; 9767 9768 netdev->features = features; 9769 9770 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9771 if (features & NETIF_F_RXCSUM) { 9772 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9773 } else { 9774 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9775 9776 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9777 } 9778 } 9779 9780 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9781 if (features & NETIF_F_RXCSUM) { 9782 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9783 } else { 9784 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9785 9786 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9787 } 9788 } 9789 9790 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9791 ixgbe_reset_l2fw_offload(adapter); 9792 else if (need_reset) 9793 ixgbe_do_reset(netdev); 9794 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9795 NETIF_F_HW_VLAN_CTAG_FILTER)) 9796 ixgbe_set_rx_mode(netdev); 9797 9798 return 0; 9799 } 9800 9801 /** 9802 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9803 * @dev: The port's netdev 9804 * @ti: Tunnel endpoint information 9805 **/ 9806 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9807 struct udp_tunnel_info *ti) 9808 { 9809 struct ixgbe_adapter *adapter = netdev_priv(dev); 9810 struct ixgbe_hw *hw = &adapter->hw; 9811 __be16 port = ti->port; 9812 u32 port_shift = 0; 9813 u32 reg; 9814 9815 if (ti->sa_family != AF_INET) 9816 return; 9817 9818 switch (ti->type) { 9819 case UDP_TUNNEL_TYPE_VXLAN: 9820 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9821 return; 9822 9823 if (adapter->vxlan_port == port) 9824 return; 9825 9826 if (adapter->vxlan_port) { 9827 netdev_info(dev, 9828 "VXLAN port %d set, not adding port %d\n", 9829 ntohs(adapter->vxlan_port), 9830 ntohs(port)); 9831 return; 9832 } 9833 9834 adapter->vxlan_port = port; 9835 break; 9836 case UDP_TUNNEL_TYPE_GENEVE: 9837 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9838 return; 9839 9840 if (adapter->geneve_port == port) 9841 return; 9842 9843 if (adapter->geneve_port) { 9844 netdev_info(dev, 9845 "GENEVE port %d set, not adding port %d\n", 9846 ntohs(adapter->geneve_port), 9847 ntohs(port)); 9848 return; 9849 } 9850 9851 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9852 adapter->geneve_port = port; 9853 break; 9854 default: 9855 return; 9856 } 9857 9858 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9859 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9860 } 9861 9862 /** 9863 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9864 * @dev: The port's netdev 9865 * @ti: Tunnel endpoint information 9866 **/ 9867 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9868 struct udp_tunnel_info *ti) 9869 { 9870 struct ixgbe_adapter *adapter = netdev_priv(dev); 9871 u32 port_mask; 9872 9873 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9874 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9875 return; 9876 9877 if (ti->sa_family != AF_INET) 9878 return; 9879 9880 switch (ti->type) { 9881 case UDP_TUNNEL_TYPE_VXLAN: 9882 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9883 return; 9884 9885 if (adapter->vxlan_port != ti->port) { 9886 netdev_info(dev, "VXLAN port %d not found\n", 9887 ntohs(ti->port)); 9888 return; 9889 } 9890 9891 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9892 break; 9893 case UDP_TUNNEL_TYPE_GENEVE: 9894 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9895 return; 9896 9897 if (adapter->geneve_port != ti->port) { 9898 netdev_info(dev, "GENEVE port %d not found\n", 9899 ntohs(ti->port)); 9900 return; 9901 } 9902 9903 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9904 break; 9905 default: 9906 return; 9907 } 9908 9909 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9910 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9911 } 9912 9913 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9914 struct net_device *dev, 9915 const unsigned char *addr, u16 vid, 9916 u16 flags) 9917 { 9918 /* guarantee we can provide a unique filter for the unicast address */ 9919 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9920 struct ixgbe_adapter *adapter = netdev_priv(dev); 9921 u16 pool = VMDQ_P(0); 9922 9923 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9924 return -ENOMEM; 9925 } 9926 9927 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9928 } 9929 9930 /** 9931 * ixgbe_configure_bridge_mode - set various bridge modes 9932 * @adapter: the private structure 9933 * @mode: requested bridge mode 9934 * 9935 * Configure some settings require for various bridge modes. 9936 **/ 9937 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9938 __u16 mode) 9939 { 9940 struct ixgbe_hw *hw = &adapter->hw; 9941 unsigned int p, num_pools; 9942 u32 vmdctl; 9943 9944 switch (mode) { 9945 case BRIDGE_MODE_VEPA: 9946 /* disable Tx loopback, rely on switch hairpin mode */ 9947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9948 9949 /* must enable Rx switching replication to allow multicast 9950 * packet reception on all VFs, and to enable source address 9951 * pruning. 9952 */ 9953 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9954 vmdctl |= IXGBE_VT_CTL_REPLEN; 9955 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9956 9957 /* enable Rx source address pruning. Note, this requires 9958 * replication to be enabled or else it does nothing. 9959 */ 9960 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9961 for (p = 0; p < num_pools; p++) { 9962 if (hw->mac.ops.set_source_address_pruning) 9963 hw->mac.ops.set_source_address_pruning(hw, 9964 true, 9965 p); 9966 } 9967 break; 9968 case BRIDGE_MODE_VEB: 9969 /* enable Tx loopback for internal VF/PF communication */ 9970 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9971 IXGBE_PFDTXGSWC_VT_LBEN); 9972 9973 /* disable Rx switching replication unless we have SR-IOV 9974 * virtual functions 9975 */ 9976 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9977 if (!adapter->num_vfs) 9978 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9979 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9980 9981 /* disable Rx source address pruning, since we don't expect to 9982 * be receiving external loopback of our transmitted frames. 9983 */ 9984 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9985 for (p = 0; p < num_pools; p++) { 9986 if (hw->mac.ops.set_source_address_pruning) 9987 hw->mac.ops.set_source_address_pruning(hw, 9988 false, 9989 p); 9990 } 9991 break; 9992 default: 9993 return -EINVAL; 9994 } 9995 9996 adapter->bridge_mode = mode; 9997 9998 e_info(drv, "enabling bridge mode: %s\n", 9999 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10000 10001 return 0; 10002 } 10003 10004 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10005 struct nlmsghdr *nlh, u16 flags, 10006 struct netlink_ext_ack *extack) 10007 { 10008 struct ixgbe_adapter *adapter = netdev_priv(dev); 10009 struct nlattr *attr, *br_spec; 10010 int rem; 10011 10012 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10013 return -EOPNOTSUPP; 10014 10015 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10016 if (!br_spec) 10017 return -EINVAL; 10018 10019 nla_for_each_nested(attr, br_spec, rem) { 10020 int status; 10021 __u16 mode; 10022 10023 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10024 continue; 10025 10026 if (nla_len(attr) < sizeof(mode)) 10027 return -EINVAL; 10028 10029 mode = nla_get_u16(attr); 10030 status = ixgbe_configure_bridge_mode(adapter, mode); 10031 if (status) 10032 return status; 10033 10034 break; 10035 } 10036 10037 return 0; 10038 } 10039 10040 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10041 struct net_device *dev, 10042 u32 filter_mask, int nlflags) 10043 { 10044 struct ixgbe_adapter *adapter = netdev_priv(dev); 10045 10046 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10047 return 0; 10048 10049 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10050 adapter->bridge_mode, 0, 0, nlflags, 10051 filter_mask, NULL); 10052 } 10053 10054 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10055 { 10056 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10057 struct ixgbe_fwd_adapter *accel; 10058 int tcs = adapter->hw_tcs ? : 1; 10059 int pool, err; 10060 10061 if (adapter->xdp_prog) { 10062 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10063 return ERR_PTR(-EINVAL); 10064 } 10065 10066 /* The hardware supported by ixgbe only filters on the destination MAC 10067 * address. In order to avoid issues we only support offloading modes 10068 * where the hardware can actually provide the functionality. 10069 */ 10070 if (!macvlan_supports_dest_filter(vdev)) 10071 return ERR_PTR(-EMEDIUMTYPE); 10072 10073 /* We need to lock down the macvlan to be a single queue device so that 10074 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10075 * the queue mapping to our netdev. 10076 */ 10077 if (netif_is_multiqueue(vdev)) 10078 return ERR_PTR(-ERANGE); 10079 10080 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10081 if (pool == adapter->num_rx_pools) { 10082 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10083 u16 reserved_pools; 10084 10085 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10086 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10087 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10088 return ERR_PTR(-EBUSY); 10089 10090 /* Hardware has a limited number of available pools. Each VF, 10091 * and the PF require a pool. Check to ensure we don't 10092 * attempt to use more then the available number of pools. 10093 */ 10094 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10095 return ERR_PTR(-EBUSY); 10096 10097 /* Enable VMDq flag so device will be set in VM mode */ 10098 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10099 IXGBE_FLAG_SRIOV_ENABLED; 10100 10101 /* Try to reserve as many queues per pool as possible, 10102 * we start with the configurations that support 4 queues 10103 * per pools, followed by 2, and then by just 1 per pool. 10104 */ 10105 if (used_pools < 32 && adapter->num_rx_pools < 16) 10106 reserved_pools = min_t(u16, 10107 32 - used_pools, 10108 16 - adapter->num_rx_pools); 10109 else if (adapter->num_rx_pools < 32) 10110 reserved_pools = min_t(u16, 10111 64 - used_pools, 10112 32 - adapter->num_rx_pools); 10113 else 10114 reserved_pools = 64 - used_pools; 10115 10116 10117 if (!reserved_pools) 10118 return ERR_PTR(-EBUSY); 10119 10120 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10121 10122 /* Force reinit of ring allocation with VMDQ enabled */ 10123 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10124 if (err) 10125 return ERR_PTR(err); 10126 10127 if (pool >= adapter->num_rx_pools) 10128 return ERR_PTR(-ENOMEM); 10129 } 10130 10131 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10132 if (!accel) 10133 return ERR_PTR(-ENOMEM); 10134 10135 set_bit(pool, adapter->fwd_bitmask); 10136 netdev_set_sb_channel(vdev, pool); 10137 accel->pool = pool; 10138 accel->netdev = vdev; 10139 10140 if (!netif_running(pdev)) 10141 return accel; 10142 10143 err = ixgbe_fwd_ring_up(adapter, accel); 10144 if (err) 10145 return ERR_PTR(err); 10146 10147 return accel; 10148 } 10149 10150 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10151 { 10152 struct ixgbe_fwd_adapter *accel = priv; 10153 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10154 unsigned int rxbase = accel->rx_base_queue; 10155 unsigned int i; 10156 10157 /* delete unicast filter associated with offloaded interface */ 10158 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10159 VMDQ_P(accel->pool)); 10160 10161 /* Allow remaining Rx packets to get flushed out of the 10162 * Rx FIFO before we drop the netdev for the ring. 10163 */ 10164 usleep_range(10000, 20000); 10165 10166 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10167 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10168 struct ixgbe_q_vector *qv = ring->q_vector; 10169 10170 /* Make sure we aren't processing any packets and clear 10171 * netdev to shut down the ring. 10172 */ 10173 if (netif_running(adapter->netdev)) 10174 napi_synchronize(&qv->napi); 10175 ring->netdev = NULL; 10176 } 10177 10178 /* unbind the queues and drop the subordinate channel config */ 10179 netdev_unbind_sb_channel(pdev, accel->netdev); 10180 netdev_set_sb_channel(accel->netdev, 0); 10181 10182 clear_bit(accel->pool, adapter->fwd_bitmask); 10183 kfree(accel); 10184 } 10185 10186 #define IXGBE_MAX_MAC_HDR_LEN 127 10187 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10188 10189 static netdev_features_t 10190 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10191 netdev_features_t features) 10192 { 10193 unsigned int network_hdr_len, mac_hdr_len; 10194 10195 /* Make certain the headers can be described by a context descriptor */ 10196 mac_hdr_len = skb_network_header(skb) - skb->data; 10197 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10198 return features & ~(NETIF_F_HW_CSUM | 10199 NETIF_F_SCTP_CRC | 10200 NETIF_F_HW_VLAN_CTAG_TX | 10201 NETIF_F_TSO | 10202 NETIF_F_TSO6); 10203 10204 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10205 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10206 return features & ~(NETIF_F_HW_CSUM | 10207 NETIF_F_SCTP_CRC | 10208 NETIF_F_TSO | 10209 NETIF_F_TSO6); 10210 10211 /* We can only support IPV4 TSO in tunnels if we can mangle the 10212 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10213 * IPsec offoad sets skb->encapsulation but still can handle 10214 * the TSO, so it's the exception. 10215 */ 10216 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10217 #ifdef CONFIG_IXGBE_IPSEC 10218 if (!secpath_exists(skb)) 10219 #endif 10220 features &= ~NETIF_F_TSO; 10221 } 10222 10223 return features; 10224 } 10225 10226 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10227 { 10228 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10229 struct ixgbe_adapter *adapter = netdev_priv(dev); 10230 struct bpf_prog *old_prog; 10231 bool need_reset; 10232 10233 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10234 return -EINVAL; 10235 10236 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10237 return -EINVAL; 10238 10239 /* verify ixgbe ring attributes are sufficient for XDP */ 10240 for (i = 0; i < adapter->num_rx_queues; i++) { 10241 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10242 10243 if (ring_is_rsc_enabled(ring)) 10244 return -EINVAL; 10245 10246 if (frame_size > ixgbe_rx_bufsz(ring)) 10247 return -EINVAL; 10248 } 10249 10250 if (nr_cpu_ids > MAX_XDP_QUEUES) 10251 return -ENOMEM; 10252 10253 old_prog = xchg(&adapter->xdp_prog, prog); 10254 need_reset = (!!prog != !!old_prog); 10255 10256 /* If transitioning XDP modes reconfigure rings */ 10257 if (need_reset) { 10258 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10259 10260 if (err) { 10261 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10262 return -EINVAL; 10263 } 10264 } else { 10265 for (i = 0; i < adapter->num_rx_queues; i++) 10266 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 10267 adapter->xdp_prog); 10268 } 10269 10270 if (old_prog) 10271 bpf_prog_put(old_prog); 10272 10273 /* Kick start the NAPI context if there is an AF_XDP socket open 10274 * on that queue id. This so that receiving will start. 10275 */ 10276 if (need_reset && prog) 10277 for (i = 0; i < adapter->num_rx_queues; i++) 10278 if (adapter->xdp_ring[i]->xsk_umem) 10279 (void)ixgbe_xsk_async_xmit(adapter->netdev, i); 10280 10281 return 0; 10282 } 10283 10284 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10285 { 10286 struct ixgbe_adapter *adapter = netdev_priv(dev); 10287 10288 switch (xdp->command) { 10289 case XDP_SETUP_PROG: 10290 return ixgbe_xdp_setup(dev, xdp->prog); 10291 case XDP_QUERY_PROG: 10292 xdp->prog_id = adapter->xdp_prog ? 10293 adapter->xdp_prog->aux->id : 0; 10294 return 0; 10295 case XDP_QUERY_XSK_UMEM: 10296 return ixgbe_xsk_umem_query(adapter, &xdp->xsk.umem, 10297 xdp->xsk.queue_id); 10298 case XDP_SETUP_XSK_UMEM: 10299 return ixgbe_xsk_umem_setup(adapter, xdp->xsk.umem, 10300 xdp->xsk.queue_id); 10301 10302 default: 10303 return -EINVAL; 10304 } 10305 } 10306 10307 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10308 { 10309 /* Force memory writes to complete before letting h/w know there 10310 * are new descriptors to fetch. 10311 */ 10312 wmb(); 10313 writel(ring->next_to_use, ring->tail); 10314 } 10315 10316 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10317 struct xdp_frame **frames, u32 flags) 10318 { 10319 struct ixgbe_adapter *adapter = netdev_priv(dev); 10320 struct ixgbe_ring *ring; 10321 int drops = 0; 10322 int i; 10323 10324 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10325 return -ENETDOWN; 10326 10327 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10328 return -EINVAL; 10329 10330 /* During program transitions its possible adapter->xdp_prog is assigned 10331 * but ring has not been configured yet. In this case simply abort xmit. 10332 */ 10333 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10334 if (unlikely(!ring)) 10335 return -ENXIO; 10336 10337 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10338 return -ENXIO; 10339 10340 for (i = 0; i < n; i++) { 10341 struct xdp_frame *xdpf = frames[i]; 10342 int err; 10343 10344 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10345 if (err != IXGBE_XDP_TX) { 10346 xdp_return_frame_rx_napi(xdpf); 10347 drops++; 10348 } 10349 } 10350 10351 if (unlikely(flags & XDP_XMIT_FLUSH)) 10352 ixgbe_xdp_ring_update_tail(ring); 10353 10354 return n - drops; 10355 } 10356 10357 static const struct net_device_ops ixgbe_netdev_ops = { 10358 .ndo_open = ixgbe_open, 10359 .ndo_stop = ixgbe_close, 10360 .ndo_start_xmit = ixgbe_xmit_frame, 10361 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10362 .ndo_validate_addr = eth_validate_addr, 10363 .ndo_set_mac_address = ixgbe_set_mac, 10364 .ndo_change_mtu = ixgbe_change_mtu, 10365 .ndo_tx_timeout = ixgbe_tx_timeout, 10366 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10367 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10368 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10369 .ndo_do_ioctl = ixgbe_ioctl, 10370 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10371 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10372 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10373 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10374 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10375 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10376 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10377 .ndo_get_stats64 = ixgbe_get_stats64, 10378 .ndo_setup_tc = __ixgbe_setup_tc, 10379 #ifdef IXGBE_FCOE 10380 .ndo_select_queue = ixgbe_select_queue, 10381 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10382 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10383 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10384 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10385 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10386 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10387 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10388 #endif /* IXGBE_FCOE */ 10389 .ndo_set_features = ixgbe_set_features, 10390 .ndo_fix_features = ixgbe_fix_features, 10391 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10392 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10393 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10394 .ndo_dfwd_add_station = ixgbe_fwd_add, 10395 .ndo_dfwd_del_station = ixgbe_fwd_del, 10396 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10397 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10398 .ndo_features_check = ixgbe_features_check, 10399 .ndo_bpf = ixgbe_xdp, 10400 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10401 .ndo_xsk_async_xmit = ixgbe_xsk_async_xmit, 10402 }; 10403 10404 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10405 struct ixgbe_ring *tx_ring) 10406 { 10407 unsigned long wait_delay, delay_interval; 10408 struct ixgbe_hw *hw = &adapter->hw; 10409 u8 reg_idx = tx_ring->reg_idx; 10410 int wait_loop; 10411 u32 txdctl; 10412 10413 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10414 10415 /* delay mechanism from ixgbe_disable_tx */ 10416 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10417 10418 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10419 wait_delay = delay_interval; 10420 10421 while (wait_loop--) { 10422 usleep_range(wait_delay, wait_delay + 10); 10423 wait_delay += delay_interval * 2; 10424 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10425 10426 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10427 return; 10428 } 10429 10430 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10431 } 10432 10433 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10434 struct ixgbe_ring *tx_ring) 10435 { 10436 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10437 ixgbe_disable_txr_hw(adapter, tx_ring); 10438 } 10439 10440 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10441 struct ixgbe_ring *rx_ring) 10442 { 10443 unsigned long wait_delay, delay_interval; 10444 struct ixgbe_hw *hw = &adapter->hw; 10445 u8 reg_idx = rx_ring->reg_idx; 10446 int wait_loop; 10447 u32 rxdctl; 10448 10449 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10450 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10451 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10452 10453 /* write value back with RXDCTL.ENABLE bit cleared */ 10454 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10455 10456 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10457 if (hw->mac.type == ixgbe_mac_82598EB && 10458 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10459 return; 10460 10461 /* delay mechanism from ixgbe_disable_rx */ 10462 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10463 10464 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10465 wait_delay = delay_interval; 10466 10467 while (wait_loop--) { 10468 usleep_range(wait_delay, wait_delay + 10); 10469 wait_delay += delay_interval * 2; 10470 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10471 10472 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10473 return; 10474 } 10475 10476 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10477 } 10478 10479 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10480 { 10481 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10482 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10483 } 10484 10485 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10486 { 10487 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10488 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10489 } 10490 10491 /** 10492 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10493 * @adapter: adapter structure 10494 * @ring: ring index 10495 * 10496 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10497 * assumes that the netdev is running. 10498 **/ 10499 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10500 { 10501 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10502 10503 rx_ring = adapter->rx_ring[ring]; 10504 tx_ring = adapter->tx_ring[ring]; 10505 xdp_ring = adapter->xdp_ring[ring]; 10506 10507 ixgbe_disable_txr(adapter, tx_ring); 10508 if (xdp_ring) 10509 ixgbe_disable_txr(adapter, xdp_ring); 10510 ixgbe_disable_rxr_hw(adapter, rx_ring); 10511 10512 if (xdp_ring) 10513 synchronize_rcu(); 10514 10515 /* Rx/Tx/XDP Tx share the same napi context. */ 10516 napi_disable(&rx_ring->q_vector->napi); 10517 10518 ixgbe_clean_tx_ring(tx_ring); 10519 if (xdp_ring) 10520 ixgbe_clean_tx_ring(xdp_ring); 10521 ixgbe_clean_rx_ring(rx_ring); 10522 10523 ixgbe_reset_txr_stats(tx_ring); 10524 if (xdp_ring) 10525 ixgbe_reset_txr_stats(xdp_ring); 10526 ixgbe_reset_rxr_stats(rx_ring); 10527 } 10528 10529 /** 10530 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10531 * @adapter: adapter structure 10532 * @ring: ring index 10533 * 10534 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10535 * assumes that the netdev is running. 10536 **/ 10537 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10538 { 10539 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10540 10541 rx_ring = adapter->rx_ring[ring]; 10542 tx_ring = adapter->tx_ring[ring]; 10543 xdp_ring = adapter->xdp_ring[ring]; 10544 10545 /* Rx/Tx/XDP Tx share the same napi context. */ 10546 napi_enable(&rx_ring->q_vector->napi); 10547 10548 ixgbe_configure_tx_ring(adapter, tx_ring); 10549 if (xdp_ring) 10550 ixgbe_configure_tx_ring(adapter, xdp_ring); 10551 ixgbe_configure_rx_ring(adapter, rx_ring); 10552 10553 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10554 if (xdp_ring) 10555 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10556 } 10557 10558 /** 10559 * ixgbe_enumerate_functions - Get the number of ports this device has 10560 * @adapter: adapter structure 10561 * 10562 * This function enumerates the phsyical functions co-located on a single slot, 10563 * in order to determine how many ports a device has. This is most useful in 10564 * determining the required GT/s of PCIe bandwidth necessary for optimal 10565 * performance. 10566 **/ 10567 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10568 { 10569 struct pci_dev *entry, *pdev = adapter->pdev; 10570 int physfns = 0; 10571 10572 /* Some cards can not use the generic count PCIe functions method, 10573 * because they are behind a parent switch, so we hardcode these with 10574 * the correct number of functions. 10575 */ 10576 if (ixgbe_pcie_from_parent(&adapter->hw)) 10577 physfns = 4; 10578 10579 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10580 /* don't count virtual functions */ 10581 if (entry->is_virtfn) 10582 continue; 10583 10584 /* When the devices on the bus don't all match our device ID, 10585 * we can't reliably determine the correct number of 10586 * functions. This can occur if a function has been direct 10587 * attached to a virtual machine using VT-d, for example. In 10588 * this case, simply return -1 to indicate this. 10589 */ 10590 if ((entry->vendor != pdev->vendor) || 10591 (entry->device != pdev->device)) 10592 return -1; 10593 10594 physfns++; 10595 } 10596 10597 return physfns; 10598 } 10599 10600 /** 10601 * ixgbe_wol_supported - Check whether device supports WoL 10602 * @adapter: the adapter private structure 10603 * @device_id: the device ID 10604 * @subdevice_id: the subsystem device ID 10605 * 10606 * This function is used by probe and ethtool to determine 10607 * which devices have WoL support 10608 * 10609 **/ 10610 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10611 u16 subdevice_id) 10612 { 10613 struct ixgbe_hw *hw = &adapter->hw; 10614 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10615 10616 /* WOL not supported on 82598 */ 10617 if (hw->mac.type == ixgbe_mac_82598EB) 10618 return false; 10619 10620 /* check eeprom to see if WOL is enabled for X540 and newer */ 10621 if (hw->mac.type >= ixgbe_mac_X540) { 10622 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10623 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10624 (hw->bus.func == 0))) 10625 return true; 10626 } 10627 10628 /* WOL is determined based on device IDs for 82599 MACs */ 10629 switch (device_id) { 10630 case IXGBE_DEV_ID_82599_SFP: 10631 /* Only these subdevices could supports WOL */ 10632 switch (subdevice_id) { 10633 case IXGBE_SUBDEV_ID_82599_560FLR: 10634 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10635 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10636 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10637 /* only support first port */ 10638 if (hw->bus.func != 0) 10639 break; 10640 /* fall through */ 10641 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10642 case IXGBE_SUBDEV_ID_82599_SFP: 10643 case IXGBE_SUBDEV_ID_82599_RNDC: 10644 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10645 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10646 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10647 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10648 return true; 10649 } 10650 break; 10651 case IXGBE_DEV_ID_82599EN_SFP: 10652 /* Only these subdevices support WOL */ 10653 switch (subdevice_id) { 10654 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10655 return true; 10656 } 10657 break; 10658 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10659 /* All except this subdevice support WOL */ 10660 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10661 return true; 10662 break; 10663 case IXGBE_DEV_ID_82599_KX4: 10664 return true; 10665 default: 10666 break; 10667 } 10668 10669 return false; 10670 } 10671 10672 /** 10673 * ixgbe_set_fw_version - Set FW version 10674 * @adapter: the adapter private structure 10675 * 10676 * This function is used by probe and ethtool to determine the FW version to 10677 * format to display. The FW version is taken from the EEPROM/NVM. 10678 */ 10679 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10680 { 10681 struct ixgbe_hw *hw = &adapter->hw; 10682 struct ixgbe_nvm_version nvm_ver; 10683 10684 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10685 if (nvm_ver.oem_valid) { 10686 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10687 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10688 nvm_ver.oem_release); 10689 return; 10690 } 10691 10692 ixgbe_get_etk_id(hw, &nvm_ver); 10693 ixgbe_get_orom_version(hw, &nvm_ver); 10694 10695 if (nvm_ver.or_valid) { 10696 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10697 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10698 nvm_ver.or_build, nvm_ver.or_patch); 10699 return; 10700 } 10701 10702 /* Set ETrack ID format */ 10703 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10704 "0x%08x", nvm_ver.etk_id); 10705 } 10706 10707 /** 10708 * ixgbe_probe - Device Initialization Routine 10709 * @pdev: PCI device information struct 10710 * @ent: entry in ixgbe_pci_tbl 10711 * 10712 * Returns 0 on success, negative on failure 10713 * 10714 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10715 * The OS initialization, configuring of the adapter private structure, 10716 * and a hardware reset occur. 10717 **/ 10718 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10719 { 10720 struct net_device *netdev; 10721 struct ixgbe_adapter *adapter = NULL; 10722 struct ixgbe_hw *hw; 10723 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10724 int i, err, pci_using_dac, expected_gts; 10725 unsigned int indices = MAX_TX_QUEUES; 10726 u8 part_str[IXGBE_PBANUM_LENGTH]; 10727 bool disable_dev = false; 10728 #ifdef IXGBE_FCOE 10729 u16 device_caps; 10730 #endif 10731 u32 eec; 10732 10733 /* Catch broken hardware that put the wrong VF device ID in 10734 * the PCIe SR-IOV capability. 10735 */ 10736 if (pdev->is_virtfn) { 10737 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10738 pci_name(pdev), pdev->vendor, pdev->device); 10739 return -EINVAL; 10740 } 10741 10742 err = pci_enable_device_mem(pdev); 10743 if (err) 10744 return err; 10745 10746 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10747 pci_using_dac = 1; 10748 } else { 10749 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10750 if (err) { 10751 dev_err(&pdev->dev, 10752 "No usable DMA configuration, aborting\n"); 10753 goto err_dma; 10754 } 10755 pci_using_dac = 0; 10756 } 10757 10758 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10759 if (err) { 10760 dev_err(&pdev->dev, 10761 "pci_request_selected_regions failed 0x%x\n", err); 10762 goto err_pci_reg; 10763 } 10764 10765 pci_enable_pcie_error_reporting(pdev); 10766 10767 pci_set_master(pdev); 10768 pci_save_state(pdev); 10769 10770 if (ii->mac == ixgbe_mac_82598EB) { 10771 #ifdef CONFIG_IXGBE_DCB 10772 /* 8 TC w/ 4 queues per TC */ 10773 indices = 4 * MAX_TRAFFIC_CLASS; 10774 #else 10775 indices = IXGBE_MAX_RSS_INDICES; 10776 #endif 10777 } 10778 10779 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10780 if (!netdev) { 10781 err = -ENOMEM; 10782 goto err_alloc_etherdev; 10783 } 10784 10785 SET_NETDEV_DEV(netdev, &pdev->dev); 10786 10787 adapter = netdev_priv(netdev); 10788 10789 adapter->netdev = netdev; 10790 adapter->pdev = pdev; 10791 hw = &adapter->hw; 10792 hw->back = adapter; 10793 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10794 10795 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10796 pci_resource_len(pdev, 0)); 10797 adapter->io_addr = hw->hw_addr; 10798 if (!hw->hw_addr) { 10799 err = -EIO; 10800 goto err_ioremap; 10801 } 10802 10803 netdev->netdev_ops = &ixgbe_netdev_ops; 10804 ixgbe_set_ethtool_ops(netdev); 10805 netdev->watchdog_timeo = 5 * HZ; 10806 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10807 10808 /* Setup hw api */ 10809 hw->mac.ops = *ii->mac_ops; 10810 hw->mac.type = ii->mac; 10811 hw->mvals = ii->mvals; 10812 if (ii->link_ops) 10813 hw->link.ops = *ii->link_ops; 10814 10815 /* EEPROM */ 10816 hw->eeprom.ops = *ii->eeprom_ops; 10817 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10818 if (ixgbe_removed(hw->hw_addr)) { 10819 err = -EIO; 10820 goto err_ioremap; 10821 } 10822 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10823 if (!(eec & BIT(8))) 10824 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10825 10826 /* PHY */ 10827 hw->phy.ops = *ii->phy_ops; 10828 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10829 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10830 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10831 hw->phy.mdio.mmds = 0; 10832 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10833 hw->phy.mdio.dev = netdev; 10834 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10835 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10836 10837 /* setup the private structure */ 10838 err = ixgbe_sw_init(adapter, ii); 10839 if (err) 10840 goto err_sw_init; 10841 10842 /* Make sure the SWFW semaphore is in a valid state */ 10843 if (hw->mac.ops.init_swfw_sync) 10844 hw->mac.ops.init_swfw_sync(hw); 10845 10846 /* Make it possible the adapter to be woken up via WOL */ 10847 switch (adapter->hw.mac.type) { 10848 case ixgbe_mac_82599EB: 10849 case ixgbe_mac_X540: 10850 case ixgbe_mac_X550: 10851 case ixgbe_mac_X550EM_x: 10852 case ixgbe_mac_x550em_a: 10853 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10854 break; 10855 default: 10856 break; 10857 } 10858 10859 /* 10860 * If there is a fan on this device and it has failed log the 10861 * failure. 10862 */ 10863 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10864 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10865 if (esdp & IXGBE_ESDP_SDP1) 10866 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10867 } 10868 10869 if (allow_unsupported_sfp) 10870 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10871 10872 /* reset_hw fills in the perm_addr as well */ 10873 hw->phy.reset_if_overtemp = true; 10874 err = hw->mac.ops.reset_hw(hw); 10875 hw->phy.reset_if_overtemp = false; 10876 ixgbe_set_eee_capable(adapter); 10877 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10878 err = 0; 10879 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10880 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10881 e_dev_err("Reload the driver after installing a supported module.\n"); 10882 goto err_sw_init; 10883 } else if (err) { 10884 e_dev_err("HW Init failed: %d\n", err); 10885 goto err_sw_init; 10886 } 10887 10888 #ifdef CONFIG_PCI_IOV 10889 /* SR-IOV not supported on the 82598 */ 10890 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10891 goto skip_sriov; 10892 /* Mailbox */ 10893 ixgbe_init_mbx_params_pf(hw); 10894 hw->mbx.ops = ii->mbx_ops; 10895 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10896 ixgbe_enable_sriov(adapter, max_vfs); 10897 skip_sriov: 10898 10899 #endif 10900 netdev->features = NETIF_F_SG | 10901 NETIF_F_TSO | 10902 NETIF_F_TSO6 | 10903 NETIF_F_RXHASH | 10904 NETIF_F_RXCSUM | 10905 NETIF_F_HW_CSUM; 10906 10907 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10908 NETIF_F_GSO_GRE_CSUM | \ 10909 NETIF_F_GSO_IPXIP4 | \ 10910 NETIF_F_GSO_IPXIP6 | \ 10911 NETIF_F_GSO_UDP_TUNNEL | \ 10912 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10913 10914 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10915 netdev->features |= NETIF_F_GSO_PARTIAL | 10916 IXGBE_GSO_PARTIAL_FEATURES; 10917 10918 if (hw->mac.type >= ixgbe_mac_82599EB) 10919 netdev->features |= NETIF_F_SCTP_CRC; 10920 10921 #ifdef CONFIG_IXGBE_IPSEC 10922 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10923 NETIF_F_HW_ESP_TX_CSUM | \ 10924 NETIF_F_GSO_ESP) 10925 10926 if (adapter->ipsec) 10927 netdev->features |= IXGBE_ESP_FEATURES; 10928 #endif 10929 /* copy netdev features into list of user selectable features */ 10930 netdev->hw_features |= netdev->features | 10931 NETIF_F_HW_VLAN_CTAG_FILTER | 10932 NETIF_F_HW_VLAN_CTAG_RX | 10933 NETIF_F_HW_VLAN_CTAG_TX | 10934 NETIF_F_RXALL | 10935 NETIF_F_HW_L2FW_DOFFLOAD; 10936 10937 if (hw->mac.type >= ixgbe_mac_82599EB) 10938 netdev->hw_features |= NETIF_F_NTUPLE | 10939 NETIF_F_HW_TC; 10940 10941 if (pci_using_dac) 10942 netdev->features |= NETIF_F_HIGHDMA; 10943 10944 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10945 netdev->hw_enc_features |= netdev->vlan_features; 10946 netdev->mpls_features |= NETIF_F_SG | 10947 NETIF_F_TSO | 10948 NETIF_F_TSO6 | 10949 NETIF_F_HW_CSUM; 10950 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10951 10952 /* set this bit last since it cannot be part of vlan_features */ 10953 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10954 NETIF_F_HW_VLAN_CTAG_RX | 10955 NETIF_F_HW_VLAN_CTAG_TX; 10956 10957 netdev->priv_flags |= IFF_UNICAST_FLT; 10958 netdev->priv_flags |= IFF_SUPP_NOFCS; 10959 10960 /* MTU range: 68 - 9710 */ 10961 netdev->min_mtu = ETH_MIN_MTU; 10962 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10963 10964 #ifdef CONFIG_IXGBE_DCB 10965 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10966 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10967 #endif 10968 10969 #ifdef IXGBE_FCOE 10970 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10971 unsigned int fcoe_l; 10972 10973 if (hw->mac.ops.get_device_caps) { 10974 hw->mac.ops.get_device_caps(hw, &device_caps); 10975 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10976 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10977 } 10978 10979 10980 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10981 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10982 10983 netdev->features |= NETIF_F_FSO | 10984 NETIF_F_FCOE_CRC; 10985 10986 netdev->vlan_features |= NETIF_F_FSO | 10987 NETIF_F_FCOE_CRC | 10988 NETIF_F_FCOE_MTU; 10989 } 10990 #endif /* IXGBE_FCOE */ 10991 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10992 netdev->hw_features |= NETIF_F_LRO; 10993 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10994 netdev->features |= NETIF_F_LRO; 10995 10996 if (ixgbe_check_fw_error(adapter)) { 10997 err = -EIO; 10998 goto err_sw_init; 10999 } 11000 11001 /* make sure the EEPROM is good */ 11002 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11003 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11004 err = -EIO; 11005 goto err_sw_init; 11006 } 11007 11008 eth_platform_get_mac_address(&adapter->pdev->dev, 11009 adapter->hw.mac.perm_addr); 11010 11011 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 11012 11013 if (!is_valid_ether_addr(netdev->dev_addr)) { 11014 e_dev_err("invalid MAC address\n"); 11015 err = -EIO; 11016 goto err_sw_init; 11017 } 11018 11019 /* Set hw->mac.addr to permanent MAC address */ 11020 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11021 ixgbe_mac_set_default_filter(adapter); 11022 11023 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11024 11025 if (ixgbe_removed(hw->hw_addr)) { 11026 err = -EIO; 11027 goto err_sw_init; 11028 } 11029 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11030 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11031 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11032 11033 err = ixgbe_init_interrupt_scheme(adapter); 11034 if (err) 11035 goto err_sw_init; 11036 11037 for (i = 0; i < adapter->num_rx_queues; i++) 11038 u64_stats_init(&adapter->rx_ring[i]->syncp); 11039 for (i = 0; i < adapter->num_tx_queues; i++) 11040 u64_stats_init(&adapter->tx_ring[i]->syncp); 11041 for (i = 0; i < adapter->num_xdp_queues; i++) 11042 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11043 11044 /* WOL not supported for all devices */ 11045 adapter->wol = 0; 11046 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11047 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11048 pdev->subsystem_device); 11049 if (hw->wol_enabled) 11050 adapter->wol = IXGBE_WUFC_MAG; 11051 11052 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11053 11054 /* save off EEPROM version number */ 11055 ixgbe_set_fw_version(adapter); 11056 11057 /* pick up the PCI bus settings for reporting later */ 11058 if (ixgbe_pcie_from_parent(hw)) 11059 ixgbe_get_parent_bus_info(adapter); 11060 else 11061 hw->mac.ops.get_bus_info(hw); 11062 11063 /* calculate the expected PCIe bandwidth required for optimal 11064 * performance. Note that some older parts will never have enough 11065 * bandwidth due to being older generation PCIe parts. We clamp these 11066 * parts to ensure no warning is displayed if it can't be fixed. 11067 */ 11068 switch (hw->mac.type) { 11069 case ixgbe_mac_82598EB: 11070 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11071 break; 11072 default: 11073 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11074 break; 11075 } 11076 11077 /* don't check link if we failed to enumerate functions */ 11078 if (expected_gts > 0) 11079 ixgbe_check_minimum_link(adapter, expected_gts); 11080 11081 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11082 if (err) 11083 strlcpy(part_str, "Unknown", sizeof(part_str)); 11084 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11085 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11086 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11087 part_str); 11088 else 11089 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11090 hw->mac.type, hw->phy.type, part_str); 11091 11092 e_dev_info("%pM\n", netdev->dev_addr); 11093 11094 /* reset the hardware with the new settings */ 11095 err = hw->mac.ops.start_hw(hw); 11096 if (err == IXGBE_ERR_EEPROM_VERSION) { 11097 /* We are running on a pre-production device, log a warning */ 11098 e_dev_warn("This device is a pre-production adapter/LOM. " 11099 "Please be aware there may be issues associated " 11100 "with your hardware. If you are experiencing " 11101 "problems please contact your Intel or hardware " 11102 "representative who provided you with this " 11103 "hardware.\n"); 11104 } 11105 strcpy(netdev->name, "eth%d"); 11106 pci_set_drvdata(pdev, adapter); 11107 err = register_netdev(netdev); 11108 if (err) 11109 goto err_register; 11110 11111 11112 /* power down the optics for 82599 SFP+ fiber */ 11113 if (hw->mac.ops.disable_tx_laser) 11114 hw->mac.ops.disable_tx_laser(hw); 11115 11116 /* carrier off reporting is important to ethtool even BEFORE open */ 11117 netif_carrier_off(netdev); 11118 11119 #ifdef CONFIG_IXGBE_DCA 11120 if (dca_add_requester(&pdev->dev) == 0) { 11121 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11122 ixgbe_setup_dca(adapter); 11123 } 11124 #endif 11125 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11126 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11127 for (i = 0; i < adapter->num_vfs; i++) 11128 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11129 } 11130 11131 /* firmware requires driver version to be 0xFFFFFFFF 11132 * since os does not support feature 11133 */ 11134 if (hw->mac.ops.set_fw_drv_ver) 11135 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11136 sizeof(ixgbe_driver_version) - 1, 11137 ixgbe_driver_version); 11138 11139 /* add san mac addr to netdev */ 11140 ixgbe_add_sanmac_netdev(netdev); 11141 11142 e_dev_info("%s\n", ixgbe_default_device_descr); 11143 11144 #ifdef CONFIG_IXGBE_HWMON 11145 if (ixgbe_sysfs_init(adapter)) 11146 e_err(probe, "failed to allocate sysfs resources\n"); 11147 #endif /* CONFIG_IXGBE_HWMON */ 11148 11149 ixgbe_dbg_adapter_init(adapter); 11150 11151 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11152 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11153 hw->mac.ops.setup_link(hw, 11154 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11155 true); 11156 11157 ixgbe_mii_bus_init(hw); 11158 11159 return 0; 11160 11161 err_register: 11162 ixgbe_release_hw_control(adapter); 11163 ixgbe_clear_interrupt_scheme(adapter); 11164 err_sw_init: 11165 ixgbe_disable_sriov(adapter); 11166 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11167 iounmap(adapter->io_addr); 11168 kfree(adapter->jump_tables[0]); 11169 kfree(adapter->mac_table); 11170 kfree(adapter->rss_key); 11171 err_ioremap: 11172 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11173 free_netdev(netdev); 11174 err_alloc_etherdev: 11175 pci_release_mem_regions(pdev); 11176 err_pci_reg: 11177 err_dma: 11178 if (!adapter || disable_dev) 11179 pci_disable_device(pdev); 11180 return err; 11181 } 11182 11183 /** 11184 * ixgbe_remove - Device Removal Routine 11185 * @pdev: PCI device information struct 11186 * 11187 * ixgbe_remove is called by the PCI subsystem to alert the driver 11188 * that it should release a PCI device. The could be caused by a 11189 * Hot-Plug event, or because the driver is going to be removed from 11190 * memory. 11191 **/ 11192 static void ixgbe_remove(struct pci_dev *pdev) 11193 { 11194 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11195 struct net_device *netdev; 11196 bool disable_dev; 11197 int i; 11198 11199 /* if !adapter then we already cleaned up in probe */ 11200 if (!adapter) 11201 return; 11202 11203 netdev = adapter->netdev; 11204 ixgbe_dbg_adapter_exit(adapter); 11205 11206 set_bit(__IXGBE_REMOVING, &adapter->state); 11207 cancel_work_sync(&adapter->service_task); 11208 11209 if (adapter->mii_bus) 11210 mdiobus_unregister(adapter->mii_bus); 11211 11212 #ifdef CONFIG_IXGBE_DCA 11213 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11214 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11215 dca_remove_requester(&pdev->dev); 11216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11217 IXGBE_DCA_CTRL_DCA_DISABLE); 11218 } 11219 11220 #endif 11221 #ifdef CONFIG_IXGBE_HWMON 11222 ixgbe_sysfs_exit(adapter); 11223 #endif /* CONFIG_IXGBE_HWMON */ 11224 11225 /* remove the added san mac */ 11226 ixgbe_del_sanmac_netdev(netdev); 11227 11228 #ifdef CONFIG_PCI_IOV 11229 ixgbe_disable_sriov(adapter); 11230 #endif 11231 if (netdev->reg_state == NETREG_REGISTERED) 11232 unregister_netdev(netdev); 11233 11234 ixgbe_stop_ipsec_offload(adapter); 11235 ixgbe_clear_interrupt_scheme(adapter); 11236 11237 ixgbe_release_hw_control(adapter); 11238 11239 #ifdef CONFIG_DCB 11240 kfree(adapter->ixgbe_ieee_pfc); 11241 kfree(adapter->ixgbe_ieee_ets); 11242 11243 #endif 11244 iounmap(adapter->io_addr); 11245 pci_release_mem_regions(pdev); 11246 11247 e_dev_info("complete\n"); 11248 11249 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11250 if (adapter->jump_tables[i]) { 11251 kfree(adapter->jump_tables[i]->input); 11252 kfree(adapter->jump_tables[i]->mask); 11253 } 11254 kfree(adapter->jump_tables[i]); 11255 } 11256 11257 kfree(adapter->mac_table); 11258 kfree(adapter->rss_key); 11259 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11260 free_netdev(netdev); 11261 11262 pci_disable_pcie_error_reporting(pdev); 11263 11264 if (disable_dev) 11265 pci_disable_device(pdev); 11266 } 11267 11268 /** 11269 * ixgbe_io_error_detected - called when PCI error is detected 11270 * @pdev: Pointer to PCI device 11271 * @state: The current pci connection state 11272 * 11273 * This function is called after a PCI bus error affecting 11274 * this device has been detected. 11275 */ 11276 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11277 pci_channel_state_t state) 11278 { 11279 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11280 struct net_device *netdev = adapter->netdev; 11281 11282 #ifdef CONFIG_PCI_IOV 11283 struct ixgbe_hw *hw = &adapter->hw; 11284 struct pci_dev *bdev, *vfdev; 11285 u32 dw0, dw1, dw2, dw3; 11286 int vf, pos; 11287 u16 req_id, pf_func; 11288 11289 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11290 adapter->num_vfs == 0) 11291 goto skip_bad_vf_detection; 11292 11293 bdev = pdev->bus->self; 11294 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11295 bdev = bdev->bus->self; 11296 11297 if (!bdev) 11298 goto skip_bad_vf_detection; 11299 11300 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11301 if (!pos) 11302 goto skip_bad_vf_detection; 11303 11304 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11305 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11306 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11307 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11308 if (ixgbe_removed(hw->hw_addr)) 11309 goto skip_bad_vf_detection; 11310 11311 req_id = dw1 >> 16; 11312 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11313 if (!(req_id & 0x0080)) 11314 goto skip_bad_vf_detection; 11315 11316 pf_func = req_id & 0x01; 11317 if ((pf_func & 1) == (pdev->devfn & 1)) { 11318 unsigned int device_id; 11319 11320 vf = (req_id & 0x7F) >> 1; 11321 e_dev_err("VF %d has caused a PCIe error\n", vf); 11322 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11323 "%8.8x\tdw3: %8.8x\n", 11324 dw0, dw1, dw2, dw3); 11325 switch (adapter->hw.mac.type) { 11326 case ixgbe_mac_82599EB: 11327 device_id = IXGBE_82599_VF_DEVICE_ID; 11328 break; 11329 case ixgbe_mac_X540: 11330 device_id = IXGBE_X540_VF_DEVICE_ID; 11331 break; 11332 case ixgbe_mac_X550: 11333 device_id = IXGBE_DEV_ID_X550_VF; 11334 break; 11335 case ixgbe_mac_X550EM_x: 11336 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11337 break; 11338 case ixgbe_mac_x550em_a: 11339 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11340 break; 11341 default: 11342 device_id = 0; 11343 break; 11344 } 11345 11346 /* Find the pci device of the offending VF */ 11347 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11348 while (vfdev) { 11349 if (vfdev->devfn == (req_id & 0xFF)) 11350 break; 11351 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11352 device_id, vfdev); 11353 } 11354 /* 11355 * There's a slim chance the VF could have been hot plugged, 11356 * so if it is no longer present we don't need to issue the 11357 * VFLR. Just clean up the AER in that case. 11358 */ 11359 if (vfdev) { 11360 pcie_flr(vfdev); 11361 /* Free device reference count */ 11362 pci_dev_put(vfdev); 11363 } 11364 } 11365 11366 /* 11367 * Even though the error may have occurred on the other port 11368 * we still need to increment the vf error reference count for 11369 * both ports because the I/O resume function will be called 11370 * for both of them. 11371 */ 11372 adapter->vferr_refcount++; 11373 11374 return PCI_ERS_RESULT_RECOVERED; 11375 11376 skip_bad_vf_detection: 11377 #endif /* CONFIG_PCI_IOV */ 11378 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11379 return PCI_ERS_RESULT_DISCONNECT; 11380 11381 if (!netif_device_present(netdev)) 11382 return PCI_ERS_RESULT_DISCONNECT; 11383 11384 rtnl_lock(); 11385 netif_device_detach(netdev); 11386 11387 if (netif_running(netdev)) 11388 ixgbe_close_suspend(adapter); 11389 11390 if (state == pci_channel_io_perm_failure) { 11391 rtnl_unlock(); 11392 return PCI_ERS_RESULT_DISCONNECT; 11393 } 11394 11395 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11396 pci_disable_device(pdev); 11397 rtnl_unlock(); 11398 11399 /* Request a slot reset. */ 11400 return PCI_ERS_RESULT_NEED_RESET; 11401 } 11402 11403 /** 11404 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11405 * @pdev: Pointer to PCI device 11406 * 11407 * Restart the card from scratch, as if from a cold-boot. 11408 */ 11409 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11410 { 11411 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11412 pci_ers_result_t result; 11413 11414 if (pci_enable_device_mem(pdev)) { 11415 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11416 result = PCI_ERS_RESULT_DISCONNECT; 11417 } else { 11418 smp_mb__before_atomic(); 11419 clear_bit(__IXGBE_DISABLED, &adapter->state); 11420 adapter->hw.hw_addr = adapter->io_addr; 11421 pci_set_master(pdev); 11422 pci_restore_state(pdev); 11423 pci_save_state(pdev); 11424 11425 pci_wake_from_d3(pdev, false); 11426 11427 ixgbe_reset(adapter); 11428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11429 result = PCI_ERS_RESULT_RECOVERED; 11430 } 11431 11432 return result; 11433 } 11434 11435 /** 11436 * ixgbe_io_resume - called when traffic can start flowing again. 11437 * @pdev: Pointer to PCI device 11438 * 11439 * This callback is called when the error recovery driver tells us that 11440 * its OK to resume normal operation. 11441 */ 11442 static void ixgbe_io_resume(struct pci_dev *pdev) 11443 { 11444 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11445 struct net_device *netdev = adapter->netdev; 11446 11447 #ifdef CONFIG_PCI_IOV 11448 if (adapter->vferr_refcount) { 11449 e_info(drv, "Resuming after VF err\n"); 11450 adapter->vferr_refcount--; 11451 return; 11452 } 11453 11454 #endif 11455 rtnl_lock(); 11456 if (netif_running(netdev)) 11457 ixgbe_open(netdev); 11458 11459 netif_device_attach(netdev); 11460 rtnl_unlock(); 11461 } 11462 11463 static const struct pci_error_handlers ixgbe_err_handler = { 11464 .error_detected = ixgbe_io_error_detected, 11465 .slot_reset = ixgbe_io_slot_reset, 11466 .resume = ixgbe_io_resume, 11467 }; 11468 11469 static struct pci_driver ixgbe_driver = { 11470 .name = ixgbe_driver_name, 11471 .id_table = ixgbe_pci_tbl, 11472 .probe = ixgbe_probe, 11473 .remove = ixgbe_remove, 11474 #ifdef CONFIG_PM 11475 .suspend = ixgbe_suspend, 11476 .resume = ixgbe_resume, 11477 #endif 11478 .shutdown = ixgbe_shutdown, 11479 .sriov_configure = ixgbe_pci_sriov_configure, 11480 .err_handler = &ixgbe_err_handler 11481 }; 11482 11483 /** 11484 * ixgbe_init_module - Driver Registration Routine 11485 * 11486 * ixgbe_init_module is the first routine called when the driver is 11487 * loaded. All it does is register with the PCI subsystem. 11488 **/ 11489 static int __init ixgbe_init_module(void) 11490 { 11491 int ret; 11492 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11493 pr_info("%s\n", ixgbe_copyright); 11494 11495 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11496 if (!ixgbe_wq) { 11497 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11498 return -ENOMEM; 11499 } 11500 11501 ixgbe_dbg_init(); 11502 11503 ret = pci_register_driver(&ixgbe_driver); 11504 if (ret) { 11505 destroy_workqueue(ixgbe_wq); 11506 ixgbe_dbg_exit(); 11507 return ret; 11508 } 11509 11510 #ifdef CONFIG_IXGBE_DCA 11511 dca_register_notify(&dca_notifier); 11512 #endif 11513 11514 return 0; 11515 } 11516 11517 module_init(ixgbe_init_module); 11518 11519 /** 11520 * ixgbe_exit_module - Driver Exit Cleanup Routine 11521 * 11522 * ixgbe_exit_module is called just before the driver is removed 11523 * from memory. 11524 **/ 11525 static void __exit ixgbe_exit_module(void) 11526 { 11527 #ifdef CONFIG_IXGBE_DCA 11528 dca_unregister_notify(&dca_notifier); 11529 #endif 11530 pci_unregister_driver(&ixgbe_driver); 11531 11532 ixgbe_dbg_exit(); 11533 if (ixgbe_wq) { 11534 destroy_workqueue(ixgbe_wq); 11535 ixgbe_wq = NULL; 11536 } 11537 } 11538 11539 #ifdef CONFIG_IXGBE_DCA 11540 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11541 void *p) 11542 { 11543 int ret_val; 11544 11545 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11546 __ixgbe_notify_dca); 11547 11548 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11549 } 11550 11551 #endif /* CONFIG_IXGBE_DCA */ 11552 11553 module_exit(ixgbe_exit_module); 11554 11555 /* ixgbe_main.c */ 11556