1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <scsi/fc/fc_fcoe.h> 31 #include <net/udp_tunnel.h> 32 #include <net/pkt_cls.h> 33 #include <net/tc_act/tc_gact.h> 34 #include <net/tc_act/tc_mirred.h> 35 #include <net/vxlan.h> 36 #include <net/mpls.h> 37 38 #include "ixgbe.h" 39 #include "ixgbe_common.h" 40 #include "ixgbe_dcb_82599.h" 41 #include "ixgbe_sriov.h" 42 #include "ixgbe_model.h" 43 44 char ixgbe_driver_name[] = "ixgbe"; 45 static const char ixgbe_driver_string[] = 46 "Intel(R) 10 Gigabit PCI Express Network Driver"; 47 #ifdef IXGBE_FCOE 48 char ixgbe_default_device_descr[] = 49 "Intel(R) 10 Gigabit Network Connection"; 50 #else 51 static char ixgbe_default_device_descr[] = 52 "Intel(R) 10 Gigabit Network Connection"; 53 #endif 54 #define DRV_VERSION "5.1.0-k" 55 const char ixgbe_driver_version[] = DRV_VERSION; 56 static const char ixgbe_copyright[] = 57 "Copyright (c) 1999-2016 Intel Corporation."; 58 59 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 60 61 static const struct ixgbe_info *ixgbe_info_tbl[] = { 62 [board_82598] = &ixgbe_82598_info, 63 [board_82599] = &ixgbe_82599_info, 64 [board_X540] = &ixgbe_X540_info, 65 [board_X550] = &ixgbe_X550_info, 66 [board_X550EM_x] = &ixgbe_X550EM_x_info, 67 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 68 [board_x550em_a] = &ixgbe_x550em_a_info, 69 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 70 }; 71 72 /* ixgbe_pci_tbl - PCI Device ID Table 73 * 74 * Wildcard entries (PCI_ANY_ID) should come last 75 * Last entry must be all 0s 76 * 77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 78 * Class, Class Mask, private data (not used) } 79 */ 80 static const struct pci_device_id ixgbe_pci_tbl[] = { 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 128 /* required last entry */ 129 {0, } 130 }; 131 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 132 133 #ifdef CONFIG_IXGBE_DCA 134 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 135 void *p); 136 static struct notifier_block dca_notifier = { 137 .notifier_call = ixgbe_notify_dca, 138 .next = NULL, 139 .priority = 0 140 }; 141 #endif 142 143 #ifdef CONFIG_PCI_IOV 144 static unsigned int max_vfs; 145 module_param(max_vfs, uint, 0); 146 MODULE_PARM_DESC(max_vfs, 147 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 148 #endif /* CONFIG_PCI_IOV */ 149 150 static unsigned int allow_unsupported_sfp; 151 module_param(allow_unsupported_sfp, uint, 0); 152 MODULE_PARM_DESC(allow_unsupported_sfp, 153 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 154 155 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 156 static int debug = -1; 157 module_param(debug, int, 0); 158 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 159 160 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 161 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 162 MODULE_LICENSE("GPL"); 163 MODULE_VERSION(DRV_VERSION); 164 165 static struct workqueue_struct *ixgbe_wq; 166 167 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 168 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 169 170 static const struct net_device_ops ixgbe_netdev_ops; 171 172 static bool netif_is_ixgbe(struct net_device *dev) 173 { 174 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 175 } 176 177 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 178 u32 reg, u16 *value) 179 { 180 struct pci_dev *parent_dev; 181 struct pci_bus *parent_bus; 182 183 parent_bus = adapter->pdev->bus->parent; 184 if (!parent_bus) 185 return -1; 186 187 parent_dev = parent_bus->self; 188 if (!parent_dev) 189 return -1; 190 191 if (!pci_is_pcie(parent_dev)) 192 return -1; 193 194 pcie_capability_read_word(parent_dev, reg, value); 195 if (*value == IXGBE_FAILED_READ_CFG_WORD && 196 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 197 return -1; 198 return 0; 199 } 200 201 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 202 { 203 struct ixgbe_hw *hw = &adapter->hw; 204 u16 link_status = 0; 205 int err; 206 207 hw->bus.type = ixgbe_bus_type_pci_express; 208 209 /* Get the negotiated link width and speed from PCI config space of the 210 * parent, as this device is behind a switch 211 */ 212 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 213 214 /* assume caller will handle error case */ 215 if (err) 216 return err; 217 218 hw->bus.width = ixgbe_convert_bus_width(link_status); 219 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 220 221 return 0; 222 } 223 224 /** 225 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 226 * @hw: hw specific details 227 * 228 * This function is used by probe to determine whether a device's PCI-Express 229 * bandwidth details should be gathered from the parent bus instead of from the 230 * device. Used to ensure that various locations all have the correct device ID 231 * checks. 232 */ 233 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 234 { 235 switch (hw->device_id) { 236 case IXGBE_DEV_ID_82599_SFP_SF_QP: 237 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 238 return true; 239 default: 240 return false; 241 } 242 } 243 244 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 245 int expected_gts) 246 { 247 struct ixgbe_hw *hw = &adapter->hw; 248 int max_gts = 0; 249 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 250 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 251 struct pci_dev *pdev; 252 253 /* Some devices are not connected over PCIe and thus do not negotiate 254 * speed. These devices do not have valid bus info, and thus any report 255 * we generate may not be correct. 256 */ 257 if (hw->bus.type == ixgbe_bus_type_internal) 258 return; 259 260 /* determine whether to use the parent device */ 261 if (ixgbe_pcie_from_parent(&adapter->hw)) 262 pdev = adapter->pdev->bus->parent->self; 263 else 264 pdev = adapter->pdev; 265 266 if (pcie_get_minimum_link(pdev, &speed, &width) || 267 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 268 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 269 return; 270 } 271 272 switch (speed) { 273 case PCIE_SPEED_2_5GT: 274 /* 8b/10b encoding reduces max throughput by 20% */ 275 max_gts = 2 * width; 276 break; 277 case PCIE_SPEED_5_0GT: 278 /* 8b/10b encoding reduces max throughput by 20% */ 279 max_gts = 4 * width; 280 break; 281 case PCIE_SPEED_8_0GT: 282 /* 128b/130b encoding reduces throughput by less than 2% */ 283 max_gts = 8 * width; 284 break; 285 default: 286 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 287 return; 288 } 289 290 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 291 max_gts); 292 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 293 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 294 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 295 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 296 "Unknown"), 297 width, 298 (speed == PCIE_SPEED_2_5GT ? "20%" : 299 speed == PCIE_SPEED_5_0GT ? "20%" : 300 speed == PCIE_SPEED_8_0GT ? "<2%" : 301 "Unknown")); 302 303 if (max_gts < expected_gts) { 304 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 305 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 306 expected_gts); 307 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 308 } 309 } 310 311 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 312 { 313 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 314 !test_bit(__IXGBE_REMOVING, &adapter->state) && 315 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 316 queue_work(ixgbe_wq, &adapter->service_task); 317 } 318 319 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 320 { 321 struct ixgbe_adapter *adapter = hw->back; 322 323 if (!hw->hw_addr) 324 return; 325 hw->hw_addr = NULL; 326 e_dev_err("Adapter removed\n"); 327 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 328 ixgbe_service_event_schedule(adapter); 329 } 330 331 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 332 { 333 u8 __iomem *reg_addr; 334 u32 value; 335 int i; 336 337 reg_addr = READ_ONCE(hw->hw_addr); 338 if (ixgbe_removed(reg_addr)) 339 return IXGBE_FAILED_READ_REG; 340 341 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 342 * so perform several status register reads to determine if the adapter 343 * has been removed. 344 */ 345 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 346 value = readl(reg_addr + IXGBE_STATUS); 347 if (value != IXGBE_FAILED_READ_REG) 348 break; 349 mdelay(3); 350 } 351 352 if (value == IXGBE_FAILED_READ_REG) 353 ixgbe_remove_adapter(hw); 354 else 355 value = readl(reg_addr + reg); 356 return value; 357 } 358 359 /** 360 * ixgbe_read_reg - Read from device register 361 * @hw: hw specific details 362 * @reg: offset of register to read 363 * 364 * Returns : value read or IXGBE_FAILED_READ_REG if removed 365 * 366 * This function is used to read device registers. It checks for device 367 * removal by confirming any read that returns all ones by checking the 368 * status register value for all ones. This function avoids reading from 369 * the hardware if a removal was previously detected in which case it 370 * returns IXGBE_FAILED_READ_REG (all ones). 371 */ 372 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 373 { 374 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 375 u32 value; 376 377 if (ixgbe_removed(reg_addr)) 378 return IXGBE_FAILED_READ_REG; 379 if (unlikely(hw->phy.nw_mng_if_sel & 380 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 381 struct ixgbe_adapter *adapter; 382 int i; 383 384 for (i = 0; i < 200; ++i) { 385 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 386 if (likely(!value)) 387 goto writes_completed; 388 if (value == IXGBE_FAILED_READ_REG) { 389 ixgbe_remove_adapter(hw); 390 return IXGBE_FAILED_READ_REG; 391 } 392 udelay(5); 393 } 394 395 adapter = hw->back; 396 e_warn(hw, "register writes incomplete %08x\n", value); 397 } 398 399 writes_completed: 400 value = readl(reg_addr + reg); 401 if (unlikely(value == IXGBE_FAILED_READ_REG)) 402 value = ixgbe_check_remove(hw, reg); 403 return value; 404 } 405 406 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 407 { 408 u16 value; 409 410 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 411 if (value == IXGBE_FAILED_READ_CFG_WORD) { 412 ixgbe_remove_adapter(hw); 413 return true; 414 } 415 return false; 416 } 417 418 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 419 { 420 struct ixgbe_adapter *adapter = hw->back; 421 u16 value; 422 423 if (ixgbe_removed(hw->hw_addr)) 424 return IXGBE_FAILED_READ_CFG_WORD; 425 pci_read_config_word(adapter->pdev, reg, &value); 426 if (value == IXGBE_FAILED_READ_CFG_WORD && 427 ixgbe_check_cfg_remove(hw, adapter->pdev)) 428 return IXGBE_FAILED_READ_CFG_WORD; 429 return value; 430 } 431 432 #ifdef CONFIG_PCI_IOV 433 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 434 { 435 struct ixgbe_adapter *adapter = hw->back; 436 u32 value; 437 438 if (ixgbe_removed(hw->hw_addr)) 439 return IXGBE_FAILED_READ_CFG_DWORD; 440 pci_read_config_dword(adapter->pdev, reg, &value); 441 if (value == IXGBE_FAILED_READ_CFG_DWORD && 442 ixgbe_check_cfg_remove(hw, adapter->pdev)) 443 return IXGBE_FAILED_READ_CFG_DWORD; 444 return value; 445 } 446 #endif /* CONFIG_PCI_IOV */ 447 448 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 449 { 450 struct ixgbe_adapter *adapter = hw->back; 451 452 if (ixgbe_removed(hw->hw_addr)) 453 return; 454 pci_write_config_word(adapter->pdev, reg, value); 455 } 456 457 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 458 { 459 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 460 461 /* flush memory to make sure state is correct before next watchdog */ 462 smp_mb__before_atomic(); 463 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 464 } 465 466 struct ixgbe_reg_info { 467 u32 ofs; 468 char *name; 469 }; 470 471 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 472 473 /* General Registers */ 474 {IXGBE_CTRL, "CTRL"}, 475 {IXGBE_STATUS, "STATUS"}, 476 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 477 478 /* Interrupt Registers */ 479 {IXGBE_EICR, "EICR"}, 480 481 /* RX Registers */ 482 {IXGBE_SRRCTL(0), "SRRCTL"}, 483 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 484 {IXGBE_RDLEN(0), "RDLEN"}, 485 {IXGBE_RDH(0), "RDH"}, 486 {IXGBE_RDT(0), "RDT"}, 487 {IXGBE_RXDCTL(0), "RXDCTL"}, 488 {IXGBE_RDBAL(0), "RDBAL"}, 489 {IXGBE_RDBAH(0), "RDBAH"}, 490 491 /* TX Registers */ 492 {IXGBE_TDBAL(0), "TDBAL"}, 493 {IXGBE_TDBAH(0), "TDBAH"}, 494 {IXGBE_TDLEN(0), "TDLEN"}, 495 {IXGBE_TDH(0), "TDH"}, 496 {IXGBE_TDT(0), "TDT"}, 497 {IXGBE_TXDCTL(0), "TXDCTL"}, 498 499 /* List Terminator */ 500 { .name = NULL } 501 }; 502 503 504 /* 505 * ixgbe_regdump - register printout routine 506 */ 507 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 508 { 509 int i; 510 char rname[16]; 511 u32 regs[64]; 512 513 switch (reginfo->ofs) { 514 case IXGBE_SRRCTL(0): 515 for (i = 0; i < 64; i++) 516 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 517 break; 518 case IXGBE_DCA_RXCTRL(0): 519 for (i = 0; i < 64; i++) 520 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 521 break; 522 case IXGBE_RDLEN(0): 523 for (i = 0; i < 64; i++) 524 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 525 break; 526 case IXGBE_RDH(0): 527 for (i = 0; i < 64; i++) 528 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 529 break; 530 case IXGBE_RDT(0): 531 for (i = 0; i < 64; i++) 532 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 533 break; 534 case IXGBE_RXDCTL(0): 535 for (i = 0; i < 64; i++) 536 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 537 break; 538 case IXGBE_RDBAL(0): 539 for (i = 0; i < 64; i++) 540 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 541 break; 542 case IXGBE_RDBAH(0): 543 for (i = 0; i < 64; i++) 544 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 545 break; 546 case IXGBE_TDBAL(0): 547 for (i = 0; i < 64; i++) 548 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 549 break; 550 case IXGBE_TDBAH(0): 551 for (i = 0; i < 64; i++) 552 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 553 break; 554 case IXGBE_TDLEN(0): 555 for (i = 0; i < 64; i++) 556 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 557 break; 558 case IXGBE_TDH(0): 559 for (i = 0; i < 64; i++) 560 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 561 break; 562 case IXGBE_TDT(0): 563 for (i = 0; i < 64; i++) 564 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 565 break; 566 case IXGBE_TXDCTL(0): 567 for (i = 0; i < 64; i++) 568 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 569 break; 570 default: 571 pr_info("%-15s %08x\n", 572 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 573 return; 574 } 575 576 i = 0; 577 while (i < 64) { 578 int j; 579 char buf[9 * 8 + 1]; 580 char *p = buf; 581 582 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 583 for (j = 0; j < 8; j++) 584 p += sprintf(p, " %08x", regs[i++]); 585 pr_err("%-15s%s\n", rname, buf); 586 } 587 588 } 589 590 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 591 { 592 struct ixgbe_tx_buffer *tx_buffer; 593 594 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 595 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 596 n, ring->next_to_use, ring->next_to_clean, 597 (u64)dma_unmap_addr(tx_buffer, dma), 598 dma_unmap_len(tx_buffer, len), 599 tx_buffer->next_to_watch, 600 (u64)tx_buffer->time_stamp); 601 } 602 603 /* 604 * ixgbe_dump - Print registers, tx-rings and rx-rings 605 */ 606 static void ixgbe_dump(struct ixgbe_adapter *adapter) 607 { 608 struct net_device *netdev = adapter->netdev; 609 struct ixgbe_hw *hw = &adapter->hw; 610 struct ixgbe_reg_info *reginfo; 611 int n = 0; 612 struct ixgbe_ring *ring; 613 struct ixgbe_tx_buffer *tx_buffer; 614 union ixgbe_adv_tx_desc *tx_desc; 615 struct my_u0 { u64 a; u64 b; } *u0; 616 struct ixgbe_ring *rx_ring; 617 union ixgbe_adv_rx_desc *rx_desc; 618 struct ixgbe_rx_buffer *rx_buffer_info; 619 int i = 0; 620 621 if (!netif_msg_hw(adapter)) 622 return; 623 624 /* Print netdevice Info */ 625 if (netdev) { 626 dev_info(&adapter->pdev->dev, "Net device Info\n"); 627 pr_info("Device Name state " 628 "trans_start\n"); 629 pr_info("%-15s %016lX %016lX\n", 630 netdev->name, 631 netdev->state, 632 dev_trans_start(netdev)); 633 } 634 635 /* Print Registers */ 636 dev_info(&adapter->pdev->dev, "Register Dump\n"); 637 pr_info(" Register Name Value\n"); 638 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 639 reginfo->name; reginfo++) { 640 ixgbe_regdump(hw, reginfo); 641 } 642 643 /* Print TX Ring Summary */ 644 if (!netdev || !netif_running(netdev)) 645 return; 646 647 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 648 pr_info(" %s %s %s %s\n", 649 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 650 "leng", "ntw", "timestamp"); 651 for (n = 0; n < adapter->num_tx_queues; n++) { 652 ring = adapter->tx_ring[n]; 653 ixgbe_print_buffer(ring, n); 654 } 655 656 for (n = 0; n < adapter->num_xdp_queues; n++) { 657 ring = adapter->xdp_ring[n]; 658 ixgbe_print_buffer(ring, n); 659 } 660 661 /* Print TX Rings */ 662 if (!netif_msg_tx_done(adapter)) 663 goto rx_ring_summary; 664 665 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 666 667 /* Transmit Descriptor Formats 668 * 669 * 82598 Advanced Transmit Descriptor 670 * +--------------------------------------------------------------+ 671 * 0 | Buffer Address [63:0] | 672 * +--------------------------------------------------------------+ 673 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 674 * +--------------------------------------------------------------+ 675 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 676 * 677 * 82598 Advanced Transmit Descriptor (Write-Back Format) 678 * +--------------------------------------------------------------+ 679 * 0 | RSV [63:0] | 680 * +--------------------------------------------------------------+ 681 * 8 | RSV | STA | NXTSEQ | 682 * +--------------------------------------------------------------+ 683 * 63 36 35 32 31 0 684 * 685 * 82599+ Advanced Transmit Descriptor 686 * +--------------------------------------------------------------+ 687 * 0 | Buffer Address [63:0] | 688 * +--------------------------------------------------------------+ 689 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 690 * +--------------------------------------------------------------+ 691 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 692 * 693 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 694 * +--------------------------------------------------------------+ 695 * 0 | RSV [63:0] | 696 * +--------------------------------------------------------------+ 697 * 8 | RSV | STA | RSV | 698 * +--------------------------------------------------------------+ 699 * 63 36 35 32 31 0 700 */ 701 702 for (n = 0; n < adapter->num_tx_queues; n++) { 703 ring = adapter->tx_ring[n]; 704 pr_info("------------------------------------\n"); 705 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 706 pr_info("------------------------------------\n"); 707 pr_info("%s%s %s %s %s %s\n", 708 "T [desc] [address 63:0 ] ", 709 "[PlPOIdStDDt Ln] [bi->dma ] ", 710 "leng", "ntw", "timestamp", "bi->skb"); 711 712 for (i = 0; ring->desc && (i < ring->count); i++) { 713 tx_desc = IXGBE_TX_DESC(ring, i); 714 tx_buffer = &ring->tx_buffer_info[i]; 715 u0 = (struct my_u0 *)tx_desc; 716 if (dma_unmap_len(tx_buffer, len) > 0) { 717 const char *ring_desc; 718 719 if (i == ring->next_to_use && 720 i == ring->next_to_clean) 721 ring_desc = " NTC/U"; 722 else if (i == ring->next_to_use) 723 ring_desc = " NTU"; 724 else if (i == ring->next_to_clean) 725 ring_desc = " NTC"; 726 else 727 ring_desc = ""; 728 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 729 i, 730 le64_to_cpu((__force __le64)u0->a), 731 le64_to_cpu((__force __le64)u0->b), 732 (u64)dma_unmap_addr(tx_buffer, dma), 733 dma_unmap_len(tx_buffer, len), 734 tx_buffer->next_to_watch, 735 (u64)tx_buffer->time_stamp, 736 tx_buffer->skb, 737 ring_desc); 738 739 if (netif_msg_pktdata(adapter) && 740 tx_buffer->skb) 741 print_hex_dump(KERN_INFO, "", 742 DUMP_PREFIX_ADDRESS, 16, 1, 743 tx_buffer->skb->data, 744 dma_unmap_len(tx_buffer, len), 745 true); 746 } 747 } 748 } 749 750 /* Print RX Rings Summary */ 751 rx_ring_summary: 752 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 753 pr_info("Queue [NTU] [NTC]\n"); 754 for (n = 0; n < adapter->num_rx_queues; n++) { 755 rx_ring = adapter->rx_ring[n]; 756 pr_info("%5d %5X %5X\n", 757 n, rx_ring->next_to_use, rx_ring->next_to_clean); 758 } 759 760 /* Print RX Rings */ 761 if (!netif_msg_rx_status(adapter)) 762 return; 763 764 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 765 766 /* Receive Descriptor Formats 767 * 768 * 82598 Advanced Receive Descriptor (Read) Format 769 * 63 1 0 770 * +-----------------------------------------------------+ 771 * 0 | Packet Buffer Address [63:1] |A0/NSE| 772 * +----------------------------------------------+------+ 773 * 8 | Header Buffer Address [63:1] | DD | 774 * +-----------------------------------------------------+ 775 * 776 * 777 * 82598 Advanced Receive Descriptor (Write-Back) Format 778 * 779 * 63 48 47 32 31 30 21 20 16 15 4 3 0 780 * +------------------------------------------------------+ 781 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 782 * | Packet | IP | | | | Type | Type | 783 * | Checksum | Ident | | | | | | 784 * +------------------------------------------------------+ 785 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 786 * +------------------------------------------------------+ 787 * 63 48 47 32 31 20 19 0 788 * 789 * 82599+ Advanced Receive Descriptor (Read) Format 790 * 63 1 0 791 * +-----------------------------------------------------+ 792 * 0 | Packet Buffer Address [63:1] |A0/NSE| 793 * +----------------------------------------------+------+ 794 * 8 | Header Buffer Address [63:1] | DD | 795 * +-----------------------------------------------------+ 796 * 797 * 798 * 82599+ Advanced Receive Descriptor (Write-Back) Format 799 * 800 * 63 48 47 32 31 30 21 20 17 16 4 3 0 801 * +------------------------------------------------------+ 802 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 803 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 804 * |/ Flow Dir Flt ID | | | | | | 805 * +------------------------------------------------------+ 806 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 807 * +------------------------------------------------------+ 808 * 63 48 47 32 31 20 19 0 809 */ 810 811 for (n = 0; n < adapter->num_rx_queues; n++) { 812 rx_ring = adapter->rx_ring[n]; 813 pr_info("------------------------------------\n"); 814 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 815 pr_info("------------------------------------\n"); 816 pr_info("%s%s%s\n", 817 "R [desc] [ PktBuf A0] ", 818 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 819 "<-- Adv Rx Read format"); 820 pr_info("%s%s%s\n", 821 "RWB[desc] [PcsmIpSHl PtRs] ", 822 "[vl er S cks ln] ---------------- [bi->skb ] ", 823 "<-- Adv Rx Write-Back format"); 824 825 for (i = 0; i < rx_ring->count; i++) { 826 const char *ring_desc; 827 828 if (i == rx_ring->next_to_use) 829 ring_desc = " NTU"; 830 else if (i == rx_ring->next_to_clean) 831 ring_desc = " NTC"; 832 else 833 ring_desc = ""; 834 835 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 836 rx_desc = IXGBE_RX_DESC(rx_ring, i); 837 u0 = (struct my_u0 *)rx_desc; 838 if (rx_desc->wb.upper.length) { 839 /* Descriptor Done */ 840 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 841 i, 842 le64_to_cpu((__force __le64)u0->a), 843 le64_to_cpu((__force __le64)u0->b), 844 rx_buffer_info->skb, 845 ring_desc); 846 } else { 847 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 848 i, 849 le64_to_cpu((__force __le64)u0->a), 850 le64_to_cpu((__force __le64)u0->b), 851 (u64)rx_buffer_info->dma, 852 rx_buffer_info->skb, 853 ring_desc); 854 855 if (netif_msg_pktdata(adapter) && 856 rx_buffer_info->dma) { 857 print_hex_dump(KERN_INFO, "", 858 DUMP_PREFIX_ADDRESS, 16, 1, 859 page_address(rx_buffer_info->page) + 860 rx_buffer_info->page_offset, 861 ixgbe_rx_bufsz(rx_ring), true); 862 } 863 } 864 } 865 } 866 } 867 868 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 869 { 870 u32 ctrl_ext; 871 872 /* Let firmware take over control of h/w */ 873 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 874 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 875 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 876 } 877 878 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 879 { 880 u32 ctrl_ext; 881 882 /* Let firmware know the driver has taken over */ 883 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 884 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 885 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 886 } 887 888 /** 889 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 890 * @adapter: pointer to adapter struct 891 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 892 * @queue: queue to map the corresponding interrupt to 893 * @msix_vector: the vector to map to the corresponding queue 894 * 895 */ 896 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 897 u8 queue, u8 msix_vector) 898 { 899 u32 ivar, index; 900 struct ixgbe_hw *hw = &adapter->hw; 901 switch (hw->mac.type) { 902 case ixgbe_mac_82598EB: 903 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 904 if (direction == -1) 905 direction = 0; 906 index = (((direction * 64) + queue) >> 2) & 0x1F; 907 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 908 ivar &= ~(0xFF << (8 * (queue & 0x3))); 909 ivar |= (msix_vector << (8 * (queue & 0x3))); 910 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 911 break; 912 case ixgbe_mac_82599EB: 913 case ixgbe_mac_X540: 914 case ixgbe_mac_X550: 915 case ixgbe_mac_X550EM_x: 916 case ixgbe_mac_x550em_a: 917 if (direction == -1) { 918 /* other causes */ 919 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 920 index = ((queue & 1) * 8); 921 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 922 ivar &= ~(0xFF << index); 923 ivar |= (msix_vector << index); 924 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 925 break; 926 } else { 927 /* tx or rx causes */ 928 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 929 index = ((16 * (queue & 1)) + (8 * direction)); 930 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 931 ivar &= ~(0xFF << index); 932 ivar |= (msix_vector << index); 933 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 934 break; 935 } 936 default: 937 break; 938 } 939 } 940 941 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 942 u64 qmask) 943 { 944 u32 mask; 945 946 switch (adapter->hw.mac.type) { 947 case ixgbe_mac_82598EB: 948 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 950 break; 951 case ixgbe_mac_82599EB: 952 case ixgbe_mac_X540: 953 case ixgbe_mac_X550: 954 case ixgbe_mac_X550EM_x: 955 case ixgbe_mac_x550em_a: 956 mask = (qmask & 0xFFFFFFFF); 957 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 958 mask = (qmask >> 32); 959 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 960 break; 961 default: 962 break; 963 } 964 } 965 966 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 967 { 968 struct ixgbe_hw *hw = &adapter->hw; 969 struct ixgbe_hw_stats *hwstats = &adapter->stats; 970 int i; 971 u32 data; 972 973 if ((hw->fc.current_mode != ixgbe_fc_full) && 974 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 975 return; 976 977 switch (hw->mac.type) { 978 case ixgbe_mac_82598EB: 979 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 980 break; 981 default: 982 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 983 } 984 hwstats->lxoffrxc += data; 985 986 /* refill credits (no tx hang) if we received xoff */ 987 if (!data) 988 return; 989 990 for (i = 0; i < adapter->num_tx_queues; i++) 991 clear_bit(__IXGBE_HANG_CHECK_ARMED, 992 &adapter->tx_ring[i]->state); 993 994 for (i = 0; i < adapter->num_xdp_queues; i++) 995 clear_bit(__IXGBE_HANG_CHECK_ARMED, 996 &adapter->xdp_ring[i]->state); 997 } 998 999 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1000 { 1001 struct ixgbe_hw *hw = &adapter->hw; 1002 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1003 u32 xoff[8] = {0}; 1004 u8 tc; 1005 int i; 1006 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1007 1008 if (adapter->ixgbe_ieee_pfc) 1009 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1010 1011 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1012 ixgbe_update_xoff_rx_lfc(adapter); 1013 return; 1014 } 1015 1016 /* update stats for each tc, only valid with PFC enabled */ 1017 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1018 u32 pxoffrxc; 1019 1020 switch (hw->mac.type) { 1021 case ixgbe_mac_82598EB: 1022 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1023 break; 1024 default: 1025 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1026 } 1027 hwstats->pxoffrxc[i] += pxoffrxc; 1028 /* Get the TC for given UP */ 1029 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1030 xoff[tc] += pxoffrxc; 1031 } 1032 1033 /* disarm tx queues that have received xoff frames */ 1034 for (i = 0; i < adapter->num_tx_queues; i++) { 1035 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1036 1037 tc = tx_ring->dcb_tc; 1038 if (xoff[tc]) 1039 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1040 } 1041 1042 for (i = 0; i < adapter->num_xdp_queues; i++) { 1043 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1044 1045 tc = xdp_ring->dcb_tc; 1046 if (xoff[tc]) 1047 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1048 } 1049 } 1050 1051 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1052 { 1053 return ring->stats.packets; 1054 } 1055 1056 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1057 { 1058 unsigned int head, tail; 1059 1060 head = ring->next_to_clean; 1061 tail = ring->next_to_use; 1062 1063 return ((head <= tail) ? tail : tail + ring->count) - head; 1064 } 1065 1066 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1067 { 1068 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1069 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1070 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1071 1072 clear_check_for_tx_hang(tx_ring); 1073 1074 /* 1075 * Check for a hung queue, but be thorough. This verifies 1076 * that a transmit has been completed since the previous 1077 * check AND there is at least one packet pending. The 1078 * ARMED bit is set to indicate a potential hang. The 1079 * bit is cleared if a pause frame is received to remove 1080 * false hang detection due to PFC or 802.3x frames. By 1081 * requiring this to fail twice we avoid races with 1082 * pfc clearing the ARMED bit and conditions where we 1083 * run the check_tx_hang logic with a transmit completion 1084 * pending but without time to complete it yet. 1085 */ 1086 if (tx_done_old == tx_done && tx_pending) 1087 /* make sure it is true for two checks in a row */ 1088 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1089 &tx_ring->state); 1090 /* update completed stats and continue */ 1091 tx_ring->tx_stats.tx_done_old = tx_done; 1092 /* reset the countdown */ 1093 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1094 1095 return false; 1096 } 1097 1098 /** 1099 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1100 * @adapter: driver private struct 1101 **/ 1102 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1103 { 1104 1105 /* Do the reset outside of interrupt context */ 1106 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1107 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1108 e_warn(drv, "initiating reset due to tx timeout\n"); 1109 ixgbe_service_event_schedule(adapter); 1110 } 1111 } 1112 1113 /** 1114 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1115 * @netdev: network interface device structure 1116 * @queue_index: Tx queue to set 1117 * @maxrate: desired maximum transmit bitrate 1118 **/ 1119 static int ixgbe_tx_maxrate(struct net_device *netdev, 1120 int queue_index, u32 maxrate) 1121 { 1122 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1123 struct ixgbe_hw *hw = &adapter->hw; 1124 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1125 1126 if (!maxrate) 1127 return 0; 1128 1129 /* Calculate the rate factor values to set */ 1130 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1131 bcnrc_val /= maxrate; 1132 1133 /* clear everything but the rate factor */ 1134 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1135 IXGBE_RTTBCNRC_RF_DEC_MASK; 1136 1137 /* enable the rate scheduler */ 1138 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1139 1140 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1141 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1142 1143 return 0; 1144 } 1145 1146 /** 1147 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1148 * @q_vector: structure containing interrupt and ring information 1149 * @tx_ring: tx ring to clean 1150 * @napi_budget: Used to determine if we are in netpoll 1151 **/ 1152 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1153 struct ixgbe_ring *tx_ring, int napi_budget) 1154 { 1155 struct ixgbe_adapter *adapter = q_vector->adapter; 1156 struct ixgbe_tx_buffer *tx_buffer; 1157 union ixgbe_adv_tx_desc *tx_desc; 1158 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1159 unsigned int budget = q_vector->tx.work_limit; 1160 unsigned int i = tx_ring->next_to_clean; 1161 1162 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1163 return true; 1164 1165 tx_buffer = &tx_ring->tx_buffer_info[i]; 1166 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1167 i -= tx_ring->count; 1168 1169 do { 1170 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1171 1172 /* if next_to_watch is not set then there is no work pending */ 1173 if (!eop_desc) 1174 break; 1175 1176 /* prevent any other reads prior to eop_desc */ 1177 smp_rmb(); 1178 1179 /* if DD is not set pending work has not been completed */ 1180 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1181 break; 1182 1183 /* clear next_to_watch to prevent false hangs */ 1184 tx_buffer->next_to_watch = NULL; 1185 1186 /* update the statistics for this packet */ 1187 total_bytes += tx_buffer->bytecount; 1188 total_packets += tx_buffer->gso_segs; 1189 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1190 total_ipsec++; 1191 1192 /* free the skb */ 1193 if (ring_is_xdp(tx_ring)) 1194 xdp_return_frame(tx_buffer->xdpf); 1195 else 1196 napi_consume_skb(tx_buffer->skb, napi_budget); 1197 1198 /* unmap skb header data */ 1199 dma_unmap_single(tx_ring->dev, 1200 dma_unmap_addr(tx_buffer, dma), 1201 dma_unmap_len(tx_buffer, len), 1202 DMA_TO_DEVICE); 1203 1204 /* clear tx_buffer data */ 1205 dma_unmap_len_set(tx_buffer, len, 0); 1206 1207 /* unmap remaining buffers */ 1208 while (tx_desc != eop_desc) { 1209 tx_buffer++; 1210 tx_desc++; 1211 i++; 1212 if (unlikely(!i)) { 1213 i -= tx_ring->count; 1214 tx_buffer = tx_ring->tx_buffer_info; 1215 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1216 } 1217 1218 /* unmap any remaining paged data */ 1219 if (dma_unmap_len(tx_buffer, len)) { 1220 dma_unmap_page(tx_ring->dev, 1221 dma_unmap_addr(tx_buffer, dma), 1222 dma_unmap_len(tx_buffer, len), 1223 DMA_TO_DEVICE); 1224 dma_unmap_len_set(tx_buffer, len, 0); 1225 } 1226 } 1227 1228 /* move us one more past the eop_desc for start of next pkt */ 1229 tx_buffer++; 1230 tx_desc++; 1231 i++; 1232 if (unlikely(!i)) { 1233 i -= tx_ring->count; 1234 tx_buffer = tx_ring->tx_buffer_info; 1235 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1236 } 1237 1238 /* issue prefetch for next Tx descriptor */ 1239 prefetch(tx_desc); 1240 1241 /* update budget accounting */ 1242 budget--; 1243 } while (likely(budget)); 1244 1245 i += tx_ring->count; 1246 tx_ring->next_to_clean = i; 1247 u64_stats_update_begin(&tx_ring->syncp); 1248 tx_ring->stats.bytes += total_bytes; 1249 tx_ring->stats.packets += total_packets; 1250 u64_stats_update_end(&tx_ring->syncp); 1251 q_vector->tx.total_bytes += total_bytes; 1252 q_vector->tx.total_packets += total_packets; 1253 adapter->tx_ipsec += total_ipsec; 1254 1255 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1256 /* schedule immediate reset if we believe we hung */ 1257 struct ixgbe_hw *hw = &adapter->hw; 1258 e_err(drv, "Detected Tx Unit Hang %s\n" 1259 " Tx Queue <%d>\n" 1260 " TDH, TDT <%x>, <%x>\n" 1261 " next_to_use <%x>\n" 1262 " next_to_clean <%x>\n" 1263 "tx_buffer_info[next_to_clean]\n" 1264 " time_stamp <%lx>\n" 1265 " jiffies <%lx>\n", 1266 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1267 tx_ring->queue_index, 1268 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1269 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1270 tx_ring->next_to_use, i, 1271 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1272 1273 if (!ring_is_xdp(tx_ring)) 1274 netif_stop_subqueue(tx_ring->netdev, 1275 tx_ring->queue_index); 1276 1277 e_info(probe, 1278 "tx hang %d detected on queue %d, resetting adapter\n", 1279 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1280 1281 /* schedule immediate reset if we believe we hung */ 1282 ixgbe_tx_timeout_reset(adapter); 1283 1284 /* the adapter is about to reset, no point in enabling stuff */ 1285 return true; 1286 } 1287 1288 if (ring_is_xdp(tx_ring)) 1289 return !!budget; 1290 1291 netdev_tx_completed_queue(txring_txq(tx_ring), 1292 total_packets, total_bytes); 1293 1294 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1295 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1296 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1297 /* Make sure that anybody stopping the queue after this 1298 * sees the new next_to_clean. 1299 */ 1300 smp_mb(); 1301 if (__netif_subqueue_stopped(tx_ring->netdev, 1302 tx_ring->queue_index) 1303 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1304 netif_wake_subqueue(tx_ring->netdev, 1305 tx_ring->queue_index); 1306 ++tx_ring->tx_stats.restart_queue; 1307 } 1308 } 1309 1310 return !!budget; 1311 } 1312 1313 #ifdef CONFIG_IXGBE_DCA 1314 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1315 struct ixgbe_ring *tx_ring, 1316 int cpu) 1317 { 1318 struct ixgbe_hw *hw = &adapter->hw; 1319 u32 txctrl = 0; 1320 u16 reg_offset; 1321 1322 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1323 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1324 1325 switch (hw->mac.type) { 1326 case ixgbe_mac_82598EB: 1327 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1328 break; 1329 case ixgbe_mac_82599EB: 1330 case ixgbe_mac_X540: 1331 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1332 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1333 break; 1334 default: 1335 /* for unknown hardware do not write register */ 1336 return; 1337 } 1338 1339 /* 1340 * We can enable relaxed ordering for reads, but not writes when 1341 * DCA is enabled. This is due to a known issue in some chipsets 1342 * which will cause the DCA tag to be cleared. 1343 */ 1344 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1345 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1346 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1347 1348 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1349 } 1350 1351 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1352 struct ixgbe_ring *rx_ring, 1353 int cpu) 1354 { 1355 struct ixgbe_hw *hw = &adapter->hw; 1356 u32 rxctrl = 0; 1357 u8 reg_idx = rx_ring->reg_idx; 1358 1359 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1360 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1361 1362 switch (hw->mac.type) { 1363 case ixgbe_mac_82599EB: 1364 case ixgbe_mac_X540: 1365 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1366 break; 1367 default: 1368 break; 1369 } 1370 1371 /* 1372 * We can enable relaxed ordering for reads, but not writes when 1373 * DCA is enabled. This is due to a known issue in some chipsets 1374 * which will cause the DCA tag to be cleared. 1375 */ 1376 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1377 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1378 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1379 1380 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1381 } 1382 1383 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1384 { 1385 struct ixgbe_adapter *adapter = q_vector->adapter; 1386 struct ixgbe_ring *ring; 1387 int cpu = get_cpu(); 1388 1389 if (q_vector->cpu == cpu) 1390 goto out_no_update; 1391 1392 ixgbe_for_each_ring(ring, q_vector->tx) 1393 ixgbe_update_tx_dca(adapter, ring, cpu); 1394 1395 ixgbe_for_each_ring(ring, q_vector->rx) 1396 ixgbe_update_rx_dca(adapter, ring, cpu); 1397 1398 q_vector->cpu = cpu; 1399 out_no_update: 1400 put_cpu(); 1401 } 1402 1403 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1404 { 1405 int i; 1406 1407 /* always use CB2 mode, difference is masked in the CB driver */ 1408 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1409 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1410 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1411 else 1412 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1413 IXGBE_DCA_CTRL_DCA_DISABLE); 1414 1415 for (i = 0; i < adapter->num_q_vectors; i++) { 1416 adapter->q_vector[i]->cpu = -1; 1417 ixgbe_update_dca(adapter->q_vector[i]); 1418 } 1419 } 1420 1421 static int __ixgbe_notify_dca(struct device *dev, void *data) 1422 { 1423 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1424 unsigned long event = *(unsigned long *)data; 1425 1426 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1427 return 0; 1428 1429 switch (event) { 1430 case DCA_PROVIDER_ADD: 1431 /* if we're already enabled, don't do it again */ 1432 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1433 break; 1434 if (dca_add_requester(dev) == 0) { 1435 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1436 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1437 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1438 break; 1439 } 1440 /* fall through - DCA is disabled. */ 1441 case DCA_PROVIDER_REMOVE: 1442 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1443 dca_remove_requester(dev); 1444 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1446 IXGBE_DCA_CTRL_DCA_DISABLE); 1447 } 1448 break; 1449 } 1450 1451 return 0; 1452 } 1453 1454 #endif /* CONFIG_IXGBE_DCA */ 1455 1456 #define IXGBE_RSS_L4_TYPES_MASK \ 1457 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1458 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1459 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1460 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1461 1462 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1463 union ixgbe_adv_rx_desc *rx_desc, 1464 struct sk_buff *skb) 1465 { 1466 u16 rss_type; 1467 1468 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1469 return; 1470 1471 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1472 IXGBE_RXDADV_RSSTYPE_MASK; 1473 1474 if (!rss_type) 1475 return; 1476 1477 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1478 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1479 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1480 } 1481 1482 #ifdef IXGBE_FCOE 1483 /** 1484 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1485 * @ring: structure containing ring specific data 1486 * @rx_desc: advanced rx descriptor 1487 * 1488 * Returns : true if it is FCoE pkt 1489 */ 1490 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1491 union ixgbe_adv_rx_desc *rx_desc) 1492 { 1493 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1494 1495 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1496 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1497 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1498 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1499 } 1500 1501 #endif /* IXGBE_FCOE */ 1502 /** 1503 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1504 * @ring: structure containing ring specific data 1505 * @rx_desc: current Rx descriptor being processed 1506 * @skb: skb currently being received and modified 1507 **/ 1508 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1509 union ixgbe_adv_rx_desc *rx_desc, 1510 struct sk_buff *skb) 1511 { 1512 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1513 bool encap_pkt = false; 1514 1515 skb_checksum_none_assert(skb); 1516 1517 /* Rx csum disabled */ 1518 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1519 return; 1520 1521 /* check for VXLAN and Geneve packets */ 1522 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1523 encap_pkt = true; 1524 skb->encapsulation = 1; 1525 } 1526 1527 /* if IP and error */ 1528 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1529 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1530 ring->rx_stats.csum_err++; 1531 return; 1532 } 1533 1534 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1535 return; 1536 1537 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1538 /* 1539 * 82599 errata, UDP frames with a 0 checksum can be marked as 1540 * checksum errors. 1541 */ 1542 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1543 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1544 return; 1545 1546 ring->rx_stats.csum_err++; 1547 return; 1548 } 1549 1550 /* It must be a TCP or UDP packet with a valid checksum */ 1551 skb->ip_summed = CHECKSUM_UNNECESSARY; 1552 if (encap_pkt) { 1553 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1554 return; 1555 1556 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1557 skb->ip_summed = CHECKSUM_NONE; 1558 return; 1559 } 1560 /* If we checked the outer header let the stack know */ 1561 skb->csum_level = 1; 1562 } 1563 } 1564 1565 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1566 { 1567 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1568 } 1569 1570 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1571 struct ixgbe_rx_buffer *bi) 1572 { 1573 struct page *page = bi->page; 1574 dma_addr_t dma; 1575 1576 /* since we are recycling buffers we should seldom need to alloc */ 1577 if (likely(page)) 1578 return true; 1579 1580 /* alloc new page for storage */ 1581 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1582 if (unlikely(!page)) { 1583 rx_ring->rx_stats.alloc_rx_page_failed++; 1584 return false; 1585 } 1586 1587 /* map page for use */ 1588 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1589 ixgbe_rx_pg_size(rx_ring), 1590 DMA_FROM_DEVICE, 1591 IXGBE_RX_DMA_ATTR); 1592 1593 /* 1594 * if mapping failed free memory back to system since 1595 * there isn't much point in holding memory we can't use 1596 */ 1597 if (dma_mapping_error(rx_ring->dev, dma)) { 1598 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1599 1600 rx_ring->rx_stats.alloc_rx_page_failed++; 1601 return false; 1602 } 1603 1604 bi->dma = dma; 1605 bi->page = page; 1606 bi->page_offset = ixgbe_rx_offset(rx_ring); 1607 page_ref_add(page, USHRT_MAX - 1); 1608 bi->pagecnt_bias = USHRT_MAX; 1609 rx_ring->rx_stats.alloc_rx_page++; 1610 1611 return true; 1612 } 1613 1614 /** 1615 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1616 * @rx_ring: ring to place buffers on 1617 * @cleaned_count: number of buffers to replace 1618 **/ 1619 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1620 { 1621 union ixgbe_adv_rx_desc *rx_desc; 1622 struct ixgbe_rx_buffer *bi; 1623 u16 i = rx_ring->next_to_use; 1624 u16 bufsz; 1625 1626 /* nothing to do */ 1627 if (!cleaned_count) 1628 return; 1629 1630 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1631 bi = &rx_ring->rx_buffer_info[i]; 1632 i -= rx_ring->count; 1633 1634 bufsz = ixgbe_rx_bufsz(rx_ring); 1635 1636 do { 1637 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1638 break; 1639 1640 /* sync the buffer for use by the device */ 1641 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1642 bi->page_offset, bufsz, 1643 DMA_FROM_DEVICE); 1644 1645 /* 1646 * Refresh the desc even if buffer_addrs didn't change 1647 * because each write-back erases this info. 1648 */ 1649 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1650 1651 rx_desc++; 1652 bi++; 1653 i++; 1654 if (unlikely(!i)) { 1655 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1656 bi = rx_ring->rx_buffer_info; 1657 i -= rx_ring->count; 1658 } 1659 1660 /* clear the length for the next_to_use descriptor */ 1661 rx_desc->wb.upper.length = 0; 1662 1663 cleaned_count--; 1664 } while (cleaned_count); 1665 1666 i += rx_ring->count; 1667 1668 if (rx_ring->next_to_use != i) { 1669 rx_ring->next_to_use = i; 1670 1671 /* update next to alloc since we have filled the ring */ 1672 rx_ring->next_to_alloc = i; 1673 1674 /* Force memory writes to complete before letting h/w 1675 * know there are new descriptors to fetch. (Only 1676 * applicable for weak-ordered memory model archs, 1677 * such as IA-64). 1678 */ 1679 wmb(); 1680 writel(i, rx_ring->tail); 1681 } 1682 } 1683 1684 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1685 struct sk_buff *skb) 1686 { 1687 u16 hdr_len = skb_headlen(skb); 1688 1689 /* set gso_size to avoid messing up TCP MSS */ 1690 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1691 IXGBE_CB(skb)->append_cnt); 1692 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1693 } 1694 1695 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1696 struct sk_buff *skb) 1697 { 1698 /* if append_cnt is 0 then frame is not RSC */ 1699 if (!IXGBE_CB(skb)->append_cnt) 1700 return; 1701 1702 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1703 rx_ring->rx_stats.rsc_flush++; 1704 1705 ixgbe_set_rsc_gso_size(rx_ring, skb); 1706 1707 /* gso_size is computed using append_cnt so always clear it last */ 1708 IXGBE_CB(skb)->append_cnt = 0; 1709 } 1710 1711 /** 1712 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1713 * @rx_ring: rx descriptor ring packet is being transacted on 1714 * @rx_desc: pointer to the EOP Rx descriptor 1715 * @skb: pointer to current skb being populated 1716 * 1717 * This function checks the ring, descriptor, and packet information in 1718 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1719 * other fields within the skb. 1720 **/ 1721 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1722 union ixgbe_adv_rx_desc *rx_desc, 1723 struct sk_buff *skb) 1724 { 1725 struct net_device *dev = rx_ring->netdev; 1726 u32 flags = rx_ring->q_vector->adapter->flags; 1727 1728 ixgbe_update_rsc_stats(rx_ring, skb); 1729 1730 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1731 1732 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1733 1734 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1735 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1736 1737 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1738 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1739 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1740 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1741 } 1742 1743 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1744 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1745 1746 /* record Rx queue, or update MACVLAN statistics */ 1747 if (netif_is_ixgbe(dev)) 1748 skb_record_rx_queue(skb, rx_ring->queue_index); 1749 else 1750 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1751 false); 1752 1753 skb->protocol = eth_type_trans(skb, dev); 1754 } 1755 1756 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1757 struct sk_buff *skb) 1758 { 1759 napi_gro_receive(&q_vector->napi, skb); 1760 } 1761 1762 /** 1763 * ixgbe_is_non_eop - process handling of non-EOP buffers 1764 * @rx_ring: Rx ring being processed 1765 * @rx_desc: Rx descriptor for current buffer 1766 * @skb: Current socket buffer containing buffer in progress 1767 * 1768 * This function updates next to clean. If the buffer is an EOP buffer 1769 * this function exits returning false, otherwise it will place the 1770 * sk_buff in the next buffer to be chained and return true indicating 1771 * that this is in fact a non-EOP buffer. 1772 **/ 1773 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1774 union ixgbe_adv_rx_desc *rx_desc, 1775 struct sk_buff *skb) 1776 { 1777 u32 ntc = rx_ring->next_to_clean + 1; 1778 1779 /* fetch, update, and store next to clean */ 1780 ntc = (ntc < rx_ring->count) ? ntc : 0; 1781 rx_ring->next_to_clean = ntc; 1782 1783 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1784 1785 /* update RSC append count if present */ 1786 if (ring_is_rsc_enabled(rx_ring)) { 1787 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1788 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1789 1790 if (unlikely(rsc_enabled)) { 1791 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1792 1793 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1794 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1795 1796 /* update ntc based on RSC value */ 1797 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1798 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1799 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1800 } 1801 } 1802 1803 /* if we are the last buffer then there is nothing else to do */ 1804 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1805 return false; 1806 1807 /* place skb in next buffer to be received */ 1808 rx_ring->rx_buffer_info[ntc].skb = skb; 1809 rx_ring->rx_stats.non_eop_descs++; 1810 1811 return true; 1812 } 1813 1814 /** 1815 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1816 * @rx_ring: rx descriptor ring packet is being transacted on 1817 * @skb: pointer to current skb being adjusted 1818 * 1819 * This function is an ixgbe specific version of __pskb_pull_tail. The 1820 * main difference between this version and the original function is that 1821 * this function can make several assumptions about the state of things 1822 * that allow for significant optimizations versus the standard function. 1823 * As a result we can do things like drop a frag and maintain an accurate 1824 * truesize for the skb. 1825 */ 1826 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1827 struct sk_buff *skb) 1828 { 1829 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1830 unsigned char *va; 1831 unsigned int pull_len; 1832 1833 /* 1834 * it is valid to use page_address instead of kmap since we are 1835 * working with pages allocated out of the lomem pool per 1836 * alloc_page(GFP_ATOMIC) 1837 */ 1838 va = skb_frag_address(frag); 1839 1840 /* 1841 * we need the header to contain the greater of either ETH_HLEN or 1842 * 60 bytes if the skb->len is less than 60 for skb_pad. 1843 */ 1844 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1845 1846 /* align pull length to size of long to optimize memcpy performance */ 1847 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1848 1849 /* update all of the pointers */ 1850 skb_frag_size_sub(frag, pull_len); 1851 frag->page_offset += pull_len; 1852 skb->data_len -= pull_len; 1853 skb->tail += pull_len; 1854 } 1855 1856 /** 1857 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1858 * @rx_ring: rx descriptor ring packet is being transacted on 1859 * @skb: pointer to current skb being updated 1860 * 1861 * This function provides a basic DMA sync up for the first fragment of an 1862 * skb. The reason for doing this is that the first fragment cannot be 1863 * unmapped until we have reached the end of packet descriptor for a buffer 1864 * chain. 1865 */ 1866 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1867 struct sk_buff *skb) 1868 { 1869 /* if the page was released unmap it, else just sync our portion */ 1870 if (unlikely(IXGBE_CB(skb)->page_released)) { 1871 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1872 ixgbe_rx_pg_size(rx_ring), 1873 DMA_FROM_DEVICE, 1874 IXGBE_RX_DMA_ATTR); 1875 } else if (ring_uses_build_skb(rx_ring)) { 1876 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1877 1878 dma_sync_single_range_for_cpu(rx_ring->dev, 1879 IXGBE_CB(skb)->dma, 1880 offset, 1881 skb_headlen(skb), 1882 DMA_FROM_DEVICE); 1883 } else { 1884 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1885 1886 dma_sync_single_range_for_cpu(rx_ring->dev, 1887 IXGBE_CB(skb)->dma, 1888 frag->page_offset, 1889 skb_frag_size(frag), 1890 DMA_FROM_DEVICE); 1891 } 1892 } 1893 1894 /** 1895 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1896 * @rx_ring: rx descriptor ring packet is being transacted on 1897 * @rx_desc: pointer to the EOP Rx descriptor 1898 * @skb: pointer to current skb being fixed 1899 * 1900 * Check if the skb is valid in the XDP case it will be an error pointer. 1901 * Return true in this case to abort processing and advance to next 1902 * descriptor. 1903 * 1904 * Check for corrupted packet headers caused by senders on the local L2 1905 * embedded NIC switch not setting up their Tx Descriptors right. These 1906 * should be very rare. 1907 * 1908 * Also address the case where we are pulling data in on pages only 1909 * and as such no data is present in the skb header. 1910 * 1911 * In addition if skb is not at least 60 bytes we need to pad it so that 1912 * it is large enough to qualify as a valid Ethernet frame. 1913 * 1914 * Returns true if an error was encountered and skb was freed. 1915 **/ 1916 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1917 union ixgbe_adv_rx_desc *rx_desc, 1918 struct sk_buff *skb) 1919 { 1920 struct net_device *netdev = rx_ring->netdev; 1921 1922 /* XDP packets use error pointer so abort at this point */ 1923 if (IS_ERR(skb)) 1924 return true; 1925 1926 /* Verify netdev is present, and that packet does not have any 1927 * errors that would be unacceptable to the netdev. 1928 */ 1929 if (!netdev || 1930 (unlikely(ixgbe_test_staterr(rx_desc, 1931 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1932 !(netdev->features & NETIF_F_RXALL)))) { 1933 dev_kfree_skb_any(skb); 1934 return true; 1935 } 1936 1937 /* place header in linear portion of buffer */ 1938 if (!skb_headlen(skb)) 1939 ixgbe_pull_tail(rx_ring, skb); 1940 1941 #ifdef IXGBE_FCOE 1942 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1943 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1944 return false; 1945 1946 #endif 1947 /* if eth_skb_pad returns an error the skb was freed */ 1948 if (eth_skb_pad(skb)) 1949 return true; 1950 1951 return false; 1952 } 1953 1954 /** 1955 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1956 * @rx_ring: rx descriptor ring to store buffers on 1957 * @old_buff: donor buffer to have page reused 1958 * 1959 * Synchronizes page for reuse by the adapter 1960 **/ 1961 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1962 struct ixgbe_rx_buffer *old_buff) 1963 { 1964 struct ixgbe_rx_buffer *new_buff; 1965 u16 nta = rx_ring->next_to_alloc; 1966 1967 new_buff = &rx_ring->rx_buffer_info[nta]; 1968 1969 /* update, and store next to alloc */ 1970 nta++; 1971 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1972 1973 /* Transfer page from old buffer to new buffer. 1974 * Move each member individually to avoid possible store 1975 * forwarding stalls and unnecessary copy of skb. 1976 */ 1977 new_buff->dma = old_buff->dma; 1978 new_buff->page = old_buff->page; 1979 new_buff->page_offset = old_buff->page_offset; 1980 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1981 } 1982 1983 static inline bool ixgbe_page_is_reserved(struct page *page) 1984 { 1985 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1986 } 1987 1988 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1989 { 1990 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1991 struct page *page = rx_buffer->page; 1992 1993 /* avoid re-using remote pages */ 1994 if (unlikely(ixgbe_page_is_reserved(page))) 1995 return false; 1996 1997 #if (PAGE_SIZE < 8192) 1998 /* if we are only owner of page we can reuse it */ 1999 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 2000 return false; 2001 #else 2002 /* The last offset is a bit aggressive in that we assume the 2003 * worst case of FCoE being enabled and using a 3K buffer. 2004 * However this should have minimal impact as the 1K extra is 2005 * still less than one buffer in size. 2006 */ 2007 #define IXGBE_LAST_OFFSET \ 2008 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2009 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2010 return false; 2011 #endif 2012 2013 /* If we have drained the page fragment pool we need to update 2014 * the pagecnt_bias and page count so that we fully restock the 2015 * number of references the driver holds. 2016 */ 2017 if (unlikely(pagecnt_bias == 1)) { 2018 page_ref_add(page, USHRT_MAX - 1); 2019 rx_buffer->pagecnt_bias = USHRT_MAX; 2020 } 2021 2022 return true; 2023 } 2024 2025 /** 2026 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2027 * @rx_ring: rx descriptor ring to transact packets on 2028 * @rx_buffer: buffer containing page to add 2029 * @skb: sk_buff to place the data into 2030 * @size: size of data in rx_buffer 2031 * 2032 * This function will add the data contained in rx_buffer->page to the skb. 2033 * This is done either through a direct copy if the data in the buffer is 2034 * less than the skb header size, otherwise it will just attach the page as 2035 * a frag to the skb. 2036 * 2037 * The function will then update the page offset if necessary and return 2038 * true if the buffer can be reused by the adapter. 2039 **/ 2040 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2041 struct ixgbe_rx_buffer *rx_buffer, 2042 struct sk_buff *skb, 2043 unsigned int size) 2044 { 2045 #if (PAGE_SIZE < 8192) 2046 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2047 #else 2048 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2049 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2050 SKB_DATA_ALIGN(size); 2051 #endif 2052 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2053 rx_buffer->page_offset, size, truesize); 2054 #if (PAGE_SIZE < 8192) 2055 rx_buffer->page_offset ^= truesize; 2056 #else 2057 rx_buffer->page_offset += truesize; 2058 #endif 2059 } 2060 2061 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2062 union ixgbe_adv_rx_desc *rx_desc, 2063 struct sk_buff **skb, 2064 const unsigned int size) 2065 { 2066 struct ixgbe_rx_buffer *rx_buffer; 2067 2068 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2069 prefetchw(rx_buffer->page); 2070 *skb = rx_buffer->skb; 2071 2072 /* Delay unmapping of the first packet. It carries the header 2073 * information, HW may still access the header after the writeback. 2074 * Only unmap it when EOP is reached 2075 */ 2076 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2077 if (!*skb) 2078 goto skip_sync; 2079 } else { 2080 if (*skb) 2081 ixgbe_dma_sync_frag(rx_ring, *skb); 2082 } 2083 2084 /* we are reusing so sync this buffer for CPU use */ 2085 dma_sync_single_range_for_cpu(rx_ring->dev, 2086 rx_buffer->dma, 2087 rx_buffer->page_offset, 2088 size, 2089 DMA_FROM_DEVICE); 2090 skip_sync: 2091 rx_buffer->pagecnt_bias--; 2092 2093 return rx_buffer; 2094 } 2095 2096 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2097 struct ixgbe_rx_buffer *rx_buffer, 2098 struct sk_buff *skb) 2099 { 2100 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2101 /* hand second half of page back to the ring */ 2102 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2103 } else { 2104 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2105 /* the page has been released from the ring */ 2106 IXGBE_CB(skb)->page_released = true; 2107 } else { 2108 /* we are not reusing the buffer so unmap it */ 2109 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2110 ixgbe_rx_pg_size(rx_ring), 2111 DMA_FROM_DEVICE, 2112 IXGBE_RX_DMA_ATTR); 2113 } 2114 __page_frag_cache_drain(rx_buffer->page, 2115 rx_buffer->pagecnt_bias); 2116 } 2117 2118 /* clear contents of rx_buffer */ 2119 rx_buffer->page = NULL; 2120 rx_buffer->skb = NULL; 2121 } 2122 2123 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2124 struct ixgbe_rx_buffer *rx_buffer, 2125 struct xdp_buff *xdp, 2126 union ixgbe_adv_rx_desc *rx_desc) 2127 { 2128 unsigned int size = xdp->data_end - xdp->data; 2129 #if (PAGE_SIZE < 8192) 2130 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2131 #else 2132 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2133 xdp->data_hard_start); 2134 #endif 2135 struct sk_buff *skb; 2136 2137 /* prefetch first cache line of first page */ 2138 prefetch(xdp->data); 2139 #if L1_CACHE_BYTES < 128 2140 prefetch(xdp->data + L1_CACHE_BYTES); 2141 #endif 2142 /* Note, we get here by enabling legacy-rx via: 2143 * 2144 * ethtool --set-priv-flags <dev> legacy-rx on 2145 * 2146 * In this mode, we currently get 0 extra XDP headroom as 2147 * opposed to having legacy-rx off, where we process XDP 2148 * packets going to stack via ixgbe_build_skb(). The latter 2149 * provides us currently with 192 bytes of headroom. 2150 * 2151 * For ixgbe_construct_skb() mode it means that the 2152 * xdp->data_meta will always point to xdp->data, since 2153 * the helper cannot expand the head. Should this ever 2154 * change in future for legacy-rx mode on, then lets also 2155 * add xdp->data_meta handling here. 2156 */ 2157 2158 /* allocate a skb to store the frags */ 2159 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2160 if (unlikely(!skb)) 2161 return NULL; 2162 2163 if (size > IXGBE_RX_HDR_SIZE) { 2164 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2165 IXGBE_CB(skb)->dma = rx_buffer->dma; 2166 2167 skb_add_rx_frag(skb, 0, rx_buffer->page, 2168 xdp->data - page_address(rx_buffer->page), 2169 size, truesize); 2170 #if (PAGE_SIZE < 8192) 2171 rx_buffer->page_offset ^= truesize; 2172 #else 2173 rx_buffer->page_offset += truesize; 2174 #endif 2175 } else { 2176 memcpy(__skb_put(skb, size), 2177 xdp->data, ALIGN(size, sizeof(long))); 2178 rx_buffer->pagecnt_bias++; 2179 } 2180 2181 return skb; 2182 } 2183 2184 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2185 struct ixgbe_rx_buffer *rx_buffer, 2186 struct xdp_buff *xdp, 2187 union ixgbe_adv_rx_desc *rx_desc) 2188 { 2189 unsigned int metasize = xdp->data - xdp->data_meta; 2190 #if (PAGE_SIZE < 8192) 2191 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2192 #else 2193 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2194 SKB_DATA_ALIGN(xdp->data_end - 2195 xdp->data_hard_start); 2196 #endif 2197 struct sk_buff *skb; 2198 2199 /* Prefetch first cache line of first page. If xdp->data_meta 2200 * is unused, this points extactly as xdp->data, otherwise we 2201 * likely have a consumer accessing first few bytes of meta 2202 * data, and then actual data. 2203 */ 2204 prefetch(xdp->data_meta); 2205 #if L1_CACHE_BYTES < 128 2206 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2207 #endif 2208 2209 /* build an skb to around the page buffer */ 2210 skb = build_skb(xdp->data_hard_start, truesize); 2211 if (unlikely(!skb)) 2212 return NULL; 2213 2214 /* update pointers within the skb to store the data */ 2215 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2216 __skb_put(skb, xdp->data_end - xdp->data); 2217 if (metasize) 2218 skb_metadata_set(skb, metasize); 2219 2220 /* record DMA address if this is the start of a chain of buffers */ 2221 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2222 IXGBE_CB(skb)->dma = rx_buffer->dma; 2223 2224 /* update buffer offset */ 2225 #if (PAGE_SIZE < 8192) 2226 rx_buffer->page_offset ^= truesize; 2227 #else 2228 rx_buffer->page_offset += truesize; 2229 #endif 2230 2231 return skb; 2232 } 2233 2234 #define IXGBE_XDP_PASS 0 2235 #define IXGBE_XDP_CONSUMED 1 2236 #define IXGBE_XDP_TX 2 2237 2238 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2239 struct xdp_frame *xdpf); 2240 2241 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2242 struct ixgbe_ring *rx_ring, 2243 struct xdp_buff *xdp) 2244 { 2245 int err, result = IXGBE_XDP_PASS; 2246 struct bpf_prog *xdp_prog; 2247 struct xdp_frame *xdpf; 2248 u32 act; 2249 2250 rcu_read_lock(); 2251 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2252 2253 if (!xdp_prog) 2254 goto xdp_out; 2255 2256 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2257 2258 act = bpf_prog_run_xdp(xdp_prog, xdp); 2259 switch (act) { 2260 case XDP_PASS: 2261 break; 2262 case XDP_TX: 2263 xdpf = convert_to_xdp_frame(xdp); 2264 if (unlikely(!xdpf)) { 2265 result = IXGBE_XDP_CONSUMED; 2266 break; 2267 } 2268 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2269 break; 2270 case XDP_REDIRECT: 2271 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2272 if (!err) 2273 result = IXGBE_XDP_TX; 2274 else 2275 result = IXGBE_XDP_CONSUMED; 2276 break; 2277 default: 2278 bpf_warn_invalid_xdp_action(act); 2279 /* fallthrough */ 2280 case XDP_ABORTED: 2281 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2282 /* fallthrough -- handle aborts by dropping packet */ 2283 case XDP_DROP: 2284 result = IXGBE_XDP_CONSUMED; 2285 break; 2286 } 2287 xdp_out: 2288 rcu_read_unlock(); 2289 return ERR_PTR(-result); 2290 } 2291 2292 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2293 struct ixgbe_rx_buffer *rx_buffer, 2294 unsigned int size) 2295 { 2296 #if (PAGE_SIZE < 8192) 2297 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2298 2299 rx_buffer->page_offset ^= truesize; 2300 #else 2301 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2302 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2303 SKB_DATA_ALIGN(size); 2304 2305 rx_buffer->page_offset += truesize; 2306 #endif 2307 } 2308 2309 /** 2310 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2311 * @q_vector: structure containing interrupt and ring information 2312 * @rx_ring: rx descriptor ring to transact packets on 2313 * @budget: Total limit on number of packets to process 2314 * 2315 * This function provides a "bounce buffer" approach to Rx interrupt 2316 * processing. The advantage to this is that on systems that have 2317 * expensive overhead for IOMMU access this provides a means of avoiding 2318 * it by maintaining the mapping of the page to the syste. 2319 * 2320 * Returns amount of work completed 2321 **/ 2322 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2323 struct ixgbe_ring *rx_ring, 2324 const int budget) 2325 { 2326 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2327 struct ixgbe_adapter *adapter = q_vector->adapter; 2328 #ifdef IXGBE_FCOE 2329 int ddp_bytes; 2330 unsigned int mss = 0; 2331 #endif /* IXGBE_FCOE */ 2332 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2333 bool xdp_xmit = false; 2334 struct xdp_buff xdp; 2335 2336 xdp.rxq = &rx_ring->xdp_rxq; 2337 2338 while (likely(total_rx_packets < budget)) { 2339 union ixgbe_adv_rx_desc *rx_desc; 2340 struct ixgbe_rx_buffer *rx_buffer; 2341 struct sk_buff *skb; 2342 unsigned int size; 2343 2344 /* return some buffers to hardware, one at a time is too slow */ 2345 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2346 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2347 cleaned_count = 0; 2348 } 2349 2350 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2351 size = le16_to_cpu(rx_desc->wb.upper.length); 2352 if (!size) 2353 break; 2354 2355 /* This memory barrier is needed to keep us from reading 2356 * any other fields out of the rx_desc until we know the 2357 * descriptor has been written back 2358 */ 2359 dma_rmb(); 2360 2361 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2362 2363 /* retrieve a buffer from the ring */ 2364 if (!skb) { 2365 xdp.data = page_address(rx_buffer->page) + 2366 rx_buffer->page_offset; 2367 xdp.data_meta = xdp.data; 2368 xdp.data_hard_start = xdp.data - 2369 ixgbe_rx_offset(rx_ring); 2370 xdp.data_end = xdp.data + size; 2371 2372 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2373 } 2374 2375 if (IS_ERR(skb)) { 2376 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2377 xdp_xmit = true; 2378 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2379 } else { 2380 rx_buffer->pagecnt_bias++; 2381 } 2382 total_rx_packets++; 2383 total_rx_bytes += size; 2384 } else if (skb) { 2385 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2386 } else if (ring_uses_build_skb(rx_ring)) { 2387 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2388 &xdp, rx_desc); 2389 } else { 2390 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2391 &xdp, rx_desc); 2392 } 2393 2394 /* exit if we failed to retrieve a buffer */ 2395 if (!skb) { 2396 rx_ring->rx_stats.alloc_rx_buff_failed++; 2397 rx_buffer->pagecnt_bias++; 2398 break; 2399 } 2400 2401 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2402 cleaned_count++; 2403 2404 /* place incomplete frames back on ring for completion */ 2405 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2406 continue; 2407 2408 /* verify the packet layout is correct */ 2409 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2410 continue; 2411 2412 /* probably a little skewed due to removing CRC */ 2413 total_rx_bytes += skb->len; 2414 2415 /* populate checksum, timestamp, VLAN, and protocol */ 2416 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2417 2418 #ifdef IXGBE_FCOE 2419 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2420 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2421 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2422 /* include DDPed FCoE data */ 2423 if (ddp_bytes > 0) { 2424 if (!mss) { 2425 mss = rx_ring->netdev->mtu - 2426 sizeof(struct fcoe_hdr) - 2427 sizeof(struct fc_frame_header) - 2428 sizeof(struct fcoe_crc_eof); 2429 if (mss > 512) 2430 mss &= ~511; 2431 } 2432 total_rx_bytes += ddp_bytes; 2433 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2434 mss); 2435 } 2436 if (!ddp_bytes) { 2437 dev_kfree_skb_any(skb); 2438 continue; 2439 } 2440 } 2441 2442 #endif /* IXGBE_FCOE */ 2443 ixgbe_rx_skb(q_vector, skb); 2444 2445 /* update budget accounting */ 2446 total_rx_packets++; 2447 } 2448 2449 if (xdp_xmit) { 2450 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2451 2452 /* Force memory writes to complete before letting h/w 2453 * know there are new descriptors to fetch. 2454 */ 2455 wmb(); 2456 writel(ring->next_to_use, ring->tail); 2457 2458 xdp_do_flush_map(); 2459 } 2460 2461 u64_stats_update_begin(&rx_ring->syncp); 2462 rx_ring->stats.packets += total_rx_packets; 2463 rx_ring->stats.bytes += total_rx_bytes; 2464 u64_stats_update_end(&rx_ring->syncp); 2465 q_vector->rx.total_packets += total_rx_packets; 2466 q_vector->rx.total_bytes += total_rx_bytes; 2467 2468 return total_rx_packets; 2469 } 2470 2471 /** 2472 * ixgbe_configure_msix - Configure MSI-X hardware 2473 * @adapter: board private structure 2474 * 2475 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2476 * interrupts. 2477 **/ 2478 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2479 { 2480 struct ixgbe_q_vector *q_vector; 2481 int v_idx; 2482 u32 mask; 2483 2484 /* Populate MSIX to EITR Select */ 2485 if (adapter->num_vfs > 32) { 2486 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2488 } 2489 2490 /* 2491 * Populate the IVAR table and set the ITR values to the 2492 * corresponding register. 2493 */ 2494 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2495 struct ixgbe_ring *ring; 2496 q_vector = adapter->q_vector[v_idx]; 2497 2498 ixgbe_for_each_ring(ring, q_vector->rx) 2499 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2500 2501 ixgbe_for_each_ring(ring, q_vector->tx) 2502 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2503 2504 ixgbe_write_eitr(q_vector); 2505 } 2506 2507 switch (adapter->hw.mac.type) { 2508 case ixgbe_mac_82598EB: 2509 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2510 v_idx); 2511 break; 2512 case ixgbe_mac_82599EB: 2513 case ixgbe_mac_X540: 2514 case ixgbe_mac_X550: 2515 case ixgbe_mac_X550EM_x: 2516 case ixgbe_mac_x550em_a: 2517 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2518 break; 2519 default: 2520 break; 2521 } 2522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2523 2524 /* set up to autoclear timer, and the vectors */ 2525 mask = IXGBE_EIMS_ENABLE_MASK; 2526 mask &= ~(IXGBE_EIMS_OTHER | 2527 IXGBE_EIMS_MAILBOX | 2528 IXGBE_EIMS_LSC); 2529 2530 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2531 } 2532 2533 /** 2534 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2535 * @q_vector: structure containing interrupt and ring information 2536 * @ring_container: structure containing ring performance data 2537 * 2538 * Stores a new ITR value based on packets and byte 2539 * counts during the last interrupt. The advantage of per interrupt 2540 * computation is faster updates and more accurate ITR for the current 2541 * traffic pattern. Constants in this function were computed 2542 * based on theoretical maximum wire speed and thresholds were set based 2543 * on testing data as well as attempting to minimize response time 2544 * while increasing bulk throughput. 2545 **/ 2546 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2547 struct ixgbe_ring_container *ring_container) 2548 { 2549 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2550 IXGBE_ITR_ADAPTIVE_LATENCY; 2551 unsigned int avg_wire_size, packets, bytes; 2552 unsigned long next_update = jiffies; 2553 2554 /* If we don't have any rings just leave ourselves set for maximum 2555 * possible latency so we take ourselves out of the equation. 2556 */ 2557 if (!ring_container->ring) 2558 return; 2559 2560 /* If we didn't update within up to 1 - 2 jiffies we can assume 2561 * that either packets are coming in so slow there hasn't been 2562 * any work, or that there is so much work that NAPI is dealing 2563 * with interrupt moderation and we don't need to do anything. 2564 */ 2565 if (time_after(next_update, ring_container->next_update)) 2566 goto clear_counts; 2567 2568 packets = ring_container->total_packets; 2569 2570 /* We have no packets to actually measure against. This means 2571 * either one of the other queues on this vector is active or 2572 * we are a Tx queue doing TSO with too high of an interrupt rate. 2573 * 2574 * When this occurs just tick up our delay by the minimum value 2575 * and hope that this extra delay will prevent us from being called 2576 * without any work on our queue. 2577 */ 2578 if (!packets) { 2579 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2580 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2581 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2582 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2583 goto clear_counts; 2584 } 2585 2586 bytes = ring_container->total_bytes; 2587 2588 /* If packets are less than 4 or bytes are less than 9000 assume 2589 * insufficient data to use bulk rate limiting approach. We are 2590 * likely latency driven. 2591 */ 2592 if (packets < 4 && bytes < 9000) { 2593 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2594 goto adjust_by_size; 2595 } 2596 2597 /* Between 4 and 48 we can assume that our current interrupt delay 2598 * is only slightly too low. As such we should increase it by a small 2599 * fixed amount. 2600 */ 2601 if (packets < 48) { 2602 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2603 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2604 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2605 goto clear_counts; 2606 } 2607 2608 /* Between 48 and 96 is our "goldilocks" zone where we are working 2609 * out "just right". Just report that our current ITR is good for us. 2610 */ 2611 if (packets < 96) { 2612 itr = q_vector->itr >> 2; 2613 goto clear_counts; 2614 } 2615 2616 /* If packet count is 96 or greater we are likely looking at a slight 2617 * overrun of the delay we want. Try halving our delay to see if that 2618 * will cut the number of packets in half per interrupt. 2619 */ 2620 if (packets < 256) { 2621 itr = q_vector->itr >> 3; 2622 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2623 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2624 goto clear_counts; 2625 } 2626 2627 /* The paths below assume we are dealing with a bulk ITR since number 2628 * of packets is 256 or greater. We are just going to have to compute 2629 * a value and try to bring the count under control, though for smaller 2630 * packet sizes there isn't much we can do as NAPI polling will likely 2631 * be kicking in sooner rather than later. 2632 */ 2633 itr = IXGBE_ITR_ADAPTIVE_BULK; 2634 2635 adjust_by_size: 2636 /* If packet counts are 256 or greater we can assume we have a gross 2637 * overestimation of what the rate should be. Instead of trying to fine 2638 * tune it just use the formula below to try and dial in an exact value 2639 * give the current packet size of the frame. 2640 */ 2641 avg_wire_size = bytes / packets; 2642 2643 /* The following is a crude approximation of: 2644 * wmem_default / (size + overhead) = desired_pkts_per_int 2645 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2646 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2647 * 2648 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2649 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2650 * formula down to 2651 * 2652 * (170 * (size + 24)) / (size + 640) = ITR 2653 * 2654 * We first do some math on the packet size and then finally bitshift 2655 * by 8 after rounding up. We also have to account for PCIe link speed 2656 * difference as ITR scales based on this. 2657 */ 2658 if (avg_wire_size <= 60) { 2659 /* Start at 50k ints/sec */ 2660 avg_wire_size = 5120; 2661 } else if (avg_wire_size <= 316) { 2662 /* 50K ints/sec to 16K ints/sec */ 2663 avg_wire_size *= 40; 2664 avg_wire_size += 2720; 2665 } else if (avg_wire_size <= 1084) { 2666 /* 16K ints/sec to 9.2K ints/sec */ 2667 avg_wire_size *= 15; 2668 avg_wire_size += 11452; 2669 } else if (avg_wire_size <= 1980) { 2670 /* 9.2K ints/sec to 8K ints/sec */ 2671 avg_wire_size *= 5; 2672 avg_wire_size += 22420; 2673 } else { 2674 /* plateau at a limit of 8K ints/sec */ 2675 avg_wire_size = 32256; 2676 } 2677 2678 /* If we are in low latency mode half our delay which doubles the rate 2679 * to somewhere between 100K to 16K ints/sec 2680 */ 2681 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2682 avg_wire_size >>= 1; 2683 2684 /* Resultant value is 256 times larger than it needs to be. This 2685 * gives us room to adjust the value as needed to either increase 2686 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2687 * 2688 * Use addition as we have already recorded the new latency flag 2689 * for the ITR value. 2690 */ 2691 switch (q_vector->adapter->link_speed) { 2692 case IXGBE_LINK_SPEED_10GB_FULL: 2693 case IXGBE_LINK_SPEED_100_FULL: 2694 default: 2695 itr += DIV_ROUND_UP(avg_wire_size, 2696 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2697 IXGBE_ITR_ADAPTIVE_MIN_INC; 2698 break; 2699 case IXGBE_LINK_SPEED_2_5GB_FULL: 2700 case IXGBE_LINK_SPEED_1GB_FULL: 2701 case IXGBE_LINK_SPEED_10_FULL: 2702 itr += DIV_ROUND_UP(avg_wire_size, 2703 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2704 IXGBE_ITR_ADAPTIVE_MIN_INC; 2705 break; 2706 } 2707 2708 clear_counts: 2709 /* write back value */ 2710 ring_container->itr = itr; 2711 2712 /* next update should occur within next jiffy */ 2713 ring_container->next_update = next_update + 1; 2714 2715 ring_container->total_bytes = 0; 2716 ring_container->total_packets = 0; 2717 } 2718 2719 /** 2720 * ixgbe_write_eitr - write EITR register in hardware specific way 2721 * @q_vector: structure containing interrupt and ring information 2722 * 2723 * This function is made to be called by ethtool and by the driver 2724 * when it needs to update EITR registers at runtime. Hardware 2725 * specific quirks/differences are taken care of here. 2726 */ 2727 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2728 { 2729 struct ixgbe_adapter *adapter = q_vector->adapter; 2730 struct ixgbe_hw *hw = &adapter->hw; 2731 int v_idx = q_vector->v_idx; 2732 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2733 2734 switch (adapter->hw.mac.type) { 2735 case ixgbe_mac_82598EB: 2736 /* must write high and low 16 bits to reset counter */ 2737 itr_reg |= (itr_reg << 16); 2738 break; 2739 case ixgbe_mac_82599EB: 2740 case ixgbe_mac_X540: 2741 case ixgbe_mac_X550: 2742 case ixgbe_mac_X550EM_x: 2743 case ixgbe_mac_x550em_a: 2744 /* 2745 * set the WDIS bit to not clear the timer bits and cause an 2746 * immediate assertion of the interrupt 2747 */ 2748 itr_reg |= IXGBE_EITR_CNT_WDIS; 2749 break; 2750 default: 2751 break; 2752 } 2753 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2754 } 2755 2756 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2757 { 2758 u32 new_itr; 2759 2760 ixgbe_update_itr(q_vector, &q_vector->tx); 2761 ixgbe_update_itr(q_vector, &q_vector->rx); 2762 2763 /* use the smallest value of new ITR delay calculations */ 2764 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2765 2766 /* Clear latency flag if set, shift into correct position */ 2767 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2768 new_itr <<= 2; 2769 2770 if (new_itr != q_vector->itr) { 2771 /* save the algorithm value here */ 2772 q_vector->itr = new_itr; 2773 2774 ixgbe_write_eitr(q_vector); 2775 } 2776 } 2777 2778 /** 2779 * ixgbe_check_overtemp_subtask - check for over temperature 2780 * @adapter: pointer to adapter 2781 **/ 2782 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2783 { 2784 struct ixgbe_hw *hw = &adapter->hw; 2785 u32 eicr = adapter->interrupt_event; 2786 s32 rc; 2787 2788 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2789 return; 2790 2791 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2792 return; 2793 2794 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2795 2796 switch (hw->device_id) { 2797 case IXGBE_DEV_ID_82599_T3_LOM: 2798 /* 2799 * Since the warning interrupt is for both ports 2800 * we don't have to check if: 2801 * - This interrupt wasn't for our port. 2802 * - We may have missed the interrupt so always have to 2803 * check if we got a LSC 2804 */ 2805 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2806 !(eicr & IXGBE_EICR_LSC)) 2807 return; 2808 2809 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2810 u32 speed; 2811 bool link_up = false; 2812 2813 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2814 2815 if (link_up) 2816 return; 2817 } 2818 2819 /* Check if this is not due to overtemp */ 2820 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2821 return; 2822 2823 break; 2824 case IXGBE_DEV_ID_X550EM_A_1G_T: 2825 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2826 rc = hw->phy.ops.check_overtemp(hw); 2827 if (rc != IXGBE_ERR_OVERTEMP) 2828 return; 2829 break; 2830 default: 2831 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2832 return; 2833 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2834 return; 2835 break; 2836 } 2837 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2838 2839 adapter->interrupt_event = 0; 2840 } 2841 2842 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2843 { 2844 struct ixgbe_hw *hw = &adapter->hw; 2845 2846 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2847 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2848 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2849 /* write to clear the interrupt */ 2850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2851 } 2852 } 2853 2854 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2855 { 2856 struct ixgbe_hw *hw = &adapter->hw; 2857 2858 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2859 return; 2860 2861 switch (adapter->hw.mac.type) { 2862 case ixgbe_mac_82599EB: 2863 /* 2864 * Need to check link state so complete overtemp check 2865 * on service task 2866 */ 2867 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2868 (eicr & IXGBE_EICR_LSC)) && 2869 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2870 adapter->interrupt_event = eicr; 2871 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2872 ixgbe_service_event_schedule(adapter); 2873 return; 2874 } 2875 return; 2876 case ixgbe_mac_x550em_a: 2877 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2878 adapter->interrupt_event = eicr; 2879 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2880 ixgbe_service_event_schedule(adapter); 2881 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2882 IXGBE_EICR_GPI_SDP0_X550EM_a); 2883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2884 IXGBE_EICR_GPI_SDP0_X550EM_a); 2885 } 2886 return; 2887 case ixgbe_mac_X550: 2888 case ixgbe_mac_X540: 2889 if (!(eicr & IXGBE_EICR_TS)) 2890 return; 2891 break; 2892 default: 2893 return; 2894 } 2895 2896 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2897 } 2898 2899 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2900 { 2901 switch (hw->mac.type) { 2902 case ixgbe_mac_82598EB: 2903 if (hw->phy.type == ixgbe_phy_nl) 2904 return true; 2905 return false; 2906 case ixgbe_mac_82599EB: 2907 case ixgbe_mac_X550EM_x: 2908 case ixgbe_mac_x550em_a: 2909 switch (hw->mac.ops.get_media_type(hw)) { 2910 case ixgbe_media_type_fiber: 2911 case ixgbe_media_type_fiber_qsfp: 2912 return true; 2913 default: 2914 return false; 2915 } 2916 default: 2917 return false; 2918 } 2919 } 2920 2921 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2922 { 2923 struct ixgbe_hw *hw = &adapter->hw; 2924 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2925 2926 if (!ixgbe_is_sfp(hw)) 2927 return; 2928 2929 /* Later MAC's use different SDP */ 2930 if (hw->mac.type >= ixgbe_mac_X540) 2931 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2932 2933 if (eicr & eicr_mask) { 2934 /* Clear the interrupt */ 2935 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2936 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2937 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2938 adapter->sfp_poll_time = 0; 2939 ixgbe_service_event_schedule(adapter); 2940 } 2941 } 2942 2943 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2944 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2945 /* Clear the interrupt */ 2946 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2947 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2948 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2949 ixgbe_service_event_schedule(adapter); 2950 } 2951 } 2952 } 2953 2954 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2955 { 2956 struct ixgbe_hw *hw = &adapter->hw; 2957 2958 adapter->lsc_int++; 2959 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2960 adapter->link_check_timeout = jiffies; 2961 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2962 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2963 IXGBE_WRITE_FLUSH(hw); 2964 ixgbe_service_event_schedule(adapter); 2965 } 2966 } 2967 2968 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2969 u64 qmask) 2970 { 2971 u32 mask; 2972 struct ixgbe_hw *hw = &adapter->hw; 2973 2974 switch (hw->mac.type) { 2975 case ixgbe_mac_82598EB: 2976 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2977 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2978 break; 2979 case ixgbe_mac_82599EB: 2980 case ixgbe_mac_X540: 2981 case ixgbe_mac_X550: 2982 case ixgbe_mac_X550EM_x: 2983 case ixgbe_mac_x550em_a: 2984 mask = (qmask & 0xFFFFFFFF); 2985 if (mask) 2986 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2987 mask = (qmask >> 32); 2988 if (mask) 2989 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2990 break; 2991 default: 2992 break; 2993 } 2994 /* skip the flush */ 2995 } 2996 2997 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2998 u64 qmask) 2999 { 3000 u32 mask; 3001 struct ixgbe_hw *hw = &adapter->hw; 3002 3003 switch (hw->mac.type) { 3004 case ixgbe_mac_82598EB: 3005 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3006 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3007 break; 3008 case ixgbe_mac_82599EB: 3009 case ixgbe_mac_X540: 3010 case ixgbe_mac_X550: 3011 case ixgbe_mac_X550EM_x: 3012 case ixgbe_mac_x550em_a: 3013 mask = (qmask & 0xFFFFFFFF); 3014 if (mask) 3015 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3016 mask = (qmask >> 32); 3017 if (mask) 3018 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3019 break; 3020 default: 3021 break; 3022 } 3023 /* skip the flush */ 3024 } 3025 3026 /** 3027 * ixgbe_irq_enable - Enable default interrupt generation settings 3028 * @adapter: board private structure 3029 * @queues: enable irqs for queues 3030 * @flush: flush register write 3031 **/ 3032 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3033 bool flush) 3034 { 3035 struct ixgbe_hw *hw = &adapter->hw; 3036 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3037 3038 /* don't reenable LSC while waiting for link */ 3039 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3040 mask &= ~IXGBE_EIMS_LSC; 3041 3042 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3043 switch (adapter->hw.mac.type) { 3044 case ixgbe_mac_82599EB: 3045 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3046 break; 3047 case ixgbe_mac_X540: 3048 case ixgbe_mac_X550: 3049 case ixgbe_mac_X550EM_x: 3050 case ixgbe_mac_x550em_a: 3051 mask |= IXGBE_EIMS_TS; 3052 break; 3053 default: 3054 break; 3055 } 3056 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3057 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3058 switch (adapter->hw.mac.type) { 3059 case ixgbe_mac_82599EB: 3060 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3061 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3062 /* fall through */ 3063 case ixgbe_mac_X540: 3064 case ixgbe_mac_X550: 3065 case ixgbe_mac_X550EM_x: 3066 case ixgbe_mac_x550em_a: 3067 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3068 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3069 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3070 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3071 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3072 mask |= IXGBE_EICR_GPI_SDP0_X540; 3073 mask |= IXGBE_EIMS_ECC; 3074 mask |= IXGBE_EIMS_MAILBOX; 3075 break; 3076 default: 3077 break; 3078 } 3079 3080 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3081 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3082 mask |= IXGBE_EIMS_FLOW_DIR; 3083 3084 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3085 if (queues) 3086 ixgbe_irq_enable_queues(adapter, ~0); 3087 if (flush) 3088 IXGBE_WRITE_FLUSH(&adapter->hw); 3089 } 3090 3091 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3092 { 3093 struct ixgbe_adapter *adapter = data; 3094 struct ixgbe_hw *hw = &adapter->hw; 3095 u32 eicr; 3096 3097 /* 3098 * Workaround for Silicon errata. Use clear-by-write instead 3099 * of clear-by-read. Reading with EICS will return the 3100 * interrupt causes without clearing, which later be done 3101 * with the write to EICR. 3102 */ 3103 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3104 3105 /* The lower 16bits of the EICR register are for the queue interrupts 3106 * which should be masked here in order to not accidentally clear them if 3107 * the bits are high when ixgbe_msix_other is called. There is a race 3108 * condition otherwise which results in possible performance loss 3109 * especially if the ixgbe_msix_other interrupt is triggering 3110 * consistently (as it would when PPS is turned on for the X540 device) 3111 */ 3112 eicr &= 0xFFFF0000; 3113 3114 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3115 3116 if (eicr & IXGBE_EICR_LSC) 3117 ixgbe_check_lsc(adapter); 3118 3119 if (eicr & IXGBE_EICR_MAILBOX) 3120 ixgbe_msg_task(adapter); 3121 3122 switch (hw->mac.type) { 3123 case ixgbe_mac_82599EB: 3124 case ixgbe_mac_X540: 3125 case ixgbe_mac_X550: 3126 case ixgbe_mac_X550EM_x: 3127 case ixgbe_mac_x550em_a: 3128 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3129 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3130 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3131 ixgbe_service_event_schedule(adapter); 3132 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3133 IXGBE_EICR_GPI_SDP0_X540); 3134 } 3135 if (eicr & IXGBE_EICR_ECC) { 3136 e_info(link, "Received ECC Err, initiating reset\n"); 3137 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3138 ixgbe_service_event_schedule(adapter); 3139 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3140 } 3141 /* Handle Flow Director Full threshold interrupt */ 3142 if (eicr & IXGBE_EICR_FLOW_DIR) { 3143 int reinit_count = 0; 3144 int i; 3145 for (i = 0; i < adapter->num_tx_queues; i++) { 3146 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3147 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3148 &ring->state)) 3149 reinit_count++; 3150 } 3151 if (reinit_count) { 3152 /* no more flow director interrupts until after init */ 3153 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3154 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3155 ixgbe_service_event_schedule(adapter); 3156 } 3157 } 3158 ixgbe_check_sfp_event(adapter, eicr); 3159 ixgbe_check_overtemp_event(adapter, eicr); 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 ixgbe_check_fan_failure(adapter, eicr); 3166 3167 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3168 ixgbe_ptp_check_pps_event(adapter); 3169 3170 /* re-enable the original interrupt state, no lsc, no queues */ 3171 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3172 ixgbe_irq_enable(adapter, false, false); 3173 3174 return IRQ_HANDLED; 3175 } 3176 3177 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3178 { 3179 struct ixgbe_q_vector *q_vector = data; 3180 3181 /* EIAM disabled interrupts (on this vector) for us */ 3182 3183 if (q_vector->rx.ring || q_vector->tx.ring) 3184 napi_schedule_irqoff(&q_vector->napi); 3185 3186 return IRQ_HANDLED; 3187 } 3188 3189 /** 3190 * ixgbe_poll - NAPI Rx polling callback 3191 * @napi: structure for representing this polling device 3192 * @budget: how many packets driver is allowed to clean 3193 * 3194 * This function is used for legacy and MSI, NAPI mode 3195 **/ 3196 int ixgbe_poll(struct napi_struct *napi, int budget) 3197 { 3198 struct ixgbe_q_vector *q_vector = 3199 container_of(napi, struct ixgbe_q_vector, napi); 3200 struct ixgbe_adapter *adapter = q_vector->adapter; 3201 struct ixgbe_ring *ring; 3202 int per_ring_budget, work_done = 0; 3203 bool clean_complete = true; 3204 3205 #ifdef CONFIG_IXGBE_DCA 3206 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3207 ixgbe_update_dca(q_vector); 3208 #endif 3209 3210 ixgbe_for_each_ring(ring, q_vector->tx) { 3211 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3212 clean_complete = false; 3213 } 3214 3215 /* Exit if we are called by netpoll */ 3216 if (budget <= 0) 3217 return budget; 3218 3219 /* attempt to distribute budget to each queue fairly, but don't allow 3220 * the budget to go below 1 because we'll exit polling */ 3221 if (q_vector->rx.count > 1) 3222 per_ring_budget = max(budget/q_vector->rx.count, 1); 3223 else 3224 per_ring_budget = budget; 3225 3226 ixgbe_for_each_ring(ring, q_vector->rx) { 3227 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3228 per_ring_budget); 3229 3230 work_done += cleaned; 3231 if (cleaned >= per_ring_budget) 3232 clean_complete = false; 3233 } 3234 3235 /* If all work not completed, return budget and keep polling */ 3236 if (!clean_complete) 3237 return budget; 3238 3239 /* all work done, exit the polling mode */ 3240 napi_complete_done(napi, work_done); 3241 if (adapter->rx_itr_setting & 1) 3242 ixgbe_set_itr(q_vector); 3243 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3244 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3245 3246 return min(work_done, budget - 1); 3247 } 3248 3249 /** 3250 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3251 * @adapter: board private structure 3252 * 3253 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3254 * interrupts from the kernel. 3255 **/ 3256 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3257 { 3258 struct net_device *netdev = adapter->netdev; 3259 unsigned int ri = 0, ti = 0; 3260 int vector, err; 3261 3262 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3263 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3264 struct msix_entry *entry = &adapter->msix_entries[vector]; 3265 3266 if (q_vector->tx.ring && q_vector->rx.ring) { 3267 snprintf(q_vector->name, sizeof(q_vector->name), 3268 "%s-TxRx-%u", netdev->name, ri++); 3269 ti++; 3270 } else if (q_vector->rx.ring) { 3271 snprintf(q_vector->name, sizeof(q_vector->name), 3272 "%s-rx-%u", netdev->name, ri++); 3273 } else if (q_vector->tx.ring) { 3274 snprintf(q_vector->name, sizeof(q_vector->name), 3275 "%s-tx-%u", netdev->name, ti++); 3276 } else { 3277 /* skip this unused q_vector */ 3278 continue; 3279 } 3280 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3281 q_vector->name, q_vector); 3282 if (err) { 3283 e_err(probe, "request_irq failed for MSIX interrupt " 3284 "Error: %d\n", err); 3285 goto free_queue_irqs; 3286 } 3287 /* If Flow Director is enabled, set interrupt affinity */ 3288 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3289 /* assign the mask for this irq */ 3290 irq_set_affinity_hint(entry->vector, 3291 &q_vector->affinity_mask); 3292 } 3293 } 3294 3295 err = request_irq(adapter->msix_entries[vector].vector, 3296 ixgbe_msix_other, 0, netdev->name, adapter); 3297 if (err) { 3298 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3299 goto free_queue_irqs; 3300 } 3301 3302 return 0; 3303 3304 free_queue_irqs: 3305 while (vector) { 3306 vector--; 3307 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3308 NULL); 3309 free_irq(adapter->msix_entries[vector].vector, 3310 adapter->q_vector[vector]); 3311 } 3312 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3313 pci_disable_msix(adapter->pdev); 3314 kfree(adapter->msix_entries); 3315 adapter->msix_entries = NULL; 3316 return err; 3317 } 3318 3319 /** 3320 * ixgbe_intr - legacy mode Interrupt Handler 3321 * @irq: interrupt number 3322 * @data: pointer to a network interface device structure 3323 **/ 3324 static irqreturn_t ixgbe_intr(int irq, void *data) 3325 { 3326 struct ixgbe_adapter *adapter = data; 3327 struct ixgbe_hw *hw = &adapter->hw; 3328 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3329 u32 eicr; 3330 3331 /* 3332 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3333 * before the read of EICR. 3334 */ 3335 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3336 3337 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3338 * therefore no explicit interrupt disable is necessary */ 3339 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3340 if (!eicr) { 3341 /* 3342 * shared interrupt alert! 3343 * make sure interrupts are enabled because the read will 3344 * have disabled interrupts due to EIAM 3345 * finish the workaround of silicon errata on 82598. Unmask 3346 * the interrupt that we masked before the EICR read. 3347 */ 3348 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3349 ixgbe_irq_enable(adapter, true, true); 3350 return IRQ_NONE; /* Not our interrupt */ 3351 } 3352 3353 if (eicr & IXGBE_EICR_LSC) 3354 ixgbe_check_lsc(adapter); 3355 3356 switch (hw->mac.type) { 3357 case ixgbe_mac_82599EB: 3358 ixgbe_check_sfp_event(adapter, eicr); 3359 /* Fall through */ 3360 case ixgbe_mac_X540: 3361 case ixgbe_mac_X550: 3362 case ixgbe_mac_X550EM_x: 3363 case ixgbe_mac_x550em_a: 3364 if (eicr & IXGBE_EICR_ECC) { 3365 e_info(link, "Received ECC Err, initiating reset\n"); 3366 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3367 ixgbe_service_event_schedule(adapter); 3368 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3369 } 3370 ixgbe_check_overtemp_event(adapter, eicr); 3371 break; 3372 default: 3373 break; 3374 } 3375 3376 ixgbe_check_fan_failure(adapter, eicr); 3377 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3378 ixgbe_ptp_check_pps_event(adapter); 3379 3380 /* would disable interrupts here but EIAM disabled it */ 3381 napi_schedule_irqoff(&q_vector->napi); 3382 3383 /* 3384 * re-enable link(maybe) and non-queue interrupts, no flush. 3385 * ixgbe_poll will re-enable the queue interrupts 3386 */ 3387 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3388 ixgbe_irq_enable(adapter, false, false); 3389 3390 return IRQ_HANDLED; 3391 } 3392 3393 /** 3394 * ixgbe_request_irq - initialize interrupts 3395 * @adapter: board private structure 3396 * 3397 * Attempts to configure interrupts using the best available 3398 * capabilities of the hardware and kernel. 3399 **/ 3400 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3401 { 3402 struct net_device *netdev = adapter->netdev; 3403 int err; 3404 3405 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3406 err = ixgbe_request_msix_irqs(adapter); 3407 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3408 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3409 netdev->name, adapter); 3410 else 3411 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3412 netdev->name, adapter); 3413 3414 if (err) 3415 e_err(probe, "request_irq failed, Error %d\n", err); 3416 3417 return err; 3418 } 3419 3420 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3421 { 3422 int vector; 3423 3424 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3425 free_irq(adapter->pdev->irq, adapter); 3426 return; 3427 } 3428 3429 if (!adapter->msix_entries) 3430 return; 3431 3432 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3433 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3434 struct msix_entry *entry = &adapter->msix_entries[vector]; 3435 3436 /* free only the irqs that were actually requested */ 3437 if (!q_vector->rx.ring && !q_vector->tx.ring) 3438 continue; 3439 3440 /* clear the affinity_mask in the IRQ descriptor */ 3441 irq_set_affinity_hint(entry->vector, NULL); 3442 3443 free_irq(entry->vector, q_vector); 3444 } 3445 3446 free_irq(adapter->msix_entries[vector].vector, adapter); 3447 } 3448 3449 /** 3450 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3451 * @adapter: board private structure 3452 **/ 3453 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3454 { 3455 switch (adapter->hw.mac.type) { 3456 case ixgbe_mac_82598EB: 3457 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3458 break; 3459 case ixgbe_mac_82599EB: 3460 case ixgbe_mac_X540: 3461 case ixgbe_mac_X550: 3462 case ixgbe_mac_X550EM_x: 3463 case ixgbe_mac_x550em_a: 3464 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3467 break; 3468 default: 3469 break; 3470 } 3471 IXGBE_WRITE_FLUSH(&adapter->hw); 3472 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3473 int vector; 3474 3475 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3476 synchronize_irq(adapter->msix_entries[vector].vector); 3477 3478 synchronize_irq(adapter->msix_entries[vector++].vector); 3479 } else { 3480 synchronize_irq(adapter->pdev->irq); 3481 } 3482 } 3483 3484 /** 3485 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3486 * @adapter: board private structure 3487 * 3488 **/ 3489 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3490 { 3491 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3492 3493 ixgbe_write_eitr(q_vector); 3494 3495 ixgbe_set_ivar(adapter, 0, 0, 0); 3496 ixgbe_set_ivar(adapter, 1, 0, 0); 3497 3498 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3499 } 3500 3501 /** 3502 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3503 * @adapter: board private structure 3504 * @ring: structure containing ring specific data 3505 * 3506 * Configure the Tx descriptor ring after a reset. 3507 **/ 3508 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3509 struct ixgbe_ring *ring) 3510 { 3511 struct ixgbe_hw *hw = &adapter->hw; 3512 u64 tdba = ring->dma; 3513 int wait_loop = 10; 3514 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3515 u8 reg_idx = ring->reg_idx; 3516 3517 /* disable queue to avoid issues while updating state */ 3518 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3519 IXGBE_WRITE_FLUSH(hw); 3520 3521 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3522 (tdba & DMA_BIT_MASK(32))); 3523 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3524 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3525 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3526 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3527 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3528 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3529 3530 /* 3531 * set WTHRESH to encourage burst writeback, it should not be set 3532 * higher than 1 when: 3533 * - ITR is 0 as it could cause false TX hangs 3534 * - ITR is set to > 100k int/sec and BQL is enabled 3535 * 3536 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3537 * to or less than the number of on chip descriptors, which is 3538 * currently 40. 3539 */ 3540 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3541 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3542 else 3543 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3544 3545 /* 3546 * Setting PTHRESH to 32 both improves performance 3547 * and avoids a TX hang with DFP enabled 3548 */ 3549 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3550 32; /* PTHRESH = 32 */ 3551 3552 /* reinitialize flowdirector state */ 3553 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3554 ring->atr_sample_rate = adapter->atr_sample_rate; 3555 ring->atr_count = 0; 3556 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3557 } else { 3558 ring->atr_sample_rate = 0; 3559 } 3560 3561 /* initialize XPS */ 3562 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3563 struct ixgbe_q_vector *q_vector = ring->q_vector; 3564 3565 if (q_vector) 3566 netif_set_xps_queue(ring->netdev, 3567 &q_vector->affinity_mask, 3568 ring->queue_index); 3569 } 3570 3571 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3572 3573 /* reinitialize tx_buffer_info */ 3574 memset(ring->tx_buffer_info, 0, 3575 sizeof(struct ixgbe_tx_buffer) * ring->count); 3576 3577 /* enable queue */ 3578 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3579 3580 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3581 if (hw->mac.type == ixgbe_mac_82598EB && 3582 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3583 return; 3584 3585 /* poll to verify queue is enabled */ 3586 do { 3587 usleep_range(1000, 2000); 3588 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3589 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3590 if (!wait_loop) 3591 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3592 } 3593 3594 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3595 { 3596 struct ixgbe_hw *hw = &adapter->hw; 3597 u32 rttdcs, mtqc; 3598 u8 tcs = adapter->hw_tcs; 3599 3600 if (hw->mac.type == ixgbe_mac_82598EB) 3601 return; 3602 3603 /* disable the arbiter while setting MTQC */ 3604 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3605 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3606 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3607 3608 /* set transmit pool layout */ 3609 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3610 mtqc = IXGBE_MTQC_VT_ENA; 3611 if (tcs > 4) 3612 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3613 else if (tcs > 1) 3614 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3615 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3616 IXGBE_82599_VMDQ_4Q_MASK) 3617 mtqc |= IXGBE_MTQC_32VF; 3618 else 3619 mtqc |= IXGBE_MTQC_64VF; 3620 } else { 3621 if (tcs > 4) 3622 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3623 else if (tcs > 1) 3624 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3625 else 3626 mtqc = IXGBE_MTQC_64Q_1PB; 3627 } 3628 3629 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3630 3631 /* Enable Security TX Buffer IFG for multiple pb */ 3632 if (tcs) { 3633 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3634 sectx |= IXGBE_SECTX_DCB; 3635 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3636 } 3637 3638 /* re-enable the arbiter */ 3639 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3640 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3641 } 3642 3643 /** 3644 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3645 * @adapter: board private structure 3646 * 3647 * Configure the Tx unit of the MAC after a reset. 3648 **/ 3649 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3650 { 3651 struct ixgbe_hw *hw = &adapter->hw; 3652 u32 dmatxctl; 3653 u32 i; 3654 3655 ixgbe_setup_mtqc(adapter); 3656 3657 if (hw->mac.type != ixgbe_mac_82598EB) { 3658 /* DMATXCTL.EN must be before Tx queues are enabled */ 3659 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3660 dmatxctl |= IXGBE_DMATXCTL_TE; 3661 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3662 } 3663 3664 /* Setup the HW Tx Head and Tail descriptor pointers */ 3665 for (i = 0; i < adapter->num_tx_queues; i++) 3666 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3667 for (i = 0; i < adapter->num_xdp_queues; i++) 3668 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3669 } 3670 3671 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3672 struct ixgbe_ring *ring) 3673 { 3674 struct ixgbe_hw *hw = &adapter->hw; 3675 u8 reg_idx = ring->reg_idx; 3676 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3677 3678 srrctl |= IXGBE_SRRCTL_DROP_EN; 3679 3680 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3681 } 3682 3683 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3684 struct ixgbe_ring *ring) 3685 { 3686 struct ixgbe_hw *hw = &adapter->hw; 3687 u8 reg_idx = ring->reg_idx; 3688 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3689 3690 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3691 3692 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3693 } 3694 3695 #ifdef CONFIG_IXGBE_DCB 3696 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3697 #else 3698 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3699 #endif 3700 { 3701 int i; 3702 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3703 3704 if (adapter->ixgbe_ieee_pfc) 3705 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3706 3707 /* 3708 * We should set the drop enable bit if: 3709 * SR-IOV is enabled 3710 * or 3711 * Number of Rx queues > 1 and flow control is disabled 3712 * 3713 * This allows us to avoid head of line blocking for security 3714 * and performance reasons. 3715 */ 3716 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3717 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3718 for (i = 0; i < adapter->num_rx_queues; i++) 3719 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3720 } else { 3721 for (i = 0; i < adapter->num_rx_queues; i++) 3722 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3723 } 3724 } 3725 3726 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3727 3728 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3729 struct ixgbe_ring *rx_ring) 3730 { 3731 struct ixgbe_hw *hw = &adapter->hw; 3732 u32 srrctl; 3733 u8 reg_idx = rx_ring->reg_idx; 3734 3735 if (hw->mac.type == ixgbe_mac_82598EB) { 3736 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3737 3738 /* 3739 * if VMDq is not active we must program one srrctl register 3740 * per RSS queue since we have enabled RDRXCTL.MVMEN 3741 */ 3742 reg_idx &= mask; 3743 } 3744 3745 /* configure header buffer length, needed for RSC */ 3746 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3747 3748 /* configure the packet buffer length */ 3749 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3750 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3751 else 3752 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3753 3754 /* configure descriptor type */ 3755 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3756 3757 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3758 } 3759 3760 /** 3761 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3762 * @adapter: device handle 3763 * 3764 * - 82598/82599/X540: 128 3765 * - X550(non-SRIOV mode): 512 3766 * - X550(SRIOV mode): 64 3767 */ 3768 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3769 { 3770 if (adapter->hw.mac.type < ixgbe_mac_X550) 3771 return 128; 3772 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3773 return 64; 3774 else 3775 return 512; 3776 } 3777 3778 /** 3779 * ixgbe_store_key - Write the RSS key to HW 3780 * @adapter: device handle 3781 * 3782 * Write the RSS key stored in adapter.rss_key to HW. 3783 */ 3784 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3785 { 3786 struct ixgbe_hw *hw = &adapter->hw; 3787 int i; 3788 3789 for (i = 0; i < 10; i++) 3790 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3791 } 3792 3793 /** 3794 * ixgbe_init_rss_key - Initialize adapter RSS key 3795 * @adapter: device handle 3796 * 3797 * Allocates and initializes the RSS key if it is not allocated. 3798 **/ 3799 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3800 { 3801 u32 *rss_key; 3802 3803 if (!adapter->rss_key) { 3804 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3805 if (unlikely(!rss_key)) 3806 return -ENOMEM; 3807 3808 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3809 adapter->rss_key = rss_key; 3810 } 3811 3812 return 0; 3813 } 3814 3815 /** 3816 * ixgbe_store_reta - Write the RETA table to HW 3817 * @adapter: device handle 3818 * 3819 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3820 */ 3821 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3822 { 3823 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3824 struct ixgbe_hw *hw = &adapter->hw; 3825 u32 reta = 0; 3826 u32 indices_multi; 3827 u8 *indir_tbl = adapter->rss_indir_tbl; 3828 3829 /* Fill out the redirection table as follows: 3830 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3831 * indices. 3832 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3833 * - X550: 8 bit wide entries containing 6 bit RSS index 3834 */ 3835 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3836 indices_multi = 0x11; 3837 else 3838 indices_multi = 0x1; 3839 3840 /* Write redirection table to HW */ 3841 for (i = 0; i < reta_entries; i++) { 3842 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3843 if ((i & 3) == 3) { 3844 if (i < 128) 3845 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3846 else 3847 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3848 reta); 3849 reta = 0; 3850 } 3851 } 3852 } 3853 3854 /** 3855 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3856 * @adapter: device handle 3857 * 3858 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3859 */ 3860 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3861 { 3862 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3863 struct ixgbe_hw *hw = &adapter->hw; 3864 u32 vfreta = 0; 3865 3866 /* Write redirection table to HW */ 3867 for (i = 0; i < reta_entries; i++) { 3868 u16 pool = adapter->num_rx_pools; 3869 3870 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3871 if ((i & 3) != 3) 3872 continue; 3873 3874 while (pool--) 3875 IXGBE_WRITE_REG(hw, 3876 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3877 vfreta); 3878 vfreta = 0; 3879 } 3880 } 3881 3882 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3883 { 3884 u32 i, j; 3885 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3886 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3887 3888 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3889 * make full use of any rings they may have. We will use the 3890 * PSRTYPE register to control how many rings we use within the PF. 3891 */ 3892 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3893 rss_i = 4; 3894 3895 /* Fill out hash function seeds */ 3896 ixgbe_store_key(adapter); 3897 3898 /* Fill out redirection table */ 3899 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3900 3901 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3902 if (j == rss_i) 3903 j = 0; 3904 3905 adapter->rss_indir_tbl[i] = j; 3906 } 3907 3908 ixgbe_store_reta(adapter); 3909 } 3910 3911 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3912 { 3913 struct ixgbe_hw *hw = &adapter->hw; 3914 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3915 int i, j; 3916 3917 /* Fill out hash function seeds */ 3918 for (i = 0; i < 10; i++) { 3919 u16 pool = adapter->num_rx_pools; 3920 3921 while (pool--) 3922 IXGBE_WRITE_REG(hw, 3923 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3924 *(adapter->rss_key + i)); 3925 } 3926 3927 /* Fill out the redirection table */ 3928 for (i = 0, j = 0; i < 64; i++, j++) { 3929 if (j == rss_i) 3930 j = 0; 3931 3932 adapter->rss_indir_tbl[i] = j; 3933 } 3934 3935 ixgbe_store_vfreta(adapter); 3936 } 3937 3938 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3939 { 3940 struct ixgbe_hw *hw = &adapter->hw; 3941 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3942 u32 rxcsum; 3943 3944 /* Disable indicating checksum in descriptor, enables RSS hash */ 3945 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3946 rxcsum |= IXGBE_RXCSUM_PCSD; 3947 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3948 3949 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3950 if (adapter->ring_feature[RING_F_RSS].mask) 3951 mrqc = IXGBE_MRQC_RSSEN; 3952 } else { 3953 u8 tcs = adapter->hw_tcs; 3954 3955 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3956 if (tcs > 4) 3957 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3958 else if (tcs > 1) 3959 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3960 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3961 IXGBE_82599_VMDQ_4Q_MASK) 3962 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3963 else 3964 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3965 3966 /* Enable L3/L4 for Tx Switched packets */ 3967 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3968 } else { 3969 if (tcs > 4) 3970 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3971 else if (tcs > 1) 3972 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3973 else 3974 mrqc = IXGBE_MRQC_RSSEN; 3975 } 3976 } 3977 3978 /* Perform hash on these packet types */ 3979 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3980 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3981 IXGBE_MRQC_RSS_FIELD_IPV6 | 3982 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3983 3984 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3985 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3986 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3987 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3988 3989 if ((hw->mac.type >= ixgbe_mac_X550) && 3990 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3991 u16 pool = adapter->num_rx_pools; 3992 3993 /* Enable VF RSS mode */ 3994 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3995 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3996 3997 /* Setup RSS through the VF registers */ 3998 ixgbe_setup_vfreta(adapter); 3999 vfmrqc = IXGBE_MRQC_RSSEN; 4000 vfmrqc |= rss_field; 4001 4002 while (pool--) 4003 IXGBE_WRITE_REG(hw, 4004 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4005 vfmrqc); 4006 } else { 4007 ixgbe_setup_reta(adapter); 4008 mrqc |= rss_field; 4009 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4010 } 4011 } 4012 4013 /** 4014 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4015 * @adapter: address of board private structure 4016 * @ring: structure containing ring specific data 4017 **/ 4018 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4019 struct ixgbe_ring *ring) 4020 { 4021 struct ixgbe_hw *hw = &adapter->hw; 4022 u32 rscctrl; 4023 u8 reg_idx = ring->reg_idx; 4024 4025 if (!ring_is_rsc_enabled(ring)) 4026 return; 4027 4028 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4029 rscctrl |= IXGBE_RSCCTL_RSCEN; 4030 /* 4031 * we must limit the number of descriptors so that the 4032 * total size of max desc * buf_len is not greater 4033 * than 65536 4034 */ 4035 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4036 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4037 } 4038 4039 #define IXGBE_MAX_RX_DESC_POLL 10 4040 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4041 struct ixgbe_ring *ring) 4042 { 4043 struct ixgbe_hw *hw = &adapter->hw; 4044 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4045 u32 rxdctl; 4046 u8 reg_idx = ring->reg_idx; 4047 4048 if (ixgbe_removed(hw->hw_addr)) 4049 return; 4050 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4051 if (hw->mac.type == ixgbe_mac_82598EB && 4052 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4053 return; 4054 4055 do { 4056 usleep_range(1000, 2000); 4057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4058 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4059 4060 if (!wait_loop) { 4061 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4062 "the polling period\n", reg_idx); 4063 } 4064 } 4065 4066 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 4067 struct ixgbe_ring *ring) 4068 { 4069 struct ixgbe_hw *hw = &adapter->hw; 4070 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4071 u32 rxdctl; 4072 u8 reg_idx = ring->reg_idx; 4073 4074 if (ixgbe_removed(hw->hw_addr)) 4075 return; 4076 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4077 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4078 4079 /* write value back with RXDCTL.ENABLE bit cleared */ 4080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4081 4082 if (hw->mac.type == ixgbe_mac_82598EB && 4083 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4084 return; 4085 4086 /* the hardware may take up to 100us to really disable the rx queue */ 4087 do { 4088 udelay(10); 4089 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4090 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 4091 4092 if (!wait_loop) { 4093 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 4094 "the polling period\n", reg_idx); 4095 } 4096 } 4097 4098 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4099 struct ixgbe_ring *ring) 4100 { 4101 struct ixgbe_hw *hw = &adapter->hw; 4102 union ixgbe_adv_rx_desc *rx_desc; 4103 u64 rdba = ring->dma; 4104 u32 rxdctl; 4105 u8 reg_idx = ring->reg_idx; 4106 4107 /* disable queue to avoid issues while updating state */ 4108 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4109 ixgbe_disable_rx_queue(adapter, ring); 4110 4111 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4112 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4113 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4114 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4115 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4116 IXGBE_WRITE_FLUSH(hw); 4117 4118 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4119 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4120 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4121 4122 ixgbe_configure_srrctl(adapter, ring); 4123 ixgbe_configure_rscctl(adapter, ring); 4124 4125 if (hw->mac.type == ixgbe_mac_82598EB) { 4126 /* 4127 * enable cache line friendly hardware writes: 4128 * PTHRESH=32 descriptors (half the internal cache), 4129 * this also removes ugly rx_no_buffer_count increment 4130 * HTHRESH=4 descriptors (to minimize latency on fetch) 4131 * WTHRESH=8 burst writeback up to two cache lines 4132 */ 4133 rxdctl &= ~0x3FFFFF; 4134 rxdctl |= 0x080420; 4135 #if (PAGE_SIZE < 8192) 4136 /* RXDCTL.RLPML does not work on 82599 */ 4137 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4138 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4139 IXGBE_RXDCTL_RLPML_EN); 4140 4141 /* Limit the maximum frame size so we don't overrun the skb. 4142 * This can happen in SRIOV mode when the MTU of the VF is 4143 * higher than the MTU of the PF. 4144 */ 4145 if (ring_uses_build_skb(ring) && 4146 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4147 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4148 IXGBE_RXDCTL_RLPML_EN; 4149 #endif 4150 } 4151 4152 /* initialize rx_buffer_info */ 4153 memset(ring->rx_buffer_info, 0, 4154 sizeof(struct ixgbe_rx_buffer) * ring->count); 4155 4156 /* initialize Rx descriptor 0 */ 4157 rx_desc = IXGBE_RX_DESC(ring, 0); 4158 rx_desc->wb.upper.length = 0; 4159 4160 /* enable receive descriptor ring */ 4161 rxdctl |= IXGBE_RXDCTL_ENABLE; 4162 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4163 4164 ixgbe_rx_desc_queue_enable(adapter, ring); 4165 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4166 } 4167 4168 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4169 { 4170 struct ixgbe_hw *hw = &adapter->hw; 4171 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4172 u16 pool = adapter->num_rx_pools; 4173 4174 /* PSRTYPE must be initialized in non 82598 adapters */ 4175 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4176 IXGBE_PSRTYPE_UDPHDR | 4177 IXGBE_PSRTYPE_IPV4HDR | 4178 IXGBE_PSRTYPE_L2HDR | 4179 IXGBE_PSRTYPE_IPV6HDR; 4180 4181 if (hw->mac.type == ixgbe_mac_82598EB) 4182 return; 4183 4184 if (rss_i > 3) 4185 psrtype |= 2u << 29; 4186 else if (rss_i > 1) 4187 psrtype |= 1u << 29; 4188 4189 while (pool--) 4190 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4191 } 4192 4193 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4194 { 4195 struct ixgbe_hw *hw = &adapter->hw; 4196 u16 pool = adapter->num_rx_pools; 4197 u32 reg_offset, vf_shift, vmolr; 4198 u32 gcr_ext, vmdctl; 4199 int i; 4200 4201 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4202 return; 4203 4204 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4205 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4206 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4207 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4208 vmdctl |= IXGBE_VT_CTL_REPLEN; 4209 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4210 4211 /* accept untagged packets until a vlan tag is 4212 * specifically set for the VMDQ queue/pool 4213 */ 4214 vmolr = IXGBE_VMOLR_AUPE; 4215 while (pool--) 4216 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4217 4218 vf_shift = VMDQ_P(0) % 32; 4219 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4220 4221 /* Enable only the PF's pool for Tx/Rx */ 4222 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4223 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4224 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4225 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4226 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4227 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4228 4229 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4230 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4231 4232 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4233 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4234 4235 /* 4236 * Set up VF register offsets for selected VT Mode, 4237 * i.e. 32 or 64 VFs for SR-IOV 4238 */ 4239 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4240 case IXGBE_82599_VMDQ_8Q_MASK: 4241 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4242 break; 4243 case IXGBE_82599_VMDQ_4Q_MASK: 4244 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4245 break; 4246 default: 4247 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4248 break; 4249 } 4250 4251 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4252 4253 for (i = 0; i < adapter->num_vfs; i++) { 4254 /* configure spoof checking */ 4255 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4256 adapter->vfinfo[i].spoofchk_enabled); 4257 4258 /* Enable/Disable RSS query feature */ 4259 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4260 adapter->vfinfo[i].rss_query_enabled); 4261 } 4262 } 4263 4264 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4265 { 4266 struct ixgbe_hw *hw = &adapter->hw; 4267 struct net_device *netdev = adapter->netdev; 4268 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4269 struct ixgbe_ring *rx_ring; 4270 int i; 4271 u32 mhadd, hlreg0; 4272 4273 #ifdef IXGBE_FCOE 4274 /* adjust max frame to be able to do baby jumbo for FCoE */ 4275 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4276 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4277 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4278 4279 #endif /* IXGBE_FCOE */ 4280 4281 /* adjust max frame to be at least the size of a standard frame */ 4282 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4283 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4284 4285 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4286 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4287 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4288 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4289 4290 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4291 } 4292 4293 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4294 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4295 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4296 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4297 4298 /* 4299 * Setup the HW Rx Head and Tail Descriptor Pointers and 4300 * the Base and Length of the Rx Descriptor Ring 4301 */ 4302 for (i = 0; i < adapter->num_rx_queues; i++) { 4303 rx_ring = adapter->rx_ring[i]; 4304 4305 clear_ring_rsc_enabled(rx_ring); 4306 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4307 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4308 4309 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4310 set_ring_rsc_enabled(rx_ring); 4311 4312 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4313 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4314 4315 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4316 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4317 continue; 4318 4319 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4320 4321 #if (PAGE_SIZE < 8192) 4322 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4323 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4324 4325 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4326 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4327 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4328 #endif 4329 } 4330 } 4331 4332 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4333 { 4334 struct ixgbe_hw *hw = &adapter->hw; 4335 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4336 4337 switch (hw->mac.type) { 4338 case ixgbe_mac_82598EB: 4339 /* 4340 * For VMDq support of different descriptor types or 4341 * buffer sizes through the use of multiple SRRCTL 4342 * registers, RDRXCTL.MVMEN must be set to 1 4343 * 4344 * also, the manual doesn't mention it clearly but DCA hints 4345 * will only use queue 0's tags unless this bit is set. Side 4346 * effects of setting this bit are only that SRRCTL must be 4347 * fully programmed [0..15] 4348 */ 4349 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4350 break; 4351 case ixgbe_mac_X550: 4352 case ixgbe_mac_X550EM_x: 4353 case ixgbe_mac_x550em_a: 4354 if (adapter->num_vfs) 4355 rdrxctl |= IXGBE_RDRXCTL_PSP; 4356 /* fall through */ 4357 case ixgbe_mac_82599EB: 4358 case ixgbe_mac_X540: 4359 /* Disable RSC for ACK packets */ 4360 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4361 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4362 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4363 /* hardware requires some bits to be set by default */ 4364 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4365 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4366 break; 4367 default: 4368 /* We should do nothing since we don't know this hardware */ 4369 return; 4370 } 4371 4372 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4373 } 4374 4375 /** 4376 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4377 * @adapter: board private structure 4378 * 4379 * Configure the Rx unit of the MAC after a reset. 4380 **/ 4381 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4382 { 4383 struct ixgbe_hw *hw = &adapter->hw; 4384 int i; 4385 u32 rxctrl, rfctl; 4386 4387 /* disable receives while setting up the descriptors */ 4388 hw->mac.ops.disable_rx(hw); 4389 4390 ixgbe_setup_psrtype(adapter); 4391 ixgbe_setup_rdrxctl(adapter); 4392 4393 /* RSC Setup */ 4394 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4395 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4396 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4397 rfctl |= IXGBE_RFCTL_RSC_DIS; 4398 4399 /* disable NFS filtering */ 4400 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4401 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4402 4403 /* Program registers for the distribution of queues */ 4404 ixgbe_setup_mrqc(adapter); 4405 4406 /* set_rx_buffer_len must be called before ring initialization */ 4407 ixgbe_set_rx_buffer_len(adapter); 4408 4409 /* 4410 * Setup the HW Rx Head and Tail Descriptor Pointers and 4411 * the Base and Length of the Rx Descriptor Ring 4412 */ 4413 for (i = 0; i < adapter->num_rx_queues; i++) 4414 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4415 4416 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4417 /* disable drop enable for 82598 parts */ 4418 if (hw->mac.type == ixgbe_mac_82598EB) 4419 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4420 4421 /* enable all receives */ 4422 rxctrl |= IXGBE_RXCTRL_RXEN; 4423 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4424 } 4425 4426 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4427 __be16 proto, u16 vid) 4428 { 4429 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4430 struct ixgbe_hw *hw = &adapter->hw; 4431 4432 /* add VID to filter table */ 4433 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4434 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4435 4436 set_bit(vid, adapter->active_vlans); 4437 4438 return 0; 4439 } 4440 4441 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4442 { 4443 u32 vlvf; 4444 int idx; 4445 4446 /* short cut the special case */ 4447 if (vlan == 0) 4448 return 0; 4449 4450 /* Search for the vlan id in the VLVF entries */ 4451 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4452 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4453 if ((vlvf & VLAN_VID_MASK) == vlan) 4454 break; 4455 } 4456 4457 return idx; 4458 } 4459 4460 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4461 { 4462 struct ixgbe_hw *hw = &adapter->hw; 4463 u32 bits, word; 4464 int idx; 4465 4466 idx = ixgbe_find_vlvf_entry(hw, vid); 4467 if (!idx) 4468 return; 4469 4470 /* See if any other pools are set for this VLAN filter 4471 * entry other than the PF. 4472 */ 4473 word = idx * 2 + (VMDQ_P(0) / 32); 4474 bits = ~BIT(VMDQ_P(0) % 32); 4475 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4476 4477 /* Disable the filter so this falls into the default pool. */ 4478 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4479 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4480 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4481 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4482 } 4483 } 4484 4485 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4486 __be16 proto, u16 vid) 4487 { 4488 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4489 struct ixgbe_hw *hw = &adapter->hw; 4490 4491 /* remove VID from filter table */ 4492 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4493 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4494 4495 clear_bit(vid, adapter->active_vlans); 4496 4497 return 0; 4498 } 4499 4500 /** 4501 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4502 * @adapter: driver data 4503 */ 4504 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4505 { 4506 struct ixgbe_hw *hw = &adapter->hw; 4507 u32 vlnctrl; 4508 int i, j; 4509 4510 switch (hw->mac.type) { 4511 case ixgbe_mac_82598EB: 4512 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4513 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4514 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4515 break; 4516 case ixgbe_mac_82599EB: 4517 case ixgbe_mac_X540: 4518 case ixgbe_mac_X550: 4519 case ixgbe_mac_X550EM_x: 4520 case ixgbe_mac_x550em_a: 4521 for (i = 0; i < adapter->num_rx_queues; i++) { 4522 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4523 4524 if (!netif_is_ixgbe(ring->netdev)) 4525 continue; 4526 4527 j = ring->reg_idx; 4528 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4529 vlnctrl &= ~IXGBE_RXDCTL_VME; 4530 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4531 } 4532 break; 4533 default: 4534 break; 4535 } 4536 } 4537 4538 /** 4539 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4540 * @adapter: driver data 4541 */ 4542 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4543 { 4544 struct ixgbe_hw *hw = &adapter->hw; 4545 u32 vlnctrl; 4546 int i, j; 4547 4548 switch (hw->mac.type) { 4549 case ixgbe_mac_82598EB: 4550 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4551 vlnctrl |= IXGBE_VLNCTRL_VME; 4552 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4553 break; 4554 case ixgbe_mac_82599EB: 4555 case ixgbe_mac_X540: 4556 case ixgbe_mac_X550: 4557 case ixgbe_mac_X550EM_x: 4558 case ixgbe_mac_x550em_a: 4559 for (i = 0; i < adapter->num_rx_queues; i++) { 4560 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4561 4562 if (!netif_is_ixgbe(ring->netdev)) 4563 continue; 4564 4565 j = ring->reg_idx; 4566 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4567 vlnctrl |= IXGBE_RXDCTL_VME; 4568 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4569 } 4570 break; 4571 default: 4572 break; 4573 } 4574 } 4575 4576 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4577 { 4578 struct ixgbe_hw *hw = &adapter->hw; 4579 u32 vlnctrl, i; 4580 4581 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4582 4583 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4584 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4585 vlnctrl |= IXGBE_VLNCTRL_VFE; 4586 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4587 } else { 4588 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4589 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4590 return; 4591 } 4592 4593 /* Nothing to do for 82598 */ 4594 if (hw->mac.type == ixgbe_mac_82598EB) 4595 return; 4596 4597 /* We are already in VLAN promisc, nothing to do */ 4598 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4599 return; 4600 4601 /* Set flag so we don't redo unnecessary work */ 4602 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4603 4604 /* Add PF to all active pools */ 4605 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4606 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4607 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4608 4609 vlvfb |= BIT(VMDQ_P(0) % 32); 4610 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4611 } 4612 4613 /* Set all bits in the VLAN filter table array */ 4614 for (i = hw->mac.vft_size; i--;) 4615 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4616 } 4617 4618 #define VFTA_BLOCK_SIZE 8 4619 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4620 { 4621 struct ixgbe_hw *hw = &adapter->hw; 4622 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4623 u32 vid_start = vfta_offset * 32; 4624 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4625 u32 i, vid, word, bits; 4626 4627 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4628 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4629 4630 /* pull VLAN ID from VLVF */ 4631 vid = vlvf & VLAN_VID_MASK; 4632 4633 /* only concern outselves with a certain range */ 4634 if (vid < vid_start || vid >= vid_end) 4635 continue; 4636 4637 if (vlvf) { 4638 /* record VLAN ID in VFTA */ 4639 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4640 4641 /* if PF is part of this then continue */ 4642 if (test_bit(vid, adapter->active_vlans)) 4643 continue; 4644 } 4645 4646 /* remove PF from the pool */ 4647 word = i * 2 + VMDQ_P(0) / 32; 4648 bits = ~BIT(VMDQ_P(0) % 32); 4649 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4650 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4651 } 4652 4653 /* extract values from active_vlans and write back to VFTA */ 4654 for (i = VFTA_BLOCK_SIZE; i--;) { 4655 vid = (vfta_offset + i) * 32; 4656 word = vid / BITS_PER_LONG; 4657 bits = vid % BITS_PER_LONG; 4658 4659 vfta[i] |= adapter->active_vlans[word] >> bits; 4660 4661 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4662 } 4663 } 4664 4665 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4666 { 4667 struct ixgbe_hw *hw = &adapter->hw; 4668 u32 vlnctrl, i; 4669 4670 /* Set VLAN filtering to enabled */ 4671 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4672 vlnctrl |= IXGBE_VLNCTRL_VFE; 4673 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4674 4675 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4676 hw->mac.type == ixgbe_mac_82598EB) 4677 return; 4678 4679 /* We are not in VLAN promisc, nothing to do */ 4680 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4681 return; 4682 4683 /* Set flag so we don't redo unnecessary work */ 4684 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4685 4686 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4687 ixgbe_scrub_vfta(adapter, i); 4688 } 4689 4690 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4691 { 4692 u16 vid = 1; 4693 4694 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4695 4696 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4697 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4698 } 4699 4700 /** 4701 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4702 * @netdev: network interface device structure 4703 * 4704 * Writes multicast address list to the MTA hash table. 4705 * Returns: -ENOMEM on failure 4706 * 0 on no addresses written 4707 * X on writing X addresses to MTA 4708 **/ 4709 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4710 { 4711 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4712 struct ixgbe_hw *hw = &adapter->hw; 4713 4714 if (!netif_running(netdev)) 4715 return 0; 4716 4717 if (hw->mac.ops.update_mc_addr_list) 4718 hw->mac.ops.update_mc_addr_list(hw, netdev); 4719 else 4720 return -ENOMEM; 4721 4722 #ifdef CONFIG_PCI_IOV 4723 ixgbe_restore_vf_multicasts(adapter); 4724 #endif 4725 4726 return netdev_mc_count(netdev); 4727 } 4728 4729 #ifdef CONFIG_PCI_IOV 4730 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4731 { 4732 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4733 struct ixgbe_hw *hw = &adapter->hw; 4734 int i; 4735 4736 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4737 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4738 4739 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4740 hw->mac.ops.set_rar(hw, i, 4741 mac_table->addr, 4742 mac_table->pool, 4743 IXGBE_RAH_AV); 4744 else 4745 hw->mac.ops.clear_rar(hw, i); 4746 } 4747 } 4748 4749 #endif 4750 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4751 { 4752 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4753 struct ixgbe_hw *hw = &adapter->hw; 4754 int i; 4755 4756 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4757 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4758 continue; 4759 4760 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4761 4762 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4763 hw->mac.ops.set_rar(hw, i, 4764 mac_table->addr, 4765 mac_table->pool, 4766 IXGBE_RAH_AV); 4767 else 4768 hw->mac.ops.clear_rar(hw, i); 4769 } 4770 } 4771 4772 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4773 { 4774 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4775 struct ixgbe_hw *hw = &adapter->hw; 4776 int i; 4777 4778 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4779 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4780 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4781 } 4782 4783 ixgbe_sync_mac_table(adapter); 4784 } 4785 4786 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4787 { 4788 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4789 struct ixgbe_hw *hw = &adapter->hw; 4790 int i, count = 0; 4791 4792 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4793 /* do not count default RAR as available */ 4794 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4795 continue; 4796 4797 /* only count unused and addresses that belong to us */ 4798 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4799 if (mac_table->pool != pool) 4800 continue; 4801 } 4802 4803 count++; 4804 } 4805 4806 return count; 4807 } 4808 4809 /* this function destroys the first RAR entry */ 4810 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4811 { 4812 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4813 struct ixgbe_hw *hw = &adapter->hw; 4814 4815 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4816 mac_table->pool = VMDQ_P(0); 4817 4818 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4819 4820 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4821 IXGBE_RAH_AV); 4822 } 4823 4824 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4825 const u8 *addr, u16 pool) 4826 { 4827 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4828 struct ixgbe_hw *hw = &adapter->hw; 4829 int i; 4830 4831 if (is_zero_ether_addr(addr)) 4832 return -EINVAL; 4833 4834 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4835 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4836 continue; 4837 4838 ether_addr_copy(mac_table->addr, addr); 4839 mac_table->pool = pool; 4840 4841 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4842 IXGBE_MAC_STATE_IN_USE; 4843 4844 ixgbe_sync_mac_table(adapter); 4845 4846 return i; 4847 } 4848 4849 return -ENOMEM; 4850 } 4851 4852 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4853 const u8 *addr, u16 pool) 4854 { 4855 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4856 struct ixgbe_hw *hw = &adapter->hw; 4857 int i; 4858 4859 if (is_zero_ether_addr(addr)) 4860 return -EINVAL; 4861 4862 /* search table for addr, if found clear IN_USE flag and sync */ 4863 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4864 /* we can only delete an entry if it is in use */ 4865 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4866 continue; 4867 /* we only care about entries that belong to the given pool */ 4868 if (mac_table->pool != pool) 4869 continue; 4870 /* we only care about a specific MAC address */ 4871 if (!ether_addr_equal(addr, mac_table->addr)) 4872 continue; 4873 4874 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4875 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4876 4877 ixgbe_sync_mac_table(adapter); 4878 4879 return 0; 4880 } 4881 4882 return -ENOMEM; 4883 } 4884 4885 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4886 { 4887 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4888 int ret; 4889 4890 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4891 4892 return min_t(int, ret, 0); 4893 } 4894 4895 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4896 { 4897 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4898 4899 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4900 4901 return 0; 4902 } 4903 4904 /** 4905 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4906 * @netdev: network interface device structure 4907 * 4908 * The set_rx_method entry point is called whenever the unicast/multicast 4909 * address list or the network interface flags are updated. This routine is 4910 * responsible for configuring the hardware for proper unicast, multicast and 4911 * promiscuous mode. 4912 **/ 4913 void ixgbe_set_rx_mode(struct net_device *netdev) 4914 { 4915 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4916 struct ixgbe_hw *hw = &adapter->hw; 4917 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4918 netdev_features_t features = netdev->features; 4919 int count; 4920 4921 /* Check for Promiscuous and All Multicast modes */ 4922 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4923 4924 /* set all bits that we expect to always be set */ 4925 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4926 fctrl |= IXGBE_FCTRL_BAM; 4927 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4928 fctrl |= IXGBE_FCTRL_PMCF; 4929 4930 /* clear the bits we are changing the status of */ 4931 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4932 if (netdev->flags & IFF_PROMISC) { 4933 hw->addr_ctrl.user_set_promisc = true; 4934 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4935 vmolr |= IXGBE_VMOLR_MPE; 4936 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4937 } else { 4938 if (netdev->flags & IFF_ALLMULTI) { 4939 fctrl |= IXGBE_FCTRL_MPE; 4940 vmolr |= IXGBE_VMOLR_MPE; 4941 } 4942 hw->addr_ctrl.user_set_promisc = false; 4943 } 4944 4945 /* 4946 * Write addresses to available RAR registers, if there is not 4947 * sufficient space to store all the addresses then enable 4948 * unicast promiscuous mode 4949 */ 4950 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4951 fctrl |= IXGBE_FCTRL_UPE; 4952 vmolr |= IXGBE_VMOLR_ROPE; 4953 } 4954 4955 /* Write addresses to the MTA, if the attempt fails 4956 * then we should just turn on promiscuous mode so 4957 * that we can at least receive multicast traffic 4958 */ 4959 count = ixgbe_write_mc_addr_list(netdev); 4960 if (count < 0) { 4961 fctrl |= IXGBE_FCTRL_MPE; 4962 vmolr |= IXGBE_VMOLR_MPE; 4963 } else if (count) { 4964 vmolr |= IXGBE_VMOLR_ROMPE; 4965 } 4966 4967 if (hw->mac.type != ixgbe_mac_82598EB) { 4968 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4969 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4970 IXGBE_VMOLR_ROPE); 4971 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4972 } 4973 4974 /* This is useful for sniffing bad packets. */ 4975 if (features & NETIF_F_RXALL) { 4976 /* UPE and MPE will be handled by normal PROMISC logic 4977 * in e1000e_set_rx_mode */ 4978 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4979 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4980 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4981 4982 fctrl &= ~(IXGBE_FCTRL_DPF); 4983 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4984 } 4985 4986 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4987 4988 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4989 ixgbe_vlan_strip_enable(adapter); 4990 else 4991 ixgbe_vlan_strip_disable(adapter); 4992 4993 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4994 ixgbe_vlan_promisc_disable(adapter); 4995 else 4996 ixgbe_vlan_promisc_enable(adapter); 4997 } 4998 4999 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5000 { 5001 int q_idx; 5002 5003 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5004 napi_enable(&adapter->q_vector[q_idx]->napi); 5005 } 5006 5007 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5008 { 5009 int q_idx; 5010 5011 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5012 napi_disable(&adapter->q_vector[q_idx]->napi); 5013 } 5014 5015 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5016 { 5017 struct ixgbe_hw *hw = &adapter->hw; 5018 u32 vxlanctrl; 5019 5020 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5021 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5022 return; 5023 5024 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5025 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5026 5027 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5028 adapter->vxlan_port = 0; 5029 5030 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5031 adapter->geneve_port = 0; 5032 } 5033 5034 #ifdef CONFIG_IXGBE_DCB 5035 /** 5036 * ixgbe_configure_dcb - Configure DCB hardware 5037 * @adapter: ixgbe adapter struct 5038 * 5039 * This is called by the driver on open to configure the DCB hardware. 5040 * This is also called by the gennetlink interface when reconfiguring 5041 * the DCB state. 5042 */ 5043 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5044 { 5045 struct ixgbe_hw *hw = &adapter->hw; 5046 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5047 5048 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5049 if (hw->mac.type == ixgbe_mac_82598EB) 5050 netif_set_gso_max_size(adapter->netdev, 65536); 5051 return; 5052 } 5053 5054 if (hw->mac.type == ixgbe_mac_82598EB) 5055 netif_set_gso_max_size(adapter->netdev, 32768); 5056 5057 #ifdef IXGBE_FCOE 5058 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5059 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5060 #endif 5061 5062 /* reconfigure the hardware */ 5063 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5064 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5065 DCB_TX_CONFIG); 5066 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5067 DCB_RX_CONFIG); 5068 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5069 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5070 ixgbe_dcb_hw_ets(&adapter->hw, 5071 adapter->ixgbe_ieee_ets, 5072 max_frame); 5073 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5074 adapter->ixgbe_ieee_pfc->pfc_en, 5075 adapter->ixgbe_ieee_ets->prio_tc); 5076 } 5077 5078 /* Enable RSS Hash per TC */ 5079 if (hw->mac.type != ixgbe_mac_82598EB) { 5080 u32 msb = 0; 5081 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5082 5083 while (rss_i) { 5084 msb++; 5085 rss_i >>= 1; 5086 } 5087 5088 /* write msb to all 8 TCs in one write */ 5089 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5090 } 5091 } 5092 #endif 5093 5094 /* Additional bittime to account for IXGBE framing */ 5095 #define IXGBE_ETH_FRAMING 20 5096 5097 /** 5098 * ixgbe_hpbthresh - calculate high water mark for flow control 5099 * 5100 * @adapter: board private structure to calculate for 5101 * @pb: packet buffer to calculate 5102 */ 5103 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5104 { 5105 struct ixgbe_hw *hw = &adapter->hw; 5106 struct net_device *dev = adapter->netdev; 5107 int link, tc, kb, marker; 5108 u32 dv_id, rx_pba; 5109 5110 /* Calculate max LAN frame size */ 5111 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5112 5113 #ifdef IXGBE_FCOE 5114 /* FCoE traffic class uses FCOE jumbo frames */ 5115 if ((dev->features & NETIF_F_FCOE_MTU) && 5116 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5117 (pb == ixgbe_fcoe_get_tc(adapter))) 5118 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5119 #endif 5120 5121 /* Calculate delay value for device */ 5122 switch (hw->mac.type) { 5123 case ixgbe_mac_X540: 5124 case ixgbe_mac_X550: 5125 case ixgbe_mac_X550EM_x: 5126 case ixgbe_mac_x550em_a: 5127 dv_id = IXGBE_DV_X540(link, tc); 5128 break; 5129 default: 5130 dv_id = IXGBE_DV(link, tc); 5131 break; 5132 } 5133 5134 /* Loopback switch introduces additional latency */ 5135 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5136 dv_id += IXGBE_B2BT(tc); 5137 5138 /* Delay value is calculated in bit times convert to KB */ 5139 kb = IXGBE_BT2KB(dv_id); 5140 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5141 5142 marker = rx_pba - kb; 5143 5144 /* It is possible that the packet buffer is not large enough 5145 * to provide required headroom. In this case throw an error 5146 * to user and a do the best we can. 5147 */ 5148 if (marker < 0) { 5149 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5150 "headroom to support flow control." 5151 "Decrease MTU or number of traffic classes\n", pb); 5152 marker = tc + 1; 5153 } 5154 5155 return marker; 5156 } 5157 5158 /** 5159 * ixgbe_lpbthresh - calculate low water mark for for flow control 5160 * 5161 * @adapter: board private structure to calculate for 5162 * @pb: packet buffer to calculate 5163 */ 5164 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5165 { 5166 struct ixgbe_hw *hw = &adapter->hw; 5167 struct net_device *dev = adapter->netdev; 5168 int tc; 5169 u32 dv_id; 5170 5171 /* Calculate max LAN frame size */ 5172 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5173 5174 #ifdef IXGBE_FCOE 5175 /* FCoE traffic class uses FCOE jumbo frames */ 5176 if ((dev->features & NETIF_F_FCOE_MTU) && 5177 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5178 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5179 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5180 #endif 5181 5182 /* Calculate delay value for device */ 5183 switch (hw->mac.type) { 5184 case ixgbe_mac_X540: 5185 case ixgbe_mac_X550: 5186 case ixgbe_mac_X550EM_x: 5187 case ixgbe_mac_x550em_a: 5188 dv_id = IXGBE_LOW_DV_X540(tc); 5189 break; 5190 default: 5191 dv_id = IXGBE_LOW_DV(tc); 5192 break; 5193 } 5194 5195 /* Delay value is calculated in bit times convert to KB */ 5196 return IXGBE_BT2KB(dv_id); 5197 } 5198 5199 /* 5200 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5201 */ 5202 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5203 { 5204 struct ixgbe_hw *hw = &adapter->hw; 5205 int num_tc = adapter->hw_tcs; 5206 int i; 5207 5208 if (!num_tc) 5209 num_tc = 1; 5210 5211 for (i = 0; i < num_tc; i++) { 5212 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5213 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5214 5215 /* Low water marks must not be larger than high water marks */ 5216 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5217 hw->fc.low_water[i] = 0; 5218 } 5219 5220 for (; i < MAX_TRAFFIC_CLASS; i++) 5221 hw->fc.high_water[i] = 0; 5222 } 5223 5224 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5225 { 5226 struct ixgbe_hw *hw = &adapter->hw; 5227 int hdrm; 5228 u8 tc = adapter->hw_tcs; 5229 5230 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5231 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5232 hdrm = 32 << adapter->fdir_pballoc; 5233 else 5234 hdrm = 0; 5235 5236 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5237 ixgbe_pbthresh_setup(adapter); 5238 } 5239 5240 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5241 { 5242 struct ixgbe_hw *hw = &adapter->hw; 5243 struct hlist_node *node2; 5244 struct ixgbe_fdir_filter *filter; 5245 5246 spin_lock(&adapter->fdir_perfect_lock); 5247 5248 if (!hlist_empty(&adapter->fdir_filter_list)) 5249 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5250 5251 hlist_for_each_entry_safe(filter, node2, 5252 &adapter->fdir_filter_list, fdir_node) { 5253 ixgbe_fdir_write_perfect_filter_82599(hw, 5254 &filter->filter, 5255 filter->sw_idx, 5256 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5257 IXGBE_FDIR_DROP_QUEUE : 5258 adapter->rx_ring[filter->action]->reg_idx); 5259 } 5260 5261 spin_unlock(&adapter->fdir_perfect_lock); 5262 } 5263 5264 /** 5265 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5266 * @rx_ring: ring to free buffers from 5267 **/ 5268 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5269 { 5270 u16 i = rx_ring->next_to_clean; 5271 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5272 5273 /* Free all the Rx ring sk_buffs */ 5274 while (i != rx_ring->next_to_alloc) { 5275 if (rx_buffer->skb) { 5276 struct sk_buff *skb = rx_buffer->skb; 5277 if (IXGBE_CB(skb)->page_released) 5278 dma_unmap_page_attrs(rx_ring->dev, 5279 IXGBE_CB(skb)->dma, 5280 ixgbe_rx_pg_size(rx_ring), 5281 DMA_FROM_DEVICE, 5282 IXGBE_RX_DMA_ATTR); 5283 dev_kfree_skb(skb); 5284 } 5285 5286 /* Invalidate cache lines that may have been written to by 5287 * device so that we avoid corrupting memory. 5288 */ 5289 dma_sync_single_range_for_cpu(rx_ring->dev, 5290 rx_buffer->dma, 5291 rx_buffer->page_offset, 5292 ixgbe_rx_bufsz(rx_ring), 5293 DMA_FROM_DEVICE); 5294 5295 /* free resources associated with mapping */ 5296 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5297 ixgbe_rx_pg_size(rx_ring), 5298 DMA_FROM_DEVICE, 5299 IXGBE_RX_DMA_ATTR); 5300 __page_frag_cache_drain(rx_buffer->page, 5301 rx_buffer->pagecnt_bias); 5302 5303 i++; 5304 rx_buffer++; 5305 if (i == rx_ring->count) { 5306 i = 0; 5307 rx_buffer = rx_ring->rx_buffer_info; 5308 } 5309 } 5310 5311 rx_ring->next_to_alloc = 0; 5312 rx_ring->next_to_clean = 0; 5313 rx_ring->next_to_use = 0; 5314 } 5315 5316 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5317 struct ixgbe_fwd_adapter *accel) 5318 { 5319 struct net_device *vdev = accel->netdev; 5320 int i, baseq, err; 5321 5322 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5323 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5324 accel->pool, adapter->num_rx_pools, 5325 baseq, baseq + adapter->num_rx_queues_per_pool); 5326 5327 accel->rx_base_queue = baseq; 5328 accel->tx_base_queue = baseq; 5329 5330 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5331 adapter->rx_ring[baseq + i]->netdev = vdev; 5332 5333 /* Guarantee all rings are updated before we update the 5334 * MAC address filter. 5335 */ 5336 wmb(); 5337 5338 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5339 * need to only treat it as an error value if it is negative. 5340 */ 5341 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5342 VMDQ_P(accel->pool)); 5343 if (err >= 0) 5344 return 0; 5345 5346 /* if we cannot add the MAC rule then disable the offload */ 5347 macvlan_release_l2fw_offload(vdev); 5348 5349 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5350 adapter->rx_ring[baseq + i]->netdev = NULL; 5351 5352 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5353 5354 clear_bit(accel->pool, adapter->fwd_bitmask); 5355 kfree(accel); 5356 5357 return err; 5358 } 5359 5360 static int ixgbe_macvlan_up(struct net_device *vdev, void *data) 5361 { 5362 struct ixgbe_adapter *adapter = data; 5363 struct ixgbe_fwd_adapter *accel; 5364 5365 if (!netif_is_macvlan(vdev)) 5366 return 0; 5367 5368 accel = macvlan_accel_priv(vdev); 5369 if (!accel) 5370 return 0; 5371 5372 ixgbe_fwd_ring_up(adapter, accel); 5373 5374 return 0; 5375 } 5376 5377 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5378 { 5379 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5380 ixgbe_macvlan_up, adapter); 5381 } 5382 5383 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5384 { 5385 struct ixgbe_hw *hw = &adapter->hw; 5386 5387 ixgbe_configure_pb(adapter); 5388 #ifdef CONFIG_IXGBE_DCB 5389 ixgbe_configure_dcb(adapter); 5390 #endif 5391 /* 5392 * We must restore virtualization before VLANs or else 5393 * the VLVF registers will not be populated 5394 */ 5395 ixgbe_configure_virtualization(adapter); 5396 5397 ixgbe_set_rx_mode(adapter->netdev); 5398 ixgbe_restore_vlan(adapter); 5399 ixgbe_ipsec_restore(adapter); 5400 5401 switch (hw->mac.type) { 5402 case ixgbe_mac_82599EB: 5403 case ixgbe_mac_X540: 5404 hw->mac.ops.disable_rx_buff(hw); 5405 break; 5406 default: 5407 break; 5408 } 5409 5410 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5411 ixgbe_init_fdir_signature_82599(&adapter->hw, 5412 adapter->fdir_pballoc); 5413 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5414 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5415 adapter->fdir_pballoc); 5416 ixgbe_fdir_filter_restore(adapter); 5417 } 5418 5419 switch (hw->mac.type) { 5420 case ixgbe_mac_82599EB: 5421 case ixgbe_mac_X540: 5422 hw->mac.ops.enable_rx_buff(hw); 5423 break; 5424 default: 5425 break; 5426 } 5427 5428 #ifdef CONFIG_IXGBE_DCA 5429 /* configure DCA */ 5430 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5431 ixgbe_setup_dca(adapter); 5432 #endif /* CONFIG_IXGBE_DCA */ 5433 5434 #ifdef IXGBE_FCOE 5435 /* configure FCoE L2 filters, redirection table, and Rx control */ 5436 ixgbe_configure_fcoe(adapter); 5437 5438 #endif /* IXGBE_FCOE */ 5439 ixgbe_configure_tx(adapter); 5440 ixgbe_configure_rx(adapter); 5441 ixgbe_configure_dfwd(adapter); 5442 } 5443 5444 /** 5445 * ixgbe_sfp_link_config - set up SFP+ link 5446 * @adapter: pointer to private adapter struct 5447 **/ 5448 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5449 { 5450 /* 5451 * We are assuming the worst case scenario here, and that 5452 * is that an SFP was inserted/removed after the reset 5453 * but before SFP detection was enabled. As such the best 5454 * solution is to just start searching as soon as we start 5455 */ 5456 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5457 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5458 5459 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5460 adapter->sfp_poll_time = 0; 5461 } 5462 5463 /** 5464 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5465 * @hw: pointer to private hardware struct 5466 * 5467 * Returns 0 on success, negative on failure 5468 **/ 5469 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5470 { 5471 u32 speed; 5472 bool autoneg, link_up = false; 5473 int ret = IXGBE_ERR_LINK_SETUP; 5474 5475 if (hw->mac.ops.check_link) 5476 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5477 5478 if (ret) 5479 return ret; 5480 5481 speed = hw->phy.autoneg_advertised; 5482 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5483 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5484 &autoneg); 5485 if (ret) 5486 return ret; 5487 5488 if (hw->mac.ops.setup_link) 5489 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5490 5491 return ret; 5492 } 5493 5494 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5495 { 5496 struct ixgbe_hw *hw = &adapter->hw; 5497 u32 gpie = 0; 5498 5499 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5500 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5501 IXGBE_GPIE_OCD; 5502 gpie |= IXGBE_GPIE_EIAME; 5503 /* 5504 * use EIAM to auto-mask when MSI-X interrupt is asserted 5505 * this saves a register write for every interrupt 5506 */ 5507 switch (hw->mac.type) { 5508 case ixgbe_mac_82598EB: 5509 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5510 break; 5511 case ixgbe_mac_82599EB: 5512 case ixgbe_mac_X540: 5513 case ixgbe_mac_X550: 5514 case ixgbe_mac_X550EM_x: 5515 case ixgbe_mac_x550em_a: 5516 default: 5517 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5518 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5519 break; 5520 } 5521 } else { 5522 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5523 * specifically only auto mask tx and rx interrupts */ 5524 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5525 } 5526 5527 /* XXX: to interrupt immediately for EICS writes, enable this */ 5528 /* gpie |= IXGBE_GPIE_EIMEN; */ 5529 5530 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5531 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5532 5533 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5534 case IXGBE_82599_VMDQ_8Q_MASK: 5535 gpie |= IXGBE_GPIE_VTMODE_16; 5536 break; 5537 case IXGBE_82599_VMDQ_4Q_MASK: 5538 gpie |= IXGBE_GPIE_VTMODE_32; 5539 break; 5540 default: 5541 gpie |= IXGBE_GPIE_VTMODE_64; 5542 break; 5543 } 5544 } 5545 5546 /* Enable Thermal over heat sensor interrupt */ 5547 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5548 switch (adapter->hw.mac.type) { 5549 case ixgbe_mac_82599EB: 5550 gpie |= IXGBE_SDP0_GPIEN_8259X; 5551 break; 5552 default: 5553 break; 5554 } 5555 } 5556 5557 /* Enable fan failure interrupt */ 5558 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5559 gpie |= IXGBE_SDP1_GPIEN(hw); 5560 5561 switch (hw->mac.type) { 5562 case ixgbe_mac_82599EB: 5563 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5564 break; 5565 case ixgbe_mac_X550EM_x: 5566 case ixgbe_mac_x550em_a: 5567 gpie |= IXGBE_SDP0_GPIEN_X540; 5568 break; 5569 default: 5570 break; 5571 } 5572 5573 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5574 } 5575 5576 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5577 { 5578 struct ixgbe_hw *hw = &adapter->hw; 5579 int err; 5580 u32 ctrl_ext; 5581 5582 ixgbe_get_hw_control(adapter); 5583 ixgbe_setup_gpie(adapter); 5584 5585 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5586 ixgbe_configure_msix(adapter); 5587 else 5588 ixgbe_configure_msi_and_legacy(adapter); 5589 5590 /* enable the optics for 82599 SFP+ fiber */ 5591 if (hw->mac.ops.enable_tx_laser) 5592 hw->mac.ops.enable_tx_laser(hw); 5593 5594 if (hw->phy.ops.set_phy_power) 5595 hw->phy.ops.set_phy_power(hw, true); 5596 5597 smp_mb__before_atomic(); 5598 clear_bit(__IXGBE_DOWN, &adapter->state); 5599 ixgbe_napi_enable_all(adapter); 5600 5601 if (ixgbe_is_sfp(hw)) { 5602 ixgbe_sfp_link_config(adapter); 5603 } else { 5604 err = ixgbe_non_sfp_link_config(hw); 5605 if (err) 5606 e_err(probe, "link_config FAILED %d\n", err); 5607 } 5608 5609 /* clear any pending interrupts, may auto mask */ 5610 IXGBE_READ_REG(hw, IXGBE_EICR); 5611 ixgbe_irq_enable(adapter, true, true); 5612 5613 /* 5614 * If this adapter has a fan, check to see if we had a failure 5615 * before we enabled the interrupt. 5616 */ 5617 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5618 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5619 if (esdp & IXGBE_ESDP_SDP1) 5620 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5621 } 5622 5623 /* bring the link up in the watchdog, this could race with our first 5624 * link up interrupt but shouldn't be a problem */ 5625 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5626 adapter->link_check_timeout = jiffies; 5627 mod_timer(&adapter->service_timer, jiffies); 5628 5629 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5630 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5631 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5632 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5633 } 5634 5635 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5636 { 5637 WARN_ON(in_interrupt()); 5638 /* put off any impending NetWatchDogTimeout */ 5639 netif_trans_update(adapter->netdev); 5640 5641 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5642 usleep_range(1000, 2000); 5643 if (adapter->hw.phy.type == ixgbe_phy_fw) 5644 ixgbe_watchdog_link_is_down(adapter); 5645 ixgbe_down(adapter); 5646 /* 5647 * If SR-IOV enabled then wait a bit before bringing the adapter 5648 * back up to give the VFs time to respond to the reset. The 5649 * two second wait is based upon the watchdog timer cycle in 5650 * the VF driver. 5651 */ 5652 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5653 msleep(2000); 5654 ixgbe_up(adapter); 5655 clear_bit(__IXGBE_RESETTING, &adapter->state); 5656 } 5657 5658 void ixgbe_up(struct ixgbe_adapter *adapter) 5659 { 5660 /* hardware has been reset, we need to reload some things */ 5661 ixgbe_configure(adapter); 5662 5663 ixgbe_up_complete(adapter); 5664 } 5665 5666 void ixgbe_reset(struct ixgbe_adapter *adapter) 5667 { 5668 struct ixgbe_hw *hw = &adapter->hw; 5669 struct net_device *netdev = adapter->netdev; 5670 int err; 5671 5672 if (ixgbe_removed(hw->hw_addr)) 5673 return; 5674 /* lock SFP init bit to prevent race conditions with the watchdog */ 5675 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5676 usleep_range(1000, 2000); 5677 5678 /* clear all SFP and link config related flags while holding SFP_INIT */ 5679 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5680 IXGBE_FLAG2_SFP_NEEDS_RESET); 5681 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5682 5683 err = hw->mac.ops.init_hw(hw); 5684 switch (err) { 5685 case 0: 5686 case IXGBE_ERR_SFP_NOT_PRESENT: 5687 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5688 break; 5689 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5690 e_dev_err("master disable timed out\n"); 5691 break; 5692 case IXGBE_ERR_EEPROM_VERSION: 5693 /* We are running on a pre-production device, log a warning */ 5694 e_dev_warn("This device is a pre-production adapter/LOM. " 5695 "Please be aware there may be issues associated with " 5696 "your hardware. If you are experiencing problems " 5697 "please contact your Intel or hardware " 5698 "representative who provided you with this " 5699 "hardware.\n"); 5700 break; 5701 default: 5702 e_dev_err("Hardware Error: %d\n", err); 5703 } 5704 5705 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5706 5707 /* flush entries out of MAC table */ 5708 ixgbe_flush_sw_mac_table(adapter); 5709 __dev_uc_unsync(netdev, NULL); 5710 5711 /* do not flush user set addresses */ 5712 ixgbe_mac_set_default_filter(adapter); 5713 5714 /* update SAN MAC vmdq pool selection */ 5715 if (hw->mac.san_mac_rar_index) 5716 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5717 5718 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5719 ixgbe_ptp_reset(adapter); 5720 5721 if (hw->phy.ops.set_phy_power) { 5722 if (!netif_running(adapter->netdev) && !adapter->wol) 5723 hw->phy.ops.set_phy_power(hw, false); 5724 else 5725 hw->phy.ops.set_phy_power(hw, true); 5726 } 5727 } 5728 5729 /** 5730 * ixgbe_clean_tx_ring - Free Tx Buffers 5731 * @tx_ring: ring to be cleaned 5732 **/ 5733 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5734 { 5735 u16 i = tx_ring->next_to_clean; 5736 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5737 5738 while (i != tx_ring->next_to_use) { 5739 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5740 5741 /* Free all the Tx ring sk_buffs */ 5742 if (ring_is_xdp(tx_ring)) 5743 xdp_return_frame(tx_buffer->xdpf); 5744 else 5745 dev_kfree_skb_any(tx_buffer->skb); 5746 5747 /* unmap skb header data */ 5748 dma_unmap_single(tx_ring->dev, 5749 dma_unmap_addr(tx_buffer, dma), 5750 dma_unmap_len(tx_buffer, len), 5751 DMA_TO_DEVICE); 5752 5753 /* check for eop_desc to determine the end of the packet */ 5754 eop_desc = tx_buffer->next_to_watch; 5755 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5756 5757 /* unmap remaining buffers */ 5758 while (tx_desc != eop_desc) { 5759 tx_buffer++; 5760 tx_desc++; 5761 i++; 5762 if (unlikely(i == tx_ring->count)) { 5763 i = 0; 5764 tx_buffer = tx_ring->tx_buffer_info; 5765 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5766 } 5767 5768 /* unmap any remaining paged data */ 5769 if (dma_unmap_len(tx_buffer, len)) 5770 dma_unmap_page(tx_ring->dev, 5771 dma_unmap_addr(tx_buffer, dma), 5772 dma_unmap_len(tx_buffer, len), 5773 DMA_TO_DEVICE); 5774 } 5775 5776 /* move us one more past the eop_desc for start of next pkt */ 5777 tx_buffer++; 5778 i++; 5779 if (unlikely(i == tx_ring->count)) { 5780 i = 0; 5781 tx_buffer = tx_ring->tx_buffer_info; 5782 } 5783 } 5784 5785 /* reset BQL for queue */ 5786 if (!ring_is_xdp(tx_ring)) 5787 netdev_tx_reset_queue(txring_txq(tx_ring)); 5788 5789 /* reset next_to_use and next_to_clean */ 5790 tx_ring->next_to_use = 0; 5791 tx_ring->next_to_clean = 0; 5792 } 5793 5794 /** 5795 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5796 * @adapter: board private structure 5797 **/ 5798 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5799 { 5800 int i; 5801 5802 for (i = 0; i < adapter->num_rx_queues; i++) 5803 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5804 } 5805 5806 /** 5807 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5808 * @adapter: board private structure 5809 **/ 5810 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5811 { 5812 int i; 5813 5814 for (i = 0; i < adapter->num_tx_queues; i++) 5815 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5816 for (i = 0; i < adapter->num_xdp_queues; i++) 5817 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5818 } 5819 5820 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5821 { 5822 struct hlist_node *node2; 5823 struct ixgbe_fdir_filter *filter; 5824 5825 spin_lock(&adapter->fdir_perfect_lock); 5826 5827 hlist_for_each_entry_safe(filter, node2, 5828 &adapter->fdir_filter_list, fdir_node) { 5829 hlist_del(&filter->fdir_node); 5830 kfree(filter); 5831 } 5832 adapter->fdir_filter_count = 0; 5833 5834 spin_unlock(&adapter->fdir_perfect_lock); 5835 } 5836 5837 void ixgbe_down(struct ixgbe_adapter *adapter) 5838 { 5839 struct net_device *netdev = adapter->netdev; 5840 struct ixgbe_hw *hw = &adapter->hw; 5841 int i; 5842 5843 /* signal that we are down to the interrupt handler */ 5844 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5845 return; /* do nothing if already down */ 5846 5847 /* disable receives */ 5848 hw->mac.ops.disable_rx(hw); 5849 5850 /* disable all enabled rx queues */ 5851 for (i = 0; i < adapter->num_rx_queues; i++) 5852 /* this call also flushes the previous write */ 5853 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5854 5855 usleep_range(10000, 20000); 5856 5857 /* synchronize_sched() needed for pending XDP buffers to drain */ 5858 if (adapter->xdp_ring[0]) 5859 synchronize_sched(); 5860 netif_tx_stop_all_queues(netdev); 5861 5862 /* call carrier off first to avoid false dev_watchdog timeouts */ 5863 netif_carrier_off(netdev); 5864 netif_tx_disable(netdev); 5865 5866 ixgbe_irq_disable(adapter); 5867 5868 ixgbe_napi_disable_all(adapter); 5869 5870 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5871 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5872 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5873 5874 del_timer_sync(&adapter->service_timer); 5875 5876 if (adapter->num_vfs) { 5877 /* Clear EITR Select mapping */ 5878 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5879 5880 /* Mark all the VFs as inactive */ 5881 for (i = 0 ; i < adapter->num_vfs; i++) 5882 adapter->vfinfo[i].clear_to_send = false; 5883 5884 /* ping all the active vfs to let them know we are going down */ 5885 ixgbe_ping_all_vfs(adapter); 5886 5887 /* Disable all VFTE/VFRE TX/RX */ 5888 ixgbe_disable_tx_rx(adapter); 5889 } 5890 5891 /* disable transmits in the hardware now that interrupts are off */ 5892 for (i = 0; i < adapter->num_tx_queues; i++) { 5893 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5894 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5895 } 5896 for (i = 0; i < adapter->num_xdp_queues; i++) { 5897 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5898 5899 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5900 } 5901 5902 /* Disable the Tx DMA engine on 82599 and later MAC */ 5903 switch (hw->mac.type) { 5904 case ixgbe_mac_82599EB: 5905 case ixgbe_mac_X540: 5906 case ixgbe_mac_X550: 5907 case ixgbe_mac_X550EM_x: 5908 case ixgbe_mac_x550em_a: 5909 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5910 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5911 ~IXGBE_DMATXCTL_TE)); 5912 break; 5913 default: 5914 break; 5915 } 5916 5917 if (!pci_channel_offline(adapter->pdev)) 5918 ixgbe_reset(adapter); 5919 5920 /* power down the optics for 82599 SFP+ fiber */ 5921 if (hw->mac.ops.disable_tx_laser) 5922 hw->mac.ops.disable_tx_laser(hw); 5923 5924 ixgbe_clean_all_tx_rings(adapter); 5925 ixgbe_clean_all_rx_rings(adapter); 5926 } 5927 5928 /** 5929 * ixgbe_eee_capable - helper function to determine EEE support on X550 5930 * @adapter: board private structure 5931 */ 5932 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5933 { 5934 struct ixgbe_hw *hw = &adapter->hw; 5935 5936 switch (hw->device_id) { 5937 case IXGBE_DEV_ID_X550EM_A_1G_T: 5938 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 5939 if (!hw->phy.eee_speeds_supported) 5940 break; 5941 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 5942 if (!hw->phy.eee_speeds_advertised) 5943 break; 5944 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 5945 break; 5946 default: 5947 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 5948 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 5949 break; 5950 } 5951 } 5952 5953 /** 5954 * ixgbe_tx_timeout - Respond to a Tx Hang 5955 * @netdev: network interface device structure 5956 **/ 5957 static void ixgbe_tx_timeout(struct net_device *netdev) 5958 { 5959 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5960 5961 /* Do the reset outside of interrupt context */ 5962 ixgbe_tx_timeout_reset(adapter); 5963 } 5964 5965 #ifdef CONFIG_IXGBE_DCB 5966 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 5967 { 5968 struct ixgbe_hw *hw = &adapter->hw; 5969 struct tc_configuration *tc; 5970 int j; 5971 5972 switch (hw->mac.type) { 5973 case ixgbe_mac_82598EB: 5974 case ixgbe_mac_82599EB: 5975 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5976 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5977 break; 5978 case ixgbe_mac_X540: 5979 case ixgbe_mac_X550: 5980 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5981 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5982 break; 5983 case ixgbe_mac_X550EM_x: 5984 case ixgbe_mac_x550em_a: 5985 default: 5986 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 5987 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 5988 break; 5989 } 5990 5991 /* Configure DCB traffic classes */ 5992 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5993 tc = &adapter->dcb_cfg.tc_config[j]; 5994 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5995 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5996 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5997 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5998 tc->dcb_pfc = pfc_disabled; 5999 } 6000 6001 /* Initialize default user to priority mapping, UPx->TC0 */ 6002 tc = &adapter->dcb_cfg.tc_config[0]; 6003 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6004 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6005 6006 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6007 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6008 adapter->dcb_cfg.pfc_mode_enable = false; 6009 adapter->dcb_set_bitmap = 0x00; 6010 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6011 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6012 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6013 sizeof(adapter->temp_dcb_cfg)); 6014 } 6015 #endif 6016 6017 /** 6018 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6019 * @adapter: board private structure to initialize 6020 * @ii: pointer to ixgbe_info for device 6021 * 6022 * ixgbe_sw_init initializes the Adapter private data structure. 6023 * Fields are initialized based on PCI device information and 6024 * OS network device settings (MTU size). 6025 **/ 6026 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6027 const struct ixgbe_info *ii) 6028 { 6029 struct ixgbe_hw *hw = &adapter->hw; 6030 struct pci_dev *pdev = adapter->pdev; 6031 unsigned int rss, fdir; 6032 u32 fwsm; 6033 int i; 6034 6035 /* PCI config space info */ 6036 6037 hw->vendor_id = pdev->vendor; 6038 hw->device_id = pdev->device; 6039 hw->revision_id = pdev->revision; 6040 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6041 hw->subsystem_device_id = pdev->subsystem_device; 6042 6043 /* get_invariants needs the device IDs */ 6044 ii->get_invariants(hw); 6045 6046 /* Set common capability flags and settings */ 6047 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6048 adapter->ring_feature[RING_F_RSS].limit = rss; 6049 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6050 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6051 adapter->atr_sample_rate = 20; 6052 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6053 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6054 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6055 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6056 #ifdef CONFIG_IXGBE_DCA 6057 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6058 #endif 6059 #ifdef CONFIG_IXGBE_DCB 6060 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6061 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6062 #endif 6063 #ifdef IXGBE_FCOE 6064 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6065 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6066 #ifdef CONFIG_IXGBE_DCB 6067 /* Default traffic class to use for FCoE */ 6068 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6069 #endif /* CONFIG_IXGBE_DCB */ 6070 #endif /* IXGBE_FCOE */ 6071 6072 /* initialize static ixgbe jump table entries */ 6073 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6074 GFP_KERNEL); 6075 if (!adapter->jump_tables[0]) 6076 return -ENOMEM; 6077 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6078 6079 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6080 adapter->jump_tables[i] = NULL; 6081 6082 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6083 hw->mac.num_rar_entries, 6084 GFP_ATOMIC); 6085 if (!adapter->mac_table) 6086 return -ENOMEM; 6087 6088 if (ixgbe_init_rss_key(adapter)) 6089 return -ENOMEM; 6090 6091 /* Set MAC specific capability flags and exceptions */ 6092 switch (hw->mac.type) { 6093 case ixgbe_mac_82598EB: 6094 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6095 6096 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6097 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6098 6099 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6100 adapter->ring_feature[RING_F_FDIR].limit = 0; 6101 adapter->atr_sample_rate = 0; 6102 adapter->fdir_pballoc = 0; 6103 #ifdef IXGBE_FCOE 6104 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6105 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6106 #ifdef CONFIG_IXGBE_DCB 6107 adapter->fcoe.up = 0; 6108 #endif /* IXGBE_DCB */ 6109 #endif /* IXGBE_FCOE */ 6110 break; 6111 case ixgbe_mac_82599EB: 6112 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6113 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6114 break; 6115 case ixgbe_mac_X540: 6116 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6117 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6118 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6119 break; 6120 case ixgbe_mac_x550em_a: 6121 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6122 switch (hw->device_id) { 6123 case IXGBE_DEV_ID_X550EM_A_1G_T: 6124 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6125 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6126 break; 6127 default: 6128 break; 6129 } 6130 /* fall through */ 6131 case ixgbe_mac_X550EM_x: 6132 #ifdef CONFIG_IXGBE_DCB 6133 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6134 #endif 6135 #ifdef IXGBE_FCOE 6136 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6137 #ifdef CONFIG_IXGBE_DCB 6138 adapter->fcoe.up = 0; 6139 #endif /* IXGBE_DCB */ 6140 #endif /* IXGBE_FCOE */ 6141 /* Fall Through */ 6142 case ixgbe_mac_X550: 6143 if (hw->mac.type == ixgbe_mac_X550) 6144 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6145 #ifdef CONFIG_IXGBE_DCA 6146 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6147 #endif 6148 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6149 break; 6150 default: 6151 break; 6152 } 6153 6154 #ifdef IXGBE_FCOE 6155 /* FCoE support exists, always init the FCoE lock */ 6156 spin_lock_init(&adapter->fcoe.lock); 6157 6158 #endif 6159 /* n-tuple support exists, always init our spinlock */ 6160 spin_lock_init(&adapter->fdir_perfect_lock); 6161 6162 #ifdef CONFIG_IXGBE_DCB 6163 ixgbe_init_dcb(adapter); 6164 #endif 6165 6166 /* default flow control settings */ 6167 hw->fc.requested_mode = ixgbe_fc_full; 6168 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6169 ixgbe_pbthresh_setup(adapter); 6170 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6171 hw->fc.send_xon = true; 6172 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6173 6174 #ifdef CONFIG_PCI_IOV 6175 if (max_vfs > 0) 6176 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6177 6178 /* assign number of SR-IOV VFs */ 6179 if (hw->mac.type != ixgbe_mac_82598EB) { 6180 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6181 max_vfs = 0; 6182 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6183 } 6184 } 6185 #endif /* CONFIG_PCI_IOV */ 6186 6187 /* enable itr by default in dynamic mode */ 6188 adapter->rx_itr_setting = 1; 6189 adapter->tx_itr_setting = 1; 6190 6191 /* set default ring sizes */ 6192 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6193 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6194 6195 /* set default work limits */ 6196 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6197 6198 /* initialize eeprom parameters */ 6199 if (ixgbe_init_eeprom_params_generic(hw)) { 6200 e_dev_err("EEPROM initialization failed\n"); 6201 return -EIO; 6202 } 6203 6204 /* PF holds first pool slot */ 6205 set_bit(0, adapter->fwd_bitmask); 6206 set_bit(__IXGBE_DOWN, &adapter->state); 6207 6208 return 0; 6209 } 6210 6211 /** 6212 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6213 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6214 * 6215 * Return 0 on success, negative on failure 6216 **/ 6217 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6218 { 6219 struct device *dev = tx_ring->dev; 6220 int orig_node = dev_to_node(dev); 6221 int ring_node = -1; 6222 int size; 6223 6224 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6225 6226 if (tx_ring->q_vector) 6227 ring_node = tx_ring->q_vector->numa_node; 6228 6229 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6230 if (!tx_ring->tx_buffer_info) 6231 tx_ring->tx_buffer_info = vmalloc(size); 6232 if (!tx_ring->tx_buffer_info) 6233 goto err; 6234 6235 /* round up to nearest 4K */ 6236 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6237 tx_ring->size = ALIGN(tx_ring->size, 4096); 6238 6239 set_dev_node(dev, ring_node); 6240 tx_ring->desc = dma_alloc_coherent(dev, 6241 tx_ring->size, 6242 &tx_ring->dma, 6243 GFP_KERNEL); 6244 set_dev_node(dev, orig_node); 6245 if (!tx_ring->desc) 6246 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6247 &tx_ring->dma, GFP_KERNEL); 6248 if (!tx_ring->desc) 6249 goto err; 6250 6251 tx_ring->next_to_use = 0; 6252 tx_ring->next_to_clean = 0; 6253 return 0; 6254 6255 err: 6256 vfree(tx_ring->tx_buffer_info); 6257 tx_ring->tx_buffer_info = NULL; 6258 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6259 return -ENOMEM; 6260 } 6261 6262 /** 6263 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6264 * @adapter: board private structure 6265 * 6266 * If this function returns with an error, then it's possible one or 6267 * more of the rings is populated (while the rest are not). It is the 6268 * callers duty to clean those orphaned rings. 6269 * 6270 * Return 0 on success, negative on failure 6271 **/ 6272 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6273 { 6274 int i, j = 0, err = 0; 6275 6276 for (i = 0; i < adapter->num_tx_queues; i++) { 6277 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6278 if (!err) 6279 continue; 6280 6281 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6282 goto err_setup_tx; 6283 } 6284 for (j = 0; j < adapter->num_xdp_queues; j++) { 6285 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6286 if (!err) 6287 continue; 6288 6289 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6290 goto err_setup_tx; 6291 } 6292 6293 return 0; 6294 err_setup_tx: 6295 /* rewind the index freeing the rings as we go */ 6296 while (j--) 6297 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6298 while (i--) 6299 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6300 return err; 6301 } 6302 6303 /** 6304 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6305 * @adapter: pointer to ixgbe_adapter 6306 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6307 * 6308 * Returns 0 on success, negative on failure 6309 **/ 6310 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6311 struct ixgbe_ring *rx_ring) 6312 { 6313 struct device *dev = rx_ring->dev; 6314 int orig_node = dev_to_node(dev); 6315 int ring_node = -1; 6316 int size, err; 6317 6318 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6319 6320 if (rx_ring->q_vector) 6321 ring_node = rx_ring->q_vector->numa_node; 6322 6323 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6324 if (!rx_ring->rx_buffer_info) 6325 rx_ring->rx_buffer_info = vmalloc(size); 6326 if (!rx_ring->rx_buffer_info) 6327 goto err; 6328 6329 /* Round up to nearest 4K */ 6330 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6331 rx_ring->size = ALIGN(rx_ring->size, 4096); 6332 6333 set_dev_node(dev, ring_node); 6334 rx_ring->desc = dma_alloc_coherent(dev, 6335 rx_ring->size, 6336 &rx_ring->dma, 6337 GFP_KERNEL); 6338 set_dev_node(dev, orig_node); 6339 if (!rx_ring->desc) 6340 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6341 &rx_ring->dma, GFP_KERNEL); 6342 if (!rx_ring->desc) 6343 goto err; 6344 6345 rx_ring->next_to_clean = 0; 6346 rx_ring->next_to_use = 0; 6347 6348 /* XDP RX-queue info */ 6349 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6350 rx_ring->queue_index) < 0) 6351 goto err; 6352 6353 err = xdp_rxq_info_reg_mem_model(&rx_ring->xdp_rxq, 6354 MEM_TYPE_PAGE_SHARED, NULL); 6355 if (err) { 6356 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6357 goto err; 6358 } 6359 6360 rx_ring->xdp_prog = adapter->xdp_prog; 6361 6362 return 0; 6363 err: 6364 vfree(rx_ring->rx_buffer_info); 6365 rx_ring->rx_buffer_info = NULL; 6366 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6367 return -ENOMEM; 6368 } 6369 6370 /** 6371 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6372 * @adapter: board private structure 6373 * 6374 * If this function returns with an error, then it's possible one or 6375 * more of the rings is populated (while the rest are not). It is the 6376 * callers duty to clean those orphaned rings. 6377 * 6378 * Return 0 on success, negative on failure 6379 **/ 6380 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6381 { 6382 int i, err = 0; 6383 6384 for (i = 0; i < adapter->num_rx_queues; i++) { 6385 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6386 if (!err) 6387 continue; 6388 6389 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6390 goto err_setup_rx; 6391 } 6392 6393 #ifdef IXGBE_FCOE 6394 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6395 if (!err) 6396 #endif 6397 return 0; 6398 err_setup_rx: 6399 /* rewind the index freeing the rings as we go */ 6400 while (i--) 6401 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6402 return err; 6403 } 6404 6405 /** 6406 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6407 * @tx_ring: Tx descriptor ring for a specific queue 6408 * 6409 * Free all transmit software resources 6410 **/ 6411 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6412 { 6413 ixgbe_clean_tx_ring(tx_ring); 6414 6415 vfree(tx_ring->tx_buffer_info); 6416 tx_ring->tx_buffer_info = NULL; 6417 6418 /* if not set, then don't free */ 6419 if (!tx_ring->desc) 6420 return; 6421 6422 dma_free_coherent(tx_ring->dev, tx_ring->size, 6423 tx_ring->desc, tx_ring->dma); 6424 6425 tx_ring->desc = NULL; 6426 } 6427 6428 /** 6429 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6430 * @adapter: board private structure 6431 * 6432 * Free all transmit software resources 6433 **/ 6434 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6435 { 6436 int i; 6437 6438 for (i = 0; i < adapter->num_tx_queues; i++) 6439 if (adapter->tx_ring[i]->desc) 6440 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6441 for (i = 0; i < adapter->num_xdp_queues; i++) 6442 if (adapter->xdp_ring[i]->desc) 6443 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6444 } 6445 6446 /** 6447 * ixgbe_free_rx_resources - Free Rx Resources 6448 * @rx_ring: ring to clean the resources from 6449 * 6450 * Free all receive software resources 6451 **/ 6452 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6453 { 6454 ixgbe_clean_rx_ring(rx_ring); 6455 6456 rx_ring->xdp_prog = NULL; 6457 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6458 vfree(rx_ring->rx_buffer_info); 6459 rx_ring->rx_buffer_info = NULL; 6460 6461 /* if not set, then don't free */ 6462 if (!rx_ring->desc) 6463 return; 6464 6465 dma_free_coherent(rx_ring->dev, rx_ring->size, 6466 rx_ring->desc, rx_ring->dma); 6467 6468 rx_ring->desc = NULL; 6469 } 6470 6471 /** 6472 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6473 * @adapter: board private structure 6474 * 6475 * Free all receive software resources 6476 **/ 6477 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6478 { 6479 int i; 6480 6481 #ifdef IXGBE_FCOE 6482 ixgbe_free_fcoe_ddp_resources(adapter); 6483 6484 #endif 6485 for (i = 0; i < adapter->num_rx_queues; i++) 6486 if (adapter->rx_ring[i]->desc) 6487 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6488 } 6489 6490 /** 6491 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6492 * @netdev: network interface device structure 6493 * @new_mtu: new value for maximum frame size 6494 * 6495 * Returns 0 on success, negative on failure 6496 **/ 6497 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6498 { 6499 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6500 6501 /* 6502 * For 82599EB we cannot allow legacy VFs to enable their receive 6503 * paths when MTU greater than 1500 is configured. So display a 6504 * warning that legacy VFs will be disabled. 6505 */ 6506 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6507 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6508 (new_mtu > ETH_DATA_LEN)) 6509 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6510 6511 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6512 6513 /* must set new MTU before calling down or up */ 6514 netdev->mtu = new_mtu; 6515 6516 if (netif_running(netdev)) 6517 ixgbe_reinit_locked(adapter); 6518 6519 return 0; 6520 } 6521 6522 /** 6523 * ixgbe_open - Called when a network interface is made active 6524 * @netdev: network interface device structure 6525 * 6526 * Returns 0 on success, negative value on failure 6527 * 6528 * The open entry point is called when a network interface is made 6529 * active by the system (IFF_UP). At this point all resources needed 6530 * for transmit and receive operations are allocated, the interrupt 6531 * handler is registered with the OS, the watchdog timer is started, 6532 * and the stack is notified that the interface is ready. 6533 **/ 6534 int ixgbe_open(struct net_device *netdev) 6535 { 6536 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6537 struct ixgbe_hw *hw = &adapter->hw; 6538 int err, queues; 6539 6540 /* disallow open during test */ 6541 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6542 return -EBUSY; 6543 6544 netif_carrier_off(netdev); 6545 6546 /* allocate transmit descriptors */ 6547 err = ixgbe_setup_all_tx_resources(adapter); 6548 if (err) 6549 goto err_setup_tx; 6550 6551 /* allocate receive descriptors */ 6552 err = ixgbe_setup_all_rx_resources(adapter); 6553 if (err) 6554 goto err_setup_rx; 6555 6556 ixgbe_configure(adapter); 6557 6558 err = ixgbe_request_irq(adapter); 6559 if (err) 6560 goto err_req_irq; 6561 6562 /* Notify the stack of the actual queue counts. */ 6563 queues = adapter->num_tx_queues; 6564 err = netif_set_real_num_tx_queues(netdev, queues); 6565 if (err) 6566 goto err_set_queues; 6567 6568 queues = adapter->num_rx_queues; 6569 err = netif_set_real_num_rx_queues(netdev, queues); 6570 if (err) 6571 goto err_set_queues; 6572 6573 ixgbe_ptp_init(adapter); 6574 6575 ixgbe_up_complete(adapter); 6576 6577 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6578 udp_tunnel_get_rx_info(netdev); 6579 6580 return 0; 6581 6582 err_set_queues: 6583 ixgbe_free_irq(adapter); 6584 err_req_irq: 6585 ixgbe_free_all_rx_resources(adapter); 6586 if (hw->phy.ops.set_phy_power && !adapter->wol) 6587 hw->phy.ops.set_phy_power(&adapter->hw, false); 6588 err_setup_rx: 6589 ixgbe_free_all_tx_resources(adapter); 6590 err_setup_tx: 6591 ixgbe_reset(adapter); 6592 6593 return err; 6594 } 6595 6596 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6597 { 6598 ixgbe_ptp_suspend(adapter); 6599 6600 if (adapter->hw.phy.ops.enter_lplu) { 6601 adapter->hw.phy.reset_disable = true; 6602 ixgbe_down(adapter); 6603 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6604 adapter->hw.phy.reset_disable = false; 6605 } else { 6606 ixgbe_down(adapter); 6607 } 6608 6609 ixgbe_free_irq(adapter); 6610 6611 ixgbe_free_all_tx_resources(adapter); 6612 ixgbe_free_all_rx_resources(adapter); 6613 } 6614 6615 /** 6616 * ixgbe_close - Disables a network interface 6617 * @netdev: network interface device structure 6618 * 6619 * Returns 0, this is not allowed to fail 6620 * 6621 * The close entry point is called when an interface is de-activated 6622 * by the OS. The hardware is still under the drivers control, but 6623 * needs to be disabled. A global MAC reset is issued to stop the 6624 * hardware, and all transmit and receive resources are freed. 6625 **/ 6626 int ixgbe_close(struct net_device *netdev) 6627 { 6628 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6629 6630 ixgbe_ptp_stop(adapter); 6631 6632 if (netif_device_present(netdev)) 6633 ixgbe_close_suspend(adapter); 6634 6635 ixgbe_fdir_filter_exit(adapter); 6636 6637 ixgbe_release_hw_control(adapter); 6638 6639 return 0; 6640 } 6641 6642 #ifdef CONFIG_PM 6643 static int ixgbe_resume(struct pci_dev *pdev) 6644 { 6645 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6646 struct net_device *netdev = adapter->netdev; 6647 u32 err; 6648 6649 adapter->hw.hw_addr = adapter->io_addr; 6650 pci_set_power_state(pdev, PCI_D0); 6651 pci_restore_state(pdev); 6652 /* 6653 * pci_restore_state clears dev->state_saved so call 6654 * pci_save_state to restore it. 6655 */ 6656 pci_save_state(pdev); 6657 6658 err = pci_enable_device_mem(pdev); 6659 if (err) { 6660 e_dev_err("Cannot enable PCI device from suspend\n"); 6661 return err; 6662 } 6663 smp_mb__before_atomic(); 6664 clear_bit(__IXGBE_DISABLED, &adapter->state); 6665 pci_set_master(pdev); 6666 6667 pci_wake_from_d3(pdev, false); 6668 6669 ixgbe_reset(adapter); 6670 6671 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6672 6673 rtnl_lock(); 6674 err = ixgbe_init_interrupt_scheme(adapter); 6675 if (!err && netif_running(netdev)) 6676 err = ixgbe_open(netdev); 6677 6678 6679 if (!err) 6680 netif_device_attach(netdev); 6681 rtnl_unlock(); 6682 6683 return err; 6684 } 6685 #endif /* CONFIG_PM */ 6686 6687 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6688 { 6689 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6690 struct net_device *netdev = adapter->netdev; 6691 struct ixgbe_hw *hw = &adapter->hw; 6692 u32 ctrl; 6693 u32 wufc = adapter->wol; 6694 #ifdef CONFIG_PM 6695 int retval = 0; 6696 #endif 6697 6698 rtnl_lock(); 6699 netif_device_detach(netdev); 6700 6701 if (netif_running(netdev)) 6702 ixgbe_close_suspend(adapter); 6703 6704 ixgbe_clear_interrupt_scheme(adapter); 6705 rtnl_unlock(); 6706 6707 #ifdef CONFIG_PM 6708 retval = pci_save_state(pdev); 6709 if (retval) 6710 return retval; 6711 6712 #endif 6713 if (hw->mac.ops.stop_link_on_d3) 6714 hw->mac.ops.stop_link_on_d3(hw); 6715 6716 if (wufc) { 6717 u32 fctrl; 6718 6719 ixgbe_set_rx_mode(netdev); 6720 6721 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6722 if (hw->mac.ops.enable_tx_laser) 6723 hw->mac.ops.enable_tx_laser(hw); 6724 6725 /* enable the reception of multicast packets */ 6726 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6727 fctrl |= IXGBE_FCTRL_MPE; 6728 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6729 6730 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6731 ctrl |= IXGBE_CTRL_GIO_DIS; 6732 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6733 6734 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6735 } else { 6736 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6737 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6738 } 6739 6740 switch (hw->mac.type) { 6741 case ixgbe_mac_82598EB: 6742 pci_wake_from_d3(pdev, false); 6743 break; 6744 case ixgbe_mac_82599EB: 6745 case ixgbe_mac_X540: 6746 case ixgbe_mac_X550: 6747 case ixgbe_mac_X550EM_x: 6748 case ixgbe_mac_x550em_a: 6749 pci_wake_from_d3(pdev, !!wufc); 6750 break; 6751 default: 6752 break; 6753 } 6754 6755 *enable_wake = !!wufc; 6756 if (hw->phy.ops.set_phy_power && !*enable_wake) 6757 hw->phy.ops.set_phy_power(hw, false); 6758 6759 ixgbe_release_hw_control(adapter); 6760 6761 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6762 pci_disable_device(pdev); 6763 6764 return 0; 6765 } 6766 6767 #ifdef CONFIG_PM 6768 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6769 { 6770 int retval; 6771 bool wake; 6772 6773 retval = __ixgbe_shutdown(pdev, &wake); 6774 if (retval) 6775 return retval; 6776 6777 if (wake) { 6778 pci_prepare_to_sleep(pdev); 6779 } else { 6780 pci_wake_from_d3(pdev, false); 6781 pci_set_power_state(pdev, PCI_D3hot); 6782 } 6783 6784 return 0; 6785 } 6786 #endif /* CONFIG_PM */ 6787 6788 static void ixgbe_shutdown(struct pci_dev *pdev) 6789 { 6790 bool wake; 6791 6792 __ixgbe_shutdown(pdev, &wake); 6793 6794 if (system_state == SYSTEM_POWER_OFF) { 6795 pci_wake_from_d3(pdev, wake); 6796 pci_set_power_state(pdev, PCI_D3hot); 6797 } 6798 } 6799 6800 /** 6801 * ixgbe_update_stats - Update the board statistics counters. 6802 * @adapter: board private structure 6803 **/ 6804 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6805 { 6806 struct net_device *netdev = adapter->netdev; 6807 struct ixgbe_hw *hw = &adapter->hw; 6808 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6809 u64 total_mpc = 0; 6810 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6811 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6812 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6813 u64 alloc_rx_page = 0; 6814 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6815 6816 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6817 test_bit(__IXGBE_RESETTING, &adapter->state)) 6818 return; 6819 6820 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6821 u64 rsc_count = 0; 6822 u64 rsc_flush = 0; 6823 for (i = 0; i < adapter->num_rx_queues; i++) { 6824 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6825 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6826 } 6827 adapter->rsc_total_count = rsc_count; 6828 adapter->rsc_total_flush = rsc_flush; 6829 } 6830 6831 for (i = 0; i < adapter->num_rx_queues; i++) { 6832 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6833 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6834 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 6835 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6836 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6837 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6838 bytes += rx_ring->stats.bytes; 6839 packets += rx_ring->stats.packets; 6840 } 6841 adapter->non_eop_descs = non_eop_descs; 6842 adapter->alloc_rx_page = alloc_rx_page; 6843 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6844 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6845 adapter->hw_csum_rx_error = hw_csum_rx_error; 6846 netdev->stats.rx_bytes = bytes; 6847 netdev->stats.rx_packets = packets; 6848 6849 bytes = 0; 6850 packets = 0; 6851 /* gather some stats to the adapter struct that are per queue */ 6852 for (i = 0; i < adapter->num_tx_queues; i++) { 6853 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6854 restart_queue += tx_ring->tx_stats.restart_queue; 6855 tx_busy += tx_ring->tx_stats.tx_busy; 6856 bytes += tx_ring->stats.bytes; 6857 packets += tx_ring->stats.packets; 6858 } 6859 for (i = 0; i < adapter->num_xdp_queues; i++) { 6860 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6861 6862 restart_queue += xdp_ring->tx_stats.restart_queue; 6863 tx_busy += xdp_ring->tx_stats.tx_busy; 6864 bytes += xdp_ring->stats.bytes; 6865 packets += xdp_ring->stats.packets; 6866 } 6867 adapter->restart_queue = restart_queue; 6868 adapter->tx_busy = tx_busy; 6869 netdev->stats.tx_bytes = bytes; 6870 netdev->stats.tx_packets = packets; 6871 6872 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6873 6874 /* 8 register reads */ 6875 for (i = 0; i < 8; i++) { 6876 /* for packet buffers not used, the register should read 0 */ 6877 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6878 missed_rx += mpc; 6879 hwstats->mpc[i] += mpc; 6880 total_mpc += hwstats->mpc[i]; 6881 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6882 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6883 switch (hw->mac.type) { 6884 case ixgbe_mac_82598EB: 6885 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6886 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6887 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6888 hwstats->pxonrxc[i] += 6889 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6890 break; 6891 case ixgbe_mac_82599EB: 6892 case ixgbe_mac_X540: 6893 case ixgbe_mac_X550: 6894 case ixgbe_mac_X550EM_x: 6895 case ixgbe_mac_x550em_a: 6896 hwstats->pxonrxc[i] += 6897 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6898 break; 6899 default: 6900 break; 6901 } 6902 } 6903 6904 /*16 register reads */ 6905 for (i = 0; i < 16; i++) { 6906 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6907 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6908 if ((hw->mac.type == ixgbe_mac_82599EB) || 6909 (hw->mac.type == ixgbe_mac_X540) || 6910 (hw->mac.type == ixgbe_mac_X550) || 6911 (hw->mac.type == ixgbe_mac_X550EM_x) || 6912 (hw->mac.type == ixgbe_mac_x550em_a)) { 6913 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6914 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6915 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6916 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6917 } 6918 } 6919 6920 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6921 /* work around hardware counting issue */ 6922 hwstats->gprc -= missed_rx; 6923 6924 ixgbe_update_xoff_received(adapter); 6925 6926 /* 82598 hardware only has a 32 bit counter in the high register */ 6927 switch (hw->mac.type) { 6928 case ixgbe_mac_82598EB: 6929 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6930 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6931 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6932 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6933 break; 6934 case ixgbe_mac_X540: 6935 case ixgbe_mac_X550: 6936 case ixgbe_mac_X550EM_x: 6937 case ixgbe_mac_x550em_a: 6938 /* OS2BMC stats are X540 and later */ 6939 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6940 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6941 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6942 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6943 /* fall through */ 6944 case ixgbe_mac_82599EB: 6945 for (i = 0; i < 16; i++) 6946 adapter->hw_rx_no_dma_resources += 6947 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6948 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6949 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6950 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6951 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6952 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6953 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6954 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6955 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6956 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6957 #ifdef IXGBE_FCOE 6958 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6959 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6960 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6961 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6962 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6963 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6964 /* Add up per cpu counters for total ddp aloc fail */ 6965 if (adapter->fcoe.ddp_pool) { 6966 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6967 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6968 unsigned int cpu; 6969 u64 noddp = 0, noddp_ext_buff = 0; 6970 for_each_possible_cpu(cpu) { 6971 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6972 noddp += ddp_pool->noddp; 6973 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6974 } 6975 hwstats->fcoe_noddp = noddp; 6976 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6977 } 6978 #endif /* IXGBE_FCOE */ 6979 break; 6980 default: 6981 break; 6982 } 6983 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6984 hwstats->bprc += bprc; 6985 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6986 if (hw->mac.type == ixgbe_mac_82598EB) 6987 hwstats->mprc -= bprc; 6988 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6989 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6990 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6991 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6992 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6993 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6994 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6995 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6996 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6997 hwstats->lxontxc += lxon; 6998 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6999 hwstats->lxofftxc += lxoff; 7000 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7001 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7002 /* 7003 * 82598 errata - tx of flow control packets is included in tx counters 7004 */ 7005 xon_off_tot = lxon + lxoff; 7006 hwstats->gptc -= xon_off_tot; 7007 hwstats->mptc -= xon_off_tot; 7008 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7009 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7010 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7011 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7012 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7013 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7014 hwstats->ptc64 -= xon_off_tot; 7015 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7016 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7017 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7018 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7019 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7020 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7021 7022 /* Fill out the OS statistics structure */ 7023 netdev->stats.multicast = hwstats->mprc; 7024 7025 /* Rx Errors */ 7026 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7027 netdev->stats.rx_dropped = 0; 7028 netdev->stats.rx_length_errors = hwstats->rlec; 7029 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7030 netdev->stats.rx_missed_errors = total_mpc; 7031 } 7032 7033 /** 7034 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7035 * @adapter: pointer to the device adapter structure 7036 **/ 7037 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7038 { 7039 struct ixgbe_hw *hw = &adapter->hw; 7040 int i; 7041 7042 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7043 return; 7044 7045 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7046 7047 /* if interface is down do nothing */ 7048 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7049 return; 7050 7051 /* do nothing if we are not using signature filters */ 7052 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7053 return; 7054 7055 adapter->fdir_overflow++; 7056 7057 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7058 for (i = 0; i < adapter->num_tx_queues; i++) 7059 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7060 &(adapter->tx_ring[i]->state)); 7061 for (i = 0; i < adapter->num_xdp_queues; i++) 7062 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7063 &adapter->xdp_ring[i]->state); 7064 /* re-enable flow director interrupts */ 7065 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7066 } else { 7067 e_err(probe, "failed to finish FDIR re-initialization, " 7068 "ignored adding FDIR ATR filters\n"); 7069 } 7070 } 7071 7072 /** 7073 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7074 * @adapter: pointer to the device adapter structure 7075 * 7076 * This function serves two purposes. First it strobes the interrupt lines 7077 * in order to make certain interrupts are occurring. Secondly it sets the 7078 * bits needed to check for TX hangs. As a result we should immediately 7079 * determine if a hang has occurred. 7080 */ 7081 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7082 { 7083 struct ixgbe_hw *hw = &adapter->hw; 7084 u64 eics = 0; 7085 int i; 7086 7087 /* If we're down, removing or resetting, just bail */ 7088 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7089 test_bit(__IXGBE_REMOVING, &adapter->state) || 7090 test_bit(__IXGBE_RESETTING, &adapter->state)) 7091 return; 7092 7093 /* Force detection of hung controller */ 7094 if (netif_carrier_ok(adapter->netdev)) { 7095 for (i = 0; i < adapter->num_tx_queues; i++) 7096 set_check_for_tx_hang(adapter->tx_ring[i]); 7097 for (i = 0; i < adapter->num_xdp_queues; i++) 7098 set_check_for_tx_hang(adapter->xdp_ring[i]); 7099 } 7100 7101 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7102 /* 7103 * for legacy and MSI interrupts don't set any bits 7104 * that are enabled for EIAM, because this operation 7105 * would set *both* EIMS and EICS for any bit in EIAM 7106 */ 7107 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7108 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7109 } else { 7110 /* get one bit for every active tx/rx interrupt vector */ 7111 for (i = 0; i < adapter->num_q_vectors; i++) { 7112 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7113 if (qv->rx.ring || qv->tx.ring) 7114 eics |= BIT_ULL(i); 7115 } 7116 } 7117 7118 /* Cause software interrupt to ensure rings are cleaned */ 7119 ixgbe_irq_rearm_queues(adapter, eics); 7120 } 7121 7122 /** 7123 * ixgbe_watchdog_update_link - update the link status 7124 * @adapter: pointer to the device adapter structure 7125 **/ 7126 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7127 { 7128 struct ixgbe_hw *hw = &adapter->hw; 7129 u32 link_speed = adapter->link_speed; 7130 bool link_up = adapter->link_up; 7131 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7132 7133 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7134 return; 7135 7136 if (hw->mac.ops.check_link) { 7137 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7138 } else { 7139 /* always assume link is up, if no check link function */ 7140 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7141 link_up = true; 7142 } 7143 7144 if (adapter->ixgbe_ieee_pfc) 7145 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7146 7147 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7148 hw->mac.ops.fc_enable(hw); 7149 ixgbe_set_rx_drop_en(adapter); 7150 } 7151 7152 if (link_up || 7153 time_after(jiffies, (adapter->link_check_timeout + 7154 IXGBE_TRY_LINK_TIMEOUT))) { 7155 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7156 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7157 IXGBE_WRITE_FLUSH(hw); 7158 } 7159 7160 adapter->link_up = link_up; 7161 adapter->link_speed = link_speed; 7162 } 7163 7164 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7165 { 7166 #ifdef CONFIG_IXGBE_DCB 7167 struct net_device *netdev = adapter->netdev; 7168 struct dcb_app app = { 7169 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7170 .protocol = 0, 7171 }; 7172 u8 up = 0; 7173 7174 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7175 up = dcb_ieee_getapp_mask(netdev, &app); 7176 7177 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7178 #endif 7179 } 7180 7181 /** 7182 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7183 * print link up message 7184 * @adapter: pointer to the device adapter structure 7185 **/ 7186 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7187 { 7188 struct net_device *netdev = adapter->netdev; 7189 struct ixgbe_hw *hw = &adapter->hw; 7190 u32 link_speed = adapter->link_speed; 7191 const char *speed_str; 7192 bool flow_rx, flow_tx; 7193 7194 /* only continue if link was previously down */ 7195 if (netif_carrier_ok(netdev)) 7196 return; 7197 7198 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7199 7200 switch (hw->mac.type) { 7201 case ixgbe_mac_82598EB: { 7202 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7203 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7204 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7205 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7206 } 7207 break; 7208 case ixgbe_mac_X540: 7209 case ixgbe_mac_X550: 7210 case ixgbe_mac_X550EM_x: 7211 case ixgbe_mac_x550em_a: 7212 case ixgbe_mac_82599EB: { 7213 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7214 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7215 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7216 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7217 } 7218 break; 7219 default: 7220 flow_tx = false; 7221 flow_rx = false; 7222 break; 7223 } 7224 7225 adapter->last_rx_ptp_check = jiffies; 7226 7227 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7228 ixgbe_ptp_start_cyclecounter(adapter); 7229 7230 switch (link_speed) { 7231 case IXGBE_LINK_SPEED_10GB_FULL: 7232 speed_str = "10 Gbps"; 7233 break; 7234 case IXGBE_LINK_SPEED_5GB_FULL: 7235 speed_str = "5 Gbps"; 7236 break; 7237 case IXGBE_LINK_SPEED_2_5GB_FULL: 7238 speed_str = "2.5 Gbps"; 7239 break; 7240 case IXGBE_LINK_SPEED_1GB_FULL: 7241 speed_str = "1 Gbps"; 7242 break; 7243 case IXGBE_LINK_SPEED_100_FULL: 7244 speed_str = "100 Mbps"; 7245 break; 7246 case IXGBE_LINK_SPEED_10_FULL: 7247 speed_str = "10 Mbps"; 7248 break; 7249 default: 7250 speed_str = "unknown speed"; 7251 break; 7252 } 7253 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7254 ((flow_rx && flow_tx) ? "RX/TX" : 7255 (flow_rx ? "RX" : 7256 (flow_tx ? "TX" : "None")))); 7257 7258 netif_carrier_on(netdev); 7259 ixgbe_check_vf_rate_limit(adapter); 7260 7261 /* enable transmits */ 7262 netif_tx_wake_all_queues(adapter->netdev); 7263 7264 /* update the default user priority for VFs */ 7265 ixgbe_update_default_up(adapter); 7266 7267 /* ping all the active vfs to let them know link has changed */ 7268 ixgbe_ping_all_vfs(adapter); 7269 } 7270 7271 /** 7272 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7273 * print link down message 7274 * @adapter: pointer to the adapter structure 7275 **/ 7276 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7277 { 7278 struct net_device *netdev = adapter->netdev; 7279 struct ixgbe_hw *hw = &adapter->hw; 7280 7281 adapter->link_up = false; 7282 adapter->link_speed = 0; 7283 7284 /* only continue if link was up previously */ 7285 if (!netif_carrier_ok(netdev)) 7286 return; 7287 7288 /* poll for SFP+ cable when link is down */ 7289 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7290 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7291 7292 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7293 ixgbe_ptp_start_cyclecounter(adapter); 7294 7295 e_info(drv, "NIC Link is Down\n"); 7296 netif_carrier_off(netdev); 7297 7298 /* ping all the active vfs to let them know link has changed */ 7299 ixgbe_ping_all_vfs(adapter); 7300 } 7301 7302 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7303 { 7304 int i; 7305 7306 for (i = 0; i < adapter->num_tx_queues; i++) { 7307 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7308 7309 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7310 return true; 7311 } 7312 7313 for (i = 0; i < adapter->num_xdp_queues; i++) { 7314 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7315 7316 if (ring->next_to_use != ring->next_to_clean) 7317 return true; 7318 } 7319 7320 return false; 7321 } 7322 7323 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7324 { 7325 struct ixgbe_hw *hw = &adapter->hw; 7326 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7327 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7328 7329 int i, j; 7330 7331 if (!adapter->num_vfs) 7332 return false; 7333 7334 /* resetting the PF is only needed for MAC before X550 */ 7335 if (hw->mac.type >= ixgbe_mac_X550) 7336 return false; 7337 7338 for (i = 0; i < adapter->num_vfs; i++) { 7339 for (j = 0; j < q_per_pool; j++) { 7340 u32 h, t; 7341 7342 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7343 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7344 7345 if (h != t) 7346 return true; 7347 } 7348 } 7349 7350 return false; 7351 } 7352 7353 /** 7354 * ixgbe_watchdog_flush_tx - flush queues on link down 7355 * @adapter: pointer to the device adapter structure 7356 **/ 7357 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7358 { 7359 if (!netif_carrier_ok(adapter->netdev)) { 7360 if (ixgbe_ring_tx_pending(adapter) || 7361 ixgbe_vf_tx_pending(adapter)) { 7362 /* We've lost link, so the controller stops DMA, 7363 * but we've got queued Tx work that's never going 7364 * to get done, so reset controller to flush Tx. 7365 * (Do the reset outside of interrupt context). 7366 */ 7367 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7368 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7369 } 7370 } 7371 } 7372 7373 #ifdef CONFIG_PCI_IOV 7374 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7375 { 7376 struct ixgbe_hw *hw = &adapter->hw; 7377 struct pci_dev *pdev = adapter->pdev; 7378 unsigned int vf; 7379 u32 gpc; 7380 7381 if (!(netif_carrier_ok(adapter->netdev))) 7382 return; 7383 7384 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7385 if (gpc) /* If incrementing then no need for the check below */ 7386 return; 7387 /* Check to see if a bad DMA write target from an errant or 7388 * malicious VF has caused a PCIe error. If so then we can 7389 * issue a VFLR to the offending VF(s) and then resume without 7390 * requesting a full slot reset. 7391 */ 7392 7393 if (!pdev) 7394 return; 7395 7396 /* check status reg for all VFs owned by this PF */ 7397 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7398 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7399 u16 status_reg; 7400 7401 if (!vfdev) 7402 continue; 7403 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7404 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7405 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7406 pcie_flr(vfdev); 7407 } 7408 } 7409 7410 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7411 { 7412 u32 ssvpc; 7413 7414 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7415 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7416 adapter->num_vfs == 0) 7417 return; 7418 7419 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7420 7421 /* 7422 * ssvpc register is cleared on read, if zero then no 7423 * spoofed packets in the last interval. 7424 */ 7425 if (!ssvpc) 7426 return; 7427 7428 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7429 } 7430 #else 7431 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7432 { 7433 } 7434 7435 static void 7436 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7437 { 7438 } 7439 #endif /* CONFIG_PCI_IOV */ 7440 7441 7442 /** 7443 * ixgbe_watchdog_subtask - check and bring link up 7444 * @adapter: pointer to the device adapter structure 7445 **/ 7446 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7447 { 7448 /* if interface is down, removing or resetting, do nothing */ 7449 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7450 test_bit(__IXGBE_REMOVING, &adapter->state) || 7451 test_bit(__IXGBE_RESETTING, &adapter->state)) 7452 return; 7453 7454 ixgbe_watchdog_update_link(adapter); 7455 7456 if (adapter->link_up) 7457 ixgbe_watchdog_link_is_up(adapter); 7458 else 7459 ixgbe_watchdog_link_is_down(adapter); 7460 7461 ixgbe_check_for_bad_vf(adapter); 7462 ixgbe_spoof_check(adapter); 7463 ixgbe_update_stats(adapter); 7464 7465 ixgbe_watchdog_flush_tx(adapter); 7466 } 7467 7468 /** 7469 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7470 * @adapter: the ixgbe adapter structure 7471 **/ 7472 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7473 { 7474 struct ixgbe_hw *hw = &adapter->hw; 7475 s32 err; 7476 7477 /* not searching for SFP so there is nothing to do here */ 7478 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7479 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7480 return; 7481 7482 if (adapter->sfp_poll_time && 7483 time_after(adapter->sfp_poll_time, jiffies)) 7484 return; /* If not yet time to poll for SFP */ 7485 7486 /* someone else is in init, wait until next service event */ 7487 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7488 return; 7489 7490 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7491 7492 err = hw->phy.ops.identify_sfp(hw); 7493 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7494 goto sfp_out; 7495 7496 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7497 /* If no cable is present, then we need to reset 7498 * the next time we find a good cable. */ 7499 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7500 } 7501 7502 /* exit on error */ 7503 if (err) 7504 goto sfp_out; 7505 7506 /* exit if reset not needed */ 7507 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7508 goto sfp_out; 7509 7510 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7511 7512 /* 7513 * A module may be identified correctly, but the EEPROM may not have 7514 * support for that module. setup_sfp() will fail in that case, so 7515 * we should not allow that module to load. 7516 */ 7517 if (hw->mac.type == ixgbe_mac_82598EB) 7518 err = hw->phy.ops.reset(hw); 7519 else 7520 err = hw->mac.ops.setup_sfp(hw); 7521 7522 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7523 goto sfp_out; 7524 7525 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7526 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7527 7528 sfp_out: 7529 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7530 7531 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7532 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7533 e_dev_err("failed to initialize because an unsupported " 7534 "SFP+ module type was detected.\n"); 7535 e_dev_err("Reload the driver after installing a " 7536 "supported module.\n"); 7537 unregister_netdev(adapter->netdev); 7538 } 7539 } 7540 7541 /** 7542 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7543 * @adapter: the ixgbe adapter structure 7544 **/ 7545 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7546 { 7547 struct ixgbe_hw *hw = &adapter->hw; 7548 u32 cap_speed; 7549 u32 speed; 7550 bool autoneg = false; 7551 7552 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7553 return; 7554 7555 /* someone else is in init, wait until next service event */ 7556 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7557 return; 7558 7559 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7560 7561 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7562 7563 /* advertise highest capable link speed */ 7564 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7565 speed = IXGBE_LINK_SPEED_10GB_FULL; 7566 else 7567 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7568 IXGBE_LINK_SPEED_1GB_FULL); 7569 7570 if (hw->mac.ops.setup_link) 7571 hw->mac.ops.setup_link(hw, speed, true); 7572 7573 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7574 adapter->link_check_timeout = jiffies; 7575 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7576 } 7577 7578 /** 7579 * ixgbe_service_timer - Timer Call-back 7580 * @t: pointer to timer_list structure 7581 **/ 7582 static void ixgbe_service_timer(struct timer_list *t) 7583 { 7584 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7585 unsigned long next_event_offset; 7586 7587 /* poll faster when waiting for link */ 7588 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7589 next_event_offset = HZ / 10; 7590 else 7591 next_event_offset = HZ * 2; 7592 7593 /* Reset the timer */ 7594 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7595 7596 ixgbe_service_event_schedule(adapter); 7597 } 7598 7599 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7600 { 7601 struct ixgbe_hw *hw = &adapter->hw; 7602 u32 status; 7603 7604 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7605 return; 7606 7607 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7608 7609 if (!hw->phy.ops.handle_lasi) 7610 return; 7611 7612 status = hw->phy.ops.handle_lasi(&adapter->hw); 7613 if (status != IXGBE_ERR_OVERTEMP) 7614 return; 7615 7616 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7617 } 7618 7619 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7620 { 7621 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7622 return; 7623 7624 /* If we're already down, removing or resetting, just bail */ 7625 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7626 test_bit(__IXGBE_REMOVING, &adapter->state) || 7627 test_bit(__IXGBE_RESETTING, &adapter->state)) 7628 return; 7629 7630 ixgbe_dump(adapter); 7631 netdev_err(adapter->netdev, "Reset adapter\n"); 7632 adapter->tx_timeout_count++; 7633 7634 rtnl_lock(); 7635 ixgbe_reinit_locked(adapter); 7636 rtnl_unlock(); 7637 } 7638 7639 /** 7640 * ixgbe_service_task - manages and runs subtasks 7641 * @work: pointer to work_struct containing our data 7642 **/ 7643 static void ixgbe_service_task(struct work_struct *work) 7644 { 7645 struct ixgbe_adapter *adapter = container_of(work, 7646 struct ixgbe_adapter, 7647 service_task); 7648 if (ixgbe_removed(adapter->hw.hw_addr)) { 7649 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7650 rtnl_lock(); 7651 ixgbe_down(adapter); 7652 rtnl_unlock(); 7653 } 7654 ixgbe_service_event_complete(adapter); 7655 return; 7656 } 7657 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7658 rtnl_lock(); 7659 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7660 udp_tunnel_get_rx_info(adapter->netdev); 7661 rtnl_unlock(); 7662 } 7663 ixgbe_reset_subtask(adapter); 7664 ixgbe_phy_interrupt_subtask(adapter); 7665 ixgbe_sfp_detection_subtask(adapter); 7666 ixgbe_sfp_link_config_subtask(adapter); 7667 ixgbe_check_overtemp_subtask(adapter); 7668 ixgbe_watchdog_subtask(adapter); 7669 ixgbe_fdir_reinit_subtask(adapter); 7670 ixgbe_check_hang_subtask(adapter); 7671 7672 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7673 ixgbe_ptp_overflow_check(adapter); 7674 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7675 ixgbe_ptp_rx_hang(adapter); 7676 ixgbe_ptp_tx_hang(adapter); 7677 } 7678 7679 ixgbe_service_event_complete(adapter); 7680 } 7681 7682 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7683 struct ixgbe_tx_buffer *first, 7684 u8 *hdr_len, 7685 struct ixgbe_ipsec_tx_data *itd) 7686 { 7687 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7688 struct sk_buff *skb = first->skb; 7689 union { 7690 struct iphdr *v4; 7691 struct ipv6hdr *v6; 7692 unsigned char *hdr; 7693 } ip; 7694 union { 7695 struct tcphdr *tcp; 7696 unsigned char *hdr; 7697 } l4; 7698 u32 paylen, l4_offset; 7699 u32 fceof_saidx = 0; 7700 int err; 7701 7702 if (skb->ip_summed != CHECKSUM_PARTIAL) 7703 return 0; 7704 7705 if (!skb_is_gso(skb)) 7706 return 0; 7707 7708 err = skb_cow_head(skb, 0); 7709 if (err < 0) 7710 return err; 7711 7712 if (eth_p_mpls(first->protocol)) 7713 ip.hdr = skb_inner_network_header(skb); 7714 else 7715 ip.hdr = skb_network_header(skb); 7716 l4.hdr = skb_checksum_start(skb); 7717 7718 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7719 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7720 7721 /* initialize outer IP header fields */ 7722 if (ip.v4->version == 4) { 7723 unsigned char *csum_start = skb_checksum_start(skb); 7724 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7725 int len = csum_start - trans_start; 7726 7727 /* IP header will have to cancel out any data that 7728 * is not a part of the outer IP header, so set to 7729 * a reverse csum if needed, else init check to 0. 7730 */ 7731 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7732 csum_fold(csum_partial(trans_start, 7733 len, 0)) : 0; 7734 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7735 7736 ip.v4->tot_len = 0; 7737 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7738 IXGBE_TX_FLAGS_CSUM | 7739 IXGBE_TX_FLAGS_IPV4; 7740 } else { 7741 ip.v6->payload_len = 0; 7742 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7743 IXGBE_TX_FLAGS_CSUM; 7744 } 7745 7746 /* determine offset of inner transport header */ 7747 l4_offset = l4.hdr - skb->data; 7748 7749 /* compute length of segmentation header */ 7750 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7751 7752 /* remove payload length from inner checksum */ 7753 paylen = skb->len - l4_offset; 7754 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 7755 7756 /* update gso size and bytecount with header size */ 7757 first->gso_segs = skb_shinfo(skb)->gso_segs; 7758 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7759 7760 /* mss_l4len_id: use 0 as index for TSO */ 7761 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7762 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7763 7764 fceof_saidx |= itd->sa_idx; 7765 type_tucmd |= itd->flags | itd->trailer_len; 7766 7767 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7768 vlan_macip_lens = l4.hdr - ip.hdr; 7769 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7770 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7771 7772 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 7773 mss_l4len_idx); 7774 7775 return 1; 7776 } 7777 7778 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7779 { 7780 unsigned int offset = 0; 7781 7782 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7783 7784 return offset == skb_checksum_start_offset(skb); 7785 } 7786 7787 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7788 struct ixgbe_tx_buffer *first, 7789 struct ixgbe_ipsec_tx_data *itd) 7790 { 7791 struct sk_buff *skb = first->skb; 7792 u32 vlan_macip_lens = 0; 7793 u32 fceof_saidx = 0; 7794 u32 type_tucmd = 0; 7795 7796 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7797 csum_failed: 7798 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7799 IXGBE_TX_FLAGS_CC))) 7800 return; 7801 goto no_csum; 7802 } 7803 7804 switch (skb->csum_offset) { 7805 case offsetof(struct tcphdr, check): 7806 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7807 /* fall through */ 7808 case offsetof(struct udphdr, check): 7809 break; 7810 case offsetof(struct sctphdr, checksum): 7811 /* validate that this is actually an SCTP request */ 7812 if (((first->protocol == htons(ETH_P_IP)) && 7813 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7814 ((first->protocol == htons(ETH_P_IPV6)) && 7815 ixgbe_ipv6_csum_is_sctp(skb))) { 7816 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7817 break; 7818 } 7819 /* fall through */ 7820 default: 7821 skb_checksum_help(skb); 7822 goto csum_failed; 7823 } 7824 7825 /* update TX checksum flag */ 7826 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7827 vlan_macip_lens = skb_checksum_start_offset(skb) - 7828 skb_network_offset(skb); 7829 no_csum: 7830 /* vlan_macip_lens: MACLEN, VLAN tag */ 7831 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7832 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7833 7834 fceof_saidx |= itd->sa_idx; 7835 type_tucmd |= itd->flags | itd->trailer_len; 7836 7837 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 7838 } 7839 7840 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7841 ((_flag <= _result) ? \ 7842 ((u32)(_input & _flag) * (_result / _flag)) : \ 7843 ((u32)(_input & _flag) / (_flag / _result))) 7844 7845 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7846 { 7847 /* set type for advanced descriptor with frame checksum insertion */ 7848 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7849 IXGBE_ADVTXD_DCMD_DEXT | 7850 IXGBE_ADVTXD_DCMD_IFCS; 7851 7852 /* set HW vlan bit if vlan is present */ 7853 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7854 IXGBE_ADVTXD_DCMD_VLE); 7855 7856 /* set segmentation enable bits for TSO/FSO */ 7857 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7858 IXGBE_ADVTXD_DCMD_TSE); 7859 7860 /* set timestamp bit if present */ 7861 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7862 IXGBE_ADVTXD_MAC_TSTAMP); 7863 7864 /* insert frame checksum */ 7865 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7866 7867 return cmd_type; 7868 } 7869 7870 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7871 u32 tx_flags, unsigned int paylen) 7872 { 7873 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7874 7875 /* enable L4 checksum for TSO and TX checksum offload */ 7876 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7877 IXGBE_TX_FLAGS_CSUM, 7878 IXGBE_ADVTXD_POPTS_TXSM); 7879 7880 /* enable IPv4 checksum for TSO */ 7881 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7882 IXGBE_TX_FLAGS_IPV4, 7883 IXGBE_ADVTXD_POPTS_IXSM); 7884 7885 /* enable IPsec */ 7886 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7887 IXGBE_TX_FLAGS_IPSEC, 7888 IXGBE_ADVTXD_POPTS_IPSEC); 7889 7890 /* 7891 * Check Context must be set if Tx switch is enabled, which it 7892 * always is for case where virtual functions are running 7893 */ 7894 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7895 IXGBE_TX_FLAGS_CC, 7896 IXGBE_ADVTXD_CC); 7897 7898 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7899 } 7900 7901 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7902 { 7903 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7904 7905 /* Herbert's original patch had: 7906 * smp_mb__after_netif_stop_queue(); 7907 * but since that doesn't exist yet, just open code it. 7908 */ 7909 smp_mb(); 7910 7911 /* We need to check again in a case another CPU has just 7912 * made room available. 7913 */ 7914 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7915 return -EBUSY; 7916 7917 /* A reprieve! - use start_queue because it doesn't call schedule */ 7918 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7919 ++tx_ring->tx_stats.restart_queue; 7920 return 0; 7921 } 7922 7923 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7924 { 7925 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7926 return 0; 7927 7928 return __ixgbe_maybe_stop_tx(tx_ring, size); 7929 } 7930 7931 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7932 IXGBE_TXD_CMD_RS) 7933 7934 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7935 struct ixgbe_tx_buffer *first, 7936 const u8 hdr_len) 7937 { 7938 struct sk_buff *skb = first->skb; 7939 struct ixgbe_tx_buffer *tx_buffer; 7940 union ixgbe_adv_tx_desc *tx_desc; 7941 struct skb_frag_struct *frag; 7942 dma_addr_t dma; 7943 unsigned int data_len, size; 7944 u32 tx_flags = first->tx_flags; 7945 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7946 u16 i = tx_ring->next_to_use; 7947 7948 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7949 7950 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7951 7952 size = skb_headlen(skb); 7953 data_len = skb->data_len; 7954 7955 #ifdef IXGBE_FCOE 7956 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7957 if (data_len < sizeof(struct fcoe_crc_eof)) { 7958 size -= sizeof(struct fcoe_crc_eof) - data_len; 7959 data_len = 0; 7960 } else { 7961 data_len -= sizeof(struct fcoe_crc_eof); 7962 } 7963 } 7964 7965 #endif 7966 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7967 7968 tx_buffer = first; 7969 7970 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7971 if (dma_mapping_error(tx_ring->dev, dma)) 7972 goto dma_error; 7973 7974 /* record length, and DMA address */ 7975 dma_unmap_len_set(tx_buffer, len, size); 7976 dma_unmap_addr_set(tx_buffer, dma, dma); 7977 7978 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7979 7980 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7981 tx_desc->read.cmd_type_len = 7982 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7983 7984 i++; 7985 tx_desc++; 7986 if (i == tx_ring->count) { 7987 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7988 i = 0; 7989 } 7990 tx_desc->read.olinfo_status = 0; 7991 7992 dma += IXGBE_MAX_DATA_PER_TXD; 7993 size -= IXGBE_MAX_DATA_PER_TXD; 7994 7995 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7996 } 7997 7998 if (likely(!data_len)) 7999 break; 8000 8001 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8002 8003 i++; 8004 tx_desc++; 8005 if (i == tx_ring->count) { 8006 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8007 i = 0; 8008 } 8009 tx_desc->read.olinfo_status = 0; 8010 8011 #ifdef IXGBE_FCOE 8012 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8013 #else 8014 size = skb_frag_size(frag); 8015 #endif 8016 data_len -= size; 8017 8018 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8019 DMA_TO_DEVICE); 8020 8021 tx_buffer = &tx_ring->tx_buffer_info[i]; 8022 } 8023 8024 /* write last descriptor with RS and EOP bits */ 8025 cmd_type |= size | IXGBE_TXD_CMD; 8026 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8027 8028 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8029 8030 /* set the timestamp */ 8031 first->time_stamp = jiffies; 8032 8033 /* 8034 * Force memory writes to complete before letting h/w know there 8035 * are new descriptors to fetch. (Only applicable for weak-ordered 8036 * memory model archs, such as IA-64). 8037 * 8038 * We also need this memory barrier to make certain all of the 8039 * status bits have been updated before next_to_watch is written. 8040 */ 8041 wmb(); 8042 8043 /* set next_to_watch value indicating a packet is present */ 8044 first->next_to_watch = tx_desc; 8045 8046 i++; 8047 if (i == tx_ring->count) 8048 i = 0; 8049 8050 tx_ring->next_to_use = i; 8051 8052 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8053 8054 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8055 writel(i, tx_ring->tail); 8056 8057 /* we need this if more than one processor can write to our tail 8058 * at a time, it synchronizes IO on IA64/Altix systems 8059 */ 8060 mmiowb(); 8061 } 8062 8063 return 0; 8064 dma_error: 8065 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8066 8067 /* clear dma mappings for failed tx_buffer_info map */ 8068 for (;;) { 8069 tx_buffer = &tx_ring->tx_buffer_info[i]; 8070 if (dma_unmap_len(tx_buffer, len)) 8071 dma_unmap_page(tx_ring->dev, 8072 dma_unmap_addr(tx_buffer, dma), 8073 dma_unmap_len(tx_buffer, len), 8074 DMA_TO_DEVICE); 8075 dma_unmap_len_set(tx_buffer, len, 0); 8076 if (tx_buffer == first) 8077 break; 8078 if (i == 0) 8079 i += tx_ring->count; 8080 i--; 8081 } 8082 8083 dev_kfree_skb_any(first->skb); 8084 first->skb = NULL; 8085 8086 tx_ring->next_to_use = i; 8087 8088 return -1; 8089 } 8090 8091 static void ixgbe_atr(struct ixgbe_ring *ring, 8092 struct ixgbe_tx_buffer *first) 8093 { 8094 struct ixgbe_q_vector *q_vector = ring->q_vector; 8095 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8096 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8097 union { 8098 unsigned char *network; 8099 struct iphdr *ipv4; 8100 struct ipv6hdr *ipv6; 8101 } hdr; 8102 struct tcphdr *th; 8103 unsigned int hlen; 8104 struct sk_buff *skb; 8105 __be16 vlan_id; 8106 int l4_proto; 8107 8108 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8109 if (!q_vector) 8110 return; 8111 8112 /* do nothing if sampling is disabled */ 8113 if (!ring->atr_sample_rate) 8114 return; 8115 8116 ring->atr_count++; 8117 8118 /* currently only IPv4/IPv6 with TCP is supported */ 8119 if ((first->protocol != htons(ETH_P_IP)) && 8120 (first->protocol != htons(ETH_P_IPV6))) 8121 return; 8122 8123 /* snag network header to get L4 type and address */ 8124 skb = first->skb; 8125 hdr.network = skb_network_header(skb); 8126 if (unlikely(hdr.network <= skb->data)) 8127 return; 8128 if (skb->encapsulation && 8129 first->protocol == htons(ETH_P_IP) && 8130 hdr.ipv4->protocol == IPPROTO_UDP) { 8131 struct ixgbe_adapter *adapter = q_vector->adapter; 8132 8133 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8134 VXLAN_HEADROOM)) 8135 return; 8136 8137 /* verify the port is recognized as VXLAN */ 8138 if (adapter->vxlan_port && 8139 udp_hdr(skb)->dest == adapter->vxlan_port) 8140 hdr.network = skb_inner_network_header(skb); 8141 8142 if (adapter->geneve_port && 8143 udp_hdr(skb)->dest == adapter->geneve_port) 8144 hdr.network = skb_inner_network_header(skb); 8145 } 8146 8147 /* Make sure we have at least [minimum IPv4 header + TCP] 8148 * or [IPv6 header] bytes 8149 */ 8150 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8151 return; 8152 8153 /* Currently only IPv4/IPv6 with TCP is supported */ 8154 switch (hdr.ipv4->version) { 8155 case IPVERSION: 8156 /* access ihl as u8 to avoid unaligned access on ia64 */ 8157 hlen = (hdr.network[0] & 0x0F) << 2; 8158 l4_proto = hdr.ipv4->protocol; 8159 break; 8160 case 6: 8161 hlen = hdr.network - skb->data; 8162 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8163 hlen -= hdr.network - skb->data; 8164 break; 8165 default: 8166 return; 8167 } 8168 8169 if (l4_proto != IPPROTO_TCP) 8170 return; 8171 8172 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8173 hlen + sizeof(struct tcphdr))) 8174 return; 8175 8176 th = (struct tcphdr *)(hdr.network + hlen); 8177 8178 /* skip this packet since the socket is closing */ 8179 if (th->fin) 8180 return; 8181 8182 /* sample on all syn packets or once every atr sample count */ 8183 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8184 return; 8185 8186 /* reset sample count */ 8187 ring->atr_count = 0; 8188 8189 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8190 8191 /* 8192 * src and dst are inverted, think how the receiver sees them 8193 * 8194 * The input is broken into two sections, a non-compressed section 8195 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8196 * is XORed together and stored in the compressed dword. 8197 */ 8198 input.formatted.vlan_id = vlan_id; 8199 8200 /* 8201 * since src port and flex bytes occupy the same word XOR them together 8202 * and write the value to source port portion of compressed dword 8203 */ 8204 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8205 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8206 else 8207 common.port.src ^= th->dest ^ first->protocol; 8208 common.port.dst ^= th->source; 8209 8210 switch (hdr.ipv4->version) { 8211 case IPVERSION: 8212 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8213 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8214 break; 8215 case 6: 8216 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8217 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8218 hdr.ipv6->saddr.s6_addr32[1] ^ 8219 hdr.ipv6->saddr.s6_addr32[2] ^ 8220 hdr.ipv6->saddr.s6_addr32[3] ^ 8221 hdr.ipv6->daddr.s6_addr32[0] ^ 8222 hdr.ipv6->daddr.s6_addr32[1] ^ 8223 hdr.ipv6->daddr.s6_addr32[2] ^ 8224 hdr.ipv6->daddr.s6_addr32[3]; 8225 break; 8226 default: 8227 break; 8228 } 8229 8230 if (hdr.network != skb_network_header(skb)) 8231 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8232 8233 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8234 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8235 input, common, ring->queue_index); 8236 } 8237 8238 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8239 void *accel_priv, select_queue_fallback_t fallback) 8240 { 8241 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8242 struct ixgbe_adapter *adapter; 8243 int txq; 8244 #ifdef IXGBE_FCOE 8245 struct ixgbe_ring_feature *f; 8246 #endif 8247 8248 if (fwd_adapter) { 8249 adapter = netdev_priv(dev); 8250 txq = reciprocal_scale(skb_get_hash(skb), 8251 adapter->num_rx_queues_per_pool); 8252 8253 return txq + fwd_adapter->tx_base_queue; 8254 } 8255 8256 #ifdef IXGBE_FCOE 8257 8258 /* 8259 * only execute the code below if protocol is FCoE 8260 * or FIP and we have FCoE enabled on the adapter 8261 */ 8262 switch (vlan_get_protocol(skb)) { 8263 case htons(ETH_P_FCOE): 8264 case htons(ETH_P_FIP): 8265 adapter = netdev_priv(dev); 8266 8267 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8268 break; 8269 /* fall through */ 8270 default: 8271 return fallback(dev, skb); 8272 } 8273 8274 f = &adapter->ring_feature[RING_F_FCOE]; 8275 8276 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8277 smp_processor_id(); 8278 8279 while (txq >= f->indices) 8280 txq -= f->indices; 8281 8282 return txq + f->offset; 8283 #else 8284 return fallback(dev, skb); 8285 #endif 8286 } 8287 8288 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8289 struct xdp_frame *xdpf) 8290 { 8291 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8292 struct ixgbe_tx_buffer *tx_buffer; 8293 union ixgbe_adv_tx_desc *tx_desc; 8294 u32 len, cmd_type; 8295 dma_addr_t dma; 8296 u16 i; 8297 8298 len = xdpf->len; 8299 8300 if (unlikely(!ixgbe_desc_unused(ring))) 8301 return IXGBE_XDP_CONSUMED; 8302 8303 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8304 if (dma_mapping_error(ring->dev, dma)) 8305 return IXGBE_XDP_CONSUMED; 8306 8307 /* record the location of the first descriptor for this packet */ 8308 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8309 tx_buffer->bytecount = len; 8310 tx_buffer->gso_segs = 1; 8311 tx_buffer->protocol = 0; 8312 8313 i = ring->next_to_use; 8314 tx_desc = IXGBE_TX_DESC(ring, i); 8315 8316 dma_unmap_len_set(tx_buffer, len, len); 8317 dma_unmap_addr_set(tx_buffer, dma, dma); 8318 tx_buffer->xdpf = xdpf; 8319 8320 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8321 8322 /* put descriptor type bits */ 8323 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8324 IXGBE_ADVTXD_DCMD_DEXT | 8325 IXGBE_ADVTXD_DCMD_IFCS; 8326 cmd_type |= len | IXGBE_TXD_CMD; 8327 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8328 tx_desc->read.olinfo_status = 8329 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8330 8331 /* Avoid any potential race with xdp_xmit and cleanup */ 8332 smp_wmb(); 8333 8334 /* set next_to_watch value indicating a packet is present */ 8335 i++; 8336 if (i == ring->count) 8337 i = 0; 8338 8339 tx_buffer->next_to_watch = tx_desc; 8340 ring->next_to_use = i; 8341 8342 return IXGBE_XDP_TX; 8343 } 8344 8345 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8346 struct ixgbe_adapter *adapter, 8347 struct ixgbe_ring *tx_ring) 8348 { 8349 struct ixgbe_tx_buffer *first; 8350 int tso; 8351 u32 tx_flags = 0; 8352 unsigned short f; 8353 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8354 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8355 __be16 protocol = skb->protocol; 8356 u8 hdr_len = 0; 8357 8358 /* 8359 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8360 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8361 * + 2 desc gap to keep tail from touching head, 8362 * + 1 desc for context descriptor, 8363 * otherwise try next time 8364 */ 8365 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8366 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8367 8368 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8369 tx_ring->tx_stats.tx_busy++; 8370 return NETDEV_TX_BUSY; 8371 } 8372 8373 /* record the location of the first descriptor for this packet */ 8374 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8375 first->skb = skb; 8376 first->bytecount = skb->len; 8377 first->gso_segs = 1; 8378 8379 /* if we have a HW VLAN tag being added default to the HW one */ 8380 if (skb_vlan_tag_present(skb)) { 8381 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8382 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8383 /* else if it is a SW VLAN check the next protocol and store the tag */ 8384 } else if (protocol == htons(ETH_P_8021Q)) { 8385 struct vlan_hdr *vhdr, _vhdr; 8386 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8387 if (!vhdr) 8388 goto out_drop; 8389 8390 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8391 IXGBE_TX_FLAGS_VLAN_SHIFT; 8392 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8393 } 8394 protocol = vlan_get_protocol(skb); 8395 8396 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8397 adapter->ptp_clock) { 8398 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8399 &adapter->state)) { 8400 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8401 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8402 8403 /* schedule check for Tx timestamp */ 8404 adapter->ptp_tx_skb = skb_get(skb); 8405 adapter->ptp_tx_start = jiffies; 8406 schedule_work(&adapter->ptp_tx_work); 8407 } else { 8408 adapter->tx_hwtstamp_skipped++; 8409 } 8410 } 8411 8412 skb_tx_timestamp(skb); 8413 8414 #ifdef CONFIG_PCI_IOV 8415 /* 8416 * Use the l2switch_enable flag - would be false if the DMA 8417 * Tx switch had been disabled. 8418 */ 8419 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8420 tx_flags |= IXGBE_TX_FLAGS_CC; 8421 8422 #endif 8423 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8424 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8425 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8426 (skb->priority != TC_PRIO_CONTROL))) { 8427 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8428 tx_flags |= (skb->priority & 0x7) << 8429 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8430 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8431 struct vlan_ethhdr *vhdr; 8432 8433 if (skb_cow_head(skb, 0)) 8434 goto out_drop; 8435 vhdr = (struct vlan_ethhdr *)skb->data; 8436 vhdr->h_vlan_TCI = htons(tx_flags >> 8437 IXGBE_TX_FLAGS_VLAN_SHIFT); 8438 } else { 8439 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8440 } 8441 } 8442 8443 /* record initial flags and protocol */ 8444 first->tx_flags = tx_flags; 8445 first->protocol = protocol; 8446 8447 #ifdef IXGBE_FCOE 8448 /* setup tx offload for FCoE */ 8449 if ((protocol == htons(ETH_P_FCOE)) && 8450 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8451 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8452 if (tso < 0) 8453 goto out_drop; 8454 8455 goto xmit_fcoe; 8456 } 8457 8458 #endif /* IXGBE_FCOE */ 8459 8460 #ifdef CONFIG_XFRM_OFFLOAD 8461 if (skb->sp && !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8462 goto out_drop; 8463 #endif 8464 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8465 if (tso < 0) 8466 goto out_drop; 8467 else if (!tso) 8468 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8469 8470 /* add the ATR filter if ATR is on */ 8471 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8472 ixgbe_atr(tx_ring, first); 8473 8474 #ifdef IXGBE_FCOE 8475 xmit_fcoe: 8476 #endif /* IXGBE_FCOE */ 8477 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8478 goto cleanup_tx_timestamp; 8479 8480 return NETDEV_TX_OK; 8481 8482 out_drop: 8483 dev_kfree_skb_any(first->skb); 8484 first->skb = NULL; 8485 cleanup_tx_timestamp: 8486 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8487 dev_kfree_skb_any(adapter->ptp_tx_skb); 8488 adapter->ptp_tx_skb = NULL; 8489 cancel_work_sync(&adapter->ptp_tx_work); 8490 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8491 } 8492 8493 return NETDEV_TX_OK; 8494 } 8495 8496 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8497 struct net_device *netdev, 8498 struct ixgbe_ring *ring) 8499 { 8500 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8501 struct ixgbe_ring *tx_ring; 8502 8503 /* 8504 * The minimum packet size for olinfo paylen is 17 so pad the skb 8505 * in order to meet this minimum size requirement. 8506 */ 8507 if (skb_put_padto(skb, 17)) 8508 return NETDEV_TX_OK; 8509 8510 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8511 8512 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8513 } 8514 8515 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8516 struct net_device *netdev) 8517 { 8518 return __ixgbe_xmit_frame(skb, netdev, NULL); 8519 } 8520 8521 /** 8522 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8523 * @netdev: network interface device structure 8524 * @p: pointer to an address structure 8525 * 8526 * Returns 0 on success, negative on failure 8527 **/ 8528 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8529 { 8530 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8531 struct ixgbe_hw *hw = &adapter->hw; 8532 struct sockaddr *addr = p; 8533 8534 if (!is_valid_ether_addr(addr->sa_data)) 8535 return -EADDRNOTAVAIL; 8536 8537 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8538 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8539 8540 ixgbe_mac_set_default_filter(adapter); 8541 8542 return 0; 8543 } 8544 8545 static int 8546 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8547 { 8548 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8549 struct ixgbe_hw *hw = &adapter->hw; 8550 u16 value; 8551 int rc; 8552 8553 if (prtad != hw->phy.mdio.prtad) 8554 return -EINVAL; 8555 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8556 if (!rc) 8557 rc = value; 8558 return rc; 8559 } 8560 8561 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8562 u16 addr, u16 value) 8563 { 8564 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8565 struct ixgbe_hw *hw = &adapter->hw; 8566 8567 if (prtad != hw->phy.mdio.prtad) 8568 return -EINVAL; 8569 return hw->phy.ops.write_reg(hw, addr, devad, value); 8570 } 8571 8572 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8573 { 8574 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8575 8576 switch (cmd) { 8577 case SIOCSHWTSTAMP: 8578 return ixgbe_ptp_set_ts_config(adapter, req); 8579 case SIOCGHWTSTAMP: 8580 return ixgbe_ptp_get_ts_config(adapter, req); 8581 case SIOCGMIIPHY: 8582 if (!adapter->hw.phy.ops.read_reg) 8583 return -EOPNOTSUPP; 8584 /* fall through */ 8585 default: 8586 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8587 } 8588 } 8589 8590 /** 8591 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8592 * netdev->dev_addrs 8593 * @dev: network interface device structure 8594 * 8595 * Returns non-zero on failure 8596 **/ 8597 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8598 { 8599 int err = 0; 8600 struct ixgbe_adapter *adapter = netdev_priv(dev); 8601 struct ixgbe_hw *hw = &adapter->hw; 8602 8603 if (is_valid_ether_addr(hw->mac.san_addr)) { 8604 rtnl_lock(); 8605 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8606 rtnl_unlock(); 8607 8608 /* update SAN MAC vmdq pool selection */ 8609 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8610 } 8611 return err; 8612 } 8613 8614 /** 8615 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8616 * netdev->dev_addrs 8617 * @dev: network interface device structure 8618 * 8619 * Returns non-zero on failure 8620 **/ 8621 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8622 { 8623 int err = 0; 8624 struct ixgbe_adapter *adapter = netdev_priv(dev); 8625 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8626 8627 if (is_valid_ether_addr(mac->san_addr)) { 8628 rtnl_lock(); 8629 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8630 rtnl_unlock(); 8631 } 8632 return err; 8633 } 8634 8635 #ifdef CONFIG_NET_POLL_CONTROLLER 8636 /* 8637 * Polling 'interrupt' - used by things like netconsole to send skbs 8638 * without having to re-enable interrupts. It's not called while 8639 * the interrupt routine is executing. 8640 */ 8641 static void ixgbe_netpoll(struct net_device *netdev) 8642 { 8643 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8644 int i; 8645 8646 /* if interface is down do nothing */ 8647 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8648 return; 8649 8650 /* loop through and schedule all active queues */ 8651 for (i = 0; i < adapter->num_q_vectors; i++) 8652 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8653 } 8654 8655 #endif 8656 8657 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8658 struct ixgbe_ring *ring) 8659 { 8660 u64 bytes, packets; 8661 unsigned int start; 8662 8663 if (ring) { 8664 do { 8665 start = u64_stats_fetch_begin_irq(&ring->syncp); 8666 packets = ring->stats.packets; 8667 bytes = ring->stats.bytes; 8668 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8669 stats->tx_packets += packets; 8670 stats->tx_bytes += bytes; 8671 } 8672 } 8673 8674 static void ixgbe_get_stats64(struct net_device *netdev, 8675 struct rtnl_link_stats64 *stats) 8676 { 8677 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8678 int i; 8679 8680 rcu_read_lock(); 8681 for (i = 0; i < adapter->num_rx_queues; i++) { 8682 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8683 u64 bytes, packets; 8684 unsigned int start; 8685 8686 if (ring) { 8687 do { 8688 start = u64_stats_fetch_begin_irq(&ring->syncp); 8689 packets = ring->stats.packets; 8690 bytes = ring->stats.bytes; 8691 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8692 stats->rx_packets += packets; 8693 stats->rx_bytes += bytes; 8694 } 8695 } 8696 8697 for (i = 0; i < adapter->num_tx_queues; i++) { 8698 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8699 8700 ixgbe_get_ring_stats64(stats, ring); 8701 } 8702 for (i = 0; i < adapter->num_xdp_queues; i++) { 8703 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8704 8705 ixgbe_get_ring_stats64(stats, ring); 8706 } 8707 rcu_read_unlock(); 8708 8709 /* following stats updated by ixgbe_watchdog_task() */ 8710 stats->multicast = netdev->stats.multicast; 8711 stats->rx_errors = netdev->stats.rx_errors; 8712 stats->rx_length_errors = netdev->stats.rx_length_errors; 8713 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8714 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8715 } 8716 8717 #ifdef CONFIG_IXGBE_DCB 8718 /** 8719 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8720 * @adapter: pointer to ixgbe_adapter 8721 * @tc: number of traffic classes currently enabled 8722 * 8723 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8724 * 802.1Q priority maps to a packet buffer that exists. 8725 */ 8726 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8727 { 8728 struct ixgbe_hw *hw = &adapter->hw; 8729 u32 reg, rsave; 8730 int i; 8731 8732 /* 82598 have a static priority to TC mapping that can not 8733 * be changed so no validation is needed. 8734 */ 8735 if (hw->mac.type == ixgbe_mac_82598EB) 8736 return; 8737 8738 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8739 rsave = reg; 8740 8741 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8742 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8743 8744 /* If up2tc is out of bounds default to zero */ 8745 if (up2tc > tc) 8746 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8747 } 8748 8749 if (reg != rsave) 8750 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8751 8752 return; 8753 } 8754 8755 /** 8756 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8757 * @adapter: Pointer to adapter struct 8758 * 8759 * Populate the netdev user priority to tc map 8760 */ 8761 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8762 { 8763 struct net_device *dev = adapter->netdev; 8764 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8765 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8766 u8 prio; 8767 8768 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8769 u8 tc = 0; 8770 8771 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8772 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8773 else if (ets) 8774 tc = ets->prio_tc[prio]; 8775 8776 netdev_set_prio_tc_map(dev, prio, tc); 8777 } 8778 } 8779 8780 #endif /* CONFIG_IXGBE_DCB */ 8781 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data) 8782 { 8783 struct ixgbe_adapter *adapter = data; 8784 struct ixgbe_fwd_adapter *accel; 8785 int pool; 8786 8787 /* we only care about macvlans... */ 8788 if (!netif_is_macvlan(vdev)) 8789 return 0; 8790 8791 /* that have hardware offload enabled... */ 8792 accel = macvlan_accel_priv(vdev); 8793 if (!accel) 8794 return 0; 8795 8796 /* If we can relocate to a different bit do so */ 8797 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 8798 if (pool < adapter->num_rx_pools) { 8799 set_bit(pool, adapter->fwd_bitmask); 8800 accel->pool = pool; 8801 return 0; 8802 } 8803 8804 /* if we cannot find a free pool then disable the offload */ 8805 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 8806 macvlan_release_l2fw_offload(vdev); 8807 kfree(accel); 8808 8809 return 0; 8810 } 8811 8812 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 8813 { 8814 struct ixgbe_adapter *adapter = netdev_priv(dev); 8815 8816 /* flush any stale bits out of the fwd bitmask */ 8817 bitmap_clear(adapter->fwd_bitmask, 1, 63); 8818 8819 /* walk through upper devices reassigning pools */ 8820 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 8821 adapter); 8822 } 8823 8824 /** 8825 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8826 * 8827 * @dev: net device to configure 8828 * @tc: number of traffic classes to enable 8829 */ 8830 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8831 { 8832 struct ixgbe_adapter *adapter = netdev_priv(dev); 8833 struct ixgbe_hw *hw = &adapter->hw; 8834 8835 /* Hardware supports up to 8 traffic classes */ 8836 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8837 return -EINVAL; 8838 8839 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8840 return -EINVAL; 8841 8842 /* Hardware has to reinitialize queues and interrupts to 8843 * match packet buffer alignment. Unfortunately, the 8844 * hardware is not flexible enough to do this dynamically. 8845 */ 8846 if (netif_running(dev)) 8847 ixgbe_close(dev); 8848 else 8849 ixgbe_reset(adapter); 8850 8851 ixgbe_clear_interrupt_scheme(adapter); 8852 8853 #ifdef CONFIG_IXGBE_DCB 8854 if (tc) { 8855 netdev_set_num_tc(dev, tc); 8856 ixgbe_set_prio_tc_map(adapter); 8857 8858 adapter->hw_tcs = tc; 8859 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8860 8861 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8862 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8863 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8864 } 8865 } else { 8866 netdev_reset_tc(dev); 8867 8868 /* To support macvlan offload we have to use num_tc to 8869 * restrict the queues that can be used by the device. 8870 * By doing this we can avoid reporting a false number of 8871 * queues. 8872 */ 8873 if (!tc && adapter->num_rx_pools > 1) 8874 netdev_set_num_tc(dev, 1); 8875 8876 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8877 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8878 8879 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8880 adapter->hw_tcs = tc; 8881 8882 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8883 adapter->dcb_cfg.pfc_mode_enable = false; 8884 } 8885 8886 ixgbe_validate_rtr(adapter, tc); 8887 8888 #endif /* CONFIG_IXGBE_DCB */ 8889 ixgbe_init_interrupt_scheme(adapter); 8890 8891 ixgbe_defrag_macvlan_pools(dev); 8892 8893 if (netif_running(dev)) 8894 return ixgbe_open(dev); 8895 8896 return 0; 8897 } 8898 8899 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8900 struct tc_cls_u32_offload *cls) 8901 { 8902 u32 hdl = cls->knode.handle; 8903 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8904 u32 loc = cls->knode.handle & 0xfffff; 8905 int err = 0, i, j; 8906 struct ixgbe_jump_table *jump = NULL; 8907 8908 if (loc > IXGBE_MAX_HW_ENTRIES) 8909 return -EINVAL; 8910 8911 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8912 return -EINVAL; 8913 8914 /* Clear this filter in the link data it is associated with */ 8915 if (uhtid != 0x800) { 8916 jump = adapter->jump_tables[uhtid]; 8917 if (!jump) 8918 return -EINVAL; 8919 if (!test_bit(loc - 1, jump->child_loc_map)) 8920 return -EINVAL; 8921 clear_bit(loc - 1, jump->child_loc_map); 8922 } 8923 8924 /* Check if the filter being deleted is a link */ 8925 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8926 jump = adapter->jump_tables[i]; 8927 if (jump && jump->link_hdl == hdl) { 8928 /* Delete filters in the hardware in the child hash 8929 * table associated with this link 8930 */ 8931 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8932 if (!test_bit(j, jump->child_loc_map)) 8933 continue; 8934 spin_lock(&adapter->fdir_perfect_lock); 8935 err = ixgbe_update_ethtool_fdir_entry(adapter, 8936 NULL, 8937 j + 1); 8938 spin_unlock(&adapter->fdir_perfect_lock); 8939 clear_bit(j, jump->child_loc_map); 8940 } 8941 /* Remove resources for this link */ 8942 kfree(jump->input); 8943 kfree(jump->mask); 8944 kfree(jump); 8945 adapter->jump_tables[i] = NULL; 8946 return err; 8947 } 8948 } 8949 8950 spin_lock(&adapter->fdir_perfect_lock); 8951 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8952 spin_unlock(&adapter->fdir_perfect_lock); 8953 return err; 8954 } 8955 8956 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8957 struct tc_cls_u32_offload *cls) 8958 { 8959 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8960 8961 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8962 return -EINVAL; 8963 8964 /* This ixgbe devices do not support hash tables at the moment 8965 * so abort when given hash tables. 8966 */ 8967 if (cls->hnode.divisor > 0) 8968 return -EINVAL; 8969 8970 set_bit(uhtid - 1, &adapter->tables); 8971 return 0; 8972 } 8973 8974 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8975 struct tc_cls_u32_offload *cls) 8976 { 8977 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8978 8979 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8980 return -EINVAL; 8981 8982 clear_bit(uhtid - 1, &adapter->tables); 8983 return 0; 8984 } 8985 8986 #ifdef CONFIG_NET_CLS_ACT 8987 struct upper_walk_data { 8988 struct ixgbe_adapter *adapter; 8989 u64 action; 8990 int ifindex; 8991 u8 queue; 8992 }; 8993 8994 static int get_macvlan_queue(struct net_device *upper, void *_data) 8995 { 8996 if (netif_is_macvlan(upper)) { 8997 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 8998 struct upper_walk_data *data = _data; 8999 struct ixgbe_adapter *adapter = data->adapter; 9000 int ifindex = data->ifindex; 9001 9002 if (vadapter && upper->ifindex == ifindex) { 9003 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9004 data->action = data->queue; 9005 return 1; 9006 } 9007 } 9008 9009 return 0; 9010 } 9011 9012 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9013 u8 *queue, u64 *action) 9014 { 9015 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9016 unsigned int num_vfs = adapter->num_vfs, vf; 9017 struct upper_walk_data data; 9018 struct net_device *upper; 9019 9020 /* redirect to a SRIOV VF */ 9021 for (vf = 0; vf < num_vfs; ++vf) { 9022 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9023 if (upper->ifindex == ifindex) { 9024 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9025 *action = vf + 1; 9026 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9027 return 0; 9028 } 9029 } 9030 9031 /* redirect to a offloaded macvlan netdev */ 9032 data.adapter = adapter; 9033 data.ifindex = ifindex; 9034 data.action = 0; 9035 data.queue = 0; 9036 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9037 get_macvlan_queue, &data)) { 9038 *action = data.action; 9039 *queue = data.queue; 9040 9041 return 0; 9042 } 9043 9044 return -EINVAL; 9045 } 9046 9047 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9048 struct tcf_exts *exts, u64 *action, u8 *queue) 9049 { 9050 const struct tc_action *a; 9051 LIST_HEAD(actions); 9052 int err; 9053 9054 if (!tcf_exts_has_actions(exts)) 9055 return -EINVAL; 9056 9057 tcf_exts_to_list(exts, &actions); 9058 list_for_each_entry(a, &actions, list) { 9059 9060 /* Drop action */ 9061 if (is_tcf_gact_shot(a)) { 9062 *action = IXGBE_FDIR_DROP_QUEUE; 9063 *queue = IXGBE_FDIR_DROP_QUEUE; 9064 return 0; 9065 } 9066 9067 /* Redirect to a VF or a offloaded macvlan */ 9068 if (is_tcf_mirred_egress_redirect(a)) { 9069 struct net_device *dev = tcf_mirred_dev(a); 9070 9071 if (!dev) 9072 return -EINVAL; 9073 err = handle_redirect_action(adapter, dev->ifindex, queue, 9074 action); 9075 if (err == 0) 9076 return err; 9077 } 9078 } 9079 9080 return -EINVAL; 9081 } 9082 #else 9083 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9084 struct tcf_exts *exts, u64 *action, u8 *queue) 9085 { 9086 return -EINVAL; 9087 } 9088 #endif /* CONFIG_NET_CLS_ACT */ 9089 9090 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9091 union ixgbe_atr_input *mask, 9092 struct tc_cls_u32_offload *cls, 9093 struct ixgbe_mat_field *field_ptr, 9094 struct ixgbe_nexthdr *nexthdr) 9095 { 9096 int i, j, off; 9097 __be32 val, m; 9098 bool found_entry = false, found_jump_field = false; 9099 9100 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9101 off = cls->knode.sel->keys[i].off; 9102 val = cls->knode.sel->keys[i].val; 9103 m = cls->knode.sel->keys[i].mask; 9104 9105 for (j = 0; field_ptr[j].val; j++) { 9106 if (field_ptr[j].off == off) { 9107 field_ptr[j].val(input, mask, (__force u32)val, 9108 (__force u32)m); 9109 input->filter.formatted.flow_type |= 9110 field_ptr[j].type; 9111 found_entry = true; 9112 break; 9113 } 9114 } 9115 if (nexthdr) { 9116 if (nexthdr->off == cls->knode.sel->keys[i].off && 9117 nexthdr->val == 9118 (__force u32)cls->knode.sel->keys[i].val && 9119 nexthdr->mask == 9120 (__force u32)cls->knode.sel->keys[i].mask) 9121 found_jump_field = true; 9122 else 9123 continue; 9124 } 9125 } 9126 9127 if (nexthdr && !found_jump_field) 9128 return -EINVAL; 9129 9130 if (!found_entry) 9131 return 0; 9132 9133 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9134 IXGBE_ATR_L4TYPE_MASK; 9135 9136 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9137 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9138 9139 return 0; 9140 } 9141 9142 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9143 struct tc_cls_u32_offload *cls) 9144 { 9145 __be16 protocol = cls->common.protocol; 9146 u32 loc = cls->knode.handle & 0xfffff; 9147 struct ixgbe_hw *hw = &adapter->hw; 9148 struct ixgbe_mat_field *field_ptr; 9149 struct ixgbe_fdir_filter *input = NULL; 9150 union ixgbe_atr_input *mask = NULL; 9151 struct ixgbe_jump_table *jump = NULL; 9152 int i, err = -EINVAL; 9153 u8 queue; 9154 u32 uhtid, link_uhtid; 9155 9156 uhtid = TC_U32_USERHTID(cls->knode.handle); 9157 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9158 9159 /* At the moment cls_u32 jumps to network layer and skips past 9160 * L2 headers. The canonical method to match L2 frames is to use 9161 * negative values. However this is error prone at best but really 9162 * just broken because there is no way to "know" what sort of hdr 9163 * is in front of the network layer. Fix cls_u32 to support L2 9164 * headers when needed. 9165 */ 9166 if (protocol != htons(ETH_P_IP)) 9167 return err; 9168 9169 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9170 e_err(drv, "Location out of range\n"); 9171 return err; 9172 } 9173 9174 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9175 * links and also the fields used to advance the parser across each 9176 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9177 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9178 * To add support for new nodes update ixgbe_model.h parse structures 9179 * this function _should_ be generic try not to hardcode values here. 9180 */ 9181 if (uhtid == 0x800) { 9182 field_ptr = (adapter->jump_tables[0])->mat; 9183 } else { 9184 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9185 return err; 9186 if (!adapter->jump_tables[uhtid]) 9187 return err; 9188 field_ptr = (adapter->jump_tables[uhtid])->mat; 9189 } 9190 9191 if (!field_ptr) 9192 return err; 9193 9194 /* At this point we know the field_ptr is valid and need to either 9195 * build cls_u32 link or attach filter. Because adding a link to 9196 * a handle that does not exist is invalid and the same for adding 9197 * rules to handles that don't exist. 9198 */ 9199 9200 if (link_uhtid) { 9201 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9202 9203 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9204 return err; 9205 9206 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9207 return err; 9208 9209 /* Multiple filters as links to the same hash table are not 9210 * supported. To add a new filter with the same next header 9211 * but different match/jump conditions, create a new hash table 9212 * and link to it. 9213 */ 9214 if (adapter->jump_tables[link_uhtid] && 9215 (adapter->jump_tables[link_uhtid])->link_hdl) { 9216 e_err(drv, "Link filter exists for link: %x\n", 9217 link_uhtid); 9218 return err; 9219 } 9220 9221 for (i = 0; nexthdr[i].jump; i++) { 9222 if (nexthdr[i].o != cls->knode.sel->offoff || 9223 nexthdr[i].s != cls->knode.sel->offshift || 9224 nexthdr[i].m != 9225 (__force u32)cls->knode.sel->offmask) 9226 return err; 9227 9228 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9229 if (!jump) 9230 return -ENOMEM; 9231 input = kzalloc(sizeof(*input), GFP_KERNEL); 9232 if (!input) { 9233 err = -ENOMEM; 9234 goto free_jump; 9235 } 9236 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9237 if (!mask) { 9238 err = -ENOMEM; 9239 goto free_input; 9240 } 9241 jump->input = input; 9242 jump->mask = mask; 9243 jump->link_hdl = cls->knode.handle; 9244 9245 err = ixgbe_clsu32_build_input(input, mask, cls, 9246 field_ptr, &nexthdr[i]); 9247 if (!err) { 9248 jump->mat = nexthdr[i].jump; 9249 adapter->jump_tables[link_uhtid] = jump; 9250 break; 9251 } 9252 } 9253 return 0; 9254 } 9255 9256 input = kzalloc(sizeof(*input), GFP_KERNEL); 9257 if (!input) 9258 return -ENOMEM; 9259 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9260 if (!mask) { 9261 err = -ENOMEM; 9262 goto free_input; 9263 } 9264 9265 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9266 if ((adapter->jump_tables[uhtid])->input) 9267 memcpy(input, (adapter->jump_tables[uhtid])->input, 9268 sizeof(*input)); 9269 if ((adapter->jump_tables[uhtid])->mask) 9270 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9271 sizeof(*mask)); 9272 9273 /* Lookup in all child hash tables if this location is already 9274 * filled with a filter 9275 */ 9276 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9277 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9278 9279 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9280 e_err(drv, "Filter exists in location: %x\n", 9281 loc); 9282 err = -EINVAL; 9283 goto err_out; 9284 } 9285 } 9286 } 9287 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9288 if (err) 9289 goto err_out; 9290 9291 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9292 &queue); 9293 if (err < 0) 9294 goto err_out; 9295 9296 input->sw_idx = loc; 9297 9298 spin_lock(&adapter->fdir_perfect_lock); 9299 9300 if (hlist_empty(&adapter->fdir_filter_list)) { 9301 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9302 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9303 if (err) 9304 goto err_out_w_lock; 9305 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9306 err = -EINVAL; 9307 goto err_out_w_lock; 9308 } 9309 9310 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9311 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9312 input->sw_idx, queue); 9313 if (!err) 9314 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9315 spin_unlock(&adapter->fdir_perfect_lock); 9316 9317 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9318 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9319 9320 kfree(mask); 9321 return err; 9322 err_out_w_lock: 9323 spin_unlock(&adapter->fdir_perfect_lock); 9324 err_out: 9325 kfree(mask); 9326 free_input: 9327 kfree(input); 9328 free_jump: 9329 kfree(jump); 9330 return err; 9331 } 9332 9333 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9334 struct tc_cls_u32_offload *cls_u32) 9335 { 9336 switch (cls_u32->command) { 9337 case TC_CLSU32_NEW_KNODE: 9338 case TC_CLSU32_REPLACE_KNODE: 9339 return ixgbe_configure_clsu32(adapter, cls_u32); 9340 case TC_CLSU32_DELETE_KNODE: 9341 return ixgbe_delete_clsu32(adapter, cls_u32); 9342 case TC_CLSU32_NEW_HNODE: 9343 case TC_CLSU32_REPLACE_HNODE: 9344 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9345 case TC_CLSU32_DELETE_HNODE: 9346 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9347 default: 9348 return -EOPNOTSUPP; 9349 } 9350 } 9351 9352 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9353 void *cb_priv) 9354 { 9355 struct ixgbe_adapter *adapter = cb_priv; 9356 9357 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9358 return -EOPNOTSUPP; 9359 9360 switch (type) { 9361 case TC_SETUP_CLSU32: 9362 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9363 default: 9364 return -EOPNOTSUPP; 9365 } 9366 } 9367 9368 static int ixgbe_setup_tc_block(struct net_device *dev, 9369 struct tc_block_offload *f) 9370 { 9371 struct ixgbe_adapter *adapter = netdev_priv(dev); 9372 9373 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9374 return -EOPNOTSUPP; 9375 9376 switch (f->command) { 9377 case TC_BLOCK_BIND: 9378 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9379 adapter, adapter); 9380 case TC_BLOCK_UNBIND: 9381 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9382 adapter); 9383 return 0; 9384 default: 9385 return -EOPNOTSUPP; 9386 } 9387 } 9388 9389 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9390 struct tc_mqprio_qopt *mqprio) 9391 { 9392 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9393 return ixgbe_setup_tc(dev, mqprio->num_tc); 9394 } 9395 9396 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9397 void *type_data) 9398 { 9399 switch (type) { 9400 case TC_SETUP_BLOCK: 9401 return ixgbe_setup_tc_block(dev, type_data); 9402 case TC_SETUP_QDISC_MQPRIO: 9403 return ixgbe_setup_tc_mqprio(dev, type_data); 9404 default: 9405 return -EOPNOTSUPP; 9406 } 9407 } 9408 9409 #ifdef CONFIG_PCI_IOV 9410 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9411 { 9412 struct net_device *netdev = adapter->netdev; 9413 9414 rtnl_lock(); 9415 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9416 rtnl_unlock(); 9417 } 9418 9419 #endif 9420 void ixgbe_do_reset(struct net_device *netdev) 9421 { 9422 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9423 9424 if (netif_running(netdev)) 9425 ixgbe_reinit_locked(adapter); 9426 else 9427 ixgbe_reset(adapter); 9428 } 9429 9430 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9431 netdev_features_t features) 9432 { 9433 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9434 9435 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9436 if (!(features & NETIF_F_RXCSUM)) 9437 features &= ~NETIF_F_LRO; 9438 9439 /* Turn off LRO if not RSC capable */ 9440 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9441 features &= ~NETIF_F_LRO; 9442 9443 return features; 9444 } 9445 9446 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9447 { 9448 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9449 num_online_cpus()); 9450 9451 /* go back to full RSS if we're not running SR-IOV */ 9452 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9453 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9454 IXGBE_FLAG_SRIOV_ENABLED); 9455 9456 adapter->ring_feature[RING_F_RSS].limit = rss; 9457 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9458 9459 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9460 } 9461 9462 static int ixgbe_set_features(struct net_device *netdev, 9463 netdev_features_t features) 9464 { 9465 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9466 netdev_features_t changed = netdev->features ^ features; 9467 bool need_reset = false; 9468 9469 /* Make sure RSC matches LRO, reset if change */ 9470 if (!(features & NETIF_F_LRO)) { 9471 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9472 need_reset = true; 9473 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9474 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9475 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9476 if (adapter->rx_itr_setting == 1 || 9477 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9478 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9479 need_reset = true; 9480 } else if ((changed ^ features) & NETIF_F_LRO) { 9481 e_info(probe, "rx-usecs set too low, " 9482 "disabling RSC\n"); 9483 } 9484 } 9485 9486 /* 9487 * Check if Flow Director n-tuple support or hw_tc support was 9488 * enabled or disabled. If the state changed, we need to reset. 9489 */ 9490 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9491 /* turn off ATR, enable perfect filters and reset */ 9492 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9493 need_reset = true; 9494 9495 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9496 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9497 } else { 9498 /* turn off perfect filters, enable ATR and reset */ 9499 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9500 need_reset = true; 9501 9502 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9503 9504 /* We cannot enable ATR if SR-IOV is enabled */ 9505 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9506 /* We cannot enable ATR if we have 2 or more tcs */ 9507 (adapter->hw_tcs > 1) || 9508 /* We cannot enable ATR if RSS is disabled */ 9509 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9510 /* A sample rate of 0 indicates ATR disabled */ 9511 (!adapter->atr_sample_rate)) 9512 ; /* do nothing not supported */ 9513 else /* otherwise supported and set the flag */ 9514 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9515 } 9516 9517 if (changed & NETIF_F_RXALL) 9518 need_reset = true; 9519 9520 netdev->features = features; 9521 9522 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9523 if (features & NETIF_F_RXCSUM) { 9524 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9525 } else { 9526 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9527 9528 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9529 } 9530 } 9531 9532 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9533 if (features & NETIF_F_RXCSUM) { 9534 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9535 } else { 9536 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9537 9538 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9539 } 9540 } 9541 9542 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9543 ixgbe_reset_l2fw_offload(adapter); 9544 else if (need_reset) 9545 ixgbe_do_reset(netdev); 9546 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9547 NETIF_F_HW_VLAN_CTAG_FILTER)) 9548 ixgbe_set_rx_mode(netdev); 9549 9550 return 0; 9551 } 9552 9553 /** 9554 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9555 * @dev: The port's netdev 9556 * @ti: Tunnel endpoint information 9557 **/ 9558 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9559 struct udp_tunnel_info *ti) 9560 { 9561 struct ixgbe_adapter *adapter = netdev_priv(dev); 9562 struct ixgbe_hw *hw = &adapter->hw; 9563 __be16 port = ti->port; 9564 u32 port_shift = 0; 9565 u32 reg; 9566 9567 if (ti->sa_family != AF_INET) 9568 return; 9569 9570 switch (ti->type) { 9571 case UDP_TUNNEL_TYPE_VXLAN: 9572 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9573 return; 9574 9575 if (adapter->vxlan_port == port) 9576 return; 9577 9578 if (adapter->vxlan_port) { 9579 netdev_info(dev, 9580 "VXLAN port %d set, not adding port %d\n", 9581 ntohs(adapter->vxlan_port), 9582 ntohs(port)); 9583 return; 9584 } 9585 9586 adapter->vxlan_port = port; 9587 break; 9588 case UDP_TUNNEL_TYPE_GENEVE: 9589 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9590 return; 9591 9592 if (adapter->geneve_port == port) 9593 return; 9594 9595 if (adapter->geneve_port) { 9596 netdev_info(dev, 9597 "GENEVE port %d set, not adding port %d\n", 9598 ntohs(adapter->geneve_port), 9599 ntohs(port)); 9600 return; 9601 } 9602 9603 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9604 adapter->geneve_port = port; 9605 break; 9606 default: 9607 return; 9608 } 9609 9610 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9611 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9612 } 9613 9614 /** 9615 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9616 * @dev: The port's netdev 9617 * @ti: Tunnel endpoint information 9618 **/ 9619 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9620 struct udp_tunnel_info *ti) 9621 { 9622 struct ixgbe_adapter *adapter = netdev_priv(dev); 9623 u32 port_mask; 9624 9625 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9626 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9627 return; 9628 9629 if (ti->sa_family != AF_INET) 9630 return; 9631 9632 switch (ti->type) { 9633 case UDP_TUNNEL_TYPE_VXLAN: 9634 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9635 return; 9636 9637 if (adapter->vxlan_port != ti->port) { 9638 netdev_info(dev, "VXLAN port %d not found\n", 9639 ntohs(ti->port)); 9640 return; 9641 } 9642 9643 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9644 break; 9645 case UDP_TUNNEL_TYPE_GENEVE: 9646 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9647 return; 9648 9649 if (adapter->geneve_port != ti->port) { 9650 netdev_info(dev, "GENEVE port %d not found\n", 9651 ntohs(ti->port)); 9652 return; 9653 } 9654 9655 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9656 break; 9657 default: 9658 return; 9659 } 9660 9661 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9662 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9663 } 9664 9665 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9666 struct net_device *dev, 9667 const unsigned char *addr, u16 vid, 9668 u16 flags) 9669 { 9670 /* guarantee we can provide a unique filter for the unicast address */ 9671 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9672 struct ixgbe_adapter *adapter = netdev_priv(dev); 9673 u16 pool = VMDQ_P(0); 9674 9675 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9676 return -ENOMEM; 9677 } 9678 9679 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9680 } 9681 9682 /** 9683 * ixgbe_configure_bridge_mode - set various bridge modes 9684 * @adapter: the private structure 9685 * @mode: requested bridge mode 9686 * 9687 * Configure some settings require for various bridge modes. 9688 **/ 9689 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9690 __u16 mode) 9691 { 9692 struct ixgbe_hw *hw = &adapter->hw; 9693 unsigned int p, num_pools; 9694 u32 vmdctl; 9695 9696 switch (mode) { 9697 case BRIDGE_MODE_VEPA: 9698 /* disable Tx loopback, rely on switch hairpin mode */ 9699 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9700 9701 /* must enable Rx switching replication to allow multicast 9702 * packet reception on all VFs, and to enable source address 9703 * pruning. 9704 */ 9705 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9706 vmdctl |= IXGBE_VT_CTL_REPLEN; 9707 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9708 9709 /* enable Rx source address pruning. Note, this requires 9710 * replication to be enabled or else it does nothing. 9711 */ 9712 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9713 for (p = 0; p < num_pools; p++) { 9714 if (hw->mac.ops.set_source_address_pruning) 9715 hw->mac.ops.set_source_address_pruning(hw, 9716 true, 9717 p); 9718 } 9719 break; 9720 case BRIDGE_MODE_VEB: 9721 /* enable Tx loopback for internal VF/PF communication */ 9722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9723 IXGBE_PFDTXGSWC_VT_LBEN); 9724 9725 /* disable Rx switching replication unless we have SR-IOV 9726 * virtual functions 9727 */ 9728 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9729 if (!adapter->num_vfs) 9730 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9731 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9732 9733 /* disable Rx source address pruning, since we don't expect to 9734 * be receiving external loopback of our transmitted frames. 9735 */ 9736 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9737 for (p = 0; p < num_pools; p++) { 9738 if (hw->mac.ops.set_source_address_pruning) 9739 hw->mac.ops.set_source_address_pruning(hw, 9740 false, 9741 p); 9742 } 9743 break; 9744 default: 9745 return -EINVAL; 9746 } 9747 9748 adapter->bridge_mode = mode; 9749 9750 e_info(drv, "enabling bridge mode: %s\n", 9751 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9752 9753 return 0; 9754 } 9755 9756 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9757 struct nlmsghdr *nlh, u16 flags) 9758 { 9759 struct ixgbe_adapter *adapter = netdev_priv(dev); 9760 struct nlattr *attr, *br_spec; 9761 int rem; 9762 9763 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9764 return -EOPNOTSUPP; 9765 9766 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9767 if (!br_spec) 9768 return -EINVAL; 9769 9770 nla_for_each_nested(attr, br_spec, rem) { 9771 int status; 9772 __u16 mode; 9773 9774 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9775 continue; 9776 9777 if (nla_len(attr) < sizeof(mode)) 9778 return -EINVAL; 9779 9780 mode = nla_get_u16(attr); 9781 status = ixgbe_configure_bridge_mode(adapter, mode); 9782 if (status) 9783 return status; 9784 9785 break; 9786 } 9787 9788 return 0; 9789 } 9790 9791 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9792 struct net_device *dev, 9793 u32 filter_mask, int nlflags) 9794 { 9795 struct ixgbe_adapter *adapter = netdev_priv(dev); 9796 9797 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9798 return 0; 9799 9800 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9801 adapter->bridge_mode, 0, 0, nlflags, 9802 filter_mask, NULL); 9803 } 9804 9805 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9806 { 9807 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9808 struct ixgbe_fwd_adapter *accel; 9809 int tcs = adapter->hw_tcs ? : 1; 9810 int pool, err; 9811 9812 /* The hardware supported by ixgbe only filters on the destination MAC 9813 * address. In order to avoid issues we only support offloading modes 9814 * where the hardware can actually provide the functionality. 9815 */ 9816 if (!macvlan_supports_dest_filter(vdev)) 9817 return ERR_PTR(-EMEDIUMTYPE); 9818 9819 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9820 if (pool == adapter->num_rx_pools) { 9821 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 9822 u16 reserved_pools; 9823 9824 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9825 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 9826 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 9827 return ERR_PTR(-EBUSY); 9828 9829 /* Hardware has a limited number of available pools. Each VF, 9830 * and the PF require a pool. Check to ensure we don't 9831 * attempt to use more then the available number of pools. 9832 */ 9833 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9834 return ERR_PTR(-EBUSY); 9835 9836 /* Enable VMDq flag so device will be set in VM mode */ 9837 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 9838 IXGBE_FLAG_SRIOV_ENABLED; 9839 9840 /* Try to reserve as many queues per pool as possible, 9841 * we start with the configurations that support 4 queues 9842 * per pools, followed by 2, and then by just 1 per pool. 9843 */ 9844 if (used_pools < 32 && adapter->num_rx_pools < 16) 9845 reserved_pools = min_t(u16, 9846 32 - used_pools, 9847 16 - adapter->num_rx_pools); 9848 else if (adapter->num_rx_pools < 32) 9849 reserved_pools = min_t(u16, 9850 64 - used_pools, 9851 32 - adapter->num_rx_pools); 9852 else 9853 reserved_pools = 64 - used_pools; 9854 9855 9856 if (!reserved_pools) 9857 return ERR_PTR(-EBUSY); 9858 9859 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 9860 9861 /* Force reinit of ring allocation with VMDQ enabled */ 9862 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 9863 if (err) 9864 return ERR_PTR(err); 9865 9866 if (pool >= adapter->num_rx_pools) 9867 return ERR_PTR(-ENOMEM); 9868 } 9869 9870 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 9871 if (!accel) 9872 return ERR_PTR(-ENOMEM); 9873 9874 set_bit(pool, adapter->fwd_bitmask); 9875 accel->pool = pool; 9876 accel->netdev = vdev; 9877 9878 if (!netif_running(pdev)) 9879 return accel; 9880 9881 err = ixgbe_fwd_ring_up(adapter, accel); 9882 if (err) 9883 return ERR_PTR(err); 9884 9885 return accel; 9886 } 9887 9888 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9889 { 9890 struct ixgbe_fwd_adapter *accel = priv; 9891 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9892 unsigned int rxbase = accel->rx_base_queue; 9893 unsigned int i; 9894 9895 /* delete unicast filter associated with offloaded interface */ 9896 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 9897 VMDQ_P(accel->pool)); 9898 9899 /* Allow remaining Rx packets to get flushed out of the 9900 * Rx FIFO before we drop the netdev for the ring. 9901 */ 9902 usleep_range(10000, 20000); 9903 9904 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 9905 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 9906 struct ixgbe_q_vector *qv = ring->q_vector; 9907 9908 /* Make sure we aren't processing any packets and clear 9909 * netdev to shut down the ring. 9910 */ 9911 if (netif_running(adapter->netdev)) 9912 napi_synchronize(&qv->napi); 9913 ring->netdev = NULL; 9914 } 9915 9916 clear_bit(accel->pool, adapter->fwd_bitmask); 9917 kfree(accel); 9918 } 9919 9920 #define IXGBE_MAX_MAC_HDR_LEN 127 9921 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9922 9923 static netdev_features_t 9924 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9925 netdev_features_t features) 9926 { 9927 unsigned int network_hdr_len, mac_hdr_len; 9928 9929 /* Make certain the headers can be described by a context descriptor */ 9930 mac_hdr_len = skb_network_header(skb) - skb->data; 9931 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9932 return features & ~(NETIF_F_HW_CSUM | 9933 NETIF_F_SCTP_CRC | 9934 NETIF_F_HW_VLAN_CTAG_TX | 9935 NETIF_F_TSO | 9936 NETIF_F_TSO6); 9937 9938 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9939 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9940 return features & ~(NETIF_F_HW_CSUM | 9941 NETIF_F_SCTP_CRC | 9942 NETIF_F_TSO | 9943 NETIF_F_TSO6); 9944 9945 /* We can only support IPV4 TSO in tunnels if we can mangle the 9946 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9947 * IPsec offoad sets skb->encapsulation but still can handle 9948 * the TSO, so it's the exception. 9949 */ 9950 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 9951 #ifdef CONFIG_XFRM 9952 if (!skb->sp) 9953 #endif 9954 features &= ~NETIF_F_TSO; 9955 } 9956 9957 return features; 9958 } 9959 9960 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9961 { 9962 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9963 struct ixgbe_adapter *adapter = netdev_priv(dev); 9964 struct bpf_prog *old_prog; 9965 9966 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9967 return -EINVAL; 9968 9969 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9970 return -EINVAL; 9971 9972 /* verify ixgbe ring attributes are sufficient for XDP */ 9973 for (i = 0; i < adapter->num_rx_queues; i++) { 9974 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9975 9976 if (ring_is_rsc_enabled(ring)) 9977 return -EINVAL; 9978 9979 if (frame_size > ixgbe_rx_bufsz(ring)) 9980 return -EINVAL; 9981 } 9982 9983 if (nr_cpu_ids > MAX_XDP_QUEUES) 9984 return -ENOMEM; 9985 9986 old_prog = xchg(&adapter->xdp_prog, prog); 9987 9988 /* If transitioning XDP modes reconfigure rings */ 9989 if (!!prog != !!old_prog) { 9990 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 9991 9992 if (err) { 9993 rcu_assign_pointer(adapter->xdp_prog, old_prog); 9994 return -EINVAL; 9995 } 9996 } else { 9997 for (i = 0; i < adapter->num_rx_queues; i++) 9998 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 9999 adapter->xdp_prog); 10000 } 10001 10002 if (old_prog) 10003 bpf_prog_put(old_prog); 10004 10005 return 0; 10006 } 10007 10008 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10009 { 10010 struct ixgbe_adapter *adapter = netdev_priv(dev); 10011 10012 switch (xdp->command) { 10013 case XDP_SETUP_PROG: 10014 return ixgbe_xdp_setup(dev, xdp->prog); 10015 case XDP_QUERY_PROG: 10016 xdp->prog_attached = !!(adapter->xdp_prog); 10017 xdp->prog_id = adapter->xdp_prog ? 10018 adapter->xdp_prog->aux->id : 0; 10019 return 0; 10020 default: 10021 return -EINVAL; 10022 } 10023 } 10024 10025 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10026 struct xdp_frame **frames) 10027 { 10028 struct ixgbe_adapter *adapter = netdev_priv(dev); 10029 struct ixgbe_ring *ring; 10030 int drops = 0; 10031 int i; 10032 10033 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10034 return -ENETDOWN; 10035 10036 /* During program transitions its possible adapter->xdp_prog is assigned 10037 * but ring has not been configured yet. In this case simply abort xmit. 10038 */ 10039 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10040 if (unlikely(!ring)) 10041 return -ENXIO; 10042 10043 for (i = 0; i < n; i++) { 10044 struct xdp_frame *xdpf = frames[i]; 10045 int err; 10046 10047 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10048 if (err != IXGBE_XDP_TX) { 10049 xdp_return_frame_rx_napi(xdpf); 10050 drops++; 10051 } 10052 } 10053 10054 return n - drops; 10055 } 10056 10057 static void ixgbe_xdp_flush(struct net_device *dev) 10058 { 10059 struct ixgbe_adapter *adapter = netdev_priv(dev); 10060 struct ixgbe_ring *ring; 10061 10062 /* Its possible the device went down between xdp xmit and flush so 10063 * we need to ensure device is still up. 10064 */ 10065 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10066 return; 10067 10068 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10069 if (unlikely(!ring)) 10070 return; 10071 10072 /* Force memory writes to complete before letting h/w know there 10073 * are new descriptors to fetch. 10074 */ 10075 wmb(); 10076 writel(ring->next_to_use, ring->tail); 10077 10078 return; 10079 } 10080 10081 static const struct net_device_ops ixgbe_netdev_ops = { 10082 .ndo_open = ixgbe_open, 10083 .ndo_stop = ixgbe_close, 10084 .ndo_start_xmit = ixgbe_xmit_frame, 10085 .ndo_select_queue = ixgbe_select_queue, 10086 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10087 .ndo_validate_addr = eth_validate_addr, 10088 .ndo_set_mac_address = ixgbe_set_mac, 10089 .ndo_change_mtu = ixgbe_change_mtu, 10090 .ndo_tx_timeout = ixgbe_tx_timeout, 10091 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10092 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10093 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10094 .ndo_do_ioctl = ixgbe_ioctl, 10095 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10096 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10097 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10098 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10099 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10100 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10101 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10102 .ndo_get_stats64 = ixgbe_get_stats64, 10103 .ndo_setup_tc = __ixgbe_setup_tc, 10104 #ifdef CONFIG_NET_POLL_CONTROLLER 10105 .ndo_poll_controller = ixgbe_netpoll, 10106 #endif 10107 #ifdef IXGBE_FCOE 10108 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10109 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10110 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10111 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10112 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10113 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10114 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10115 #endif /* IXGBE_FCOE */ 10116 .ndo_set_features = ixgbe_set_features, 10117 .ndo_fix_features = ixgbe_fix_features, 10118 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10119 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10120 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10121 .ndo_dfwd_add_station = ixgbe_fwd_add, 10122 .ndo_dfwd_del_station = ixgbe_fwd_del, 10123 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10124 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10125 .ndo_features_check = ixgbe_features_check, 10126 .ndo_bpf = ixgbe_xdp, 10127 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10128 .ndo_xdp_flush = ixgbe_xdp_flush, 10129 }; 10130 10131 /** 10132 * ixgbe_enumerate_functions - Get the number of ports this device has 10133 * @adapter: adapter structure 10134 * 10135 * This function enumerates the phsyical functions co-located on a single slot, 10136 * in order to determine how many ports a device has. This is most useful in 10137 * determining the required GT/s of PCIe bandwidth necessary for optimal 10138 * performance. 10139 **/ 10140 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10141 { 10142 struct pci_dev *entry, *pdev = adapter->pdev; 10143 int physfns = 0; 10144 10145 /* Some cards can not use the generic count PCIe functions method, 10146 * because they are behind a parent switch, so we hardcode these with 10147 * the correct number of functions. 10148 */ 10149 if (ixgbe_pcie_from_parent(&adapter->hw)) 10150 physfns = 4; 10151 10152 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10153 /* don't count virtual functions */ 10154 if (entry->is_virtfn) 10155 continue; 10156 10157 /* When the devices on the bus don't all match our device ID, 10158 * we can't reliably determine the correct number of 10159 * functions. This can occur if a function has been direct 10160 * attached to a virtual machine using VT-d, for example. In 10161 * this case, simply return -1 to indicate this. 10162 */ 10163 if ((entry->vendor != pdev->vendor) || 10164 (entry->device != pdev->device)) 10165 return -1; 10166 10167 physfns++; 10168 } 10169 10170 return physfns; 10171 } 10172 10173 /** 10174 * ixgbe_wol_supported - Check whether device supports WoL 10175 * @adapter: the adapter private structure 10176 * @device_id: the device ID 10177 * @subdevice_id: the subsystem device ID 10178 * 10179 * This function is used by probe and ethtool to determine 10180 * which devices have WoL support 10181 * 10182 **/ 10183 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10184 u16 subdevice_id) 10185 { 10186 struct ixgbe_hw *hw = &adapter->hw; 10187 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10188 10189 /* WOL not supported on 82598 */ 10190 if (hw->mac.type == ixgbe_mac_82598EB) 10191 return false; 10192 10193 /* check eeprom to see if WOL is enabled for X540 and newer */ 10194 if (hw->mac.type >= ixgbe_mac_X540) { 10195 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10196 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10197 (hw->bus.func == 0))) 10198 return true; 10199 } 10200 10201 /* WOL is determined based on device IDs for 82599 MACs */ 10202 switch (device_id) { 10203 case IXGBE_DEV_ID_82599_SFP: 10204 /* Only these subdevices could supports WOL */ 10205 switch (subdevice_id) { 10206 case IXGBE_SUBDEV_ID_82599_560FLR: 10207 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10208 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10209 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10210 /* only support first port */ 10211 if (hw->bus.func != 0) 10212 break; 10213 /* fall through */ 10214 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10215 case IXGBE_SUBDEV_ID_82599_SFP: 10216 case IXGBE_SUBDEV_ID_82599_RNDC: 10217 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10218 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10219 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10220 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10221 return true; 10222 } 10223 break; 10224 case IXGBE_DEV_ID_82599EN_SFP: 10225 /* Only these subdevices support WOL */ 10226 switch (subdevice_id) { 10227 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10228 return true; 10229 } 10230 break; 10231 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10232 /* All except this subdevice support WOL */ 10233 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10234 return true; 10235 break; 10236 case IXGBE_DEV_ID_82599_KX4: 10237 return true; 10238 default: 10239 break; 10240 } 10241 10242 return false; 10243 } 10244 10245 /** 10246 * ixgbe_set_fw_version - Set FW version 10247 * @adapter: the adapter private structure 10248 * 10249 * This function is used by probe and ethtool to determine the FW version to 10250 * format to display. The FW version is taken from the EEPROM/NVM. 10251 */ 10252 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10253 { 10254 struct ixgbe_hw *hw = &adapter->hw; 10255 struct ixgbe_nvm_version nvm_ver; 10256 10257 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10258 if (nvm_ver.oem_valid) { 10259 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10260 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10261 nvm_ver.oem_release); 10262 return; 10263 } 10264 10265 ixgbe_get_etk_id(hw, &nvm_ver); 10266 ixgbe_get_orom_version(hw, &nvm_ver); 10267 10268 if (nvm_ver.or_valid) { 10269 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10270 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10271 nvm_ver.or_build, nvm_ver.or_patch); 10272 return; 10273 } 10274 10275 /* Set ETrack ID format */ 10276 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10277 "0x%08x", nvm_ver.etk_id); 10278 } 10279 10280 /** 10281 * ixgbe_probe - Device Initialization Routine 10282 * @pdev: PCI device information struct 10283 * @ent: entry in ixgbe_pci_tbl 10284 * 10285 * Returns 0 on success, negative on failure 10286 * 10287 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10288 * The OS initialization, configuring of the adapter private structure, 10289 * and a hardware reset occur. 10290 **/ 10291 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10292 { 10293 struct net_device *netdev; 10294 struct ixgbe_adapter *adapter = NULL; 10295 struct ixgbe_hw *hw; 10296 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10297 int i, err, pci_using_dac, expected_gts; 10298 unsigned int indices = MAX_TX_QUEUES; 10299 u8 part_str[IXGBE_PBANUM_LENGTH]; 10300 bool disable_dev = false; 10301 #ifdef IXGBE_FCOE 10302 u16 device_caps; 10303 #endif 10304 u32 eec; 10305 10306 /* Catch broken hardware that put the wrong VF device ID in 10307 * the PCIe SR-IOV capability. 10308 */ 10309 if (pdev->is_virtfn) { 10310 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10311 pci_name(pdev), pdev->vendor, pdev->device); 10312 return -EINVAL; 10313 } 10314 10315 err = pci_enable_device_mem(pdev); 10316 if (err) 10317 return err; 10318 10319 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10320 pci_using_dac = 1; 10321 } else { 10322 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10323 if (err) { 10324 dev_err(&pdev->dev, 10325 "No usable DMA configuration, aborting\n"); 10326 goto err_dma; 10327 } 10328 pci_using_dac = 0; 10329 } 10330 10331 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10332 if (err) { 10333 dev_err(&pdev->dev, 10334 "pci_request_selected_regions failed 0x%x\n", err); 10335 goto err_pci_reg; 10336 } 10337 10338 pci_enable_pcie_error_reporting(pdev); 10339 10340 pci_set_master(pdev); 10341 pci_save_state(pdev); 10342 10343 if (ii->mac == ixgbe_mac_82598EB) { 10344 #ifdef CONFIG_IXGBE_DCB 10345 /* 8 TC w/ 4 queues per TC */ 10346 indices = 4 * MAX_TRAFFIC_CLASS; 10347 #else 10348 indices = IXGBE_MAX_RSS_INDICES; 10349 #endif 10350 } 10351 10352 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10353 if (!netdev) { 10354 err = -ENOMEM; 10355 goto err_alloc_etherdev; 10356 } 10357 10358 SET_NETDEV_DEV(netdev, &pdev->dev); 10359 10360 adapter = netdev_priv(netdev); 10361 10362 adapter->netdev = netdev; 10363 adapter->pdev = pdev; 10364 hw = &adapter->hw; 10365 hw->back = adapter; 10366 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10367 10368 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10369 pci_resource_len(pdev, 0)); 10370 adapter->io_addr = hw->hw_addr; 10371 if (!hw->hw_addr) { 10372 err = -EIO; 10373 goto err_ioremap; 10374 } 10375 10376 netdev->netdev_ops = &ixgbe_netdev_ops; 10377 ixgbe_set_ethtool_ops(netdev); 10378 netdev->watchdog_timeo = 5 * HZ; 10379 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10380 10381 /* Setup hw api */ 10382 hw->mac.ops = *ii->mac_ops; 10383 hw->mac.type = ii->mac; 10384 hw->mvals = ii->mvals; 10385 if (ii->link_ops) 10386 hw->link.ops = *ii->link_ops; 10387 10388 /* EEPROM */ 10389 hw->eeprom.ops = *ii->eeprom_ops; 10390 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10391 if (ixgbe_removed(hw->hw_addr)) { 10392 err = -EIO; 10393 goto err_ioremap; 10394 } 10395 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10396 if (!(eec & BIT(8))) 10397 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10398 10399 /* PHY */ 10400 hw->phy.ops = *ii->phy_ops; 10401 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10402 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10403 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10404 hw->phy.mdio.mmds = 0; 10405 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10406 hw->phy.mdio.dev = netdev; 10407 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10408 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10409 10410 /* setup the private structure */ 10411 err = ixgbe_sw_init(adapter, ii); 10412 if (err) 10413 goto err_sw_init; 10414 10415 /* Make sure the SWFW semaphore is in a valid state */ 10416 if (hw->mac.ops.init_swfw_sync) 10417 hw->mac.ops.init_swfw_sync(hw); 10418 10419 /* Make it possible the adapter to be woken up via WOL */ 10420 switch (adapter->hw.mac.type) { 10421 case ixgbe_mac_82599EB: 10422 case ixgbe_mac_X540: 10423 case ixgbe_mac_X550: 10424 case ixgbe_mac_X550EM_x: 10425 case ixgbe_mac_x550em_a: 10426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10427 break; 10428 default: 10429 break; 10430 } 10431 10432 /* 10433 * If there is a fan on this device and it has failed log the 10434 * failure. 10435 */ 10436 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10437 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10438 if (esdp & IXGBE_ESDP_SDP1) 10439 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10440 } 10441 10442 if (allow_unsupported_sfp) 10443 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10444 10445 /* reset_hw fills in the perm_addr as well */ 10446 hw->phy.reset_if_overtemp = true; 10447 err = hw->mac.ops.reset_hw(hw); 10448 hw->phy.reset_if_overtemp = false; 10449 ixgbe_set_eee_capable(adapter); 10450 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10451 err = 0; 10452 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10453 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10454 e_dev_err("Reload the driver after installing a supported module.\n"); 10455 goto err_sw_init; 10456 } else if (err) { 10457 e_dev_err("HW Init failed: %d\n", err); 10458 goto err_sw_init; 10459 } 10460 10461 #ifdef CONFIG_PCI_IOV 10462 /* SR-IOV not supported on the 82598 */ 10463 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10464 goto skip_sriov; 10465 /* Mailbox */ 10466 ixgbe_init_mbx_params_pf(hw); 10467 hw->mbx.ops = ii->mbx_ops; 10468 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10469 ixgbe_enable_sriov(adapter, max_vfs); 10470 skip_sriov: 10471 10472 #endif 10473 netdev->features = NETIF_F_SG | 10474 NETIF_F_TSO | 10475 NETIF_F_TSO6 | 10476 NETIF_F_RXHASH | 10477 NETIF_F_RXCSUM | 10478 NETIF_F_HW_CSUM; 10479 10480 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10481 NETIF_F_GSO_GRE_CSUM | \ 10482 NETIF_F_GSO_IPXIP4 | \ 10483 NETIF_F_GSO_IPXIP6 | \ 10484 NETIF_F_GSO_UDP_TUNNEL | \ 10485 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10486 10487 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10488 netdev->features |= NETIF_F_GSO_PARTIAL | 10489 IXGBE_GSO_PARTIAL_FEATURES; 10490 10491 if (hw->mac.type >= ixgbe_mac_82599EB) 10492 netdev->features |= NETIF_F_SCTP_CRC; 10493 10494 /* copy netdev features into list of user selectable features */ 10495 netdev->hw_features |= netdev->features | 10496 NETIF_F_HW_VLAN_CTAG_FILTER | 10497 NETIF_F_HW_VLAN_CTAG_RX | 10498 NETIF_F_HW_VLAN_CTAG_TX | 10499 NETIF_F_RXALL | 10500 NETIF_F_HW_L2FW_DOFFLOAD; 10501 10502 if (hw->mac.type >= ixgbe_mac_82599EB) 10503 netdev->hw_features |= NETIF_F_NTUPLE | 10504 NETIF_F_HW_TC; 10505 10506 if (pci_using_dac) 10507 netdev->features |= NETIF_F_HIGHDMA; 10508 10509 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10510 netdev->hw_enc_features |= netdev->vlan_features; 10511 netdev->mpls_features |= NETIF_F_SG | 10512 NETIF_F_TSO | 10513 NETIF_F_TSO6 | 10514 NETIF_F_HW_CSUM; 10515 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10516 10517 /* set this bit last since it cannot be part of vlan_features */ 10518 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10519 NETIF_F_HW_VLAN_CTAG_RX | 10520 NETIF_F_HW_VLAN_CTAG_TX; 10521 10522 netdev->priv_flags |= IFF_UNICAST_FLT; 10523 netdev->priv_flags |= IFF_SUPP_NOFCS; 10524 10525 /* MTU range: 68 - 9710 */ 10526 netdev->min_mtu = ETH_MIN_MTU; 10527 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10528 10529 #ifdef CONFIG_IXGBE_DCB 10530 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10531 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10532 #endif 10533 10534 #ifdef IXGBE_FCOE 10535 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10536 unsigned int fcoe_l; 10537 10538 if (hw->mac.ops.get_device_caps) { 10539 hw->mac.ops.get_device_caps(hw, &device_caps); 10540 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10541 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10542 } 10543 10544 10545 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10546 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10547 10548 netdev->features |= NETIF_F_FSO | 10549 NETIF_F_FCOE_CRC; 10550 10551 netdev->vlan_features |= NETIF_F_FSO | 10552 NETIF_F_FCOE_CRC | 10553 NETIF_F_FCOE_MTU; 10554 } 10555 #endif /* IXGBE_FCOE */ 10556 ixgbe_init_ipsec_offload(adapter); 10557 10558 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10559 netdev->hw_features |= NETIF_F_LRO; 10560 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10561 netdev->features |= NETIF_F_LRO; 10562 10563 /* make sure the EEPROM is good */ 10564 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10565 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10566 err = -EIO; 10567 goto err_sw_init; 10568 } 10569 10570 eth_platform_get_mac_address(&adapter->pdev->dev, 10571 adapter->hw.mac.perm_addr); 10572 10573 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10574 10575 if (!is_valid_ether_addr(netdev->dev_addr)) { 10576 e_dev_err("invalid MAC address\n"); 10577 err = -EIO; 10578 goto err_sw_init; 10579 } 10580 10581 /* Set hw->mac.addr to permanent MAC address */ 10582 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10583 ixgbe_mac_set_default_filter(adapter); 10584 10585 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10586 10587 if (ixgbe_removed(hw->hw_addr)) { 10588 err = -EIO; 10589 goto err_sw_init; 10590 } 10591 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10592 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10593 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10594 10595 err = ixgbe_init_interrupt_scheme(adapter); 10596 if (err) 10597 goto err_sw_init; 10598 10599 for (i = 0; i < adapter->num_rx_queues; i++) 10600 u64_stats_init(&adapter->rx_ring[i]->syncp); 10601 for (i = 0; i < adapter->num_tx_queues; i++) 10602 u64_stats_init(&adapter->tx_ring[i]->syncp); 10603 for (i = 0; i < adapter->num_xdp_queues; i++) 10604 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10605 10606 /* WOL not supported for all devices */ 10607 adapter->wol = 0; 10608 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10609 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10610 pdev->subsystem_device); 10611 if (hw->wol_enabled) 10612 adapter->wol = IXGBE_WUFC_MAG; 10613 10614 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10615 10616 /* save off EEPROM version number */ 10617 ixgbe_set_fw_version(adapter); 10618 10619 /* pick up the PCI bus settings for reporting later */ 10620 if (ixgbe_pcie_from_parent(hw)) 10621 ixgbe_get_parent_bus_info(adapter); 10622 else 10623 hw->mac.ops.get_bus_info(hw); 10624 10625 /* calculate the expected PCIe bandwidth required for optimal 10626 * performance. Note that some older parts will never have enough 10627 * bandwidth due to being older generation PCIe parts. We clamp these 10628 * parts to ensure no warning is displayed if it can't be fixed. 10629 */ 10630 switch (hw->mac.type) { 10631 case ixgbe_mac_82598EB: 10632 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10633 break; 10634 default: 10635 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10636 break; 10637 } 10638 10639 /* don't check link if we failed to enumerate functions */ 10640 if (expected_gts > 0) 10641 ixgbe_check_minimum_link(adapter, expected_gts); 10642 10643 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10644 if (err) 10645 strlcpy(part_str, "Unknown", sizeof(part_str)); 10646 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10647 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10648 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10649 part_str); 10650 else 10651 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10652 hw->mac.type, hw->phy.type, part_str); 10653 10654 e_dev_info("%pM\n", netdev->dev_addr); 10655 10656 /* reset the hardware with the new settings */ 10657 err = hw->mac.ops.start_hw(hw); 10658 if (err == IXGBE_ERR_EEPROM_VERSION) { 10659 /* We are running on a pre-production device, log a warning */ 10660 e_dev_warn("This device is a pre-production adapter/LOM. " 10661 "Please be aware there may be issues associated " 10662 "with your hardware. If you are experiencing " 10663 "problems please contact your Intel or hardware " 10664 "representative who provided you with this " 10665 "hardware.\n"); 10666 } 10667 strcpy(netdev->name, "eth%d"); 10668 pci_set_drvdata(pdev, adapter); 10669 err = register_netdev(netdev); 10670 if (err) 10671 goto err_register; 10672 10673 10674 /* power down the optics for 82599 SFP+ fiber */ 10675 if (hw->mac.ops.disable_tx_laser) 10676 hw->mac.ops.disable_tx_laser(hw); 10677 10678 /* carrier off reporting is important to ethtool even BEFORE open */ 10679 netif_carrier_off(netdev); 10680 10681 #ifdef CONFIG_IXGBE_DCA 10682 if (dca_add_requester(&pdev->dev) == 0) { 10683 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10684 ixgbe_setup_dca(adapter); 10685 } 10686 #endif 10687 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10688 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10689 for (i = 0; i < adapter->num_vfs; i++) 10690 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10691 } 10692 10693 /* firmware requires driver version to be 0xFFFFFFFF 10694 * since os does not support feature 10695 */ 10696 if (hw->mac.ops.set_fw_drv_ver) 10697 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10698 sizeof(ixgbe_driver_version) - 1, 10699 ixgbe_driver_version); 10700 10701 /* add san mac addr to netdev */ 10702 ixgbe_add_sanmac_netdev(netdev); 10703 10704 e_dev_info("%s\n", ixgbe_default_device_descr); 10705 10706 #ifdef CONFIG_IXGBE_HWMON 10707 if (ixgbe_sysfs_init(adapter)) 10708 e_err(probe, "failed to allocate sysfs resources\n"); 10709 #endif /* CONFIG_IXGBE_HWMON */ 10710 10711 ixgbe_dbg_adapter_init(adapter); 10712 10713 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10714 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10715 hw->mac.ops.setup_link(hw, 10716 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10717 true); 10718 10719 return 0; 10720 10721 err_register: 10722 ixgbe_release_hw_control(adapter); 10723 ixgbe_clear_interrupt_scheme(adapter); 10724 err_sw_init: 10725 ixgbe_disable_sriov(adapter); 10726 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10727 iounmap(adapter->io_addr); 10728 kfree(adapter->jump_tables[0]); 10729 kfree(adapter->mac_table); 10730 kfree(adapter->rss_key); 10731 err_ioremap: 10732 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10733 free_netdev(netdev); 10734 err_alloc_etherdev: 10735 pci_release_mem_regions(pdev); 10736 err_pci_reg: 10737 err_dma: 10738 if (!adapter || disable_dev) 10739 pci_disable_device(pdev); 10740 return err; 10741 } 10742 10743 /** 10744 * ixgbe_remove - Device Removal Routine 10745 * @pdev: PCI device information struct 10746 * 10747 * ixgbe_remove is called by the PCI subsystem to alert the driver 10748 * that it should release a PCI device. The could be caused by a 10749 * Hot-Plug event, or because the driver is going to be removed from 10750 * memory. 10751 **/ 10752 static void ixgbe_remove(struct pci_dev *pdev) 10753 { 10754 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10755 struct net_device *netdev; 10756 bool disable_dev; 10757 int i; 10758 10759 /* if !adapter then we already cleaned up in probe */ 10760 if (!adapter) 10761 return; 10762 10763 netdev = adapter->netdev; 10764 ixgbe_dbg_adapter_exit(adapter); 10765 10766 set_bit(__IXGBE_REMOVING, &adapter->state); 10767 cancel_work_sync(&adapter->service_task); 10768 10769 10770 #ifdef CONFIG_IXGBE_DCA 10771 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10772 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10773 dca_remove_requester(&pdev->dev); 10774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10775 IXGBE_DCA_CTRL_DCA_DISABLE); 10776 } 10777 10778 #endif 10779 #ifdef CONFIG_IXGBE_HWMON 10780 ixgbe_sysfs_exit(adapter); 10781 #endif /* CONFIG_IXGBE_HWMON */ 10782 10783 /* remove the added san mac */ 10784 ixgbe_del_sanmac_netdev(netdev); 10785 10786 #ifdef CONFIG_PCI_IOV 10787 ixgbe_disable_sriov(adapter); 10788 #endif 10789 if (netdev->reg_state == NETREG_REGISTERED) 10790 unregister_netdev(netdev); 10791 10792 ixgbe_stop_ipsec_offload(adapter); 10793 ixgbe_clear_interrupt_scheme(adapter); 10794 10795 ixgbe_release_hw_control(adapter); 10796 10797 #ifdef CONFIG_DCB 10798 kfree(adapter->ixgbe_ieee_pfc); 10799 kfree(adapter->ixgbe_ieee_ets); 10800 10801 #endif 10802 iounmap(adapter->io_addr); 10803 pci_release_mem_regions(pdev); 10804 10805 e_dev_info("complete\n"); 10806 10807 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10808 if (adapter->jump_tables[i]) { 10809 kfree(adapter->jump_tables[i]->input); 10810 kfree(adapter->jump_tables[i]->mask); 10811 } 10812 kfree(adapter->jump_tables[i]); 10813 } 10814 10815 kfree(adapter->mac_table); 10816 kfree(adapter->rss_key); 10817 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10818 free_netdev(netdev); 10819 10820 pci_disable_pcie_error_reporting(pdev); 10821 10822 if (disable_dev) 10823 pci_disable_device(pdev); 10824 } 10825 10826 /** 10827 * ixgbe_io_error_detected - called when PCI error is detected 10828 * @pdev: Pointer to PCI device 10829 * @state: The current pci connection state 10830 * 10831 * This function is called after a PCI bus error affecting 10832 * this device has been detected. 10833 */ 10834 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10835 pci_channel_state_t state) 10836 { 10837 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10838 struct net_device *netdev = adapter->netdev; 10839 10840 #ifdef CONFIG_PCI_IOV 10841 struct ixgbe_hw *hw = &adapter->hw; 10842 struct pci_dev *bdev, *vfdev; 10843 u32 dw0, dw1, dw2, dw3; 10844 int vf, pos; 10845 u16 req_id, pf_func; 10846 10847 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10848 adapter->num_vfs == 0) 10849 goto skip_bad_vf_detection; 10850 10851 bdev = pdev->bus->self; 10852 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10853 bdev = bdev->bus->self; 10854 10855 if (!bdev) 10856 goto skip_bad_vf_detection; 10857 10858 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10859 if (!pos) 10860 goto skip_bad_vf_detection; 10861 10862 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10863 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10864 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10865 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10866 if (ixgbe_removed(hw->hw_addr)) 10867 goto skip_bad_vf_detection; 10868 10869 req_id = dw1 >> 16; 10870 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10871 if (!(req_id & 0x0080)) 10872 goto skip_bad_vf_detection; 10873 10874 pf_func = req_id & 0x01; 10875 if ((pf_func & 1) == (pdev->devfn & 1)) { 10876 unsigned int device_id; 10877 10878 vf = (req_id & 0x7F) >> 1; 10879 e_dev_err("VF %d has caused a PCIe error\n", vf); 10880 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10881 "%8.8x\tdw3: %8.8x\n", 10882 dw0, dw1, dw2, dw3); 10883 switch (adapter->hw.mac.type) { 10884 case ixgbe_mac_82599EB: 10885 device_id = IXGBE_82599_VF_DEVICE_ID; 10886 break; 10887 case ixgbe_mac_X540: 10888 device_id = IXGBE_X540_VF_DEVICE_ID; 10889 break; 10890 case ixgbe_mac_X550: 10891 device_id = IXGBE_DEV_ID_X550_VF; 10892 break; 10893 case ixgbe_mac_X550EM_x: 10894 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10895 break; 10896 case ixgbe_mac_x550em_a: 10897 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10898 break; 10899 default: 10900 device_id = 0; 10901 break; 10902 } 10903 10904 /* Find the pci device of the offending VF */ 10905 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10906 while (vfdev) { 10907 if (vfdev->devfn == (req_id & 0xFF)) 10908 break; 10909 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10910 device_id, vfdev); 10911 } 10912 /* 10913 * There's a slim chance the VF could have been hot plugged, 10914 * so if it is no longer present we don't need to issue the 10915 * VFLR. Just clean up the AER in that case. 10916 */ 10917 if (vfdev) { 10918 pcie_flr(vfdev); 10919 /* Free device reference count */ 10920 pci_dev_put(vfdev); 10921 } 10922 10923 pci_cleanup_aer_uncorrect_error_status(pdev); 10924 } 10925 10926 /* 10927 * Even though the error may have occurred on the other port 10928 * we still need to increment the vf error reference count for 10929 * both ports because the I/O resume function will be called 10930 * for both of them. 10931 */ 10932 adapter->vferr_refcount++; 10933 10934 return PCI_ERS_RESULT_RECOVERED; 10935 10936 skip_bad_vf_detection: 10937 #endif /* CONFIG_PCI_IOV */ 10938 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10939 return PCI_ERS_RESULT_DISCONNECT; 10940 10941 if (!netif_device_present(netdev)) 10942 return PCI_ERS_RESULT_DISCONNECT; 10943 10944 rtnl_lock(); 10945 netif_device_detach(netdev); 10946 10947 if (netif_running(netdev)) 10948 ixgbe_close_suspend(adapter); 10949 10950 if (state == pci_channel_io_perm_failure) { 10951 rtnl_unlock(); 10952 return PCI_ERS_RESULT_DISCONNECT; 10953 } 10954 10955 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10956 pci_disable_device(pdev); 10957 rtnl_unlock(); 10958 10959 /* Request a slot reset. */ 10960 return PCI_ERS_RESULT_NEED_RESET; 10961 } 10962 10963 /** 10964 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10965 * @pdev: Pointer to PCI device 10966 * 10967 * Restart the card from scratch, as if from a cold-boot. 10968 */ 10969 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10970 { 10971 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10972 pci_ers_result_t result; 10973 int err; 10974 10975 if (pci_enable_device_mem(pdev)) { 10976 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10977 result = PCI_ERS_RESULT_DISCONNECT; 10978 } else { 10979 smp_mb__before_atomic(); 10980 clear_bit(__IXGBE_DISABLED, &adapter->state); 10981 adapter->hw.hw_addr = adapter->io_addr; 10982 pci_set_master(pdev); 10983 pci_restore_state(pdev); 10984 pci_save_state(pdev); 10985 10986 pci_wake_from_d3(pdev, false); 10987 10988 ixgbe_reset(adapter); 10989 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10990 result = PCI_ERS_RESULT_RECOVERED; 10991 } 10992 10993 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10994 if (err) { 10995 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10996 "failed 0x%0x\n", err); 10997 /* non-fatal, continue */ 10998 } 10999 11000 return result; 11001 } 11002 11003 /** 11004 * ixgbe_io_resume - called when traffic can start flowing again. 11005 * @pdev: Pointer to PCI device 11006 * 11007 * This callback is called when the error recovery driver tells us that 11008 * its OK to resume normal operation. 11009 */ 11010 static void ixgbe_io_resume(struct pci_dev *pdev) 11011 { 11012 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11013 struct net_device *netdev = adapter->netdev; 11014 11015 #ifdef CONFIG_PCI_IOV 11016 if (adapter->vferr_refcount) { 11017 e_info(drv, "Resuming after VF err\n"); 11018 adapter->vferr_refcount--; 11019 return; 11020 } 11021 11022 #endif 11023 rtnl_lock(); 11024 if (netif_running(netdev)) 11025 ixgbe_open(netdev); 11026 11027 netif_device_attach(netdev); 11028 rtnl_unlock(); 11029 } 11030 11031 static const struct pci_error_handlers ixgbe_err_handler = { 11032 .error_detected = ixgbe_io_error_detected, 11033 .slot_reset = ixgbe_io_slot_reset, 11034 .resume = ixgbe_io_resume, 11035 }; 11036 11037 static struct pci_driver ixgbe_driver = { 11038 .name = ixgbe_driver_name, 11039 .id_table = ixgbe_pci_tbl, 11040 .probe = ixgbe_probe, 11041 .remove = ixgbe_remove, 11042 #ifdef CONFIG_PM 11043 .suspend = ixgbe_suspend, 11044 .resume = ixgbe_resume, 11045 #endif 11046 .shutdown = ixgbe_shutdown, 11047 .sriov_configure = ixgbe_pci_sriov_configure, 11048 .err_handler = &ixgbe_err_handler 11049 }; 11050 11051 /** 11052 * ixgbe_init_module - Driver Registration Routine 11053 * 11054 * ixgbe_init_module is the first routine called when the driver is 11055 * loaded. All it does is register with the PCI subsystem. 11056 **/ 11057 static int __init ixgbe_init_module(void) 11058 { 11059 int ret; 11060 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11061 pr_info("%s\n", ixgbe_copyright); 11062 11063 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11064 if (!ixgbe_wq) { 11065 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11066 return -ENOMEM; 11067 } 11068 11069 ixgbe_dbg_init(); 11070 11071 ret = pci_register_driver(&ixgbe_driver); 11072 if (ret) { 11073 destroy_workqueue(ixgbe_wq); 11074 ixgbe_dbg_exit(); 11075 return ret; 11076 } 11077 11078 #ifdef CONFIG_IXGBE_DCA 11079 dca_register_notify(&dca_notifier); 11080 #endif 11081 11082 return 0; 11083 } 11084 11085 module_init(ixgbe_init_module); 11086 11087 /** 11088 * ixgbe_exit_module - Driver Exit Cleanup Routine 11089 * 11090 * ixgbe_exit_module is called just before the driver is removed 11091 * from memory. 11092 **/ 11093 static void __exit ixgbe_exit_module(void) 11094 { 11095 #ifdef CONFIG_IXGBE_DCA 11096 dca_unregister_notify(&dca_notifier); 11097 #endif 11098 pci_unregister_driver(&ixgbe_driver); 11099 11100 ixgbe_dbg_exit(); 11101 if (ixgbe_wq) { 11102 destroy_workqueue(ixgbe_wq); 11103 ixgbe_wq = NULL; 11104 } 11105 } 11106 11107 #ifdef CONFIG_IXGBE_DCA 11108 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11109 void *p) 11110 { 11111 int ret_val; 11112 11113 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11114 __ixgbe_notify_dca); 11115 11116 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11117 } 11118 11119 #endif /* CONFIG_IXGBE_DCA */ 11120 11121 module_exit(ixgbe_exit_module); 11122 11123 /* ixgbe_main.c */ 11124