1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <scsi/fc/fc_fcoe.h> 32 #include <net/udp_tunnel.h> 33 #include <net/pkt_cls.h> 34 #include <net/tc_act/tc_gact.h> 35 #include <net/tc_act/tc_mirred.h> 36 #include <net/vxlan.h> 37 #include <net/mpls.h> 38 #include <net/xdp_sock.h> 39 40 #include "ixgbe.h" 41 #include "ixgbe_common.h" 42 #include "ixgbe_dcb_82599.h" 43 #include "ixgbe_phy.h" 44 #include "ixgbe_sriov.h" 45 #include "ixgbe_model.h" 46 #include "ixgbe_txrx_common.h" 47 48 char ixgbe_driver_name[] = "ixgbe"; 49 static const char ixgbe_driver_string[] = 50 "Intel(R) 10 Gigabit PCI Express Network Driver"; 51 #ifdef IXGBE_FCOE 52 char ixgbe_default_device_descr[] = 53 "Intel(R) 10 Gigabit Network Connection"; 54 #else 55 static char ixgbe_default_device_descr[] = 56 "Intel(R) 10 Gigabit Network Connection"; 57 #endif 58 #define DRV_VERSION "5.1.0-k" 59 const char ixgbe_driver_version[] = DRV_VERSION; 60 static const char ixgbe_copyright[] = 61 "Copyright (c) 1999-2016 Intel Corporation."; 62 63 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 64 65 static const struct ixgbe_info *ixgbe_info_tbl[] = { 66 [board_82598] = &ixgbe_82598_info, 67 [board_82599] = &ixgbe_82599_info, 68 [board_X540] = &ixgbe_X540_info, 69 [board_X550] = &ixgbe_X550_info, 70 [board_X550EM_x] = &ixgbe_X550EM_x_info, 71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 72 [board_x550em_a] = &ixgbe_x550em_a_info, 73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 74 }; 75 76 /* ixgbe_pci_tbl - PCI Device ID Table 77 * 78 * Wildcard entries (PCI_ANY_ID) should come last 79 * Last entry must be all 0s 80 * 81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 82 * Class, Class Mask, private data (not used) } 83 */ 84 static const struct pci_device_id ixgbe_pci_tbl[] = { 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 132 /* required last entry */ 133 {0, } 134 }; 135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 136 137 #ifdef CONFIG_IXGBE_DCA 138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 139 void *p); 140 static struct notifier_block dca_notifier = { 141 .notifier_call = ixgbe_notify_dca, 142 .next = NULL, 143 .priority = 0 144 }; 145 #endif 146 147 #ifdef CONFIG_PCI_IOV 148 static unsigned int max_vfs; 149 module_param(max_vfs, uint, 0); 150 MODULE_PARM_DESC(max_vfs, 151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 152 #endif /* CONFIG_PCI_IOV */ 153 154 static unsigned int allow_unsupported_sfp; 155 module_param(allow_unsupported_sfp, uint, 0); 156 MODULE_PARM_DESC(allow_unsupported_sfp, 157 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 158 159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 160 static int debug = -1; 161 module_param(debug, int, 0); 162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 163 164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 166 MODULE_LICENSE("GPL v2"); 167 MODULE_VERSION(DRV_VERSION); 168 169 static struct workqueue_struct *ixgbe_wq; 170 171 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 172 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 173 174 static const struct net_device_ops ixgbe_netdev_ops; 175 176 static bool netif_is_ixgbe(struct net_device *dev) 177 { 178 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 179 } 180 181 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 182 u32 reg, u16 *value) 183 { 184 struct pci_dev *parent_dev; 185 struct pci_bus *parent_bus; 186 187 parent_bus = adapter->pdev->bus->parent; 188 if (!parent_bus) 189 return -1; 190 191 parent_dev = parent_bus->self; 192 if (!parent_dev) 193 return -1; 194 195 if (!pci_is_pcie(parent_dev)) 196 return -1; 197 198 pcie_capability_read_word(parent_dev, reg, value); 199 if (*value == IXGBE_FAILED_READ_CFG_WORD && 200 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 201 return -1; 202 return 0; 203 } 204 205 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 206 { 207 struct ixgbe_hw *hw = &adapter->hw; 208 u16 link_status = 0; 209 int err; 210 211 hw->bus.type = ixgbe_bus_type_pci_express; 212 213 /* Get the negotiated link width and speed from PCI config space of the 214 * parent, as this device is behind a switch 215 */ 216 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 217 218 /* assume caller will handle error case */ 219 if (err) 220 return err; 221 222 hw->bus.width = ixgbe_convert_bus_width(link_status); 223 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 224 225 return 0; 226 } 227 228 /** 229 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 230 * @hw: hw specific details 231 * 232 * This function is used by probe to determine whether a device's PCI-Express 233 * bandwidth details should be gathered from the parent bus instead of from the 234 * device. Used to ensure that various locations all have the correct device ID 235 * checks. 236 */ 237 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 238 { 239 switch (hw->device_id) { 240 case IXGBE_DEV_ID_82599_SFP_SF_QP: 241 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 242 return true; 243 default: 244 return false; 245 } 246 } 247 248 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 249 int expected_gts) 250 { 251 struct ixgbe_hw *hw = &adapter->hw; 252 struct pci_dev *pdev; 253 254 /* Some devices are not connected over PCIe and thus do not negotiate 255 * speed. These devices do not have valid bus info, and thus any report 256 * we generate may not be correct. 257 */ 258 if (hw->bus.type == ixgbe_bus_type_internal) 259 return; 260 261 /* determine whether to use the parent device */ 262 if (ixgbe_pcie_from_parent(&adapter->hw)) 263 pdev = adapter->pdev->bus->parent->self; 264 else 265 pdev = adapter->pdev; 266 267 pcie_print_link_status(pdev); 268 } 269 270 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 271 { 272 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 273 !test_bit(__IXGBE_REMOVING, &adapter->state) && 274 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 275 queue_work(ixgbe_wq, &adapter->service_task); 276 } 277 278 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 279 { 280 struct ixgbe_adapter *adapter = hw->back; 281 282 if (!hw->hw_addr) 283 return; 284 hw->hw_addr = NULL; 285 e_dev_err("Adapter removed\n"); 286 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 287 ixgbe_service_event_schedule(adapter); 288 } 289 290 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 291 { 292 u8 __iomem *reg_addr; 293 u32 value; 294 int i; 295 296 reg_addr = READ_ONCE(hw->hw_addr); 297 if (ixgbe_removed(reg_addr)) 298 return IXGBE_FAILED_READ_REG; 299 300 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 301 * so perform several status register reads to determine if the adapter 302 * has been removed. 303 */ 304 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 305 value = readl(reg_addr + IXGBE_STATUS); 306 if (value != IXGBE_FAILED_READ_REG) 307 break; 308 mdelay(3); 309 } 310 311 if (value == IXGBE_FAILED_READ_REG) 312 ixgbe_remove_adapter(hw); 313 else 314 value = readl(reg_addr + reg); 315 return value; 316 } 317 318 /** 319 * ixgbe_read_reg - Read from device register 320 * @hw: hw specific details 321 * @reg: offset of register to read 322 * 323 * Returns : value read or IXGBE_FAILED_READ_REG if removed 324 * 325 * This function is used to read device registers. It checks for device 326 * removal by confirming any read that returns all ones by checking the 327 * status register value for all ones. This function avoids reading from 328 * the hardware if a removal was previously detected in which case it 329 * returns IXGBE_FAILED_READ_REG (all ones). 330 */ 331 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 332 { 333 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 334 u32 value; 335 336 if (ixgbe_removed(reg_addr)) 337 return IXGBE_FAILED_READ_REG; 338 if (unlikely(hw->phy.nw_mng_if_sel & 339 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 340 struct ixgbe_adapter *adapter; 341 int i; 342 343 for (i = 0; i < 200; ++i) { 344 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 345 if (likely(!value)) 346 goto writes_completed; 347 if (value == IXGBE_FAILED_READ_REG) { 348 ixgbe_remove_adapter(hw); 349 return IXGBE_FAILED_READ_REG; 350 } 351 udelay(5); 352 } 353 354 adapter = hw->back; 355 e_warn(hw, "register writes incomplete %08x\n", value); 356 } 357 358 writes_completed: 359 value = readl(reg_addr + reg); 360 if (unlikely(value == IXGBE_FAILED_READ_REG)) 361 value = ixgbe_check_remove(hw, reg); 362 return value; 363 } 364 365 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 366 { 367 u16 value; 368 369 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 370 if (value == IXGBE_FAILED_READ_CFG_WORD) { 371 ixgbe_remove_adapter(hw); 372 return true; 373 } 374 return false; 375 } 376 377 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 378 { 379 struct ixgbe_adapter *adapter = hw->back; 380 u16 value; 381 382 if (ixgbe_removed(hw->hw_addr)) 383 return IXGBE_FAILED_READ_CFG_WORD; 384 pci_read_config_word(adapter->pdev, reg, &value); 385 if (value == IXGBE_FAILED_READ_CFG_WORD && 386 ixgbe_check_cfg_remove(hw, adapter->pdev)) 387 return IXGBE_FAILED_READ_CFG_WORD; 388 return value; 389 } 390 391 #ifdef CONFIG_PCI_IOV 392 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 393 { 394 struct ixgbe_adapter *adapter = hw->back; 395 u32 value; 396 397 if (ixgbe_removed(hw->hw_addr)) 398 return IXGBE_FAILED_READ_CFG_DWORD; 399 pci_read_config_dword(adapter->pdev, reg, &value); 400 if (value == IXGBE_FAILED_READ_CFG_DWORD && 401 ixgbe_check_cfg_remove(hw, adapter->pdev)) 402 return IXGBE_FAILED_READ_CFG_DWORD; 403 return value; 404 } 405 #endif /* CONFIG_PCI_IOV */ 406 407 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 408 { 409 struct ixgbe_adapter *adapter = hw->back; 410 411 if (ixgbe_removed(hw->hw_addr)) 412 return; 413 pci_write_config_word(adapter->pdev, reg, value); 414 } 415 416 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 417 { 418 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 419 420 /* flush memory to make sure state is correct before next watchdog */ 421 smp_mb__before_atomic(); 422 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 423 } 424 425 struct ixgbe_reg_info { 426 u32 ofs; 427 char *name; 428 }; 429 430 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 431 432 /* General Registers */ 433 {IXGBE_CTRL, "CTRL"}, 434 {IXGBE_STATUS, "STATUS"}, 435 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 436 437 /* Interrupt Registers */ 438 {IXGBE_EICR, "EICR"}, 439 440 /* RX Registers */ 441 {IXGBE_SRRCTL(0), "SRRCTL"}, 442 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 443 {IXGBE_RDLEN(0), "RDLEN"}, 444 {IXGBE_RDH(0), "RDH"}, 445 {IXGBE_RDT(0), "RDT"}, 446 {IXGBE_RXDCTL(0), "RXDCTL"}, 447 {IXGBE_RDBAL(0), "RDBAL"}, 448 {IXGBE_RDBAH(0), "RDBAH"}, 449 450 /* TX Registers */ 451 {IXGBE_TDBAL(0), "TDBAL"}, 452 {IXGBE_TDBAH(0), "TDBAH"}, 453 {IXGBE_TDLEN(0), "TDLEN"}, 454 {IXGBE_TDH(0), "TDH"}, 455 {IXGBE_TDT(0), "TDT"}, 456 {IXGBE_TXDCTL(0), "TXDCTL"}, 457 458 /* List Terminator */ 459 { .name = NULL } 460 }; 461 462 463 /* 464 * ixgbe_regdump - register printout routine 465 */ 466 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 467 { 468 int i; 469 char rname[16]; 470 u32 regs[64]; 471 472 switch (reginfo->ofs) { 473 case IXGBE_SRRCTL(0): 474 for (i = 0; i < 64; i++) 475 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 476 break; 477 case IXGBE_DCA_RXCTRL(0): 478 for (i = 0; i < 64; i++) 479 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 480 break; 481 case IXGBE_RDLEN(0): 482 for (i = 0; i < 64; i++) 483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 484 break; 485 case IXGBE_RDH(0): 486 for (i = 0; i < 64; i++) 487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 488 break; 489 case IXGBE_RDT(0): 490 for (i = 0; i < 64; i++) 491 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 492 break; 493 case IXGBE_RXDCTL(0): 494 for (i = 0; i < 64; i++) 495 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 496 break; 497 case IXGBE_RDBAL(0): 498 for (i = 0; i < 64; i++) 499 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 500 break; 501 case IXGBE_RDBAH(0): 502 for (i = 0; i < 64; i++) 503 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 504 break; 505 case IXGBE_TDBAL(0): 506 for (i = 0; i < 64; i++) 507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 508 break; 509 case IXGBE_TDBAH(0): 510 for (i = 0; i < 64; i++) 511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 512 break; 513 case IXGBE_TDLEN(0): 514 for (i = 0; i < 64; i++) 515 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 516 break; 517 case IXGBE_TDH(0): 518 for (i = 0; i < 64; i++) 519 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 520 break; 521 case IXGBE_TDT(0): 522 for (i = 0; i < 64; i++) 523 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 524 break; 525 case IXGBE_TXDCTL(0): 526 for (i = 0; i < 64; i++) 527 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 528 break; 529 default: 530 pr_info("%-15s %08x\n", 531 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 532 return; 533 } 534 535 i = 0; 536 while (i < 64) { 537 int j; 538 char buf[9 * 8 + 1]; 539 char *p = buf; 540 541 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 542 for (j = 0; j < 8; j++) 543 p += sprintf(p, " %08x", regs[i++]); 544 pr_err("%-15s%s\n", rname, buf); 545 } 546 547 } 548 549 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 550 { 551 struct ixgbe_tx_buffer *tx_buffer; 552 553 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 554 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 555 n, ring->next_to_use, ring->next_to_clean, 556 (u64)dma_unmap_addr(tx_buffer, dma), 557 dma_unmap_len(tx_buffer, len), 558 tx_buffer->next_to_watch, 559 (u64)tx_buffer->time_stamp); 560 } 561 562 /* 563 * ixgbe_dump - Print registers, tx-rings and rx-rings 564 */ 565 static void ixgbe_dump(struct ixgbe_adapter *adapter) 566 { 567 struct net_device *netdev = adapter->netdev; 568 struct ixgbe_hw *hw = &adapter->hw; 569 struct ixgbe_reg_info *reginfo; 570 int n = 0; 571 struct ixgbe_ring *ring; 572 struct ixgbe_tx_buffer *tx_buffer; 573 union ixgbe_adv_tx_desc *tx_desc; 574 struct my_u0 { u64 a; u64 b; } *u0; 575 struct ixgbe_ring *rx_ring; 576 union ixgbe_adv_rx_desc *rx_desc; 577 struct ixgbe_rx_buffer *rx_buffer_info; 578 int i = 0; 579 580 if (!netif_msg_hw(adapter)) 581 return; 582 583 /* Print netdevice Info */ 584 if (netdev) { 585 dev_info(&adapter->pdev->dev, "Net device Info\n"); 586 pr_info("Device Name state " 587 "trans_start\n"); 588 pr_info("%-15s %016lX %016lX\n", 589 netdev->name, 590 netdev->state, 591 dev_trans_start(netdev)); 592 } 593 594 /* Print Registers */ 595 dev_info(&adapter->pdev->dev, "Register Dump\n"); 596 pr_info(" Register Name Value\n"); 597 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 598 reginfo->name; reginfo++) { 599 ixgbe_regdump(hw, reginfo); 600 } 601 602 /* Print TX Ring Summary */ 603 if (!netdev || !netif_running(netdev)) 604 return; 605 606 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 607 pr_info(" %s %s %s %s\n", 608 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 609 "leng", "ntw", "timestamp"); 610 for (n = 0; n < adapter->num_tx_queues; n++) { 611 ring = adapter->tx_ring[n]; 612 ixgbe_print_buffer(ring, n); 613 } 614 615 for (n = 0; n < adapter->num_xdp_queues; n++) { 616 ring = adapter->xdp_ring[n]; 617 ixgbe_print_buffer(ring, n); 618 } 619 620 /* Print TX Rings */ 621 if (!netif_msg_tx_done(adapter)) 622 goto rx_ring_summary; 623 624 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 625 626 /* Transmit Descriptor Formats 627 * 628 * 82598 Advanced Transmit Descriptor 629 * +--------------------------------------------------------------+ 630 * 0 | Buffer Address [63:0] | 631 * +--------------------------------------------------------------+ 632 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 633 * +--------------------------------------------------------------+ 634 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 635 * 636 * 82598 Advanced Transmit Descriptor (Write-Back Format) 637 * +--------------------------------------------------------------+ 638 * 0 | RSV [63:0] | 639 * +--------------------------------------------------------------+ 640 * 8 | RSV | STA | NXTSEQ | 641 * +--------------------------------------------------------------+ 642 * 63 36 35 32 31 0 643 * 644 * 82599+ Advanced Transmit Descriptor 645 * +--------------------------------------------------------------+ 646 * 0 | Buffer Address [63:0] | 647 * +--------------------------------------------------------------+ 648 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 649 * +--------------------------------------------------------------+ 650 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 651 * 652 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 653 * +--------------------------------------------------------------+ 654 * 0 | RSV [63:0] | 655 * +--------------------------------------------------------------+ 656 * 8 | RSV | STA | RSV | 657 * +--------------------------------------------------------------+ 658 * 63 36 35 32 31 0 659 */ 660 661 for (n = 0; n < adapter->num_tx_queues; n++) { 662 ring = adapter->tx_ring[n]; 663 pr_info("------------------------------------\n"); 664 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 665 pr_info("------------------------------------\n"); 666 pr_info("%s%s %s %s %s %s\n", 667 "T [desc] [address 63:0 ] ", 668 "[PlPOIdStDDt Ln] [bi->dma ] ", 669 "leng", "ntw", "timestamp", "bi->skb"); 670 671 for (i = 0; ring->desc && (i < ring->count); i++) { 672 tx_desc = IXGBE_TX_DESC(ring, i); 673 tx_buffer = &ring->tx_buffer_info[i]; 674 u0 = (struct my_u0 *)tx_desc; 675 if (dma_unmap_len(tx_buffer, len) > 0) { 676 const char *ring_desc; 677 678 if (i == ring->next_to_use && 679 i == ring->next_to_clean) 680 ring_desc = " NTC/U"; 681 else if (i == ring->next_to_use) 682 ring_desc = " NTU"; 683 else if (i == ring->next_to_clean) 684 ring_desc = " NTC"; 685 else 686 ring_desc = ""; 687 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 688 i, 689 le64_to_cpu((__force __le64)u0->a), 690 le64_to_cpu((__force __le64)u0->b), 691 (u64)dma_unmap_addr(tx_buffer, dma), 692 dma_unmap_len(tx_buffer, len), 693 tx_buffer->next_to_watch, 694 (u64)tx_buffer->time_stamp, 695 tx_buffer->skb, 696 ring_desc); 697 698 if (netif_msg_pktdata(adapter) && 699 tx_buffer->skb) 700 print_hex_dump(KERN_INFO, "", 701 DUMP_PREFIX_ADDRESS, 16, 1, 702 tx_buffer->skb->data, 703 dma_unmap_len(tx_buffer, len), 704 true); 705 } 706 } 707 } 708 709 /* Print RX Rings Summary */ 710 rx_ring_summary: 711 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 712 pr_info("Queue [NTU] [NTC]\n"); 713 for (n = 0; n < adapter->num_rx_queues; n++) { 714 rx_ring = adapter->rx_ring[n]; 715 pr_info("%5d %5X %5X\n", 716 n, rx_ring->next_to_use, rx_ring->next_to_clean); 717 } 718 719 /* Print RX Rings */ 720 if (!netif_msg_rx_status(adapter)) 721 return; 722 723 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 724 725 /* Receive Descriptor Formats 726 * 727 * 82598 Advanced Receive Descriptor (Read) Format 728 * 63 1 0 729 * +-----------------------------------------------------+ 730 * 0 | Packet Buffer Address [63:1] |A0/NSE| 731 * +----------------------------------------------+------+ 732 * 8 | Header Buffer Address [63:1] | DD | 733 * +-----------------------------------------------------+ 734 * 735 * 736 * 82598 Advanced Receive Descriptor (Write-Back) Format 737 * 738 * 63 48 47 32 31 30 21 20 16 15 4 3 0 739 * +------------------------------------------------------+ 740 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 741 * | Packet | IP | | | | Type | Type | 742 * | Checksum | Ident | | | | | | 743 * +------------------------------------------------------+ 744 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 745 * +------------------------------------------------------+ 746 * 63 48 47 32 31 20 19 0 747 * 748 * 82599+ Advanced Receive Descriptor (Read) Format 749 * 63 1 0 750 * +-----------------------------------------------------+ 751 * 0 | Packet Buffer Address [63:1] |A0/NSE| 752 * +----------------------------------------------+------+ 753 * 8 | Header Buffer Address [63:1] | DD | 754 * +-----------------------------------------------------+ 755 * 756 * 757 * 82599+ Advanced Receive Descriptor (Write-Back) Format 758 * 759 * 63 48 47 32 31 30 21 20 17 16 4 3 0 760 * +------------------------------------------------------+ 761 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 762 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 763 * |/ Flow Dir Flt ID | | | | | | 764 * +------------------------------------------------------+ 765 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 766 * +------------------------------------------------------+ 767 * 63 48 47 32 31 20 19 0 768 */ 769 770 for (n = 0; n < adapter->num_rx_queues; n++) { 771 rx_ring = adapter->rx_ring[n]; 772 pr_info("------------------------------------\n"); 773 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 774 pr_info("------------------------------------\n"); 775 pr_info("%s%s%s\n", 776 "R [desc] [ PktBuf A0] ", 777 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 778 "<-- Adv Rx Read format"); 779 pr_info("%s%s%s\n", 780 "RWB[desc] [PcsmIpSHl PtRs] ", 781 "[vl er S cks ln] ---------------- [bi->skb ] ", 782 "<-- Adv Rx Write-Back format"); 783 784 for (i = 0; i < rx_ring->count; i++) { 785 const char *ring_desc; 786 787 if (i == rx_ring->next_to_use) 788 ring_desc = " NTU"; 789 else if (i == rx_ring->next_to_clean) 790 ring_desc = " NTC"; 791 else 792 ring_desc = ""; 793 794 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 795 rx_desc = IXGBE_RX_DESC(rx_ring, i); 796 u0 = (struct my_u0 *)rx_desc; 797 if (rx_desc->wb.upper.length) { 798 /* Descriptor Done */ 799 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 800 i, 801 le64_to_cpu((__force __le64)u0->a), 802 le64_to_cpu((__force __le64)u0->b), 803 rx_buffer_info->skb, 804 ring_desc); 805 } else { 806 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 807 i, 808 le64_to_cpu((__force __le64)u0->a), 809 le64_to_cpu((__force __le64)u0->b), 810 (u64)rx_buffer_info->dma, 811 rx_buffer_info->skb, 812 ring_desc); 813 814 if (netif_msg_pktdata(adapter) && 815 rx_buffer_info->dma) { 816 print_hex_dump(KERN_INFO, "", 817 DUMP_PREFIX_ADDRESS, 16, 1, 818 page_address(rx_buffer_info->page) + 819 rx_buffer_info->page_offset, 820 ixgbe_rx_bufsz(rx_ring), true); 821 } 822 } 823 } 824 } 825 } 826 827 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 828 { 829 u32 ctrl_ext; 830 831 /* Let firmware take over control of h/w */ 832 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 833 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 834 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 835 } 836 837 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 838 { 839 u32 ctrl_ext; 840 841 /* Let firmware know the driver has taken over */ 842 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 843 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 844 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 845 } 846 847 /** 848 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 849 * @adapter: pointer to adapter struct 850 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 851 * @queue: queue to map the corresponding interrupt to 852 * @msix_vector: the vector to map to the corresponding queue 853 * 854 */ 855 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 856 u8 queue, u8 msix_vector) 857 { 858 u32 ivar, index; 859 struct ixgbe_hw *hw = &adapter->hw; 860 switch (hw->mac.type) { 861 case ixgbe_mac_82598EB: 862 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 863 if (direction == -1) 864 direction = 0; 865 index = (((direction * 64) + queue) >> 2) & 0x1F; 866 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 867 ivar &= ~(0xFF << (8 * (queue & 0x3))); 868 ivar |= (msix_vector << (8 * (queue & 0x3))); 869 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 870 break; 871 case ixgbe_mac_82599EB: 872 case ixgbe_mac_X540: 873 case ixgbe_mac_X550: 874 case ixgbe_mac_X550EM_x: 875 case ixgbe_mac_x550em_a: 876 if (direction == -1) { 877 /* other causes */ 878 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 879 index = ((queue & 1) * 8); 880 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 881 ivar &= ~(0xFF << index); 882 ivar |= (msix_vector << index); 883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 884 break; 885 } else { 886 /* tx or rx causes */ 887 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 888 index = ((16 * (queue & 1)) + (8 * direction)); 889 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 890 ivar &= ~(0xFF << index); 891 ivar |= (msix_vector << index); 892 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 893 break; 894 } 895 default: 896 break; 897 } 898 } 899 900 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 901 u64 qmask) 902 { 903 u32 mask; 904 905 switch (adapter->hw.mac.type) { 906 case ixgbe_mac_82598EB: 907 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 909 break; 910 case ixgbe_mac_82599EB: 911 case ixgbe_mac_X540: 912 case ixgbe_mac_X550: 913 case ixgbe_mac_X550EM_x: 914 case ixgbe_mac_x550em_a: 915 mask = (qmask & 0xFFFFFFFF); 916 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 917 mask = (qmask >> 32); 918 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 919 break; 920 default: 921 break; 922 } 923 } 924 925 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 926 { 927 struct ixgbe_hw *hw = &adapter->hw; 928 struct ixgbe_hw_stats *hwstats = &adapter->stats; 929 int i; 930 u32 data; 931 932 if ((hw->fc.current_mode != ixgbe_fc_full) && 933 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 934 return; 935 936 switch (hw->mac.type) { 937 case ixgbe_mac_82598EB: 938 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 939 break; 940 default: 941 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 942 } 943 hwstats->lxoffrxc += data; 944 945 /* refill credits (no tx hang) if we received xoff */ 946 if (!data) 947 return; 948 949 for (i = 0; i < adapter->num_tx_queues; i++) 950 clear_bit(__IXGBE_HANG_CHECK_ARMED, 951 &adapter->tx_ring[i]->state); 952 953 for (i = 0; i < adapter->num_xdp_queues; i++) 954 clear_bit(__IXGBE_HANG_CHECK_ARMED, 955 &adapter->xdp_ring[i]->state); 956 } 957 958 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 959 { 960 struct ixgbe_hw *hw = &adapter->hw; 961 struct ixgbe_hw_stats *hwstats = &adapter->stats; 962 u32 xoff[8] = {0}; 963 u8 tc; 964 int i; 965 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 966 967 if (adapter->ixgbe_ieee_pfc) 968 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 969 970 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 971 ixgbe_update_xoff_rx_lfc(adapter); 972 return; 973 } 974 975 /* update stats for each tc, only valid with PFC enabled */ 976 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 977 u32 pxoffrxc; 978 979 switch (hw->mac.type) { 980 case ixgbe_mac_82598EB: 981 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 982 break; 983 default: 984 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 985 } 986 hwstats->pxoffrxc[i] += pxoffrxc; 987 /* Get the TC for given UP */ 988 tc = netdev_get_prio_tc_map(adapter->netdev, i); 989 xoff[tc] += pxoffrxc; 990 } 991 992 /* disarm tx queues that have received xoff frames */ 993 for (i = 0; i < adapter->num_tx_queues; i++) { 994 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 995 996 tc = tx_ring->dcb_tc; 997 if (xoff[tc]) 998 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 999 } 1000 1001 for (i = 0; i < adapter->num_xdp_queues; i++) { 1002 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1003 1004 tc = xdp_ring->dcb_tc; 1005 if (xoff[tc]) 1006 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1007 } 1008 } 1009 1010 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1011 { 1012 return ring->stats.packets; 1013 } 1014 1015 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1016 { 1017 unsigned int head, tail; 1018 1019 head = ring->next_to_clean; 1020 tail = ring->next_to_use; 1021 1022 return ((head <= tail) ? tail : tail + ring->count) - head; 1023 } 1024 1025 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1026 { 1027 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1028 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1029 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1030 1031 clear_check_for_tx_hang(tx_ring); 1032 1033 /* 1034 * Check for a hung queue, but be thorough. This verifies 1035 * that a transmit has been completed since the previous 1036 * check AND there is at least one packet pending. The 1037 * ARMED bit is set to indicate a potential hang. The 1038 * bit is cleared if a pause frame is received to remove 1039 * false hang detection due to PFC or 802.3x frames. By 1040 * requiring this to fail twice we avoid races with 1041 * pfc clearing the ARMED bit and conditions where we 1042 * run the check_tx_hang logic with a transmit completion 1043 * pending but without time to complete it yet. 1044 */ 1045 if (tx_done_old == tx_done && tx_pending) 1046 /* make sure it is true for two checks in a row */ 1047 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1048 &tx_ring->state); 1049 /* update completed stats and continue */ 1050 tx_ring->tx_stats.tx_done_old = tx_done; 1051 /* reset the countdown */ 1052 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1053 1054 return false; 1055 } 1056 1057 /** 1058 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1059 * @adapter: driver private struct 1060 **/ 1061 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1062 { 1063 1064 /* Do the reset outside of interrupt context */ 1065 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1066 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1067 e_warn(drv, "initiating reset due to tx timeout\n"); 1068 ixgbe_service_event_schedule(adapter); 1069 } 1070 } 1071 1072 /** 1073 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1074 * @netdev: network interface device structure 1075 * @queue_index: Tx queue to set 1076 * @maxrate: desired maximum transmit bitrate 1077 **/ 1078 static int ixgbe_tx_maxrate(struct net_device *netdev, 1079 int queue_index, u32 maxrate) 1080 { 1081 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1082 struct ixgbe_hw *hw = &adapter->hw; 1083 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1084 1085 if (!maxrate) 1086 return 0; 1087 1088 /* Calculate the rate factor values to set */ 1089 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1090 bcnrc_val /= maxrate; 1091 1092 /* clear everything but the rate factor */ 1093 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1094 IXGBE_RTTBCNRC_RF_DEC_MASK; 1095 1096 /* enable the rate scheduler */ 1097 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1098 1099 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1100 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1101 1102 return 0; 1103 } 1104 1105 /** 1106 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1107 * @q_vector: structure containing interrupt and ring information 1108 * @tx_ring: tx ring to clean 1109 * @napi_budget: Used to determine if we are in netpoll 1110 **/ 1111 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1112 struct ixgbe_ring *tx_ring, int napi_budget) 1113 { 1114 struct ixgbe_adapter *adapter = q_vector->adapter; 1115 struct ixgbe_tx_buffer *tx_buffer; 1116 union ixgbe_adv_tx_desc *tx_desc; 1117 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1118 unsigned int budget = q_vector->tx.work_limit; 1119 unsigned int i = tx_ring->next_to_clean; 1120 1121 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1122 return true; 1123 1124 tx_buffer = &tx_ring->tx_buffer_info[i]; 1125 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1126 i -= tx_ring->count; 1127 1128 do { 1129 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1130 1131 /* if next_to_watch is not set then there is no work pending */ 1132 if (!eop_desc) 1133 break; 1134 1135 /* prevent any other reads prior to eop_desc */ 1136 smp_rmb(); 1137 1138 /* if DD is not set pending work has not been completed */ 1139 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1140 break; 1141 1142 /* clear next_to_watch to prevent false hangs */ 1143 tx_buffer->next_to_watch = NULL; 1144 1145 /* update the statistics for this packet */ 1146 total_bytes += tx_buffer->bytecount; 1147 total_packets += tx_buffer->gso_segs; 1148 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1149 total_ipsec++; 1150 1151 /* free the skb */ 1152 if (ring_is_xdp(tx_ring)) 1153 xdp_return_frame(tx_buffer->xdpf); 1154 else 1155 napi_consume_skb(tx_buffer->skb, napi_budget); 1156 1157 /* unmap skb header data */ 1158 dma_unmap_single(tx_ring->dev, 1159 dma_unmap_addr(tx_buffer, dma), 1160 dma_unmap_len(tx_buffer, len), 1161 DMA_TO_DEVICE); 1162 1163 /* clear tx_buffer data */ 1164 dma_unmap_len_set(tx_buffer, len, 0); 1165 1166 /* unmap remaining buffers */ 1167 while (tx_desc != eop_desc) { 1168 tx_buffer++; 1169 tx_desc++; 1170 i++; 1171 if (unlikely(!i)) { 1172 i -= tx_ring->count; 1173 tx_buffer = tx_ring->tx_buffer_info; 1174 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1175 } 1176 1177 /* unmap any remaining paged data */ 1178 if (dma_unmap_len(tx_buffer, len)) { 1179 dma_unmap_page(tx_ring->dev, 1180 dma_unmap_addr(tx_buffer, dma), 1181 dma_unmap_len(tx_buffer, len), 1182 DMA_TO_DEVICE); 1183 dma_unmap_len_set(tx_buffer, len, 0); 1184 } 1185 } 1186 1187 /* move us one more past the eop_desc for start of next pkt */ 1188 tx_buffer++; 1189 tx_desc++; 1190 i++; 1191 if (unlikely(!i)) { 1192 i -= tx_ring->count; 1193 tx_buffer = tx_ring->tx_buffer_info; 1194 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1195 } 1196 1197 /* issue prefetch for next Tx descriptor */ 1198 prefetch(tx_desc); 1199 1200 /* update budget accounting */ 1201 budget--; 1202 } while (likely(budget)); 1203 1204 i += tx_ring->count; 1205 tx_ring->next_to_clean = i; 1206 u64_stats_update_begin(&tx_ring->syncp); 1207 tx_ring->stats.bytes += total_bytes; 1208 tx_ring->stats.packets += total_packets; 1209 u64_stats_update_end(&tx_ring->syncp); 1210 q_vector->tx.total_bytes += total_bytes; 1211 q_vector->tx.total_packets += total_packets; 1212 adapter->tx_ipsec += total_ipsec; 1213 1214 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1215 /* schedule immediate reset if we believe we hung */ 1216 struct ixgbe_hw *hw = &adapter->hw; 1217 e_err(drv, "Detected Tx Unit Hang %s\n" 1218 " Tx Queue <%d>\n" 1219 " TDH, TDT <%x>, <%x>\n" 1220 " next_to_use <%x>\n" 1221 " next_to_clean <%x>\n" 1222 "tx_buffer_info[next_to_clean]\n" 1223 " time_stamp <%lx>\n" 1224 " jiffies <%lx>\n", 1225 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1226 tx_ring->queue_index, 1227 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1228 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1229 tx_ring->next_to_use, i, 1230 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1231 1232 if (!ring_is_xdp(tx_ring)) 1233 netif_stop_subqueue(tx_ring->netdev, 1234 tx_ring->queue_index); 1235 1236 e_info(probe, 1237 "tx hang %d detected on queue %d, resetting adapter\n", 1238 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1239 1240 /* schedule immediate reset if we believe we hung */ 1241 ixgbe_tx_timeout_reset(adapter); 1242 1243 /* the adapter is about to reset, no point in enabling stuff */ 1244 return true; 1245 } 1246 1247 if (ring_is_xdp(tx_ring)) 1248 return !!budget; 1249 1250 netdev_tx_completed_queue(txring_txq(tx_ring), 1251 total_packets, total_bytes); 1252 1253 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1254 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1255 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1256 /* Make sure that anybody stopping the queue after this 1257 * sees the new next_to_clean. 1258 */ 1259 smp_mb(); 1260 if (__netif_subqueue_stopped(tx_ring->netdev, 1261 tx_ring->queue_index) 1262 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1263 netif_wake_subqueue(tx_ring->netdev, 1264 tx_ring->queue_index); 1265 ++tx_ring->tx_stats.restart_queue; 1266 } 1267 } 1268 1269 return !!budget; 1270 } 1271 1272 #ifdef CONFIG_IXGBE_DCA 1273 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1274 struct ixgbe_ring *tx_ring, 1275 int cpu) 1276 { 1277 struct ixgbe_hw *hw = &adapter->hw; 1278 u32 txctrl = 0; 1279 u16 reg_offset; 1280 1281 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1282 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1283 1284 switch (hw->mac.type) { 1285 case ixgbe_mac_82598EB: 1286 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1287 break; 1288 case ixgbe_mac_82599EB: 1289 case ixgbe_mac_X540: 1290 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1291 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1292 break; 1293 default: 1294 /* for unknown hardware do not write register */ 1295 return; 1296 } 1297 1298 /* 1299 * We can enable relaxed ordering for reads, but not writes when 1300 * DCA is enabled. This is due to a known issue in some chipsets 1301 * which will cause the DCA tag to be cleared. 1302 */ 1303 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1304 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1305 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1306 1307 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1308 } 1309 1310 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1311 struct ixgbe_ring *rx_ring, 1312 int cpu) 1313 { 1314 struct ixgbe_hw *hw = &adapter->hw; 1315 u32 rxctrl = 0; 1316 u8 reg_idx = rx_ring->reg_idx; 1317 1318 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1319 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1320 1321 switch (hw->mac.type) { 1322 case ixgbe_mac_82599EB: 1323 case ixgbe_mac_X540: 1324 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1325 break; 1326 default: 1327 break; 1328 } 1329 1330 /* 1331 * We can enable relaxed ordering for reads, but not writes when 1332 * DCA is enabled. This is due to a known issue in some chipsets 1333 * which will cause the DCA tag to be cleared. 1334 */ 1335 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1336 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1337 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1338 1339 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1340 } 1341 1342 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1343 { 1344 struct ixgbe_adapter *adapter = q_vector->adapter; 1345 struct ixgbe_ring *ring; 1346 int cpu = get_cpu(); 1347 1348 if (q_vector->cpu == cpu) 1349 goto out_no_update; 1350 1351 ixgbe_for_each_ring(ring, q_vector->tx) 1352 ixgbe_update_tx_dca(adapter, ring, cpu); 1353 1354 ixgbe_for_each_ring(ring, q_vector->rx) 1355 ixgbe_update_rx_dca(adapter, ring, cpu); 1356 1357 q_vector->cpu = cpu; 1358 out_no_update: 1359 put_cpu(); 1360 } 1361 1362 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1363 { 1364 int i; 1365 1366 /* always use CB2 mode, difference is masked in the CB driver */ 1367 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1369 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1370 else 1371 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1372 IXGBE_DCA_CTRL_DCA_DISABLE); 1373 1374 for (i = 0; i < adapter->num_q_vectors; i++) { 1375 adapter->q_vector[i]->cpu = -1; 1376 ixgbe_update_dca(adapter->q_vector[i]); 1377 } 1378 } 1379 1380 static int __ixgbe_notify_dca(struct device *dev, void *data) 1381 { 1382 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1383 unsigned long event = *(unsigned long *)data; 1384 1385 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1386 return 0; 1387 1388 switch (event) { 1389 case DCA_PROVIDER_ADD: 1390 /* if we're already enabled, don't do it again */ 1391 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1392 break; 1393 if (dca_add_requester(dev) == 0) { 1394 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1396 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1397 break; 1398 } 1399 /* fall through - DCA is disabled. */ 1400 case DCA_PROVIDER_REMOVE: 1401 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1402 dca_remove_requester(dev); 1403 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1404 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1405 IXGBE_DCA_CTRL_DCA_DISABLE); 1406 } 1407 break; 1408 } 1409 1410 return 0; 1411 } 1412 1413 #endif /* CONFIG_IXGBE_DCA */ 1414 1415 #define IXGBE_RSS_L4_TYPES_MASK \ 1416 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1419 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1420 1421 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1422 union ixgbe_adv_rx_desc *rx_desc, 1423 struct sk_buff *skb) 1424 { 1425 u16 rss_type; 1426 1427 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1428 return; 1429 1430 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1431 IXGBE_RXDADV_RSSTYPE_MASK; 1432 1433 if (!rss_type) 1434 return; 1435 1436 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1437 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1438 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1439 } 1440 1441 #ifdef IXGBE_FCOE 1442 /** 1443 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1444 * @ring: structure containing ring specific data 1445 * @rx_desc: advanced rx descriptor 1446 * 1447 * Returns : true if it is FCoE pkt 1448 */ 1449 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1450 union ixgbe_adv_rx_desc *rx_desc) 1451 { 1452 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1453 1454 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1455 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1456 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1457 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1458 } 1459 1460 #endif /* IXGBE_FCOE */ 1461 /** 1462 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1463 * @ring: structure containing ring specific data 1464 * @rx_desc: current Rx descriptor being processed 1465 * @skb: skb currently being received and modified 1466 **/ 1467 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1468 union ixgbe_adv_rx_desc *rx_desc, 1469 struct sk_buff *skb) 1470 { 1471 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1472 bool encap_pkt = false; 1473 1474 skb_checksum_none_assert(skb); 1475 1476 /* Rx csum disabled */ 1477 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1478 return; 1479 1480 /* check for VXLAN and Geneve packets */ 1481 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1482 encap_pkt = true; 1483 skb->encapsulation = 1; 1484 } 1485 1486 /* if IP and error */ 1487 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1488 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1489 ring->rx_stats.csum_err++; 1490 return; 1491 } 1492 1493 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1494 return; 1495 1496 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1497 /* 1498 * 82599 errata, UDP frames with a 0 checksum can be marked as 1499 * checksum errors. 1500 */ 1501 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1502 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1503 return; 1504 1505 ring->rx_stats.csum_err++; 1506 return; 1507 } 1508 1509 /* It must be a TCP or UDP packet with a valid checksum */ 1510 skb->ip_summed = CHECKSUM_UNNECESSARY; 1511 if (encap_pkt) { 1512 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1513 return; 1514 1515 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1516 skb->ip_summed = CHECKSUM_NONE; 1517 return; 1518 } 1519 /* If we checked the outer header let the stack know */ 1520 skb->csum_level = 1; 1521 } 1522 } 1523 1524 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1525 { 1526 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1527 } 1528 1529 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1530 struct ixgbe_rx_buffer *bi) 1531 { 1532 struct page *page = bi->page; 1533 dma_addr_t dma; 1534 1535 /* since we are recycling buffers we should seldom need to alloc */ 1536 if (likely(page)) 1537 return true; 1538 1539 /* alloc new page for storage */ 1540 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1541 if (unlikely(!page)) { 1542 rx_ring->rx_stats.alloc_rx_page_failed++; 1543 return false; 1544 } 1545 1546 /* map page for use */ 1547 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1548 ixgbe_rx_pg_size(rx_ring), 1549 DMA_FROM_DEVICE, 1550 IXGBE_RX_DMA_ATTR); 1551 1552 /* 1553 * if mapping failed free memory back to system since 1554 * there isn't much point in holding memory we can't use 1555 */ 1556 if (dma_mapping_error(rx_ring->dev, dma)) { 1557 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1558 1559 rx_ring->rx_stats.alloc_rx_page_failed++; 1560 return false; 1561 } 1562 1563 bi->dma = dma; 1564 bi->page = page; 1565 bi->page_offset = ixgbe_rx_offset(rx_ring); 1566 page_ref_add(page, USHRT_MAX - 1); 1567 bi->pagecnt_bias = USHRT_MAX; 1568 rx_ring->rx_stats.alloc_rx_page++; 1569 1570 return true; 1571 } 1572 1573 /** 1574 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1575 * @rx_ring: ring to place buffers on 1576 * @cleaned_count: number of buffers to replace 1577 **/ 1578 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1579 { 1580 union ixgbe_adv_rx_desc *rx_desc; 1581 struct ixgbe_rx_buffer *bi; 1582 u16 i = rx_ring->next_to_use; 1583 u16 bufsz; 1584 1585 /* nothing to do */ 1586 if (!cleaned_count) 1587 return; 1588 1589 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1590 bi = &rx_ring->rx_buffer_info[i]; 1591 i -= rx_ring->count; 1592 1593 bufsz = ixgbe_rx_bufsz(rx_ring); 1594 1595 do { 1596 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1597 break; 1598 1599 /* sync the buffer for use by the device */ 1600 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1601 bi->page_offset, bufsz, 1602 DMA_FROM_DEVICE); 1603 1604 /* 1605 * Refresh the desc even if buffer_addrs didn't change 1606 * because each write-back erases this info. 1607 */ 1608 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1609 1610 rx_desc++; 1611 bi++; 1612 i++; 1613 if (unlikely(!i)) { 1614 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1615 bi = rx_ring->rx_buffer_info; 1616 i -= rx_ring->count; 1617 } 1618 1619 /* clear the length for the next_to_use descriptor */ 1620 rx_desc->wb.upper.length = 0; 1621 1622 cleaned_count--; 1623 } while (cleaned_count); 1624 1625 i += rx_ring->count; 1626 1627 if (rx_ring->next_to_use != i) { 1628 rx_ring->next_to_use = i; 1629 1630 /* update next to alloc since we have filled the ring */ 1631 rx_ring->next_to_alloc = i; 1632 1633 /* Force memory writes to complete before letting h/w 1634 * know there are new descriptors to fetch. (Only 1635 * applicable for weak-ordered memory model archs, 1636 * such as IA-64). 1637 */ 1638 wmb(); 1639 writel(i, rx_ring->tail); 1640 } 1641 } 1642 1643 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1644 struct sk_buff *skb) 1645 { 1646 u16 hdr_len = skb_headlen(skb); 1647 1648 /* set gso_size to avoid messing up TCP MSS */ 1649 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1650 IXGBE_CB(skb)->append_cnt); 1651 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1652 } 1653 1654 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1655 struct sk_buff *skb) 1656 { 1657 /* if append_cnt is 0 then frame is not RSC */ 1658 if (!IXGBE_CB(skb)->append_cnt) 1659 return; 1660 1661 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1662 rx_ring->rx_stats.rsc_flush++; 1663 1664 ixgbe_set_rsc_gso_size(rx_ring, skb); 1665 1666 /* gso_size is computed using append_cnt so always clear it last */ 1667 IXGBE_CB(skb)->append_cnt = 0; 1668 } 1669 1670 /** 1671 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1672 * @rx_ring: rx descriptor ring packet is being transacted on 1673 * @rx_desc: pointer to the EOP Rx descriptor 1674 * @skb: pointer to current skb being populated 1675 * 1676 * This function checks the ring, descriptor, and packet information in 1677 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1678 * other fields within the skb. 1679 **/ 1680 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1681 union ixgbe_adv_rx_desc *rx_desc, 1682 struct sk_buff *skb) 1683 { 1684 struct net_device *dev = rx_ring->netdev; 1685 u32 flags = rx_ring->q_vector->adapter->flags; 1686 1687 ixgbe_update_rsc_stats(rx_ring, skb); 1688 1689 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1690 1691 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1692 1693 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1694 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1695 1696 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1697 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1698 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1699 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1700 } 1701 1702 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1703 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1704 1705 /* record Rx queue, or update MACVLAN statistics */ 1706 if (netif_is_ixgbe(dev)) 1707 skb_record_rx_queue(skb, rx_ring->queue_index); 1708 else 1709 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1710 false); 1711 1712 skb->protocol = eth_type_trans(skb, dev); 1713 } 1714 1715 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1716 struct sk_buff *skb) 1717 { 1718 napi_gro_receive(&q_vector->napi, skb); 1719 } 1720 1721 /** 1722 * ixgbe_is_non_eop - process handling of non-EOP buffers 1723 * @rx_ring: Rx ring being processed 1724 * @rx_desc: Rx descriptor for current buffer 1725 * @skb: Current socket buffer containing buffer in progress 1726 * 1727 * This function updates next to clean. If the buffer is an EOP buffer 1728 * this function exits returning false, otherwise it will place the 1729 * sk_buff in the next buffer to be chained and return true indicating 1730 * that this is in fact a non-EOP buffer. 1731 **/ 1732 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1733 union ixgbe_adv_rx_desc *rx_desc, 1734 struct sk_buff *skb) 1735 { 1736 u32 ntc = rx_ring->next_to_clean + 1; 1737 1738 /* fetch, update, and store next to clean */ 1739 ntc = (ntc < rx_ring->count) ? ntc : 0; 1740 rx_ring->next_to_clean = ntc; 1741 1742 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1743 1744 /* update RSC append count if present */ 1745 if (ring_is_rsc_enabled(rx_ring)) { 1746 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1747 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1748 1749 if (unlikely(rsc_enabled)) { 1750 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1751 1752 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1753 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1754 1755 /* update ntc based on RSC value */ 1756 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1757 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1758 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1759 } 1760 } 1761 1762 /* if we are the last buffer then there is nothing else to do */ 1763 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1764 return false; 1765 1766 /* place skb in next buffer to be received */ 1767 rx_ring->rx_buffer_info[ntc].skb = skb; 1768 rx_ring->rx_stats.non_eop_descs++; 1769 1770 return true; 1771 } 1772 1773 /** 1774 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1775 * @rx_ring: rx descriptor ring packet is being transacted on 1776 * @skb: pointer to current skb being adjusted 1777 * 1778 * This function is an ixgbe specific version of __pskb_pull_tail. The 1779 * main difference between this version and the original function is that 1780 * this function can make several assumptions about the state of things 1781 * that allow for significant optimizations versus the standard function. 1782 * As a result we can do things like drop a frag and maintain an accurate 1783 * truesize for the skb. 1784 */ 1785 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1786 struct sk_buff *skb) 1787 { 1788 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1789 unsigned char *va; 1790 unsigned int pull_len; 1791 1792 /* 1793 * it is valid to use page_address instead of kmap since we are 1794 * working with pages allocated out of the lomem pool per 1795 * alloc_page(GFP_ATOMIC) 1796 */ 1797 va = skb_frag_address(frag); 1798 1799 /* 1800 * we need the header to contain the greater of either ETH_HLEN or 1801 * 60 bytes if the skb->len is less than 60 for skb_pad. 1802 */ 1803 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1804 1805 /* align pull length to size of long to optimize memcpy performance */ 1806 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1807 1808 /* update all of the pointers */ 1809 skb_frag_size_sub(frag, pull_len); 1810 frag->page_offset += pull_len; 1811 skb->data_len -= pull_len; 1812 skb->tail += pull_len; 1813 } 1814 1815 /** 1816 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1817 * @rx_ring: rx descriptor ring packet is being transacted on 1818 * @skb: pointer to current skb being updated 1819 * 1820 * This function provides a basic DMA sync up for the first fragment of an 1821 * skb. The reason for doing this is that the first fragment cannot be 1822 * unmapped until we have reached the end of packet descriptor for a buffer 1823 * chain. 1824 */ 1825 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1826 struct sk_buff *skb) 1827 { 1828 /* if the page was released unmap it, else just sync our portion */ 1829 if (unlikely(IXGBE_CB(skb)->page_released)) { 1830 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1831 ixgbe_rx_pg_size(rx_ring), 1832 DMA_FROM_DEVICE, 1833 IXGBE_RX_DMA_ATTR); 1834 } else if (ring_uses_build_skb(rx_ring)) { 1835 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1836 1837 dma_sync_single_range_for_cpu(rx_ring->dev, 1838 IXGBE_CB(skb)->dma, 1839 offset, 1840 skb_headlen(skb), 1841 DMA_FROM_DEVICE); 1842 } else { 1843 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1844 1845 dma_sync_single_range_for_cpu(rx_ring->dev, 1846 IXGBE_CB(skb)->dma, 1847 frag->page_offset, 1848 skb_frag_size(frag), 1849 DMA_FROM_DEVICE); 1850 } 1851 } 1852 1853 /** 1854 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1855 * @rx_ring: rx descriptor ring packet is being transacted on 1856 * @rx_desc: pointer to the EOP Rx descriptor 1857 * @skb: pointer to current skb being fixed 1858 * 1859 * Check if the skb is valid in the XDP case it will be an error pointer. 1860 * Return true in this case to abort processing and advance to next 1861 * descriptor. 1862 * 1863 * Check for corrupted packet headers caused by senders on the local L2 1864 * embedded NIC switch not setting up their Tx Descriptors right. These 1865 * should be very rare. 1866 * 1867 * Also address the case where we are pulling data in on pages only 1868 * and as such no data is present in the skb header. 1869 * 1870 * In addition if skb is not at least 60 bytes we need to pad it so that 1871 * it is large enough to qualify as a valid Ethernet frame. 1872 * 1873 * Returns true if an error was encountered and skb was freed. 1874 **/ 1875 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1876 union ixgbe_adv_rx_desc *rx_desc, 1877 struct sk_buff *skb) 1878 { 1879 struct net_device *netdev = rx_ring->netdev; 1880 1881 /* XDP packets use error pointer so abort at this point */ 1882 if (IS_ERR(skb)) 1883 return true; 1884 1885 /* Verify netdev is present, and that packet does not have any 1886 * errors that would be unacceptable to the netdev. 1887 */ 1888 if (!netdev || 1889 (unlikely(ixgbe_test_staterr(rx_desc, 1890 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1891 !(netdev->features & NETIF_F_RXALL)))) { 1892 dev_kfree_skb_any(skb); 1893 return true; 1894 } 1895 1896 /* place header in linear portion of buffer */ 1897 if (!skb_headlen(skb)) 1898 ixgbe_pull_tail(rx_ring, skb); 1899 1900 #ifdef IXGBE_FCOE 1901 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1902 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1903 return false; 1904 1905 #endif 1906 /* if eth_skb_pad returns an error the skb was freed */ 1907 if (eth_skb_pad(skb)) 1908 return true; 1909 1910 return false; 1911 } 1912 1913 /** 1914 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1915 * @rx_ring: rx descriptor ring to store buffers on 1916 * @old_buff: donor buffer to have page reused 1917 * 1918 * Synchronizes page for reuse by the adapter 1919 **/ 1920 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1921 struct ixgbe_rx_buffer *old_buff) 1922 { 1923 struct ixgbe_rx_buffer *new_buff; 1924 u16 nta = rx_ring->next_to_alloc; 1925 1926 new_buff = &rx_ring->rx_buffer_info[nta]; 1927 1928 /* update, and store next to alloc */ 1929 nta++; 1930 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1931 1932 /* Transfer page from old buffer to new buffer. 1933 * Move each member individually to avoid possible store 1934 * forwarding stalls and unnecessary copy of skb. 1935 */ 1936 new_buff->dma = old_buff->dma; 1937 new_buff->page = old_buff->page; 1938 new_buff->page_offset = old_buff->page_offset; 1939 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1940 } 1941 1942 static inline bool ixgbe_page_is_reserved(struct page *page) 1943 { 1944 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1945 } 1946 1947 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1948 { 1949 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1950 struct page *page = rx_buffer->page; 1951 1952 /* avoid re-using remote pages */ 1953 if (unlikely(ixgbe_page_is_reserved(page))) 1954 return false; 1955 1956 #if (PAGE_SIZE < 8192) 1957 /* if we are only owner of page we can reuse it */ 1958 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1959 return false; 1960 #else 1961 /* The last offset is a bit aggressive in that we assume the 1962 * worst case of FCoE being enabled and using a 3K buffer. 1963 * However this should have minimal impact as the 1K extra is 1964 * still less than one buffer in size. 1965 */ 1966 #define IXGBE_LAST_OFFSET \ 1967 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1968 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1969 return false; 1970 #endif 1971 1972 /* If we have drained the page fragment pool we need to update 1973 * the pagecnt_bias and page count so that we fully restock the 1974 * number of references the driver holds. 1975 */ 1976 if (unlikely(pagecnt_bias == 1)) { 1977 page_ref_add(page, USHRT_MAX - 1); 1978 rx_buffer->pagecnt_bias = USHRT_MAX; 1979 } 1980 1981 return true; 1982 } 1983 1984 /** 1985 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1986 * @rx_ring: rx descriptor ring to transact packets on 1987 * @rx_buffer: buffer containing page to add 1988 * @skb: sk_buff to place the data into 1989 * @size: size of data in rx_buffer 1990 * 1991 * This function will add the data contained in rx_buffer->page to the skb. 1992 * This is done either through a direct copy if the data in the buffer is 1993 * less than the skb header size, otherwise it will just attach the page as 1994 * a frag to the skb. 1995 * 1996 * The function will then update the page offset if necessary and return 1997 * true if the buffer can be reused by the adapter. 1998 **/ 1999 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2000 struct ixgbe_rx_buffer *rx_buffer, 2001 struct sk_buff *skb, 2002 unsigned int size) 2003 { 2004 #if (PAGE_SIZE < 8192) 2005 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2006 #else 2007 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2008 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2009 SKB_DATA_ALIGN(size); 2010 #endif 2011 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2012 rx_buffer->page_offset, size, truesize); 2013 #if (PAGE_SIZE < 8192) 2014 rx_buffer->page_offset ^= truesize; 2015 #else 2016 rx_buffer->page_offset += truesize; 2017 #endif 2018 } 2019 2020 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2021 union ixgbe_adv_rx_desc *rx_desc, 2022 struct sk_buff **skb, 2023 const unsigned int size) 2024 { 2025 struct ixgbe_rx_buffer *rx_buffer; 2026 2027 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2028 prefetchw(rx_buffer->page); 2029 *skb = rx_buffer->skb; 2030 2031 /* Delay unmapping of the first packet. It carries the header 2032 * information, HW may still access the header after the writeback. 2033 * Only unmap it when EOP is reached 2034 */ 2035 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2036 if (!*skb) 2037 goto skip_sync; 2038 } else { 2039 if (*skb) 2040 ixgbe_dma_sync_frag(rx_ring, *skb); 2041 } 2042 2043 /* we are reusing so sync this buffer for CPU use */ 2044 dma_sync_single_range_for_cpu(rx_ring->dev, 2045 rx_buffer->dma, 2046 rx_buffer->page_offset, 2047 size, 2048 DMA_FROM_DEVICE); 2049 skip_sync: 2050 rx_buffer->pagecnt_bias--; 2051 2052 return rx_buffer; 2053 } 2054 2055 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2056 struct ixgbe_rx_buffer *rx_buffer, 2057 struct sk_buff *skb) 2058 { 2059 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2060 /* hand second half of page back to the ring */ 2061 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2062 } else { 2063 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2064 /* the page has been released from the ring */ 2065 IXGBE_CB(skb)->page_released = true; 2066 } else { 2067 /* we are not reusing the buffer so unmap it */ 2068 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2069 ixgbe_rx_pg_size(rx_ring), 2070 DMA_FROM_DEVICE, 2071 IXGBE_RX_DMA_ATTR); 2072 } 2073 __page_frag_cache_drain(rx_buffer->page, 2074 rx_buffer->pagecnt_bias); 2075 } 2076 2077 /* clear contents of rx_buffer */ 2078 rx_buffer->page = NULL; 2079 rx_buffer->skb = NULL; 2080 } 2081 2082 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2083 struct ixgbe_rx_buffer *rx_buffer, 2084 struct xdp_buff *xdp, 2085 union ixgbe_adv_rx_desc *rx_desc) 2086 { 2087 unsigned int size = xdp->data_end - xdp->data; 2088 #if (PAGE_SIZE < 8192) 2089 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2090 #else 2091 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2092 xdp->data_hard_start); 2093 #endif 2094 struct sk_buff *skb; 2095 2096 /* prefetch first cache line of first page */ 2097 prefetch(xdp->data); 2098 #if L1_CACHE_BYTES < 128 2099 prefetch(xdp->data + L1_CACHE_BYTES); 2100 #endif 2101 /* Note, we get here by enabling legacy-rx via: 2102 * 2103 * ethtool --set-priv-flags <dev> legacy-rx on 2104 * 2105 * In this mode, we currently get 0 extra XDP headroom as 2106 * opposed to having legacy-rx off, where we process XDP 2107 * packets going to stack via ixgbe_build_skb(). The latter 2108 * provides us currently with 192 bytes of headroom. 2109 * 2110 * For ixgbe_construct_skb() mode it means that the 2111 * xdp->data_meta will always point to xdp->data, since 2112 * the helper cannot expand the head. Should this ever 2113 * change in future for legacy-rx mode on, then lets also 2114 * add xdp->data_meta handling here. 2115 */ 2116 2117 /* allocate a skb to store the frags */ 2118 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2119 if (unlikely(!skb)) 2120 return NULL; 2121 2122 if (size > IXGBE_RX_HDR_SIZE) { 2123 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2124 IXGBE_CB(skb)->dma = rx_buffer->dma; 2125 2126 skb_add_rx_frag(skb, 0, rx_buffer->page, 2127 xdp->data - page_address(rx_buffer->page), 2128 size, truesize); 2129 #if (PAGE_SIZE < 8192) 2130 rx_buffer->page_offset ^= truesize; 2131 #else 2132 rx_buffer->page_offset += truesize; 2133 #endif 2134 } else { 2135 memcpy(__skb_put(skb, size), 2136 xdp->data, ALIGN(size, sizeof(long))); 2137 rx_buffer->pagecnt_bias++; 2138 } 2139 2140 return skb; 2141 } 2142 2143 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2144 struct ixgbe_rx_buffer *rx_buffer, 2145 struct xdp_buff *xdp, 2146 union ixgbe_adv_rx_desc *rx_desc) 2147 { 2148 unsigned int metasize = xdp->data - xdp->data_meta; 2149 #if (PAGE_SIZE < 8192) 2150 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2151 #else 2152 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2153 SKB_DATA_ALIGN(xdp->data_end - 2154 xdp->data_hard_start); 2155 #endif 2156 struct sk_buff *skb; 2157 2158 /* Prefetch first cache line of first page. If xdp->data_meta 2159 * is unused, this points extactly as xdp->data, otherwise we 2160 * likely have a consumer accessing first few bytes of meta 2161 * data, and then actual data. 2162 */ 2163 prefetch(xdp->data_meta); 2164 #if L1_CACHE_BYTES < 128 2165 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2166 #endif 2167 2168 /* build an skb to around the page buffer */ 2169 skb = build_skb(xdp->data_hard_start, truesize); 2170 if (unlikely(!skb)) 2171 return NULL; 2172 2173 /* update pointers within the skb to store the data */ 2174 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2175 __skb_put(skb, xdp->data_end - xdp->data); 2176 if (metasize) 2177 skb_metadata_set(skb, metasize); 2178 2179 /* record DMA address if this is the start of a chain of buffers */ 2180 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2181 IXGBE_CB(skb)->dma = rx_buffer->dma; 2182 2183 /* update buffer offset */ 2184 #if (PAGE_SIZE < 8192) 2185 rx_buffer->page_offset ^= truesize; 2186 #else 2187 rx_buffer->page_offset += truesize; 2188 #endif 2189 2190 return skb; 2191 } 2192 2193 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2194 struct ixgbe_ring *rx_ring, 2195 struct xdp_buff *xdp) 2196 { 2197 int err, result = IXGBE_XDP_PASS; 2198 struct bpf_prog *xdp_prog; 2199 struct xdp_frame *xdpf; 2200 u32 act; 2201 2202 rcu_read_lock(); 2203 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2204 2205 if (!xdp_prog) 2206 goto xdp_out; 2207 2208 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2209 2210 act = bpf_prog_run_xdp(xdp_prog, xdp); 2211 switch (act) { 2212 case XDP_PASS: 2213 break; 2214 case XDP_TX: 2215 xdpf = convert_to_xdp_frame(xdp); 2216 if (unlikely(!xdpf)) { 2217 result = IXGBE_XDP_CONSUMED; 2218 break; 2219 } 2220 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2221 break; 2222 case XDP_REDIRECT: 2223 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2224 if (!err) 2225 result = IXGBE_XDP_REDIR; 2226 else 2227 result = IXGBE_XDP_CONSUMED; 2228 break; 2229 default: 2230 bpf_warn_invalid_xdp_action(act); 2231 /* fallthrough */ 2232 case XDP_ABORTED: 2233 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2234 /* fallthrough -- handle aborts by dropping packet */ 2235 case XDP_DROP: 2236 result = IXGBE_XDP_CONSUMED; 2237 break; 2238 } 2239 xdp_out: 2240 rcu_read_unlock(); 2241 return ERR_PTR(-result); 2242 } 2243 2244 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2245 struct ixgbe_rx_buffer *rx_buffer, 2246 unsigned int size) 2247 { 2248 #if (PAGE_SIZE < 8192) 2249 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2250 2251 rx_buffer->page_offset ^= truesize; 2252 #else 2253 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2254 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2255 SKB_DATA_ALIGN(size); 2256 2257 rx_buffer->page_offset += truesize; 2258 #endif 2259 } 2260 2261 /** 2262 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2263 * @q_vector: structure containing interrupt and ring information 2264 * @rx_ring: rx descriptor ring to transact packets on 2265 * @budget: Total limit on number of packets to process 2266 * 2267 * This function provides a "bounce buffer" approach to Rx interrupt 2268 * processing. The advantage to this is that on systems that have 2269 * expensive overhead for IOMMU access this provides a means of avoiding 2270 * it by maintaining the mapping of the page to the syste. 2271 * 2272 * Returns amount of work completed 2273 **/ 2274 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2275 struct ixgbe_ring *rx_ring, 2276 const int budget) 2277 { 2278 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2279 struct ixgbe_adapter *adapter = q_vector->adapter; 2280 #ifdef IXGBE_FCOE 2281 int ddp_bytes; 2282 unsigned int mss = 0; 2283 #endif /* IXGBE_FCOE */ 2284 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2285 unsigned int xdp_xmit = 0; 2286 struct xdp_buff xdp; 2287 2288 xdp.rxq = &rx_ring->xdp_rxq; 2289 2290 while (likely(total_rx_packets < budget)) { 2291 union ixgbe_adv_rx_desc *rx_desc; 2292 struct ixgbe_rx_buffer *rx_buffer; 2293 struct sk_buff *skb; 2294 unsigned int size; 2295 2296 /* return some buffers to hardware, one at a time is too slow */ 2297 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2298 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2299 cleaned_count = 0; 2300 } 2301 2302 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2303 size = le16_to_cpu(rx_desc->wb.upper.length); 2304 if (!size) 2305 break; 2306 2307 /* This memory barrier is needed to keep us from reading 2308 * any other fields out of the rx_desc until we know the 2309 * descriptor has been written back 2310 */ 2311 dma_rmb(); 2312 2313 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2314 2315 /* retrieve a buffer from the ring */ 2316 if (!skb) { 2317 xdp.data = page_address(rx_buffer->page) + 2318 rx_buffer->page_offset; 2319 xdp.data_meta = xdp.data; 2320 xdp.data_hard_start = xdp.data - 2321 ixgbe_rx_offset(rx_ring); 2322 xdp.data_end = xdp.data + size; 2323 2324 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2325 } 2326 2327 if (IS_ERR(skb)) { 2328 unsigned int xdp_res = -PTR_ERR(skb); 2329 2330 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2331 xdp_xmit |= xdp_res; 2332 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2333 } else { 2334 rx_buffer->pagecnt_bias++; 2335 } 2336 total_rx_packets++; 2337 total_rx_bytes += size; 2338 } else if (skb) { 2339 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2340 } else if (ring_uses_build_skb(rx_ring)) { 2341 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2342 &xdp, rx_desc); 2343 } else { 2344 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2345 &xdp, rx_desc); 2346 } 2347 2348 /* exit if we failed to retrieve a buffer */ 2349 if (!skb) { 2350 rx_ring->rx_stats.alloc_rx_buff_failed++; 2351 rx_buffer->pagecnt_bias++; 2352 break; 2353 } 2354 2355 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2356 cleaned_count++; 2357 2358 /* place incomplete frames back on ring for completion */ 2359 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2360 continue; 2361 2362 /* verify the packet layout is correct */ 2363 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2364 continue; 2365 2366 /* probably a little skewed due to removing CRC */ 2367 total_rx_bytes += skb->len; 2368 2369 /* populate checksum, timestamp, VLAN, and protocol */ 2370 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2371 2372 #ifdef IXGBE_FCOE 2373 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2374 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2375 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2376 /* include DDPed FCoE data */ 2377 if (ddp_bytes > 0) { 2378 if (!mss) { 2379 mss = rx_ring->netdev->mtu - 2380 sizeof(struct fcoe_hdr) - 2381 sizeof(struct fc_frame_header) - 2382 sizeof(struct fcoe_crc_eof); 2383 if (mss > 512) 2384 mss &= ~511; 2385 } 2386 total_rx_bytes += ddp_bytes; 2387 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2388 mss); 2389 } 2390 if (!ddp_bytes) { 2391 dev_kfree_skb_any(skb); 2392 continue; 2393 } 2394 } 2395 2396 #endif /* IXGBE_FCOE */ 2397 ixgbe_rx_skb(q_vector, skb); 2398 2399 /* update budget accounting */ 2400 total_rx_packets++; 2401 } 2402 2403 if (xdp_xmit & IXGBE_XDP_REDIR) 2404 xdp_do_flush_map(); 2405 2406 if (xdp_xmit & IXGBE_XDP_TX) { 2407 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2408 2409 /* Force memory writes to complete before letting h/w 2410 * know there are new descriptors to fetch. 2411 */ 2412 wmb(); 2413 writel(ring->next_to_use, ring->tail); 2414 } 2415 2416 u64_stats_update_begin(&rx_ring->syncp); 2417 rx_ring->stats.packets += total_rx_packets; 2418 rx_ring->stats.bytes += total_rx_bytes; 2419 u64_stats_update_end(&rx_ring->syncp); 2420 q_vector->rx.total_packets += total_rx_packets; 2421 q_vector->rx.total_bytes += total_rx_bytes; 2422 2423 return total_rx_packets; 2424 } 2425 2426 /** 2427 * ixgbe_configure_msix - Configure MSI-X hardware 2428 * @adapter: board private structure 2429 * 2430 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2431 * interrupts. 2432 **/ 2433 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2434 { 2435 struct ixgbe_q_vector *q_vector; 2436 int v_idx; 2437 u32 mask; 2438 2439 /* Populate MSIX to EITR Select */ 2440 if (adapter->num_vfs > 32) { 2441 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2442 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2443 } 2444 2445 /* 2446 * Populate the IVAR table and set the ITR values to the 2447 * corresponding register. 2448 */ 2449 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2450 struct ixgbe_ring *ring; 2451 q_vector = adapter->q_vector[v_idx]; 2452 2453 ixgbe_for_each_ring(ring, q_vector->rx) 2454 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2455 2456 ixgbe_for_each_ring(ring, q_vector->tx) 2457 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2458 2459 ixgbe_write_eitr(q_vector); 2460 } 2461 2462 switch (adapter->hw.mac.type) { 2463 case ixgbe_mac_82598EB: 2464 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2465 v_idx); 2466 break; 2467 case ixgbe_mac_82599EB: 2468 case ixgbe_mac_X540: 2469 case ixgbe_mac_X550: 2470 case ixgbe_mac_X550EM_x: 2471 case ixgbe_mac_x550em_a: 2472 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2473 break; 2474 default: 2475 break; 2476 } 2477 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2478 2479 /* set up to autoclear timer, and the vectors */ 2480 mask = IXGBE_EIMS_ENABLE_MASK; 2481 mask &= ~(IXGBE_EIMS_OTHER | 2482 IXGBE_EIMS_MAILBOX | 2483 IXGBE_EIMS_LSC); 2484 2485 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2486 } 2487 2488 /** 2489 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2490 * @q_vector: structure containing interrupt and ring information 2491 * @ring_container: structure containing ring performance data 2492 * 2493 * Stores a new ITR value based on packets and byte 2494 * counts during the last interrupt. The advantage of per interrupt 2495 * computation is faster updates and more accurate ITR for the current 2496 * traffic pattern. Constants in this function were computed 2497 * based on theoretical maximum wire speed and thresholds were set based 2498 * on testing data as well as attempting to minimize response time 2499 * while increasing bulk throughput. 2500 **/ 2501 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2502 struct ixgbe_ring_container *ring_container) 2503 { 2504 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2505 IXGBE_ITR_ADAPTIVE_LATENCY; 2506 unsigned int avg_wire_size, packets, bytes; 2507 unsigned long next_update = jiffies; 2508 2509 /* If we don't have any rings just leave ourselves set for maximum 2510 * possible latency so we take ourselves out of the equation. 2511 */ 2512 if (!ring_container->ring) 2513 return; 2514 2515 /* If we didn't update within up to 1 - 2 jiffies we can assume 2516 * that either packets are coming in so slow there hasn't been 2517 * any work, or that there is so much work that NAPI is dealing 2518 * with interrupt moderation and we don't need to do anything. 2519 */ 2520 if (time_after(next_update, ring_container->next_update)) 2521 goto clear_counts; 2522 2523 packets = ring_container->total_packets; 2524 2525 /* We have no packets to actually measure against. This means 2526 * either one of the other queues on this vector is active or 2527 * we are a Tx queue doing TSO with too high of an interrupt rate. 2528 * 2529 * When this occurs just tick up our delay by the minimum value 2530 * and hope that this extra delay will prevent us from being called 2531 * without any work on our queue. 2532 */ 2533 if (!packets) { 2534 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2535 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2536 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2537 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2538 goto clear_counts; 2539 } 2540 2541 bytes = ring_container->total_bytes; 2542 2543 /* If packets are less than 4 or bytes are less than 9000 assume 2544 * insufficient data to use bulk rate limiting approach. We are 2545 * likely latency driven. 2546 */ 2547 if (packets < 4 && bytes < 9000) { 2548 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2549 goto adjust_by_size; 2550 } 2551 2552 /* Between 4 and 48 we can assume that our current interrupt delay 2553 * is only slightly too low. As such we should increase it by a small 2554 * fixed amount. 2555 */ 2556 if (packets < 48) { 2557 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2558 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2559 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2560 goto clear_counts; 2561 } 2562 2563 /* Between 48 and 96 is our "goldilocks" zone where we are working 2564 * out "just right". Just report that our current ITR is good for us. 2565 */ 2566 if (packets < 96) { 2567 itr = q_vector->itr >> 2; 2568 goto clear_counts; 2569 } 2570 2571 /* If packet count is 96 or greater we are likely looking at a slight 2572 * overrun of the delay we want. Try halving our delay to see if that 2573 * will cut the number of packets in half per interrupt. 2574 */ 2575 if (packets < 256) { 2576 itr = q_vector->itr >> 3; 2577 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2578 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2579 goto clear_counts; 2580 } 2581 2582 /* The paths below assume we are dealing with a bulk ITR since number 2583 * of packets is 256 or greater. We are just going to have to compute 2584 * a value and try to bring the count under control, though for smaller 2585 * packet sizes there isn't much we can do as NAPI polling will likely 2586 * be kicking in sooner rather than later. 2587 */ 2588 itr = IXGBE_ITR_ADAPTIVE_BULK; 2589 2590 adjust_by_size: 2591 /* If packet counts are 256 or greater we can assume we have a gross 2592 * overestimation of what the rate should be. Instead of trying to fine 2593 * tune it just use the formula below to try and dial in an exact value 2594 * give the current packet size of the frame. 2595 */ 2596 avg_wire_size = bytes / packets; 2597 2598 /* The following is a crude approximation of: 2599 * wmem_default / (size + overhead) = desired_pkts_per_int 2600 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2601 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2602 * 2603 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2604 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2605 * formula down to 2606 * 2607 * (170 * (size + 24)) / (size + 640) = ITR 2608 * 2609 * We first do some math on the packet size and then finally bitshift 2610 * by 8 after rounding up. We also have to account for PCIe link speed 2611 * difference as ITR scales based on this. 2612 */ 2613 if (avg_wire_size <= 60) { 2614 /* Start at 50k ints/sec */ 2615 avg_wire_size = 5120; 2616 } else if (avg_wire_size <= 316) { 2617 /* 50K ints/sec to 16K ints/sec */ 2618 avg_wire_size *= 40; 2619 avg_wire_size += 2720; 2620 } else if (avg_wire_size <= 1084) { 2621 /* 16K ints/sec to 9.2K ints/sec */ 2622 avg_wire_size *= 15; 2623 avg_wire_size += 11452; 2624 } else if (avg_wire_size <= 1980) { 2625 /* 9.2K ints/sec to 8K ints/sec */ 2626 avg_wire_size *= 5; 2627 avg_wire_size += 22420; 2628 } else { 2629 /* plateau at a limit of 8K ints/sec */ 2630 avg_wire_size = 32256; 2631 } 2632 2633 /* If we are in low latency mode half our delay which doubles the rate 2634 * to somewhere between 100K to 16K ints/sec 2635 */ 2636 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2637 avg_wire_size >>= 1; 2638 2639 /* Resultant value is 256 times larger than it needs to be. This 2640 * gives us room to adjust the value as needed to either increase 2641 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2642 * 2643 * Use addition as we have already recorded the new latency flag 2644 * for the ITR value. 2645 */ 2646 switch (q_vector->adapter->link_speed) { 2647 case IXGBE_LINK_SPEED_10GB_FULL: 2648 case IXGBE_LINK_SPEED_100_FULL: 2649 default: 2650 itr += DIV_ROUND_UP(avg_wire_size, 2651 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2652 IXGBE_ITR_ADAPTIVE_MIN_INC; 2653 break; 2654 case IXGBE_LINK_SPEED_2_5GB_FULL: 2655 case IXGBE_LINK_SPEED_1GB_FULL: 2656 case IXGBE_LINK_SPEED_10_FULL: 2657 itr += DIV_ROUND_UP(avg_wire_size, 2658 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2659 IXGBE_ITR_ADAPTIVE_MIN_INC; 2660 break; 2661 } 2662 2663 clear_counts: 2664 /* write back value */ 2665 ring_container->itr = itr; 2666 2667 /* next update should occur within next jiffy */ 2668 ring_container->next_update = next_update + 1; 2669 2670 ring_container->total_bytes = 0; 2671 ring_container->total_packets = 0; 2672 } 2673 2674 /** 2675 * ixgbe_write_eitr - write EITR register in hardware specific way 2676 * @q_vector: structure containing interrupt and ring information 2677 * 2678 * This function is made to be called by ethtool and by the driver 2679 * when it needs to update EITR registers at runtime. Hardware 2680 * specific quirks/differences are taken care of here. 2681 */ 2682 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2683 { 2684 struct ixgbe_adapter *adapter = q_vector->adapter; 2685 struct ixgbe_hw *hw = &adapter->hw; 2686 int v_idx = q_vector->v_idx; 2687 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2688 2689 switch (adapter->hw.mac.type) { 2690 case ixgbe_mac_82598EB: 2691 /* must write high and low 16 bits to reset counter */ 2692 itr_reg |= (itr_reg << 16); 2693 break; 2694 case ixgbe_mac_82599EB: 2695 case ixgbe_mac_X540: 2696 case ixgbe_mac_X550: 2697 case ixgbe_mac_X550EM_x: 2698 case ixgbe_mac_x550em_a: 2699 /* 2700 * set the WDIS bit to not clear the timer bits and cause an 2701 * immediate assertion of the interrupt 2702 */ 2703 itr_reg |= IXGBE_EITR_CNT_WDIS; 2704 break; 2705 default: 2706 break; 2707 } 2708 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2709 } 2710 2711 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2712 { 2713 u32 new_itr; 2714 2715 ixgbe_update_itr(q_vector, &q_vector->tx); 2716 ixgbe_update_itr(q_vector, &q_vector->rx); 2717 2718 /* use the smallest value of new ITR delay calculations */ 2719 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2720 2721 /* Clear latency flag if set, shift into correct position */ 2722 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2723 new_itr <<= 2; 2724 2725 if (new_itr != q_vector->itr) { 2726 /* save the algorithm value here */ 2727 q_vector->itr = new_itr; 2728 2729 ixgbe_write_eitr(q_vector); 2730 } 2731 } 2732 2733 /** 2734 * ixgbe_check_overtemp_subtask - check for over temperature 2735 * @adapter: pointer to adapter 2736 **/ 2737 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2738 { 2739 struct ixgbe_hw *hw = &adapter->hw; 2740 u32 eicr = adapter->interrupt_event; 2741 s32 rc; 2742 2743 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2744 return; 2745 2746 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2747 return; 2748 2749 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2750 2751 switch (hw->device_id) { 2752 case IXGBE_DEV_ID_82599_T3_LOM: 2753 /* 2754 * Since the warning interrupt is for both ports 2755 * we don't have to check if: 2756 * - This interrupt wasn't for our port. 2757 * - We may have missed the interrupt so always have to 2758 * check if we got a LSC 2759 */ 2760 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2761 !(eicr & IXGBE_EICR_LSC)) 2762 return; 2763 2764 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2765 u32 speed; 2766 bool link_up = false; 2767 2768 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2769 2770 if (link_up) 2771 return; 2772 } 2773 2774 /* Check if this is not due to overtemp */ 2775 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2776 return; 2777 2778 break; 2779 case IXGBE_DEV_ID_X550EM_A_1G_T: 2780 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2781 rc = hw->phy.ops.check_overtemp(hw); 2782 if (rc != IXGBE_ERR_OVERTEMP) 2783 return; 2784 break; 2785 default: 2786 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2787 return; 2788 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2789 return; 2790 break; 2791 } 2792 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2793 2794 adapter->interrupt_event = 0; 2795 } 2796 2797 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2798 { 2799 struct ixgbe_hw *hw = &adapter->hw; 2800 2801 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2802 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2803 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2804 /* write to clear the interrupt */ 2805 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2806 } 2807 } 2808 2809 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2810 { 2811 struct ixgbe_hw *hw = &adapter->hw; 2812 2813 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2814 return; 2815 2816 switch (adapter->hw.mac.type) { 2817 case ixgbe_mac_82599EB: 2818 /* 2819 * Need to check link state so complete overtemp check 2820 * on service task 2821 */ 2822 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2823 (eicr & IXGBE_EICR_LSC)) && 2824 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2825 adapter->interrupt_event = eicr; 2826 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2827 ixgbe_service_event_schedule(adapter); 2828 return; 2829 } 2830 return; 2831 case ixgbe_mac_x550em_a: 2832 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2833 adapter->interrupt_event = eicr; 2834 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2835 ixgbe_service_event_schedule(adapter); 2836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2837 IXGBE_EICR_GPI_SDP0_X550EM_a); 2838 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2839 IXGBE_EICR_GPI_SDP0_X550EM_a); 2840 } 2841 return; 2842 case ixgbe_mac_X550: 2843 case ixgbe_mac_X540: 2844 if (!(eicr & IXGBE_EICR_TS)) 2845 return; 2846 break; 2847 default: 2848 return; 2849 } 2850 2851 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2852 } 2853 2854 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2855 { 2856 switch (hw->mac.type) { 2857 case ixgbe_mac_82598EB: 2858 if (hw->phy.type == ixgbe_phy_nl) 2859 return true; 2860 return false; 2861 case ixgbe_mac_82599EB: 2862 case ixgbe_mac_X550EM_x: 2863 case ixgbe_mac_x550em_a: 2864 switch (hw->mac.ops.get_media_type(hw)) { 2865 case ixgbe_media_type_fiber: 2866 case ixgbe_media_type_fiber_qsfp: 2867 return true; 2868 default: 2869 return false; 2870 } 2871 default: 2872 return false; 2873 } 2874 } 2875 2876 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2877 { 2878 struct ixgbe_hw *hw = &adapter->hw; 2879 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2880 2881 if (!ixgbe_is_sfp(hw)) 2882 return; 2883 2884 /* Later MAC's use different SDP */ 2885 if (hw->mac.type >= ixgbe_mac_X540) 2886 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2887 2888 if (eicr & eicr_mask) { 2889 /* Clear the interrupt */ 2890 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2891 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2892 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2893 adapter->sfp_poll_time = 0; 2894 ixgbe_service_event_schedule(adapter); 2895 } 2896 } 2897 2898 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2899 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2900 /* Clear the interrupt */ 2901 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2902 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2903 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2904 ixgbe_service_event_schedule(adapter); 2905 } 2906 } 2907 } 2908 2909 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2910 { 2911 struct ixgbe_hw *hw = &adapter->hw; 2912 2913 adapter->lsc_int++; 2914 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2915 adapter->link_check_timeout = jiffies; 2916 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2917 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2918 IXGBE_WRITE_FLUSH(hw); 2919 ixgbe_service_event_schedule(adapter); 2920 } 2921 } 2922 2923 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2924 u64 qmask) 2925 { 2926 u32 mask; 2927 struct ixgbe_hw *hw = &adapter->hw; 2928 2929 switch (hw->mac.type) { 2930 case ixgbe_mac_82598EB: 2931 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2932 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2933 break; 2934 case ixgbe_mac_82599EB: 2935 case ixgbe_mac_X540: 2936 case ixgbe_mac_X550: 2937 case ixgbe_mac_X550EM_x: 2938 case ixgbe_mac_x550em_a: 2939 mask = (qmask & 0xFFFFFFFF); 2940 if (mask) 2941 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2942 mask = (qmask >> 32); 2943 if (mask) 2944 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2945 break; 2946 default: 2947 break; 2948 } 2949 /* skip the flush */ 2950 } 2951 2952 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2953 u64 qmask) 2954 { 2955 u32 mask; 2956 struct ixgbe_hw *hw = &adapter->hw; 2957 2958 switch (hw->mac.type) { 2959 case ixgbe_mac_82598EB: 2960 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2961 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2962 break; 2963 case ixgbe_mac_82599EB: 2964 case ixgbe_mac_X540: 2965 case ixgbe_mac_X550: 2966 case ixgbe_mac_X550EM_x: 2967 case ixgbe_mac_x550em_a: 2968 mask = (qmask & 0xFFFFFFFF); 2969 if (mask) 2970 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2971 mask = (qmask >> 32); 2972 if (mask) 2973 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2974 break; 2975 default: 2976 break; 2977 } 2978 /* skip the flush */ 2979 } 2980 2981 /** 2982 * ixgbe_irq_enable - Enable default interrupt generation settings 2983 * @adapter: board private structure 2984 * @queues: enable irqs for queues 2985 * @flush: flush register write 2986 **/ 2987 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2988 bool flush) 2989 { 2990 struct ixgbe_hw *hw = &adapter->hw; 2991 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2992 2993 /* don't reenable LSC while waiting for link */ 2994 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2995 mask &= ~IXGBE_EIMS_LSC; 2996 2997 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2998 switch (adapter->hw.mac.type) { 2999 case ixgbe_mac_82599EB: 3000 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3001 break; 3002 case ixgbe_mac_X540: 3003 case ixgbe_mac_X550: 3004 case ixgbe_mac_X550EM_x: 3005 case ixgbe_mac_x550em_a: 3006 mask |= IXGBE_EIMS_TS; 3007 break; 3008 default: 3009 break; 3010 } 3011 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3012 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3013 switch (adapter->hw.mac.type) { 3014 case ixgbe_mac_82599EB: 3015 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3016 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3017 /* fall through */ 3018 case ixgbe_mac_X540: 3019 case ixgbe_mac_X550: 3020 case ixgbe_mac_X550EM_x: 3021 case ixgbe_mac_x550em_a: 3022 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3023 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3024 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3025 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3026 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3027 mask |= IXGBE_EICR_GPI_SDP0_X540; 3028 mask |= IXGBE_EIMS_ECC; 3029 mask |= IXGBE_EIMS_MAILBOX; 3030 break; 3031 default: 3032 break; 3033 } 3034 3035 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3036 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3037 mask |= IXGBE_EIMS_FLOW_DIR; 3038 3039 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3040 if (queues) 3041 ixgbe_irq_enable_queues(adapter, ~0); 3042 if (flush) 3043 IXGBE_WRITE_FLUSH(&adapter->hw); 3044 } 3045 3046 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3047 { 3048 struct ixgbe_adapter *adapter = data; 3049 struct ixgbe_hw *hw = &adapter->hw; 3050 u32 eicr; 3051 3052 /* 3053 * Workaround for Silicon errata. Use clear-by-write instead 3054 * of clear-by-read. Reading with EICS will return the 3055 * interrupt causes without clearing, which later be done 3056 * with the write to EICR. 3057 */ 3058 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3059 3060 /* The lower 16bits of the EICR register are for the queue interrupts 3061 * which should be masked here in order to not accidentally clear them if 3062 * the bits are high when ixgbe_msix_other is called. There is a race 3063 * condition otherwise which results in possible performance loss 3064 * especially if the ixgbe_msix_other interrupt is triggering 3065 * consistently (as it would when PPS is turned on for the X540 device) 3066 */ 3067 eicr &= 0xFFFF0000; 3068 3069 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3070 3071 if (eicr & IXGBE_EICR_LSC) 3072 ixgbe_check_lsc(adapter); 3073 3074 if (eicr & IXGBE_EICR_MAILBOX) 3075 ixgbe_msg_task(adapter); 3076 3077 switch (hw->mac.type) { 3078 case ixgbe_mac_82599EB: 3079 case ixgbe_mac_X540: 3080 case ixgbe_mac_X550: 3081 case ixgbe_mac_X550EM_x: 3082 case ixgbe_mac_x550em_a: 3083 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3084 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3085 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3086 ixgbe_service_event_schedule(adapter); 3087 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3088 IXGBE_EICR_GPI_SDP0_X540); 3089 } 3090 if (eicr & IXGBE_EICR_ECC) { 3091 e_info(link, "Received ECC Err, initiating reset\n"); 3092 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3093 ixgbe_service_event_schedule(adapter); 3094 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3095 } 3096 /* Handle Flow Director Full threshold interrupt */ 3097 if (eicr & IXGBE_EICR_FLOW_DIR) { 3098 int reinit_count = 0; 3099 int i; 3100 for (i = 0; i < adapter->num_tx_queues; i++) { 3101 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3102 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3103 &ring->state)) 3104 reinit_count++; 3105 } 3106 if (reinit_count) { 3107 /* no more flow director interrupts until after init */ 3108 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3109 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3110 ixgbe_service_event_schedule(adapter); 3111 } 3112 } 3113 ixgbe_check_sfp_event(adapter, eicr); 3114 ixgbe_check_overtemp_event(adapter, eicr); 3115 break; 3116 default: 3117 break; 3118 } 3119 3120 ixgbe_check_fan_failure(adapter, eicr); 3121 3122 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3123 ixgbe_ptp_check_pps_event(adapter); 3124 3125 /* re-enable the original interrupt state, no lsc, no queues */ 3126 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3127 ixgbe_irq_enable(adapter, false, false); 3128 3129 return IRQ_HANDLED; 3130 } 3131 3132 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3133 { 3134 struct ixgbe_q_vector *q_vector = data; 3135 3136 /* EIAM disabled interrupts (on this vector) for us */ 3137 3138 if (q_vector->rx.ring || q_vector->tx.ring) 3139 napi_schedule_irqoff(&q_vector->napi); 3140 3141 return IRQ_HANDLED; 3142 } 3143 3144 /** 3145 * ixgbe_poll - NAPI Rx polling callback 3146 * @napi: structure for representing this polling device 3147 * @budget: how many packets driver is allowed to clean 3148 * 3149 * This function is used for legacy and MSI, NAPI mode 3150 **/ 3151 int ixgbe_poll(struct napi_struct *napi, int budget) 3152 { 3153 struct ixgbe_q_vector *q_vector = 3154 container_of(napi, struct ixgbe_q_vector, napi); 3155 struct ixgbe_adapter *adapter = q_vector->adapter; 3156 struct ixgbe_ring *ring; 3157 int per_ring_budget, work_done = 0; 3158 bool clean_complete = true; 3159 3160 #ifdef CONFIG_IXGBE_DCA 3161 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3162 ixgbe_update_dca(q_vector); 3163 #endif 3164 3165 ixgbe_for_each_ring(ring, q_vector->tx) { 3166 bool wd = ring->xsk_umem ? 3167 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3168 ixgbe_clean_tx_irq(q_vector, ring, budget); 3169 3170 if (!wd) 3171 clean_complete = false; 3172 } 3173 3174 /* Exit if we are called by netpoll */ 3175 if (budget <= 0) 3176 return budget; 3177 3178 /* attempt to distribute budget to each queue fairly, but don't allow 3179 * the budget to go below 1 because we'll exit polling */ 3180 if (q_vector->rx.count > 1) 3181 per_ring_budget = max(budget/q_vector->rx.count, 1); 3182 else 3183 per_ring_budget = budget; 3184 3185 ixgbe_for_each_ring(ring, q_vector->rx) { 3186 int cleaned = ring->xsk_umem ? 3187 ixgbe_clean_rx_irq_zc(q_vector, ring, 3188 per_ring_budget) : 3189 ixgbe_clean_rx_irq(q_vector, ring, 3190 per_ring_budget); 3191 3192 work_done += cleaned; 3193 if (cleaned >= per_ring_budget) 3194 clean_complete = false; 3195 } 3196 3197 /* If all work not completed, return budget and keep polling */ 3198 if (!clean_complete) 3199 return budget; 3200 3201 /* all work done, exit the polling mode */ 3202 if (likely(napi_complete_done(napi, work_done))) { 3203 if (adapter->rx_itr_setting & 1) 3204 ixgbe_set_itr(q_vector); 3205 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3206 ixgbe_irq_enable_queues(adapter, 3207 BIT_ULL(q_vector->v_idx)); 3208 } 3209 3210 return min(work_done, budget - 1); 3211 } 3212 3213 /** 3214 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3215 * @adapter: board private structure 3216 * 3217 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3218 * interrupts from the kernel. 3219 **/ 3220 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3221 { 3222 struct net_device *netdev = adapter->netdev; 3223 unsigned int ri = 0, ti = 0; 3224 int vector, err; 3225 3226 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3227 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3228 struct msix_entry *entry = &adapter->msix_entries[vector]; 3229 3230 if (q_vector->tx.ring && q_vector->rx.ring) { 3231 snprintf(q_vector->name, sizeof(q_vector->name), 3232 "%s-TxRx-%u", netdev->name, ri++); 3233 ti++; 3234 } else if (q_vector->rx.ring) { 3235 snprintf(q_vector->name, sizeof(q_vector->name), 3236 "%s-rx-%u", netdev->name, ri++); 3237 } else if (q_vector->tx.ring) { 3238 snprintf(q_vector->name, sizeof(q_vector->name), 3239 "%s-tx-%u", netdev->name, ti++); 3240 } else { 3241 /* skip this unused q_vector */ 3242 continue; 3243 } 3244 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3245 q_vector->name, q_vector); 3246 if (err) { 3247 e_err(probe, "request_irq failed for MSIX interrupt " 3248 "Error: %d\n", err); 3249 goto free_queue_irqs; 3250 } 3251 /* If Flow Director is enabled, set interrupt affinity */ 3252 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3253 /* assign the mask for this irq */ 3254 irq_set_affinity_hint(entry->vector, 3255 &q_vector->affinity_mask); 3256 } 3257 } 3258 3259 err = request_irq(adapter->msix_entries[vector].vector, 3260 ixgbe_msix_other, 0, netdev->name, adapter); 3261 if (err) { 3262 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3263 goto free_queue_irqs; 3264 } 3265 3266 return 0; 3267 3268 free_queue_irqs: 3269 while (vector) { 3270 vector--; 3271 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3272 NULL); 3273 free_irq(adapter->msix_entries[vector].vector, 3274 adapter->q_vector[vector]); 3275 } 3276 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3277 pci_disable_msix(adapter->pdev); 3278 kfree(adapter->msix_entries); 3279 adapter->msix_entries = NULL; 3280 return err; 3281 } 3282 3283 /** 3284 * ixgbe_intr - legacy mode Interrupt Handler 3285 * @irq: interrupt number 3286 * @data: pointer to a network interface device structure 3287 **/ 3288 static irqreturn_t ixgbe_intr(int irq, void *data) 3289 { 3290 struct ixgbe_adapter *adapter = data; 3291 struct ixgbe_hw *hw = &adapter->hw; 3292 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3293 u32 eicr; 3294 3295 /* 3296 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3297 * before the read of EICR. 3298 */ 3299 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3300 3301 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3302 * therefore no explicit interrupt disable is necessary */ 3303 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3304 if (!eicr) { 3305 /* 3306 * shared interrupt alert! 3307 * make sure interrupts are enabled because the read will 3308 * have disabled interrupts due to EIAM 3309 * finish the workaround of silicon errata on 82598. Unmask 3310 * the interrupt that we masked before the EICR read. 3311 */ 3312 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3313 ixgbe_irq_enable(adapter, true, true); 3314 return IRQ_NONE; /* Not our interrupt */ 3315 } 3316 3317 if (eicr & IXGBE_EICR_LSC) 3318 ixgbe_check_lsc(adapter); 3319 3320 switch (hw->mac.type) { 3321 case ixgbe_mac_82599EB: 3322 ixgbe_check_sfp_event(adapter, eicr); 3323 /* Fall through */ 3324 case ixgbe_mac_X540: 3325 case ixgbe_mac_X550: 3326 case ixgbe_mac_X550EM_x: 3327 case ixgbe_mac_x550em_a: 3328 if (eicr & IXGBE_EICR_ECC) { 3329 e_info(link, "Received ECC Err, initiating reset\n"); 3330 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3331 ixgbe_service_event_schedule(adapter); 3332 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3333 } 3334 ixgbe_check_overtemp_event(adapter, eicr); 3335 break; 3336 default: 3337 break; 3338 } 3339 3340 ixgbe_check_fan_failure(adapter, eicr); 3341 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3342 ixgbe_ptp_check_pps_event(adapter); 3343 3344 /* would disable interrupts here but EIAM disabled it */ 3345 napi_schedule_irqoff(&q_vector->napi); 3346 3347 /* 3348 * re-enable link(maybe) and non-queue interrupts, no flush. 3349 * ixgbe_poll will re-enable the queue interrupts 3350 */ 3351 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3352 ixgbe_irq_enable(adapter, false, false); 3353 3354 return IRQ_HANDLED; 3355 } 3356 3357 /** 3358 * ixgbe_request_irq - initialize interrupts 3359 * @adapter: board private structure 3360 * 3361 * Attempts to configure interrupts using the best available 3362 * capabilities of the hardware and kernel. 3363 **/ 3364 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3365 { 3366 struct net_device *netdev = adapter->netdev; 3367 int err; 3368 3369 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3370 err = ixgbe_request_msix_irqs(adapter); 3371 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3372 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3373 netdev->name, adapter); 3374 else 3375 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3376 netdev->name, adapter); 3377 3378 if (err) 3379 e_err(probe, "request_irq failed, Error %d\n", err); 3380 3381 return err; 3382 } 3383 3384 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3385 { 3386 int vector; 3387 3388 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3389 free_irq(adapter->pdev->irq, adapter); 3390 return; 3391 } 3392 3393 if (!adapter->msix_entries) 3394 return; 3395 3396 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3397 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3398 struct msix_entry *entry = &adapter->msix_entries[vector]; 3399 3400 /* free only the irqs that were actually requested */ 3401 if (!q_vector->rx.ring && !q_vector->tx.ring) 3402 continue; 3403 3404 /* clear the affinity_mask in the IRQ descriptor */ 3405 irq_set_affinity_hint(entry->vector, NULL); 3406 3407 free_irq(entry->vector, q_vector); 3408 } 3409 3410 free_irq(adapter->msix_entries[vector].vector, adapter); 3411 } 3412 3413 /** 3414 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3415 * @adapter: board private structure 3416 **/ 3417 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3418 { 3419 switch (adapter->hw.mac.type) { 3420 case ixgbe_mac_82598EB: 3421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3422 break; 3423 case ixgbe_mac_82599EB: 3424 case ixgbe_mac_X540: 3425 case ixgbe_mac_X550: 3426 case ixgbe_mac_X550EM_x: 3427 case ixgbe_mac_x550em_a: 3428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3429 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3430 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3431 break; 3432 default: 3433 break; 3434 } 3435 IXGBE_WRITE_FLUSH(&adapter->hw); 3436 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3437 int vector; 3438 3439 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3440 synchronize_irq(adapter->msix_entries[vector].vector); 3441 3442 synchronize_irq(adapter->msix_entries[vector++].vector); 3443 } else { 3444 synchronize_irq(adapter->pdev->irq); 3445 } 3446 } 3447 3448 /** 3449 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3450 * @adapter: board private structure 3451 * 3452 **/ 3453 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3454 { 3455 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3456 3457 ixgbe_write_eitr(q_vector); 3458 3459 ixgbe_set_ivar(adapter, 0, 0, 0); 3460 ixgbe_set_ivar(adapter, 1, 0, 0); 3461 3462 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3463 } 3464 3465 /** 3466 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3467 * @adapter: board private structure 3468 * @ring: structure containing ring specific data 3469 * 3470 * Configure the Tx descriptor ring after a reset. 3471 **/ 3472 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3473 struct ixgbe_ring *ring) 3474 { 3475 struct ixgbe_hw *hw = &adapter->hw; 3476 u64 tdba = ring->dma; 3477 int wait_loop = 10; 3478 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3479 u8 reg_idx = ring->reg_idx; 3480 3481 ring->xsk_umem = NULL; 3482 if (ring_is_xdp(ring)) 3483 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 3484 3485 /* disable queue to avoid issues while updating state */ 3486 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3487 IXGBE_WRITE_FLUSH(hw); 3488 3489 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3490 (tdba & DMA_BIT_MASK(32))); 3491 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3492 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3493 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3494 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3495 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3496 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3497 3498 /* 3499 * set WTHRESH to encourage burst writeback, it should not be set 3500 * higher than 1 when: 3501 * - ITR is 0 as it could cause false TX hangs 3502 * - ITR is set to > 100k int/sec and BQL is enabled 3503 * 3504 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3505 * to or less than the number of on chip descriptors, which is 3506 * currently 40. 3507 */ 3508 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3509 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3510 else 3511 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3512 3513 /* 3514 * Setting PTHRESH to 32 both improves performance 3515 * and avoids a TX hang with DFP enabled 3516 */ 3517 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3518 32; /* PTHRESH = 32 */ 3519 3520 /* reinitialize flowdirector state */ 3521 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3522 ring->atr_sample_rate = adapter->atr_sample_rate; 3523 ring->atr_count = 0; 3524 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3525 } else { 3526 ring->atr_sample_rate = 0; 3527 } 3528 3529 /* initialize XPS */ 3530 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3531 struct ixgbe_q_vector *q_vector = ring->q_vector; 3532 3533 if (q_vector) 3534 netif_set_xps_queue(ring->netdev, 3535 &q_vector->affinity_mask, 3536 ring->queue_index); 3537 } 3538 3539 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3540 3541 /* reinitialize tx_buffer_info */ 3542 memset(ring->tx_buffer_info, 0, 3543 sizeof(struct ixgbe_tx_buffer) * ring->count); 3544 3545 /* enable queue */ 3546 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3547 3548 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3549 if (hw->mac.type == ixgbe_mac_82598EB && 3550 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3551 return; 3552 3553 /* poll to verify queue is enabled */ 3554 do { 3555 usleep_range(1000, 2000); 3556 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3557 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3558 if (!wait_loop) 3559 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3560 } 3561 3562 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3563 { 3564 struct ixgbe_hw *hw = &adapter->hw; 3565 u32 rttdcs, mtqc; 3566 u8 tcs = adapter->hw_tcs; 3567 3568 if (hw->mac.type == ixgbe_mac_82598EB) 3569 return; 3570 3571 /* disable the arbiter while setting MTQC */ 3572 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3573 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3574 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3575 3576 /* set transmit pool layout */ 3577 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3578 mtqc = IXGBE_MTQC_VT_ENA; 3579 if (tcs > 4) 3580 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3581 else if (tcs > 1) 3582 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3583 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3584 IXGBE_82599_VMDQ_4Q_MASK) 3585 mtqc |= IXGBE_MTQC_32VF; 3586 else 3587 mtqc |= IXGBE_MTQC_64VF; 3588 } else { 3589 if (tcs > 4) { 3590 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3591 } else if (tcs > 1) { 3592 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3593 } else { 3594 u8 max_txq = adapter->num_tx_queues + 3595 adapter->num_xdp_queues; 3596 if (max_txq > 63) 3597 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3598 else 3599 mtqc = IXGBE_MTQC_64Q_1PB; 3600 } 3601 } 3602 3603 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3604 3605 /* Enable Security TX Buffer IFG for multiple pb */ 3606 if (tcs) { 3607 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3608 sectx |= IXGBE_SECTX_DCB; 3609 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3610 } 3611 3612 /* re-enable the arbiter */ 3613 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3614 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3615 } 3616 3617 /** 3618 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3619 * @adapter: board private structure 3620 * 3621 * Configure the Tx unit of the MAC after a reset. 3622 **/ 3623 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3624 { 3625 struct ixgbe_hw *hw = &adapter->hw; 3626 u32 dmatxctl; 3627 u32 i; 3628 3629 ixgbe_setup_mtqc(adapter); 3630 3631 if (hw->mac.type != ixgbe_mac_82598EB) { 3632 /* DMATXCTL.EN must be before Tx queues are enabled */ 3633 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3634 dmatxctl |= IXGBE_DMATXCTL_TE; 3635 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3636 } 3637 3638 /* Setup the HW Tx Head and Tail descriptor pointers */ 3639 for (i = 0; i < adapter->num_tx_queues; i++) 3640 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3641 for (i = 0; i < adapter->num_xdp_queues; i++) 3642 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3643 } 3644 3645 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3646 struct ixgbe_ring *ring) 3647 { 3648 struct ixgbe_hw *hw = &adapter->hw; 3649 u8 reg_idx = ring->reg_idx; 3650 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3651 3652 srrctl |= IXGBE_SRRCTL_DROP_EN; 3653 3654 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3655 } 3656 3657 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3658 struct ixgbe_ring *ring) 3659 { 3660 struct ixgbe_hw *hw = &adapter->hw; 3661 u8 reg_idx = ring->reg_idx; 3662 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3663 3664 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3665 3666 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3667 } 3668 3669 #ifdef CONFIG_IXGBE_DCB 3670 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3671 #else 3672 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3673 #endif 3674 { 3675 int i; 3676 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3677 3678 if (adapter->ixgbe_ieee_pfc) 3679 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3680 3681 /* 3682 * We should set the drop enable bit if: 3683 * SR-IOV is enabled 3684 * or 3685 * Number of Rx queues > 1 and flow control is disabled 3686 * 3687 * This allows us to avoid head of line blocking for security 3688 * and performance reasons. 3689 */ 3690 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3691 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3692 for (i = 0; i < adapter->num_rx_queues; i++) 3693 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3694 } else { 3695 for (i = 0; i < adapter->num_rx_queues; i++) 3696 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3697 } 3698 } 3699 3700 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3701 3702 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3703 struct ixgbe_ring *rx_ring) 3704 { 3705 struct ixgbe_hw *hw = &adapter->hw; 3706 u32 srrctl; 3707 u8 reg_idx = rx_ring->reg_idx; 3708 3709 if (hw->mac.type == ixgbe_mac_82598EB) { 3710 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3711 3712 /* 3713 * if VMDq is not active we must program one srrctl register 3714 * per RSS queue since we have enabled RDRXCTL.MVMEN 3715 */ 3716 reg_idx &= mask; 3717 } 3718 3719 /* configure header buffer length, needed for RSC */ 3720 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3721 3722 /* configure the packet buffer length */ 3723 if (rx_ring->xsk_umem) { 3724 u32 xsk_buf_len = rx_ring->xsk_umem->chunk_size_nohr - 3725 XDP_PACKET_HEADROOM; 3726 3727 /* If the MAC support setting RXDCTL.RLPML, the 3728 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3729 * RXDCTL.RLPML is set to the actual UMEM buffer 3730 * size. If not, then we are stuck with a 1k buffer 3731 * size resolution. In this case frames larger than 3732 * the UMEM buffer size viewed in a 1k resolution will 3733 * be dropped. 3734 */ 3735 if (hw->mac.type != ixgbe_mac_82599EB) 3736 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3737 else 3738 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3739 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3740 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3741 } else { 3742 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3743 } 3744 3745 /* configure descriptor type */ 3746 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3747 3748 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3749 } 3750 3751 /** 3752 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3753 * @adapter: device handle 3754 * 3755 * - 82598/82599/X540: 128 3756 * - X550(non-SRIOV mode): 512 3757 * - X550(SRIOV mode): 64 3758 */ 3759 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3760 { 3761 if (adapter->hw.mac.type < ixgbe_mac_X550) 3762 return 128; 3763 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3764 return 64; 3765 else 3766 return 512; 3767 } 3768 3769 /** 3770 * ixgbe_store_key - Write the RSS key to HW 3771 * @adapter: device handle 3772 * 3773 * Write the RSS key stored in adapter.rss_key to HW. 3774 */ 3775 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3776 { 3777 struct ixgbe_hw *hw = &adapter->hw; 3778 int i; 3779 3780 for (i = 0; i < 10; i++) 3781 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3782 } 3783 3784 /** 3785 * ixgbe_init_rss_key - Initialize adapter RSS key 3786 * @adapter: device handle 3787 * 3788 * Allocates and initializes the RSS key if it is not allocated. 3789 **/ 3790 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3791 { 3792 u32 *rss_key; 3793 3794 if (!adapter->rss_key) { 3795 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3796 if (unlikely(!rss_key)) 3797 return -ENOMEM; 3798 3799 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3800 adapter->rss_key = rss_key; 3801 } 3802 3803 return 0; 3804 } 3805 3806 /** 3807 * ixgbe_store_reta - Write the RETA table to HW 3808 * @adapter: device handle 3809 * 3810 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3811 */ 3812 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3813 { 3814 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3815 struct ixgbe_hw *hw = &adapter->hw; 3816 u32 reta = 0; 3817 u32 indices_multi; 3818 u8 *indir_tbl = adapter->rss_indir_tbl; 3819 3820 /* Fill out the redirection table as follows: 3821 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3822 * indices. 3823 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3824 * - X550: 8 bit wide entries containing 6 bit RSS index 3825 */ 3826 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3827 indices_multi = 0x11; 3828 else 3829 indices_multi = 0x1; 3830 3831 /* Write redirection table to HW */ 3832 for (i = 0; i < reta_entries; i++) { 3833 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3834 if ((i & 3) == 3) { 3835 if (i < 128) 3836 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3837 else 3838 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3839 reta); 3840 reta = 0; 3841 } 3842 } 3843 } 3844 3845 /** 3846 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3847 * @adapter: device handle 3848 * 3849 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3850 */ 3851 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3852 { 3853 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3854 struct ixgbe_hw *hw = &adapter->hw; 3855 u32 vfreta = 0; 3856 3857 /* Write redirection table to HW */ 3858 for (i = 0; i < reta_entries; i++) { 3859 u16 pool = adapter->num_rx_pools; 3860 3861 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3862 if ((i & 3) != 3) 3863 continue; 3864 3865 while (pool--) 3866 IXGBE_WRITE_REG(hw, 3867 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3868 vfreta); 3869 vfreta = 0; 3870 } 3871 } 3872 3873 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3874 { 3875 u32 i, j; 3876 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3877 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3878 3879 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3880 * make full use of any rings they may have. We will use the 3881 * PSRTYPE register to control how many rings we use within the PF. 3882 */ 3883 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3884 rss_i = 4; 3885 3886 /* Fill out hash function seeds */ 3887 ixgbe_store_key(adapter); 3888 3889 /* Fill out redirection table */ 3890 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3891 3892 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3893 if (j == rss_i) 3894 j = 0; 3895 3896 adapter->rss_indir_tbl[i] = j; 3897 } 3898 3899 ixgbe_store_reta(adapter); 3900 } 3901 3902 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3903 { 3904 struct ixgbe_hw *hw = &adapter->hw; 3905 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3906 int i, j; 3907 3908 /* Fill out hash function seeds */ 3909 for (i = 0; i < 10; i++) { 3910 u16 pool = adapter->num_rx_pools; 3911 3912 while (pool--) 3913 IXGBE_WRITE_REG(hw, 3914 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3915 *(adapter->rss_key + i)); 3916 } 3917 3918 /* Fill out the redirection table */ 3919 for (i = 0, j = 0; i < 64; i++, j++) { 3920 if (j == rss_i) 3921 j = 0; 3922 3923 adapter->rss_indir_tbl[i] = j; 3924 } 3925 3926 ixgbe_store_vfreta(adapter); 3927 } 3928 3929 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3930 { 3931 struct ixgbe_hw *hw = &adapter->hw; 3932 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3933 u32 rxcsum; 3934 3935 /* Disable indicating checksum in descriptor, enables RSS hash */ 3936 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3937 rxcsum |= IXGBE_RXCSUM_PCSD; 3938 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3939 3940 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3941 if (adapter->ring_feature[RING_F_RSS].mask) 3942 mrqc = IXGBE_MRQC_RSSEN; 3943 } else { 3944 u8 tcs = adapter->hw_tcs; 3945 3946 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3947 if (tcs > 4) 3948 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3949 else if (tcs > 1) 3950 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3951 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3952 IXGBE_82599_VMDQ_4Q_MASK) 3953 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3954 else 3955 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3956 3957 /* Enable L3/L4 for Tx Switched packets only for X550, 3958 * older devices do not support this feature 3959 */ 3960 if (hw->mac.type >= ixgbe_mac_X550) 3961 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3962 } else { 3963 if (tcs > 4) 3964 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3965 else if (tcs > 1) 3966 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3967 else 3968 mrqc = IXGBE_MRQC_RSSEN; 3969 } 3970 } 3971 3972 /* Perform hash on these packet types */ 3973 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3974 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3975 IXGBE_MRQC_RSS_FIELD_IPV6 | 3976 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3977 3978 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3979 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3980 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3981 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3982 3983 if ((hw->mac.type >= ixgbe_mac_X550) && 3984 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3985 u16 pool = adapter->num_rx_pools; 3986 3987 /* Enable VF RSS mode */ 3988 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3989 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3990 3991 /* Setup RSS through the VF registers */ 3992 ixgbe_setup_vfreta(adapter); 3993 vfmrqc = IXGBE_MRQC_RSSEN; 3994 vfmrqc |= rss_field; 3995 3996 while (pool--) 3997 IXGBE_WRITE_REG(hw, 3998 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3999 vfmrqc); 4000 } else { 4001 ixgbe_setup_reta(adapter); 4002 mrqc |= rss_field; 4003 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4004 } 4005 } 4006 4007 /** 4008 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4009 * @adapter: address of board private structure 4010 * @ring: structure containing ring specific data 4011 **/ 4012 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4013 struct ixgbe_ring *ring) 4014 { 4015 struct ixgbe_hw *hw = &adapter->hw; 4016 u32 rscctrl; 4017 u8 reg_idx = ring->reg_idx; 4018 4019 if (!ring_is_rsc_enabled(ring)) 4020 return; 4021 4022 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4023 rscctrl |= IXGBE_RSCCTL_RSCEN; 4024 /* 4025 * we must limit the number of descriptors so that the 4026 * total size of max desc * buf_len is not greater 4027 * than 65536 4028 */ 4029 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4030 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4031 } 4032 4033 #define IXGBE_MAX_RX_DESC_POLL 10 4034 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4035 struct ixgbe_ring *ring) 4036 { 4037 struct ixgbe_hw *hw = &adapter->hw; 4038 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4039 u32 rxdctl; 4040 u8 reg_idx = ring->reg_idx; 4041 4042 if (ixgbe_removed(hw->hw_addr)) 4043 return; 4044 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4045 if (hw->mac.type == ixgbe_mac_82598EB && 4046 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4047 return; 4048 4049 do { 4050 usleep_range(1000, 2000); 4051 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4052 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4053 4054 if (!wait_loop) { 4055 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4056 "the polling period\n", reg_idx); 4057 } 4058 } 4059 4060 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4061 struct ixgbe_ring *ring) 4062 { 4063 struct ixgbe_hw *hw = &adapter->hw; 4064 union ixgbe_adv_rx_desc *rx_desc; 4065 u64 rdba = ring->dma; 4066 u32 rxdctl; 4067 u8 reg_idx = ring->reg_idx; 4068 4069 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4070 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 4071 if (ring->xsk_umem) { 4072 ring->zca.free = ixgbe_zca_free; 4073 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4074 MEM_TYPE_ZERO_COPY, 4075 &ring->zca)); 4076 4077 } else { 4078 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4079 MEM_TYPE_PAGE_SHARED, NULL)); 4080 } 4081 4082 /* disable queue to avoid use of these values while updating state */ 4083 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4084 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4085 4086 /* write value back with RXDCTL.ENABLE bit cleared */ 4087 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4088 IXGBE_WRITE_FLUSH(hw); 4089 4090 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4091 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4092 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4093 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4094 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4095 IXGBE_WRITE_FLUSH(hw); 4096 4097 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4098 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4099 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4100 4101 ixgbe_configure_srrctl(adapter, ring); 4102 ixgbe_configure_rscctl(adapter, ring); 4103 4104 if (hw->mac.type == ixgbe_mac_82598EB) { 4105 /* 4106 * enable cache line friendly hardware writes: 4107 * PTHRESH=32 descriptors (half the internal cache), 4108 * this also removes ugly rx_no_buffer_count increment 4109 * HTHRESH=4 descriptors (to minimize latency on fetch) 4110 * WTHRESH=8 burst writeback up to two cache lines 4111 */ 4112 rxdctl &= ~0x3FFFFF; 4113 rxdctl |= 0x080420; 4114 #if (PAGE_SIZE < 8192) 4115 /* RXDCTL.RLPML does not work on 82599 */ 4116 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4117 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4118 IXGBE_RXDCTL_RLPML_EN); 4119 4120 /* Limit the maximum frame size so we don't overrun the skb. 4121 * This can happen in SRIOV mode when the MTU of the VF is 4122 * higher than the MTU of the PF. 4123 */ 4124 if (ring_uses_build_skb(ring) && 4125 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4126 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4127 IXGBE_RXDCTL_RLPML_EN; 4128 #endif 4129 } 4130 4131 if (ring->xsk_umem && hw->mac.type != ixgbe_mac_82599EB) { 4132 u32 xsk_buf_len = ring->xsk_umem->chunk_size_nohr - 4133 XDP_PACKET_HEADROOM; 4134 4135 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4136 IXGBE_RXDCTL_RLPML_EN); 4137 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4138 4139 ring->rx_buf_len = xsk_buf_len; 4140 } 4141 4142 /* initialize rx_buffer_info */ 4143 memset(ring->rx_buffer_info, 0, 4144 sizeof(struct ixgbe_rx_buffer) * ring->count); 4145 4146 /* initialize Rx descriptor 0 */ 4147 rx_desc = IXGBE_RX_DESC(ring, 0); 4148 rx_desc->wb.upper.length = 0; 4149 4150 /* enable receive descriptor ring */ 4151 rxdctl |= IXGBE_RXDCTL_ENABLE; 4152 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4153 4154 ixgbe_rx_desc_queue_enable(adapter, ring); 4155 if (ring->xsk_umem) 4156 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4157 else 4158 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4159 } 4160 4161 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4162 { 4163 struct ixgbe_hw *hw = &adapter->hw; 4164 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4165 u16 pool = adapter->num_rx_pools; 4166 4167 /* PSRTYPE must be initialized in non 82598 adapters */ 4168 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4169 IXGBE_PSRTYPE_UDPHDR | 4170 IXGBE_PSRTYPE_IPV4HDR | 4171 IXGBE_PSRTYPE_L2HDR | 4172 IXGBE_PSRTYPE_IPV6HDR; 4173 4174 if (hw->mac.type == ixgbe_mac_82598EB) 4175 return; 4176 4177 if (rss_i > 3) 4178 psrtype |= 2u << 29; 4179 else if (rss_i > 1) 4180 psrtype |= 1u << 29; 4181 4182 while (pool--) 4183 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4184 } 4185 4186 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4187 { 4188 struct ixgbe_hw *hw = &adapter->hw; 4189 u16 pool = adapter->num_rx_pools; 4190 u32 reg_offset, vf_shift, vmolr; 4191 u32 gcr_ext, vmdctl; 4192 int i; 4193 4194 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4195 return; 4196 4197 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4198 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4199 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4200 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4201 vmdctl |= IXGBE_VT_CTL_REPLEN; 4202 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4203 4204 /* accept untagged packets until a vlan tag is 4205 * specifically set for the VMDQ queue/pool 4206 */ 4207 vmolr = IXGBE_VMOLR_AUPE; 4208 while (pool--) 4209 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4210 4211 vf_shift = VMDQ_P(0) % 32; 4212 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4213 4214 /* Enable only the PF's pool for Tx/Rx */ 4215 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4216 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4217 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4218 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4219 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4220 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4221 4222 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4223 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4224 4225 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4226 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4227 4228 /* 4229 * Set up VF register offsets for selected VT Mode, 4230 * i.e. 32 or 64 VFs for SR-IOV 4231 */ 4232 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4233 case IXGBE_82599_VMDQ_8Q_MASK: 4234 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4235 break; 4236 case IXGBE_82599_VMDQ_4Q_MASK: 4237 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4238 break; 4239 default: 4240 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4241 break; 4242 } 4243 4244 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4245 4246 for (i = 0; i < adapter->num_vfs; i++) { 4247 /* configure spoof checking */ 4248 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4249 adapter->vfinfo[i].spoofchk_enabled); 4250 4251 /* Enable/Disable RSS query feature */ 4252 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4253 adapter->vfinfo[i].rss_query_enabled); 4254 } 4255 } 4256 4257 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4258 { 4259 struct ixgbe_hw *hw = &adapter->hw; 4260 struct net_device *netdev = adapter->netdev; 4261 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4262 struct ixgbe_ring *rx_ring; 4263 int i; 4264 u32 mhadd, hlreg0; 4265 4266 #ifdef IXGBE_FCOE 4267 /* adjust max frame to be able to do baby jumbo for FCoE */ 4268 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4269 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4270 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4271 4272 #endif /* IXGBE_FCOE */ 4273 4274 /* adjust max frame to be at least the size of a standard frame */ 4275 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4276 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4277 4278 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4279 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4280 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4281 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4282 4283 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4284 } 4285 4286 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4287 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4288 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4289 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4290 4291 /* 4292 * Setup the HW Rx Head and Tail Descriptor Pointers and 4293 * the Base and Length of the Rx Descriptor Ring 4294 */ 4295 for (i = 0; i < adapter->num_rx_queues; i++) { 4296 rx_ring = adapter->rx_ring[i]; 4297 4298 clear_ring_rsc_enabled(rx_ring); 4299 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4300 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4301 4302 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4303 set_ring_rsc_enabled(rx_ring); 4304 4305 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4306 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4307 4308 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4309 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4310 continue; 4311 4312 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4313 4314 #if (PAGE_SIZE < 8192) 4315 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4316 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4317 4318 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4319 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4320 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4321 #endif 4322 } 4323 } 4324 4325 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4326 { 4327 struct ixgbe_hw *hw = &adapter->hw; 4328 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4329 4330 switch (hw->mac.type) { 4331 case ixgbe_mac_82598EB: 4332 /* 4333 * For VMDq support of different descriptor types or 4334 * buffer sizes through the use of multiple SRRCTL 4335 * registers, RDRXCTL.MVMEN must be set to 1 4336 * 4337 * also, the manual doesn't mention it clearly but DCA hints 4338 * will only use queue 0's tags unless this bit is set. Side 4339 * effects of setting this bit are only that SRRCTL must be 4340 * fully programmed [0..15] 4341 */ 4342 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4343 break; 4344 case ixgbe_mac_X550: 4345 case ixgbe_mac_X550EM_x: 4346 case ixgbe_mac_x550em_a: 4347 if (adapter->num_vfs) 4348 rdrxctl |= IXGBE_RDRXCTL_PSP; 4349 /* fall through */ 4350 case ixgbe_mac_82599EB: 4351 case ixgbe_mac_X540: 4352 /* Disable RSC for ACK packets */ 4353 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4354 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4355 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4356 /* hardware requires some bits to be set by default */ 4357 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4358 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4359 break; 4360 default: 4361 /* We should do nothing since we don't know this hardware */ 4362 return; 4363 } 4364 4365 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4366 } 4367 4368 /** 4369 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4370 * @adapter: board private structure 4371 * 4372 * Configure the Rx unit of the MAC after a reset. 4373 **/ 4374 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4375 { 4376 struct ixgbe_hw *hw = &adapter->hw; 4377 int i; 4378 u32 rxctrl, rfctl; 4379 4380 /* disable receives while setting up the descriptors */ 4381 hw->mac.ops.disable_rx(hw); 4382 4383 ixgbe_setup_psrtype(adapter); 4384 ixgbe_setup_rdrxctl(adapter); 4385 4386 /* RSC Setup */ 4387 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4388 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4389 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4390 rfctl |= IXGBE_RFCTL_RSC_DIS; 4391 4392 /* disable NFS filtering */ 4393 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4394 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4395 4396 /* Program registers for the distribution of queues */ 4397 ixgbe_setup_mrqc(adapter); 4398 4399 /* set_rx_buffer_len must be called before ring initialization */ 4400 ixgbe_set_rx_buffer_len(adapter); 4401 4402 /* 4403 * Setup the HW Rx Head and Tail Descriptor Pointers and 4404 * the Base and Length of the Rx Descriptor Ring 4405 */ 4406 for (i = 0; i < adapter->num_rx_queues; i++) 4407 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4408 4409 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4410 /* disable drop enable for 82598 parts */ 4411 if (hw->mac.type == ixgbe_mac_82598EB) 4412 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4413 4414 /* enable all receives */ 4415 rxctrl |= IXGBE_RXCTRL_RXEN; 4416 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4417 } 4418 4419 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4420 __be16 proto, u16 vid) 4421 { 4422 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4423 struct ixgbe_hw *hw = &adapter->hw; 4424 4425 /* add VID to filter table */ 4426 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4427 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4428 4429 set_bit(vid, adapter->active_vlans); 4430 4431 return 0; 4432 } 4433 4434 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4435 { 4436 u32 vlvf; 4437 int idx; 4438 4439 /* short cut the special case */ 4440 if (vlan == 0) 4441 return 0; 4442 4443 /* Search for the vlan id in the VLVF entries */ 4444 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4445 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4446 if ((vlvf & VLAN_VID_MASK) == vlan) 4447 break; 4448 } 4449 4450 return idx; 4451 } 4452 4453 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4454 { 4455 struct ixgbe_hw *hw = &adapter->hw; 4456 u32 bits, word; 4457 int idx; 4458 4459 idx = ixgbe_find_vlvf_entry(hw, vid); 4460 if (!idx) 4461 return; 4462 4463 /* See if any other pools are set for this VLAN filter 4464 * entry other than the PF. 4465 */ 4466 word = idx * 2 + (VMDQ_P(0) / 32); 4467 bits = ~BIT(VMDQ_P(0) % 32); 4468 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4469 4470 /* Disable the filter so this falls into the default pool. */ 4471 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4472 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4473 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4474 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4475 } 4476 } 4477 4478 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4479 __be16 proto, u16 vid) 4480 { 4481 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4482 struct ixgbe_hw *hw = &adapter->hw; 4483 4484 /* remove VID from filter table */ 4485 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4486 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4487 4488 clear_bit(vid, adapter->active_vlans); 4489 4490 return 0; 4491 } 4492 4493 /** 4494 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4495 * @adapter: driver data 4496 */ 4497 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4498 { 4499 struct ixgbe_hw *hw = &adapter->hw; 4500 u32 vlnctrl; 4501 int i, j; 4502 4503 switch (hw->mac.type) { 4504 case ixgbe_mac_82598EB: 4505 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4506 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4507 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4508 break; 4509 case ixgbe_mac_82599EB: 4510 case ixgbe_mac_X540: 4511 case ixgbe_mac_X550: 4512 case ixgbe_mac_X550EM_x: 4513 case ixgbe_mac_x550em_a: 4514 for (i = 0; i < adapter->num_rx_queues; i++) { 4515 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4516 4517 if (!netif_is_ixgbe(ring->netdev)) 4518 continue; 4519 4520 j = ring->reg_idx; 4521 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4522 vlnctrl &= ~IXGBE_RXDCTL_VME; 4523 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4524 } 4525 break; 4526 default: 4527 break; 4528 } 4529 } 4530 4531 /** 4532 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4533 * @adapter: driver data 4534 */ 4535 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4536 { 4537 struct ixgbe_hw *hw = &adapter->hw; 4538 u32 vlnctrl; 4539 int i, j; 4540 4541 switch (hw->mac.type) { 4542 case ixgbe_mac_82598EB: 4543 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4544 vlnctrl |= IXGBE_VLNCTRL_VME; 4545 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4546 break; 4547 case ixgbe_mac_82599EB: 4548 case ixgbe_mac_X540: 4549 case ixgbe_mac_X550: 4550 case ixgbe_mac_X550EM_x: 4551 case ixgbe_mac_x550em_a: 4552 for (i = 0; i < adapter->num_rx_queues; i++) { 4553 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4554 4555 if (!netif_is_ixgbe(ring->netdev)) 4556 continue; 4557 4558 j = ring->reg_idx; 4559 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4560 vlnctrl |= IXGBE_RXDCTL_VME; 4561 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4562 } 4563 break; 4564 default: 4565 break; 4566 } 4567 } 4568 4569 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4570 { 4571 struct ixgbe_hw *hw = &adapter->hw; 4572 u32 vlnctrl, i; 4573 4574 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4575 4576 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4577 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4578 vlnctrl |= IXGBE_VLNCTRL_VFE; 4579 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4580 } else { 4581 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4582 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4583 return; 4584 } 4585 4586 /* Nothing to do for 82598 */ 4587 if (hw->mac.type == ixgbe_mac_82598EB) 4588 return; 4589 4590 /* We are already in VLAN promisc, nothing to do */ 4591 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4592 return; 4593 4594 /* Set flag so we don't redo unnecessary work */ 4595 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4596 4597 /* Add PF to all active pools */ 4598 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4599 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4600 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4601 4602 vlvfb |= BIT(VMDQ_P(0) % 32); 4603 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4604 } 4605 4606 /* Set all bits in the VLAN filter table array */ 4607 for (i = hw->mac.vft_size; i--;) 4608 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4609 } 4610 4611 #define VFTA_BLOCK_SIZE 8 4612 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4613 { 4614 struct ixgbe_hw *hw = &adapter->hw; 4615 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4616 u32 vid_start = vfta_offset * 32; 4617 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4618 u32 i, vid, word, bits; 4619 4620 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4621 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4622 4623 /* pull VLAN ID from VLVF */ 4624 vid = vlvf & VLAN_VID_MASK; 4625 4626 /* only concern outselves with a certain range */ 4627 if (vid < vid_start || vid >= vid_end) 4628 continue; 4629 4630 if (vlvf) { 4631 /* record VLAN ID in VFTA */ 4632 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4633 4634 /* if PF is part of this then continue */ 4635 if (test_bit(vid, adapter->active_vlans)) 4636 continue; 4637 } 4638 4639 /* remove PF from the pool */ 4640 word = i * 2 + VMDQ_P(0) / 32; 4641 bits = ~BIT(VMDQ_P(0) % 32); 4642 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4643 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4644 } 4645 4646 /* extract values from active_vlans and write back to VFTA */ 4647 for (i = VFTA_BLOCK_SIZE; i--;) { 4648 vid = (vfta_offset + i) * 32; 4649 word = vid / BITS_PER_LONG; 4650 bits = vid % BITS_PER_LONG; 4651 4652 vfta[i] |= adapter->active_vlans[word] >> bits; 4653 4654 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4655 } 4656 } 4657 4658 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4659 { 4660 struct ixgbe_hw *hw = &adapter->hw; 4661 u32 vlnctrl, i; 4662 4663 /* Set VLAN filtering to enabled */ 4664 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4665 vlnctrl |= IXGBE_VLNCTRL_VFE; 4666 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4667 4668 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4669 hw->mac.type == ixgbe_mac_82598EB) 4670 return; 4671 4672 /* We are not in VLAN promisc, nothing to do */ 4673 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4674 return; 4675 4676 /* Set flag so we don't redo unnecessary work */ 4677 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4678 4679 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4680 ixgbe_scrub_vfta(adapter, i); 4681 } 4682 4683 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4684 { 4685 u16 vid = 1; 4686 4687 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4688 4689 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4690 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4691 } 4692 4693 /** 4694 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4695 * @netdev: network interface device structure 4696 * 4697 * Writes multicast address list to the MTA hash table. 4698 * Returns: -ENOMEM on failure 4699 * 0 on no addresses written 4700 * X on writing X addresses to MTA 4701 **/ 4702 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4703 { 4704 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4705 struct ixgbe_hw *hw = &adapter->hw; 4706 4707 if (!netif_running(netdev)) 4708 return 0; 4709 4710 if (hw->mac.ops.update_mc_addr_list) 4711 hw->mac.ops.update_mc_addr_list(hw, netdev); 4712 else 4713 return -ENOMEM; 4714 4715 #ifdef CONFIG_PCI_IOV 4716 ixgbe_restore_vf_multicasts(adapter); 4717 #endif 4718 4719 return netdev_mc_count(netdev); 4720 } 4721 4722 #ifdef CONFIG_PCI_IOV 4723 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4724 { 4725 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4726 struct ixgbe_hw *hw = &adapter->hw; 4727 int i; 4728 4729 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4730 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4731 4732 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4733 hw->mac.ops.set_rar(hw, i, 4734 mac_table->addr, 4735 mac_table->pool, 4736 IXGBE_RAH_AV); 4737 else 4738 hw->mac.ops.clear_rar(hw, i); 4739 } 4740 } 4741 4742 #endif 4743 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4744 { 4745 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4746 struct ixgbe_hw *hw = &adapter->hw; 4747 int i; 4748 4749 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4750 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4751 continue; 4752 4753 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4754 4755 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4756 hw->mac.ops.set_rar(hw, i, 4757 mac_table->addr, 4758 mac_table->pool, 4759 IXGBE_RAH_AV); 4760 else 4761 hw->mac.ops.clear_rar(hw, i); 4762 } 4763 } 4764 4765 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4766 { 4767 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4768 struct ixgbe_hw *hw = &adapter->hw; 4769 int i; 4770 4771 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4772 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4773 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4774 } 4775 4776 ixgbe_sync_mac_table(adapter); 4777 } 4778 4779 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4780 { 4781 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4782 struct ixgbe_hw *hw = &adapter->hw; 4783 int i, count = 0; 4784 4785 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4786 /* do not count default RAR as available */ 4787 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4788 continue; 4789 4790 /* only count unused and addresses that belong to us */ 4791 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4792 if (mac_table->pool != pool) 4793 continue; 4794 } 4795 4796 count++; 4797 } 4798 4799 return count; 4800 } 4801 4802 /* this function destroys the first RAR entry */ 4803 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4804 { 4805 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4806 struct ixgbe_hw *hw = &adapter->hw; 4807 4808 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4809 mac_table->pool = VMDQ_P(0); 4810 4811 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4812 4813 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4814 IXGBE_RAH_AV); 4815 } 4816 4817 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4818 const u8 *addr, u16 pool) 4819 { 4820 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4821 struct ixgbe_hw *hw = &adapter->hw; 4822 int i; 4823 4824 if (is_zero_ether_addr(addr)) 4825 return -EINVAL; 4826 4827 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4828 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4829 continue; 4830 4831 ether_addr_copy(mac_table->addr, addr); 4832 mac_table->pool = pool; 4833 4834 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4835 IXGBE_MAC_STATE_IN_USE; 4836 4837 ixgbe_sync_mac_table(adapter); 4838 4839 return i; 4840 } 4841 4842 return -ENOMEM; 4843 } 4844 4845 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4846 const u8 *addr, u16 pool) 4847 { 4848 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4849 struct ixgbe_hw *hw = &adapter->hw; 4850 int i; 4851 4852 if (is_zero_ether_addr(addr)) 4853 return -EINVAL; 4854 4855 /* search table for addr, if found clear IN_USE flag and sync */ 4856 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4857 /* we can only delete an entry if it is in use */ 4858 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4859 continue; 4860 /* we only care about entries that belong to the given pool */ 4861 if (mac_table->pool != pool) 4862 continue; 4863 /* we only care about a specific MAC address */ 4864 if (!ether_addr_equal(addr, mac_table->addr)) 4865 continue; 4866 4867 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4868 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4869 4870 ixgbe_sync_mac_table(adapter); 4871 4872 return 0; 4873 } 4874 4875 return -ENOMEM; 4876 } 4877 4878 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4879 { 4880 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4881 int ret; 4882 4883 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4884 4885 return min_t(int, ret, 0); 4886 } 4887 4888 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4889 { 4890 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4891 4892 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4893 4894 return 0; 4895 } 4896 4897 /** 4898 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4899 * @netdev: network interface device structure 4900 * 4901 * The set_rx_method entry point is called whenever the unicast/multicast 4902 * address list or the network interface flags are updated. This routine is 4903 * responsible for configuring the hardware for proper unicast, multicast and 4904 * promiscuous mode. 4905 **/ 4906 void ixgbe_set_rx_mode(struct net_device *netdev) 4907 { 4908 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4909 struct ixgbe_hw *hw = &adapter->hw; 4910 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4911 netdev_features_t features = netdev->features; 4912 int count; 4913 4914 /* Check for Promiscuous and All Multicast modes */ 4915 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4916 4917 /* set all bits that we expect to always be set */ 4918 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4919 fctrl |= IXGBE_FCTRL_BAM; 4920 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4921 fctrl |= IXGBE_FCTRL_PMCF; 4922 4923 /* clear the bits we are changing the status of */ 4924 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4925 if (netdev->flags & IFF_PROMISC) { 4926 hw->addr_ctrl.user_set_promisc = true; 4927 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4928 vmolr |= IXGBE_VMOLR_MPE; 4929 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4930 } else { 4931 if (netdev->flags & IFF_ALLMULTI) { 4932 fctrl |= IXGBE_FCTRL_MPE; 4933 vmolr |= IXGBE_VMOLR_MPE; 4934 } 4935 hw->addr_ctrl.user_set_promisc = false; 4936 } 4937 4938 /* 4939 * Write addresses to available RAR registers, if there is not 4940 * sufficient space to store all the addresses then enable 4941 * unicast promiscuous mode 4942 */ 4943 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4944 fctrl |= IXGBE_FCTRL_UPE; 4945 vmolr |= IXGBE_VMOLR_ROPE; 4946 } 4947 4948 /* Write addresses to the MTA, if the attempt fails 4949 * then we should just turn on promiscuous mode so 4950 * that we can at least receive multicast traffic 4951 */ 4952 count = ixgbe_write_mc_addr_list(netdev); 4953 if (count < 0) { 4954 fctrl |= IXGBE_FCTRL_MPE; 4955 vmolr |= IXGBE_VMOLR_MPE; 4956 } else if (count) { 4957 vmolr |= IXGBE_VMOLR_ROMPE; 4958 } 4959 4960 if (hw->mac.type != ixgbe_mac_82598EB) { 4961 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4962 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4963 IXGBE_VMOLR_ROPE); 4964 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4965 } 4966 4967 /* This is useful for sniffing bad packets. */ 4968 if (features & NETIF_F_RXALL) { 4969 /* UPE and MPE will be handled by normal PROMISC logic 4970 * in e1000e_set_rx_mode */ 4971 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4972 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4973 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4974 4975 fctrl &= ~(IXGBE_FCTRL_DPF); 4976 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4977 } 4978 4979 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4980 4981 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4982 ixgbe_vlan_strip_enable(adapter); 4983 else 4984 ixgbe_vlan_strip_disable(adapter); 4985 4986 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4987 ixgbe_vlan_promisc_disable(adapter); 4988 else 4989 ixgbe_vlan_promisc_enable(adapter); 4990 } 4991 4992 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4993 { 4994 int q_idx; 4995 4996 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4997 napi_enable(&adapter->q_vector[q_idx]->napi); 4998 } 4999 5000 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5001 { 5002 int q_idx; 5003 5004 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5005 napi_disable(&adapter->q_vector[q_idx]->napi); 5006 } 5007 5008 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5009 { 5010 struct ixgbe_hw *hw = &adapter->hw; 5011 u32 vxlanctrl; 5012 5013 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5014 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5015 return; 5016 5017 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5018 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5019 5020 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5021 adapter->vxlan_port = 0; 5022 5023 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5024 adapter->geneve_port = 0; 5025 } 5026 5027 #ifdef CONFIG_IXGBE_DCB 5028 /** 5029 * ixgbe_configure_dcb - Configure DCB hardware 5030 * @adapter: ixgbe adapter struct 5031 * 5032 * This is called by the driver on open to configure the DCB hardware. 5033 * This is also called by the gennetlink interface when reconfiguring 5034 * the DCB state. 5035 */ 5036 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5037 { 5038 struct ixgbe_hw *hw = &adapter->hw; 5039 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5040 5041 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5042 if (hw->mac.type == ixgbe_mac_82598EB) 5043 netif_set_gso_max_size(adapter->netdev, 65536); 5044 return; 5045 } 5046 5047 if (hw->mac.type == ixgbe_mac_82598EB) 5048 netif_set_gso_max_size(adapter->netdev, 32768); 5049 5050 #ifdef IXGBE_FCOE 5051 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5052 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5053 #endif 5054 5055 /* reconfigure the hardware */ 5056 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5057 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5058 DCB_TX_CONFIG); 5059 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5060 DCB_RX_CONFIG); 5061 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5062 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5063 ixgbe_dcb_hw_ets(&adapter->hw, 5064 adapter->ixgbe_ieee_ets, 5065 max_frame); 5066 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5067 adapter->ixgbe_ieee_pfc->pfc_en, 5068 adapter->ixgbe_ieee_ets->prio_tc); 5069 } 5070 5071 /* Enable RSS Hash per TC */ 5072 if (hw->mac.type != ixgbe_mac_82598EB) { 5073 u32 msb = 0; 5074 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5075 5076 while (rss_i) { 5077 msb++; 5078 rss_i >>= 1; 5079 } 5080 5081 /* write msb to all 8 TCs in one write */ 5082 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5083 } 5084 } 5085 #endif 5086 5087 /* Additional bittime to account for IXGBE framing */ 5088 #define IXGBE_ETH_FRAMING 20 5089 5090 /** 5091 * ixgbe_hpbthresh - calculate high water mark for flow control 5092 * 5093 * @adapter: board private structure to calculate for 5094 * @pb: packet buffer to calculate 5095 */ 5096 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5097 { 5098 struct ixgbe_hw *hw = &adapter->hw; 5099 struct net_device *dev = adapter->netdev; 5100 int link, tc, kb, marker; 5101 u32 dv_id, rx_pba; 5102 5103 /* Calculate max LAN frame size */ 5104 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5105 5106 #ifdef IXGBE_FCOE 5107 /* FCoE traffic class uses FCOE jumbo frames */ 5108 if ((dev->features & NETIF_F_FCOE_MTU) && 5109 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5110 (pb == ixgbe_fcoe_get_tc(adapter))) 5111 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5112 #endif 5113 5114 /* Calculate delay value for device */ 5115 switch (hw->mac.type) { 5116 case ixgbe_mac_X540: 5117 case ixgbe_mac_X550: 5118 case ixgbe_mac_X550EM_x: 5119 case ixgbe_mac_x550em_a: 5120 dv_id = IXGBE_DV_X540(link, tc); 5121 break; 5122 default: 5123 dv_id = IXGBE_DV(link, tc); 5124 break; 5125 } 5126 5127 /* Loopback switch introduces additional latency */ 5128 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5129 dv_id += IXGBE_B2BT(tc); 5130 5131 /* Delay value is calculated in bit times convert to KB */ 5132 kb = IXGBE_BT2KB(dv_id); 5133 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5134 5135 marker = rx_pba - kb; 5136 5137 /* It is possible that the packet buffer is not large enough 5138 * to provide required headroom. In this case throw an error 5139 * to user and a do the best we can. 5140 */ 5141 if (marker < 0) { 5142 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5143 "headroom to support flow control." 5144 "Decrease MTU or number of traffic classes\n", pb); 5145 marker = tc + 1; 5146 } 5147 5148 return marker; 5149 } 5150 5151 /** 5152 * ixgbe_lpbthresh - calculate low water mark for for flow control 5153 * 5154 * @adapter: board private structure to calculate for 5155 * @pb: packet buffer to calculate 5156 */ 5157 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5158 { 5159 struct ixgbe_hw *hw = &adapter->hw; 5160 struct net_device *dev = adapter->netdev; 5161 int tc; 5162 u32 dv_id; 5163 5164 /* Calculate max LAN frame size */ 5165 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5166 5167 #ifdef IXGBE_FCOE 5168 /* FCoE traffic class uses FCOE jumbo frames */ 5169 if ((dev->features & NETIF_F_FCOE_MTU) && 5170 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5171 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5172 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5173 #endif 5174 5175 /* Calculate delay value for device */ 5176 switch (hw->mac.type) { 5177 case ixgbe_mac_X540: 5178 case ixgbe_mac_X550: 5179 case ixgbe_mac_X550EM_x: 5180 case ixgbe_mac_x550em_a: 5181 dv_id = IXGBE_LOW_DV_X540(tc); 5182 break; 5183 default: 5184 dv_id = IXGBE_LOW_DV(tc); 5185 break; 5186 } 5187 5188 /* Delay value is calculated in bit times convert to KB */ 5189 return IXGBE_BT2KB(dv_id); 5190 } 5191 5192 /* 5193 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5194 */ 5195 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5196 { 5197 struct ixgbe_hw *hw = &adapter->hw; 5198 int num_tc = adapter->hw_tcs; 5199 int i; 5200 5201 if (!num_tc) 5202 num_tc = 1; 5203 5204 for (i = 0; i < num_tc; i++) { 5205 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5206 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5207 5208 /* Low water marks must not be larger than high water marks */ 5209 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5210 hw->fc.low_water[i] = 0; 5211 } 5212 5213 for (; i < MAX_TRAFFIC_CLASS; i++) 5214 hw->fc.high_water[i] = 0; 5215 } 5216 5217 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5218 { 5219 struct ixgbe_hw *hw = &adapter->hw; 5220 int hdrm; 5221 u8 tc = adapter->hw_tcs; 5222 5223 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5224 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5225 hdrm = 32 << adapter->fdir_pballoc; 5226 else 5227 hdrm = 0; 5228 5229 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5230 ixgbe_pbthresh_setup(adapter); 5231 } 5232 5233 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5234 { 5235 struct ixgbe_hw *hw = &adapter->hw; 5236 struct hlist_node *node2; 5237 struct ixgbe_fdir_filter *filter; 5238 u64 action; 5239 5240 spin_lock(&adapter->fdir_perfect_lock); 5241 5242 if (!hlist_empty(&adapter->fdir_filter_list)) 5243 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5244 5245 hlist_for_each_entry_safe(filter, node2, 5246 &adapter->fdir_filter_list, fdir_node) { 5247 action = filter->action; 5248 if (action != IXGBE_FDIR_DROP_QUEUE && action != 0) 5249 action = 5250 (action >> ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF) - 1; 5251 5252 ixgbe_fdir_write_perfect_filter_82599(hw, 5253 &filter->filter, 5254 filter->sw_idx, 5255 (action == IXGBE_FDIR_DROP_QUEUE) ? 5256 IXGBE_FDIR_DROP_QUEUE : 5257 adapter->rx_ring[action]->reg_idx); 5258 } 5259 5260 spin_unlock(&adapter->fdir_perfect_lock); 5261 } 5262 5263 /** 5264 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5265 * @rx_ring: ring to free buffers from 5266 **/ 5267 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5268 { 5269 u16 i = rx_ring->next_to_clean; 5270 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5271 5272 if (rx_ring->xsk_umem) { 5273 ixgbe_xsk_clean_rx_ring(rx_ring); 5274 goto skip_free; 5275 } 5276 5277 /* Free all the Rx ring sk_buffs */ 5278 while (i != rx_ring->next_to_alloc) { 5279 if (rx_buffer->skb) { 5280 struct sk_buff *skb = rx_buffer->skb; 5281 if (IXGBE_CB(skb)->page_released) 5282 dma_unmap_page_attrs(rx_ring->dev, 5283 IXGBE_CB(skb)->dma, 5284 ixgbe_rx_pg_size(rx_ring), 5285 DMA_FROM_DEVICE, 5286 IXGBE_RX_DMA_ATTR); 5287 dev_kfree_skb(skb); 5288 } 5289 5290 /* Invalidate cache lines that may have been written to by 5291 * device so that we avoid corrupting memory. 5292 */ 5293 dma_sync_single_range_for_cpu(rx_ring->dev, 5294 rx_buffer->dma, 5295 rx_buffer->page_offset, 5296 ixgbe_rx_bufsz(rx_ring), 5297 DMA_FROM_DEVICE); 5298 5299 /* free resources associated with mapping */ 5300 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5301 ixgbe_rx_pg_size(rx_ring), 5302 DMA_FROM_DEVICE, 5303 IXGBE_RX_DMA_ATTR); 5304 __page_frag_cache_drain(rx_buffer->page, 5305 rx_buffer->pagecnt_bias); 5306 5307 i++; 5308 rx_buffer++; 5309 if (i == rx_ring->count) { 5310 i = 0; 5311 rx_buffer = rx_ring->rx_buffer_info; 5312 } 5313 } 5314 5315 skip_free: 5316 rx_ring->next_to_alloc = 0; 5317 rx_ring->next_to_clean = 0; 5318 rx_ring->next_to_use = 0; 5319 } 5320 5321 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5322 struct ixgbe_fwd_adapter *accel) 5323 { 5324 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5325 int num_tc = netdev_get_num_tc(adapter->netdev); 5326 struct net_device *vdev = accel->netdev; 5327 int i, baseq, err; 5328 5329 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5330 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5331 accel->pool, adapter->num_rx_pools, 5332 baseq, baseq + adapter->num_rx_queues_per_pool); 5333 5334 accel->rx_base_queue = baseq; 5335 accel->tx_base_queue = baseq; 5336 5337 /* record configuration for macvlan interface in vdev */ 5338 for (i = 0; i < num_tc; i++) 5339 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5340 i, rss_i, baseq + (rss_i * i)); 5341 5342 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5343 adapter->rx_ring[baseq + i]->netdev = vdev; 5344 5345 /* Guarantee all rings are updated before we update the 5346 * MAC address filter. 5347 */ 5348 wmb(); 5349 5350 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5351 * need to only treat it as an error value if it is negative. 5352 */ 5353 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5354 VMDQ_P(accel->pool)); 5355 if (err >= 0) 5356 return 0; 5357 5358 /* if we cannot add the MAC rule then disable the offload */ 5359 macvlan_release_l2fw_offload(vdev); 5360 5361 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5362 adapter->rx_ring[baseq + i]->netdev = NULL; 5363 5364 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5365 5366 /* unbind the queues and drop the subordinate channel config */ 5367 netdev_unbind_sb_channel(adapter->netdev, vdev); 5368 netdev_set_sb_channel(vdev, 0); 5369 5370 clear_bit(accel->pool, adapter->fwd_bitmask); 5371 kfree(accel); 5372 5373 return err; 5374 } 5375 5376 static int ixgbe_macvlan_up(struct net_device *vdev, void *data) 5377 { 5378 struct ixgbe_adapter *adapter = data; 5379 struct ixgbe_fwd_adapter *accel; 5380 5381 if (!netif_is_macvlan(vdev)) 5382 return 0; 5383 5384 accel = macvlan_accel_priv(vdev); 5385 if (!accel) 5386 return 0; 5387 5388 ixgbe_fwd_ring_up(adapter, accel); 5389 5390 return 0; 5391 } 5392 5393 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5394 { 5395 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5396 ixgbe_macvlan_up, adapter); 5397 } 5398 5399 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5400 { 5401 struct ixgbe_hw *hw = &adapter->hw; 5402 5403 ixgbe_configure_pb(adapter); 5404 #ifdef CONFIG_IXGBE_DCB 5405 ixgbe_configure_dcb(adapter); 5406 #endif 5407 /* 5408 * We must restore virtualization before VLANs or else 5409 * the VLVF registers will not be populated 5410 */ 5411 ixgbe_configure_virtualization(adapter); 5412 5413 ixgbe_set_rx_mode(adapter->netdev); 5414 ixgbe_restore_vlan(adapter); 5415 ixgbe_ipsec_restore(adapter); 5416 5417 switch (hw->mac.type) { 5418 case ixgbe_mac_82599EB: 5419 case ixgbe_mac_X540: 5420 hw->mac.ops.disable_rx_buff(hw); 5421 break; 5422 default: 5423 break; 5424 } 5425 5426 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5427 ixgbe_init_fdir_signature_82599(&adapter->hw, 5428 adapter->fdir_pballoc); 5429 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5430 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5431 adapter->fdir_pballoc); 5432 ixgbe_fdir_filter_restore(adapter); 5433 } 5434 5435 switch (hw->mac.type) { 5436 case ixgbe_mac_82599EB: 5437 case ixgbe_mac_X540: 5438 hw->mac.ops.enable_rx_buff(hw); 5439 break; 5440 default: 5441 break; 5442 } 5443 5444 #ifdef CONFIG_IXGBE_DCA 5445 /* configure DCA */ 5446 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5447 ixgbe_setup_dca(adapter); 5448 #endif /* CONFIG_IXGBE_DCA */ 5449 5450 #ifdef IXGBE_FCOE 5451 /* configure FCoE L2 filters, redirection table, and Rx control */ 5452 ixgbe_configure_fcoe(adapter); 5453 5454 #endif /* IXGBE_FCOE */ 5455 ixgbe_configure_tx(adapter); 5456 ixgbe_configure_rx(adapter); 5457 ixgbe_configure_dfwd(adapter); 5458 } 5459 5460 /** 5461 * ixgbe_sfp_link_config - set up SFP+ link 5462 * @adapter: pointer to private adapter struct 5463 **/ 5464 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5465 { 5466 /* 5467 * We are assuming the worst case scenario here, and that 5468 * is that an SFP was inserted/removed after the reset 5469 * but before SFP detection was enabled. As such the best 5470 * solution is to just start searching as soon as we start 5471 */ 5472 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5473 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5474 5475 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5476 adapter->sfp_poll_time = 0; 5477 } 5478 5479 /** 5480 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5481 * @hw: pointer to private hardware struct 5482 * 5483 * Returns 0 on success, negative on failure 5484 **/ 5485 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5486 { 5487 u32 speed; 5488 bool autoneg, link_up = false; 5489 int ret = IXGBE_ERR_LINK_SETUP; 5490 5491 if (hw->mac.ops.check_link) 5492 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5493 5494 if (ret) 5495 return ret; 5496 5497 speed = hw->phy.autoneg_advertised; 5498 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5499 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5500 &autoneg); 5501 if (ret) 5502 return ret; 5503 5504 if (hw->mac.ops.setup_link) 5505 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5506 5507 return ret; 5508 } 5509 5510 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5511 { 5512 struct ixgbe_hw *hw = &adapter->hw; 5513 u32 gpie = 0; 5514 5515 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5516 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5517 IXGBE_GPIE_OCD; 5518 gpie |= IXGBE_GPIE_EIAME; 5519 /* 5520 * use EIAM to auto-mask when MSI-X interrupt is asserted 5521 * this saves a register write for every interrupt 5522 */ 5523 switch (hw->mac.type) { 5524 case ixgbe_mac_82598EB: 5525 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5526 break; 5527 case ixgbe_mac_82599EB: 5528 case ixgbe_mac_X540: 5529 case ixgbe_mac_X550: 5530 case ixgbe_mac_X550EM_x: 5531 case ixgbe_mac_x550em_a: 5532 default: 5533 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5534 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5535 break; 5536 } 5537 } else { 5538 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5539 * specifically only auto mask tx and rx interrupts */ 5540 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5541 } 5542 5543 /* XXX: to interrupt immediately for EICS writes, enable this */ 5544 /* gpie |= IXGBE_GPIE_EIMEN; */ 5545 5546 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5547 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5548 5549 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5550 case IXGBE_82599_VMDQ_8Q_MASK: 5551 gpie |= IXGBE_GPIE_VTMODE_16; 5552 break; 5553 case IXGBE_82599_VMDQ_4Q_MASK: 5554 gpie |= IXGBE_GPIE_VTMODE_32; 5555 break; 5556 default: 5557 gpie |= IXGBE_GPIE_VTMODE_64; 5558 break; 5559 } 5560 } 5561 5562 /* Enable Thermal over heat sensor interrupt */ 5563 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5564 switch (adapter->hw.mac.type) { 5565 case ixgbe_mac_82599EB: 5566 gpie |= IXGBE_SDP0_GPIEN_8259X; 5567 break; 5568 default: 5569 break; 5570 } 5571 } 5572 5573 /* Enable fan failure interrupt */ 5574 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5575 gpie |= IXGBE_SDP1_GPIEN(hw); 5576 5577 switch (hw->mac.type) { 5578 case ixgbe_mac_82599EB: 5579 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5580 break; 5581 case ixgbe_mac_X550EM_x: 5582 case ixgbe_mac_x550em_a: 5583 gpie |= IXGBE_SDP0_GPIEN_X540; 5584 break; 5585 default: 5586 break; 5587 } 5588 5589 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5590 } 5591 5592 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5593 { 5594 struct ixgbe_hw *hw = &adapter->hw; 5595 int err; 5596 u32 ctrl_ext; 5597 5598 ixgbe_get_hw_control(adapter); 5599 ixgbe_setup_gpie(adapter); 5600 5601 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5602 ixgbe_configure_msix(adapter); 5603 else 5604 ixgbe_configure_msi_and_legacy(adapter); 5605 5606 /* enable the optics for 82599 SFP+ fiber */ 5607 if (hw->mac.ops.enable_tx_laser) 5608 hw->mac.ops.enable_tx_laser(hw); 5609 5610 if (hw->phy.ops.set_phy_power) 5611 hw->phy.ops.set_phy_power(hw, true); 5612 5613 smp_mb__before_atomic(); 5614 clear_bit(__IXGBE_DOWN, &adapter->state); 5615 ixgbe_napi_enable_all(adapter); 5616 5617 if (ixgbe_is_sfp(hw)) { 5618 ixgbe_sfp_link_config(adapter); 5619 } else { 5620 err = ixgbe_non_sfp_link_config(hw); 5621 if (err) 5622 e_err(probe, "link_config FAILED %d\n", err); 5623 } 5624 5625 /* clear any pending interrupts, may auto mask */ 5626 IXGBE_READ_REG(hw, IXGBE_EICR); 5627 ixgbe_irq_enable(adapter, true, true); 5628 5629 /* 5630 * If this adapter has a fan, check to see if we had a failure 5631 * before we enabled the interrupt. 5632 */ 5633 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5634 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5635 if (esdp & IXGBE_ESDP_SDP1) 5636 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5637 } 5638 5639 /* bring the link up in the watchdog, this could race with our first 5640 * link up interrupt but shouldn't be a problem */ 5641 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5642 adapter->link_check_timeout = jiffies; 5643 mod_timer(&adapter->service_timer, jiffies); 5644 5645 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5646 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5647 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5648 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5649 } 5650 5651 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5652 { 5653 WARN_ON(in_interrupt()); 5654 /* put off any impending NetWatchDogTimeout */ 5655 netif_trans_update(adapter->netdev); 5656 5657 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5658 usleep_range(1000, 2000); 5659 if (adapter->hw.phy.type == ixgbe_phy_fw) 5660 ixgbe_watchdog_link_is_down(adapter); 5661 ixgbe_down(adapter); 5662 /* 5663 * If SR-IOV enabled then wait a bit before bringing the adapter 5664 * back up to give the VFs time to respond to the reset. The 5665 * two second wait is based upon the watchdog timer cycle in 5666 * the VF driver. 5667 */ 5668 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5669 msleep(2000); 5670 ixgbe_up(adapter); 5671 clear_bit(__IXGBE_RESETTING, &adapter->state); 5672 } 5673 5674 void ixgbe_up(struct ixgbe_adapter *adapter) 5675 { 5676 /* hardware has been reset, we need to reload some things */ 5677 ixgbe_configure(adapter); 5678 5679 ixgbe_up_complete(adapter); 5680 } 5681 5682 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5683 { 5684 u16 devctl2; 5685 5686 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5687 5688 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5689 case IXGBE_PCIDEVCTRL2_17_34s: 5690 case IXGBE_PCIDEVCTRL2_4_8s: 5691 /* For now we cap the upper limit on delay to 2 seconds 5692 * as we end up going up to 34 seconds of delay in worst 5693 * case timeout value. 5694 */ 5695 case IXGBE_PCIDEVCTRL2_1_2s: 5696 return 2000000ul; /* 2.0 s */ 5697 case IXGBE_PCIDEVCTRL2_260_520ms: 5698 return 520000ul; /* 520 ms */ 5699 case IXGBE_PCIDEVCTRL2_65_130ms: 5700 return 130000ul; /* 130 ms */ 5701 case IXGBE_PCIDEVCTRL2_16_32ms: 5702 return 32000ul; /* 32 ms */ 5703 case IXGBE_PCIDEVCTRL2_1_2ms: 5704 return 2000ul; /* 2 ms */ 5705 case IXGBE_PCIDEVCTRL2_50_100us: 5706 return 100ul; /* 100 us */ 5707 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5708 return 32000ul; /* 32 ms */ 5709 default: 5710 break; 5711 } 5712 5713 /* We shouldn't need to hit this path, but just in case default as 5714 * though completion timeout is not supported and support 32ms. 5715 */ 5716 return 32000ul; 5717 } 5718 5719 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5720 { 5721 unsigned long wait_delay, delay_interval; 5722 struct ixgbe_hw *hw = &adapter->hw; 5723 int i, wait_loop; 5724 u32 rxdctl; 5725 5726 /* disable receives */ 5727 hw->mac.ops.disable_rx(hw); 5728 5729 if (ixgbe_removed(hw->hw_addr)) 5730 return; 5731 5732 /* disable all enabled Rx queues */ 5733 for (i = 0; i < adapter->num_rx_queues; i++) { 5734 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5735 u8 reg_idx = ring->reg_idx; 5736 5737 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5738 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5739 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5740 5741 /* write value back with RXDCTL.ENABLE bit cleared */ 5742 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5743 } 5744 5745 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5746 if (hw->mac.type == ixgbe_mac_82598EB && 5747 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5748 return; 5749 5750 /* Determine our minimum delay interval. We will increase this value 5751 * with each subsequent test. This way if the device returns quickly 5752 * we should spend as little time as possible waiting, however as 5753 * the time increases we will wait for larger periods of time. 5754 * 5755 * The trick here is that we increase the interval using the 5756 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5757 * of that wait is that it totals up to 100x whatever interval we 5758 * choose. Since our minimum wait is 100us we can just divide the 5759 * total timeout by 100 to get our minimum delay interval. 5760 */ 5761 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5762 5763 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5764 wait_delay = delay_interval; 5765 5766 while (wait_loop--) { 5767 usleep_range(wait_delay, wait_delay + 10); 5768 wait_delay += delay_interval * 2; 5769 rxdctl = 0; 5770 5771 /* OR together the reading of all the active RXDCTL registers, 5772 * and then test the result. We need the disable to complete 5773 * before we start freeing the memory and invalidating the 5774 * DMA mappings. 5775 */ 5776 for (i = 0; i < adapter->num_rx_queues; i++) { 5777 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5778 u8 reg_idx = ring->reg_idx; 5779 5780 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5781 } 5782 5783 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5784 return; 5785 } 5786 5787 e_err(drv, 5788 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5789 } 5790 5791 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5792 { 5793 unsigned long wait_delay, delay_interval; 5794 struct ixgbe_hw *hw = &adapter->hw; 5795 int i, wait_loop; 5796 u32 txdctl; 5797 5798 if (ixgbe_removed(hw->hw_addr)) 5799 return; 5800 5801 /* disable all enabled Tx queues */ 5802 for (i = 0; i < adapter->num_tx_queues; i++) { 5803 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5804 u8 reg_idx = ring->reg_idx; 5805 5806 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5807 } 5808 5809 /* disable all enabled XDP Tx queues */ 5810 for (i = 0; i < adapter->num_xdp_queues; i++) { 5811 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5812 u8 reg_idx = ring->reg_idx; 5813 5814 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5815 } 5816 5817 /* If the link is not up there shouldn't be much in the way of 5818 * pending transactions. Those that are left will be flushed out 5819 * when the reset logic goes through the flush sequence to clean out 5820 * the pending Tx transactions. 5821 */ 5822 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5823 goto dma_engine_disable; 5824 5825 /* Determine our minimum delay interval. We will increase this value 5826 * with each subsequent test. This way if the device returns quickly 5827 * we should spend as little time as possible waiting, however as 5828 * the time increases we will wait for larger periods of time. 5829 * 5830 * The trick here is that we increase the interval using the 5831 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5832 * of that wait is that it totals up to 100x whatever interval we 5833 * choose. Since our minimum wait is 100us we can just divide the 5834 * total timeout by 100 to get our minimum delay interval. 5835 */ 5836 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5837 5838 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5839 wait_delay = delay_interval; 5840 5841 while (wait_loop--) { 5842 usleep_range(wait_delay, wait_delay + 10); 5843 wait_delay += delay_interval * 2; 5844 txdctl = 0; 5845 5846 /* OR together the reading of all the active TXDCTL registers, 5847 * and then test the result. We need the disable to complete 5848 * before we start freeing the memory and invalidating the 5849 * DMA mappings. 5850 */ 5851 for (i = 0; i < adapter->num_tx_queues; i++) { 5852 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5853 u8 reg_idx = ring->reg_idx; 5854 5855 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5856 } 5857 for (i = 0; i < adapter->num_xdp_queues; i++) { 5858 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5859 u8 reg_idx = ring->reg_idx; 5860 5861 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5862 } 5863 5864 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5865 goto dma_engine_disable; 5866 } 5867 5868 e_err(drv, 5869 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5870 5871 dma_engine_disable: 5872 /* Disable the Tx DMA engine on 82599 and later MAC */ 5873 switch (hw->mac.type) { 5874 case ixgbe_mac_82599EB: 5875 case ixgbe_mac_X540: 5876 case ixgbe_mac_X550: 5877 case ixgbe_mac_X550EM_x: 5878 case ixgbe_mac_x550em_a: 5879 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5880 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5881 ~IXGBE_DMATXCTL_TE)); 5882 /* fall through */ 5883 default: 5884 break; 5885 } 5886 } 5887 5888 void ixgbe_reset(struct ixgbe_adapter *adapter) 5889 { 5890 struct ixgbe_hw *hw = &adapter->hw; 5891 struct net_device *netdev = adapter->netdev; 5892 int err; 5893 5894 if (ixgbe_removed(hw->hw_addr)) 5895 return; 5896 /* lock SFP init bit to prevent race conditions with the watchdog */ 5897 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5898 usleep_range(1000, 2000); 5899 5900 /* clear all SFP and link config related flags while holding SFP_INIT */ 5901 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5902 IXGBE_FLAG2_SFP_NEEDS_RESET); 5903 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5904 5905 err = hw->mac.ops.init_hw(hw); 5906 switch (err) { 5907 case 0: 5908 case IXGBE_ERR_SFP_NOT_PRESENT: 5909 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5910 break; 5911 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5912 e_dev_err("master disable timed out\n"); 5913 break; 5914 case IXGBE_ERR_EEPROM_VERSION: 5915 /* We are running on a pre-production device, log a warning */ 5916 e_dev_warn("This device is a pre-production adapter/LOM. " 5917 "Please be aware there may be issues associated with " 5918 "your hardware. If you are experiencing problems " 5919 "please contact your Intel or hardware " 5920 "representative who provided you with this " 5921 "hardware.\n"); 5922 break; 5923 default: 5924 e_dev_err("Hardware Error: %d\n", err); 5925 } 5926 5927 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5928 5929 /* flush entries out of MAC table */ 5930 ixgbe_flush_sw_mac_table(adapter); 5931 __dev_uc_unsync(netdev, NULL); 5932 5933 /* do not flush user set addresses */ 5934 ixgbe_mac_set_default_filter(adapter); 5935 5936 /* update SAN MAC vmdq pool selection */ 5937 if (hw->mac.san_mac_rar_index) 5938 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5939 5940 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5941 ixgbe_ptp_reset(adapter); 5942 5943 if (hw->phy.ops.set_phy_power) { 5944 if (!netif_running(adapter->netdev) && !adapter->wol) 5945 hw->phy.ops.set_phy_power(hw, false); 5946 else 5947 hw->phy.ops.set_phy_power(hw, true); 5948 } 5949 } 5950 5951 /** 5952 * ixgbe_clean_tx_ring - Free Tx Buffers 5953 * @tx_ring: ring to be cleaned 5954 **/ 5955 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5956 { 5957 u16 i = tx_ring->next_to_clean; 5958 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5959 5960 if (tx_ring->xsk_umem) { 5961 ixgbe_xsk_clean_tx_ring(tx_ring); 5962 goto out; 5963 } 5964 5965 while (i != tx_ring->next_to_use) { 5966 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5967 5968 /* Free all the Tx ring sk_buffs */ 5969 if (ring_is_xdp(tx_ring)) 5970 xdp_return_frame(tx_buffer->xdpf); 5971 else 5972 dev_kfree_skb_any(tx_buffer->skb); 5973 5974 /* unmap skb header data */ 5975 dma_unmap_single(tx_ring->dev, 5976 dma_unmap_addr(tx_buffer, dma), 5977 dma_unmap_len(tx_buffer, len), 5978 DMA_TO_DEVICE); 5979 5980 /* check for eop_desc to determine the end of the packet */ 5981 eop_desc = tx_buffer->next_to_watch; 5982 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5983 5984 /* unmap remaining buffers */ 5985 while (tx_desc != eop_desc) { 5986 tx_buffer++; 5987 tx_desc++; 5988 i++; 5989 if (unlikely(i == tx_ring->count)) { 5990 i = 0; 5991 tx_buffer = tx_ring->tx_buffer_info; 5992 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5993 } 5994 5995 /* unmap any remaining paged data */ 5996 if (dma_unmap_len(tx_buffer, len)) 5997 dma_unmap_page(tx_ring->dev, 5998 dma_unmap_addr(tx_buffer, dma), 5999 dma_unmap_len(tx_buffer, len), 6000 DMA_TO_DEVICE); 6001 } 6002 6003 /* move us one more past the eop_desc for start of next pkt */ 6004 tx_buffer++; 6005 i++; 6006 if (unlikely(i == tx_ring->count)) { 6007 i = 0; 6008 tx_buffer = tx_ring->tx_buffer_info; 6009 } 6010 } 6011 6012 /* reset BQL for queue */ 6013 if (!ring_is_xdp(tx_ring)) 6014 netdev_tx_reset_queue(txring_txq(tx_ring)); 6015 6016 out: 6017 /* reset next_to_use and next_to_clean */ 6018 tx_ring->next_to_use = 0; 6019 tx_ring->next_to_clean = 0; 6020 } 6021 6022 /** 6023 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6024 * @adapter: board private structure 6025 **/ 6026 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6027 { 6028 int i; 6029 6030 for (i = 0; i < adapter->num_rx_queues; i++) 6031 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6032 } 6033 6034 /** 6035 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6036 * @adapter: board private structure 6037 **/ 6038 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6039 { 6040 int i; 6041 6042 for (i = 0; i < adapter->num_tx_queues; i++) 6043 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6044 for (i = 0; i < adapter->num_xdp_queues; i++) 6045 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6046 } 6047 6048 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6049 { 6050 struct hlist_node *node2; 6051 struct ixgbe_fdir_filter *filter; 6052 6053 spin_lock(&adapter->fdir_perfect_lock); 6054 6055 hlist_for_each_entry_safe(filter, node2, 6056 &adapter->fdir_filter_list, fdir_node) { 6057 hlist_del(&filter->fdir_node); 6058 kfree(filter); 6059 } 6060 adapter->fdir_filter_count = 0; 6061 6062 spin_unlock(&adapter->fdir_perfect_lock); 6063 } 6064 6065 void ixgbe_down(struct ixgbe_adapter *adapter) 6066 { 6067 struct net_device *netdev = adapter->netdev; 6068 struct ixgbe_hw *hw = &adapter->hw; 6069 int i; 6070 6071 /* signal that we are down to the interrupt handler */ 6072 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6073 return; /* do nothing if already down */ 6074 6075 /* Shut off incoming Tx traffic */ 6076 netif_tx_stop_all_queues(netdev); 6077 6078 /* call carrier off first to avoid false dev_watchdog timeouts */ 6079 netif_carrier_off(netdev); 6080 netif_tx_disable(netdev); 6081 6082 /* Disable Rx */ 6083 ixgbe_disable_rx(adapter); 6084 6085 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6086 if (adapter->xdp_ring[0]) 6087 synchronize_rcu(); 6088 6089 ixgbe_irq_disable(adapter); 6090 6091 ixgbe_napi_disable_all(adapter); 6092 6093 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6094 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6095 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6096 6097 del_timer_sync(&adapter->service_timer); 6098 6099 if (adapter->num_vfs) { 6100 /* Clear EITR Select mapping */ 6101 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6102 6103 /* Mark all the VFs as inactive */ 6104 for (i = 0 ; i < adapter->num_vfs; i++) 6105 adapter->vfinfo[i].clear_to_send = false; 6106 6107 /* ping all the active vfs to let them know we are going down */ 6108 ixgbe_ping_all_vfs(adapter); 6109 6110 /* Disable all VFTE/VFRE TX/RX */ 6111 ixgbe_disable_tx_rx(adapter); 6112 } 6113 6114 /* disable transmits in the hardware now that interrupts are off */ 6115 ixgbe_disable_tx(adapter); 6116 6117 if (!pci_channel_offline(adapter->pdev)) 6118 ixgbe_reset(adapter); 6119 6120 /* power down the optics for 82599 SFP+ fiber */ 6121 if (hw->mac.ops.disable_tx_laser) 6122 hw->mac.ops.disable_tx_laser(hw); 6123 6124 ixgbe_clean_all_tx_rings(adapter); 6125 ixgbe_clean_all_rx_rings(adapter); 6126 } 6127 6128 /** 6129 * ixgbe_eee_capable - helper function to determine EEE support on X550 6130 * @adapter: board private structure 6131 */ 6132 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6133 { 6134 struct ixgbe_hw *hw = &adapter->hw; 6135 6136 switch (hw->device_id) { 6137 case IXGBE_DEV_ID_X550EM_A_1G_T: 6138 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6139 if (!hw->phy.eee_speeds_supported) 6140 break; 6141 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6142 if (!hw->phy.eee_speeds_advertised) 6143 break; 6144 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6145 break; 6146 default: 6147 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6148 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6149 break; 6150 } 6151 } 6152 6153 /** 6154 * ixgbe_tx_timeout - Respond to a Tx Hang 6155 * @netdev: network interface device structure 6156 **/ 6157 static void ixgbe_tx_timeout(struct net_device *netdev) 6158 { 6159 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6160 6161 /* Do the reset outside of interrupt context */ 6162 ixgbe_tx_timeout_reset(adapter); 6163 } 6164 6165 #ifdef CONFIG_IXGBE_DCB 6166 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6167 { 6168 struct ixgbe_hw *hw = &adapter->hw; 6169 struct tc_configuration *tc; 6170 int j; 6171 6172 switch (hw->mac.type) { 6173 case ixgbe_mac_82598EB: 6174 case ixgbe_mac_82599EB: 6175 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6176 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6177 break; 6178 case ixgbe_mac_X540: 6179 case ixgbe_mac_X550: 6180 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6181 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6182 break; 6183 case ixgbe_mac_X550EM_x: 6184 case ixgbe_mac_x550em_a: 6185 default: 6186 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6187 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6188 break; 6189 } 6190 6191 /* Configure DCB traffic classes */ 6192 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6193 tc = &adapter->dcb_cfg.tc_config[j]; 6194 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6195 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6196 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6197 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6198 tc->dcb_pfc = pfc_disabled; 6199 } 6200 6201 /* Initialize default user to priority mapping, UPx->TC0 */ 6202 tc = &adapter->dcb_cfg.tc_config[0]; 6203 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6204 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6205 6206 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6207 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6208 adapter->dcb_cfg.pfc_mode_enable = false; 6209 adapter->dcb_set_bitmap = 0x00; 6210 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6211 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6212 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6213 sizeof(adapter->temp_dcb_cfg)); 6214 } 6215 #endif 6216 6217 /** 6218 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6219 * @adapter: board private structure to initialize 6220 * @ii: pointer to ixgbe_info for device 6221 * 6222 * ixgbe_sw_init initializes the Adapter private data structure. 6223 * Fields are initialized based on PCI device information and 6224 * OS network device settings (MTU size). 6225 **/ 6226 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6227 const struct ixgbe_info *ii) 6228 { 6229 struct ixgbe_hw *hw = &adapter->hw; 6230 struct pci_dev *pdev = adapter->pdev; 6231 unsigned int rss, fdir; 6232 u32 fwsm; 6233 int i; 6234 6235 /* PCI config space info */ 6236 6237 hw->vendor_id = pdev->vendor; 6238 hw->device_id = pdev->device; 6239 hw->revision_id = pdev->revision; 6240 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6241 hw->subsystem_device_id = pdev->subsystem_device; 6242 6243 /* get_invariants needs the device IDs */ 6244 ii->get_invariants(hw); 6245 6246 /* Set common capability flags and settings */ 6247 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6248 adapter->ring_feature[RING_F_RSS].limit = rss; 6249 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6250 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6251 adapter->atr_sample_rate = 20; 6252 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6253 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6254 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6255 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6256 #ifdef CONFIG_IXGBE_DCA 6257 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6258 #endif 6259 #ifdef CONFIG_IXGBE_DCB 6260 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6261 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6262 #endif 6263 #ifdef IXGBE_FCOE 6264 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6265 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6266 #ifdef CONFIG_IXGBE_DCB 6267 /* Default traffic class to use for FCoE */ 6268 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6269 #endif /* CONFIG_IXGBE_DCB */ 6270 #endif /* IXGBE_FCOE */ 6271 6272 /* initialize static ixgbe jump table entries */ 6273 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6274 GFP_KERNEL); 6275 if (!adapter->jump_tables[0]) 6276 return -ENOMEM; 6277 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6278 6279 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6280 adapter->jump_tables[i] = NULL; 6281 6282 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6283 sizeof(struct ixgbe_mac_addr), 6284 GFP_KERNEL); 6285 if (!adapter->mac_table) 6286 return -ENOMEM; 6287 6288 if (ixgbe_init_rss_key(adapter)) 6289 return -ENOMEM; 6290 6291 /* Set MAC specific capability flags and exceptions */ 6292 switch (hw->mac.type) { 6293 case ixgbe_mac_82598EB: 6294 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6295 6296 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6297 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6298 6299 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6300 adapter->ring_feature[RING_F_FDIR].limit = 0; 6301 adapter->atr_sample_rate = 0; 6302 adapter->fdir_pballoc = 0; 6303 #ifdef IXGBE_FCOE 6304 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6305 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6306 #ifdef CONFIG_IXGBE_DCB 6307 adapter->fcoe.up = 0; 6308 #endif /* IXGBE_DCB */ 6309 #endif /* IXGBE_FCOE */ 6310 break; 6311 case ixgbe_mac_82599EB: 6312 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6313 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6314 break; 6315 case ixgbe_mac_X540: 6316 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6317 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6318 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6319 break; 6320 case ixgbe_mac_x550em_a: 6321 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6322 switch (hw->device_id) { 6323 case IXGBE_DEV_ID_X550EM_A_1G_T: 6324 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6325 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6326 break; 6327 default: 6328 break; 6329 } 6330 /* fall through */ 6331 case ixgbe_mac_X550EM_x: 6332 #ifdef CONFIG_IXGBE_DCB 6333 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6334 #endif 6335 #ifdef IXGBE_FCOE 6336 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6337 #ifdef CONFIG_IXGBE_DCB 6338 adapter->fcoe.up = 0; 6339 #endif /* IXGBE_DCB */ 6340 #endif /* IXGBE_FCOE */ 6341 /* Fall Through */ 6342 case ixgbe_mac_X550: 6343 if (hw->mac.type == ixgbe_mac_X550) 6344 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6345 #ifdef CONFIG_IXGBE_DCA 6346 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6347 #endif 6348 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6349 break; 6350 default: 6351 break; 6352 } 6353 6354 #ifdef IXGBE_FCOE 6355 /* FCoE support exists, always init the FCoE lock */ 6356 spin_lock_init(&adapter->fcoe.lock); 6357 6358 #endif 6359 /* n-tuple support exists, always init our spinlock */ 6360 spin_lock_init(&adapter->fdir_perfect_lock); 6361 6362 #ifdef CONFIG_IXGBE_DCB 6363 ixgbe_init_dcb(adapter); 6364 #endif 6365 ixgbe_init_ipsec_offload(adapter); 6366 6367 /* default flow control settings */ 6368 hw->fc.requested_mode = ixgbe_fc_full; 6369 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6370 ixgbe_pbthresh_setup(adapter); 6371 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6372 hw->fc.send_xon = true; 6373 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6374 6375 #ifdef CONFIG_PCI_IOV 6376 if (max_vfs > 0) 6377 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6378 6379 /* assign number of SR-IOV VFs */ 6380 if (hw->mac.type != ixgbe_mac_82598EB) { 6381 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6382 max_vfs = 0; 6383 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6384 } 6385 } 6386 #endif /* CONFIG_PCI_IOV */ 6387 6388 /* enable itr by default in dynamic mode */ 6389 adapter->rx_itr_setting = 1; 6390 adapter->tx_itr_setting = 1; 6391 6392 /* set default ring sizes */ 6393 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6394 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6395 6396 /* set default work limits */ 6397 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6398 6399 /* initialize eeprom parameters */ 6400 if (ixgbe_init_eeprom_params_generic(hw)) { 6401 e_dev_err("EEPROM initialization failed\n"); 6402 return -EIO; 6403 } 6404 6405 /* PF holds first pool slot */ 6406 set_bit(0, adapter->fwd_bitmask); 6407 set_bit(__IXGBE_DOWN, &adapter->state); 6408 6409 return 0; 6410 } 6411 6412 /** 6413 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6414 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6415 * 6416 * Return 0 on success, negative on failure 6417 **/ 6418 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6419 { 6420 struct device *dev = tx_ring->dev; 6421 int orig_node = dev_to_node(dev); 6422 int ring_node = NUMA_NO_NODE; 6423 int size; 6424 6425 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6426 6427 if (tx_ring->q_vector) 6428 ring_node = tx_ring->q_vector->numa_node; 6429 6430 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6431 if (!tx_ring->tx_buffer_info) 6432 tx_ring->tx_buffer_info = vmalloc(size); 6433 if (!tx_ring->tx_buffer_info) 6434 goto err; 6435 6436 /* round up to nearest 4K */ 6437 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6438 tx_ring->size = ALIGN(tx_ring->size, 4096); 6439 6440 set_dev_node(dev, ring_node); 6441 tx_ring->desc = dma_alloc_coherent(dev, 6442 tx_ring->size, 6443 &tx_ring->dma, 6444 GFP_KERNEL); 6445 set_dev_node(dev, orig_node); 6446 if (!tx_ring->desc) 6447 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6448 &tx_ring->dma, GFP_KERNEL); 6449 if (!tx_ring->desc) 6450 goto err; 6451 6452 tx_ring->next_to_use = 0; 6453 tx_ring->next_to_clean = 0; 6454 return 0; 6455 6456 err: 6457 vfree(tx_ring->tx_buffer_info); 6458 tx_ring->tx_buffer_info = NULL; 6459 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6460 return -ENOMEM; 6461 } 6462 6463 /** 6464 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6465 * @adapter: board private structure 6466 * 6467 * If this function returns with an error, then it's possible one or 6468 * more of the rings is populated (while the rest are not). It is the 6469 * callers duty to clean those orphaned rings. 6470 * 6471 * Return 0 on success, negative on failure 6472 **/ 6473 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6474 { 6475 int i, j = 0, err = 0; 6476 6477 for (i = 0; i < adapter->num_tx_queues; i++) { 6478 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6479 if (!err) 6480 continue; 6481 6482 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6483 goto err_setup_tx; 6484 } 6485 for (j = 0; j < adapter->num_xdp_queues; j++) { 6486 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6487 if (!err) 6488 continue; 6489 6490 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6491 goto err_setup_tx; 6492 } 6493 6494 return 0; 6495 err_setup_tx: 6496 /* rewind the index freeing the rings as we go */ 6497 while (j--) 6498 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6499 while (i--) 6500 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6501 return err; 6502 } 6503 6504 /** 6505 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6506 * @adapter: pointer to ixgbe_adapter 6507 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6508 * 6509 * Returns 0 on success, negative on failure 6510 **/ 6511 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6512 struct ixgbe_ring *rx_ring) 6513 { 6514 struct device *dev = rx_ring->dev; 6515 int orig_node = dev_to_node(dev); 6516 int ring_node = NUMA_NO_NODE; 6517 int size; 6518 6519 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6520 6521 if (rx_ring->q_vector) 6522 ring_node = rx_ring->q_vector->numa_node; 6523 6524 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6525 if (!rx_ring->rx_buffer_info) 6526 rx_ring->rx_buffer_info = vmalloc(size); 6527 if (!rx_ring->rx_buffer_info) 6528 goto err; 6529 6530 /* Round up to nearest 4K */ 6531 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6532 rx_ring->size = ALIGN(rx_ring->size, 4096); 6533 6534 set_dev_node(dev, ring_node); 6535 rx_ring->desc = dma_alloc_coherent(dev, 6536 rx_ring->size, 6537 &rx_ring->dma, 6538 GFP_KERNEL); 6539 set_dev_node(dev, orig_node); 6540 if (!rx_ring->desc) 6541 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6542 &rx_ring->dma, GFP_KERNEL); 6543 if (!rx_ring->desc) 6544 goto err; 6545 6546 rx_ring->next_to_clean = 0; 6547 rx_ring->next_to_use = 0; 6548 6549 /* XDP RX-queue info */ 6550 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6551 rx_ring->queue_index) < 0) 6552 goto err; 6553 6554 rx_ring->xdp_prog = adapter->xdp_prog; 6555 6556 return 0; 6557 err: 6558 vfree(rx_ring->rx_buffer_info); 6559 rx_ring->rx_buffer_info = NULL; 6560 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6561 return -ENOMEM; 6562 } 6563 6564 /** 6565 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6566 * @adapter: board private structure 6567 * 6568 * If this function returns with an error, then it's possible one or 6569 * more of the rings is populated (while the rest are not). It is the 6570 * callers duty to clean those orphaned rings. 6571 * 6572 * Return 0 on success, negative on failure 6573 **/ 6574 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6575 { 6576 int i, err = 0; 6577 6578 for (i = 0; i < adapter->num_rx_queues; i++) { 6579 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6580 if (!err) 6581 continue; 6582 6583 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6584 goto err_setup_rx; 6585 } 6586 6587 #ifdef IXGBE_FCOE 6588 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6589 if (!err) 6590 #endif 6591 return 0; 6592 err_setup_rx: 6593 /* rewind the index freeing the rings as we go */ 6594 while (i--) 6595 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6596 return err; 6597 } 6598 6599 /** 6600 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6601 * @tx_ring: Tx descriptor ring for a specific queue 6602 * 6603 * Free all transmit software resources 6604 **/ 6605 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6606 { 6607 ixgbe_clean_tx_ring(tx_ring); 6608 6609 vfree(tx_ring->tx_buffer_info); 6610 tx_ring->tx_buffer_info = NULL; 6611 6612 /* if not set, then don't free */ 6613 if (!tx_ring->desc) 6614 return; 6615 6616 dma_free_coherent(tx_ring->dev, tx_ring->size, 6617 tx_ring->desc, tx_ring->dma); 6618 6619 tx_ring->desc = NULL; 6620 } 6621 6622 /** 6623 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6624 * @adapter: board private structure 6625 * 6626 * Free all transmit software resources 6627 **/ 6628 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6629 { 6630 int i; 6631 6632 for (i = 0; i < adapter->num_tx_queues; i++) 6633 if (adapter->tx_ring[i]->desc) 6634 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6635 for (i = 0; i < adapter->num_xdp_queues; i++) 6636 if (adapter->xdp_ring[i]->desc) 6637 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6638 } 6639 6640 /** 6641 * ixgbe_free_rx_resources - Free Rx Resources 6642 * @rx_ring: ring to clean the resources from 6643 * 6644 * Free all receive software resources 6645 **/ 6646 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6647 { 6648 ixgbe_clean_rx_ring(rx_ring); 6649 6650 rx_ring->xdp_prog = NULL; 6651 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6652 vfree(rx_ring->rx_buffer_info); 6653 rx_ring->rx_buffer_info = NULL; 6654 6655 /* if not set, then don't free */ 6656 if (!rx_ring->desc) 6657 return; 6658 6659 dma_free_coherent(rx_ring->dev, rx_ring->size, 6660 rx_ring->desc, rx_ring->dma); 6661 6662 rx_ring->desc = NULL; 6663 } 6664 6665 /** 6666 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6667 * @adapter: board private structure 6668 * 6669 * Free all receive software resources 6670 **/ 6671 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6672 { 6673 int i; 6674 6675 #ifdef IXGBE_FCOE 6676 ixgbe_free_fcoe_ddp_resources(adapter); 6677 6678 #endif 6679 for (i = 0; i < adapter->num_rx_queues; i++) 6680 if (adapter->rx_ring[i]->desc) 6681 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6682 } 6683 6684 /** 6685 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6686 * @netdev: network interface device structure 6687 * @new_mtu: new value for maximum frame size 6688 * 6689 * Returns 0 on success, negative on failure 6690 **/ 6691 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6692 { 6693 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6694 6695 if (adapter->xdp_prog) { 6696 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 6697 VLAN_HLEN; 6698 int i; 6699 6700 for (i = 0; i < adapter->num_rx_queues; i++) { 6701 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6702 6703 if (new_frame_size > ixgbe_rx_bufsz(ring)) { 6704 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6705 return -EINVAL; 6706 } 6707 } 6708 } 6709 6710 /* 6711 * For 82599EB we cannot allow legacy VFs to enable their receive 6712 * paths when MTU greater than 1500 is configured. So display a 6713 * warning that legacy VFs will be disabled. 6714 */ 6715 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6716 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6717 (new_mtu > ETH_DATA_LEN)) 6718 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6719 6720 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6721 6722 /* must set new MTU before calling down or up */ 6723 netdev->mtu = new_mtu; 6724 6725 if (netif_running(netdev)) 6726 ixgbe_reinit_locked(adapter); 6727 6728 return 0; 6729 } 6730 6731 /** 6732 * ixgbe_open - Called when a network interface is made active 6733 * @netdev: network interface device structure 6734 * 6735 * Returns 0 on success, negative value on failure 6736 * 6737 * The open entry point is called when a network interface is made 6738 * active by the system (IFF_UP). At this point all resources needed 6739 * for transmit and receive operations are allocated, the interrupt 6740 * handler is registered with the OS, the watchdog timer is started, 6741 * and the stack is notified that the interface is ready. 6742 **/ 6743 int ixgbe_open(struct net_device *netdev) 6744 { 6745 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6746 struct ixgbe_hw *hw = &adapter->hw; 6747 int err, queues; 6748 6749 /* disallow open during test */ 6750 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6751 return -EBUSY; 6752 6753 netif_carrier_off(netdev); 6754 6755 /* allocate transmit descriptors */ 6756 err = ixgbe_setup_all_tx_resources(adapter); 6757 if (err) 6758 goto err_setup_tx; 6759 6760 /* allocate receive descriptors */ 6761 err = ixgbe_setup_all_rx_resources(adapter); 6762 if (err) 6763 goto err_setup_rx; 6764 6765 ixgbe_configure(adapter); 6766 6767 err = ixgbe_request_irq(adapter); 6768 if (err) 6769 goto err_req_irq; 6770 6771 /* Notify the stack of the actual queue counts. */ 6772 queues = adapter->num_tx_queues; 6773 err = netif_set_real_num_tx_queues(netdev, queues); 6774 if (err) 6775 goto err_set_queues; 6776 6777 queues = adapter->num_rx_queues; 6778 err = netif_set_real_num_rx_queues(netdev, queues); 6779 if (err) 6780 goto err_set_queues; 6781 6782 ixgbe_ptp_init(adapter); 6783 6784 ixgbe_up_complete(adapter); 6785 6786 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6787 udp_tunnel_get_rx_info(netdev); 6788 6789 return 0; 6790 6791 err_set_queues: 6792 ixgbe_free_irq(adapter); 6793 err_req_irq: 6794 ixgbe_free_all_rx_resources(adapter); 6795 if (hw->phy.ops.set_phy_power && !adapter->wol) 6796 hw->phy.ops.set_phy_power(&adapter->hw, false); 6797 err_setup_rx: 6798 ixgbe_free_all_tx_resources(adapter); 6799 err_setup_tx: 6800 ixgbe_reset(adapter); 6801 6802 return err; 6803 } 6804 6805 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6806 { 6807 ixgbe_ptp_suspend(adapter); 6808 6809 if (adapter->hw.phy.ops.enter_lplu) { 6810 adapter->hw.phy.reset_disable = true; 6811 ixgbe_down(adapter); 6812 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6813 adapter->hw.phy.reset_disable = false; 6814 } else { 6815 ixgbe_down(adapter); 6816 } 6817 6818 ixgbe_free_irq(adapter); 6819 6820 ixgbe_free_all_tx_resources(adapter); 6821 ixgbe_free_all_rx_resources(adapter); 6822 } 6823 6824 /** 6825 * ixgbe_close - Disables a network interface 6826 * @netdev: network interface device structure 6827 * 6828 * Returns 0, this is not allowed to fail 6829 * 6830 * The close entry point is called when an interface is de-activated 6831 * by the OS. The hardware is still under the drivers control, but 6832 * needs to be disabled. A global MAC reset is issued to stop the 6833 * hardware, and all transmit and receive resources are freed. 6834 **/ 6835 int ixgbe_close(struct net_device *netdev) 6836 { 6837 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6838 6839 ixgbe_ptp_stop(adapter); 6840 6841 if (netif_device_present(netdev)) 6842 ixgbe_close_suspend(adapter); 6843 6844 ixgbe_fdir_filter_exit(adapter); 6845 6846 ixgbe_release_hw_control(adapter); 6847 6848 return 0; 6849 } 6850 6851 #ifdef CONFIG_PM 6852 static int ixgbe_resume(struct pci_dev *pdev) 6853 { 6854 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6855 struct net_device *netdev = adapter->netdev; 6856 u32 err; 6857 6858 adapter->hw.hw_addr = adapter->io_addr; 6859 pci_set_power_state(pdev, PCI_D0); 6860 pci_restore_state(pdev); 6861 /* 6862 * pci_restore_state clears dev->state_saved so call 6863 * pci_save_state to restore it. 6864 */ 6865 pci_save_state(pdev); 6866 6867 err = pci_enable_device_mem(pdev); 6868 if (err) { 6869 e_dev_err("Cannot enable PCI device from suspend\n"); 6870 return err; 6871 } 6872 smp_mb__before_atomic(); 6873 clear_bit(__IXGBE_DISABLED, &adapter->state); 6874 pci_set_master(pdev); 6875 6876 pci_wake_from_d3(pdev, false); 6877 6878 ixgbe_reset(adapter); 6879 6880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6881 6882 rtnl_lock(); 6883 err = ixgbe_init_interrupt_scheme(adapter); 6884 if (!err && netif_running(netdev)) 6885 err = ixgbe_open(netdev); 6886 6887 6888 if (!err) 6889 netif_device_attach(netdev); 6890 rtnl_unlock(); 6891 6892 return err; 6893 } 6894 #endif /* CONFIG_PM */ 6895 6896 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6897 { 6898 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6899 struct net_device *netdev = adapter->netdev; 6900 struct ixgbe_hw *hw = &adapter->hw; 6901 u32 ctrl; 6902 u32 wufc = adapter->wol; 6903 #ifdef CONFIG_PM 6904 int retval = 0; 6905 #endif 6906 6907 rtnl_lock(); 6908 netif_device_detach(netdev); 6909 6910 if (netif_running(netdev)) 6911 ixgbe_close_suspend(adapter); 6912 6913 ixgbe_clear_interrupt_scheme(adapter); 6914 rtnl_unlock(); 6915 6916 #ifdef CONFIG_PM 6917 retval = pci_save_state(pdev); 6918 if (retval) 6919 return retval; 6920 6921 #endif 6922 if (hw->mac.ops.stop_link_on_d3) 6923 hw->mac.ops.stop_link_on_d3(hw); 6924 6925 if (wufc) { 6926 u32 fctrl; 6927 6928 ixgbe_set_rx_mode(netdev); 6929 6930 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6931 if (hw->mac.ops.enable_tx_laser) 6932 hw->mac.ops.enable_tx_laser(hw); 6933 6934 /* enable the reception of multicast packets */ 6935 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6936 fctrl |= IXGBE_FCTRL_MPE; 6937 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6938 6939 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6940 ctrl |= IXGBE_CTRL_GIO_DIS; 6941 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6942 6943 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6944 } else { 6945 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6946 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6947 } 6948 6949 switch (hw->mac.type) { 6950 case ixgbe_mac_82598EB: 6951 pci_wake_from_d3(pdev, false); 6952 break; 6953 case ixgbe_mac_82599EB: 6954 case ixgbe_mac_X540: 6955 case ixgbe_mac_X550: 6956 case ixgbe_mac_X550EM_x: 6957 case ixgbe_mac_x550em_a: 6958 pci_wake_from_d3(pdev, !!wufc); 6959 break; 6960 default: 6961 break; 6962 } 6963 6964 *enable_wake = !!wufc; 6965 if (hw->phy.ops.set_phy_power && !*enable_wake) 6966 hw->phy.ops.set_phy_power(hw, false); 6967 6968 ixgbe_release_hw_control(adapter); 6969 6970 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6971 pci_disable_device(pdev); 6972 6973 return 0; 6974 } 6975 6976 #ifdef CONFIG_PM 6977 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6978 { 6979 int retval; 6980 bool wake; 6981 6982 retval = __ixgbe_shutdown(pdev, &wake); 6983 if (retval) 6984 return retval; 6985 6986 if (wake) { 6987 pci_prepare_to_sleep(pdev); 6988 } else { 6989 pci_wake_from_d3(pdev, false); 6990 pci_set_power_state(pdev, PCI_D3hot); 6991 } 6992 6993 return 0; 6994 } 6995 #endif /* CONFIG_PM */ 6996 6997 static void ixgbe_shutdown(struct pci_dev *pdev) 6998 { 6999 bool wake; 7000 7001 __ixgbe_shutdown(pdev, &wake); 7002 7003 if (system_state == SYSTEM_POWER_OFF) { 7004 pci_wake_from_d3(pdev, wake); 7005 pci_set_power_state(pdev, PCI_D3hot); 7006 } 7007 } 7008 7009 /** 7010 * ixgbe_update_stats - Update the board statistics counters. 7011 * @adapter: board private structure 7012 **/ 7013 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7014 { 7015 struct net_device *netdev = adapter->netdev; 7016 struct ixgbe_hw *hw = &adapter->hw; 7017 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7018 u64 total_mpc = 0; 7019 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7020 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7021 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7022 u64 alloc_rx_page = 0; 7023 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7024 7025 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7026 test_bit(__IXGBE_RESETTING, &adapter->state)) 7027 return; 7028 7029 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7030 u64 rsc_count = 0; 7031 u64 rsc_flush = 0; 7032 for (i = 0; i < adapter->num_rx_queues; i++) { 7033 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7034 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7035 } 7036 adapter->rsc_total_count = rsc_count; 7037 adapter->rsc_total_flush = rsc_flush; 7038 } 7039 7040 for (i = 0; i < adapter->num_rx_queues; i++) { 7041 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 7042 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7043 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7044 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7045 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7046 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7047 bytes += rx_ring->stats.bytes; 7048 packets += rx_ring->stats.packets; 7049 } 7050 adapter->non_eop_descs = non_eop_descs; 7051 adapter->alloc_rx_page = alloc_rx_page; 7052 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7053 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7054 adapter->hw_csum_rx_error = hw_csum_rx_error; 7055 netdev->stats.rx_bytes = bytes; 7056 netdev->stats.rx_packets = packets; 7057 7058 bytes = 0; 7059 packets = 0; 7060 /* gather some stats to the adapter struct that are per queue */ 7061 for (i = 0; i < adapter->num_tx_queues; i++) { 7062 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7063 restart_queue += tx_ring->tx_stats.restart_queue; 7064 tx_busy += tx_ring->tx_stats.tx_busy; 7065 bytes += tx_ring->stats.bytes; 7066 packets += tx_ring->stats.packets; 7067 } 7068 for (i = 0; i < adapter->num_xdp_queues; i++) { 7069 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 7070 7071 restart_queue += xdp_ring->tx_stats.restart_queue; 7072 tx_busy += xdp_ring->tx_stats.tx_busy; 7073 bytes += xdp_ring->stats.bytes; 7074 packets += xdp_ring->stats.packets; 7075 } 7076 adapter->restart_queue = restart_queue; 7077 adapter->tx_busy = tx_busy; 7078 netdev->stats.tx_bytes = bytes; 7079 netdev->stats.tx_packets = packets; 7080 7081 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7082 7083 /* 8 register reads */ 7084 for (i = 0; i < 8; i++) { 7085 /* for packet buffers not used, the register should read 0 */ 7086 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7087 missed_rx += mpc; 7088 hwstats->mpc[i] += mpc; 7089 total_mpc += hwstats->mpc[i]; 7090 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7091 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7092 switch (hw->mac.type) { 7093 case ixgbe_mac_82598EB: 7094 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7095 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7096 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7097 hwstats->pxonrxc[i] += 7098 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7099 break; 7100 case ixgbe_mac_82599EB: 7101 case ixgbe_mac_X540: 7102 case ixgbe_mac_X550: 7103 case ixgbe_mac_X550EM_x: 7104 case ixgbe_mac_x550em_a: 7105 hwstats->pxonrxc[i] += 7106 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7107 break; 7108 default: 7109 break; 7110 } 7111 } 7112 7113 /*16 register reads */ 7114 for (i = 0; i < 16; i++) { 7115 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7116 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7117 if ((hw->mac.type == ixgbe_mac_82599EB) || 7118 (hw->mac.type == ixgbe_mac_X540) || 7119 (hw->mac.type == ixgbe_mac_X550) || 7120 (hw->mac.type == ixgbe_mac_X550EM_x) || 7121 (hw->mac.type == ixgbe_mac_x550em_a)) { 7122 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7123 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7124 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7125 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7126 } 7127 } 7128 7129 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7130 /* work around hardware counting issue */ 7131 hwstats->gprc -= missed_rx; 7132 7133 ixgbe_update_xoff_received(adapter); 7134 7135 /* 82598 hardware only has a 32 bit counter in the high register */ 7136 switch (hw->mac.type) { 7137 case ixgbe_mac_82598EB: 7138 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7139 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7140 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7141 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7142 break; 7143 case ixgbe_mac_X540: 7144 case ixgbe_mac_X550: 7145 case ixgbe_mac_X550EM_x: 7146 case ixgbe_mac_x550em_a: 7147 /* OS2BMC stats are X540 and later */ 7148 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7149 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7150 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7151 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7152 /* fall through */ 7153 case ixgbe_mac_82599EB: 7154 for (i = 0; i < 16; i++) 7155 adapter->hw_rx_no_dma_resources += 7156 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7157 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7158 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7159 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7160 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7161 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7162 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7163 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7164 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7165 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7166 #ifdef IXGBE_FCOE 7167 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7168 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7169 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7170 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7171 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7172 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7173 /* Add up per cpu counters for total ddp aloc fail */ 7174 if (adapter->fcoe.ddp_pool) { 7175 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7176 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7177 unsigned int cpu; 7178 u64 noddp = 0, noddp_ext_buff = 0; 7179 for_each_possible_cpu(cpu) { 7180 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7181 noddp += ddp_pool->noddp; 7182 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7183 } 7184 hwstats->fcoe_noddp = noddp; 7185 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7186 } 7187 #endif /* IXGBE_FCOE */ 7188 break; 7189 default: 7190 break; 7191 } 7192 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7193 hwstats->bprc += bprc; 7194 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7195 if (hw->mac.type == ixgbe_mac_82598EB) 7196 hwstats->mprc -= bprc; 7197 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7198 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7199 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7200 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7201 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7202 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7203 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7204 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7205 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7206 hwstats->lxontxc += lxon; 7207 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7208 hwstats->lxofftxc += lxoff; 7209 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7210 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7211 /* 7212 * 82598 errata - tx of flow control packets is included in tx counters 7213 */ 7214 xon_off_tot = lxon + lxoff; 7215 hwstats->gptc -= xon_off_tot; 7216 hwstats->mptc -= xon_off_tot; 7217 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7218 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7219 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7220 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7221 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7222 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7223 hwstats->ptc64 -= xon_off_tot; 7224 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7225 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7226 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7227 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7228 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7229 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7230 7231 /* Fill out the OS statistics structure */ 7232 netdev->stats.multicast = hwstats->mprc; 7233 7234 /* Rx Errors */ 7235 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7236 netdev->stats.rx_dropped = 0; 7237 netdev->stats.rx_length_errors = hwstats->rlec; 7238 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7239 netdev->stats.rx_missed_errors = total_mpc; 7240 } 7241 7242 /** 7243 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7244 * @adapter: pointer to the device adapter structure 7245 **/ 7246 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7247 { 7248 struct ixgbe_hw *hw = &adapter->hw; 7249 int i; 7250 7251 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7252 return; 7253 7254 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7255 7256 /* if interface is down do nothing */ 7257 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7258 return; 7259 7260 /* do nothing if we are not using signature filters */ 7261 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7262 return; 7263 7264 adapter->fdir_overflow++; 7265 7266 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7267 for (i = 0; i < adapter->num_tx_queues; i++) 7268 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7269 &(adapter->tx_ring[i]->state)); 7270 for (i = 0; i < adapter->num_xdp_queues; i++) 7271 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7272 &adapter->xdp_ring[i]->state); 7273 /* re-enable flow director interrupts */ 7274 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7275 } else { 7276 e_err(probe, "failed to finish FDIR re-initialization, " 7277 "ignored adding FDIR ATR filters\n"); 7278 } 7279 } 7280 7281 /** 7282 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7283 * @adapter: pointer to the device adapter structure 7284 * 7285 * This function serves two purposes. First it strobes the interrupt lines 7286 * in order to make certain interrupts are occurring. Secondly it sets the 7287 * bits needed to check for TX hangs. As a result we should immediately 7288 * determine if a hang has occurred. 7289 */ 7290 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7291 { 7292 struct ixgbe_hw *hw = &adapter->hw; 7293 u64 eics = 0; 7294 int i; 7295 7296 /* If we're down, removing or resetting, just bail */ 7297 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7298 test_bit(__IXGBE_REMOVING, &adapter->state) || 7299 test_bit(__IXGBE_RESETTING, &adapter->state)) 7300 return; 7301 7302 /* Force detection of hung controller */ 7303 if (netif_carrier_ok(adapter->netdev)) { 7304 for (i = 0; i < adapter->num_tx_queues; i++) 7305 set_check_for_tx_hang(adapter->tx_ring[i]); 7306 for (i = 0; i < adapter->num_xdp_queues; i++) 7307 set_check_for_tx_hang(adapter->xdp_ring[i]); 7308 } 7309 7310 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7311 /* 7312 * for legacy and MSI interrupts don't set any bits 7313 * that are enabled for EIAM, because this operation 7314 * would set *both* EIMS and EICS for any bit in EIAM 7315 */ 7316 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7317 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7318 } else { 7319 /* get one bit for every active tx/rx interrupt vector */ 7320 for (i = 0; i < adapter->num_q_vectors; i++) { 7321 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7322 if (qv->rx.ring || qv->tx.ring) 7323 eics |= BIT_ULL(i); 7324 } 7325 } 7326 7327 /* Cause software interrupt to ensure rings are cleaned */ 7328 ixgbe_irq_rearm_queues(adapter, eics); 7329 } 7330 7331 /** 7332 * ixgbe_watchdog_update_link - update the link status 7333 * @adapter: pointer to the device adapter structure 7334 **/ 7335 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7336 { 7337 struct ixgbe_hw *hw = &adapter->hw; 7338 u32 link_speed = adapter->link_speed; 7339 bool link_up = adapter->link_up; 7340 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7341 7342 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7343 return; 7344 7345 if (hw->mac.ops.check_link) { 7346 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7347 } else { 7348 /* always assume link is up, if no check link function */ 7349 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7350 link_up = true; 7351 } 7352 7353 if (adapter->ixgbe_ieee_pfc) 7354 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7355 7356 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7357 hw->mac.ops.fc_enable(hw); 7358 ixgbe_set_rx_drop_en(adapter); 7359 } 7360 7361 if (link_up || 7362 time_after(jiffies, (adapter->link_check_timeout + 7363 IXGBE_TRY_LINK_TIMEOUT))) { 7364 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7365 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7366 IXGBE_WRITE_FLUSH(hw); 7367 } 7368 7369 adapter->link_up = link_up; 7370 adapter->link_speed = link_speed; 7371 } 7372 7373 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7374 { 7375 #ifdef CONFIG_IXGBE_DCB 7376 struct net_device *netdev = adapter->netdev; 7377 struct dcb_app app = { 7378 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7379 .protocol = 0, 7380 }; 7381 u8 up = 0; 7382 7383 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7384 up = dcb_ieee_getapp_mask(netdev, &app); 7385 7386 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7387 #endif 7388 } 7389 7390 /** 7391 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7392 * print link up message 7393 * @adapter: pointer to the device adapter structure 7394 **/ 7395 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7396 { 7397 struct net_device *netdev = adapter->netdev; 7398 struct ixgbe_hw *hw = &adapter->hw; 7399 u32 link_speed = adapter->link_speed; 7400 const char *speed_str; 7401 bool flow_rx, flow_tx; 7402 7403 /* only continue if link was previously down */ 7404 if (netif_carrier_ok(netdev)) 7405 return; 7406 7407 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7408 7409 switch (hw->mac.type) { 7410 case ixgbe_mac_82598EB: { 7411 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7412 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7413 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7414 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7415 } 7416 break; 7417 case ixgbe_mac_X540: 7418 case ixgbe_mac_X550: 7419 case ixgbe_mac_X550EM_x: 7420 case ixgbe_mac_x550em_a: 7421 case ixgbe_mac_82599EB: { 7422 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7423 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7424 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7425 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7426 } 7427 break; 7428 default: 7429 flow_tx = false; 7430 flow_rx = false; 7431 break; 7432 } 7433 7434 adapter->last_rx_ptp_check = jiffies; 7435 7436 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7437 ixgbe_ptp_start_cyclecounter(adapter); 7438 7439 switch (link_speed) { 7440 case IXGBE_LINK_SPEED_10GB_FULL: 7441 speed_str = "10 Gbps"; 7442 break; 7443 case IXGBE_LINK_SPEED_5GB_FULL: 7444 speed_str = "5 Gbps"; 7445 break; 7446 case IXGBE_LINK_SPEED_2_5GB_FULL: 7447 speed_str = "2.5 Gbps"; 7448 break; 7449 case IXGBE_LINK_SPEED_1GB_FULL: 7450 speed_str = "1 Gbps"; 7451 break; 7452 case IXGBE_LINK_SPEED_100_FULL: 7453 speed_str = "100 Mbps"; 7454 break; 7455 case IXGBE_LINK_SPEED_10_FULL: 7456 speed_str = "10 Mbps"; 7457 break; 7458 default: 7459 speed_str = "unknown speed"; 7460 break; 7461 } 7462 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7463 ((flow_rx && flow_tx) ? "RX/TX" : 7464 (flow_rx ? "RX" : 7465 (flow_tx ? "TX" : "None")))); 7466 7467 netif_carrier_on(netdev); 7468 ixgbe_check_vf_rate_limit(adapter); 7469 7470 /* enable transmits */ 7471 netif_tx_wake_all_queues(adapter->netdev); 7472 7473 /* update the default user priority for VFs */ 7474 ixgbe_update_default_up(adapter); 7475 7476 /* ping all the active vfs to let them know link has changed */ 7477 ixgbe_ping_all_vfs(adapter); 7478 } 7479 7480 /** 7481 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7482 * print link down message 7483 * @adapter: pointer to the adapter structure 7484 **/ 7485 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7486 { 7487 struct net_device *netdev = adapter->netdev; 7488 struct ixgbe_hw *hw = &adapter->hw; 7489 7490 adapter->link_up = false; 7491 adapter->link_speed = 0; 7492 7493 /* only continue if link was up previously */ 7494 if (!netif_carrier_ok(netdev)) 7495 return; 7496 7497 /* poll for SFP+ cable when link is down */ 7498 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7499 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7500 7501 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7502 ixgbe_ptp_start_cyclecounter(adapter); 7503 7504 e_info(drv, "NIC Link is Down\n"); 7505 netif_carrier_off(netdev); 7506 7507 /* ping all the active vfs to let them know link has changed */ 7508 ixgbe_ping_all_vfs(adapter); 7509 } 7510 7511 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7512 { 7513 int i; 7514 7515 for (i = 0; i < adapter->num_tx_queues; i++) { 7516 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7517 7518 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7519 return true; 7520 } 7521 7522 for (i = 0; i < adapter->num_xdp_queues; i++) { 7523 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7524 7525 if (ring->next_to_use != ring->next_to_clean) 7526 return true; 7527 } 7528 7529 return false; 7530 } 7531 7532 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7533 { 7534 struct ixgbe_hw *hw = &adapter->hw; 7535 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7536 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7537 7538 int i, j; 7539 7540 if (!adapter->num_vfs) 7541 return false; 7542 7543 /* resetting the PF is only needed for MAC before X550 */ 7544 if (hw->mac.type >= ixgbe_mac_X550) 7545 return false; 7546 7547 for (i = 0; i < adapter->num_vfs; i++) { 7548 for (j = 0; j < q_per_pool; j++) { 7549 u32 h, t; 7550 7551 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7552 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7553 7554 if (h != t) 7555 return true; 7556 } 7557 } 7558 7559 return false; 7560 } 7561 7562 /** 7563 * ixgbe_watchdog_flush_tx - flush queues on link down 7564 * @adapter: pointer to the device adapter structure 7565 **/ 7566 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7567 { 7568 if (!netif_carrier_ok(adapter->netdev)) { 7569 if (ixgbe_ring_tx_pending(adapter) || 7570 ixgbe_vf_tx_pending(adapter)) { 7571 /* We've lost link, so the controller stops DMA, 7572 * but we've got queued Tx work that's never going 7573 * to get done, so reset controller to flush Tx. 7574 * (Do the reset outside of interrupt context). 7575 */ 7576 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7577 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7578 } 7579 } 7580 } 7581 7582 #ifdef CONFIG_PCI_IOV 7583 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7584 { 7585 struct ixgbe_hw *hw = &adapter->hw; 7586 struct pci_dev *pdev = adapter->pdev; 7587 unsigned int vf; 7588 u32 gpc; 7589 7590 if (!(netif_carrier_ok(adapter->netdev))) 7591 return; 7592 7593 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7594 if (gpc) /* If incrementing then no need for the check below */ 7595 return; 7596 /* Check to see if a bad DMA write target from an errant or 7597 * malicious VF has caused a PCIe error. If so then we can 7598 * issue a VFLR to the offending VF(s) and then resume without 7599 * requesting a full slot reset. 7600 */ 7601 7602 if (!pdev) 7603 return; 7604 7605 /* check status reg for all VFs owned by this PF */ 7606 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7607 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7608 u16 status_reg; 7609 7610 if (!vfdev) 7611 continue; 7612 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7613 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7614 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7615 pcie_flr(vfdev); 7616 } 7617 } 7618 7619 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7620 { 7621 u32 ssvpc; 7622 7623 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7624 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7625 adapter->num_vfs == 0) 7626 return; 7627 7628 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7629 7630 /* 7631 * ssvpc register is cleared on read, if zero then no 7632 * spoofed packets in the last interval. 7633 */ 7634 if (!ssvpc) 7635 return; 7636 7637 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7638 } 7639 #else 7640 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7641 { 7642 } 7643 7644 static void 7645 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7646 { 7647 } 7648 #endif /* CONFIG_PCI_IOV */ 7649 7650 7651 /** 7652 * ixgbe_watchdog_subtask - check and bring link up 7653 * @adapter: pointer to the device adapter structure 7654 **/ 7655 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7656 { 7657 /* if interface is down, removing or resetting, do nothing */ 7658 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7659 test_bit(__IXGBE_REMOVING, &adapter->state) || 7660 test_bit(__IXGBE_RESETTING, &adapter->state)) 7661 return; 7662 7663 ixgbe_watchdog_update_link(adapter); 7664 7665 if (adapter->link_up) 7666 ixgbe_watchdog_link_is_up(adapter); 7667 else 7668 ixgbe_watchdog_link_is_down(adapter); 7669 7670 ixgbe_check_for_bad_vf(adapter); 7671 ixgbe_spoof_check(adapter); 7672 ixgbe_update_stats(adapter); 7673 7674 ixgbe_watchdog_flush_tx(adapter); 7675 } 7676 7677 /** 7678 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7679 * @adapter: the ixgbe adapter structure 7680 **/ 7681 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7682 { 7683 struct ixgbe_hw *hw = &adapter->hw; 7684 s32 err; 7685 7686 /* not searching for SFP so there is nothing to do here */ 7687 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7688 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7689 return; 7690 7691 if (adapter->sfp_poll_time && 7692 time_after(adapter->sfp_poll_time, jiffies)) 7693 return; /* If not yet time to poll for SFP */ 7694 7695 /* someone else is in init, wait until next service event */ 7696 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7697 return; 7698 7699 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7700 7701 err = hw->phy.ops.identify_sfp(hw); 7702 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7703 goto sfp_out; 7704 7705 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7706 /* If no cable is present, then we need to reset 7707 * the next time we find a good cable. */ 7708 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7709 } 7710 7711 /* exit on error */ 7712 if (err) 7713 goto sfp_out; 7714 7715 /* exit if reset not needed */ 7716 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7717 goto sfp_out; 7718 7719 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7720 7721 /* 7722 * A module may be identified correctly, but the EEPROM may not have 7723 * support for that module. setup_sfp() will fail in that case, so 7724 * we should not allow that module to load. 7725 */ 7726 if (hw->mac.type == ixgbe_mac_82598EB) 7727 err = hw->phy.ops.reset(hw); 7728 else 7729 err = hw->mac.ops.setup_sfp(hw); 7730 7731 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7732 goto sfp_out; 7733 7734 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7735 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7736 7737 sfp_out: 7738 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7739 7740 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7741 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7742 e_dev_err("failed to initialize because an unsupported " 7743 "SFP+ module type was detected.\n"); 7744 e_dev_err("Reload the driver after installing a " 7745 "supported module.\n"); 7746 unregister_netdev(adapter->netdev); 7747 } 7748 } 7749 7750 /** 7751 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7752 * @adapter: the ixgbe adapter structure 7753 **/ 7754 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7755 { 7756 struct ixgbe_hw *hw = &adapter->hw; 7757 u32 cap_speed; 7758 u32 speed; 7759 bool autoneg = false; 7760 7761 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7762 return; 7763 7764 /* someone else is in init, wait until next service event */ 7765 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7766 return; 7767 7768 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7769 7770 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7771 7772 /* advertise highest capable link speed */ 7773 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7774 speed = IXGBE_LINK_SPEED_10GB_FULL; 7775 else 7776 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7777 IXGBE_LINK_SPEED_1GB_FULL); 7778 7779 if (hw->mac.ops.setup_link) 7780 hw->mac.ops.setup_link(hw, speed, true); 7781 7782 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7783 adapter->link_check_timeout = jiffies; 7784 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7785 } 7786 7787 /** 7788 * ixgbe_service_timer - Timer Call-back 7789 * @t: pointer to timer_list structure 7790 **/ 7791 static void ixgbe_service_timer(struct timer_list *t) 7792 { 7793 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7794 unsigned long next_event_offset; 7795 7796 /* poll faster when waiting for link */ 7797 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7798 next_event_offset = HZ / 10; 7799 else 7800 next_event_offset = HZ * 2; 7801 7802 /* Reset the timer */ 7803 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7804 7805 ixgbe_service_event_schedule(adapter); 7806 } 7807 7808 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7809 { 7810 struct ixgbe_hw *hw = &adapter->hw; 7811 u32 status; 7812 7813 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7814 return; 7815 7816 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7817 7818 if (!hw->phy.ops.handle_lasi) 7819 return; 7820 7821 status = hw->phy.ops.handle_lasi(&adapter->hw); 7822 if (status != IXGBE_ERR_OVERTEMP) 7823 return; 7824 7825 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7826 } 7827 7828 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7829 { 7830 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7831 return; 7832 7833 rtnl_lock(); 7834 /* If we're already down, removing or resetting, just bail */ 7835 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7836 test_bit(__IXGBE_REMOVING, &adapter->state) || 7837 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7838 rtnl_unlock(); 7839 return; 7840 } 7841 7842 ixgbe_dump(adapter); 7843 netdev_err(adapter->netdev, "Reset adapter\n"); 7844 adapter->tx_timeout_count++; 7845 7846 ixgbe_reinit_locked(adapter); 7847 rtnl_unlock(); 7848 } 7849 7850 /** 7851 * ixgbe_check_fw_error - Check firmware for errors 7852 * @adapter: the adapter private structure 7853 * 7854 * Check firmware errors in register FWSM 7855 */ 7856 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7857 { 7858 struct ixgbe_hw *hw = &adapter->hw; 7859 u32 fwsm; 7860 7861 /* read fwsm.ext_err_ind register and log errors */ 7862 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7863 7864 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7865 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7866 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7867 fwsm); 7868 7869 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7870 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7871 return true; 7872 } 7873 7874 return false; 7875 } 7876 7877 /** 7878 * ixgbe_service_task - manages and runs subtasks 7879 * @work: pointer to work_struct containing our data 7880 **/ 7881 static void ixgbe_service_task(struct work_struct *work) 7882 { 7883 struct ixgbe_adapter *adapter = container_of(work, 7884 struct ixgbe_adapter, 7885 service_task); 7886 if (ixgbe_removed(adapter->hw.hw_addr)) { 7887 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7888 rtnl_lock(); 7889 ixgbe_down(adapter); 7890 rtnl_unlock(); 7891 } 7892 ixgbe_service_event_complete(adapter); 7893 return; 7894 } 7895 if (ixgbe_check_fw_error(adapter)) { 7896 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7897 rtnl_lock(); 7898 unregister_netdev(adapter->netdev); 7899 rtnl_unlock(); 7900 } 7901 ixgbe_service_event_complete(adapter); 7902 return; 7903 } 7904 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7905 rtnl_lock(); 7906 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7907 udp_tunnel_get_rx_info(adapter->netdev); 7908 rtnl_unlock(); 7909 } 7910 ixgbe_reset_subtask(adapter); 7911 ixgbe_phy_interrupt_subtask(adapter); 7912 ixgbe_sfp_detection_subtask(adapter); 7913 ixgbe_sfp_link_config_subtask(adapter); 7914 ixgbe_check_overtemp_subtask(adapter); 7915 ixgbe_watchdog_subtask(adapter); 7916 ixgbe_fdir_reinit_subtask(adapter); 7917 ixgbe_check_hang_subtask(adapter); 7918 7919 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7920 ixgbe_ptp_overflow_check(adapter); 7921 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7922 ixgbe_ptp_rx_hang(adapter); 7923 ixgbe_ptp_tx_hang(adapter); 7924 } 7925 7926 ixgbe_service_event_complete(adapter); 7927 } 7928 7929 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7930 struct ixgbe_tx_buffer *first, 7931 u8 *hdr_len, 7932 struct ixgbe_ipsec_tx_data *itd) 7933 { 7934 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7935 struct sk_buff *skb = first->skb; 7936 union { 7937 struct iphdr *v4; 7938 struct ipv6hdr *v6; 7939 unsigned char *hdr; 7940 } ip; 7941 union { 7942 struct tcphdr *tcp; 7943 unsigned char *hdr; 7944 } l4; 7945 u32 paylen, l4_offset; 7946 u32 fceof_saidx = 0; 7947 int err; 7948 7949 if (skb->ip_summed != CHECKSUM_PARTIAL) 7950 return 0; 7951 7952 if (!skb_is_gso(skb)) 7953 return 0; 7954 7955 err = skb_cow_head(skb, 0); 7956 if (err < 0) 7957 return err; 7958 7959 if (eth_p_mpls(first->protocol)) 7960 ip.hdr = skb_inner_network_header(skb); 7961 else 7962 ip.hdr = skb_network_header(skb); 7963 l4.hdr = skb_checksum_start(skb); 7964 7965 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7966 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7967 7968 /* initialize outer IP header fields */ 7969 if (ip.v4->version == 4) { 7970 unsigned char *csum_start = skb_checksum_start(skb); 7971 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7972 int len = csum_start - trans_start; 7973 7974 /* IP header will have to cancel out any data that 7975 * is not a part of the outer IP header, so set to 7976 * a reverse csum if needed, else init check to 0. 7977 */ 7978 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7979 csum_fold(csum_partial(trans_start, 7980 len, 0)) : 0; 7981 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7982 7983 ip.v4->tot_len = 0; 7984 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7985 IXGBE_TX_FLAGS_CSUM | 7986 IXGBE_TX_FLAGS_IPV4; 7987 } else { 7988 ip.v6->payload_len = 0; 7989 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7990 IXGBE_TX_FLAGS_CSUM; 7991 } 7992 7993 /* determine offset of inner transport header */ 7994 l4_offset = l4.hdr - skb->data; 7995 7996 /* compute length of segmentation header */ 7997 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7998 7999 /* remove payload length from inner checksum */ 8000 paylen = skb->len - l4_offset; 8001 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 8002 8003 /* update gso size and bytecount with header size */ 8004 first->gso_segs = skb_shinfo(skb)->gso_segs; 8005 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8006 8007 /* mss_l4len_id: use 0 as index for TSO */ 8008 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8009 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8010 8011 fceof_saidx |= itd->sa_idx; 8012 type_tucmd |= itd->flags | itd->trailer_len; 8013 8014 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8015 vlan_macip_lens = l4.hdr - ip.hdr; 8016 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8017 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8018 8019 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8020 mss_l4len_idx); 8021 8022 return 1; 8023 } 8024 8025 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 8026 { 8027 unsigned int offset = 0; 8028 8029 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 8030 8031 return offset == skb_checksum_start_offset(skb); 8032 } 8033 8034 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8035 struct ixgbe_tx_buffer *first, 8036 struct ixgbe_ipsec_tx_data *itd) 8037 { 8038 struct sk_buff *skb = first->skb; 8039 u32 vlan_macip_lens = 0; 8040 u32 fceof_saidx = 0; 8041 u32 type_tucmd = 0; 8042 8043 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8044 csum_failed: 8045 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8046 IXGBE_TX_FLAGS_CC))) 8047 return; 8048 goto no_csum; 8049 } 8050 8051 switch (skb->csum_offset) { 8052 case offsetof(struct tcphdr, check): 8053 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8054 /* fall through */ 8055 case offsetof(struct udphdr, check): 8056 break; 8057 case offsetof(struct sctphdr, checksum): 8058 /* validate that this is actually an SCTP request */ 8059 if (((first->protocol == htons(ETH_P_IP)) && 8060 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 8061 ((first->protocol == htons(ETH_P_IPV6)) && 8062 ixgbe_ipv6_csum_is_sctp(skb))) { 8063 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8064 break; 8065 } 8066 /* fall through */ 8067 default: 8068 skb_checksum_help(skb); 8069 goto csum_failed; 8070 } 8071 8072 /* update TX checksum flag */ 8073 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8074 vlan_macip_lens = skb_checksum_start_offset(skb) - 8075 skb_network_offset(skb); 8076 no_csum: 8077 /* vlan_macip_lens: MACLEN, VLAN tag */ 8078 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8079 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8080 8081 fceof_saidx |= itd->sa_idx; 8082 type_tucmd |= itd->flags | itd->trailer_len; 8083 8084 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8085 } 8086 8087 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8088 ((_flag <= _result) ? \ 8089 ((u32)(_input & _flag) * (_result / _flag)) : \ 8090 ((u32)(_input & _flag) / (_flag / _result))) 8091 8092 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8093 { 8094 /* set type for advanced descriptor with frame checksum insertion */ 8095 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8096 IXGBE_ADVTXD_DCMD_DEXT | 8097 IXGBE_ADVTXD_DCMD_IFCS; 8098 8099 /* set HW vlan bit if vlan is present */ 8100 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8101 IXGBE_ADVTXD_DCMD_VLE); 8102 8103 /* set segmentation enable bits for TSO/FSO */ 8104 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8105 IXGBE_ADVTXD_DCMD_TSE); 8106 8107 /* set timestamp bit if present */ 8108 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8109 IXGBE_ADVTXD_MAC_TSTAMP); 8110 8111 /* insert frame checksum */ 8112 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8113 8114 return cmd_type; 8115 } 8116 8117 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8118 u32 tx_flags, unsigned int paylen) 8119 { 8120 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8121 8122 /* enable L4 checksum for TSO and TX checksum offload */ 8123 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8124 IXGBE_TX_FLAGS_CSUM, 8125 IXGBE_ADVTXD_POPTS_TXSM); 8126 8127 /* enable IPv4 checksum for TSO */ 8128 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8129 IXGBE_TX_FLAGS_IPV4, 8130 IXGBE_ADVTXD_POPTS_IXSM); 8131 8132 /* enable IPsec */ 8133 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8134 IXGBE_TX_FLAGS_IPSEC, 8135 IXGBE_ADVTXD_POPTS_IPSEC); 8136 8137 /* 8138 * Check Context must be set if Tx switch is enabled, which it 8139 * always is for case where virtual functions are running 8140 */ 8141 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8142 IXGBE_TX_FLAGS_CC, 8143 IXGBE_ADVTXD_CC); 8144 8145 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8146 } 8147 8148 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8149 { 8150 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8151 8152 /* Herbert's original patch had: 8153 * smp_mb__after_netif_stop_queue(); 8154 * but since that doesn't exist yet, just open code it. 8155 */ 8156 smp_mb(); 8157 8158 /* We need to check again in a case another CPU has just 8159 * made room available. 8160 */ 8161 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8162 return -EBUSY; 8163 8164 /* A reprieve! - use start_queue because it doesn't call schedule */ 8165 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8166 ++tx_ring->tx_stats.restart_queue; 8167 return 0; 8168 } 8169 8170 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8171 { 8172 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8173 return 0; 8174 8175 return __ixgbe_maybe_stop_tx(tx_ring, size); 8176 } 8177 8178 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8179 struct ixgbe_tx_buffer *first, 8180 const u8 hdr_len) 8181 { 8182 struct sk_buff *skb = first->skb; 8183 struct ixgbe_tx_buffer *tx_buffer; 8184 union ixgbe_adv_tx_desc *tx_desc; 8185 struct skb_frag_struct *frag; 8186 dma_addr_t dma; 8187 unsigned int data_len, size; 8188 u32 tx_flags = first->tx_flags; 8189 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8190 u16 i = tx_ring->next_to_use; 8191 8192 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8193 8194 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8195 8196 size = skb_headlen(skb); 8197 data_len = skb->data_len; 8198 8199 #ifdef IXGBE_FCOE 8200 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8201 if (data_len < sizeof(struct fcoe_crc_eof)) { 8202 size -= sizeof(struct fcoe_crc_eof) - data_len; 8203 data_len = 0; 8204 } else { 8205 data_len -= sizeof(struct fcoe_crc_eof); 8206 } 8207 } 8208 8209 #endif 8210 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8211 8212 tx_buffer = first; 8213 8214 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8215 if (dma_mapping_error(tx_ring->dev, dma)) 8216 goto dma_error; 8217 8218 /* record length, and DMA address */ 8219 dma_unmap_len_set(tx_buffer, len, size); 8220 dma_unmap_addr_set(tx_buffer, dma, dma); 8221 8222 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8223 8224 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8225 tx_desc->read.cmd_type_len = 8226 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8227 8228 i++; 8229 tx_desc++; 8230 if (i == tx_ring->count) { 8231 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8232 i = 0; 8233 } 8234 tx_desc->read.olinfo_status = 0; 8235 8236 dma += IXGBE_MAX_DATA_PER_TXD; 8237 size -= IXGBE_MAX_DATA_PER_TXD; 8238 8239 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8240 } 8241 8242 if (likely(!data_len)) 8243 break; 8244 8245 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8246 8247 i++; 8248 tx_desc++; 8249 if (i == tx_ring->count) { 8250 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8251 i = 0; 8252 } 8253 tx_desc->read.olinfo_status = 0; 8254 8255 #ifdef IXGBE_FCOE 8256 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8257 #else 8258 size = skb_frag_size(frag); 8259 #endif 8260 data_len -= size; 8261 8262 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8263 DMA_TO_DEVICE); 8264 8265 tx_buffer = &tx_ring->tx_buffer_info[i]; 8266 } 8267 8268 /* write last descriptor with RS and EOP bits */ 8269 cmd_type |= size | IXGBE_TXD_CMD; 8270 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8271 8272 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8273 8274 /* set the timestamp */ 8275 first->time_stamp = jiffies; 8276 8277 skb_tx_timestamp(skb); 8278 8279 /* 8280 * Force memory writes to complete before letting h/w know there 8281 * are new descriptors to fetch. (Only applicable for weak-ordered 8282 * memory model archs, such as IA-64). 8283 * 8284 * We also need this memory barrier to make certain all of the 8285 * status bits have been updated before next_to_watch is written. 8286 */ 8287 wmb(); 8288 8289 /* set next_to_watch value indicating a packet is present */ 8290 first->next_to_watch = tx_desc; 8291 8292 i++; 8293 if (i == tx_ring->count) 8294 i = 0; 8295 8296 tx_ring->next_to_use = i; 8297 8298 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8299 8300 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8301 writel(i, tx_ring->tail); 8302 8303 /* we need this if more than one processor can write to our tail 8304 * at a time, it synchronizes IO on IA64/Altix systems 8305 */ 8306 mmiowb(); 8307 } 8308 8309 return 0; 8310 dma_error: 8311 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8312 8313 /* clear dma mappings for failed tx_buffer_info map */ 8314 for (;;) { 8315 tx_buffer = &tx_ring->tx_buffer_info[i]; 8316 if (dma_unmap_len(tx_buffer, len)) 8317 dma_unmap_page(tx_ring->dev, 8318 dma_unmap_addr(tx_buffer, dma), 8319 dma_unmap_len(tx_buffer, len), 8320 DMA_TO_DEVICE); 8321 dma_unmap_len_set(tx_buffer, len, 0); 8322 if (tx_buffer == first) 8323 break; 8324 if (i == 0) 8325 i += tx_ring->count; 8326 i--; 8327 } 8328 8329 dev_kfree_skb_any(first->skb); 8330 first->skb = NULL; 8331 8332 tx_ring->next_to_use = i; 8333 8334 return -1; 8335 } 8336 8337 static void ixgbe_atr(struct ixgbe_ring *ring, 8338 struct ixgbe_tx_buffer *first) 8339 { 8340 struct ixgbe_q_vector *q_vector = ring->q_vector; 8341 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8342 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8343 union { 8344 unsigned char *network; 8345 struct iphdr *ipv4; 8346 struct ipv6hdr *ipv6; 8347 } hdr; 8348 struct tcphdr *th; 8349 unsigned int hlen; 8350 struct sk_buff *skb; 8351 __be16 vlan_id; 8352 int l4_proto; 8353 8354 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8355 if (!q_vector) 8356 return; 8357 8358 /* do nothing if sampling is disabled */ 8359 if (!ring->atr_sample_rate) 8360 return; 8361 8362 ring->atr_count++; 8363 8364 /* currently only IPv4/IPv6 with TCP is supported */ 8365 if ((first->protocol != htons(ETH_P_IP)) && 8366 (first->protocol != htons(ETH_P_IPV6))) 8367 return; 8368 8369 /* snag network header to get L4 type and address */ 8370 skb = first->skb; 8371 hdr.network = skb_network_header(skb); 8372 if (unlikely(hdr.network <= skb->data)) 8373 return; 8374 if (skb->encapsulation && 8375 first->protocol == htons(ETH_P_IP) && 8376 hdr.ipv4->protocol == IPPROTO_UDP) { 8377 struct ixgbe_adapter *adapter = q_vector->adapter; 8378 8379 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8380 VXLAN_HEADROOM)) 8381 return; 8382 8383 /* verify the port is recognized as VXLAN */ 8384 if (adapter->vxlan_port && 8385 udp_hdr(skb)->dest == adapter->vxlan_port) 8386 hdr.network = skb_inner_network_header(skb); 8387 8388 if (adapter->geneve_port && 8389 udp_hdr(skb)->dest == adapter->geneve_port) 8390 hdr.network = skb_inner_network_header(skb); 8391 } 8392 8393 /* Make sure we have at least [minimum IPv4 header + TCP] 8394 * or [IPv6 header] bytes 8395 */ 8396 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8397 return; 8398 8399 /* Currently only IPv4/IPv6 with TCP is supported */ 8400 switch (hdr.ipv4->version) { 8401 case IPVERSION: 8402 /* access ihl as u8 to avoid unaligned access on ia64 */ 8403 hlen = (hdr.network[0] & 0x0F) << 2; 8404 l4_proto = hdr.ipv4->protocol; 8405 break; 8406 case 6: 8407 hlen = hdr.network - skb->data; 8408 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8409 hlen -= hdr.network - skb->data; 8410 break; 8411 default: 8412 return; 8413 } 8414 8415 if (l4_proto != IPPROTO_TCP) 8416 return; 8417 8418 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8419 hlen + sizeof(struct tcphdr))) 8420 return; 8421 8422 th = (struct tcphdr *)(hdr.network + hlen); 8423 8424 /* skip this packet since the socket is closing */ 8425 if (th->fin) 8426 return; 8427 8428 /* sample on all syn packets or once every atr sample count */ 8429 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8430 return; 8431 8432 /* reset sample count */ 8433 ring->atr_count = 0; 8434 8435 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8436 8437 /* 8438 * src and dst are inverted, think how the receiver sees them 8439 * 8440 * The input is broken into two sections, a non-compressed section 8441 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8442 * is XORed together and stored in the compressed dword. 8443 */ 8444 input.formatted.vlan_id = vlan_id; 8445 8446 /* 8447 * since src port and flex bytes occupy the same word XOR them together 8448 * and write the value to source port portion of compressed dword 8449 */ 8450 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8451 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8452 else 8453 common.port.src ^= th->dest ^ first->protocol; 8454 common.port.dst ^= th->source; 8455 8456 switch (hdr.ipv4->version) { 8457 case IPVERSION: 8458 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8459 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8460 break; 8461 case 6: 8462 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8463 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8464 hdr.ipv6->saddr.s6_addr32[1] ^ 8465 hdr.ipv6->saddr.s6_addr32[2] ^ 8466 hdr.ipv6->saddr.s6_addr32[3] ^ 8467 hdr.ipv6->daddr.s6_addr32[0] ^ 8468 hdr.ipv6->daddr.s6_addr32[1] ^ 8469 hdr.ipv6->daddr.s6_addr32[2] ^ 8470 hdr.ipv6->daddr.s6_addr32[3]; 8471 break; 8472 default: 8473 break; 8474 } 8475 8476 if (hdr.network != skb_network_header(skb)) 8477 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8478 8479 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8480 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8481 input, common, ring->queue_index); 8482 } 8483 8484 #ifdef IXGBE_FCOE 8485 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8486 struct net_device *sb_dev, 8487 select_queue_fallback_t fallback) 8488 { 8489 struct ixgbe_adapter *adapter; 8490 struct ixgbe_ring_feature *f; 8491 int txq; 8492 8493 if (sb_dev) { 8494 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8495 struct net_device *vdev = sb_dev; 8496 8497 txq = vdev->tc_to_txq[tc].offset; 8498 txq += reciprocal_scale(skb_get_hash(skb), 8499 vdev->tc_to_txq[tc].count); 8500 8501 return txq; 8502 } 8503 8504 /* 8505 * only execute the code below if protocol is FCoE 8506 * or FIP and we have FCoE enabled on the adapter 8507 */ 8508 switch (vlan_get_protocol(skb)) { 8509 case htons(ETH_P_FCOE): 8510 case htons(ETH_P_FIP): 8511 adapter = netdev_priv(dev); 8512 8513 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8514 break; 8515 /* fall through */ 8516 default: 8517 return fallback(dev, skb, sb_dev); 8518 } 8519 8520 f = &adapter->ring_feature[RING_F_FCOE]; 8521 8522 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8523 smp_processor_id(); 8524 8525 while (txq >= f->indices) 8526 txq -= f->indices; 8527 8528 return txq + f->offset; 8529 } 8530 8531 #endif 8532 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8533 struct xdp_frame *xdpf) 8534 { 8535 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8536 struct ixgbe_tx_buffer *tx_buffer; 8537 union ixgbe_adv_tx_desc *tx_desc; 8538 u32 len, cmd_type; 8539 dma_addr_t dma; 8540 u16 i; 8541 8542 len = xdpf->len; 8543 8544 if (unlikely(!ixgbe_desc_unused(ring))) 8545 return IXGBE_XDP_CONSUMED; 8546 8547 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8548 if (dma_mapping_error(ring->dev, dma)) 8549 return IXGBE_XDP_CONSUMED; 8550 8551 /* record the location of the first descriptor for this packet */ 8552 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8553 tx_buffer->bytecount = len; 8554 tx_buffer->gso_segs = 1; 8555 tx_buffer->protocol = 0; 8556 8557 i = ring->next_to_use; 8558 tx_desc = IXGBE_TX_DESC(ring, i); 8559 8560 dma_unmap_len_set(tx_buffer, len, len); 8561 dma_unmap_addr_set(tx_buffer, dma, dma); 8562 tx_buffer->xdpf = xdpf; 8563 8564 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8565 8566 /* put descriptor type bits */ 8567 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8568 IXGBE_ADVTXD_DCMD_DEXT | 8569 IXGBE_ADVTXD_DCMD_IFCS; 8570 cmd_type |= len | IXGBE_TXD_CMD; 8571 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8572 tx_desc->read.olinfo_status = 8573 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8574 8575 /* Avoid any potential race with xdp_xmit and cleanup */ 8576 smp_wmb(); 8577 8578 /* set next_to_watch value indicating a packet is present */ 8579 i++; 8580 if (i == ring->count) 8581 i = 0; 8582 8583 tx_buffer->next_to_watch = tx_desc; 8584 ring->next_to_use = i; 8585 8586 return IXGBE_XDP_TX; 8587 } 8588 8589 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8590 struct ixgbe_adapter *adapter, 8591 struct ixgbe_ring *tx_ring) 8592 { 8593 struct ixgbe_tx_buffer *first; 8594 int tso; 8595 u32 tx_flags = 0; 8596 unsigned short f; 8597 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8598 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8599 __be16 protocol = skb->protocol; 8600 u8 hdr_len = 0; 8601 8602 /* 8603 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8604 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8605 * + 2 desc gap to keep tail from touching head, 8606 * + 1 desc for context descriptor, 8607 * otherwise try next time 8608 */ 8609 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8610 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8611 8612 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8613 tx_ring->tx_stats.tx_busy++; 8614 return NETDEV_TX_BUSY; 8615 } 8616 8617 /* record the location of the first descriptor for this packet */ 8618 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8619 first->skb = skb; 8620 first->bytecount = skb->len; 8621 first->gso_segs = 1; 8622 8623 /* if we have a HW VLAN tag being added default to the HW one */ 8624 if (skb_vlan_tag_present(skb)) { 8625 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8626 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8627 /* else if it is a SW VLAN check the next protocol and store the tag */ 8628 } else if (protocol == htons(ETH_P_8021Q)) { 8629 struct vlan_hdr *vhdr, _vhdr; 8630 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8631 if (!vhdr) 8632 goto out_drop; 8633 8634 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8635 IXGBE_TX_FLAGS_VLAN_SHIFT; 8636 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8637 } 8638 protocol = vlan_get_protocol(skb); 8639 8640 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8641 adapter->ptp_clock) { 8642 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8643 &adapter->state)) { 8644 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8645 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8646 8647 /* schedule check for Tx timestamp */ 8648 adapter->ptp_tx_skb = skb_get(skb); 8649 adapter->ptp_tx_start = jiffies; 8650 schedule_work(&adapter->ptp_tx_work); 8651 } else { 8652 adapter->tx_hwtstamp_skipped++; 8653 } 8654 } 8655 8656 #ifdef CONFIG_PCI_IOV 8657 /* 8658 * Use the l2switch_enable flag - would be false if the DMA 8659 * Tx switch had been disabled. 8660 */ 8661 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8662 tx_flags |= IXGBE_TX_FLAGS_CC; 8663 8664 #endif 8665 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8666 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8667 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8668 (skb->priority != TC_PRIO_CONTROL))) { 8669 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8670 tx_flags |= (skb->priority & 0x7) << 8671 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8672 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8673 struct vlan_ethhdr *vhdr; 8674 8675 if (skb_cow_head(skb, 0)) 8676 goto out_drop; 8677 vhdr = (struct vlan_ethhdr *)skb->data; 8678 vhdr->h_vlan_TCI = htons(tx_flags >> 8679 IXGBE_TX_FLAGS_VLAN_SHIFT); 8680 } else { 8681 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8682 } 8683 } 8684 8685 /* record initial flags and protocol */ 8686 first->tx_flags = tx_flags; 8687 first->protocol = protocol; 8688 8689 #ifdef IXGBE_FCOE 8690 /* setup tx offload for FCoE */ 8691 if ((protocol == htons(ETH_P_FCOE)) && 8692 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8693 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8694 if (tso < 0) 8695 goto out_drop; 8696 8697 goto xmit_fcoe; 8698 } 8699 8700 #endif /* IXGBE_FCOE */ 8701 8702 #ifdef CONFIG_IXGBE_IPSEC 8703 if (secpath_exists(skb) && 8704 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8705 goto out_drop; 8706 #endif 8707 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8708 if (tso < 0) 8709 goto out_drop; 8710 else if (!tso) 8711 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8712 8713 /* add the ATR filter if ATR is on */ 8714 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8715 ixgbe_atr(tx_ring, first); 8716 8717 #ifdef IXGBE_FCOE 8718 xmit_fcoe: 8719 #endif /* IXGBE_FCOE */ 8720 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8721 goto cleanup_tx_timestamp; 8722 8723 return NETDEV_TX_OK; 8724 8725 out_drop: 8726 dev_kfree_skb_any(first->skb); 8727 first->skb = NULL; 8728 cleanup_tx_timestamp: 8729 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8730 dev_kfree_skb_any(adapter->ptp_tx_skb); 8731 adapter->ptp_tx_skb = NULL; 8732 cancel_work_sync(&adapter->ptp_tx_work); 8733 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8734 } 8735 8736 return NETDEV_TX_OK; 8737 } 8738 8739 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8740 struct net_device *netdev, 8741 struct ixgbe_ring *ring) 8742 { 8743 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8744 struct ixgbe_ring *tx_ring; 8745 8746 /* 8747 * The minimum packet size for olinfo paylen is 17 so pad the skb 8748 * in order to meet this minimum size requirement. 8749 */ 8750 if (skb_put_padto(skb, 17)) 8751 return NETDEV_TX_OK; 8752 8753 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8754 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8755 return NETDEV_TX_BUSY; 8756 8757 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8758 } 8759 8760 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8761 struct net_device *netdev) 8762 { 8763 return __ixgbe_xmit_frame(skb, netdev, NULL); 8764 } 8765 8766 /** 8767 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8768 * @netdev: network interface device structure 8769 * @p: pointer to an address structure 8770 * 8771 * Returns 0 on success, negative on failure 8772 **/ 8773 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8774 { 8775 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8776 struct ixgbe_hw *hw = &adapter->hw; 8777 struct sockaddr *addr = p; 8778 8779 if (!is_valid_ether_addr(addr->sa_data)) 8780 return -EADDRNOTAVAIL; 8781 8782 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8783 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8784 8785 ixgbe_mac_set_default_filter(adapter); 8786 8787 return 0; 8788 } 8789 8790 static int 8791 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8792 { 8793 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8794 struct ixgbe_hw *hw = &adapter->hw; 8795 u16 value; 8796 int rc; 8797 8798 if (adapter->mii_bus) { 8799 int regnum = addr; 8800 8801 if (devad != MDIO_DEVAD_NONE) 8802 regnum |= (devad << 16) | MII_ADDR_C45; 8803 8804 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8805 } 8806 8807 if (prtad != hw->phy.mdio.prtad) 8808 return -EINVAL; 8809 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8810 if (!rc) 8811 rc = value; 8812 return rc; 8813 } 8814 8815 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8816 u16 addr, u16 value) 8817 { 8818 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8819 struct ixgbe_hw *hw = &adapter->hw; 8820 8821 if (adapter->mii_bus) { 8822 int regnum = addr; 8823 8824 if (devad != MDIO_DEVAD_NONE) 8825 regnum |= (devad << 16) | MII_ADDR_C45; 8826 8827 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8828 } 8829 8830 if (prtad != hw->phy.mdio.prtad) 8831 return -EINVAL; 8832 return hw->phy.ops.write_reg(hw, addr, devad, value); 8833 } 8834 8835 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8836 { 8837 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8838 8839 switch (cmd) { 8840 case SIOCSHWTSTAMP: 8841 return ixgbe_ptp_set_ts_config(adapter, req); 8842 case SIOCGHWTSTAMP: 8843 return ixgbe_ptp_get_ts_config(adapter, req); 8844 case SIOCGMIIPHY: 8845 if (!adapter->hw.phy.ops.read_reg) 8846 return -EOPNOTSUPP; 8847 /* fall through */ 8848 default: 8849 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8850 } 8851 } 8852 8853 /** 8854 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8855 * netdev->dev_addrs 8856 * @dev: network interface device structure 8857 * 8858 * Returns non-zero on failure 8859 **/ 8860 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8861 { 8862 int err = 0; 8863 struct ixgbe_adapter *adapter = netdev_priv(dev); 8864 struct ixgbe_hw *hw = &adapter->hw; 8865 8866 if (is_valid_ether_addr(hw->mac.san_addr)) { 8867 rtnl_lock(); 8868 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8869 rtnl_unlock(); 8870 8871 /* update SAN MAC vmdq pool selection */ 8872 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8873 } 8874 return err; 8875 } 8876 8877 /** 8878 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8879 * netdev->dev_addrs 8880 * @dev: network interface device structure 8881 * 8882 * Returns non-zero on failure 8883 **/ 8884 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8885 { 8886 int err = 0; 8887 struct ixgbe_adapter *adapter = netdev_priv(dev); 8888 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8889 8890 if (is_valid_ether_addr(mac->san_addr)) { 8891 rtnl_lock(); 8892 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8893 rtnl_unlock(); 8894 } 8895 return err; 8896 } 8897 8898 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8899 struct ixgbe_ring *ring) 8900 { 8901 u64 bytes, packets; 8902 unsigned int start; 8903 8904 if (ring) { 8905 do { 8906 start = u64_stats_fetch_begin_irq(&ring->syncp); 8907 packets = ring->stats.packets; 8908 bytes = ring->stats.bytes; 8909 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8910 stats->tx_packets += packets; 8911 stats->tx_bytes += bytes; 8912 } 8913 } 8914 8915 static void ixgbe_get_stats64(struct net_device *netdev, 8916 struct rtnl_link_stats64 *stats) 8917 { 8918 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8919 int i; 8920 8921 rcu_read_lock(); 8922 for (i = 0; i < adapter->num_rx_queues; i++) { 8923 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8924 u64 bytes, packets; 8925 unsigned int start; 8926 8927 if (ring) { 8928 do { 8929 start = u64_stats_fetch_begin_irq(&ring->syncp); 8930 packets = ring->stats.packets; 8931 bytes = ring->stats.bytes; 8932 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8933 stats->rx_packets += packets; 8934 stats->rx_bytes += bytes; 8935 } 8936 } 8937 8938 for (i = 0; i < adapter->num_tx_queues; i++) { 8939 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8940 8941 ixgbe_get_ring_stats64(stats, ring); 8942 } 8943 for (i = 0; i < adapter->num_xdp_queues; i++) { 8944 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8945 8946 ixgbe_get_ring_stats64(stats, ring); 8947 } 8948 rcu_read_unlock(); 8949 8950 /* following stats updated by ixgbe_watchdog_task() */ 8951 stats->multicast = netdev->stats.multicast; 8952 stats->rx_errors = netdev->stats.rx_errors; 8953 stats->rx_length_errors = netdev->stats.rx_length_errors; 8954 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8955 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8956 } 8957 8958 #ifdef CONFIG_IXGBE_DCB 8959 /** 8960 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8961 * @adapter: pointer to ixgbe_adapter 8962 * @tc: number of traffic classes currently enabled 8963 * 8964 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8965 * 802.1Q priority maps to a packet buffer that exists. 8966 */ 8967 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8968 { 8969 struct ixgbe_hw *hw = &adapter->hw; 8970 u32 reg, rsave; 8971 int i; 8972 8973 /* 82598 have a static priority to TC mapping that can not 8974 * be changed so no validation is needed. 8975 */ 8976 if (hw->mac.type == ixgbe_mac_82598EB) 8977 return; 8978 8979 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8980 rsave = reg; 8981 8982 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8983 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8984 8985 /* If up2tc is out of bounds default to zero */ 8986 if (up2tc > tc) 8987 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8988 } 8989 8990 if (reg != rsave) 8991 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8992 8993 return; 8994 } 8995 8996 /** 8997 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8998 * @adapter: Pointer to adapter struct 8999 * 9000 * Populate the netdev user priority to tc map 9001 */ 9002 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9003 { 9004 struct net_device *dev = adapter->netdev; 9005 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9006 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9007 u8 prio; 9008 9009 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9010 u8 tc = 0; 9011 9012 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9013 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9014 else if (ets) 9015 tc = ets->prio_tc[prio]; 9016 9017 netdev_set_prio_tc_map(dev, prio, tc); 9018 } 9019 } 9020 9021 #endif /* CONFIG_IXGBE_DCB */ 9022 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data) 9023 { 9024 struct ixgbe_adapter *adapter = data; 9025 struct ixgbe_fwd_adapter *accel; 9026 int pool; 9027 9028 /* we only care about macvlans... */ 9029 if (!netif_is_macvlan(vdev)) 9030 return 0; 9031 9032 /* that have hardware offload enabled... */ 9033 accel = macvlan_accel_priv(vdev); 9034 if (!accel) 9035 return 0; 9036 9037 /* If we can relocate to a different bit do so */ 9038 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9039 if (pool < adapter->num_rx_pools) { 9040 set_bit(pool, adapter->fwd_bitmask); 9041 accel->pool = pool; 9042 return 0; 9043 } 9044 9045 /* if we cannot find a free pool then disable the offload */ 9046 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9047 macvlan_release_l2fw_offload(vdev); 9048 9049 /* unbind the queues and drop the subordinate channel config */ 9050 netdev_unbind_sb_channel(adapter->netdev, vdev); 9051 netdev_set_sb_channel(vdev, 0); 9052 9053 kfree(accel); 9054 9055 return 0; 9056 } 9057 9058 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9059 { 9060 struct ixgbe_adapter *adapter = netdev_priv(dev); 9061 9062 /* flush any stale bits out of the fwd bitmask */ 9063 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9064 9065 /* walk through upper devices reassigning pools */ 9066 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9067 adapter); 9068 } 9069 9070 /** 9071 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9072 * 9073 * @dev: net device to configure 9074 * @tc: number of traffic classes to enable 9075 */ 9076 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9077 { 9078 struct ixgbe_adapter *adapter = netdev_priv(dev); 9079 struct ixgbe_hw *hw = &adapter->hw; 9080 9081 /* Hardware supports up to 8 traffic classes */ 9082 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9083 return -EINVAL; 9084 9085 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9086 return -EINVAL; 9087 9088 /* Hardware has to reinitialize queues and interrupts to 9089 * match packet buffer alignment. Unfortunately, the 9090 * hardware is not flexible enough to do this dynamically. 9091 */ 9092 if (netif_running(dev)) 9093 ixgbe_close(dev); 9094 else 9095 ixgbe_reset(adapter); 9096 9097 ixgbe_clear_interrupt_scheme(adapter); 9098 9099 #ifdef CONFIG_IXGBE_DCB 9100 if (tc) { 9101 if (adapter->xdp_prog) { 9102 e_warn(probe, "DCB is not supported with XDP\n"); 9103 9104 ixgbe_init_interrupt_scheme(adapter); 9105 if (netif_running(dev)) 9106 ixgbe_open(dev); 9107 return -EINVAL; 9108 } 9109 9110 netdev_set_num_tc(dev, tc); 9111 ixgbe_set_prio_tc_map(adapter); 9112 9113 adapter->hw_tcs = tc; 9114 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9115 9116 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9117 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9118 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9119 } 9120 } else { 9121 netdev_reset_tc(dev); 9122 9123 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9124 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9125 9126 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9127 adapter->hw_tcs = tc; 9128 9129 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9130 adapter->dcb_cfg.pfc_mode_enable = false; 9131 } 9132 9133 ixgbe_validate_rtr(adapter, tc); 9134 9135 #endif /* CONFIG_IXGBE_DCB */ 9136 ixgbe_init_interrupt_scheme(adapter); 9137 9138 ixgbe_defrag_macvlan_pools(dev); 9139 9140 if (netif_running(dev)) 9141 return ixgbe_open(dev); 9142 9143 return 0; 9144 } 9145 9146 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9147 struct tc_cls_u32_offload *cls) 9148 { 9149 u32 hdl = cls->knode.handle; 9150 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9151 u32 loc = cls->knode.handle & 0xfffff; 9152 int err = 0, i, j; 9153 struct ixgbe_jump_table *jump = NULL; 9154 9155 if (loc > IXGBE_MAX_HW_ENTRIES) 9156 return -EINVAL; 9157 9158 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9159 return -EINVAL; 9160 9161 /* Clear this filter in the link data it is associated with */ 9162 if (uhtid != 0x800) { 9163 jump = adapter->jump_tables[uhtid]; 9164 if (!jump) 9165 return -EINVAL; 9166 if (!test_bit(loc - 1, jump->child_loc_map)) 9167 return -EINVAL; 9168 clear_bit(loc - 1, jump->child_loc_map); 9169 } 9170 9171 /* Check if the filter being deleted is a link */ 9172 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9173 jump = adapter->jump_tables[i]; 9174 if (jump && jump->link_hdl == hdl) { 9175 /* Delete filters in the hardware in the child hash 9176 * table associated with this link 9177 */ 9178 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9179 if (!test_bit(j, jump->child_loc_map)) 9180 continue; 9181 spin_lock(&adapter->fdir_perfect_lock); 9182 err = ixgbe_update_ethtool_fdir_entry(adapter, 9183 NULL, 9184 j + 1); 9185 spin_unlock(&adapter->fdir_perfect_lock); 9186 clear_bit(j, jump->child_loc_map); 9187 } 9188 /* Remove resources for this link */ 9189 kfree(jump->input); 9190 kfree(jump->mask); 9191 kfree(jump); 9192 adapter->jump_tables[i] = NULL; 9193 return err; 9194 } 9195 } 9196 9197 spin_lock(&adapter->fdir_perfect_lock); 9198 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9199 spin_unlock(&adapter->fdir_perfect_lock); 9200 return err; 9201 } 9202 9203 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9204 struct tc_cls_u32_offload *cls) 9205 { 9206 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9207 9208 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9209 return -EINVAL; 9210 9211 /* This ixgbe devices do not support hash tables at the moment 9212 * so abort when given hash tables. 9213 */ 9214 if (cls->hnode.divisor > 0) 9215 return -EINVAL; 9216 9217 set_bit(uhtid - 1, &adapter->tables); 9218 return 0; 9219 } 9220 9221 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9222 struct tc_cls_u32_offload *cls) 9223 { 9224 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9225 9226 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9227 return -EINVAL; 9228 9229 clear_bit(uhtid - 1, &adapter->tables); 9230 return 0; 9231 } 9232 9233 #ifdef CONFIG_NET_CLS_ACT 9234 struct upper_walk_data { 9235 struct ixgbe_adapter *adapter; 9236 u64 action; 9237 int ifindex; 9238 u8 queue; 9239 }; 9240 9241 static int get_macvlan_queue(struct net_device *upper, void *_data) 9242 { 9243 if (netif_is_macvlan(upper)) { 9244 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9245 struct upper_walk_data *data = _data; 9246 struct ixgbe_adapter *adapter = data->adapter; 9247 int ifindex = data->ifindex; 9248 9249 if (vadapter && upper->ifindex == ifindex) { 9250 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9251 data->action = data->queue; 9252 return 1; 9253 } 9254 } 9255 9256 return 0; 9257 } 9258 9259 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9260 u8 *queue, u64 *action) 9261 { 9262 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9263 unsigned int num_vfs = adapter->num_vfs, vf; 9264 struct upper_walk_data data; 9265 struct net_device *upper; 9266 9267 /* redirect to a SRIOV VF */ 9268 for (vf = 0; vf < num_vfs; ++vf) { 9269 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9270 if (upper->ifindex == ifindex) { 9271 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9272 *action = vf + 1; 9273 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9274 return 0; 9275 } 9276 } 9277 9278 /* redirect to a offloaded macvlan netdev */ 9279 data.adapter = adapter; 9280 data.ifindex = ifindex; 9281 data.action = 0; 9282 data.queue = 0; 9283 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9284 get_macvlan_queue, &data)) { 9285 *action = data.action; 9286 *queue = data.queue; 9287 9288 return 0; 9289 } 9290 9291 return -EINVAL; 9292 } 9293 9294 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9295 struct tcf_exts *exts, u64 *action, u8 *queue) 9296 { 9297 const struct tc_action *a; 9298 int i; 9299 9300 if (!tcf_exts_has_actions(exts)) 9301 return -EINVAL; 9302 9303 tcf_exts_for_each_action(i, a, exts) { 9304 /* Drop action */ 9305 if (is_tcf_gact_shot(a)) { 9306 *action = IXGBE_FDIR_DROP_QUEUE; 9307 *queue = IXGBE_FDIR_DROP_QUEUE; 9308 return 0; 9309 } 9310 9311 /* Redirect to a VF or a offloaded macvlan */ 9312 if (is_tcf_mirred_egress_redirect(a)) { 9313 struct net_device *dev = tcf_mirred_dev(a); 9314 9315 if (!dev) 9316 return -EINVAL; 9317 return handle_redirect_action(adapter, dev->ifindex, 9318 queue, action); 9319 } 9320 9321 return -EINVAL; 9322 } 9323 9324 return -EINVAL; 9325 } 9326 #else 9327 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9328 struct tcf_exts *exts, u64 *action, u8 *queue) 9329 { 9330 return -EINVAL; 9331 } 9332 #endif /* CONFIG_NET_CLS_ACT */ 9333 9334 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9335 union ixgbe_atr_input *mask, 9336 struct tc_cls_u32_offload *cls, 9337 struct ixgbe_mat_field *field_ptr, 9338 struct ixgbe_nexthdr *nexthdr) 9339 { 9340 int i, j, off; 9341 __be32 val, m; 9342 bool found_entry = false, found_jump_field = false; 9343 9344 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9345 off = cls->knode.sel->keys[i].off; 9346 val = cls->knode.sel->keys[i].val; 9347 m = cls->knode.sel->keys[i].mask; 9348 9349 for (j = 0; field_ptr[j].val; j++) { 9350 if (field_ptr[j].off == off) { 9351 field_ptr[j].val(input, mask, (__force u32)val, 9352 (__force u32)m); 9353 input->filter.formatted.flow_type |= 9354 field_ptr[j].type; 9355 found_entry = true; 9356 break; 9357 } 9358 } 9359 if (nexthdr) { 9360 if (nexthdr->off == cls->knode.sel->keys[i].off && 9361 nexthdr->val == 9362 (__force u32)cls->knode.sel->keys[i].val && 9363 nexthdr->mask == 9364 (__force u32)cls->knode.sel->keys[i].mask) 9365 found_jump_field = true; 9366 else 9367 continue; 9368 } 9369 } 9370 9371 if (nexthdr && !found_jump_field) 9372 return -EINVAL; 9373 9374 if (!found_entry) 9375 return 0; 9376 9377 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9378 IXGBE_ATR_L4TYPE_MASK; 9379 9380 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9381 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9382 9383 return 0; 9384 } 9385 9386 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9387 struct tc_cls_u32_offload *cls) 9388 { 9389 __be16 protocol = cls->common.protocol; 9390 u32 loc = cls->knode.handle & 0xfffff; 9391 struct ixgbe_hw *hw = &adapter->hw; 9392 struct ixgbe_mat_field *field_ptr; 9393 struct ixgbe_fdir_filter *input = NULL; 9394 union ixgbe_atr_input *mask = NULL; 9395 struct ixgbe_jump_table *jump = NULL; 9396 int i, err = -EINVAL; 9397 u8 queue; 9398 u32 uhtid, link_uhtid; 9399 9400 uhtid = TC_U32_USERHTID(cls->knode.handle); 9401 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9402 9403 /* At the moment cls_u32 jumps to network layer and skips past 9404 * L2 headers. The canonical method to match L2 frames is to use 9405 * negative values. However this is error prone at best but really 9406 * just broken because there is no way to "know" what sort of hdr 9407 * is in front of the network layer. Fix cls_u32 to support L2 9408 * headers when needed. 9409 */ 9410 if (protocol != htons(ETH_P_IP)) 9411 return err; 9412 9413 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9414 e_err(drv, "Location out of range\n"); 9415 return err; 9416 } 9417 9418 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9419 * links and also the fields used to advance the parser across each 9420 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9421 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9422 * To add support for new nodes update ixgbe_model.h parse structures 9423 * this function _should_ be generic try not to hardcode values here. 9424 */ 9425 if (uhtid == 0x800) { 9426 field_ptr = (adapter->jump_tables[0])->mat; 9427 } else { 9428 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9429 return err; 9430 if (!adapter->jump_tables[uhtid]) 9431 return err; 9432 field_ptr = (adapter->jump_tables[uhtid])->mat; 9433 } 9434 9435 if (!field_ptr) 9436 return err; 9437 9438 /* At this point we know the field_ptr is valid and need to either 9439 * build cls_u32 link or attach filter. Because adding a link to 9440 * a handle that does not exist is invalid and the same for adding 9441 * rules to handles that don't exist. 9442 */ 9443 9444 if (link_uhtid) { 9445 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9446 9447 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9448 return err; 9449 9450 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9451 return err; 9452 9453 /* Multiple filters as links to the same hash table are not 9454 * supported. To add a new filter with the same next header 9455 * but different match/jump conditions, create a new hash table 9456 * and link to it. 9457 */ 9458 if (adapter->jump_tables[link_uhtid] && 9459 (adapter->jump_tables[link_uhtid])->link_hdl) { 9460 e_err(drv, "Link filter exists for link: %x\n", 9461 link_uhtid); 9462 return err; 9463 } 9464 9465 for (i = 0; nexthdr[i].jump; i++) { 9466 if (nexthdr[i].o != cls->knode.sel->offoff || 9467 nexthdr[i].s != cls->knode.sel->offshift || 9468 nexthdr[i].m != 9469 (__force u32)cls->knode.sel->offmask) 9470 return err; 9471 9472 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9473 if (!jump) 9474 return -ENOMEM; 9475 input = kzalloc(sizeof(*input), GFP_KERNEL); 9476 if (!input) { 9477 err = -ENOMEM; 9478 goto free_jump; 9479 } 9480 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9481 if (!mask) { 9482 err = -ENOMEM; 9483 goto free_input; 9484 } 9485 jump->input = input; 9486 jump->mask = mask; 9487 jump->link_hdl = cls->knode.handle; 9488 9489 err = ixgbe_clsu32_build_input(input, mask, cls, 9490 field_ptr, &nexthdr[i]); 9491 if (!err) { 9492 jump->mat = nexthdr[i].jump; 9493 adapter->jump_tables[link_uhtid] = jump; 9494 break; 9495 } 9496 } 9497 return 0; 9498 } 9499 9500 input = kzalloc(sizeof(*input), GFP_KERNEL); 9501 if (!input) 9502 return -ENOMEM; 9503 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9504 if (!mask) { 9505 err = -ENOMEM; 9506 goto free_input; 9507 } 9508 9509 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9510 if ((adapter->jump_tables[uhtid])->input) 9511 memcpy(input, (adapter->jump_tables[uhtid])->input, 9512 sizeof(*input)); 9513 if ((adapter->jump_tables[uhtid])->mask) 9514 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9515 sizeof(*mask)); 9516 9517 /* Lookup in all child hash tables if this location is already 9518 * filled with a filter 9519 */ 9520 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9521 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9522 9523 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9524 e_err(drv, "Filter exists in location: %x\n", 9525 loc); 9526 err = -EINVAL; 9527 goto err_out; 9528 } 9529 } 9530 } 9531 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9532 if (err) 9533 goto err_out; 9534 9535 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9536 &queue); 9537 if (err < 0) 9538 goto err_out; 9539 9540 input->sw_idx = loc; 9541 9542 spin_lock(&adapter->fdir_perfect_lock); 9543 9544 if (hlist_empty(&adapter->fdir_filter_list)) { 9545 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9546 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9547 if (err) 9548 goto err_out_w_lock; 9549 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9550 err = -EINVAL; 9551 goto err_out_w_lock; 9552 } 9553 9554 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9555 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9556 input->sw_idx, queue); 9557 if (!err) 9558 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9559 spin_unlock(&adapter->fdir_perfect_lock); 9560 9561 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9562 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9563 9564 kfree(mask); 9565 return err; 9566 err_out_w_lock: 9567 spin_unlock(&adapter->fdir_perfect_lock); 9568 err_out: 9569 kfree(mask); 9570 free_input: 9571 kfree(input); 9572 free_jump: 9573 kfree(jump); 9574 return err; 9575 } 9576 9577 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9578 struct tc_cls_u32_offload *cls_u32) 9579 { 9580 switch (cls_u32->command) { 9581 case TC_CLSU32_NEW_KNODE: 9582 case TC_CLSU32_REPLACE_KNODE: 9583 return ixgbe_configure_clsu32(adapter, cls_u32); 9584 case TC_CLSU32_DELETE_KNODE: 9585 return ixgbe_delete_clsu32(adapter, cls_u32); 9586 case TC_CLSU32_NEW_HNODE: 9587 case TC_CLSU32_REPLACE_HNODE: 9588 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9589 case TC_CLSU32_DELETE_HNODE: 9590 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9591 default: 9592 return -EOPNOTSUPP; 9593 } 9594 } 9595 9596 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9597 void *cb_priv) 9598 { 9599 struct ixgbe_adapter *adapter = cb_priv; 9600 9601 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9602 return -EOPNOTSUPP; 9603 9604 switch (type) { 9605 case TC_SETUP_CLSU32: 9606 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9607 default: 9608 return -EOPNOTSUPP; 9609 } 9610 } 9611 9612 static int ixgbe_setup_tc_block(struct net_device *dev, 9613 struct tc_block_offload *f) 9614 { 9615 struct ixgbe_adapter *adapter = netdev_priv(dev); 9616 9617 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9618 return -EOPNOTSUPP; 9619 9620 switch (f->command) { 9621 case TC_BLOCK_BIND: 9622 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9623 adapter, adapter, f->extack); 9624 case TC_BLOCK_UNBIND: 9625 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9626 adapter); 9627 return 0; 9628 default: 9629 return -EOPNOTSUPP; 9630 } 9631 } 9632 9633 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9634 struct tc_mqprio_qopt *mqprio) 9635 { 9636 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9637 return ixgbe_setup_tc(dev, mqprio->num_tc); 9638 } 9639 9640 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9641 void *type_data) 9642 { 9643 switch (type) { 9644 case TC_SETUP_BLOCK: 9645 return ixgbe_setup_tc_block(dev, type_data); 9646 case TC_SETUP_QDISC_MQPRIO: 9647 return ixgbe_setup_tc_mqprio(dev, type_data); 9648 default: 9649 return -EOPNOTSUPP; 9650 } 9651 } 9652 9653 #ifdef CONFIG_PCI_IOV 9654 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9655 { 9656 struct net_device *netdev = adapter->netdev; 9657 9658 rtnl_lock(); 9659 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9660 rtnl_unlock(); 9661 } 9662 9663 #endif 9664 void ixgbe_do_reset(struct net_device *netdev) 9665 { 9666 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9667 9668 if (netif_running(netdev)) 9669 ixgbe_reinit_locked(adapter); 9670 else 9671 ixgbe_reset(adapter); 9672 } 9673 9674 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9675 netdev_features_t features) 9676 { 9677 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9678 9679 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9680 if (!(features & NETIF_F_RXCSUM)) 9681 features &= ~NETIF_F_LRO; 9682 9683 /* Turn off LRO if not RSC capable */ 9684 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9685 features &= ~NETIF_F_LRO; 9686 9687 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9688 e_dev_err("LRO is not supported with XDP\n"); 9689 features &= ~NETIF_F_LRO; 9690 } 9691 9692 return features; 9693 } 9694 9695 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9696 { 9697 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9698 num_online_cpus()); 9699 9700 /* go back to full RSS if we're not running SR-IOV */ 9701 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9702 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9703 IXGBE_FLAG_SRIOV_ENABLED); 9704 9705 adapter->ring_feature[RING_F_RSS].limit = rss; 9706 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9707 9708 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9709 } 9710 9711 static int ixgbe_set_features(struct net_device *netdev, 9712 netdev_features_t features) 9713 { 9714 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9715 netdev_features_t changed = netdev->features ^ features; 9716 bool need_reset = false; 9717 9718 /* Make sure RSC matches LRO, reset if change */ 9719 if (!(features & NETIF_F_LRO)) { 9720 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9721 need_reset = true; 9722 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9723 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9724 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9725 if (adapter->rx_itr_setting == 1 || 9726 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9727 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9728 need_reset = true; 9729 } else if ((changed ^ features) & NETIF_F_LRO) { 9730 e_info(probe, "rx-usecs set too low, " 9731 "disabling RSC\n"); 9732 } 9733 } 9734 9735 /* 9736 * Check if Flow Director n-tuple support or hw_tc support was 9737 * enabled or disabled. If the state changed, we need to reset. 9738 */ 9739 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9740 /* turn off ATR, enable perfect filters and reset */ 9741 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9742 need_reset = true; 9743 9744 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9745 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9746 } else { 9747 /* turn off perfect filters, enable ATR and reset */ 9748 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9749 need_reset = true; 9750 9751 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9752 9753 /* We cannot enable ATR if SR-IOV is enabled */ 9754 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9755 /* We cannot enable ATR if we have 2 or more tcs */ 9756 (adapter->hw_tcs > 1) || 9757 /* We cannot enable ATR if RSS is disabled */ 9758 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9759 /* A sample rate of 0 indicates ATR disabled */ 9760 (!adapter->atr_sample_rate)) 9761 ; /* do nothing not supported */ 9762 else /* otherwise supported and set the flag */ 9763 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9764 } 9765 9766 if (changed & NETIF_F_RXALL) 9767 need_reset = true; 9768 9769 netdev->features = features; 9770 9771 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9772 if (features & NETIF_F_RXCSUM) { 9773 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9774 } else { 9775 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9776 9777 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9778 } 9779 } 9780 9781 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9782 if (features & NETIF_F_RXCSUM) { 9783 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9784 } else { 9785 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9786 9787 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9788 } 9789 } 9790 9791 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9792 ixgbe_reset_l2fw_offload(adapter); 9793 else if (need_reset) 9794 ixgbe_do_reset(netdev); 9795 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9796 NETIF_F_HW_VLAN_CTAG_FILTER)) 9797 ixgbe_set_rx_mode(netdev); 9798 9799 return 0; 9800 } 9801 9802 /** 9803 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9804 * @dev: The port's netdev 9805 * @ti: Tunnel endpoint information 9806 **/ 9807 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9808 struct udp_tunnel_info *ti) 9809 { 9810 struct ixgbe_adapter *adapter = netdev_priv(dev); 9811 struct ixgbe_hw *hw = &adapter->hw; 9812 __be16 port = ti->port; 9813 u32 port_shift = 0; 9814 u32 reg; 9815 9816 if (ti->sa_family != AF_INET) 9817 return; 9818 9819 switch (ti->type) { 9820 case UDP_TUNNEL_TYPE_VXLAN: 9821 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9822 return; 9823 9824 if (adapter->vxlan_port == port) 9825 return; 9826 9827 if (adapter->vxlan_port) { 9828 netdev_info(dev, 9829 "VXLAN port %d set, not adding port %d\n", 9830 ntohs(adapter->vxlan_port), 9831 ntohs(port)); 9832 return; 9833 } 9834 9835 adapter->vxlan_port = port; 9836 break; 9837 case UDP_TUNNEL_TYPE_GENEVE: 9838 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9839 return; 9840 9841 if (adapter->geneve_port == port) 9842 return; 9843 9844 if (adapter->geneve_port) { 9845 netdev_info(dev, 9846 "GENEVE port %d set, not adding port %d\n", 9847 ntohs(adapter->geneve_port), 9848 ntohs(port)); 9849 return; 9850 } 9851 9852 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9853 adapter->geneve_port = port; 9854 break; 9855 default: 9856 return; 9857 } 9858 9859 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9860 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9861 } 9862 9863 /** 9864 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9865 * @dev: The port's netdev 9866 * @ti: Tunnel endpoint information 9867 **/ 9868 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9869 struct udp_tunnel_info *ti) 9870 { 9871 struct ixgbe_adapter *adapter = netdev_priv(dev); 9872 u32 port_mask; 9873 9874 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9875 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9876 return; 9877 9878 if (ti->sa_family != AF_INET) 9879 return; 9880 9881 switch (ti->type) { 9882 case UDP_TUNNEL_TYPE_VXLAN: 9883 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9884 return; 9885 9886 if (adapter->vxlan_port != ti->port) { 9887 netdev_info(dev, "VXLAN port %d not found\n", 9888 ntohs(ti->port)); 9889 return; 9890 } 9891 9892 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9893 break; 9894 case UDP_TUNNEL_TYPE_GENEVE: 9895 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9896 return; 9897 9898 if (adapter->geneve_port != ti->port) { 9899 netdev_info(dev, "GENEVE port %d not found\n", 9900 ntohs(ti->port)); 9901 return; 9902 } 9903 9904 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9905 break; 9906 default: 9907 return; 9908 } 9909 9910 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9911 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9912 } 9913 9914 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9915 struct net_device *dev, 9916 const unsigned char *addr, u16 vid, 9917 u16 flags, 9918 struct netlink_ext_ack *extack) 9919 { 9920 /* guarantee we can provide a unique filter for the unicast address */ 9921 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9922 struct ixgbe_adapter *adapter = netdev_priv(dev); 9923 u16 pool = VMDQ_P(0); 9924 9925 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9926 return -ENOMEM; 9927 } 9928 9929 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9930 } 9931 9932 /** 9933 * ixgbe_configure_bridge_mode - set various bridge modes 9934 * @adapter: the private structure 9935 * @mode: requested bridge mode 9936 * 9937 * Configure some settings require for various bridge modes. 9938 **/ 9939 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9940 __u16 mode) 9941 { 9942 struct ixgbe_hw *hw = &adapter->hw; 9943 unsigned int p, num_pools; 9944 u32 vmdctl; 9945 9946 switch (mode) { 9947 case BRIDGE_MODE_VEPA: 9948 /* disable Tx loopback, rely on switch hairpin mode */ 9949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9950 9951 /* must enable Rx switching replication to allow multicast 9952 * packet reception on all VFs, and to enable source address 9953 * pruning. 9954 */ 9955 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9956 vmdctl |= IXGBE_VT_CTL_REPLEN; 9957 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9958 9959 /* enable Rx source address pruning. Note, this requires 9960 * replication to be enabled or else it does nothing. 9961 */ 9962 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9963 for (p = 0; p < num_pools; p++) { 9964 if (hw->mac.ops.set_source_address_pruning) 9965 hw->mac.ops.set_source_address_pruning(hw, 9966 true, 9967 p); 9968 } 9969 break; 9970 case BRIDGE_MODE_VEB: 9971 /* enable Tx loopback for internal VF/PF communication */ 9972 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9973 IXGBE_PFDTXGSWC_VT_LBEN); 9974 9975 /* disable Rx switching replication unless we have SR-IOV 9976 * virtual functions 9977 */ 9978 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9979 if (!adapter->num_vfs) 9980 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9981 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9982 9983 /* disable Rx source address pruning, since we don't expect to 9984 * be receiving external loopback of our transmitted frames. 9985 */ 9986 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9987 for (p = 0; p < num_pools; p++) { 9988 if (hw->mac.ops.set_source_address_pruning) 9989 hw->mac.ops.set_source_address_pruning(hw, 9990 false, 9991 p); 9992 } 9993 break; 9994 default: 9995 return -EINVAL; 9996 } 9997 9998 adapter->bridge_mode = mode; 9999 10000 e_info(drv, "enabling bridge mode: %s\n", 10001 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10002 10003 return 0; 10004 } 10005 10006 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10007 struct nlmsghdr *nlh, u16 flags, 10008 struct netlink_ext_ack *extack) 10009 { 10010 struct ixgbe_adapter *adapter = netdev_priv(dev); 10011 struct nlattr *attr, *br_spec; 10012 int rem; 10013 10014 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10015 return -EOPNOTSUPP; 10016 10017 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10018 if (!br_spec) 10019 return -EINVAL; 10020 10021 nla_for_each_nested(attr, br_spec, rem) { 10022 int status; 10023 __u16 mode; 10024 10025 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10026 continue; 10027 10028 if (nla_len(attr) < sizeof(mode)) 10029 return -EINVAL; 10030 10031 mode = nla_get_u16(attr); 10032 status = ixgbe_configure_bridge_mode(adapter, mode); 10033 if (status) 10034 return status; 10035 10036 break; 10037 } 10038 10039 return 0; 10040 } 10041 10042 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10043 struct net_device *dev, 10044 u32 filter_mask, int nlflags) 10045 { 10046 struct ixgbe_adapter *adapter = netdev_priv(dev); 10047 10048 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10049 return 0; 10050 10051 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10052 adapter->bridge_mode, 0, 0, nlflags, 10053 filter_mask, NULL); 10054 } 10055 10056 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10057 { 10058 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10059 struct ixgbe_fwd_adapter *accel; 10060 int tcs = adapter->hw_tcs ? : 1; 10061 int pool, err; 10062 10063 if (adapter->xdp_prog) { 10064 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10065 return ERR_PTR(-EINVAL); 10066 } 10067 10068 /* The hardware supported by ixgbe only filters on the destination MAC 10069 * address. In order to avoid issues we only support offloading modes 10070 * where the hardware can actually provide the functionality. 10071 */ 10072 if (!macvlan_supports_dest_filter(vdev)) 10073 return ERR_PTR(-EMEDIUMTYPE); 10074 10075 /* We need to lock down the macvlan to be a single queue device so that 10076 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10077 * the queue mapping to our netdev. 10078 */ 10079 if (netif_is_multiqueue(vdev)) 10080 return ERR_PTR(-ERANGE); 10081 10082 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10083 if (pool == adapter->num_rx_pools) { 10084 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10085 u16 reserved_pools; 10086 10087 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10088 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10089 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10090 return ERR_PTR(-EBUSY); 10091 10092 /* Hardware has a limited number of available pools. Each VF, 10093 * and the PF require a pool. Check to ensure we don't 10094 * attempt to use more then the available number of pools. 10095 */ 10096 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10097 return ERR_PTR(-EBUSY); 10098 10099 /* Enable VMDq flag so device will be set in VM mode */ 10100 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10101 IXGBE_FLAG_SRIOV_ENABLED; 10102 10103 /* Try to reserve as many queues per pool as possible, 10104 * we start with the configurations that support 4 queues 10105 * per pools, followed by 2, and then by just 1 per pool. 10106 */ 10107 if (used_pools < 32 && adapter->num_rx_pools < 16) 10108 reserved_pools = min_t(u16, 10109 32 - used_pools, 10110 16 - adapter->num_rx_pools); 10111 else if (adapter->num_rx_pools < 32) 10112 reserved_pools = min_t(u16, 10113 64 - used_pools, 10114 32 - adapter->num_rx_pools); 10115 else 10116 reserved_pools = 64 - used_pools; 10117 10118 10119 if (!reserved_pools) 10120 return ERR_PTR(-EBUSY); 10121 10122 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10123 10124 /* Force reinit of ring allocation with VMDQ enabled */ 10125 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10126 if (err) 10127 return ERR_PTR(err); 10128 10129 if (pool >= adapter->num_rx_pools) 10130 return ERR_PTR(-ENOMEM); 10131 } 10132 10133 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10134 if (!accel) 10135 return ERR_PTR(-ENOMEM); 10136 10137 set_bit(pool, adapter->fwd_bitmask); 10138 netdev_set_sb_channel(vdev, pool); 10139 accel->pool = pool; 10140 accel->netdev = vdev; 10141 10142 if (!netif_running(pdev)) 10143 return accel; 10144 10145 err = ixgbe_fwd_ring_up(adapter, accel); 10146 if (err) 10147 return ERR_PTR(err); 10148 10149 return accel; 10150 } 10151 10152 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10153 { 10154 struct ixgbe_fwd_adapter *accel = priv; 10155 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10156 unsigned int rxbase = accel->rx_base_queue; 10157 unsigned int i; 10158 10159 /* delete unicast filter associated with offloaded interface */ 10160 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10161 VMDQ_P(accel->pool)); 10162 10163 /* Allow remaining Rx packets to get flushed out of the 10164 * Rx FIFO before we drop the netdev for the ring. 10165 */ 10166 usleep_range(10000, 20000); 10167 10168 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10169 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10170 struct ixgbe_q_vector *qv = ring->q_vector; 10171 10172 /* Make sure we aren't processing any packets and clear 10173 * netdev to shut down the ring. 10174 */ 10175 if (netif_running(adapter->netdev)) 10176 napi_synchronize(&qv->napi); 10177 ring->netdev = NULL; 10178 } 10179 10180 /* unbind the queues and drop the subordinate channel config */ 10181 netdev_unbind_sb_channel(pdev, accel->netdev); 10182 netdev_set_sb_channel(accel->netdev, 0); 10183 10184 clear_bit(accel->pool, adapter->fwd_bitmask); 10185 kfree(accel); 10186 } 10187 10188 #define IXGBE_MAX_MAC_HDR_LEN 127 10189 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10190 10191 static netdev_features_t 10192 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10193 netdev_features_t features) 10194 { 10195 unsigned int network_hdr_len, mac_hdr_len; 10196 10197 /* Make certain the headers can be described by a context descriptor */ 10198 mac_hdr_len = skb_network_header(skb) - skb->data; 10199 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10200 return features & ~(NETIF_F_HW_CSUM | 10201 NETIF_F_SCTP_CRC | 10202 NETIF_F_HW_VLAN_CTAG_TX | 10203 NETIF_F_TSO | 10204 NETIF_F_TSO6); 10205 10206 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10207 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10208 return features & ~(NETIF_F_HW_CSUM | 10209 NETIF_F_SCTP_CRC | 10210 NETIF_F_TSO | 10211 NETIF_F_TSO6); 10212 10213 /* We can only support IPV4 TSO in tunnels if we can mangle the 10214 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10215 * IPsec offoad sets skb->encapsulation but still can handle 10216 * the TSO, so it's the exception. 10217 */ 10218 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10219 #ifdef CONFIG_IXGBE_IPSEC 10220 if (!secpath_exists(skb)) 10221 #endif 10222 features &= ~NETIF_F_TSO; 10223 } 10224 10225 return features; 10226 } 10227 10228 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10229 { 10230 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10231 struct ixgbe_adapter *adapter = netdev_priv(dev); 10232 struct bpf_prog *old_prog; 10233 bool need_reset; 10234 10235 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10236 return -EINVAL; 10237 10238 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10239 return -EINVAL; 10240 10241 /* verify ixgbe ring attributes are sufficient for XDP */ 10242 for (i = 0; i < adapter->num_rx_queues; i++) { 10243 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10244 10245 if (ring_is_rsc_enabled(ring)) 10246 return -EINVAL; 10247 10248 if (frame_size > ixgbe_rx_bufsz(ring)) 10249 return -EINVAL; 10250 } 10251 10252 if (nr_cpu_ids > MAX_XDP_QUEUES) 10253 return -ENOMEM; 10254 10255 old_prog = xchg(&adapter->xdp_prog, prog); 10256 need_reset = (!!prog != !!old_prog); 10257 10258 /* If transitioning XDP modes reconfigure rings */ 10259 if (need_reset) { 10260 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10261 10262 if (err) { 10263 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10264 return -EINVAL; 10265 } 10266 } else { 10267 for (i = 0; i < adapter->num_rx_queues; i++) 10268 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 10269 adapter->xdp_prog); 10270 } 10271 10272 if (old_prog) 10273 bpf_prog_put(old_prog); 10274 10275 /* Kick start the NAPI context if there is an AF_XDP socket open 10276 * on that queue id. This so that receiving will start. 10277 */ 10278 if (need_reset && prog) 10279 for (i = 0; i < adapter->num_rx_queues; i++) 10280 if (adapter->xdp_ring[i]->xsk_umem) 10281 (void)ixgbe_xsk_async_xmit(adapter->netdev, i); 10282 10283 return 0; 10284 } 10285 10286 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10287 { 10288 struct ixgbe_adapter *adapter = netdev_priv(dev); 10289 10290 switch (xdp->command) { 10291 case XDP_SETUP_PROG: 10292 return ixgbe_xdp_setup(dev, xdp->prog); 10293 case XDP_QUERY_PROG: 10294 xdp->prog_id = adapter->xdp_prog ? 10295 adapter->xdp_prog->aux->id : 0; 10296 return 0; 10297 case XDP_SETUP_XSK_UMEM: 10298 return ixgbe_xsk_umem_setup(adapter, xdp->xsk.umem, 10299 xdp->xsk.queue_id); 10300 10301 default: 10302 return -EINVAL; 10303 } 10304 } 10305 10306 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10307 { 10308 /* Force memory writes to complete before letting h/w know there 10309 * are new descriptors to fetch. 10310 */ 10311 wmb(); 10312 writel(ring->next_to_use, ring->tail); 10313 } 10314 10315 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10316 struct xdp_frame **frames, u32 flags) 10317 { 10318 struct ixgbe_adapter *adapter = netdev_priv(dev); 10319 struct ixgbe_ring *ring; 10320 int drops = 0; 10321 int i; 10322 10323 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10324 return -ENETDOWN; 10325 10326 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10327 return -EINVAL; 10328 10329 /* During program transitions its possible adapter->xdp_prog is assigned 10330 * but ring has not been configured yet. In this case simply abort xmit. 10331 */ 10332 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10333 if (unlikely(!ring)) 10334 return -ENXIO; 10335 10336 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10337 return -ENXIO; 10338 10339 for (i = 0; i < n; i++) { 10340 struct xdp_frame *xdpf = frames[i]; 10341 int err; 10342 10343 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10344 if (err != IXGBE_XDP_TX) { 10345 xdp_return_frame_rx_napi(xdpf); 10346 drops++; 10347 } 10348 } 10349 10350 if (unlikely(flags & XDP_XMIT_FLUSH)) 10351 ixgbe_xdp_ring_update_tail(ring); 10352 10353 return n - drops; 10354 } 10355 10356 static const struct net_device_ops ixgbe_netdev_ops = { 10357 .ndo_open = ixgbe_open, 10358 .ndo_stop = ixgbe_close, 10359 .ndo_start_xmit = ixgbe_xmit_frame, 10360 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10361 .ndo_validate_addr = eth_validate_addr, 10362 .ndo_set_mac_address = ixgbe_set_mac, 10363 .ndo_change_mtu = ixgbe_change_mtu, 10364 .ndo_tx_timeout = ixgbe_tx_timeout, 10365 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10366 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10367 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10368 .ndo_do_ioctl = ixgbe_ioctl, 10369 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10370 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10371 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10372 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10373 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10374 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10375 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10376 .ndo_get_stats64 = ixgbe_get_stats64, 10377 .ndo_setup_tc = __ixgbe_setup_tc, 10378 #ifdef IXGBE_FCOE 10379 .ndo_select_queue = ixgbe_select_queue, 10380 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10381 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10382 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10383 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10384 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10385 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10386 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10387 #endif /* IXGBE_FCOE */ 10388 .ndo_set_features = ixgbe_set_features, 10389 .ndo_fix_features = ixgbe_fix_features, 10390 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10391 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10392 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10393 .ndo_dfwd_add_station = ixgbe_fwd_add, 10394 .ndo_dfwd_del_station = ixgbe_fwd_del, 10395 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10396 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10397 .ndo_features_check = ixgbe_features_check, 10398 .ndo_bpf = ixgbe_xdp, 10399 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10400 .ndo_xsk_async_xmit = ixgbe_xsk_async_xmit, 10401 }; 10402 10403 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10404 struct ixgbe_ring *tx_ring) 10405 { 10406 unsigned long wait_delay, delay_interval; 10407 struct ixgbe_hw *hw = &adapter->hw; 10408 u8 reg_idx = tx_ring->reg_idx; 10409 int wait_loop; 10410 u32 txdctl; 10411 10412 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10413 10414 /* delay mechanism from ixgbe_disable_tx */ 10415 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10416 10417 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10418 wait_delay = delay_interval; 10419 10420 while (wait_loop--) { 10421 usleep_range(wait_delay, wait_delay + 10); 10422 wait_delay += delay_interval * 2; 10423 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10424 10425 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10426 return; 10427 } 10428 10429 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10430 } 10431 10432 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10433 struct ixgbe_ring *tx_ring) 10434 { 10435 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10436 ixgbe_disable_txr_hw(adapter, tx_ring); 10437 } 10438 10439 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10440 struct ixgbe_ring *rx_ring) 10441 { 10442 unsigned long wait_delay, delay_interval; 10443 struct ixgbe_hw *hw = &adapter->hw; 10444 u8 reg_idx = rx_ring->reg_idx; 10445 int wait_loop; 10446 u32 rxdctl; 10447 10448 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10449 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10450 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10451 10452 /* write value back with RXDCTL.ENABLE bit cleared */ 10453 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10454 10455 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10456 if (hw->mac.type == ixgbe_mac_82598EB && 10457 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10458 return; 10459 10460 /* delay mechanism from ixgbe_disable_rx */ 10461 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10462 10463 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10464 wait_delay = delay_interval; 10465 10466 while (wait_loop--) { 10467 usleep_range(wait_delay, wait_delay + 10); 10468 wait_delay += delay_interval * 2; 10469 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10470 10471 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10472 return; 10473 } 10474 10475 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10476 } 10477 10478 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10479 { 10480 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10481 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10482 } 10483 10484 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10485 { 10486 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10487 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10488 } 10489 10490 /** 10491 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10492 * @adapter: adapter structure 10493 * @ring: ring index 10494 * 10495 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10496 * assumes that the netdev is running. 10497 **/ 10498 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10499 { 10500 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10501 10502 rx_ring = adapter->rx_ring[ring]; 10503 tx_ring = adapter->tx_ring[ring]; 10504 xdp_ring = adapter->xdp_ring[ring]; 10505 10506 ixgbe_disable_txr(adapter, tx_ring); 10507 if (xdp_ring) 10508 ixgbe_disable_txr(adapter, xdp_ring); 10509 ixgbe_disable_rxr_hw(adapter, rx_ring); 10510 10511 if (xdp_ring) 10512 synchronize_rcu(); 10513 10514 /* Rx/Tx/XDP Tx share the same napi context. */ 10515 napi_disable(&rx_ring->q_vector->napi); 10516 10517 ixgbe_clean_tx_ring(tx_ring); 10518 if (xdp_ring) 10519 ixgbe_clean_tx_ring(xdp_ring); 10520 ixgbe_clean_rx_ring(rx_ring); 10521 10522 ixgbe_reset_txr_stats(tx_ring); 10523 if (xdp_ring) 10524 ixgbe_reset_txr_stats(xdp_ring); 10525 ixgbe_reset_rxr_stats(rx_ring); 10526 } 10527 10528 /** 10529 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10530 * @adapter: adapter structure 10531 * @ring: ring index 10532 * 10533 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10534 * assumes that the netdev is running. 10535 **/ 10536 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10537 { 10538 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10539 10540 rx_ring = adapter->rx_ring[ring]; 10541 tx_ring = adapter->tx_ring[ring]; 10542 xdp_ring = adapter->xdp_ring[ring]; 10543 10544 /* Rx/Tx/XDP Tx share the same napi context. */ 10545 napi_enable(&rx_ring->q_vector->napi); 10546 10547 ixgbe_configure_tx_ring(adapter, tx_ring); 10548 if (xdp_ring) 10549 ixgbe_configure_tx_ring(adapter, xdp_ring); 10550 ixgbe_configure_rx_ring(adapter, rx_ring); 10551 10552 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10553 if (xdp_ring) 10554 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10555 } 10556 10557 /** 10558 * ixgbe_enumerate_functions - Get the number of ports this device has 10559 * @adapter: adapter structure 10560 * 10561 * This function enumerates the phsyical functions co-located on a single slot, 10562 * in order to determine how many ports a device has. This is most useful in 10563 * determining the required GT/s of PCIe bandwidth necessary for optimal 10564 * performance. 10565 **/ 10566 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10567 { 10568 struct pci_dev *entry, *pdev = adapter->pdev; 10569 int physfns = 0; 10570 10571 /* Some cards can not use the generic count PCIe functions method, 10572 * because they are behind a parent switch, so we hardcode these with 10573 * the correct number of functions. 10574 */ 10575 if (ixgbe_pcie_from_parent(&adapter->hw)) 10576 physfns = 4; 10577 10578 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10579 /* don't count virtual functions */ 10580 if (entry->is_virtfn) 10581 continue; 10582 10583 /* When the devices on the bus don't all match our device ID, 10584 * we can't reliably determine the correct number of 10585 * functions. This can occur if a function has been direct 10586 * attached to a virtual machine using VT-d, for example. In 10587 * this case, simply return -1 to indicate this. 10588 */ 10589 if ((entry->vendor != pdev->vendor) || 10590 (entry->device != pdev->device)) 10591 return -1; 10592 10593 physfns++; 10594 } 10595 10596 return physfns; 10597 } 10598 10599 /** 10600 * ixgbe_wol_supported - Check whether device supports WoL 10601 * @adapter: the adapter private structure 10602 * @device_id: the device ID 10603 * @subdevice_id: the subsystem device ID 10604 * 10605 * This function is used by probe and ethtool to determine 10606 * which devices have WoL support 10607 * 10608 **/ 10609 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10610 u16 subdevice_id) 10611 { 10612 struct ixgbe_hw *hw = &adapter->hw; 10613 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10614 10615 /* WOL not supported on 82598 */ 10616 if (hw->mac.type == ixgbe_mac_82598EB) 10617 return false; 10618 10619 /* check eeprom to see if WOL is enabled for X540 and newer */ 10620 if (hw->mac.type >= ixgbe_mac_X540) { 10621 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10622 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10623 (hw->bus.func == 0))) 10624 return true; 10625 } 10626 10627 /* WOL is determined based on device IDs for 82599 MACs */ 10628 switch (device_id) { 10629 case IXGBE_DEV_ID_82599_SFP: 10630 /* Only these subdevices could supports WOL */ 10631 switch (subdevice_id) { 10632 case IXGBE_SUBDEV_ID_82599_560FLR: 10633 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10634 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10635 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10636 /* only support first port */ 10637 if (hw->bus.func != 0) 10638 break; 10639 /* fall through */ 10640 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10641 case IXGBE_SUBDEV_ID_82599_SFP: 10642 case IXGBE_SUBDEV_ID_82599_RNDC: 10643 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10644 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10645 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10646 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10647 return true; 10648 } 10649 break; 10650 case IXGBE_DEV_ID_82599EN_SFP: 10651 /* Only these subdevices support WOL */ 10652 switch (subdevice_id) { 10653 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10654 return true; 10655 } 10656 break; 10657 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10658 /* All except this subdevice support WOL */ 10659 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10660 return true; 10661 break; 10662 case IXGBE_DEV_ID_82599_KX4: 10663 return true; 10664 default: 10665 break; 10666 } 10667 10668 return false; 10669 } 10670 10671 /** 10672 * ixgbe_set_fw_version - Set FW version 10673 * @adapter: the adapter private structure 10674 * 10675 * This function is used by probe and ethtool to determine the FW version to 10676 * format to display. The FW version is taken from the EEPROM/NVM. 10677 */ 10678 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10679 { 10680 struct ixgbe_hw *hw = &adapter->hw; 10681 struct ixgbe_nvm_version nvm_ver; 10682 10683 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10684 if (nvm_ver.oem_valid) { 10685 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10686 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10687 nvm_ver.oem_release); 10688 return; 10689 } 10690 10691 ixgbe_get_etk_id(hw, &nvm_ver); 10692 ixgbe_get_orom_version(hw, &nvm_ver); 10693 10694 if (nvm_ver.or_valid) { 10695 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10696 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10697 nvm_ver.or_build, nvm_ver.or_patch); 10698 return; 10699 } 10700 10701 /* Set ETrack ID format */ 10702 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10703 "0x%08x", nvm_ver.etk_id); 10704 } 10705 10706 /** 10707 * ixgbe_probe - Device Initialization Routine 10708 * @pdev: PCI device information struct 10709 * @ent: entry in ixgbe_pci_tbl 10710 * 10711 * Returns 0 on success, negative on failure 10712 * 10713 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10714 * The OS initialization, configuring of the adapter private structure, 10715 * and a hardware reset occur. 10716 **/ 10717 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10718 { 10719 struct net_device *netdev; 10720 struct ixgbe_adapter *adapter = NULL; 10721 struct ixgbe_hw *hw; 10722 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10723 int i, err, pci_using_dac, expected_gts; 10724 unsigned int indices = MAX_TX_QUEUES; 10725 u8 part_str[IXGBE_PBANUM_LENGTH]; 10726 bool disable_dev = false; 10727 #ifdef IXGBE_FCOE 10728 u16 device_caps; 10729 #endif 10730 u32 eec; 10731 10732 /* Catch broken hardware that put the wrong VF device ID in 10733 * the PCIe SR-IOV capability. 10734 */ 10735 if (pdev->is_virtfn) { 10736 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10737 pci_name(pdev), pdev->vendor, pdev->device); 10738 return -EINVAL; 10739 } 10740 10741 err = pci_enable_device_mem(pdev); 10742 if (err) 10743 return err; 10744 10745 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10746 pci_using_dac = 1; 10747 } else { 10748 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10749 if (err) { 10750 dev_err(&pdev->dev, 10751 "No usable DMA configuration, aborting\n"); 10752 goto err_dma; 10753 } 10754 pci_using_dac = 0; 10755 } 10756 10757 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10758 if (err) { 10759 dev_err(&pdev->dev, 10760 "pci_request_selected_regions failed 0x%x\n", err); 10761 goto err_pci_reg; 10762 } 10763 10764 pci_enable_pcie_error_reporting(pdev); 10765 10766 pci_set_master(pdev); 10767 pci_save_state(pdev); 10768 10769 if (ii->mac == ixgbe_mac_82598EB) { 10770 #ifdef CONFIG_IXGBE_DCB 10771 /* 8 TC w/ 4 queues per TC */ 10772 indices = 4 * MAX_TRAFFIC_CLASS; 10773 #else 10774 indices = IXGBE_MAX_RSS_INDICES; 10775 #endif 10776 } 10777 10778 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10779 if (!netdev) { 10780 err = -ENOMEM; 10781 goto err_alloc_etherdev; 10782 } 10783 10784 SET_NETDEV_DEV(netdev, &pdev->dev); 10785 10786 adapter = netdev_priv(netdev); 10787 10788 adapter->netdev = netdev; 10789 adapter->pdev = pdev; 10790 hw = &adapter->hw; 10791 hw->back = adapter; 10792 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10793 10794 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10795 pci_resource_len(pdev, 0)); 10796 adapter->io_addr = hw->hw_addr; 10797 if (!hw->hw_addr) { 10798 err = -EIO; 10799 goto err_ioremap; 10800 } 10801 10802 netdev->netdev_ops = &ixgbe_netdev_ops; 10803 ixgbe_set_ethtool_ops(netdev); 10804 netdev->watchdog_timeo = 5 * HZ; 10805 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10806 10807 /* Setup hw api */ 10808 hw->mac.ops = *ii->mac_ops; 10809 hw->mac.type = ii->mac; 10810 hw->mvals = ii->mvals; 10811 if (ii->link_ops) 10812 hw->link.ops = *ii->link_ops; 10813 10814 /* EEPROM */ 10815 hw->eeprom.ops = *ii->eeprom_ops; 10816 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10817 if (ixgbe_removed(hw->hw_addr)) { 10818 err = -EIO; 10819 goto err_ioremap; 10820 } 10821 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10822 if (!(eec & BIT(8))) 10823 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10824 10825 /* PHY */ 10826 hw->phy.ops = *ii->phy_ops; 10827 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10828 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10829 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10830 hw->phy.mdio.mmds = 0; 10831 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10832 hw->phy.mdio.dev = netdev; 10833 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10834 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10835 10836 /* setup the private structure */ 10837 err = ixgbe_sw_init(adapter, ii); 10838 if (err) 10839 goto err_sw_init; 10840 10841 /* Make sure the SWFW semaphore is in a valid state */ 10842 if (hw->mac.ops.init_swfw_sync) 10843 hw->mac.ops.init_swfw_sync(hw); 10844 10845 /* Make it possible the adapter to be woken up via WOL */ 10846 switch (adapter->hw.mac.type) { 10847 case ixgbe_mac_82599EB: 10848 case ixgbe_mac_X540: 10849 case ixgbe_mac_X550: 10850 case ixgbe_mac_X550EM_x: 10851 case ixgbe_mac_x550em_a: 10852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10853 break; 10854 default: 10855 break; 10856 } 10857 10858 /* 10859 * If there is a fan on this device and it has failed log the 10860 * failure. 10861 */ 10862 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10863 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10864 if (esdp & IXGBE_ESDP_SDP1) 10865 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10866 } 10867 10868 if (allow_unsupported_sfp) 10869 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10870 10871 /* reset_hw fills in the perm_addr as well */ 10872 hw->phy.reset_if_overtemp = true; 10873 err = hw->mac.ops.reset_hw(hw); 10874 hw->phy.reset_if_overtemp = false; 10875 ixgbe_set_eee_capable(adapter); 10876 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10877 err = 0; 10878 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10879 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10880 e_dev_err("Reload the driver after installing a supported module.\n"); 10881 goto err_sw_init; 10882 } else if (err) { 10883 e_dev_err("HW Init failed: %d\n", err); 10884 goto err_sw_init; 10885 } 10886 10887 #ifdef CONFIG_PCI_IOV 10888 /* SR-IOV not supported on the 82598 */ 10889 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10890 goto skip_sriov; 10891 /* Mailbox */ 10892 ixgbe_init_mbx_params_pf(hw); 10893 hw->mbx.ops = ii->mbx_ops; 10894 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10895 ixgbe_enable_sriov(adapter, max_vfs); 10896 skip_sriov: 10897 10898 #endif 10899 netdev->features = NETIF_F_SG | 10900 NETIF_F_TSO | 10901 NETIF_F_TSO6 | 10902 NETIF_F_RXHASH | 10903 NETIF_F_RXCSUM | 10904 NETIF_F_HW_CSUM; 10905 10906 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10907 NETIF_F_GSO_GRE_CSUM | \ 10908 NETIF_F_GSO_IPXIP4 | \ 10909 NETIF_F_GSO_IPXIP6 | \ 10910 NETIF_F_GSO_UDP_TUNNEL | \ 10911 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10912 10913 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10914 netdev->features |= NETIF_F_GSO_PARTIAL | 10915 IXGBE_GSO_PARTIAL_FEATURES; 10916 10917 if (hw->mac.type >= ixgbe_mac_82599EB) 10918 netdev->features |= NETIF_F_SCTP_CRC; 10919 10920 #ifdef CONFIG_IXGBE_IPSEC 10921 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10922 NETIF_F_HW_ESP_TX_CSUM | \ 10923 NETIF_F_GSO_ESP) 10924 10925 if (adapter->ipsec) 10926 netdev->features |= IXGBE_ESP_FEATURES; 10927 #endif 10928 /* copy netdev features into list of user selectable features */ 10929 netdev->hw_features |= netdev->features | 10930 NETIF_F_HW_VLAN_CTAG_FILTER | 10931 NETIF_F_HW_VLAN_CTAG_RX | 10932 NETIF_F_HW_VLAN_CTAG_TX | 10933 NETIF_F_RXALL | 10934 NETIF_F_HW_L2FW_DOFFLOAD; 10935 10936 if (hw->mac.type >= ixgbe_mac_82599EB) 10937 netdev->hw_features |= NETIF_F_NTUPLE | 10938 NETIF_F_HW_TC; 10939 10940 if (pci_using_dac) 10941 netdev->features |= NETIF_F_HIGHDMA; 10942 10943 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10944 netdev->hw_enc_features |= netdev->vlan_features; 10945 netdev->mpls_features |= NETIF_F_SG | 10946 NETIF_F_TSO | 10947 NETIF_F_TSO6 | 10948 NETIF_F_HW_CSUM; 10949 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10950 10951 /* set this bit last since it cannot be part of vlan_features */ 10952 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10953 NETIF_F_HW_VLAN_CTAG_RX | 10954 NETIF_F_HW_VLAN_CTAG_TX; 10955 10956 netdev->priv_flags |= IFF_UNICAST_FLT; 10957 netdev->priv_flags |= IFF_SUPP_NOFCS; 10958 10959 /* MTU range: 68 - 9710 */ 10960 netdev->min_mtu = ETH_MIN_MTU; 10961 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10962 10963 #ifdef CONFIG_IXGBE_DCB 10964 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10965 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10966 #endif 10967 10968 #ifdef IXGBE_FCOE 10969 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10970 unsigned int fcoe_l; 10971 10972 if (hw->mac.ops.get_device_caps) { 10973 hw->mac.ops.get_device_caps(hw, &device_caps); 10974 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10975 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10976 } 10977 10978 10979 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10980 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10981 10982 netdev->features |= NETIF_F_FSO | 10983 NETIF_F_FCOE_CRC; 10984 10985 netdev->vlan_features |= NETIF_F_FSO | 10986 NETIF_F_FCOE_CRC | 10987 NETIF_F_FCOE_MTU; 10988 } 10989 #endif /* IXGBE_FCOE */ 10990 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10991 netdev->hw_features |= NETIF_F_LRO; 10992 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10993 netdev->features |= NETIF_F_LRO; 10994 10995 if (ixgbe_check_fw_error(adapter)) { 10996 err = -EIO; 10997 goto err_sw_init; 10998 } 10999 11000 /* make sure the EEPROM is good */ 11001 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11002 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11003 err = -EIO; 11004 goto err_sw_init; 11005 } 11006 11007 eth_platform_get_mac_address(&adapter->pdev->dev, 11008 adapter->hw.mac.perm_addr); 11009 11010 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 11011 11012 if (!is_valid_ether_addr(netdev->dev_addr)) { 11013 e_dev_err("invalid MAC address\n"); 11014 err = -EIO; 11015 goto err_sw_init; 11016 } 11017 11018 /* Set hw->mac.addr to permanent MAC address */ 11019 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11020 ixgbe_mac_set_default_filter(adapter); 11021 11022 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11023 11024 if (ixgbe_removed(hw->hw_addr)) { 11025 err = -EIO; 11026 goto err_sw_init; 11027 } 11028 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11029 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11030 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11031 11032 err = ixgbe_init_interrupt_scheme(adapter); 11033 if (err) 11034 goto err_sw_init; 11035 11036 for (i = 0; i < adapter->num_rx_queues; i++) 11037 u64_stats_init(&adapter->rx_ring[i]->syncp); 11038 for (i = 0; i < adapter->num_tx_queues; i++) 11039 u64_stats_init(&adapter->tx_ring[i]->syncp); 11040 for (i = 0; i < adapter->num_xdp_queues; i++) 11041 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11042 11043 /* WOL not supported for all devices */ 11044 adapter->wol = 0; 11045 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11046 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11047 pdev->subsystem_device); 11048 if (hw->wol_enabled) 11049 adapter->wol = IXGBE_WUFC_MAG; 11050 11051 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11052 11053 /* save off EEPROM version number */ 11054 ixgbe_set_fw_version(adapter); 11055 11056 /* pick up the PCI bus settings for reporting later */ 11057 if (ixgbe_pcie_from_parent(hw)) 11058 ixgbe_get_parent_bus_info(adapter); 11059 else 11060 hw->mac.ops.get_bus_info(hw); 11061 11062 /* calculate the expected PCIe bandwidth required for optimal 11063 * performance. Note that some older parts will never have enough 11064 * bandwidth due to being older generation PCIe parts. We clamp these 11065 * parts to ensure no warning is displayed if it can't be fixed. 11066 */ 11067 switch (hw->mac.type) { 11068 case ixgbe_mac_82598EB: 11069 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11070 break; 11071 default: 11072 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11073 break; 11074 } 11075 11076 /* don't check link if we failed to enumerate functions */ 11077 if (expected_gts > 0) 11078 ixgbe_check_minimum_link(adapter, expected_gts); 11079 11080 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11081 if (err) 11082 strlcpy(part_str, "Unknown", sizeof(part_str)); 11083 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11084 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11085 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11086 part_str); 11087 else 11088 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11089 hw->mac.type, hw->phy.type, part_str); 11090 11091 e_dev_info("%pM\n", netdev->dev_addr); 11092 11093 /* reset the hardware with the new settings */ 11094 err = hw->mac.ops.start_hw(hw); 11095 if (err == IXGBE_ERR_EEPROM_VERSION) { 11096 /* We are running on a pre-production device, log a warning */ 11097 e_dev_warn("This device is a pre-production adapter/LOM. " 11098 "Please be aware there may be issues associated " 11099 "with your hardware. If you are experiencing " 11100 "problems please contact your Intel or hardware " 11101 "representative who provided you with this " 11102 "hardware.\n"); 11103 } 11104 strcpy(netdev->name, "eth%d"); 11105 pci_set_drvdata(pdev, adapter); 11106 err = register_netdev(netdev); 11107 if (err) 11108 goto err_register; 11109 11110 11111 /* power down the optics for 82599 SFP+ fiber */ 11112 if (hw->mac.ops.disable_tx_laser) 11113 hw->mac.ops.disable_tx_laser(hw); 11114 11115 /* carrier off reporting is important to ethtool even BEFORE open */ 11116 netif_carrier_off(netdev); 11117 11118 #ifdef CONFIG_IXGBE_DCA 11119 if (dca_add_requester(&pdev->dev) == 0) { 11120 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11121 ixgbe_setup_dca(adapter); 11122 } 11123 #endif 11124 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11125 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11126 for (i = 0; i < adapter->num_vfs; i++) 11127 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11128 } 11129 11130 /* firmware requires driver version to be 0xFFFFFFFF 11131 * since os does not support feature 11132 */ 11133 if (hw->mac.ops.set_fw_drv_ver) 11134 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11135 sizeof(ixgbe_driver_version) - 1, 11136 ixgbe_driver_version); 11137 11138 /* add san mac addr to netdev */ 11139 ixgbe_add_sanmac_netdev(netdev); 11140 11141 e_dev_info("%s\n", ixgbe_default_device_descr); 11142 11143 #ifdef CONFIG_IXGBE_HWMON 11144 if (ixgbe_sysfs_init(adapter)) 11145 e_err(probe, "failed to allocate sysfs resources\n"); 11146 #endif /* CONFIG_IXGBE_HWMON */ 11147 11148 ixgbe_dbg_adapter_init(adapter); 11149 11150 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11151 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11152 hw->mac.ops.setup_link(hw, 11153 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11154 true); 11155 11156 ixgbe_mii_bus_init(hw); 11157 11158 return 0; 11159 11160 err_register: 11161 ixgbe_release_hw_control(adapter); 11162 ixgbe_clear_interrupt_scheme(adapter); 11163 err_sw_init: 11164 ixgbe_disable_sriov(adapter); 11165 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11166 iounmap(adapter->io_addr); 11167 kfree(adapter->jump_tables[0]); 11168 kfree(adapter->mac_table); 11169 kfree(adapter->rss_key); 11170 err_ioremap: 11171 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11172 free_netdev(netdev); 11173 err_alloc_etherdev: 11174 pci_release_mem_regions(pdev); 11175 err_pci_reg: 11176 err_dma: 11177 if (!adapter || disable_dev) 11178 pci_disable_device(pdev); 11179 return err; 11180 } 11181 11182 /** 11183 * ixgbe_remove - Device Removal Routine 11184 * @pdev: PCI device information struct 11185 * 11186 * ixgbe_remove is called by the PCI subsystem to alert the driver 11187 * that it should release a PCI device. The could be caused by a 11188 * Hot-Plug event, or because the driver is going to be removed from 11189 * memory. 11190 **/ 11191 static void ixgbe_remove(struct pci_dev *pdev) 11192 { 11193 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11194 struct net_device *netdev; 11195 bool disable_dev; 11196 int i; 11197 11198 /* if !adapter then we already cleaned up in probe */ 11199 if (!adapter) 11200 return; 11201 11202 netdev = adapter->netdev; 11203 ixgbe_dbg_adapter_exit(adapter); 11204 11205 set_bit(__IXGBE_REMOVING, &adapter->state); 11206 cancel_work_sync(&adapter->service_task); 11207 11208 if (adapter->mii_bus) 11209 mdiobus_unregister(adapter->mii_bus); 11210 11211 #ifdef CONFIG_IXGBE_DCA 11212 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11213 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11214 dca_remove_requester(&pdev->dev); 11215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11216 IXGBE_DCA_CTRL_DCA_DISABLE); 11217 } 11218 11219 #endif 11220 #ifdef CONFIG_IXGBE_HWMON 11221 ixgbe_sysfs_exit(adapter); 11222 #endif /* CONFIG_IXGBE_HWMON */ 11223 11224 /* remove the added san mac */ 11225 ixgbe_del_sanmac_netdev(netdev); 11226 11227 #ifdef CONFIG_PCI_IOV 11228 ixgbe_disable_sriov(adapter); 11229 #endif 11230 if (netdev->reg_state == NETREG_REGISTERED) 11231 unregister_netdev(netdev); 11232 11233 ixgbe_stop_ipsec_offload(adapter); 11234 ixgbe_clear_interrupt_scheme(adapter); 11235 11236 ixgbe_release_hw_control(adapter); 11237 11238 #ifdef CONFIG_DCB 11239 kfree(adapter->ixgbe_ieee_pfc); 11240 kfree(adapter->ixgbe_ieee_ets); 11241 11242 #endif 11243 iounmap(adapter->io_addr); 11244 pci_release_mem_regions(pdev); 11245 11246 e_dev_info("complete\n"); 11247 11248 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11249 if (adapter->jump_tables[i]) { 11250 kfree(adapter->jump_tables[i]->input); 11251 kfree(adapter->jump_tables[i]->mask); 11252 } 11253 kfree(adapter->jump_tables[i]); 11254 } 11255 11256 kfree(adapter->mac_table); 11257 kfree(adapter->rss_key); 11258 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11259 free_netdev(netdev); 11260 11261 pci_disable_pcie_error_reporting(pdev); 11262 11263 if (disable_dev) 11264 pci_disable_device(pdev); 11265 } 11266 11267 /** 11268 * ixgbe_io_error_detected - called when PCI error is detected 11269 * @pdev: Pointer to PCI device 11270 * @state: The current pci connection state 11271 * 11272 * This function is called after a PCI bus error affecting 11273 * this device has been detected. 11274 */ 11275 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11276 pci_channel_state_t state) 11277 { 11278 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11279 struct net_device *netdev = adapter->netdev; 11280 11281 #ifdef CONFIG_PCI_IOV 11282 struct ixgbe_hw *hw = &adapter->hw; 11283 struct pci_dev *bdev, *vfdev; 11284 u32 dw0, dw1, dw2, dw3; 11285 int vf, pos; 11286 u16 req_id, pf_func; 11287 11288 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11289 adapter->num_vfs == 0) 11290 goto skip_bad_vf_detection; 11291 11292 bdev = pdev->bus->self; 11293 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11294 bdev = bdev->bus->self; 11295 11296 if (!bdev) 11297 goto skip_bad_vf_detection; 11298 11299 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11300 if (!pos) 11301 goto skip_bad_vf_detection; 11302 11303 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11304 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11305 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11306 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11307 if (ixgbe_removed(hw->hw_addr)) 11308 goto skip_bad_vf_detection; 11309 11310 req_id = dw1 >> 16; 11311 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11312 if (!(req_id & 0x0080)) 11313 goto skip_bad_vf_detection; 11314 11315 pf_func = req_id & 0x01; 11316 if ((pf_func & 1) == (pdev->devfn & 1)) { 11317 unsigned int device_id; 11318 11319 vf = (req_id & 0x7F) >> 1; 11320 e_dev_err("VF %d has caused a PCIe error\n", vf); 11321 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11322 "%8.8x\tdw3: %8.8x\n", 11323 dw0, dw1, dw2, dw3); 11324 switch (adapter->hw.mac.type) { 11325 case ixgbe_mac_82599EB: 11326 device_id = IXGBE_82599_VF_DEVICE_ID; 11327 break; 11328 case ixgbe_mac_X540: 11329 device_id = IXGBE_X540_VF_DEVICE_ID; 11330 break; 11331 case ixgbe_mac_X550: 11332 device_id = IXGBE_DEV_ID_X550_VF; 11333 break; 11334 case ixgbe_mac_X550EM_x: 11335 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11336 break; 11337 case ixgbe_mac_x550em_a: 11338 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11339 break; 11340 default: 11341 device_id = 0; 11342 break; 11343 } 11344 11345 /* Find the pci device of the offending VF */ 11346 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11347 while (vfdev) { 11348 if (vfdev->devfn == (req_id & 0xFF)) 11349 break; 11350 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11351 device_id, vfdev); 11352 } 11353 /* 11354 * There's a slim chance the VF could have been hot plugged, 11355 * so if it is no longer present we don't need to issue the 11356 * VFLR. Just clean up the AER in that case. 11357 */ 11358 if (vfdev) { 11359 pcie_flr(vfdev); 11360 /* Free device reference count */ 11361 pci_dev_put(vfdev); 11362 } 11363 } 11364 11365 /* 11366 * Even though the error may have occurred on the other port 11367 * we still need to increment the vf error reference count for 11368 * both ports because the I/O resume function will be called 11369 * for both of them. 11370 */ 11371 adapter->vferr_refcount++; 11372 11373 return PCI_ERS_RESULT_RECOVERED; 11374 11375 skip_bad_vf_detection: 11376 #endif /* CONFIG_PCI_IOV */ 11377 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11378 return PCI_ERS_RESULT_DISCONNECT; 11379 11380 if (!netif_device_present(netdev)) 11381 return PCI_ERS_RESULT_DISCONNECT; 11382 11383 rtnl_lock(); 11384 netif_device_detach(netdev); 11385 11386 if (netif_running(netdev)) 11387 ixgbe_close_suspend(adapter); 11388 11389 if (state == pci_channel_io_perm_failure) { 11390 rtnl_unlock(); 11391 return PCI_ERS_RESULT_DISCONNECT; 11392 } 11393 11394 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11395 pci_disable_device(pdev); 11396 rtnl_unlock(); 11397 11398 /* Request a slot reset. */ 11399 return PCI_ERS_RESULT_NEED_RESET; 11400 } 11401 11402 /** 11403 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11404 * @pdev: Pointer to PCI device 11405 * 11406 * Restart the card from scratch, as if from a cold-boot. 11407 */ 11408 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11409 { 11410 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11411 pci_ers_result_t result; 11412 11413 if (pci_enable_device_mem(pdev)) { 11414 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11415 result = PCI_ERS_RESULT_DISCONNECT; 11416 } else { 11417 smp_mb__before_atomic(); 11418 clear_bit(__IXGBE_DISABLED, &adapter->state); 11419 adapter->hw.hw_addr = adapter->io_addr; 11420 pci_set_master(pdev); 11421 pci_restore_state(pdev); 11422 pci_save_state(pdev); 11423 11424 pci_wake_from_d3(pdev, false); 11425 11426 ixgbe_reset(adapter); 11427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11428 result = PCI_ERS_RESULT_RECOVERED; 11429 } 11430 11431 return result; 11432 } 11433 11434 /** 11435 * ixgbe_io_resume - called when traffic can start flowing again. 11436 * @pdev: Pointer to PCI device 11437 * 11438 * This callback is called when the error recovery driver tells us that 11439 * its OK to resume normal operation. 11440 */ 11441 static void ixgbe_io_resume(struct pci_dev *pdev) 11442 { 11443 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11444 struct net_device *netdev = adapter->netdev; 11445 11446 #ifdef CONFIG_PCI_IOV 11447 if (adapter->vferr_refcount) { 11448 e_info(drv, "Resuming after VF err\n"); 11449 adapter->vferr_refcount--; 11450 return; 11451 } 11452 11453 #endif 11454 rtnl_lock(); 11455 if (netif_running(netdev)) 11456 ixgbe_open(netdev); 11457 11458 netif_device_attach(netdev); 11459 rtnl_unlock(); 11460 } 11461 11462 static const struct pci_error_handlers ixgbe_err_handler = { 11463 .error_detected = ixgbe_io_error_detected, 11464 .slot_reset = ixgbe_io_slot_reset, 11465 .resume = ixgbe_io_resume, 11466 }; 11467 11468 static struct pci_driver ixgbe_driver = { 11469 .name = ixgbe_driver_name, 11470 .id_table = ixgbe_pci_tbl, 11471 .probe = ixgbe_probe, 11472 .remove = ixgbe_remove, 11473 #ifdef CONFIG_PM 11474 .suspend = ixgbe_suspend, 11475 .resume = ixgbe_resume, 11476 #endif 11477 .shutdown = ixgbe_shutdown, 11478 .sriov_configure = ixgbe_pci_sriov_configure, 11479 .err_handler = &ixgbe_err_handler 11480 }; 11481 11482 /** 11483 * ixgbe_init_module - Driver Registration Routine 11484 * 11485 * ixgbe_init_module is the first routine called when the driver is 11486 * loaded. All it does is register with the PCI subsystem. 11487 **/ 11488 static int __init ixgbe_init_module(void) 11489 { 11490 int ret; 11491 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11492 pr_info("%s\n", ixgbe_copyright); 11493 11494 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11495 if (!ixgbe_wq) { 11496 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11497 return -ENOMEM; 11498 } 11499 11500 ixgbe_dbg_init(); 11501 11502 ret = pci_register_driver(&ixgbe_driver); 11503 if (ret) { 11504 destroy_workqueue(ixgbe_wq); 11505 ixgbe_dbg_exit(); 11506 return ret; 11507 } 11508 11509 #ifdef CONFIG_IXGBE_DCA 11510 dca_register_notify(&dca_notifier); 11511 #endif 11512 11513 return 0; 11514 } 11515 11516 module_init(ixgbe_init_module); 11517 11518 /** 11519 * ixgbe_exit_module - Driver Exit Cleanup Routine 11520 * 11521 * ixgbe_exit_module is called just before the driver is removed 11522 * from memory. 11523 **/ 11524 static void __exit ixgbe_exit_module(void) 11525 { 11526 #ifdef CONFIG_IXGBE_DCA 11527 dca_unregister_notify(&dca_notifier); 11528 #endif 11529 pci_unregister_driver(&ixgbe_driver); 11530 11531 ixgbe_dbg_exit(); 11532 if (ixgbe_wq) { 11533 destroy_workqueue(ixgbe_wq); 11534 ixgbe_wq = NULL; 11535 } 11536 } 11537 11538 #ifdef CONFIG_IXGBE_DCA 11539 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11540 void *p) 11541 { 11542 int ret_val; 11543 11544 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11545 __ixgbe_notify_dca); 11546 11547 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11548 } 11549 11550 #endif /* CONFIG_IXGBE_DCA */ 11551 11552 module_exit(ixgbe_exit_module); 11553 11554 /* ixgbe_main.c */ 11555