1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <generated/utsrelease.h> 32 #include <scsi/fc/fc_fcoe.h> 33 #include <net/udp_tunnel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/vxlan.h> 38 #include <net/mpls.h> 39 #include <net/xdp_sock_drv.h> 40 #include <net/xfrm.h> 41 42 #include "ixgbe.h" 43 #include "ixgbe_common.h" 44 #include "ixgbe_dcb_82599.h" 45 #include "ixgbe_phy.h" 46 #include "ixgbe_sriov.h" 47 #include "ixgbe_model.h" 48 #include "ixgbe_txrx_common.h" 49 50 char ixgbe_driver_name[] = "ixgbe"; 51 static const char ixgbe_driver_string[] = 52 "Intel(R) 10 Gigabit PCI Express Network Driver"; 53 #ifdef IXGBE_FCOE 54 char ixgbe_default_device_descr[] = 55 "Intel(R) 10 Gigabit Network Connection"; 56 #else 57 static char ixgbe_default_device_descr[] = 58 "Intel(R) 10 Gigabit Network Connection"; 59 #endif 60 static const char ixgbe_copyright[] = 61 "Copyright (c) 1999-2016 Intel Corporation."; 62 63 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 64 65 static const struct ixgbe_info *ixgbe_info_tbl[] = { 66 [board_82598] = &ixgbe_82598_info, 67 [board_82599] = &ixgbe_82599_info, 68 [board_X540] = &ixgbe_X540_info, 69 [board_X550] = &ixgbe_X550_info, 70 [board_X550EM_x] = &ixgbe_X550EM_x_info, 71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 72 [board_x550em_a] = &ixgbe_x550em_a_info, 73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 74 }; 75 76 /* ixgbe_pci_tbl - PCI Device ID Table 77 * 78 * Wildcard entries (PCI_ANY_ID) should come last 79 * Last entry must be all 0s 80 * 81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 82 * Class, Class Mask, private data (not used) } 83 */ 84 static const struct pci_device_id ixgbe_pci_tbl[] = { 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 132 /* required last entry */ 133 {0, } 134 }; 135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 136 137 #ifdef CONFIG_IXGBE_DCA 138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 139 void *p); 140 static struct notifier_block dca_notifier = { 141 .notifier_call = ixgbe_notify_dca, 142 .next = NULL, 143 .priority = 0 144 }; 145 #endif 146 147 #ifdef CONFIG_PCI_IOV 148 static unsigned int max_vfs; 149 module_param(max_vfs, uint, 0); 150 MODULE_PARM_DESC(max_vfs, 151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 152 #endif /* CONFIG_PCI_IOV */ 153 154 static unsigned int allow_unsupported_sfp; 155 module_param(allow_unsupported_sfp, uint, 0); 156 MODULE_PARM_DESC(allow_unsupported_sfp, 157 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 158 159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 160 static int debug = -1; 161 module_param(debug, int, 0); 162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 163 164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 166 MODULE_LICENSE("GPL v2"); 167 168 static struct workqueue_struct *ixgbe_wq; 169 170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 171 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 172 173 static const struct net_device_ops ixgbe_netdev_ops; 174 175 static bool netif_is_ixgbe(struct net_device *dev) 176 { 177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 178 } 179 180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 181 u32 reg, u16 *value) 182 { 183 struct pci_dev *parent_dev; 184 struct pci_bus *parent_bus; 185 186 parent_bus = adapter->pdev->bus->parent; 187 if (!parent_bus) 188 return -1; 189 190 parent_dev = parent_bus->self; 191 if (!parent_dev) 192 return -1; 193 194 if (!pci_is_pcie(parent_dev)) 195 return -1; 196 197 pcie_capability_read_word(parent_dev, reg, value); 198 if (*value == IXGBE_FAILED_READ_CFG_WORD && 199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 200 return -1; 201 return 0; 202 } 203 204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 205 { 206 struct ixgbe_hw *hw = &adapter->hw; 207 u16 link_status = 0; 208 int err; 209 210 hw->bus.type = ixgbe_bus_type_pci_express; 211 212 /* Get the negotiated link width and speed from PCI config space of the 213 * parent, as this device is behind a switch 214 */ 215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 216 217 /* assume caller will handle error case */ 218 if (err) 219 return err; 220 221 hw->bus.width = ixgbe_convert_bus_width(link_status); 222 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 223 224 return 0; 225 } 226 227 /** 228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 229 * @hw: hw specific details 230 * 231 * This function is used by probe to determine whether a device's PCI-Express 232 * bandwidth details should be gathered from the parent bus instead of from the 233 * device. Used to ensure that various locations all have the correct device ID 234 * checks. 235 */ 236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 237 { 238 switch (hw->device_id) { 239 case IXGBE_DEV_ID_82599_SFP_SF_QP: 240 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 241 return true; 242 default: 243 return false; 244 } 245 } 246 247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 248 int expected_gts) 249 { 250 struct ixgbe_hw *hw = &adapter->hw; 251 struct pci_dev *pdev; 252 253 /* Some devices are not connected over PCIe and thus do not negotiate 254 * speed. These devices do not have valid bus info, and thus any report 255 * we generate may not be correct. 256 */ 257 if (hw->bus.type == ixgbe_bus_type_internal) 258 return; 259 260 /* determine whether to use the parent device */ 261 if (ixgbe_pcie_from_parent(&adapter->hw)) 262 pdev = adapter->pdev->bus->parent->self; 263 else 264 pdev = adapter->pdev; 265 266 pcie_print_link_status(pdev); 267 } 268 269 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 270 { 271 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 272 !test_bit(__IXGBE_REMOVING, &adapter->state) && 273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 274 queue_work(ixgbe_wq, &adapter->service_task); 275 } 276 277 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 278 { 279 struct ixgbe_adapter *adapter = hw->back; 280 281 if (!hw->hw_addr) 282 return; 283 hw->hw_addr = NULL; 284 e_dev_err("Adapter removed\n"); 285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 286 ixgbe_service_event_schedule(adapter); 287 } 288 289 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 290 { 291 u8 __iomem *reg_addr; 292 u32 value; 293 int i; 294 295 reg_addr = READ_ONCE(hw->hw_addr); 296 if (ixgbe_removed(reg_addr)) 297 return IXGBE_FAILED_READ_REG; 298 299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 300 * so perform several status register reads to determine if the adapter 301 * has been removed. 302 */ 303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 304 value = readl(reg_addr + IXGBE_STATUS); 305 if (value != IXGBE_FAILED_READ_REG) 306 break; 307 mdelay(3); 308 } 309 310 if (value == IXGBE_FAILED_READ_REG) 311 ixgbe_remove_adapter(hw); 312 else 313 value = readl(reg_addr + reg); 314 return value; 315 } 316 317 /** 318 * ixgbe_read_reg - Read from device register 319 * @hw: hw specific details 320 * @reg: offset of register to read 321 * 322 * Returns : value read or IXGBE_FAILED_READ_REG if removed 323 * 324 * This function is used to read device registers. It checks for device 325 * removal by confirming any read that returns all ones by checking the 326 * status register value for all ones. This function avoids reading from 327 * the hardware if a removal was previously detected in which case it 328 * returns IXGBE_FAILED_READ_REG (all ones). 329 */ 330 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 331 { 332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 333 u32 value; 334 335 if (ixgbe_removed(reg_addr)) 336 return IXGBE_FAILED_READ_REG; 337 if (unlikely(hw->phy.nw_mng_if_sel & 338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 339 struct ixgbe_adapter *adapter; 340 int i; 341 342 for (i = 0; i < 200; ++i) { 343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 344 if (likely(!value)) 345 goto writes_completed; 346 if (value == IXGBE_FAILED_READ_REG) { 347 ixgbe_remove_adapter(hw); 348 return IXGBE_FAILED_READ_REG; 349 } 350 udelay(5); 351 } 352 353 adapter = hw->back; 354 e_warn(hw, "register writes incomplete %08x\n", value); 355 } 356 357 writes_completed: 358 value = readl(reg_addr + reg); 359 if (unlikely(value == IXGBE_FAILED_READ_REG)) 360 value = ixgbe_check_remove(hw, reg); 361 return value; 362 } 363 364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 365 { 366 u16 value; 367 368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 369 if (value == IXGBE_FAILED_READ_CFG_WORD) { 370 ixgbe_remove_adapter(hw); 371 return true; 372 } 373 return false; 374 } 375 376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 377 { 378 struct ixgbe_adapter *adapter = hw->back; 379 u16 value; 380 381 if (ixgbe_removed(hw->hw_addr)) 382 return IXGBE_FAILED_READ_CFG_WORD; 383 pci_read_config_word(adapter->pdev, reg, &value); 384 if (value == IXGBE_FAILED_READ_CFG_WORD && 385 ixgbe_check_cfg_remove(hw, adapter->pdev)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 return value; 388 } 389 390 #ifdef CONFIG_PCI_IOV 391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 392 { 393 struct ixgbe_adapter *adapter = hw->back; 394 u32 value; 395 396 if (ixgbe_removed(hw->hw_addr)) 397 return IXGBE_FAILED_READ_CFG_DWORD; 398 pci_read_config_dword(adapter->pdev, reg, &value); 399 if (value == IXGBE_FAILED_READ_CFG_DWORD && 400 ixgbe_check_cfg_remove(hw, adapter->pdev)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 return value; 403 } 404 #endif /* CONFIG_PCI_IOV */ 405 406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 407 { 408 struct ixgbe_adapter *adapter = hw->back; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return; 412 pci_write_config_word(adapter->pdev, reg, value); 413 } 414 415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 416 { 417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 418 419 /* flush memory to make sure state is correct before next watchdog */ 420 smp_mb__before_atomic(); 421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 422 } 423 424 struct ixgbe_reg_info { 425 u32 ofs; 426 char *name; 427 }; 428 429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 430 431 /* General Registers */ 432 {IXGBE_CTRL, "CTRL"}, 433 {IXGBE_STATUS, "STATUS"}, 434 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 435 436 /* Interrupt Registers */ 437 {IXGBE_EICR, "EICR"}, 438 439 /* RX Registers */ 440 {IXGBE_SRRCTL(0), "SRRCTL"}, 441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 442 {IXGBE_RDLEN(0), "RDLEN"}, 443 {IXGBE_RDH(0), "RDH"}, 444 {IXGBE_RDT(0), "RDT"}, 445 {IXGBE_RXDCTL(0), "RXDCTL"}, 446 {IXGBE_RDBAL(0), "RDBAL"}, 447 {IXGBE_RDBAH(0), "RDBAH"}, 448 449 /* TX Registers */ 450 {IXGBE_TDBAL(0), "TDBAL"}, 451 {IXGBE_TDBAH(0), "TDBAH"}, 452 {IXGBE_TDLEN(0), "TDLEN"}, 453 {IXGBE_TDH(0), "TDH"}, 454 {IXGBE_TDT(0), "TDT"}, 455 {IXGBE_TXDCTL(0), "TXDCTL"}, 456 457 /* List Terminator */ 458 { .name = NULL } 459 }; 460 461 462 /* 463 * ixgbe_regdump - register printout routine 464 */ 465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 466 { 467 int i; 468 char rname[16]; 469 u32 regs[64]; 470 471 switch (reginfo->ofs) { 472 case IXGBE_SRRCTL(0): 473 for (i = 0; i < 64; i++) 474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 475 break; 476 case IXGBE_DCA_RXCTRL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 479 break; 480 case IXGBE_RDLEN(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 483 break; 484 case IXGBE_RDH(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 487 break; 488 case IXGBE_RDT(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 491 break; 492 case IXGBE_RXDCTL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 495 break; 496 case IXGBE_RDBAL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 499 break; 500 case IXGBE_RDBAH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 503 break; 504 case IXGBE_TDBAL(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 507 break; 508 case IXGBE_TDBAH(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 511 break; 512 case IXGBE_TDLEN(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 515 break; 516 case IXGBE_TDH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 519 break; 520 case IXGBE_TDT(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 523 break; 524 case IXGBE_TXDCTL(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 527 break; 528 default: 529 pr_info("%-15s %08x\n", 530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 531 return; 532 } 533 534 i = 0; 535 while (i < 64) { 536 int j; 537 char buf[9 * 8 + 1]; 538 char *p = buf; 539 540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 541 for (j = 0; j < 8; j++) 542 p += sprintf(p, " %08x", regs[i++]); 543 pr_err("%-15s%s\n", rname, buf); 544 } 545 546 } 547 548 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 549 { 550 struct ixgbe_tx_buffer *tx_buffer; 551 552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 554 n, ring->next_to_use, ring->next_to_clean, 555 (u64)dma_unmap_addr(tx_buffer, dma), 556 dma_unmap_len(tx_buffer, len), 557 tx_buffer->next_to_watch, 558 (u64)tx_buffer->time_stamp); 559 } 560 561 /* 562 * ixgbe_dump - Print registers, tx-rings and rx-rings 563 */ 564 static void ixgbe_dump(struct ixgbe_adapter *adapter) 565 { 566 struct net_device *netdev = adapter->netdev; 567 struct ixgbe_hw *hw = &adapter->hw; 568 struct ixgbe_reg_info *reginfo; 569 int n = 0; 570 struct ixgbe_ring *ring; 571 struct ixgbe_tx_buffer *tx_buffer; 572 union ixgbe_adv_tx_desc *tx_desc; 573 struct my_u0 { u64 a; u64 b; } *u0; 574 struct ixgbe_ring *rx_ring; 575 union ixgbe_adv_rx_desc *rx_desc; 576 struct ixgbe_rx_buffer *rx_buffer_info; 577 int i = 0; 578 579 if (!netif_msg_hw(adapter)) 580 return; 581 582 /* Print netdevice Info */ 583 if (netdev) { 584 dev_info(&adapter->pdev->dev, "Net device Info\n"); 585 pr_info("Device Name state " 586 "trans_start\n"); 587 pr_info("%-15s %016lX %016lX\n", 588 netdev->name, 589 netdev->state, 590 dev_trans_start(netdev)); 591 } 592 593 /* Print Registers */ 594 dev_info(&adapter->pdev->dev, "Register Dump\n"); 595 pr_info(" Register Name Value\n"); 596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 597 reginfo->name; reginfo++) { 598 ixgbe_regdump(hw, reginfo); 599 } 600 601 /* Print TX Ring Summary */ 602 if (!netdev || !netif_running(netdev)) 603 return; 604 605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 606 pr_info(" %s %s %s %s\n", 607 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 608 "leng", "ntw", "timestamp"); 609 for (n = 0; n < adapter->num_tx_queues; n++) { 610 ring = adapter->tx_ring[n]; 611 ixgbe_print_buffer(ring, n); 612 } 613 614 for (n = 0; n < adapter->num_xdp_queues; n++) { 615 ring = adapter->xdp_ring[n]; 616 ixgbe_print_buffer(ring, n); 617 } 618 619 /* Print TX Rings */ 620 if (!netif_msg_tx_done(adapter)) 621 goto rx_ring_summary; 622 623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 624 625 /* Transmit Descriptor Formats 626 * 627 * 82598 Advanced Transmit Descriptor 628 * +--------------------------------------------------------------+ 629 * 0 | Buffer Address [63:0] | 630 * +--------------------------------------------------------------+ 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 632 * +--------------------------------------------------------------+ 633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 634 * 635 * 82598 Advanced Transmit Descriptor (Write-Back Format) 636 * +--------------------------------------------------------------+ 637 * 0 | RSV [63:0] | 638 * +--------------------------------------------------------------+ 639 * 8 | RSV | STA | NXTSEQ | 640 * +--------------------------------------------------------------+ 641 * 63 36 35 32 31 0 642 * 643 * 82599+ Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 650 * 651 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | RSV | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 */ 659 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 ring = adapter->tx_ring[n]; 662 pr_info("------------------------------------\n"); 663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 664 pr_info("------------------------------------\n"); 665 pr_info("%s%s %s %s %s %s\n", 666 "T [desc] [address 63:0 ] ", 667 "[PlPOIdStDDt Ln] [bi->dma ] ", 668 "leng", "ntw", "timestamp", "bi->skb"); 669 670 for (i = 0; ring->desc && (i < ring->count); i++) { 671 tx_desc = IXGBE_TX_DESC(ring, i); 672 tx_buffer = &ring->tx_buffer_info[i]; 673 u0 = (struct my_u0 *)tx_desc; 674 if (dma_unmap_len(tx_buffer, len) > 0) { 675 const char *ring_desc; 676 677 if (i == ring->next_to_use && 678 i == ring->next_to_clean) 679 ring_desc = " NTC/U"; 680 else if (i == ring->next_to_use) 681 ring_desc = " NTU"; 682 else if (i == ring->next_to_clean) 683 ring_desc = " NTC"; 684 else 685 ring_desc = ""; 686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 687 i, 688 le64_to_cpu((__force __le64)u0->a), 689 le64_to_cpu((__force __le64)u0->b), 690 (u64)dma_unmap_addr(tx_buffer, dma), 691 dma_unmap_len(tx_buffer, len), 692 tx_buffer->next_to_watch, 693 (u64)tx_buffer->time_stamp, 694 tx_buffer->skb, 695 ring_desc); 696 697 if (netif_msg_pktdata(adapter) && 698 tx_buffer->skb) 699 print_hex_dump(KERN_INFO, "", 700 DUMP_PREFIX_ADDRESS, 16, 1, 701 tx_buffer->skb->data, 702 dma_unmap_len(tx_buffer, len), 703 true); 704 } 705 } 706 } 707 708 /* Print RX Rings Summary */ 709 rx_ring_summary: 710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 711 pr_info("Queue [NTU] [NTC]\n"); 712 for (n = 0; n < adapter->num_rx_queues; n++) { 713 rx_ring = adapter->rx_ring[n]; 714 pr_info("%5d %5X %5X\n", 715 n, rx_ring->next_to_use, rx_ring->next_to_clean); 716 } 717 718 /* Print RX Rings */ 719 if (!netif_msg_rx_status(adapter)) 720 return; 721 722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 723 724 /* Receive Descriptor Formats 725 * 726 * 82598 Advanced Receive Descriptor (Read) Format 727 * 63 1 0 728 * +-----------------------------------------------------+ 729 * 0 | Packet Buffer Address [63:1] |A0/NSE| 730 * +----------------------------------------------+------+ 731 * 8 | Header Buffer Address [63:1] | DD | 732 * +-----------------------------------------------------+ 733 * 734 * 735 * 82598 Advanced Receive Descriptor (Write-Back) Format 736 * 737 * 63 48 47 32 31 30 21 20 16 15 4 3 0 738 * +------------------------------------------------------+ 739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 740 * | Packet | IP | | | | Type | Type | 741 * | Checksum | Ident | | | | | | 742 * +------------------------------------------------------+ 743 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 744 * +------------------------------------------------------+ 745 * 63 48 47 32 31 20 19 0 746 * 747 * 82599+ Advanced Receive Descriptor (Read) Format 748 * 63 1 0 749 * +-----------------------------------------------------+ 750 * 0 | Packet Buffer Address [63:1] |A0/NSE| 751 * +----------------------------------------------+------+ 752 * 8 | Header Buffer Address [63:1] | DD | 753 * +-----------------------------------------------------+ 754 * 755 * 756 * 82599+ Advanced Receive Descriptor (Write-Back) Format 757 * 758 * 63 48 47 32 31 30 21 20 17 16 4 3 0 759 * +------------------------------------------------------+ 760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 762 * |/ Flow Dir Flt ID | | | | | | 763 * +------------------------------------------------------+ 764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 765 * +------------------------------------------------------+ 766 * 63 48 47 32 31 20 19 0 767 */ 768 769 for (n = 0; n < adapter->num_rx_queues; n++) { 770 rx_ring = adapter->rx_ring[n]; 771 pr_info("------------------------------------\n"); 772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 773 pr_info("------------------------------------\n"); 774 pr_info("%s%s%s\n", 775 "R [desc] [ PktBuf A0] ", 776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 777 "<-- Adv Rx Read format"); 778 pr_info("%s%s%s\n", 779 "RWB[desc] [PcsmIpSHl PtRs] ", 780 "[vl er S cks ln] ---------------- [bi->skb ] ", 781 "<-- Adv Rx Write-Back format"); 782 783 for (i = 0; i < rx_ring->count; i++) { 784 const char *ring_desc; 785 786 if (i == rx_ring->next_to_use) 787 ring_desc = " NTU"; 788 else if (i == rx_ring->next_to_clean) 789 ring_desc = " NTC"; 790 else 791 ring_desc = ""; 792 793 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 794 rx_desc = IXGBE_RX_DESC(rx_ring, i); 795 u0 = (struct my_u0 *)rx_desc; 796 if (rx_desc->wb.upper.length) { 797 /* Descriptor Done */ 798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 799 i, 800 le64_to_cpu((__force __le64)u0->a), 801 le64_to_cpu((__force __le64)u0->b), 802 rx_buffer_info->skb, 803 ring_desc); 804 } else { 805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 806 i, 807 le64_to_cpu((__force __le64)u0->a), 808 le64_to_cpu((__force __le64)u0->b), 809 (u64)rx_buffer_info->dma, 810 rx_buffer_info->skb, 811 ring_desc); 812 813 if (netif_msg_pktdata(adapter) && 814 rx_buffer_info->dma) { 815 print_hex_dump(KERN_INFO, "", 816 DUMP_PREFIX_ADDRESS, 16, 1, 817 page_address(rx_buffer_info->page) + 818 rx_buffer_info->page_offset, 819 ixgbe_rx_bufsz(rx_ring), true); 820 } 821 } 822 } 823 } 824 } 825 826 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 827 { 828 u32 ctrl_ext; 829 830 /* Let firmware take over control of h/w */ 831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 834 } 835 836 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 837 { 838 u32 ctrl_ext; 839 840 /* Let firmware know the driver has taken over */ 841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 844 } 845 846 /** 847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 848 * @adapter: pointer to adapter struct 849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 850 * @queue: queue to map the corresponding interrupt to 851 * @msix_vector: the vector to map to the corresponding queue 852 * 853 */ 854 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 855 u8 queue, u8 msix_vector) 856 { 857 u32 ivar, index; 858 struct ixgbe_hw *hw = &adapter->hw; 859 switch (hw->mac.type) { 860 case ixgbe_mac_82598EB: 861 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 862 if (direction == -1) 863 direction = 0; 864 index = (((direction * 64) + queue) >> 2) & 0x1F; 865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 866 ivar &= ~(0xFF << (8 * (queue & 0x3))); 867 ivar |= (msix_vector << (8 * (queue & 0x3))); 868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 869 break; 870 case ixgbe_mac_82599EB: 871 case ixgbe_mac_X540: 872 case ixgbe_mac_X550: 873 case ixgbe_mac_X550EM_x: 874 case ixgbe_mac_x550em_a: 875 if (direction == -1) { 876 /* other causes */ 877 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 878 index = ((queue & 1) * 8); 879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 880 ivar &= ~(0xFF << index); 881 ivar |= (msix_vector << index); 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 883 break; 884 } else { 885 /* tx or rx causes */ 886 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 887 index = ((16 * (queue & 1)) + (8 * direction)); 888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 889 ivar &= ~(0xFF << index); 890 ivar |= (msix_vector << index); 891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 892 break; 893 } 894 default: 895 break; 896 } 897 } 898 899 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 900 u64 qmask) 901 { 902 u32 mask; 903 904 switch (adapter->hw.mac.type) { 905 case ixgbe_mac_82598EB: 906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 908 break; 909 case ixgbe_mac_82599EB: 910 case ixgbe_mac_X540: 911 case ixgbe_mac_X550: 912 case ixgbe_mac_X550EM_x: 913 case ixgbe_mac_x550em_a: 914 mask = (qmask & 0xFFFFFFFF); 915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 916 mask = (qmask >> 32); 917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 918 break; 919 default: 920 break; 921 } 922 } 923 924 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 925 { 926 struct ixgbe_hw *hw = &adapter->hw; 927 struct ixgbe_hw_stats *hwstats = &adapter->stats; 928 int i; 929 u32 data; 930 931 if ((hw->fc.current_mode != ixgbe_fc_full) && 932 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 933 return; 934 935 switch (hw->mac.type) { 936 case ixgbe_mac_82598EB: 937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 938 break; 939 default: 940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 941 } 942 hwstats->lxoffrxc += data; 943 944 /* refill credits (no tx hang) if we received xoff */ 945 if (!data) 946 return; 947 948 for (i = 0; i < adapter->num_tx_queues; i++) 949 clear_bit(__IXGBE_HANG_CHECK_ARMED, 950 &adapter->tx_ring[i]->state); 951 952 for (i = 0; i < adapter->num_xdp_queues; i++) 953 clear_bit(__IXGBE_HANG_CHECK_ARMED, 954 &adapter->xdp_ring[i]->state); 955 } 956 957 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 958 { 959 struct ixgbe_hw *hw = &adapter->hw; 960 struct ixgbe_hw_stats *hwstats = &adapter->stats; 961 u32 xoff[8] = {0}; 962 u8 tc; 963 int i; 964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 965 966 if (adapter->ixgbe_ieee_pfc) 967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 968 969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 970 ixgbe_update_xoff_rx_lfc(adapter); 971 return; 972 } 973 974 /* update stats for each tc, only valid with PFC enabled */ 975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 976 u32 pxoffrxc; 977 978 switch (hw->mac.type) { 979 case ixgbe_mac_82598EB: 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 981 break; 982 default: 983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 984 } 985 hwstats->pxoffrxc[i] += pxoffrxc; 986 /* Get the TC for given UP */ 987 tc = netdev_get_prio_tc_map(adapter->netdev, i); 988 xoff[tc] += pxoffrxc; 989 } 990 991 /* disarm tx queues that have received xoff frames */ 992 for (i = 0; i < adapter->num_tx_queues; i++) { 993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 994 995 tc = tx_ring->dcb_tc; 996 if (xoff[tc]) 997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 998 } 999 1000 for (i = 0; i < adapter->num_xdp_queues; i++) { 1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1002 1003 tc = xdp_ring->dcb_tc; 1004 if (xoff[tc]) 1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1006 } 1007 } 1008 1009 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1010 { 1011 return ring->stats.packets; 1012 } 1013 1014 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1015 { 1016 unsigned int head, tail; 1017 1018 head = ring->next_to_clean; 1019 tail = ring->next_to_use; 1020 1021 return ((head <= tail) ? tail : tail + ring->count) - head; 1022 } 1023 1024 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1025 { 1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1029 1030 clear_check_for_tx_hang(tx_ring); 1031 1032 /* 1033 * Check for a hung queue, but be thorough. This verifies 1034 * that a transmit has been completed since the previous 1035 * check AND there is at least one packet pending. The 1036 * ARMED bit is set to indicate a potential hang. The 1037 * bit is cleared if a pause frame is received to remove 1038 * false hang detection due to PFC or 802.3x frames. By 1039 * requiring this to fail twice we avoid races with 1040 * pfc clearing the ARMED bit and conditions where we 1041 * run the check_tx_hang logic with a transmit completion 1042 * pending but without time to complete it yet. 1043 */ 1044 if (tx_done_old == tx_done && tx_pending) 1045 /* make sure it is true for two checks in a row */ 1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1047 &tx_ring->state); 1048 /* update completed stats and continue */ 1049 tx_ring->tx_stats.tx_done_old = tx_done; 1050 /* reset the countdown */ 1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1052 1053 return false; 1054 } 1055 1056 /** 1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1058 * @adapter: driver private struct 1059 **/ 1060 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1061 { 1062 1063 /* Do the reset outside of interrupt context */ 1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1066 e_warn(drv, "initiating reset due to tx timeout\n"); 1067 ixgbe_service_event_schedule(adapter); 1068 } 1069 } 1070 1071 /** 1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1073 * @netdev: network interface device structure 1074 * @queue_index: Tx queue to set 1075 * @maxrate: desired maximum transmit bitrate 1076 **/ 1077 static int ixgbe_tx_maxrate(struct net_device *netdev, 1078 int queue_index, u32 maxrate) 1079 { 1080 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1081 struct ixgbe_hw *hw = &adapter->hw; 1082 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1083 1084 if (!maxrate) 1085 return 0; 1086 1087 /* Calculate the rate factor values to set */ 1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1089 bcnrc_val /= maxrate; 1090 1091 /* clear everything but the rate factor */ 1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1093 IXGBE_RTTBCNRC_RF_DEC_MASK; 1094 1095 /* enable the rate scheduler */ 1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1097 1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1100 1101 return 0; 1102 } 1103 1104 /** 1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1106 * @q_vector: structure containing interrupt and ring information 1107 * @tx_ring: tx ring to clean 1108 * @napi_budget: Used to determine if we are in netpoll 1109 **/ 1110 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1111 struct ixgbe_ring *tx_ring, int napi_budget) 1112 { 1113 struct ixgbe_adapter *adapter = q_vector->adapter; 1114 struct ixgbe_tx_buffer *tx_buffer; 1115 union ixgbe_adv_tx_desc *tx_desc; 1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1117 unsigned int budget = q_vector->tx.work_limit; 1118 unsigned int i = tx_ring->next_to_clean; 1119 1120 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1121 return true; 1122 1123 tx_buffer = &tx_ring->tx_buffer_info[i]; 1124 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1125 i -= tx_ring->count; 1126 1127 do { 1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1129 1130 /* if next_to_watch is not set then there is no work pending */ 1131 if (!eop_desc) 1132 break; 1133 1134 /* prevent any other reads prior to eop_desc */ 1135 smp_rmb(); 1136 1137 /* if DD is not set pending work has not been completed */ 1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1139 break; 1140 1141 /* clear next_to_watch to prevent false hangs */ 1142 tx_buffer->next_to_watch = NULL; 1143 1144 /* update the statistics for this packet */ 1145 total_bytes += tx_buffer->bytecount; 1146 total_packets += tx_buffer->gso_segs; 1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1148 total_ipsec++; 1149 1150 /* free the skb */ 1151 if (ring_is_xdp(tx_ring)) 1152 xdp_return_frame(tx_buffer->xdpf); 1153 else 1154 napi_consume_skb(tx_buffer->skb, napi_budget); 1155 1156 /* unmap skb header data */ 1157 dma_unmap_single(tx_ring->dev, 1158 dma_unmap_addr(tx_buffer, dma), 1159 dma_unmap_len(tx_buffer, len), 1160 DMA_TO_DEVICE); 1161 1162 /* clear tx_buffer data */ 1163 dma_unmap_len_set(tx_buffer, len, 0); 1164 1165 /* unmap remaining buffers */ 1166 while (tx_desc != eop_desc) { 1167 tx_buffer++; 1168 tx_desc++; 1169 i++; 1170 if (unlikely(!i)) { 1171 i -= tx_ring->count; 1172 tx_buffer = tx_ring->tx_buffer_info; 1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1174 } 1175 1176 /* unmap any remaining paged data */ 1177 if (dma_unmap_len(tx_buffer, len)) { 1178 dma_unmap_page(tx_ring->dev, 1179 dma_unmap_addr(tx_buffer, dma), 1180 dma_unmap_len(tx_buffer, len), 1181 DMA_TO_DEVICE); 1182 dma_unmap_len_set(tx_buffer, len, 0); 1183 } 1184 } 1185 1186 /* move us one more past the eop_desc for start of next pkt */ 1187 tx_buffer++; 1188 tx_desc++; 1189 i++; 1190 if (unlikely(!i)) { 1191 i -= tx_ring->count; 1192 tx_buffer = tx_ring->tx_buffer_info; 1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1194 } 1195 1196 /* issue prefetch for next Tx descriptor */ 1197 prefetch(tx_desc); 1198 1199 /* update budget accounting */ 1200 budget--; 1201 } while (likely(budget)); 1202 1203 i += tx_ring->count; 1204 tx_ring->next_to_clean = i; 1205 u64_stats_update_begin(&tx_ring->syncp); 1206 tx_ring->stats.bytes += total_bytes; 1207 tx_ring->stats.packets += total_packets; 1208 u64_stats_update_end(&tx_ring->syncp); 1209 q_vector->tx.total_bytes += total_bytes; 1210 q_vector->tx.total_packets += total_packets; 1211 adapter->tx_ipsec += total_ipsec; 1212 1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1214 /* schedule immediate reset if we believe we hung */ 1215 struct ixgbe_hw *hw = &adapter->hw; 1216 e_err(drv, "Detected Tx Unit Hang %s\n" 1217 " Tx Queue <%d>\n" 1218 " TDH, TDT <%x>, <%x>\n" 1219 " next_to_use <%x>\n" 1220 " next_to_clean <%x>\n" 1221 "tx_buffer_info[next_to_clean]\n" 1222 " time_stamp <%lx>\n" 1223 " jiffies <%lx>\n", 1224 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1225 tx_ring->queue_index, 1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1228 tx_ring->next_to_use, i, 1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1230 1231 if (!ring_is_xdp(tx_ring)) 1232 netif_stop_subqueue(tx_ring->netdev, 1233 tx_ring->queue_index); 1234 1235 e_info(probe, 1236 "tx hang %d detected on queue %d, resetting adapter\n", 1237 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1238 1239 /* schedule immediate reset if we believe we hung */ 1240 ixgbe_tx_timeout_reset(adapter); 1241 1242 /* the adapter is about to reset, no point in enabling stuff */ 1243 return true; 1244 } 1245 1246 if (ring_is_xdp(tx_ring)) 1247 return !!budget; 1248 1249 netdev_tx_completed_queue(txring_txq(tx_ring), 1250 total_packets, total_bytes); 1251 1252 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1255 /* Make sure that anybody stopping the queue after this 1256 * sees the new next_to_clean. 1257 */ 1258 smp_mb(); 1259 if (__netif_subqueue_stopped(tx_ring->netdev, 1260 tx_ring->queue_index) 1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1262 netif_wake_subqueue(tx_ring->netdev, 1263 tx_ring->queue_index); 1264 ++tx_ring->tx_stats.restart_queue; 1265 } 1266 } 1267 1268 return !!budget; 1269 } 1270 1271 #ifdef CONFIG_IXGBE_DCA 1272 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1273 struct ixgbe_ring *tx_ring, 1274 int cpu) 1275 { 1276 struct ixgbe_hw *hw = &adapter->hw; 1277 u32 txctrl = 0; 1278 u16 reg_offset; 1279 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1281 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1282 1283 switch (hw->mac.type) { 1284 case ixgbe_mac_82598EB: 1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1286 break; 1287 case ixgbe_mac_82599EB: 1288 case ixgbe_mac_X540: 1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1291 break; 1292 default: 1293 /* for unknown hardware do not write register */ 1294 return; 1295 } 1296 1297 /* 1298 * We can enable relaxed ordering for reads, but not writes when 1299 * DCA is enabled. This is due to a known issue in some chipsets 1300 * which will cause the DCA tag to be cleared. 1301 */ 1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1305 1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1307 } 1308 1309 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1310 struct ixgbe_ring *rx_ring, 1311 int cpu) 1312 { 1313 struct ixgbe_hw *hw = &adapter->hw; 1314 u32 rxctrl = 0; 1315 u8 reg_idx = rx_ring->reg_idx; 1316 1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1319 1320 switch (hw->mac.type) { 1321 case ixgbe_mac_82599EB: 1322 case ixgbe_mac_X540: 1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1324 break; 1325 default: 1326 break; 1327 } 1328 1329 /* 1330 * We can enable relaxed ordering for reads, but not writes when 1331 * DCA is enabled. This is due to a known issue in some chipsets 1332 * which will cause the DCA tag to be cleared. 1333 */ 1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1337 1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1339 } 1340 1341 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1342 { 1343 struct ixgbe_adapter *adapter = q_vector->adapter; 1344 struct ixgbe_ring *ring; 1345 int cpu = get_cpu(); 1346 1347 if (q_vector->cpu == cpu) 1348 goto out_no_update; 1349 1350 ixgbe_for_each_ring(ring, q_vector->tx) 1351 ixgbe_update_tx_dca(adapter, ring, cpu); 1352 1353 ixgbe_for_each_ring(ring, q_vector->rx) 1354 ixgbe_update_rx_dca(adapter, ring, cpu); 1355 1356 q_vector->cpu = cpu; 1357 out_no_update: 1358 put_cpu(); 1359 } 1360 1361 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1362 { 1363 int i; 1364 1365 /* always use CB2 mode, difference is masked in the CB driver */ 1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1368 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1369 else 1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1371 IXGBE_DCA_CTRL_DCA_DISABLE); 1372 1373 for (i = 0; i < adapter->num_q_vectors; i++) { 1374 adapter->q_vector[i]->cpu = -1; 1375 ixgbe_update_dca(adapter->q_vector[i]); 1376 } 1377 } 1378 1379 static int __ixgbe_notify_dca(struct device *dev, void *data) 1380 { 1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1382 unsigned long event = *(unsigned long *)data; 1383 1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1385 return 0; 1386 1387 switch (event) { 1388 case DCA_PROVIDER_ADD: 1389 /* if we're already enabled, don't do it again */ 1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1391 break; 1392 if (dca_add_requester(dev) == 0) { 1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1395 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1396 break; 1397 } 1398 fallthrough; /* DCA is disabled. */ 1399 case DCA_PROVIDER_REMOVE: 1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1401 dca_remove_requester(dev); 1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1404 IXGBE_DCA_CTRL_DCA_DISABLE); 1405 } 1406 break; 1407 } 1408 1409 return 0; 1410 } 1411 1412 #endif /* CONFIG_IXGBE_DCA */ 1413 1414 #define IXGBE_RSS_L4_TYPES_MASK \ 1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1419 1420 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1421 union ixgbe_adv_rx_desc *rx_desc, 1422 struct sk_buff *skb) 1423 { 1424 u16 rss_type; 1425 1426 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1427 return; 1428 1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1430 IXGBE_RXDADV_RSSTYPE_MASK; 1431 1432 if (!rss_type) 1433 return; 1434 1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1438 } 1439 1440 #ifdef IXGBE_FCOE 1441 /** 1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1443 * @ring: structure containing ring specific data 1444 * @rx_desc: advanced rx descriptor 1445 * 1446 * Returns : true if it is FCoE pkt 1447 */ 1448 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1449 union ixgbe_adv_rx_desc *rx_desc) 1450 { 1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1452 1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1457 } 1458 1459 #endif /* IXGBE_FCOE */ 1460 /** 1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1462 * @ring: structure containing ring specific data 1463 * @rx_desc: current Rx descriptor being processed 1464 * @skb: skb currently being received and modified 1465 **/ 1466 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1467 union ixgbe_adv_rx_desc *rx_desc, 1468 struct sk_buff *skb) 1469 { 1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1471 bool encap_pkt = false; 1472 1473 skb_checksum_none_assert(skb); 1474 1475 /* Rx csum disabled */ 1476 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1477 return; 1478 1479 /* check for VXLAN and Geneve packets */ 1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1481 encap_pkt = true; 1482 skb->encapsulation = 1; 1483 } 1484 1485 /* if IP and error */ 1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1488 ring->rx_stats.csum_err++; 1489 return; 1490 } 1491 1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1493 return; 1494 1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1496 /* 1497 * 82599 errata, UDP frames with a 0 checksum can be marked as 1498 * checksum errors. 1499 */ 1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1502 return; 1503 1504 ring->rx_stats.csum_err++; 1505 return; 1506 } 1507 1508 /* It must be a TCP or UDP packet with a valid checksum */ 1509 skb->ip_summed = CHECKSUM_UNNECESSARY; 1510 if (encap_pkt) { 1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1512 return; 1513 1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1515 skb->ip_summed = CHECKSUM_NONE; 1516 return; 1517 } 1518 /* If we checked the outer header let the stack know */ 1519 skb->csum_level = 1; 1520 } 1521 } 1522 1523 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1524 { 1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1526 } 1527 1528 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1529 struct ixgbe_rx_buffer *bi) 1530 { 1531 struct page *page = bi->page; 1532 dma_addr_t dma; 1533 1534 /* since we are recycling buffers we should seldom need to alloc */ 1535 if (likely(page)) 1536 return true; 1537 1538 /* alloc new page for storage */ 1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1540 if (unlikely(!page)) { 1541 rx_ring->rx_stats.alloc_rx_page_failed++; 1542 return false; 1543 } 1544 1545 /* map page for use */ 1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1547 ixgbe_rx_pg_size(rx_ring), 1548 DMA_FROM_DEVICE, 1549 IXGBE_RX_DMA_ATTR); 1550 1551 /* 1552 * if mapping failed free memory back to system since 1553 * there isn't much point in holding memory we can't use 1554 */ 1555 if (dma_mapping_error(rx_ring->dev, dma)) { 1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1557 1558 rx_ring->rx_stats.alloc_rx_page_failed++; 1559 return false; 1560 } 1561 1562 bi->dma = dma; 1563 bi->page = page; 1564 bi->page_offset = rx_ring->rx_offset; 1565 page_ref_add(page, USHRT_MAX - 1); 1566 bi->pagecnt_bias = USHRT_MAX; 1567 rx_ring->rx_stats.alloc_rx_page++; 1568 1569 return true; 1570 } 1571 1572 /** 1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1574 * @rx_ring: ring to place buffers on 1575 * @cleaned_count: number of buffers to replace 1576 **/ 1577 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1578 { 1579 union ixgbe_adv_rx_desc *rx_desc; 1580 struct ixgbe_rx_buffer *bi; 1581 u16 i = rx_ring->next_to_use; 1582 u16 bufsz; 1583 1584 /* nothing to do */ 1585 if (!cleaned_count) 1586 return; 1587 1588 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1589 bi = &rx_ring->rx_buffer_info[i]; 1590 i -= rx_ring->count; 1591 1592 bufsz = ixgbe_rx_bufsz(rx_ring); 1593 1594 do { 1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1596 break; 1597 1598 /* sync the buffer for use by the device */ 1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1600 bi->page_offset, bufsz, 1601 DMA_FROM_DEVICE); 1602 1603 /* 1604 * Refresh the desc even if buffer_addrs didn't change 1605 * because each write-back erases this info. 1606 */ 1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1608 1609 rx_desc++; 1610 bi++; 1611 i++; 1612 if (unlikely(!i)) { 1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1614 bi = rx_ring->rx_buffer_info; 1615 i -= rx_ring->count; 1616 } 1617 1618 /* clear the length for the next_to_use descriptor */ 1619 rx_desc->wb.upper.length = 0; 1620 1621 cleaned_count--; 1622 } while (cleaned_count); 1623 1624 i += rx_ring->count; 1625 1626 if (rx_ring->next_to_use != i) { 1627 rx_ring->next_to_use = i; 1628 1629 /* update next to alloc since we have filled the ring */ 1630 rx_ring->next_to_alloc = i; 1631 1632 /* Force memory writes to complete before letting h/w 1633 * know there are new descriptors to fetch. (Only 1634 * applicable for weak-ordered memory model archs, 1635 * such as IA-64). 1636 */ 1637 wmb(); 1638 writel(i, rx_ring->tail); 1639 } 1640 } 1641 1642 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1643 struct sk_buff *skb) 1644 { 1645 u16 hdr_len = skb_headlen(skb); 1646 1647 /* set gso_size to avoid messing up TCP MSS */ 1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1649 IXGBE_CB(skb)->append_cnt); 1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1651 } 1652 1653 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1654 struct sk_buff *skb) 1655 { 1656 /* if append_cnt is 0 then frame is not RSC */ 1657 if (!IXGBE_CB(skb)->append_cnt) 1658 return; 1659 1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1661 rx_ring->rx_stats.rsc_flush++; 1662 1663 ixgbe_set_rsc_gso_size(rx_ring, skb); 1664 1665 /* gso_size is computed using append_cnt so always clear it last */ 1666 IXGBE_CB(skb)->append_cnt = 0; 1667 } 1668 1669 /** 1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1671 * @rx_ring: rx descriptor ring packet is being transacted on 1672 * @rx_desc: pointer to the EOP Rx descriptor 1673 * @skb: pointer to current skb being populated 1674 * 1675 * This function checks the ring, descriptor, and packet information in 1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1677 * other fields within the skb. 1678 **/ 1679 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1680 union ixgbe_adv_rx_desc *rx_desc, 1681 struct sk_buff *skb) 1682 { 1683 struct net_device *dev = rx_ring->netdev; 1684 u32 flags = rx_ring->q_vector->adapter->flags; 1685 1686 ixgbe_update_rsc_stats(rx_ring, skb); 1687 1688 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1689 1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1691 1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1694 1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1699 } 1700 1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1703 1704 /* record Rx queue, or update MACVLAN statistics */ 1705 if (netif_is_ixgbe(dev)) 1706 skb_record_rx_queue(skb, rx_ring->queue_index); 1707 else 1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1709 false); 1710 1711 skb->protocol = eth_type_trans(skb, dev); 1712 } 1713 1714 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1715 struct sk_buff *skb) 1716 { 1717 napi_gro_receive(&q_vector->napi, skb); 1718 } 1719 1720 /** 1721 * ixgbe_is_non_eop - process handling of non-EOP buffers 1722 * @rx_ring: Rx ring being processed 1723 * @rx_desc: Rx descriptor for current buffer 1724 * @skb: Current socket buffer containing buffer in progress 1725 * 1726 * This function updates next to clean. If the buffer is an EOP buffer 1727 * this function exits returning false, otherwise it will place the 1728 * sk_buff in the next buffer to be chained and return true indicating 1729 * that this is in fact a non-EOP buffer. 1730 **/ 1731 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1732 union ixgbe_adv_rx_desc *rx_desc, 1733 struct sk_buff *skb) 1734 { 1735 u32 ntc = rx_ring->next_to_clean + 1; 1736 1737 /* fetch, update, and store next to clean */ 1738 ntc = (ntc < rx_ring->count) ? ntc : 0; 1739 rx_ring->next_to_clean = ntc; 1740 1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1742 1743 /* update RSC append count if present */ 1744 if (ring_is_rsc_enabled(rx_ring)) { 1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1747 1748 if (unlikely(rsc_enabled)) { 1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1750 1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1753 1754 /* update ntc based on RSC value */ 1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1756 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1758 } 1759 } 1760 1761 /* if we are the last buffer then there is nothing else to do */ 1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1763 return false; 1764 1765 /* place skb in next buffer to be received */ 1766 rx_ring->rx_buffer_info[ntc].skb = skb; 1767 rx_ring->rx_stats.non_eop_descs++; 1768 1769 return true; 1770 } 1771 1772 /** 1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1774 * @rx_ring: rx descriptor ring packet is being transacted on 1775 * @skb: pointer to current skb being adjusted 1776 * 1777 * This function is an ixgbe specific version of __pskb_pull_tail. The 1778 * main difference between this version and the original function is that 1779 * this function can make several assumptions about the state of things 1780 * that allow for significant optimizations versus the standard function. 1781 * As a result we can do things like drop a frag and maintain an accurate 1782 * truesize for the skb. 1783 */ 1784 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1785 struct sk_buff *skb) 1786 { 1787 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1788 unsigned char *va; 1789 unsigned int pull_len; 1790 1791 /* 1792 * it is valid to use page_address instead of kmap since we are 1793 * working with pages allocated out of the lomem pool per 1794 * alloc_page(GFP_ATOMIC) 1795 */ 1796 va = skb_frag_address(frag); 1797 1798 /* 1799 * we need the header to contain the greater of either ETH_HLEN or 1800 * 60 bytes if the skb->len is less than 60 for skb_pad. 1801 */ 1802 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1803 1804 /* align pull length to size of long to optimize memcpy performance */ 1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1806 1807 /* update all of the pointers */ 1808 skb_frag_size_sub(frag, pull_len); 1809 skb_frag_off_add(frag, pull_len); 1810 skb->data_len -= pull_len; 1811 skb->tail += pull_len; 1812 } 1813 1814 /** 1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1816 * @rx_ring: rx descriptor ring packet is being transacted on 1817 * @skb: pointer to current skb being updated 1818 * 1819 * This function provides a basic DMA sync up for the first fragment of an 1820 * skb. The reason for doing this is that the first fragment cannot be 1821 * unmapped until we have reached the end of packet descriptor for a buffer 1822 * chain. 1823 */ 1824 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1825 struct sk_buff *skb) 1826 { 1827 if (ring_uses_build_skb(rx_ring)) { 1828 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1829 1830 dma_sync_single_range_for_cpu(rx_ring->dev, 1831 IXGBE_CB(skb)->dma, 1832 offset, 1833 skb_headlen(skb), 1834 DMA_FROM_DEVICE); 1835 } else { 1836 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1837 1838 dma_sync_single_range_for_cpu(rx_ring->dev, 1839 IXGBE_CB(skb)->dma, 1840 skb_frag_off(frag), 1841 skb_frag_size(frag), 1842 DMA_FROM_DEVICE); 1843 } 1844 1845 /* If the page was released, just unmap it. */ 1846 if (unlikely(IXGBE_CB(skb)->page_released)) { 1847 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1848 ixgbe_rx_pg_size(rx_ring), 1849 DMA_FROM_DEVICE, 1850 IXGBE_RX_DMA_ATTR); 1851 } 1852 } 1853 1854 /** 1855 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1856 * @rx_ring: rx descriptor ring packet is being transacted on 1857 * @rx_desc: pointer to the EOP Rx descriptor 1858 * @skb: pointer to current skb being fixed 1859 * 1860 * Check if the skb is valid in the XDP case it will be an error pointer. 1861 * Return true in this case to abort processing and advance to next 1862 * descriptor. 1863 * 1864 * Check for corrupted packet headers caused by senders on the local L2 1865 * embedded NIC switch not setting up their Tx Descriptors right. These 1866 * should be very rare. 1867 * 1868 * Also address the case where we are pulling data in on pages only 1869 * and as such no data is present in the skb header. 1870 * 1871 * In addition if skb is not at least 60 bytes we need to pad it so that 1872 * it is large enough to qualify as a valid Ethernet frame. 1873 * 1874 * Returns true if an error was encountered and skb was freed. 1875 **/ 1876 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1877 union ixgbe_adv_rx_desc *rx_desc, 1878 struct sk_buff *skb) 1879 { 1880 struct net_device *netdev = rx_ring->netdev; 1881 1882 /* XDP packets use error pointer so abort at this point */ 1883 if (IS_ERR(skb)) 1884 return true; 1885 1886 /* Verify netdev is present, and that packet does not have any 1887 * errors that would be unacceptable to the netdev. 1888 */ 1889 if (!netdev || 1890 (unlikely(ixgbe_test_staterr(rx_desc, 1891 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1892 !(netdev->features & NETIF_F_RXALL)))) { 1893 dev_kfree_skb_any(skb); 1894 return true; 1895 } 1896 1897 /* place header in linear portion of buffer */ 1898 if (!skb_headlen(skb)) 1899 ixgbe_pull_tail(rx_ring, skb); 1900 1901 #ifdef IXGBE_FCOE 1902 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1903 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1904 return false; 1905 1906 #endif 1907 /* if eth_skb_pad returns an error the skb was freed */ 1908 if (eth_skb_pad(skb)) 1909 return true; 1910 1911 return false; 1912 } 1913 1914 /** 1915 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1916 * @rx_ring: rx descriptor ring to store buffers on 1917 * @old_buff: donor buffer to have page reused 1918 * 1919 * Synchronizes page for reuse by the adapter 1920 **/ 1921 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1922 struct ixgbe_rx_buffer *old_buff) 1923 { 1924 struct ixgbe_rx_buffer *new_buff; 1925 u16 nta = rx_ring->next_to_alloc; 1926 1927 new_buff = &rx_ring->rx_buffer_info[nta]; 1928 1929 /* update, and store next to alloc */ 1930 nta++; 1931 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1932 1933 /* Transfer page from old buffer to new buffer. 1934 * Move each member individually to avoid possible store 1935 * forwarding stalls and unnecessary copy of skb. 1936 */ 1937 new_buff->dma = old_buff->dma; 1938 new_buff->page = old_buff->page; 1939 new_buff->page_offset = old_buff->page_offset; 1940 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1941 } 1942 1943 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 1944 int rx_buffer_pgcnt) 1945 { 1946 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1947 struct page *page = rx_buffer->page; 1948 1949 /* avoid re-using remote and pfmemalloc pages */ 1950 if (!dev_page_is_reusable(page)) 1951 return false; 1952 1953 #if (PAGE_SIZE < 8192) 1954 /* if we are only owner of page we can reuse it */ 1955 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1956 return false; 1957 #else 1958 /* The last offset is a bit aggressive in that we assume the 1959 * worst case of FCoE being enabled and using a 3K buffer. 1960 * However this should have minimal impact as the 1K extra is 1961 * still less than one buffer in size. 1962 */ 1963 #define IXGBE_LAST_OFFSET \ 1964 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1965 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1966 return false; 1967 #endif 1968 1969 /* If we have drained the page fragment pool we need to update 1970 * the pagecnt_bias and page count so that we fully restock the 1971 * number of references the driver holds. 1972 */ 1973 if (unlikely(pagecnt_bias == 1)) { 1974 page_ref_add(page, USHRT_MAX - 1); 1975 rx_buffer->pagecnt_bias = USHRT_MAX; 1976 } 1977 1978 return true; 1979 } 1980 1981 /** 1982 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1983 * @rx_ring: rx descriptor ring to transact packets on 1984 * @rx_buffer: buffer containing page to add 1985 * @skb: sk_buff to place the data into 1986 * @size: size of data in rx_buffer 1987 * 1988 * This function will add the data contained in rx_buffer->page to the skb. 1989 * This is done either through a direct copy if the data in the buffer is 1990 * less than the skb header size, otherwise it will just attach the page as 1991 * a frag to the skb. 1992 * 1993 * The function will then update the page offset if necessary and return 1994 * true if the buffer can be reused by the adapter. 1995 **/ 1996 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1997 struct ixgbe_rx_buffer *rx_buffer, 1998 struct sk_buff *skb, 1999 unsigned int size) 2000 { 2001 #if (PAGE_SIZE < 8192) 2002 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2003 #else 2004 unsigned int truesize = rx_ring->rx_offset ? 2005 SKB_DATA_ALIGN(rx_ring->rx_offset + size) : 2006 SKB_DATA_ALIGN(size); 2007 #endif 2008 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2009 rx_buffer->page_offset, size, truesize); 2010 #if (PAGE_SIZE < 8192) 2011 rx_buffer->page_offset ^= truesize; 2012 #else 2013 rx_buffer->page_offset += truesize; 2014 #endif 2015 } 2016 2017 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2018 union ixgbe_adv_rx_desc *rx_desc, 2019 struct sk_buff **skb, 2020 const unsigned int size, 2021 int *rx_buffer_pgcnt) 2022 { 2023 struct ixgbe_rx_buffer *rx_buffer; 2024 2025 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2026 *rx_buffer_pgcnt = 2027 #if (PAGE_SIZE < 8192) 2028 page_count(rx_buffer->page); 2029 #else 2030 0; 2031 #endif 2032 prefetchw(rx_buffer->page); 2033 *skb = rx_buffer->skb; 2034 2035 /* Delay unmapping of the first packet. It carries the header 2036 * information, HW may still access the header after the writeback. 2037 * Only unmap it when EOP is reached 2038 */ 2039 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2040 if (!*skb) 2041 goto skip_sync; 2042 } else { 2043 if (*skb) 2044 ixgbe_dma_sync_frag(rx_ring, *skb); 2045 } 2046 2047 /* we are reusing so sync this buffer for CPU use */ 2048 dma_sync_single_range_for_cpu(rx_ring->dev, 2049 rx_buffer->dma, 2050 rx_buffer->page_offset, 2051 size, 2052 DMA_FROM_DEVICE); 2053 skip_sync: 2054 rx_buffer->pagecnt_bias--; 2055 2056 return rx_buffer; 2057 } 2058 2059 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2060 struct ixgbe_rx_buffer *rx_buffer, 2061 struct sk_buff *skb, 2062 int rx_buffer_pgcnt) 2063 { 2064 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2065 /* hand second half of page back to the ring */ 2066 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2067 } else { 2068 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2069 /* the page has been released from the ring */ 2070 IXGBE_CB(skb)->page_released = true; 2071 } else { 2072 /* we are not reusing the buffer so unmap it */ 2073 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2074 ixgbe_rx_pg_size(rx_ring), 2075 DMA_FROM_DEVICE, 2076 IXGBE_RX_DMA_ATTR); 2077 } 2078 __page_frag_cache_drain(rx_buffer->page, 2079 rx_buffer->pagecnt_bias); 2080 } 2081 2082 /* clear contents of rx_buffer */ 2083 rx_buffer->page = NULL; 2084 rx_buffer->skb = NULL; 2085 } 2086 2087 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2088 struct ixgbe_rx_buffer *rx_buffer, 2089 struct xdp_buff *xdp, 2090 union ixgbe_adv_rx_desc *rx_desc) 2091 { 2092 unsigned int size = xdp->data_end - xdp->data; 2093 #if (PAGE_SIZE < 8192) 2094 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2095 #else 2096 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2097 xdp->data_hard_start); 2098 #endif 2099 struct sk_buff *skb; 2100 2101 /* prefetch first cache line of first page */ 2102 net_prefetch(xdp->data); 2103 2104 /* Note, we get here by enabling legacy-rx via: 2105 * 2106 * ethtool --set-priv-flags <dev> legacy-rx on 2107 * 2108 * In this mode, we currently get 0 extra XDP headroom as 2109 * opposed to having legacy-rx off, where we process XDP 2110 * packets going to stack via ixgbe_build_skb(). The latter 2111 * provides us currently with 192 bytes of headroom. 2112 * 2113 * For ixgbe_construct_skb() mode it means that the 2114 * xdp->data_meta will always point to xdp->data, since 2115 * the helper cannot expand the head. Should this ever 2116 * change in future for legacy-rx mode on, then lets also 2117 * add xdp->data_meta handling here. 2118 */ 2119 2120 /* allocate a skb to store the frags */ 2121 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2122 if (unlikely(!skb)) 2123 return NULL; 2124 2125 if (size > IXGBE_RX_HDR_SIZE) { 2126 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2127 IXGBE_CB(skb)->dma = rx_buffer->dma; 2128 2129 skb_add_rx_frag(skb, 0, rx_buffer->page, 2130 xdp->data - page_address(rx_buffer->page), 2131 size, truesize); 2132 #if (PAGE_SIZE < 8192) 2133 rx_buffer->page_offset ^= truesize; 2134 #else 2135 rx_buffer->page_offset += truesize; 2136 #endif 2137 } else { 2138 memcpy(__skb_put(skb, size), 2139 xdp->data, ALIGN(size, sizeof(long))); 2140 rx_buffer->pagecnt_bias++; 2141 } 2142 2143 return skb; 2144 } 2145 2146 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2147 struct ixgbe_rx_buffer *rx_buffer, 2148 struct xdp_buff *xdp, 2149 union ixgbe_adv_rx_desc *rx_desc) 2150 { 2151 unsigned int metasize = xdp->data - xdp->data_meta; 2152 #if (PAGE_SIZE < 8192) 2153 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2154 #else 2155 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2156 SKB_DATA_ALIGN(xdp->data_end - 2157 xdp->data_hard_start); 2158 #endif 2159 struct sk_buff *skb; 2160 2161 /* Prefetch first cache line of first page. If xdp->data_meta 2162 * is unused, this points extactly as xdp->data, otherwise we 2163 * likely have a consumer accessing first few bytes of meta 2164 * data, and then actual data. 2165 */ 2166 net_prefetch(xdp->data_meta); 2167 2168 /* build an skb to around the page buffer */ 2169 skb = build_skb(xdp->data_hard_start, truesize); 2170 if (unlikely(!skb)) 2171 return NULL; 2172 2173 /* update pointers within the skb to store the data */ 2174 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2175 __skb_put(skb, xdp->data_end - xdp->data); 2176 if (metasize) 2177 skb_metadata_set(skb, metasize); 2178 2179 /* record DMA address if this is the start of a chain of buffers */ 2180 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2181 IXGBE_CB(skb)->dma = rx_buffer->dma; 2182 2183 /* update buffer offset */ 2184 #if (PAGE_SIZE < 8192) 2185 rx_buffer->page_offset ^= truesize; 2186 #else 2187 rx_buffer->page_offset += truesize; 2188 #endif 2189 2190 return skb; 2191 } 2192 2193 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2194 struct ixgbe_ring *rx_ring, 2195 struct xdp_buff *xdp) 2196 { 2197 int err, result = IXGBE_XDP_PASS; 2198 struct bpf_prog *xdp_prog; 2199 struct xdp_frame *xdpf; 2200 u32 act; 2201 2202 rcu_read_lock(); 2203 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2204 2205 if (!xdp_prog) 2206 goto xdp_out; 2207 2208 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2209 2210 act = bpf_prog_run_xdp(xdp_prog, xdp); 2211 switch (act) { 2212 case XDP_PASS: 2213 break; 2214 case XDP_TX: 2215 xdpf = xdp_convert_buff_to_frame(xdp); 2216 if (unlikely(!xdpf)) { 2217 result = IXGBE_XDP_CONSUMED; 2218 break; 2219 } 2220 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2221 break; 2222 case XDP_REDIRECT: 2223 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2224 if (!err) 2225 result = IXGBE_XDP_REDIR; 2226 else 2227 result = IXGBE_XDP_CONSUMED; 2228 break; 2229 default: 2230 bpf_warn_invalid_xdp_action(act); 2231 fallthrough; 2232 case XDP_ABORTED: 2233 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2234 fallthrough; /* handle aborts by dropping packet */ 2235 case XDP_DROP: 2236 result = IXGBE_XDP_CONSUMED; 2237 break; 2238 } 2239 xdp_out: 2240 rcu_read_unlock(); 2241 return ERR_PTR(-result); 2242 } 2243 2244 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2245 unsigned int size) 2246 { 2247 unsigned int truesize; 2248 2249 #if (PAGE_SIZE < 8192) 2250 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2251 #else 2252 truesize = rx_ring->rx_offset ? 2253 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 2254 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2255 SKB_DATA_ALIGN(size); 2256 #endif 2257 return truesize; 2258 } 2259 2260 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2261 struct ixgbe_rx_buffer *rx_buffer, 2262 unsigned int size) 2263 { 2264 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2265 #if (PAGE_SIZE < 8192) 2266 rx_buffer->page_offset ^= truesize; 2267 #else 2268 rx_buffer->page_offset += truesize; 2269 #endif 2270 } 2271 2272 /** 2273 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2274 * @q_vector: structure containing interrupt and ring information 2275 * @rx_ring: rx descriptor ring to transact packets on 2276 * @budget: Total limit on number of packets to process 2277 * 2278 * This function provides a "bounce buffer" approach to Rx interrupt 2279 * processing. The advantage to this is that on systems that have 2280 * expensive overhead for IOMMU access this provides a means of avoiding 2281 * it by maintaining the mapping of the page to the syste. 2282 * 2283 * Returns amount of work completed 2284 **/ 2285 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2286 struct ixgbe_ring *rx_ring, 2287 const int budget) 2288 { 2289 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; 2290 struct ixgbe_adapter *adapter = q_vector->adapter; 2291 #ifdef IXGBE_FCOE 2292 int ddp_bytes; 2293 unsigned int mss = 0; 2294 #endif /* IXGBE_FCOE */ 2295 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2296 unsigned int offset = rx_ring->rx_offset; 2297 unsigned int xdp_xmit = 0; 2298 struct xdp_buff xdp; 2299 2300 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2301 #if (PAGE_SIZE < 8192) 2302 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2303 #endif 2304 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 2305 2306 while (likely(total_rx_packets < budget)) { 2307 union ixgbe_adv_rx_desc *rx_desc; 2308 struct ixgbe_rx_buffer *rx_buffer; 2309 struct sk_buff *skb; 2310 int rx_buffer_pgcnt; 2311 unsigned int size; 2312 2313 /* return some buffers to hardware, one at a time is too slow */ 2314 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2315 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2316 cleaned_count = 0; 2317 } 2318 2319 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2320 size = le16_to_cpu(rx_desc->wb.upper.length); 2321 if (!size) 2322 break; 2323 2324 /* This memory barrier is needed to keep us from reading 2325 * any other fields out of the rx_desc until we know the 2326 * descriptor has been written back 2327 */ 2328 dma_rmb(); 2329 2330 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2331 2332 /* retrieve a buffer from the ring */ 2333 if (!skb) { 2334 unsigned char *hard_start; 2335 2336 hard_start = page_address(rx_buffer->page) + 2337 rx_buffer->page_offset - offset; 2338 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 2339 #if (PAGE_SIZE > 4096) 2340 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2341 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2342 #endif 2343 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2344 } 2345 2346 if (IS_ERR(skb)) { 2347 unsigned int xdp_res = -PTR_ERR(skb); 2348 2349 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2350 xdp_xmit |= xdp_res; 2351 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2352 } else { 2353 rx_buffer->pagecnt_bias++; 2354 } 2355 total_rx_packets++; 2356 total_rx_bytes += size; 2357 } else if (skb) { 2358 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2359 } else if (ring_uses_build_skb(rx_ring)) { 2360 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2361 &xdp, rx_desc); 2362 } else { 2363 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2364 &xdp, rx_desc); 2365 } 2366 2367 /* exit if we failed to retrieve a buffer */ 2368 if (!skb) { 2369 rx_ring->rx_stats.alloc_rx_buff_failed++; 2370 rx_buffer->pagecnt_bias++; 2371 break; 2372 } 2373 2374 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2375 cleaned_count++; 2376 2377 /* place incomplete frames back on ring for completion */ 2378 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2379 continue; 2380 2381 /* verify the packet layout is correct */ 2382 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2383 continue; 2384 2385 /* probably a little skewed due to removing CRC */ 2386 total_rx_bytes += skb->len; 2387 2388 /* populate checksum, timestamp, VLAN, and protocol */ 2389 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2390 2391 #ifdef IXGBE_FCOE 2392 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2393 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2394 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2395 /* include DDPed FCoE data */ 2396 if (ddp_bytes > 0) { 2397 if (!mss) { 2398 mss = rx_ring->netdev->mtu - 2399 sizeof(struct fcoe_hdr) - 2400 sizeof(struct fc_frame_header) - 2401 sizeof(struct fcoe_crc_eof); 2402 if (mss > 512) 2403 mss &= ~511; 2404 } 2405 total_rx_bytes += ddp_bytes; 2406 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2407 mss); 2408 } 2409 if (!ddp_bytes) { 2410 dev_kfree_skb_any(skb); 2411 continue; 2412 } 2413 } 2414 2415 #endif /* IXGBE_FCOE */ 2416 ixgbe_rx_skb(q_vector, skb); 2417 2418 /* update budget accounting */ 2419 total_rx_packets++; 2420 } 2421 2422 if (xdp_xmit & IXGBE_XDP_REDIR) 2423 xdp_do_flush_map(); 2424 2425 if (xdp_xmit & IXGBE_XDP_TX) { 2426 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2427 2428 /* Force memory writes to complete before letting h/w 2429 * know there are new descriptors to fetch. 2430 */ 2431 wmb(); 2432 writel(ring->next_to_use, ring->tail); 2433 } 2434 2435 u64_stats_update_begin(&rx_ring->syncp); 2436 rx_ring->stats.packets += total_rx_packets; 2437 rx_ring->stats.bytes += total_rx_bytes; 2438 u64_stats_update_end(&rx_ring->syncp); 2439 q_vector->rx.total_packets += total_rx_packets; 2440 q_vector->rx.total_bytes += total_rx_bytes; 2441 2442 return total_rx_packets; 2443 } 2444 2445 /** 2446 * ixgbe_configure_msix - Configure MSI-X hardware 2447 * @adapter: board private structure 2448 * 2449 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2450 * interrupts. 2451 **/ 2452 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2453 { 2454 struct ixgbe_q_vector *q_vector; 2455 int v_idx; 2456 u32 mask; 2457 2458 /* Populate MSIX to EITR Select */ 2459 if (adapter->num_vfs > 32) { 2460 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2462 } 2463 2464 /* 2465 * Populate the IVAR table and set the ITR values to the 2466 * corresponding register. 2467 */ 2468 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2469 struct ixgbe_ring *ring; 2470 q_vector = adapter->q_vector[v_idx]; 2471 2472 ixgbe_for_each_ring(ring, q_vector->rx) 2473 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2474 2475 ixgbe_for_each_ring(ring, q_vector->tx) 2476 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2477 2478 ixgbe_write_eitr(q_vector); 2479 } 2480 2481 switch (adapter->hw.mac.type) { 2482 case ixgbe_mac_82598EB: 2483 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2484 v_idx); 2485 break; 2486 case ixgbe_mac_82599EB: 2487 case ixgbe_mac_X540: 2488 case ixgbe_mac_X550: 2489 case ixgbe_mac_X550EM_x: 2490 case ixgbe_mac_x550em_a: 2491 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2492 break; 2493 default: 2494 break; 2495 } 2496 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2497 2498 /* set up to autoclear timer, and the vectors */ 2499 mask = IXGBE_EIMS_ENABLE_MASK; 2500 mask &= ~(IXGBE_EIMS_OTHER | 2501 IXGBE_EIMS_MAILBOX | 2502 IXGBE_EIMS_LSC); 2503 2504 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2505 } 2506 2507 /** 2508 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2509 * @q_vector: structure containing interrupt and ring information 2510 * @ring_container: structure containing ring performance data 2511 * 2512 * Stores a new ITR value based on packets and byte 2513 * counts during the last interrupt. The advantage of per interrupt 2514 * computation is faster updates and more accurate ITR for the current 2515 * traffic pattern. Constants in this function were computed 2516 * based on theoretical maximum wire speed and thresholds were set based 2517 * on testing data as well as attempting to minimize response time 2518 * while increasing bulk throughput. 2519 **/ 2520 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2521 struct ixgbe_ring_container *ring_container) 2522 { 2523 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2524 IXGBE_ITR_ADAPTIVE_LATENCY; 2525 unsigned int avg_wire_size, packets, bytes; 2526 unsigned long next_update = jiffies; 2527 2528 /* If we don't have any rings just leave ourselves set for maximum 2529 * possible latency so we take ourselves out of the equation. 2530 */ 2531 if (!ring_container->ring) 2532 return; 2533 2534 /* If we didn't update within up to 1 - 2 jiffies we can assume 2535 * that either packets are coming in so slow there hasn't been 2536 * any work, or that there is so much work that NAPI is dealing 2537 * with interrupt moderation and we don't need to do anything. 2538 */ 2539 if (time_after(next_update, ring_container->next_update)) 2540 goto clear_counts; 2541 2542 packets = ring_container->total_packets; 2543 2544 /* We have no packets to actually measure against. This means 2545 * either one of the other queues on this vector is active or 2546 * we are a Tx queue doing TSO with too high of an interrupt rate. 2547 * 2548 * When this occurs just tick up our delay by the minimum value 2549 * and hope that this extra delay will prevent us from being called 2550 * without any work on our queue. 2551 */ 2552 if (!packets) { 2553 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2554 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2555 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2556 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2557 goto clear_counts; 2558 } 2559 2560 bytes = ring_container->total_bytes; 2561 2562 /* If packets are less than 4 or bytes are less than 9000 assume 2563 * insufficient data to use bulk rate limiting approach. We are 2564 * likely latency driven. 2565 */ 2566 if (packets < 4 && bytes < 9000) { 2567 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2568 goto adjust_by_size; 2569 } 2570 2571 /* Between 4 and 48 we can assume that our current interrupt delay 2572 * is only slightly too low. As such we should increase it by a small 2573 * fixed amount. 2574 */ 2575 if (packets < 48) { 2576 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2577 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2578 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2579 goto clear_counts; 2580 } 2581 2582 /* Between 48 and 96 is our "goldilocks" zone where we are working 2583 * out "just right". Just report that our current ITR is good for us. 2584 */ 2585 if (packets < 96) { 2586 itr = q_vector->itr >> 2; 2587 goto clear_counts; 2588 } 2589 2590 /* If packet count is 96 or greater we are likely looking at a slight 2591 * overrun of the delay we want. Try halving our delay to see if that 2592 * will cut the number of packets in half per interrupt. 2593 */ 2594 if (packets < 256) { 2595 itr = q_vector->itr >> 3; 2596 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2597 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2598 goto clear_counts; 2599 } 2600 2601 /* The paths below assume we are dealing with a bulk ITR since number 2602 * of packets is 256 or greater. We are just going to have to compute 2603 * a value and try to bring the count under control, though for smaller 2604 * packet sizes there isn't much we can do as NAPI polling will likely 2605 * be kicking in sooner rather than later. 2606 */ 2607 itr = IXGBE_ITR_ADAPTIVE_BULK; 2608 2609 adjust_by_size: 2610 /* If packet counts are 256 or greater we can assume we have a gross 2611 * overestimation of what the rate should be. Instead of trying to fine 2612 * tune it just use the formula below to try and dial in an exact value 2613 * give the current packet size of the frame. 2614 */ 2615 avg_wire_size = bytes / packets; 2616 2617 /* The following is a crude approximation of: 2618 * wmem_default / (size + overhead) = desired_pkts_per_int 2619 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2620 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2621 * 2622 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2623 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2624 * formula down to 2625 * 2626 * (170 * (size + 24)) / (size + 640) = ITR 2627 * 2628 * We first do some math on the packet size and then finally bitshift 2629 * by 8 after rounding up. We also have to account for PCIe link speed 2630 * difference as ITR scales based on this. 2631 */ 2632 if (avg_wire_size <= 60) { 2633 /* Start at 50k ints/sec */ 2634 avg_wire_size = 5120; 2635 } else if (avg_wire_size <= 316) { 2636 /* 50K ints/sec to 16K ints/sec */ 2637 avg_wire_size *= 40; 2638 avg_wire_size += 2720; 2639 } else if (avg_wire_size <= 1084) { 2640 /* 16K ints/sec to 9.2K ints/sec */ 2641 avg_wire_size *= 15; 2642 avg_wire_size += 11452; 2643 } else if (avg_wire_size < 1968) { 2644 /* 9.2K ints/sec to 8K ints/sec */ 2645 avg_wire_size *= 5; 2646 avg_wire_size += 22420; 2647 } else { 2648 /* plateau at a limit of 8K ints/sec */ 2649 avg_wire_size = 32256; 2650 } 2651 2652 /* If we are in low latency mode half our delay which doubles the rate 2653 * to somewhere between 100K to 16K ints/sec 2654 */ 2655 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2656 avg_wire_size >>= 1; 2657 2658 /* Resultant value is 256 times larger than it needs to be. This 2659 * gives us room to adjust the value as needed to either increase 2660 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2661 * 2662 * Use addition as we have already recorded the new latency flag 2663 * for the ITR value. 2664 */ 2665 switch (q_vector->adapter->link_speed) { 2666 case IXGBE_LINK_SPEED_10GB_FULL: 2667 case IXGBE_LINK_SPEED_100_FULL: 2668 default: 2669 itr += DIV_ROUND_UP(avg_wire_size, 2670 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2671 IXGBE_ITR_ADAPTIVE_MIN_INC; 2672 break; 2673 case IXGBE_LINK_SPEED_2_5GB_FULL: 2674 case IXGBE_LINK_SPEED_1GB_FULL: 2675 case IXGBE_LINK_SPEED_10_FULL: 2676 if (avg_wire_size > 8064) 2677 avg_wire_size = 8064; 2678 itr += DIV_ROUND_UP(avg_wire_size, 2679 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2680 IXGBE_ITR_ADAPTIVE_MIN_INC; 2681 break; 2682 } 2683 2684 clear_counts: 2685 /* write back value */ 2686 ring_container->itr = itr; 2687 2688 /* next update should occur within next jiffy */ 2689 ring_container->next_update = next_update + 1; 2690 2691 ring_container->total_bytes = 0; 2692 ring_container->total_packets = 0; 2693 } 2694 2695 /** 2696 * ixgbe_write_eitr - write EITR register in hardware specific way 2697 * @q_vector: structure containing interrupt and ring information 2698 * 2699 * This function is made to be called by ethtool and by the driver 2700 * when it needs to update EITR registers at runtime. Hardware 2701 * specific quirks/differences are taken care of here. 2702 */ 2703 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2704 { 2705 struct ixgbe_adapter *adapter = q_vector->adapter; 2706 struct ixgbe_hw *hw = &adapter->hw; 2707 int v_idx = q_vector->v_idx; 2708 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2709 2710 switch (adapter->hw.mac.type) { 2711 case ixgbe_mac_82598EB: 2712 /* must write high and low 16 bits to reset counter */ 2713 itr_reg |= (itr_reg << 16); 2714 break; 2715 case ixgbe_mac_82599EB: 2716 case ixgbe_mac_X540: 2717 case ixgbe_mac_X550: 2718 case ixgbe_mac_X550EM_x: 2719 case ixgbe_mac_x550em_a: 2720 /* 2721 * set the WDIS bit to not clear the timer bits and cause an 2722 * immediate assertion of the interrupt 2723 */ 2724 itr_reg |= IXGBE_EITR_CNT_WDIS; 2725 break; 2726 default: 2727 break; 2728 } 2729 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2730 } 2731 2732 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2733 { 2734 u32 new_itr; 2735 2736 ixgbe_update_itr(q_vector, &q_vector->tx); 2737 ixgbe_update_itr(q_vector, &q_vector->rx); 2738 2739 /* use the smallest value of new ITR delay calculations */ 2740 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2741 2742 /* Clear latency flag if set, shift into correct position */ 2743 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2744 new_itr <<= 2; 2745 2746 if (new_itr != q_vector->itr) { 2747 /* save the algorithm value here */ 2748 q_vector->itr = new_itr; 2749 2750 ixgbe_write_eitr(q_vector); 2751 } 2752 } 2753 2754 /** 2755 * ixgbe_check_overtemp_subtask - check for over temperature 2756 * @adapter: pointer to adapter 2757 **/ 2758 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2759 { 2760 struct ixgbe_hw *hw = &adapter->hw; 2761 u32 eicr = adapter->interrupt_event; 2762 s32 rc; 2763 2764 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2765 return; 2766 2767 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2768 return; 2769 2770 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2771 2772 switch (hw->device_id) { 2773 case IXGBE_DEV_ID_82599_T3_LOM: 2774 /* 2775 * Since the warning interrupt is for both ports 2776 * we don't have to check if: 2777 * - This interrupt wasn't for our port. 2778 * - We may have missed the interrupt so always have to 2779 * check if we got a LSC 2780 */ 2781 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2782 !(eicr & IXGBE_EICR_LSC)) 2783 return; 2784 2785 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2786 u32 speed; 2787 bool link_up = false; 2788 2789 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2790 2791 if (link_up) 2792 return; 2793 } 2794 2795 /* Check if this is not due to overtemp */ 2796 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2797 return; 2798 2799 break; 2800 case IXGBE_DEV_ID_X550EM_A_1G_T: 2801 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2802 rc = hw->phy.ops.check_overtemp(hw); 2803 if (rc != IXGBE_ERR_OVERTEMP) 2804 return; 2805 break; 2806 default: 2807 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2808 return; 2809 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2810 return; 2811 break; 2812 } 2813 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2814 2815 adapter->interrupt_event = 0; 2816 } 2817 2818 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2819 { 2820 struct ixgbe_hw *hw = &adapter->hw; 2821 2822 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2823 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2824 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2825 /* write to clear the interrupt */ 2826 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2827 } 2828 } 2829 2830 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2831 { 2832 struct ixgbe_hw *hw = &adapter->hw; 2833 2834 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2835 return; 2836 2837 switch (adapter->hw.mac.type) { 2838 case ixgbe_mac_82599EB: 2839 /* 2840 * Need to check link state so complete overtemp check 2841 * on service task 2842 */ 2843 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2844 (eicr & IXGBE_EICR_LSC)) && 2845 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2846 adapter->interrupt_event = eicr; 2847 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2848 ixgbe_service_event_schedule(adapter); 2849 return; 2850 } 2851 return; 2852 case ixgbe_mac_x550em_a: 2853 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2854 adapter->interrupt_event = eicr; 2855 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2856 ixgbe_service_event_schedule(adapter); 2857 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2858 IXGBE_EICR_GPI_SDP0_X550EM_a); 2859 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2860 IXGBE_EICR_GPI_SDP0_X550EM_a); 2861 } 2862 return; 2863 case ixgbe_mac_X550: 2864 case ixgbe_mac_X540: 2865 if (!(eicr & IXGBE_EICR_TS)) 2866 return; 2867 break; 2868 default: 2869 return; 2870 } 2871 2872 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2873 } 2874 2875 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2876 { 2877 switch (hw->mac.type) { 2878 case ixgbe_mac_82598EB: 2879 if (hw->phy.type == ixgbe_phy_nl) 2880 return true; 2881 return false; 2882 case ixgbe_mac_82599EB: 2883 case ixgbe_mac_X550EM_x: 2884 case ixgbe_mac_x550em_a: 2885 switch (hw->mac.ops.get_media_type(hw)) { 2886 case ixgbe_media_type_fiber: 2887 case ixgbe_media_type_fiber_qsfp: 2888 return true; 2889 default: 2890 return false; 2891 } 2892 default: 2893 return false; 2894 } 2895 } 2896 2897 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2898 { 2899 struct ixgbe_hw *hw = &adapter->hw; 2900 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2901 2902 if (!ixgbe_is_sfp(hw)) 2903 return; 2904 2905 /* Later MAC's use different SDP */ 2906 if (hw->mac.type >= ixgbe_mac_X540) 2907 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2908 2909 if (eicr & eicr_mask) { 2910 /* Clear the interrupt */ 2911 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2912 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2913 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2914 adapter->sfp_poll_time = 0; 2915 ixgbe_service_event_schedule(adapter); 2916 } 2917 } 2918 2919 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2920 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2921 /* Clear the interrupt */ 2922 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2923 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2924 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2925 ixgbe_service_event_schedule(adapter); 2926 } 2927 } 2928 } 2929 2930 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2931 { 2932 struct ixgbe_hw *hw = &adapter->hw; 2933 2934 adapter->lsc_int++; 2935 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2936 adapter->link_check_timeout = jiffies; 2937 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2938 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2939 IXGBE_WRITE_FLUSH(hw); 2940 ixgbe_service_event_schedule(adapter); 2941 } 2942 } 2943 2944 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2945 u64 qmask) 2946 { 2947 u32 mask; 2948 struct ixgbe_hw *hw = &adapter->hw; 2949 2950 switch (hw->mac.type) { 2951 case ixgbe_mac_82598EB: 2952 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2953 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2954 break; 2955 case ixgbe_mac_82599EB: 2956 case ixgbe_mac_X540: 2957 case ixgbe_mac_X550: 2958 case ixgbe_mac_X550EM_x: 2959 case ixgbe_mac_x550em_a: 2960 mask = (qmask & 0xFFFFFFFF); 2961 if (mask) 2962 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2963 mask = (qmask >> 32); 2964 if (mask) 2965 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2966 break; 2967 default: 2968 break; 2969 } 2970 /* skip the flush */ 2971 } 2972 2973 /** 2974 * ixgbe_irq_enable - Enable default interrupt generation settings 2975 * @adapter: board private structure 2976 * @queues: enable irqs for queues 2977 * @flush: flush register write 2978 **/ 2979 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2980 bool flush) 2981 { 2982 struct ixgbe_hw *hw = &adapter->hw; 2983 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2984 2985 /* don't reenable LSC while waiting for link */ 2986 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2987 mask &= ~IXGBE_EIMS_LSC; 2988 2989 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2990 switch (adapter->hw.mac.type) { 2991 case ixgbe_mac_82599EB: 2992 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2993 break; 2994 case ixgbe_mac_X540: 2995 case ixgbe_mac_X550: 2996 case ixgbe_mac_X550EM_x: 2997 case ixgbe_mac_x550em_a: 2998 mask |= IXGBE_EIMS_TS; 2999 break; 3000 default: 3001 break; 3002 } 3003 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3004 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3005 switch (adapter->hw.mac.type) { 3006 case ixgbe_mac_82599EB: 3007 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3008 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3009 fallthrough; 3010 case ixgbe_mac_X540: 3011 case ixgbe_mac_X550: 3012 case ixgbe_mac_X550EM_x: 3013 case ixgbe_mac_x550em_a: 3014 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3015 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3016 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3017 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3018 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3019 mask |= IXGBE_EICR_GPI_SDP0_X540; 3020 mask |= IXGBE_EIMS_ECC; 3021 mask |= IXGBE_EIMS_MAILBOX; 3022 break; 3023 default: 3024 break; 3025 } 3026 3027 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3028 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3029 mask |= IXGBE_EIMS_FLOW_DIR; 3030 3031 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3032 if (queues) 3033 ixgbe_irq_enable_queues(adapter, ~0); 3034 if (flush) 3035 IXGBE_WRITE_FLUSH(&adapter->hw); 3036 } 3037 3038 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3039 { 3040 struct ixgbe_adapter *adapter = data; 3041 struct ixgbe_hw *hw = &adapter->hw; 3042 u32 eicr; 3043 3044 /* 3045 * Workaround for Silicon errata. Use clear-by-write instead 3046 * of clear-by-read. Reading with EICS will return the 3047 * interrupt causes without clearing, which later be done 3048 * with the write to EICR. 3049 */ 3050 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3051 3052 /* The lower 16bits of the EICR register are for the queue interrupts 3053 * which should be masked here in order to not accidentally clear them if 3054 * the bits are high when ixgbe_msix_other is called. There is a race 3055 * condition otherwise which results in possible performance loss 3056 * especially if the ixgbe_msix_other interrupt is triggering 3057 * consistently (as it would when PPS is turned on for the X540 device) 3058 */ 3059 eicr &= 0xFFFF0000; 3060 3061 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3062 3063 if (eicr & IXGBE_EICR_LSC) 3064 ixgbe_check_lsc(adapter); 3065 3066 if (eicr & IXGBE_EICR_MAILBOX) 3067 ixgbe_msg_task(adapter); 3068 3069 switch (hw->mac.type) { 3070 case ixgbe_mac_82599EB: 3071 case ixgbe_mac_X540: 3072 case ixgbe_mac_X550: 3073 case ixgbe_mac_X550EM_x: 3074 case ixgbe_mac_x550em_a: 3075 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3076 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3077 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3078 ixgbe_service_event_schedule(adapter); 3079 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3080 IXGBE_EICR_GPI_SDP0_X540); 3081 } 3082 if (eicr & IXGBE_EICR_ECC) { 3083 e_info(link, "Received ECC Err, initiating reset\n"); 3084 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3085 ixgbe_service_event_schedule(adapter); 3086 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3087 } 3088 /* Handle Flow Director Full threshold interrupt */ 3089 if (eicr & IXGBE_EICR_FLOW_DIR) { 3090 int reinit_count = 0; 3091 int i; 3092 for (i = 0; i < adapter->num_tx_queues; i++) { 3093 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3094 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3095 &ring->state)) 3096 reinit_count++; 3097 } 3098 if (reinit_count) { 3099 /* no more flow director interrupts until after init */ 3100 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3101 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3102 ixgbe_service_event_schedule(adapter); 3103 } 3104 } 3105 ixgbe_check_sfp_event(adapter, eicr); 3106 ixgbe_check_overtemp_event(adapter, eicr); 3107 break; 3108 default: 3109 break; 3110 } 3111 3112 ixgbe_check_fan_failure(adapter, eicr); 3113 3114 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3115 ixgbe_ptp_check_pps_event(adapter); 3116 3117 /* re-enable the original interrupt state, no lsc, no queues */ 3118 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3119 ixgbe_irq_enable(adapter, false, false); 3120 3121 return IRQ_HANDLED; 3122 } 3123 3124 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3125 { 3126 struct ixgbe_q_vector *q_vector = data; 3127 3128 /* EIAM disabled interrupts (on this vector) for us */ 3129 3130 if (q_vector->rx.ring || q_vector->tx.ring) 3131 napi_schedule_irqoff(&q_vector->napi); 3132 3133 return IRQ_HANDLED; 3134 } 3135 3136 /** 3137 * ixgbe_poll - NAPI Rx polling callback 3138 * @napi: structure for representing this polling device 3139 * @budget: how many packets driver is allowed to clean 3140 * 3141 * This function is used for legacy and MSI, NAPI mode 3142 **/ 3143 int ixgbe_poll(struct napi_struct *napi, int budget) 3144 { 3145 struct ixgbe_q_vector *q_vector = 3146 container_of(napi, struct ixgbe_q_vector, napi); 3147 struct ixgbe_adapter *adapter = q_vector->adapter; 3148 struct ixgbe_ring *ring; 3149 int per_ring_budget, work_done = 0; 3150 bool clean_complete = true; 3151 3152 #ifdef CONFIG_IXGBE_DCA 3153 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3154 ixgbe_update_dca(q_vector); 3155 #endif 3156 3157 ixgbe_for_each_ring(ring, q_vector->tx) { 3158 bool wd = ring->xsk_pool ? 3159 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3160 ixgbe_clean_tx_irq(q_vector, ring, budget); 3161 3162 if (!wd) 3163 clean_complete = false; 3164 } 3165 3166 /* Exit if we are called by netpoll */ 3167 if (budget <= 0) 3168 return budget; 3169 3170 /* attempt to distribute budget to each queue fairly, but don't allow 3171 * the budget to go below 1 because we'll exit polling */ 3172 if (q_vector->rx.count > 1) 3173 per_ring_budget = max(budget/q_vector->rx.count, 1); 3174 else 3175 per_ring_budget = budget; 3176 3177 ixgbe_for_each_ring(ring, q_vector->rx) { 3178 int cleaned = ring->xsk_pool ? 3179 ixgbe_clean_rx_irq_zc(q_vector, ring, 3180 per_ring_budget) : 3181 ixgbe_clean_rx_irq(q_vector, ring, 3182 per_ring_budget); 3183 3184 work_done += cleaned; 3185 if (cleaned >= per_ring_budget) 3186 clean_complete = false; 3187 } 3188 3189 /* If all work not completed, return budget and keep polling */ 3190 if (!clean_complete) 3191 return budget; 3192 3193 /* all work done, exit the polling mode */ 3194 if (likely(napi_complete_done(napi, work_done))) { 3195 if (adapter->rx_itr_setting & 1) 3196 ixgbe_set_itr(q_vector); 3197 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3198 ixgbe_irq_enable_queues(adapter, 3199 BIT_ULL(q_vector->v_idx)); 3200 } 3201 3202 return min(work_done, budget - 1); 3203 } 3204 3205 /** 3206 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3207 * @adapter: board private structure 3208 * 3209 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3210 * interrupts from the kernel. 3211 **/ 3212 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3213 { 3214 struct net_device *netdev = adapter->netdev; 3215 unsigned int ri = 0, ti = 0; 3216 int vector, err; 3217 3218 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3219 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3220 struct msix_entry *entry = &adapter->msix_entries[vector]; 3221 3222 if (q_vector->tx.ring && q_vector->rx.ring) { 3223 snprintf(q_vector->name, sizeof(q_vector->name), 3224 "%s-TxRx-%u", netdev->name, ri++); 3225 ti++; 3226 } else if (q_vector->rx.ring) { 3227 snprintf(q_vector->name, sizeof(q_vector->name), 3228 "%s-rx-%u", netdev->name, ri++); 3229 } else if (q_vector->tx.ring) { 3230 snprintf(q_vector->name, sizeof(q_vector->name), 3231 "%s-tx-%u", netdev->name, ti++); 3232 } else { 3233 /* skip this unused q_vector */ 3234 continue; 3235 } 3236 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3237 q_vector->name, q_vector); 3238 if (err) { 3239 e_err(probe, "request_irq failed for MSIX interrupt " 3240 "Error: %d\n", err); 3241 goto free_queue_irqs; 3242 } 3243 /* If Flow Director is enabled, set interrupt affinity */ 3244 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3245 /* assign the mask for this irq */ 3246 irq_set_affinity_hint(entry->vector, 3247 &q_vector->affinity_mask); 3248 } 3249 } 3250 3251 err = request_irq(adapter->msix_entries[vector].vector, 3252 ixgbe_msix_other, 0, netdev->name, adapter); 3253 if (err) { 3254 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3255 goto free_queue_irqs; 3256 } 3257 3258 return 0; 3259 3260 free_queue_irqs: 3261 while (vector) { 3262 vector--; 3263 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3264 NULL); 3265 free_irq(adapter->msix_entries[vector].vector, 3266 adapter->q_vector[vector]); 3267 } 3268 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3269 pci_disable_msix(adapter->pdev); 3270 kfree(adapter->msix_entries); 3271 adapter->msix_entries = NULL; 3272 return err; 3273 } 3274 3275 /** 3276 * ixgbe_intr - legacy mode Interrupt Handler 3277 * @irq: interrupt number 3278 * @data: pointer to a network interface device structure 3279 **/ 3280 static irqreturn_t ixgbe_intr(int irq, void *data) 3281 { 3282 struct ixgbe_adapter *adapter = data; 3283 struct ixgbe_hw *hw = &adapter->hw; 3284 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3285 u32 eicr; 3286 3287 /* 3288 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3289 * before the read of EICR. 3290 */ 3291 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3292 3293 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3294 * therefore no explicit interrupt disable is necessary */ 3295 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3296 if (!eicr) { 3297 /* 3298 * shared interrupt alert! 3299 * make sure interrupts are enabled because the read will 3300 * have disabled interrupts due to EIAM 3301 * finish the workaround of silicon errata on 82598. Unmask 3302 * the interrupt that we masked before the EICR read. 3303 */ 3304 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3305 ixgbe_irq_enable(adapter, true, true); 3306 return IRQ_NONE; /* Not our interrupt */ 3307 } 3308 3309 if (eicr & IXGBE_EICR_LSC) 3310 ixgbe_check_lsc(adapter); 3311 3312 switch (hw->mac.type) { 3313 case ixgbe_mac_82599EB: 3314 ixgbe_check_sfp_event(adapter, eicr); 3315 fallthrough; 3316 case ixgbe_mac_X540: 3317 case ixgbe_mac_X550: 3318 case ixgbe_mac_X550EM_x: 3319 case ixgbe_mac_x550em_a: 3320 if (eicr & IXGBE_EICR_ECC) { 3321 e_info(link, "Received ECC Err, initiating reset\n"); 3322 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3323 ixgbe_service_event_schedule(adapter); 3324 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3325 } 3326 ixgbe_check_overtemp_event(adapter, eicr); 3327 break; 3328 default: 3329 break; 3330 } 3331 3332 ixgbe_check_fan_failure(adapter, eicr); 3333 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3334 ixgbe_ptp_check_pps_event(adapter); 3335 3336 /* would disable interrupts here but EIAM disabled it */ 3337 napi_schedule_irqoff(&q_vector->napi); 3338 3339 /* 3340 * re-enable link(maybe) and non-queue interrupts, no flush. 3341 * ixgbe_poll will re-enable the queue interrupts 3342 */ 3343 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3344 ixgbe_irq_enable(adapter, false, false); 3345 3346 return IRQ_HANDLED; 3347 } 3348 3349 /** 3350 * ixgbe_request_irq - initialize interrupts 3351 * @adapter: board private structure 3352 * 3353 * Attempts to configure interrupts using the best available 3354 * capabilities of the hardware and kernel. 3355 **/ 3356 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3357 { 3358 struct net_device *netdev = adapter->netdev; 3359 int err; 3360 3361 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3362 err = ixgbe_request_msix_irqs(adapter); 3363 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3364 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3365 netdev->name, adapter); 3366 else 3367 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3368 netdev->name, adapter); 3369 3370 if (err) 3371 e_err(probe, "request_irq failed, Error %d\n", err); 3372 3373 return err; 3374 } 3375 3376 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3377 { 3378 int vector; 3379 3380 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3381 free_irq(adapter->pdev->irq, adapter); 3382 return; 3383 } 3384 3385 if (!adapter->msix_entries) 3386 return; 3387 3388 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3389 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3390 struct msix_entry *entry = &adapter->msix_entries[vector]; 3391 3392 /* free only the irqs that were actually requested */ 3393 if (!q_vector->rx.ring && !q_vector->tx.ring) 3394 continue; 3395 3396 /* clear the affinity_mask in the IRQ descriptor */ 3397 irq_set_affinity_hint(entry->vector, NULL); 3398 3399 free_irq(entry->vector, q_vector); 3400 } 3401 3402 free_irq(adapter->msix_entries[vector].vector, adapter); 3403 } 3404 3405 /** 3406 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3407 * @adapter: board private structure 3408 **/ 3409 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3410 { 3411 switch (adapter->hw.mac.type) { 3412 case ixgbe_mac_82598EB: 3413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3414 break; 3415 case ixgbe_mac_82599EB: 3416 case ixgbe_mac_X540: 3417 case ixgbe_mac_X550: 3418 case ixgbe_mac_X550EM_x: 3419 case ixgbe_mac_x550em_a: 3420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3423 break; 3424 default: 3425 break; 3426 } 3427 IXGBE_WRITE_FLUSH(&adapter->hw); 3428 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3429 int vector; 3430 3431 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3432 synchronize_irq(adapter->msix_entries[vector].vector); 3433 3434 synchronize_irq(adapter->msix_entries[vector++].vector); 3435 } else { 3436 synchronize_irq(adapter->pdev->irq); 3437 } 3438 } 3439 3440 /** 3441 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3442 * @adapter: board private structure 3443 * 3444 **/ 3445 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3446 { 3447 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3448 3449 ixgbe_write_eitr(q_vector); 3450 3451 ixgbe_set_ivar(adapter, 0, 0, 0); 3452 ixgbe_set_ivar(adapter, 1, 0, 0); 3453 3454 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3455 } 3456 3457 /** 3458 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3459 * @adapter: board private structure 3460 * @ring: structure containing ring specific data 3461 * 3462 * Configure the Tx descriptor ring after a reset. 3463 **/ 3464 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3465 struct ixgbe_ring *ring) 3466 { 3467 struct ixgbe_hw *hw = &adapter->hw; 3468 u64 tdba = ring->dma; 3469 int wait_loop = 10; 3470 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3471 u8 reg_idx = ring->reg_idx; 3472 3473 ring->xsk_pool = NULL; 3474 if (ring_is_xdp(ring)) 3475 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3476 3477 /* disable queue to avoid issues while updating state */ 3478 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3479 IXGBE_WRITE_FLUSH(hw); 3480 3481 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3482 (tdba & DMA_BIT_MASK(32))); 3483 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3484 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3485 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3486 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3487 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3488 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3489 3490 /* 3491 * set WTHRESH to encourage burst writeback, it should not be set 3492 * higher than 1 when: 3493 * - ITR is 0 as it could cause false TX hangs 3494 * - ITR is set to > 100k int/sec and BQL is enabled 3495 * 3496 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3497 * to or less than the number of on chip descriptors, which is 3498 * currently 40. 3499 */ 3500 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3501 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3502 else 3503 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3504 3505 /* 3506 * Setting PTHRESH to 32 both improves performance 3507 * and avoids a TX hang with DFP enabled 3508 */ 3509 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3510 32; /* PTHRESH = 32 */ 3511 3512 /* reinitialize flowdirector state */ 3513 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3514 ring->atr_sample_rate = adapter->atr_sample_rate; 3515 ring->atr_count = 0; 3516 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3517 } else { 3518 ring->atr_sample_rate = 0; 3519 } 3520 3521 /* initialize XPS */ 3522 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3523 struct ixgbe_q_vector *q_vector = ring->q_vector; 3524 3525 if (q_vector) 3526 netif_set_xps_queue(ring->netdev, 3527 &q_vector->affinity_mask, 3528 ring->queue_index); 3529 } 3530 3531 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3532 3533 /* reinitialize tx_buffer_info */ 3534 memset(ring->tx_buffer_info, 0, 3535 sizeof(struct ixgbe_tx_buffer) * ring->count); 3536 3537 /* enable queue */ 3538 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3539 3540 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3541 if (hw->mac.type == ixgbe_mac_82598EB && 3542 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3543 return; 3544 3545 /* poll to verify queue is enabled */ 3546 do { 3547 usleep_range(1000, 2000); 3548 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3549 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3550 if (!wait_loop) 3551 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3552 } 3553 3554 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3555 { 3556 struct ixgbe_hw *hw = &adapter->hw; 3557 u32 rttdcs, mtqc; 3558 u8 tcs = adapter->hw_tcs; 3559 3560 if (hw->mac.type == ixgbe_mac_82598EB) 3561 return; 3562 3563 /* disable the arbiter while setting MTQC */ 3564 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3565 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3566 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3567 3568 /* set transmit pool layout */ 3569 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3570 mtqc = IXGBE_MTQC_VT_ENA; 3571 if (tcs > 4) 3572 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3573 else if (tcs > 1) 3574 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3575 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3576 IXGBE_82599_VMDQ_4Q_MASK) 3577 mtqc |= IXGBE_MTQC_32VF; 3578 else 3579 mtqc |= IXGBE_MTQC_64VF; 3580 } else { 3581 if (tcs > 4) { 3582 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3583 } else if (tcs > 1) { 3584 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3585 } else { 3586 u8 max_txq = adapter->num_tx_queues + 3587 adapter->num_xdp_queues; 3588 if (max_txq > 63) 3589 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3590 else 3591 mtqc = IXGBE_MTQC_64Q_1PB; 3592 } 3593 } 3594 3595 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3596 3597 /* Enable Security TX Buffer IFG for multiple pb */ 3598 if (tcs) { 3599 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3600 sectx |= IXGBE_SECTX_DCB; 3601 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3602 } 3603 3604 /* re-enable the arbiter */ 3605 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3606 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3607 } 3608 3609 /** 3610 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3611 * @adapter: board private structure 3612 * 3613 * Configure the Tx unit of the MAC after a reset. 3614 **/ 3615 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3616 { 3617 struct ixgbe_hw *hw = &adapter->hw; 3618 u32 dmatxctl; 3619 u32 i; 3620 3621 ixgbe_setup_mtqc(adapter); 3622 3623 if (hw->mac.type != ixgbe_mac_82598EB) { 3624 /* DMATXCTL.EN must be before Tx queues are enabled */ 3625 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3626 dmatxctl |= IXGBE_DMATXCTL_TE; 3627 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3628 } 3629 3630 /* Setup the HW Tx Head and Tail descriptor pointers */ 3631 for (i = 0; i < adapter->num_tx_queues; i++) 3632 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3633 for (i = 0; i < adapter->num_xdp_queues; i++) 3634 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3635 } 3636 3637 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3638 struct ixgbe_ring *ring) 3639 { 3640 struct ixgbe_hw *hw = &adapter->hw; 3641 u8 reg_idx = ring->reg_idx; 3642 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3643 3644 srrctl |= IXGBE_SRRCTL_DROP_EN; 3645 3646 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3647 } 3648 3649 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3650 struct ixgbe_ring *ring) 3651 { 3652 struct ixgbe_hw *hw = &adapter->hw; 3653 u8 reg_idx = ring->reg_idx; 3654 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3655 3656 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3657 3658 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3659 } 3660 3661 #ifdef CONFIG_IXGBE_DCB 3662 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3663 #else 3664 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3665 #endif 3666 { 3667 int i; 3668 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3669 3670 if (adapter->ixgbe_ieee_pfc) 3671 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3672 3673 /* 3674 * We should set the drop enable bit if: 3675 * SR-IOV is enabled 3676 * or 3677 * Number of Rx queues > 1 and flow control is disabled 3678 * 3679 * This allows us to avoid head of line blocking for security 3680 * and performance reasons. 3681 */ 3682 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3683 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3684 for (i = 0; i < adapter->num_rx_queues; i++) 3685 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3686 } else { 3687 for (i = 0; i < adapter->num_rx_queues; i++) 3688 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3689 } 3690 } 3691 3692 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3693 3694 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3695 struct ixgbe_ring *rx_ring) 3696 { 3697 struct ixgbe_hw *hw = &adapter->hw; 3698 u32 srrctl; 3699 u8 reg_idx = rx_ring->reg_idx; 3700 3701 if (hw->mac.type == ixgbe_mac_82598EB) { 3702 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3703 3704 /* 3705 * if VMDq is not active we must program one srrctl register 3706 * per RSS queue since we have enabled RDRXCTL.MVMEN 3707 */ 3708 reg_idx &= mask; 3709 } 3710 3711 /* configure header buffer length, needed for RSC */ 3712 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3713 3714 /* configure the packet buffer length */ 3715 if (rx_ring->xsk_pool) { 3716 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 3717 3718 /* If the MAC support setting RXDCTL.RLPML, the 3719 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3720 * RXDCTL.RLPML is set to the actual UMEM buffer 3721 * size. If not, then we are stuck with a 1k buffer 3722 * size resolution. In this case frames larger than 3723 * the UMEM buffer size viewed in a 1k resolution will 3724 * be dropped. 3725 */ 3726 if (hw->mac.type != ixgbe_mac_82599EB) 3727 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3728 else 3729 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3730 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3731 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3732 } else { 3733 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3734 } 3735 3736 /* configure descriptor type */ 3737 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3738 3739 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3740 } 3741 3742 /** 3743 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3744 * @adapter: device handle 3745 * 3746 * - 82598/82599/X540: 128 3747 * - X550(non-SRIOV mode): 512 3748 * - X550(SRIOV mode): 64 3749 */ 3750 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3751 { 3752 if (adapter->hw.mac.type < ixgbe_mac_X550) 3753 return 128; 3754 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3755 return 64; 3756 else 3757 return 512; 3758 } 3759 3760 /** 3761 * ixgbe_store_key - Write the RSS key to HW 3762 * @adapter: device handle 3763 * 3764 * Write the RSS key stored in adapter.rss_key to HW. 3765 */ 3766 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3767 { 3768 struct ixgbe_hw *hw = &adapter->hw; 3769 int i; 3770 3771 for (i = 0; i < 10; i++) 3772 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3773 } 3774 3775 /** 3776 * ixgbe_init_rss_key - Initialize adapter RSS key 3777 * @adapter: device handle 3778 * 3779 * Allocates and initializes the RSS key if it is not allocated. 3780 **/ 3781 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3782 { 3783 u32 *rss_key; 3784 3785 if (!adapter->rss_key) { 3786 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3787 if (unlikely(!rss_key)) 3788 return -ENOMEM; 3789 3790 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3791 adapter->rss_key = rss_key; 3792 } 3793 3794 return 0; 3795 } 3796 3797 /** 3798 * ixgbe_store_reta - Write the RETA table to HW 3799 * @adapter: device handle 3800 * 3801 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3802 */ 3803 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3804 { 3805 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3806 struct ixgbe_hw *hw = &adapter->hw; 3807 u32 reta = 0; 3808 u32 indices_multi; 3809 u8 *indir_tbl = adapter->rss_indir_tbl; 3810 3811 /* Fill out the redirection table as follows: 3812 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3813 * indices. 3814 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3815 * - X550: 8 bit wide entries containing 6 bit RSS index 3816 */ 3817 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3818 indices_multi = 0x11; 3819 else 3820 indices_multi = 0x1; 3821 3822 /* Write redirection table to HW */ 3823 for (i = 0; i < reta_entries; i++) { 3824 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3825 if ((i & 3) == 3) { 3826 if (i < 128) 3827 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3828 else 3829 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3830 reta); 3831 reta = 0; 3832 } 3833 } 3834 } 3835 3836 /** 3837 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3838 * @adapter: device handle 3839 * 3840 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3841 */ 3842 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3843 { 3844 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3845 struct ixgbe_hw *hw = &adapter->hw; 3846 u32 vfreta = 0; 3847 3848 /* Write redirection table to HW */ 3849 for (i = 0; i < reta_entries; i++) { 3850 u16 pool = adapter->num_rx_pools; 3851 3852 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3853 if ((i & 3) != 3) 3854 continue; 3855 3856 while (pool--) 3857 IXGBE_WRITE_REG(hw, 3858 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3859 vfreta); 3860 vfreta = 0; 3861 } 3862 } 3863 3864 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3865 { 3866 u32 i, j; 3867 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3868 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3869 3870 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3871 * make full use of any rings they may have. We will use the 3872 * PSRTYPE register to control how many rings we use within the PF. 3873 */ 3874 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3875 rss_i = 4; 3876 3877 /* Fill out hash function seeds */ 3878 ixgbe_store_key(adapter); 3879 3880 /* Fill out redirection table */ 3881 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3882 3883 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3884 if (j == rss_i) 3885 j = 0; 3886 3887 adapter->rss_indir_tbl[i] = j; 3888 } 3889 3890 ixgbe_store_reta(adapter); 3891 } 3892 3893 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3894 { 3895 struct ixgbe_hw *hw = &adapter->hw; 3896 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3897 int i, j; 3898 3899 /* Fill out hash function seeds */ 3900 for (i = 0; i < 10; i++) { 3901 u16 pool = adapter->num_rx_pools; 3902 3903 while (pool--) 3904 IXGBE_WRITE_REG(hw, 3905 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3906 *(adapter->rss_key + i)); 3907 } 3908 3909 /* Fill out the redirection table */ 3910 for (i = 0, j = 0; i < 64; i++, j++) { 3911 if (j == rss_i) 3912 j = 0; 3913 3914 adapter->rss_indir_tbl[i] = j; 3915 } 3916 3917 ixgbe_store_vfreta(adapter); 3918 } 3919 3920 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3921 { 3922 struct ixgbe_hw *hw = &adapter->hw; 3923 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3924 u32 rxcsum; 3925 3926 /* Disable indicating checksum in descriptor, enables RSS hash */ 3927 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3928 rxcsum |= IXGBE_RXCSUM_PCSD; 3929 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3930 3931 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3932 if (adapter->ring_feature[RING_F_RSS].mask) 3933 mrqc = IXGBE_MRQC_RSSEN; 3934 } else { 3935 u8 tcs = adapter->hw_tcs; 3936 3937 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3938 if (tcs > 4) 3939 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3940 else if (tcs > 1) 3941 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3942 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3943 IXGBE_82599_VMDQ_4Q_MASK) 3944 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3945 else 3946 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3947 3948 /* Enable L3/L4 for Tx Switched packets only for X550, 3949 * older devices do not support this feature 3950 */ 3951 if (hw->mac.type >= ixgbe_mac_X550) 3952 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3953 } else { 3954 if (tcs > 4) 3955 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3956 else if (tcs > 1) 3957 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3958 else 3959 mrqc = IXGBE_MRQC_RSSEN; 3960 } 3961 } 3962 3963 /* Perform hash on these packet types */ 3964 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3965 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3966 IXGBE_MRQC_RSS_FIELD_IPV6 | 3967 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3968 3969 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3970 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3971 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3972 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3973 3974 if ((hw->mac.type >= ixgbe_mac_X550) && 3975 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3976 u16 pool = adapter->num_rx_pools; 3977 3978 /* Enable VF RSS mode */ 3979 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3980 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3981 3982 /* Setup RSS through the VF registers */ 3983 ixgbe_setup_vfreta(adapter); 3984 vfmrqc = IXGBE_MRQC_RSSEN; 3985 vfmrqc |= rss_field; 3986 3987 while (pool--) 3988 IXGBE_WRITE_REG(hw, 3989 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3990 vfmrqc); 3991 } else { 3992 ixgbe_setup_reta(adapter); 3993 mrqc |= rss_field; 3994 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3995 } 3996 } 3997 3998 /** 3999 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4000 * @adapter: address of board private structure 4001 * @ring: structure containing ring specific data 4002 **/ 4003 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4004 struct ixgbe_ring *ring) 4005 { 4006 struct ixgbe_hw *hw = &adapter->hw; 4007 u32 rscctrl; 4008 u8 reg_idx = ring->reg_idx; 4009 4010 if (!ring_is_rsc_enabled(ring)) 4011 return; 4012 4013 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4014 rscctrl |= IXGBE_RSCCTL_RSCEN; 4015 /* 4016 * we must limit the number of descriptors so that the 4017 * total size of max desc * buf_len is not greater 4018 * than 65536 4019 */ 4020 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4021 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4022 } 4023 4024 #define IXGBE_MAX_RX_DESC_POLL 10 4025 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4026 struct ixgbe_ring *ring) 4027 { 4028 struct ixgbe_hw *hw = &adapter->hw; 4029 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4030 u32 rxdctl; 4031 u8 reg_idx = ring->reg_idx; 4032 4033 if (ixgbe_removed(hw->hw_addr)) 4034 return; 4035 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4036 if (hw->mac.type == ixgbe_mac_82598EB && 4037 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4038 return; 4039 4040 do { 4041 usleep_range(1000, 2000); 4042 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4043 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4044 4045 if (!wait_loop) { 4046 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4047 "the polling period\n", reg_idx); 4048 } 4049 } 4050 4051 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4052 struct ixgbe_ring *ring) 4053 { 4054 struct ixgbe_hw *hw = &adapter->hw; 4055 union ixgbe_adv_rx_desc *rx_desc; 4056 u64 rdba = ring->dma; 4057 u32 rxdctl; 4058 u8 reg_idx = ring->reg_idx; 4059 4060 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4061 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4062 if (ring->xsk_pool) { 4063 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4064 MEM_TYPE_XSK_BUFF_POOL, 4065 NULL)); 4066 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4067 } else { 4068 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4069 MEM_TYPE_PAGE_SHARED, NULL)); 4070 } 4071 4072 /* disable queue to avoid use of these values while updating state */ 4073 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4074 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4075 4076 /* write value back with RXDCTL.ENABLE bit cleared */ 4077 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4078 IXGBE_WRITE_FLUSH(hw); 4079 4080 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4081 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4082 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4083 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4084 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4085 IXGBE_WRITE_FLUSH(hw); 4086 4087 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4088 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4089 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4090 4091 ixgbe_configure_srrctl(adapter, ring); 4092 ixgbe_configure_rscctl(adapter, ring); 4093 4094 if (hw->mac.type == ixgbe_mac_82598EB) { 4095 /* 4096 * enable cache line friendly hardware writes: 4097 * PTHRESH=32 descriptors (half the internal cache), 4098 * this also removes ugly rx_no_buffer_count increment 4099 * HTHRESH=4 descriptors (to minimize latency on fetch) 4100 * WTHRESH=8 burst writeback up to two cache lines 4101 */ 4102 rxdctl &= ~0x3FFFFF; 4103 rxdctl |= 0x080420; 4104 #if (PAGE_SIZE < 8192) 4105 /* RXDCTL.RLPML does not work on 82599 */ 4106 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4107 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4108 IXGBE_RXDCTL_RLPML_EN); 4109 4110 /* Limit the maximum frame size so we don't overrun the skb. 4111 * This can happen in SRIOV mode when the MTU of the VF is 4112 * higher than the MTU of the PF. 4113 */ 4114 if (ring_uses_build_skb(ring) && 4115 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4116 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4117 IXGBE_RXDCTL_RLPML_EN; 4118 #endif 4119 } 4120 4121 ring->rx_offset = ixgbe_rx_offset(ring); 4122 4123 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4124 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4125 4126 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4127 IXGBE_RXDCTL_RLPML_EN); 4128 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4129 4130 ring->rx_buf_len = xsk_buf_len; 4131 } 4132 4133 /* initialize rx_buffer_info */ 4134 memset(ring->rx_buffer_info, 0, 4135 sizeof(struct ixgbe_rx_buffer) * ring->count); 4136 4137 /* initialize Rx descriptor 0 */ 4138 rx_desc = IXGBE_RX_DESC(ring, 0); 4139 rx_desc->wb.upper.length = 0; 4140 4141 /* enable receive descriptor ring */ 4142 rxdctl |= IXGBE_RXDCTL_ENABLE; 4143 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4144 4145 ixgbe_rx_desc_queue_enable(adapter, ring); 4146 if (ring->xsk_pool) 4147 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4148 else 4149 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4150 } 4151 4152 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4153 { 4154 struct ixgbe_hw *hw = &adapter->hw; 4155 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4156 u16 pool = adapter->num_rx_pools; 4157 4158 /* PSRTYPE must be initialized in non 82598 adapters */ 4159 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4160 IXGBE_PSRTYPE_UDPHDR | 4161 IXGBE_PSRTYPE_IPV4HDR | 4162 IXGBE_PSRTYPE_L2HDR | 4163 IXGBE_PSRTYPE_IPV6HDR; 4164 4165 if (hw->mac.type == ixgbe_mac_82598EB) 4166 return; 4167 4168 if (rss_i > 3) 4169 psrtype |= 2u << 29; 4170 else if (rss_i > 1) 4171 psrtype |= 1u << 29; 4172 4173 while (pool--) 4174 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4175 } 4176 4177 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4178 { 4179 struct ixgbe_hw *hw = &adapter->hw; 4180 u16 pool = adapter->num_rx_pools; 4181 u32 reg_offset, vf_shift, vmolr; 4182 u32 gcr_ext, vmdctl; 4183 int i; 4184 4185 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4186 return; 4187 4188 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4189 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4190 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4191 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4192 vmdctl |= IXGBE_VT_CTL_REPLEN; 4193 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4194 4195 /* accept untagged packets until a vlan tag is 4196 * specifically set for the VMDQ queue/pool 4197 */ 4198 vmolr = IXGBE_VMOLR_AUPE; 4199 while (pool--) 4200 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4201 4202 vf_shift = VMDQ_P(0) % 32; 4203 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4204 4205 /* Enable only the PF's pool for Tx/Rx */ 4206 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4207 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4208 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4209 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4210 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4211 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4212 4213 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4214 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4215 4216 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4217 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4218 4219 /* 4220 * Set up VF register offsets for selected VT Mode, 4221 * i.e. 32 or 64 VFs for SR-IOV 4222 */ 4223 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4224 case IXGBE_82599_VMDQ_8Q_MASK: 4225 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4226 break; 4227 case IXGBE_82599_VMDQ_4Q_MASK: 4228 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4229 break; 4230 default: 4231 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4232 break; 4233 } 4234 4235 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4236 4237 for (i = 0; i < adapter->num_vfs; i++) { 4238 /* configure spoof checking */ 4239 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4240 adapter->vfinfo[i].spoofchk_enabled); 4241 4242 /* Enable/Disable RSS query feature */ 4243 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4244 adapter->vfinfo[i].rss_query_enabled); 4245 } 4246 } 4247 4248 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4249 { 4250 struct ixgbe_hw *hw = &adapter->hw; 4251 struct net_device *netdev = adapter->netdev; 4252 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4253 struct ixgbe_ring *rx_ring; 4254 int i; 4255 u32 mhadd, hlreg0; 4256 4257 #ifdef IXGBE_FCOE 4258 /* adjust max frame to be able to do baby jumbo for FCoE */ 4259 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4260 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4261 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4262 4263 #endif /* IXGBE_FCOE */ 4264 4265 /* adjust max frame to be at least the size of a standard frame */ 4266 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4267 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4268 4269 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4270 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4271 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4272 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4273 4274 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4275 } 4276 4277 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4278 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4279 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4280 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4281 4282 /* 4283 * Setup the HW Rx Head and Tail Descriptor Pointers and 4284 * the Base and Length of the Rx Descriptor Ring 4285 */ 4286 for (i = 0; i < adapter->num_rx_queues; i++) { 4287 rx_ring = adapter->rx_ring[i]; 4288 4289 clear_ring_rsc_enabled(rx_ring); 4290 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4291 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4292 4293 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4294 set_ring_rsc_enabled(rx_ring); 4295 4296 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4297 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4298 4299 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4300 continue; 4301 4302 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4303 4304 #if (PAGE_SIZE < 8192) 4305 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4306 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4307 4308 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4309 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4310 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4311 #endif 4312 } 4313 } 4314 4315 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4316 { 4317 struct ixgbe_hw *hw = &adapter->hw; 4318 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4319 4320 switch (hw->mac.type) { 4321 case ixgbe_mac_82598EB: 4322 /* 4323 * For VMDq support of different descriptor types or 4324 * buffer sizes through the use of multiple SRRCTL 4325 * registers, RDRXCTL.MVMEN must be set to 1 4326 * 4327 * also, the manual doesn't mention it clearly but DCA hints 4328 * will only use queue 0's tags unless this bit is set. Side 4329 * effects of setting this bit are only that SRRCTL must be 4330 * fully programmed [0..15] 4331 */ 4332 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4333 break; 4334 case ixgbe_mac_X550: 4335 case ixgbe_mac_X550EM_x: 4336 case ixgbe_mac_x550em_a: 4337 if (adapter->num_vfs) 4338 rdrxctl |= IXGBE_RDRXCTL_PSP; 4339 fallthrough; 4340 case ixgbe_mac_82599EB: 4341 case ixgbe_mac_X540: 4342 /* Disable RSC for ACK packets */ 4343 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4344 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4345 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4346 /* hardware requires some bits to be set by default */ 4347 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4348 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4349 break; 4350 default: 4351 /* We should do nothing since we don't know this hardware */ 4352 return; 4353 } 4354 4355 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4356 } 4357 4358 /** 4359 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4360 * @adapter: board private structure 4361 * 4362 * Configure the Rx unit of the MAC after a reset. 4363 **/ 4364 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4365 { 4366 struct ixgbe_hw *hw = &adapter->hw; 4367 int i; 4368 u32 rxctrl, rfctl; 4369 4370 /* disable receives while setting up the descriptors */ 4371 hw->mac.ops.disable_rx(hw); 4372 4373 ixgbe_setup_psrtype(adapter); 4374 ixgbe_setup_rdrxctl(adapter); 4375 4376 /* RSC Setup */ 4377 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4378 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4379 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4380 rfctl |= IXGBE_RFCTL_RSC_DIS; 4381 4382 /* disable NFS filtering */ 4383 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4384 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4385 4386 /* Program registers for the distribution of queues */ 4387 ixgbe_setup_mrqc(adapter); 4388 4389 /* set_rx_buffer_len must be called before ring initialization */ 4390 ixgbe_set_rx_buffer_len(adapter); 4391 4392 /* 4393 * Setup the HW Rx Head and Tail Descriptor Pointers and 4394 * the Base and Length of the Rx Descriptor Ring 4395 */ 4396 for (i = 0; i < adapter->num_rx_queues; i++) 4397 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4398 4399 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4400 /* disable drop enable for 82598 parts */ 4401 if (hw->mac.type == ixgbe_mac_82598EB) 4402 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4403 4404 /* enable all receives */ 4405 rxctrl |= IXGBE_RXCTRL_RXEN; 4406 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4407 } 4408 4409 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4410 __be16 proto, u16 vid) 4411 { 4412 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4413 struct ixgbe_hw *hw = &adapter->hw; 4414 4415 /* add VID to filter table */ 4416 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4417 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4418 4419 set_bit(vid, adapter->active_vlans); 4420 4421 return 0; 4422 } 4423 4424 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4425 { 4426 u32 vlvf; 4427 int idx; 4428 4429 /* short cut the special case */ 4430 if (vlan == 0) 4431 return 0; 4432 4433 /* Search for the vlan id in the VLVF entries */ 4434 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4435 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4436 if ((vlvf & VLAN_VID_MASK) == vlan) 4437 break; 4438 } 4439 4440 return idx; 4441 } 4442 4443 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4444 { 4445 struct ixgbe_hw *hw = &adapter->hw; 4446 u32 bits, word; 4447 int idx; 4448 4449 idx = ixgbe_find_vlvf_entry(hw, vid); 4450 if (!idx) 4451 return; 4452 4453 /* See if any other pools are set for this VLAN filter 4454 * entry other than the PF. 4455 */ 4456 word = idx * 2 + (VMDQ_P(0) / 32); 4457 bits = ~BIT(VMDQ_P(0) % 32); 4458 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4459 4460 /* Disable the filter so this falls into the default pool. */ 4461 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4462 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4463 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4464 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4465 } 4466 } 4467 4468 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4469 __be16 proto, u16 vid) 4470 { 4471 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4472 struct ixgbe_hw *hw = &adapter->hw; 4473 4474 /* remove VID from filter table */ 4475 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4476 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4477 4478 clear_bit(vid, adapter->active_vlans); 4479 4480 return 0; 4481 } 4482 4483 /** 4484 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4485 * @adapter: driver data 4486 */ 4487 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4488 { 4489 struct ixgbe_hw *hw = &adapter->hw; 4490 u32 vlnctrl; 4491 int i, j; 4492 4493 switch (hw->mac.type) { 4494 case ixgbe_mac_82598EB: 4495 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4496 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4497 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4498 break; 4499 case ixgbe_mac_82599EB: 4500 case ixgbe_mac_X540: 4501 case ixgbe_mac_X550: 4502 case ixgbe_mac_X550EM_x: 4503 case ixgbe_mac_x550em_a: 4504 for (i = 0; i < adapter->num_rx_queues; i++) { 4505 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4506 4507 if (!netif_is_ixgbe(ring->netdev)) 4508 continue; 4509 4510 j = ring->reg_idx; 4511 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4512 vlnctrl &= ~IXGBE_RXDCTL_VME; 4513 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4514 } 4515 break; 4516 default: 4517 break; 4518 } 4519 } 4520 4521 /** 4522 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4523 * @adapter: driver data 4524 */ 4525 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4526 { 4527 struct ixgbe_hw *hw = &adapter->hw; 4528 u32 vlnctrl; 4529 int i, j; 4530 4531 switch (hw->mac.type) { 4532 case ixgbe_mac_82598EB: 4533 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4534 vlnctrl |= IXGBE_VLNCTRL_VME; 4535 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4536 break; 4537 case ixgbe_mac_82599EB: 4538 case ixgbe_mac_X540: 4539 case ixgbe_mac_X550: 4540 case ixgbe_mac_X550EM_x: 4541 case ixgbe_mac_x550em_a: 4542 for (i = 0; i < adapter->num_rx_queues; i++) { 4543 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4544 4545 if (!netif_is_ixgbe(ring->netdev)) 4546 continue; 4547 4548 j = ring->reg_idx; 4549 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4550 vlnctrl |= IXGBE_RXDCTL_VME; 4551 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4552 } 4553 break; 4554 default: 4555 break; 4556 } 4557 } 4558 4559 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4560 { 4561 struct ixgbe_hw *hw = &adapter->hw; 4562 u32 vlnctrl, i; 4563 4564 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4565 4566 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4567 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4568 vlnctrl |= IXGBE_VLNCTRL_VFE; 4569 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4570 } else { 4571 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4572 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4573 return; 4574 } 4575 4576 /* Nothing to do for 82598 */ 4577 if (hw->mac.type == ixgbe_mac_82598EB) 4578 return; 4579 4580 /* We are already in VLAN promisc, nothing to do */ 4581 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4582 return; 4583 4584 /* Set flag so we don't redo unnecessary work */ 4585 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4586 4587 /* Add PF to all active pools */ 4588 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4589 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4590 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4591 4592 vlvfb |= BIT(VMDQ_P(0) % 32); 4593 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4594 } 4595 4596 /* Set all bits in the VLAN filter table array */ 4597 for (i = hw->mac.vft_size; i--;) 4598 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4599 } 4600 4601 #define VFTA_BLOCK_SIZE 8 4602 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4603 { 4604 struct ixgbe_hw *hw = &adapter->hw; 4605 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4606 u32 vid_start = vfta_offset * 32; 4607 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4608 u32 i, vid, word, bits; 4609 4610 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4611 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4612 4613 /* pull VLAN ID from VLVF */ 4614 vid = vlvf & VLAN_VID_MASK; 4615 4616 /* only concern outselves with a certain range */ 4617 if (vid < vid_start || vid >= vid_end) 4618 continue; 4619 4620 if (vlvf) { 4621 /* record VLAN ID in VFTA */ 4622 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4623 4624 /* if PF is part of this then continue */ 4625 if (test_bit(vid, adapter->active_vlans)) 4626 continue; 4627 } 4628 4629 /* remove PF from the pool */ 4630 word = i * 2 + VMDQ_P(0) / 32; 4631 bits = ~BIT(VMDQ_P(0) % 32); 4632 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4633 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4634 } 4635 4636 /* extract values from active_vlans and write back to VFTA */ 4637 for (i = VFTA_BLOCK_SIZE; i--;) { 4638 vid = (vfta_offset + i) * 32; 4639 word = vid / BITS_PER_LONG; 4640 bits = vid % BITS_PER_LONG; 4641 4642 vfta[i] |= adapter->active_vlans[word] >> bits; 4643 4644 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4645 } 4646 } 4647 4648 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4649 { 4650 struct ixgbe_hw *hw = &adapter->hw; 4651 u32 vlnctrl, i; 4652 4653 /* Set VLAN filtering to enabled */ 4654 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4655 vlnctrl |= IXGBE_VLNCTRL_VFE; 4656 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4657 4658 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4659 hw->mac.type == ixgbe_mac_82598EB) 4660 return; 4661 4662 /* We are not in VLAN promisc, nothing to do */ 4663 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4664 return; 4665 4666 /* Set flag so we don't redo unnecessary work */ 4667 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4668 4669 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4670 ixgbe_scrub_vfta(adapter, i); 4671 } 4672 4673 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4674 { 4675 u16 vid = 1; 4676 4677 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4678 4679 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4680 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4681 } 4682 4683 /** 4684 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4685 * @netdev: network interface device structure 4686 * 4687 * Writes multicast address list to the MTA hash table. 4688 * Returns: -ENOMEM on failure 4689 * 0 on no addresses written 4690 * X on writing X addresses to MTA 4691 **/ 4692 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4693 { 4694 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4695 struct ixgbe_hw *hw = &adapter->hw; 4696 4697 if (!netif_running(netdev)) 4698 return 0; 4699 4700 if (hw->mac.ops.update_mc_addr_list) 4701 hw->mac.ops.update_mc_addr_list(hw, netdev); 4702 else 4703 return -ENOMEM; 4704 4705 #ifdef CONFIG_PCI_IOV 4706 ixgbe_restore_vf_multicasts(adapter); 4707 #endif 4708 4709 return netdev_mc_count(netdev); 4710 } 4711 4712 #ifdef CONFIG_PCI_IOV 4713 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4714 { 4715 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4716 struct ixgbe_hw *hw = &adapter->hw; 4717 int i; 4718 4719 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4720 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4721 4722 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4723 hw->mac.ops.set_rar(hw, i, 4724 mac_table->addr, 4725 mac_table->pool, 4726 IXGBE_RAH_AV); 4727 else 4728 hw->mac.ops.clear_rar(hw, i); 4729 } 4730 } 4731 4732 #endif 4733 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4734 { 4735 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4736 struct ixgbe_hw *hw = &adapter->hw; 4737 int i; 4738 4739 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4740 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4741 continue; 4742 4743 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4744 4745 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4746 hw->mac.ops.set_rar(hw, i, 4747 mac_table->addr, 4748 mac_table->pool, 4749 IXGBE_RAH_AV); 4750 else 4751 hw->mac.ops.clear_rar(hw, i); 4752 } 4753 } 4754 4755 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4756 { 4757 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4758 struct ixgbe_hw *hw = &adapter->hw; 4759 int i; 4760 4761 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4762 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4763 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4764 } 4765 4766 ixgbe_sync_mac_table(adapter); 4767 } 4768 4769 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4770 { 4771 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4772 struct ixgbe_hw *hw = &adapter->hw; 4773 int i, count = 0; 4774 4775 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4776 /* do not count default RAR as available */ 4777 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4778 continue; 4779 4780 /* only count unused and addresses that belong to us */ 4781 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4782 if (mac_table->pool != pool) 4783 continue; 4784 } 4785 4786 count++; 4787 } 4788 4789 return count; 4790 } 4791 4792 /* this function destroys the first RAR entry */ 4793 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4794 { 4795 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4796 struct ixgbe_hw *hw = &adapter->hw; 4797 4798 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4799 mac_table->pool = VMDQ_P(0); 4800 4801 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4802 4803 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4804 IXGBE_RAH_AV); 4805 } 4806 4807 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4808 const u8 *addr, u16 pool) 4809 { 4810 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4811 struct ixgbe_hw *hw = &adapter->hw; 4812 int i; 4813 4814 if (is_zero_ether_addr(addr)) 4815 return -EINVAL; 4816 4817 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4818 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4819 continue; 4820 4821 ether_addr_copy(mac_table->addr, addr); 4822 mac_table->pool = pool; 4823 4824 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4825 IXGBE_MAC_STATE_IN_USE; 4826 4827 ixgbe_sync_mac_table(adapter); 4828 4829 return i; 4830 } 4831 4832 return -ENOMEM; 4833 } 4834 4835 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4836 const u8 *addr, u16 pool) 4837 { 4838 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4839 struct ixgbe_hw *hw = &adapter->hw; 4840 int i; 4841 4842 if (is_zero_ether_addr(addr)) 4843 return -EINVAL; 4844 4845 /* search table for addr, if found clear IN_USE flag and sync */ 4846 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4847 /* we can only delete an entry if it is in use */ 4848 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4849 continue; 4850 /* we only care about entries that belong to the given pool */ 4851 if (mac_table->pool != pool) 4852 continue; 4853 /* we only care about a specific MAC address */ 4854 if (!ether_addr_equal(addr, mac_table->addr)) 4855 continue; 4856 4857 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4858 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4859 4860 ixgbe_sync_mac_table(adapter); 4861 4862 return 0; 4863 } 4864 4865 return -ENOMEM; 4866 } 4867 4868 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4869 { 4870 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4871 int ret; 4872 4873 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4874 4875 return min_t(int, ret, 0); 4876 } 4877 4878 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4879 { 4880 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4881 4882 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4883 4884 return 0; 4885 } 4886 4887 /** 4888 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4889 * @netdev: network interface device structure 4890 * 4891 * The set_rx_method entry point is called whenever the unicast/multicast 4892 * address list or the network interface flags are updated. This routine is 4893 * responsible for configuring the hardware for proper unicast, multicast and 4894 * promiscuous mode. 4895 **/ 4896 void ixgbe_set_rx_mode(struct net_device *netdev) 4897 { 4898 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4899 struct ixgbe_hw *hw = &adapter->hw; 4900 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4901 netdev_features_t features = netdev->features; 4902 int count; 4903 4904 /* Check for Promiscuous and All Multicast modes */ 4905 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4906 4907 /* set all bits that we expect to always be set */ 4908 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4909 fctrl |= IXGBE_FCTRL_BAM; 4910 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4911 fctrl |= IXGBE_FCTRL_PMCF; 4912 4913 /* clear the bits we are changing the status of */ 4914 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4915 if (netdev->flags & IFF_PROMISC) { 4916 hw->addr_ctrl.user_set_promisc = true; 4917 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4918 vmolr |= IXGBE_VMOLR_MPE; 4919 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4920 } else { 4921 if (netdev->flags & IFF_ALLMULTI) { 4922 fctrl |= IXGBE_FCTRL_MPE; 4923 vmolr |= IXGBE_VMOLR_MPE; 4924 } 4925 hw->addr_ctrl.user_set_promisc = false; 4926 } 4927 4928 /* 4929 * Write addresses to available RAR registers, if there is not 4930 * sufficient space to store all the addresses then enable 4931 * unicast promiscuous mode 4932 */ 4933 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4934 fctrl |= IXGBE_FCTRL_UPE; 4935 vmolr |= IXGBE_VMOLR_ROPE; 4936 } 4937 4938 /* Write addresses to the MTA, if the attempt fails 4939 * then we should just turn on promiscuous mode so 4940 * that we can at least receive multicast traffic 4941 */ 4942 count = ixgbe_write_mc_addr_list(netdev); 4943 if (count < 0) { 4944 fctrl |= IXGBE_FCTRL_MPE; 4945 vmolr |= IXGBE_VMOLR_MPE; 4946 } else if (count) { 4947 vmolr |= IXGBE_VMOLR_ROMPE; 4948 } 4949 4950 if (hw->mac.type != ixgbe_mac_82598EB) { 4951 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4952 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4953 IXGBE_VMOLR_ROPE); 4954 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4955 } 4956 4957 /* This is useful for sniffing bad packets. */ 4958 if (features & NETIF_F_RXALL) { 4959 /* UPE and MPE will be handled by normal PROMISC logic 4960 * in e1000e_set_rx_mode */ 4961 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4962 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4963 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4964 4965 fctrl &= ~(IXGBE_FCTRL_DPF); 4966 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4967 } 4968 4969 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4970 4971 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4972 ixgbe_vlan_strip_enable(adapter); 4973 else 4974 ixgbe_vlan_strip_disable(adapter); 4975 4976 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4977 ixgbe_vlan_promisc_disable(adapter); 4978 else 4979 ixgbe_vlan_promisc_enable(adapter); 4980 } 4981 4982 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4983 { 4984 int q_idx; 4985 4986 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4987 napi_enable(&adapter->q_vector[q_idx]->napi); 4988 } 4989 4990 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4991 { 4992 int q_idx; 4993 4994 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4995 napi_disable(&adapter->q_vector[q_idx]->napi); 4996 } 4997 4998 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 4999 { 5000 struct ixgbe_adapter *adapter = netdev_priv(dev); 5001 struct ixgbe_hw *hw = &adapter->hw; 5002 struct udp_tunnel_info ti; 5003 5004 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5005 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5006 adapter->vxlan_port = ti.port; 5007 else 5008 adapter->geneve_port = ti.port; 5009 5010 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5011 ntohs(adapter->vxlan_port) | 5012 ntohs(adapter->geneve_port) << 5013 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5014 return 0; 5015 } 5016 5017 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5018 .sync_table = ixgbe_udp_tunnel_sync, 5019 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5020 .tables = { 5021 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5022 }, 5023 }; 5024 5025 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5026 .sync_table = ixgbe_udp_tunnel_sync, 5027 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5028 .tables = { 5029 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5030 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5031 }, 5032 }; 5033 5034 #ifdef CONFIG_IXGBE_DCB 5035 /** 5036 * ixgbe_configure_dcb - Configure DCB hardware 5037 * @adapter: ixgbe adapter struct 5038 * 5039 * This is called by the driver on open to configure the DCB hardware. 5040 * This is also called by the gennetlink interface when reconfiguring 5041 * the DCB state. 5042 */ 5043 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5044 { 5045 struct ixgbe_hw *hw = &adapter->hw; 5046 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5047 5048 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5049 if (hw->mac.type == ixgbe_mac_82598EB) 5050 netif_set_gso_max_size(adapter->netdev, 65536); 5051 return; 5052 } 5053 5054 if (hw->mac.type == ixgbe_mac_82598EB) 5055 netif_set_gso_max_size(adapter->netdev, 32768); 5056 5057 #ifdef IXGBE_FCOE 5058 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5059 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5060 #endif 5061 5062 /* reconfigure the hardware */ 5063 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5064 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5065 DCB_TX_CONFIG); 5066 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5067 DCB_RX_CONFIG); 5068 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5069 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5070 ixgbe_dcb_hw_ets(&adapter->hw, 5071 adapter->ixgbe_ieee_ets, 5072 max_frame); 5073 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5074 adapter->ixgbe_ieee_pfc->pfc_en, 5075 adapter->ixgbe_ieee_ets->prio_tc); 5076 } 5077 5078 /* Enable RSS Hash per TC */ 5079 if (hw->mac.type != ixgbe_mac_82598EB) { 5080 u32 msb = 0; 5081 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5082 5083 while (rss_i) { 5084 msb++; 5085 rss_i >>= 1; 5086 } 5087 5088 /* write msb to all 8 TCs in one write */ 5089 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5090 } 5091 } 5092 #endif 5093 5094 /* Additional bittime to account for IXGBE framing */ 5095 #define IXGBE_ETH_FRAMING 20 5096 5097 /** 5098 * ixgbe_hpbthresh - calculate high water mark for flow control 5099 * 5100 * @adapter: board private structure to calculate for 5101 * @pb: packet buffer to calculate 5102 */ 5103 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5104 { 5105 struct ixgbe_hw *hw = &adapter->hw; 5106 struct net_device *dev = adapter->netdev; 5107 int link, tc, kb, marker; 5108 u32 dv_id, rx_pba; 5109 5110 /* Calculate max LAN frame size */ 5111 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5112 5113 #ifdef IXGBE_FCOE 5114 /* FCoE traffic class uses FCOE jumbo frames */ 5115 if ((dev->features & NETIF_F_FCOE_MTU) && 5116 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5117 (pb == ixgbe_fcoe_get_tc(adapter))) 5118 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5119 #endif 5120 5121 /* Calculate delay value for device */ 5122 switch (hw->mac.type) { 5123 case ixgbe_mac_X540: 5124 case ixgbe_mac_X550: 5125 case ixgbe_mac_X550EM_x: 5126 case ixgbe_mac_x550em_a: 5127 dv_id = IXGBE_DV_X540(link, tc); 5128 break; 5129 default: 5130 dv_id = IXGBE_DV(link, tc); 5131 break; 5132 } 5133 5134 /* Loopback switch introduces additional latency */ 5135 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5136 dv_id += IXGBE_B2BT(tc); 5137 5138 /* Delay value is calculated in bit times convert to KB */ 5139 kb = IXGBE_BT2KB(dv_id); 5140 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5141 5142 marker = rx_pba - kb; 5143 5144 /* It is possible that the packet buffer is not large enough 5145 * to provide required headroom. In this case throw an error 5146 * to user and a do the best we can. 5147 */ 5148 if (marker < 0) { 5149 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5150 "headroom to support flow control." 5151 "Decrease MTU or number of traffic classes\n", pb); 5152 marker = tc + 1; 5153 } 5154 5155 return marker; 5156 } 5157 5158 /** 5159 * ixgbe_lpbthresh - calculate low water mark for for flow control 5160 * 5161 * @adapter: board private structure to calculate for 5162 * @pb: packet buffer to calculate 5163 */ 5164 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5165 { 5166 struct ixgbe_hw *hw = &adapter->hw; 5167 struct net_device *dev = adapter->netdev; 5168 int tc; 5169 u32 dv_id; 5170 5171 /* Calculate max LAN frame size */ 5172 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5173 5174 #ifdef IXGBE_FCOE 5175 /* FCoE traffic class uses FCOE jumbo frames */ 5176 if ((dev->features & NETIF_F_FCOE_MTU) && 5177 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5178 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5179 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5180 #endif 5181 5182 /* Calculate delay value for device */ 5183 switch (hw->mac.type) { 5184 case ixgbe_mac_X540: 5185 case ixgbe_mac_X550: 5186 case ixgbe_mac_X550EM_x: 5187 case ixgbe_mac_x550em_a: 5188 dv_id = IXGBE_LOW_DV_X540(tc); 5189 break; 5190 default: 5191 dv_id = IXGBE_LOW_DV(tc); 5192 break; 5193 } 5194 5195 /* Delay value is calculated in bit times convert to KB */ 5196 return IXGBE_BT2KB(dv_id); 5197 } 5198 5199 /* 5200 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5201 */ 5202 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5203 { 5204 struct ixgbe_hw *hw = &adapter->hw; 5205 int num_tc = adapter->hw_tcs; 5206 int i; 5207 5208 if (!num_tc) 5209 num_tc = 1; 5210 5211 for (i = 0; i < num_tc; i++) { 5212 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5213 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5214 5215 /* Low water marks must not be larger than high water marks */ 5216 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5217 hw->fc.low_water[i] = 0; 5218 } 5219 5220 for (; i < MAX_TRAFFIC_CLASS; i++) 5221 hw->fc.high_water[i] = 0; 5222 } 5223 5224 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5225 { 5226 struct ixgbe_hw *hw = &adapter->hw; 5227 int hdrm; 5228 u8 tc = adapter->hw_tcs; 5229 5230 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5231 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5232 hdrm = 32 << adapter->fdir_pballoc; 5233 else 5234 hdrm = 0; 5235 5236 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5237 ixgbe_pbthresh_setup(adapter); 5238 } 5239 5240 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5241 { 5242 struct ixgbe_hw *hw = &adapter->hw; 5243 struct hlist_node *node2; 5244 struct ixgbe_fdir_filter *filter; 5245 u8 queue; 5246 5247 spin_lock(&adapter->fdir_perfect_lock); 5248 5249 if (!hlist_empty(&adapter->fdir_filter_list)) 5250 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5251 5252 hlist_for_each_entry_safe(filter, node2, 5253 &adapter->fdir_filter_list, fdir_node) { 5254 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5255 queue = IXGBE_FDIR_DROP_QUEUE; 5256 } else { 5257 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5258 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5259 5260 if (!vf && (ring >= adapter->num_rx_queues)) { 5261 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5262 ring); 5263 continue; 5264 } else if (vf && 5265 ((vf > adapter->num_vfs) || 5266 ring >= adapter->num_rx_queues_per_pool)) { 5267 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5268 vf, ring); 5269 continue; 5270 } 5271 5272 /* Map the ring onto the absolute queue index */ 5273 if (!vf) 5274 queue = adapter->rx_ring[ring]->reg_idx; 5275 else 5276 queue = ((vf - 1) * 5277 adapter->num_rx_queues_per_pool) + ring; 5278 } 5279 5280 ixgbe_fdir_write_perfect_filter_82599(hw, 5281 &filter->filter, filter->sw_idx, queue); 5282 } 5283 5284 spin_unlock(&adapter->fdir_perfect_lock); 5285 } 5286 5287 /** 5288 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5289 * @rx_ring: ring to free buffers from 5290 **/ 5291 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5292 { 5293 u16 i = rx_ring->next_to_clean; 5294 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5295 5296 if (rx_ring->xsk_pool) { 5297 ixgbe_xsk_clean_rx_ring(rx_ring); 5298 goto skip_free; 5299 } 5300 5301 /* Free all the Rx ring sk_buffs */ 5302 while (i != rx_ring->next_to_alloc) { 5303 if (rx_buffer->skb) { 5304 struct sk_buff *skb = rx_buffer->skb; 5305 if (IXGBE_CB(skb)->page_released) 5306 dma_unmap_page_attrs(rx_ring->dev, 5307 IXGBE_CB(skb)->dma, 5308 ixgbe_rx_pg_size(rx_ring), 5309 DMA_FROM_DEVICE, 5310 IXGBE_RX_DMA_ATTR); 5311 dev_kfree_skb(skb); 5312 } 5313 5314 /* Invalidate cache lines that may have been written to by 5315 * device so that we avoid corrupting memory. 5316 */ 5317 dma_sync_single_range_for_cpu(rx_ring->dev, 5318 rx_buffer->dma, 5319 rx_buffer->page_offset, 5320 ixgbe_rx_bufsz(rx_ring), 5321 DMA_FROM_DEVICE); 5322 5323 /* free resources associated with mapping */ 5324 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5325 ixgbe_rx_pg_size(rx_ring), 5326 DMA_FROM_DEVICE, 5327 IXGBE_RX_DMA_ATTR); 5328 __page_frag_cache_drain(rx_buffer->page, 5329 rx_buffer->pagecnt_bias); 5330 5331 i++; 5332 rx_buffer++; 5333 if (i == rx_ring->count) { 5334 i = 0; 5335 rx_buffer = rx_ring->rx_buffer_info; 5336 } 5337 } 5338 5339 skip_free: 5340 rx_ring->next_to_alloc = 0; 5341 rx_ring->next_to_clean = 0; 5342 rx_ring->next_to_use = 0; 5343 } 5344 5345 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5346 struct ixgbe_fwd_adapter *accel) 5347 { 5348 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5349 int num_tc = netdev_get_num_tc(adapter->netdev); 5350 struct net_device *vdev = accel->netdev; 5351 int i, baseq, err; 5352 5353 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5354 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5355 accel->pool, adapter->num_rx_pools, 5356 baseq, baseq + adapter->num_rx_queues_per_pool); 5357 5358 accel->rx_base_queue = baseq; 5359 accel->tx_base_queue = baseq; 5360 5361 /* record configuration for macvlan interface in vdev */ 5362 for (i = 0; i < num_tc; i++) 5363 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5364 i, rss_i, baseq + (rss_i * i)); 5365 5366 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5367 adapter->rx_ring[baseq + i]->netdev = vdev; 5368 5369 /* Guarantee all rings are updated before we update the 5370 * MAC address filter. 5371 */ 5372 wmb(); 5373 5374 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5375 * need to only treat it as an error value if it is negative. 5376 */ 5377 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5378 VMDQ_P(accel->pool)); 5379 if (err >= 0) 5380 return 0; 5381 5382 /* if we cannot add the MAC rule then disable the offload */ 5383 macvlan_release_l2fw_offload(vdev); 5384 5385 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5386 adapter->rx_ring[baseq + i]->netdev = NULL; 5387 5388 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5389 5390 /* unbind the queues and drop the subordinate channel config */ 5391 netdev_unbind_sb_channel(adapter->netdev, vdev); 5392 netdev_set_sb_channel(vdev, 0); 5393 5394 clear_bit(accel->pool, adapter->fwd_bitmask); 5395 kfree(accel); 5396 5397 return err; 5398 } 5399 5400 static int ixgbe_macvlan_up(struct net_device *vdev, 5401 struct netdev_nested_priv *priv) 5402 { 5403 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5404 struct ixgbe_fwd_adapter *accel; 5405 5406 if (!netif_is_macvlan(vdev)) 5407 return 0; 5408 5409 accel = macvlan_accel_priv(vdev); 5410 if (!accel) 5411 return 0; 5412 5413 ixgbe_fwd_ring_up(adapter, accel); 5414 5415 return 0; 5416 } 5417 5418 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5419 { 5420 struct netdev_nested_priv priv = { 5421 .data = (void *)adapter, 5422 }; 5423 5424 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5425 ixgbe_macvlan_up, &priv); 5426 } 5427 5428 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5429 { 5430 struct ixgbe_hw *hw = &adapter->hw; 5431 5432 ixgbe_configure_pb(adapter); 5433 #ifdef CONFIG_IXGBE_DCB 5434 ixgbe_configure_dcb(adapter); 5435 #endif 5436 /* 5437 * We must restore virtualization before VLANs or else 5438 * the VLVF registers will not be populated 5439 */ 5440 ixgbe_configure_virtualization(adapter); 5441 5442 ixgbe_set_rx_mode(adapter->netdev); 5443 ixgbe_restore_vlan(adapter); 5444 ixgbe_ipsec_restore(adapter); 5445 5446 switch (hw->mac.type) { 5447 case ixgbe_mac_82599EB: 5448 case ixgbe_mac_X540: 5449 hw->mac.ops.disable_rx_buff(hw); 5450 break; 5451 default: 5452 break; 5453 } 5454 5455 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5456 ixgbe_init_fdir_signature_82599(&adapter->hw, 5457 adapter->fdir_pballoc); 5458 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5459 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5460 adapter->fdir_pballoc); 5461 ixgbe_fdir_filter_restore(adapter); 5462 } 5463 5464 switch (hw->mac.type) { 5465 case ixgbe_mac_82599EB: 5466 case ixgbe_mac_X540: 5467 hw->mac.ops.enable_rx_buff(hw); 5468 break; 5469 default: 5470 break; 5471 } 5472 5473 #ifdef CONFIG_IXGBE_DCA 5474 /* configure DCA */ 5475 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5476 ixgbe_setup_dca(adapter); 5477 #endif /* CONFIG_IXGBE_DCA */ 5478 5479 #ifdef IXGBE_FCOE 5480 /* configure FCoE L2 filters, redirection table, and Rx control */ 5481 ixgbe_configure_fcoe(adapter); 5482 5483 #endif /* IXGBE_FCOE */ 5484 ixgbe_configure_tx(adapter); 5485 ixgbe_configure_rx(adapter); 5486 ixgbe_configure_dfwd(adapter); 5487 } 5488 5489 /** 5490 * ixgbe_sfp_link_config - set up SFP+ link 5491 * @adapter: pointer to private adapter struct 5492 **/ 5493 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5494 { 5495 /* 5496 * We are assuming the worst case scenario here, and that 5497 * is that an SFP was inserted/removed after the reset 5498 * but before SFP detection was enabled. As such the best 5499 * solution is to just start searching as soon as we start 5500 */ 5501 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5502 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5503 5504 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5505 adapter->sfp_poll_time = 0; 5506 } 5507 5508 /** 5509 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5510 * @hw: pointer to private hardware struct 5511 * 5512 * Returns 0 on success, negative on failure 5513 **/ 5514 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5515 { 5516 u32 speed; 5517 bool autoneg, link_up = false; 5518 int ret = IXGBE_ERR_LINK_SETUP; 5519 5520 if (hw->mac.ops.check_link) 5521 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5522 5523 if (ret) 5524 return ret; 5525 5526 speed = hw->phy.autoneg_advertised; 5527 if (!speed && hw->mac.ops.get_link_capabilities) { 5528 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5529 &autoneg); 5530 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 5531 IXGBE_LINK_SPEED_2_5GB_FULL); 5532 } 5533 5534 if (ret) 5535 return ret; 5536 5537 if (hw->mac.ops.setup_link) 5538 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5539 5540 return ret; 5541 } 5542 5543 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5544 { 5545 struct ixgbe_hw *hw = &adapter->hw; 5546 u32 gpie = 0; 5547 5548 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5549 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5550 IXGBE_GPIE_OCD; 5551 gpie |= IXGBE_GPIE_EIAME; 5552 /* 5553 * use EIAM to auto-mask when MSI-X interrupt is asserted 5554 * this saves a register write for every interrupt 5555 */ 5556 switch (hw->mac.type) { 5557 case ixgbe_mac_82598EB: 5558 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5559 break; 5560 case ixgbe_mac_82599EB: 5561 case ixgbe_mac_X540: 5562 case ixgbe_mac_X550: 5563 case ixgbe_mac_X550EM_x: 5564 case ixgbe_mac_x550em_a: 5565 default: 5566 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5567 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5568 break; 5569 } 5570 } else { 5571 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5572 * specifically only auto mask tx and rx interrupts */ 5573 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5574 } 5575 5576 /* XXX: to interrupt immediately for EICS writes, enable this */ 5577 /* gpie |= IXGBE_GPIE_EIMEN; */ 5578 5579 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5580 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5581 5582 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5583 case IXGBE_82599_VMDQ_8Q_MASK: 5584 gpie |= IXGBE_GPIE_VTMODE_16; 5585 break; 5586 case IXGBE_82599_VMDQ_4Q_MASK: 5587 gpie |= IXGBE_GPIE_VTMODE_32; 5588 break; 5589 default: 5590 gpie |= IXGBE_GPIE_VTMODE_64; 5591 break; 5592 } 5593 } 5594 5595 /* Enable Thermal over heat sensor interrupt */ 5596 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5597 switch (adapter->hw.mac.type) { 5598 case ixgbe_mac_82599EB: 5599 gpie |= IXGBE_SDP0_GPIEN_8259X; 5600 break; 5601 default: 5602 break; 5603 } 5604 } 5605 5606 /* Enable fan failure interrupt */ 5607 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5608 gpie |= IXGBE_SDP1_GPIEN(hw); 5609 5610 switch (hw->mac.type) { 5611 case ixgbe_mac_82599EB: 5612 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5613 break; 5614 case ixgbe_mac_X550EM_x: 5615 case ixgbe_mac_x550em_a: 5616 gpie |= IXGBE_SDP0_GPIEN_X540; 5617 break; 5618 default: 5619 break; 5620 } 5621 5622 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5623 } 5624 5625 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5626 { 5627 struct ixgbe_hw *hw = &adapter->hw; 5628 int err; 5629 u32 ctrl_ext; 5630 5631 ixgbe_get_hw_control(adapter); 5632 ixgbe_setup_gpie(adapter); 5633 5634 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5635 ixgbe_configure_msix(adapter); 5636 else 5637 ixgbe_configure_msi_and_legacy(adapter); 5638 5639 /* enable the optics for 82599 SFP+ fiber */ 5640 if (hw->mac.ops.enable_tx_laser) 5641 hw->mac.ops.enable_tx_laser(hw); 5642 5643 if (hw->phy.ops.set_phy_power) 5644 hw->phy.ops.set_phy_power(hw, true); 5645 5646 smp_mb__before_atomic(); 5647 clear_bit(__IXGBE_DOWN, &adapter->state); 5648 ixgbe_napi_enable_all(adapter); 5649 5650 if (ixgbe_is_sfp(hw)) { 5651 ixgbe_sfp_link_config(adapter); 5652 } else { 5653 err = ixgbe_non_sfp_link_config(hw); 5654 if (err) 5655 e_err(probe, "link_config FAILED %d\n", err); 5656 } 5657 5658 /* clear any pending interrupts, may auto mask */ 5659 IXGBE_READ_REG(hw, IXGBE_EICR); 5660 ixgbe_irq_enable(adapter, true, true); 5661 5662 /* 5663 * If this adapter has a fan, check to see if we had a failure 5664 * before we enabled the interrupt. 5665 */ 5666 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5667 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5668 if (esdp & IXGBE_ESDP_SDP1) 5669 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5670 } 5671 5672 /* bring the link up in the watchdog, this could race with our first 5673 * link up interrupt but shouldn't be a problem */ 5674 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5675 adapter->link_check_timeout = jiffies; 5676 mod_timer(&adapter->service_timer, jiffies); 5677 5678 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5679 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5680 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5681 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5682 } 5683 5684 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5685 { 5686 /* put off any impending NetWatchDogTimeout */ 5687 netif_trans_update(adapter->netdev); 5688 5689 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5690 usleep_range(1000, 2000); 5691 if (adapter->hw.phy.type == ixgbe_phy_fw) 5692 ixgbe_watchdog_link_is_down(adapter); 5693 ixgbe_down(adapter); 5694 /* 5695 * If SR-IOV enabled then wait a bit before bringing the adapter 5696 * back up to give the VFs time to respond to the reset. The 5697 * two second wait is based upon the watchdog timer cycle in 5698 * the VF driver. 5699 */ 5700 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5701 msleep(2000); 5702 ixgbe_up(adapter); 5703 clear_bit(__IXGBE_RESETTING, &adapter->state); 5704 } 5705 5706 void ixgbe_up(struct ixgbe_adapter *adapter) 5707 { 5708 /* hardware has been reset, we need to reload some things */ 5709 ixgbe_configure(adapter); 5710 5711 ixgbe_up_complete(adapter); 5712 } 5713 5714 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5715 { 5716 u16 devctl2; 5717 5718 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5719 5720 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5721 case IXGBE_PCIDEVCTRL2_17_34s: 5722 case IXGBE_PCIDEVCTRL2_4_8s: 5723 /* For now we cap the upper limit on delay to 2 seconds 5724 * as we end up going up to 34 seconds of delay in worst 5725 * case timeout value. 5726 */ 5727 case IXGBE_PCIDEVCTRL2_1_2s: 5728 return 2000000ul; /* 2.0 s */ 5729 case IXGBE_PCIDEVCTRL2_260_520ms: 5730 return 520000ul; /* 520 ms */ 5731 case IXGBE_PCIDEVCTRL2_65_130ms: 5732 return 130000ul; /* 130 ms */ 5733 case IXGBE_PCIDEVCTRL2_16_32ms: 5734 return 32000ul; /* 32 ms */ 5735 case IXGBE_PCIDEVCTRL2_1_2ms: 5736 return 2000ul; /* 2 ms */ 5737 case IXGBE_PCIDEVCTRL2_50_100us: 5738 return 100ul; /* 100 us */ 5739 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5740 return 32000ul; /* 32 ms */ 5741 default: 5742 break; 5743 } 5744 5745 /* We shouldn't need to hit this path, but just in case default as 5746 * though completion timeout is not supported and support 32ms. 5747 */ 5748 return 32000ul; 5749 } 5750 5751 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5752 { 5753 unsigned long wait_delay, delay_interval; 5754 struct ixgbe_hw *hw = &adapter->hw; 5755 int i, wait_loop; 5756 u32 rxdctl; 5757 5758 /* disable receives */ 5759 hw->mac.ops.disable_rx(hw); 5760 5761 if (ixgbe_removed(hw->hw_addr)) 5762 return; 5763 5764 /* disable all enabled Rx queues */ 5765 for (i = 0; i < adapter->num_rx_queues; i++) { 5766 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5767 u8 reg_idx = ring->reg_idx; 5768 5769 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5770 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5771 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5772 5773 /* write value back with RXDCTL.ENABLE bit cleared */ 5774 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5775 } 5776 5777 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5778 if (hw->mac.type == ixgbe_mac_82598EB && 5779 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5780 return; 5781 5782 /* Determine our minimum delay interval. We will increase this value 5783 * with each subsequent test. This way if the device returns quickly 5784 * we should spend as little time as possible waiting, however as 5785 * the time increases we will wait for larger periods of time. 5786 * 5787 * The trick here is that we increase the interval using the 5788 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5789 * of that wait is that it totals up to 100x whatever interval we 5790 * choose. Since our minimum wait is 100us we can just divide the 5791 * total timeout by 100 to get our minimum delay interval. 5792 */ 5793 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5794 5795 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5796 wait_delay = delay_interval; 5797 5798 while (wait_loop--) { 5799 usleep_range(wait_delay, wait_delay + 10); 5800 wait_delay += delay_interval * 2; 5801 rxdctl = 0; 5802 5803 /* OR together the reading of all the active RXDCTL registers, 5804 * and then test the result. We need the disable to complete 5805 * before we start freeing the memory and invalidating the 5806 * DMA mappings. 5807 */ 5808 for (i = 0; i < adapter->num_rx_queues; i++) { 5809 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5810 u8 reg_idx = ring->reg_idx; 5811 5812 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5813 } 5814 5815 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5816 return; 5817 } 5818 5819 e_err(drv, 5820 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5821 } 5822 5823 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5824 { 5825 unsigned long wait_delay, delay_interval; 5826 struct ixgbe_hw *hw = &adapter->hw; 5827 int i, wait_loop; 5828 u32 txdctl; 5829 5830 if (ixgbe_removed(hw->hw_addr)) 5831 return; 5832 5833 /* disable all enabled Tx queues */ 5834 for (i = 0; i < adapter->num_tx_queues; i++) { 5835 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5836 u8 reg_idx = ring->reg_idx; 5837 5838 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5839 } 5840 5841 /* disable all enabled XDP Tx queues */ 5842 for (i = 0; i < adapter->num_xdp_queues; i++) { 5843 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5844 u8 reg_idx = ring->reg_idx; 5845 5846 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5847 } 5848 5849 /* If the link is not up there shouldn't be much in the way of 5850 * pending transactions. Those that are left will be flushed out 5851 * when the reset logic goes through the flush sequence to clean out 5852 * the pending Tx transactions. 5853 */ 5854 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5855 goto dma_engine_disable; 5856 5857 /* Determine our minimum delay interval. We will increase this value 5858 * with each subsequent test. This way if the device returns quickly 5859 * we should spend as little time as possible waiting, however as 5860 * the time increases we will wait for larger periods of time. 5861 * 5862 * The trick here is that we increase the interval using the 5863 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5864 * of that wait is that it totals up to 100x whatever interval we 5865 * choose. Since our minimum wait is 100us we can just divide the 5866 * total timeout by 100 to get our minimum delay interval. 5867 */ 5868 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5869 5870 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5871 wait_delay = delay_interval; 5872 5873 while (wait_loop--) { 5874 usleep_range(wait_delay, wait_delay + 10); 5875 wait_delay += delay_interval * 2; 5876 txdctl = 0; 5877 5878 /* OR together the reading of all the active TXDCTL registers, 5879 * and then test the result. We need the disable to complete 5880 * before we start freeing the memory and invalidating the 5881 * DMA mappings. 5882 */ 5883 for (i = 0; i < adapter->num_tx_queues; i++) { 5884 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5885 u8 reg_idx = ring->reg_idx; 5886 5887 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5888 } 5889 for (i = 0; i < adapter->num_xdp_queues; i++) { 5890 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5891 u8 reg_idx = ring->reg_idx; 5892 5893 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5894 } 5895 5896 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5897 goto dma_engine_disable; 5898 } 5899 5900 e_err(drv, 5901 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5902 5903 dma_engine_disable: 5904 /* Disable the Tx DMA engine on 82599 and later MAC */ 5905 switch (hw->mac.type) { 5906 case ixgbe_mac_82599EB: 5907 case ixgbe_mac_X540: 5908 case ixgbe_mac_X550: 5909 case ixgbe_mac_X550EM_x: 5910 case ixgbe_mac_x550em_a: 5911 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5912 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5913 ~IXGBE_DMATXCTL_TE)); 5914 fallthrough; 5915 default: 5916 break; 5917 } 5918 } 5919 5920 void ixgbe_reset(struct ixgbe_adapter *adapter) 5921 { 5922 struct ixgbe_hw *hw = &adapter->hw; 5923 struct net_device *netdev = adapter->netdev; 5924 int err; 5925 5926 if (ixgbe_removed(hw->hw_addr)) 5927 return; 5928 /* lock SFP init bit to prevent race conditions with the watchdog */ 5929 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5930 usleep_range(1000, 2000); 5931 5932 /* clear all SFP and link config related flags while holding SFP_INIT */ 5933 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5934 IXGBE_FLAG2_SFP_NEEDS_RESET); 5935 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5936 5937 err = hw->mac.ops.init_hw(hw); 5938 switch (err) { 5939 case 0: 5940 case IXGBE_ERR_SFP_NOT_PRESENT: 5941 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5942 break; 5943 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5944 e_dev_err("master disable timed out\n"); 5945 break; 5946 case IXGBE_ERR_EEPROM_VERSION: 5947 /* We are running on a pre-production device, log a warning */ 5948 e_dev_warn("This device is a pre-production adapter/LOM. " 5949 "Please be aware there may be issues associated with " 5950 "your hardware. If you are experiencing problems " 5951 "please contact your Intel or hardware " 5952 "representative who provided you with this " 5953 "hardware.\n"); 5954 break; 5955 default: 5956 e_dev_err("Hardware Error: %d\n", err); 5957 } 5958 5959 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5960 5961 /* flush entries out of MAC table */ 5962 ixgbe_flush_sw_mac_table(adapter); 5963 __dev_uc_unsync(netdev, NULL); 5964 5965 /* do not flush user set addresses */ 5966 ixgbe_mac_set_default_filter(adapter); 5967 5968 /* update SAN MAC vmdq pool selection */ 5969 if (hw->mac.san_mac_rar_index) 5970 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5971 5972 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5973 ixgbe_ptp_reset(adapter); 5974 5975 if (hw->phy.ops.set_phy_power) { 5976 if (!netif_running(adapter->netdev) && !adapter->wol) 5977 hw->phy.ops.set_phy_power(hw, false); 5978 else 5979 hw->phy.ops.set_phy_power(hw, true); 5980 } 5981 } 5982 5983 /** 5984 * ixgbe_clean_tx_ring - Free Tx Buffers 5985 * @tx_ring: ring to be cleaned 5986 **/ 5987 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5988 { 5989 u16 i = tx_ring->next_to_clean; 5990 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5991 5992 if (tx_ring->xsk_pool) { 5993 ixgbe_xsk_clean_tx_ring(tx_ring); 5994 goto out; 5995 } 5996 5997 while (i != tx_ring->next_to_use) { 5998 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5999 6000 /* Free all the Tx ring sk_buffs */ 6001 if (ring_is_xdp(tx_ring)) 6002 xdp_return_frame(tx_buffer->xdpf); 6003 else 6004 dev_kfree_skb_any(tx_buffer->skb); 6005 6006 /* unmap skb header data */ 6007 dma_unmap_single(tx_ring->dev, 6008 dma_unmap_addr(tx_buffer, dma), 6009 dma_unmap_len(tx_buffer, len), 6010 DMA_TO_DEVICE); 6011 6012 /* check for eop_desc to determine the end of the packet */ 6013 eop_desc = tx_buffer->next_to_watch; 6014 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6015 6016 /* unmap remaining buffers */ 6017 while (tx_desc != eop_desc) { 6018 tx_buffer++; 6019 tx_desc++; 6020 i++; 6021 if (unlikely(i == tx_ring->count)) { 6022 i = 0; 6023 tx_buffer = tx_ring->tx_buffer_info; 6024 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6025 } 6026 6027 /* unmap any remaining paged data */ 6028 if (dma_unmap_len(tx_buffer, len)) 6029 dma_unmap_page(tx_ring->dev, 6030 dma_unmap_addr(tx_buffer, dma), 6031 dma_unmap_len(tx_buffer, len), 6032 DMA_TO_DEVICE); 6033 } 6034 6035 /* move us one more past the eop_desc for start of next pkt */ 6036 tx_buffer++; 6037 i++; 6038 if (unlikely(i == tx_ring->count)) { 6039 i = 0; 6040 tx_buffer = tx_ring->tx_buffer_info; 6041 } 6042 } 6043 6044 /* reset BQL for queue */ 6045 if (!ring_is_xdp(tx_ring)) 6046 netdev_tx_reset_queue(txring_txq(tx_ring)); 6047 6048 out: 6049 /* reset next_to_use and next_to_clean */ 6050 tx_ring->next_to_use = 0; 6051 tx_ring->next_to_clean = 0; 6052 } 6053 6054 /** 6055 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6056 * @adapter: board private structure 6057 **/ 6058 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6059 { 6060 int i; 6061 6062 for (i = 0; i < adapter->num_rx_queues; i++) 6063 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6064 } 6065 6066 /** 6067 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6068 * @adapter: board private structure 6069 **/ 6070 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6071 { 6072 int i; 6073 6074 for (i = 0; i < adapter->num_tx_queues; i++) 6075 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6076 for (i = 0; i < adapter->num_xdp_queues; i++) 6077 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6078 } 6079 6080 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6081 { 6082 struct hlist_node *node2; 6083 struct ixgbe_fdir_filter *filter; 6084 6085 spin_lock(&adapter->fdir_perfect_lock); 6086 6087 hlist_for_each_entry_safe(filter, node2, 6088 &adapter->fdir_filter_list, fdir_node) { 6089 hlist_del(&filter->fdir_node); 6090 kfree(filter); 6091 } 6092 adapter->fdir_filter_count = 0; 6093 6094 spin_unlock(&adapter->fdir_perfect_lock); 6095 } 6096 6097 void ixgbe_down(struct ixgbe_adapter *adapter) 6098 { 6099 struct net_device *netdev = adapter->netdev; 6100 struct ixgbe_hw *hw = &adapter->hw; 6101 int i; 6102 6103 /* signal that we are down to the interrupt handler */ 6104 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6105 return; /* do nothing if already down */ 6106 6107 /* Shut off incoming Tx traffic */ 6108 netif_tx_stop_all_queues(netdev); 6109 6110 /* call carrier off first to avoid false dev_watchdog timeouts */ 6111 netif_carrier_off(netdev); 6112 netif_tx_disable(netdev); 6113 6114 /* Disable Rx */ 6115 ixgbe_disable_rx(adapter); 6116 6117 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6118 if (adapter->xdp_ring[0]) 6119 synchronize_rcu(); 6120 6121 ixgbe_irq_disable(adapter); 6122 6123 ixgbe_napi_disable_all(adapter); 6124 6125 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6126 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6127 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6128 6129 del_timer_sync(&adapter->service_timer); 6130 6131 if (adapter->num_vfs) { 6132 /* Clear EITR Select mapping */ 6133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6134 6135 /* Mark all the VFs as inactive */ 6136 for (i = 0 ; i < adapter->num_vfs; i++) 6137 adapter->vfinfo[i].clear_to_send = false; 6138 6139 /* ping all the active vfs to let them know we are going down */ 6140 ixgbe_ping_all_vfs(adapter); 6141 6142 /* Disable all VFTE/VFRE TX/RX */ 6143 ixgbe_disable_tx_rx(adapter); 6144 } 6145 6146 /* disable transmits in the hardware now that interrupts are off */ 6147 ixgbe_disable_tx(adapter); 6148 6149 if (!pci_channel_offline(adapter->pdev)) 6150 ixgbe_reset(adapter); 6151 6152 /* power down the optics for 82599 SFP+ fiber */ 6153 if (hw->mac.ops.disable_tx_laser) 6154 hw->mac.ops.disable_tx_laser(hw); 6155 6156 ixgbe_clean_all_tx_rings(adapter); 6157 ixgbe_clean_all_rx_rings(adapter); 6158 } 6159 6160 /** 6161 * ixgbe_eee_capable - helper function to determine EEE support on X550 6162 * @adapter: board private structure 6163 */ 6164 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6165 { 6166 struct ixgbe_hw *hw = &adapter->hw; 6167 6168 switch (hw->device_id) { 6169 case IXGBE_DEV_ID_X550EM_A_1G_T: 6170 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6171 if (!hw->phy.eee_speeds_supported) 6172 break; 6173 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6174 if (!hw->phy.eee_speeds_advertised) 6175 break; 6176 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6177 break; 6178 default: 6179 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6180 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6181 break; 6182 } 6183 } 6184 6185 /** 6186 * ixgbe_tx_timeout - Respond to a Tx Hang 6187 * @netdev: network interface device structure 6188 * @txqueue: queue number that timed out 6189 **/ 6190 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6191 { 6192 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6193 6194 /* Do the reset outside of interrupt context */ 6195 ixgbe_tx_timeout_reset(adapter); 6196 } 6197 6198 #ifdef CONFIG_IXGBE_DCB 6199 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6200 { 6201 struct ixgbe_hw *hw = &adapter->hw; 6202 struct tc_configuration *tc; 6203 int j; 6204 6205 switch (hw->mac.type) { 6206 case ixgbe_mac_82598EB: 6207 case ixgbe_mac_82599EB: 6208 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6209 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6210 break; 6211 case ixgbe_mac_X540: 6212 case ixgbe_mac_X550: 6213 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6214 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6215 break; 6216 case ixgbe_mac_X550EM_x: 6217 case ixgbe_mac_x550em_a: 6218 default: 6219 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6220 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6221 break; 6222 } 6223 6224 /* Configure DCB traffic classes */ 6225 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6226 tc = &adapter->dcb_cfg.tc_config[j]; 6227 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6228 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6229 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6230 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6231 tc->dcb_pfc = pfc_disabled; 6232 } 6233 6234 /* Initialize default user to priority mapping, UPx->TC0 */ 6235 tc = &adapter->dcb_cfg.tc_config[0]; 6236 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6237 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6238 6239 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6240 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6241 adapter->dcb_cfg.pfc_mode_enable = false; 6242 adapter->dcb_set_bitmap = 0x00; 6243 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6244 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6245 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6246 sizeof(adapter->temp_dcb_cfg)); 6247 } 6248 #endif 6249 6250 /** 6251 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6252 * @adapter: board private structure to initialize 6253 * @ii: pointer to ixgbe_info for device 6254 * 6255 * ixgbe_sw_init initializes the Adapter private data structure. 6256 * Fields are initialized based on PCI device information and 6257 * OS network device settings (MTU size). 6258 **/ 6259 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6260 const struct ixgbe_info *ii) 6261 { 6262 struct ixgbe_hw *hw = &adapter->hw; 6263 struct pci_dev *pdev = adapter->pdev; 6264 unsigned int rss, fdir; 6265 u32 fwsm; 6266 int i; 6267 6268 /* PCI config space info */ 6269 6270 hw->vendor_id = pdev->vendor; 6271 hw->device_id = pdev->device; 6272 hw->revision_id = pdev->revision; 6273 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6274 hw->subsystem_device_id = pdev->subsystem_device; 6275 6276 /* get_invariants needs the device IDs */ 6277 ii->get_invariants(hw); 6278 6279 /* Set common capability flags and settings */ 6280 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6281 adapter->ring_feature[RING_F_RSS].limit = rss; 6282 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6283 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6284 adapter->atr_sample_rate = 20; 6285 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6286 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6287 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6288 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6289 #ifdef CONFIG_IXGBE_DCA 6290 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6291 #endif 6292 #ifdef CONFIG_IXGBE_DCB 6293 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6294 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6295 #endif 6296 #ifdef IXGBE_FCOE 6297 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6298 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6299 #ifdef CONFIG_IXGBE_DCB 6300 /* Default traffic class to use for FCoE */ 6301 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6302 #endif /* CONFIG_IXGBE_DCB */ 6303 #endif /* IXGBE_FCOE */ 6304 6305 /* initialize static ixgbe jump table entries */ 6306 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6307 GFP_KERNEL); 6308 if (!adapter->jump_tables[0]) 6309 return -ENOMEM; 6310 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6311 6312 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6313 adapter->jump_tables[i] = NULL; 6314 6315 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6316 sizeof(struct ixgbe_mac_addr), 6317 GFP_KERNEL); 6318 if (!adapter->mac_table) 6319 return -ENOMEM; 6320 6321 if (ixgbe_init_rss_key(adapter)) 6322 return -ENOMEM; 6323 6324 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL); 6325 if (!adapter->af_xdp_zc_qps) 6326 return -ENOMEM; 6327 6328 /* Set MAC specific capability flags and exceptions */ 6329 switch (hw->mac.type) { 6330 case ixgbe_mac_82598EB: 6331 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6332 6333 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6334 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6335 6336 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6337 adapter->ring_feature[RING_F_FDIR].limit = 0; 6338 adapter->atr_sample_rate = 0; 6339 adapter->fdir_pballoc = 0; 6340 #ifdef IXGBE_FCOE 6341 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6342 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6343 #ifdef CONFIG_IXGBE_DCB 6344 adapter->fcoe.up = 0; 6345 #endif /* IXGBE_DCB */ 6346 #endif /* IXGBE_FCOE */ 6347 break; 6348 case ixgbe_mac_82599EB: 6349 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6350 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6351 break; 6352 case ixgbe_mac_X540: 6353 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6354 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6355 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6356 break; 6357 case ixgbe_mac_x550em_a: 6358 switch (hw->device_id) { 6359 case IXGBE_DEV_ID_X550EM_A_1G_T: 6360 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6361 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6362 break; 6363 default: 6364 break; 6365 } 6366 fallthrough; 6367 case ixgbe_mac_X550EM_x: 6368 #ifdef CONFIG_IXGBE_DCB 6369 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6370 #endif 6371 #ifdef IXGBE_FCOE 6372 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6373 #ifdef CONFIG_IXGBE_DCB 6374 adapter->fcoe.up = 0; 6375 #endif /* IXGBE_DCB */ 6376 #endif /* IXGBE_FCOE */ 6377 fallthrough; 6378 case ixgbe_mac_X550: 6379 if (hw->mac.type == ixgbe_mac_X550) 6380 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6381 #ifdef CONFIG_IXGBE_DCA 6382 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6383 #endif 6384 break; 6385 default: 6386 break; 6387 } 6388 6389 #ifdef IXGBE_FCOE 6390 /* FCoE support exists, always init the FCoE lock */ 6391 spin_lock_init(&adapter->fcoe.lock); 6392 6393 #endif 6394 /* n-tuple support exists, always init our spinlock */ 6395 spin_lock_init(&adapter->fdir_perfect_lock); 6396 6397 #ifdef CONFIG_IXGBE_DCB 6398 ixgbe_init_dcb(adapter); 6399 #endif 6400 ixgbe_init_ipsec_offload(adapter); 6401 6402 /* default flow control settings */ 6403 hw->fc.requested_mode = ixgbe_fc_full; 6404 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6405 ixgbe_pbthresh_setup(adapter); 6406 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6407 hw->fc.send_xon = true; 6408 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6409 6410 #ifdef CONFIG_PCI_IOV 6411 if (max_vfs > 0) 6412 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6413 6414 /* assign number of SR-IOV VFs */ 6415 if (hw->mac.type != ixgbe_mac_82598EB) { 6416 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6417 max_vfs = 0; 6418 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6419 } 6420 } 6421 #endif /* CONFIG_PCI_IOV */ 6422 6423 /* enable itr by default in dynamic mode */ 6424 adapter->rx_itr_setting = 1; 6425 adapter->tx_itr_setting = 1; 6426 6427 /* set default ring sizes */ 6428 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6429 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6430 6431 /* set default work limits */ 6432 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6433 6434 /* initialize eeprom parameters */ 6435 if (ixgbe_init_eeprom_params_generic(hw)) { 6436 e_dev_err("EEPROM initialization failed\n"); 6437 return -EIO; 6438 } 6439 6440 /* PF holds first pool slot */ 6441 set_bit(0, adapter->fwd_bitmask); 6442 set_bit(__IXGBE_DOWN, &adapter->state); 6443 6444 return 0; 6445 } 6446 6447 /** 6448 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6449 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6450 * 6451 * Return 0 on success, negative on failure 6452 **/ 6453 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6454 { 6455 struct device *dev = tx_ring->dev; 6456 int orig_node = dev_to_node(dev); 6457 int ring_node = NUMA_NO_NODE; 6458 int size; 6459 6460 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6461 6462 if (tx_ring->q_vector) 6463 ring_node = tx_ring->q_vector->numa_node; 6464 6465 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6466 if (!tx_ring->tx_buffer_info) 6467 tx_ring->tx_buffer_info = vmalloc(size); 6468 if (!tx_ring->tx_buffer_info) 6469 goto err; 6470 6471 /* round up to nearest 4K */ 6472 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6473 tx_ring->size = ALIGN(tx_ring->size, 4096); 6474 6475 set_dev_node(dev, ring_node); 6476 tx_ring->desc = dma_alloc_coherent(dev, 6477 tx_ring->size, 6478 &tx_ring->dma, 6479 GFP_KERNEL); 6480 set_dev_node(dev, orig_node); 6481 if (!tx_ring->desc) 6482 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6483 &tx_ring->dma, GFP_KERNEL); 6484 if (!tx_ring->desc) 6485 goto err; 6486 6487 tx_ring->next_to_use = 0; 6488 tx_ring->next_to_clean = 0; 6489 return 0; 6490 6491 err: 6492 vfree(tx_ring->tx_buffer_info); 6493 tx_ring->tx_buffer_info = NULL; 6494 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6495 return -ENOMEM; 6496 } 6497 6498 /** 6499 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6500 * @adapter: board private structure 6501 * 6502 * If this function returns with an error, then it's possible one or 6503 * more of the rings is populated (while the rest are not). It is the 6504 * callers duty to clean those orphaned rings. 6505 * 6506 * Return 0 on success, negative on failure 6507 **/ 6508 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6509 { 6510 int i, j = 0, err = 0; 6511 6512 for (i = 0; i < adapter->num_tx_queues; i++) { 6513 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6514 if (!err) 6515 continue; 6516 6517 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6518 goto err_setup_tx; 6519 } 6520 for (j = 0; j < adapter->num_xdp_queues; j++) { 6521 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6522 if (!err) 6523 continue; 6524 6525 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6526 goto err_setup_tx; 6527 } 6528 6529 return 0; 6530 err_setup_tx: 6531 /* rewind the index freeing the rings as we go */ 6532 while (j--) 6533 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6534 while (i--) 6535 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6536 return err; 6537 } 6538 6539 /** 6540 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6541 * @adapter: pointer to ixgbe_adapter 6542 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6543 * 6544 * Returns 0 on success, negative on failure 6545 **/ 6546 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6547 struct ixgbe_ring *rx_ring) 6548 { 6549 struct device *dev = rx_ring->dev; 6550 int orig_node = dev_to_node(dev); 6551 int ring_node = NUMA_NO_NODE; 6552 int size; 6553 6554 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6555 6556 if (rx_ring->q_vector) 6557 ring_node = rx_ring->q_vector->numa_node; 6558 6559 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6560 if (!rx_ring->rx_buffer_info) 6561 rx_ring->rx_buffer_info = vmalloc(size); 6562 if (!rx_ring->rx_buffer_info) 6563 goto err; 6564 6565 /* Round up to nearest 4K */ 6566 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6567 rx_ring->size = ALIGN(rx_ring->size, 4096); 6568 6569 set_dev_node(dev, ring_node); 6570 rx_ring->desc = dma_alloc_coherent(dev, 6571 rx_ring->size, 6572 &rx_ring->dma, 6573 GFP_KERNEL); 6574 set_dev_node(dev, orig_node); 6575 if (!rx_ring->desc) 6576 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6577 &rx_ring->dma, GFP_KERNEL); 6578 if (!rx_ring->desc) 6579 goto err; 6580 6581 rx_ring->next_to_clean = 0; 6582 rx_ring->next_to_use = 0; 6583 6584 /* XDP RX-queue info */ 6585 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6586 rx_ring->queue_index, rx_ring->q_vector->napi.napi_id) < 0) 6587 goto err; 6588 6589 rx_ring->xdp_prog = adapter->xdp_prog; 6590 6591 return 0; 6592 err: 6593 vfree(rx_ring->rx_buffer_info); 6594 rx_ring->rx_buffer_info = NULL; 6595 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6596 return -ENOMEM; 6597 } 6598 6599 /** 6600 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6601 * @adapter: board private structure 6602 * 6603 * If this function returns with an error, then it's possible one or 6604 * more of the rings is populated (while the rest are not). It is the 6605 * callers duty to clean those orphaned rings. 6606 * 6607 * Return 0 on success, negative on failure 6608 **/ 6609 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6610 { 6611 int i, err = 0; 6612 6613 for (i = 0; i < adapter->num_rx_queues; i++) { 6614 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6615 if (!err) 6616 continue; 6617 6618 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6619 goto err_setup_rx; 6620 } 6621 6622 #ifdef IXGBE_FCOE 6623 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6624 if (!err) 6625 #endif 6626 return 0; 6627 err_setup_rx: 6628 /* rewind the index freeing the rings as we go */ 6629 while (i--) 6630 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6631 return err; 6632 } 6633 6634 /** 6635 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6636 * @tx_ring: Tx descriptor ring for a specific queue 6637 * 6638 * Free all transmit software resources 6639 **/ 6640 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6641 { 6642 ixgbe_clean_tx_ring(tx_ring); 6643 6644 vfree(tx_ring->tx_buffer_info); 6645 tx_ring->tx_buffer_info = NULL; 6646 6647 /* if not set, then don't free */ 6648 if (!tx_ring->desc) 6649 return; 6650 6651 dma_free_coherent(tx_ring->dev, tx_ring->size, 6652 tx_ring->desc, tx_ring->dma); 6653 6654 tx_ring->desc = NULL; 6655 } 6656 6657 /** 6658 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6659 * @adapter: board private structure 6660 * 6661 * Free all transmit software resources 6662 **/ 6663 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6664 { 6665 int i; 6666 6667 for (i = 0; i < adapter->num_tx_queues; i++) 6668 if (adapter->tx_ring[i]->desc) 6669 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6670 for (i = 0; i < adapter->num_xdp_queues; i++) 6671 if (adapter->xdp_ring[i]->desc) 6672 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6673 } 6674 6675 /** 6676 * ixgbe_free_rx_resources - Free Rx Resources 6677 * @rx_ring: ring to clean the resources from 6678 * 6679 * Free all receive software resources 6680 **/ 6681 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6682 { 6683 ixgbe_clean_rx_ring(rx_ring); 6684 6685 rx_ring->xdp_prog = NULL; 6686 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6687 vfree(rx_ring->rx_buffer_info); 6688 rx_ring->rx_buffer_info = NULL; 6689 6690 /* if not set, then don't free */ 6691 if (!rx_ring->desc) 6692 return; 6693 6694 dma_free_coherent(rx_ring->dev, rx_ring->size, 6695 rx_ring->desc, rx_ring->dma); 6696 6697 rx_ring->desc = NULL; 6698 } 6699 6700 /** 6701 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6702 * @adapter: board private structure 6703 * 6704 * Free all receive software resources 6705 **/ 6706 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6707 { 6708 int i; 6709 6710 #ifdef IXGBE_FCOE 6711 ixgbe_free_fcoe_ddp_resources(adapter); 6712 6713 #endif 6714 for (i = 0; i < adapter->num_rx_queues; i++) 6715 if (adapter->rx_ring[i]->desc) 6716 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6717 } 6718 6719 /** 6720 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6721 * @netdev: network interface device structure 6722 * @new_mtu: new value for maximum frame size 6723 * 6724 * Returns 0 on success, negative on failure 6725 **/ 6726 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6727 { 6728 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6729 6730 if (adapter->xdp_prog) { 6731 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 6732 VLAN_HLEN; 6733 int i; 6734 6735 for (i = 0; i < adapter->num_rx_queues; i++) { 6736 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6737 6738 if (new_frame_size > ixgbe_rx_bufsz(ring)) { 6739 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6740 return -EINVAL; 6741 } 6742 } 6743 } 6744 6745 /* 6746 * For 82599EB we cannot allow legacy VFs to enable their receive 6747 * paths when MTU greater than 1500 is configured. So display a 6748 * warning that legacy VFs will be disabled. 6749 */ 6750 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6751 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6752 (new_mtu > ETH_DATA_LEN)) 6753 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6754 6755 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6756 netdev->mtu, new_mtu); 6757 6758 /* must set new MTU before calling down or up */ 6759 netdev->mtu = new_mtu; 6760 6761 if (netif_running(netdev)) 6762 ixgbe_reinit_locked(adapter); 6763 6764 return 0; 6765 } 6766 6767 /** 6768 * ixgbe_open - Called when a network interface is made active 6769 * @netdev: network interface device structure 6770 * 6771 * Returns 0 on success, negative value on failure 6772 * 6773 * The open entry point is called when a network interface is made 6774 * active by the system (IFF_UP). At this point all resources needed 6775 * for transmit and receive operations are allocated, the interrupt 6776 * handler is registered with the OS, the watchdog timer is started, 6777 * and the stack is notified that the interface is ready. 6778 **/ 6779 int ixgbe_open(struct net_device *netdev) 6780 { 6781 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6782 struct ixgbe_hw *hw = &adapter->hw; 6783 int err, queues; 6784 6785 /* disallow open during test */ 6786 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6787 return -EBUSY; 6788 6789 netif_carrier_off(netdev); 6790 6791 /* allocate transmit descriptors */ 6792 err = ixgbe_setup_all_tx_resources(adapter); 6793 if (err) 6794 goto err_setup_tx; 6795 6796 /* allocate receive descriptors */ 6797 err = ixgbe_setup_all_rx_resources(adapter); 6798 if (err) 6799 goto err_setup_rx; 6800 6801 ixgbe_configure(adapter); 6802 6803 err = ixgbe_request_irq(adapter); 6804 if (err) 6805 goto err_req_irq; 6806 6807 /* Notify the stack of the actual queue counts. */ 6808 queues = adapter->num_tx_queues; 6809 err = netif_set_real_num_tx_queues(netdev, queues); 6810 if (err) 6811 goto err_set_queues; 6812 6813 queues = adapter->num_rx_queues; 6814 err = netif_set_real_num_rx_queues(netdev, queues); 6815 if (err) 6816 goto err_set_queues; 6817 6818 ixgbe_ptp_init(adapter); 6819 6820 ixgbe_up_complete(adapter); 6821 6822 udp_tunnel_nic_reset_ntf(netdev); 6823 6824 return 0; 6825 6826 err_set_queues: 6827 ixgbe_free_irq(adapter); 6828 err_req_irq: 6829 ixgbe_free_all_rx_resources(adapter); 6830 if (hw->phy.ops.set_phy_power && !adapter->wol) 6831 hw->phy.ops.set_phy_power(&adapter->hw, false); 6832 err_setup_rx: 6833 ixgbe_free_all_tx_resources(adapter); 6834 err_setup_tx: 6835 ixgbe_reset(adapter); 6836 6837 return err; 6838 } 6839 6840 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6841 { 6842 ixgbe_ptp_suspend(adapter); 6843 6844 if (adapter->hw.phy.ops.enter_lplu) { 6845 adapter->hw.phy.reset_disable = true; 6846 ixgbe_down(adapter); 6847 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6848 adapter->hw.phy.reset_disable = false; 6849 } else { 6850 ixgbe_down(adapter); 6851 } 6852 6853 ixgbe_free_irq(adapter); 6854 6855 ixgbe_free_all_tx_resources(adapter); 6856 ixgbe_free_all_rx_resources(adapter); 6857 } 6858 6859 /** 6860 * ixgbe_close - Disables a network interface 6861 * @netdev: network interface device structure 6862 * 6863 * Returns 0, this is not allowed to fail 6864 * 6865 * The close entry point is called when an interface is de-activated 6866 * by the OS. The hardware is still under the drivers control, but 6867 * needs to be disabled. A global MAC reset is issued to stop the 6868 * hardware, and all transmit and receive resources are freed. 6869 **/ 6870 int ixgbe_close(struct net_device *netdev) 6871 { 6872 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6873 6874 ixgbe_ptp_stop(adapter); 6875 6876 if (netif_device_present(netdev)) 6877 ixgbe_close_suspend(adapter); 6878 6879 ixgbe_fdir_filter_exit(adapter); 6880 6881 ixgbe_release_hw_control(adapter); 6882 6883 return 0; 6884 } 6885 6886 static int __maybe_unused ixgbe_resume(struct device *dev_d) 6887 { 6888 struct pci_dev *pdev = to_pci_dev(dev_d); 6889 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6890 struct net_device *netdev = adapter->netdev; 6891 u32 err; 6892 6893 adapter->hw.hw_addr = adapter->io_addr; 6894 6895 smp_mb__before_atomic(); 6896 clear_bit(__IXGBE_DISABLED, &adapter->state); 6897 pci_set_master(pdev); 6898 6899 device_wakeup_disable(dev_d); 6900 6901 ixgbe_reset(adapter); 6902 6903 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6904 6905 rtnl_lock(); 6906 err = ixgbe_init_interrupt_scheme(adapter); 6907 if (!err && netif_running(netdev)) 6908 err = ixgbe_open(netdev); 6909 6910 6911 if (!err) 6912 netif_device_attach(netdev); 6913 rtnl_unlock(); 6914 6915 return err; 6916 } 6917 6918 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6919 { 6920 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6921 struct net_device *netdev = adapter->netdev; 6922 struct ixgbe_hw *hw = &adapter->hw; 6923 u32 ctrl; 6924 u32 wufc = adapter->wol; 6925 6926 rtnl_lock(); 6927 netif_device_detach(netdev); 6928 6929 if (netif_running(netdev)) 6930 ixgbe_close_suspend(adapter); 6931 6932 ixgbe_clear_interrupt_scheme(adapter); 6933 rtnl_unlock(); 6934 6935 if (hw->mac.ops.stop_link_on_d3) 6936 hw->mac.ops.stop_link_on_d3(hw); 6937 6938 if (wufc) { 6939 u32 fctrl; 6940 6941 ixgbe_set_rx_mode(netdev); 6942 6943 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6944 if (hw->mac.ops.enable_tx_laser) 6945 hw->mac.ops.enable_tx_laser(hw); 6946 6947 /* enable the reception of multicast packets */ 6948 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6949 fctrl |= IXGBE_FCTRL_MPE; 6950 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6951 6952 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6953 ctrl |= IXGBE_CTRL_GIO_DIS; 6954 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6955 6956 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6957 } else { 6958 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6959 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6960 } 6961 6962 switch (hw->mac.type) { 6963 case ixgbe_mac_82598EB: 6964 pci_wake_from_d3(pdev, false); 6965 break; 6966 case ixgbe_mac_82599EB: 6967 case ixgbe_mac_X540: 6968 case ixgbe_mac_X550: 6969 case ixgbe_mac_X550EM_x: 6970 case ixgbe_mac_x550em_a: 6971 pci_wake_from_d3(pdev, !!wufc); 6972 break; 6973 default: 6974 break; 6975 } 6976 6977 *enable_wake = !!wufc; 6978 if (hw->phy.ops.set_phy_power && !*enable_wake) 6979 hw->phy.ops.set_phy_power(hw, false); 6980 6981 ixgbe_release_hw_control(adapter); 6982 6983 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6984 pci_disable_device(pdev); 6985 6986 return 0; 6987 } 6988 6989 static int __maybe_unused ixgbe_suspend(struct device *dev_d) 6990 { 6991 struct pci_dev *pdev = to_pci_dev(dev_d); 6992 int retval; 6993 bool wake; 6994 6995 retval = __ixgbe_shutdown(pdev, &wake); 6996 6997 device_set_wakeup_enable(dev_d, wake); 6998 6999 return retval; 7000 } 7001 7002 static void ixgbe_shutdown(struct pci_dev *pdev) 7003 { 7004 bool wake; 7005 7006 __ixgbe_shutdown(pdev, &wake); 7007 7008 if (system_state == SYSTEM_POWER_OFF) { 7009 pci_wake_from_d3(pdev, wake); 7010 pci_set_power_state(pdev, PCI_D3hot); 7011 } 7012 } 7013 7014 /** 7015 * ixgbe_update_stats - Update the board statistics counters. 7016 * @adapter: board private structure 7017 **/ 7018 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7019 { 7020 struct net_device *netdev = adapter->netdev; 7021 struct ixgbe_hw *hw = &adapter->hw; 7022 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7023 u64 total_mpc = 0; 7024 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7025 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7026 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7027 u64 alloc_rx_page = 0; 7028 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7029 7030 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7031 test_bit(__IXGBE_RESETTING, &adapter->state)) 7032 return; 7033 7034 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7035 u64 rsc_count = 0; 7036 u64 rsc_flush = 0; 7037 for (i = 0; i < adapter->num_rx_queues; i++) { 7038 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7039 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7040 } 7041 adapter->rsc_total_count = rsc_count; 7042 adapter->rsc_total_flush = rsc_flush; 7043 } 7044 7045 for (i = 0; i < adapter->num_rx_queues; i++) { 7046 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7047 7048 if (!rx_ring) 7049 continue; 7050 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7051 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7052 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7053 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7054 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7055 bytes += rx_ring->stats.bytes; 7056 packets += rx_ring->stats.packets; 7057 } 7058 adapter->non_eop_descs = non_eop_descs; 7059 adapter->alloc_rx_page = alloc_rx_page; 7060 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7061 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7062 adapter->hw_csum_rx_error = hw_csum_rx_error; 7063 netdev->stats.rx_bytes = bytes; 7064 netdev->stats.rx_packets = packets; 7065 7066 bytes = 0; 7067 packets = 0; 7068 /* gather some stats to the adapter struct that are per queue */ 7069 for (i = 0; i < adapter->num_tx_queues; i++) { 7070 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7071 7072 if (!tx_ring) 7073 continue; 7074 restart_queue += tx_ring->tx_stats.restart_queue; 7075 tx_busy += tx_ring->tx_stats.tx_busy; 7076 bytes += tx_ring->stats.bytes; 7077 packets += tx_ring->stats.packets; 7078 } 7079 for (i = 0; i < adapter->num_xdp_queues; i++) { 7080 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7081 7082 if (!xdp_ring) 7083 continue; 7084 restart_queue += xdp_ring->tx_stats.restart_queue; 7085 tx_busy += xdp_ring->tx_stats.tx_busy; 7086 bytes += xdp_ring->stats.bytes; 7087 packets += xdp_ring->stats.packets; 7088 } 7089 adapter->restart_queue = restart_queue; 7090 adapter->tx_busy = tx_busy; 7091 netdev->stats.tx_bytes = bytes; 7092 netdev->stats.tx_packets = packets; 7093 7094 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7095 7096 /* 8 register reads */ 7097 for (i = 0; i < 8; i++) { 7098 /* for packet buffers not used, the register should read 0 */ 7099 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7100 missed_rx += mpc; 7101 hwstats->mpc[i] += mpc; 7102 total_mpc += hwstats->mpc[i]; 7103 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7104 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7105 switch (hw->mac.type) { 7106 case ixgbe_mac_82598EB: 7107 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7108 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7109 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7110 hwstats->pxonrxc[i] += 7111 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7112 break; 7113 case ixgbe_mac_82599EB: 7114 case ixgbe_mac_X540: 7115 case ixgbe_mac_X550: 7116 case ixgbe_mac_X550EM_x: 7117 case ixgbe_mac_x550em_a: 7118 hwstats->pxonrxc[i] += 7119 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7120 break; 7121 default: 7122 break; 7123 } 7124 } 7125 7126 /*16 register reads */ 7127 for (i = 0; i < 16; i++) { 7128 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7129 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7130 if ((hw->mac.type == ixgbe_mac_82599EB) || 7131 (hw->mac.type == ixgbe_mac_X540) || 7132 (hw->mac.type == ixgbe_mac_X550) || 7133 (hw->mac.type == ixgbe_mac_X550EM_x) || 7134 (hw->mac.type == ixgbe_mac_x550em_a)) { 7135 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7136 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7137 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7138 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7139 } 7140 } 7141 7142 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7143 /* work around hardware counting issue */ 7144 hwstats->gprc -= missed_rx; 7145 7146 ixgbe_update_xoff_received(adapter); 7147 7148 /* 82598 hardware only has a 32 bit counter in the high register */ 7149 switch (hw->mac.type) { 7150 case ixgbe_mac_82598EB: 7151 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7152 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7153 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7154 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7155 break; 7156 case ixgbe_mac_X540: 7157 case ixgbe_mac_X550: 7158 case ixgbe_mac_X550EM_x: 7159 case ixgbe_mac_x550em_a: 7160 /* OS2BMC stats are X540 and later */ 7161 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7162 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7163 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7164 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7165 fallthrough; 7166 case ixgbe_mac_82599EB: 7167 for (i = 0; i < 16; i++) 7168 adapter->hw_rx_no_dma_resources += 7169 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7170 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7171 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7172 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7173 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7174 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7175 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7176 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7177 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7178 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7179 #ifdef IXGBE_FCOE 7180 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7181 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7182 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7183 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7184 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7185 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7186 /* Add up per cpu counters for total ddp aloc fail */ 7187 if (adapter->fcoe.ddp_pool) { 7188 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7189 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7190 unsigned int cpu; 7191 u64 noddp = 0, noddp_ext_buff = 0; 7192 for_each_possible_cpu(cpu) { 7193 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7194 noddp += ddp_pool->noddp; 7195 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7196 } 7197 hwstats->fcoe_noddp = noddp; 7198 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7199 } 7200 #endif /* IXGBE_FCOE */ 7201 break; 7202 default: 7203 break; 7204 } 7205 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7206 hwstats->bprc += bprc; 7207 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7208 if (hw->mac.type == ixgbe_mac_82598EB) 7209 hwstats->mprc -= bprc; 7210 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7211 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7212 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7213 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7214 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7215 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7216 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7217 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7218 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7219 hwstats->lxontxc += lxon; 7220 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7221 hwstats->lxofftxc += lxoff; 7222 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7223 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7224 /* 7225 * 82598 errata - tx of flow control packets is included in tx counters 7226 */ 7227 xon_off_tot = lxon + lxoff; 7228 hwstats->gptc -= xon_off_tot; 7229 hwstats->mptc -= xon_off_tot; 7230 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7231 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7232 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7233 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7234 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7235 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7236 hwstats->ptc64 -= xon_off_tot; 7237 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7238 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7239 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7240 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7241 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7242 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7243 7244 /* Fill out the OS statistics structure */ 7245 netdev->stats.multicast = hwstats->mprc; 7246 7247 /* Rx Errors */ 7248 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7249 netdev->stats.rx_dropped = 0; 7250 netdev->stats.rx_length_errors = hwstats->rlec; 7251 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7252 netdev->stats.rx_missed_errors = total_mpc; 7253 } 7254 7255 /** 7256 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7257 * @adapter: pointer to the device adapter structure 7258 **/ 7259 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7260 { 7261 struct ixgbe_hw *hw = &adapter->hw; 7262 int i; 7263 7264 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7265 return; 7266 7267 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7268 7269 /* if interface is down do nothing */ 7270 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7271 return; 7272 7273 /* do nothing if we are not using signature filters */ 7274 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7275 return; 7276 7277 adapter->fdir_overflow++; 7278 7279 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7280 for (i = 0; i < adapter->num_tx_queues; i++) 7281 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7282 &(adapter->tx_ring[i]->state)); 7283 for (i = 0; i < adapter->num_xdp_queues; i++) 7284 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7285 &adapter->xdp_ring[i]->state); 7286 /* re-enable flow director interrupts */ 7287 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7288 } else { 7289 e_err(probe, "failed to finish FDIR re-initialization, " 7290 "ignored adding FDIR ATR filters\n"); 7291 } 7292 } 7293 7294 /** 7295 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7296 * @adapter: pointer to the device adapter structure 7297 * 7298 * This function serves two purposes. First it strobes the interrupt lines 7299 * in order to make certain interrupts are occurring. Secondly it sets the 7300 * bits needed to check for TX hangs. As a result we should immediately 7301 * determine if a hang has occurred. 7302 */ 7303 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7304 { 7305 struct ixgbe_hw *hw = &adapter->hw; 7306 u64 eics = 0; 7307 int i; 7308 7309 /* If we're down, removing or resetting, just bail */ 7310 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7311 test_bit(__IXGBE_REMOVING, &adapter->state) || 7312 test_bit(__IXGBE_RESETTING, &adapter->state)) 7313 return; 7314 7315 /* Force detection of hung controller */ 7316 if (netif_carrier_ok(adapter->netdev)) { 7317 for (i = 0; i < adapter->num_tx_queues; i++) 7318 set_check_for_tx_hang(adapter->tx_ring[i]); 7319 for (i = 0; i < adapter->num_xdp_queues; i++) 7320 set_check_for_tx_hang(adapter->xdp_ring[i]); 7321 } 7322 7323 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7324 /* 7325 * for legacy and MSI interrupts don't set any bits 7326 * that are enabled for EIAM, because this operation 7327 * would set *both* EIMS and EICS for any bit in EIAM 7328 */ 7329 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7330 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7331 } else { 7332 /* get one bit for every active tx/rx interrupt vector */ 7333 for (i = 0; i < adapter->num_q_vectors; i++) { 7334 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7335 if (qv->rx.ring || qv->tx.ring) 7336 eics |= BIT_ULL(i); 7337 } 7338 } 7339 7340 /* Cause software interrupt to ensure rings are cleaned */ 7341 ixgbe_irq_rearm_queues(adapter, eics); 7342 } 7343 7344 /** 7345 * ixgbe_watchdog_update_link - update the link status 7346 * @adapter: pointer to the device adapter structure 7347 **/ 7348 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7349 { 7350 struct ixgbe_hw *hw = &adapter->hw; 7351 u32 link_speed = adapter->link_speed; 7352 bool link_up = adapter->link_up; 7353 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7354 7355 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7356 return; 7357 7358 if (hw->mac.ops.check_link) { 7359 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7360 } else { 7361 /* always assume link is up, if no check link function */ 7362 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7363 link_up = true; 7364 } 7365 7366 if (adapter->ixgbe_ieee_pfc) 7367 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7368 7369 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7370 hw->mac.ops.fc_enable(hw); 7371 ixgbe_set_rx_drop_en(adapter); 7372 } 7373 7374 if (link_up || 7375 time_after(jiffies, (adapter->link_check_timeout + 7376 IXGBE_TRY_LINK_TIMEOUT))) { 7377 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7378 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7379 IXGBE_WRITE_FLUSH(hw); 7380 } 7381 7382 adapter->link_up = link_up; 7383 adapter->link_speed = link_speed; 7384 } 7385 7386 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7387 { 7388 #ifdef CONFIG_IXGBE_DCB 7389 struct net_device *netdev = adapter->netdev; 7390 struct dcb_app app = { 7391 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7392 .protocol = 0, 7393 }; 7394 u8 up = 0; 7395 7396 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7397 up = dcb_ieee_getapp_mask(netdev, &app); 7398 7399 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7400 #endif 7401 } 7402 7403 /** 7404 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7405 * print link up message 7406 * @adapter: pointer to the device adapter structure 7407 **/ 7408 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7409 { 7410 struct net_device *netdev = adapter->netdev; 7411 struct ixgbe_hw *hw = &adapter->hw; 7412 u32 link_speed = adapter->link_speed; 7413 const char *speed_str; 7414 bool flow_rx, flow_tx; 7415 7416 /* only continue if link was previously down */ 7417 if (netif_carrier_ok(netdev)) 7418 return; 7419 7420 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7421 7422 switch (hw->mac.type) { 7423 case ixgbe_mac_82598EB: { 7424 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7425 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7426 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7427 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7428 } 7429 break; 7430 case ixgbe_mac_X540: 7431 case ixgbe_mac_X550: 7432 case ixgbe_mac_X550EM_x: 7433 case ixgbe_mac_x550em_a: 7434 case ixgbe_mac_82599EB: { 7435 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7436 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7437 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7438 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7439 } 7440 break; 7441 default: 7442 flow_tx = false; 7443 flow_rx = false; 7444 break; 7445 } 7446 7447 adapter->last_rx_ptp_check = jiffies; 7448 7449 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7450 ixgbe_ptp_start_cyclecounter(adapter); 7451 7452 switch (link_speed) { 7453 case IXGBE_LINK_SPEED_10GB_FULL: 7454 speed_str = "10 Gbps"; 7455 break; 7456 case IXGBE_LINK_SPEED_5GB_FULL: 7457 speed_str = "5 Gbps"; 7458 break; 7459 case IXGBE_LINK_SPEED_2_5GB_FULL: 7460 speed_str = "2.5 Gbps"; 7461 break; 7462 case IXGBE_LINK_SPEED_1GB_FULL: 7463 speed_str = "1 Gbps"; 7464 break; 7465 case IXGBE_LINK_SPEED_100_FULL: 7466 speed_str = "100 Mbps"; 7467 break; 7468 case IXGBE_LINK_SPEED_10_FULL: 7469 speed_str = "10 Mbps"; 7470 break; 7471 default: 7472 speed_str = "unknown speed"; 7473 break; 7474 } 7475 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7476 ((flow_rx && flow_tx) ? "RX/TX" : 7477 (flow_rx ? "RX" : 7478 (flow_tx ? "TX" : "None")))); 7479 7480 netif_carrier_on(netdev); 7481 ixgbe_check_vf_rate_limit(adapter); 7482 7483 /* enable transmits */ 7484 netif_tx_wake_all_queues(adapter->netdev); 7485 7486 /* update the default user priority for VFs */ 7487 ixgbe_update_default_up(adapter); 7488 7489 /* ping all the active vfs to let them know link has changed */ 7490 ixgbe_ping_all_vfs(adapter); 7491 } 7492 7493 /** 7494 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7495 * print link down message 7496 * @adapter: pointer to the adapter structure 7497 **/ 7498 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7499 { 7500 struct net_device *netdev = adapter->netdev; 7501 struct ixgbe_hw *hw = &adapter->hw; 7502 7503 adapter->link_up = false; 7504 adapter->link_speed = 0; 7505 7506 /* only continue if link was up previously */ 7507 if (!netif_carrier_ok(netdev)) 7508 return; 7509 7510 /* poll for SFP+ cable when link is down */ 7511 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7512 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7513 7514 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7515 ixgbe_ptp_start_cyclecounter(adapter); 7516 7517 e_info(drv, "NIC Link is Down\n"); 7518 netif_carrier_off(netdev); 7519 7520 /* ping all the active vfs to let them know link has changed */ 7521 ixgbe_ping_all_vfs(adapter); 7522 } 7523 7524 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7525 { 7526 int i; 7527 7528 for (i = 0; i < adapter->num_tx_queues; i++) { 7529 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7530 7531 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7532 return true; 7533 } 7534 7535 for (i = 0; i < adapter->num_xdp_queues; i++) { 7536 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7537 7538 if (ring->next_to_use != ring->next_to_clean) 7539 return true; 7540 } 7541 7542 return false; 7543 } 7544 7545 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7546 { 7547 struct ixgbe_hw *hw = &adapter->hw; 7548 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7549 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7550 7551 int i, j; 7552 7553 if (!adapter->num_vfs) 7554 return false; 7555 7556 /* resetting the PF is only needed for MAC before X550 */ 7557 if (hw->mac.type >= ixgbe_mac_X550) 7558 return false; 7559 7560 for (i = 0; i < adapter->num_vfs; i++) { 7561 for (j = 0; j < q_per_pool; j++) { 7562 u32 h, t; 7563 7564 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7565 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7566 7567 if (h != t) 7568 return true; 7569 } 7570 } 7571 7572 return false; 7573 } 7574 7575 /** 7576 * ixgbe_watchdog_flush_tx - flush queues on link down 7577 * @adapter: pointer to the device adapter structure 7578 **/ 7579 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7580 { 7581 if (!netif_carrier_ok(adapter->netdev)) { 7582 if (ixgbe_ring_tx_pending(adapter) || 7583 ixgbe_vf_tx_pending(adapter)) { 7584 /* We've lost link, so the controller stops DMA, 7585 * but we've got queued Tx work that's never going 7586 * to get done, so reset controller to flush Tx. 7587 * (Do the reset outside of interrupt context). 7588 */ 7589 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7590 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7591 } 7592 } 7593 } 7594 7595 #ifdef CONFIG_PCI_IOV 7596 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7597 { 7598 struct ixgbe_hw *hw = &adapter->hw; 7599 struct pci_dev *pdev = adapter->pdev; 7600 unsigned int vf; 7601 u32 gpc; 7602 7603 if (!(netif_carrier_ok(adapter->netdev))) 7604 return; 7605 7606 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7607 if (gpc) /* If incrementing then no need for the check below */ 7608 return; 7609 /* Check to see if a bad DMA write target from an errant or 7610 * malicious VF has caused a PCIe error. If so then we can 7611 * issue a VFLR to the offending VF(s) and then resume without 7612 * requesting a full slot reset. 7613 */ 7614 7615 if (!pdev) 7616 return; 7617 7618 /* check status reg for all VFs owned by this PF */ 7619 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7620 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7621 u16 status_reg; 7622 7623 if (!vfdev) 7624 continue; 7625 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7626 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7627 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7628 pcie_flr(vfdev); 7629 } 7630 } 7631 7632 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7633 { 7634 u32 ssvpc; 7635 7636 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7637 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7638 adapter->num_vfs == 0) 7639 return; 7640 7641 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7642 7643 /* 7644 * ssvpc register is cleared on read, if zero then no 7645 * spoofed packets in the last interval. 7646 */ 7647 if (!ssvpc) 7648 return; 7649 7650 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7651 } 7652 #else 7653 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7654 { 7655 } 7656 7657 static void 7658 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7659 { 7660 } 7661 #endif /* CONFIG_PCI_IOV */ 7662 7663 7664 /** 7665 * ixgbe_watchdog_subtask - check and bring link up 7666 * @adapter: pointer to the device adapter structure 7667 **/ 7668 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7669 { 7670 /* if interface is down, removing or resetting, do nothing */ 7671 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7672 test_bit(__IXGBE_REMOVING, &adapter->state) || 7673 test_bit(__IXGBE_RESETTING, &adapter->state)) 7674 return; 7675 7676 ixgbe_watchdog_update_link(adapter); 7677 7678 if (adapter->link_up) 7679 ixgbe_watchdog_link_is_up(adapter); 7680 else 7681 ixgbe_watchdog_link_is_down(adapter); 7682 7683 ixgbe_check_for_bad_vf(adapter); 7684 ixgbe_spoof_check(adapter); 7685 ixgbe_update_stats(adapter); 7686 7687 ixgbe_watchdog_flush_tx(adapter); 7688 } 7689 7690 /** 7691 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7692 * @adapter: the ixgbe adapter structure 7693 **/ 7694 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7695 { 7696 struct ixgbe_hw *hw = &adapter->hw; 7697 s32 err; 7698 7699 /* not searching for SFP so there is nothing to do here */ 7700 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7701 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7702 return; 7703 7704 if (adapter->sfp_poll_time && 7705 time_after(adapter->sfp_poll_time, jiffies)) 7706 return; /* If not yet time to poll for SFP */ 7707 7708 /* someone else is in init, wait until next service event */ 7709 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7710 return; 7711 7712 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7713 7714 err = hw->phy.ops.identify_sfp(hw); 7715 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7716 goto sfp_out; 7717 7718 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7719 /* If no cable is present, then we need to reset 7720 * the next time we find a good cable. */ 7721 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7722 } 7723 7724 /* exit on error */ 7725 if (err) 7726 goto sfp_out; 7727 7728 /* exit if reset not needed */ 7729 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7730 goto sfp_out; 7731 7732 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7733 7734 /* 7735 * A module may be identified correctly, but the EEPROM may not have 7736 * support for that module. setup_sfp() will fail in that case, so 7737 * we should not allow that module to load. 7738 */ 7739 if (hw->mac.type == ixgbe_mac_82598EB) 7740 err = hw->phy.ops.reset(hw); 7741 else 7742 err = hw->mac.ops.setup_sfp(hw); 7743 7744 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7745 goto sfp_out; 7746 7747 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7748 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7749 7750 sfp_out: 7751 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7752 7753 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7754 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7755 e_dev_err("failed to initialize because an unsupported " 7756 "SFP+ module type was detected.\n"); 7757 e_dev_err("Reload the driver after installing a " 7758 "supported module.\n"); 7759 unregister_netdev(adapter->netdev); 7760 } 7761 } 7762 7763 /** 7764 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7765 * @adapter: the ixgbe adapter structure 7766 **/ 7767 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7768 { 7769 struct ixgbe_hw *hw = &adapter->hw; 7770 u32 cap_speed; 7771 u32 speed; 7772 bool autoneg = false; 7773 7774 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7775 return; 7776 7777 /* someone else is in init, wait until next service event */ 7778 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7779 return; 7780 7781 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7782 7783 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7784 7785 /* advertise highest capable link speed */ 7786 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7787 speed = IXGBE_LINK_SPEED_10GB_FULL; 7788 else 7789 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7790 IXGBE_LINK_SPEED_1GB_FULL); 7791 7792 if (hw->mac.ops.setup_link) 7793 hw->mac.ops.setup_link(hw, speed, true); 7794 7795 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7796 adapter->link_check_timeout = jiffies; 7797 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7798 } 7799 7800 /** 7801 * ixgbe_service_timer - Timer Call-back 7802 * @t: pointer to timer_list structure 7803 **/ 7804 static void ixgbe_service_timer(struct timer_list *t) 7805 { 7806 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7807 unsigned long next_event_offset; 7808 7809 /* poll faster when waiting for link */ 7810 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7811 next_event_offset = HZ / 10; 7812 else 7813 next_event_offset = HZ * 2; 7814 7815 /* Reset the timer */ 7816 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7817 7818 ixgbe_service_event_schedule(adapter); 7819 } 7820 7821 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7822 { 7823 struct ixgbe_hw *hw = &adapter->hw; 7824 u32 status; 7825 7826 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7827 return; 7828 7829 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7830 7831 if (!hw->phy.ops.handle_lasi) 7832 return; 7833 7834 status = hw->phy.ops.handle_lasi(&adapter->hw); 7835 if (status != IXGBE_ERR_OVERTEMP) 7836 return; 7837 7838 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7839 } 7840 7841 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7842 { 7843 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7844 return; 7845 7846 rtnl_lock(); 7847 /* If we're already down, removing or resetting, just bail */ 7848 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7849 test_bit(__IXGBE_REMOVING, &adapter->state) || 7850 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7851 rtnl_unlock(); 7852 return; 7853 } 7854 7855 ixgbe_dump(adapter); 7856 netdev_err(adapter->netdev, "Reset adapter\n"); 7857 adapter->tx_timeout_count++; 7858 7859 ixgbe_reinit_locked(adapter); 7860 rtnl_unlock(); 7861 } 7862 7863 /** 7864 * ixgbe_check_fw_error - Check firmware for errors 7865 * @adapter: the adapter private structure 7866 * 7867 * Check firmware errors in register FWSM 7868 */ 7869 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7870 { 7871 struct ixgbe_hw *hw = &adapter->hw; 7872 u32 fwsm; 7873 7874 /* read fwsm.ext_err_ind register and log errors */ 7875 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7876 7877 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7878 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7879 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7880 fwsm); 7881 7882 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7883 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7884 return true; 7885 } 7886 7887 return false; 7888 } 7889 7890 /** 7891 * ixgbe_service_task - manages and runs subtasks 7892 * @work: pointer to work_struct containing our data 7893 **/ 7894 static void ixgbe_service_task(struct work_struct *work) 7895 { 7896 struct ixgbe_adapter *adapter = container_of(work, 7897 struct ixgbe_adapter, 7898 service_task); 7899 if (ixgbe_removed(adapter->hw.hw_addr)) { 7900 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7901 rtnl_lock(); 7902 ixgbe_down(adapter); 7903 rtnl_unlock(); 7904 } 7905 ixgbe_service_event_complete(adapter); 7906 return; 7907 } 7908 if (ixgbe_check_fw_error(adapter)) { 7909 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 7910 unregister_netdev(adapter->netdev); 7911 ixgbe_service_event_complete(adapter); 7912 return; 7913 } 7914 ixgbe_reset_subtask(adapter); 7915 ixgbe_phy_interrupt_subtask(adapter); 7916 ixgbe_sfp_detection_subtask(adapter); 7917 ixgbe_sfp_link_config_subtask(adapter); 7918 ixgbe_check_overtemp_subtask(adapter); 7919 ixgbe_watchdog_subtask(adapter); 7920 ixgbe_fdir_reinit_subtask(adapter); 7921 ixgbe_check_hang_subtask(adapter); 7922 7923 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7924 ixgbe_ptp_overflow_check(adapter); 7925 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7926 ixgbe_ptp_rx_hang(adapter); 7927 ixgbe_ptp_tx_hang(adapter); 7928 } 7929 7930 ixgbe_service_event_complete(adapter); 7931 } 7932 7933 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7934 struct ixgbe_tx_buffer *first, 7935 u8 *hdr_len, 7936 struct ixgbe_ipsec_tx_data *itd) 7937 { 7938 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7939 struct sk_buff *skb = first->skb; 7940 union { 7941 struct iphdr *v4; 7942 struct ipv6hdr *v6; 7943 unsigned char *hdr; 7944 } ip; 7945 union { 7946 struct tcphdr *tcp; 7947 struct udphdr *udp; 7948 unsigned char *hdr; 7949 } l4; 7950 u32 paylen, l4_offset; 7951 u32 fceof_saidx = 0; 7952 int err; 7953 7954 if (skb->ip_summed != CHECKSUM_PARTIAL) 7955 return 0; 7956 7957 if (!skb_is_gso(skb)) 7958 return 0; 7959 7960 err = skb_cow_head(skb, 0); 7961 if (err < 0) 7962 return err; 7963 7964 if (eth_p_mpls(first->protocol)) 7965 ip.hdr = skb_inner_network_header(skb); 7966 else 7967 ip.hdr = skb_network_header(skb); 7968 l4.hdr = skb_checksum_start(skb); 7969 7970 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7971 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 7972 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 7973 7974 /* initialize outer IP header fields */ 7975 if (ip.v4->version == 4) { 7976 unsigned char *csum_start = skb_checksum_start(skb); 7977 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7978 int len = csum_start - trans_start; 7979 7980 /* IP header will have to cancel out any data that 7981 * is not a part of the outer IP header, so set to 7982 * a reverse csum if needed, else init check to 0. 7983 */ 7984 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7985 csum_fold(csum_partial(trans_start, 7986 len, 0)) : 0; 7987 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7988 7989 ip.v4->tot_len = 0; 7990 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7991 IXGBE_TX_FLAGS_CSUM | 7992 IXGBE_TX_FLAGS_IPV4; 7993 } else { 7994 ip.v6->payload_len = 0; 7995 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7996 IXGBE_TX_FLAGS_CSUM; 7997 } 7998 7999 /* determine offset of inner transport header */ 8000 l4_offset = l4.hdr - skb->data; 8001 8002 /* remove payload length from inner checksum */ 8003 paylen = skb->len - l4_offset; 8004 8005 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8006 /* compute length of segmentation header */ 8007 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8008 csum_replace_by_diff(&l4.tcp->check, 8009 (__force __wsum)htonl(paylen)); 8010 } else { 8011 /* compute length of segmentation header */ 8012 *hdr_len = sizeof(*l4.udp) + l4_offset; 8013 csum_replace_by_diff(&l4.udp->check, 8014 (__force __wsum)htonl(paylen)); 8015 } 8016 8017 /* update gso size and bytecount with header size */ 8018 first->gso_segs = skb_shinfo(skb)->gso_segs; 8019 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8020 8021 /* mss_l4len_id: use 0 as index for TSO */ 8022 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8023 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8024 8025 fceof_saidx |= itd->sa_idx; 8026 type_tucmd |= itd->flags | itd->trailer_len; 8027 8028 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8029 vlan_macip_lens = l4.hdr - ip.hdr; 8030 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8031 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8032 8033 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8034 mss_l4len_idx); 8035 8036 return 1; 8037 } 8038 8039 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8040 struct ixgbe_tx_buffer *first, 8041 struct ixgbe_ipsec_tx_data *itd) 8042 { 8043 struct sk_buff *skb = first->skb; 8044 u32 vlan_macip_lens = 0; 8045 u32 fceof_saidx = 0; 8046 u32 type_tucmd = 0; 8047 8048 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8049 csum_failed: 8050 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8051 IXGBE_TX_FLAGS_CC))) 8052 return; 8053 goto no_csum; 8054 } 8055 8056 switch (skb->csum_offset) { 8057 case offsetof(struct tcphdr, check): 8058 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8059 fallthrough; 8060 case offsetof(struct udphdr, check): 8061 break; 8062 case offsetof(struct sctphdr, checksum): 8063 /* validate that this is actually an SCTP request */ 8064 if (skb_csum_is_sctp(skb)) { 8065 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8066 break; 8067 } 8068 fallthrough; 8069 default: 8070 skb_checksum_help(skb); 8071 goto csum_failed; 8072 } 8073 8074 /* update TX checksum flag */ 8075 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8076 vlan_macip_lens = skb_checksum_start_offset(skb) - 8077 skb_network_offset(skb); 8078 no_csum: 8079 /* vlan_macip_lens: MACLEN, VLAN tag */ 8080 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8081 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8082 8083 fceof_saidx |= itd->sa_idx; 8084 type_tucmd |= itd->flags | itd->trailer_len; 8085 8086 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8087 } 8088 8089 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8090 ((_flag <= _result) ? \ 8091 ((u32)(_input & _flag) * (_result / _flag)) : \ 8092 ((u32)(_input & _flag) / (_flag / _result))) 8093 8094 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8095 { 8096 /* set type for advanced descriptor with frame checksum insertion */ 8097 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8098 IXGBE_ADVTXD_DCMD_DEXT | 8099 IXGBE_ADVTXD_DCMD_IFCS; 8100 8101 /* set HW vlan bit if vlan is present */ 8102 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8103 IXGBE_ADVTXD_DCMD_VLE); 8104 8105 /* set segmentation enable bits for TSO/FSO */ 8106 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8107 IXGBE_ADVTXD_DCMD_TSE); 8108 8109 /* set timestamp bit if present */ 8110 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8111 IXGBE_ADVTXD_MAC_TSTAMP); 8112 8113 /* insert frame checksum */ 8114 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8115 8116 return cmd_type; 8117 } 8118 8119 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8120 u32 tx_flags, unsigned int paylen) 8121 { 8122 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8123 8124 /* enable L4 checksum for TSO and TX checksum offload */ 8125 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8126 IXGBE_TX_FLAGS_CSUM, 8127 IXGBE_ADVTXD_POPTS_TXSM); 8128 8129 /* enable IPv4 checksum for TSO */ 8130 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8131 IXGBE_TX_FLAGS_IPV4, 8132 IXGBE_ADVTXD_POPTS_IXSM); 8133 8134 /* enable IPsec */ 8135 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8136 IXGBE_TX_FLAGS_IPSEC, 8137 IXGBE_ADVTXD_POPTS_IPSEC); 8138 8139 /* 8140 * Check Context must be set if Tx switch is enabled, which it 8141 * always is for case where virtual functions are running 8142 */ 8143 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8144 IXGBE_TX_FLAGS_CC, 8145 IXGBE_ADVTXD_CC); 8146 8147 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8148 } 8149 8150 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8151 { 8152 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8153 8154 /* Herbert's original patch had: 8155 * smp_mb__after_netif_stop_queue(); 8156 * but since that doesn't exist yet, just open code it. 8157 */ 8158 smp_mb(); 8159 8160 /* We need to check again in a case another CPU has just 8161 * made room available. 8162 */ 8163 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8164 return -EBUSY; 8165 8166 /* A reprieve! - use start_queue because it doesn't call schedule */ 8167 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8168 ++tx_ring->tx_stats.restart_queue; 8169 return 0; 8170 } 8171 8172 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8173 { 8174 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8175 return 0; 8176 8177 return __ixgbe_maybe_stop_tx(tx_ring, size); 8178 } 8179 8180 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8181 struct ixgbe_tx_buffer *first, 8182 const u8 hdr_len) 8183 { 8184 struct sk_buff *skb = first->skb; 8185 struct ixgbe_tx_buffer *tx_buffer; 8186 union ixgbe_adv_tx_desc *tx_desc; 8187 skb_frag_t *frag; 8188 dma_addr_t dma; 8189 unsigned int data_len, size; 8190 u32 tx_flags = first->tx_flags; 8191 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8192 u16 i = tx_ring->next_to_use; 8193 8194 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8195 8196 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8197 8198 size = skb_headlen(skb); 8199 data_len = skb->data_len; 8200 8201 #ifdef IXGBE_FCOE 8202 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8203 if (data_len < sizeof(struct fcoe_crc_eof)) { 8204 size -= sizeof(struct fcoe_crc_eof) - data_len; 8205 data_len = 0; 8206 } else { 8207 data_len -= sizeof(struct fcoe_crc_eof); 8208 } 8209 } 8210 8211 #endif 8212 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8213 8214 tx_buffer = first; 8215 8216 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8217 if (dma_mapping_error(tx_ring->dev, dma)) 8218 goto dma_error; 8219 8220 /* record length, and DMA address */ 8221 dma_unmap_len_set(tx_buffer, len, size); 8222 dma_unmap_addr_set(tx_buffer, dma, dma); 8223 8224 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8225 8226 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8227 tx_desc->read.cmd_type_len = 8228 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8229 8230 i++; 8231 tx_desc++; 8232 if (i == tx_ring->count) { 8233 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8234 i = 0; 8235 } 8236 tx_desc->read.olinfo_status = 0; 8237 8238 dma += IXGBE_MAX_DATA_PER_TXD; 8239 size -= IXGBE_MAX_DATA_PER_TXD; 8240 8241 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8242 } 8243 8244 if (likely(!data_len)) 8245 break; 8246 8247 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8248 8249 i++; 8250 tx_desc++; 8251 if (i == tx_ring->count) { 8252 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8253 i = 0; 8254 } 8255 tx_desc->read.olinfo_status = 0; 8256 8257 #ifdef IXGBE_FCOE 8258 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8259 #else 8260 size = skb_frag_size(frag); 8261 #endif 8262 data_len -= size; 8263 8264 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8265 DMA_TO_DEVICE); 8266 8267 tx_buffer = &tx_ring->tx_buffer_info[i]; 8268 } 8269 8270 /* write last descriptor with RS and EOP bits */ 8271 cmd_type |= size | IXGBE_TXD_CMD; 8272 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8273 8274 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8275 8276 /* set the timestamp */ 8277 first->time_stamp = jiffies; 8278 8279 skb_tx_timestamp(skb); 8280 8281 /* 8282 * Force memory writes to complete before letting h/w know there 8283 * are new descriptors to fetch. (Only applicable for weak-ordered 8284 * memory model archs, such as IA-64). 8285 * 8286 * We also need this memory barrier to make certain all of the 8287 * status bits have been updated before next_to_watch is written. 8288 */ 8289 wmb(); 8290 8291 /* set next_to_watch value indicating a packet is present */ 8292 first->next_to_watch = tx_desc; 8293 8294 i++; 8295 if (i == tx_ring->count) 8296 i = 0; 8297 8298 tx_ring->next_to_use = i; 8299 8300 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8301 8302 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8303 writel(i, tx_ring->tail); 8304 } 8305 8306 return 0; 8307 dma_error: 8308 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8309 8310 /* clear dma mappings for failed tx_buffer_info map */ 8311 for (;;) { 8312 tx_buffer = &tx_ring->tx_buffer_info[i]; 8313 if (dma_unmap_len(tx_buffer, len)) 8314 dma_unmap_page(tx_ring->dev, 8315 dma_unmap_addr(tx_buffer, dma), 8316 dma_unmap_len(tx_buffer, len), 8317 DMA_TO_DEVICE); 8318 dma_unmap_len_set(tx_buffer, len, 0); 8319 if (tx_buffer == first) 8320 break; 8321 if (i == 0) 8322 i += tx_ring->count; 8323 i--; 8324 } 8325 8326 dev_kfree_skb_any(first->skb); 8327 first->skb = NULL; 8328 8329 tx_ring->next_to_use = i; 8330 8331 return -1; 8332 } 8333 8334 static void ixgbe_atr(struct ixgbe_ring *ring, 8335 struct ixgbe_tx_buffer *first) 8336 { 8337 struct ixgbe_q_vector *q_vector = ring->q_vector; 8338 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8339 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8340 union { 8341 unsigned char *network; 8342 struct iphdr *ipv4; 8343 struct ipv6hdr *ipv6; 8344 } hdr; 8345 struct tcphdr *th; 8346 unsigned int hlen; 8347 struct sk_buff *skb; 8348 __be16 vlan_id; 8349 int l4_proto; 8350 8351 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8352 if (!q_vector) 8353 return; 8354 8355 /* do nothing if sampling is disabled */ 8356 if (!ring->atr_sample_rate) 8357 return; 8358 8359 ring->atr_count++; 8360 8361 /* currently only IPv4/IPv6 with TCP is supported */ 8362 if ((first->protocol != htons(ETH_P_IP)) && 8363 (first->protocol != htons(ETH_P_IPV6))) 8364 return; 8365 8366 /* snag network header to get L4 type and address */ 8367 skb = first->skb; 8368 hdr.network = skb_network_header(skb); 8369 if (unlikely(hdr.network <= skb->data)) 8370 return; 8371 if (skb->encapsulation && 8372 first->protocol == htons(ETH_P_IP) && 8373 hdr.ipv4->protocol == IPPROTO_UDP) { 8374 struct ixgbe_adapter *adapter = q_vector->adapter; 8375 8376 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8377 VXLAN_HEADROOM)) 8378 return; 8379 8380 /* verify the port is recognized as VXLAN */ 8381 if (adapter->vxlan_port && 8382 udp_hdr(skb)->dest == adapter->vxlan_port) 8383 hdr.network = skb_inner_network_header(skb); 8384 8385 if (adapter->geneve_port && 8386 udp_hdr(skb)->dest == adapter->geneve_port) 8387 hdr.network = skb_inner_network_header(skb); 8388 } 8389 8390 /* Make sure we have at least [minimum IPv4 header + TCP] 8391 * or [IPv6 header] bytes 8392 */ 8393 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8394 return; 8395 8396 /* Currently only IPv4/IPv6 with TCP is supported */ 8397 switch (hdr.ipv4->version) { 8398 case IPVERSION: 8399 /* access ihl as u8 to avoid unaligned access on ia64 */ 8400 hlen = (hdr.network[0] & 0x0F) << 2; 8401 l4_proto = hdr.ipv4->protocol; 8402 break; 8403 case 6: 8404 hlen = hdr.network - skb->data; 8405 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8406 hlen -= hdr.network - skb->data; 8407 break; 8408 default: 8409 return; 8410 } 8411 8412 if (l4_proto != IPPROTO_TCP) 8413 return; 8414 8415 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8416 hlen + sizeof(struct tcphdr))) 8417 return; 8418 8419 th = (struct tcphdr *)(hdr.network + hlen); 8420 8421 /* skip this packet since the socket is closing */ 8422 if (th->fin) 8423 return; 8424 8425 /* sample on all syn packets or once every atr sample count */ 8426 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8427 return; 8428 8429 /* reset sample count */ 8430 ring->atr_count = 0; 8431 8432 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8433 8434 /* 8435 * src and dst are inverted, think how the receiver sees them 8436 * 8437 * The input is broken into two sections, a non-compressed section 8438 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8439 * is XORed together and stored in the compressed dword. 8440 */ 8441 input.formatted.vlan_id = vlan_id; 8442 8443 /* 8444 * since src port and flex bytes occupy the same word XOR them together 8445 * and write the value to source port portion of compressed dword 8446 */ 8447 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8448 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8449 else 8450 common.port.src ^= th->dest ^ first->protocol; 8451 common.port.dst ^= th->source; 8452 8453 switch (hdr.ipv4->version) { 8454 case IPVERSION: 8455 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8456 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8457 break; 8458 case 6: 8459 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8460 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8461 hdr.ipv6->saddr.s6_addr32[1] ^ 8462 hdr.ipv6->saddr.s6_addr32[2] ^ 8463 hdr.ipv6->saddr.s6_addr32[3] ^ 8464 hdr.ipv6->daddr.s6_addr32[0] ^ 8465 hdr.ipv6->daddr.s6_addr32[1] ^ 8466 hdr.ipv6->daddr.s6_addr32[2] ^ 8467 hdr.ipv6->daddr.s6_addr32[3]; 8468 break; 8469 default: 8470 break; 8471 } 8472 8473 if (hdr.network != skb_network_header(skb)) 8474 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8475 8476 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8477 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8478 input, common, ring->queue_index); 8479 } 8480 8481 #ifdef IXGBE_FCOE 8482 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8483 struct net_device *sb_dev) 8484 { 8485 struct ixgbe_adapter *adapter; 8486 struct ixgbe_ring_feature *f; 8487 int txq; 8488 8489 if (sb_dev) { 8490 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8491 struct net_device *vdev = sb_dev; 8492 8493 txq = vdev->tc_to_txq[tc].offset; 8494 txq += reciprocal_scale(skb_get_hash(skb), 8495 vdev->tc_to_txq[tc].count); 8496 8497 return txq; 8498 } 8499 8500 /* 8501 * only execute the code below if protocol is FCoE 8502 * or FIP and we have FCoE enabled on the adapter 8503 */ 8504 switch (vlan_get_protocol(skb)) { 8505 case htons(ETH_P_FCOE): 8506 case htons(ETH_P_FIP): 8507 adapter = netdev_priv(dev); 8508 8509 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8510 break; 8511 fallthrough; 8512 default: 8513 return netdev_pick_tx(dev, skb, sb_dev); 8514 } 8515 8516 f = &adapter->ring_feature[RING_F_FCOE]; 8517 8518 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8519 smp_processor_id(); 8520 8521 while (txq >= f->indices) 8522 txq -= f->indices; 8523 8524 return txq + f->offset; 8525 } 8526 8527 #endif 8528 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8529 struct xdp_frame *xdpf) 8530 { 8531 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8532 struct ixgbe_tx_buffer *tx_buffer; 8533 union ixgbe_adv_tx_desc *tx_desc; 8534 u32 len, cmd_type; 8535 dma_addr_t dma; 8536 u16 i; 8537 8538 len = xdpf->len; 8539 8540 if (unlikely(!ixgbe_desc_unused(ring))) 8541 return IXGBE_XDP_CONSUMED; 8542 8543 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8544 if (dma_mapping_error(ring->dev, dma)) 8545 return IXGBE_XDP_CONSUMED; 8546 8547 /* record the location of the first descriptor for this packet */ 8548 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8549 tx_buffer->bytecount = len; 8550 tx_buffer->gso_segs = 1; 8551 tx_buffer->protocol = 0; 8552 8553 i = ring->next_to_use; 8554 tx_desc = IXGBE_TX_DESC(ring, i); 8555 8556 dma_unmap_len_set(tx_buffer, len, len); 8557 dma_unmap_addr_set(tx_buffer, dma, dma); 8558 tx_buffer->xdpf = xdpf; 8559 8560 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8561 8562 /* put descriptor type bits */ 8563 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8564 IXGBE_ADVTXD_DCMD_DEXT | 8565 IXGBE_ADVTXD_DCMD_IFCS; 8566 cmd_type |= len | IXGBE_TXD_CMD; 8567 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8568 tx_desc->read.olinfo_status = 8569 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8570 8571 /* Avoid any potential race with xdp_xmit and cleanup */ 8572 smp_wmb(); 8573 8574 /* set next_to_watch value indicating a packet is present */ 8575 i++; 8576 if (i == ring->count) 8577 i = 0; 8578 8579 tx_buffer->next_to_watch = tx_desc; 8580 ring->next_to_use = i; 8581 8582 return IXGBE_XDP_TX; 8583 } 8584 8585 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8586 struct ixgbe_adapter *adapter, 8587 struct ixgbe_ring *tx_ring) 8588 { 8589 struct ixgbe_tx_buffer *first; 8590 int tso; 8591 u32 tx_flags = 0; 8592 unsigned short f; 8593 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8594 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8595 __be16 protocol = skb->protocol; 8596 u8 hdr_len = 0; 8597 8598 /* 8599 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8600 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8601 * + 2 desc gap to keep tail from touching head, 8602 * + 1 desc for context descriptor, 8603 * otherwise try next time 8604 */ 8605 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8606 count += TXD_USE_COUNT(skb_frag_size( 8607 &skb_shinfo(skb)->frags[f])); 8608 8609 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8610 tx_ring->tx_stats.tx_busy++; 8611 return NETDEV_TX_BUSY; 8612 } 8613 8614 /* record the location of the first descriptor for this packet */ 8615 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8616 first->skb = skb; 8617 first->bytecount = skb->len; 8618 first->gso_segs = 1; 8619 8620 /* if we have a HW VLAN tag being added default to the HW one */ 8621 if (skb_vlan_tag_present(skb)) { 8622 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8623 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8624 /* else if it is a SW VLAN check the next protocol and store the tag */ 8625 } else if (protocol == htons(ETH_P_8021Q)) { 8626 struct vlan_hdr *vhdr, _vhdr; 8627 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8628 if (!vhdr) 8629 goto out_drop; 8630 8631 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8632 IXGBE_TX_FLAGS_VLAN_SHIFT; 8633 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8634 } 8635 protocol = vlan_get_protocol(skb); 8636 8637 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8638 adapter->ptp_clock) { 8639 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 8640 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8641 &adapter->state)) { 8642 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8643 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8644 8645 /* schedule check for Tx timestamp */ 8646 adapter->ptp_tx_skb = skb_get(skb); 8647 adapter->ptp_tx_start = jiffies; 8648 schedule_work(&adapter->ptp_tx_work); 8649 } else { 8650 adapter->tx_hwtstamp_skipped++; 8651 } 8652 } 8653 8654 #ifdef CONFIG_PCI_IOV 8655 /* 8656 * Use the l2switch_enable flag - would be false if the DMA 8657 * Tx switch had been disabled. 8658 */ 8659 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8660 tx_flags |= IXGBE_TX_FLAGS_CC; 8661 8662 #endif 8663 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8664 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8665 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8666 (skb->priority != TC_PRIO_CONTROL))) { 8667 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8668 tx_flags |= (skb->priority & 0x7) << 8669 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8670 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8671 struct vlan_ethhdr *vhdr; 8672 8673 if (skb_cow_head(skb, 0)) 8674 goto out_drop; 8675 vhdr = (struct vlan_ethhdr *)skb->data; 8676 vhdr->h_vlan_TCI = htons(tx_flags >> 8677 IXGBE_TX_FLAGS_VLAN_SHIFT); 8678 } else { 8679 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8680 } 8681 } 8682 8683 /* record initial flags and protocol */ 8684 first->tx_flags = tx_flags; 8685 first->protocol = protocol; 8686 8687 #ifdef IXGBE_FCOE 8688 /* setup tx offload for FCoE */ 8689 if ((protocol == htons(ETH_P_FCOE)) && 8690 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8691 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8692 if (tso < 0) 8693 goto out_drop; 8694 8695 goto xmit_fcoe; 8696 } 8697 8698 #endif /* IXGBE_FCOE */ 8699 8700 #ifdef CONFIG_IXGBE_IPSEC 8701 if (xfrm_offload(skb) && 8702 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8703 goto out_drop; 8704 #endif 8705 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8706 if (tso < 0) 8707 goto out_drop; 8708 else if (!tso) 8709 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8710 8711 /* add the ATR filter if ATR is on */ 8712 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8713 ixgbe_atr(tx_ring, first); 8714 8715 #ifdef IXGBE_FCOE 8716 xmit_fcoe: 8717 #endif /* IXGBE_FCOE */ 8718 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8719 goto cleanup_tx_timestamp; 8720 8721 return NETDEV_TX_OK; 8722 8723 out_drop: 8724 dev_kfree_skb_any(first->skb); 8725 first->skb = NULL; 8726 cleanup_tx_timestamp: 8727 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8728 dev_kfree_skb_any(adapter->ptp_tx_skb); 8729 adapter->ptp_tx_skb = NULL; 8730 cancel_work_sync(&adapter->ptp_tx_work); 8731 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8732 } 8733 8734 return NETDEV_TX_OK; 8735 } 8736 8737 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8738 struct net_device *netdev, 8739 struct ixgbe_ring *ring) 8740 { 8741 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8742 struct ixgbe_ring *tx_ring; 8743 8744 /* 8745 * The minimum packet size for olinfo paylen is 17 so pad the skb 8746 * in order to meet this minimum size requirement. 8747 */ 8748 if (skb_put_padto(skb, 17)) 8749 return NETDEV_TX_OK; 8750 8751 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 8752 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8753 return NETDEV_TX_BUSY; 8754 8755 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8756 } 8757 8758 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8759 struct net_device *netdev) 8760 { 8761 return __ixgbe_xmit_frame(skb, netdev, NULL); 8762 } 8763 8764 /** 8765 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8766 * @netdev: network interface device structure 8767 * @p: pointer to an address structure 8768 * 8769 * Returns 0 on success, negative on failure 8770 **/ 8771 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8772 { 8773 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8774 struct ixgbe_hw *hw = &adapter->hw; 8775 struct sockaddr *addr = p; 8776 8777 if (!is_valid_ether_addr(addr->sa_data)) 8778 return -EADDRNOTAVAIL; 8779 8780 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8781 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8782 8783 ixgbe_mac_set_default_filter(adapter); 8784 8785 return 0; 8786 } 8787 8788 static int 8789 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8790 { 8791 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8792 struct ixgbe_hw *hw = &adapter->hw; 8793 u16 value; 8794 int rc; 8795 8796 if (adapter->mii_bus) { 8797 int regnum = addr; 8798 8799 if (devad != MDIO_DEVAD_NONE) 8800 regnum |= (devad << 16) | MII_ADDR_C45; 8801 8802 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8803 } 8804 8805 if (prtad != hw->phy.mdio.prtad) 8806 return -EINVAL; 8807 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8808 if (!rc) 8809 rc = value; 8810 return rc; 8811 } 8812 8813 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8814 u16 addr, u16 value) 8815 { 8816 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8817 struct ixgbe_hw *hw = &adapter->hw; 8818 8819 if (adapter->mii_bus) { 8820 int regnum = addr; 8821 8822 if (devad != MDIO_DEVAD_NONE) 8823 regnum |= (devad << 16) | MII_ADDR_C45; 8824 8825 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8826 } 8827 8828 if (prtad != hw->phy.mdio.prtad) 8829 return -EINVAL; 8830 return hw->phy.ops.write_reg(hw, addr, devad, value); 8831 } 8832 8833 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8834 { 8835 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8836 8837 switch (cmd) { 8838 case SIOCSHWTSTAMP: 8839 return ixgbe_ptp_set_ts_config(adapter, req); 8840 case SIOCGHWTSTAMP: 8841 return ixgbe_ptp_get_ts_config(adapter, req); 8842 case SIOCGMIIPHY: 8843 if (!adapter->hw.phy.ops.read_reg) 8844 return -EOPNOTSUPP; 8845 fallthrough; 8846 default: 8847 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8848 } 8849 } 8850 8851 /** 8852 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8853 * netdev->dev_addrs 8854 * @dev: network interface device structure 8855 * 8856 * Returns non-zero on failure 8857 **/ 8858 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8859 { 8860 int err = 0; 8861 struct ixgbe_adapter *adapter = netdev_priv(dev); 8862 struct ixgbe_hw *hw = &adapter->hw; 8863 8864 if (is_valid_ether_addr(hw->mac.san_addr)) { 8865 rtnl_lock(); 8866 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8867 rtnl_unlock(); 8868 8869 /* update SAN MAC vmdq pool selection */ 8870 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8871 } 8872 return err; 8873 } 8874 8875 /** 8876 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8877 * netdev->dev_addrs 8878 * @dev: network interface device structure 8879 * 8880 * Returns non-zero on failure 8881 **/ 8882 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8883 { 8884 int err = 0; 8885 struct ixgbe_adapter *adapter = netdev_priv(dev); 8886 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8887 8888 if (is_valid_ether_addr(mac->san_addr)) { 8889 rtnl_lock(); 8890 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8891 rtnl_unlock(); 8892 } 8893 return err; 8894 } 8895 8896 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8897 struct ixgbe_ring *ring) 8898 { 8899 u64 bytes, packets; 8900 unsigned int start; 8901 8902 if (ring) { 8903 do { 8904 start = u64_stats_fetch_begin_irq(&ring->syncp); 8905 packets = ring->stats.packets; 8906 bytes = ring->stats.bytes; 8907 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8908 stats->tx_packets += packets; 8909 stats->tx_bytes += bytes; 8910 } 8911 } 8912 8913 static void ixgbe_get_stats64(struct net_device *netdev, 8914 struct rtnl_link_stats64 *stats) 8915 { 8916 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8917 int i; 8918 8919 rcu_read_lock(); 8920 for (i = 0; i < adapter->num_rx_queues; i++) { 8921 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8922 u64 bytes, packets; 8923 unsigned int start; 8924 8925 if (ring) { 8926 do { 8927 start = u64_stats_fetch_begin_irq(&ring->syncp); 8928 packets = ring->stats.packets; 8929 bytes = ring->stats.bytes; 8930 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8931 stats->rx_packets += packets; 8932 stats->rx_bytes += bytes; 8933 } 8934 } 8935 8936 for (i = 0; i < adapter->num_tx_queues; i++) { 8937 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8938 8939 ixgbe_get_ring_stats64(stats, ring); 8940 } 8941 for (i = 0; i < adapter->num_xdp_queues; i++) { 8942 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8943 8944 ixgbe_get_ring_stats64(stats, ring); 8945 } 8946 rcu_read_unlock(); 8947 8948 /* following stats updated by ixgbe_watchdog_task() */ 8949 stats->multicast = netdev->stats.multicast; 8950 stats->rx_errors = netdev->stats.rx_errors; 8951 stats->rx_length_errors = netdev->stats.rx_length_errors; 8952 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8953 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8954 } 8955 8956 #ifdef CONFIG_IXGBE_DCB 8957 /** 8958 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8959 * @adapter: pointer to ixgbe_adapter 8960 * @tc: number of traffic classes currently enabled 8961 * 8962 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8963 * 802.1Q priority maps to a packet buffer that exists. 8964 */ 8965 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8966 { 8967 struct ixgbe_hw *hw = &adapter->hw; 8968 u32 reg, rsave; 8969 int i; 8970 8971 /* 82598 have a static priority to TC mapping that can not 8972 * be changed so no validation is needed. 8973 */ 8974 if (hw->mac.type == ixgbe_mac_82598EB) 8975 return; 8976 8977 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8978 rsave = reg; 8979 8980 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8981 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8982 8983 /* If up2tc is out of bounds default to zero */ 8984 if (up2tc > tc) 8985 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8986 } 8987 8988 if (reg != rsave) 8989 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8990 8991 return; 8992 } 8993 8994 /** 8995 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8996 * @adapter: Pointer to adapter struct 8997 * 8998 * Populate the netdev user priority to tc map 8999 */ 9000 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9001 { 9002 struct net_device *dev = adapter->netdev; 9003 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9004 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9005 u8 prio; 9006 9007 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9008 u8 tc = 0; 9009 9010 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9011 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9012 else if (ets) 9013 tc = ets->prio_tc[prio]; 9014 9015 netdev_set_prio_tc_map(dev, prio, tc); 9016 } 9017 } 9018 9019 #endif /* CONFIG_IXGBE_DCB */ 9020 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9021 struct netdev_nested_priv *priv) 9022 { 9023 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9024 struct ixgbe_fwd_adapter *accel; 9025 int pool; 9026 9027 /* we only care about macvlans... */ 9028 if (!netif_is_macvlan(vdev)) 9029 return 0; 9030 9031 /* that have hardware offload enabled... */ 9032 accel = macvlan_accel_priv(vdev); 9033 if (!accel) 9034 return 0; 9035 9036 /* If we can relocate to a different bit do so */ 9037 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9038 if (pool < adapter->num_rx_pools) { 9039 set_bit(pool, adapter->fwd_bitmask); 9040 accel->pool = pool; 9041 return 0; 9042 } 9043 9044 /* if we cannot find a free pool then disable the offload */ 9045 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9046 macvlan_release_l2fw_offload(vdev); 9047 9048 /* unbind the queues and drop the subordinate channel config */ 9049 netdev_unbind_sb_channel(adapter->netdev, vdev); 9050 netdev_set_sb_channel(vdev, 0); 9051 9052 kfree(accel); 9053 9054 return 0; 9055 } 9056 9057 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9058 { 9059 struct ixgbe_adapter *adapter = netdev_priv(dev); 9060 struct netdev_nested_priv priv = { 9061 .data = (void *)adapter, 9062 }; 9063 9064 /* flush any stale bits out of the fwd bitmask */ 9065 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9066 9067 /* walk through upper devices reassigning pools */ 9068 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9069 &priv); 9070 } 9071 9072 /** 9073 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9074 * 9075 * @dev: net device to configure 9076 * @tc: number of traffic classes to enable 9077 */ 9078 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9079 { 9080 struct ixgbe_adapter *adapter = netdev_priv(dev); 9081 struct ixgbe_hw *hw = &adapter->hw; 9082 9083 /* Hardware supports up to 8 traffic classes */ 9084 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9085 return -EINVAL; 9086 9087 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9088 return -EINVAL; 9089 9090 /* Hardware has to reinitialize queues and interrupts to 9091 * match packet buffer alignment. Unfortunately, the 9092 * hardware is not flexible enough to do this dynamically. 9093 */ 9094 if (netif_running(dev)) 9095 ixgbe_close(dev); 9096 else 9097 ixgbe_reset(adapter); 9098 9099 ixgbe_clear_interrupt_scheme(adapter); 9100 9101 #ifdef CONFIG_IXGBE_DCB 9102 if (tc) { 9103 if (adapter->xdp_prog) { 9104 e_warn(probe, "DCB is not supported with XDP\n"); 9105 9106 ixgbe_init_interrupt_scheme(adapter); 9107 if (netif_running(dev)) 9108 ixgbe_open(dev); 9109 return -EINVAL; 9110 } 9111 9112 netdev_set_num_tc(dev, tc); 9113 ixgbe_set_prio_tc_map(adapter); 9114 9115 adapter->hw_tcs = tc; 9116 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9117 9118 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9119 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9120 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9121 } 9122 } else { 9123 netdev_reset_tc(dev); 9124 9125 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9126 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9127 9128 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9129 adapter->hw_tcs = tc; 9130 9131 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9132 adapter->dcb_cfg.pfc_mode_enable = false; 9133 } 9134 9135 ixgbe_validate_rtr(adapter, tc); 9136 9137 #endif /* CONFIG_IXGBE_DCB */ 9138 ixgbe_init_interrupt_scheme(adapter); 9139 9140 ixgbe_defrag_macvlan_pools(dev); 9141 9142 if (netif_running(dev)) 9143 return ixgbe_open(dev); 9144 9145 return 0; 9146 } 9147 9148 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9149 struct tc_cls_u32_offload *cls) 9150 { 9151 u32 hdl = cls->knode.handle; 9152 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9153 u32 loc = cls->knode.handle & 0xfffff; 9154 int err = 0, i, j; 9155 struct ixgbe_jump_table *jump = NULL; 9156 9157 if (loc > IXGBE_MAX_HW_ENTRIES) 9158 return -EINVAL; 9159 9160 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9161 return -EINVAL; 9162 9163 /* Clear this filter in the link data it is associated with */ 9164 if (uhtid != 0x800) { 9165 jump = adapter->jump_tables[uhtid]; 9166 if (!jump) 9167 return -EINVAL; 9168 if (!test_bit(loc - 1, jump->child_loc_map)) 9169 return -EINVAL; 9170 clear_bit(loc - 1, jump->child_loc_map); 9171 } 9172 9173 /* Check if the filter being deleted is a link */ 9174 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9175 jump = adapter->jump_tables[i]; 9176 if (jump && jump->link_hdl == hdl) { 9177 /* Delete filters in the hardware in the child hash 9178 * table associated with this link 9179 */ 9180 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9181 if (!test_bit(j, jump->child_loc_map)) 9182 continue; 9183 spin_lock(&adapter->fdir_perfect_lock); 9184 err = ixgbe_update_ethtool_fdir_entry(adapter, 9185 NULL, 9186 j + 1); 9187 spin_unlock(&adapter->fdir_perfect_lock); 9188 clear_bit(j, jump->child_loc_map); 9189 } 9190 /* Remove resources for this link */ 9191 kfree(jump->input); 9192 kfree(jump->mask); 9193 kfree(jump); 9194 adapter->jump_tables[i] = NULL; 9195 return err; 9196 } 9197 } 9198 9199 spin_lock(&adapter->fdir_perfect_lock); 9200 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9201 spin_unlock(&adapter->fdir_perfect_lock); 9202 return err; 9203 } 9204 9205 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9206 struct tc_cls_u32_offload *cls) 9207 { 9208 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9209 9210 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9211 return -EINVAL; 9212 9213 /* This ixgbe devices do not support hash tables at the moment 9214 * so abort when given hash tables. 9215 */ 9216 if (cls->hnode.divisor > 0) 9217 return -EINVAL; 9218 9219 set_bit(uhtid - 1, &adapter->tables); 9220 return 0; 9221 } 9222 9223 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9224 struct tc_cls_u32_offload *cls) 9225 { 9226 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9227 9228 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9229 return -EINVAL; 9230 9231 clear_bit(uhtid - 1, &adapter->tables); 9232 return 0; 9233 } 9234 9235 #ifdef CONFIG_NET_CLS_ACT 9236 struct upper_walk_data { 9237 struct ixgbe_adapter *adapter; 9238 u64 action; 9239 int ifindex; 9240 u8 queue; 9241 }; 9242 9243 static int get_macvlan_queue(struct net_device *upper, 9244 struct netdev_nested_priv *priv) 9245 { 9246 if (netif_is_macvlan(upper)) { 9247 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9248 struct ixgbe_adapter *adapter; 9249 struct upper_walk_data *data; 9250 int ifindex; 9251 9252 data = (struct upper_walk_data *)priv->data; 9253 ifindex = data->ifindex; 9254 adapter = data->adapter; 9255 if (vadapter && upper->ifindex == ifindex) { 9256 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9257 data->action = data->queue; 9258 return 1; 9259 } 9260 } 9261 9262 return 0; 9263 } 9264 9265 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9266 u8 *queue, u64 *action) 9267 { 9268 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9269 unsigned int num_vfs = adapter->num_vfs, vf; 9270 struct netdev_nested_priv priv; 9271 struct upper_walk_data data; 9272 struct net_device *upper; 9273 9274 /* redirect to a SRIOV VF */ 9275 for (vf = 0; vf < num_vfs; ++vf) { 9276 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9277 if (upper->ifindex == ifindex) { 9278 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9279 *action = vf + 1; 9280 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9281 return 0; 9282 } 9283 } 9284 9285 /* redirect to a offloaded macvlan netdev */ 9286 data.adapter = adapter; 9287 data.ifindex = ifindex; 9288 data.action = 0; 9289 data.queue = 0; 9290 priv.data = (void *)&data; 9291 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9292 get_macvlan_queue, &priv)) { 9293 *action = data.action; 9294 *queue = data.queue; 9295 9296 return 0; 9297 } 9298 9299 return -EINVAL; 9300 } 9301 9302 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9303 struct tcf_exts *exts, u64 *action, u8 *queue) 9304 { 9305 const struct tc_action *a; 9306 int i; 9307 9308 if (!tcf_exts_has_actions(exts)) 9309 return -EINVAL; 9310 9311 tcf_exts_for_each_action(i, a, exts) { 9312 /* Drop action */ 9313 if (is_tcf_gact_shot(a)) { 9314 *action = IXGBE_FDIR_DROP_QUEUE; 9315 *queue = IXGBE_FDIR_DROP_QUEUE; 9316 return 0; 9317 } 9318 9319 /* Redirect to a VF or a offloaded macvlan */ 9320 if (is_tcf_mirred_egress_redirect(a)) { 9321 struct net_device *dev = tcf_mirred_dev(a); 9322 9323 if (!dev) 9324 return -EINVAL; 9325 return handle_redirect_action(adapter, dev->ifindex, 9326 queue, action); 9327 } 9328 9329 return -EINVAL; 9330 } 9331 9332 return -EINVAL; 9333 } 9334 #else 9335 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9336 struct tcf_exts *exts, u64 *action, u8 *queue) 9337 { 9338 return -EINVAL; 9339 } 9340 #endif /* CONFIG_NET_CLS_ACT */ 9341 9342 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9343 union ixgbe_atr_input *mask, 9344 struct tc_cls_u32_offload *cls, 9345 struct ixgbe_mat_field *field_ptr, 9346 struct ixgbe_nexthdr *nexthdr) 9347 { 9348 int i, j, off; 9349 __be32 val, m; 9350 bool found_entry = false, found_jump_field = false; 9351 9352 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9353 off = cls->knode.sel->keys[i].off; 9354 val = cls->knode.sel->keys[i].val; 9355 m = cls->knode.sel->keys[i].mask; 9356 9357 for (j = 0; field_ptr[j].val; j++) { 9358 if (field_ptr[j].off == off) { 9359 field_ptr[j].val(input, mask, (__force u32)val, 9360 (__force u32)m); 9361 input->filter.formatted.flow_type |= 9362 field_ptr[j].type; 9363 found_entry = true; 9364 break; 9365 } 9366 } 9367 if (nexthdr) { 9368 if (nexthdr->off == cls->knode.sel->keys[i].off && 9369 nexthdr->val == 9370 (__force u32)cls->knode.sel->keys[i].val && 9371 nexthdr->mask == 9372 (__force u32)cls->knode.sel->keys[i].mask) 9373 found_jump_field = true; 9374 else 9375 continue; 9376 } 9377 } 9378 9379 if (nexthdr && !found_jump_field) 9380 return -EINVAL; 9381 9382 if (!found_entry) 9383 return 0; 9384 9385 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9386 IXGBE_ATR_L4TYPE_MASK; 9387 9388 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9389 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9390 9391 return 0; 9392 } 9393 9394 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9395 struct tc_cls_u32_offload *cls) 9396 { 9397 __be16 protocol = cls->common.protocol; 9398 u32 loc = cls->knode.handle & 0xfffff; 9399 struct ixgbe_hw *hw = &adapter->hw; 9400 struct ixgbe_mat_field *field_ptr; 9401 struct ixgbe_fdir_filter *input = NULL; 9402 union ixgbe_atr_input *mask = NULL; 9403 struct ixgbe_jump_table *jump = NULL; 9404 int i, err = -EINVAL; 9405 u8 queue; 9406 u32 uhtid, link_uhtid; 9407 9408 uhtid = TC_U32_USERHTID(cls->knode.handle); 9409 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9410 9411 /* At the moment cls_u32 jumps to network layer and skips past 9412 * L2 headers. The canonical method to match L2 frames is to use 9413 * negative values. However this is error prone at best but really 9414 * just broken because there is no way to "know" what sort of hdr 9415 * is in front of the network layer. Fix cls_u32 to support L2 9416 * headers when needed. 9417 */ 9418 if (protocol != htons(ETH_P_IP)) 9419 return err; 9420 9421 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9422 e_err(drv, "Location out of range\n"); 9423 return err; 9424 } 9425 9426 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9427 * links and also the fields used to advance the parser across each 9428 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9429 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9430 * To add support for new nodes update ixgbe_model.h parse structures 9431 * this function _should_ be generic try not to hardcode values here. 9432 */ 9433 if (uhtid == 0x800) { 9434 field_ptr = (adapter->jump_tables[0])->mat; 9435 } else { 9436 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9437 return err; 9438 if (!adapter->jump_tables[uhtid]) 9439 return err; 9440 field_ptr = (adapter->jump_tables[uhtid])->mat; 9441 } 9442 9443 if (!field_ptr) 9444 return err; 9445 9446 /* At this point we know the field_ptr is valid and need to either 9447 * build cls_u32 link or attach filter. Because adding a link to 9448 * a handle that does not exist is invalid and the same for adding 9449 * rules to handles that don't exist. 9450 */ 9451 9452 if (link_uhtid) { 9453 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9454 9455 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9456 return err; 9457 9458 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9459 return err; 9460 9461 /* Multiple filters as links to the same hash table are not 9462 * supported. To add a new filter with the same next header 9463 * but different match/jump conditions, create a new hash table 9464 * and link to it. 9465 */ 9466 if (adapter->jump_tables[link_uhtid] && 9467 (adapter->jump_tables[link_uhtid])->link_hdl) { 9468 e_err(drv, "Link filter exists for link: %x\n", 9469 link_uhtid); 9470 return err; 9471 } 9472 9473 for (i = 0; nexthdr[i].jump; i++) { 9474 if (nexthdr[i].o != cls->knode.sel->offoff || 9475 nexthdr[i].s != cls->knode.sel->offshift || 9476 nexthdr[i].m != 9477 (__force u32)cls->knode.sel->offmask) 9478 return err; 9479 9480 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9481 if (!jump) 9482 return -ENOMEM; 9483 input = kzalloc(sizeof(*input), GFP_KERNEL); 9484 if (!input) { 9485 err = -ENOMEM; 9486 goto free_jump; 9487 } 9488 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9489 if (!mask) { 9490 err = -ENOMEM; 9491 goto free_input; 9492 } 9493 jump->input = input; 9494 jump->mask = mask; 9495 jump->link_hdl = cls->knode.handle; 9496 9497 err = ixgbe_clsu32_build_input(input, mask, cls, 9498 field_ptr, &nexthdr[i]); 9499 if (!err) { 9500 jump->mat = nexthdr[i].jump; 9501 adapter->jump_tables[link_uhtid] = jump; 9502 break; 9503 } else { 9504 kfree(mask); 9505 kfree(input); 9506 kfree(jump); 9507 } 9508 } 9509 return 0; 9510 } 9511 9512 input = kzalloc(sizeof(*input), GFP_KERNEL); 9513 if (!input) 9514 return -ENOMEM; 9515 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9516 if (!mask) { 9517 err = -ENOMEM; 9518 goto free_input; 9519 } 9520 9521 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9522 if ((adapter->jump_tables[uhtid])->input) 9523 memcpy(input, (adapter->jump_tables[uhtid])->input, 9524 sizeof(*input)); 9525 if ((adapter->jump_tables[uhtid])->mask) 9526 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9527 sizeof(*mask)); 9528 9529 /* Lookup in all child hash tables if this location is already 9530 * filled with a filter 9531 */ 9532 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9533 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9534 9535 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9536 e_err(drv, "Filter exists in location: %x\n", 9537 loc); 9538 err = -EINVAL; 9539 goto err_out; 9540 } 9541 } 9542 } 9543 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9544 if (err) 9545 goto err_out; 9546 9547 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9548 &queue); 9549 if (err < 0) 9550 goto err_out; 9551 9552 input->sw_idx = loc; 9553 9554 spin_lock(&adapter->fdir_perfect_lock); 9555 9556 if (hlist_empty(&adapter->fdir_filter_list)) { 9557 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9558 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9559 if (err) 9560 goto err_out_w_lock; 9561 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9562 err = -EINVAL; 9563 goto err_out_w_lock; 9564 } 9565 9566 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9567 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9568 input->sw_idx, queue); 9569 if (err) 9570 goto err_out_w_lock; 9571 9572 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9573 spin_unlock(&adapter->fdir_perfect_lock); 9574 9575 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9576 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9577 9578 kfree(mask); 9579 return err; 9580 err_out_w_lock: 9581 spin_unlock(&adapter->fdir_perfect_lock); 9582 err_out: 9583 kfree(mask); 9584 free_input: 9585 kfree(input); 9586 free_jump: 9587 kfree(jump); 9588 return err; 9589 } 9590 9591 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9592 struct tc_cls_u32_offload *cls_u32) 9593 { 9594 switch (cls_u32->command) { 9595 case TC_CLSU32_NEW_KNODE: 9596 case TC_CLSU32_REPLACE_KNODE: 9597 return ixgbe_configure_clsu32(adapter, cls_u32); 9598 case TC_CLSU32_DELETE_KNODE: 9599 return ixgbe_delete_clsu32(adapter, cls_u32); 9600 case TC_CLSU32_NEW_HNODE: 9601 case TC_CLSU32_REPLACE_HNODE: 9602 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9603 case TC_CLSU32_DELETE_HNODE: 9604 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9605 default: 9606 return -EOPNOTSUPP; 9607 } 9608 } 9609 9610 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9611 void *cb_priv) 9612 { 9613 struct ixgbe_adapter *adapter = cb_priv; 9614 9615 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9616 return -EOPNOTSUPP; 9617 9618 switch (type) { 9619 case TC_SETUP_CLSU32: 9620 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9621 default: 9622 return -EOPNOTSUPP; 9623 } 9624 } 9625 9626 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9627 struct tc_mqprio_qopt *mqprio) 9628 { 9629 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9630 return ixgbe_setup_tc(dev, mqprio->num_tc); 9631 } 9632 9633 static LIST_HEAD(ixgbe_block_cb_list); 9634 9635 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9636 void *type_data) 9637 { 9638 struct ixgbe_adapter *adapter = netdev_priv(dev); 9639 9640 switch (type) { 9641 case TC_SETUP_BLOCK: 9642 return flow_block_cb_setup_simple(type_data, 9643 &ixgbe_block_cb_list, 9644 ixgbe_setup_tc_block_cb, 9645 adapter, adapter, true); 9646 case TC_SETUP_QDISC_MQPRIO: 9647 return ixgbe_setup_tc_mqprio(dev, type_data); 9648 default: 9649 return -EOPNOTSUPP; 9650 } 9651 } 9652 9653 #ifdef CONFIG_PCI_IOV 9654 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9655 { 9656 struct net_device *netdev = adapter->netdev; 9657 9658 rtnl_lock(); 9659 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9660 rtnl_unlock(); 9661 } 9662 9663 #endif 9664 void ixgbe_do_reset(struct net_device *netdev) 9665 { 9666 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9667 9668 if (netif_running(netdev)) 9669 ixgbe_reinit_locked(adapter); 9670 else 9671 ixgbe_reset(adapter); 9672 } 9673 9674 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9675 netdev_features_t features) 9676 { 9677 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9678 9679 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9680 if (!(features & NETIF_F_RXCSUM)) 9681 features &= ~NETIF_F_LRO; 9682 9683 /* Turn off LRO if not RSC capable */ 9684 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9685 features &= ~NETIF_F_LRO; 9686 9687 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9688 e_dev_err("LRO is not supported with XDP\n"); 9689 features &= ~NETIF_F_LRO; 9690 } 9691 9692 return features; 9693 } 9694 9695 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9696 { 9697 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9698 num_online_cpus()); 9699 9700 /* go back to full RSS if we're not running SR-IOV */ 9701 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9702 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9703 IXGBE_FLAG_SRIOV_ENABLED); 9704 9705 adapter->ring_feature[RING_F_RSS].limit = rss; 9706 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9707 9708 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9709 } 9710 9711 static int ixgbe_set_features(struct net_device *netdev, 9712 netdev_features_t features) 9713 { 9714 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9715 netdev_features_t changed = netdev->features ^ features; 9716 bool need_reset = false; 9717 9718 /* Make sure RSC matches LRO, reset if change */ 9719 if (!(features & NETIF_F_LRO)) { 9720 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9721 need_reset = true; 9722 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9723 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9724 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9725 if (adapter->rx_itr_setting == 1 || 9726 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9727 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9728 need_reset = true; 9729 } else if ((changed ^ features) & NETIF_F_LRO) { 9730 e_info(probe, "rx-usecs set too low, " 9731 "disabling RSC\n"); 9732 } 9733 } 9734 9735 /* 9736 * Check if Flow Director n-tuple support or hw_tc support was 9737 * enabled or disabled. If the state changed, we need to reset. 9738 */ 9739 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9740 /* turn off ATR, enable perfect filters and reset */ 9741 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9742 need_reset = true; 9743 9744 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9745 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9746 } else { 9747 /* turn off perfect filters, enable ATR and reset */ 9748 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9749 need_reset = true; 9750 9751 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9752 9753 /* We cannot enable ATR if SR-IOV is enabled */ 9754 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9755 /* We cannot enable ATR if we have 2 or more tcs */ 9756 (adapter->hw_tcs > 1) || 9757 /* We cannot enable ATR if RSS is disabled */ 9758 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9759 /* A sample rate of 0 indicates ATR disabled */ 9760 (!adapter->atr_sample_rate)) 9761 ; /* do nothing not supported */ 9762 else /* otherwise supported and set the flag */ 9763 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9764 } 9765 9766 if (changed & NETIF_F_RXALL) 9767 need_reset = true; 9768 9769 netdev->features = features; 9770 9771 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9772 ixgbe_reset_l2fw_offload(adapter); 9773 else if (need_reset) 9774 ixgbe_do_reset(netdev); 9775 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9776 NETIF_F_HW_VLAN_CTAG_FILTER)) 9777 ixgbe_set_rx_mode(netdev); 9778 9779 return 1; 9780 } 9781 9782 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9783 struct net_device *dev, 9784 const unsigned char *addr, u16 vid, 9785 u16 flags, 9786 struct netlink_ext_ack *extack) 9787 { 9788 /* guarantee we can provide a unique filter for the unicast address */ 9789 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9790 struct ixgbe_adapter *adapter = netdev_priv(dev); 9791 u16 pool = VMDQ_P(0); 9792 9793 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9794 return -ENOMEM; 9795 } 9796 9797 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9798 } 9799 9800 /** 9801 * ixgbe_configure_bridge_mode - set various bridge modes 9802 * @adapter: the private structure 9803 * @mode: requested bridge mode 9804 * 9805 * Configure some settings require for various bridge modes. 9806 **/ 9807 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9808 __u16 mode) 9809 { 9810 struct ixgbe_hw *hw = &adapter->hw; 9811 unsigned int p, num_pools; 9812 u32 vmdctl; 9813 9814 switch (mode) { 9815 case BRIDGE_MODE_VEPA: 9816 /* disable Tx loopback, rely on switch hairpin mode */ 9817 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9818 9819 /* must enable Rx switching replication to allow multicast 9820 * packet reception on all VFs, and to enable source address 9821 * pruning. 9822 */ 9823 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9824 vmdctl |= IXGBE_VT_CTL_REPLEN; 9825 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9826 9827 /* enable Rx source address pruning. Note, this requires 9828 * replication to be enabled or else it does nothing. 9829 */ 9830 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9831 for (p = 0; p < num_pools; p++) { 9832 if (hw->mac.ops.set_source_address_pruning) 9833 hw->mac.ops.set_source_address_pruning(hw, 9834 true, 9835 p); 9836 } 9837 break; 9838 case BRIDGE_MODE_VEB: 9839 /* enable Tx loopback for internal VF/PF communication */ 9840 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9841 IXGBE_PFDTXGSWC_VT_LBEN); 9842 9843 /* disable Rx switching replication unless we have SR-IOV 9844 * virtual functions 9845 */ 9846 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9847 if (!adapter->num_vfs) 9848 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9849 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9850 9851 /* disable Rx source address pruning, since we don't expect to 9852 * be receiving external loopback of our transmitted frames. 9853 */ 9854 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9855 for (p = 0; p < num_pools; p++) { 9856 if (hw->mac.ops.set_source_address_pruning) 9857 hw->mac.ops.set_source_address_pruning(hw, 9858 false, 9859 p); 9860 } 9861 break; 9862 default: 9863 return -EINVAL; 9864 } 9865 9866 adapter->bridge_mode = mode; 9867 9868 e_info(drv, "enabling bridge mode: %s\n", 9869 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9870 9871 return 0; 9872 } 9873 9874 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9875 struct nlmsghdr *nlh, u16 flags, 9876 struct netlink_ext_ack *extack) 9877 { 9878 struct ixgbe_adapter *adapter = netdev_priv(dev); 9879 struct nlattr *attr, *br_spec; 9880 int rem; 9881 9882 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9883 return -EOPNOTSUPP; 9884 9885 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9886 if (!br_spec) 9887 return -EINVAL; 9888 9889 nla_for_each_nested(attr, br_spec, rem) { 9890 int status; 9891 __u16 mode; 9892 9893 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9894 continue; 9895 9896 if (nla_len(attr) < sizeof(mode)) 9897 return -EINVAL; 9898 9899 mode = nla_get_u16(attr); 9900 status = ixgbe_configure_bridge_mode(adapter, mode); 9901 if (status) 9902 return status; 9903 9904 break; 9905 } 9906 9907 return 0; 9908 } 9909 9910 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9911 struct net_device *dev, 9912 u32 filter_mask, int nlflags) 9913 { 9914 struct ixgbe_adapter *adapter = netdev_priv(dev); 9915 9916 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9917 return 0; 9918 9919 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9920 adapter->bridge_mode, 0, 0, nlflags, 9921 filter_mask, NULL); 9922 } 9923 9924 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9925 { 9926 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9927 struct ixgbe_fwd_adapter *accel; 9928 int tcs = adapter->hw_tcs ? : 1; 9929 int pool, err; 9930 9931 if (adapter->xdp_prog) { 9932 e_warn(probe, "L2FW offload is not supported with XDP\n"); 9933 return ERR_PTR(-EINVAL); 9934 } 9935 9936 /* The hardware supported by ixgbe only filters on the destination MAC 9937 * address. In order to avoid issues we only support offloading modes 9938 * where the hardware can actually provide the functionality. 9939 */ 9940 if (!macvlan_supports_dest_filter(vdev)) 9941 return ERR_PTR(-EMEDIUMTYPE); 9942 9943 /* We need to lock down the macvlan to be a single queue device so that 9944 * we can reuse the tc_to_txq field in the macvlan netdev to represent 9945 * the queue mapping to our netdev. 9946 */ 9947 if (netif_is_multiqueue(vdev)) 9948 return ERR_PTR(-ERANGE); 9949 9950 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9951 if (pool == adapter->num_rx_pools) { 9952 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 9953 u16 reserved_pools; 9954 9955 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9956 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 9957 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 9958 return ERR_PTR(-EBUSY); 9959 9960 /* Hardware has a limited number of available pools. Each VF, 9961 * and the PF require a pool. Check to ensure we don't 9962 * attempt to use more then the available number of pools. 9963 */ 9964 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9965 return ERR_PTR(-EBUSY); 9966 9967 /* Enable VMDq flag so device will be set in VM mode */ 9968 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 9969 IXGBE_FLAG_SRIOV_ENABLED; 9970 9971 /* Try to reserve as many queues per pool as possible, 9972 * we start with the configurations that support 4 queues 9973 * per pools, followed by 2, and then by just 1 per pool. 9974 */ 9975 if (used_pools < 32 && adapter->num_rx_pools < 16) 9976 reserved_pools = min_t(u16, 9977 32 - used_pools, 9978 16 - adapter->num_rx_pools); 9979 else if (adapter->num_rx_pools < 32) 9980 reserved_pools = min_t(u16, 9981 64 - used_pools, 9982 32 - adapter->num_rx_pools); 9983 else 9984 reserved_pools = 64 - used_pools; 9985 9986 9987 if (!reserved_pools) 9988 return ERR_PTR(-EBUSY); 9989 9990 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 9991 9992 /* Force reinit of ring allocation with VMDQ enabled */ 9993 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 9994 if (err) 9995 return ERR_PTR(err); 9996 9997 if (pool >= adapter->num_rx_pools) 9998 return ERR_PTR(-ENOMEM); 9999 } 10000 10001 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10002 if (!accel) 10003 return ERR_PTR(-ENOMEM); 10004 10005 set_bit(pool, adapter->fwd_bitmask); 10006 netdev_set_sb_channel(vdev, pool); 10007 accel->pool = pool; 10008 accel->netdev = vdev; 10009 10010 if (!netif_running(pdev)) 10011 return accel; 10012 10013 err = ixgbe_fwd_ring_up(adapter, accel); 10014 if (err) 10015 return ERR_PTR(err); 10016 10017 return accel; 10018 } 10019 10020 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10021 { 10022 struct ixgbe_fwd_adapter *accel = priv; 10023 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10024 unsigned int rxbase = accel->rx_base_queue; 10025 unsigned int i; 10026 10027 /* delete unicast filter associated with offloaded interface */ 10028 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10029 VMDQ_P(accel->pool)); 10030 10031 /* Allow remaining Rx packets to get flushed out of the 10032 * Rx FIFO before we drop the netdev for the ring. 10033 */ 10034 usleep_range(10000, 20000); 10035 10036 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10037 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10038 struct ixgbe_q_vector *qv = ring->q_vector; 10039 10040 /* Make sure we aren't processing any packets and clear 10041 * netdev to shut down the ring. 10042 */ 10043 if (netif_running(adapter->netdev)) 10044 napi_synchronize(&qv->napi); 10045 ring->netdev = NULL; 10046 } 10047 10048 /* unbind the queues and drop the subordinate channel config */ 10049 netdev_unbind_sb_channel(pdev, accel->netdev); 10050 netdev_set_sb_channel(accel->netdev, 0); 10051 10052 clear_bit(accel->pool, adapter->fwd_bitmask); 10053 kfree(accel); 10054 } 10055 10056 #define IXGBE_MAX_MAC_HDR_LEN 127 10057 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10058 10059 static netdev_features_t 10060 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10061 netdev_features_t features) 10062 { 10063 unsigned int network_hdr_len, mac_hdr_len; 10064 10065 /* Make certain the headers can be described by a context descriptor */ 10066 mac_hdr_len = skb_network_header(skb) - skb->data; 10067 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10068 return features & ~(NETIF_F_HW_CSUM | 10069 NETIF_F_SCTP_CRC | 10070 NETIF_F_GSO_UDP_L4 | 10071 NETIF_F_HW_VLAN_CTAG_TX | 10072 NETIF_F_TSO | 10073 NETIF_F_TSO6); 10074 10075 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10076 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10077 return features & ~(NETIF_F_HW_CSUM | 10078 NETIF_F_SCTP_CRC | 10079 NETIF_F_GSO_UDP_L4 | 10080 NETIF_F_TSO | 10081 NETIF_F_TSO6); 10082 10083 /* We can only support IPV4 TSO in tunnels if we can mangle the 10084 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10085 * IPsec offoad sets skb->encapsulation but still can handle 10086 * the TSO, so it's the exception. 10087 */ 10088 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10089 #ifdef CONFIG_IXGBE_IPSEC 10090 if (!secpath_exists(skb)) 10091 #endif 10092 features &= ~NETIF_F_TSO; 10093 } 10094 10095 return features; 10096 } 10097 10098 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10099 { 10100 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10101 struct ixgbe_adapter *adapter = netdev_priv(dev); 10102 struct bpf_prog *old_prog; 10103 bool need_reset; 10104 10105 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10106 return -EINVAL; 10107 10108 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10109 return -EINVAL; 10110 10111 /* verify ixgbe ring attributes are sufficient for XDP */ 10112 for (i = 0; i < adapter->num_rx_queues; i++) { 10113 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10114 10115 if (ring_is_rsc_enabled(ring)) 10116 return -EINVAL; 10117 10118 if (frame_size > ixgbe_rx_bufsz(ring)) 10119 return -EINVAL; 10120 } 10121 10122 if (nr_cpu_ids > MAX_XDP_QUEUES) 10123 return -ENOMEM; 10124 10125 old_prog = xchg(&adapter->xdp_prog, prog); 10126 need_reset = (!!prog != !!old_prog); 10127 10128 /* If transitioning XDP modes reconfigure rings */ 10129 if (need_reset) { 10130 int err; 10131 10132 if (!prog) 10133 /* Wait until ndo_xsk_wakeup completes. */ 10134 synchronize_rcu(); 10135 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10136 10137 if (err) { 10138 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10139 return -EINVAL; 10140 } 10141 } else { 10142 for (i = 0; i < adapter->num_rx_queues; i++) 10143 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 10144 adapter->xdp_prog); 10145 } 10146 10147 if (old_prog) 10148 bpf_prog_put(old_prog); 10149 10150 /* Kick start the NAPI context if there is an AF_XDP socket open 10151 * on that queue id. This so that receiving will start. 10152 */ 10153 if (need_reset && prog) 10154 for (i = 0; i < adapter->num_rx_queues; i++) 10155 if (adapter->xdp_ring[i]->xsk_pool) 10156 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10157 XDP_WAKEUP_RX); 10158 10159 return 0; 10160 } 10161 10162 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10163 { 10164 struct ixgbe_adapter *adapter = netdev_priv(dev); 10165 10166 switch (xdp->command) { 10167 case XDP_SETUP_PROG: 10168 return ixgbe_xdp_setup(dev, xdp->prog); 10169 case XDP_SETUP_XSK_POOL: 10170 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10171 xdp->xsk.queue_id); 10172 10173 default: 10174 return -EINVAL; 10175 } 10176 } 10177 10178 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10179 { 10180 /* Force memory writes to complete before letting h/w know there 10181 * are new descriptors to fetch. 10182 */ 10183 wmb(); 10184 writel(ring->next_to_use, ring->tail); 10185 } 10186 10187 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10188 struct xdp_frame **frames, u32 flags) 10189 { 10190 struct ixgbe_adapter *adapter = netdev_priv(dev); 10191 struct ixgbe_ring *ring; 10192 int drops = 0; 10193 int i; 10194 10195 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10196 return -ENETDOWN; 10197 10198 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10199 return -EINVAL; 10200 10201 /* During program transitions its possible adapter->xdp_prog is assigned 10202 * but ring has not been configured yet. In this case simply abort xmit. 10203 */ 10204 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10205 if (unlikely(!ring)) 10206 return -ENXIO; 10207 10208 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10209 return -ENXIO; 10210 10211 for (i = 0; i < n; i++) { 10212 struct xdp_frame *xdpf = frames[i]; 10213 int err; 10214 10215 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10216 if (err != IXGBE_XDP_TX) { 10217 xdp_return_frame_rx_napi(xdpf); 10218 drops++; 10219 } 10220 } 10221 10222 if (unlikely(flags & XDP_XMIT_FLUSH)) 10223 ixgbe_xdp_ring_update_tail(ring); 10224 10225 return n - drops; 10226 } 10227 10228 static const struct net_device_ops ixgbe_netdev_ops = { 10229 .ndo_open = ixgbe_open, 10230 .ndo_stop = ixgbe_close, 10231 .ndo_start_xmit = ixgbe_xmit_frame, 10232 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10233 .ndo_validate_addr = eth_validate_addr, 10234 .ndo_set_mac_address = ixgbe_set_mac, 10235 .ndo_change_mtu = ixgbe_change_mtu, 10236 .ndo_tx_timeout = ixgbe_tx_timeout, 10237 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10238 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10239 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10240 .ndo_do_ioctl = ixgbe_ioctl, 10241 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10242 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10243 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10244 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10245 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10246 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10247 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10248 .ndo_get_stats64 = ixgbe_get_stats64, 10249 .ndo_setup_tc = __ixgbe_setup_tc, 10250 #ifdef IXGBE_FCOE 10251 .ndo_select_queue = ixgbe_select_queue, 10252 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10253 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10254 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10255 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10256 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10257 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10258 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10259 #endif /* IXGBE_FCOE */ 10260 .ndo_set_features = ixgbe_set_features, 10261 .ndo_fix_features = ixgbe_fix_features, 10262 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10263 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10264 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10265 .ndo_dfwd_add_station = ixgbe_fwd_add, 10266 .ndo_dfwd_del_station = ixgbe_fwd_del, 10267 .ndo_features_check = ixgbe_features_check, 10268 .ndo_bpf = ixgbe_xdp, 10269 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10270 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10271 }; 10272 10273 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10274 struct ixgbe_ring *tx_ring) 10275 { 10276 unsigned long wait_delay, delay_interval; 10277 struct ixgbe_hw *hw = &adapter->hw; 10278 u8 reg_idx = tx_ring->reg_idx; 10279 int wait_loop; 10280 u32 txdctl; 10281 10282 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10283 10284 /* delay mechanism from ixgbe_disable_tx */ 10285 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10286 10287 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10288 wait_delay = delay_interval; 10289 10290 while (wait_loop--) { 10291 usleep_range(wait_delay, wait_delay + 10); 10292 wait_delay += delay_interval * 2; 10293 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10294 10295 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10296 return; 10297 } 10298 10299 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10300 } 10301 10302 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10303 struct ixgbe_ring *tx_ring) 10304 { 10305 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10306 ixgbe_disable_txr_hw(adapter, tx_ring); 10307 } 10308 10309 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10310 struct ixgbe_ring *rx_ring) 10311 { 10312 unsigned long wait_delay, delay_interval; 10313 struct ixgbe_hw *hw = &adapter->hw; 10314 u8 reg_idx = rx_ring->reg_idx; 10315 int wait_loop; 10316 u32 rxdctl; 10317 10318 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10319 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10320 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10321 10322 /* write value back with RXDCTL.ENABLE bit cleared */ 10323 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10324 10325 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10326 if (hw->mac.type == ixgbe_mac_82598EB && 10327 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10328 return; 10329 10330 /* delay mechanism from ixgbe_disable_rx */ 10331 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10332 10333 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10334 wait_delay = delay_interval; 10335 10336 while (wait_loop--) { 10337 usleep_range(wait_delay, wait_delay + 10); 10338 wait_delay += delay_interval * 2; 10339 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10340 10341 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10342 return; 10343 } 10344 10345 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10346 } 10347 10348 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10349 { 10350 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10351 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10352 } 10353 10354 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10355 { 10356 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10357 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10358 } 10359 10360 /** 10361 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10362 * @adapter: adapter structure 10363 * @ring: ring index 10364 * 10365 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10366 * assumes that the netdev is running. 10367 **/ 10368 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10369 { 10370 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10371 10372 rx_ring = adapter->rx_ring[ring]; 10373 tx_ring = adapter->tx_ring[ring]; 10374 xdp_ring = adapter->xdp_ring[ring]; 10375 10376 ixgbe_disable_txr(adapter, tx_ring); 10377 if (xdp_ring) 10378 ixgbe_disable_txr(adapter, xdp_ring); 10379 ixgbe_disable_rxr_hw(adapter, rx_ring); 10380 10381 if (xdp_ring) 10382 synchronize_rcu(); 10383 10384 /* Rx/Tx/XDP Tx share the same napi context. */ 10385 napi_disable(&rx_ring->q_vector->napi); 10386 10387 ixgbe_clean_tx_ring(tx_ring); 10388 if (xdp_ring) 10389 ixgbe_clean_tx_ring(xdp_ring); 10390 ixgbe_clean_rx_ring(rx_ring); 10391 10392 ixgbe_reset_txr_stats(tx_ring); 10393 if (xdp_ring) 10394 ixgbe_reset_txr_stats(xdp_ring); 10395 ixgbe_reset_rxr_stats(rx_ring); 10396 } 10397 10398 /** 10399 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10400 * @adapter: adapter structure 10401 * @ring: ring index 10402 * 10403 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10404 * assumes that the netdev is running. 10405 **/ 10406 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10407 { 10408 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10409 10410 rx_ring = adapter->rx_ring[ring]; 10411 tx_ring = adapter->tx_ring[ring]; 10412 xdp_ring = adapter->xdp_ring[ring]; 10413 10414 /* Rx/Tx/XDP Tx share the same napi context. */ 10415 napi_enable(&rx_ring->q_vector->napi); 10416 10417 ixgbe_configure_tx_ring(adapter, tx_ring); 10418 if (xdp_ring) 10419 ixgbe_configure_tx_ring(adapter, xdp_ring); 10420 ixgbe_configure_rx_ring(adapter, rx_ring); 10421 10422 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10423 if (xdp_ring) 10424 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10425 } 10426 10427 /** 10428 * ixgbe_enumerate_functions - Get the number of ports this device has 10429 * @adapter: adapter structure 10430 * 10431 * This function enumerates the phsyical functions co-located on a single slot, 10432 * in order to determine how many ports a device has. This is most useful in 10433 * determining the required GT/s of PCIe bandwidth necessary for optimal 10434 * performance. 10435 **/ 10436 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10437 { 10438 struct pci_dev *entry, *pdev = adapter->pdev; 10439 int physfns = 0; 10440 10441 /* Some cards can not use the generic count PCIe functions method, 10442 * because they are behind a parent switch, so we hardcode these with 10443 * the correct number of functions. 10444 */ 10445 if (ixgbe_pcie_from_parent(&adapter->hw)) 10446 physfns = 4; 10447 10448 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10449 /* don't count virtual functions */ 10450 if (entry->is_virtfn) 10451 continue; 10452 10453 /* When the devices on the bus don't all match our device ID, 10454 * we can't reliably determine the correct number of 10455 * functions. This can occur if a function has been direct 10456 * attached to a virtual machine using VT-d, for example. In 10457 * this case, simply return -1 to indicate this. 10458 */ 10459 if ((entry->vendor != pdev->vendor) || 10460 (entry->device != pdev->device)) 10461 return -1; 10462 10463 physfns++; 10464 } 10465 10466 return physfns; 10467 } 10468 10469 /** 10470 * ixgbe_wol_supported - Check whether device supports WoL 10471 * @adapter: the adapter private structure 10472 * @device_id: the device ID 10473 * @subdevice_id: the subsystem device ID 10474 * 10475 * This function is used by probe and ethtool to determine 10476 * which devices have WoL support 10477 * 10478 **/ 10479 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10480 u16 subdevice_id) 10481 { 10482 struct ixgbe_hw *hw = &adapter->hw; 10483 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10484 10485 /* WOL not supported on 82598 */ 10486 if (hw->mac.type == ixgbe_mac_82598EB) 10487 return false; 10488 10489 /* check eeprom to see if WOL is enabled for X540 and newer */ 10490 if (hw->mac.type >= ixgbe_mac_X540) { 10491 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10492 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10493 (hw->bus.func == 0))) 10494 return true; 10495 } 10496 10497 /* WOL is determined based on device IDs for 82599 MACs */ 10498 switch (device_id) { 10499 case IXGBE_DEV_ID_82599_SFP: 10500 /* Only these subdevices could supports WOL */ 10501 switch (subdevice_id) { 10502 case IXGBE_SUBDEV_ID_82599_560FLR: 10503 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10504 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10505 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10506 /* only support first port */ 10507 if (hw->bus.func != 0) 10508 break; 10509 fallthrough; 10510 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10511 case IXGBE_SUBDEV_ID_82599_SFP: 10512 case IXGBE_SUBDEV_ID_82599_RNDC: 10513 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10514 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10515 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10516 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10517 return true; 10518 } 10519 break; 10520 case IXGBE_DEV_ID_82599EN_SFP: 10521 /* Only these subdevices support WOL */ 10522 switch (subdevice_id) { 10523 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10524 return true; 10525 } 10526 break; 10527 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10528 /* All except this subdevice support WOL */ 10529 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10530 return true; 10531 break; 10532 case IXGBE_DEV_ID_82599_KX4: 10533 return true; 10534 default: 10535 break; 10536 } 10537 10538 return false; 10539 } 10540 10541 /** 10542 * ixgbe_set_fw_version - Set FW version 10543 * @adapter: the adapter private structure 10544 * 10545 * This function is used by probe and ethtool to determine the FW version to 10546 * format to display. The FW version is taken from the EEPROM/NVM. 10547 */ 10548 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10549 { 10550 struct ixgbe_hw *hw = &adapter->hw; 10551 struct ixgbe_nvm_version nvm_ver; 10552 10553 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10554 if (nvm_ver.oem_valid) { 10555 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10556 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10557 nvm_ver.oem_release); 10558 return; 10559 } 10560 10561 ixgbe_get_etk_id(hw, &nvm_ver); 10562 ixgbe_get_orom_version(hw, &nvm_ver); 10563 10564 if (nvm_ver.or_valid) { 10565 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10566 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10567 nvm_ver.or_build, nvm_ver.or_patch); 10568 return; 10569 } 10570 10571 /* Set ETrack ID format */ 10572 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10573 "0x%08x", nvm_ver.etk_id); 10574 } 10575 10576 /** 10577 * ixgbe_probe - Device Initialization Routine 10578 * @pdev: PCI device information struct 10579 * @ent: entry in ixgbe_pci_tbl 10580 * 10581 * Returns 0 on success, negative on failure 10582 * 10583 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10584 * The OS initialization, configuring of the adapter private structure, 10585 * and a hardware reset occur. 10586 **/ 10587 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10588 { 10589 struct net_device *netdev; 10590 struct ixgbe_adapter *adapter = NULL; 10591 struct ixgbe_hw *hw; 10592 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10593 int i, err, pci_using_dac, expected_gts; 10594 unsigned int indices = MAX_TX_QUEUES; 10595 u8 part_str[IXGBE_PBANUM_LENGTH]; 10596 bool disable_dev = false; 10597 #ifdef IXGBE_FCOE 10598 u16 device_caps; 10599 #endif 10600 u32 eec; 10601 10602 /* Catch broken hardware that put the wrong VF device ID in 10603 * the PCIe SR-IOV capability. 10604 */ 10605 if (pdev->is_virtfn) { 10606 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10607 pci_name(pdev), pdev->vendor, pdev->device); 10608 return -EINVAL; 10609 } 10610 10611 err = pci_enable_device_mem(pdev); 10612 if (err) 10613 return err; 10614 10615 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10616 pci_using_dac = 1; 10617 } else { 10618 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10619 if (err) { 10620 dev_err(&pdev->dev, 10621 "No usable DMA configuration, aborting\n"); 10622 goto err_dma; 10623 } 10624 pci_using_dac = 0; 10625 } 10626 10627 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10628 if (err) { 10629 dev_err(&pdev->dev, 10630 "pci_request_selected_regions failed 0x%x\n", err); 10631 goto err_pci_reg; 10632 } 10633 10634 pci_enable_pcie_error_reporting(pdev); 10635 10636 pci_set_master(pdev); 10637 pci_save_state(pdev); 10638 10639 if (ii->mac == ixgbe_mac_82598EB) { 10640 #ifdef CONFIG_IXGBE_DCB 10641 /* 8 TC w/ 4 queues per TC */ 10642 indices = 4 * MAX_TRAFFIC_CLASS; 10643 #else 10644 indices = IXGBE_MAX_RSS_INDICES; 10645 #endif 10646 } 10647 10648 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10649 if (!netdev) { 10650 err = -ENOMEM; 10651 goto err_alloc_etherdev; 10652 } 10653 10654 SET_NETDEV_DEV(netdev, &pdev->dev); 10655 10656 adapter = netdev_priv(netdev); 10657 10658 adapter->netdev = netdev; 10659 adapter->pdev = pdev; 10660 hw = &adapter->hw; 10661 hw->back = adapter; 10662 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10663 10664 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10665 pci_resource_len(pdev, 0)); 10666 adapter->io_addr = hw->hw_addr; 10667 if (!hw->hw_addr) { 10668 err = -EIO; 10669 goto err_ioremap; 10670 } 10671 10672 netdev->netdev_ops = &ixgbe_netdev_ops; 10673 ixgbe_set_ethtool_ops(netdev); 10674 netdev->watchdog_timeo = 5 * HZ; 10675 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10676 10677 /* Setup hw api */ 10678 hw->mac.ops = *ii->mac_ops; 10679 hw->mac.type = ii->mac; 10680 hw->mvals = ii->mvals; 10681 if (ii->link_ops) 10682 hw->link.ops = *ii->link_ops; 10683 10684 /* EEPROM */ 10685 hw->eeprom.ops = *ii->eeprom_ops; 10686 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10687 if (ixgbe_removed(hw->hw_addr)) { 10688 err = -EIO; 10689 goto err_ioremap; 10690 } 10691 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10692 if (!(eec & BIT(8))) 10693 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10694 10695 /* PHY */ 10696 hw->phy.ops = *ii->phy_ops; 10697 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10698 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10699 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10700 hw->phy.mdio.mmds = 0; 10701 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10702 hw->phy.mdio.dev = netdev; 10703 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10704 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10705 10706 /* setup the private structure */ 10707 err = ixgbe_sw_init(adapter, ii); 10708 if (err) 10709 goto err_sw_init; 10710 10711 switch (adapter->hw.mac.type) { 10712 case ixgbe_mac_X550: 10713 case ixgbe_mac_X550EM_x: 10714 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 10715 break; 10716 case ixgbe_mac_x550em_a: 10717 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 10718 break; 10719 default: 10720 break; 10721 } 10722 10723 /* Make sure the SWFW semaphore is in a valid state */ 10724 if (hw->mac.ops.init_swfw_sync) 10725 hw->mac.ops.init_swfw_sync(hw); 10726 10727 /* Make it possible the adapter to be woken up via WOL */ 10728 switch (adapter->hw.mac.type) { 10729 case ixgbe_mac_82599EB: 10730 case ixgbe_mac_X540: 10731 case ixgbe_mac_X550: 10732 case ixgbe_mac_X550EM_x: 10733 case ixgbe_mac_x550em_a: 10734 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10735 break; 10736 default: 10737 break; 10738 } 10739 10740 /* 10741 * If there is a fan on this device and it has failed log the 10742 * failure. 10743 */ 10744 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10745 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10746 if (esdp & IXGBE_ESDP_SDP1) 10747 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10748 } 10749 10750 if (allow_unsupported_sfp) 10751 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10752 10753 /* reset_hw fills in the perm_addr as well */ 10754 hw->phy.reset_if_overtemp = true; 10755 err = hw->mac.ops.reset_hw(hw); 10756 hw->phy.reset_if_overtemp = false; 10757 ixgbe_set_eee_capable(adapter); 10758 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10759 err = 0; 10760 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10761 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10762 e_dev_err("Reload the driver after installing a supported module.\n"); 10763 goto err_sw_init; 10764 } else if (err) { 10765 e_dev_err("HW Init failed: %d\n", err); 10766 goto err_sw_init; 10767 } 10768 10769 #ifdef CONFIG_PCI_IOV 10770 /* SR-IOV not supported on the 82598 */ 10771 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10772 goto skip_sriov; 10773 /* Mailbox */ 10774 ixgbe_init_mbx_params_pf(hw); 10775 hw->mbx.ops = ii->mbx_ops; 10776 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10777 ixgbe_enable_sriov(adapter, max_vfs); 10778 skip_sriov: 10779 10780 #endif 10781 netdev->features = NETIF_F_SG | 10782 NETIF_F_TSO | 10783 NETIF_F_TSO6 | 10784 NETIF_F_RXHASH | 10785 NETIF_F_RXCSUM | 10786 NETIF_F_HW_CSUM; 10787 10788 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10789 NETIF_F_GSO_GRE_CSUM | \ 10790 NETIF_F_GSO_IPXIP4 | \ 10791 NETIF_F_GSO_IPXIP6 | \ 10792 NETIF_F_GSO_UDP_TUNNEL | \ 10793 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10794 10795 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10796 netdev->features |= NETIF_F_GSO_PARTIAL | 10797 IXGBE_GSO_PARTIAL_FEATURES; 10798 10799 if (hw->mac.type >= ixgbe_mac_82599EB) 10800 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 10801 10802 #ifdef CONFIG_IXGBE_IPSEC 10803 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10804 NETIF_F_HW_ESP_TX_CSUM | \ 10805 NETIF_F_GSO_ESP) 10806 10807 if (adapter->ipsec) 10808 netdev->features |= IXGBE_ESP_FEATURES; 10809 #endif 10810 /* copy netdev features into list of user selectable features */ 10811 netdev->hw_features |= netdev->features | 10812 NETIF_F_HW_VLAN_CTAG_FILTER | 10813 NETIF_F_HW_VLAN_CTAG_RX | 10814 NETIF_F_HW_VLAN_CTAG_TX | 10815 NETIF_F_RXALL | 10816 NETIF_F_HW_L2FW_DOFFLOAD; 10817 10818 if (hw->mac.type >= ixgbe_mac_82599EB) 10819 netdev->hw_features |= NETIF_F_NTUPLE | 10820 NETIF_F_HW_TC; 10821 10822 if (pci_using_dac) 10823 netdev->features |= NETIF_F_HIGHDMA; 10824 10825 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10826 netdev->hw_enc_features |= netdev->vlan_features; 10827 netdev->mpls_features |= NETIF_F_SG | 10828 NETIF_F_TSO | 10829 NETIF_F_TSO6 | 10830 NETIF_F_HW_CSUM; 10831 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10832 10833 /* set this bit last since it cannot be part of vlan_features */ 10834 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10835 NETIF_F_HW_VLAN_CTAG_RX | 10836 NETIF_F_HW_VLAN_CTAG_TX; 10837 10838 netdev->priv_flags |= IFF_UNICAST_FLT; 10839 netdev->priv_flags |= IFF_SUPP_NOFCS; 10840 10841 /* MTU range: 68 - 9710 */ 10842 netdev->min_mtu = ETH_MIN_MTU; 10843 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10844 10845 #ifdef CONFIG_IXGBE_DCB 10846 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10847 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10848 #endif 10849 10850 #ifdef IXGBE_FCOE 10851 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10852 unsigned int fcoe_l; 10853 10854 if (hw->mac.ops.get_device_caps) { 10855 hw->mac.ops.get_device_caps(hw, &device_caps); 10856 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10857 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10858 } 10859 10860 10861 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10862 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10863 10864 netdev->features |= NETIF_F_FSO | 10865 NETIF_F_FCOE_CRC; 10866 10867 netdev->vlan_features |= NETIF_F_FSO | 10868 NETIF_F_FCOE_CRC | 10869 NETIF_F_FCOE_MTU; 10870 } 10871 #endif /* IXGBE_FCOE */ 10872 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10873 netdev->hw_features |= NETIF_F_LRO; 10874 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10875 netdev->features |= NETIF_F_LRO; 10876 10877 if (ixgbe_check_fw_error(adapter)) { 10878 err = -EIO; 10879 goto err_sw_init; 10880 } 10881 10882 /* make sure the EEPROM is good */ 10883 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10884 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10885 err = -EIO; 10886 goto err_sw_init; 10887 } 10888 10889 eth_platform_get_mac_address(&adapter->pdev->dev, 10890 adapter->hw.mac.perm_addr); 10891 10892 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10893 10894 if (!is_valid_ether_addr(netdev->dev_addr)) { 10895 e_dev_err("invalid MAC address\n"); 10896 err = -EIO; 10897 goto err_sw_init; 10898 } 10899 10900 /* Set hw->mac.addr to permanent MAC address */ 10901 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10902 ixgbe_mac_set_default_filter(adapter); 10903 10904 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10905 10906 if (ixgbe_removed(hw->hw_addr)) { 10907 err = -EIO; 10908 goto err_sw_init; 10909 } 10910 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10911 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10912 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10913 10914 err = ixgbe_init_interrupt_scheme(adapter); 10915 if (err) 10916 goto err_sw_init; 10917 10918 for (i = 0; i < adapter->num_rx_queues; i++) 10919 u64_stats_init(&adapter->rx_ring[i]->syncp); 10920 for (i = 0; i < adapter->num_tx_queues; i++) 10921 u64_stats_init(&adapter->tx_ring[i]->syncp); 10922 for (i = 0; i < adapter->num_xdp_queues; i++) 10923 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10924 10925 /* WOL not supported for all devices */ 10926 adapter->wol = 0; 10927 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10928 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10929 pdev->subsystem_device); 10930 if (hw->wol_enabled) 10931 adapter->wol = IXGBE_WUFC_MAG; 10932 10933 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10934 10935 /* save off EEPROM version number */ 10936 ixgbe_set_fw_version(adapter); 10937 10938 /* pick up the PCI bus settings for reporting later */ 10939 if (ixgbe_pcie_from_parent(hw)) 10940 ixgbe_get_parent_bus_info(adapter); 10941 else 10942 hw->mac.ops.get_bus_info(hw); 10943 10944 /* calculate the expected PCIe bandwidth required for optimal 10945 * performance. Note that some older parts will never have enough 10946 * bandwidth due to being older generation PCIe parts. We clamp these 10947 * parts to ensure no warning is displayed if it can't be fixed. 10948 */ 10949 switch (hw->mac.type) { 10950 case ixgbe_mac_82598EB: 10951 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10952 break; 10953 default: 10954 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10955 break; 10956 } 10957 10958 /* don't check link if we failed to enumerate functions */ 10959 if (expected_gts > 0) 10960 ixgbe_check_minimum_link(adapter, expected_gts); 10961 10962 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10963 if (err) 10964 strlcpy(part_str, "Unknown", sizeof(part_str)); 10965 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10966 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10967 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10968 part_str); 10969 else 10970 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10971 hw->mac.type, hw->phy.type, part_str); 10972 10973 e_dev_info("%pM\n", netdev->dev_addr); 10974 10975 /* reset the hardware with the new settings */ 10976 err = hw->mac.ops.start_hw(hw); 10977 if (err == IXGBE_ERR_EEPROM_VERSION) { 10978 /* We are running on a pre-production device, log a warning */ 10979 e_dev_warn("This device is a pre-production adapter/LOM. " 10980 "Please be aware there may be issues associated " 10981 "with your hardware. If you are experiencing " 10982 "problems please contact your Intel or hardware " 10983 "representative who provided you with this " 10984 "hardware.\n"); 10985 } 10986 strcpy(netdev->name, "eth%d"); 10987 pci_set_drvdata(pdev, adapter); 10988 err = register_netdev(netdev); 10989 if (err) 10990 goto err_register; 10991 10992 10993 /* power down the optics for 82599 SFP+ fiber */ 10994 if (hw->mac.ops.disable_tx_laser) 10995 hw->mac.ops.disable_tx_laser(hw); 10996 10997 /* carrier off reporting is important to ethtool even BEFORE open */ 10998 netif_carrier_off(netdev); 10999 11000 #ifdef CONFIG_IXGBE_DCA 11001 if (dca_add_requester(&pdev->dev) == 0) { 11002 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11003 ixgbe_setup_dca(adapter); 11004 } 11005 #endif 11006 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11007 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11008 for (i = 0; i < adapter->num_vfs; i++) 11009 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11010 } 11011 11012 /* firmware requires driver version to be 0xFFFFFFFF 11013 * since os does not support feature 11014 */ 11015 if (hw->mac.ops.set_fw_drv_ver) 11016 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11017 sizeof(UTS_RELEASE) - 1, 11018 UTS_RELEASE); 11019 11020 /* add san mac addr to netdev */ 11021 ixgbe_add_sanmac_netdev(netdev); 11022 11023 e_dev_info("%s\n", ixgbe_default_device_descr); 11024 11025 #ifdef CONFIG_IXGBE_HWMON 11026 if (ixgbe_sysfs_init(adapter)) 11027 e_err(probe, "failed to allocate sysfs resources\n"); 11028 #endif /* CONFIG_IXGBE_HWMON */ 11029 11030 ixgbe_dbg_adapter_init(adapter); 11031 11032 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11033 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11034 hw->mac.ops.setup_link(hw, 11035 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11036 true); 11037 11038 err = ixgbe_mii_bus_init(hw); 11039 if (err) 11040 goto err_netdev; 11041 11042 return 0; 11043 11044 err_netdev: 11045 unregister_netdev(netdev); 11046 err_register: 11047 ixgbe_release_hw_control(adapter); 11048 ixgbe_clear_interrupt_scheme(adapter); 11049 err_sw_init: 11050 ixgbe_disable_sriov(adapter); 11051 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11052 iounmap(adapter->io_addr); 11053 kfree(adapter->jump_tables[0]); 11054 kfree(adapter->mac_table); 11055 kfree(adapter->rss_key); 11056 bitmap_free(adapter->af_xdp_zc_qps); 11057 err_ioremap: 11058 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11059 free_netdev(netdev); 11060 err_alloc_etherdev: 11061 pci_release_mem_regions(pdev); 11062 err_pci_reg: 11063 err_dma: 11064 if (!adapter || disable_dev) 11065 pci_disable_device(pdev); 11066 return err; 11067 } 11068 11069 /** 11070 * ixgbe_remove - Device Removal Routine 11071 * @pdev: PCI device information struct 11072 * 11073 * ixgbe_remove is called by the PCI subsystem to alert the driver 11074 * that it should release a PCI device. The could be caused by a 11075 * Hot-Plug event, or because the driver is going to be removed from 11076 * memory. 11077 **/ 11078 static void ixgbe_remove(struct pci_dev *pdev) 11079 { 11080 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11081 struct net_device *netdev; 11082 bool disable_dev; 11083 int i; 11084 11085 /* if !adapter then we already cleaned up in probe */ 11086 if (!adapter) 11087 return; 11088 11089 netdev = adapter->netdev; 11090 ixgbe_dbg_adapter_exit(adapter); 11091 11092 set_bit(__IXGBE_REMOVING, &adapter->state); 11093 cancel_work_sync(&adapter->service_task); 11094 11095 if (adapter->mii_bus) 11096 mdiobus_unregister(adapter->mii_bus); 11097 11098 #ifdef CONFIG_IXGBE_DCA 11099 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11100 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11101 dca_remove_requester(&pdev->dev); 11102 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11103 IXGBE_DCA_CTRL_DCA_DISABLE); 11104 } 11105 11106 #endif 11107 #ifdef CONFIG_IXGBE_HWMON 11108 ixgbe_sysfs_exit(adapter); 11109 #endif /* CONFIG_IXGBE_HWMON */ 11110 11111 /* remove the added san mac */ 11112 ixgbe_del_sanmac_netdev(netdev); 11113 11114 #ifdef CONFIG_PCI_IOV 11115 ixgbe_disable_sriov(adapter); 11116 #endif 11117 if (netdev->reg_state == NETREG_REGISTERED) 11118 unregister_netdev(netdev); 11119 11120 ixgbe_stop_ipsec_offload(adapter); 11121 ixgbe_clear_interrupt_scheme(adapter); 11122 11123 ixgbe_release_hw_control(adapter); 11124 11125 #ifdef CONFIG_DCB 11126 kfree(adapter->ixgbe_ieee_pfc); 11127 kfree(adapter->ixgbe_ieee_ets); 11128 11129 #endif 11130 iounmap(adapter->io_addr); 11131 pci_release_mem_regions(pdev); 11132 11133 e_dev_info("complete\n"); 11134 11135 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11136 if (adapter->jump_tables[i]) { 11137 kfree(adapter->jump_tables[i]->input); 11138 kfree(adapter->jump_tables[i]->mask); 11139 } 11140 kfree(adapter->jump_tables[i]); 11141 } 11142 11143 kfree(adapter->mac_table); 11144 kfree(adapter->rss_key); 11145 bitmap_free(adapter->af_xdp_zc_qps); 11146 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11147 free_netdev(netdev); 11148 11149 pci_disable_pcie_error_reporting(pdev); 11150 11151 if (disable_dev) 11152 pci_disable_device(pdev); 11153 } 11154 11155 /** 11156 * ixgbe_io_error_detected - called when PCI error is detected 11157 * @pdev: Pointer to PCI device 11158 * @state: The current pci connection state 11159 * 11160 * This function is called after a PCI bus error affecting 11161 * this device has been detected. 11162 */ 11163 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11164 pci_channel_state_t state) 11165 { 11166 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11167 struct net_device *netdev = adapter->netdev; 11168 11169 #ifdef CONFIG_PCI_IOV 11170 struct ixgbe_hw *hw = &adapter->hw; 11171 struct pci_dev *bdev, *vfdev; 11172 u32 dw0, dw1, dw2, dw3; 11173 int vf, pos; 11174 u16 req_id, pf_func; 11175 11176 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11177 adapter->num_vfs == 0) 11178 goto skip_bad_vf_detection; 11179 11180 bdev = pdev->bus->self; 11181 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11182 bdev = bdev->bus->self; 11183 11184 if (!bdev) 11185 goto skip_bad_vf_detection; 11186 11187 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11188 if (!pos) 11189 goto skip_bad_vf_detection; 11190 11191 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11192 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11193 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11194 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11195 if (ixgbe_removed(hw->hw_addr)) 11196 goto skip_bad_vf_detection; 11197 11198 req_id = dw1 >> 16; 11199 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11200 if (!(req_id & 0x0080)) 11201 goto skip_bad_vf_detection; 11202 11203 pf_func = req_id & 0x01; 11204 if ((pf_func & 1) == (pdev->devfn & 1)) { 11205 unsigned int device_id; 11206 11207 vf = (req_id & 0x7F) >> 1; 11208 e_dev_err("VF %d has caused a PCIe error\n", vf); 11209 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11210 "%8.8x\tdw3: %8.8x\n", 11211 dw0, dw1, dw2, dw3); 11212 switch (adapter->hw.mac.type) { 11213 case ixgbe_mac_82599EB: 11214 device_id = IXGBE_82599_VF_DEVICE_ID; 11215 break; 11216 case ixgbe_mac_X540: 11217 device_id = IXGBE_X540_VF_DEVICE_ID; 11218 break; 11219 case ixgbe_mac_X550: 11220 device_id = IXGBE_DEV_ID_X550_VF; 11221 break; 11222 case ixgbe_mac_X550EM_x: 11223 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11224 break; 11225 case ixgbe_mac_x550em_a: 11226 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11227 break; 11228 default: 11229 device_id = 0; 11230 break; 11231 } 11232 11233 /* Find the pci device of the offending VF */ 11234 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11235 while (vfdev) { 11236 if (vfdev->devfn == (req_id & 0xFF)) 11237 break; 11238 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11239 device_id, vfdev); 11240 } 11241 /* 11242 * There's a slim chance the VF could have been hot plugged, 11243 * so if it is no longer present we don't need to issue the 11244 * VFLR. Just clean up the AER in that case. 11245 */ 11246 if (vfdev) { 11247 pcie_flr(vfdev); 11248 /* Free device reference count */ 11249 pci_dev_put(vfdev); 11250 } 11251 } 11252 11253 /* 11254 * Even though the error may have occurred on the other port 11255 * we still need to increment the vf error reference count for 11256 * both ports because the I/O resume function will be called 11257 * for both of them. 11258 */ 11259 adapter->vferr_refcount++; 11260 11261 return PCI_ERS_RESULT_RECOVERED; 11262 11263 skip_bad_vf_detection: 11264 #endif /* CONFIG_PCI_IOV */ 11265 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11266 return PCI_ERS_RESULT_DISCONNECT; 11267 11268 if (!netif_device_present(netdev)) 11269 return PCI_ERS_RESULT_DISCONNECT; 11270 11271 rtnl_lock(); 11272 netif_device_detach(netdev); 11273 11274 if (netif_running(netdev)) 11275 ixgbe_close_suspend(adapter); 11276 11277 if (state == pci_channel_io_perm_failure) { 11278 rtnl_unlock(); 11279 return PCI_ERS_RESULT_DISCONNECT; 11280 } 11281 11282 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11283 pci_disable_device(pdev); 11284 rtnl_unlock(); 11285 11286 /* Request a slot reset. */ 11287 return PCI_ERS_RESULT_NEED_RESET; 11288 } 11289 11290 /** 11291 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11292 * @pdev: Pointer to PCI device 11293 * 11294 * Restart the card from scratch, as if from a cold-boot. 11295 */ 11296 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11297 { 11298 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11299 pci_ers_result_t result; 11300 11301 if (pci_enable_device_mem(pdev)) { 11302 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11303 result = PCI_ERS_RESULT_DISCONNECT; 11304 } else { 11305 smp_mb__before_atomic(); 11306 clear_bit(__IXGBE_DISABLED, &adapter->state); 11307 adapter->hw.hw_addr = adapter->io_addr; 11308 pci_set_master(pdev); 11309 pci_restore_state(pdev); 11310 pci_save_state(pdev); 11311 11312 pci_wake_from_d3(pdev, false); 11313 11314 ixgbe_reset(adapter); 11315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11316 result = PCI_ERS_RESULT_RECOVERED; 11317 } 11318 11319 return result; 11320 } 11321 11322 /** 11323 * ixgbe_io_resume - called when traffic can start flowing again. 11324 * @pdev: Pointer to PCI device 11325 * 11326 * This callback is called when the error recovery driver tells us that 11327 * its OK to resume normal operation. 11328 */ 11329 static void ixgbe_io_resume(struct pci_dev *pdev) 11330 { 11331 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11332 struct net_device *netdev = adapter->netdev; 11333 11334 #ifdef CONFIG_PCI_IOV 11335 if (adapter->vferr_refcount) { 11336 e_info(drv, "Resuming after VF err\n"); 11337 adapter->vferr_refcount--; 11338 return; 11339 } 11340 11341 #endif 11342 rtnl_lock(); 11343 if (netif_running(netdev)) 11344 ixgbe_open(netdev); 11345 11346 netif_device_attach(netdev); 11347 rtnl_unlock(); 11348 } 11349 11350 static const struct pci_error_handlers ixgbe_err_handler = { 11351 .error_detected = ixgbe_io_error_detected, 11352 .slot_reset = ixgbe_io_slot_reset, 11353 .resume = ixgbe_io_resume, 11354 }; 11355 11356 static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11357 11358 static struct pci_driver ixgbe_driver = { 11359 .name = ixgbe_driver_name, 11360 .id_table = ixgbe_pci_tbl, 11361 .probe = ixgbe_probe, 11362 .remove = ixgbe_remove, 11363 .driver.pm = &ixgbe_pm_ops, 11364 .shutdown = ixgbe_shutdown, 11365 .sriov_configure = ixgbe_pci_sriov_configure, 11366 .err_handler = &ixgbe_err_handler 11367 }; 11368 11369 /** 11370 * ixgbe_init_module - Driver Registration Routine 11371 * 11372 * ixgbe_init_module is the first routine called when the driver is 11373 * loaded. All it does is register with the PCI subsystem. 11374 **/ 11375 static int __init ixgbe_init_module(void) 11376 { 11377 int ret; 11378 pr_info("%s\n", ixgbe_driver_string); 11379 pr_info("%s\n", ixgbe_copyright); 11380 11381 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11382 if (!ixgbe_wq) { 11383 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11384 return -ENOMEM; 11385 } 11386 11387 ixgbe_dbg_init(); 11388 11389 ret = pci_register_driver(&ixgbe_driver); 11390 if (ret) { 11391 destroy_workqueue(ixgbe_wq); 11392 ixgbe_dbg_exit(); 11393 return ret; 11394 } 11395 11396 #ifdef CONFIG_IXGBE_DCA 11397 dca_register_notify(&dca_notifier); 11398 #endif 11399 11400 return 0; 11401 } 11402 11403 module_init(ixgbe_init_module); 11404 11405 /** 11406 * ixgbe_exit_module - Driver Exit Cleanup Routine 11407 * 11408 * ixgbe_exit_module is called just before the driver is removed 11409 * from memory. 11410 **/ 11411 static void __exit ixgbe_exit_module(void) 11412 { 11413 #ifdef CONFIG_IXGBE_DCA 11414 dca_unregister_notify(&dca_notifier); 11415 #endif 11416 pci_unregister_driver(&ixgbe_driver); 11417 11418 ixgbe_dbg_exit(); 11419 if (ixgbe_wq) { 11420 destroy_workqueue(ixgbe_wq); 11421 ixgbe_wq = NULL; 11422 } 11423 } 11424 11425 #ifdef CONFIG_IXGBE_DCA 11426 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11427 void *p) 11428 { 11429 int ret_val; 11430 11431 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11432 __ixgbe_notify_dca); 11433 11434 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11435 } 11436 11437 #endif /* CONFIG_IXGBE_DCA */ 11438 11439 module_exit(ixgbe_exit_module); 11440 11441 /* ixgbe_main.c */ 11442