1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <generated/utsrelease.h> 32 #include <scsi/fc/fc_fcoe.h> 33 #include <net/udp_tunnel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include <net/vxlan.h> 38 #include <net/mpls.h> 39 #include <net/xdp_sock_drv.h> 40 #include <net/xfrm.h> 41 42 #include "ixgbe.h" 43 #include "ixgbe_common.h" 44 #include "ixgbe_dcb_82599.h" 45 #include "ixgbe_phy.h" 46 #include "ixgbe_sriov.h" 47 #include "ixgbe_model.h" 48 #include "ixgbe_txrx_common.h" 49 50 char ixgbe_driver_name[] = "ixgbe"; 51 static const char ixgbe_driver_string[] = 52 "Intel(R) 10 Gigabit PCI Express Network Driver"; 53 #ifdef IXGBE_FCOE 54 char ixgbe_default_device_descr[] = 55 "Intel(R) 10 Gigabit Network Connection"; 56 #else 57 static char ixgbe_default_device_descr[] = 58 "Intel(R) 10 Gigabit Network Connection"; 59 #endif 60 static const char ixgbe_copyright[] = 61 "Copyright (c) 1999-2016 Intel Corporation."; 62 63 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 64 65 static const struct ixgbe_info *ixgbe_info_tbl[] = { 66 [board_82598] = &ixgbe_82598_info, 67 [board_82599] = &ixgbe_82599_info, 68 [board_X540] = &ixgbe_X540_info, 69 [board_X550] = &ixgbe_X550_info, 70 [board_X550EM_x] = &ixgbe_X550EM_x_info, 71 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 72 [board_x550em_a] = &ixgbe_x550em_a_info, 73 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 74 }; 75 76 /* ixgbe_pci_tbl - PCI Device ID Table 77 * 78 * Wildcard entries (PCI_ANY_ID) should come last 79 * Last entry must be all 0s 80 * 81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 82 * Class, Class Mask, private data (not used) } 83 */ 84 static const struct pci_device_id ixgbe_pci_tbl[] = { 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 132 /* required last entry */ 133 {0, } 134 }; 135 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 136 137 #ifdef CONFIG_IXGBE_DCA 138 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 139 void *p); 140 static struct notifier_block dca_notifier = { 141 .notifier_call = ixgbe_notify_dca, 142 .next = NULL, 143 .priority = 0 144 }; 145 #endif 146 147 #ifdef CONFIG_PCI_IOV 148 static unsigned int max_vfs; 149 module_param(max_vfs, uint, 0); 150 MODULE_PARM_DESC(max_vfs, 151 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 152 #endif /* CONFIG_PCI_IOV */ 153 154 static unsigned int allow_unsupported_sfp; 155 module_param(allow_unsupported_sfp, uint, 0); 156 MODULE_PARM_DESC(allow_unsupported_sfp, 157 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 158 159 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 160 static int debug = -1; 161 module_param(debug, int, 0); 162 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 163 164 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 165 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 166 MODULE_LICENSE("GPL v2"); 167 168 static struct workqueue_struct *ixgbe_wq; 169 170 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 171 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 172 173 static const struct net_device_ops ixgbe_netdev_ops; 174 175 static bool netif_is_ixgbe(struct net_device *dev) 176 { 177 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 178 } 179 180 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 181 u32 reg, u16 *value) 182 { 183 struct pci_dev *parent_dev; 184 struct pci_bus *parent_bus; 185 186 parent_bus = adapter->pdev->bus->parent; 187 if (!parent_bus) 188 return -1; 189 190 parent_dev = parent_bus->self; 191 if (!parent_dev) 192 return -1; 193 194 if (!pci_is_pcie(parent_dev)) 195 return -1; 196 197 pcie_capability_read_word(parent_dev, reg, value); 198 if (*value == IXGBE_FAILED_READ_CFG_WORD && 199 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 200 return -1; 201 return 0; 202 } 203 204 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 205 { 206 struct ixgbe_hw *hw = &adapter->hw; 207 u16 link_status = 0; 208 int err; 209 210 hw->bus.type = ixgbe_bus_type_pci_express; 211 212 /* Get the negotiated link width and speed from PCI config space of the 213 * parent, as this device is behind a switch 214 */ 215 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 216 217 /* assume caller will handle error case */ 218 if (err) 219 return err; 220 221 hw->bus.width = ixgbe_convert_bus_width(link_status); 222 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 223 224 return 0; 225 } 226 227 /** 228 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 229 * @hw: hw specific details 230 * 231 * This function is used by probe to determine whether a device's PCI-Express 232 * bandwidth details should be gathered from the parent bus instead of from the 233 * device. Used to ensure that various locations all have the correct device ID 234 * checks. 235 */ 236 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 237 { 238 switch (hw->device_id) { 239 case IXGBE_DEV_ID_82599_SFP_SF_QP: 240 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 241 return true; 242 default: 243 return false; 244 } 245 } 246 247 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 248 int expected_gts) 249 { 250 struct ixgbe_hw *hw = &adapter->hw; 251 struct pci_dev *pdev; 252 253 /* Some devices are not connected over PCIe and thus do not negotiate 254 * speed. These devices do not have valid bus info, and thus any report 255 * we generate may not be correct. 256 */ 257 if (hw->bus.type == ixgbe_bus_type_internal) 258 return; 259 260 /* determine whether to use the parent device */ 261 if (ixgbe_pcie_from_parent(&adapter->hw)) 262 pdev = adapter->pdev->bus->parent->self; 263 else 264 pdev = adapter->pdev; 265 266 pcie_print_link_status(pdev); 267 } 268 269 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 270 { 271 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 272 !test_bit(__IXGBE_REMOVING, &adapter->state) && 273 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 274 queue_work(ixgbe_wq, &adapter->service_task); 275 } 276 277 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 278 { 279 struct ixgbe_adapter *adapter = hw->back; 280 281 if (!hw->hw_addr) 282 return; 283 hw->hw_addr = NULL; 284 e_dev_err("Adapter removed\n"); 285 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 286 ixgbe_service_event_schedule(adapter); 287 } 288 289 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 290 { 291 u8 __iomem *reg_addr; 292 u32 value; 293 int i; 294 295 reg_addr = READ_ONCE(hw->hw_addr); 296 if (ixgbe_removed(reg_addr)) 297 return IXGBE_FAILED_READ_REG; 298 299 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 300 * so perform several status register reads to determine if the adapter 301 * has been removed. 302 */ 303 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 304 value = readl(reg_addr + IXGBE_STATUS); 305 if (value != IXGBE_FAILED_READ_REG) 306 break; 307 mdelay(3); 308 } 309 310 if (value == IXGBE_FAILED_READ_REG) 311 ixgbe_remove_adapter(hw); 312 else 313 value = readl(reg_addr + reg); 314 return value; 315 } 316 317 /** 318 * ixgbe_read_reg - Read from device register 319 * @hw: hw specific details 320 * @reg: offset of register to read 321 * 322 * Returns : value read or IXGBE_FAILED_READ_REG if removed 323 * 324 * This function is used to read device registers. It checks for device 325 * removal by confirming any read that returns all ones by checking the 326 * status register value for all ones. This function avoids reading from 327 * the hardware if a removal was previously detected in which case it 328 * returns IXGBE_FAILED_READ_REG (all ones). 329 */ 330 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 331 { 332 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 333 u32 value; 334 335 if (ixgbe_removed(reg_addr)) 336 return IXGBE_FAILED_READ_REG; 337 if (unlikely(hw->phy.nw_mng_if_sel & 338 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 339 struct ixgbe_adapter *adapter; 340 int i; 341 342 for (i = 0; i < 200; ++i) { 343 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 344 if (likely(!value)) 345 goto writes_completed; 346 if (value == IXGBE_FAILED_READ_REG) { 347 ixgbe_remove_adapter(hw); 348 return IXGBE_FAILED_READ_REG; 349 } 350 udelay(5); 351 } 352 353 adapter = hw->back; 354 e_warn(hw, "register writes incomplete %08x\n", value); 355 } 356 357 writes_completed: 358 value = readl(reg_addr + reg); 359 if (unlikely(value == IXGBE_FAILED_READ_REG)) 360 value = ixgbe_check_remove(hw, reg); 361 return value; 362 } 363 364 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 365 { 366 u16 value; 367 368 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 369 if (value == IXGBE_FAILED_READ_CFG_WORD) { 370 ixgbe_remove_adapter(hw); 371 return true; 372 } 373 return false; 374 } 375 376 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 377 { 378 struct ixgbe_adapter *adapter = hw->back; 379 u16 value; 380 381 if (ixgbe_removed(hw->hw_addr)) 382 return IXGBE_FAILED_READ_CFG_WORD; 383 pci_read_config_word(adapter->pdev, reg, &value); 384 if (value == IXGBE_FAILED_READ_CFG_WORD && 385 ixgbe_check_cfg_remove(hw, adapter->pdev)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 return value; 388 } 389 390 #ifdef CONFIG_PCI_IOV 391 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 392 { 393 struct ixgbe_adapter *adapter = hw->back; 394 u32 value; 395 396 if (ixgbe_removed(hw->hw_addr)) 397 return IXGBE_FAILED_READ_CFG_DWORD; 398 pci_read_config_dword(adapter->pdev, reg, &value); 399 if (value == IXGBE_FAILED_READ_CFG_DWORD && 400 ixgbe_check_cfg_remove(hw, adapter->pdev)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 return value; 403 } 404 #endif /* CONFIG_PCI_IOV */ 405 406 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 407 { 408 struct ixgbe_adapter *adapter = hw->back; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return; 412 pci_write_config_word(adapter->pdev, reg, value); 413 } 414 415 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 416 { 417 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 418 419 /* flush memory to make sure state is correct before next watchdog */ 420 smp_mb__before_atomic(); 421 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 422 } 423 424 struct ixgbe_reg_info { 425 u32 ofs; 426 char *name; 427 }; 428 429 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 430 431 /* General Registers */ 432 {IXGBE_CTRL, "CTRL"}, 433 {IXGBE_STATUS, "STATUS"}, 434 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 435 436 /* Interrupt Registers */ 437 {IXGBE_EICR, "EICR"}, 438 439 /* RX Registers */ 440 {IXGBE_SRRCTL(0), "SRRCTL"}, 441 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 442 {IXGBE_RDLEN(0), "RDLEN"}, 443 {IXGBE_RDH(0), "RDH"}, 444 {IXGBE_RDT(0), "RDT"}, 445 {IXGBE_RXDCTL(0), "RXDCTL"}, 446 {IXGBE_RDBAL(0), "RDBAL"}, 447 {IXGBE_RDBAH(0), "RDBAH"}, 448 449 /* TX Registers */ 450 {IXGBE_TDBAL(0), "TDBAL"}, 451 {IXGBE_TDBAH(0), "TDBAH"}, 452 {IXGBE_TDLEN(0), "TDLEN"}, 453 {IXGBE_TDH(0), "TDH"}, 454 {IXGBE_TDT(0), "TDT"}, 455 {IXGBE_TXDCTL(0), "TXDCTL"}, 456 457 /* List Terminator */ 458 { .name = NULL } 459 }; 460 461 462 /* 463 * ixgbe_regdump - register printout routine 464 */ 465 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 466 { 467 int i; 468 char rname[16]; 469 u32 regs[64]; 470 471 switch (reginfo->ofs) { 472 case IXGBE_SRRCTL(0): 473 for (i = 0; i < 64; i++) 474 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 475 break; 476 case IXGBE_DCA_RXCTRL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 479 break; 480 case IXGBE_RDLEN(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 483 break; 484 case IXGBE_RDH(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 487 break; 488 case IXGBE_RDT(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 491 break; 492 case IXGBE_RXDCTL(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 495 break; 496 case IXGBE_RDBAL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 499 break; 500 case IXGBE_RDBAH(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 503 break; 504 case IXGBE_TDBAL(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 507 break; 508 case IXGBE_TDBAH(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 511 break; 512 case IXGBE_TDLEN(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 515 break; 516 case IXGBE_TDH(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 519 break; 520 case IXGBE_TDT(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 523 break; 524 case IXGBE_TXDCTL(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 527 break; 528 default: 529 pr_info("%-15s %08x\n", 530 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 531 return; 532 } 533 534 i = 0; 535 while (i < 64) { 536 int j; 537 char buf[9 * 8 + 1]; 538 char *p = buf; 539 540 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 541 for (j = 0; j < 8; j++) 542 p += sprintf(p, " %08x", regs[i++]); 543 pr_err("%-15s%s\n", rname, buf); 544 } 545 546 } 547 548 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 549 { 550 struct ixgbe_tx_buffer *tx_buffer; 551 552 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 553 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 554 n, ring->next_to_use, ring->next_to_clean, 555 (u64)dma_unmap_addr(tx_buffer, dma), 556 dma_unmap_len(tx_buffer, len), 557 tx_buffer->next_to_watch, 558 (u64)tx_buffer->time_stamp); 559 } 560 561 /* 562 * ixgbe_dump - Print registers, tx-rings and rx-rings 563 */ 564 static void ixgbe_dump(struct ixgbe_adapter *adapter) 565 { 566 struct net_device *netdev = adapter->netdev; 567 struct ixgbe_hw *hw = &adapter->hw; 568 struct ixgbe_reg_info *reginfo; 569 int n = 0; 570 struct ixgbe_ring *ring; 571 struct ixgbe_tx_buffer *tx_buffer; 572 union ixgbe_adv_tx_desc *tx_desc; 573 struct my_u0 { u64 a; u64 b; } *u0; 574 struct ixgbe_ring *rx_ring; 575 union ixgbe_adv_rx_desc *rx_desc; 576 struct ixgbe_rx_buffer *rx_buffer_info; 577 int i = 0; 578 579 if (!netif_msg_hw(adapter)) 580 return; 581 582 /* Print netdevice Info */ 583 if (netdev) { 584 dev_info(&adapter->pdev->dev, "Net device Info\n"); 585 pr_info("Device Name state " 586 "trans_start\n"); 587 pr_info("%-15s %016lX %016lX\n", 588 netdev->name, 589 netdev->state, 590 dev_trans_start(netdev)); 591 } 592 593 /* Print Registers */ 594 dev_info(&adapter->pdev->dev, "Register Dump\n"); 595 pr_info(" Register Name Value\n"); 596 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 597 reginfo->name; reginfo++) { 598 ixgbe_regdump(hw, reginfo); 599 } 600 601 /* Print TX Ring Summary */ 602 if (!netdev || !netif_running(netdev)) 603 return; 604 605 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 606 pr_info(" %s %s %s %s\n", 607 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 608 "leng", "ntw", "timestamp"); 609 for (n = 0; n < adapter->num_tx_queues; n++) { 610 ring = adapter->tx_ring[n]; 611 ixgbe_print_buffer(ring, n); 612 } 613 614 for (n = 0; n < adapter->num_xdp_queues; n++) { 615 ring = adapter->xdp_ring[n]; 616 ixgbe_print_buffer(ring, n); 617 } 618 619 /* Print TX Rings */ 620 if (!netif_msg_tx_done(adapter)) 621 goto rx_ring_summary; 622 623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 624 625 /* Transmit Descriptor Formats 626 * 627 * 82598 Advanced Transmit Descriptor 628 * +--------------------------------------------------------------+ 629 * 0 | Buffer Address [63:0] | 630 * +--------------------------------------------------------------+ 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 632 * +--------------------------------------------------------------+ 633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 634 * 635 * 82598 Advanced Transmit Descriptor (Write-Back Format) 636 * +--------------------------------------------------------------+ 637 * 0 | RSV [63:0] | 638 * +--------------------------------------------------------------+ 639 * 8 | RSV | STA | NXTSEQ | 640 * +--------------------------------------------------------------+ 641 * 63 36 35 32 31 0 642 * 643 * 82599+ Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 650 * 651 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | RSV | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 */ 659 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 ring = adapter->tx_ring[n]; 662 pr_info("------------------------------------\n"); 663 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 664 pr_info("------------------------------------\n"); 665 pr_info("%s%s %s %s %s %s\n", 666 "T [desc] [address 63:0 ] ", 667 "[PlPOIdStDDt Ln] [bi->dma ] ", 668 "leng", "ntw", "timestamp", "bi->skb"); 669 670 for (i = 0; ring->desc && (i < ring->count); i++) { 671 tx_desc = IXGBE_TX_DESC(ring, i); 672 tx_buffer = &ring->tx_buffer_info[i]; 673 u0 = (struct my_u0 *)tx_desc; 674 if (dma_unmap_len(tx_buffer, len) > 0) { 675 const char *ring_desc; 676 677 if (i == ring->next_to_use && 678 i == ring->next_to_clean) 679 ring_desc = " NTC/U"; 680 else if (i == ring->next_to_use) 681 ring_desc = " NTU"; 682 else if (i == ring->next_to_clean) 683 ring_desc = " NTC"; 684 else 685 ring_desc = ""; 686 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 687 i, 688 le64_to_cpu((__force __le64)u0->a), 689 le64_to_cpu((__force __le64)u0->b), 690 (u64)dma_unmap_addr(tx_buffer, dma), 691 dma_unmap_len(tx_buffer, len), 692 tx_buffer->next_to_watch, 693 (u64)tx_buffer->time_stamp, 694 tx_buffer->skb, 695 ring_desc); 696 697 if (netif_msg_pktdata(adapter) && 698 tx_buffer->skb) 699 print_hex_dump(KERN_INFO, "", 700 DUMP_PREFIX_ADDRESS, 16, 1, 701 tx_buffer->skb->data, 702 dma_unmap_len(tx_buffer, len), 703 true); 704 } 705 } 706 } 707 708 /* Print RX Rings Summary */ 709 rx_ring_summary: 710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 711 pr_info("Queue [NTU] [NTC]\n"); 712 for (n = 0; n < adapter->num_rx_queues; n++) { 713 rx_ring = adapter->rx_ring[n]; 714 pr_info("%5d %5X %5X\n", 715 n, rx_ring->next_to_use, rx_ring->next_to_clean); 716 } 717 718 /* Print RX Rings */ 719 if (!netif_msg_rx_status(adapter)) 720 return; 721 722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 723 724 /* Receive Descriptor Formats 725 * 726 * 82598 Advanced Receive Descriptor (Read) Format 727 * 63 1 0 728 * +-----------------------------------------------------+ 729 * 0 | Packet Buffer Address [63:1] |A0/NSE| 730 * +----------------------------------------------+------+ 731 * 8 | Header Buffer Address [63:1] | DD | 732 * +-----------------------------------------------------+ 733 * 734 * 735 * 82598 Advanced Receive Descriptor (Write-Back) Format 736 * 737 * 63 48 47 32 31 30 21 20 16 15 4 3 0 738 * +------------------------------------------------------+ 739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 740 * | Packet | IP | | | | Type | Type | 741 * | Checksum | Ident | | | | | | 742 * +------------------------------------------------------+ 743 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 744 * +------------------------------------------------------+ 745 * 63 48 47 32 31 20 19 0 746 * 747 * 82599+ Advanced Receive Descriptor (Read) Format 748 * 63 1 0 749 * +-----------------------------------------------------+ 750 * 0 | Packet Buffer Address [63:1] |A0/NSE| 751 * +----------------------------------------------+------+ 752 * 8 | Header Buffer Address [63:1] | DD | 753 * +-----------------------------------------------------+ 754 * 755 * 756 * 82599+ Advanced Receive Descriptor (Write-Back) Format 757 * 758 * 63 48 47 32 31 30 21 20 17 16 4 3 0 759 * +------------------------------------------------------+ 760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 762 * |/ Flow Dir Flt ID | | | | | | 763 * +------------------------------------------------------+ 764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 765 * +------------------------------------------------------+ 766 * 63 48 47 32 31 20 19 0 767 */ 768 769 for (n = 0; n < adapter->num_rx_queues; n++) { 770 rx_ring = adapter->rx_ring[n]; 771 pr_info("------------------------------------\n"); 772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 773 pr_info("------------------------------------\n"); 774 pr_info("%s%s%s\n", 775 "R [desc] [ PktBuf A0] ", 776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 777 "<-- Adv Rx Read format"); 778 pr_info("%s%s%s\n", 779 "RWB[desc] [PcsmIpSHl PtRs] ", 780 "[vl er S cks ln] ---------------- [bi->skb ] ", 781 "<-- Adv Rx Write-Back format"); 782 783 for (i = 0; i < rx_ring->count; i++) { 784 const char *ring_desc; 785 786 if (i == rx_ring->next_to_use) 787 ring_desc = " NTU"; 788 else if (i == rx_ring->next_to_clean) 789 ring_desc = " NTC"; 790 else 791 ring_desc = ""; 792 793 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 794 rx_desc = IXGBE_RX_DESC(rx_ring, i); 795 u0 = (struct my_u0 *)rx_desc; 796 if (rx_desc->wb.upper.length) { 797 /* Descriptor Done */ 798 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 799 i, 800 le64_to_cpu((__force __le64)u0->a), 801 le64_to_cpu((__force __le64)u0->b), 802 rx_buffer_info->skb, 803 ring_desc); 804 } else { 805 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 806 i, 807 le64_to_cpu((__force __le64)u0->a), 808 le64_to_cpu((__force __le64)u0->b), 809 (u64)rx_buffer_info->dma, 810 rx_buffer_info->skb, 811 ring_desc); 812 813 if (netif_msg_pktdata(adapter) && 814 rx_buffer_info->dma) { 815 print_hex_dump(KERN_INFO, "", 816 DUMP_PREFIX_ADDRESS, 16, 1, 817 page_address(rx_buffer_info->page) + 818 rx_buffer_info->page_offset, 819 ixgbe_rx_bufsz(rx_ring), true); 820 } 821 } 822 } 823 } 824 } 825 826 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 827 { 828 u32 ctrl_ext; 829 830 /* Let firmware take over control of h/w */ 831 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 833 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 834 } 835 836 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 837 { 838 u32 ctrl_ext; 839 840 /* Let firmware know the driver has taken over */ 841 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 843 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 844 } 845 846 /** 847 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 848 * @adapter: pointer to adapter struct 849 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 850 * @queue: queue to map the corresponding interrupt to 851 * @msix_vector: the vector to map to the corresponding queue 852 * 853 */ 854 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 855 u8 queue, u8 msix_vector) 856 { 857 u32 ivar, index; 858 struct ixgbe_hw *hw = &adapter->hw; 859 switch (hw->mac.type) { 860 case ixgbe_mac_82598EB: 861 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 862 if (direction == -1) 863 direction = 0; 864 index = (((direction * 64) + queue) >> 2) & 0x1F; 865 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 866 ivar &= ~(0xFF << (8 * (queue & 0x3))); 867 ivar |= (msix_vector << (8 * (queue & 0x3))); 868 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 869 break; 870 case ixgbe_mac_82599EB: 871 case ixgbe_mac_X540: 872 case ixgbe_mac_X550: 873 case ixgbe_mac_X550EM_x: 874 case ixgbe_mac_x550em_a: 875 if (direction == -1) { 876 /* other causes */ 877 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 878 index = ((queue & 1) * 8); 879 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 880 ivar &= ~(0xFF << index); 881 ivar |= (msix_vector << index); 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 883 break; 884 } else { 885 /* tx or rx causes */ 886 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 887 index = ((16 * (queue & 1)) + (8 * direction)); 888 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 889 ivar &= ~(0xFF << index); 890 ivar |= (msix_vector << index); 891 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 892 break; 893 } 894 default: 895 break; 896 } 897 } 898 899 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 900 u64 qmask) 901 { 902 u32 mask; 903 904 switch (adapter->hw.mac.type) { 905 case ixgbe_mac_82598EB: 906 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 908 break; 909 case ixgbe_mac_82599EB: 910 case ixgbe_mac_X540: 911 case ixgbe_mac_X550: 912 case ixgbe_mac_X550EM_x: 913 case ixgbe_mac_x550em_a: 914 mask = (qmask & 0xFFFFFFFF); 915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 916 mask = (qmask >> 32); 917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 918 break; 919 default: 920 break; 921 } 922 } 923 924 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 925 { 926 struct ixgbe_hw *hw = &adapter->hw; 927 struct ixgbe_hw_stats *hwstats = &adapter->stats; 928 int i; 929 u32 data; 930 931 if ((hw->fc.current_mode != ixgbe_fc_full) && 932 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 933 return; 934 935 switch (hw->mac.type) { 936 case ixgbe_mac_82598EB: 937 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 938 break; 939 default: 940 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 941 } 942 hwstats->lxoffrxc += data; 943 944 /* refill credits (no tx hang) if we received xoff */ 945 if (!data) 946 return; 947 948 for (i = 0; i < adapter->num_tx_queues; i++) 949 clear_bit(__IXGBE_HANG_CHECK_ARMED, 950 &adapter->tx_ring[i]->state); 951 952 for (i = 0; i < adapter->num_xdp_queues; i++) 953 clear_bit(__IXGBE_HANG_CHECK_ARMED, 954 &adapter->xdp_ring[i]->state); 955 } 956 957 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 958 { 959 struct ixgbe_hw *hw = &adapter->hw; 960 struct ixgbe_hw_stats *hwstats = &adapter->stats; 961 u32 xoff[8] = {0}; 962 u8 tc; 963 int i; 964 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 965 966 if (adapter->ixgbe_ieee_pfc) 967 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 968 969 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 970 ixgbe_update_xoff_rx_lfc(adapter); 971 return; 972 } 973 974 /* update stats for each tc, only valid with PFC enabled */ 975 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 976 u32 pxoffrxc; 977 978 switch (hw->mac.type) { 979 case ixgbe_mac_82598EB: 980 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 981 break; 982 default: 983 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 984 } 985 hwstats->pxoffrxc[i] += pxoffrxc; 986 /* Get the TC for given UP */ 987 tc = netdev_get_prio_tc_map(adapter->netdev, i); 988 xoff[tc] += pxoffrxc; 989 } 990 991 /* disarm tx queues that have received xoff frames */ 992 for (i = 0; i < adapter->num_tx_queues; i++) { 993 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 994 995 tc = tx_ring->dcb_tc; 996 if (xoff[tc]) 997 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 998 } 999 1000 for (i = 0; i < adapter->num_xdp_queues; i++) { 1001 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1002 1003 tc = xdp_ring->dcb_tc; 1004 if (xoff[tc]) 1005 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1006 } 1007 } 1008 1009 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1010 { 1011 return ring->stats.packets; 1012 } 1013 1014 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1015 { 1016 unsigned int head, tail; 1017 1018 head = ring->next_to_clean; 1019 tail = ring->next_to_use; 1020 1021 return ((head <= tail) ? tail : tail + ring->count) - head; 1022 } 1023 1024 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1025 { 1026 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1027 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1028 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1029 1030 clear_check_for_tx_hang(tx_ring); 1031 1032 /* 1033 * Check for a hung queue, but be thorough. This verifies 1034 * that a transmit has been completed since the previous 1035 * check AND there is at least one packet pending. The 1036 * ARMED bit is set to indicate a potential hang. The 1037 * bit is cleared if a pause frame is received to remove 1038 * false hang detection due to PFC or 802.3x frames. By 1039 * requiring this to fail twice we avoid races with 1040 * pfc clearing the ARMED bit and conditions where we 1041 * run the check_tx_hang logic with a transmit completion 1042 * pending but without time to complete it yet. 1043 */ 1044 if (tx_done_old == tx_done && tx_pending) 1045 /* make sure it is true for two checks in a row */ 1046 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1047 &tx_ring->state); 1048 /* update completed stats and continue */ 1049 tx_ring->tx_stats.tx_done_old = tx_done; 1050 /* reset the countdown */ 1051 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1052 1053 return false; 1054 } 1055 1056 /** 1057 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1058 * @adapter: driver private struct 1059 **/ 1060 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1061 { 1062 1063 /* Do the reset outside of interrupt context */ 1064 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1065 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1066 e_warn(drv, "initiating reset due to tx timeout\n"); 1067 ixgbe_service_event_schedule(adapter); 1068 } 1069 } 1070 1071 /** 1072 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1073 * @netdev: network interface device structure 1074 * @queue_index: Tx queue to set 1075 * @maxrate: desired maximum transmit bitrate 1076 **/ 1077 static int ixgbe_tx_maxrate(struct net_device *netdev, 1078 int queue_index, u32 maxrate) 1079 { 1080 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1081 struct ixgbe_hw *hw = &adapter->hw; 1082 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1083 1084 if (!maxrate) 1085 return 0; 1086 1087 /* Calculate the rate factor values to set */ 1088 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1089 bcnrc_val /= maxrate; 1090 1091 /* clear everything but the rate factor */ 1092 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1093 IXGBE_RTTBCNRC_RF_DEC_MASK; 1094 1095 /* enable the rate scheduler */ 1096 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1097 1098 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1099 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1100 1101 return 0; 1102 } 1103 1104 /** 1105 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1106 * @q_vector: structure containing interrupt and ring information 1107 * @tx_ring: tx ring to clean 1108 * @napi_budget: Used to determine if we are in netpoll 1109 **/ 1110 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1111 struct ixgbe_ring *tx_ring, int napi_budget) 1112 { 1113 struct ixgbe_adapter *adapter = q_vector->adapter; 1114 struct ixgbe_tx_buffer *tx_buffer; 1115 union ixgbe_adv_tx_desc *tx_desc; 1116 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1117 unsigned int budget = q_vector->tx.work_limit; 1118 unsigned int i = tx_ring->next_to_clean; 1119 1120 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1121 return true; 1122 1123 tx_buffer = &tx_ring->tx_buffer_info[i]; 1124 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1125 i -= tx_ring->count; 1126 1127 do { 1128 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1129 1130 /* if next_to_watch is not set then there is no work pending */ 1131 if (!eop_desc) 1132 break; 1133 1134 /* prevent any other reads prior to eop_desc */ 1135 smp_rmb(); 1136 1137 /* if DD is not set pending work has not been completed */ 1138 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1139 break; 1140 1141 /* clear next_to_watch to prevent false hangs */ 1142 tx_buffer->next_to_watch = NULL; 1143 1144 /* update the statistics for this packet */ 1145 total_bytes += tx_buffer->bytecount; 1146 total_packets += tx_buffer->gso_segs; 1147 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1148 total_ipsec++; 1149 1150 /* free the skb */ 1151 if (ring_is_xdp(tx_ring)) 1152 xdp_return_frame(tx_buffer->xdpf); 1153 else 1154 napi_consume_skb(tx_buffer->skb, napi_budget); 1155 1156 /* unmap skb header data */ 1157 dma_unmap_single(tx_ring->dev, 1158 dma_unmap_addr(tx_buffer, dma), 1159 dma_unmap_len(tx_buffer, len), 1160 DMA_TO_DEVICE); 1161 1162 /* clear tx_buffer data */ 1163 dma_unmap_len_set(tx_buffer, len, 0); 1164 1165 /* unmap remaining buffers */ 1166 while (tx_desc != eop_desc) { 1167 tx_buffer++; 1168 tx_desc++; 1169 i++; 1170 if (unlikely(!i)) { 1171 i -= tx_ring->count; 1172 tx_buffer = tx_ring->tx_buffer_info; 1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1174 } 1175 1176 /* unmap any remaining paged data */ 1177 if (dma_unmap_len(tx_buffer, len)) { 1178 dma_unmap_page(tx_ring->dev, 1179 dma_unmap_addr(tx_buffer, dma), 1180 dma_unmap_len(tx_buffer, len), 1181 DMA_TO_DEVICE); 1182 dma_unmap_len_set(tx_buffer, len, 0); 1183 } 1184 } 1185 1186 /* move us one more past the eop_desc for start of next pkt */ 1187 tx_buffer++; 1188 tx_desc++; 1189 i++; 1190 if (unlikely(!i)) { 1191 i -= tx_ring->count; 1192 tx_buffer = tx_ring->tx_buffer_info; 1193 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1194 } 1195 1196 /* issue prefetch for next Tx descriptor */ 1197 prefetch(tx_desc); 1198 1199 /* update budget accounting */ 1200 budget--; 1201 } while (likely(budget)); 1202 1203 i += tx_ring->count; 1204 tx_ring->next_to_clean = i; 1205 u64_stats_update_begin(&tx_ring->syncp); 1206 tx_ring->stats.bytes += total_bytes; 1207 tx_ring->stats.packets += total_packets; 1208 u64_stats_update_end(&tx_ring->syncp); 1209 q_vector->tx.total_bytes += total_bytes; 1210 q_vector->tx.total_packets += total_packets; 1211 adapter->tx_ipsec += total_ipsec; 1212 1213 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1214 /* schedule immediate reset if we believe we hung */ 1215 struct ixgbe_hw *hw = &adapter->hw; 1216 e_err(drv, "Detected Tx Unit Hang %s\n" 1217 " Tx Queue <%d>\n" 1218 " TDH, TDT <%x>, <%x>\n" 1219 " next_to_use <%x>\n" 1220 " next_to_clean <%x>\n" 1221 "tx_buffer_info[next_to_clean]\n" 1222 " time_stamp <%lx>\n" 1223 " jiffies <%lx>\n", 1224 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1225 tx_ring->queue_index, 1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1228 tx_ring->next_to_use, i, 1229 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1230 1231 if (!ring_is_xdp(tx_ring)) 1232 netif_stop_subqueue(tx_ring->netdev, 1233 tx_ring->queue_index); 1234 1235 e_info(probe, 1236 "tx hang %d detected on queue %d, resetting adapter\n", 1237 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1238 1239 /* schedule immediate reset if we believe we hung */ 1240 ixgbe_tx_timeout_reset(adapter); 1241 1242 /* the adapter is about to reset, no point in enabling stuff */ 1243 return true; 1244 } 1245 1246 if (ring_is_xdp(tx_ring)) 1247 return !!budget; 1248 1249 netdev_tx_completed_queue(txring_txq(tx_ring), 1250 total_packets, total_bytes); 1251 1252 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1253 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1254 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1255 /* Make sure that anybody stopping the queue after this 1256 * sees the new next_to_clean. 1257 */ 1258 smp_mb(); 1259 if (__netif_subqueue_stopped(tx_ring->netdev, 1260 tx_ring->queue_index) 1261 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1262 netif_wake_subqueue(tx_ring->netdev, 1263 tx_ring->queue_index); 1264 ++tx_ring->tx_stats.restart_queue; 1265 } 1266 } 1267 1268 return !!budget; 1269 } 1270 1271 #ifdef CONFIG_IXGBE_DCA 1272 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1273 struct ixgbe_ring *tx_ring, 1274 int cpu) 1275 { 1276 struct ixgbe_hw *hw = &adapter->hw; 1277 u32 txctrl = 0; 1278 u16 reg_offset; 1279 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1281 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1282 1283 switch (hw->mac.type) { 1284 case ixgbe_mac_82598EB: 1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1286 break; 1287 case ixgbe_mac_82599EB: 1288 case ixgbe_mac_X540: 1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1290 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1291 break; 1292 default: 1293 /* for unknown hardware do not write register */ 1294 return; 1295 } 1296 1297 /* 1298 * We can enable relaxed ordering for reads, but not writes when 1299 * DCA is enabled. This is due to a known issue in some chipsets 1300 * which will cause the DCA tag to be cleared. 1301 */ 1302 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1303 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1304 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1305 1306 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1307 } 1308 1309 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1310 struct ixgbe_ring *rx_ring, 1311 int cpu) 1312 { 1313 struct ixgbe_hw *hw = &adapter->hw; 1314 u32 rxctrl = 0; 1315 u8 reg_idx = rx_ring->reg_idx; 1316 1317 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1318 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1319 1320 switch (hw->mac.type) { 1321 case ixgbe_mac_82599EB: 1322 case ixgbe_mac_X540: 1323 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1324 break; 1325 default: 1326 break; 1327 } 1328 1329 /* 1330 * We can enable relaxed ordering for reads, but not writes when 1331 * DCA is enabled. This is due to a known issue in some chipsets 1332 * which will cause the DCA tag to be cleared. 1333 */ 1334 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1335 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1336 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1337 1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1339 } 1340 1341 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1342 { 1343 struct ixgbe_adapter *adapter = q_vector->adapter; 1344 struct ixgbe_ring *ring; 1345 int cpu = get_cpu(); 1346 1347 if (q_vector->cpu == cpu) 1348 goto out_no_update; 1349 1350 ixgbe_for_each_ring(ring, q_vector->tx) 1351 ixgbe_update_tx_dca(adapter, ring, cpu); 1352 1353 ixgbe_for_each_ring(ring, q_vector->rx) 1354 ixgbe_update_rx_dca(adapter, ring, cpu); 1355 1356 q_vector->cpu = cpu; 1357 out_no_update: 1358 put_cpu(); 1359 } 1360 1361 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1362 { 1363 int i; 1364 1365 /* always use CB2 mode, difference is masked in the CB driver */ 1366 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1368 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1369 else 1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1371 IXGBE_DCA_CTRL_DCA_DISABLE); 1372 1373 for (i = 0; i < adapter->num_q_vectors; i++) { 1374 adapter->q_vector[i]->cpu = -1; 1375 ixgbe_update_dca(adapter->q_vector[i]); 1376 } 1377 } 1378 1379 static int __ixgbe_notify_dca(struct device *dev, void *data) 1380 { 1381 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1382 unsigned long event = *(unsigned long *)data; 1383 1384 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1385 return 0; 1386 1387 switch (event) { 1388 case DCA_PROVIDER_ADD: 1389 /* if we're already enabled, don't do it again */ 1390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1391 break; 1392 if (dca_add_requester(dev) == 0) { 1393 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1395 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1396 break; 1397 } 1398 fallthrough; /* DCA is disabled. */ 1399 case DCA_PROVIDER_REMOVE: 1400 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1401 dca_remove_requester(dev); 1402 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1403 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1404 IXGBE_DCA_CTRL_DCA_DISABLE); 1405 } 1406 break; 1407 } 1408 1409 return 0; 1410 } 1411 1412 #endif /* CONFIG_IXGBE_DCA */ 1413 1414 #define IXGBE_RSS_L4_TYPES_MASK \ 1415 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1416 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1417 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1419 1420 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1421 union ixgbe_adv_rx_desc *rx_desc, 1422 struct sk_buff *skb) 1423 { 1424 u16 rss_type; 1425 1426 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1427 return; 1428 1429 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1430 IXGBE_RXDADV_RSSTYPE_MASK; 1431 1432 if (!rss_type) 1433 return; 1434 1435 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1436 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1437 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1438 } 1439 1440 #ifdef IXGBE_FCOE 1441 /** 1442 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1443 * @ring: structure containing ring specific data 1444 * @rx_desc: advanced rx descriptor 1445 * 1446 * Returns : true if it is FCoE pkt 1447 */ 1448 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1449 union ixgbe_adv_rx_desc *rx_desc) 1450 { 1451 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1452 1453 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1454 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1455 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1456 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1457 } 1458 1459 #endif /* IXGBE_FCOE */ 1460 /** 1461 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1462 * @ring: structure containing ring specific data 1463 * @rx_desc: current Rx descriptor being processed 1464 * @skb: skb currently being received and modified 1465 **/ 1466 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1467 union ixgbe_adv_rx_desc *rx_desc, 1468 struct sk_buff *skb) 1469 { 1470 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1471 bool encap_pkt = false; 1472 1473 skb_checksum_none_assert(skb); 1474 1475 /* Rx csum disabled */ 1476 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1477 return; 1478 1479 /* check for VXLAN and Geneve packets */ 1480 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1481 encap_pkt = true; 1482 skb->encapsulation = 1; 1483 } 1484 1485 /* if IP and error */ 1486 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1487 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1488 ring->rx_stats.csum_err++; 1489 return; 1490 } 1491 1492 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1493 return; 1494 1495 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1496 /* 1497 * 82599 errata, UDP frames with a 0 checksum can be marked as 1498 * checksum errors. 1499 */ 1500 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1501 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1502 return; 1503 1504 ring->rx_stats.csum_err++; 1505 return; 1506 } 1507 1508 /* It must be a TCP or UDP packet with a valid checksum */ 1509 skb->ip_summed = CHECKSUM_UNNECESSARY; 1510 if (encap_pkt) { 1511 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1512 return; 1513 1514 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1515 skb->ip_summed = CHECKSUM_NONE; 1516 return; 1517 } 1518 /* If we checked the outer header let the stack know */ 1519 skb->csum_level = 1; 1520 } 1521 } 1522 1523 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1524 { 1525 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1526 } 1527 1528 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1529 struct ixgbe_rx_buffer *bi) 1530 { 1531 struct page *page = bi->page; 1532 dma_addr_t dma; 1533 1534 /* since we are recycling buffers we should seldom need to alloc */ 1535 if (likely(page)) 1536 return true; 1537 1538 /* alloc new page for storage */ 1539 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1540 if (unlikely(!page)) { 1541 rx_ring->rx_stats.alloc_rx_page_failed++; 1542 return false; 1543 } 1544 1545 /* map page for use */ 1546 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1547 ixgbe_rx_pg_size(rx_ring), 1548 DMA_FROM_DEVICE, 1549 IXGBE_RX_DMA_ATTR); 1550 1551 /* 1552 * if mapping failed free memory back to system since 1553 * there isn't much point in holding memory we can't use 1554 */ 1555 if (dma_mapping_error(rx_ring->dev, dma)) { 1556 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1557 1558 rx_ring->rx_stats.alloc_rx_page_failed++; 1559 return false; 1560 } 1561 1562 bi->dma = dma; 1563 bi->page = page; 1564 bi->page_offset = rx_ring->rx_offset; 1565 page_ref_add(page, USHRT_MAX - 1); 1566 bi->pagecnt_bias = USHRT_MAX; 1567 rx_ring->rx_stats.alloc_rx_page++; 1568 1569 return true; 1570 } 1571 1572 /** 1573 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1574 * @rx_ring: ring to place buffers on 1575 * @cleaned_count: number of buffers to replace 1576 **/ 1577 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1578 { 1579 union ixgbe_adv_rx_desc *rx_desc; 1580 struct ixgbe_rx_buffer *bi; 1581 u16 i = rx_ring->next_to_use; 1582 u16 bufsz; 1583 1584 /* nothing to do */ 1585 if (!cleaned_count) 1586 return; 1587 1588 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1589 bi = &rx_ring->rx_buffer_info[i]; 1590 i -= rx_ring->count; 1591 1592 bufsz = ixgbe_rx_bufsz(rx_ring); 1593 1594 do { 1595 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1596 break; 1597 1598 /* sync the buffer for use by the device */ 1599 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1600 bi->page_offset, bufsz, 1601 DMA_FROM_DEVICE); 1602 1603 /* 1604 * Refresh the desc even if buffer_addrs didn't change 1605 * because each write-back erases this info. 1606 */ 1607 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1608 1609 rx_desc++; 1610 bi++; 1611 i++; 1612 if (unlikely(!i)) { 1613 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1614 bi = rx_ring->rx_buffer_info; 1615 i -= rx_ring->count; 1616 } 1617 1618 /* clear the length for the next_to_use descriptor */ 1619 rx_desc->wb.upper.length = 0; 1620 1621 cleaned_count--; 1622 } while (cleaned_count); 1623 1624 i += rx_ring->count; 1625 1626 if (rx_ring->next_to_use != i) { 1627 rx_ring->next_to_use = i; 1628 1629 /* update next to alloc since we have filled the ring */ 1630 rx_ring->next_to_alloc = i; 1631 1632 /* Force memory writes to complete before letting h/w 1633 * know there are new descriptors to fetch. (Only 1634 * applicable for weak-ordered memory model archs, 1635 * such as IA-64). 1636 */ 1637 wmb(); 1638 writel(i, rx_ring->tail); 1639 } 1640 } 1641 1642 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1643 struct sk_buff *skb) 1644 { 1645 u16 hdr_len = skb_headlen(skb); 1646 1647 /* set gso_size to avoid messing up TCP MSS */ 1648 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1649 IXGBE_CB(skb)->append_cnt); 1650 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1651 } 1652 1653 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1654 struct sk_buff *skb) 1655 { 1656 /* if append_cnt is 0 then frame is not RSC */ 1657 if (!IXGBE_CB(skb)->append_cnt) 1658 return; 1659 1660 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1661 rx_ring->rx_stats.rsc_flush++; 1662 1663 ixgbe_set_rsc_gso_size(rx_ring, skb); 1664 1665 /* gso_size is computed using append_cnt so always clear it last */ 1666 IXGBE_CB(skb)->append_cnt = 0; 1667 } 1668 1669 /** 1670 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1671 * @rx_ring: rx descriptor ring packet is being transacted on 1672 * @rx_desc: pointer to the EOP Rx descriptor 1673 * @skb: pointer to current skb being populated 1674 * 1675 * This function checks the ring, descriptor, and packet information in 1676 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1677 * other fields within the skb. 1678 **/ 1679 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1680 union ixgbe_adv_rx_desc *rx_desc, 1681 struct sk_buff *skb) 1682 { 1683 struct net_device *dev = rx_ring->netdev; 1684 u32 flags = rx_ring->q_vector->adapter->flags; 1685 1686 ixgbe_update_rsc_stats(rx_ring, skb); 1687 1688 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1689 1690 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1691 1692 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1694 1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1699 } 1700 1701 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1702 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1703 1704 /* record Rx queue, or update MACVLAN statistics */ 1705 if (netif_is_ixgbe(dev)) 1706 skb_record_rx_queue(skb, rx_ring->queue_index); 1707 else 1708 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1709 false); 1710 1711 skb->protocol = eth_type_trans(skb, dev); 1712 } 1713 1714 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1715 struct sk_buff *skb) 1716 { 1717 napi_gro_receive(&q_vector->napi, skb); 1718 } 1719 1720 /** 1721 * ixgbe_is_non_eop - process handling of non-EOP buffers 1722 * @rx_ring: Rx ring being processed 1723 * @rx_desc: Rx descriptor for current buffer 1724 * @skb: Current socket buffer containing buffer in progress 1725 * 1726 * This function updates next to clean. If the buffer is an EOP buffer 1727 * this function exits returning false, otherwise it will place the 1728 * sk_buff in the next buffer to be chained and return true indicating 1729 * that this is in fact a non-EOP buffer. 1730 **/ 1731 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1732 union ixgbe_adv_rx_desc *rx_desc, 1733 struct sk_buff *skb) 1734 { 1735 u32 ntc = rx_ring->next_to_clean + 1; 1736 1737 /* fetch, update, and store next to clean */ 1738 ntc = (ntc < rx_ring->count) ? ntc : 0; 1739 rx_ring->next_to_clean = ntc; 1740 1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1742 1743 /* update RSC append count if present */ 1744 if (ring_is_rsc_enabled(rx_ring)) { 1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1747 1748 if (unlikely(rsc_enabled)) { 1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1750 1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1753 1754 /* update ntc based on RSC value */ 1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1756 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1758 } 1759 } 1760 1761 /* if we are the last buffer then there is nothing else to do */ 1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1763 return false; 1764 1765 /* place skb in next buffer to be received */ 1766 rx_ring->rx_buffer_info[ntc].skb = skb; 1767 rx_ring->rx_stats.non_eop_descs++; 1768 1769 return true; 1770 } 1771 1772 /** 1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1774 * @rx_ring: rx descriptor ring packet is being transacted on 1775 * @skb: pointer to current skb being adjusted 1776 * 1777 * This function is an ixgbe specific version of __pskb_pull_tail. The 1778 * main difference between this version and the original function is that 1779 * this function can make several assumptions about the state of things 1780 * that allow for significant optimizations versus the standard function. 1781 * As a result we can do things like drop a frag and maintain an accurate 1782 * truesize for the skb. 1783 */ 1784 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1785 struct sk_buff *skb) 1786 { 1787 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1788 unsigned char *va; 1789 unsigned int pull_len; 1790 1791 /* 1792 * it is valid to use page_address instead of kmap since we are 1793 * working with pages allocated out of the lomem pool per 1794 * alloc_page(GFP_ATOMIC) 1795 */ 1796 va = skb_frag_address(frag); 1797 1798 /* 1799 * we need the header to contain the greater of either ETH_HLEN or 1800 * 60 bytes if the skb->len is less than 60 for skb_pad. 1801 */ 1802 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1803 1804 /* align pull length to size of long to optimize memcpy performance */ 1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1806 1807 /* update all of the pointers */ 1808 skb_frag_size_sub(frag, pull_len); 1809 skb_frag_off_add(frag, pull_len); 1810 skb->data_len -= pull_len; 1811 skb->tail += pull_len; 1812 } 1813 1814 /** 1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1816 * @rx_ring: rx descriptor ring packet is being transacted on 1817 * @skb: pointer to current skb being updated 1818 * 1819 * This function provides a basic DMA sync up for the first fragment of an 1820 * skb. The reason for doing this is that the first fragment cannot be 1821 * unmapped until we have reached the end of packet descriptor for a buffer 1822 * chain. 1823 */ 1824 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1825 struct sk_buff *skb) 1826 { 1827 if (ring_uses_build_skb(rx_ring)) { 1828 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1829 1830 dma_sync_single_range_for_cpu(rx_ring->dev, 1831 IXGBE_CB(skb)->dma, 1832 offset, 1833 skb_headlen(skb), 1834 DMA_FROM_DEVICE); 1835 } else { 1836 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1837 1838 dma_sync_single_range_for_cpu(rx_ring->dev, 1839 IXGBE_CB(skb)->dma, 1840 skb_frag_off(frag), 1841 skb_frag_size(frag), 1842 DMA_FROM_DEVICE); 1843 } 1844 1845 /* If the page was released, just unmap it. */ 1846 if (unlikely(IXGBE_CB(skb)->page_released)) { 1847 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1848 ixgbe_rx_pg_size(rx_ring), 1849 DMA_FROM_DEVICE, 1850 IXGBE_RX_DMA_ATTR); 1851 } 1852 } 1853 1854 /** 1855 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1856 * @rx_ring: rx descriptor ring packet is being transacted on 1857 * @rx_desc: pointer to the EOP Rx descriptor 1858 * @skb: pointer to current skb being fixed 1859 * 1860 * Check if the skb is valid in the XDP case it will be an error pointer. 1861 * Return true in this case to abort processing and advance to next 1862 * descriptor. 1863 * 1864 * Check for corrupted packet headers caused by senders on the local L2 1865 * embedded NIC switch not setting up their Tx Descriptors right. These 1866 * should be very rare. 1867 * 1868 * Also address the case where we are pulling data in on pages only 1869 * and as such no data is present in the skb header. 1870 * 1871 * In addition if skb is not at least 60 bytes we need to pad it so that 1872 * it is large enough to qualify as a valid Ethernet frame. 1873 * 1874 * Returns true if an error was encountered and skb was freed. 1875 **/ 1876 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1877 union ixgbe_adv_rx_desc *rx_desc, 1878 struct sk_buff *skb) 1879 { 1880 struct net_device *netdev = rx_ring->netdev; 1881 1882 /* XDP packets use error pointer so abort at this point */ 1883 if (IS_ERR(skb)) 1884 return true; 1885 1886 /* Verify netdev is present, and that packet does not have any 1887 * errors that would be unacceptable to the netdev. 1888 */ 1889 if (!netdev || 1890 (unlikely(ixgbe_test_staterr(rx_desc, 1891 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1892 !(netdev->features & NETIF_F_RXALL)))) { 1893 dev_kfree_skb_any(skb); 1894 return true; 1895 } 1896 1897 /* place header in linear portion of buffer */ 1898 if (!skb_headlen(skb)) 1899 ixgbe_pull_tail(rx_ring, skb); 1900 1901 #ifdef IXGBE_FCOE 1902 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1903 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1904 return false; 1905 1906 #endif 1907 /* if eth_skb_pad returns an error the skb was freed */ 1908 if (eth_skb_pad(skb)) 1909 return true; 1910 1911 return false; 1912 } 1913 1914 /** 1915 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1916 * @rx_ring: rx descriptor ring to store buffers on 1917 * @old_buff: donor buffer to have page reused 1918 * 1919 * Synchronizes page for reuse by the adapter 1920 **/ 1921 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1922 struct ixgbe_rx_buffer *old_buff) 1923 { 1924 struct ixgbe_rx_buffer *new_buff; 1925 u16 nta = rx_ring->next_to_alloc; 1926 1927 new_buff = &rx_ring->rx_buffer_info[nta]; 1928 1929 /* update, and store next to alloc */ 1930 nta++; 1931 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1932 1933 /* Transfer page from old buffer to new buffer. 1934 * Move each member individually to avoid possible store 1935 * forwarding stalls and unnecessary copy of skb. 1936 */ 1937 new_buff->dma = old_buff->dma; 1938 new_buff->page = old_buff->page; 1939 new_buff->page_offset = old_buff->page_offset; 1940 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1941 } 1942 1943 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 1944 int rx_buffer_pgcnt) 1945 { 1946 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1947 struct page *page = rx_buffer->page; 1948 1949 /* avoid re-using remote and pfmemalloc pages */ 1950 if (!dev_page_is_reusable(page)) 1951 return false; 1952 1953 #if (PAGE_SIZE < 8192) 1954 /* if we are only owner of page we can reuse it */ 1955 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1956 return false; 1957 #else 1958 /* The last offset is a bit aggressive in that we assume the 1959 * worst case of FCoE being enabled and using a 3K buffer. 1960 * However this should have minimal impact as the 1K extra is 1961 * still less than one buffer in size. 1962 */ 1963 #define IXGBE_LAST_OFFSET \ 1964 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1965 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1966 return false; 1967 #endif 1968 1969 /* If we have drained the page fragment pool we need to update 1970 * the pagecnt_bias and page count so that we fully restock the 1971 * number of references the driver holds. 1972 */ 1973 if (unlikely(pagecnt_bias == 1)) { 1974 page_ref_add(page, USHRT_MAX - 1); 1975 rx_buffer->pagecnt_bias = USHRT_MAX; 1976 } 1977 1978 return true; 1979 } 1980 1981 /** 1982 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1983 * @rx_ring: rx descriptor ring to transact packets on 1984 * @rx_buffer: buffer containing page to add 1985 * @skb: sk_buff to place the data into 1986 * @size: size of data in rx_buffer 1987 * 1988 * This function will add the data contained in rx_buffer->page to the skb. 1989 * This is done either through a direct copy if the data in the buffer is 1990 * less than the skb header size, otherwise it will just attach the page as 1991 * a frag to the skb. 1992 * 1993 * The function will then update the page offset if necessary and return 1994 * true if the buffer can be reused by the adapter. 1995 **/ 1996 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1997 struct ixgbe_rx_buffer *rx_buffer, 1998 struct sk_buff *skb, 1999 unsigned int size) 2000 { 2001 #if (PAGE_SIZE < 8192) 2002 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2003 #else 2004 unsigned int truesize = rx_ring->rx_offset ? 2005 SKB_DATA_ALIGN(rx_ring->rx_offset + size) : 2006 SKB_DATA_ALIGN(size); 2007 #endif 2008 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2009 rx_buffer->page_offset, size, truesize); 2010 #if (PAGE_SIZE < 8192) 2011 rx_buffer->page_offset ^= truesize; 2012 #else 2013 rx_buffer->page_offset += truesize; 2014 #endif 2015 } 2016 2017 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2018 union ixgbe_adv_rx_desc *rx_desc, 2019 struct sk_buff **skb, 2020 const unsigned int size, 2021 int *rx_buffer_pgcnt) 2022 { 2023 struct ixgbe_rx_buffer *rx_buffer; 2024 2025 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2026 *rx_buffer_pgcnt = 2027 #if (PAGE_SIZE < 8192) 2028 page_count(rx_buffer->page); 2029 #else 2030 0; 2031 #endif 2032 prefetchw(rx_buffer->page); 2033 *skb = rx_buffer->skb; 2034 2035 /* Delay unmapping of the first packet. It carries the header 2036 * information, HW may still access the header after the writeback. 2037 * Only unmap it when EOP is reached 2038 */ 2039 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2040 if (!*skb) 2041 goto skip_sync; 2042 } else { 2043 if (*skb) 2044 ixgbe_dma_sync_frag(rx_ring, *skb); 2045 } 2046 2047 /* we are reusing so sync this buffer for CPU use */ 2048 dma_sync_single_range_for_cpu(rx_ring->dev, 2049 rx_buffer->dma, 2050 rx_buffer->page_offset, 2051 size, 2052 DMA_FROM_DEVICE); 2053 skip_sync: 2054 rx_buffer->pagecnt_bias--; 2055 2056 return rx_buffer; 2057 } 2058 2059 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2060 struct ixgbe_rx_buffer *rx_buffer, 2061 struct sk_buff *skb, 2062 int rx_buffer_pgcnt) 2063 { 2064 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2065 /* hand second half of page back to the ring */ 2066 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2067 } else { 2068 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2069 /* the page has been released from the ring */ 2070 IXGBE_CB(skb)->page_released = true; 2071 } else { 2072 /* we are not reusing the buffer so unmap it */ 2073 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2074 ixgbe_rx_pg_size(rx_ring), 2075 DMA_FROM_DEVICE, 2076 IXGBE_RX_DMA_ATTR); 2077 } 2078 __page_frag_cache_drain(rx_buffer->page, 2079 rx_buffer->pagecnt_bias); 2080 } 2081 2082 /* clear contents of rx_buffer */ 2083 rx_buffer->page = NULL; 2084 rx_buffer->skb = NULL; 2085 } 2086 2087 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2088 struct ixgbe_rx_buffer *rx_buffer, 2089 struct xdp_buff *xdp, 2090 union ixgbe_adv_rx_desc *rx_desc) 2091 { 2092 unsigned int size = xdp->data_end - xdp->data; 2093 #if (PAGE_SIZE < 8192) 2094 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2095 #else 2096 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2097 xdp->data_hard_start); 2098 #endif 2099 struct sk_buff *skb; 2100 2101 /* prefetch first cache line of first page */ 2102 net_prefetch(xdp->data); 2103 2104 /* Note, we get here by enabling legacy-rx via: 2105 * 2106 * ethtool --set-priv-flags <dev> legacy-rx on 2107 * 2108 * In this mode, we currently get 0 extra XDP headroom as 2109 * opposed to having legacy-rx off, where we process XDP 2110 * packets going to stack via ixgbe_build_skb(). The latter 2111 * provides us currently with 192 bytes of headroom. 2112 * 2113 * For ixgbe_construct_skb() mode it means that the 2114 * xdp->data_meta will always point to xdp->data, since 2115 * the helper cannot expand the head. Should this ever 2116 * change in future for legacy-rx mode on, then lets also 2117 * add xdp->data_meta handling here. 2118 */ 2119 2120 /* allocate a skb to store the frags */ 2121 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2122 if (unlikely(!skb)) 2123 return NULL; 2124 2125 if (size > IXGBE_RX_HDR_SIZE) { 2126 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2127 IXGBE_CB(skb)->dma = rx_buffer->dma; 2128 2129 skb_add_rx_frag(skb, 0, rx_buffer->page, 2130 xdp->data - page_address(rx_buffer->page), 2131 size, truesize); 2132 #if (PAGE_SIZE < 8192) 2133 rx_buffer->page_offset ^= truesize; 2134 #else 2135 rx_buffer->page_offset += truesize; 2136 #endif 2137 } else { 2138 memcpy(__skb_put(skb, size), 2139 xdp->data, ALIGN(size, sizeof(long))); 2140 rx_buffer->pagecnt_bias++; 2141 } 2142 2143 return skb; 2144 } 2145 2146 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2147 struct ixgbe_rx_buffer *rx_buffer, 2148 struct xdp_buff *xdp, 2149 union ixgbe_adv_rx_desc *rx_desc) 2150 { 2151 unsigned int metasize = xdp->data - xdp->data_meta; 2152 #if (PAGE_SIZE < 8192) 2153 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2154 #else 2155 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2156 SKB_DATA_ALIGN(xdp->data_end - 2157 xdp->data_hard_start); 2158 #endif 2159 struct sk_buff *skb; 2160 2161 /* Prefetch first cache line of first page. If xdp->data_meta 2162 * is unused, this points extactly as xdp->data, otherwise we 2163 * likely have a consumer accessing first few bytes of meta 2164 * data, and then actual data. 2165 */ 2166 net_prefetch(xdp->data_meta); 2167 2168 /* build an skb to around the page buffer */ 2169 skb = build_skb(xdp->data_hard_start, truesize); 2170 if (unlikely(!skb)) 2171 return NULL; 2172 2173 /* update pointers within the skb to store the data */ 2174 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2175 __skb_put(skb, xdp->data_end - xdp->data); 2176 if (metasize) 2177 skb_metadata_set(skb, metasize); 2178 2179 /* record DMA address if this is the start of a chain of buffers */ 2180 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2181 IXGBE_CB(skb)->dma = rx_buffer->dma; 2182 2183 /* update buffer offset */ 2184 #if (PAGE_SIZE < 8192) 2185 rx_buffer->page_offset ^= truesize; 2186 #else 2187 rx_buffer->page_offset += truesize; 2188 #endif 2189 2190 return skb; 2191 } 2192 2193 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2194 struct ixgbe_ring *rx_ring, 2195 struct xdp_buff *xdp) 2196 { 2197 int err, result = IXGBE_XDP_PASS; 2198 struct bpf_prog *xdp_prog; 2199 struct xdp_frame *xdpf; 2200 u32 act; 2201 2202 rcu_read_lock(); 2203 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2204 2205 if (!xdp_prog) 2206 goto xdp_out; 2207 2208 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2209 2210 act = bpf_prog_run_xdp(xdp_prog, xdp); 2211 switch (act) { 2212 case XDP_PASS: 2213 break; 2214 case XDP_TX: 2215 xdpf = xdp_convert_buff_to_frame(xdp); 2216 if (unlikely(!xdpf)) { 2217 result = IXGBE_XDP_CONSUMED; 2218 break; 2219 } 2220 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2221 break; 2222 case XDP_REDIRECT: 2223 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2224 if (!err) 2225 result = IXGBE_XDP_REDIR; 2226 else 2227 result = IXGBE_XDP_CONSUMED; 2228 break; 2229 default: 2230 bpf_warn_invalid_xdp_action(act); 2231 fallthrough; 2232 case XDP_ABORTED: 2233 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2234 fallthrough; /* handle aborts by dropping packet */ 2235 case XDP_DROP: 2236 result = IXGBE_XDP_CONSUMED; 2237 break; 2238 } 2239 xdp_out: 2240 rcu_read_unlock(); 2241 return ERR_PTR(-result); 2242 } 2243 2244 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2245 unsigned int size) 2246 { 2247 unsigned int truesize; 2248 2249 #if (PAGE_SIZE < 8192) 2250 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2251 #else 2252 truesize = rx_ring->rx_offset ? 2253 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 2254 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2255 SKB_DATA_ALIGN(size); 2256 #endif 2257 return truesize; 2258 } 2259 2260 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2261 struct ixgbe_rx_buffer *rx_buffer, 2262 unsigned int size) 2263 { 2264 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2265 #if (PAGE_SIZE < 8192) 2266 rx_buffer->page_offset ^= truesize; 2267 #else 2268 rx_buffer->page_offset += truesize; 2269 #endif 2270 } 2271 2272 /** 2273 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2274 * @q_vector: structure containing interrupt and ring information 2275 * @rx_ring: rx descriptor ring to transact packets on 2276 * @budget: Total limit on number of packets to process 2277 * 2278 * This function provides a "bounce buffer" approach to Rx interrupt 2279 * processing. The advantage to this is that on systems that have 2280 * expensive overhead for IOMMU access this provides a means of avoiding 2281 * it by maintaining the mapping of the page to the syste. 2282 * 2283 * Returns amount of work completed 2284 **/ 2285 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2286 struct ixgbe_ring *rx_ring, 2287 const int budget) 2288 { 2289 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; 2290 struct ixgbe_adapter *adapter = q_vector->adapter; 2291 #ifdef IXGBE_FCOE 2292 int ddp_bytes; 2293 unsigned int mss = 0; 2294 #endif /* IXGBE_FCOE */ 2295 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2296 unsigned int offset = rx_ring->rx_offset; 2297 unsigned int xdp_xmit = 0; 2298 struct xdp_buff xdp; 2299 2300 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2301 #if (PAGE_SIZE < 8192) 2302 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2303 #endif 2304 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 2305 2306 while (likely(total_rx_packets < budget)) { 2307 union ixgbe_adv_rx_desc *rx_desc; 2308 struct ixgbe_rx_buffer *rx_buffer; 2309 struct sk_buff *skb; 2310 int rx_buffer_pgcnt; 2311 unsigned int size; 2312 2313 /* return some buffers to hardware, one at a time is too slow */ 2314 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2315 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2316 cleaned_count = 0; 2317 } 2318 2319 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2320 size = le16_to_cpu(rx_desc->wb.upper.length); 2321 if (!size) 2322 break; 2323 2324 /* This memory barrier is needed to keep us from reading 2325 * any other fields out of the rx_desc until we know the 2326 * descriptor has been written back 2327 */ 2328 dma_rmb(); 2329 2330 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2331 2332 /* retrieve a buffer from the ring */ 2333 if (!skb) { 2334 unsigned char *hard_start; 2335 2336 hard_start = page_address(rx_buffer->page) + 2337 rx_buffer->page_offset - offset; 2338 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 2339 #if (PAGE_SIZE > 4096) 2340 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2341 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2342 #endif 2343 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2344 } 2345 2346 if (IS_ERR(skb)) { 2347 unsigned int xdp_res = -PTR_ERR(skb); 2348 2349 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2350 xdp_xmit |= xdp_res; 2351 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2352 } else { 2353 rx_buffer->pagecnt_bias++; 2354 } 2355 total_rx_packets++; 2356 total_rx_bytes += size; 2357 } else if (skb) { 2358 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2359 } else if (ring_uses_build_skb(rx_ring)) { 2360 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2361 &xdp, rx_desc); 2362 } else { 2363 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2364 &xdp, rx_desc); 2365 } 2366 2367 /* exit if we failed to retrieve a buffer */ 2368 if (!skb) { 2369 rx_ring->rx_stats.alloc_rx_buff_failed++; 2370 rx_buffer->pagecnt_bias++; 2371 break; 2372 } 2373 2374 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2375 cleaned_count++; 2376 2377 /* place incomplete frames back on ring for completion */ 2378 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2379 continue; 2380 2381 /* verify the packet layout is correct */ 2382 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2383 continue; 2384 2385 /* probably a little skewed due to removing CRC */ 2386 total_rx_bytes += skb->len; 2387 2388 /* populate checksum, timestamp, VLAN, and protocol */ 2389 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2390 2391 #ifdef IXGBE_FCOE 2392 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2393 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2394 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2395 /* include DDPed FCoE data */ 2396 if (ddp_bytes > 0) { 2397 if (!mss) { 2398 mss = rx_ring->netdev->mtu - 2399 sizeof(struct fcoe_hdr) - 2400 sizeof(struct fc_frame_header) - 2401 sizeof(struct fcoe_crc_eof); 2402 if (mss > 512) 2403 mss &= ~511; 2404 } 2405 total_rx_bytes += ddp_bytes; 2406 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2407 mss); 2408 } 2409 if (!ddp_bytes) { 2410 dev_kfree_skb_any(skb); 2411 continue; 2412 } 2413 } 2414 2415 #endif /* IXGBE_FCOE */ 2416 ixgbe_rx_skb(q_vector, skb); 2417 2418 /* update budget accounting */ 2419 total_rx_packets++; 2420 } 2421 2422 if (xdp_xmit & IXGBE_XDP_REDIR) 2423 xdp_do_flush_map(); 2424 2425 if (xdp_xmit & IXGBE_XDP_TX) { 2426 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2427 2428 /* Force memory writes to complete before letting h/w 2429 * know there are new descriptors to fetch. 2430 */ 2431 wmb(); 2432 writel(ring->next_to_use, ring->tail); 2433 } 2434 2435 u64_stats_update_begin(&rx_ring->syncp); 2436 rx_ring->stats.packets += total_rx_packets; 2437 rx_ring->stats.bytes += total_rx_bytes; 2438 u64_stats_update_end(&rx_ring->syncp); 2439 q_vector->rx.total_packets += total_rx_packets; 2440 q_vector->rx.total_bytes += total_rx_bytes; 2441 2442 return total_rx_packets; 2443 } 2444 2445 /** 2446 * ixgbe_configure_msix - Configure MSI-X hardware 2447 * @adapter: board private structure 2448 * 2449 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2450 * interrupts. 2451 **/ 2452 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2453 { 2454 struct ixgbe_q_vector *q_vector; 2455 int v_idx; 2456 u32 mask; 2457 2458 /* Populate MSIX to EITR Select */ 2459 if (adapter->num_vfs > 32) { 2460 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2462 } 2463 2464 /* 2465 * Populate the IVAR table and set the ITR values to the 2466 * corresponding register. 2467 */ 2468 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2469 struct ixgbe_ring *ring; 2470 q_vector = adapter->q_vector[v_idx]; 2471 2472 ixgbe_for_each_ring(ring, q_vector->rx) 2473 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2474 2475 ixgbe_for_each_ring(ring, q_vector->tx) 2476 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2477 2478 ixgbe_write_eitr(q_vector); 2479 } 2480 2481 switch (adapter->hw.mac.type) { 2482 case ixgbe_mac_82598EB: 2483 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2484 v_idx); 2485 break; 2486 case ixgbe_mac_82599EB: 2487 case ixgbe_mac_X540: 2488 case ixgbe_mac_X550: 2489 case ixgbe_mac_X550EM_x: 2490 case ixgbe_mac_x550em_a: 2491 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2492 break; 2493 default: 2494 break; 2495 } 2496 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2497 2498 /* set up to autoclear timer, and the vectors */ 2499 mask = IXGBE_EIMS_ENABLE_MASK; 2500 mask &= ~(IXGBE_EIMS_OTHER | 2501 IXGBE_EIMS_MAILBOX | 2502 IXGBE_EIMS_LSC); 2503 2504 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2505 } 2506 2507 /** 2508 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2509 * @q_vector: structure containing interrupt and ring information 2510 * @ring_container: structure containing ring performance data 2511 * 2512 * Stores a new ITR value based on packets and byte 2513 * counts during the last interrupt. The advantage of per interrupt 2514 * computation is faster updates and more accurate ITR for the current 2515 * traffic pattern. Constants in this function were computed 2516 * based on theoretical maximum wire speed and thresholds were set based 2517 * on testing data as well as attempting to minimize response time 2518 * while increasing bulk throughput. 2519 **/ 2520 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2521 struct ixgbe_ring_container *ring_container) 2522 { 2523 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2524 IXGBE_ITR_ADAPTIVE_LATENCY; 2525 unsigned int avg_wire_size, packets, bytes; 2526 unsigned long next_update = jiffies; 2527 2528 /* If we don't have any rings just leave ourselves set for maximum 2529 * possible latency so we take ourselves out of the equation. 2530 */ 2531 if (!ring_container->ring) 2532 return; 2533 2534 /* If we didn't update within up to 1 - 2 jiffies we can assume 2535 * that either packets are coming in so slow there hasn't been 2536 * any work, or that there is so much work that NAPI is dealing 2537 * with interrupt moderation and we don't need to do anything. 2538 */ 2539 if (time_after(next_update, ring_container->next_update)) 2540 goto clear_counts; 2541 2542 packets = ring_container->total_packets; 2543 2544 /* We have no packets to actually measure against. This means 2545 * either one of the other queues on this vector is active or 2546 * we are a Tx queue doing TSO with too high of an interrupt rate. 2547 * 2548 * When this occurs just tick up our delay by the minimum value 2549 * and hope that this extra delay will prevent us from being called 2550 * without any work on our queue. 2551 */ 2552 if (!packets) { 2553 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2554 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2555 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2556 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2557 goto clear_counts; 2558 } 2559 2560 bytes = ring_container->total_bytes; 2561 2562 /* If packets are less than 4 or bytes are less than 9000 assume 2563 * insufficient data to use bulk rate limiting approach. We are 2564 * likely latency driven. 2565 */ 2566 if (packets < 4 && bytes < 9000) { 2567 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2568 goto adjust_by_size; 2569 } 2570 2571 /* Between 4 and 48 we can assume that our current interrupt delay 2572 * is only slightly too low. As such we should increase it by a small 2573 * fixed amount. 2574 */ 2575 if (packets < 48) { 2576 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2577 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2578 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2579 goto clear_counts; 2580 } 2581 2582 /* Between 48 and 96 is our "goldilocks" zone where we are working 2583 * out "just right". Just report that our current ITR is good for us. 2584 */ 2585 if (packets < 96) { 2586 itr = q_vector->itr >> 2; 2587 goto clear_counts; 2588 } 2589 2590 /* If packet count is 96 or greater we are likely looking at a slight 2591 * overrun of the delay we want. Try halving our delay to see if that 2592 * will cut the number of packets in half per interrupt. 2593 */ 2594 if (packets < 256) { 2595 itr = q_vector->itr >> 3; 2596 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2597 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2598 goto clear_counts; 2599 } 2600 2601 /* The paths below assume we are dealing with a bulk ITR since number 2602 * of packets is 256 or greater. We are just going to have to compute 2603 * a value and try to bring the count under control, though for smaller 2604 * packet sizes there isn't much we can do as NAPI polling will likely 2605 * be kicking in sooner rather than later. 2606 */ 2607 itr = IXGBE_ITR_ADAPTIVE_BULK; 2608 2609 adjust_by_size: 2610 /* If packet counts are 256 or greater we can assume we have a gross 2611 * overestimation of what the rate should be. Instead of trying to fine 2612 * tune it just use the formula below to try and dial in an exact value 2613 * give the current packet size of the frame. 2614 */ 2615 avg_wire_size = bytes / packets; 2616 2617 /* The following is a crude approximation of: 2618 * wmem_default / (size + overhead) = desired_pkts_per_int 2619 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2620 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2621 * 2622 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2623 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2624 * formula down to 2625 * 2626 * (170 * (size + 24)) / (size + 640) = ITR 2627 * 2628 * We first do some math on the packet size and then finally bitshift 2629 * by 8 after rounding up. We also have to account for PCIe link speed 2630 * difference as ITR scales based on this. 2631 */ 2632 if (avg_wire_size <= 60) { 2633 /* Start at 50k ints/sec */ 2634 avg_wire_size = 5120; 2635 } else if (avg_wire_size <= 316) { 2636 /* 50K ints/sec to 16K ints/sec */ 2637 avg_wire_size *= 40; 2638 avg_wire_size += 2720; 2639 } else if (avg_wire_size <= 1084) { 2640 /* 16K ints/sec to 9.2K ints/sec */ 2641 avg_wire_size *= 15; 2642 avg_wire_size += 11452; 2643 } else if (avg_wire_size < 1968) { 2644 /* 9.2K ints/sec to 8K ints/sec */ 2645 avg_wire_size *= 5; 2646 avg_wire_size += 22420; 2647 } else { 2648 /* plateau at a limit of 8K ints/sec */ 2649 avg_wire_size = 32256; 2650 } 2651 2652 /* If we are in low latency mode half our delay which doubles the rate 2653 * to somewhere between 100K to 16K ints/sec 2654 */ 2655 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2656 avg_wire_size >>= 1; 2657 2658 /* Resultant value is 256 times larger than it needs to be. This 2659 * gives us room to adjust the value as needed to either increase 2660 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2661 * 2662 * Use addition as we have already recorded the new latency flag 2663 * for the ITR value. 2664 */ 2665 switch (q_vector->adapter->link_speed) { 2666 case IXGBE_LINK_SPEED_10GB_FULL: 2667 case IXGBE_LINK_SPEED_100_FULL: 2668 default: 2669 itr += DIV_ROUND_UP(avg_wire_size, 2670 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2671 IXGBE_ITR_ADAPTIVE_MIN_INC; 2672 break; 2673 case IXGBE_LINK_SPEED_2_5GB_FULL: 2674 case IXGBE_LINK_SPEED_1GB_FULL: 2675 case IXGBE_LINK_SPEED_10_FULL: 2676 if (avg_wire_size > 8064) 2677 avg_wire_size = 8064; 2678 itr += DIV_ROUND_UP(avg_wire_size, 2679 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2680 IXGBE_ITR_ADAPTIVE_MIN_INC; 2681 break; 2682 } 2683 2684 clear_counts: 2685 /* write back value */ 2686 ring_container->itr = itr; 2687 2688 /* next update should occur within next jiffy */ 2689 ring_container->next_update = next_update + 1; 2690 2691 ring_container->total_bytes = 0; 2692 ring_container->total_packets = 0; 2693 } 2694 2695 /** 2696 * ixgbe_write_eitr - write EITR register in hardware specific way 2697 * @q_vector: structure containing interrupt and ring information 2698 * 2699 * This function is made to be called by ethtool and by the driver 2700 * when it needs to update EITR registers at runtime. Hardware 2701 * specific quirks/differences are taken care of here. 2702 */ 2703 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2704 { 2705 struct ixgbe_adapter *adapter = q_vector->adapter; 2706 struct ixgbe_hw *hw = &adapter->hw; 2707 int v_idx = q_vector->v_idx; 2708 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2709 2710 switch (adapter->hw.mac.type) { 2711 case ixgbe_mac_82598EB: 2712 /* must write high and low 16 bits to reset counter */ 2713 itr_reg |= (itr_reg << 16); 2714 break; 2715 case ixgbe_mac_82599EB: 2716 case ixgbe_mac_X540: 2717 case ixgbe_mac_X550: 2718 case ixgbe_mac_X550EM_x: 2719 case ixgbe_mac_x550em_a: 2720 /* 2721 * set the WDIS bit to not clear the timer bits and cause an 2722 * immediate assertion of the interrupt 2723 */ 2724 itr_reg |= IXGBE_EITR_CNT_WDIS; 2725 break; 2726 default: 2727 break; 2728 } 2729 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2730 } 2731 2732 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2733 { 2734 u32 new_itr; 2735 2736 ixgbe_update_itr(q_vector, &q_vector->tx); 2737 ixgbe_update_itr(q_vector, &q_vector->rx); 2738 2739 /* use the smallest value of new ITR delay calculations */ 2740 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2741 2742 /* Clear latency flag if set, shift into correct position */ 2743 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2744 new_itr <<= 2; 2745 2746 if (new_itr != q_vector->itr) { 2747 /* save the algorithm value here */ 2748 q_vector->itr = new_itr; 2749 2750 ixgbe_write_eitr(q_vector); 2751 } 2752 } 2753 2754 /** 2755 * ixgbe_check_overtemp_subtask - check for over temperature 2756 * @adapter: pointer to adapter 2757 **/ 2758 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2759 { 2760 struct ixgbe_hw *hw = &adapter->hw; 2761 u32 eicr = adapter->interrupt_event; 2762 s32 rc; 2763 2764 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2765 return; 2766 2767 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2768 return; 2769 2770 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2771 2772 switch (hw->device_id) { 2773 case IXGBE_DEV_ID_82599_T3_LOM: 2774 /* 2775 * Since the warning interrupt is for both ports 2776 * we don't have to check if: 2777 * - This interrupt wasn't for our port. 2778 * - We may have missed the interrupt so always have to 2779 * check if we got a LSC 2780 */ 2781 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2782 !(eicr & IXGBE_EICR_LSC)) 2783 return; 2784 2785 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2786 u32 speed; 2787 bool link_up = false; 2788 2789 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2790 2791 if (link_up) 2792 return; 2793 } 2794 2795 /* Check if this is not due to overtemp */ 2796 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2797 return; 2798 2799 break; 2800 case IXGBE_DEV_ID_X550EM_A_1G_T: 2801 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2802 rc = hw->phy.ops.check_overtemp(hw); 2803 if (rc != IXGBE_ERR_OVERTEMP) 2804 return; 2805 break; 2806 default: 2807 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2808 return; 2809 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2810 return; 2811 break; 2812 } 2813 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2814 2815 adapter->interrupt_event = 0; 2816 } 2817 2818 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2819 { 2820 struct ixgbe_hw *hw = &adapter->hw; 2821 2822 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2823 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2824 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2825 /* write to clear the interrupt */ 2826 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2827 } 2828 } 2829 2830 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2831 { 2832 struct ixgbe_hw *hw = &adapter->hw; 2833 2834 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2835 return; 2836 2837 switch (adapter->hw.mac.type) { 2838 case ixgbe_mac_82599EB: 2839 /* 2840 * Need to check link state so complete overtemp check 2841 * on service task 2842 */ 2843 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2844 (eicr & IXGBE_EICR_LSC)) && 2845 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2846 adapter->interrupt_event = eicr; 2847 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2848 ixgbe_service_event_schedule(adapter); 2849 return; 2850 } 2851 return; 2852 case ixgbe_mac_x550em_a: 2853 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2854 adapter->interrupt_event = eicr; 2855 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2856 ixgbe_service_event_schedule(adapter); 2857 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2858 IXGBE_EICR_GPI_SDP0_X550EM_a); 2859 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2860 IXGBE_EICR_GPI_SDP0_X550EM_a); 2861 } 2862 return; 2863 case ixgbe_mac_X550: 2864 case ixgbe_mac_X540: 2865 if (!(eicr & IXGBE_EICR_TS)) 2866 return; 2867 break; 2868 default: 2869 return; 2870 } 2871 2872 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2873 } 2874 2875 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2876 { 2877 switch (hw->mac.type) { 2878 case ixgbe_mac_82598EB: 2879 if (hw->phy.type == ixgbe_phy_nl) 2880 return true; 2881 return false; 2882 case ixgbe_mac_82599EB: 2883 case ixgbe_mac_X550EM_x: 2884 case ixgbe_mac_x550em_a: 2885 switch (hw->mac.ops.get_media_type(hw)) { 2886 case ixgbe_media_type_fiber: 2887 case ixgbe_media_type_fiber_qsfp: 2888 return true; 2889 default: 2890 return false; 2891 } 2892 default: 2893 return false; 2894 } 2895 } 2896 2897 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2898 { 2899 struct ixgbe_hw *hw = &adapter->hw; 2900 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2901 2902 if (!ixgbe_is_sfp(hw)) 2903 return; 2904 2905 /* Later MAC's use different SDP */ 2906 if (hw->mac.type >= ixgbe_mac_X540) 2907 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2908 2909 if (eicr & eicr_mask) { 2910 /* Clear the interrupt */ 2911 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2912 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2913 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2914 adapter->sfp_poll_time = 0; 2915 ixgbe_service_event_schedule(adapter); 2916 } 2917 } 2918 2919 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2920 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2921 /* Clear the interrupt */ 2922 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2923 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2924 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2925 ixgbe_service_event_schedule(adapter); 2926 } 2927 } 2928 } 2929 2930 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2931 { 2932 struct ixgbe_hw *hw = &adapter->hw; 2933 2934 adapter->lsc_int++; 2935 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2936 adapter->link_check_timeout = jiffies; 2937 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2938 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2939 IXGBE_WRITE_FLUSH(hw); 2940 ixgbe_service_event_schedule(adapter); 2941 } 2942 } 2943 2944 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2945 u64 qmask) 2946 { 2947 u32 mask; 2948 struct ixgbe_hw *hw = &adapter->hw; 2949 2950 switch (hw->mac.type) { 2951 case ixgbe_mac_82598EB: 2952 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2953 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2954 break; 2955 case ixgbe_mac_82599EB: 2956 case ixgbe_mac_X540: 2957 case ixgbe_mac_X550: 2958 case ixgbe_mac_X550EM_x: 2959 case ixgbe_mac_x550em_a: 2960 mask = (qmask & 0xFFFFFFFF); 2961 if (mask) 2962 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2963 mask = (qmask >> 32); 2964 if (mask) 2965 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2966 break; 2967 default: 2968 break; 2969 } 2970 /* skip the flush */ 2971 } 2972 2973 /** 2974 * ixgbe_irq_enable - Enable default interrupt generation settings 2975 * @adapter: board private structure 2976 * @queues: enable irqs for queues 2977 * @flush: flush register write 2978 **/ 2979 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2980 bool flush) 2981 { 2982 struct ixgbe_hw *hw = &adapter->hw; 2983 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2984 2985 /* don't reenable LSC while waiting for link */ 2986 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2987 mask &= ~IXGBE_EIMS_LSC; 2988 2989 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2990 switch (adapter->hw.mac.type) { 2991 case ixgbe_mac_82599EB: 2992 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2993 break; 2994 case ixgbe_mac_X540: 2995 case ixgbe_mac_X550: 2996 case ixgbe_mac_X550EM_x: 2997 case ixgbe_mac_x550em_a: 2998 mask |= IXGBE_EIMS_TS; 2999 break; 3000 default: 3001 break; 3002 } 3003 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3004 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3005 switch (adapter->hw.mac.type) { 3006 case ixgbe_mac_82599EB: 3007 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3008 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3009 fallthrough; 3010 case ixgbe_mac_X540: 3011 case ixgbe_mac_X550: 3012 case ixgbe_mac_X550EM_x: 3013 case ixgbe_mac_x550em_a: 3014 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3015 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3016 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3017 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3018 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3019 mask |= IXGBE_EICR_GPI_SDP0_X540; 3020 mask |= IXGBE_EIMS_ECC; 3021 mask |= IXGBE_EIMS_MAILBOX; 3022 break; 3023 default: 3024 break; 3025 } 3026 3027 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3028 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3029 mask |= IXGBE_EIMS_FLOW_DIR; 3030 3031 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3032 if (queues) 3033 ixgbe_irq_enable_queues(adapter, ~0); 3034 if (flush) 3035 IXGBE_WRITE_FLUSH(&adapter->hw); 3036 } 3037 3038 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3039 { 3040 struct ixgbe_adapter *adapter = data; 3041 struct ixgbe_hw *hw = &adapter->hw; 3042 u32 eicr; 3043 3044 /* 3045 * Workaround for Silicon errata. Use clear-by-write instead 3046 * of clear-by-read. Reading with EICS will return the 3047 * interrupt causes without clearing, which later be done 3048 * with the write to EICR. 3049 */ 3050 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3051 3052 /* The lower 16bits of the EICR register are for the queue interrupts 3053 * which should be masked here in order to not accidentally clear them if 3054 * the bits are high when ixgbe_msix_other is called. There is a race 3055 * condition otherwise which results in possible performance loss 3056 * especially if the ixgbe_msix_other interrupt is triggering 3057 * consistently (as it would when PPS is turned on for the X540 device) 3058 */ 3059 eicr &= 0xFFFF0000; 3060 3061 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3062 3063 if (eicr & IXGBE_EICR_LSC) 3064 ixgbe_check_lsc(adapter); 3065 3066 if (eicr & IXGBE_EICR_MAILBOX) 3067 ixgbe_msg_task(adapter); 3068 3069 switch (hw->mac.type) { 3070 case ixgbe_mac_82599EB: 3071 case ixgbe_mac_X540: 3072 case ixgbe_mac_X550: 3073 case ixgbe_mac_X550EM_x: 3074 case ixgbe_mac_x550em_a: 3075 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3076 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3077 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3078 ixgbe_service_event_schedule(adapter); 3079 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3080 IXGBE_EICR_GPI_SDP0_X540); 3081 } 3082 if (eicr & IXGBE_EICR_ECC) { 3083 e_info(link, "Received ECC Err, initiating reset\n"); 3084 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3085 ixgbe_service_event_schedule(adapter); 3086 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3087 } 3088 /* Handle Flow Director Full threshold interrupt */ 3089 if (eicr & IXGBE_EICR_FLOW_DIR) { 3090 int reinit_count = 0; 3091 int i; 3092 for (i = 0; i < adapter->num_tx_queues; i++) { 3093 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3094 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3095 &ring->state)) 3096 reinit_count++; 3097 } 3098 if (reinit_count) { 3099 /* no more flow director interrupts until after init */ 3100 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3101 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3102 ixgbe_service_event_schedule(adapter); 3103 } 3104 } 3105 ixgbe_check_sfp_event(adapter, eicr); 3106 ixgbe_check_overtemp_event(adapter, eicr); 3107 break; 3108 default: 3109 break; 3110 } 3111 3112 ixgbe_check_fan_failure(adapter, eicr); 3113 3114 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3115 ixgbe_ptp_check_pps_event(adapter); 3116 3117 /* re-enable the original interrupt state, no lsc, no queues */ 3118 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3119 ixgbe_irq_enable(adapter, false, false); 3120 3121 return IRQ_HANDLED; 3122 } 3123 3124 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3125 { 3126 struct ixgbe_q_vector *q_vector = data; 3127 3128 /* EIAM disabled interrupts (on this vector) for us */ 3129 3130 if (q_vector->rx.ring || q_vector->tx.ring) 3131 napi_schedule_irqoff(&q_vector->napi); 3132 3133 return IRQ_HANDLED; 3134 } 3135 3136 /** 3137 * ixgbe_poll - NAPI Rx polling callback 3138 * @napi: structure for representing this polling device 3139 * @budget: how many packets driver is allowed to clean 3140 * 3141 * This function is used for legacy and MSI, NAPI mode 3142 **/ 3143 int ixgbe_poll(struct napi_struct *napi, int budget) 3144 { 3145 struct ixgbe_q_vector *q_vector = 3146 container_of(napi, struct ixgbe_q_vector, napi); 3147 struct ixgbe_adapter *adapter = q_vector->adapter; 3148 struct ixgbe_ring *ring; 3149 int per_ring_budget, work_done = 0; 3150 bool clean_complete = true; 3151 3152 #ifdef CONFIG_IXGBE_DCA 3153 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3154 ixgbe_update_dca(q_vector); 3155 #endif 3156 3157 ixgbe_for_each_ring(ring, q_vector->tx) { 3158 bool wd = ring->xsk_pool ? 3159 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3160 ixgbe_clean_tx_irq(q_vector, ring, budget); 3161 3162 if (!wd) 3163 clean_complete = false; 3164 } 3165 3166 /* Exit if we are called by netpoll */ 3167 if (budget <= 0) 3168 return budget; 3169 3170 /* attempt to distribute budget to each queue fairly, but don't allow 3171 * the budget to go below 1 because we'll exit polling */ 3172 if (q_vector->rx.count > 1) 3173 per_ring_budget = max(budget/q_vector->rx.count, 1); 3174 else 3175 per_ring_budget = budget; 3176 3177 ixgbe_for_each_ring(ring, q_vector->rx) { 3178 int cleaned = ring->xsk_pool ? 3179 ixgbe_clean_rx_irq_zc(q_vector, ring, 3180 per_ring_budget) : 3181 ixgbe_clean_rx_irq(q_vector, ring, 3182 per_ring_budget); 3183 3184 work_done += cleaned; 3185 if (cleaned >= per_ring_budget) 3186 clean_complete = false; 3187 } 3188 3189 /* If all work not completed, return budget and keep polling */ 3190 if (!clean_complete) 3191 return budget; 3192 3193 /* all work done, exit the polling mode */ 3194 if (likely(napi_complete_done(napi, work_done))) { 3195 if (adapter->rx_itr_setting & 1) 3196 ixgbe_set_itr(q_vector); 3197 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3198 ixgbe_irq_enable_queues(adapter, 3199 BIT_ULL(q_vector->v_idx)); 3200 } 3201 3202 return min(work_done, budget - 1); 3203 } 3204 3205 /** 3206 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3207 * @adapter: board private structure 3208 * 3209 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3210 * interrupts from the kernel. 3211 **/ 3212 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3213 { 3214 struct net_device *netdev = adapter->netdev; 3215 unsigned int ri = 0, ti = 0; 3216 int vector, err; 3217 3218 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3219 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3220 struct msix_entry *entry = &adapter->msix_entries[vector]; 3221 3222 if (q_vector->tx.ring && q_vector->rx.ring) { 3223 snprintf(q_vector->name, sizeof(q_vector->name), 3224 "%s-TxRx-%u", netdev->name, ri++); 3225 ti++; 3226 } else if (q_vector->rx.ring) { 3227 snprintf(q_vector->name, sizeof(q_vector->name), 3228 "%s-rx-%u", netdev->name, ri++); 3229 } else if (q_vector->tx.ring) { 3230 snprintf(q_vector->name, sizeof(q_vector->name), 3231 "%s-tx-%u", netdev->name, ti++); 3232 } else { 3233 /* skip this unused q_vector */ 3234 continue; 3235 } 3236 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3237 q_vector->name, q_vector); 3238 if (err) { 3239 e_err(probe, "request_irq failed for MSIX interrupt " 3240 "Error: %d\n", err); 3241 goto free_queue_irqs; 3242 } 3243 /* If Flow Director is enabled, set interrupt affinity */ 3244 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3245 /* assign the mask for this irq */ 3246 irq_set_affinity_hint(entry->vector, 3247 &q_vector->affinity_mask); 3248 } 3249 } 3250 3251 err = request_irq(adapter->msix_entries[vector].vector, 3252 ixgbe_msix_other, 0, netdev->name, adapter); 3253 if (err) { 3254 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3255 goto free_queue_irqs; 3256 } 3257 3258 return 0; 3259 3260 free_queue_irqs: 3261 while (vector) { 3262 vector--; 3263 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3264 NULL); 3265 free_irq(adapter->msix_entries[vector].vector, 3266 adapter->q_vector[vector]); 3267 } 3268 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3269 pci_disable_msix(adapter->pdev); 3270 kfree(adapter->msix_entries); 3271 adapter->msix_entries = NULL; 3272 return err; 3273 } 3274 3275 /** 3276 * ixgbe_intr - legacy mode Interrupt Handler 3277 * @irq: interrupt number 3278 * @data: pointer to a network interface device structure 3279 **/ 3280 static irqreturn_t ixgbe_intr(int irq, void *data) 3281 { 3282 struct ixgbe_adapter *adapter = data; 3283 struct ixgbe_hw *hw = &adapter->hw; 3284 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3285 u32 eicr; 3286 3287 /* 3288 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3289 * before the read of EICR. 3290 */ 3291 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3292 3293 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3294 * therefore no explicit interrupt disable is necessary */ 3295 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3296 if (!eicr) { 3297 /* 3298 * shared interrupt alert! 3299 * make sure interrupts are enabled because the read will 3300 * have disabled interrupts due to EIAM 3301 * finish the workaround of silicon errata on 82598. Unmask 3302 * the interrupt that we masked before the EICR read. 3303 */ 3304 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3305 ixgbe_irq_enable(adapter, true, true); 3306 return IRQ_NONE; /* Not our interrupt */ 3307 } 3308 3309 if (eicr & IXGBE_EICR_LSC) 3310 ixgbe_check_lsc(adapter); 3311 3312 switch (hw->mac.type) { 3313 case ixgbe_mac_82599EB: 3314 ixgbe_check_sfp_event(adapter, eicr); 3315 fallthrough; 3316 case ixgbe_mac_X540: 3317 case ixgbe_mac_X550: 3318 case ixgbe_mac_X550EM_x: 3319 case ixgbe_mac_x550em_a: 3320 if (eicr & IXGBE_EICR_ECC) { 3321 e_info(link, "Received ECC Err, initiating reset\n"); 3322 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3323 ixgbe_service_event_schedule(adapter); 3324 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3325 } 3326 ixgbe_check_overtemp_event(adapter, eicr); 3327 break; 3328 default: 3329 break; 3330 } 3331 3332 ixgbe_check_fan_failure(adapter, eicr); 3333 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3334 ixgbe_ptp_check_pps_event(adapter); 3335 3336 /* would disable interrupts here but EIAM disabled it */ 3337 napi_schedule_irqoff(&q_vector->napi); 3338 3339 /* 3340 * re-enable link(maybe) and non-queue interrupts, no flush. 3341 * ixgbe_poll will re-enable the queue interrupts 3342 */ 3343 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3344 ixgbe_irq_enable(adapter, false, false); 3345 3346 return IRQ_HANDLED; 3347 } 3348 3349 /** 3350 * ixgbe_request_irq - initialize interrupts 3351 * @adapter: board private structure 3352 * 3353 * Attempts to configure interrupts using the best available 3354 * capabilities of the hardware and kernel. 3355 **/ 3356 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3357 { 3358 struct net_device *netdev = adapter->netdev; 3359 int err; 3360 3361 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3362 err = ixgbe_request_msix_irqs(adapter); 3363 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3364 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3365 netdev->name, adapter); 3366 else 3367 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3368 netdev->name, adapter); 3369 3370 if (err) 3371 e_err(probe, "request_irq failed, Error %d\n", err); 3372 3373 return err; 3374 } 3375 3376 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3377 { 3378 int vector; 3379 3380 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3381 free_irq(adapter->pdev->irq, adapter); 3382 return; 3383 } 3384 3385 if (!adapter->msix_entries) 3386 return; 3387 3388 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3389 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3390 struct msix_entry *entry = &adapter->msix_entries[vector]; 3391 3392 /* free only the irqs that were actually requested */ 3393 if (!q_vector->rx.ring && !q_vector->tx.ring) 3394 continue; 3395 3396 /* clear the affinity_mask in the IRQ descriptor */ 3397 irq_set_affinity_hint(entry->vector, NULL); 3398 3399 free_irq(entry->vector, q_vector); 3400 } 3401 3402 free_irq(adapter->msix_entries[vector].vector, adapter); 3403 } 3404 3405 /** 3406 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3407 * @adapter: board private structure 3408 **/ 3409 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3410 { 3411 switch (adapter->hw.mac.type) { 3412 case ixgbe_mac_82598EB: 3413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3414 break; 3415 case ixgbe_mac_82599EB: 3416 case ixgbe_mac_X540: 3417 case ixgbe_mac_X550: 3418 case ixgbe_mac_X550EM_x: 3419 case ixgbe_mac_x550em_a: 3420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3423 break; 3424 default: 3425 break; 3426 } 3427 IXGBE_WRITE_FLUSH(&adapter->hw); 3428 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3429 int vector; 3430 3431 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3432 synchronize_irq(adapter->msix_entries[vector].vector); 3433 3434 synchronize_irq(adapter->msix_entries[vector++].vector); 3435 } else { 3436 synchronize_irq(adapter->pdev->irq); 3437 } 3438 } 3439 3440 /** 3441 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3442 * @adapter: board private structure 3443 * 3444 **/ 3445 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3446 { 3447 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3448 3449 ixgbe_write_eitr(q_vector); 3450 3451 ixgbe_set_ivar(adapter, 0, 0, 0); 3452 ixgbe_set_ivar(adapter, 1, 0, 0); 3453 3454 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3455 } 3456 3457 /** 3458 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3459 * @adapter: board private structure 3460 * @ring: structure containing ring specific data 3461 * 3462 * Configure the Tx descriptor ring after a reset. 3463 **/ 3464 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3465 struct ixgbe_ring *ring) 3466 { 3467 struct ixgbe_hw *hw = &adapter->hw; 3468 u64 tdba = ring->dma; 3469 int wait_loop = 10; 3470 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3471 u8 reg_idx = ring->reg_idx; 3472 3473 ring->xsk_pool = NULL; 3474 if (ring_is_xdp(ring)) 3475 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3476 3477 /* disable queue to avoid issues while updating state */ 3478 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3479 IXGBE_WRITE_FLUSH(hw); 3480 3481 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3482 (tdba & DMA_BIT_MASK(32))); 3483 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3484 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3485 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3486 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3487 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3488 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3489 3490 /* 3491 * set WTHRESH to encourage burst writeback, it should not be set 3492 * higher than 1 when: 3493 * - ITR is 0 as it could cause false TX hangs 3494 * - ITR is set to > 100k int/sec and BQL is enabled 3495 * 3496 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3497 * to or less than the number of on chip descriptors, which is 3498 * currently 40. 3499 */ 3500 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3501 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3502 else 3503 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3504 3505 /* 3506 * Setting PTHRESH to 32 both improves performance 3507 * and avoids a TX hang with DFP enabled 3508 */ 3509 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3510 32; /* PTHRESH = 32 */ 3511 3512 /* reinitialize flowdirector state */ 3513 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3514 ring->atr_sample_rate = adapter->atr_sample_rate; 3515 ring->atr_count = 0; 3516 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3517 } else { 3518 ring->atr_sample_rate = 0; 3519 } 3520 3521 /* initialize XPS */ 3522 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3523 struct ixgbe_q_vector *q_vector = ring->q_vector; 3524 3525 if (q_vector) 3526 netif_set_xps_queue(ring->netdev, 3527 &q_vector->affinity_mask, 3528 ring->queue_index); 3529 } 3530 3531 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3532 3533 /* reinitialize tx_buffer_info */ 3534 memset(ring->tx_buffer_info, 0, 3535 sizeof(struct ixgbe_tx_buffer) * ring->count); 3536 3537 /* enable queue */ 3538 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3539 3540 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3541 if (hw->mac.type == ixgbe_mac_82598EB && 3542 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3543 return; 3544 3545 /* poll to verify queue is enabled */ 3546 do { 3547 usleep_range(1000, 2000); 3548 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3549 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3550 if (!wait_loop) 3551 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3552 } 3553 3554 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3555 { 3556 struct ixgbe_hw *hw = &adapter->hw; 3557 u32 rttdcs, mtqc; 3558 u8 tcs = adapter->hw_tcs; 3559 3560 if (hw->mac.type == ixgbe_mac_82598EB) 3561 return; 3562 3563 /* disable the arbiter while setting MTQC */ 3564 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3565 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3566 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3567 3568 /* set transmit pool layout */ 3569 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3570 mtqc = IXGBE_MTQC_VT_ENA; 3571 if (tcs > 4) 3572 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3573 else if (tcs > 1) 3574 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3575 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3576 IXGBE_82599_VMDQ_4Q_MASK) 3577 mtqc |= IXGBE_MTQC_32VF; 3578 else 3579 mtqc |= IXGBE_MTQC_64VF; 3580 } else { 3581 if (tcs > 4) { 3582 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3583 } else if (tcs > 1) { 3584 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3585 } else { 3586 u8 max_txq = adapter->num_tx_queues + 3587 adapter->num_xdp_queues; 3588 if (max_txq > 63) 3589 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3590 else 3591 mtqc = IXGBE_MTQC_64Q_1PB; 3592 } 3593 } 3594 3595 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3596 3597 /* Enable Security TX Buffer IFG for multiple pb */ 3598 if (tcs) { 3599 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3600 sectx |= IXGBE_SECTX_DCB; 3601 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3602 } 3603 3604 /* re-enable the arbiter */ 3605 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3606 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3607 } 3608 3609 /** 3610 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3611 * @adapter: board private structure 3612 * 3613 * Configure the Tx unit of the MAC after a reset. 3614 **/ 3615 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3616 { 3617 struct ixgbe_hw *hw = &adapter->hw; 3618 u32 dmatxctl; 3619 u32 i; 3620 3621 ixgbe_setup_mtqc(adapter); 3622 3623 if (hw->mac.type != ixgbe_mac_82598EB) { 3624 /* DMATXCTL.EN must be before Tx queues are enabled */ 3625 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3626 dmatxctl |= IXGBE_DMATXCTL_TE; 3627 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3628 } 3629 3630 /* Setup the HW Tx Head and Tail descriptor pointers */ 3631 for (i = 0; i < adapter->num_tx_queues; i++) 3632 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3633 for (i = 0; i < adapter->num_xdp_queues; i++) 3634 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3635 } 3636 3637 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3638 struct ixgbe_ring *ring) 3639 { 3640 struct ixgbe_hw *hw = &adapter->hw; 3641 u8 reg_idx = ring->reg_idx; 3642 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3643 3644 srrctl |= IXGBE_SRRCTL_DROP_EN; 3645 3646 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3647 } 3648 3649 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3650 struct ixgbe_ring *ring) 3651 { 3652 struct ixgbe_hw *hw = &adapter->hw; 3653 u8 reg_idx = ring->reg_idx; 3654 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3655 3656 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3657 3658 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3659 } 3660 3661 #ifdef CONFIG_IXGBE_DCB 3662 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3663 #else 3664 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3665 #endif 3666 { 3667 int i; 3668 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3669 3670 if (adapter->ixgbe_ieee_pfc) 3671 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3672 3673 /* 3674 * We should set the drop enable bit if: 3675 * SR-IOV is enabled 3676 * or 3677 * Number of Rx queues > 1 and flow control is disabled 3678 * 3679 * This allows us to avoid head of line blocking for security 3680 * and performance reasons. 3681 */ 3682 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3683 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3684 for (i = 0; i < adapter->num_rx_queues; i++) 3685 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3686 } else { 3687 for (i = 0; i < adapter->num_rx_queues; i++) 3688 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3689 } 3690 } 3691 3692 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3693 3694 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3695 struct ixgbe_ring *rx_ring) 3696 { 3697 struct ixgbe_hw *hw = &adapter->hw; 3698 u32 srrctl; 3699 u8 reg_idx = rx_ring->reg_idx; 3700 3701 if (hw->mac.type == ixgbe_mac_82598EB) { 3702 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3703 3704 /* 3705 * if VMDq is not active we must program one srrctl register 3706 * per RSS queue since we have enabled RDRXCTL.MVMEN 3707 */ 3708 reg_idx &= mask; 3709 } 3710 3711 /* configure header buffer length, needed for RSC */ 3712 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3713 3714 /* configure the packet buffer length */ 3715 if (rx_ring->xsk_pool) { 3716 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 3717 3718 /* If the MAC support setting RXDCTL.RLPML, the 3719 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3720 * RXDCTL.RLPML is set to the actual UMEM buffer 3721 * size. If not, then we are stuck with a 1k buffer 3722 * size resolution. In this case frames larger than 3723 * the UMEM buffer size viewed in a 1k resolution will 3724 * be dropped. 3725 */ 3726 if (hw->mac.type != ixgbe_mac_82599EB) 3727 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3728 else 3729 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3730 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3731 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3732 } else { 3733 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3734 } 3735 3736 /* configure descriptor type */ 3737 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3738 3739 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3740 } 3741 3742 /** 3743 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3744 * @adapter: device handle 3745 * 3746 * - 82598/82599/X540: 128 3747 * - X550(non-SRIOV mode): 512 3748 * - X550(SRIOV mode): 64 3749 */ 3750 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3751 { 3752 if (adapter->hw.mac.type < ixgbe_mac_X550) 3753 return 128; 3754 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3755 return 64; 3756 else 3757 return 512; 3758 } 3759 3760 /** 3761 * ixgbe_store_key - Write the RSS key to HW 3762 * @adapter: device handle 3763 * 3764 * Write the RSS key stored in adapter.rss_key to HW. 3765 */ 3766 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3767 { 3768 struct ixgbe_hw *hw = &adapter->hw; 3769 int i; 3770 3771 for (i = 0; i < 10; i++) 3772 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3773 } 3774 3775 /** 3776 * ixgbe_init_rss_key - Initialize adapter RSS key 3777 * @adapter: device handle 3778 * 3779 * Allocates and initializes the RSS key if it is not allocated. 3780 **/ 3781 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3782 { 3783 u32 *rss_key; 3784 3785 if (!adapter->rss_key) { 3786 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3787 if (unlikely(!rss_key)) 3788 return -ENOMEM; 3789 3790 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3791 adapter->rss_key = rss_key; 3792 } 3793 3794 return 0; 3795 } 3796 3797 /** 3798 * ixgbe_store_reta - Write the RETA table to HW 3799 * @adapter: device handle 3800 * 3801 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3802 */ 3803 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3804 { 3805 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3806 struct ixgbe_hw *hw = &adapter->hw; 3807 u32 reta = 0; 3808 u32 indices_multi; 3809 u8 *indir_tbl = adapter->rss_indir_tbl; 3810 3811 /* Fill out the redirection table as follows: 3812 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3813 * indices. 3814 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3815 * - X550: 8 bit wide entries containing 6 bit RSS index 3816 */ 3817 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3818 indices_multi = 0x11; 3819 else 3820 indices_multi = 0x1; 3821 3822 /* Write redirection table to HW */ 3823 for (i = 0; i < reta_entries; i++) { 3824 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3825 if ((i & 3) == 3) { 3826 if (i < 128) 3827 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3828 else 3829 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3830 reta); 3831 reta = 0; 3832 } 3833 } 3834 } 3835 3836 /** 3837 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3838 * @adapter: device handle 3839 * 3840 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3841 */ 3842 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3843 { 3844 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3845 struct ixgbe_hw *hw = &adapter->hw; 3846 u32 vfreta = 0; 3847 3848 /* Write redirection table to HW */ 3849 for (i = 0; i < reta_entries; i++) { 3850 u16 pool = adapter->num_rx_pools; 3851 3852 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3853 if ((i & 3) != 3) 3854 continue; 3855 3856 while (pool--) 3857 IXGBE_WRITE_REG(hw, 3858 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3859 vfreta); 3860 vfreta = 0; 3861 } 3862 } 3863 3864 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3865 { 3866 u32 i, j; 3867 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3868 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3869 3870 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3871 * make full use of any rings they may have. We will use the 3872 * PSRTYPE register to control how many rings we use within the PF. 3873 */ 3874 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3875 rss_i = 4; 3876 3877 /* Fill out hash function seeds */ 3878 ixgbe_store_key(adapter); 3879 3880 /* Fill out redirection table */ 3881 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3882 3883 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3884 if (j == rss_i) 3885 j = 0; 3886 3887 adapter->rss_indir_tbl[i] = j; 3888 } 3889 3890 ixgbe_store_reta(adapter); 3891 } 3892 3893 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3894 { 3895 struct ixgbe_hw *hw = &adapter->hw; 3896 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3897 int i, j; 3898 3899 /* Fill out hash function seeds */ 3900 for (i = 0; i < 10; i++) { 3901 u16 pool = adapter->num_rx_pools; 3902 3903 while (pool--) 3904 IXGBE_WRITE_REG(hw, 3905 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3906 *(adapter->rss_key + i)); 3907 } 3908 3909 /* Fill out the redirection table */ 3910 for (i = 0, j = 0; i < 64; i++, j++) { 3911 if (j == rss_i) 3912 j = 0; 3913 3914 adapter->rss_indir_tbl[i] = j; 3915 } 3916 3917 ixgbe_store_vfreta(adapter); 3918 } 3919 3920 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3921 { 3922 struct ixgbe_hw *hw = &adapter->hw; 3923 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3924 u32 rxcsum; 3925 3926 /* Disable indicating checksum in descriptor, enables RSS hash */ 3927 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3928 rxcsum |= IXGBE_RXCSUM_PCSD; 3929 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3930 3931 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3932 if (adapter->ring_feature[RING_F_RSS].mask) 3933 mrqc = IXGBE_MRQC_RSSEN; 3934 } else { 3935 u8 tcs = adapter->hw_tcs; 3936 3937 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3938 if (tcs > 4) 3939 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3940 else if (tcs > 1) 3941 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3942 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3943 IXGBE_82599_VMDQ_4Q_MASK) 3944 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3945 else 3946 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3947 3948 /* Enable L3/L4 for Tx Switched packets only for X550, 3949 * older devices do not support this feature 3950 */ 3951 if (hw->mac.type >= ixgbe_mac_X550) 3952 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3953 } else { 3954 if (tcs > 4) 3955 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3956 else if (tcs > 1) 3957 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3958 else 3959 mrqc = IXGBE_MRQC_RSSEN; 3960 } 3961 } 3962 3963 /* Perform hash on these packet types */ 3964 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3965 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3966 IXGBE_MRQC_RSS_FIELD_IPV6 | 3967 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3968 3969 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3970 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3971 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3972 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3973 3974 if ((hw->mac.type >= ixgbe_mac_X550) && 3975 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3976 u16 pool = adapter->num_rx_pools; 3977 3978 /* Enable VF RSS mode */ 3979 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3980 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3981 3982 /* Setup RSS through the VF registers */ 3983 ixgbe_setup_vfreta(adapter); 3984 vfmrqc = IXGBE_MRQC_RSSEN; 3985 vfmrqc |= rss_field; 3986 3987 while (pool--) 3988 IXGBE_WRITE_REG(hw, 3989 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3990 vfmrqc); 3991 } else { 3992 ixgbe_setup_reta(adapter); 3993 mrqc |= rss_field; 3994 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3995 } 3996 } 3997 3998 /** 3999 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4000 * @adapter: address of board private structure 4001 * @ring: structure containing ring specific data 4002 **/ 4003 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4004 struct ixgbe_ring *ring) 4005 { 4006 struct ixgbe_hw *hw = &adapter->hw; 4007 u32 rscctrl; 4008 u8 reg_idx = ring->reg_idx; 4009 4010 if (!ring_is_rsc_enabled(ring)) 4011 return; 4012 4013 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4014 rscctrl |= IXGBE_RSCCTL_RSCEN; 4015 /* 4016 * we must limit the number of descriptors so that the 4017 * total size of max desc * buf_len is not greater 4018 * than 65536 4019 */ 4020 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4021 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4022 } 4023 4024 #define IXGBE_MAX_RX_DESC_POLL 10 4025 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4026 struct ixgbe_ring *ring) 4027 { 4028 struct ixgbe_hw *hw = &adapter->hw; 4029 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4030 u32 rxdctl; 4031 u8 reg_idx = ring->reg_idx; 4032 4033 if (ixgbe_removed(hw->hw_addr)) 4034 return; 4035 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4036 if (hw->mac.type == ixgbe_mac_82598EB && 4037 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4038 return; 4039 4040 do { 4041 usleep_range(1000, 2000); 4042 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4043 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4044 4045 if (!wait_loop) { 4046 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4047 "the polling period\n", reg_idx); 4048 } 4049 } 4050 4051 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4052 struct ixgbe_ring *ring) 4053 { 4054 struct ixgbe_hw *hw = &adapter->hw; 4055 union ixgbe_adv_rx_desc *rx_desc; 4056 u64 rdba = ring->dma; 4057 u32 rxdctl; 4058 u8 reg_idx = ring->reg_idx; 4059 4060 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4061 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4062 if (ring->xsk_pool) { 4063 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4064 MEM_TYPE_XSK_BUFF_POOL, 4065 NULL)); 4066 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4067 } else { 4068 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4069 MEM_TYPE_PAGE_SHARED, NULL)); 4070 } 4071 4072 /* disable queue to avoid use of these values while updating state */ 4073 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4074 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4075 4076 /* write value back with RXDCTL.ENABLE bit cleared */ 4077 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4078 IXGBE_WRITE_FLUSH(hw); 4079 4080 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4081 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4082 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4083 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4084 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4085 IXGBE_WRITE_FLUSH(hw); 4086 4087 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4088 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4089 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4090 4091 ixgbe_configure_srrctl(adapter, ring); 4092 ixgbe_configure_rscctl(adapter, ring); 4093 4094 if (hw->mac.type == ixgbe_mac_82598EB) { 4095 /* 4096 * enable cache line friendly hardware writes: 4097 * PTHRESH=32 descriptors (half the internal cache), 4098 * this also removes ugly rx_no_buffer_count increment 4099 * HTHRESH=4 descriptors (to minimize latency on fetch) 4100 * WTHRESH=8 burst writeback up to two cache lines 4101 */ 4102 rxdctl &= ~0x3FFFFF; 4103 rxdctl |= 0x080420; 4104 #if (PAGE_SIZE < 8192) 4105 /* RXDCTL.RLPML does not work on 82599 */ 4106 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4107 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4108 IXGBE_RXDCTL_RLPML_EN); 4109 4110 /* Limit the maximum frame size so we don't overrun the skb. 4111 * This can happen in SRIOV mode when the MTU of the VF is 4112 * higher than the MTU of the PF. 4113 */ 4114 if (ring_uses_build_skb(ring) && 4115 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4116 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4117 IXGBE_RXDCTL_RLPML_EN; 4118 #endif 4119 } 4120 4121 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4122 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4123 4124 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4125 IXGBE_RXDCTL_RLPML_EN); 4126 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4127 4128 ring->rx_buf_len = xsk_buf_len; 4129 } 4130 4131 /* initialize rx_buffer_info */ 4132 memset(ring->rx_buffer_info, 0, 4133 sizeof(struct ixgbe_rx_buffer) * ring->count); 4134 4135 /* initialize Rx descriptor 0 */ 4136 rx_desc = IXGBE_RX_DESC(ring, 0); 4137 rx_desc->wb.upper.length = 0; 4138 4139 /* enable receive descriptor ring */ 4140 rxdctl |= IXGBE_RXDCTL_ENABLE; 4141 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4142 4143 ixgbe_rx_desc_queue_enable(adapter, ring); 4144 if (ring->xsk_pool) 4145 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4146 else 4147 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4148 } 4149 4150 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4151 { 4152 struct ixgbe_hw *hw = &adapter->hw; 4153 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4154 u16 pool = adapter->num_rx_pools; 4155 4156 /* PSRTYPE must be initialized in non 82598 adapters */ 4157 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4158 IXGBE_PSRTYPE_UDPHDR | 4159 IXGBE_PSRTYPE_IPV4HDR | 4160 IXGBE_PSRTYPE_L2HDR | 4161 IXGBE_PSRTYPE_IPV6HDR; 4162 4163 if (hw->mac.type == ixgbe_mac_82598EB) 4164 return; 4165 4166 if (rss_i > 3) 4167 psrtype |= 2u << 29; 4168 else if (rss_i > 1) 4169 psrtype |= 1u << 29; 4170 4171 while (pool--) 4172 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4173 } 4174 4175 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4176 { 4177 struct ixgbe_hw *hw = &adapter->hw; 4178 u16 pool = adapter->num_rx_pools; 4179 u32 reg_offset, vf_shift, vmolr; 4180 u32 gcr_ext, vmdctl; 4181 int i; 4182 4183 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4184 return; 4185 4186 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4187 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4188 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4189 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4190 vmdctl |= IXGBE_VT_CTL_REPLEN; 4191 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4192 4193 /* accept untagged packets until a vlan tag is 4194 * specifically set for the VMDQ queue/pool 4195 */ 4196 vmolr = IXGBE_VMOLR_AUPE; 4197 while (pool--) 4198 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4199 4200 vf_shift = VMDQ_P(0) % 32; 4201 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4202 4203 /* Enable only the PF's pool for Tx/Rx */ 4204 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4205 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4206 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4207 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4208 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4209 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4210 4211 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4212 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4213 4214 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4215 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4216 4217 /* 4218 * Set up VF register offsets for selected VT Mode, 4219 * i.e. 32 or 64 VFs for SR-IOV 4220 */ 4221 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4222 case IXGBE_82599_VMDQ_8Q_MASK: 4223 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4224 break; 4225 case IXGBE_82599_VMDQ_4Q_MASK: 4226 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4227 break; 4228 default: 4229 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4230 break; 4231 } 4232 4233 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4234 4235 for (i = 0; i < adapter->num_vfs; i++) { 4236 /* configure spoof checking */ 4237 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4238 adapter->vfinfo[i].spoofchk_enabled); 4239 4240 /* Enable/Disable RSS query feature */ 4241 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4242 adapter->vfinfo[i].rss_query_enabled); 4243 } 4244 } 4245 4246 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4247 { 4248 struct ixgbe_hw *hw = &adapter->hw; 4249 struct net_device *netdev = adapter->netdev; 4250 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4251 struct ixgbe_ring *rx_ring; 4252 int i; 4253 u32 mhadd, hlreg0; 4254 4255 #ifdef IXGBE_FCOE 4256 /* adjust max frame to be able to do baby jumbo for FCoE */ 4257 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4258 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4259 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4260 4261 #endif /* IXGBE_FCOE */ 4262 4263 /* adjust max frame to be at least the size of a standard frame */ 4264 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4265 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4266 4267 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4268 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4269 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4270 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4271 4272 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4273 } 4274 4275 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4276 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4277 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4278 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4279 4280 /* 4281 * Setup the HW Rx Head and Tail Descriptor Pointers and 4282 * the Base and Length of the Rx Descriptor Ring 4283 */ 4284 for (i = 0; i < adapter->num_rx_queues; i++) { 4285 rx_ring = adapter->rx_ring[i]; 4286 4287 clear_ring_rsc_enabled(rx_ring); 4288 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4289 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4290 4291 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4292 set_ring_rsc_enabled(rx_ring); 4293 4294 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4295 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4296 4297 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4298 continue; 4299 4300 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4301 4302 #if (PAGE_SIZE < 8192) 4303 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4304 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4305 4306 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4307 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4308 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4309 #endif 4310 } 4311 } 4312 4313 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4314 { 4315 struct ixgbe_hw *hw = &adapter->hw; 4316 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4317 4318 switch (hw->mac.type) { 4319 case ixgbe_mac_82598EB: 4320 /* 4321 * For VMDq support of different descriptor types or 4322 * buffer sizes through the use of multiple SRRCTL 4323 * registers, RDRXCTL.MVMEN must be set to 1 4324 * 4325 * also, the manual doesn't mention it clearly but DCA hints 4326 * will only use queue 0's tags unless this bit is set. Side 4327 * effects of setting this bit are only that SRRCTL must be 4328 * fully programmed [0..15] 4329 */ 4330 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4331 break; 4332 case ixgbe_mac_X550: 4333 case ixgbe_mac_X550EM_x: 4334 case ixgbe_mac_x550em_a: 4335 if (adapter->num_vfs) 4336 rdrxctl |= IXGBE_RDRXCTL_PSP; 4337 fallthrough; 4338 case ixgbe_mac_82599EB: 4339 case ixgbe_mac_X540: 4340 /* Disable RSC for ACK packets */ 4341 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4342 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4343 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4344 /* hardware requires some bits to be set by default */ 4345 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4346 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4347 break; 4348 default: 4349 /* We should do nothing since we don't know this hardware */ 4350 return; 4351 } 4352 4353 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4354 } 4355 4356 /** 4357 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4358 * @adapter: board private structure 4359 * 4360 * Configure the Rx unit of the MAC after a reset. 4361 **/ 4362 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4363 { 4364 struct ixgbe_hw *hw = &adapter->hw; 4365 int i; 4366 u32 rxctrl, rfctl; 4367 4368 /* disable receives while setting up the descriptors */ 4369 hw->mac.ops.disable_rx(hw); 4370 4371 ixgbe_setup_psrtype(adapter); 4372 ixgbe_setup_rdrxctl(adapter); 4373 4374 /* RSC Setup */ 4375 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4376 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4377 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4378 rfctl |= IXGBE_RFCTL_RSC_DIS; 4379 4380 /* disable NFS filtering */ 4381 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4382 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4383 4384 /* Program registers for the distribution of queues */ 4385 ixgbe_setup_mrqc(adapter); 4386 4387 /* set_rx_buffer_len must be called before ring initialization */ 4388 ixgbe_set_rx_buffer_len(adapter); 4389 4390 /* 4391 * Setup the HW Rx Head and Tail Descriptor Pointers and 4392 * the Base and Length of the Rx Descriptor Ring 4393 */ 4394 for (i = 0; i < adapter->num_rx_queues; i++) 4395 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4396 4397 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4398 /* disable drop enable for 82598 parts */ 4399 if (hw->mac.type == ixgbe_mac_82598EB) 4400 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4401 4402 /* enable all receives */ 4403 rxctrl |= IXGBE_RXCTRL_RXEN; 4404 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4405 } 4406 4407 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4408 __be16 proto, u16 vid) 4409 { 4410 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4411 struct ixgbe_hw *hw = &adapter->hw; 4412 4413 /* add VID to filter table */ 4414 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4415 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4416 4417 set_bit(vid, adapter->active_vlans); 4418 4419 return 0; 4420 } 4421 4422 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4423 { 4424 u32 vlvf; 4425 int idx; 4426 4427 /* short cut the special case */ 4428 if (vlan == 0) 4429 return 0; 4430 4431 /* Search for the vlan id in the VLVF entries */ 4432 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4433 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4434 if ((vlvf & VLAN_VID_MASK) == vlan) 4435 break; 4436 } 4437 4438 return idx; 4439 } 4440 4441 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4442 { 4443 struct ixgbe_hw *hw = &adapter->hw; 4444 u32 bits, word; 4445 int idx; 4446 4447 idx = ixgbe_find_vlvf_entry(hw, vid); 4448 if (!idx) 4449 return; 4450 4451 /* See if any other pools are set for this VLAN filter 4452 * entry other than the PF. 4453 */ 4454 word = idx * 2 + (VMDQ_P(0) / 32); 4455 bits = ~BIT(VMDQ_P(0) % 32); 4456 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4457 4458 /* Disable the filter so this falls into the default pool. */ 4459 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4460 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4461 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4462 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4463 } 4464 } 4465 4466 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4467 __be16 proto, u16 vid) 4468 { 4469 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4470 struct ixgbe_hw *hw = &adapter->hw; 4471 4472 /* remove VID from filter table */ 4473 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4474 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4475 4476 clear_bit(vid, adapter->active_vlans); 4477 4478 return 0; 4479 } 4480 4481 /** 4482 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4483 * @adapter: driver data 4484 */ 4485 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4486 { 4487 struct ixgbe_hw *hw = &adapter->hw; 4488 u32 vlnctrl; 4489 int i, j; 4490 4491 switch (hw->mac.type) { 4492 case ixgbe_mac_82598EB: 4493 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4494 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4495 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4496 break; 4497 case ixgbe_mac_82599EB: 4498 case ixgbe_mac_X540: 4499 case ixgbe_mac_X550: 4500 case ixgbe_mac_X550EM_x: 4501 case ixgbe_mac_x550em_a: 4502 for (i = 0; i < adapter->num_rx_queues; i++) { 4503 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4504 4505 if (!netif_is_ixgbe(ring->netdev)) 4506 continue; 4507 4508 j = ring->reg_idx; 4509 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4510 vlnctrl &= ~IXGBE_RXDCTL_VME; 4511 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4512 } 4513 break; 4514 default: 4515 break; 4516 } 4517 } 4518 4519 /** 4520 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4521 * @adapter: driver data 4522 */ 4523 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4524 { 4525 struct ixgbe_hw *hw = &adapter->hw; 4526 u32 vlnctrl; 4527 int i, j; 4528 4529 switch (hw->mac.type) { 4530 case ixgbe_mac_82598EB: 4531 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4532 vlnctrl |= IXGBE_VLNCTRL_VME; 4533 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4534 break; 4535 case ixgbe_mac_82599EB: 4536 case ixgbe_mac_X540: 4537 case ixgbe_mac_X550: 4538 case ixgbe_mac_X550EM_x: 4539 case ixgbe_mac_x550em_a: 4540 for (i = 0; i < adapter->num_rx_queues; i++) { 4541 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4542 4543 if (!netif_is_ixgbe(ring->netdev)) 4544 continue; 4545 4546 j = ring->reg_idx; 4547 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4548 vlnctrl |= IXGBE_RXDCTL_VME; 4549 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4550 } 4551 break; 4552 default: 4553 break; 4554 } 4555 } 4556 4557 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4558 { 4559 struct ixgbe_hw *hw = &adapter->hw; 4560 u32 vlnctrl, i; 4561 4562 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4563 4564 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4565 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4566 vlnctrl |= IXGBE_VLNCTRL_VFE; 4567 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4568 } else { 4569 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4570 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4571 return; 4572 } 4573 4574 /* Nothing to do for 82598 */ 4575 if (hw->mac.type == ixgbe_mac_82598EB) 4576 return; 4577 4578 /* We are already in VLAN promisc, nothing to do */ 4579 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4580 return; 4581 4582 /* Set flag so we don't redo unnecessary work */ 4583 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4584 4585 /* Add PF to all active pools */ 4586 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4587 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4588 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4589 4590 vlvfb |= BIT(VMDQ_P(0) % 32); 4591 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4592 } 4593 4594 /* Set all bits in the VLAN filter table array */ 4595 for (i = hw->mac.vft_size; i--;) 4596 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4597 } 4598 4599 #define VFTA_BLOCK_SIZE 8 4600 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4601 { 4602 struct ixgbe_hw *hw = &adapter->hw; 4603 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4604 u32 vid_start = vfta_offset * 32; 4605 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4606 u32 i, vid, word, bits; 4607 4608 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4609 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4610 4611 /* pull VLAN ID from VLVF */ 4612 vid = vlvf & VLAN_VID_MASK; 4613 4614 /* only concern outselves with a certain range */ 4615 if (vid < vid_start || vid >= vid_end) 4616 continue; 4617 4618 if (vlvf) { 4619 /* record VLAN ID in VFTA */ 4620 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4621 4622 /* if PF is part of this then continue */ 4623 if (test_bit(vid, adapter->active_vlans)) 4624 continue; 4625 } 4626 4627 /* remove PF from the pool */ 4628 word = i * 2 + VMDQ_P(0) / 32; 4629 bits = ~BIT(VMDQ_P(0) % 32); 4630 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4631 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4632 } 4633 4634 /* extract values from active_vlans and write back to VFTA */ 4635 for (i = VFTA_BLOCK_SIZE; i--;) { 4636 vid = (vfta_offset + i) * 32; 4637 word = vid / BITS_PER_LONG; 4638 bits = vid % BITS_PER_LONG; 4639 4640 vfta[i] |= adapter->active_vlans[word] >> bits; 4641 4642 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4643 } 4644 } 4645 4646 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4647 { 4648 struct ixgbe_hw *hw = &adapter->hw; 4649 u32 vlnctrl, i; 4650 4651 /* Set VLAN filtering to enabled */ 4652 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4653 vlnctrl |= IXGBE_VLNCTRL_VFE; 4654 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4655 4656 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4657 hw->mac.type == ixgbe_mac_82598EB) 4658 return; 4659 4660 /* We are not in VLAN promisc, nothing to do */ 4661 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4662 return; 4663 4664 /* Set flag so we don't redo unnecessary work */ 4665 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4666 4667 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4668 ixgbe_scrub_vfta(adapter, i); 4669 } 4670 4671 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4672 { 4673 u16 vid = 1; 4674 4675 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4676 4677 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4678 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4679 } 4680 4681 /** 4682 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4683 * @netdev: network interface device structure 4684 * 4685 * Writes multicast address list to the MTA hash table. 4686 * Returns: -ENOMEM on failure 4687 * 0 on no addresses written 4688 * X on writing X addresses to MTA 4689 **/ 4690 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4691 { 4692 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4693 struct ixgbe_hw *hw = &adapter->hw; 4694 4695 if (!netif_running(netdev)) 4696 return 0; 4697 4698 if (hw->mac.ops.update_mc_addr_list) 4699 hw->mac.ops.update_mc_addr_list(hw, netdev); 4700 else 4701 return -ENOMEM; 4702 4703 #ifdef CONFIG_PCI_IOV 4704 ixgbe_restore_vf_multicasts(adapter); 4705 #endif 4706 4707 return netdev_mc_count(netdev); 4708 } 4709 4710 #ifdef CONFIG_PCI_IOV 4711 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4712 { 4713 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4714 struct ixgbe_hw *hw = &adapter->hw; 4715 int i; 4716 4717 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4718 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4719 4720 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4721 hw->mac.ops.set_rar(hw, i, 4722 mac_table->addr, 4723 mac_table->pool, 4724 IXGBE_RAH_AV); 4725 else 4726 hw->mac.ops.clear_rar(hw, i); 4727 } 4728 } 4729 4730 #endif 4731 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4732 { 4733 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4734 struct ixgbe_hw *hw = &adapter->hw; 4735 int i; 4736 4737 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4738 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4739 continue; 4740 4741 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4742 4743 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4744 hw->mac.ops.set_rar(hw, i, 4745 mac_table->addr, 4746 mac_table->pool, 4747 IXGBE_RAH_AV); 4748 else 4749 hw->mac.ops.clear_rar(hw, i); 4750 } 4751 } 4752 4753 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4754 { 4755 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4756 struct ixgbe_hw *hw = &adapter->hw; 4757 int i; 4758 4759 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4760 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4761 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4762 } 4763 4764 ixgbe_sync_mac_table(adapter); 4765 } 4766 4767 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4768 { 4769 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4770 struct ixgbe_hw *hw = &adapter->hw; 4771 int i, count = 0; 4772 4773 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4774 /* do not count default RAR as available */ 4775 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4776 continue; 4777 4778 /* only count unused and addresses that belong to us */ 4779 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4780 if (mac_table->pool != pool) 4781 continue; 4782 } 4783 4784 count++; 4785 } 4786 4787 return count; 4788 } 4789 4790 /* this function destroys the first RAR entry */ 4791 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4792 { 4793 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4794 struct ixgbe_hw *hw = &adapter->hw; 4795 4796 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4797 mac_table->pool = VMDQ_P(0); 4798 4799 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4800 4801 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4802 IXGBE_RAH_AV); 4803 } 4804 4805 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4806 const u8 *addr, u16 pool) 4807 { 4808 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4809 struct ixgbe_hw *hw = &adapter->hw; 4810 int i; 4811 4812 if (is_zero_ether_addr(addr)) 4813 return -EINVAL; 4814 4815 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4816 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4817 continue; 4818 4819 ether_addr_copy(mac_table->addr, addr); 4820 mac_table->pool = pool; 4821 4822 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4823 IXGBE_MAC_STATE_IN_USE; 4824 4825 ixgbe_sync_mac_table(adapter); 4826 4827 return i; 4828 } 4829 4830 return -ENOMEM; 4831 } 4832 4833 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4834 const u8 *addr, u16 pool) 4835 { 4836 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4837 struct ixgbe_hw *hw = &adapter->hw; 4838 int i; 4839 4840 if (is_zero_ether_addr(addr)) 4841 return -EINVAL; 4842 4843 /* search table for addr, if found clear IN_USE flag and sync */ 4844 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4845 /* we can only delete an entry if it is in use */ 4846 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4847 continue; 4848 /* we only care about entries that belong to the given pool */ 4849 if (mac_table->pool != pool) 4850 continue; 4851 /* we only care about a specific MAC address */ 4852 if (!ether_addr_equal(addr, mac_table->addr)) 4853 continue; 4854 4855 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4856 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4857 4858 ixgbe_sync_mac_table(adapter); 4859 4860 return 0; 4861 } 4862 4863 return -ENOMEM; 4864 } 4865 4866 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4867 { 4868 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4869 int ret; 4870 4871 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4872 4873 return min_t(int, ret, 0); 4874 } 4875 4876 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4877 { 4878 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4879 4880 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4881 4882 return 0; 4883 } 4884 4885 /** 4886 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4887 * @netdev: network interface device structure 4888 * 4889 * The set_rx_method entry point is called whenever the unicast/multicast 4890 * address list or the network interface flags are updated. This routine is 4891 * responsible for configuring the hardware for proper unicast, multicast and 4892 * promiscuous mode. 4893 **/ 4894 void ixgbe_set_rx_mode(struct net_device *netdev) 4895 { 4896 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4897 struct ixgbe_hw *hw = &adapter->hw; 4898 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4899 netdev_features_t features = netdev->features; 4900 int count; 4901 4902 /* Check for Promiscuous and All Multicast modes */ 4903 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4904 4905 /* set all bits that we expect to always be set */ 4906 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4907 fctrl |= IXGBE_FCTRL_BAM; 4908 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4909 fctrl |= IXGBE_FCTRL_PMCF; 4910 4911 /* clear the bits we are changing the status of */ 4912 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4913 if (netdev->flags & IFF_PROMISC) { 4914 hw->addr_ctrl.user_set_promisc = true; 4915 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4916 vmolr |= IXGBE_VMOLR_MPE; 4917 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4918 } else { 4919 if (netdev->flags & IFF_ALLMULTI) { 4920 fctrl |= IXGBE_FCTRL_MPE; 4921 vmolr |= IXGBE_VMOLR_MPE; 4922 } 4923 hw->addr_ctrl.user_set_promisc = false; 4924 } 4925 4926 /* 4927 * Write addresses to available RAR registers, if there is not 4928 * sufficient space to store all the addresses then enable 4929 * unicast promiscuous mode 4930 */ 4931 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4932 fctrl |= IXGBE_FCTRL_UPE; 4933 vmolr |= IXGBE_VMOLR_ROPE; 4934 } 4935 4936 /* Write addresses to the MTA, if the attempt fails 4937 * then we should just turn on promiscuous mode so 4938 * that we can at least receive multicast traffic 4939 */ 4940 count = ixgbe_write_mc_addr_list(netdev); 4941 if (count < 0) { 4942 fctrl |= IXGBE_FCTRL_MPE; 4943 vmolr |= IXGBE_VMOLR_MPE; 4944 } else if (count) { 4945 vmolr |= IXGBE_VMOLR_ROMPE; 4946 } 4947 4948 if (hw->mac.type != ixgbe_mac_82598EB) { 4949 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4950 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4951 IXGBE_VMOLR_ROPE); 4952 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4953 } 4954 4955 /* This is useful for sniffing bad packets. */ 4956 if (features & NETIF_F_RXALL) { 4957 /* UPE and MPE will be handled by normal PROMISC logic 4958 * in e1000e_set_rx_mode */ 4959 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4960 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4961 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4962 4963 fctrl &= ~(IXGBE_FCTRL_DPF); 4964 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4965 } 4966 4967 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4968 4969 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4970 ixgbe_vlan_strip_enable(adapter); 4971 else 4972 ixgbe_vlan_strip_disable(adapter); 4973 4974 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4975 ixgbe_vlan_promisc_disable(adapter); 4976 else 4977 ixgbe_vlan_promisc_enable(adapter); 4978 } 4979 4980 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4981 { 4982 int q_idx; 4983 4984 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4985 napi_enable(&adapter->q_vector[q_idx]->napi); 4986 } 4987 4988 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4989 { 4990 int q_idx; 4991 4992 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4993 napi_disable(&adapter->q_vector[q_idx]->napi); 4994 } 4995 4996 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 4997 { 4998 struct ixgbe_adapter *adapter = netdev_priv(dev); 4999 struct ixgbe_hw *hw = &adapter->hw; 5000 struct udp_tunnel_info ti; 5001 5002 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5003 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5004 adapter->vxlan_port = ti.port; 5005 else 5006 adapter->geneve_port = ti.port; 5007 5008 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5009 ntohs(adapter->vxlan_port) | 5010 ntohs(adapter->geneve_port) << 5011 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5012 return 0; 5013 } 5014 5015 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5016 .sync_table = ixgbe_udp_tunnel_sync, 5017 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5018 .tables = { 5019 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5020 }, 5021 }; 5022 5023 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5024 .sync_table = ixgbe_udp_tunnel_sync, 5025 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5026 .tables = { 5027 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5028 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5029 }, 5030 }; 5031 5032 #ifdef CONFIG_IXGBE_DCB 5033 /** 5034 * ixgbe_configure_dcb - Configure DCB hardware 5035 * @adapter: ixgbe adapter struct 5036 * 5037 * This is called by the driver on open to configure the DCB hardware. 5038 * This is also called by the gennetlink interface when reconfiguring 5039 * the DCB state. 5040 */ 5041 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5042 { 5043 struct ixgbe_hw *hw = &adapter->hw; 5044 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5045 5046 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5047 if (hw->mac.type == ixgbe_mac_82598EB) 5048 netif_set_gso_max_size(adapter->netdev, 65536); 5049 return; 5050 } 5051 5052 if (hw->mac.type == ixgbe_mac_82598EB) 5053 netif_set_gso_max_size(adapter->netdev, 32768); 5054 5055 #ifdef IXGBE_FCOE 5056 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5057 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5058 #endif 5059 5060 /* reconfigure the hardware */ 5061 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5062 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5063 DCB_TX_CONFIG); 5064 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5065 DCB_RX_CONFIG); 5066 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5067 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5068 ixgbe_dcb_hw_ets(&adapter->hw, 5069 adapter->ixgbe_ieee_ets, 5070 max_frame); 5071 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5072 adapter->ixgbe_ieee_pfc->pfc_en, 5073 adapter->ixgbe_ieee_ets->prio_tc); 5074 } 5075 5076 /* Enable RSS Hash per TC */ 5077 if (hw->mac.type != ixgbe_mac_82598EB) { 5078 u32 msb = 0; 5079 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5080 5081 while (rss_i) { 5082 msb++; 5083 rss_i >>= 1; 5084 } 5085 5086 /* write msb to all 8 TCs in one write */ 5087 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5088 } 5089 } 5090 #endif 5091 5092 /* Additional bittime to account for IXGBE framing */ 5093 #define IXGBE_ETH_FRAMING 20 5094 5095 /** 5096 * ixgbe_hpbthresh - calculate high water mark for flow control 5097 * 5098 * @adapter: board private structure to calculate for 5099 * @pb: packet buffer to calculate 5100 */ 5101 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5102 { 5103 struct ixgbe_hw *hw = &adapter->hw; 5104 struct net_device *dev = adapter->netdev; 5105 int link, tc, kb, marker; 5106 u32 dv_id, rx_pba; 5107 5108 /* Calculate max LAN frame size */ 5109 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5110 5111 #ifdef IXGBE_FCOE 5112 /* FCoE traffic class uses FCOE jumbo frames */ 5113 if ((dev->features & NETIF_F_FCOE_MTU) && 5114 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5115 (pb == ixgbe_fcoe_get_tc(adapter))) 5116 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5117 #endif 5118 5119 /* Calculate delay value for device */ 5120 switch (hw->mac.type) { 5121 case ixgbe_mac_X540: 5122 case ixgbe_mac_X550: 5123 case ixgbe_mac_X550EM_x: 5124 case ixgbe_mac_x550em_a: 5125 dv_id = IXGBE_DV_X540(link, tc); 5126 break; 5127 default: 5128 dv_id = IXGBE_DV(link, tc); 5129 break; 5130 } 5131 5132 /* Loopback switch introduces additional latency */ 5133 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5134 dv_id += IXGBE_B2BT(tc); 5135 5136 /* Delay value is calculated in bit times convert to KB */ 5137 kb = IXGBE_BT2KB(dv_id); 5138 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5139 5140 marker = rx_pba - kb; 5141 5142 /* It is possible that the packet buffer is not large enough 5143 * to provide required headroom. In this case throw an error 5144 * to user and a do the best we can. 5145 */ 5146 if (marker < 0) { 5147 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5148 "headroom to support flow control." 5149 "Decrease MTU or number of traffic classes\n", pb); 5150 marker = tc + 1; 5151 } 5152 5153 return marker; 5154 } 5155 5156 /** 5157 * ixgbe_lpbthresh - calculate low water mark for for flow control 5158 * 5159 * @adapter: board private structure to calculate for 5160 * @pb: packet buffer to calculate 5161 */ 5162 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5163 { 5164 struct ixgbe_hw *hw = &adapter->hw; 5165 struct net_device *dev = adapter->netdev; 5166 int tc; 5167 u32 dv_id; 5168 5169 /* Calculate max LAN frame size */ 5170 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5171 5172 #ifdef IXGBE_FCOE 5173 /* FCoE traffic class uses FCOE jumbo frames */ 5174 if ((dev->features & NETIF_F_FCOE_MTU) && 5175 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5176 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5177 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5178 #endif 5179 5180 /* Calculate delay value for device */ 5181 switch (hw->mac.type) { 5182 case ixgbe_mac_X540: 5183 case ixgbe_mac_X550: 5184 case ixgbe_mac_X550EM_x: 5185 case ixgbe_mac_x550em_a: 5186 dv_id = IXGBE_LOW_DV_X540(tc); 5187 break; 5188 default: 5189 dv_id = IXGBE_LOW_DV(tc); 5190 break; 5191 } 5192 5193 /* Delay value is calculated in bit times convert to KB */ 5194 return IXGBE_BT2KB(dv_id); 5195 } 5196 5197 /* 5198 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5199 */ 5200 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5201 { 5202 struct ixgbe_hw *hw = &adapter->hw; 5203 int num_tc = adapter->hw_tcs; 5204 int i; 5205 5206 if (!num_tc) 5207 num_tc = 1; 5208 5209 for (i = 0; i < num_tc; i++) { 5210 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5211 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5212 5213 /* Low water marks must not be larger than high water marks */ 5214 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5215 hw->fc.low_water[i] = 0; 5216 } 5217 5218 for (; i < MAX_TRAFFIC_CLASS; i++) 5219 hw->fc.high_water[i] = 0; 5220 } 5221 5222 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5223 { 5224 struct ixgbe_hw *hw = &adapter->hw; 5225 int hdrm; 5226 u8 tc = adapter->hw_tcs; 5227 5228 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5229 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5230 hdrm = 32 << adapter->fdir_pballoc; 5231 else 5232 hdrm = 0; 5233 5234 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5235 ixgbe_pbthresh_setup(adapter); 5236 } 5237 5238 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5239 { 5240 struct ixgbe_hw *hw = &adapter->hw; 5241 struct hlist_node *node2; 5242 struct ixgbe_fdir_filter *filter; 5243 u8 queue; 5244 5245 spin_lock(&adapter->fdir_perfect_lock); 5246 5247 if (!hlist_empty(&adapter->fdir_filter_list)) 5248 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5249 5250 hlist_for_each_entry_safe(filter, node2, 5251 &adapter->fdir_filter_list, fdir_node) { 5252 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5253 queue = IXGBE_FDIR_DROP_QUEUE; 5254 } else { 5255 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5256 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5257 5258 if (!vf && (ring >= adapter->num_rx_queues)) { 5259 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5260 ring); 5261 continue; 5262 } else if (vf && 5263 ((vf > adapter->num_vfs) || 5264 ring >= adapter->num_rx_queues_per_pool)) { 5265 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5266 vf, ring); 5267 continue; 5268 } 5269 5270 /* Map the ring onto the absolute queue index */ 5271 if (!vf) 5272 queue = adapter->rx_ring[ring]->reg_idx; 5273 else 5274 queue = ((vf - 1) * 5275 adapter->num_rx_queues_per_pool) + ring; 5276 } 5277 5278 ixgbe_fdir_write_perfect_filter_82599(hw, 5279 &filter->filter, filter->sw_idx, queue); 5280 } 5281 5282 spin_unlock(&adapter->fdir_perfect_lock); 5283 } 5284 5285 /** 5286 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5287 * @rx_ring: ring to free buffers from 5288 **/ 5289 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5290 { 5291 u16 i = rx_ring->next_to_clean; 5292 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5293 5294 if (rx_ring->xsk_pool) { 5295 ixgbe_xsk_clean_rx_ring(rx_ring); 5296 goto skip_free; 5297 } 5298 5299 /* Free all the Rx ring sk_buffs */ 5300 while (i != rx_ring->next_to_alloc) { 5301 if (rx_buffer->skb) { 5302 struct sk_buff *skb = rx_buffer->skb; 5303 if (IXGBE_CB(skb)->page_released) 5304 dma_unmap_page_attrs(rx_ring->dev, 5305 IXGBE_CB(skb)->dma, 5306 ixgbe_rx_pg_size(rx_ring), 5307 DMA_FROM_DEVICE, 5308 IXGBE_RX_DMA_ATTR); 5309 dev_kfree_skb(skb); 5310 } 5311 5312 /* Invalidate cache lines that may have been written to by 5313 * device so that we avoid corrupting memory. 5314 */ 5315 dma_sync_single_range_for_cpu(rx_ring->dev, 5316 rx_buffer->dma, 5317 rx_buffer->page_offset, 5318 ixgbe_rx_bufsz(rx_ring), 5319 DMA_FROM_DEVICE); 5320 5321 /* free resources associated with mapping */ 5322 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5323 ixgbe_rx_pg_size(rx_ring), 5324 DMA_FROM_DEVICE, 5325 IXGBE_RX_DMA_ATTR); 5326 __page_frag_cache_drain(rx_buffer->page, 5327 rx_buffer->pagecnt_bias); 5328 5329 i++; 5330 rx_buffer++; 5331 if (i == rx_ring->count) { 5332 i = 0; 5333 rx_buffer = rx_ring->rx_buffer_info; 5334 } 5335 } 5336 5337 skip_free: 5338 rx_ring->next_to_alloc = 0; 5339 rx_ring->next_to_clean = 0; 5340 rx_ring->next_to_use = 0; 5341 } 5342 5343 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5344 struct ixgbe_fwd_adapter *accel) 5345 { 5346 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5347 int num_tc = netdev_get_num_tc(adapter->netdev); 5348 struct net_device *vdev = accel->netdev; 5349 int i, baseq, err; 5350 5351 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5352 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5353 accel->pool, adapter->num_rx_pools, 5354 baseq, baseq + adapter->num_rx_queues_per_pool); 5355 5356 accel->rx_base_queue = baseq; 5357 accel->tx_base_queue = baseq; 5358 5359 /* record configuration for macvlan interface in vdev */ 5360 for (i = 0; i < num_tc; i++) 5361 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5362 i, rss_i, baseq + (rss_i * i)); 5363 5364 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5365 adapter->rx_ring[baseq + i]->netdev = vdev; 5366 5367 /* Guarantee all rings are updated before we update the 5368 * MAC address filter. 5369 */ 5370 wmb(); 5371 5372 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5373 * need to only treat it as an error value if it is negative. 5374 */ 5375 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5376 VMDQ_P(accel->pool)); 5377 if (err >= 0) 5378 return 0; 5379 5380 /* if we cannot add the MAC rule then disable the offload */ 5381 macvlan_release_l2fw_offload(vdev); 5382 5383 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5384 adapter->rx_ring[baseq + i]->netdev = NULL; 5385 5386 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5387 5388 /* unbind the queues and drop the subordinate channel config */ 5389 netdev_unbind_sb_channel(adapter->netdev, vdev); 5390 netdev_set_sb_channel(vdev, 0); 5391 5392 clear_bit(accel->pool, adapter->fwd_bitmask); 5393 kfree(accel); 5394 5395 return err; 5396 } 5397 5398 static int ixgbe_macvlan_up(struct net_device *vdev, 5399 struct netdev_nested_priv *priv) 5400 { 5401 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5402 struct ixgbe_fwd_adapter *accel; 5403 5404 if (!netif_is_macvlan(vdev)) 5405 return 0; 5406 5407 accel = macvlan_accel_priv(vdev); 5408 if (!accel) 5409 return 0; 5410 5411 ixgbe_fwd_ring_up(adapter, accel); 5412 5413 return 0; 5414 } 5415 5416 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5417 { 5418 struct netdev_nested_priv priv = { 5419 .data = (void *)adapter, 5420 }; 5421 5422 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5423 ixgbe_macvlan_up, &priv); 5424 } 5425 5426 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5427 { 5428 struct ixgbe_hw *hw = &adapter->hw; 5429 5430 ixgbe_configure_pb(adapter); 5431 #ifdef CONFIG_IXGBE_DCB 5432 ixgbe_configure_dcb(adapter); 5433 #endif 5434 /* 5435 * We must restore virtualization before VLANs or else 5436 * the VLVF registers will not be populated 5437 */ 5438 ixgbe_configure_virtualization(adapter); 5439 5440 ixgbe_set_rx_mode(adapter->netdev); 5441 ixgbe_restore_vlan(adapter); 5442 ixgbe_ipsec_restore(adapter); 5443 5444 switch (hw->mac.type) { 5445 case ixgbe_mac_82599EB: 5446 case ixgbe_mac_X540: 5447 hw->mac.ops.disable_rx_buff(hw); 5448 break; 5449 default: 5450 break; 5451 } 5452 5453 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5454 ixgbe_init_fdir_signature_82599(&adapter->hw, 5455 adapter->fdir_pballoc); 5456 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5457 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5458 adapter->fdir_pballoc); 5459 ixgbe_fdir_filter_restore(adapter); 5460 } 5461 5462 switch (hw->mac.type) { 5463 case ixgbe_mac_82599EB: 5464 case ixgbe_mac_X540: 5465 hw->mac.ops.enable_rx_buff(hw); 5466 break; 5467 default: 5468 break; 5469 } 5470 5471 #ifdef CONFIG_IXGBE_DCA 5472 /* configure DCA */ 5473 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5474 ixgbe_setup_dca(adapter); 5475 #endif /* CONFIG_IXGBE_DCA */ 5476 5477 #ifdef IXGBE_FCOE 5478 /* configure FCoE L2 filters, redirection table, and Rx control */ 5479 ixgbe_configure_fcoe(adapter); 5480 5481 #endif /* IXGBE_FCOE */ 5482 ixgbe_configure_tx(adapter); 5483 ixgbe_configure_rx(adapter); 5484 ixgbe_configure_dfwd(adapter); 5485 } 5486 5487 /** 5488 * ixgbe_sfp_link_config - set up SFP+ link 5489 * @adapter: pointer to private adapter struct 5490 **/ 5491 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5492 { 5493 /* 5494 * We are assuming the worst case scenario here, and that 5495 * is that an SFP was inserted/removed after the reset 5496 * but before SFP detection was enabled. As such the best 5497 * solution is to just start searching as soon as we start 5498 */ 5499 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5500 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5501 5502 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5503 adapter->sfp_poll_time = 0; 5504 } 5505 5506 /** 5507 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5508 * @hw: pointer to private hardware struct 5509 * 5510 * Returns 0 on success, negative on failure 5511 **/ 5512 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5513 { 5514 u32 speed; 5515 bool autoneg, link_up = false; 5516 int ret = IXGBE_ERR_LINK_SETUP; 5517 5518 if (hw->mac.ops.check_link) 5519 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5520 5521 if (ret) 5522 return ret; 5523 5524 speed = hw->phy.autoneg_advertised; 5525 if (!speed && hw->mac.ops.get_link_capabilities) { 5526 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5527 &autoneg); 5528 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 5529 IXGBE_LINK_SPEED_2_5GB_FULL); 5530 } 5531 5532 if (ret) 5533 return ret; 5534 5535 if (hw->mac.ops.setup_link) 5536 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5537 5538 return ret; 5539 } 5540 5541 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5542 { 5543 struct ixgbe_hw *hw = &adapter->hw; 5544 u32 gpie = 0; 5545 5546 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5547 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5548 IXGBE_GPIE_OCD; 5549 gpie |= IXGBE_GPIE_EIAME; 5550 /* 5551 * use EIAM to auto-mask when MSI-X interrupt is asserted 5552 * this saves a register write for every interrupt 5553 */ 5554 switch (hw->mac.type) { 5555 case ixgbe_mac_82598EB: 5556 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5557 break; 5558 case ixgbe_mac_82599EB: 5559 case ixgbe_mac_X540: 5560 case ixgbe_mac_X550: 5561 case ixgbe_mac_X550EM_x: 5562 case ixgbe_mac_x550em_a: 5563 default: 5564 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5565 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5566 break; 5567 } 5568 } else { 5569 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5570 * specifically only auto mask tx and rx interrupts */ 5571 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5572 } 5573 5574 /* XXX: to interrupt immediately for EICS writes, enable this */ 5575 /* gpie |= IXGBE_GPIE_EIMEN; */ 5576 5577 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5578 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5579 5580 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5581 case IXGBE_82599_VMDQ_8Q_MASK: 5582 gpie |= IXGBE_GPIE_VTMODE_16; 5583 break; 5584 case IXGBE_82599_VMDQ_4Q_MASK: 5585 gpie |= IXGBE_GPIE_VTMODE_32; 5586 break; 5587 default: 5588 gpie |= IXGBE_GPIE_VTMODE_64; 5589 break; 5590 } 5591 } 5592 5593 /* Enable Thermal over heat sensor interrupt */ 5594 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5595 switch (adapter->hw.mac.type) { 5596 case ixgbe_mac_82599EB: 5597 gpie |= IXGBE_SDP0_GPIEN_8259X; 5598 break; 5599 default: 5600 break; 5601 } 5602 } 5603 5604 /* Enable fan failure interrupt */ 5605 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5606 gpie |= IXGBE_SDP1_GPIEN(hw); 5607 5608 switch (hw->mac.type) { 5609 case ixgbe_mac_82599EB: 5610 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5611 break; 5612 case ixgbe_mac_X550EM_x: 5613 case ixgbe_mac_x550em_a: 5614 gpie |= IXGBE_SDP0_GPIEN_X540; 5615 break; 5616 default: 5617 break; 5618 } 5619 5620 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5621 } 5622 5623 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5624 { 5625 struct ixgbe_hw *hw = &adapter->hw; 5626 int err; 5627 u32 ctrl_ext; 5628 5629 ixgbe_get_hw_control(adapter); 5630 ixgbe_setup_gpie(adapter); 5631 5632 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5633 ixgbe_configure_msix(adapter); 5634 else 5635 ixgbe_configure_msi_and_legacy(adapter); 5636 5637 /* enable the optics for 82599 SFP+ fiber */ 5638 if (hw->mac.ops.enable_tx_laser) 5639 hw->mac.ops.enable_tx_laser(hw); 5640 5641 if (hw->phy.ops.set_phy_power) 5642 hw->phy.ops.set_phy_power(hw, true); 5643 5644 smp_mb__before_atomic(); 5645 clear_bit(__IXGBE_DOWN, &adapter->state); 5646 ixgbe_napi_enable_all(adapter); 5647 5648 if (ixgbe_is_sfp(hw)) { 5649 ixgbe_sfp_link_config(adapter); 5650 } else { 5651 err = ixgbe_non_sfp_link_config(hw); 5652 if (err) 5653 e_err(probe, "link_config FAILED %d\n", err); 5654 } 5655 5656 /* clear any pending interrupts, may auto mask */ 5657 IXGBE_READ_REG(hw, IXGBE_EICR); 5658 ixgbe_irq_enable(adapter, true, true); 5659 5660 /* 5661 * If this adapter has a fan, check to see if we had a failure 5662 * before we enabled the interrupt. 5663 */ 5664 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5665 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5666 if (esdp & IXGBE_ESDP_SDP1) 5667 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5668 } 5669 5670 /* bring the link up in the watchdog, this could race with our first 5671 * link up interrupt but shouldn't be a problem */ 5672 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5673 adapter->link_check_timeout = jiffies; 5674 mod_timer(&adapter->service_timer, jiffies); 5675 5676 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5677 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5678 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5679 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5680 } 5681 5682 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5683 { 5684 /* put off any impending NetWatchDogTimeout */ 5685 netif_trans_update(adapter->netdev); 5686 5687 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5688 usleep_range(1000, 2000); 5689 if (adapter->hw.phy.type == ixgbe_phy_fw) 5690 ixgbe_watchdog_link_is_down(adapter); 5691 ixgbe_down(adapter); 5692 /* 5693 * If SR-IOV enabled then wait a bit before bringing the adapter 5694 * back up to give the VFs time to respond to the reset. The 5695 * two second wait is based upon the watchdog timer cycle in 5696 * the VF driver. 5697 */ 5698 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5699 msleep(2000); 5700 ixgbe_up(adapter); 5701 clear_bit(__IXGBE_RESETTING, &adapter->state); 5702 } 5703 5704 void ixgbe_up(struct ixgbe_adapter *adapter) 5705 { 5706 /* hardware has been reset, we need to reload some things */ 5707 ixgbe_configure(adapter); 5708 5709 ixgbe_up_complete(adapter); 5710 } 5711 5712 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5713 { 5714 u16 devctl2; 5715 5716 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5717 5718 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5719 case IXGBE_PCIDEVCTRL2_17_34s: 5720 case IXGBE_PCIDEVCTRL2_4_8s: 5721 /* For now we cap the upper limit on delay to 2 seconds 5722 * as we end up going up to 34 seconds of delay in worst 5723 * case timeout value. 5724 */ 5725 case IXGBE_PCIDEVCTRL2_1_2s: 5726 return 2000000ul; /* 2.0 s */ 5727 case IXGBE_PCIDEVCTRL2_260_520ms: 5728 return 520000ul; /* 520 ms */ 5729 case IXGBE_PCIDEVCTRL2_65_130ms: 5730 return 130000ul; /* 130 ms */ 5731 case IXGBE_PCIDEVCTRL2_16_32ms: 5732 return 32000ul; /* 32 ms */ 5733 case IXGBE_PCIDEVCTRL2_1_2ms: 5734 return 2000ul; /* 2 ms */ 5735 case IXGBE_PCIDEVCTRL2_50_100us: 5736 return 100ul; /* 100 us */ 5737 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5738 return 32000ul; /* 32 ms */ 5739 default: 5740 break; 5741 } 5742 5743 /* We shouldn't need to hit this path, but just in case default as 5744 * though completion timeout is not supported and support 32ms. 5745 */ 5746 return 32000ul; 5747 } 5748 5749 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5750 { 5751 unsigned long wait_delay, delay_interval; 5752 struct ixgbe_hw *hw = &adapter->hw; 5753 int i, wait_loop; 5754 u32 rxdctl; 5755 5756 /* disable receives */ 5757 hw->mac.ops.disable_rx(hw); 5758 5759 if (ixgbe_removed(hw->hw_addr)) 5760 return; 5761 5762 /* disable all enabled Rx queues */ 5763 for (i = 0; i < adapter->num_rx_queues; i++) { 5764 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5765 u8 reg_idx = ring->reg_idx; 5766 5767 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5768 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5769 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5770 5771 /* write value back with RXDCTL.ENABLE bit cleared */ 5772 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5773 } 5774 5775 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5776 if (hw->mac.type == ixgbe_mac_82598EB && 5777 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5778 return; 5779 5780 /* Determine our minimum delay interval. We will increase this value 5781 * with each subsequent test. This way if the device returns quickly 5782 * we should spend as little time as possible waiting, however as 5783 * the time increases we will wait for larger periods of time. 5784 * 5785 * The trick here is that we increase the interval using the 5786 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5787 * of that wait is that it totals up to 100x whatever interval we 5788 * choose. Since our minimum wait is 100us we can just divide the 5789 * total timeout by 100 to get our minimum delay interval. 5790 */ 5791 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5792 5793 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5794 wait_delay = delay_interval; 5795 5796 while (wait_loop--) { 5797 usleep_range(wait_delay, wait_delay + 10); 5798 wait_delay += delay_interval * 2; 5799 rxdctl = 0; 5800 5801 /* OR together the reading of all the active RXDCTL registers, 5802 * and then test the result. We need the disable to complete 5803 * before we start freeing the memory and invalidating the 5804 * DMA mappings. 5805 */ 5806 for (i = 0; i < adapter->num_rx_queues; i++) { 5807 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5808 u8 reg_idx = ring->reg_idx; 5809 5810 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5811 } 5812 5813 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5814 return; 5815 } 5816 5817 e_err(drv, 5818 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5819 } 5820 5821 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5822 { 5823 unsigned long wait_delay, delay_interval; 5824 struct ixgbe_hw *hw = &adapter->hw; 5825 int i, wait_loop; 5826 u32 txdctl; 5827 5828 if (ixgbe_removed(hw->hw_addr)) 5829 return; 5830 5831 /* disable all enabled Tx queues */ 5832 for (i = 0; i < adapter->num_tx_queues; i++) { 5833 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5834 u8 reg_idx = ring->reg_idx; 5835 5836 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5837 } 5838 5839 /* disable all enabled XDP Tx queues */ 5840 for (i = 0; i < adapter->num_xdp_queues; i++) { 5841 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5842 u8 reg_idx = ring->reg_idx; 5843 5844 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5845 } 5846 5847 /* If the link is not up there shouldn't be much in the way of 5848 * pending transactions. Those that are left will be flushed out 5849 * when the reset logic goes through the flush sequence to clean out 5850 * the pending Tx transactions. 5851 */ 5852 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5853 goto dma_engine_disable; 5854 5855 /* Determine our minimum delay interval. We will increase this value 5856 * with each subsequent test. This way if the device returns quickly 5857 * we should spend as little time as possible waiting, however as 5858 * the time increases we will wait for larger periods of time. 5859 * 5860 * The trick here is that we increase the interval using the 5861 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5862 * of that wait is that it totals up to 100x whatever interval we 5863 * choose. Since our minimum wait is 100us we can just divide the 5864 * total timeout by 100 to get our minimum delay interval. 5865 */ 5866 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5867 5868 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5869 wait_delay = delay_interval; 5870 5871 while (wait_loop--) { 5872 usleep_range(wait_delay, wait_delay + 10); 5873 wait_delay += delay_interval * 2; 5874 txdctl = 0; 5875 5876 /* OR together the reading of all the active TXDCTL registers, 5877 * and then test the result. We need the disable to complete 5878 * before we start freeing the memory and invalidating the 5879 * DMA mappings. 5880 */ 5881 for (i = 0; i < adapter->num_tx_queues; i++) { 5882 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5883 u8 reg_idx = ring->reg_idx; 5884 5885 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5886 } 5887 for (i = 0; i < adapter->num_xdp_queues; i++) { 5888 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5889 u8 reg_idx = ring->reg_idx; 5890 5891 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5892 } 5893 5894 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5895 goto dma_engine_disable; 5896 } 5897 5898 e_err(drv, 5899 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5900 5901 dma_engine_disable: 5902 /* Disable the Tx DMA engine on 82599 and later MAC */ 5903 switch (hw->mac.type) { 5904 case ixgbe_mac_82599EB: 5905 case ixgbe_mac_X540: 5906 case ixgbe_mac_X550: 5907 case ixgbe_mac_X550EM_x: 5908 case ixgbe_mac_x550em_a: 5909 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5910 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5911 ~IXGBE_DMATXCTL_TE)); 5912 fallthrough; 5913 default: 5914 break; 5915 } 5916 } 5917 5918 void ixgbe_reset(struct ixgbe_adapter *adapter) 5919 { 5920 struct ixgbe_hw *hw = &adapter->hw; 5921 struct net_device *netdev = adapter->netdev; 5922 int err; 5923 5924 if (ixgbe_removed(hw->hw_addr)) 5925 return; 5926 /* lock SFP init bit to prevent race conditions with the watchdog */ 5927 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5928 usleep_range(1000, 2000); 5929 5930 /* clear all SFP and link config related flags while holding SFP_INIT */ 5931 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5932 IXGBE_FLAG2_SFP_NEEDS_RESET); 5933 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5934 5935 err = hw->mac.ops.init_hw(hw); 5936 switch (err) { 5937 case 0: 5938 case IXGBE_ERR_SFP_NOT_PRESENT: 5939 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5940 break; 5941 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5942 e_dev_err("master disable timed out\n"); 5943 break; 5944 case IXGBE_ERR_EEPROM_VERSION: 5945 /* We are running on a pre-production device, log a warning */ 5946 e_dev_warn("This device is a pre-production adapter/LOM. " 5947 "Please be aware there may be issues associated with " 5948 "your hardware. If you are experiencing problems " 5949 "please contact your Intel or hardware " 5950 "representative who provided you with this " 5951 "hardware.\n"); 5952 break; 5953 default: 5954 e_dev_err("Hardware Error: %d\n", err); 5955 } 5956 5957 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5958 5959 /* flush entries out of MAC table */ 5960 ixgbe_flush_sw_mac_table(adapter); 5961 __dev_uc_unsync(netdev, NULL); 5962 5963 /* do not flush user set addresses */ 5964 ixgbe_mac_set_default_filter(adapter); 5965 5966 /* update SAN MAC vmdq pool selection */ 5967 if (hw->mac.san_mac_rar_index) 5968 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5969 5970 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5971 ixgbe_ptp_reset(adapter); 5972 5973 if (hw->phy.ops.set_phy_power) { 5974 if (!netif_running(adapter->netdev) && !adapter->wol) 5975 hw->phy.ops.set_phy_power(hw, false); 5976 else 5977 hw->phy.ops.set_phy_power(hw, true); 5978 } 5979 } 5980 5981 /** 5982 * ixgbe_clean_tx_ring - Free Tx Buffers 5983 * @tx_ring: ring to be cleaned 5984 **/ 5985 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5986 { 5987 u16 i = tx_ring->next_to_clean; 5988 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5989 5990 if (tx_ring->xsk_pool) { 5991 ixgbe_xsk_clean_tx_ring(tx_ring); 5992 goto out; 5993 } 5994 5995 while (i != tx_ring->next_to_use) { 5996 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5997 5998 /* Free all the Tx ring sk_buffs */ 5999 if (ring_is_xdp(tx_ring)) 6000 xdp_return_frame(tx_buffer->xdpf); 6001 else 6002 dev_kfree_skb_any(tx_buffer->skb); 6003 6004 /* unmap skb header data */ 6005 dma_unmap_single(tx_ring->dev, 6006 dma_unmap_addr(tx_buffer, dma), 6007 dma_unmap_len(tx_buffer, len), 6008 DMA_TO_DEVICE); 6009 6010 /* check for eop_desc to determine the end of the packet */ 6011 eop_desc = tx_buffer->next_to_watch; 6012 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6013 6014 /* unmap remaining buffers */ 6015 while (tx_desc != eop_desc) { 6016 tx_buffer++; 6017 tx_desc++; 6018 i++; 6019 if (unlikely(i == tx_ring->count)) { 6020 i = 0; 6021 tx_buffer = tx_ring->tx_buffer_info; 6022 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6023 } 6024 6025 /* unmap any remaining paged data */ 6026 if (dma_unmap_len(tx_buffer, len)) 6027 dma_unmap_page(tx_ring->dev, 6028 dma_unmap_addr(tx_buffer, dma), 6029 dma_unmap_len(tx_buffer, len), 6030 DMA_TO_DEVICE); 6031 } 6032 6033 /* move us one more past the eop_desc for start of next pkt */ 6034 tx_buffer++; 6035 i++; 6036 if (unlikely(i == tx_ring->count)) { 6037 i = 0; 6038 tx_buffer = tx_ring->tx_buffer_info; 6039 } 6040 } 6041 6042 /* reset BQL for queue */ 6043 if (!ring_is_xdp(tx_ring)) 6044 netdev_tx_reset_queue(txring_txq(tx_ring)); 6045 6046 out: 6047 /* reset next_to_use and next_to_clean */ 6048 tx_ring->next_to_use = 0; 6049 tx_ring->next_to_clean = 0; 6050 } 6051 6052 /** 6053 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6054 * @adapter: board private structure 6055 **/ 6056 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6057 { 6058 int i; 6059 6060 for (i = 0; i < adapter->num_rx_queues; i++) 6061 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6062 } 6063 6064 /** 6065 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6066 * @adapter: board private structure 6067 **/ 6068 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6069 { 6070 int i; 6071 6072 for (i = 0; i < adapter->num_tx_queues; i++) 6073 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6074 for (i = 0; i < adapter->num_xdp_queues; i++) 6075 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6076 } 6077 6078 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6079 { 6080 struct hlist_node *node2; 6081 struct ixgbe_fdir_filter *filter; 6082 6083 spin_lock(&adapter->fdir_perfect_lock); 6084 6085 hlist_for_each_entry_safe(filter, node2, 6086 &adapter->fdir_filter_list, fdir_node) { 6087 hlist_del(&filter->fdir_node); 6088 kfree(filter); 6089 } 6090 adapter->fdir_filter_count = 0; 6091 6092 spin_unlock(&adapter->fdir_perfect_lock); 6093 } 6094 6095 void ixgbe_down(struct ixgbe_adapter *adapter) 6096 { 6097 struct net_device *netdev = adapter->netdev; 6098 struct ixgbe_hw *hw = &adapter->hw; 6099 int i; 6100 6101 /* signal that we are down to the interrupt handler */ 6102 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6103 return; /* do nothing if already down */ 6104 6105 /* Shut off incoming Tx traffic */ 6106 netif_tx_stop_all_queues(netdev); 6107 6108 /* call carrier off first to avoid false dev_watchdog timeouts */ 6109 netif_carrier_off(netdev); 6110 netif_tx_disable(netdev); 6111 6112 /* Disable Rx */ 6113 ixgbe_disable_rx(adapter); 6114 6115 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6116 if (adapter->xdp_ring[0]) 6117 synchronize_rcu(); 6118 6119 ixgbe_irq_disable(adapter); 6120 6121 ixgbe_napi_disable_all(adapter); 6122 6123 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6124 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6125 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6126 6127 del_timer_sync(&adapter->service_timer); 6128 6129 if (adapter->num_vfs) { 6130 /* Clear EITR Select mapping */ 6131 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6132 6133 /* Mark all the VFs as inactive */ 6134 for (i = 0 ; i < adapter->num_vfs; i++) 6135 adapter->vfinfo[i].clear_to_send = false; 6136 6137 /* ping all the active vfs to let them know we are going down */ 6138 ixgbe_ping_all_vfs(adapter); 6139 6140 /* Disable all VFTE/VFRE TX/RX */ 6141 ixgbe_disable_tx_rx(adapter); 6142 } 6143 6144 /* disable transmits in the hardware now that interrupts are off */ 6145 ixgbe_disable_tx(adapter); 6146 6147 if (!pci_channel_offline(adapter->pdev)) 6148 ixgbe_reset(adapter); 6149 6150 /* power down the optics for 82599 SFP+ fiber */ 6151 if (hw->mac.ops.disable_tx_laser) 6152 hw->mac.ops.disable_tx_laser(hw); 6153 6154 ixgbe_clean_all_tx_rings(adapter); 6155 ixgbe_clean_all_rx_rings(adapter); 6156 } 6157 6158 /** 6159 * ixgbe_eee_capable - helper function to determine EEE support on X550 6160 * @adapter: board private structure 6161 */ 6162 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6163 { 6164 struct ixgbe_hw *hw = &adapter->hw; 6165 6166 switch (hw->device_id) { 6167 case IXGBE_DEV_ID_X550EM_A_1G_T: 6168 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6169 if (!hw->phy.eee_speeds_supported) 6170 break; 6171 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6172 if (!hw->phy.eee_speeds_advertised) 6173 break; 6174 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6175 break; 6176 default: 6177 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6178 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6179 break; 6180 } 6181 } 6182 6183 /** 6184 * ixgbe_tx_timeout - Respond to a Tx Hang 6185 * @netdev: network interface device structure 6186 * @txqueue: queue number that timed out 6187 **/ 6188 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6189 { 6190 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6191 6192 /* Do the reset outside of interrupt context */ 6193 ixgbe_tx_timeout_reset(adapter); 6194 } 6195 6196 #ifdef CONFIG_IXGBE_DCB 6197 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6198 { 6199 struct ixgbe_hw *hw = &adapter->hw; 6200 struct tc_configuration *tc; 6201 int j; 6202 6203 switch (hw->mac.type) { 6204 case ixgbe_mac_82598EB: 6205 case ixgbe_mac_82599EB: 6206 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6207 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6208 break; 6209 case ixgbe_mac_X540: 6210 case ixgbe_mac_X550: 6211 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6212 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6213 break; 6214 case ixgbe_mac_X550EM_x: 6215 case ixgbe_mac_x550em_a: 6216 default: 6217 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6218 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6219 break; 6220 } 6221 6222 /* Configure DCB traffic classes */ 6223 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6224 tc = &adapter->dcb_cfg.tc_config[j]; 6225 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6226 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6227 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6228 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6229 tc->dcb_pfc = pfc_disabled; 6230 } 6231 6232 /* Initialize default user to priority mapping, UPx->TC0 */ 6233 tc = &adapter->dcb_cfg.tc_config[0]; 6234 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6235 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6236 6237 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6238 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6239 adapter->dcb_cfg.pfc_mode_enable = false; 6240 adapter->dcb_set_bitmap = 0x00; 6241 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6242 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6243 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6244 sizeof(adapter->temp_dcb_cfg)); 6245 } 6246 #endif 6247 6248 /** 6249 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6250 * @adapter: board private structure to initialize 6251 * @ii: pointer to ixgbe_info for device 6252 * 6253 * ixgbe_sw_init initializes the Adapter private data structure. 6254 * Fields are initialized based on PCI device information and 6255 * OS network device settings (MTU size). 6256 **/ 6257 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6258 const struct ixgbe_info *ii) 6259 { 6260 struct ixgbe_hw *hw = &adapter->hw; 6261 struct pci_dev *pdev = adapter->pdev; 6262 unsigned int rss, fdir; 6263 u32 fwsm; 6264 int i; 6265 6266 /* PCI config space info */ 6267 6268 hw->vendor_id = pdev->vendor; 6269 hw->device_id = pdev->device; 6270 hw->revision_id = pdev->revision; 6271 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6272 hw->subsystem_device_id = pdev->subsystem_device; 6273 6274 /* get_invariants needs the device IDs */ 6275 ii->get_invariants(hw); 6276 6277 /* Set common capability flags and settings */ 6278 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6279 adapter->ring_feature[RING_F_RSS].limit = rss; 6280 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6281 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6282 adapter->atr_sample_rate = 20; 6283 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6284 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6285 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6286 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6287 #ifdef CONFIG_IXGBE_DCA 6288 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6289 #endif 6290 #ifdef CONFIG_IXGBE_DCB 6291 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6292 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6293 #endif 6294 #ifdef IXGBE_FCOE 6295 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6296 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6297 #ifdef CONFIG_IXGBE_DCB 6298 /* Default traffic class to use for FCoE */ 6299 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6300 #endif /* CONFIG_IXGBE_DCB */ 6301 #endif /* IXGBE_FCOE */ 6302 6303 /* initialize static ixgbe jump table entries */ 6304 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6305 GFP_KERNEL); 6306 if (!adapter->jump_tables[0]) 6307 return -ENOMEM; 6308 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6309 6310 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6311 adapter->jump_tables[i] = NULL; 6312 6313 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6314 sizeof(struct ixgbe_mac_addr), 6315 GFP_KERNEL); 6316 if (!adapter->mac_table) 6317 return -ENOMEM; 6318 6319 if (ixgbe_init_rss_key(adapter)) 6320 return -ENOMEM; 6321 6322 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL); 6323 if (!adapter->af_xdp_zc_qps) 6324 return -ENOMEM; 6325 6326 /* Set MAC specific capability flags and exceptions */ 6327 switch (hw->mac.type) { 6328 case ixgbe_mac_82598EB: 6329 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6330 6331 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6332 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6333 6334 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6335 adapter->ring_feature[RING_F_FDIR].limit = 0; 6336 adapter->atr_sample_rate = 0; 6337 adapter->fdir_pballoc = 0; 6338 #ifdef IXGBE_FCOE 6339 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6340 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6341 #ifdef CONFIG_IXGBE_DCB 6342 adapter->fcoe.up = 0; 6343 #endif /* IXGBE_DCB */ 6344 #endif /* IXGBE_FCOE */ 6345 break; 6346 case ixgbe_mac_82599EB: 6347 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6348 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6349 break; 6350 case ixgbe_mac_X540: 6351 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6352 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6353 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6354 break; 6355 case ixgbe_mac_x550em_a: 6356 switch (hw->device_id) { 6357 case IXGBE_DEV_ID_X550EM_A_1G_T: 6358 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6359 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6360 break; 6361 default: 6362 break; 6363 } 6364 fallthrough; 6365 case ixgbe_mac_X550EM_x: 6366 #ifdef CONFIG_IXGBE_DCB 6367 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6368 #endif 6369 #ifdef IXGBE_FCOE 6370 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6371 #ifdef CONFIG_IXGBE_DCB 6372 adapter->fcoe.up = 0; 6373 #endif /* IXGBE_DCB */ 6374 #endif /* IXGBE_FCOE */ 6375 fallthrough; 6376 case ixgbe_mac_X550: 6377 if (hw->mac.type == ixgbe_mac_X550) 6378 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6379 #ifdef CONFIG_IXGBE_DCA 6380 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6381 #endif 6382 break; 6383 default: 6384 break; 6385 } 6386 6387 #ifdef IXGBE_FCOE 6388 /* FCoE support exists, always init the FCoE lock */ 6389 spin_lock_init(&adapter->fcoe.lock); 6390 6391 #endif 6392 /* n-tuple support exists, always init our spinlock */ 6393 spin_lock_init(&adapter->fdir_perfect_lock); 6394 6395 #ifdef CONFIG_IXGBE_DCB 6396 ixgbe_init_dcb(adapter); 6397 #endif 6398 ixgbe_init_ipsec_offload(adapter); 6399 6400 /* default flow control settings */ 6401 hw->fc.requested_mode = ixgbe_fc_full; 6402 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6403 ixgbe_pbthresh_setup(adapter); 6404 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6405 hw->fc.send_xon = true; 6406 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6407 6408 #ifdef CONFIG_PCI_IOV 6409 if (max_vfs > 0) 6410 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6411 6412 /* assign number of SR-IOV VFs */ 6413 if (hw->mac.type != ixgbe_mac_82598EB) { 6414 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6415 max_vfs = 0; 6416 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6417 } 6418 } 6419 #endif /* CONFIG_PCI_IOV */ 6420 6421 /* enable itr by default in dynamic mode */ 6422 adapter->rx_itr_setting = 1; 6423 adapter->tx_itr_setting = 1; 6424 6425 /* set default ring sizes */ 6426 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6427 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6428 6429 /* set default work limits */ 6430 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6431 6432 /* initialize eeprom parameters */ 6433 if (ixgbe_init_eeprom_params_generic(hw)) { 6434 e_dev_err("EEPROM initialization failed\n"); 6435 return -EIO; 6436 } 6437 6438 /* PF holds first pool slot */ 6439 set_bit(0, adapter->fwd_bitmask); 6440 set_bit(__IXGBE_DOWN, &adapter->state); 6441 6442 return 0; 6443 } 6444 6445 /** 6446 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6447 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6448 * 6449 * Return 0 on success, negative on failure 6450 **/ 6451 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6452 { 6453 struct device *dev = tx_ring->dev; 6454 int orig_node = dev_to_node(dev); 6455 int ring_node = NUMA_NO_NODE; 6456 int size; 6457 6458 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6459 6460 if (tx_ring->q_vector) 6461 ring_node = tx_ring->q_vector->numa_node; 6462 6463 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6464 if (!tx_ring->tx_buffer_info) 6465 tx_ring->tx_buffer_info = vmalloc(size); 6466 if (!tx_ring->tx_buffer_info) 6467 goto err; 6468 6469 /* round up to nearest 4K */ 6470 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6471 tx_ring->size = ALIGN(tx_ring->size, 4096); 6472 6473 set_dev_node(dev, ring_node); 6474 tx_ring->desc = dma_alloc_coherent(dev, 6475 tx_ring->size, 6476 &tx_ring->dma, 6477 GFP_KERNEL); 6478 set_dev_node(dev, orig_node); 6479 if (!tx_ring->desc) 6480 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6481 &tx_ring->dma, GFP_KERNEL); 6482 if (!tx_ring->desc) 6483 goto err; 6484 6485 tx_ring->next_to_use = 0; 6486 tx_ring->next_to_clean = 0; 6487 return 0; 6488 6489 err: 6490 vfree(tx_ring->tx_buffer_info); 6491 tx_ring->tx_buffer_info = NULL; 6492 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6493 return -ENOMEM; 6494 } 6495 6496 /** 6497 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6498 * @adapter: board private structure 6499 * 6500 * If this function returns with an error, then it's possible one or 6501 * more of the rings is populated (while the rest are not). It is the 6502 * callers duty to clean those orphaned rings. 6503 * 6504 * Return 0 on success, negative on failure 6505 **/ 6506 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6507 { 6508 int i, j = 0, err = 0; 6509 6510 for (i = 0; i < adapter->num_tx_queues; i++) { 6511 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6512 if (!err) 6513 continue; 6514 6515 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6516 goto err_setup_tx; 6517 } 6518 for (j = 0; j < adapter->num_xdp_queues; j++) { 6519 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6520 if (!err) 6521 continue; 6522 6523 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6524 goto err_setup_tx; 6525 } 6526 6527 return 0; 6528 err_setup_tx: 6529 /* rewind the index freeing the rings as we go */ 6530 while (j--) 6531 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6532 while (i--) 6533 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6534 return err; 6535 } 6536 6537 /** 6538 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6539 * @adapter: pointer to ixgbe_adapter 6540 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6541 * 6542 * Returns 0 on success, negative on failure 6543 **/ 6544 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6545 struct ixgbe_ring *rx_ring) 6546 { 6547 struct device *dev = rx_ring->dev; 6548 int orig_node = dev_to_node(dev); 6549 int ring_node = NUMA_NO_NODE; 6550 int size; 6551 6552 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6553 6554 if (rx_ring->q_vector) 6555 ring_node = rx_ring->q_vector->numa_node; 6556 6557 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6558 if (!rx_ring->rx_buffer_info) 6559 rx_ring->rx_buffer_info = vmalloc(size); 6560 if (!rx_ring->rx_buffer_info) 6561 goto err; 6562 6563 /* Round up to nearest 4K */ 6564 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6565 rx_ring->size = ALIGN(rx_ring->size, 4096); 6566 6567 set_dev_node(dev, ring_node); 6568 rx_ring->desc = dma_alloc_coherent(dev, 6569 rx_ring->size, 6570 &rx_ring->dma, 6571 GFP_KERNEL); 6572 set_dev_node(dev, orig_node); 6573 if (!rx_ring->desc) 6574 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6575 &rx_ring->dma, GFP_KERNEL); 6576 if (!rx_ring->desc) 6577 goto err; 6578 6579 rx_ring->next_to_clean = 0; 6580 rx_ring->next_to_use = 0; 6581 rx_ring->rx_offset = ixgbe_rx_offset(rx_ring); 6582 6583 /* XDP RX-queue info */ 6584 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6585 rx_ring->queue_index, rx_ring->q_vector->napi.napi_id) < 0) 6586 goto err; 6587 6588 rx_ring->xdp_prog = adapter->xdp_prog; 6589 6590 return 0; 6591 err: 6592 vfree(rx_ring->rx_buffer_info); 6593 rx_ring->rx_buffer_info = NULL; 6594 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6595 return -ENOMEM; 6596 } 6597 6598 /** 6599 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6600 * @adapter: board private structure 6601 * 6602 * If this function returns with an error, then it's possible one or 6603 * more of the rings is populated (while the rest are not). It is the 6604 * callers duty to clean those orphaned rings. 6605 * 6606 * Return 0 on success, negative on failure 6607 **/ 6608 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6609 { 6610 int i, err = 0; 6611 6612 for (i = 0; i < adapter->num_rx_queues; i++) { 6613 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6614 if (!err) 6615 continue; 6616 6617 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6618 goto err_setup_rx; 6619 } 6620 6621 #ifdef IXGBE_FCOE 6622 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6623 if (!err) 6624 #endif 6625 return 0; 6626 err_setup_rx: 6627 /* rewind the index freeing the rings as we go */ 6628 while (i--) 6629 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6630 return err; 6631 } 6632 6633 /** 6634 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6635 * @tx_ring: Tx descriptor ring for a specific queue 6636 * 6637 * Free all transmit software resources 6638 **/ 6639 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6640 { 6641 ixgbe_clean_tx_ring(tx_ring); 6642 6643 vfree(tx_ring->tx_buffer_info); 6644 tx_ring->tx_buffer_info = NULL; 6645 6646 /* if not set, then don't free */ 6647 if (!tx_ring->desc) 6648 return; 6649 6650 dma_free_coherent(tx_ring->dev, tx_ring->size, 6651 tx_ring->desc, tx_ring->dma); 6652 6653 tx_ring->desc = NULL; 6654 } 6655 6656 /** 6657 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6658 * @adapter: board private structure 6659 * 6660 * Free all transmit software resources 6661 **/ 6662 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6663 { 6664 int i; 6665 6666 for (i = 0; i < adapter->num_tx_queues; i++) 6667 if (adapter->tx_ring[i]->desc) 6668 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6669 for (i = 0; i < adapter->num_xdp_queues; i++) 6670 if (adapter->xdp_ring[i]->desc) 6671 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6672 } 6673 6674 /** 6675 * ixgbe_free_rx_resources - Free Rx Resources 6676 * @rx_ring: ring to clean the resources from 6677 * 6678 * Free all receive software resources 6679 **/ 6680 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6681 { 6682 ixgbe_clean_rx_ring(rx_ring); 6683 6684 rx_ring->xdp_prog = NULL; 6685 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6686 vfree(rx_ring->rx_buffer_info); 6687 rx_ring->rx_buffer_info = NULL; 6688 6689 /* if not set, then don't free */ 6690 if (!rx_ring->desc) 6691 return; 6692 6693 dma_free_coherent(rx_ring->dev, rx_ring->size, 6694 rx_ring->desc, rx_ring->dma); 6695 6696 rx_ring->desc = NULL; 6697 } 6698 6699 /** 6700 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6701 * @adapter: board private structure 6702 * 6703 * Free all receive software resources 6704 **/ 6705 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6706 { 6707 int i; 6708 6709 #ifdef IXGBE_FCOE 6710 ixgbe_free_fcoe_ddp_resources(adapter); 6711 6712 #endif 6713 for (i = 0; i < adapter->num_rx_queues; i++) 6714 if (adapter->rx_ring[i]->desc) 6715 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6716 } 6717 6718 /** 6719 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6720 * @netdev: network interface device structure 6721 * @new_mtu: new value for maximum frame size 6722 * 6723 * Returns 0 on success, negative on failure 6724 **/ 6725 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6726 { 6727 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6728 6729 if (adapter->xdp_prog) { 6730 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 6731 VLAN_HLEN; 6732 int i; 6733 6734 for (i = 0; i < adapter->num_rx_queues; i++) { 6735 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6736 6737 if (new_frame_size > ixgbe_rx_bufsz(ring)) { 6738 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6739 return -EINVAL; 6740 } 6741 } 6742 } 6743 6744 /* 6745 * For 82599EB we cannot allow legacy VFs to enable their receive 6746 * paths when MTU greater than 1500 is configured. So display a 6747 * warning that legacy VFs will be disabled. 6748 */ 6749 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6750 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6751 (new_mtu > ETH_DATA_LEN)) 6752 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6753 6754 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6755 netdev->mtu, new_mtu); 6756 6757 /* must set new MTU before calling down or up */ 6758 netdev->mtu = new_mtu; 6759 6760 if (netif_running(netdev)) 6761 ixgbe_reinit_locked(adapter); 6762 6763 return 0; 6764 } 6765 6766 /** 6767 * ixgbe_open - Called when a network interface is made active 6768 * @netdev: network interface device structure 6769 * 6770 * Returns 0 on success, negative value on failure 6771 * 6772 * The open entry point is called when a network interface is made 6773 * active by the system (IFF_UP). At this point all resources needed 6774 * for transmit and receive operations are allocated, the interrupt 6775 * handler is registered with the OS, the watchdog timer is started, 6776 * and the stack is notified that the interface is ready. 6777 **/ 6778 int ixgbe_open(struct net_device *netdev) 6779 { 6780 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6781 struct ixgbe_hw *hw = &adapter->hw; 6782 int err, queues; 6783 6784 /* disallow open during test */ 6785 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6786 return -EBUSY; 6787 6788 netif_carrier_off(netdev); 6789 6790 /* allocate transmit descriptors */ 6791 err = ixgbe_setup_all_tx_resources(adapter); 6792 if (err) 6793 goto err_setup_tx; 6794 6795 /* allocate receive descriptors */ 6796 err = ixgbe_setup_all_rx_resources(adapter); 6797 if (err) 6798 goto err_setup_rx; 6799 6800 ixgbe_configure(adapter); 6801 6802 err = ixgbe_request_irq(adapter); 6803 if (err) 6804 goto err_req_irq; 6805 6806 /* Notify the stack of the actual queue counts. */ 6807 queues = adapter->num_tx_queues; 6808 err = netif_set_real_num_tx_queues(netdev, queues); 6809 if (err) 6810 goto err_set_queues; 6811 6812 queues = adapter->num_rx_queues; 6813 err = netif_set_real_num_rx_queues(netdev, queues); 6814 if (err) 6815 goto err_set_queues; 6816 6817 ixgbe_ptp_init(adapter); 6818 6819 ixgbe_up_complete(adapter); 6820 6821 udp_tunnel_nic_reset_ntf(netdev); 6822 6823 return 0; 6824 6825 err_set_queues: 6826 ixgbe_free_irq(adapter); 6827 err_req_irq: 6828 ixgbe_free_all_rx_resources(adapter); 6829 if (hw->phy.ops.set_phy_power && !adapter->wol) 6830 hw->phy.ops.set_phy_power(&adapter->hw, false); 6831 err_setup_rx: 6832 ixgbe_free_all_tx_resources(adapter); 6833 err_setup_tx: 6834 ixgbe_reset(adapter); 6835 6836 return err; 6837 } 6838 6839 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6840 { 6841 ixgbe_ptp_suspend(adapter); 6842 6843 if (adapter->hw.phy.ops.enter_lplu) { 6844 adapter->hw.phy.reset_disable = true; 6845 ixgbe_down(adapter); 6846 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6847 adapter->hw.phy.reset_disable = false; 6848 } else { 6849 ixgbe_down(adapter); 6850 } 6851 6852 ixgbe_free_irq(adapter); 6853 6854 ixgbe_free_all_tx_resources(adapter); 6855 ixgbe_free_all_rx_resources(adapter); 6856 } 6857 6858 /** 6859 * ixgbe_close - Disables a network interface 6860 * @netdev: network interface device structure 6861 * 6862 * Returns 0, this is not allowed to fail 6863 * 6864 * The close entry point is called when an interface is de-activated 6865 * by the OS. The hardware is still under the drivers control, but 6866 * needs to be disabled. A global MAC reset is issued to stop the 6867 * hardware, and all transmit and receive resources are freed. 6868 **/ 6869 int ixgbe_close(struct net_device *netdev) 6870 { 6871 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6872 6873 ixgbe_ptp_stop(adapter); 6874 6875 if (netif_device_present(netdev)) 6876 ixgbe_close_suspend(adapter); 6877 6878 ixgbe_fdir_filter_exit(adapter); 6879 6880 ixgbe_release_hw_control(adapter); 6881 6882 return 0; 6883 } 6884 6885 static int __maybe_unused ixgbe_resume(struct device *dev_d) 6886 { 6887 struct pci_dev *pdev = to_pci_dev(dev_d); 6888 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6889 struct net_device *netdev = adapter->netdev; 6890 u32 err; 6891 6892 adapter->hw.hw_addr = adapter->io_addr; 6893 6894 smp_mb__before_atomic(); 6895 clear_bit(__IXGBE_DISABLED, &adapter->state); 6896 pci_set_master(pdev); 6897 6898 device_wakeup_disable(dev_d); 6899 6900 ixgbe_reset(adapter); 6901 6902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6903 6904 rtnl_lock(); 6905 err = ixgbe_init_interrupt_scheme(adapter); 6906 if (!err && netif_running(netdev)) 6907 err = ixgbe_open(netdev); 6908 6909 6910 if (!err) 6911 netif_device_attach(netdev); 6912 rtnl_unlock(); 6913 6914 return err; 6915 } 6916 6917 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6918 { 6919 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6920 struct net_device *netdev = adapter->netdev; 6921 struct ixgbe_hw *hw = &adapter->hw; 6922 u32 ctrl; 6923 u32 wufc = adapter->wol; 6924 6925 rtnl_lock(); 6926 netif_device_detach(netdev); 6927 6928 if (netif_running(netdev)) 6929 ixgbe_close_suspend(adapter); 6930 6931 ixgbe_clear_interrupt_scheme(adapter); 6932 rtnl_unlock(); 6933 6934 if (hw->mac.ops.stop_link_on_d3) 6935 hw->mac.ops.stop_link_on_d3(hw); 6936 6937 if (wufc) { 6938 u32 fctrl; 6939 6940 ixgbe_set_rx_mode(netdev); 6941 6942 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6943 if (hw->mac.ops.enable_tx_laser) 6944 hw->mac.ops.enable_tx_laser(hw); 6945 6946 /* enable the reception of multicast packets */ 6947 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6948 fctrl |= IXGBE_FCTRL_MPE; 6949 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6950 6951 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6952 ctrl |= IXGBE_CTRL_GIO_DIS; 6953 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6954 6955 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6956 } else { 6957 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6958 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6959 } 6960 6961 switch (hw->mac.type) { 6962 case ixgbe_mac_82598EB: 6963 pci_wake_from_d3(pdev, false); 6964 break; 6965 case ixgbe_mac_82599EB: 6966 case ixgbe_mac_X540: 6967 case ixgbe_mac_X550: 6968 case ixgbe_mac_X550EM_x: 6969 case ixgbe_mac_x550em_a: 6970 pci_wake_from_d3(pdev, !!wufc); 6971 break; 6972 default: 6973 break; 6974 } 6975 6976 *enable_wake = !!wufc; 6977 if (hw->phy.ops.set_phy_power && !*enable_wake) 6978 hw->phy.ops.set_phy_power(hw, false); 6979 6980 ixgbe_release_hw_control(adapter); 6981 6982 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6983 pci_disable_device(pdev); 6984 6985 return 0; 6986 } 6987 6988 static int __maybe_unused ixgbe_suspend(struct device *dev_d) 6989 { 6990 struct pci_dev *pdev = to_pci_dev(dev_d); 6991 int retval; 6992 bool wake; 6993 6994 retval = __ixgbe_shutdown(pdev, &wake); 6995 6996 device_set_wakeup_enable(dev_d, wake); 6997 6998 return retval; 6999 } 7000 7001 static void ixgbe_shutdown(struct pci_dev *pdev) 7002 { 7003 bool wake; 7004 7005 __ixgbe_shutdown(pdev, &wake); 7006 7007 if (system_state == SYSTEM_POWER_OFF) { 7008 pci_wake_from_d3(pdev, wake); 7009 pci_set_power_state(pdev, PCI_D3hot); 7010 } 7011 } 7012 7013 /** 7014 * ixgbe_update_stats - Update the board statistics counters. 7015 * @adapter: board private structure 7016 **/ 7017 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7018 { 7019 struct net_device *netdev = adapter->netdev; 7020 struct ixgbe_hw *hw = &adapter->hw; 7021 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7022 u64 total_mpc = 0; 7023 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7024 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7025 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7026 u64 alloc_rx_page = 0; 7027 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7028 7029 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7030 test_bit(__IXGBE_RESETTING, &adapter->state)) 7031 return; 7032 7033 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7034 u64 rsc_count = 0; 7035 u64 rsc_flush = 0; 7036 for (i = 0; i < adapter->num_rx_queues; i++) { 7037 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7038 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7039 } 7040 adapter->rsc_total_count = rsc_count; 7041 adapter->rsc_total_flush = rsc_flush; 7042 } 7043 7044 for (i = 0; i < adapter->num_rx_queues; i++) { 7045 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7046 7047 if (!rx_ring) 7048 continue; 7049 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7050 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7051 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7052 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7053 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7054 bytes += rx_ring->stats.bytes; 7055 packets += rx_ring->stats.packets; 7056 } 7057 adapter->non_eop_descs = non_eop_descs; 7058 adapter->alloc_rx_page = alloc_rx_page; 7059 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7060 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7061 adapter->hw_csum_rx_error = hw_csum_rx_error; 7062 netdev->stats.rx_bytes = bytes; 7063 netdev->stats.rx_packets = packets; 7064 7065 bytes = 0; 7066 packets = 0; 7067 /* gather some stats to the adapter struct that are per queue */ 7068 for (i = 0; i < adapter->num_tx_queues; i++) { 7069 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7070 7071 if (!tx_ring) 7072 continue; 7073 restart_queue += tx_ring->tx_stats.restart_queue; 7074 tx_busy += tx_ring->tx_stats.tx_busy; 7075 bytes += tx_ring->stats.bytes; 7076 packets += tx_ring->stats.packets; 7077 } 7078 for (i = 0; i < adapter->num_xdp_queues; i++) { 7079 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7080 7081 if (!xdp_ring) 7082 continue; 7083 restart_queue += xdp_ring->tx_stats.restart_queue; 7084 tx_busy += xdp_ring->tx_stats.tx_busy; 7085 bytes += xdp_ring->stats.bytes; 7086 packets += xdp_ring->stats.packets; 7087 } 7088 adapter->restart_queue = restart_queue; 7089 adapter->tx_busy = tx_busy; 7090 netdev->stats.tx_bytes = bytes; 7091 netdev->stats.tx_packets = packets; 7092 7093 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7094 7095 /* 8 register reads */ 7096 for (i = 0; i < 8; i++) { 7097 /* for packet buffers not used, the register should read 0 */ 7098 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7099 missed_rx += mpc; 7100 hwstats->mpc[i] += mpc; 7101 total_mpc += hwstats->mpc[i]; 7102 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7103 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7104 switch (hw->mac.type) { 7105 case ixgbe_mac_82598EB: 7106 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7107 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7108 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7109 hwstats->pxonrxc[i] += 7110 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7111 break; 7112 case ixgbe_mac_82599EB: 7113 case ixgbe_mac_X540: 7114 case ixgbe_mac_X550: 7115 case ixgbe_mac_X550EM_x: 7116 case ixgbe_mac_x550em_a: 7117 hwstats->pxonrxc[i] += 7118 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7119 break; 7120 default: 7121 break; 7122 } 7123 } 7124 7125 /*16 register reads */ 7126 for (i = 0; i < 16; i++) { 7127 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7128 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7129 if ((hw->mac.type == ixgbe_mac_82599EB) || 7130 (hw->mac.type == ixgbe_mac_X540) || 7131 (hw->mac.type == ixgbe_mac_X550) || 7132 (hw->mac.type == ixgbe_mac_X550EM_x) || 7133 (hw->mac.type == ixgbe_mac_x550em_a)) { 7134 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7135 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7136 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7137 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7138 } 7139 } 7140 7141 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7142 /* work around hardware counting issue */ 7143 hwstats->gprc -= missed_rx; 7144 7145 ixgbe_update_xoff_received(adapter); 7146 7147 /* 82598 hardware only has a 32 bit counter in the high register */ 7148 switch (hw->mac.type) { 7149 case ixgbe_mac_82598EB: 7150 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7151 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7152 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7153 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7154 break; 7155 case ixgbe_mac_X540: 7156 case ixgbe_mac_X550: 7157 case ixgbe_mac_X550EM_x: 7158 case ixgbe_mac_x550em_a: 7159 /* OS2BMC stats are X540 and later */ 7160 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7161 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7162 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7163 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7164 fallthrough; 7165 case ixgbe_mac_82599EB: 7166 for (i = 0; i < 16; i++) 7167 adapter->hw_rx_no_dma_resources += 7168 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7169 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7170 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7171 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7172 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7173 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7174 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7175 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7176 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7177 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7178 #ifdef IXGBE_FCOE 7179 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7180 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7181 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7182 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7183 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7184 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7185 /* Add up per cpu counters for total ddp aloc fail */ 7186 if (adapter->fcoe.ddp_pool) { 7187 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7188 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7189 unsigned int cpu; 7190 u64 noddp = 0, noddp_ext_buff = 0; 7191 for_each_possible_cpu(cpu) { 7192 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7193 noddp += ddp_pool->noddp; 7194 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7195 } 7196 hwstats->fcoe_noddp = noddp; 7197 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7198 } 7199 #endif /* IXGBE_FCOE */ 7200 break; 7201 default: 7202 break; 7203 } 7204 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7205 hwstats->bprc += bprc; 7206 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7207 if (hw->mac.type == ixgbe_mac_82598EB) 7208 hwstats->mprc -= bprc; 7209 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7210 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7211 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7212 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7213 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7214 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7215 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7216 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7217 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7218 hwstats->lxontxc += lxon; 7219 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7220 hwstats->lxofftxc += lxoff; 7221 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7222 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7223 /* 7224 * 82598 errata - tx of flow control packets is included in tx counters 7225 */ 7226 xon_off_tot = lxon + lxoff; 7227 hwstats->gptc -= xon_off_tot; 7228 hwstats->mptc -= xon_off_tot; 7229 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7230 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7231 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7232 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7233 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7234 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7235 hwstats->ptc64 -= xon_off_tot; 7236 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7237 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7238 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7239 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7240 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7241 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7242 7243 /* Fill out the OS statistics structure */ 7244 netdev->stats.multicast = hwstats->mprc; 7245 7246 /* Rx Errors */ 7247 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7248 netdev->stats.rx_dropped = 0; 7249 netdev->stats.rx_length_errors = hwstats->rlec; 7250 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7251 netdev->stats.rx_missed_errors = total_mpc; 7252 } 7253 7254 /** 7255 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7256 * @adapter: pointer to the device adapter structure 7257 **/ 7258 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7259 { 7260 struct ixgbe_hw *hw = &adapter->hw; 7261 int i; 7262 7263 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7264 return; 7265 7266 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7267 7268 /* if interface is down do nothing */ 7269 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7270 return; 7271 7272 /* do nothing if we are not using signature filters */ 7273 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7274 return; 7275 7276 adapter->fdir_overflow++; 7277 7278 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7279 for (i = 0; i < adapter->num_tx_queues; i++) 7280 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7281 &(adapter->tx_ring[i]->state)); 7282 for (i = 0; i < adapter->num_xdp_queues; i++) 7283 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7284 &adapter->xdp_ring[i]->state); 7285 /* re-enable flow director interrupts */ 7286 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7287 } else { 7288 e_err(probe, "failed to finish FDIR re-initialization, " 7289 "ignored adding FDIR ATR filters\n"); 7290 } 7291 } 7292 7293 /** 7294 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7295 * @adapter: pointer to the device adapter structure 7296 * 7297 * This function serves two purposes. First it strobes the interrupt lines 7298 * in order to make certain interrupts are occurring. Secondly it sets the 7299 * bits needed to check for TX hangs. As a result we should immediately 7300 * determine if a hang has occurred. 7301 */ 7302 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7303 { 7304 struct ixgbe_hw *hw = &adapter->hw; 7305 u64 eics = 0; 7306 int i; 7307 7308 /* If we're down, removing or resetting, just bail */ 7309 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7310 test_bit(__IXGBE_REMOVING, &adapter->state) || 7311 test_bit(__IXGBE_RESETTING, &adapter->state)) 7312 return; 7313 7314 /* Force detection of hung controller */ 7315 if (netif_carrier_ok(adapter->netdev)) { 7316 for (i = 0; i < adapter->num_tx_queues; i++) 7317 set_check_for_tx_hang(adapter->tx_ring[i]); 7318 for (i = 0; i < adapter->num_xdp_queues; i++) 7319 set_check_for_tx_hang(adapter->xdp_ring[i]); 7320 } 7321 7322 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7323 /* 7324 * for legacy and MSI interrupts don't set any bits 7325 * that are enabled for EIAM, because this operation 7326 * would set *both* EIMS and EICS for any bit in EIAM 7327 */ 7328 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7329 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7330 } else { 7331 /* get one bit for every active tx/rx interrupt vector */ 7332 for (i = 0; i < adapter->num_q_vectors; i++) { 7333 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7334 if (qv->rx.ring || qv->tx.ring) 7335 eics |= BIT_ULL(i); 7336 } 7337 } 7338 7339 /* Cause software interrupt to ensure rings are cleaned */ 7340 ixgbe_irq_rearm_queues(adapter, eics); 7341 } 7342 7343 /** 7344 * ixgbe_watchdog_update_link - update the link status 7345 * @adapter: pointer to the device adapter structure 7346 **/ 7347 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7348 { 7349 struct ixgbe_hw *hw = &adapter->hw; 7350 u32 link_speed = adapter->link_speed; 7351 bool link_up = adapter->link_up; 7352 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7353 7354 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7355 return; 7356 7357 if (hw->mac.ops.check_link) { 7358 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7359 } else { 7360 /* always assume link is up, if no check link function */ 7361 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7362 link_up = true; 7363 } 7364 7365 if (adapter->ixgbe_ieee_pfc) 7366 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7367 7368 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7369 hw->mac.ops.fc_enable(hw); 7370 ixgbe_set_rx_drop_en(adapter); 7371 } 7372 7373 if (link_up || 7374 time_after(jiffies, (adapter->link_check_timeout + 7375 IXGBE_TRY_LINK_TIMEOUT))) { 7376 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7377 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7378 IXGBE_WRITE_FLUSH(hw); 7379 } 7380 7381 adapter->link_up = link_up; 7382 adapter->link_speed = link_speed; 7383 } 7384 7385 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7386 { 7387 #ifdef CONFIG_IXGBE_DCB 7388 struct net_device *netdev = adapter->netdev; 7389 struct dcb_app app = { 7390 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7391 .protocol = 0, 7392 }; 7393 u8 up = 0; 7394 7395 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7396 up = dcb_ieee_getapp_mask(netdev, &app); 7397 7398 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7399 #endif 7400 } 7401 7402 /** 7403 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7404 * print link up message 7405 * @adapter: pointer to the device adapter structure 7406 **/ 7407 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7408 { 7409 struct net_device *netdev = adapter->netdev; 7410 struct ixgbe_hw *hw = &adapter->hw; 7411 u32 link_speed = adapter->link_speed; 7412 const char *speed_str; 7413 bool flow_rx, flow_tx; 7414 7415 /* only continue if link was previously down */ 7416 if (netif_carrier_ok(netdev)) 7417 return; 7418 7419 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7420 7421 switch (hw->mac.type) { 7422 case ixgbe_mac_82598EB: { 7423 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7424 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7425 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7426 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7427 } 7428 break; 7429 case ixgbe_mac_X540: 7430 case ixgbe_mac_X550: 7431 case ixgbe_mac_X550EM_x: 7432 case ixgbe_mac_x550em_a: 7433 case ixgbe_mac_82599EB: { 7434 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7435 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7436 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7437 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7438 } 7439 break; 7440 default: 7441 flow_tx = false; 7442 flow_rx = false; 7443 break; 7444 } 7445 7446 adapter->last_rx_ptp_check = jiffies; 7447 7448 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7449 ixgbe_ptp_start_cyclecounter(adapter); 7450 7451 switch (link_speed) { 7452 case IXGBE_LINK_SPEED_10GB_FULL: 7453 speed_str = "10 Gbps"; 7454 break; 7455 case IXGBE_LINK_SPEED_5GB_FULL: 7456 speed_str = "5 Gbps"; 7457 break; 7458 case IXGBE_LINK_SPEED_2_5GB_FULL: 7459 speed_str = "2.5 Gbps"; 7460 break; 7461 case IXGBE_LINK_SPEED_1GB_FULL: 7462 speed_str = "1 Gbps"; 7463 break; 7464 case IXGBE_LINK_SPEED_100_FULL: 7465 speed_str = "100 Mbps"; 7466 break; 7467 case IXGBE_LINK_SPEED_10_FULL: 7468 speed_str = "10 Mbps"; 7469 break; 7470 default: 7471 speed_str = "unknown speed"; 7472 break; 7473 } 7474 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7475 ((flow_rx && flow_tx) ? "RX/TX" : 7476 (flow_rx ? "RX" : 7477 (flow_tx ? "TX" : "None")))); 7478 7479 netif_carrier_on(netdev); 7480 ixgbe_check_vf_rate_limit(adapter); 7481 7482 /* enable transmits */ 7483 netif_tx_wake_all_queues(adapter->netdev); 7484 7485 /* update the default user priority for VFs */ 7486 ixgbe_update_default_up(adapter); 7487 7488 /* ping all the active vfs to let them know link has changed */ 7489 ixgbe_ping_all_vfs(adapter); 7490 } 7491 7492 /** 7493 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7494 * print link down message 7495 * @adapter: pointer to the adapter structure 7496 **/ 7497 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7498 { 7499 struct net_device *netdev = adapter->netdev; 7500 struct ixgbe_hw *hw = &adapter->hw; 7501 7502 adapter->link_up = false; 7503 adapter->link_speed = 0; 7504 7505 /* only continue if link was up previously */ 7506 if (!netif_carrier_ok(netdev)) 7507 return; 7508 7509 /* poll for SFP+ cable when link is down */ 7510 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7511 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7512 7513 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7514 ixgbe_ptp_start_cyclecounter(adapter); 7515 7516 e_info(drv, "NIC Link is Down\n"); 7517 netif_carrier_off(netdev); 7518 7519 /* ping all the active vfs to let them know link has changed */ 7520 ixgbe_ping_all_vfs(adapter); 7521 } 7522 7523 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7524 { 7525 int i; 7526 7527 for (i = 0; i < adapter->num_tx_queues; i++) { 7528 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7529 7530 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7531 return true; 7532 } 7533 7534 for (i = 0; i < adapter->num_xdp_queues; i++) { 7535 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7536 7537 if (ring->next_to_use != ring->next_to_clean) 7538 return true; 7539 } 7540 7541 return false; 7542 } 7543 7544 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7545 { 7546 struct ixgbe_hw *hw = &adapter->hw; 7547 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7548 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7549 7550 int i, j; 7551 7552 if (!adapter->num_vfs) 7553 return false; 7554 7555 /* resetting the PF is only needed for MAC before X550 */ 7556 if (hw->mac.type >= ixgbe_mac_X550) 7557 return false; 7558 7559 for (i = 0; i < adapter->num_vfs; i++) { 7560 for (j = 0; j < q_per_pool; j++) { 7561 u32 h, t; 7562 7563 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7564 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7565 7566 if (h != t) 7567 return true; 7568 } 7569 } 7570 7571 return false; 7572 } 7573 7574 /** 7575 * ixgbe_watchdog_flush_tx - flush queues on link down 7576 * @adapter: pointer to the device adapter structure 7577 **/ 7578 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7579 { 7580 if (!netif_carrier_ok(adapter->netdev)) { 7581 if (ixgbe_ring_tx_pending(adapter) || 7582 ixgbe_vf_tx_pending(adapter)) { 7583 /* We've lost link, so the controller stops DMA, 7584 * but we've got queued Tx work that's never going 7585 * to get done, so reset controller to flush Tx. 7586 * (Do the reset outside of interrupt context). 7587 */ 7588 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7589 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7590 } 7591 } 7592 } 7593 7594 #ifdef CONFIG_PCI_IOV 7595 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7596 { 7597 struct ixgbe_hw *hw = &adapter->hw; 7598 struct pci_dev *pdev = adapter->pdev; 7599 unsigned int vf; 7600 u32 gpc; 7601 7602 if (!(netif_carrier_ok(adapter->netdev))) 7603 return; 7604 7605 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7606 if (gpc) /* If incrementing then no need for the check below */ 7607 return; 7608 /* Check to see if a bad DMA write target from an errant or 7609 * malicious VF has caused a PCIe error. If so then we can 7610 * issue a VFLR to the offending VF(s) and then resume without 7611 * requesting a full slot reset. 7612 */ 7613 7614 if (!pdev) 7615 return; 7616 7617 /* check status reg for all VFs owned by this PF */ 7618 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7619 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7620 u16 status_reg; 7621 7622 if (!vfdev) 7623 continue; 7624 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7625 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7626 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7627 pcie_flr(vfdev); 7628 } 7629 } 7630 7631 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7632 { 7633 u32 ssvpc; 7634 7635 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7636 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7637 adapter->num_vfs == 0) 7638 return; 7639 7640 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7641 7642 /* 7643 * ssvpc register is cleared on read, if zero then no 7644 * spoofed packets in the last interval. 7645 */ 7646 if (!ssvpc) 7647 return; 7648 7649 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7650 } 7651 #else 7652 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7653 { 7654 } 7655 7656 static void 7657 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7658 { 7659 } 7660 #endif /* CONFIG_PCI_IOV */ 7661 7662 7663 /** 7664 * ixgbe_watchdog_subtask - check and bring link up 7665 * @adapter: pointer to the device adapter structure 7666 **/ 7667 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7668 { 7669 /* if interface is down, removing or resetting, do nothing */ 7670 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7671 test_bit(__IXGBE_REMOVING, &adapter->state) || 7672 test_bit(__IXGBE_RESETTING, &adapter->state)) 7673 return; 7674 7675 ixgbe_watchdog_update_link(adapter); 7676 7677 if (adapter->link_up) 7678 ixgbe_watchdog_link_is_up(adapter); 7679 else 7680 ixgbe_watchdog_link_is_down(adapter); 7681 7682 ixgbe_check_for_bad_vf(adapter); 7683 ixgbe_spoof_check(adapter); 7684 ixgbe_update_stats(adapter); 7685 7686 ixgbe_watchdog_flush_tx(adapter); 7687 } 7688 7689 /** 7690 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7691 * @adapter: the ixgbe adapter structure 7692 **/ 7693 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7694 { 7695 struct ixgbe_hw *hw = &adapter->hw; 7696 s32 err; 7697 7698 /* not searching for SFP so there is nothing to do here */ 7699 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7700 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7701 return; 7702 7703 if (adapter->sfp_poll_time && 7704 time_after(adapter->sfp_poll_time, jiffies)) 7705 return; /* If not yet time to poll for SFP */ 7706 7707 /* someone else is in init, wait until next service event */ 7708 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7709 return; 7710 7711 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7712 7713 err = hw->phy.ops.identify_sfp(hw); 7714 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7715 goto sfp_out; 7716 7717 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7718 /* If no cable is present, then we need to reset 7719 * the next time we find a good cable. */ 7720 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7721 } 7722 7723 /* exit on error */ 7724 if (err) 7725 goto sfp_out; 7726 7727 /* exit if reset not needed */ 7728 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7729 goto sfp_out; 7730 7731 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7732 7733 /* 7734 * A module may be identified correctly, but the EEPROM may not have 7735 * support for that module. setup_sfp() will fail in that case, so 7736 * we should not allow that module to load. 7737 */ 7738 if (hw->mac.type == ixgbe_mac_82598EB) 7739 err = hw->phy.ops.reset(hw); 7740 else 7741 err = hw->mac.ops.setup_sfp(hw); 7742 7743 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7744 goto sfp_out; 7745 7746 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7747 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7748 7749 sfp_out: 7750 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7751 7752 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7753 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7754 e_dev_err("failed to initialize because an unsupported " 7755 "SFP+ module type was detected.\n"); 7756 e_dev_err("Reload the driver after installing a " 7757 "supported module.\n"); 7758 unregister_netdev(adapter->netdev); 7759 } 7760 } 7761 7762 /** 7763 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7764 * @adapter: the ixgbe adapter structure 7765 **/ 7766 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7767 { 7768 struct ixgbe_hw *hw = &adapter->hw; 7769 u32 cap_speed; 7770 u32 speed; 7771 bool autoneg = false; 7772 7773 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7774 return; 7775 7776 /* someone else is in init, wait until next service event */ 7777 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7778 return; 7779 7780 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7781 7782 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7783 7784 /* advertise highest capable link speed */ 7785 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7786 speed = IXGBE_LINK_SPEED_10GB_FULL; 7787 else 7788 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7789 IXGBE_LINK_SPEED_1GB_FULL); 7790 7791 if (hw->mac.ops.setup_link) 7792 hw->mac.ops.setup_link(hw, speed, true); 7793 7794 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7795 adapter->link_check_timeout = jiffies; 7796 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7797 } 7798 7799 /** 7800 * ixgbe_service_timer - Timer Call-back 7801 * @t: pointer to timer_list structure 7802 **/ 7803 static void ixgbe_service_timer(struct timer_list *t) 7804 { 7805 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7806 unsigned long next_event_offset; 7807 7808 /* poll faster when waiting for link */ 7809 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7810 next_event_offset = HZ / 10; 7811 else 7812 next_event_offset = HZ * 2; 7813 7814 /* Reset the timer */ 7815 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7816 7817 ixgbe_service_event_schedule(adapter); 7818 } 7819 7820 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7821 { 7822 struct ixgbe_hw *hw = &adapter->hw; 7823 u32 status; 7824 7825 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7826 return; 7827 7828 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7829 7830 if (!hw->phy.ops.handle_lasi) 7831 return; 7832 7833 status = hw->phy.ops.handle_lasi(&adapter->hw); 7834 if (status != IXGBE_ERR_OVERTEMP) 7835 return; 7836 7837 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7838 } 7839 7840 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7841 { 7842 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7843 return; 7844 7845 rtnl_lock(); 7846 /* If we're already down, removing or resetting, just bail */ 7847 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7848 test_bit(__IXGBE_REMOVING, &adapter->state) || 7849 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7850 rtnl_unlock(); 7851 return; 7852 } 7853 7854 ixgbe_dump(adapter); 7855 netdev_err(adapter->netdev, "Reset adapter\n"); 7856 adapter->tx_timeout_count++; 7857 7858 ixgbe_reinit_locked(adapter); 7859 rtnl_unlock(); 7860 } 7861 7862 /** 7863 * ixgbe_check_fw_error - Check firmware for errors 7864 * @adapter: the adapter private structure 7865 * 7866 * Check firmware errors in register FWSM 7867 */ 7868 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7869 { 7870 struct ixgbe_hw *hw = &adapter->hw; 7871 u32 fwsm; 7872 7873 /* read fwsm.ext_err_ind register and log errors */ 7874 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7875 7876 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7877 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7878 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7879 fwsm); 7880 7881 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7882 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7883 return true; 7884 } 7885 7886 return false; 7887 } 7888 7889 /** 7890 * ixgbe_service_task - manages and runs subtasks 7891 * @work: pointer to work_struct containing our data 7892 **/ 7893 static void ixgbe_service_task(struct work_struct *work) 7894 { 7895 struct ixgbe_adapter *adapter = container_of(work, 7896 struct ixgbe_adapter, 7897 service_task); 7898 if (ixgbe_removed(adapter->hw.hw_addr)) { 7899 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7900 rtnl_lock(); 7901 ixgbe_down(adapter); 7902 rtnl_unlock(); 7903 } 7904 ixgbe_service_event_complete(adapter); 7905 return; 7906 } 7907 if (ixgbe_check_fw_error(adapter)) { 7908 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 7909 unregister_netdev(adapter->netdev); 7910 ixgbe_service_event_complete(adapter); 7911 return; 7912 } 7913 ixgbe_reset_subtask(adapter); 7914 ixgbe_phy_interrupt_subtask(adapter); 7915 ixgbe_sfp_detection_subtask(adapter); 7916 ixgbe_sfp_link_config_subtask(adapter); 7917 ixgbe_check_overtemp_subtask(adapter); 7918 ixgbe_watchdog_subtask(adapter); 7919 ixgbe_fdir_reinit_subtask(adapter); 7920 ixgbe_check_hang_subtask(adapter); 7921 7922 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7923 ixgbe_ptp_overflow_check(adapter); 7924 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7925 ixgbe_ptp_rx_hang(adapter); 7926 ixgbe_ptp_tx_hang(adapter); 7927 } 7928 7929 ixgbe_service_event_complete(adapter); 7930 } 7931 7932 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7933 struct ixgbe_tx_buffer *first, 7934 u8 *hdr_len, 7935 struct ixgbe_ipsec_tx_data *itd) 7936 { 7937 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7938 struct sk_buff *skb = first->skb; 7939 union { 7940 struct iphdr *v4; 7941 struct ipv6hdr *v6; 7942 unsigned char *hdr; 7943 } ip; 7944 union { 7945 struct tcphdr *tcp; 7946 struct udphdr *udp; 7947 unsigned char *hdr; 7948 } l4; 7949 u32 paylen, l4_offset; 7950 u32 fceof_saidx = 0; 7951 int err; 7952 7953 if (skb->ip_summed != CHECKSUM_PARTIAL) 7954 return 0; 7955 7956 if (!skb_is_gso(skb)) 7957 return 0; 7958 7959 err = skb_cow_head(skb, 0); 7960 if (err < 0) 7961 return err; 7962 7963 if (eth_p_mpls(first->protocol)) 7964 ip.hdr = skb_inner_network_header(skb); 7965 else 7966 ip.hdr = skb_network_header(skb); 7967 l4.hdr = skb_checksum_start(skb); 7968 7969 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7970 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 7971 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 7972 7973 /* initialize outer IP header fields */ 7974 if (ip.v4->version == 4) { 7975 unsigned char *csum_start = skb_checksum_start(skb); 7976 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7977 int len = csum_start - trans_start; 7978 7979 /* IP header will have to cancel out any data that 7980 * is not a part of the outer IP header, so set to 7981 * a reverse csum if needed, else init check to 0. 7982 */ 7983 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7984 csum_fold(csum_partial(trans_start, 7985 len, 0)) : 0; 7986 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7987 7988 ip.v4->tot_len = 0; 7989 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7990 IXGBE_TX_FLAGS_CSUM | 7991 IXGBE_TX_FLAGS_IPV4; 7992 } else { 7993 ip.v6->payload_len = 0; 7994 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7995 IXGBE_TX_FLAGS_CSUM; 7996 } 7997 7998 /* determine offset of inner transport header */ 7999 l4_offset = l4.hdr - skb->data; 8000 8001 /* remove payload length from inner checksum */ 8002 paylen = skb->len - l4_offset; 8003 8004 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8005 /* compute length of segmentation header */ 8006 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8007 csum_replace_by_diff(&l4.tcp->check, 8008 (__force __wsum)htonl(paylen)); 8009 } else { 8010 /* compute length of segmentation header */ 8011 *hdr_len = sizeof(*l4.udp) + l4_offset; 8012 csum_replace_by_diff(&l4.udp->check, 8013 (__force __wsum)htonl(paylen)); 8014 } 8015 8016 /* update gso size and bytecount with header size */ 8017 first->gso_segs = skb_shinfo(skb)->gso_segs; 8018 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8019 8020 /* mss_l4len_id: use 0 as index for TSO */ 8021 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8022 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8023 8024 fceof_saidx |= itd->sa_idx; 8025 type_tucmd |= itd->flags | itd->trailer_len; 8026 8027 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8028 vlan_macip_lens = l4.hdr - ip.hdr; 8029 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8030 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8031 8032 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8033 mss_l4len_idx); 8034 8035 return 1; 8036 } 8037 8038 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8039 struct ixgbe_tx_buffer *first, 8040 struct ixgbe_ipsec_tx_data *itd) 8041 { 8042 struct sk_buff *skb = first->skb; 8043 u32 vlan_macip_lens = 0; 8044 u32 fceof_saidx = 0; 8045 u32 type_tucmd = 0; 8046 8047 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8048 csum_failed: 8049 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8050 IXGBE_TX_FLAGS_CC))) 8051 return; 8052 goto no_csum; 8053 } 8054 8055 switch (skb->csum_offset) { 8056 case offsetof(struct tcphdr, check): 8057 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8058 fallthrough; 8059 case offsetof(struct udphdr, check): 8060 break; 8061 case offsetof(struct sctphdr, checksum): 8062 /* validate that this is actually an SCTP request */ 8063 if (skb_csum_is_sctp(skb)) { 8064 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8065 break; 8066 } 8067 fallthrough; 8068 default: 8069 skb_checksum_help(skb); 8070 goto csum_failed; 8071 } 8072 8073 /* update TX checksum flag */ 8074 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8075 vlan_macip_lens = skb_checksum_start_offset(skb) - 8076 skb_network_offset(skb); 8077 no_csum: 8078 /* vlan_macip_lens: MACLEN, VLAN tag */ 8079 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8080 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8081 8082 fceof_saidx |= itd->sa_idx; 8083 type_tucmd |= itd->flags | itd->trailer_len; 8084 8085 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8086 } 8087 8088 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8089 ((_flag <= _result) ? \ 8090 ((u32)(_input & _flag) * (_result / _flag)) : \ 8091 ((u32)(_input & _flag) / (_flag / _result))) 8092 8093 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8094 { 8095 /* set type for advanced descriptor with frame checksum insertion */ 8096 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8097 IXGBE_ADVTXD_DCMD_DEXT | 8098 IXGBE_ADVTXD_DCMD_IFCS; 8099 8100 /* set HW vlan bit if vlan is present */ 8101 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8102 IXGBE_ADVTXD_DCMD_VLE); 8103 8104 /* set segmentation enable bits for TSO/FSO */ 8105 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8106 IXGBE_ADVTXD_DCMD_TSE); 8107 8108 /* set timestamp bit if present */ 8109 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8110 IXGBE_ADVTXD_MAC_TSTAMP); 8111 8112 /* insert frame checksum */ 8113 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8114 8115 return cmd_type; 8116 } 8117 8118 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8119 u32 tx_flags, unsigned int paylen) 8120 { 8121 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8122 8123 /* enable L4 checksum for TSO and TX checksum offload */ 8124 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8125 IXGBE_TX_FLAGS_CSUM, 8126 IXGBE_ADVTXD_POPTS_TXSM); 8127 8128 /* enable IPv4 checksum for TSO */ 8129 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8130 IXGBE_TX_FLAGS_IPV4, 8131 IXGBE_ADVTXD_POPTS_IXSM); 8132 8133 /* enable IPsec */ 8134 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8135 IXGBE_TX_FLAGS_IPSEC, 8136 IXGBE_ADVTXD_POPTS_IPSEC); 8137 8138 /* 8139 * Check Context must be set if Tx switch is enabled, which it 8140 * always is for case where virtual functions are running 8141 */ 8142 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8143 IXGBE_TX_FLAGS_CC, 8144 IXGBE_ADVTXD_CC); 8145 8146 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8147 } 8148 8149 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8150 { 8151 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8152 8153 /* Herbert's original patch had: 8154 * smp_mb__after_netif_stop_queue(); 8155 * but since that doesn't exist yet, just open code it. 8156 */ 8157 smp_mb(); 8158 8159 /* We need to check again in a case another CPU has just 8160 * made room available. 8161 */ 8162 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8163 return -EBUSY; 8164 8165 /* A reprieve! - use start_queue because it doesn't call schedule */ 8166 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8167 ++tx_ring->tx_stats.restart_queue; 8168 return 0; 8169 } 8170 8171 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8172 { 8173 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8174 return 0; 8175 8176 return __ixgbe_maybe_stop_tx(tx_ring, size); 8177 } 8178 8179 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8180 struct ixgbe_tx_buffer *first, 8181 const u8 hdr_len) 8182 { 8183 struct sk_buff *skb = first->skb; 8184 struct ixgbe_tx_buffer *tx_buffer; 8185 union ixgbe_adv_tx_desc *tx_desc; 8186 skb_frag_t *frag; 8187 dma_addr_t dma; 8188 unsigned int data_len, size; 8189 u32 tx_flags = first->tx_flags; 8190 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8191 u16 i = tx_ring->next_to_use; 8192 8193 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8194 8195 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8196 8197 size = skb_headlen(skb); 8198 data_len = skb->data_len; 8199 8200 #ifdef IXGBE_FCOE 8201 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8202 if (data_len < sizeof(struct fcoe_crc_eof)) { 8203 size -= sizeof(struct fcoe_crc_eof) - data_len; 8204 data_len = 0; 8205 } else { 8206 data_len -= sizeof(struct fcoe_crc_eof); 8207 } 8208 } 8209 8210 #endif 8211 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8212 8213 tx_buffer = first; 8214 8215 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8216 if (dma_mapping_error(tx_ring->dev, dma)) 8217 goto dma_error; 8218 8219 /* record length, and DMA address */ 8220 dma_unmap_len_set(tx_buffer, len, size); 8221 dma_unmap_addr_set(tx_buffer, dma, dma); 8222 8223 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8224 8225 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8226 tx_desc->read.cmd_type_len = 8227 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8228 8229 i++; 8230 tx_desc++; 8231 if (i == tx_ring->count) { 8232 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8233 i = 0; 8234 } 8235 tx_desc->read.olinfo_status = 0; 8236 8237 dma += IXGBE_MAX_DATA_PER_TXD; 8238 size -= IXGBE_MAX_DATA_PER_TXD; 8239 8240 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8241 } 8242 8243 if (likely(!data_len)) 8244 break; 8245 8246 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8247 8248 i++; 8249 tx_desc++; 8250 if (i == tx_ring->count) { 8251 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8252 i = 0; 8253 } 8254 tx_desc->read.olinfo_status = 0; 8255 8256 #ifdef IXGBE_FCOE 8257 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8258 #else 8259 size = skb_frag_size(frag); 8260 #endif 8261 data_len -= size; 8262 8263 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8264 DMA_TO_DEVICE); 8265 8266 tx_buffer = &tx_ring->tx_buffer_info[i]; 8267 } 8268 8269 /* write last descriptor with RS and EOP bits */ 8270 cmd_type |= size | IXGBE_TXD_CMD; 8271 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8272 8273 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8274 8275 /* set the timestamp */ 8276 first->time_stamp = jiffies; 8277 8278 skb_tx_timestamp(skb); 8279 8280 /* 8281 * Force memory writes to complete before letting h/w know there 8282 * are new descriptors to fetch. (Only applicable for weak-ordered 8283 * memory model archs, such as IA-64). 8284 * 8285 * We also need this memory barrier to make certain all of the 8286 * status bits have been updated before next_to_watch is written. 8287 */ 8288 wmb(); 8289 8290 /* set next_to_watch value indicating a packet is present */ 8291 first->next_to_watch = tx_desc; 8292 8293 i++; 8294 if (i == tx_ring->count) 8295 i = 0; 8296 8297 tx_ring->next_to_use = i; 8298 8299 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8300 8301 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8302 writel(i, tx_ring->tail); 8303 } 8304 8305 return 0; 8306 dma_error: 8307 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8308 8309 /* clear dma mappings for failed tx_buffer_info map */ 8310 for (;;) { 8311 tx_buffer = &tx_ring->tx_buffer_info[i]; 8312 if (dma_unmap_len(tx_buffer, len)) 8313 dma_unmap_page(tx_ring->dev, 8314 dma_unmap_addr(tx_buffer, dma), 8315 dma_unmap_len(tx_buffer, len), 8316 DMA_TO_DEVICE); 8317 dma_unmap_len_set(tx_buffer, len, 0); 8318 if (tx_buffer == first) 8319 break; 8320 if (i == 0) 8321 i += tx_ring->count; 8322 i--; 8323 } 8324 8325 dev_kfree_skb_any(first->skb); 8326 first->skb = NULL; 8327 8328 tx_ring->next_to_use = i; 8329 8330 return -1; 8331 } 8332 8333 static void ixgbe_atr(struct ixgbe_ring *ring, 8334 struct ixgbe_tx_buffer *first) 8335 { 8336 struct ixgbe_q_vector *q_vector = ring->q_vector; 8337 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8338 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8339 union { 8340 unsigned char *network; 8341 struct iphdr *ipv4; 8342 struct ipv6hdr *ipv6; 8343 } hdr; 8344 struct tcphdr *th; 8345 unsigned int hlen; 8346 struct sk_buff *skb; 8347 __be16 vlan_id; 8348 int l4_proto; 8349 8350 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8351 if (!q_vector) 8352 return; 8353 8354 /* do nothing if sampling is disabled */ 8355 if (!ring->atr_sample_rate) 8356 return; 8357 8358 ring->atr_count++; 8359 8360 /* currently only IPv4/IPv6 with TCP is supported */ 8361 if ((first->protocol != htons(ETH_P_IP)) && 8362 (first->protocol != htons(ETH_P_IPV6))) 8363 return; 8364 8365 /* snag network header to get L4 type and address */ 8366 skb = first->skb; 8367 hdr.network = skb_network_header(skb); 8368 if (unlikely(hdr.network <= skb->data)) 8369 return; 8370 if (skb->encapsulation && 8371 first->protocol == htons(ETH_P_IP) && 8372 hdr.ipv4->protocol == IPPROTO_UDP) { 8373 struct ixgbe_adapter *adapter = q_vector->adapter; 8374 8375 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8376 VXLAN_HEADROOM)) 8377 return; 8378 8379 /* verify the port is recognized as VXLAN */ 8380 if (adapter->vxlan_port && 8381 udp_hdr(skb)->dest == adapter->vxlan_port) 8382 hdr.network = skb_inner_network_header(skb); 8383 8384 if (adapter->geneve_port && 8385 udp_hdr(skb)->dest == adapter->geneve_port) 8386 hdr.network = skb_inner_network_header(skb); 8387 } 8388 8389 /* Make sure we have at least [minimum IPv4 header + TCP] 8390 * or [IPv6 header] bytes 8391 */ 8392 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8393 return; 8394 8395 /* Currently only IPv4/IPv6 with TCP is supported */ 8396 switch (hdr.ipv4->version) { 8397 case IPVERSION: 8398 /* access ihl as u8 to avoid unaligned access on ia64 */ 8399 hlen = (hdr.network[0] & 0x0F) << 2; 8400 l4_proto = hdr.ipv4->protocol; 8401 break; 8402 case 6: 8403 hlen = hdr.network - skb->data; 8404 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8405 hlen -= hdr.network - skb->data; 8406 break; 8407 default: 8408 return; 8409 } 8410 8411 if (l4_proto != IPPROTO_TCP) 8412 return; 8413 8414 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8415 hlen + sizeof(struct tcphdr))) 8416 return; 8417 8418 th = (struct tcphdr *)(hdr.network + hlen); 8419 8420 /* skip this packet since the socket is closing */ 8421 if (th->fin) 8422 return; 8423 8424 /* sample on all syn packets or once every atr sample count */ 8425 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8426 return; 8427 8428 /* reset sample count */ 8429 ring->atr_count = 0; 8430 8431 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8432 8433 /* 8434 * src and dst are inverted, think how the receiver sees them 8435 * 8436 * The input is broken into two sections, a non-compressed section 8437 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8438 * is XORed together and stored in the compressed dword. 8439 */ 8440 input.formatted.vlan_id = vlan_id; 8441 8442 /* 8443 * since src port and flex bytes occupy the same word XOR them together 8444 * and write the value to source port portion of compressed dword 8445 */ 8446 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8447 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8448 else 8449 common.port.src ^= th->dest ^ first->protocol; 8450 common.port.dst ^= th->source; 8451 8452 switch (hdr.ipv4->version) { 8453 case IPVERSION: 8454 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8455 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8456 break; 8457 case 6: 8458 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8459 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8460 hdr.ipv6->saddr.s6_addr32[1] ^ 8461 hdr.ipv6->saddr.s6_addr32[2] ^ 8462 hdr.ipv6->saddr.s6_addr32[3] ^ 8463 hdr.ipv6->daddr.s6_addr32[0] ^ 8464 hdr.ipv6->daddr.s6_addr32[1] ^ 8465 hdr.ipv6->daddr.s6_addr32[2] ^ 8466 hdr.ipv6->daddr.s6_addr32[3]; 8467 break; 8468 default: 8469 break; 8470 } 8471 8472 if (hdr.network != skb_network_header(skb)) 8473 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8474 8475 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8476 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8477 input, common, ring->queue_index); 8478 } 8479 8480 #ifdef IXGBE_FCOE 8481 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8482 struct net_device *sb_dev) 8483 { 8484 struct ixgbe_adapter *adapter; 8485 struct ixgbe_ring_feature *f; 8486 int txq; 8487 8488 if (sb_dev) { 8489 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8490 struct net_device *vdev = sb_dev; 8491 8492 txq = vdev->tc_to_txq[tc].offset; 8493 txq += reciprocal_scale(skb_get_hash(skb), 8494 vdev->tc_to_txq[tc].count); 8495 8496 return txq; 8497 } 8498 8499 /* 8500 * only execute the code below if protocol is FCoE 8501 * or FIP and we have FCoE enabled on the adapter 8502 */ 8503 switch (vlan_get_protocol(skb)) { 8504 case htons(ETH_P_FCOE): 8505 case htons(ETH_P_FIP): 8506 adapter = netdev_priv(dev); 8507 8508 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8509 break; 8510 fallthrough; 8511 default: 8512 return netdev_pick_tx(dev, skb, sb_dev); 8513 } 8514 8515 f = &adapter->ring_feature[RING_F_FCOE]; 8516 8517 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8518 smp_processor_id(); 8519 8520 while (txq >= f->indices) 8521 txq -= f->indices; 8522 8523 return txq + f->offset; 8524 } 8525 8526 #endif 8527 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8528 struct xdp_frame *xdpf) 8529 { 8530 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8531 struct ixgbe_tx_buffer *tx_buffer; 8532 union ixgbe_adv_tx_desc *tx_desc; 8533 u32 len, cmd_type; 8534 dma_addr_t dma; 8535 u16 i; 8536 8537 len = xdpf->len; 8538 8539 if (unlikely(!ixgbe_desc_unused(ring))) 8540 return IXGBE_XDP_CONSUMED; 8541 8542 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8543 if (dma_mapping_error(ring->dev, dma)) 8544 return IXGBE_XDP_CONSUMED; 8545 8546 /* record the location of the first descriptor for this packet */ 8547 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8548 tx_buffer->bytecount = len; 8549 tx_buffer->gso_segs = 1; 8550 tx_buffer->protocol = 0; 8551 8552 i = ring->next_to_use; 8553 tx_desc = IXGBE_TX_DESC(ring, i); 8554 8555 dma_unmap_len_set(tx_buffer, len, len); 8556 dma_unmap_addr_set(tx_buffer, dma, dma); 8557 tx_buffer->xdpf = xdpf; 8558 8559 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8560 8561 /* put descriptor type bits */ 8562 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8563 IXGBE_ADVTXD_DCMD_DEXT | 8564 IXGBE_ADVTXD_DCMD_IFCS; 8565 cmd_type |= len | IXGBE_TXD_CMD; 8566 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8567 tx_desc->read.olinfo_status = 8568 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8569 8570 /* Avoid any potential race with xdp_xmit and cleanup */ 8571 smp_wmb(); 8572 8573 /* set next_to_watch value indicating a packet is present */ 8574 i++; 8575 if (i == ring->count) 8576 i = 0; 8577 8578 tx_buffer->next_to_watch = tx_desc; 8579 ring->next_to_use = i; 8580 8581 return IXGBE_XDP_TX; 8582 } 8583 8584 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8585 struct ixgbe_adapter *adapter, 8586 struct ixgbe_ring *tx_ring) 8587 { 8588 struct ixgbe_tx_buffer *first; 8589 int tso; 8590 u32 tx_flags = 0; 8591 unsigned short f; 8592 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8593 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8594 __be16 protocol = skb->protocol; 8595 u8 hdr_len = 0; 8596 8597 /* 8598 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8599 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8600 * + 2 desc gap to keep tail from touching head, 8601 * + 1 desc for context descriptor, 8602 * otherwise try next time 8603 */ 8604 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8605 count += TXD_USE_COUNT(skb_frag_size( 8606 &skb_shinfo(skb)->frags[f])); 8607 8608 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8609 tx_ring->tx_stats.tx_busy++; 8610 return NETDEV_TX_BUSY; 8611 } 8612 8613 /* record the location of the first descriptor for this packet */ 8614 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8615 first->skb = skb; 8616 first->bytecount = skb->len; 8617 first->gso_segs = 1; 8618 8619 /* if we have a HW VLAN tag being added default to the HW one */ 8620 if (skb_vlan_tag_present(skb)) { 8621 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8622 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8623 /* else if it is a SW VLAN check the next protocol and store the tag */ 8624 } else if (protocol == htons(ETH_P_8021Q)) { 8625 struct vlan_hdr *vhdr, _vhdr; 8626 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8627 if (!vhdr) 8628 goto out_drop; 8629 8630 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8631 IXGBE_TX_FLAGS_VLAN_SHIFT; 8632 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8633 } 8634 protocol = vlan_get_protocol(skb); 8635 8636 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8637 adapter->ptp_clock) { 8638 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 8639 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8640 &adapter->state)) { 8641 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8642 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8643 8644 /* schedule check for Tx timestamp */ 8645 adapter->ptp_tx_skb = skb_get(skb); 8646 adapter->ptp_tx_start = jiffies; 8647 schedule_work(&adapter->ptp_tx_work); 8648 } else { 8649 adapter->tx_hwtstamp_skipped++; 8650 } 8651 } 8652 8653 #ifdef CONFIG_PCI_IOV 8654 /* 8655 * Use the l2switch_enable flag - would be false if the DMA 8656 * Tx switch had been disabled. 8657 */ 8658 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8659 tx_flags |= IXGBE_TX_FLAGS_CC; 8660 8661 #endif 8662 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8663 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8664 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8665 (skb->priority != TC_PRIO_CONTROL))) { 8666 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8667 tx_flags |= (skb->priority & 0x7) << 8668 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8669 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8670 struct vlan_ethhdr *vhdr; 8671 8672 if (skb_cow_head(skb, 0)) 8673 goto out_drop; 8674 vhdr = (struct vlan_ethhdr *)skb->data; 8675 vhdr->h_vlan_TCI = htons(tx_flags >> 8676 IXGBE_TX_FLAGS_VLAN_SHIFT); 8677 } else { 8678 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8679 } 8680 } 8681 8682 /* record initial flags and protocol */ 8683 first->tx_flags = tx_flags; 8684 first->protocol = protocol; 8685 8686 #ifdef IXGBE_FCOE 8687 /* setup tx offload for FCoE */ 8688 if ((protocol == htons(ETH_P_FCOE)) && 8689 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8690 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8691 if (tso < 0) 8692 goto out_drop; 8693 8694 goto xmit_fcoe; 8695 } 8696 8697 #endif /* IXGBE_FCOE */ 8698 8699 #ifdef CONFIG_IXGBE_IPSEC 8700 if (xfrm_offload(skb) && 8701 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8702 goto out_drop; 8703 #endif 8704 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8705 if (tso < 0) 8706 goto out_drop; 8707 else if (!tso) 8708 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8709 8710 /* add the ATR filter if ATR is on */ 8711 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8712 ixgbe_atr(tx_ring, first); 8713 8714 #ifdef IXGBE_FCOE 8715 xmit_fcoe: 8716 #endif /* IXGBE_FCOE */ 8717 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8718 goto cleanup_tx_timestamp; 8719 8720 return NETDEV_TX_OK; 8721 8722 out_drop: 8723 dev_kfree_skb_any(first->skb); 8724 first->skb = NULL; 8725 cleanup_tx_timestamp: 8726 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8727 dev_kfree_skb_any(adapter->ptp_tx_skb); 8728 adapter->ptp_tx_skb = NULL; 8729 cancel_work_sync(&adapter->ptp_tx_work); 8730 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8731 } 8732 8733 return NETDEV_TX_OK; 8734 } 8735 8736 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8737 struct net_device *netdev, 8738 struct ixgbe_ring *ring) 8739 { 8740 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8741 struct ixgbe_ring *tx_ring; 8742 8743 /* 8744 * The minimum packet size for olinfo paylen is 17 so pad the skb 8745 * in order to meet this minimum size requirement. 8746 */ 8747 if (skb_put_padto(skb, 17)) 8748 return NETDEV_TX_OK; 8749 8750 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 8751 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8752 return NETDEV_TX_BUSY; 8753 8754 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8755 } 8756 8757 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8758 struct net_device *netdev) 8759 { 8760 return __ixgbe_xmit_frame(skb, netdev, NULL); 8761 } 8762 8763 /** 8764 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8765 * @netdev: network interface device structure 8766 * @p: pointer to an address structure 8767 * 8768 * Returns 0 on success, negative on failure 8769 **/ 8770 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8771 { 8772 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8773 struct ixgbe_hw *hw = &adapter->hw; 8774 struct sockaddr *addr = p; 8775 8776 if (!is_valid_ether_addr(addr->sa_data)) 8777 return -EADDRNOTAVAIL; 8778 8779 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8780 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8781 8782 ixgbe_mac_set_default_filter(adapter); 8783 8784 return 0; 8785 } 8786 8787 static int 8788 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8789 { 8790 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8791 struct ixgbe_hw *hw = &adapter->hw; 8792 u16 value; 8793 int rc; 8794 8795 if (adapter->mii_bus) { 8796 int regnum = addr; 8797 8798 if (devad != MDIO_DEVAD_NONE) 8799 regnum |= (devad << 16) | MII_ADDR_C45; 8800 8801 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8802 } 8803 8804 if (prtad != hw->phy.mdio.prtad) 8805 return -EINVAL; 8806 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8807 if (!rc) 8808 rc = value; 8809 return rc; 8810 } 8811 8812 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8813 u16 addr, u16 value) 8814 { 8815 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8816 struct ixgbe_hw *hw = &adapter->hw; 8817 8818 if (adapter->mii_bus) { 8819 int regnum = addr; 8820 8821 if (devad != MDIO_DEVAD_NONE) 8822 regnum |= (devad << 16) | MII_ADDR_C45; 8823 8824 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8825 } 8826 8827 if (prtad != hw->phy.mdio.prtad) 8828 return -EINVAL; 8829 return hw->phy.ops.write_reg(hw, addr, devad, value); 8830 } 8831 8832 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8833 { 8834 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8835 8836 switch (cmd) { 8837 case SIOCSHWTSTAMP: 8838 return ixgbe_ptp_set_ts_config(adapter, req); 8839 case SIOCGHWTSTAMP: 8840 return ixgbe_ptp_get_ts_config(adapter, req); 8841 case SIOCGMIIPHY: 8842 if (!adapter->hw.phy.ops.read_reg) 8843 return -EOPNOTSUPP; 8844 fallthrough; 8845 default: 8846 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8847 } 8848 } 8849 8850 /** 8851 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8852 * netdev->dev_addrs 8853 * @dev: network interface device structure 8854 * 8855 * Returns non-zero on failure 8856 **/ 8857 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8858 { 8859 int err = 0; 8860 struct ixgbe_adapter *adapter = netdev_priv(dev); 8861 struct ixgbe_hw *hw = &adapter->hw; 8862 8863 if (is_valid_ether_addr(hw->mac.san_addr)) { 8864 rtnl_lock(); 8865 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8866 rtnl_unlock(); 8867 8868 /* update SAN MAC vmdq pool selection */ 8869 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8870 } 8871 return err; 8872 } 8873 8874 /** 8875 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8876 * netdev->dev_addrs 8877 * @dev: network interface device structure 8878 * 8879 * Returns non-zero on failure 8880 **/ 8881 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8882 { 8883 int err = 0; 8884 struct ixgbe_adapter *adapter = netdev_priv(dev); 8885 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8886 8887 if (is_valid_ether_addr(mac->san_addr)) { 8888 rtnl_lock(); 8889 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8890 rtnl_unlock(); 8891 } 8892 return err; 8893 } 8894 8895 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8896 struct ixgbe_ring *ring) 8897 { 8898 u64 bytes, packets; 8899 unsigned int start; 8900 8901 if (ring) { 8902 do { 8903 start = u64_stats_fetch_begin_irq(&ring->syncp); 8904 packets = ring->stats.packets; 8905 bytes = ring->stats.bytes; 8906 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8907 stats->tx_packets += packets; 8908 stats->tx_bytes += bytes; 8909 } 8910 } 8911 8912 static void ixgbe_get_stats64(struct net_device *netdev, 8913 struct rtnl_link_stats64 *stats) 8914 { 8915 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8916 int i; 8917 8918 rcu_read_lock(); 8919 for (i = 0; i < adapter->num_rx_queues; i++) { 8920 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8921 u64 bytes, packets; 8922 unsigned int start; 8923 8924 if (ring) { 8925 do { 8926 start = u64_stats_fetch_begin_irq(&ring->syncp); 8927 packets = ring->stats.packets; 8928 bytes = ring->stats.bytes; 8929 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8930 stats->rx_packets += packets; 8931 stats->rx_bytes += bytes; 8932 } 8933 } 8934 8935 for (i = 0; i < adapter->num_tx_queues; i++) { 8936 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8937 8938 ixgbe_get_ring_stats64(stats, ring); 8939 } 8940 for (i = 0; i < adapter->num_xdp_queues; i++) { 8941 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8942 8943 ixgbe_get_ring_stats64(stats, ring); 8944 } 8945 rcu_read_unlock(); 8946 8947 /* following stats updated by ixgbe_watchdog_task() */ 8948 stats->multicast = netdev->stats.multicast; 8949 stats->rx_errors = netdev->stats.rx_errors; 8950 stats->rx_length_errors = netdev->stats.rx_length_errors; 8951 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8952 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8953 } 8954 8955 #ifdef CONFIG_IXGBE_DCB 8956 /** 8957 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8958 * @adapter: pointer to ixgbe_adapter 8959 * @tc: number of traffic classes currently enabled 8960 * 8961 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8962 * 802.1Q priority maps to a packet buffer that exists. 8963 */ 8964 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8965 { 8966 struct ixgbe_hw *hw = &adapter->hw; 8967 u32 reg, rsave; 8968 int i; 8969 8970 /* 82598 have a static priority to TC mapping that can not 8971 * be changed so no validation is needed. 8972 */ 8973 if (hw->mac.type == ixgbe_mac_82598EB) 8974 return; 8975 8976 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8977 rsave = reg; 8978 8979 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8980 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8981 8982 /* If up2tc is out of bounds default to zero */ 8983 if (up2tc > tc) 8984 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8985 } 8986 8987 if (reg != rsave) 8988 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8989 8990 return; 8991 } 8992 8993 /** 8994 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8995 * @adapter: Pointer to adapter struct 8996 * 8997 * Populate the netdev user priority to tc map 8998 */ 8999 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9000 { 9001 struct net_device *dev = adapter->netdev; 9002 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9003 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9004 u8 prio; 9005 9006 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9007 u8 tc = 0; 9008 9009 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9010 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9011 else if (ets) 9012 tc = ets->prio_tc[prio]; 9013 9014 netdev_set_prio_tc_map(dev, prio, tc); 9015 } 9016 } 9017 9018 #endif /* CONFIG_IXGBE_DCB */ 9019 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9020 struct netdev_nested_priv *priv) 9021 { 9022 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9023 struct ixgbe_fwd_adapter *accel; 9024 int pool; 9025 9026 /* we only care about macvlans... */ 9027 if (!netif_is_macvlan(vdev)) 9028 return 0; 9029 9030 /* that have hardware offload enabled... */ 9031 accel = macvlan_accel_priv(vdev); 9032 if (!accel) 9033 return 0; 9034 9035 /* If we can relocate to a different bit do so */ 9036 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9037 if (pool < adapter->num_rx_pools) { 9038 set_bit(pool, adapter->fwd_bitmask); 9039 accel->pool = pool; 9040 return 0; 9041 } 9042 9043 /* if we cannot find a free pool then disable the offload */ 9044 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9045 macvlan_release_l2fw_offload(vdev); 9046 9047 /* unbind the queues and drop the subordinate channel config */ 9048 netdev_unbind_sb_channel(adapter->netdev, vdev); 9049 netdev_set_sb_channel(vdev, 0); 9050 9051 kfree(accel); 9052 9053 return 0; 9054 } 9055 9056 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9057 { 9058 struct ixgbe_adapter *adapter = netdev_priv(dev); 9059 struct netdev_nested_priv priv = { 9060 .data = (void *)adapter, 9061 }; 9062 9063 /* flush any stale bits out of the fwd bitmask */ 9064 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9065 9066 /* walk through upper devices reassigning pools */ 9067 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9068 &priv); 9069 } 9070 9071 /** 9072 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9073 * 9074 * @dev: net device to configure 9075 * @tc: number of traffic classes to enable 9076 */ 9077 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9078 { 9079 struct ixgbe_adapter *adapter = netdev_priv(dev); 9080 struct ixgbe_hw *hw = &adapter->hw; 9081 9082 /* Hardware supports up to 8 traffic classes */ 9083 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9084 return -EINVAL; 9085 9086 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9087 return -EINVAL; 9088 9089 /* Hardware has to reinitialize queues and interrupts to 9090 * match packet buffer alignment. Unfortunately, the 9091 * hardware is not flexible enough to do this dynamically. 9092 */ 9093 if (netif_running(dev)) 9094 ixgbe_close(dev); 9095 else 9096 ixgbe_reset(adapter); 9097 9098 ixgbe_clear_interrupt_scheme(adapter); 9099 9100 #ifdef CONFIG_IXGBE_DCB 9101 if (tc) { 9102 if (adapter->xdp_prog) { 9103 e_warn(probe, "DCB is not supported with XDP\n"); 9104 9105 ixgbe_init_interrupt_scheme(adapter); 9106 if (netif_running(dev)) 9107 ixgbe_open(dev); 9108 return -EINVAL; 9109 } 9110 9111 netdev_set_num_tc(dev, tc); 9112 ixgbe_set_prio_tc_map(adapter); 9113 9114 adapter->hw_tcs = tc; 9115 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9116 9117 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9118 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9119 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9120 } 9121 } else { 9122 netdev_reset_tc(dev); 9123 9124 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9125 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9126 9127 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9128 adapter->hw_tcs = tc; 9129 9130 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9131 adapter->dcb_cfg.pfc_mode_enable = false; 9132 } 9133 9134 ixgbe_validate_rtr(adapter, tc); 9135 9136 #endif /* CONFIG_IXGBE_DCB */ 9137 ixgbe_init_interrupt_scheme(adapter); 9138 9139 ixgbe_defrag_macvlan_pools(dev); 9140 9141 if (netif_running(dev)) 9142 return ixgbe_open(dev); 9143 9144 return 0; 9145 } 9146 9147 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9148 struct tc_cls_u32_offload *cls) 9149 { 9150 u32 hdl = cls->knode.handle; 9151 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9152 u32 loc = cls->knode.handle & 0xfffff; 9153 int err = 0, i, j; 9154 struct ixgbe_jump_table *jump = NULL; 9155 9156 if (loc > IXGBE_MAX_HW_ENTRIES) 9157 return -EINVAL; 9158 9159 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9160 return -EINVAL; 9161 9162 /* Clear this filter in the link data it is associated with */ 9163 if (uhtid != 0x800) { 9164 jump = adapter->jump_tables[uhtid]; 9165 if (!jump) 9166 return -EINVAL; 9167 if (!test_bit(loc - 1, jump->child_loc_map)) 9168 return -EINVAL; 9169 clear_bit(loc - 1, jump->child_loc_map); 9170 } 9171 9172 /* Check if the filter being deleted is a link */ 9173 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9174 jump = adapter->jump_tables[i]; 9175 if (jump && jump->link_hdl == hdl) { 9176 /* Delete filters in the hardware in the child hash 9177 * table associated with this link 9178 */ 9179 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9180 if (!test_bit(j, jump->child_loc_map)) 9181 continue; 9182 spin_lock(&adapter->fdir_perfect_lock); 9183 err = ixgbe_update_ethtool_fdir_entry(adapter, 9184 NULL, 9185 j + 1); 9186 spin_unlock(&adapter->fdir_perfect_lock); 9187 clear_bit(j, jump->child_loc_map); 9188 } 9189 /* Remove resources for this link */ 9190 kfree(jump->input); 9191 kfree(jump->mask); 9192 kfree(jump); 9193 adapter->jump_tables[i] = NULL; 9194 return err; 9195 } 9196 } 9197 9198 spin_lock(&adapter->fdir_perfect_lock); 9199 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9200 spin_unlock(&adapter->fdir_perfect_lock); 9201 return err; 9202 } 9203 9204 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9205 struct tc_cls_u32_offload *cls) 9206 { 9207 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9208 9209 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9210 return -EINVAL; 9211 9212 /* This ixgbe devices do not support hash tables at the moment 9213 * so abort when given hash tables. 9214 */ 9215 if (cls->hnode.divisor > 0) 9216 return -EINVAL; 9217 9218 set_bit(uhtid - 1, &adapter->tables); 9219 return 0; 9220 } 9221 9222 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9223 struct tc_cls_u32_offload *cls) 9224 { 9225 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9226 9227 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9228 return -EINVAL; 9229 9230 clear_bit(uhtid - 1, &adapter->tables); 9231 return 0; 9232 } 9233 9234 #ifdef CONFIG_NET_CLS_ACT 9235 struct upper_walk_data { 9236 struct ixgbe_adapter *adapter; 9237 u64 action; 9238 int ifindex; 9239 u8 queue; 9240 }; 9241 9242 static int get_macvlan_queue(struct net_device *upper, 9243 struct netdev_nested_priv *priv) 9244 { 9245 if (netif_is_macvlan(upper)) { 9246 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9247 struct ixgbe_adapter *adapter; 9248 struct upper_walk_data *data; 9249 int ifindex; 9250 9251 data = (struct upper_walk_data *)priv->data; 9252 ifindex = data->ifindex; 9253 adapter = data->adapter; 9254 if (vadapter && upper->ifindex == ifindex) { 9255 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9256 data->action = data->queue; 9257 return 1; 9258 } 9259 } 9260 9261 return 0; 9262 } 9263 9264 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9265 u8 *queue, u64 *action) 9266 { 9267 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9268 unsigned int num_vfs = adapter->num_vfs, vf; 9269 struct netdev_nested_priv priv; 9270 struct upper_walk_data data; 9271 struct net_device *upper; 9272 9273 /* redirect to a SRIOV VF */ 9274 for (vf = 0; vf < num_vfs; ++vf) { 9275 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9276 if (upper->ifindex == ifindex) { 9277 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9278 *action = vf + 1; 9279 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9280 return 0; 9281 } 9282 } 9283 9284 /* redirect to a offloaded macvlan netdev */ 9285 data.adapter = adapter; 9286 data.ifindex = ifindex; 9287 data.action = 0; 9288 data.queue = 0; 9289 priv.data = (void *)&data; 9290 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9291 get_macvlan_queue, &priv)) { 9292 *action = data.action; 9293 *queue = data.queue; 9294 9295 return 0; 9296 } 9297 9298 return -EINVAL; 9299 } 9300 9301 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9302 struct tcf_exts *exts, u64 *action, u8 *queue) 9303 { 9304 const struct tc_action *a; 9305 int i; 9306 9307 if (!tcf_exts_has_actions(exts)) 9308 return -EINVAL; 9309 9310 tcf_exts_for_each_action(i, a, exts) { 9311 /* Drop action */ 9312 if (is_tcf_gact_shot(a)) { 9313 *action = IXGBE_FDIR_DROP_QUEUE; 9314 *queue = IXGBE_FDIR_DROP_QUEUE; 9315 return 0; 9316 } 9317 9318 /* Redirect to a VF or a offloaded macvlan */ 9319 if (is_tcf_mirred_egress_redirect(a)) { 9320 struct net_device *dev = tcf_mirred_dev(a); 9321 9322 if (!dev) 9323 return -EINVAL; 9324 return handle_redirect_action(adapter, dev->ifindex, 9325 queue, action); 9326 } 9327 9328 return -EINVAL; 9329 } 9330 9331 return -EINVAL; 9332 } 9333 #else 9334 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9335 struct tcf_exts *exts, u64 *action, u8 *queue) 9336 { 9337 return -EINVAL; 9338 } 9339 #endif /* CONFIG_NET_CLS_ACT */ 9340 9341 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9342 union ixgbe_atr_input *mask, 9343 struct tc_cls_u32_offload *cls, 9344 struct ixgbe_mat_field *field_ptr, 9345 struct ixgbe_nexthdr *nexthdr) 9346 { 9347 int i, j, off; 9348 __be32 val, m; 9349 bool found_entry = false, found_jump_field = false; 9350 9351 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9352 off = cls->knode.sel->keys[i].off; 9353 val = cls->knode.sel->keys[i].val; 9354 m = cls->knode.sel->keys[i].mask; 9355 9356 for (j = 0; field_ptr[j].val; j++) { 9357 if (field_ptr[j].off == off) { 9358 field_ptr[j].val(input, mask, (__force u32)val, 9359 (__force u32)m); 9360 input->filter.formatted.flow_type |= 9361 field_ptr[j].type; 9362 found_entry = true; 9363 break; 9364 } 9365 } 9366 if (nexthdr) { 9367 if (nexthdr->off == cls->knode.sel->keys[i].off && 9368 nexthdr->val == 9369 (__force u32)cls->knode.sel->keys[i].val && 9370 nexthdr->mask == 9371 (__force u32)cls->knode.sel->keys[i].mask) 9372 found_jump_field = true; 9373 else 9374 continue; 9375 } 9376 } 9377 9378 if (nexthdr && !found_jump_field) 9379 return -EINVAL; 9380 9381 if (!found_entry) 9382 return 0; 9383 9384 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9385 IXGBE_ATR_L4TYPE_MASK; 9386 9387 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9388 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9389 9390 return 0; 9391 } 9392 9393 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9394 struct tc_cls_u32_offload *cls) 9395 { 9396 __be16 protocol = cls->common.protocol; 9397 u32 loc = cls->knode.handle & 0xfffff; 9398 struct ixgbe_hw *hw = &adapter->hw; 9399 struct ixgbe_mat_field *field_ptr; 9400 struct ixgbe_fdir_filter *input = NULL; 9401 union ixgbe_atr_input *mask = NULL; 9402 struct ixgbe_jump_table *jump = NULL; 9403 int i, err = -EINVAL; 9404 u8 queue; 9405 u32 uhtid, link_uhtid; 9406 9407 uhtid = TC_U32_USERHTID(cls->knode.handle); 9408 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9409 9410 /* At the moment cls_u32 jumps to network layer and skips past 9411 * L2 headers. The canonical method to match L2 frames is to use 9412 * negative values. However this is error prone at best but really 9413 * just broken because there is no way to "know" what sort of hdr 9414 * is in front of the network layer. Fix cls_u32 to support L2 9415 * headers when needed. 9416 */ 9417 if (protocol != htons(ETH_P_IP)) 9418 return err; 9419 9420 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9421 e_err(drv, "Location out of range\n"); 9422 return err; 9423 } 9424 9425 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9426 * links and also the fields used to advance the parser across each 9427 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9428 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9429 * To add support for new nodes update ixgbe_model.h parse structures 9430 * this function _should_ be generic try not to hardcode values here. 9431 */ 9432 if (uhtid == 0x800) { 9433 field_ptr = (adapter->jump_tables[0])->mat; 9434 } else { 9435 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9436 return err; 9437 if (!adapter->jump_tables[uhtid]) 9438 return err; 9439 field_ptr = (adapter->jump_tables[uhtid])->mat; 9440 } 9441 9442 if (!field_ptr) 9443 return err; 9444 9445 /* At this point we know the field_ptr is valid and need to either 9446 * build cls_u32 link or attach filter. Because adding a link to 9447 * a handle that does not exist is invalid and the same for adding 9448 * rules to handles that don't exist. 9449 */ 9450 9451 if (link_uhtid) { 9452 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9453 9454 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9455 return err; 9456 9457 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9458 return err; 9459 9460 /* Multiple filters as links to the same hash table are not 9461 * supported. To add a new filter with the same next header 9462 * but different match/jump conditions, create a new hash table 9463 * and link to it. 9464 */ 9465 if (adapter->jump_tables[link_uhtid] && 9466 (adapter->jump_tables[link_uhtid])->link_hdl) { 9467 e_err(drv, "Link filter exists for link: %x\n", 9468 link_uhtid); 9469 return err; 9470 } 9471 9472 for (i = 0; nexthdr[i].jump; i++) { 9473 if (nexthdr[i].o != cls->knode.sel->offoff || 9474 nexthdr[i].s != cls->knode.sel->offshift || 9475 nexthdr[i].m != 9476 (__force u32)cls->knode.sel->offmask) 9477 return err; 9478 9479 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9480 if (!jump) 9481 return -ENOMEM; 9482 input = kzalloc(sizeof(*input), GFP_KERNEL); 9483 if (!input) { 9484 err = -ENOMEM; 9485 goto free_jump; 9486 } 9487 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9488 if (!mask) { 9489 err = -ENOMEM; 9490 goto free_input; 9491 } 9492 jump->input = input; 9493 jump->mask = mask; 9494 jump->link_hdl = cls->knode.handle; 9495 9496 err = ixgbe_clsu32_build_input(input, mask, cls, 9497 field_ptr, &nexthdr[i]); 9498 if (!err) { 9499 jump->mat = nexthdr[i].jump; 9500 adapter->jump_tables[link_uhtid] = jump; 9501 break; 9502 } else { 9503 kfree(mask); 9504 kfree(input); 9505 kfree(jump); 9506 } 9507 } 9508 return 0; 9509 } 9510 9511 input = kzalloc(sizeof(*input), GFP_KERNEL); 9512 if (!input) 9513 return -ENOMEM; 9514 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9515 if (!mask) { 9516 err = -ENOMEM; 9517 goto free_input; 9518 } 9519 9520 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9521 if ((adapter->jump_tables[uhtid])->input) 9522 memcpy(input, (adapter->jump_tables[uhtid])->input, 9523 sizeof(*input)); 9524 if ((adapter->jump_tables[uhtid])->mask) 9525 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9526 sizeof(*mask)); 9527 9528 /* Lookup in all child hash tables if this location is already 9529 * filled with a filter 9530 */ 9531 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9532 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9533 9534 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9535 e_err(drv, "Filter exists in location: %x\n", 9536 loc); 9537 err = -EINVAL; 9538 goto err_out; 9539 } 9540 } 9541 } 9542 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9543 if (err) 9544 goto err_out; 9545 9546 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9547 &queue); 9548 if (err < 0) 9549 goto err_out; 9550 9551 input->sw_idx = loc; 9552 9553 spin_lock(&adapter->fdir_perfect_lock); 9554 9555 if (hlist_empty(&adapter->fdir_filter_list)) { 9556 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9557 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9558 if (err) 9559 goto err_out_w_lock; 9560 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9561 err = -EINVAL; 9562 goto err_out_w_lock; 9563 } 9564 9565 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9566 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9567 input->sw_idx, queue); 9568 if (!err) 9569 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9570 spin_unlock(&adapter->fdir_perfect_lock); 9571 9572 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9573 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9574 9575 kfree(mask); 9576 return err; 9577 err_out_w_lock: 9578 spin_unlock(&adapter->fdir_perfect_lock); 9579 err_out: 9580 kfree(mask); 9581 free_input: 9582 kfree(input); 9583 free_jump: 9584 kfree(jump); 9585 return err; 9586 } 9587 9588 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9589 struct tc_cls_u32_offload *cls_u32) 9590 { 9591 switch (cls_u32->command) { 9592 case TC_CLSU32_NEW_KNODE: 9593 case TC_CLSU32_REPLACE_KNODE: 9594 return ixgbe_configure_clsu32(adapter, cls_u32); 9595 case TC_CLSU32_DELETE_KNODE: 9596 return ixgbe_delete_clsu32(adapter, cls_u32); 9597 case TC_CLSU32_NEW_HNODE: 9598 case TC_CLSU32_REPLACE_HNODE: 9599 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9600 case TC_CLSU32_DELETE_HNODE: 9601 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9602 default: 9603 return -EOPNOTSUPP; 9604 } 9605 } 9606 9607 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9608 void *cb_priv) 9609 { 9610 struct ixgbe_adapter *adapter = cb_priv; 9611 9612 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9613 return -EOPNOTSUPP; 9614 9615 switch (type) { 9616 case TC_SETUP_CLSU32: 9617 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9618 default: 9619 return -EOPNOTSUPP; 9620 } 9621 } 9622 9623 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9624 struct tc_mqprio_qopt *mqprio) 9625 { 9626 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9627 return ixgbe_setup_tc(dev, mqprio->num_tc); 9628 } 9629 9630 static LIST_HEAD(ixgbe_block_cb_list); 9631 9632 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9633 void *type_data) 9634 { 9635 struct ixgbe_adapter *adapter = netdev_priv(dev); 9636 9637 switch (type) { 9638 case TC_SETUP_BLOCK: 9639 return flow_block_cb_setup_simple(type_data, 9640 &ixgbe_block_cb_list, 9641 ixgbe_setup_tc_block_cb, 9642 adapter, adapter, true); 9643 case TC_SETUP_QDISC_MQPRIO: 9644 return ixgbe_setup_tc_mqprio(dev, type_data); 9645 default: 9646 return -EOPNOTSUPP; 9647 } 9648 } 9649 9650 #ifdef CONFIG_PCI_IOV 9651 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9652 { 9653 struct net_device *netdev = adapter->netdev; 9654 9655 rtnl_lock(); 9656 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9657 rtnl_unlock(); 9658 } 9659 9660 #endif 9661 void ixgbe_do_reset(struct net_device *netdev) 9662 { 9663 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9664 9665 if (netif_running(netdev)) 9666 ixgbe_reinit_locked(adapter); 9667 else 9668 ixgbe_reset(adapter); 9669 } 9670 9671 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9672 netdev_features_t features) 9673 { 9674 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9675 9676 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9677 if (!(features & NETIF_F_RXCSUM)) 9678 features &= ~NETIF_F_LRO; 9679 9680 /* Turn off LRO if not RSC capable */ 9681 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9682 features &= ~NETIF_F_LRO; 9683 9684 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9685 e_dev_err("LRO is not supported with XDP\n"); 9686 features &= ~NETIF_F_LRO; 9687 } 9688 9689 return features; 9690 } 9691 9692 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9693 { 9694 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9695 num_online_cpus()); 9696 9697 /* go back to full RSS if we're not running SR-IOV */ 9698 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9699 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9700 IXGBE_FLAG_SRIOV_ENABLED); 9701 9702 adapter->ring_feature[RING_F_RSS].limit = rss; 9703 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9704 9705 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9706 } 9707 9708 static int ixgbe_set_features(struct net_device *netdev, 9709 netdev_features_t features) 9710 { 9711 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9712 netdev_features_t changed = netdev->features ^ features; 9713 bool need_reset = false; 9714 9715 /* Make sure RSC matches LRO, reset if change */ 9716 if (!(features & NETIF_F_LRO)) { 9717 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9718 need_reset = true; 9719 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9720 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9721 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9722 if (adapter->rx_itr_setting == 1 || 9723 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9724 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9725 need_reset = true; 9726 } else if ((changed ^ features) & NETIF_F_LRO) { 9727 e_info(probe, "rx-usecs set too low, " 9728 "disabling RSC\n"); 9729 } 9730 } 9731 9732 /* 9733 * Check if Flow Director n-tuple support or hw_tc support was 9734 * enabled or disabled. If the state changed, we need to reset. 9735 */ 9736 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9737 /* turn off ATR, enable perfect filters and reset */ 9738 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9739 need_reset = true; 9740 9741 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9742 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9743 } else { 9744 /* turn off perfect filters, enable ATR and reset */ 9745 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9746 need_reset = true; 9747 9748 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9749 9750 /* We cannot enable ATR if SR-IOV is enabled */ 9751 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9752 /* We cannot enable ATR if we have 2 or more tcs */ 9753 (adapter->hw_tcs > 1) || 9754 /* We cannot enable ATR if RSS is disabled */ 9755 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9756 /* A sample rate of 0 indicates ATR disabled */ 9757 (!adapter->atr_sample_rate)) 9758 ; /* do nothing not supported */ 9759 else /* otherwise supported and set the flag */ 9760 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9761 } 9762 9763 if (changed & NETIF_F_RXALL) 9764 need_reset = true; 9765 9766 netdev->features = features; 9767 9768 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9769 ixgbe_reset_l2fw_offload(adapter); 9770 else if (need_reset) 9771 ixgbe_do_reset(netdev); 9772 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9773 NETIF_F_HW_VLAN_CTAG_FILTER)) 9774 ixgbe_set_rx_mode(netdev); 9775 9776 return 1; 9777 } 9778 9779 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9780 struct net_device *dev, 9781 const unsigned char *addr, u16 vid, 9782 u16 flags, 9783 struct netlink_ext_ack *extack) 9784 { 9785 /* guarantee we can provide a unique filter for the unicast address */ 9786 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9787 struct ixgbe_adapter *adapter = netdev_priv(dev); 9788 u16 pool = VMDQ_P(0); 9789 9790 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9791 return -ENOMEM; 9792 } 9793 9794 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9795 } 9796 9797 /** 9798 * ixgbe_configure_bridge_mode - set various bridge modes 9799 * @adapter: the private structure 9800 * @mode: requested bridge mode 9801 * 9802 * Configure some settings require for various bridge modes. 9803 **/ 9804 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9805 __u16 mode) 9806 { 9807 struct ixgbe_hw *hw = &adapter->hw; 9808 unsigned int p, num_pools; 9809 u32 vmdctl; 9810 9811 switch (mode) { 9812 case BRIDGE_MODE_VEPA: 9813 /* disable Tx loopback, rely on switch hairpin mode */ 9814 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9815 9816 /* must enable Rx switching replication to allow multicast 9817 * packet reception on all VFs, and to enable source address 9818 * pruning. 9819 */ 9820 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9821 vmdctl |= IXGBE_VT_CTL_REPLEN; 9822 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9823 9824 /* enable Rx source address pruning. Note, this requires 9825 * replication to be enabled or else it does nothing. 9826 */ 9827 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9828 for (p = 0; p < num_pools; p++) { 9829 if (hw->mac.ops.set_source_address_pruning) 9830 hw->mac.ops.set_source_address_pruning(hw, 9831 true, 9832 p); 9833 } 9834 break; 9835 case BRIDGE_MODE_VEB: 9836 /* enable Tx loopback for internal VF/PF communication */ 9837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9838 IXGBE_PFDTXGSWC_VT_LBEN); 9839 9840 /* disable Rx switching replication unless we have SR-IOV 9841 * virtual functions 9842 */ 9843 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9844 if (!adapter->num_vfs) 9845 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9846 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9847 9848 /* disable Rx source address pruning, since we don't expect to 9849 * be receiving external loopback of our transmitted frames. 9850 */ 9851 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9852 for (p = 0; p < num_pools; p++) { 9853 if (hw->mac.ops.set_source_address_pruning) 9854 hw->mac.ops.set_source_address_pruning(hw, 9855 false, 9856 p); 9857 } 9858 break; 9859 default: 9860 return -EINVAL; 9861 } 9862 9863 adapter->bridge_mode = mode; 9864 9865 e_info(drv, "enabling bridge mode: %s\n", 9866 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9867 9868 return 0; 9869 } 9870 9871 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9872 struct nlmsghdr *nlh, u16 flags, 9873 struct netlink_ext_ack *extack) 9874 { 9875 struct ixgbe_adapter *adapter = netdev_priv(dev); 9876 struct nlattr *attr, *br_spec; 9877 int rem; 9878 9879 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9880 return -EOPNOTSUPP; 9881 9882 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9883 if (!br_spec) 9884 return -EINVAL; 9885 9886 nla_for_each_nested(attr, br_spec, rem) { 9887 int status; 9888 __u16 mode; 9889 9890 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9891 continue; 9892 9893 if (nla_len(attr) < sizeof(mode)) 9894 return -EINVAL; 9895 9896 mode = nla_get_u16(attr); 9897 status = ixgbe_configure_bridge_mode(adapter, mode); 9898 if (status) 9899 return status; 9900 9901 break; 9902 } 9903 9904 return 0; 9905 } 9906 9907 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9908 struct net_device *dev, 9909 u32 filter_mask, int nlflags) 9910 { 9911 struct ixgbe_adapter *adapter = netdev_priv(dev); 9912 9913 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9914 return 0; 9915 9916 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9917 adapter->bridge_mode, 0, 0, nlflags, 9918 filter_mask, NULL); 9919 } 9920 9921 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9922 { 9923 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9924 struct ixgbe_fwd_adapter *accel; 9925 int tcs = adapter->hw_tcs ? : 1; 9926 int pool, err; 9927 9928 if (adapter->xdp_prog) { 9929 e_warn(probe, "L2FW offload is not supported with XDP\n"); 9930 return ERR_PTR(-EINVAL); 9931 } 9932 9933 /* The hardware supported by ixgbe only filters on the destination MAC 9934 * address. In order to avoid issues we only support offloading modes 9935 * where the hardware can actually provide the functionality. 9936 */ 9937 if (!macvlan_supports_dest_filter(vdev)) 9938 return ERR_PTR(-EMEDIUMTYPE); 9939 9940 /* We need to lock down the macvlan to be a single queue device so that 9941 * we can reuse the tc_to_txq field in the macvlan netdev to represent 9942 * the queue mapping to our netdev. 9943 */ 9944 if (netif_is_multiqueue(vdev)) 9945 return ERR_PTR(-ERANGE); 9946 9947 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9948 if (pool == adapter->num_rx_pools) { 9949 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 9950 u16 reserved_pools; 9951 9952 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9953 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 9954 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 9955 return ERR_PTR(-EBUSY); 9956 9957 /* Hardware has a limited number of available pools. Each VF, 9958 * and the PF require a pool. Check to ensure we don't 9959 * attempt to use more then the available number of pools. 9960 */ 9961 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9962 return ERR_PTR(-EBUSY); 9963 9964 /* Enable VMDq flag so device will be set in VM mode */ 9965 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 9966 IXGBE_FLAG_SRIOV_ENABLED; 9967 9968 /* Try to reserve as many queues per pool as possible, 9969 * we start with the configurations that support 4 queues 9970 * per pools, followed by 2, and then by just 1 per pool. 9971 */ 9972 if (used_pools < 32 && adapter->num_rx_pools < 16) 9973 reserved_pools = min_t(u16, 9974 32 - used_pools, 9975 16 - adapter->num_rx_pools); 9976 else if (adapter->num_rx_pools < 32) 9977 reserved_pools = min_t(u16, 9978 64 - used_pools, 9979 32 - adapter->num_rx_pools); 9980 else 9981 reserved_pools = 64 - used_pools; 9982 9983 9984 if (!reserved_pools) 9985 return ERR_PTR(-EBUSY); 9986 9987 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 9988 9989 /* Force reinit of ring allocation with VMDQ enabled */ 9990 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 9991 if (err) 9992 return ERR_PTR(err); 9993 9994 if (pool >= adapter->num_rx_pools) 9995 return ERR_PTR(-ENOMEM); 9996 } 9997 9998 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 9999 if (!accel) 10000 return ERR_PTR(-ENOMEM); 10001 10002 set_bit(pool, adapter->fwd_bitmask); 10003 netdev_set_sb_channel(vdev, pool); 10004 accel->pool = pool; 10005 accel->netdev = vdev; 10006 10007 if (!netif_running(pdev)) 10008 return accel; 10009 10010 err = ixgbe_fwd_ring_up(adapter, accel); 10011 if (err) 10012 return ERR_PTR(err); 10013 10014 return accel; 10015 } 10016 10017 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10018 { 10019 struct ixgbe_fwd_adapter *accel = priv; 10020 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10021 unsigned int rxbase = accel->rx_base_queue; 10022 unsigned int i; 10023 10024 /* delete unicast filter associated with offloaded interface */ 10025 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10026 VMDQ_P(accel->pool)); 10027 10028 /* Allow remaining Rx packets to get flushed out of the 10029 * Rx FIFO before we drop the netdev for the ring. 10030 */ 10031 usleep_range(10000, 20000); 10032 10033 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10034 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10035 struct ixgbe_q_vector *qv = ring->q_vector; 10036 10037 /* Make sure we aren't processing any packets and clear 10038 * netdev to shut down the ring. 10039 */ 10040 if (netif_running(adapter->netdev)) 10041 napi_synchronize(&qv->napi); 10042 ring->netdev = NULL; 10043 } 10044 10045 /* unbind the queues and drop the subordinate channel config */ 10046 netdev_unbind_sb_channel(pdev, accel->netdev); 10047 netdev_set_sb_channel(accel->netdev, 0); 10048 10049 clear_bit(accel->pool, adapter->fwd_bitmask); 10050 kfree(accel); 10051 } 10052 10053 #define IXGBE_MAX_MAC_HDR_LEN 127 10054 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10055 10056 static netdev_features_t 10057 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10058 netdev_features_t features) 10059 { 10060 unsigned int network_hdr_len, mac_hdr_len; 10061 10062 /* Make certain the headers can be described by a context descriptor */ 10063 mac_hdr_len = skb_network_header(skb) - skb->data; 10064 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10065 return features & ~(NETIF_F_HW_CSUM | 10066 NETIF_F_SCTP_CRC | 10067 NETIF_F_GSO_UDP_L4 | 10068 NETIF_F_HW_VLAN_CTAG_TX | 10069 NETIF_F_TSO | 10070 NETIF_F_TSO6); 10071 10072 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10073 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10074 return features & ~(NETIF_F_HW_CSUM | 10075 NETIF_F_SCTP_CRC | 10076 NETIF_F_GSO_UDP_L4 | 10077 NETIF_F_TSO | 10078 NETIF_F_TSO6); 10079 10080 /* We can only support IPV4 TSO in tunnels if we can mangle the 10081 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10082 * IPsec offoad sets skb->encapsulation but still can handle 10083 * the TSO, so it's the exception. 10084 */ 10085 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10086 #ifdef CONFIG_IXGBE_IPSEC 10087 if (!secpath_exists(skb)) 10088 #endif 10089 features &= ~NETIF_F_TSO; 10090 } 10091 10092 return features; 10093 } 10094 10095 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10096 { 10097 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10098 struct ixgbe_adapter *adapter = netdev_priv(dev); 10099 struct bpf_prog *old_prog; 10100 bool need_reset; 10101 10102 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10103 return -EINVAL; 10104 10105 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10106 return -EINVAL; 10107 10108 /* verify ixgbe ring attributes are sufficient for XDP */ 10109 for (i = 0; i < adapter->num_rx_queues; i++) { 10110 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10111 10112 if (ring_is_rsc_enabled(ring)) 10113 return -EINVAL; 10114 10115 if (frame_size > ixgbe_rx_bufsz(ring)) 10116 return -EINVAL; 10117 } 10118 10119 if (nr_cpu_ids > MAX_XDP_QUEUES) 10120 return -ENOMEM; 10121 10122 old_prog = xchg(&adapter->xdp_prog, prog); 10123 need_reset = (!!prog != !!old_prog); 10124 10125 /* If transitioning XDP modes reconfigure rings */ 10126 if (need_reset) { 10127 int err; 10128 10129 if (!prog) 10130 /* Wait until ndo_xsk_wakeup completes. */ 10131 synchronize_rcu(); 10132 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10133 10134 if (err) { 10135 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10136 return -EINVAL; 10137 } 10138 } else { 10139 for (i = 0; i < adapter->num_rx_queues; i++) 10140 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 10141 adapter->xdp_prog); 10142 } 10143 10144 if (old_prog) 10145 bpf_prog_put(old_prog); 10146 10147 /* Kick start the NAPI context if there is an AF_XDP socket open 10148 * on that queue id. This so that receiving will start. 10149 */ 10150 if (need_reset && prog) 10151 for (i = 0; i < adapter->num_rx_queues; i++) 10152 if (adapter->xdp_ring[i]->xsk_pool) 10153 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10154 XDP_WAKEUP_RX); 10155 10156 return 0; 10157 } 10158 10159 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10160 { 10161 struct ixgbe_adapter *adapter = netdev_priv(dev); 10162 10163 switch (xdp->command) { 10164 case XDP_SETUP_PROG: 10165 return ixgbe_xdp_setup(dev, xdp->prog); 10166 case XDP_SETUP_XSK_POOL: 10167 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10168 xdp->xsk.queue_id); 10169 10170 default: 10171 return -EINVAL; 10172 } 10173 } 10174 10175 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10176 { 10177 /* Force memory writes to complete before letting h/w know there 10178 * are new descriptors to fetch. 10179 */ 10180 wmb(); 10181 writel(ring->next_to_use, ring->tail); 10182 } 10183 10184 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10185 struct xdp_frame **frames, u32 flags) 10186 { 10187 struct ixgbe_adapter *adapter = netdev_priv(dev); 10188 struct ixgbe_ring *ring; 10189 int drops = 0; 10190 int i; 10191 10192 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10193 return -ENETDOWN; 10194 10195 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10196 return -EINVAL; 10197 10198 /* During program transitions its possible adapter->xdp_prog is assigned 10199 * but ring has not been configured yet. In this case simply abort xmit. 10200 */ 10201 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10202 if (unlikely(!ring)) 10203 return -ENXIO; 10204 10205 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10206 return -ENXIO; 10207 10208 for (i = 0; i < n; i++) { 10209 struct xdp_frame *xdpf = frames[i]; 10210 int err; 10211 10212 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10213 if (err != IXGBE_XDP_TX) { 10214 xdp_return_frame_rx_napi(xdpf); 10215 drops++; 10216 } 10217 } 10218 10219 if (unlikely(flags & XDP_XMIT_FLUSH)) 10220 ixgbe_xdp_ring_update_tail(ring); 10221 10222 return n - drops; 10223 } 10224 10225 static const struct net_device_ops ixgbe_netdev_ops = { 10226 .ndo_open = ixgbe_open, 10227 .ndo_stop = ixgbe_close, 10228 .ndo_start_xmit = ixgbe_xmit_frame, 10229 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10230 .ndo_validate_addr = eth_validate_addr, 10231 .ndo_set_mac_address = ixgbe_set_mac, 10232 .ndo_change_mtu = ixgbe_change_mtu, 10233 .ndo_tx_timeout = ixgbe_tx_timeout, 10234 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10235 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10236 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10237 .ndo_do_ioctl = ixgbe_ioctl, 10238 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10239 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10240 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10241 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10242 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10243 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10244 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10245 .ndo_get_stats64 = ixgbe_get_stats64, 10246 .ndo_setup_tc = __ixgbe_setup_tc, 10247 #ifdef IXGBE_FCOE 10248 .ndo_select_queue = ixgbe_select_queue, 10249 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10250 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10251 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10252 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10253 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10254 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10255 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10256 #endif /* IXGBE_FCOE */ 10257 .ndo_set_features = ixgbe_set_features, 10258 .ndo_fix_features = ixgbe_fix_features, 10259 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10260 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10261 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10262 .ndo_dfwd_add_station = ixgbe_fwd_add, 10263 .ndo_dfwd_del_station = ixgbe_fwd_del, 10264 .ndo_features_check = ixgbe_features_check, 10265 .ndo_bpf = ixgbe_xdp, 10266 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10267 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10268 }; 10269 10270 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10271 struct ixgbe_ring *tx_ring) 10272 { 10273 unsigned long wait_delay, delay_interval; 10274 struct ixgbe_hw *hw = &adapter->hw; 10275 u8 reg_idx = tx_ring->reg_idx; 10276 int wait_loop; 10277 u32 txdctl; 10278 10279 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10280 10281 /* delay mechanism from ixgbe_disable_tx */ 10282 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10283 10284 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10285 wait_delay = delay_interval; 10286 10287 while (wait_loop--) { 10288 usleep_range(wait_delay, wait_delay + 10); 10289 wait_delay += delay_interval * 2; 10290 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10291 10292 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10293 return; 10294 } 10295 10296 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10297 } 10298 10299 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10300 struct ixgbe_ring *tx_ring) 10301 { 10302 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10303 ixgbe_disable_txr_hw(adapter, tx_ring); 10304 } 10305 10306 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10307 struct ixgbe_ring *rx_ring) 10308 { 10309 unsigned long wait_delay, delay_interval; 10310 struct ixgbe_hw *hw = &adapter->hw; 10311 u8 reg_idx = rx_ring->reg_idx; 10312 int wait_loop; 10313 u32 rxdctl; 10314 10315 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10316 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10317 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10318 10319 /* write value back with RXDCTL.ENABLE bit cleared */ 10320 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10321 10322 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10323 if (hw->mac.type == ixgbe_mac_82598EB && 10324 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10325 return; 10326 10327 /* delay mechanism from ixgbe_disable_rx */ 10328 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10329 10330 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10331 wait_delay = delay_interval; 10332 10333 while (wait_loop--) { 10334 usleep_range(wait_delay, wait_delay + 10); 10335 wait_delay += delay_interval * 2; 10336 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10337 10338 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10339 return; 10340 } 10341 10342 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10343 } 10344 10345 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10346 { 10347 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10348 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10349 } 10350 10351 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10352 { 10353 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10354 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10355 } 10356 10357 /** 10358 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10359 * @adapter: adapter structure 10360 * @ring: ring index 10361 * 10362 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10363 * assumes that the netdev is running. 10364 **/ 10365 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10366 { 10367 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10368 10369 rx_ring = adapter->rx_ring[ring]; 10370 tx_ring = adapter->tx_ring[ring]; 10371 xdp_ring = adapter->xdp_ring[ring]; 10372 10373 ixgbe_disable_txr(adapter, tx_ring); 10374 if (xdp_ring) 10375 ixgbe_disable_txr(adapter, xdp_ring); 10376 ixgbe_disable_rxr_hw(adapter, rx_ring); 10377 10378 if (xdp_ring) 10379 synchronize_rcu(); 10380 10381 /* Rx/Tx/XDP Tx share the same napi context. */ 10382 napi_disable(&rx_ring->q_vector->napi); 10383 10384 ixgbe_clean_tx_ring(tx_ring); 10385 if (xdp_ring) 10386 ixgbe_clean_tx_ring(xdp_ring); 10387 ixgbe_clean_rx_ring(rx_ring); 10388 10389 ixgbe_reset_txr_stats(tx_ring); 10390 if (xdp_ring) 10391 ixgbe_reset_txr_stats(xdp_ring); 10392 ixgbe_reset_rxr_stats(rx_ring); 10393 } 10394 10395 /** 10396 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10397 * @adapter: adapter structure 10398 * @ring: ring index 10399 * 10400 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10401 * assumes that the netdev is running. 10402 **/ 10403 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10404 { 10405 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10406 10407 rx_ring = adapter->rx_ring[ring]; 10408 tx_ring = adapter->tx_ring[ring]; 10409 xdp_ring = adapter->xdp_ring[ring]; 10410 10411 /* Rx/Tx/XDP Tx share the same napi context. */ 10412 napi_enable(&rx_ring->q_vector->napi); 10413 10414 ixgbe_configure_tx_ring(adapter, tx_ring); 10415 if (xdp_ring) 10416 ixgbe_configure_tx_ring(adapter, xdp_ring); 10417 ixgbe_configure_rx_ring(adapter, rx_ring); 10418 10419 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10420 if (xdp_ring) 10421 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10422 } 10423 10424 /** 10425 * ixgbe_enumerate_functions - Get the number of ports this device has 10426 * @adapter: adapter structure 10427 * 10428 * This function enumerates the phsyical functions co-located on a single slot, 10429 * in order to determine how many ports a device has. This is most useful in 10430 * determining the required GT/s of PCIe bandwidth necessary for optimal 10431 * performance. 10432 **/ 10433 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10434 { 10435 struct pci_dev *entry, *pdev = adapter->pdev; 10436 int physfns = 0; 10437 10438 /* Some cards can not use the generic count PCIe functions method, 10439 * because they are behind a parent switch, so we hardcode these with 10440 * the correct number of functions. 10441 */ 10442 if (ixgbe_pcie_from_parent(&adapter->hw)) 10443 physfns = 4; 10444 10445 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10446 /* don't count virtual functions */ 10447 if (entry->is_virtfn) 10448 continue; 10449 10450 /* When the devices on the bus don't all match our device ID, 10451 * we can't reliably determine the correct number of 10452 * functions. This can occur if a function has been direct 10453 * attached to a virtual machine using VT-d, for example. In 10454 * this case, simply return -1 to indicate this. 10455 */ 10456 if ((entry->vendor != pdev->vendor) || 10457 (entry->device != pdev->device)) 10458 return -1; 10459 10460 physfns++; 10461 } 10462 10463 return physfns; 10464 } 10465 10466 /** 10467 * ixgbe_wol_supported - Check whether device supports WoL 10468 * @adapter: the adapter private structure 10469 * @device_id: the device ID 10470 * @subdevice_id: the subsystem device ID 10471 * 10472 * This function is used by probe and ethtool to determine 10473 * which devices have WoL support 10474 * 10475 **/ 10476 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10477 u16 subdevice_id) 10478 { 10479 struct ixgbe_hw *hw = &adapter->hw; 10480 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10481 10482 /* WOL not supported on 82598 */ 10483 if (hw->mac.type == ixgbe_mac_82598EB) 10484 return false; 10485 10486 /* check eeprom to see if WOL is enabled for X540 and newer */ 10487 if (hw->mac.type >= ixgbe_mac_X540) { 10488 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10489 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10490 (hw->bus.func == 0))) 10491 return true; 10492 } 10493 10494 /* WOL is determined based on device IDs for 82599 MACs */ 10495 switch (device_id) { 10496 case IXGBE_DEV_ID_82599_SFP: 10497 /* Only these subdevices could supports WOL */ 10498 switch (subdevice_id) { 10499 case IXGBE_SUBDEV_ID_82599_560FLR: 10500 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10501 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10502 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10503 /* only support first port */ 10504 if (hw->bus.func != 0) 10505 break; 10506 fallthrough; 10507 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10508 case IXGBE_SUBDEV_ID_82599_SFP: 10509 case IXGBE_SUBDEV_ID_82599_RNDC: 10510 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10511 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10512 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10513 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10514 return true; 10515 } 10516 break; 10517 case IXGBE_DEV_ID_82599EN_SFP: 10518 /* Only these subdevices support WOL */ 10519 switch (subdevice_id) { 10520 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10521 return true; 10522 } 10523 break; 10524 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10525 /* All except this subdevice support WOL */ 10526 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10527 return true; 10528 break; 10529 case IXGBE_DEV_ID_82599_KX4: 10530 return true; 10531 default: 10532 break; 10533 } 10534 10535 return false; 10536 } 10537 10538 /** 10539 * ixgbe_set_fw_version - Set FW version 10540 * @adapter: the adapter private structure 10541 * 10542 * This function is used by probe and ethtool to determine the FW version to 10543 * format to display. The FW version is taken from the EEPROM/NVM. 10544 */ 10545 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10546 { 10547 struct ixgbe_hw *hw = &adapter->hw; 10548 struct ixgbe_nvm_version nvm_ver; 10549 10550 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10551 if (nvm_ver.oem_valid) { 10552 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10553 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10554 nvm_ver.oem_release); 10555 return; 10556 } 10557 10558 ixgbe_get_etk_id(hw, &nvm_ver); 10559 ixgbe_get_orom_version(hw, &nvm_ver); 10560 10561 if (nvm_ver.or_valid) { 10562 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10563 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10564 nvm_ver.or_build, nvm_ver.or_patch); 10565 return; 10566 } 10567 10568 /* Set ETrack ID format */ 10569 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10570 "0x%08x", nvm_ver.etk_id); 10571 } 10572 10573 /** 10574 * ixgbe_probe - Device Initialization Routine 10575 * @pdev: PCI device information struct 10576 * @ent: entry in ixgbe_pci_tbl 10577 * 10578 * Returns 0 on success, negative on failure 10579 * 10580 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10581 * The OS initialization, configuring of the adapter private structure, 10582 * and a hardware reset occur. 10583 **/ 10584 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10585 { 10586 struct net_device *netdev; 10587 struct ixgbe_adapter *adapter = NULL; 10588 struct ixgbe_hw *hw; 10589 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10590 int i, err, pci_using_dac, expected_gts; 10591 unsigned int indices = MAX_TX_QUEUES; 10592 u8 part_str[IXGBE_PBANUM_LENGTH]; 10593 bool disable_dev = false; 10594 #ifdef IXGBE_FCOE 10595 u16 device_caps; 10596 #endif 10597 u32 eec; 10598 10599 /* Catch broken hardware that put the wrong VF device ID in 10600 * the PCIe SR-IOV capability. 10601 */ 10602 if (pdev->is_virtfn) { 10603 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10604 pci_name(pdev), pdev->vendor, pdev->device); 10605 return -EINVAL; 10606 } 10607 10608 err = pci_enable_device_mem(pdev); 10609 if (err) 10610 return err; 10611 10612 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10613 pci_using_dac = 1; 10614 } else { 10615 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10616 if (err) { 10617 dev_err(&pdev->dev, 10618 "No usable DMA configuration, aborting\n"); 10619 goto err_dma; 10620 } 10621 pci_using_dac = 0; 10622 } 10623 10624 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10625 if (err) { 10626 dev_err(&pdev->dev, 10627 "pci_request_selected_regions failed 0x%x\n", err); 10628 goto err_pci_reg; 10629 } 10630 10631 pci_enable_pcie_error_reporting(pdev); 10632 10633 pci_set_master(pdev); 10634 pci_save_state(pdev); 10635 10636 if (ii->mac == ixgbe_mac_82598EB) { 10637 #ifdef CONFIG_IXGBE_DCB 10638 /* 8 TC w/ 4 queues per TC */ 10639 indices = 4 * MAX_TRAFFIC_CLASS; 10640 #else 10641 indices = IXGBE_MAX_RSS_INDICES; 10642 #endif 10643 } 10644 10645 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10646 if (!netdev) { 10647 err = -ENOMEM; 10648 goto err_alloc_etherdev; 10649 } 10650 10651 SET_NETDEV_DEV(netdev, &pdev->dev); 10652 10653 adapter = netdev_priv(netdev); 10654 10655 adapter->netdev = netdev; 10656 adapter->pdev = pdev; 10657 hw = &adapter->hw; 10658 hw->back = adapter; 10659 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10660 10661 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10662 pci_resource_len(pdev, 0)); 10663 adapter->io_addr = hw->hw_addr; 10664 if (!hw->hw_addr) { 10665 err = -EIO; 10666 goto err_ioremap; 10667 } 10668 10669 netdev->netdev_ops = &ixgbe_netdev_ops; 10670 ixgbe_set_ethtool_ops(netdev); 10671 netdev->watchdog_timeo = 5 * HZ; 10672 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10673 10674 /* Setup hw api */ 10675 hw->mac.ops = *ii->mac_ops; 10676 hw->mac.type = ii->mac; 10677 hw->mvals = ii->mvals; 10678 if (ii->link_ops) 10679 hw->link.ops = *ii->link_ops; 10680 10681 /* EEPROM */ 10682 hw->eeprom.ops = *ii->eeprom_ops; 10683 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10684 if (ixgbe_removed(hw->hw_addr)) { 10685 err = -EIO; 10686 goto err_ioremap; 10687 } 10688 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10689 if (!(eec & BIT(8))) 10690 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10691 10692 /* PHY */ 10693 hw->phy.ops = *ii->phy_ops; 10694 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10695 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10696 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10697 hw->phy.mdio.mmds = 0; 10698 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10699 hw->phy.mdio.dev = netdev; 10700 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10701 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10702 10703 /* setup the private structure */ 10704 err = ixgbe_sw_init(adapter, ii); 10705 if (err) 10706 goto err_sw_init; 10707 10708 switch (adapter->hw.mac.type) { 10709 case ixgbe_mac_X550: 10710 case ixgbe_mac_X550EM_x: 10711 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 10712 break; 10713 case ixgbe_mac_x550em_a: 10714 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 10715 break; 10716 default: 10717 break; 10718 } 10719 10720 /* Make sure the SWFW semaphore is in a valid state */ 10721 if (hw->mac.ops.init_swfw_sync) 10722 hw->mac.ops.init_swfw_sync(hw); 10723 10724 /* Make it possible the adapter to be woken up via WOL */ 10725 switch (adapter->hw.mac.type) { 10726 case ixgbe_mac_82599EB: 10727 case ixgbe_mac_X540: 10728 case ixgbe_mac_X550: 10729 case ixgbe_mac_X550EM_x: 10730 case ixgbe_mac_x550em_a: 10731 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10732 break; 10733 default: 10734 break; 10735 } 10736 10737 /* 10738 * If there is a fan on this device and it has failed log the 10739 * failure. 10740 */ 10741 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10742 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10743 if (esdp & IXGBE_ESDP_SDP1) 10744 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10745 } 10746 10747 if (allow_unsupported_sfp) 10748 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10749 10750 /* reset_hw fills in the perm_addr as well */ 10751 hw->phy.reset_if_overtemp = true; 10752 err = hw->mac.ops.reset_hw(hw); 10753 hw->phy.reset_if_overtemp = false; 10754 ixgbe_set_eee_capable(adapter); 10755 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10756 err = 0; 10757 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10758 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10759 e_dev_err("Reload the driver after installing a supported module.\n"); 10760 goto err_sw_init; 10761 } else if (err) { 10762 e_dev_err("HW Init failed: %d\n", err); 10763 goto err_sw_init; 10764 } 10765 10766 #ifdef CONFIG_PCI_IOV 10767 /* SR-IOV not supported on the 82598 */ 10768 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10769 goto skip_sriov; 10770 /* Mailbox */ 10771 ixgbe_init_mbx_params_pf(hw); 10772 hw->mbx.ops = ii->mbx_ops; 10773 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10774 ixgbe_enable_sriov(adapter, max_vfs); 10775 skip_sriov: 10776 10777 #endif 10778 netdev->features = NETIF_F_SG | 10779 NETIF_F_TSO | 10780 NETIF_F_TSO6 | 10781 NETIF_F_RXHASH | 10782 NETIF_F_RXCSUM | 10783 NETIF_F_HW_CSUM; 10784 10785 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10786 NETIF_F_GSO_GRE_CSUM | \ 10787 NETIF_F_GSO_IPXIP4 | \ 10788 NETIF_F_GSO_IPXIP6 | \ 10789 NETIF_F_GSO_UDP_TUNNEL | \ 10790 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10791 10792 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10793 netdev->features |= NETIF_F_GSO_PARTIAL | 10794 IXGBE_GSO_PARTIAL_FEATURES; 10795 10796 if (hw->mac.type >= ixgbe_mac_82599EB) 10797 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 10798 10799 #ifdef CONFIG_IXGBE_IPSEC 10800 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10801 NETIF_F_HW_ESP_TX_CSUM | \ 10802 NETIF_F_GSO_ESP) 10803 10804 if (adapter->ipsec) 10805 netdev->features |= IXGBE_ESP_FEATURES; 10806 #endif 10807 /* copy netdev features into list of user selectable features */ 10808 netdev->hw_features |= netdev->features | 10809 NETIF_F_HW_VLAN_CTAG_FILTER | 10810 NETIF_F_HW_VLAN_CTAG_RX | 10811 NETIF_F_HW_VLAN_CTAG_TX | 10812 NETIF_F_RXALL | 10813 NETIF_F_HW_L2FW_DOFFLOAD; 10814 10815 if (hw->mac.type >= ixgbe_mac_82599EB) 10816 netdev->hw_features |= NETIF_F_NTUPLE | 10817 NETIF_F_HW_TC; 10818 10819 if (pci_using_dac) 10820 netdev->features |= NETIF_F_HIGHDMA; 10821 10822 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10823 netdev->hw_enc_features |= netdev->vlan_features; 10824 netdev->mpls_features |= NETIF_F_SG | 10825 NETIF_F_TSO | 10826 NETIF_F_TSO6 | 10827 NETIF_F_HW_CSUM; 10828 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10829 10830 /* set this bit last since it cannot be part of vlan_features */ 10831 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10832 NETIF_F_HW_VLAN_CTAG_RX | 10833 NETIF_F_HW_VLAN_CTAG_TX; 10834 10835 netdev->priv_flags |= IFF_UNICAST_FLT; 10836 netdev->priv_flags |= IFF_SUPP_NOFCS; 10837 10838 /* MTU range: 68 - 9710 */ 10839 netdev->min_mtu = ETH_MIN_MTU; 10840 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10841 10842 #ifdef CONFIG_IXGBE_DCB 10843 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10844 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10845 #endif 10846 10847 #ifdef IXGBE_FCOE 10848 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10849 unsigned int fcoe_l; 10850 10851 if (hw->mac.ops.get_device_caps) { 10852 hw->mac.ops.get_device_caps(hw, &device_caps); 10853 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10854 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10855 } 10856 10857 10858 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10859 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10860 10861 netdev->features |= NETIF_F_FSO | 10862 NETIF_F_FCOE_CRC; 10863 10864 netdev->vlan_features |= NETIF_F_FSO | 10865 NETIF_F_FCOE_CRC | 10866 NETIF_F_FCOE_MTU; 10867 } 10868 #endif /* IXGBE_FCOE */ 10869 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10870 netdev->hw_features |= NETIF_F_LRO; 10871 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10872 netdev->features |= NETIF_F_LRO; 10873 10874 if (ixgbe_check_fw_error(adapter)) { 10875 err = -EIO; 10876 goto err_sw_init; 10877 } 10878 10879 /* make sure the EEPROM is good */ 10880 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10881 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10882 err = -EIO; 10883 goto err_sw_init; 10884 } 10885 10886 eth_platform_get_mac_address(&adapter->pdev->dev, 10887 adapter->hw.mac.perm_addr); 10888 10889 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10890 10891 if (!is_valid_ether_addr(netdev->dev_addr)) { 10892 e_dev_err("invalid MAC address\n"); 10893 err = -EIO; 10894 goto err_sw_init; 10895 } 10896 10897 /* Set hw->mac.addr to permanent MAC address */ 10898 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10899 ixgbe_mac_set_default_filter(adapter); 10900 10901 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10902 10903 if (ixgbe_removed(hw->hw_addr)) { 10904 err = -EIO; 10905 goto err_sw_init; 10906 } 10907 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10908 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10909 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10910 10911 err = ixgbe_init_interrupt_scheme(adapter); 10912 if (err) 10913 goto err_sw_init; 10914 10915 for (i = 0; i < adapter->num_rx_queues; i++) 10916 u64_stats_init(&adapter->rx_ring[i]->syncp); 10917 for (i = 0; i < adapter->num_tx_queues; i++) 10918 u64_stats_init(&adapter->tx_ring[i]->syncp); 10919 for (i = 0; i < adapter->num_xdp_queues; i++) 10920 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10921 10922 /* WOL not supported for all devices */ 10923 adapter->wol = 0; 10924 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10925 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10926 pdev->subsystem_device); 10927 if (hw->wol_enabled) 10928 adapter->wol = IXGBE_WUFC_MAG; 10929 10930 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10931 10932 /* save off EEPROM version number */ 10933 ixgbe_set_fw_version(adapter); 10934 10935 /* pick up the PCI bus settings for reporting later */ 10936 if (ixgbe_pcie_from_parent(hw)) 10937 ixgbe_get_parent_bus_info(adapter); 10938 else 10939 hw->mac.ops.get_bus_info(hw); 10940 10941 /* calculate the expected PCIe bandwidth required for optimal 10942 * performance. Note that some older parts will never have enough 10943 * bandwidth due to being older generation PCIe parts. We clamp these 10944 * parts to ensure no warning is displayed if it can't be fixed. 10945 */ 10946 switch (hw->mac.type) { 10947 case ixgbe_mac_82598EB: 10948 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10949 break; 10950 default: 10951 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10952 break; 10953 } 10954 10955 /* don't check link if we failed to enumerate functions */ 10956 if (expected_gts > 0) 10957 ixgbe_check_minimum_link(adapter, expected_gts); 10958 10959 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10960 if (err) 10961 strlcpy(part_str, "Unknown", sizeof(part_str)); 10962 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10963 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10964 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10965 part_str); 10966 else 10967 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10968 hw->mac.type, hw->phy.type, part_str); 10969 10970 e_dev_info("%pM\n", netdev->dev_addr); 10971 10972 /* reset the hardware with the new settings */ 10973 err = hw->mac.ops.start_hw(hw); 10974 if (err == IXGBE_ERR_EEPROM_VERSION) { 10975 /* We are running on a pre-production device, log a warning */ 10976 e_dev_warn("This device is a pre-production adapter/LOM. " 10977 "Please be aware there may be issues associated " 10978 "with your hardware. If you are experiencing " 10979 "problems please contact your Intel or hardware " 10980 "representative who provided you with this " 10981 "hardware.\n"); 10982 } 10983 strcpy(netdev->name, "eth%d"); 10984 pci_set_drvdata(pdev, adapter); 10985 err = register_netdev(netdev); 10986 if (err) 10987 goto err_register; 10988 10989 10990 /* power down the optics for 82599 SFP+ fiber */ 10991 if (hw->mac.ops.disable_tx_laser) 10992 hw->mac.ops.disable_tx_laser(hw); 10993 10994 /* carrier off reporting is important to ethtool even BEFORE open */ 10995 netif_carrier_off(netdev); 10996 10997 #ifdef CONFIG_IXGBE_DCA 10998 if (dca_add_requester(&pdev->dev) == 0) { 10999 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11000 ixgbe_setup_dca(adapter); 11001 } 11002 #endif 11003 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11004 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11005 for (i = 0; i < adapter->num_vfs; i++) 11006 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11007 } 11008 11009 /* firmware requires driver version to be 0xFFFFFFFF 11010 * since os does not support feature 11011 */ 11012 if (hw->mac.ops.set_fw_drv_ver) 11013 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11014 sizeof(UTS_RELEASE) - 1, 11015 UTS_RELEASE); 11016 11017 /* add san mac addr to netdev */ 11018 ixgbe_add_sanmac_netdev(netdev); 11019 11020 e_dev_info("%s\n", ixgbe_default_device_descr); 11021 11022 #ifdef CONFIG_IXGBE_HWMON 11023 if (ixgbe_sysfs_init(adapter)) 11024 e_err(probe, "failed to allocate sysfs resources\n"); 11025 #endif /* CONFIG_IXGBE_HWMON */ 11026 11027 ixgbe_dbg_adapter_init(adapter); 11028 11029 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11030 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11031 hw->mac.ops.setup_link(hw, 11032 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11033 true); 11034 11035 err = ixgbe_mii_bus_init(hw); 11036 if (err) 11037 goto err_netdev; 11038 11039 return 0; 11040 11041 err_netdev: 11042 unregister_netdev(netdev); 11043 err_register: 11044 ixgbe_release_hw_control(adapter); 11045 ixgbe_clear_interrupt_scheme(adapter); 11046 err_sw_init: 11047 ixgbe_disable_sriov(adapter); 11048 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11049 iounmap(adapter->io_addr); 11050 kfree(adapter->jump_tables[0]); 11051 kfree(adapter->mac_table); 11052 kfree(adapter->rss_key); 11053 bitmap_free(adapter->af_xdp_zc_qps); 11054 err_ioremap: 11055 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11056 free_netdev(netdev); 11057 err_alloc_etherdev: 11058 pci_release_mem_regions(pdev); 11059 err_pci_reg: 11060 err_dma: 11061 if (!adapter || disable_dev) 11062 pci_disable_device(pdev); 11063 return err; 11064 } 11065 11066 /** 11067 * ixgbe_remove - Device Removal Routine 11068 * @pdev: PCI device information struct 11069 * 11070 * ixgbe_remove is called by the PCI subsystem to alert the driver 11071 * that it should release a PCI device. The could be caused by a 11072 * Hot-Plug event, or because the driver is going to be removed from 11073 * memory. 11074 **/ 11075 static void ixgbe_remove(struct pci_dev *pdev) 11076 { 11077 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11078 struct net_device *netdev; 11079 bool disable_dev; 11080 int i; 11081 11082 /* if !adapter then we already cleaned up in probe */ 11083 if (!adapter) 11084 return; 11085 11086 netdev = adapter->netdev; 11087 ixgbe_dbg_adapter_exit(adapter); 11088 11089 set_bit(__IXGBE_REMOVING, &adapter->state); 11090 cancel_work_sync(&adapter->service_task); 11091 11092 if (adapter->mii_bus) 11093 mdiobus_unregister(adapter->mii_bus); 11094 11095 #ifdef CONFIG_IXGBE_DCA 11096 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11097 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11098 dca_remove_requester(&pdev->dev); 11099 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11100 IXGBE_DCA_CTRL_DCA_DISABLE); 11101 } 11102 11103 #endif 11104 #ifdef CONFIG_IXGBE_HWMON 11105 ixgbe_sysfs_exit(adapter); 11106 #endif /* CONFIG_IXGBE_HWMON */ 11107 11108 /* remove the added san mac */ 11109 ixgbe_del_sanmac_netdev(netdev); 11110 11111 #ifdef CONFIG_PCI_IOV 11112 ixgbe_disable_sriov(adapter); 11113 #endif 11114 if (netdev->reg_state == NETREG_REGISTERED) 11115 unregister_netdev(netdev); 11116 11117 ixgbe_stop_ipsec_offload(adapter); 11118 ixgbe_clear_interrupt_scheme(adapter); 11119 11120 ixgbe_release_hw_control(adapter); 11121 11122 #ifdef CONFIG_DCB 11123 kfree(adapter->ixgbe_ieee_pfc); 11124 kfree(adapter->ixgbe_ieee_ets); 11125 11126 #endif 11127 iounmap(adapter->io_addr); 11128 pci_release_mem_regions(pdev); 11129 11130 e_dev_info("complete\n"); 11131 11132 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11133 if (adapter->jump_tables[i]) { 11134 kfree(adapter->jump_tables[i]->input); 11135 kfree(adapter->jump_tables[i]->mask); 11136 } 11137 kfree(adapter->jump_tables[i]); 11138 } 11139 11140 kfree(adapter->mac_table); 11141 kfree(adapter->rss_key); 11142 bitmap_free(adapter->af_xdp_zc_qps); 11143 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11144 free_netdev(netdev); 11145 11146 pci_disable_pcie_error_reporting(pdev); 11147 11148 if (disable_dev) 11149 pci_disable_device(pdev); 11150 } 11151 11152 /** 11153 * ixgbe_io_error_detected - called when PCI error is detected 11154 * @pdev: Pointer to PCI device 11155 * @state: The current pci connection state 11156 * 11157 * This function is called after a PCI bus error affecting 11158 * this device has been detected. 11159 */ 11160 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11161 pci_channel_state_t state) 11162 { 11163 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11164 struct net_device *netdev = adapter->netdev; 11165 11166 #ifdef CONFIG_PCI_IOV 11167 struct ixgbe_hw *hw = &adapter->hw; 11168 struct pci_dev *bdev, *vfdev; 11169 u32 dw0, dw1, dw2, dw3; 11170 int vf, pos; 11171 u16 req_id, pf_func; 11172 11173 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11174 adapter->num_vfs == 0) 11175 goto skip_bad_vf_detection; 11176 11177 bdev = pdev->bus->self; 11178 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11179 bdev = bdev->bus->self; 11180 11181 if (!bdev) 11182 goto skip_bad_vf_detection; 11183 11184 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11185 if (!pos) 11186 goto skip_bad_vf_detection; 11187 11188 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11189 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11190 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11191 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11192 if (ixgbe_removed(hw->hw_addr)) 11193 goto skip_bad_vf_detection; 11194 11195 req_id = dw1 >> 16; 11196 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11197 if (!(req_id & 0x0080)) 11198 goto skip_bad_vf_detection; 11199 11200 pf_func = req_id & 0x01; 11201 if ((pf_func & 1) == (pdev->devfn & 1)) { 11202 unsigned int device_id; 11203 11204 vf = (req_id & 0x7F) >> 1; 11205 e_dev_err("VF %d has caused a PCIe error\n", vf); 11206 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11207 "%8.8x\tdw3: %8.8x\n", 11208 dw0, dw1, dw2, dw3); 11209 switch (adapter->hw.mac.type) { 11210 case ixgbe_mac_82599EB: 11211 device_id = IXGBE_82599_VF_DEVICE_ID; 11212 break; 11213 case ixgbe_mac_X540: 11214 device_id = IXGBE_X540_VF_DEVICE_ID; 11215 break; 11216 case ixgbe_mac_X550: 11217 device_id = IXGBE_DEV_ID_X550_VF; 11218 break; 11219 case ixgbe_mac_X550EM_x: 11220 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11221 break; 11222 case ixgbe_mac_x550em_a: 11223 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11224 break; 11225 default: 11226 device_id = 0; 11227 break; 11228 } 11229 11230 /* Find the pci device of the offending VF */ 11231 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11232 while (vfdev) { 11233 if (vfdev->devfn == (req_id & 0xFF)) 11234 break; 11235 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11236 device_id, vfdev); 11237 } 11238 /* 11239 * There's a slim chance the VF could have been hot plugged, 11240 * so if it is no longer present we don't need to issue the 11241 * VFLR. Just clean up the AER in that case. 11242 */ 11243 if (vfdev) { 11244 pcie_flr(vfdev); 11245 /* Free device reference count */ 11246 pci_dev_put(vfdev); 11247 } 11248 } 11249 11250 /* 11251 * Even though the error may have occurred on the other port 11252 * we still need to increment the vf error reference count for 11253 * both ports because the I/O resume function will be called 11254 * for both of them. 11255 */ 11256 adapter->vferr_refcount++; 11257 11258 return PCI_ERS_RESULT_RECOVERED; 11259 11260 skip_bad_vf_detection: 11261 #endif /* CONFIG_PCI_IOV */ 11262 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11263 return PCI_ERS_RESULT_DISCONNECT; 11264 11265 if (!netif_device_present(netdev)) 11266 return PCI_ERS_RESULT_DISCONNECT; 11267 11268 rtnl_lock(); 11269 netif_device_detach(netdev); 11270 11271 if (netif_running(netdev)) 11272 ixgbe_close_suspend(adapter); 11273 11274 if (state == pci_channel_io_perm_failure) { 11275 rtnl_unlock(); 11276 return PCI_ERS_RESULT_DISCONNECT; 11277 } 11278 11279 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11280 pci_disable_device(pdev); 11281 rtnl_unlock(); 11282 11283 /* Request a slot reset. */ 11284 return PCI_ERS_RESULT_NEED_RESET; 11285 } 11286 11287 /** 11288 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11289 * @pdev: Pointer to PCI device 11290 * 11291 * Restart the card from scratch, as if from a cold-boot. 11292 */ 11293 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11294 { 11295 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11296 pci_ers_result_t result; 11297 11298 if (pci_enable_device_mem(pdev)) { 11299 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11300 result = PCI_ERS_RESULT_DISCONNECT; 11301 } else { 11302 smp_mb__before_atomic(); 11303 clear_bit(__IXGBE_DISABLED, &adapter->state); 11304 adapter->hw.hw_addr = adapter->io_addr; 11305 pci_set_master(pdev); 11306 pci_restore_state(pdev); 11307 pci_save_state(pdev); 11308 11309 pci_wake_from_d3(pdev, false); 11310 11311 ixgbe_reset(adapter); 11312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11313 result = PCI_ERS_RESULT_RECOVERED; 11314 } 11315 11316 return result; 11317 } 11318 11319 /** 11320 * ixgbe_io_resume - called when traffic can start flowing again. 11321 * @pdev: Pointer to PCI device 11322 * 11323 * This callback is called when the error recovery driver tells us that 11324 * its OK to resume normal operation. 11325 */ 11326 static void ixgbe_io_resume(struct pci_dev *pdev) 11327 { 11328 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11329 struct net_device *netdev = adapter->netdev; 11330 11331 #ifdef CONFIG_PCI_IOV 11332 if (adapter->vferr_refcount) { 11333 e_info(drv, "Resuming after VF err\n"); 11334 adapter->vferr_refcount--; 11335 return; 11336 } 11337 11338 #endif 11339 rtnl_lock(); 11340 if (netif_running(netdev)) 11341 ixgbe_open(netdev); 11342 11343 netif_device_attach(netdev); 11344 rtnl_unlock(); 11345 } 11346 11347 static const struct pci_error_handlers ixgbe_err_handler = { 11348 .error_detected = ixgbe_io_error_detected, 11349 .slot_reset = ixgbe_io_slot_reset, 11350 .resume = ixgbe_io_resume, 11351 }; 11352 11353 static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11354 11355 static struct pci_driver ixgbe_driver = { 11356 .name = ixgbe_driver_name, 11357 .id_table = ixgbe_pci_tbl, 11358 .probe = ixgbe_probe, 11359 .remove = ixgbe_remove, 11360 .driver.pm = &ixgbe_pm_ops, 11361 .shutdown = ixgbe_shutdown, 11362 .sriov_configure = ixgbe_pci_sriov_configure, 11363 .err_handler = &ixgbe_err_handler 11364 }; 11365 11366 /** 11367 * ixgbe_init_module - Driver Registration Routine 11368 * 11369 * ixgbe_init_module is the first routine called when the driver is 11370 * loaded. All it does is register with the PCI subsystem. 11371 **/ 11372 static int __init ixgbe_init_module(void) 11373 { 11374 int ret; 11375 pr_info("%s\n", ixgbe_driver_string); 11376 pr_info("%s\n", ixgbe_copyright); 11377 11378 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11379 if (!ixgbe_wq) { 11380 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11381 return -ENOMEM; 11382 } 11383 11384 ixgbe_dbg_init(); 11385 11386 ret = pci_register_driver(&ixgbe_driver); 11387 if (ret) { 11388 destroy_workqueue(ixgbe_wq); 11389 ixgbe_dbg_exit(); 11390 return ret; 11391 } 11392 11393 #ifdef CONFIG_IXGBE_DCA 11394 dca_register_notify(&dca_notifier); 11395 #endif 11396 11397 return 0; 11398 } 11399 11400 module_init(ixgbe_init_module); 11401 11402 /** 11403 * ixgbe_exit_module - Driver Exit Cleanup Routine 11404 * 11405 * ixgbe_exit_module is called just before the driver is removed 11406 * from memory. 11407 **/ 11408 static void __exit ixgbe_exit_module(void) 11409 { 11410 #ifdef CONFIG_IXGBE_DCA 11411 dca_unregister_notify(&dca_notifier); 11412 #endif 11413 pci_unregister_driver(&ixgbe_driver); 11414 11415 ixgbe_dbg_exit(); 11416 if (ixgbe_wq) { 11417 destroy_workqueue(ixgbe_wq); 11418 ixgbe_wq = NULL; 11419 } 11420 } 11421 11422 #ifdef CONFIG_IXGBE_DCA 11423 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11424 void *p) 11425 { 11426 int ret_val; 11427 11428 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11429 __ixgbe_notify_dca); 11430 11431 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11432 } 11433 11434 #endif /* CONFIG_IXGBE_DCA */ 11435 11436 module_exit(ixgbe_exit_module); 11437 11438 /* ixgbe_main.c */ 11439