1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <linux/bpf.h> 53 #include <linux/bpf_trace.h> 54 #include <linux/atomic.h> 55 #include <scsi/fc/fc_fcoe.h> 56 #include <net/udp_tunnel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/vxlan.h> 61 #include <net/mpls.h> 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 #include "ixgbe_model.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "5.1.0-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2016 Intel Corporation."; 83 84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 85 86 static const struct ixgbe_info *ixgbe_info_tbl[] = { 87 [board_82598] = &ixgbe_82598_info, 88 [board_82599] = &ixgbe_82599_info, 89 [board_X540] = &ixgbe_X540_info, 90 [board_X550] = &ixgbe_X550_info, 91 [board_X550EM_x] = &ixgbe_X550EM_x_info, 92 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 93 [board_x550em_a] = &ixgbe_x550em_a_info, 94 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 152 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 153 /* required last entry */ 154 {0, } 155 }; 156 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 157 158 #ifdef CONFIG_IXGBE_DCA 159 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 160 void *p); 161 static struct notifier_block dca_notifier = { 162 .notifier_call = ixgbe_notify_dca, 163 .next = NULL, 164 .priority = 0 165 }; 166 #endif 167 168 #ifdef CONFIG_PCI_IOV 169 static unsigned int max_vfs; 170 module_param(max_vfs, uint, 0); 171 MODULE_PARM_DESC(max_vfs, 172 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 173 #endif /* CONFIG_PCI_IOV */ 174 175 static unsigned int allow_unsupported_sfp; 176 module_param(allow_unsupported_sfp, uint, 0); 177 MODULE_PARM_DESC(allow_unsupported_sfp, 178 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 179 180 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 181 static int debug = -1; 182 module_param(debug, int, 0); 183 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 184 185 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 186 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 187 MODULE_LICENSE("GPL"); 188 MODULE_VERSION(DRV_VERSION); 189 190 static struct workqueue_struct *ixgbe_wq; 191 192 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 193 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 194 195 static const struct net_device_ops ixgbe_netdev_ops; 196 197 static bool netif_is_ixgbe(struct net_device *dev) 198 { 199 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 200 } 201 202 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 203 u32 reg, u16 *value) 204 { 205 struct pci_dev *parent_dev; 206 struct pci_bus *parent_bus; 207 208 parent_bus = adapter->pdev->bus->parent; 209 if (!parent_bus) 210 return -1; 211 212 parent_dev = parent_bus->self; 213 if (!parent_dev) 214 return -1; 215 216 if (!pci_is_pcie(parent_dev)) 217 return -1; 218 219 pcie_capability_read_word(parent_dev, reg, value); 220 if (*value == IXGBE_FAILED_READ_CFG_WORD && 221 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 222 return -1; 223 return 0; 224 } 225 226 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 227 { 228 struct ixgbe_hw *hw = &adapter->hw; 229 u16 link_status = 0; 230 int err; 231 232 hw->bus.type = ixgbe_bus_type_pci_express; 233 234 /* Get the negotiated link width and speed from PCI config space of the 235 * parent, as this device is behind a switch 236 */ 237 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 238 239 /* assume caller will handle error case */ 240 if (err) 241 return err; 242 243 hw->bus.width = ixgbe_convert_bus_width(link_status); 244 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 245 246 return 0; 247 } 248 249 /** 250 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 251 * @hw: hw specific details 252 * 253 * This function is used by probe to determine whether a device's PCI-Express 254 * bandwidth details should be gathered from the parent bus instead of from the 255 * device. Used to ensure that various locations all have the correct device ID 256 * checks. 257 */ 258 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 259 { 260 switch (hw->device_id) { 261 case IXGBE_DEV_ID_82599_SFP_SF_QP: 262 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 263 return true; 264 default: 265 return false; 266 } 267 } 268 269 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 270 int expected_gts) 271 { 272 struct ixgbe_hw *hw = &adapter->hw; 273 int max_gts = 0; 274 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 275 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 276 struct pci_dev *pdev; 277 278 /* Some devices are not connected over PCIe and thus do not negotiate 279 * speed. These devices do not have valid bus info, and thus any report 280 * we generate may not be correct. 281 */ 282 if (hw->bus.type == ixgbe_bus_type_internal) 283 return; 284 285 /* determine whether to use the parent device */ 286 if (ixgbe_pcie_from_parent(&adapter->hw)) 287 pdev = adapter->pdev->bus->parent->self; 288 else 289 pdev = adapter->pdev; 290 291 if (pcie_get_minimum_link(pdev, &speed, &width) || 292 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 293 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 294 return; 295 } 296 297 switch (speed) { 298 case PCIE_SPEED_2_5GT: 299 /* 8b/10b encoding reduces max throughput by 20% */ 300 max_gts = 2 * width; 301 break; 302 case PCIE_SPEED_5_0GT: 303 /* 8b/10b encoding reduces max throughput by 20% */ 304 max_gts = 4 * width; 305 break; 306 case PCIE_SPEED_8_0GT: 307 /* 128b/130b encoding reduces throughput by less than 2% */ 308 max_gts = 8 * width; 309 break; 310 default: 311 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 312 return; 313 } 314 315 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 316 max_gts); 317 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 318 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 319 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 320 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 321 "Unknown"), 322 width, 323 (speed == PCIE_SPEED_2_5GT ? "20%" : 324 speed == PCIE_SPEED_5_0GT ? "20%" : 325 speed == PCIE_SPEED_8_0GT ? "<2%" : 326 "Unknown")); 327 328 if (max_gts < expected_gts) { 329 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 330 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 331 expected_gts); 332 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 333 } 334 } 335 336 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 337 { 338 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 339 !test_bit(__IXGBE_REMOVING, &adapter->state) && 340 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 341 queue_work(ixgbe_wq, &adapter->service_task); 342 } 343 344 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 345 { 346 struct ixgbe_adapter *adapter = hw->back; 347 348 if (!hw->hw_addr) 349 return; 350 hw->hw_addr = NULL; 351 e_dev_err("Adapter removed\n"); 352 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 353 ixgbe_service_event_schedule(adapter); 354 } 355 356 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 357 { 358 u8 __iomem *reg_addr; 359 u32 value; 360 int i; 361 362 reg_addr = READ_ONCE(hw->hw_addr); 363 if (ixgbe_removed(reg_addr)) 364 return IXGBE_FAILED_READ_REG; 365 366 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 367 * so perform several status register reads to determine if the adapter 368 * has been removed. 369 */ 370 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 371 value = readl(reg_addr + IXGBE_STATUS); 372 if (value != IXGBE_FAILED_READ_REG) 373 break; 374 mdelay(3); 375 } 376 377 if (value == IXGBE_FAILED_READ_REG) 378 ixgbe_remove_adapter(hw); 379 else 380 value = readl(reg_addr + reg); 381 return value; 382 } 383 384 /** 385 * ixgbe_read_reg - Read from device register 386 * @hw: hw specific details 387 * @reg: offset of register to read 388 * 389 * Returns : value read or IXGBE_FAILED_READ_REG if removed 390 * 391 * This function is used to read device registers. It checks for device 392 * removal by confirming any read that returns all ones by checking the 393 * status register value for all ones. This function avoids reading from 394 * the hardware if a removal was previously detected in which case it 395 * returns IXGBE_FAILED_READ_REG (all ones). 396 */ 397 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 398 { 399 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 400 u32 value; 401 402 if (ixgbe_removed(reg_addr)) 403 return IXGBE_FAILED_READ_REG; 404 if (unlikely(hw->phy.nw_mng_if_sel & 405 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 406 struct ixgbe_adapter *adapter; 407 int i; 408 409 for (i = 0; i < 200; ++i) { 410 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 411 if (likely(!value)) 412 goto writes_completed; 413 if (value == IXGBE_FAILED_READ_REG) { 414 ixgbe_remove_adapter(hw); 415 return IXGBE_FAILED_READ_REG; 416 } 417 udelay(5); 418 } 419 420 adapter = hw->back; 421 e_warn(hw, "register writes incomplete %08x\n", value); 422 } 423 424 writes_completed: 425 value = readl(reg_addr + reg); 426 if (unlikely(value == IXGBE_FAILED_READ_REG)) 427 value = ixgbe_check_remove(hw, reg); 428 return value; 429 } 430 431 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 432 { 433 u16 value; 434 435 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 436 if (value == IXGBE_FAILED_READ_CFG_WORD) { 437 ixgbe_remove_adapter(hw); 438 return true; 439 } 440 return false; 441 } 442 443 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 444 { 445 struct ixgbe_adapter *adapter = hw->back; 446 u16 value; 447 448 if (ixgbe_removed(hw->hw_addr)) 449 return IXGBE_FAILED_READ_CFG_WORD; 450 pci_read_config_word(adapter->pdev, reg, &value); 451 if (value == IXGBE_FAILED_READ_CFG_WORD && 452 ixgbe_check_cfg_remove(hw, adapter->pdev)) 453 return IXGBE_FAILED_READ_CFG_WORD; 454 return value; 455 } 456 457 #ifdef CONFIG_PCI_IOV 458 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 459 { 460 struct ixgbe_adapter *adapter = hw->back; 461 u32 value; 462 463 if (ixgbe_removed(hw->hw_addr)) 464 return IXGBE_FAILED_READ_CFG_DWORD; 465 pci_read_config_dword(adapter->pdev, reg, &value); 466 if (value == IXGBE_FAILED_READ_CFG_DWORD && 467 ixgbe_check_cfg_remove(hw, adapter->pdev)) 468 return IXGBE_FAILED_READ_CFG_DWORD; 469 return value; 470 } 471 #endif /* CONFIG_PCI_IOV */ 472 473 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 474 { 475 struct ixgbe_adapter *adapter = hw->back; 476 477 if (ixgbe_removed(hw->hw_addr)) 478 return; 479 pci_write_config_word(adapter->pdev, reg, value); 480 } 481 482 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 483 { 484 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 485 486 /* flush memory to make sure state is correct before next watchdog */ 487 smp_mb__before_atomic(); 488 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 489 } 490 491 struct ixgbe_reg_info { 492 u32 ofs; 493 char *name; 494 }; 495 496 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 497 498 /* General Registers */ 499 {IXGBE_CTRL, "CTRL"}, 500 {IXGBE_STATUS, "STATUS"}, 501 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 502 503 /* Interrupt Registers */ 504 {IXGBE_EICR, "EICR"}, 505 506 /* RX Registers */ 507 {IXGBE_SRRCTL(0), "SRRCTL"}, 508 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 509 {IXGBE_RDLEN(0), "RDLEN"}, 510 {IXGBE_RDH(0), "RDH"}, 511 {IXGBE_RDT(0), "RDT"}, 512 {IXGBE_RXDCTL(0), "RXDCTL"}, 513 {IXGBE_RDBAL(0), "RDBAL"}, 514 {IXGBE_RDBAH(0), "RDBAH"}, 515 516 /* TX Registers */ 517 {IXGBE_TDBAL(0), "TDBAL"}, 518 {IXGBE_TDBAH(0), "TDBAH"}, 519 {IXGBE_TDLEN(0), "TDLEN"}, 520 {IXGBE_TDH(0), "TDH"}, 521 {IXGBE_TDT(0), "TDT"}, 522 {IXGBE_TXDCTL(0), "TXDCTL"}, 523 524 /* List Terminator */ 525 { .name = NULL } 526 }; 527 528 529 /* 530 * ixgbe_regdump - register printout routine 531 */ 532 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 533 { 534 int i; 535 char rname[16]; 536 u32 regs[64]; 537 538 switch (reginfo->ofs) { 539 case IXGBE_SRRCTL(0): 540 for (i = 0; i < 64; i++) 541 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 542 break; 543 case IXGBE_DCA_RXCTRL(0): 544 for (i = 0; i < 64; i++) 545 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 546 break; 547 case IXGBE_RDLEN(0): 548 for (i = 0; i < 64; i++) 549 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 550 break; 551 case IXGBE_RDH(0): 552 for (i = 0; i < 64; i++) 553 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 554 break; 555 case IXGBE_RDT(0): 556 for (i = 0; i < 64; i++) 557 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 558 break; 559 case IXGBE_RXDCTL(0): 560 for (i = 0; i < 64; i++) 561 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 562 break; 563 case IXGBE_RDBAL(0): 564 for (i = 0; i < 64; i++) 565 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 566 break; 567 case IXGBE_RDBAH(0): 568 for (i = 0; i < 64; i++) 569 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 570 break; 571 case IXGBE_TDBAL(0): 572 for (i = 0; i < 64; i++) 573 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 574 break; 575 case IXGBE_TDBAH(0): 576 for (i = 0; i < 64; i++) 577 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 578 break; 579 case IXGBE_TDLEN(0): 580 for (i = 0; i < 64; i++) 581 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 582 break; 583 case IXGBE_TDH(0): 584 for (i = 0; i < 64; i++) 585 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 586 break; 587 case IXGBE_TDT(0): 588 for (i = 0; i < 64; i++) 589 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 590 break; 591 case IXGBE_TXDCTL(0): 592 for (i = 0; i < 64; i++) 593 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 594 break; 595 default: 596 pr_info("%-15s %08x\n", 597 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 598 return; 599 } 600 601 i = 0; 602 while (i < 64) { 603 int j; 604 char buf[9 * 8 + 1]; 605 char *p = buf; 606 607 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 608 for (j = 0; j < 8; j++) 609 p += sprintf(p, " %08x", regs[i++]); 610 pr_err("%-15s%s\n", rname, buf); 611 } 612 613 } 614 615 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 616 { 617 struct ixgbe_tx_buffer *tx_buffer; 618 619 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 620 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 621 n, ring->next_to_use, ring->next_to_clean, 622 (u64)dma_unmap_addr(tx_buffer, dma), 623 dma_unmap_len(tx_buffer, len), 624 tx_buffer->next_to_watch, 625 (u64)tx_buffer->time_stamp); 626 } 627 628 /* 629 * ixgbe_dump - Print registers, tx-rings and rx-rings 630 */ 631 static void ixgbe_dump(struct ixgbe_adapter *adapter) 632 { 633 struct net_device *netdev = adapter->netdev; 634 struct ixgbe_hw *hw = &adapter->hw; 635 struct ixgbe_reg_info *reginfo; 636 int n = 0; 637 struct ixgbe_ring *ring; 638 struct ixgbe_tx_buffer *tx_buffer; 639 union ixgbe_adv_tx_desc *tx_desc; 640 struct my_u0 { u64 a; u64 b; } *u0; 641 struct ixgbe_ring *rx_ring; 642 union ixgbe_adv_rx_desc *rx_desc; 643 struct ixgbe_rx_buffer *rx_buffer_info; 644 int i = 0; 645 646 if (!netif_msg_hw(adapter)) 647 return; 648 649 /* Print netdevice Info */ 650 if (netdev) { 651 dev_info(&adapter->pdev->dev, "Net device Info\n"); 652 pr_info("Device Name state " 653 "trans_start\n"); 654 pr_info("%-15s %016lX %016lX\n", 655 netdev->name, 656 netdev->state, 657 dev_trans_start(netdev)); 658 } 659 660 /* Print Registers */ 661 dev_info(&adapter->pdev->dev, "Register Dump\n"); 662 pr_info(" Register Name Value\n"); 663 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 664 reginfo->name; reginfo++) { 665 ixgbe_regdump(hw, reginfo); 666 } 667 668 /* Print TX Ring Summary */ 669 if (!netdev || !netif_running(netdev)) 670 return; 671 672 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 673 pr_info(" %s %s %s %s\n", 674 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 675 "leng", "ntw", "timestamp"); 676 for (n = 0; n < adapter->num_tx_queues; n++) { 677 ring = adapter->tx_ring[n]; 678 ixgbe_print_buffer(ring, n); 679 } 680 681 for (n = 0; n < adapter->num_xdp_queues; n++) { 682 ring = adapter->xdp_ring[n]; 683 ixgbe_print_buffer(ring, n); 684 } 685 686 /* Print TX Rings */ 687 if (!netif_msg_tx_done(adapter)) 688 goto rx_ring_summary; 689 690 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 691 692 /* Transmit Descriptor Formats 693 * 694 * 82598 Advanced Transmit Descriptor 695 * +--------------------------------------------------------------+ 696 * 0 | Buffer Address [63:0] | 697 * +--------------------------------------------------------------+ 698 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 699 * +--------------------------------------------------------------+ 700 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 701 * 702 * 82598 Advanced Transmit Descriptor (Write-Back Format) 703 * +--------------------------------------------------------------+ 704 * 0 | RSV [63:0] | 705 * +--------------------------------------------------------------+ 706 * 8 | RSV | STA | NXTSEQ | 707 * +--------------------------------------------------------------+ 708 * 63 36 35 32 31 0 709 * 710 * 82599+ Advanced Transmit Descriptor 711 * +--------------------------------------------------------------+ 712 * 0 | Buffer Address [63:0] | 713 * +--------------------------------------------------------------+ 714 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 715 * +--------------------------------------------------------------+ 716 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 717 * 718 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 719 * +--------------------------------------------------------------+ 720 * 0 | RSV [63:0] | 721 * +--------------------------------------------------------------+ 722 * 8 | RSV | STA | RSV | 723 * +--------------------------------------------------------------+ 724 * 63 36 35 32 31 0 725 */ 726 727 for (n = 0; n < adapter->num_tx_queues; n++) { 728 ring = adapter->tx_ring[n]; 729 pr_info("------------------------------------\n"); 730 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 731 pr_info("------------------------------------\n"); 732 pr_info("%s%s %s %s %s %s\n", 733 "T [desc] [address 63:0 ] ", 734 "[PlPOIdStDDt Ln] [bi->dma ] ", 735 "leng", "ntw", "timestamp", "bi->skb"); 736 737 for (i = 0; ring->desc && (i < ring->count); i++) { 738 tx_desc = IXGBE_TX_DESC(ring, i); 739 tx_buffer = &ring->tx_buffer_info[i]; 740 u0 = (struct my_u0 *)tx_desc; 741 if (dma_unmap_len(tx_buffer, len) > 0) { 742 const char *ring_desc; 743 744 if (i == ring->next_to_use && 745 i == ring->next_to_clean) 746 ring_desc = " NTC/U"; 747 else if (i == ring->next_to_use) 748 ring_desc = " NTU"; 749 else if (i == ring->next_to_clean) 750 ring_desc = " NTC"; 751 else 752 ring_desc = ""; 753 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 754 i, 755 le64_to_cpu(u0->a), 756 le64_to_cpu(u0->b), 757 (u64)dma_unmap_addr(tx_buffer, dma), 758 dma_unmap_len(tx_buffer, len), 759 tx_buffer->next_to_watch, 760 (u64)tx_buffer->time_stamp, 761 tx_buffer->skb, 762 ring_desc); 763 764 if (netif_msg_pktdata(adapter) && 765 tx_buffer->skb) 766 print_hex_dump(KERN_INFO, "", 767 DUMP_PREFIX_ADDRESS, 16, 1, 768 tx_buffer->skb->data, 769 dma_unmap_len(tx_buffer, len), 770 true); 771 } 772 } 773 } 774 775 /* Print RX Rings Summary */ 776 rx_ring_summary: 777 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 778 pr_info("Queue [NTU] [NTC]\n"); 779 for (n = 0; n < adapter->num_rx_queues; n++) { 780 rx_ring = adapter->rx_ring[n]; 781 pr_info("%5d %5X %5X\n", 782 n, rx_ring->next_to_use, rx_ring->next_to_clean); 783 } 784 785 /* Print RX Rings */ 786 if (!netif_msg_rx_status(adapter)) 787 return; 788 789 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 790 791 /* Receive Descriptor Formats 792 * 793 * 82598 Advanced Receive Descriptor (Read) Format 794 * 63 1 0 795 * +-----------------------------------------------------+ 796 * 0 | Packet Buffer Address [63:1] |A0/NSE| 797 * +----------------------------------------------+------+ 798 * 8 | Header Buffer Address [63:1] | DD | 799 * +-----------------------------------------------------+ 800 * 801 * 802 * 82598 Advanced Receive Descriptor (Write-Back) Format 803 * 804 * 63 48 47 32 31 30 21 20 16 15 4 3 0 805 * +------------------------------------------------------+ 806 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 807 * | Packet | IP | | | | Type | Type | 808 * | Checksum | Ident | | | | | | 809 * +------------------------------------------------------+ 810 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 811 * +------------------------------------------------------+ 812 * 63 48 47 32 31 20 19 0 813 * 814 * 82599+ Advanced Receive Descriptor (Read) Format 815 * 63 1 0 816 * +-----------------------------------------------------+ 817 * 0 | Packet Buffer Address [63:1] |A0/NSE| 818 * +----------------------------------------------+------+ 819 * 8 | Header Buffer Address [63:1] | DD | 820 * +-----------------------------------------------------+ 821 * 822 * 823 * 82599+ Advanced Receive Descriptor (Write-Back) Format 824 * 825 * 63 48 47 32 31 30 21 20 17 16 4 3 0 826 * +------------------------------------------------------+ 827 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 828 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 829 * |/ Flow Dir Flt ID | | | | | | 830 * +------------------------------------------------------+ 831 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 832 * +------------------------------------------------------+ 833 * 63 48 47 32 31 20 19 0 834 */ 835 836 for (n = 0; n < adapter->num_rx_queues; n++) { 837 rx_ring = adapter->rx_ring[n]; 838 pr_info("------------------------------------\n"); 839 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 840 pr_info("------------------------------------\n"); 841 pr_info("%s%s%s\n", 842 "R [desc] [ PktBuf A0] ", 843 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 844 "<-- Adv Rx Read format"); 845 pr_info("%s%s%s\n", 846 "RWB[desc] [PcsmIpSHl PtRs] ", 847 "[vl er S cks ln] ---------------- [bi->skb ] ", 848 "<-- Adv Rx Write-Back format"); 849 850 for (i = 0; i < rx_ring->count; i++) { 851 const char *ring_desc; 852 853 if (i == rx_ring->next_to_use) 854 ring_desc = " NTU"; 855 else if (i == rx_ring->next_to_clean) 856 ring_desc = " NTC"; 857 else 858 ring_desc = ""; 859 860 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 861 rx_desc = IXGBE_RX_DESC(rx_ring, i); 862 u0 = (struct my_u0 *)rx_desc; 863 if (rx_desc->wb.upper.length) { 864 /* Descriptor Done */ 865 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 866 i, 867 le64_to_cpu(u0->a), 868 le64_to_cpu(u0->b), 869 rx_buffer_info->skb, 870 ring_desc); 871 } else { 872 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 873 i, 874 le64_to_cpu(u0->a), 875 le64_to_cpu(u0->b), 876 (u64)rx_buffer_info->dma, 877 rx_buffer_info->skb, 878 ring_desc); 879 880 if (netif_msg_pktdata(adapter) && 881 rx_buffer_info->dma) { 882 print_hex_dump(KERN_INFO, "", 883 DUMP_PREFIX_ADDRESS, 16, 1, 884 page_address(rx_buffer_info->page) + 885 rx_buffer_info->page_offset, 886 ixgbe_rx_bufsz(rx_ring), true); 887 } 888 } 889 } 890 } 891 } 892 893 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 894 { 895 u32 ctrl_ext; 896 897 /* Let firmware take over control of h/w */ 898 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 900 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 901 } 902 903 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 904 { 905 u32 ctrl_ext; 906 907 /* Let firmware know the driver has taken over */ 908 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 910 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 911 } 912 913 /** 914 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 915 * @adapter: pointer to adapter struct 916 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 917 * @queue: queue to map the corresponding interrupt to 918 * @msix_vector: the vector to map to the corresponding queue 919 * 920 */ 921 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 922 u8 queue, u8 msix_vector) 923 { 924 u32 ivar, index; 925 struct ixgbe_hw *hw = &adapter->hw; 926 switch (hw->mac.type) { 927 case ixgbe_mac_82598EB: 928 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 929 if (direction == -1) 930 direction = 0; 931 index = (((direction * 64) + queue) >> 2) & 0x1F; 932 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 933 ivar &= ~(0xFF << (8 * (queue & 0x3))); 934 ivar |= (msix_vector << (8 * (queue & 0x3))); 935 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 936 break; 937 case ixgbe_mac_82599EB: 938 case ixgbe_mac_X540: 939 case ixgbe_mac_X550: 940 case ixgbe_mac_X550EM_x: 941 case ixgbe_mac_x550em_a: 942 if (direction == -1) { 943 /* other causes */ 944 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 945 index = ((queue & 1) * 8); 946 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 947 ivar &= ~(0xFF << index); 948 ivar |= (msix_vector << index); 949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 950 break; 951 } else { 952 /* tx or rx causes */ 953 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 954 index = ((16 * (queue & 1)) + (8 * direction)); 955 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 956 ivar &= ~(0xFF << index); 957 ivar |= (msix_vector << index); 958 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 959 break; 960 } 961 default: 962 break; 963 } 964 } 965 966 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 967 u64 qmask) 968 { 969 u32 mask; 970 971 switch (adapter->hw.mac.type) { 972 case ixgbe_mac_82598EB: 973 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 974 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 975 break; 976 case ixgbe_mac_82599EB: 977 case ixgbe_mac_X540: 978 case ixgbe_mac_X550: 979 case ixgbe_mac_X550EM_x: 980 case ixgbe_mac_x550em_a: 981 mask = (qmask & 0xFFFFFFFF); 982 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 983 mask = (qmask >> 32); 984 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 985 break; 986 default: 987 break; 988 } 989 } 990 991 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 992 { 993 struct ixgbe_hw *hw = &adapter->hw; 994 struct ixgbe_hw_stats *hwstats = &adapter->stats; 995 int i; 996 u32 data; 997 998 if ((hw->fc.current_mode != ixgbe_fc_full) && 999 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 1000 return; 1001 1002 switch (hw->mac.type) { 1003 case ixgbe_mac_82598EB: 1004 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 1005 break; 1006 default: 1007 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 1008 } 1009 hwstats->lxoffrxc += data; 1010 1011 /* refill credits (no tx hang) if we received xoff */ 1012 if (!data) 1013 return; 1014 1015 for (i = 0; i < adapter->num_tx_queues; i++) 1016 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1017 &adapter->tx_ring[i]->state); 1018 1019 for (i = 0; i < adapter->num_xdp_queues; i++) 1020 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1021 &adapter->xdp_ring[i]->state); 1022 } 1023 1024 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1025 { 1026 struct ixgbe_hw *hw = &adapter->hw; 1027 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1028 u32 xoff[8] = {0}; 1029 u8 tc; 1030 int i; 1031 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1032 1033 if (adapter->ixgbe_ieee_pfc) 1034 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1035 1036 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1037 ixgbe_update_xoff_rx_lfc(adapter); 1038 return; 1039 } 1040 1041 /* update stats for each tc, only valid with PFC enabled */ 1042 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1043 u32 pxoffrxc; 1044 1045 switch (hw->mac.type) { 1046 case ixgbe_mac_82598EB: 1047 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1048 break; 1049 default: 1050 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1051 } 1052 hwstats->pxoffrxc[i] += pxoffrxc; 1053 /* Get the TC for given UP */ 1054 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1055 xoff[tc] += pxoffrxc; 1056 } 1057 1058 /* disarm tx queues that have received xoff frames */ 1059 for (i = 0; i < adapter->num_tx_queues; i++) { 1060 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1061 1062 tc = tx_ring->dcb_tc; 1063 if (xoff[tc]) 1064 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1065 } 1066 1067 for (i = 0; i < adapter->num_xdp_queues; i++) { 1068 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1069 1070 tc = xdp_ring->dcb_tc; 1071 if (xoff[tc]) 1072 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1073 } 1074 } 1075 1076 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1077 { 1078 return ring->stats.packets; 1079 } 1080 1081 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1082 { 1083 unsigned int head, tail; 1084 1085 head = ring->next_to_clean; 1086 tail = ring->next_to_use; 1087 1088 return ((head <= tail) ? tail : tail + ring->count) - head; 1089 } 1090 1091 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1092 { 1093 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1094 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1095 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1096 1097 clear_check_for_tx_hang(tx_ring); 1098 1099 /* 1100 * Check for a hung queue, but be thorough. This verifies 1101 * that a transmit has been completed since the previous 1102 * check AND there is at least one packet pending. The 1103 * ARMED bit is set to indicate a potential hang. The 1104 * bit is cleared if a pause frame is received to remove 1105 * false hang detection due to PFC or 802.3x frames. By 1106 * requiring this to fail twice we avoid races with 1107 * pfc clearing the ARMED bit and conditions where we 1108 * run the check_tx_hang logic with a transmit completion 1109 * pending but without time to complete it yet. 1110 */ 1111 if (tx_done_old == tx_done && tx_pending) 1112 /* make sure it is true for two checks in a row */ 1113 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1114 &tx_ring->state); 1115 /* update completed stats and continue */ 1116 tx_ring->tx_stats.tx_done_old = tx_done; 1117 /* reset the countdown */ 1118 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1119 1120 return false; 1121 } 1122 1123 /** 1124 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1125 * @adapter: driver private struct 1126 **/ 1127 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1128 { 1129 1130 /* Do the reset outside of interrupt context */ 1131 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1132 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1133 e_warn(drv, "initiating reset due to tx timeout\n"); 1134 ixgbe_service_event_schedule(adapter); 1135 } 1136 } 1137 1138 /** 1139 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1140 * @netdev: network interface device structure 1141 * @queue_index: Tx queue to set 1142 * @maxrate: desired maximum transmit bitrate 1143 **/ 1144 static int ixgbe_tx_maxrate(struct net_device *netdev, 1145 int queue_index, u32 maxrate) 1146 { 1147 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1148 struct ixgbe_hw *hw = &adapter->hw; 1149 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1150 1151 if (!maxrate) 1152 return 0; 1153 1154 /* Calculate the rate factor values to set */ 1155 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1156 bcnrc_val /= maxrate; 1157 1158 /* clear everything but the rate factor */ 1159 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1160 IXGBE_RTTBCNRC_RF_DEC_MASK; 1161 1162 /* enable the rate scheduler */ 1163 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1164 1165 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1166 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1167 1168 return 0; 1169 } 1170 1171 /** 1172 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1173 * @q_vector: structure containing interrupt and ring information 1174 * @tx_ring: tx ring to clean 1175 * @napi_budget: Used to determine if we are in netpoll 1176 **/ 1177 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1178 struct ixgbe_ring *tx_ring, int napi_budget) 1179 { 1180 struct ixgbe_adapter *adapter = q_vector->adapter; 1181 struct ixgbe_tx_buffer *tx_buffer; 1182 union ixgbe_adv_tx_desc *tx_desc; 1183 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1184 unsigned int budget = q_vector->tx.work_limit; 1185 unsigned int i = tx_ring->next_to_clean; 1186 1187 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1188 return true; 1189 1190 tx_buffer = &tx_ring->tx_buffer_info[i]; 1191 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1192 i -= tx_ring->count; 1193 1194 do { 1195 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1196 1197 /* if next_to_watch is not set then there is no work pending */ 1198 if (!eop_desc) 1199 break; 1200 1201 /* prevent any other reads prior to eop_desc */ 1202 smp_rmb(); 1203 1204 /* if DD is not set pending work has not been completed */ 1205 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1206 break; 1207 1208 /* clear next_to_watch to prevent false hangs */ 1209 tx_buffer->next_to_watch = NULL; 1210 1211 /* update the statistics for this packet */ 1212 total_bytes += tx_buffer->bytecount; 1213 total_packets += tx_buffer->gso_segs; 1214 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1215 total_ipsec++; 1216 1217 /* free the skb */ 1218 if (ring_is_xdp(tx_ring)) 1219 xdp_return_frame(tx_buffer->xdpf); 1220 else 1221 napi_consume_skb(tx_buffer->skb, napi_budget); 1222 1223 /* unmap skb header data */ 1224 dma_unmap_single(tx_ring->dev, 1225 dma_unmap_addr(tx_buffer, dma), 1226 dma_unmap_len(tx_buffer, len), 1227 DMA_TO_DEVICE); 1228 1229 /* clear tx_buffer data */ 1230 dma_unmap_len_set(tx_buffer, len, 0); 1231 1232 /* unmap remaining buffers */ 1233 while (tx_desc != eop_desc) { 1234 tx_buffer++; 1235 tx_desc++; 1236 i++; 1237 if (unlikely(!i)) { 1238 i -= tx_ring->count; 1239 tx_buffer = tx_ring->tx_buffer_info; 1240 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1241 } 1242 1243 /* unmap any remaining paged data */ 1244 if (dma_unmap_len(tx_buffer, len)) { 1245 dma_unmap_page(tx_ring->dev, 1246 dma_unmap_addr(tx_buffer, dma), 1247 dma_unmap_len(tx_buffer, len), 1248 DMA_TO_DEVICE); 1249 dma_unmap_len_set(tx_buffer, len, 0); 1250 } 1251 } 1252 1253 /* move us one more past the eop_desc for start of next pkt */ 1254 tx_buffer++; 1255 tx_desc++; 1256 i++; 1257 if (unlikely(!i)) { 1258 i -= tx_ring->count; 1259 tx_buffer = tx_ring->tx_buffer_info; 1260 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1261 } 1262 1263 /* issue prefetch for next Tx descriptor */ 1264 prefetch(tx_desc); 1265 1266 /* update budget accounting */ 1267 budget--; 1268 } while (likely(budget)); 1269 1270 i += tx_ring->count; 1271 tx_ring->next_to_clean = i; 1272 u64_stats_update_begin(&tx_ring->syncp); 1273 tx_ring->stats.bytes += total_bytes; 1274 tx_ring->stats.packets += total_packets; 1275 u64_stats_update_end(&tx_ring->syncp); 1276 q_vector->tx.total_bytes += total_bytes; 1277 q_vector->tx.total_packets += total_packets; 1278 adapter->tx_ipsec += total_ipsec; 1279 1280 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1281 /* schedule immediate reset if we believe we hung */ 1282 struct ixgbe_hw *hw = &adapter->hw; 1283 e_err(drv, "Detected Tx Unit Hang %s\n" 1284 " Tx Queue <%d>\n" 1285 " TDH, TDT <%x>, <%x>\n" 1286 " next_to_use <%x>\n" 1287 " next_to_clean <%x>\n" 1288 "tx_buffer_info[next_to_clean]\n" 1289 " time_stamp <%lx>\n" 1290 " jiffies <%lx>\n", 1291 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1292 tx_ring->queue_index, 1293 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1294 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1295 tx_ring->next_to_use, i, 1296 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1297 1298 if (!ring_is_xdp(tx_ring)) 1299 netif_stop_subqueue(tx_ring->netdev, 1300 tx_ring->queue_index); 1301 1302 e_info(probe, 1303 "tx hang %d detected on queue %d, resetting adapter\n", 1304 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1305 1306 /* schedule immediate reset if we believe we hung */ 1307 ixgbe_tx_timeout_reset(adapter); 1308 1309 /* the adapter is about to reset, no point in enabling stuff */ 1310 return true; 1311 } 1312 1313 if (ring_is_xdp(tx_ring)) 1314 return !!budget; 1315 1316 netdev_tx_completed_queue(txring_txq(tx_ring), 1317 total_packets, total_bytes); 1318 1319 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1320 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1321 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1322 /* Make sure that anybody stopping the queue after this 1323 * sees the new next_to_clean. 1324 */ 1325 smp_mb(); 1326 if (__netif_subqueue_stopped(tx_ring->netdev, 1327 tx_ring->queue_index) 1328 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1329 netif_wake_subqueue(tx_ring->netdev, 1330 tx_ring->queue_index); 1331 ++tx_ring->tx_stats.restart_queue; 1332 } 1333 } 1334 1335 return !!budget; 1336 } 1337 1338 #ifdef CONFIG_IXGBE_DCA 1339 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1340 struct ixgbe_ring *tx_ring, 1341 int cpu) 1342 { 1343 struct ixgbe_hw *hw = &adapter->hw; 1344 u32 txctrl = 0; 1345 u16 reg_offset; 1346 1347 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1348 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1349 1350 switch (hw->mac.type) { 1351 case ixgbe_mac_82598EB: 1352 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1353 break; 1354 case ixgbe_mac_82599EB: 1355 case ixgbe_mac_X540: 1356 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1357 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1358 break; 1359 default: 1360 /* for unknown hardware do not write register */ 1361 return; 1362 } 1363 1364 /* 1365 * We can enable relaxed ordering for reads, but not writes when 1366 * DCA is enabled. This is due to a known issue in some chipsets 1367 * which will cause the DCA tag to be cleared. 1368 */ 1369 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1370 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1371 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1372 1373 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1374 } 1375 1376 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1377 struct ixgbe_ring *rx_ring, 1378 int cpu) 1379 { 1380 struct ixgbe_hw *hw = &adapter->hw; 1381 u32 rxctrl = 0; 1382 u8 reg_idx = rx_ring->reg_idx; 1383 1384 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1385 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1386 1387 switch (hw->mac.type) { 1388 case ixgbe_mac_82599EB: 1389 case ixgbe_mac_X540: 1390 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1391 break; 1392 default: 1393 break; 1394 } 1395 1396 /* 1397 * We can enable relaxed ordering for reads, but not writes when 1398 * DCA is enabled. This is due to a known issue in some chipsets 1399 * which will cause the DCA tag to be cleared. 1400 */ 1401 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1402 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1403 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1404 1405 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1406 } 1407 1408 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1409 { 1410 struct ixgbe_adapter *adapter = q_vector->adapter; 1411 struct ixgbe_ring *ring; 1412 int cpu = get_cpu(); 1413 1414 if (q_vector->cpu == cpu) 1415 goto out_no_update; 1416 1417 ixgbe_for_each_ring(ring, q_vector->tx) 1418 ixgbe_update_tx_dca(adapter, ring, cpu); 1419 1420 ixgbe_for_each_ring(ring, q_vector->rx) 1421 ixgbe_update_rx_dca(adapter, ring, cpu); 1422 1423 q_vector->cpu = cpu; 1424 out_no_update: 1425 put_cpu(); 1426 } 1427 1428 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1429 { 1430 int i; 1431 1432 /* always use CB2 mode, difference is masked in the CB driver */ 1433 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1435 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1436 else 1437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1438 IXGBE_DCA_CTRL_DCA_DISABLE); 1439 1440 for (i = 0; i < adapter->num_q_vectors; i++) { 1441 adapter->q_vector[i]->cpu = -1; 1442 ixgbe_update_dca(adapter->q_vector[i]); 1443 } 1444 } 1445 1446 static int __ixgbe_notify_dca(struct device *dev, void *data) 1447 { 1448 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1449 unsigned long event = *(unsigned long *)data; 1450 1451 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1452 return 0; 1453 1454 switch (event) { 1455 case DCA_PROVIDER_ADD: 1456 /* if we're already enabled, don't do it again */ 1457 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1458 break; 1459 if (dca_add_requester(dev) == 0) { 1460 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1462 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1463 break; 1464 } 1465 /* fall through - DCA is disabled. */ 1466 case DCA_PROVIDER_REMOVE: 1467 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1468 dca_remove_requester(dev); 1469 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1470 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1471 IXGBE_DCA_CTRL_DCA_DISABLE); 1472 } 1473 break; 1474 } 1475 1476 return 0; 1477 } 1478 1479 #endif /* CONFIG_IXGBE_DCA */ 1480 1481 #define IXGBE_RSS_L4_TYPES_MASK \ 1482 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1483 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1484 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1485 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1486 1487 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1488 union ixgbe_adv_rx_desc *rx_desc, 1489 struct sk_buff *skb) 1490 { 1491 u16 rss_type; 1492 1493 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1494 return; 1495 1496 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1497 IXGBE_RXDADV_RSSTYPE_MASK; 1498 1499 if (!rss_type) 1500 return; 1501 1502 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1503 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1504 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1505 } 1506 1507 #ifdef IXGBE_FCOE 1508 /** 1509 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1510 * @ring: structure containing ring specific data 1511 * @rx_desc: advanced rx descriptor 1512 * 1513 * Returns : true if it is FCoE pkt 1514 */ 1515 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1516 union ixgbe_adv_rx_desc *rx_desc) 1517 { 1518 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1519 1520 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1521 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1522 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1523 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1524 } 1525 1526 #endif /* IXGBE_FCOE */ 1527 /** 1528 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1529 * @ring: structure containing ring specific data 1530 * @rx_desc: current Rx descriptor being processed 1531 * @skb: skb currently being received and modified 1532 **/ 1533 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1534 union ixgbe_adv_rx_desc *rx_desc, 1535 struct sk_buff *skb) 1536 { 1537 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1538 bool encap_pkt = false; 1539 1540 skb_checksum_none_assert(skb); 1541 1542 /* Rx csum disabled */ 1543 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1544 return; 1545 1546 /* check for VXLAN and Geneve packets */ 1547 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1548 encap_pkt = true; 1549 skb->encapsulation = 1; 1550 } 1551 1552 /* if IP and error */ 1553 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1554 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1555 ring->rx_stats.csum_err++; 1556 return; 1557 } 1558 1559 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1560 return; 1561 1562 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1563 /* 1564 * 82599 errata, UDP frames with a 0 checksum can be marked as 1565 * checksum errors. 1566 */ 1567 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1568 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1569 return; 1570 1571 ring->rx_stats.csum_err++; 1572 return; 1573 } 1574 1575 /* It must be a TCP or UDP packet with a valid checksum */ 1576 skb->ip_summed = CHECKSUM_UNNECESSARY; 1577 if (encap_pkt) { 1578 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1579 return; 1580 1581 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1582 skb->ip_summed = CHECKSUM_NONE; 1583 return; 1584 } 1585 /* If we checked the outer header let the stack know */ 1586 skb->csum_level = 1; 1587 } 1588 } 1589 1590 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1591 { 1592 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1593 } 1594 1595 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1596 struct ixgbe_rx_buffer *bi) 1597 { 1598 struct page *page = bi->page; 1599 dma_addr_t dma; 1600 1601 /* since we are recycling buffers we should seldom need to alloc */ 1602 if (likely(page)) 1603 return true; 1604 1605 /* alloc new page for storage */ 1606 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1607 if (unlikely(!page)) { 1608 rx_ring->rx_stats.alloc_rx_page_failed++; 1609 return false; 1610 } 1611 1612 /* map page for use */ 1613 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1614 ixgbe_rx_pg_size(rx_ring), 1615 DMA_FROM_DEVICE, 1616 IXGBE_RX_DMA_ATTR); 1617 1618 /* 1619 * if mapping failed free memory back to system since 1620 * there isn't much point in holding memory we can't use 1621 */ 1622 if (dma_mapping_error(rx_ring->dev, dma)) { 1623 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1624 1625 rx_ring->rx_stats.alloc_rx_page_failed++; 1626 return false; 1627 } 1628 1629 bi->dma = dma; 1630 bi->page = page; 1631 bi->page_offset = ixgbe_rx_offset(rx_ring); 1632 page_ref_add(page, USHRT_MAX - 1); 1633 bi->pagecnt_bias = USHRT_MAX; 1634 rx_ring->rx_stats.alloc_rx_page++; 1635 1636 return true; 1637 } 1638 1639 /** 1640 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1641 * @rx_ring: ring to place buffers on 1642 * @cleaned_count: number of buffers to replace 1643 **/ 1644 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1645 { 1646 union ixgbe_adv_rx_desc *rx_desc; 1647 struct ixgbe_rx_buffer *bi; 1648 u16 i = rx_ring->next_to_use; 1649 u16 bufsz; 1650 1651 /* nothing to do */ 1652 if (!cleaned_count) 1653 return; 1654 1655 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1656 bi = &rx_ring->rx_buffer_info[i]; 1657 i -= rx_ring->count; 1658 1659 bufsz = ixgbe_rx_bufsz(rx_ring); 1660 1661 do { 1662 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1663 break; 1664 1665 /* sync the buffer for use by the device */ 1666 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1667 bi->page_offset, bufsz, 1668 DMA_FROM_DEVICE); 1669 1670 /* 1671 * Refresh the desc even if buffer_addrs didn't change 1672 * because each write-back erases this info. 1673 */ 1674 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1675 1676 rx_desc++; 1677 bi++; 1678 i++; 1679 if (unlikely(!i)) { 1680 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1681 bi = rx_ring->rx_buffer_info; 1682 i -= rx_ring->count; 1683 } 1684 1685 /* clear the length for the next_to_use descriptor */ 1686 rx_desc->wb.upper.length = 0; 1687 1688 cleaned_count--; 1689 } while (cleaned_count); 1690 1691 i += rx_ring->count; 1692 1693 if (rx_ring->next_to_use != i) { 1694 rx_ring->next_to_use = i; 1695 1696 /* update next to alloc since we have filled the ring */ 1697 rx_ring->next_to_alloc = i; 1698 1699 /* Force memory writes to complete before letting h/w 1700 * know there are new descriptors to fetch. (Only 1701 * applicable for weak-ordered memory model archs, 1702 * such as IA-64). 1703 */ 1704 wmb(); 1705 writel(i, rx_ring->tail); 1706 } 1707 } 1708 1709 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1710 struct sk_buff *skb) 1711 { 1712 u16 hdr_len = skb_headlen(skb); 1713 1714 /* set gso_size to avoid messing up TCP MSS */ 1715 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1716 IXGBE_CB(skb)->append_cnt); 1717 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1718 } 1719 1720 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1721 struct sk_buff *skb) 1722 { 1723 /* if append_cnt is 0 then frame is not RSC */ 1724 if (!IXGBE_CB(skb)->append_cnt) 1725 return; 1726 1727 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1728 rx_ring->rx_stats.rsc_flush++; 1729 1730 ixgbe_set_rsc_gso_size(rx_ring, skb); 1731 1732 /* gso_size is computed using append_cnt so always clear it last */ 1733 IXGBE_CB(skb)->append_cnt = 0; 1734 } 1735 1736 /** 1737 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1738 * @rx_ring: rx descriptor ring packet is being transacted on 1739 * @rx_desc: pointer to the EOP Rx descriptor 1740 * @skb: pointer to current skb being populated 1741 * 1742 * This function checks the ring, descriptor, and packet information in 1743 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1744 * other fields within the skb. 1745 **/ 1746 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1747 union ixgbe_adv_rx_desc *rx_desc, 1748 struct sk_buff *skb) 1749 { 1750 struct net_device *dev = rx_ring->netdev; 1751 u32 flags = rx_ring->q_vector->adapter->flags; 1752 1753 ixgbe_update_rsc_stats(rx_ring, skb); 1754 1755 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1756 1757 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1758 1759 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1760 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1761 1762 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1763 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1764 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1765 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1766 } 1767 1768 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1769 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1770 1771 skb->protocol = eth_type_trans(skb, dev); 1772 1773 /* record Rx queue, or update MACVLAN statistics */ 1774 if (netif_is_ixgbe(dev)) 1775 skb_record_rx_queue(skb, rx_ring->queue_index); 1776 else 1777 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1778 (skb->pkt_type == PACKET_BROADCAST) || 1779 (skb->pkt_type == PACKET_MULTICAST)); 1780 } 1781 1782 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1783 struct sk_buff *skb) 1784 { 1785 napi_gro_receive(&q_vector->napi, skb); 1786 } 1787 1788 /** 1789 * ixgbe_is_non_eop - process handling of non-EOP buffers 1790 * @rx_ring: Rx ring being processed 1791 * @rx_desc: Rx descriptor for current buffer 1792 * @skb: Current socket buffer containing buffer in progress 1793 * 1794 * This function updates next to clean. If the buffer is an EOP buffer 1795 * this function exits returning false, otherwise it will place the 1796 * sk_buff in the next buffer to be chained and return true indicating 1797 * that this is in fact a non-EOP buffer. 1798 **/ 1799 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1800 union ixgbe_adv_rx_desc *rx_desc, 1801 struct sk_buff *skb) 1802 { 1803 u32 ntc = rx_ring->next_to_clean + 1; 1804 1805 /* fetch, update, and store next to clean */ 1806 ntc = (ntc < rx_ring->count) ? ntc : 0; 1807 rx_ring->next_to_clean = ntc; 1808 1809 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1810 1811 /* update RSC append count if present */ 1812 if (ring_is_rsc_enabled(rx_ring)) { 1813 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1814 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1815 1816 if (unlikely(rsc_enabled)) { 1817 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1818 1819 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1820 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1821 1822 /* update ntc based on RSC value */ 1823 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1824 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1825 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1826 } 1827 } 1828 1829 /* if we are the last buffer then there is nothing else to do */ 1830 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1831 return false; 1832 1833 /* place skb in next buffer to be received */ 1834 rx_ring->rx_buffer_info[ntc].skb = skb; 1835 rx_ring->rx_stats.non_eop_descs++; 1836 1837 return true; 1838 } 1839 1840 /** 1841 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1842 * @rx_ring: rx descriptor ring packet is being transacted on 1843 * @skb: pointer to current skb being adjusted 1844 * 1845 * This function is an ixgbe specific version of __pskb_pull_tail. The 1846 * main difference between this version and the original function is that 1847 * this function can make several assumptions about the state of things 1848 * that allow for significant optimizations versus the standard function. 1849 * As a result we can do things like drop a frag and maintain an accurate 1850 * truesize for the skb. 1851 */ 1852 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1853 struct sk_buff *skb) 1854 { 1855 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1856 unsigned char *va; 1857 unsigned int pull_len; 1858 1859 /* 1860 * it is valid to use page_address instead of kmap since we are 1861 * working with pages allocated out of the lomem pool per 1862 * alloc_page(GFP_ATOMIC) 1863 */ 1864 va = skb_frag_address(frag); 1865 1866 /* 1867 * we need the header to contain the greater of either ETH_HLEN or 1868 * 60 bytes if the skb->len is less than 60 for skb_pad. 1869 */ 1870 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1871 1872 /* align pull length to size of long to optimize memcpy performance */ 1873 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1874 1875 /* update all of the pointers */ 1876 skb_frag_size_sub(frag, pull_len); 1877 frag->page_offset += pull_len; 1878 skb->data_len -= pull_len; 1879 skb->tail += pull_len; 1880 } 1881 1882 /** 1883 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1884 * @rx_ring: rx descriptor ring packet is being transacted on 1885 * @skb: pointer to current skb being updated 1886 * 1887 * This function provides a basic DMA sync up for the first fragment of an 1888 * skb. The reason for doing this is that the first fragment cannot be 1889 * unmapped until we have reached the end of packet descriptor for a buffer 1890 * chain. 1891 */ 1892 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1893 struct sk_buff *skb) 1894 { 1895 /* if the page was released unmap it, else just sync our portion */ 1896 if (unlikely(IXGBE_CB(skb)->page_released)) { 1897 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1898 ixgbe_rx_pg_size(rx_ring), 1899 DMA_FROM_DEVICE, 1900 IXGBE_RX_DMA_ATTR); 1901 } else if (ring_uses_build_skb(rx_ring)) { 1902 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1903 1904 dma_sync_single_range_for_cpu(rx_ring->dev, 1905 IXGBE_CB(skb)->dma, 1906 offset, 1907 skb_headlen(skb), 1908 DMA_FROM_DEVICE); 1909 } else { 1910 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1911 1912 dma_sync_single_range_for_cpu(rx_ring->dev, 1913 IXGBE_CB(skb)->dma, 1914 frag->page_offset, 1915 skb_frag_size(frag), 1916 DMA_FROM_DEVICE); 1917 } 1918 } 1919 1920 /** 1921 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1922 * @rx_ring: rx descriptor ring packet is being transacted on 1923 * @rx_desc: pointer to the EOP Rx descriptor 1924 * @skb: pointer to current skb being fixed 1925 * 1926 * Check if the skb is valid in the XDP case it will be an error pointer. 1927 * Return true in this case to abort processing and advance to next 1928 * descriptor. 1929 * 1930 * Check for corrupted packet headers caused by senders on the local L2 1931 * embedded NIC switch not setting up their Tx Descriptors right. These 1932 * should be very rare. 1933 * 1934 * Also address the case where we are pulling data in on pages only 1935 * and as such no data is present in the skb header. 1936 * 1937 * In addition if skb is not at least 60 bytes we need to pad it so that 1938 * it is large enough to qualify as a valid Ethernet frame. 1939 * 1940 * Returns true if an error was encountered and skb was freed. 1941 **/ 1942 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1943 union ixgbe_adv_rx_desc *rx_desc, 1944 struct sk_buff *skb) 1945 { 1946 struct net_device *netdev = rx_ring->netdev; 1947 1948 /* XDP packets use error pointer so abort at this point */ 1949 if (IS_ERR(skb)) 1950 return true; 1951 1952 /* Verify netdev is present, and that packet does not have any 1953 * errors that would be unacceptable to the netdev. 1954 */ 1955 if (!netdev || 1956 (unlikely(ixgbe_test_staterr(rx_desc, 1957 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1958 !(netdev->features & NETIF_F_RXALL)))) { 1959 dev_kfree_skb_any(skb); 1960 return true; 1961 } 1962 1963 /* place header in linear portion of buffer */ 1964 if (!skb_headlen(skb)) 1965 ixgbe_pull_tail(rx_ring, skb); 1966 1967 #ifdef IXGBE_FCOE 1968 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1969 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1970 return false; 1971 1972 #endif 1973 /* if eth_skb_pad returns an error the skb was freed */ 1974 if (eth_skb_pad(skb)) 1975 return true; 1976 1977 return false; 1978 } 1979 1980 /** 1981 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1982 * @rx_ring: rx descriptor ring to store buffers on 1983 * @old_buff: donor buffer to have page reused 1984 * 1985 * Synchronizes page for reuse by the adapter 1986 **/ 1987 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1988 struct ixgbe_rx_buffer *old_buff) 1989 { 1990 struct ixgbe_rx_buffer *new_buff; 1991 u16 nta = rx_ring->next_to_alloc; 1992 1993 new_buff = &rx_ring->rx_buffer_info[nta]; 1994 1995 /* update, and store next to alloc */ 1996 nta++; 1997 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1998 1999 /* Transfer page from old buffer to new buffer. 2000 * Move each member individually to avoid possible store 2001 * forwarding stalls and unnecessary copy of skb. 2002 */ 2003 new_buff->dma = old_buff->dma; 2004 new_buff->page = old_buff->page; 2005 new_buff->page_offset = old_buff->page_offset; 2006 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 2007 } 2008 2009 static inline bool ixgbe_page_is_reserved(struct page *page) 2010 { 2011 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 2012 } 2013 2014 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 2015 { 2016 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 2017 struct page *page = rx_buffer->page; 2018 2019 /* avoid re-using remote pages */ 2020 if (unlikely(ixgbe_page_is_reserved(page))) 2021 return false; 2022 2023 #if (PAGE_SIZE < 8192) 2024 /* if we are only owner of page we can reuse it */ 2025 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 2026 return false; 2027 #else 2028 /* The last offset is a bit aggressive in that we assume the 2029 * worst case of FCoE being enabled and using a 3K buffer. 2030 * However this should have minimal impact as the 1K extra is 2031 * still less than one buffer in size. 2032 */ 2033 #define IXGBE_LAST_OFFSET \ 2034 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2035 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2036 return false; 2037 #endif 2038 2039 /* If we have drained the page fragment pool we need to update 2040 * the pagecnt_bias and page count so that we fully restock the 2041 * number of references the driver holds. 2042 */ 2043 if (unlikely(pagecnt_bias == 1)) { 2044 page_ref_add(page, USHRT_MAX - 1); 2045 rx_buffer->pagecnt_bias = USHRT_MAX; 2046 } 2047 2048 return true; 2049 } 2050 2051 /** 2052 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2053 * @rx_ring: rx descriptor ring to transact packets on 2054 * @rx_buffer: buffer containing page to add 2055 * @skb: sk_buff to place the data into 2056 * @size: size of data in rx_buffer 2057 * 2058 * This function will add the data contained in rx_buffer->page to the skb. 2059 * This is done either through a direct copy if the data in the buffer is 2060 * less than the skb header size, otherwise it will just attach the page as 2061 * a frag to the skb. 2062 * 2063 * The function will then update the page offset if necessary and return 2064 * true if the buffer can be reused by the adapter. 2065 **/ 2066 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2067 struct ixgbe_rx_buffer *rx_buffer, 2068 struct sk_buff *skb, 2069 unsigned int size) 2070 { 2071 #if (PAGE_SIZE < 8192) 2072 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2073 #else 2074 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2075 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2076 SKB_DATA_ALIGN(size); 2077 #endif 2078 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2079 rx_buffer->page_offset, size, truesize); 2080 #if (PAGE_SIZE < 8192) 2081 rx_buffer->page_offset ^= truesize; 2082 #else 2083 rx_buffer->page_offset += truesize; 2084 #endif 2085 } 2086 2087 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2088 union ixgbe_adv_rx_desc *rx_desc, 2089 struct sk_buff **skb, 2090 const unsigned int size) 2091 { 2092 struct ixgbe_rx_buffer *rx_buffer; 2093 2094 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2095 prefetchw(rx_buffer->page); 2096 *skb = rx_buffer->skb; 2097 2098 /* Delay unmapping of the first packet. It carries the header 2099 * information, HW may still access the header after the writeback. 2100 * Only unmap it when EOP is reached 2101 */ 2102 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2103 if (!*skb) 2104 goto skip_sync; 2105 } else { 2106 if (*skb) 2107 ixgbe_dma_sync_frag(rx_ring, *skb); 2108 } 2109 2110 /* we are reusing so sync this buffer for CPU use */ 2111 dma_sync_single_range_for_cpu(rx_ring->dev, 2112 rx_buffer->dma, 2113 rx_buffer->page_offset, 2114 size, 2115 DMA_FROM_DEVICE); 2116 skip_sync: 2117 rx_buffer->pagecnt_bias--; 2118 2119 return rx_buffer; 2120 } 2121 2122 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2123 struct ixgbe_rx_buffer *rx_buffer, 2124 struct sk_buff *skb) 2125 { 2126 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2127 /* hand second half of page back to the ring */ 2128 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2129 } else { 2130 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2131 /* the page has been released from the ring */ 2132 IXGBE_CB(skb)->page_released = true; 2133 } else { 2134 /* we are not reusing the buffer so unmap it */ 2135 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2136 ixgbe_rx_pg_size(rx_ring), 2137 DMA_FROM_DEVICE, 2138 IXGBE_RX_DMA_ATTR); 2139 } 2140 __page_frag_cache_drain(rx_buffer->page, 2141 rx_buffer->pagecnt_bias); 2142 } 2143 2144 /* clear contents of rx_buffer */ 2145 rx_buffer->page = NULL; 2146 rx_buffer->skb = NULL; 2147 } 2148 2149 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2150 struct ixgbe_rx_buffer *rx_buffer, 2151 struct xdp_buff *xdp, 2152 union ixgbe_adv_rx_desc *rx_desc) 2153 { 2154 unsigned int size = xdp->data_end - xdp->data; 2155 #if (PAGE_SIZE < 8192) 2156 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2157 #else 2158 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2159 xdp->data_hard_start); 2160 #endif 2161 struct sk_buff *skb; 2162 2163 /* prefetch first cache line of first page */ 2164 prefetch(xdp->data); 2165 #if L1_CACHE_BYTES < 128 2166 prefetch(xdp->data + L1_CACHE_BYTES); 2167 #endif 2168 /* Note, we get here by enabling legacy-rx via: 2169 * 2170 * ethtool --set-priv-flags <dev> legacy-rx on 2171 * 2172 * In this mode, we currently get 0 extra XDP headroom as 2173 * opposed to having legacy-rx off, where we process XDP 2174 * packets going to stack via ixgbe_build_skb(). The latter 2175 * provides us currently with 192 bytes of headroom. 2176 * 2177 * For ixgbe_construct_skb() mode it means that the 2178 * xdp->data_meta will always point to xdp->data, since 2179 * the helper cannot expand the head. Should this ever 2180 * change in future for legacy-rx mode on, then lets also 2181 * add xdp->data_meta handling here. 2182 */ 2183 2184 /* allocate a skb to store the frags */ 2185 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2186 if (unlikely(!skb)) 2187 return NULL; 2188 2189 if (size > IXGBE_RX_HDR_SIZE) { 2190 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2191 IXGBE_CB(skb)->dma = rx_buffer->dma; 2192 2193 skb_add_rx_frag(skb, 0, rx_buffer->page, 2194 xdp->data - page_address(rx_buffer->page), 2195 size, truesize); 2196 #if (PAGE_SIZE < 8192) 2197 rx_buffer->page_offset ^= truesize; 2198 #else 2199 rx_buffer->page_offset += truesize; 2200 #endif 2201 } else { 2202 memcpy(__skb_put(skb, size), 2203 xdp->data, ALIGN(size, sizeof(long))); 2204 rx_buffer->pagecnt_bias++; 2205 } 2206 2207 return skb; 2208 } 2209 2210 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2211 struct ixgbe_rx_buffer *rx_buffer, 2212 struct xdp_buff *xdp, 2213 union ixgbe_adv_rx_desc *rx_desc) 2214 { 2215 unsigned int metasize = xdp->data - xdp->data_meta; 2216 #if (PAGE_SIZE < 8192) 2217 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2218 #else 2219 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2220 SKB_DATA_ALIGN(xdp->data_end - 2221 xdp->data_hard_start); 2222 #endif 2223 struct sk_buff *skb; 2224 2225 /* Prefetch first cache line of first page. If xdp->data_meta 2226 * is unused, this points extactly as xdp->data, otherwise we 2227 * likely have a consumer accessing first few bytes of meta 2228 * data, and then actual data. 2229 */ 2230 prefetch(xdp->data_meta); 2231 #if L1_CACHE_BYTES < 128 2232 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2233 #endif 2234 2235 /* build an skb to around the page buffer */ 2236 skb = build_skb(xdp->data_hard_start, truesize); 2237 if (unlikely(!skb)) 2238 return NULL; 2239 2240 /* update pointers within the skb to store the data */ 2241 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2242 __skb_put(skb, xdp->data_end - xdp->data); 2243 if (metasize) 2244 skb_metadata_set(skb, metasize); 2245 2246 /* record DMA address if this is the start of a chain of buffers */ 2247 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2248 IXGBE_CB(skb)->dma = rx_buffer->dma; 2249 2250 /* update buffer offset */ 2251 #if (PAGE_SIZE < 8192) 2252 rx_buffer->page_offset ^= truesize; 2253 #else 2254 rx_buffer->page_offset += truesize; 2255 #endif 2256 2257 return skb; 2258 } 2259 2260 #define IXGBE_XDP_PASS 0 2261 #define IXGBE_XDP_CONSUMED 1 2262 #define IXGBE_XDP_TX 2 2263 2264 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2265 struct xdp_frame *xdpf); 2266 2267 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2268 struct ixgbe_ring *rx_ring, 2269 struct xdp_buff *xdp) 2270 { 2271 int err, result = IXGBE_XDP_PASS; 2272 struct bpf_prog *xdp_prog; 2273 struct xdp_frame *xdpf; 2274 u32 act; 2275 2276 rcu_read_lock(); 2277 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2278 2279 if (!xdp_prog) 2280 goto xdp_out; 2281 2282 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2283 2284 act = bpf_prog_run_xdp(xdp_prog, xdp); 2285 switch (act) { 2286 case XDP_PASS: 2287 break; 2288 case XDP_TX: 2289 xdpf = convert_to_xdp_frame(xdp); 2290 if (unlikely(!xdpf)) { 2291 result = IXGBE_XDP_CONSUMED; 2292 break; 2293 } 2294 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2295 break; 2296 case XDP_REDIRECT: 2297 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2298 if (!err) 2299 result = IXGBE_XDP_TX; 2300 else 2301 result = IXGBE_XDP_CONSUMED; 2302 break; 2303 default: 2304 bpf_warn_invalid_xdp_action(act); 2305 /* fallthrough */ 2306 case XDP_ABORTED: 2307 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2308 /* fallthrough -- handle aborts by dropping packet */ 2309 case XDP_DROP: 2310 result = IXGBE_XDP_CONSUMED; 2311 break; 2312 } 2313 xdp_out: 2314 rcu_read_unlock(); 2315 return ERR_PTR(-result); 2316 } 2317 2318 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2319 struct ixgbe_rx_buffer *rx_buffer, 2320 unsigned int size) 2321 { 2322 #if (PAGE_SIZE < 8192) 2323 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2324 2325 rx_buffer->page_offset ^= truesize; 2326 #else 2327 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2328 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2329 SKB_DATA_ALIGN(size); 2330 2331 rx_buffer->page_offset += truesize; 2332 #endif 2333 } 2334 2335 /** 2336 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2337 * @q_vector: structure containing interrupt and ring information 2338 * @rx_ring: rx descriptor ring to transact packets on 2339 * @budget: Total limit on number of packets to process 2340 * 2341 * This function provides a "bounce buffer" approach to Rx interrupt 2342 * processing. The advantage to this is that on systems that have 2343 * expensive overhead for IOMMU access this provides a means of avoiding 2344 * it by maintaining the mapping of the page to the syste. 2345 * 2346 * Returns amount of work completed 2347 **/ 2348 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2349 struct ixgbe_ring *rx_ring, 2350 const int budget) 2351 { 2352 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2353 struct ixgbe_adapter *adapter = q_vector->adapter; 2354 #ifdef IXGBE_FCOE 2355 int ddp_bytes; 2356 unsigned int mss = 0; 2357 #endif /* IXGBE_FCOE */ 2358 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2359 bool xdp_xmit = false; 2360 struct xdp_buff xdp; 2361 2362 xdp.rxq = &rx_ring->xdp_rxq; 2363 2364 while (likely(total_rx_packets < budget)) { 2365 union ixgbe_adv_rx_desc *rx_desc; 2366 struct ixgbe_rx_buffer *rx_buffer; 2367 struct sk_buff *skb; 2368 unsigned int size; 2369 2370 /* return some buffers to hardware, one at a time is too slow */ 2371 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2372 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2373 cleaned_count = 0; 2374 } 2375 2376 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2377 size = le16_to_cpu(rx_desc->wb.upper.length); 2378 if (!size) 2379 break; 2380 2381 /* This memory barrier is needed to keep us from reading 2382 * any other fields out of the rx_desc until we know the 2383 * descriptor has been written back 2384 */ 2385 dma_rmb(); 2386 2387 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2388 2389 /* retrieve a buffer from the ring */ 2390 if (!skb) { 2391 xdp.data = page_address(rx_buffer->page) + 2392 rx_buffer->page_offset; 2393 xdp.data_meta = xdp.data; 2394 xdp.data_hard_start = xdp.data - 2395 ixgbe_rx_offset(rx_ring); 2396 xdp.data_end = xdp.data + size; 2397 2398 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2399 } 2400 2401 if (IS_ERR(skb)) { 2402 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2403 xdp_xmit = true; 2404 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2405 } else { 2406 rx_buffer->pagecnt_bias++; 2407 } 2408 total_rx_packets++; 2409 total_rx_bytes += size; 2410 } else if (skb) { 2411 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2412 } else if (ring_uses_build_skb(rx_ring)) { 2413 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2414 &xdp, rx_desc); 2415 } else { 2416 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2417 &xdp, rx_desc); 2418 } 2419 2420 /* exit if we failed to retrieve a buffer */ 2421 if (!skb) { 2422 rx_ring->rx_stats.alloc_rx_buff_failed++; 2423 rx_buffer->pagecnt_bias++; 2424 break; 2425 } 2426 2427 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2428 cleaned_count++; 2429 2430 /* place incomplete frames back on ring for completion */ 2431 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2432 continue; 2433 2434 /* verify the packet layout is correct */ 2435 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2436 continue; 2437 2438 /* probably a little skewed due to removing CRC */ 2439 total_rx_bytes += skb->len; 2440 2441 /* populate checksum, timestamp, VLAN, and protocol */ 2442 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2443 2444 #ifdef IXGBE_FCOE 2445 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2446 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2447 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2448 /* include DDPed FCoE data */ 2449 if (ddp_bytes > 0) { 2450 if (!mss) { 2451 mss = rx_ring->netdev->mtu - 2452 sizeof(struct fcoe_hdr) - 2453 sizeof(struct fc_frame_header) - 2454 sizeof(struct fcoe_crc_eof); 2455 if (mss > 512) 2456 mss &= ~511; 2457 } 2458 total_rx_bytes += ddp_bytes; 2459 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2460 mss); 2461 } 2462 if (!ddp_bytes) { 2463 dev_kfree_skb_any(skb); 2464 continue; 2465 } 2466 } 2467 2468 #endif /* IXGBE_FCOE */ 2469 ixgbe_rx_skb(q_vector, skb); 2470 2471 /* update budget accounting */ 2472 total_rx_packets++; 2473 } 2474 2475 if (xdp_xmit) { 2476 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2477 2478 /* Force memory writes to complete before letting h/w 2479 * know there are new descriptors to fetch. 2480 */ 2481 wmb(); 2482 writel(ring->next_to_use, ring->tail); 2483 2484 xdp_do_flush_map(); 2485 } 2486 2487 u64_stats_update_begin(&rx_ring->syncp); 2488 rx_ring->stats.packets += total_rx_packets; 2489 rx_ring->stats.bytes += total_rx_bytes; 2490 u64_stats_update_end(&rx_ring->syncp); 2491 q_vector->rx.total_packets += total_rx_packets; 2492 q_vector->rx.total_bytes += total_rx_bytes; 2493 2494 return total_rx_packets; 2495 } 2496 2497 /** 2498 * ixgbe_configure_msix - Configure MSI-X hardware 2499 * @adapter: board private structure 2500 * 2501 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2502 * interrupts. 2503 **/ 2504 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2505 { 2506 struct ixgbe_q_vector *q_vector; 2507 int v_idx; 2508 u32 mask; 2509 2510 /* Populate MSIX to EITR Select */ 2511 if (adapter->num_vfs > 32) { 2512 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2513 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2514 } 2515 2516 /* 2517 * Populate the IVAR table and set the ITR values to the 2518 * corresponding register. 2519 */ 2520 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2521 struct ixgbe_ring *ring; 2522 q_vector = adapter->q_vector[v_idx]; 2523 2524 ixgbe_for_each_ring(ring, q_vector->rx) 2525 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2526 2527 ixgbe_for_each_ring(ring, q_vector->tx) 2528 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2529 2530 ixgbe_write_eitr(q_vector); 2531 } 2532 2533 switch (adapter->hw.mac.type) { 2534 case ixgbe_mac_82598EB: 2535 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2536 v_idx); 2537 break; 2538 case ixgbe_mac_82599EB: 2539 case ixgbe_mac_X540: 2540 case ixgbe_mac_X550: 2541 case ixgbe_mac_X550EM_x: 2542 case ixgbe_mac_x550em_a: 2543 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2544 break; 2545 default: 2546 break; 2547 } 2548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2549 2550 /* set up to autoclear timer, and the vectors */ 2551 mask = IXGBE_EIMS_ENABLE_MASK; 2552 mask &= ~(IXGBE_EIMS_OTHER | 2553 IXGBE_EIMS_MAILBOX | 2554 IXGBE_EIMS_LSC); 2555 2556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2557 } 2558 2559 /** 2560 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2561 * @q_vector: structure containing interrupt and ring information 2562 * @ring_container: structure containing ring performance data 2563 * 2564 * Stores a new ITR value based on packets and byte 2565 * counts during the last interrupt. The advantage of per interrupt 2566 * computation is faster updates and more accurate ITR for the current 2567 * traffic pattern. Constants in this function were computed 2568 * based on theoretical maximum wire speed and thresholds were set based 2569 * on testing data as well as attempting to minimize response time 2570 * while increasing bulk throughput. 2571 **/ 2572 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2573 struct ixgbe_ring_container *ring_container) 2574 { 2575 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2576 IXGBE_ITR_ADAPTIVE_LATENCY; 2577 unsigned int avg_wire_size, packets, bytes; 2578 unsigned long next_update = jiffies; 2579 2580 /* If we don't have any rings just leave ourselves set for maximum 2581 * possible latency so we take ourselves out of the equation. 2582 */ 2583 if (!ring_container->ring) 2584 return; 2585 2586 /* If we didn't update within up to 1 - 2 jiffies we can assume 2587 * that either packets are coming in so slow there hasn't been 2588 * any work, or that there is so much work that NAPI is dealing 2589 * with interrupt moderation and we don't need to do anything. 2590 */ 2591 if (time_after(next_update, ring_container->next_update)) 2592 goto clear_counts; 2593 2594 packets = ring_container->total_packets; 2595 2596 /* We have no packets to actually measure against. This means 2597 * either one of the other queues on this vector is active or 2598 * we are a Tx queue doing TSO with too high of an interrupt rate. 2599 * 2600 * When this occurs just tick up our delay by the minimum value 2601 * and hope that this extra delay will prevent us from being called 2602 * without any work on our queue. 2603 */ 2604 if (!packets) { 2605 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2606 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2607 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2608 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2609 goto clear_counts; 2610 } 2611 2612 bytes = ring_container->total_bytes; 2613 2614 /* If packets are less than 4 or bytes are less than 9000 assume 2615 * insufficient data to use bulk rate limiting approach. We are 2616 * likely latency driven. 2617 */ 2618 if (packets < 4 && bytes < 9000) { 2619 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2620 goto adjust_by_size; 2621 } 2622 2623 /* Between 4 and 48 we can assume that our current interrupt delay 2624 * is only slightly too low. As such we should increase it by a small 2625 * fixed amount. 2626 */ 2627 if (packets < 48) { 2628 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2629 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2630 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2631 goto clear_counts; 2632 } 2633 2634 /* Between 48 and 96 is our "goldilocks" zone where we are working 2635 * out "just right". Just report that our current ITR is good for us. 2636 */ 2637 if (packets < 96) { 2638 itr = q_vector->itr >> 2; 2639 goto clear_counts; 2640 } 2641 2642 /* If packet count is 96 or greater we are likely looking at a slight 2643 * overrun of the delay we want. Try halving our delay to see if that 2644 * will cut the number of packets in half per interrupt. 2645 */ 2646 if (packets < 256) { 2647 itr = q_vector->itr >> 3; 2648 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2649 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2650 goto clear_counts; 2651 } 2652 2653 /* The paths below assume we are dealing with a bulk ITR since number 2654 * of packets is 256 or greater. We are just going to have to compute 2655 * a value and try to bring the count under control, though for smaller 2656 * packet sizes there isn't much we can do as NAPI polling will likely 2657 * be kicking in sooner rather than later. 2658 */ 2659 itr = IXGBE_ITR_ADAPTIVE_BULK; 2660 2661 adjust_by_size: 2662 /* If packet counts are 256 or greater we can assume we have a gross 2663 * overestimation of what the rate should be. Instead of trying to fine 2664 * tune it just use the formula below to try and dial in an exact value 2665 * give the current packet size of the frame. 2666 */ 2667 avg_wire_size = bytes / packets; 2668 2669 /* The following is a crude approximation of: 2670 * wmem_default / (size + overhead) = desired_pkts_per_int 2671 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2672 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2673 * 2674 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2675 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2676 * formula down to 2677 * 2678 * (170 * (size + 24)) / (size + 640) = ITR 2679 * 2680 * We first do some math on the packet size and then finally bitshift 2681 * by 8 after rounding up. We also have to account for PCIe link speed 2682 * difference as ITR scales based on this. 2683 */ 2684 if (avg_wire_size <= 60) { 2685 /* Start at 50k ints/sec */ 2686 avg_wire_size = 5120; 2687 } else if (avg_wire_size <= 316) { 2688 /* 50K ints/sec to 16K ints/sec */ 2689 avg_wire_size *= 40; 2690 avg_wire_size += 2720; 2691 } else if (avg_wire_size <= 1084) { 2692 /* 16K ints/sec to 9.2K ints/sec */ 2693 avg_wire_size *= 15; 2694 avg_wire_size += 11452; 2695 } else if (avg_wire_size <= 1980) { 2696 /* 9.2K ints/sec to 8K ints/sec */ 2697 avg_wire_size *= 5; 2698 avg_wire_size += 22420; 2699 } else { 2700 /* plateau at a limit of 8K ints/sec */ 2701 avg_wire_size = 32256; 2702 } 2703 2704 /* If we are in low latency mode half our delay which doubles the rate 2705 * to somewhere between 100K to 16K ints/sec 2706 */ 2707 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2708 avg_wire_size >>= 1; 2709 2710 /* Resultant value is 256 times larger than it needs to be. This 2711 * gives us room to adjust the value as needed to either increase 2712 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2713 * 2714 * Use addition as we have already recorded the new latency flag 2715 * for the ITR value. 2716 */ 2717 switch (q_vector->adapter->link_speed) { 2718 case IXGBE_LINK_SPEED_10GB_FULL: 2719 case IXGBE_LINK_SPEED_100_FULL: 2720 default: 2721 itr += DIV_ROUND_UP(avg_wire_size, 2722 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2723 IXGBE_ITR_ADAPTIVE_MIN_INC; 2724 break; 2725 case IXGBE_LINK_SPEED_2_5GB_FULL: 2726 case IXGBE_LINK_SPEED_1GB_FULL: 2727 case IXGBE_LINK_SPEED_10_FULL: 2728 itr += DIV_ROUND_UP(avg_wire_size, 2729 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2730 IXGBE_ITR_ADAPTIVE_MIN_INC; 2731 break; 2732 } 2733 2734 clear_counts: 2735 /* write back value */ 2736 ring_container->itr = itr; 2737 2738 /* next update should occur within next jiffy */ 2739 ring_container->next_update = next_update + 1; 2740 2741 ring_container->total_bytes = 0; 2742 ring_container->total_packets = 0; 2743 } 2744 2745 /** 2746 * ixgbe_write_eitr - write EITR register in hardware specific way 2747 * @q_vector: structure containing interrupt and ring information 2748 * 2749 * This function is made to be called by ethtool and by the driver 2750 * when it needs to update EITR registers at runtime. Hardware 2751 * specific quirks/differences are taken care of here. 2752 */ 2753 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2754 { 2755 struct ixgbe_adapter *adapter = q_vector->adapter; 2756 struct ixgbe_hw *hw = &adapter->hw; 2757 int v_idx = q_vector->v_idx; 2758 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2759 2760 switch (adapter->hw.mac.type) { 2761 case ixgbe_mac_82598EB: 2762 /* must write high and low 16 bits to reset counter */ 2763 itr_reg |= (itr_reg << 16); 2764 break; 2765 case ixgbe_mac_82599EB: 2766 case ixgbe_mac_X540: 2767 case ixgbe_mac_X550: 2768 case ixgbe_mac_X550EM_x: 2769 case ixgbe_mac_x550em_a: 2770 /* 2771 * set the WDIS bit to not clear the timer bits and cause an 2772 * immediate assertion of the interrupt 2773 */ 2774 itr_reg |= IXGBE_EITR_CNT_WDIS; 2775 break; 2776 default: 2777 break; 2778 } 2779 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2780 } 2781 2782 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2783 { 2784 u32 new_itr; 2785 2786 ixgbe_update_itr(q_vector, &q_vector->tx); 2787 ixgbe_update_itr(q_vector, &q_vector->rx); 2788 2789 /* use the smallest value of new ITR delay calculations */ 2790 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2791 2792 /* Clear latency flag if set, shift into correct position */ 2793 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2794 new_itr <<= 2; 2795 2796 if (new_itr != q_vector->itr) { 2797 /* save the algorithm value here */ 2798 q_vector->itr = new_itr; 2799 2800 ixgbe_write_eitr(q_vector); 2801 } 2802 } 2803 2804 /** 2805 * ixgbe_check_overtemp_subtask - check for over temperature 2806 * @adapter: pointer to adapter 2807 **/ 2808 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2809 { 2810 struct ixgbe_hw *hw = &adapter->hw; 2811 u32 eicr = adapter->interrupt_event; 2812 s32 rc; 2813 2814 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2815 return; 2816 2817 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2818 return; 2819 2820 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2821 2822 switch (hw->device_id) { 2823 case IXGBE_DEV_ID_82599_T3_LOM: 2824 /* 2825 * Since the warning interrupt is for both ports 2826 * we don't have to check if: 2827 * - This interrupt wasn't for our port. 2828 * - We may have missed the interrupt so always have to 2829 * check if we got a LSC 2830 */ 2831 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2832 !(eicr & IXGBE_EICR_LSC)) 2833 return; 2834 2835 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2836 u32 speed; 2837 bool link_up = false; 2838 2839 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2840 2841 if (link_up) 2842 return; 2843 } 2844 2845 /* Check if this is not due to overtemp */ 2846 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2847 return; 2848 2849 break; 2850 case IXGBE_DEV_ID_X550EM_A_1G_T: 2851 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2852 rc = hw->phy.ops.check_overtemp(hw); 2853 if (rc != IXGBE_ERR_OVERTEMP) 2854 return; 2855 break; 2856 default: 2857 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2858 return; 2859 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2860 return; 2861 break; 2862 } 2863 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2864 2865 adapter->interrupt_event = 0; 2866 } 2867 2868 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2869 { 2870 struct ixgbe_hw *hw = &adapter->hw; 2871 2872 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2873 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2874 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2875 /* write to clear the interrupt */ 2876 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2877 } 2878 } 2879 2880 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2881 { 2882 struct ixgbe_hw *hw = &adapter->hw; 2883 2884 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2885 return; 2886 2887 switch (adapter->hw.mac.type) { 2888 case ixgbe_mac_82599EB: 2889 /* 2890 * Need to check link state so complete overtemp check 2891 * on service task 2892 */ 2893 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2894 (eicr & IXGBE_EICR_LSC)) && 2895 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2896 adapter->interrupt_event = eicr; 2897 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2898 ixgbe_service_event_schedule(adapter); 2899 return; 2900 } 2901 return; 2902 case ixgbe_mac_x550em_a: 2903 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2904 adapter->interrupt_event = eicr; 2905 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2906 ixgbe_service_event_schedule(adapter); 2907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2908 IXGBE_EICR_GPI_SDP0_X550EM_a); 2909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2910 IXGBE_EICR_GPI_SDP0_X550EM_a); 2911 } 2912 return; 2913 case ixgbe_mac_X550: 2914 case ixgbe_mac_X540: 2915 if (!(eicr & IXGBE_EICR_TS)) 2916 return; 2917 break; 2918 default: 2919 return; 2920 } 2921 2922 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2923 } 2924 2925 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2926 { 2927 switch (hw->mac.type) { 2928 case ixgbe_mac_82598EB: 2929 if (hw->phy.type == ixgbe_phy_nl) 2930 return true; 2931 return false; 2932 case ixgbe_mac_82599EB: 2933 case ixgbe_mac_X550EM_x: 2934 case ixgbe_mac_x550em_a: 2935 switch (hw->mac.ops.get_media_type(hw)) { 2936 case ixgbe_media_type_fiber: 2937 case ixgbe_media_type_fiber_qsfp: 2938 return true; 2939 default: 2940 return false; 2941 } 2942 default: 2943 return false; 2944 } 2945 } 2946 2947 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2948 { 2949 struct ixgbe_hw *hw = &adapter->hw; 2950 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2951 2952 if (!ixgbe_is_sfp(hw)) 2953 return; 2954 2955 /* Later MAC's use different SDP */ 2956 if (hw->mac.type >= ixgbe_mac_X540) 2957 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2958 2959 if (eicr & eicr_mask) { 2960 /* Clear the interrupt */ 2961 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2962 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2963 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2964 adapter->sfp_poll_time = 0; 2965 ixgbe_service_event_schedule(adapter); 2966 } 2967 } 2968 2969 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2970 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2971 /* Clear the interrupt */ 2972 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2973 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2974 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2975 ixgbe_service_event_schedule(adapter); 2976 } 2977 } 2978 } 2979 2980 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2981 { 2982 struct ixgbe_hw *hw = &adapter->hw; 2983 2984 adapter->lsc_int++; 2985 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2986 adapter->link_check_timeout = jiffies; 2987 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2988 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2989 IXGBE_WRITE_FLUSH(hw); 2990 ixgbe_service_event_schedule(adapter); 2991 } 2992 } 2993 2994 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2995 u64 qmask) 2996 { 2997 u32 mask; 2998 struct ixgbe_hw *hw = &adapter->hw; 2999 3000 switch (hw->mac.type) { 3001 case ixgbe_mac_82598EB: 3002 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3003 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3004 break; 3005 case ixgbe_mac_82599EB: 3006 case ixgbe_mac_X540: 3007 case ixgbe_mac_X550: 3008 case ixgbe_mac_X550EM_x: 3009 case ixgbe_mac_x550em_a: 3010 mask = (qmask & 0xFFFFFFFF); 3011 if (mask) 3012 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3013 mask = (qmask >> 32); 3014 if (mask) 3015 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3016 break; 3017 default: 3018 break; 3019 } 3020 /* skip the flush */ 3021 } 3022 3023 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 3024 u64 qmask) 3025 { 3026 u32 mask; 3027 struct ixgbe_hw *hw = &adapter->hw; 3028 3029 switch (hw->mac.type) { 3030 case ixgbe_mac_82598EB: 3031 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3032 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3033 break; 3034 case ixgbe_mac_82599EB: 3035 case ixgbe_mac_X540: 3036 case ixgbe_mac_X550: 3037 case ixgbe_mac_X550EM_x: 3038 case ixgbe_mac_x550em_a: 3039 mask = (qmask & 0xFFFFFFFF); 3040 if (mask) 3041 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3042 mask = (qmask >> 32); 3043 if (mask) 3044 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3045 break; 3046 default: 3047 break; 3048 } 3049 /* skip the flush */ 3050 } 3051 3052 /** 3053 * ixgbe_irq_enable - Enable default interrupt generation settings 3054 * @adapter: board private structure 3055 * @queues: enable irqs for queues 3056 * @flush: flush register write 3057 **/ 3058 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3059 bool flush) 3060 { 3061 struct ixgbe_hw *hw = &adapter->hw; 3062 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3063 3064 /* don't reenable LSC while waiting for link */ 3065 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3066 mask &= ~IXGBE_EIMS_LSC; 3067 3068 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3069 switch (adapter->hw.mac.type) { 3070 case ixgbe_mac_82599EB: 3071 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3072 break; 3073 case ixgbe_mac_X540: 3074 case ixgbe_mac_X550: 3075 case ixgbe_mac_X550EM_x: 3076 case ixgbe_mac_x550em_a: 3077 mask |= IXGBE_EIMS_TS; 3078 break; 3079 default: 3080 break; 3081 } 3082 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3083 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3084 switch (adapter->hw.mac.type) { 3085 case ixgbe_mac_82599EB: 3086 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3087 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3088 /* fall through */ 3089 case ixgbe_mac_X540: 3090 case ixgbe_mac_X550: 3091 case ixgbe_mac_X550EM_x: 3092 case ixgbe_mac_x550em_a: 3093 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3094 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3095 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3096 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3097 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3098 mask |= IXGBE_EICR_GPI_SDP0_X540; 3099 mask |= IXGBE_EIMS_ECC; 3100 mask |= IXGBE_EIMS_MAILBOX; 3101 break; 3102 default: 3103 break; 3104 } 3105 3106 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3107 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3108 mask |= IXGBE_EIMS_FLOW_DIR; 3109 3110 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3111 if (queues) 3112 ixgbe_irq_enable_queues(adapter, ~0); 3113 if (flush) 3114 IXGBE_WRITE_FLUSH(&adapter->hw); 3115 } 3116 3117 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3118 { 3119 struct ixgbe_adapter *adapter = data; 3120 struct ixgbe_hw *hw = &adapter->hw; 3121 u32 eicr; 3122 3123 /* 3124 * Workaround for Silicon errata. Use clear-by-write instead 3125 * of clear-by-read. Reading with EICS will return the 3126 * interrupt causes without clearing, which later be done 3127 * with the write to EICR. 3128 */ 3129 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3130 3131 /* The lower 16bits of the EICR register are for the queue interrupts 3132 * which should be masked here in order to not accidentally clear them if 3133 * the bits are high when ixgbe_msix_other is called. There is a race 3134 * condition otherwise which results in possible performance loss 3135 * especially if the ixgbe_msix_other interrupt is triggering 3136 * consistently (as it would when PPS is turned on for the X540 device) 3137 */ 3138 eicr &= 0xFFFF0000; 3139 3140 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3141 3142 if (eicr & IXGBE_EICR_LSC) 3143 ixgbe_check_lsc(adapter); 3144 3145 if (eicr & IXGBE_EICR_MAILBOX) 3146 ixgbe_msg_task(adapter); 3147 3148 switch (hw->mac.type) { 3149 case ixgbe_mac_82599EB: 3150 case ixgbe_mac_X540: 3151 case ixgbe_mac_X550: 3152 case ixgbe_mac_X550EM_x: 3153 case ixgbe_mac_x550em_a: 3154 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3155 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3156 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3157 ixgbe_service_event_schedule(adapter); 3158 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3159 IXGBE_EICR_GPI_SDP0_X540); 3160 } 3161 if (eicr & IXGBE_EICR_ECC) { 3162 e_info(link, "Received ECC Err, initiating reset\n"); 3163 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3164 ixgbe_service_event_schedule(adapter); 3165 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3166 } 3167 /* Handle Flow Director Full threshold interrupt */ 3168 if (eicr & IXGBE_EICR_FLOW_DIR) { 3169 int reinit_count = 0; 3170 int i; 3171 for (i = 0; i < adapter->num_tx_queues; i++) { 3172 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3173 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3174 &ring->state)) 3175 reinit_count++; 3176 } 3177 if (reinit_count) { 3178 /* no more flow director interrupts until after init */ 3179 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3180 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3181 ixgbe_service_event_schedule(adapter); 3182 } 3183 } 3184 ixgbe_check_sfp_event(adapter, eicr); 3185 ixgbe_check_overtemp_event(adapter, eicr); 3186 break; 3187 default: 3188 break; 3189 } 3190 3191 ixgbe_check_fan_failure(adapter, eicr); 3192 3193 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3194 ixgbe_ptp_check_pps_event(adapter); 3195 3196 /* re-enable the original interrupt state, no lsc, no queues */ 3197 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3198 ixgbe_irq_enable(adapter, false, false); 3199 3200 return IRQ_HANDLED; 3201 } 3202 3203 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3204 { 3205 struct ixgbe_q_vector *q_vector = data; 3206 3207 /* EIAM disabled interrupts (on this vector) for us */ 3208 3209 if (q_vector->rx.ring || q_vector->tx.ring) 3210 napi_schedule_irqoff(&q_vector->napi); 3211 3212 return IRQ_HANDLED; 3213 } 3214 3215 /** 3216 * ixgbe_poll - NAPI Rx polling callback 3217 * @napi: structure for representing this polling device 3218 * @budget: how many packets driver is allowed to clean 3219 * 3220 * This function is used for legacy and MSI, NAPI mode 3221 **/ 3222 int ixgbe_poll(struct napi_struct *napi, int budget) 3223 { 3224 struct ixgbe_q_vector *q_vector = 3225 container_of(napi, struct ixgbe_q_vector, napi); 3226 struct ixgbe_adapter *adapter = q_vector->adapter; 3227 struct ixgbe_ring *ring; 3228 int per_ring_budget, work_done = 0; 3229 bool clean_complete = true; 3230 3231 #ifdef CONFIG_IXGBE_DCA 3232 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3233 ixgbe_update_dca(q_vector); 3234 #endif 3235 3236 ixgbe_for_each_ring(ring, q_vector->tx) { 3237 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3238 clean_complete = false; 3239 } 3240 3241 /* Exit if we are called by netpoll */ 3242 if (budget <= 0) 3243 return budget; 3244 3245 /* attempt to distribute budget to each queue fairly, but don't allow 3246 * the budget to go below 1 because we'll exit polling */ 3247 if (q_vector->rx.count > 1) 3248 per_ring_budget = max(budget/q_vector->rx.count, 1); 3249 else 3250 per_ring_budget = budget; 3251 3252 ixgbe_for_each_ring(ring, q_vector->rx) { 3253 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3254 per_ring_budget); 3255 3256 work_done += cleaned; 3257 if (cleaned >= per_ring_budget) 3258 clean_complete = false; 3259 } 3260 3261 /* If all work not completed, return budget and keep polling */ 3262 if (!clean_complete) 3263 return budget; 3264 3265 /* all work done, exit the polling mode */ 3266 napi_complete_done(napi, work_done); 3267 if (adapter->rx_itr_setting & 1) 3268 ixgbe_set_itr(q_vector); 3269 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3270 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3271 3272 return min(work_done, budget - 1); 3273 } 3274 3275 /** 3276 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3277 * @adapter: board private structure 3278 * 3279 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3280 * interrupts from the kernel. 3281 **/ 3282 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3283 { 3284 struct net_device *netdev = adapter->netdev; 3285 unsigned int ri = 0, ti = 0; 3286 int vector, err; 3287 3288 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3289 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3290 struct msix_entry *entry = &adapter->msix_entries[vector]; 3291 3292 if (q_vector->tx.ring && q_vector->rx.ring) { 3293 snprintf(q_vector->name, sizeof(q_vector->name), 3294 "%s-TxRx-%u", netdev->name, ri++); 3295 ti++; 3296 } else if (q_vector->rx.ring) { 3297 snprintf(q_vector->name, sizeof(q_vector->name), 3298 "%s-rx-%u", netdev->name, ri++); 3299 } else if (q_vector->tx.ring) { 3300 snprintf(q_vector->name, sizeof(q_vector->name), 3301 "%s-tx-%u", netdev->name, ti++); 3302 } else { 3303 /* skip this unused q_vector */ 3304 continue; 3305 } 3306 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3307 q_vector->name, q_vector); 3308 if (err) { 3309 e_err(probe, "request_irq failed for MSIX interrupt " 3310 "Error: %d\n", err); 3311 goto free_queue_irqs; 3312 } 3313 /* If Flow Director is enabled, set interrupt affinity */ 3314 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3315 /* assign the mask for this irq */ 3316 irq_set_affinity_hint(entry->vector, 3317 &q_vector->affinity_mask); 3318 } 3319 } 3320 3321 err = request_irq(adapter->msix_entries[vector].vector, 3322 ixgbe_msix_other, 0, netdev->name, adapter); 3323 if (err) { 3324 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3325 goto free_queue_irqs; 3326 } 3327 3328 return 0; 3329 3330 free_queue_irqs: 3331 while (vector) { 3332 vector--; 3333 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3334 NULL); 3335 free_irq(adapter->msix_entries[vector].vector, 3336 adapter->q_vector[vector]); 3337 } 3338 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3339 pci_disable_msix(adapter->pdev); 3340 kfree(adapter->msix_entries); 3341 adapter->msix_entries = NULL; 3342 return err; 3343 } 3344 3345 /** 3346 * ixgbe_intr - legacy mode Interrupt Handler 3347 * @irq: interrupt number 3348 * @data: pointer to a network interface device structure 3349 **/ 3350 static irqreturn_t ixgbe_intr(int irq, void *data) 3351 { 3352 struct ixgbe_adapter *adapter = data; 3353 struct ixgbe_hw *hw = &adapter->hw; 3354 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3355 u32 eicr; 3356 3357 /* 3358 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3359 * before the read of EICR. 3360 */ 3361 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3362 3363 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3364 * therefore no explicit interrupt disable is necessary */ 3365 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3366 if (!eicr) { 3367 /* 3368 * shared interrupt alert! 3369 * make sure interrupts are enabled because the read will 3370 * have disabled interrupts due to EIAM 3371 * finish the workaround of silicon errata on 82598. Unmask 3372 * the interrupt that we masked before the EICR read. 3373 */ 3374 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3375 ixgbe_irq_enable(adapter, true, true); 3376 return IRQ_NONE; /* Not our interrupt */ 3377 } 3378 3379 if (eicr & IXGBE_EICR_LSC) 3380 ixgbe_check_lsc(adapter); 3381 3382 switch (hw->mac.type) { 3383 case ixgbe_mac_82599EB: 3384 ixgbe_check_sfp_event(adapter, eicr); 3385 /* Fall through */ 3386 case ixgbe_mac_X540: 3387 case ixgbe_mac_X550: 3388 case ixgbe_mac_X550EM_x: 3389 case ixgbe_mac_x550em_a: 3390 if (eicr & IXGBE_EICR_ECC) { 3391 e_info(link, "Received ECC Err, initiating reset\n"); 3392 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3393 ixgbe_service_event_schedule(adapter); 3394 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3395 } 3396 ixgbe_check_overtemp_event(adapter, eicr); 3397 break; 3398 default: 3399 break; 3400 } 3401 3402 ixgbe_check_fan_failure(adapter, eicr); 3403 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3404 ixgbe_ptp_check_pps_event(adapter); 3405 3406 /* would disable interrupts here but EIAM disabled it */ 3407 napi_schedule_irqoff(&q_vector->napi); 3408 3409 /* 3410 * re-enable link(maybe) and non-queue interrupts, no flush. 3411 * ixgbe_poll will re-enable the queue interrupts 3412 */ 3413 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3414 ixgbe_irq_enable(adapter, false, false); 3415 3416 return IRQ_HANDLED; 3417 } 3418 3419 /** 3420 * ixgbe_request_irq - initialize interrupts 3421 * @adapter: board private structure 3422 * 3423 * Attempts to configure interrupts using the best available 3424 * capabilities of the hardware and kernel. 3425 **/ 3426 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3427 { 3428 struct net_device *netdev = adapter->netdev; 3429 int err; 3430 3431 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3432 err = ixgbe_request_msix_irqs(adapter); 3433 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3434 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3435 netdev->name, adapter); 3436 else 3437 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3438 netdev->name, adapter); 3439 3440 if (err) 3441 e_err(probe, "request_irq failed, Error %d\n", err); 3442 3443 return err; 3444 } 3445 3446 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3447 { 3448 int vector; 3449 3450 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3451 free_irq(adapter->pdev->irq, adapter); 3452 return; 3453 } 3454 3455 if (!adapter->msix_entries) 3456 return; 3457 3458 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3459 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3460 struct msix_entry *entry = &adapter->msix_entries[vector]; 3461 3462 /* free only the irqs that were actually requested */ 3463 if (!q_vector->rx.ring && !q_vector->tx.ring) 3464 continue; 3465 3466 /* clear the affinity_mask in the IRQ descriptor */ 3467 irq_set_affinity_hint(entry->vector, NULL); 3468 3469 free_irq(entry->vector, q_vector); 3470 } 3471 3472 free_irq(adapter->msix_entries[vector].vector, adapter); 3473 } 3474 3475 /** 3476 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3477 * @adapter: board private structure 3478 **/ 3479 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3480 { 3481 switch (adapter->hw.mac.type) { 3482 case ixgbe_mac_82598EB: 3483 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3484 break; 3485 case ixgbe_mac_82599EB: 3486 case ixgbe_mac_X540: 3487 case ixgbe_mac_X550: 3488 case ixgbe_mac_X550EM_x: 3489 case ixgbe_mac_x550em_a: 3490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3491 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3492 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3493 break; 3494 default: 3495 break; 3496 } 3497 IXGBE_WRITE_FLUSH(&adapter->hw); 3498 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3499 int vector; 3500 3501 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3502 synchronize_irq(adapter->msix_entries[vector].vector); 3503 3504 synchronize_irq(adapter->msix_entries[vector++].vector); 3505 } else { 3506 synchronize_irq(adapter->pdev->irq); 3507 } 3508 } 3509 3510 /** 3511 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3512 * @adapter: board private structure 3513 * 3514 **/ 3515 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3516 { 3517 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3518 3519 ixgbe_write_eitr(q_vector); 3520 3521 ixgbe_set_ivar(adapter, 0, 0, 0); 3522 ixgbe_set_ivar(adapter, 1, 0, 0); 3523 3524 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3525 } 3526 3527 /** 3528 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3529 * @adapter: board private structure 3530 * @ring: structure containing ring specific data 3531 * 3532 * Configure the Tx descriptor ring after a reset. 3533 **/ 3534 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3535 struct ixgbe_ring *ring) 3536 { 3537 struct ixgbe_hw *hw = &adapter->hw; 3538 u64 tdba = ring->dma; 3539 int wait_loop = 10; 3540 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3541 u8 reg_idx = ring->reg_idx; 3542 3543 /* disable queue to avoid issues while updating state */ 3544 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3545 IXGBE_WRITE_FLUSH(hw); 3546 3547 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3548 (tdba & DMA_BIT_MASK(32))); 3549 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3550 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3551 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3552 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3553 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3554 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3555 3556 /* 3557 * set WTHRESH to encourage burst writeback, it should not be set 3558 * higher than 1 when: 3559 * - ITR is 0 as it could cause false TX hangs 3560 * - ITR is set to > 100k int/sec and BQL is enabled 3561 * 3562 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3563 * to or less than the number of on chip descriptors, which is 3564 * currently 40. 3565 */ 3566 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3567 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3568 else 3569 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3570 3571 /* 3572 * Setting PTHRESH to 32 both improves performance 3573 * and avoids a TX hang with DFP enabled 3574 */ 3575 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3576 32; /* PTHRESH = 32 */ 3577 3578 /* reinitialize flowdirector state */ 3579 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3580 ring->atr_sample_rate = adapter->atr_sample_rate; 3581 ring->atr_count = 0; 3582 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3583 } else { 3584 ring->atr_sample_rate = 0; 3585 } 3586 3587 /* initialize XPS */ 3588 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3589 struct ixgbe_q_vector *q_vector = ring->q_vector; 3590 3591 if (q_vector) 3592 netif_set_xps_queue(ring->netdev, 3593 &q_vector->affinity_mask, 3594 ring->queue_index); 3595 } 3596 3597 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3598 3599 /* reinitialize tx_buffer_info */ 3600 memset(ring->tx_buffer_info, 0, 3601 sizeof(struct ixgbe_tx_buffer) * ring->count); 3602 3603 /* enable queue */ 3604 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3605 3606 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3607 if (hw->mac.type == ixgbe_mac_82598EB && 3608 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3609 return; 3610 3611 /* poll to verify queue is enabled */ 3612 do { 3613 usleep_range(1000, 2000); 3614 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3615 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3616 if (!wait_loop) 3617 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3618 } 3619 3620 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3621 { 3622 struct ixgbe_hw *hw = &adapter->hw; 3623 u32 rttdcs, mtqc; 3624 u8 tcs = adapter->hw_tcs; 3625 3626 if (hw->mac.type == ixgbe_mac_82598EB) 3627 return; 3628 3629 /* disable the arbiter while setting MTQC */ 3630 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3631 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3632 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3633 3634 /* set transmit pool layout */ 3635 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3636 mtqc = IXGBE_MTQC_VT_ENA; 3637 if (tcs > 4) 3638 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3639 else if (tcs > 1) 3640 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3641 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3642 IXGBE_82599_VMDQ_4Q_MASK) 3643 mtqc |= IXGBE_MTQC_32VF; 3644 else 3645 mtqc |= IXGBE_MTQC_64VF; 3646 } else { 3647 if (tcs > 4) 3648 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3649 else if (tcs > 1) 3650 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3651 else 3652 mtqc = IXGBE_MTQC_64Q_1PB; 3653 } 3654 3655 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3656 3657 /* Enable Security TX Buffer IFG for multiple pb */ 3658 if (tcs) { 3659 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3660 sectx |= IXGBE_SECTX_DCB; 3661 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3662 } 3663 3664 /* re-enable the arbiter */ 3665 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3666 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3667 } 3668 3669 /** 3670 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3671 * @adapter: board private structure 3672 * 3673 * Configure the Tx unit of the MAC after a reset. 3674 **/ 3675 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3676 { 3677 struct ixgbe_hw *hw = &adapter->hw; 3678 u32 dmatxctl; 3679 u32 i; 3680 3681 ixgbe_setup_mtqc(adapter); 3682 3683 if (hw->mac.type != ixgbe_mac_82598EB) { 3684 /* DMATXCTL.EN must be before Tx queues are enabled */ 3685 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3686 dmatxctl |= IXGBE_DMATXCTL_TE; 3687 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3688 } 3689 3690 /* Setup the HW Tx Head and Tail descriptor pointers */ 3691 for (i = 0; i < adapter->num_tx_queues; i++) 3692 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3693 for (i = 0; i < adapter->num_xdp_queues; i++) 3694 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3695 } 3696 3697 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3698 struct ixgbe_ring *ring) 3699 { 3700 struct ixgbe_hw *hw = &adapter->hw; 3701 u8 reg_idx = ring->reg_idx; 3702 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3703 3704 srrctl |= IXGBE_SRRCTL_DROP_EN; 3705 3706 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3707 } 3708 3709 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3710 struct ixgbe_ring *ring) 3711 { 3712 struct ixgbe_hw *hw = &adapter->hw; 3713 u8 reg_idx = ring->reg_idx; 3714 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3715 3716 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3717 3718 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3719 } 3720 3721 #ifdef CONFIG_IXGBE_DCB 3722 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3723 #else 3724 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3725 #endif 3726 { 3727 int i; 3728 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3729 3730 if (adapter->ixgbe_ieee_pfc) 3731 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3732 3733 /* 3734 * We should set the drop enable bit if: 3735 * SR-IOV is enabled 3736 * or 3737 * Number of Rx queues > 1 and flow control is disabled 3738 * 3739 * This allows us to avoid head of line blocking for security 3740 * and performance reasons. 3741 */ 3742 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3743 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3744 for (i = 0; i < adapter->num_rx_queues; i++) 3745 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3746 } else { 3747 for (i = 0; i < adapter->num_rx_queues; i++) 3748 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3749 } 3750 } 3751 3752 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3753 3754 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3755 struct ixgbe_ring *rx_ring) 3756 { 3757 struct ixgbe_hw *hw = &adapter->hw; 3758 u32 srrctl; 3759 u8 reg_idx = rx_ring->reg_idx; 3760 3761 if (hw->mac.type == ixgbe_mac_82598EB) { 3762 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3763 3764 /* 3765 * if VMDq is not active we must program one srrctl register 3766 * per RSS queue since we have enabled RDRXCTL.MVMEN 3767 */ 3768 reg_idx &= mask; 3769 } 3770 3771 /* configure header buffer length, needed for RSC */ 3772 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3773 3774 /* configure the packet buffer length */ 3775 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3776 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3777 else 3778 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3779 3780 /* configure descriptor type */ 3781 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3782 3783 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3784 } 3785 3786 /** 3787 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3788 * @adapter: device handle 3789 * 3790 * - 82598/82599/X540: 128 3791 * - X550(non-SRIOV mode): 512 3792 * - X550(SRIOV mode): 64 3793 */ 3794 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3795 { 3796 if (adapter->hw.mac.type < ixgbe_mac_X550) 3797 return 128; 3798 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3799 return 64; 3800 else 3801 return 512; 3802 } 3803 3804 /** 3805 * ixgbe_store_key - Write the RSS key to HW 3806 * @adapter: device handle 3807 * 3808 * Write the RSS key stored in adapter.rss_key to HW. 3809 */ 3810 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3811 { 3812 struct ixgbe_hw *hw = &adapter->hw; 3813 int i; 3814 3815 for (i = 0; i < 10; i++) 3816 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3817 } 3818 3819 /** 3820 * ixgbe_init_rss_key - Initialize adapter RSS key 3821 * @adapter: device handle 3822 * 3823 * Allocates and initializes the RSS key if it is not allocated. 3824 **/ 3825 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3826 { 3827 u32 *rss_key; 3828 3829 if (!adapter->rss_key) { 3830 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3831 if (unlikely(!rss_key)) 3832 return -ENOMEM; 3833 3834 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3835 adapter->rss_key = rss_key; 3836 } 3837 3838 return 0; 3839 } 3840 3841 /** 3842 * ixgbe_store_reta - Write the RETA table to HW 3843 * @adapter: device handle 3844 * 3845 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3846 */ 3847 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3848 { 3849 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3850 struct ixgbe_hw *hw = &adapter->hw; 3851 u32 reta = 0; 3852 u32 indices_multi; 3853 u8 *indir_tbl = adapter->rss_indir_tbl; 3854 3855 /* Fill out the redirection table as follows: 3856 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3857 * indices. 3858 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3859 * - X550: 8 bit wide entries containing 6 bit RSS index 3860 */ 3861 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3862 indices_multi = 0x11; 3863 else 3864 indices_multi = 0x1; 3865 3866 /* Write redirection table to HW */ 3867 for (i = 0; i < reta_entries; i++) { 3868 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3869 if ((i & 3) == 3) { 3870 if (i < 128) 3871 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3872 else 3873 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3874 reta); 3875 reta = 0; 3876 } 3877 } 3878 } 3879 3880 /** 3881 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3882 * @adapter: device handle 3883 * 3884 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3885 */ 3886 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3887 { 3888 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3889 struct ixgbe_hw *hw = &adapter->hw; 3890 u32 vfreta = 0; 3891 3892 /* Write redirection table to HW */ 3893 for (i = 0; i < reta_entries; i++) { 3894 u16 pool = adapter->num_rx_pools; 3895 3896 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3897 if ((i & 3) != 3) 3898 continue; 3899 3900 while (pool--) 3901 IXGBE_WRITE_REG(hw, 3902 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3903 vfreta); 3904 vfreta = 0; 3905 } 3906 } 3907 3908 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3909 { 3910 u32 i, j; 3911 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3912 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3913 3914 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3915 * make full use of any rings they may have. We will use the 3916 * PSRTYPE register to control how many rings we use within the PF. 3917 */ 3918 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3919 rss_i = 4; 3920 3921 /* Fill out hash function seeds */ 3922 ixgbe_store_key(adapter); 3923 3924 /* Fill out redirection table */ 3925 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3926 3927 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3928 if (j == rss_i) 3929 j = 0; 3930 3931 adapter->rss_indir_tbl[i] = j; 3932 } 3933 3934 ixgbe_store_reta(adapter); 3935 } 3936 3937 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3938 { 3939 struct ixgbe_hw *hw = &adapter->hw; 3940 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3941 int i, j; 3942 3943 /* Fill out hash function seeds */ 3944 for (i = 0; i < 10; i++) { 3945 u16 pool = adapter->num_rx_pools; 3946 3947 while (pool--) 3948 IXGBE_WRITE_REG(hw, 3949 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3950 *(adapter->rss_key + i)); 3951 } 3952 3953 /* Fill out the redirection table */ 3954 for (i = 0, j = 0; i < 64; i++, j++) { 3955 if (j == rss_i) 3956 j = 0; 3957 3958 adapter->rss_indir_tbl[i] = j; 3959 } 3960 3961 ixgbe_store_vfreta(adapter); 3962 } 3963 3964 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3965 { 3966 struct ixgbe_hw *hw = &adapter->hw; 3967 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3968 u32 rxcsum; 3969 3970 /* Disable indicating checksum in descriptor, enables RSS hash */ 3971 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3972 rxcsum |= IXGBE_RXCSUM_PCSD; 3973 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3974 3975 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3976 if (adapter->ring_feature[RING_F_RSS].mask) 3977 mrqc = IXGBE_MRQC_RSSEN; 3978 } else { 3979 u8 tcs = adapter->hw_tcs; 3980 3981 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3982 if (tcs > 4) 3983 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3984 else if (tcs > 1) 3985 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3986 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3987 IXGBE_82599_VMDQ_4Q_MASK) 3988 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3989 else 3990 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3991 3992 /* Enable L3/L4 for Tx Switched packets */ 3993 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3994 } else { 3995 if (tcs > 4) 3996 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3997 else if (tcs > 1) 3998 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3999 else 4000 mrqc = IXGBE_MRQC_RSSEN; 4001 } 4002 } 4003 4004 /* Perform hash on these packet types */ 4005 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 4006 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 4007 IXGBE_MRQC_RSS_FIELD_IPV6 | 4008 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 4009 4010 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 4011 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 4012 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 4013 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 4014 4015 if ((hw->mac.type >= ixgbe_mac_X550) && 4016 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 4017 u16 pool = adapter->num_rx_pools; 4018 4019 /* Enable VF RSS mode */ 4020 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 4021 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4022 4023 /* Setup RSS through the VF registers */ 4024 ixgbe_setup_vfreta(adapter); 4025 vfmrqc = IXGBE_MRQC_RSSEN; 4026 vfmrqc |= rss_field; 4027 4028 while (pool--) 4029 IXGBE_WRITE_REG(hw, 4030 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4031 vfmrqc); 4032 } else { 4033 ixgbe_setup_reta(adapter); 4034 mrqc |= rss_field; 4035 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4036 } 4037 } 4038 4039 /** 4040 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4041 * @adapter: address of board private structure 4042 * @ring: structure containing ring specific data 4043 **/ 4044 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4045 struct ixgbe_ring *ring) 4046 { 4047 struct ixgbe_hw *hw = &adapter->hw; 4048 u32 rscctrl; 4049 u8 reg_idx = ring->reg_idx; 4050 4051 if (!ring_is_rsc_enabled(ring)) 4052 return; 4053 4054 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4055 rscctrl |= IXGBE_RSCCTL_RSCEN; 4056 /* 4057 * we must limit the number of descriptors so that the 4058 * total size of max desc * buf_len is not greater 4059 * than 65536 4060 */ 4061 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4062 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4063 } 4064 4065 #define IXGBE_MAX_RX_DESC_POLL 10 4066 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4067 struct ixgbe_ring *ring) 4068 { 4069 struct ixgbe_hw *hw = &adapter->hw; 4070 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4071 u32 rxdctl; 4072 u8 reg_idx = ring->reg_idx; 4073 4074 if (ixgbe_removed(hw->hw_addr)) 4075 return; 4076 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4077 if (hw->mac.type == ixgbe_mac_82598EB && 4078 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4079 return; 4080 4081 do { 4082 usleep_range(1000, 2000); 4083 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4084 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4085 4086 if (!wait_loop) { 4087 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4088 "the polling period\n", reg_idx); 4089 } 4090 } 4091 4092 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 4093 struct ixgbe_ring *ring) 4094 { 4095 struct ixgbe_hw *hw = &adapter->hw; 4096 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4097 u32 rxdctl; 4098 u8 reg_idx = ring->reg_idx; 4099 4100 if (ixgbe_removed(hw->hw_addr)) 4101 return; 4102 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4103 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4104 4105 /* write value back with RXDCTL.ENABLE bit cleared */ 4106 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4107 4108 if (hw->mac.type == ixgbe_mac_82598EB && 4109 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4110 return; 4111 4112 /* the hardware may take up to 100us to really disable the rx queue */ 4113 do { 4114 udelay(10); 4115 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4116 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 4117 4118 if (!wait_loop) { 4119 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 4120 "the polling period\n", reg_idx); 4121 } 4122 } 4123 4124 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4125 struct ixgbe_ring *ring) 4126 { 4127 struct ixgbe_hw *hw = &adapter->hw; 4128 union ixgbe_adv_rx_desc *rx_desc; 4129 u64 rdba = ring->dma; 4130 u32 rxdctl; 4131 u8 reg_idx = ring->reg_idx; 4132 4133 /* disable queue to avoid issues while updating state */ 4134 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4135 ixgbe_disable_rx_queue(adapter, ring); 4136 4137 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4138 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4139 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4140 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4141 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4142 IXGBE_WRITE_FLUSH(hw); 4143 4144 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4145 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4146 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4147 4148 ixgbe_configure_srrctl(adapter, ring); 4149 ixgbe_configure_rscctl(adapter, ring); 4150 4151 if (hw->mac.type == ixgbe_mac_82598EB) { 4152 /* 4153 * enable cache line friendly hardware writes: 4154 * PTHRESH=32 descriptors (half the internal cache), 4155 * this also removes ugly rx_no_buffer_count increment 4156 * HTHRESH=4 descriptors (to minimize latency on fetch) 4157 * WTHRESH=8 burst writeback up to two cache lines 4158 */ 4159 rxdctl &= ~0x3FFFFF; 4160 rxdctl |= 0x080420; 4161 #if (PAGE_SIZE < 8192) 4162 /* RXDCTL.RLPML does not work on 82599 */ 4163 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4164 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4165 IXGBE_RXDCTL_RLPML_EN); 4166 4167 /* Limit the maximum frame size so we don't overrun the skb. 4168 * This can happen in SRIOV mode when the MTU of the VF is 4169 * higher than the MTU of the PF. 4170 */ 4171 if (ring_uses_build_skb(ring) && 4172 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4173 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4174 IXGBE_RXDCTL_RLPML_EN; 4175 #endif 4176 } 4177 4178 /* initialize rx_buffer_info */ 4179 memset(ring->rx_buffer_info, 0, 4180 sizeof(struct ixgbe_rx_buffer) * ring->count); 4181 4182 /* initialize Rx descriptor 0 */ 4183 rx_desc = IXGBE_RX_DESC(ring, 0); 4184 rx_desc->wb.upper.length = 0; 4185 4186 /* enable receive descriptor ring */ 4187 rxdctl |= IXGBE_RXDCTL_ENABLE; 4188 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4189 4190 ixgbe_rx_desc_queue_enable(adapter, ring); 4191 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4192 } 4193 4194 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4195 { 4196 struct ixgbe_hw *hw = &adapter->hw; 4197 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4198 u16 pool = adapter->num_rx_pools; 4199 4200 /* PSRTYPE must be initialized in non 82598 adapters */ 4201 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4202 IXGBE_PSRTYPE_UDPHDR | 4203 IXGBE_PSRTYPE_IPV4HDR | 4204 IXGBE_PSRTYPE_L2HDR | 4205 IXGBE_PSRTYPE_IPV6HDR; 4206 4207 if (hw->mac.type == ixgbe_mac_82598EB) 4208 return; 4209 4210 if (rss_i > 3) 4211 psrtype |= 2u << 29; 4212 else if (rss_i > 1) 4213 psrtype |= 1u << 29; 4214 4215 while (pool--) 4216 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4217 } 4218 4219 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4220 { 4221 struct ixgbe_hw *hw = &adapter->hw; 4222 u32 reg_offset, vf_shift; 4223 u32 gcr_ext, vmdctl; 4224 int i; 4225 4226 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4227 return; 4228 4229 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4230 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4231 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4232 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4233 vmdctl |= IXGBE_VT_CTL_REPLEN; 4234 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4235 4236 vf_shift = VMDQ_P(0) % 32; 4237 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4238 4239 /* Enable only the PF's pool for Tx/Rx */ 4240 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4241 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4242 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4243 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4244 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4245 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4246 4247 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4248 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4249 4250 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4251 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4252 4253 /* 4254 * Set up VF register offsets for selected VT Mode, 4255 * i.e. 32 or 64 VFs for SR-IOV 4256 */ 4257 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4258 case IXGBE_82599_VMDQ_8Q_MASK: 4259 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4260 break; 4261 case IXGBE_82599_VMDQ_4Q_MASK: 4262 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4263 break; 4264 default: 4265 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4266 break; 4267 } 4268 4269 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4270 4271 for (i = 0; i < adapter->num_vfs; i++) { 4272 /* configure spoof checking */ 4273 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4274 adapter->vfinfo[i].spoofchk_enabled); 4275 4276 /* Enable/Disable RSS query feature */ 4277 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4278 adapter->vfinfo[i].rss_query_enabled); 4279 } 4280 } 4281 4282 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4283 { 4284 struct ixgbe_hw *hw = &adapter->hw; 4285 struct net_device *netdev = adapter->netdev; 4286 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4287 struct ixgbe_ring *rx_ring; 4288 int i; 4289 u32 mhadd, hlreg0; 4290 4291 #ifdef IXGBE_FCOE 4292 /* adjust max frame to be able to do baby jumbo for FCoE */ 4293 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4294 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4295 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4296 4297 #endif /* IXGBE_FCOE */ 4298 4299 /* adjust max frame to be at least the size of a standard frame */ 4300 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4301 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4302 4303 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4304 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4305 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4306 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4307 4308 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4309 } 4310 4311 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4312 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4313 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4314 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4315 4316 /* 4317 * Setup the HW Rx Head and Tail Descriptor Pointers and 4318 * the Base and Length of the Rx Descriptor Ring 4319 */ 4320 for (i = 0; i < adapter->num_rx_queues; i++) { 4321 rx_ring = adapter->rx_ring[i]; 4322 4323 clear_ring_rsc_enabled(rx_ring); 4324 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4325 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4326 4327 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4328 set_ring_rsc_enabled(rx_ring); 4329 4330 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4331 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4332 4333 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4334 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4335 continue; 4336 4337 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4338 4339 #if (PAGE_SIZE < 8192) 4340 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4341 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4342 4343 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4344 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4345 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4346 #endif 4347 } 4348 } 4349 4350 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4351 { 4352 struct ixgbe_hw *hw = &adapter->hw; 4353 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4354 4355 switch (hw->mac.type) { 4356 case ixgbe_mac_82598EB: 4357 /* 4358 * For VMDq support of different descriptor types or 4359 * buffer sizes through the use of multiple SRRCTL 4360 * registers, RDRXCTL.MVMEN must be set to 1 4361 * 4362 * also, the manual doesn't mention it clearly but DCA hints 4363 * will only use queue 0's tags unless this bit is set. Side 4364 * effects of setting this bit are only that SRRCTL must be 4365 * fully programmed [0..15] 4366 */ 4367 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4368 break; 4369 case ixgbe_mac_X550: 4370 case ixgbe_mac_X550EM_x: 4371 case ixgbe_mac_x550em_a: 4372 if (adapter->num_vfs) 4373 rdrxctl |= IXGBE_RDRXCTL_PSP; 4374 /* fall through */ 4375 case ixgbe_mac_82599EB: 4376 case ixgbe_mac_X540: 4377 /* Disable RSC for ACK packets */ 4378 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4379 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4380 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4381 /* hardware requires some bits to be set by default */ 4382 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4383 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4384 break; 4385 default: 4386 /* We should do nothing since we don't know this hardware */ 4387 return; 4388 } 4389 4390 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4391 } 4392 4393 /** 4394 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4395 * @adapter: board private structure 4396 * 4397 * Configure the Rx unit of the MAC after a reset. 4398 **/ 4399 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4400 { 4401 struct ixgbe_hw *hw = &adapter->hw; 4402 int i; 4403 u32 rxctrl, rfctl; 4404 4405 /* disable receives while setting up the descriptors */ 4406 hw->mac.ops.disable_rx(hw); 4407 4408 ixgbe_setup_psrtype(adapter); 4409 ixgbe_setup_rdrxctl(adapter); 4410 4411 /* RSC Setup */ 4412 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4413 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4414 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4415 rfctl |= IXGBE_RFCTL_RSC_DIS; 4416 4417 /* disable NFS filtering */ 4418 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4419 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4420 4421 /* Program registers for the distribution of queues */ 4422 ixgbe_setup_mrqc(adapter); 4423 4424 /* set_rx_buffer_len must be called before ring initialization */ 4425 ixgbe_set_rx_buffer_len(adapter); 4426 4427 /* 4428 * Setup the HW Rx Head and Tail Descriptor Pointers and 4429 * the Base and Length of the Rx Descriptor Ring 4430 */ 4431 for (i = 0; i < adapter->num_rx_queues; i++) 4432 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4433 4434 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4435 /* disable drop enable for 82598 parts */ 4436 if (hw->mac.type == ixgbe_mac_82598EB) 4437 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4438 4439 /* enable all receives */ 4440 rxctrl |= IXGBE_RXCTRL_RXEN; 4441 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4442 } 4443 4444 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4445 __be16 proto, u16 vid) 4446 { 4447 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4448 struct ixgbe_hw *hw = &adapter->hw; 4449 4450 /* add VID to filter table */ 4451 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4452 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4453 4454 set_bit(vid, adapter->active_vlans); 4455 4456 return 0; 4457 } 4458 4459 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4460 { 4461 u32 vlvf; 4462 int idx; 4463 4464 /* short cut the special case */ 4465 if (vlan == 0) 4466 return 0; 4467 4468 /* Search for the vlan id in the VLVF entries */ 4469 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4470 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4471 if ((vlvf & VLAN_VID_MASK) == vlan) 4472 break; 4473 } 4474 4475 return idx; 4476 } 4477 4478 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4479 { 4480 struct ixgbe_hw *hw = &adapter->hw; 4481 u32 bits, word; 4482 int idx; 4483 4484 idx = ixgbe_find_vlvf_entry(hw, vid); 4485 if (!idx) 4486 return; 4487 4488 /* See if any other pools are set for this VLAN filter 4489 * entry other than the PF. 4490 */ 4491 word = idx * 2 + (VMDQ_P(0) / 32); 4492 bits = ~BIT(VMDQ_P(0) % 32); 4493 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4494 4495 /* Disable the filter so this falls into the default pool. */ 4496 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4497 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4498 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4499 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4500 } 4501 } 4502 4503 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4504 __be16 proto, u16 vid) 4505 { 4506 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4507 struct ixgbe_hw *hw = &adapter->hw; 4508 4509 /* remove VID from filter table */ 4510 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4511 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4512 4513 clear_bit(vid, adapter->active_vlans); 4514 4515 return 0; 4516 } 4517 4518 /** 4519 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4520 * @adapter: driver data 4521 */ 4522 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4523 { 4524 struct ixgbe_hw *hw = &adapter->hw; 4525 u32 vlnctrl; 4526 int i, j; 4527 4528 switch (hw->mac.type) { 4529 case ixgbe_mac_82598EB: 4530 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4531 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4532 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4533 break; 4534 case ixgbe_mac_82599EB: 4535 case ixgbe_mac_X540: 4536 case ixgbe_mac_X550: 4537 case ixgbe_mac_X550EM_x: 4538 case ixgbe_mac_x550em_a: 4539 for (i = 0; i < adapter->num_rx_queues; i++) { 4540 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4541 4542 if (!netif_is_ixgbe(ring->netdev)) 4543 continue; 4544 4545 j = ring->reg_idx; 4546 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4547 vlnctrl &= ~IXGBE_RXDCTL_VME; 4548 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4549 } 4550 break; 4551 default: 4552 break; 4553 } 4554 } 4555 4556 /** 4557 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4558 * @adapter: driver data 4559 */ 4560 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4561 { 4562 struct ixgbe_hw *hw = &adapter->hw; 4563 u32 vlnctrl; 4564 int i, j; 4565 4566 switch (hw->mac.type) { 4567 case ixgbe_mac_82598EB: 4568 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4569 vlnctrl |= IXGBE_VLNCTRL_VME; 4570 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4571 break; 4572 case ixgbe_mac_82599EB: 4573 case ixgbe_mac_X540: 4574 case ixgbe_mac_X550: 4575 case ixgbe_mac_X550EM_x: 4576 case ixgbe_mac_x550em_a: 4577 for (i = 0; i < adapter->num_rx_queues; i++) { 4578 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4579 4580 if (!netif_is_ixgbe(ring->netdev)) 4581 continue; 4582 4583 j = ring->reg_idx; 4584 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4585 vlnctrl |= IXGBE_RXDCTL_VME; 4586 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4587 } 4588 break; 4589 default: 4590 break; 4591 } 4592 } 4593 4594 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4595 { 4596 struct ixgbe_hw *hw = &adapter->hw; 4597 u32 vlnctrl, i; 4598 4599 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4600 4601 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4602 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4603 vlnctrl |= IXGBE_VLNCTRL_VFE; 4604 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4605 } else { 4606 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4607 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4608 return; 4609 } 4610 4611 /* Nothing to do for 82598 */ 4612 if (hw->mac.type == ixgbe_mac_82598EB) 4613 return; 4614 4615 /* We are already in VLAN promisc, nothing to do */ 4616 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4617 return; 4618 4619 /* Set flag so we don't redo unnecessary work */ 4620 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4621 4622 /* Add PF to all active pools */ 4623 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4624 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4625 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4626 4627 vlvfb |= BIT(VMDQ_P(0) % 32); 4628 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4629 } 4630 4631 /* Set all bits in the VLAN filter table array */ 4632 for (i = hw->mac.vft_size; i--;) 4633 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4634 } 4635 4636 #define VFTA_BLOCK_SIZE 8 4637 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4638 { 4639 struct ixgbe_hw *hw = &adapter->hw; 4640 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4641 u32 vid_start = vfta_offset * 32; 4642 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4643 u32 i, vid, word, bits; 4644 4645 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4646 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4647 4648 /* pull VLAN ID from VLVF */ 4649 vid = vlvf & VLAN_VID_MASK; 4650 4651 /* only concern outselves with a certain range */ 4652 if (vid < vid_start || vid >= vid_end) 4653 continue; 4654 4655 if (vlvf) { 4656 /* record VLAN ID in VFTA */ 4657 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4658 4659 /* if PF is part of this then continue */ 4660 if (test_bit(vid, adapter->active_vlans)) 4661 continue; 4662 } 4663 4664 /* remove PF from the pool */ 4665 word = i * 2 + VMDQ_P(0) / 32; 4666 bits = ~BIT(VMDQ_P(0) % 32); 4667 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4668 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4669 } 4670 4671 /* extract values from active_vlans and write back to VFTA */ 4672 for (i = VFTA_BLOCK_SIZE; i--;) { 4673 vid = (vfta_offset + i) * 32; 4674 word = vid / BITS_PER_LONG; 4675 bits = vid % BITS_PER_LONG; 4676 4677 vfta[i] |= adapter->active_vlans[word] >> bits; 4678 4679 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4680 } 4681 } 4682 4683 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4684 { 4685 struct ixgbe_hw *hw = &adapter->hw; 4686 u32 vlnctrl, i; 4687 4688 /* Set VLAN filtering to enabled */ 4689 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4690 vlnctrl |= IXGBE_VLNCTRL_VFE; 4691 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4692 4693 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4694 hw->mac.type == ixgbe_mac_82598EB) 4695 return; 4696 4697 /* We are not in VLAN promisc, nothing to do */ 4698 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4699 return; 4700 4701 /* Set flag so we don't redo unnecessary work */ 4702 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4703 4704 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4705 ixgbe_scrub_vfta(adapter, i); 4706 } 4707 4708 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4709 { 4710 u16 vid = 1; 4711 4712 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4713 4714 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4715 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4716 } 4717 4718 /** 4719 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4720 * @netdev: network interface device structure 4721 * 4722 * Writes multicast address list to the MTA hash table. 4723 * Returns: -ENOMEM on failure 4724 * 0 on no addresses written 4725 * X on writing X addresses to MTA 4726 **/ 4727 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4728 { 4729 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4730 struct ixgbe_hw *hw = &adapter->hw; 4731 4732 if (!netif_running(netdev)) 4733 return 0; 4734 4735 if (hw->mac.ops.update_mc_addr_list) 4736 hw->mac.ops.update_mc_addr_list(hw, netdev); 4737 else 4738 return -ENOMEM; 4739 4740 #ifdef CONFIG_PCI_IOV 4741 ixgbe_restore_vf_multicasts(adapter); 4742 #endif 4743 4744 return netdev_mc_count(netdev); 4745 } 4746 4747 #ifdef CONFIG_PCI_IOV 4748 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4749 { 4750 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4751 struct ixgbe_hw *hw = &adapter->hw; 4752 int i; 4753 4754 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4755 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4756 4757 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4758 hw->mac.ops.set_rar(hw, i, 4759 mac_table->addr, 4760 mac_table->pool, 4761 IXGBE_RAH_AV); 4762 else 4763 hw->mac.ops.clear_rar(hw, i); 4764 } 4765 } 4766 4767 #endif 4768 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4769 { 4770 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4771 struct ixgbe_hw *hw = &adapter->hw; 4772 int i; 4773 4774 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4775 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4776 continue; 4777 4778 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4779 4780 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4781 hw->mac.ops.set_rar(hw, i, 4782 mac_table->addr, 4783 mac_table->pool, 4784 IXGBE_RAH_AV); 4785 else 4786 hw->mac.ops.clear_rar(hw, i); 4787 } 4788 } 4789 4790 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4791 { 4792 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4793 struct ixgbe_hw *hw = &adapter->hw; 4794 int i; 4795 4796 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4797 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4798 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4799 } 4800 4801 ixgbe_sync_mac_table(adapter); 4802 } 4803 4804 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4805 { 4806 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4807 struct ixgbe_hw *hw = &adapter->hw; 4808 int i, count = 0; 4809 4810 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4811 /* do not count default RAR as available */ 4812 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4813 continue; 4814 4815 /* only count unused and addresses that belong to us */ 4816 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4817 if (mac_table->pool != pool) 4818 continue; 4819 } 4820 4821 count++; 4822 } 4823 4824 return count; 4825 } 4826 4827 /* this function destroys the first RAR entry */ 4828 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4829 { 4830 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4831 struct ixgbe_hw *hw = &adapter->hw; 4832 4833 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4834 mac_table->pool = VMDQ_P(0); 4835 4836 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4837 4838 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4839 IXGBE_RAH_AV); 4840 } 4841 4842 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4843 const u8 *addr, u16 pool) 4844 { 4845 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4846 struct ixgbe_hw *hw = &adapter->hw; 4847 int i; 4848 4849 if (is_zero_ether_addr(addr)) 4850 return -EINVAL; 4851 4852 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4853 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4854 continue; 4855 4856 ether_addr_copy(mac_table->addr, addr); 4857 mac_table->pool = pool; 4858 4859 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4860 IXGBE_MAC_STATE_IN_USE; 4861 4862 ixgbe_sync_mac_table(adapter); 4863 4864 return i; 4865 } 4866 4867 return -ENOMEM; 4868 } 4869 4870 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4871 const u8 *addr, u16 pool) 4872 { 4873 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4874 struct ixgbe_hw *hw = &adapter->hw; 4875 int i; 4876 4877 if (is_zero_ether_addr(addr)) 4878 return -EINVAL; 4879 4880 /* search table for addr, if found clear IN_USE flag and sync */ 4881 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4882 /* we can only delete an entry if it is in use */ 4883 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4884 continue; 4885 /* we only care about entries that belong to the given pool */ 4886 if (mac_table->pool != pool) 4887 continue; 4888 /* we only care about a specific MAC address */ 4889 if (!ether_addr_equal(addr, mac_table->addr)) 4890 continue; 4891 4892 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4893 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4894 4895 ixgbe_sync_mac_table(adapter); 4896 4897 return 0; 4898 } 4899 4900 return -ENOMEM; 4901 } 4902 4903 /** 4904 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4905 * @netdev: network interface device structure 4906 * @vfn: pool to associate with unicast addresses 4907 * 4908 * Writes unicast address list to the RAR table. 4909 * Returns: -ENOMEM on failure/insufficient address space 4910 * 0 on no addresses written 4911 * X on writing X addresses to the RAR table 4912 **/ 4913 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4914 { 4915 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4916 int count = 0; 4917 4918 /* return ENOMEM indicating insufficient memory for addresses */ 4919 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) 4920 return -ENOMEM; 4921 4922 if (!netdev_uc_empty(netdev)) { 4923 struct netdev_hw_addr *ha; 4924 netdev_for_each_uc_addr(ha, netdev) { 4925 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4926 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4927 count++; 4928 } 4929 } 4930 return count; 4931 } 4932 4933 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4934 { 4935 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4936 int ret; 4937 4938 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4939 4940 return min_t(int, ret, 0); 4941 } 4942 4943 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4944 { 4945 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4946 4947 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4948 4949 return 0; 4950 } 4951 4952 /** 4953 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4954 * @netdev: network interface device structure 4955 * 4956 * The set_rx_method entry point is called whenever the unicast/multicast 4957 * address list or the network interface flags are updated. This routine is 4958 * responsible for configuring the hardware for proper unicast, multicast and 4959 * promiscuous mode. 4960 **/ 4961 void ixgbe_set_rx_mode(struct net_device *netdev) 4962 { 4963 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4964 struct ixgbe_hw *hw = &adapter->hw; 4965 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4966 netdev_features_t features = netdev->features; 4967 int count; 4968 4969 /* Check for Promiscuous and All Multicast modes */ 4970 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4971 4972 /* set all bits that we expect to always be set */ 4973 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4974 fctrl |= IXGBE_FCTRL_BAM; 4975 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4976 fctrl |= IXGBE_FCTRL_PMCF; 4977 4978 /* clear the bits we are changing the status of */ 4979 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4980 if (netdev->flags & IFF_PROMISC) { 4981 hw->addr_ctrl.user_set_promisc = true; 4982 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4983 vmolr |= IXGBE_VMOLR_MPE; 4984 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4985 } else { 4986 if (netdev->flags & IFF_ALLMULTI) { 4987 fctrl |= IXGBE_FCTRL_MPE; 4988 vmolr |= IXGBE_VMOLR_MPE; 4989 } 4990 hw->addr_ctrl.user_set_promisc = false; 4991 } 4992 4993 /* 4994 * Write addresses to available RAR registers, if there is not 4995 * sufficient space to store all the addresses then enable 4996 * unicast promiscuous mode 4997 */ 4998 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4999 fctrl |= IXGBE_FCTRL_UPE; 5000 vmolr |= IXGBE_VMOLR_ROPE; 5001 } 5002 5003 /* Write addresses to the MTA, if the attempt fails 5004 * then we should just turn on promiscuous mode so 5005 * that we can at least receive multicast traffic 5006 */ 5007 count = ixgbe_write_mc_addr_list(netdev); 5008 if (count < 0) { 5009 fctrl |= IXGBE_FCTRL_MPE; 5010 vmolr |= IXGBE_VMOLR_MPE; 5011 } else if (count) { 5012 vmolr |= IXGBE_VMOLR_ROMPE; 5013 } 5014 5015 if (hw->mac.type != ixgbe_mac_82598EB) { 5016 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 5017 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 5018 IXGBE_VMOLR_ROPE); 5019 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 5020 } 5021 5022 /* This is useful for sniffing bad packets. */ 5023 if (features & NETIF_F_RXALL) { 5024 /* UPE and MPE will be handled by normal PROMISC logic 5025 * in e1000e_set_rx_mode */ 5026 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 5027 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 5028 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 5029 5030 fctrl &= ~(IXGBE_FCTRL_DPF); 5031 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 5032 } 5033 5034 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5035 5036 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5037 ixgbe_vlan_strip_enable(adapter); 5038 else 5039 ixgbe_vlan_strip_disable(adapter); 5040 5041 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 5042 ixgbe_vlan_promisc_disable(adapter); 5043 else 5044 ixgbe_vlan_promisc_enable(adapter); 5045 } 5046 5047 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5048 { 5049 int q_idx; 5050 5051 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5052 napi_enable(&adapter->q_vector[q_idx]->napi); 5053 } 5054 5055 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5056 { 5057 int q_idx; 5058 5059 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5060 napi_disable(&adapter->q_vector[q_idx]->napi); 5061 } 5062 5063 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5064 { 5065 struct ixgbe_hw *hw = &adapter->hw; 5066 u32 vxlanctrl; 5067 5068 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5069 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5070 return; 5071 5072 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5073 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5074 5075 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5076 adapter->vxlan_port = 0; 5077 5078 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5079 adapter->geneve_port = 0; 5080 } 5081 5082 #ifdef CONFIG_IXGBE_DCB 5083 /** 5084 * ixgbe_configure_dcb - Configure DCB hardware 5085 * @adapter: ixgbe adapter struct 5086 * 5087 * This is called by the driver on open to configure the DCB hardware. 5088 * This is also called by the gennetlink interface when reconfiguring 5089 * the DCB state. 5090 */ 5091 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5092 { 5093 struct ixgbe_hw *hw = &adapter->hw; 5094 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5095 5096 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5097 if (hw->mac.type == ixgbe_mac_82598EB) 5098 netif_set_gso_max_size(adapter->netdev, 65536); 5099 return; 5100 } 5101 5102 if (hw->mac.type == ixgbe_mac_82598EB) 5103 netif_set_gso_max_size(adapter->netdev, 32768); 5104 5105 #ifdef IXGBE_FCOE 5106 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5107 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5108 #endif 5109 5110 /* reconfigure the hardware */ 5111 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5112 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5113 DCB_TX_CONFIG); 5114 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5115 DCB_RX_CONFIG); 5116 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5117 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5118 ixgbe_dcb_hw_ets(&adapter->hw, 5119 adapter->ixgbe_ieee_ets, 5120 max_frame); 5121 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5122 adapter->ixgbe_ieee_pfc->pfc_en, 5123 adapter->ixgbe_ieee_ets->prio_tc); 5124 } 5125 5126 /* Enable RSS Hash per TC */ 5127 if (hw->mac.type != ixgbe_mac_82598EB) { 5128 u32 msb = 0; 5129 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5130 5131 while (rss_i) { 5132 msb++; 5133 rss_i >>= 1; 5134 } 5135 5136 /* write msb to all 8 TCs in one write */ 5137 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5138 } 5139 } 5140 #endif 5141 5142 /* Additional bittime to account for IXGBE framing */ 5143 #define IXGBE_ETH_FRAMING 20 5144 5145 /** 5146 * ixgbe_hpbthresh - calculate high water mark for flow control 5147 * 5148 * @adapter: board private structure to calculate for 5149 * @pb: packet buffer to calculate 5150 */ 5151 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5152 { 5153 struct ixgbe_hw *hw = &adapter->hw; 5154 struct net_device *dev = adapter->netdev; 5155 int link, tc, kb, marker; 5156 u32 dv_id, rx_pba; 5157 5158 /* Calculate max LAN frame size */ 5159 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5160 5161 #ifdef IXGBE_FCOE 5162 /* FCoE traffic class uses FCOE jumbo frames */ 5163 if ((dev->features & NETIF_F_FCOE_MTU) && 5164 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5165 (pb == ixgbe_fcoe_get_tc(adapter))) 5166 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5167 #endif 5168 5169 /* Calculate delay value for device */ 5170 switch (hw->mac.type) { 5171 case ixgbe_mac_X540: 5172 case ixgbe_mac_X550: 5173 case ixgbe_mac_X550EM_x: 5174 case ixgbe_mac_x550em_a: 5175 dv_id = IXGBE_DV_X540(link, tc); 5176 break; 5177 default: 5178 dv_id = IXGBE_DV(link, tc); 5179 break; 5180 } 5181 5182 /* Loopback switch introduces additional latency */ 5183 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5184 dv_id += IXGBE_B2BT(tc); 5185 5186 /* Delay value is calculated in bit times convert to KB */ 5187 kb = IXGBE_BT2KB(dv_id); 5188 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5189 5190 marker = rx_pba - kb; 5191 5192 /* It is possible that the packet buffer is not large enough 5193 * to provide required headroom. In this case throw an error 5194 * to user and a do the best we can. 5195 */ 5196 if (marker < 0) { 5197 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5198 "headroom to support flow control." 5199 "Decrease MTU or number of traffic classes\n", pb); 5200 marker = tc + 1; 5201 } 5202 5203 return marker; 5204 } 5205 5206 /** 5207 * ixgbe_lpbthresh - calculate low water mark for for flow control 5208 * 5209 * @adapter: board private structure to calculate for 5210 * @pb: packet buffer to calculate 5211 */ 5212 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5213 { 5214 struct ixgbe_hw *hw = &adapter->hw; 5215 struct net_device *dev = adapter->netdev; 5216 int tc; 5217 u32 dv_id; 5218 5219 /* Calculate max LAN frame size */ 5220 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5221 5222 #ifdef IXGBE_FCOE 5223 /* FCoE traffic class uses FCOE jumbo frames */ 5224 if ((dev->features & NETIF_F_FCOE_MTU) && 5225 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5226 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5227 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5228 #endif 5229 5230 /* Calculate delay value for device */ 5231 switch (hw->mac.type) { 5232 case ixgbe_mac_X540: 5233 case ixgbe_mac_X550: 5234 case ixgbe_mac_X550EM_x: 5235 case ixgbe_mac_x550em_a: 5236 dv_id = IXGBE_LOW_DV_X540(tc); 5237 break; 5238 default: 5239 dv_id = IXGBE_LOW_DV(tc); 5240 break; 5241 } 5242 5243 /* Delay value is calculated in bit times convert to KB */ 5244 return IXGBE_BT2KB(dv_id); 5245 } 5246 5247 /* 5248 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5249 */ 5250 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5251 { 5252 struct ixgbe_hw *hw = &adapter->hw; 5253 int num_tc = adapter->hw_tcs; 5254 int i; 5255 5256 if (!num_tc) 5257 num_tc = 1; 5258 5259 for (i = 0; i < num_tc; i++) { 5260 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5261 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5262 5263 /* Low water marks must not be larger than high water marks */ 5264 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5265 hw->fc.low_water[i] = 0; 5266 } 5267 5268 for (; i < MAX_TRAFFIC_CLASS; i++) 5269 hw->fc.high_water[i] = 0; 5270 } 5271 5272 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5273 { 5274 struct ixgbe_hw *hw = &adapter->hw; 5275 int hdrm; 5276 u8 tc = adapter->hw_tcs; 5277 5278 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5279 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5280 hdrm = 32 << adapter->fdir_pballoc; 5281 else 5282 hdrm = 0; 5283 5284 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5285 ixgbe_pbthresh_setup(adapter); 5286 } 5287 5288 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5289 { 5290 struct ixgbe_hw *hw = &adapter->hw; 5291 struct hlist_node *node2; 5292 struct ixgbe_fdir_filter *filter; 5293 5294 spin_lock(&adapter->fdir_perfect_lock); 5295 5296 if (!hlist_empty(&adapter->fdir_filter_list)) 5297 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5298 5299 hlist_for_each_entry_safe(filter, node2, 5300 &adapter->fdir_filter_list, fdir_node) { 5301 ixgbe_fdir_write_perfect_filter_82599(hw, 5302 &filter->filter, 5303 filter->sw_idx, 5304 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5305 IXGBE_FDIR_DROP_QUEUE : 5306 adapter->rx_ring[filter->action]->reg_idx); 5307 } 5308 5309 spin_unlock(&adapter->fdir_perfect_lock); 5310 } 5311 5312 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 5313 struct ixgbe_adapter *adapter) 5314 { 5315 struct ixgbe_hw *hw = &adapter->hw; 5316 u32 vmolr; 5317 5318 /* No unicast promiscuous support for VMDQ devices. */ 5319 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 5320 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 5321 5322 /* clear the affected bit */ 5323 vmolr &= ~IXGBE_VMOLR_MPE; 5324 5325 if (dev->flags & IFF_ALLMULTI) { 5326 vmolr |= IXGBE_VMOLR_MPE; 5327 } else { 5328 vmolr |= IXGBE_VMOLR_ROMPE; 5329 hw->mac.ops.update_mc_addr_list(hw, dev); 5330 } 5331 ixgbe_write_uc_addr_list(adapter->netdev, pool); 5332 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 5333 } 5334 5335 /** 5336 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5337 * @rx_ring: ring to free buffers from 5338 **/ 5339 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5340 { 5341 u16 i = rx_ring->next_to_clean; 5342 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5343 5344 /* Free all the Rx ring sk_buffs */ 5345 while (i != rx_ring->next_to_alloc) { 5346 if (rx_buffer->skb) { 5347 struct sk_buff *skb = rx_buffer->skb; 5348 if (IXGBE_CB(skb)->page_released) 5349 dma_unmap_page_attrs(rx_ring->dev, 5350 IXGBE_CB(skb)->dma, 5351 ixgbe_rx_pg_size(rx_ring), 5352 DMA_FROM_DEVICE, 5353 IXGBE_RX_DMA_ATTR); 5354 dev_kfree_skb(skb); 5355 } 5356 5357 /* Invalidate cache lines that may have been written to by 5358 * device so that we avoid corrupting memory. 5359 */ 5360 dma_sync_single_range_for_cpu(rx_ring->dev, 5361 rx_buffer->dma, 5362 rx_buffer->page_offset, 5363 ixgbe_rx_bufsz(rx_ring), 5364 DMA_FROM_DEVICE); 5365 5366 /* free resources associated with mapping */ 5367 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5368 ixgbe_rx_pg_size(rx_ring), 5369 DMA_FROM_DEVICE, 5370 IXGBE_RX_DMA_ATTR); 5371 __page_frag_cache_drain(rx_buffer->page, 5372 rx_buffer->pagecnt_bias); 5373 5374 i++; 5375 rx_buffer++; 5376 if (i == rx_ring->count) { 5377 i = 0; 5378 rx_buffer = rx_ring->rx_buffer_info; 5379 } 5380 } 5381 5382 rx_ring->next_to_alloc = 0; 5383 rx_ring->next_to_clean = 0; 5384 rx_ring->next_to_use = 0; 5385 } 5386 5387 static int ixgbe_fwd_ring_up(struct net_device *vdev, 5388 struct ixgbe_fwd_adapter *accel) 5389 { 5390 struct ixgbe_adapter *adapter = accel->real_adapter; 5391 int i, baseq, err; 5392 5393 if (!test_bit(accel->pool, adapter->fwd_bitmask)) 5394 return 0; 5395 5396 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5397 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5398 accel->pool, adapter->num_rx_pools, 5399 baseq, baseq + adapter->num_rx_queues_per_pool); 5400 5401 accel->netdev = vdev; 5402 accel->rx_base_queue = baseq; 5403 accel->tx_base_queue = baseq; 5404 5405 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5406 adapter->rx_ring[baseq + i]->netdev = vdev; 5407 5408 /* Guarantee all rings are updated before we update the 5409 * MAC address filter. 5410 */ 5411 wmb(); 5412 5413 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5414 * need to only treat it as an error value if it is negative. 5415 */ 5416 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5417 VMDQ_P(accel->pool)); 5418 if (err >= 0) { 5419 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 5420 return 0; 5421 } 5422 5423 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5424 adapter->rx_ring[baseq + i]->netdev = NULL; 5425 5426 return err; 5427 } 5428 5429 static int ixgbe_upper_dev_walk(struct net_device *upper, void *data) 5430 { 5431 if (netif_is_macvlan(upper)) { 5432 struct macvlan_dev *dfwd = netdev_priv(upper); 5433 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 5434 5435 if (dfwd->fwd_priv) 5436 ixgbe_fwd_ring_up(upper, vadapter); 5437 } 5438 5439 return 0; 5440 } 5441 5442 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5443 { 5444 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5445 ixgbe_upper_dev_walk, NULL); 5446 } 5447 5448 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5449 { 5450 struct ixgbe_hw *hw = &adapter->hw; 5451 5452 ixgbe_configure_pb(adapter); 5453 #ifdef CONFIG_IXGBE_DCB 5454 ixgbe_configure_dcb(adapter); 5455 #endif 5456 /* 5457 * We must restore virtualization before VLANs or else 5458 * the VLVF registers will not be populated 5459 */ 5460 ixgbe_configure_virtualization(adapter); 5461 5462 ixgbe_set_rx_mode(adapter->netdev); 5463 ixgbe_restore_vlan(adapter); 5464 ixgbe_ipsec_restore(adapter); 5465 5466 switch (hw->mac.type) { 5467 case ixgbe_mac_82599EB: 5468 case ixgbe_mac_X540: 5469 hw->mac.ops.disable_rx_buff(hw); 5470 break; 5471 default: 5472 break; 5473 } 5474 5475 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5476 ixgbe_init_fdir_signature_82599(&adapter->hw, 5477 adapter->fdir_pballoc); 5478 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5479 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5480 adapter->fdir_pballoc); 5481 ixgbe_fdir_filter_restore(adapter); 5482 } 5483 5484 switch (hw->mac.type) { 5485 case ixgbe_mac_82599EB: 5486 case ixgbe_mac_X540: 5487 hw->mac.ops.enable_rx_buff(hw); 5488 break; 5489 default: 5490 break; 5491 } 5492 5493 #ifdef CONFIG_IXGBE_DCA 5494 /* configure DCA */ 5495 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5496 ixgbe_setup_dca(adapter); 5497 #endif /* CONFIG_IXGBE_DCA */ 5498 5499 #ifdef IXGBE_FCOE 5500 /* configure FCoE L2 filters, redirection table, and Rx control */ 5501 ixgbe_configure_fcoe(adapter); 5502 5503 #endif /* IXGBE_FCOE */ 5504 ixgbe_configure_tx(adapter); 5505 ixgbe_configure_rx(adapter); 5506 ixgbe_configure_dfwd(adapter); 5507 } 5508 5509 /** 5510 * ixgbe_sfp_link_config - set up SFP+ link 5511 * @adapter: pointer to private adapter struct 5512 **/ 5513 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5514 { 5515 /* 5516 * We are assuming the worst case scenario here, and that 5517 * is that an SFP was inserted/removed after the reset 5518 * but before SFP detection was enabled. As such the best 5519 * solution is to just start searching as soon as we start 5520 */ 5521 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5522 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5523 5524 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5525 adapter->sfp_poll_time = 0; 5526 } 5527 5528 /** 5529 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5530 * @hw: pointer to private hardware struct 5531 * 5532 * Returns 0 on success, negative on failure 5533 **/ 5534 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5535 { 5536 u32 speed; 5537 bool autoneg, link_up = false; 5538 int ret = IXGBE_ERR_LINK_SETUP; 5539 5540 if (hw->mac.ops.check_link) 5541 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5542 5543 if (ret) 5544 return ret; 5545 5546 speed = hw->phy.autoneg_advertised; 5547 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5548 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5549 &autoneg); 5550 if (ret) 5551 return ret; 5552 5553 if (hw->mac.ops.setup_link) 5554 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5555 5556 return ret; 5557 } 5558 5559 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5560 { 5561 struct ixgbe_hw *hw = &adapter->hw; 5562 u32 gpie = 0; 5563 5564 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5565 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5566 IXGBE_GPIE_OCD; 5567 gpie |= IXGBE_GPIE_EIAME; 5568 /* 5569 * use EIAM to auto-mask when MSI-X interrupt is asserted 5570 * this saves a register write for every interrupt 5571 */ 5572 switch (hw->mac.type) { 5573 case ixgbe_mac_82598EB: 5574 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5575 break; 5576 case ixgbe_mac_82599EB: 5577 case ixgbe_mac_X540: 5578 case ixgbe_mac_X550: 5579 case ixgbe_mac_X550EM_x: 5580 case ixgbe_mac_x550em_a: 5581 default: 5582 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5583 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5584 break; 5585 } 5586 } else { 5587 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5588 * specifically only auto mask tx and rx interrupts */ 5589 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5590 } 5591 5592 /* XXX: to interrupt immediately for EICS writes, enable this */ 5593 /* gpie |= IXGBE_GPIE_EIMEN; */ 5594 5595 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5596 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5597 5598 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5599 case IXGBE_82599_VMDQ_8Q_MASK: 5600 gpie |= IXGBE_GPIE_VTMODE_16; 5601 break; 5602 case IXGBE_82599_VMDQ_4Q_MASK: 5603 gpie |= IXGBE_GPIE_VTMODE_32; 5604 break; 5605 default: 5606 gpie |= IXGBE_GPIE_VTMODE_64; 5607 break; 5608 } 5609 } 5610 5611 /* Enable Thermal over heat sensor interrupt */ 5612 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5613 switch (adapter->hw.mac.type) { 5614 case ixgbe_mac_82599EB: 5615 gpie |= IXGBE_SDP0_GPIEN_8259X; 5616 break; 5617 default: 5618 break; 5619 } 5620 } 5621 5622 /* Enable fan failure interrupt */ 5623 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5624 gpie |= IXGBE_SDP1_GPIEN(hw); 5625 5626 switch (hw->mac.type) { 5627 case ixgbe_mac_82599EB: 5628 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5629 break; 5630 case ixgbe_mac_X550EM_x: 5631 case ixgbe_mac_x550em_a: 5632 gpie |= IXGBE_SDP0_GPIEN_X540; 5633 break; 5634 default: 5635 break; 5636 } 5637 5638 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5639 } 5640 5641 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5642 { 5643 struct ixgbe_hw *hw = &adapter->hw; 5644 int err; 5645 u32 ctrl_ext; 5646 5647 ixgbe_get_hw_control(adapter); 5648 ixgbe_setup_gpie(adapter); 5649 5650 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5651 ixgbe_configure_msix(adapter); 5652 else 5653 ixgbe_configure_msi_and_legacy(adapter); 5654 5655 /* enable the optics for 82599 SFP+ fiber */ 5656 if (hw->mac.ops.enable_tx_laser) 5657 hw->mac.ops.enable_tx_laser(hw); 5658 5659 if (hw->phy.ops.set_phy_power) 5660 hw->phy.ops.set_phy_power(hw, true); 5661 5662 smp_mb__before_atomic(); 5663 clear_bit(__IXGBE_DOWN, &adapter->state); 5664 ixgbe_napi_enable_all(adapter); 5665 5666 if (ixgbe_is_sfp(hw)) { 5667 ixgbe_sfp_link_config(adapter); 5668 } else { 5669 err = ixgbe_non_sfp_link_config(hw); 5670 if (err) 5671 e_err(probe, "link_config FAILED %d\n", err); 5672 } 5673 5674 /* clear any pending interrupts, may auto mask */ 5675 IXGBE_READ_REG(hw, IXGBE_EICR); 5676 ixgbe_irq_enable(adapter, true, true); 5677 5678 /* 5679 * If this adapter has a fan, check to see if we had a failure 5680 * before we enabled the interrupt. 5681 */ 5682 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5683 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5684 if (esdp & IXGBE_ESDP_SDP1) 5685 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5686 } 5687 5688 /* bring the link up in the watchdog, this could race with our first 5689 * link up interrupt but shouldn't be a problem */ 5690 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5691 adapter->link_check_timeout = jiffies; 5692 mod_timer(&adapter->service_timer, jiffies); 5693 5694 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5695 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5696 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5697 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5698 } 5699 5700 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5701 { 5702 WARN_ON(in_interrupt()); 5703 /* put off any impending NetWatchDogTimeout */ 5704 netif_trans_update(adapter->netdev); 5705 5706 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5707 usleep_range(1000, 2000); 5708 if (adapter->hw.phy.type == ixgbe_phy_fw) 5709 ixgbe_watchdog_link_is_down(adapter); 5710 ixgbe_down(adapter); 5711 /* 5712 * If SR-IOV enabled then wait a bit before bringing the adapter 5713 * back up to give the VFs time to respond to the reset. The 5714 * two second wait is based upon the watchdog timer cycle in 5715 * the VF driver. 5716 */ 5717 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5718 msleep(2000); 5719 ixgbe_up(adapter); 5720 clear_bit(__IXGBE_RESETTING, &adapter->state); 5721 } 5722 5723 void ixgbe_up(struct ixgbe_adapter *adapter) 5724 { 5725 /* hardware has been reset, we need to reload some things */ 5726 ixgbe_configure(adapter); 5727 5728 ixgbe_up_complete(adapter); 5729 } 5730 5731 void ixgbe_reset(struct ixgbe_adapter *adapter) 5732 { 5733 struct ixgbe_hw *hw = &adapter->hw; 5734 struct net_device *netdev = adapter->netdev; 5735 int err; 5736 5737 if (ixgbe_removed(hw->hw_addr)) 5738 return; 5739 /* lock SFP init bit to prevent race conditions with the watchdog */ 5740 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5741 usleep_range(1000, 2000); 5742 5743 /* clear all SFP and link config related flags while holding SFP_INIT */ 5744 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5745 IXGBE_FLAG2_SFP_NEEDS_RESET); 5746 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5747 5748 err = hw->mac.ops.init_hw(hw); 5749 switch (err) { 5750 case 0: 5751 case IXGBE_ERR_SFP_NOT_PRESENT: 5752 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5753 break; 5754 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5755 e_dev_err("master disable timed out\n"); 5756 break; 5757 case IXGBE_ERR_EEPROM_VERSION: 5758 /* We are running on a pre-production device, log a warning */ 5759 e_dev_warn("This device is a pre-production adapter/LOM. " 5760 "Please be aware there may be issues associated with " 5761 "your hardware. If you are experiencing problems " 5762 "please contact your Intel or hardware " 5763 "representative who provided you with this " 5764 "hardware.\n"); 5765 break; 5766 default: 5767 e_dev_err("Hardware Error: %d\n", err); 5768 } 5769 5770 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5771 5772 /* flush entries out of MAC table */ 5773 ixgbe_flush_sw_mac_table(adapter); 5774 __dev_uc_unsync(netdev, NULL); 5775 5776 /* do not flush user set addresses */ 5777 ixgbe_mac_set_default_filter(adapter); 5778 5779 /* update SAN MAC vmdq pool selection */ 5780 if (hw->mac.san_mac_rar_index) 5781 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5782 5783 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5784 ixgbe_ptp_reset(adapter); 5785 5786 if (hw->phy.ops.set_phy_power) { 5787 if (!netif_running(adapter->netdev) && !adapter->wol) 5788 hw->phy.ops.set_phy_power(hw, false); 5789 else 5790 hw->phy.ops.set_phy_power(hw, true); 5791 } 5792 } 5793 5794 /** 5795 * ixgbe_clean_tx_ring - Free Tx Buffers 5796 * @tx_ring: ring to be cleaned 5797 **/ 5798 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5799 { 5800 u16 i = tx_ring->next_to_clean; 5801 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5802 5803 while (i != tx_ring->next_to_use) { 5804 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5805 5806 /* Free all the Tx ring sk_buffs */ 5807 if (ring_is_xdp(tx_ring)) 5808 xdp_return_frame(tx_buffer->xdpf); 5809 else 5810 dev_kfree_skb_any(tx_buffer->skb); 5811 5812 /* unmap skb header data */ 5813 dma_unmap_single(tx_ring->dev, 5814 dma_unmap_addr(tx_buffer, dma), 5815 dma_unmap_len(tx_buffer, len), 5816 DMA_TO_DEVICE); 5817 5818 /* check for eop_desc to determine the end of the packet */ 5819 eop_desc = tx_buffer->next_to_watch; 5820 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5821 5822 /* unmap remaining buffers */ 5823 while (tx_desc != eop_desc) { 5824 tx_buffer++; 5825 tx_desc++; 5826 i++; 5827 if (unlikely(i == tx_ring->count)) { 5828 i = 0; 5829 tx_buffer = tx_ring->tx_buffer_info; 5830 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5831 } 5832 5833 /* unmap any remaining paged data */ 5834 if (dma_unmap_len(tx_buffer, len)) 5835 dma_unmap_page(tx_ring->dev, 5836 dma_unmap_addr(tx_buffer, dma), 5837 dma_unmap_len(tx_buffer, len), 5838 DMA_TO_DEVICE); 5839 } 5840 5841 /* move us one more past the eop_desc for start of next pkt */ 5842 tx_buffer++; 5843 i++; 5844 if (unlikely(i == tx_ring->count)) { 5845 i = 0; 5846 tx_buffer = tx_ring->tx_buffer_info; 5847 } 5848 } 5849 5850 /* reset BQL for queue */ 5851 if (!ring_is_xdp(tx_ring)) 5852 netdev_tx_reset_queue(txring_txq(tx_ring)); 5853 5854 /* reset next_to_use and next_to_clean */ 5855 tx_ring->next_to_use = 0; 5856 tx_ring->next_to_clean = 0; 5857 } 5858 5859 /** 5860 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5861 * @adapter: board private structure 5862 **/ 5863 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5864 { 5865 int i; 5866 5867 for (i = 0; i < adapter->num_rx_queues; i++) 5868 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5869 } 5870 5871 /** 5872 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5873 * @adapter: board private structure 5874 **/ 5875 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5876 { 5877 int i; 5878 5879 for (i = 0; i < adapter->num_tx_queues; i++) 5880 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5881 for (i = 0; i < adapter->num_xdp_queues; i++) 5882 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5883 } 5884 5885 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5886 { 5887 struct hlist_node *node2; 5888 struct ixgbe_fdir_filter *filter; 5889 5890 spin_lock(&adapter->fdir_perfect_lock); 5891 5892 hlist_for_each_entry_safe(filter, node2, 5893 &adapter->fdir_filter_list, fdir_node) { 5894 hlist_del(&filter->fdir_node); 5895 kfree(filter); 5896 } 5897 adapter->fdir_filter_count = 0; 5898 5899 spin_unlock(&adapter->fdir_perfect_lock); 5900 } 5901 5902 void ixgbe_down(struct ixgbe_adapter *adapter) 5903 { 5904 struct net_device *netdev = adapter->netdev; 5905 struct ixgbe_hw *hw = &adapter->hw; 5906 int i; 5907 5908 /* signal that we are down to the interrupt handler */ 5909 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5910 return; /* do nothing if already down */ 5911 5912 /* disable receives */ 5913 hw->mac.ops.disable_rx(hw); 5914 5915 /* disable all enabled rx queues */ 5916 for (i = 0; i < adapter->num_rx_queues; i++) 5917 /* this call also flushes the previous write */ 5918 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5919 5920 usleep_range(10000, 20000); 5921 5922 /* synchronize_sched() needed for pending XDP buffers to drain */ 5923 if (adapter->xdp_ring[0]) 5924 synchronize_sched(); 5925 netif_tx_stop_all_queues(netdev); 5926 5927 /* call carrier off first to avoid false dev_watchdog timeouts */ 5928 netif_carrier_off(netdev); 5929 netif_tx_disable(netdev); 5930 5931 ixgbe_irq_disable(adapter); 5932 5933 ixgbe_napi_disable_all(adapter); 5934 5935 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5936 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5937 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5938 5939 del_timer_sync(&adapter->service_timer); 5940 5941 if (adapter->num_vfs) { 5942 /* Clear EITR Select mapping */ 5943 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5944 5945 /* Mark all the VFs as inactive */ 5946 for (i = 0 ; i < adapter->num_vfs; i++) 5947 adapter->vfinfo[i].clear_to_send = false; 5948 5949 /* ping all the active vfs to let them know we are going down */ 5950 ixgbe_ping_all_vfs(adapter); 5951 5952 /* Disable all VFTE/VFRE TX/RX */ 5953 ixgbe_disable_tx_rx(adapter); 5954 } 5955 5956 /* disable transmits in the hardware now that interrupts are off */ 5957 for (i = 0; i < adapter->num_tx_queues; i++) { 5958 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5959 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5960 } 5961 for (i = 0; i < adapter->num_xdp_queues; i++) { 5962 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5963 5964 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5965 } 5966 5967 /* Disable the Tx DMA engine on 82599 and later MAC */ 5968 switch (hw->mac.type) { 5969 case ixgbe_mac_82599EB: 5970 case ixgbe_mac_X540: 5971 case ixgbe_mac_X550: 5972 case ixgbe_mac_X550EM_x: 5973 case ixgbe_mac_x550em_a: 5974 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5975 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5976 ~IXGBE_DMATXCTL_TE)); 5977 break; 5978 default: 5979 break; 5980 } 5981 5982 if (!pci_channel_offline(adapter->pdev)) 5983 ixgbe_reset(adapter); 5984 5985 /* power down the optics for 82599 SFP+ fiber */ 5986 if (hw->mac.ops.disable_tx_laser) 5987 hw->mac.ops.disable_tx_laser(hw); 5988 5989 ixgbe_clean_all_tx_rings(adapter); 5990 ixgbe_clean_all_rx_rings(adapter); 5991 } 5992 5993 /** 5994 * ixgbe_eee_capable - helper function to determine EEE support on X550 5995 * @adapter: board private structure 5996 */ 5997 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5998 { 5999 struct ixgbe_hw *hw = &adapter->hw; 6000 6001 switch (hw->device_id) { 6002 case IXGBE_DEV_ID_X550EM_A_1G_T: 6003 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6004 if (!hw->phy.eee_speeds_supported) 6005 break; 6006 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6007 if (!hw->phy.eee_speeds_advertised) 6008 break; 6009 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6010 break; 6011 default: 6012 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6013 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6014 break; 6015 } 6016 } 6017 6018 /** 6019 * ixgbe_tx_timeout - Respond to a Tx Hang 6020 * @netdev: network interface device structure 6021 **/ 6022 static void ixgbe_tx_timeout(struct net_device *netdev) 6023 { 6024 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6025 6026 /* Do the reset outside of interrupt context */ 6027 ixgbe_tx_timeout_reset(adapter); 6028 } 6029 6030 #ifdef CONFIG_IXGBE_DCB 6031 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6032 { 6033 struct ixgbe_hw *hw = &adapter->hw; 6034 struct tc_configuration *tc; 6035 int j; 6036 6037 switch (hw->mac.type) { 6038 case ixgbe_mac_82598EB: 6039 case ixgbe_mac_82599EB: 6040 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6041 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6042 break; 6043 case ixgbe_mac_X540: 6044 case ixgbe_mac_X550: 6045 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6046 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6047 break; 6048 case ixgbe_mac_X550EM_x: 6049 case ixgbe_mac_x550em_a: 6050 default: 6051 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6052 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6053 break; 6054 } 6055 6056 /* Configure DCB traffic classes */ 6057 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6058 tc = &adapter->dcb_cfg.tc_config[j]; 6059 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6060 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6061 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6062 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6063 tc->dcb_pfc = pfc_disabled; 6064 } 6065 6066 /* Initialize default user to priority mapping, UPx->TC0 */ 6067 tc = &adapter->dcb_cfg.tc_config[0]; 6068 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6069 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6070 6071 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6072 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6073 adapter->dcb_cfg.pfc_mode_enable = false; 6074 adapter->dcb_set_bitmap = 0x00; 6075 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6076 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6077 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6078 sizeof(adapter->temp_dcb_cfg)); 6079 } 6080 #endif 6081 6082 /** 6083 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6084 * @adapter: board private structure to initialize 6085 * @ii: pointer to ixgbe_info for device 6086 * 6087 * ixgbe_sw_init initializes the Adapter private data structure. 6088 * Fields are initialized based on PCI device information and 6089 * OS network device settings (MTU size). 6090 **/ 6091 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6092 const struct ixgbe_info *ii) 6093 { 6094 struct ixgbe_hw *hw = &adapter->hw; 6095 struct pci_dev *pdev = adapter->pdev; 6096 unsigned int rss, fdir; 6097 u32 fwsm; 6098 int i; 6099 6100 /* PCI config space info */ 6101 6102 hw->vendor_id = pdev->vendor; 6103 hw->device_id = pdev->device; 6104 hw->revision_id = pdev->revision; 6105 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6106 hw->subsystem_device_id = pdev->subsystem_device; 6107 6108 /* get_invariants needs the device IDs */ 6109 ii->get_invariants(hw); 6110 6111 /* Set common capability flags and settings */ 6112 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6113 adapter->ring_feature[RING_F_RSS].limit = rss; 6114 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6115 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6116 adapter->atr_sample_rate = 20; 6117 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6118 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6119 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6120 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6121 #ifdef CONFIG_IXGBE_DCA 6122 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6123 #endif 6124 #ifdef CONFIG_IXGBE_DCB 6125 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6126 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6127 #endif 6128 #ifdef IXGBE_FCOE 6129 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6130 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6131 #ifdef CONFIG_IXGBE_DCB 6132 /* Default traffic class to use for FCoE */ 6133 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6134 #endif /* CONFIG_IXGBE_DCB */ 6135 #endif /* IXGBE_FCOE */ 6136 6137 /* initialize static ixgbe jump table entries */ 6138 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6139 GFP_KERNEL); 6140 if (!adapter->jump_tables[0]) 6141 return -ENOMEM; 6142 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6143 6144 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6145 adapter->jump_tables[i] = NULL; 6146 6147 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6148 hw->mac.num_rar_entries, 6149 GFP_ATOMIC); 6150 if (!adapter->mac_table) 6151 return -ENOMEM; 6152 6153 if (ixgbe_init_rss_key(adapter)) 6154 return -ENOMEM; 6155 6156 /* Set MAC specific capability flags and exceptions */ 6157 switch (hw->mac.type) { 6158 case ixgbe_mac_82598EB: 6159 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6160 6161 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6162 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6163 6164 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6165 adapter->ring_feature[RING_F_FDIR].limit = 0; 6166 adapter->atr_sample_rate = 0; 6167 adapter->fdir_pballoc = 0; 6168 #ifdef IXGBE_FCOE 6169 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6170 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6171 #ifdef CONFIG_IXGBE_DCB 6172 adapter->fcoe.up = 0; 6173 #endif /* IXGBE_DCB */ 6174 #endif /* IXGBE_FCOE */ 6175 break; 6176 case ixgbe_mac_82599EB: 6177 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6178 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6179 break; 6180 case ixgbe_mac_X540: 6181 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6182 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6183 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6184 break; 6185 case ixgbe_mac_x550em_a: 6186 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6187 switch (hw->device_id) { 6188 case IXGBE_DEV_ID_X550EM_A_1G_T: 6189 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6190 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6191 break; 6192 default: 6193 break; 6194 } 6195 /* fall through */ 6196 case ixgbe_mac_X550EM_x: 6197 #ifdef CONFIG_IXGBE_DCB 6198 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6199 #endif 6200 #ifdef IXGBE_FCOE 6201 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6202 #ifdef CONFIG_IXGBE_DCB 6203 adapter->fcoe.up = 0; 6204 #endif /* IXGBE_DCB */ 6205 #endif /* IXGBE_FCOE */ 6206 /* Fall Through */ 6207 case ixgbe_mac_X550: 6208 if (hw->mac.type == ixgbe_mac_X550) 6209 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6210 #ifdef CONFIG_IXGBE_DCA 6211 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6212 #endif 6213 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6214 break; 6215 default: 6216 break; 6217 } 6218 6219 #ifdef IXGBE_FCOE 6220 /* FCoE support exists, always init the FCoE lock */ 6221 spin_lock_init(&adapter->fcoe.lock); 6222 6223 #endif 6224 /* n-tuple support exists, always init our spinlock */ 6225 spin_lock_init(&adapter->fdir_perfect_lock); 6226 6227 #ifdef CONFIG_IXGBE_DCB 6228 ixgbe_init_dcb(adapter); 6229 #endif 6230 6231 /* default flow control settings */ 6232 hw->fc.requested_mode = ixgbe_fc_full; 6233 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6234 ixgbe_pbthresh_setup(adapter); 6235 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6236 hw->fc.send_xon = true; 6237 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6238 6239 #ifdef CONFIG_PCI_IOV 6240 if (max_vfs > 0) 6241 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6242 6243 /* assign number of SR-IOV VFs */ 6244 if (hw->mac.type != ixgbe_mac_82598EB) { 6245 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6246 max_vfs = 0; 6247 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6248 } 6249 } 6250 #endif /* CONFIG_PCI_IOV */ 6251 6252 /* enable itr by default in dynamic mode */ 6253 adapter->rx_itr_setting = 1; 6254 adapter->tx_itr_setting = 1; 6255 6256 /* set default ring sizes */ 6257 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6258 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6259 6260 /* set default work limits */ 6261 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6262 6263 /* initialize eeprom parameters */ 6264 if (ixgbe_init_eeprom_params_generic(hw)) { 6265 e_dev_err("EEPROM initialization failed\n"); 6266 return -EIO; 6267 } 6268 6269 /* PF holds first pool slot */ 6270 set_bit(0, adapter->fwd_bitmask); 6271 set_bit(__IXGBE_DOWN, &adapter->state); 6272 6273 return 0; 6274 } 6275 6276 /** 6277 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6278 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6279 * 6280 * Return 0 on success, negative on failure 6281 **/ 6282 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6283 { 6284 struct device *dev = tx_ring->dev; 6285 int orig_node = dev_to_node(dev); 6286 int ring_node = -1; 6287 int size; 6288 6289 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6290 6291 if (tx_ring->q_vector) 6292 ring_node = tx_ring->q_vector->numa_node; 6293 6294 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6295 if (!tx_ring->tx_buffer_info) 6296 tx_ring->tx_buffer_info = vmalloc(size); 6297 if (!tx_ring->tx_buffer_info) 6298 goto err; 6299 6300 /* round up to nearest 4K */ 6301 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6302 tx_ring->size = ALIGN(tx_ring->size, 4096); 6303 6304 set_dev_node(dev, ring_node); 6305 tx_ring->desc = dma_alloc_coherent(dev, 6306 tx_ring->size, 6307 &tx_ring->dma, 6308 GFP_KERNEL); 6309 set_dev_node(dev, orig_node); 6310 if (!tx_ring->desc) 6311 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6312 &tx_ring->dma, GFP_KERNEL); 6313 if (!tx_ring->desc) 6314 goto err; 6315 6316 tx_ring->next_to_use = 0; 6317 tx_ring->next_to_clean = 0; 6318 return 0; 6319 6320 err: 6321 vfree(tx_ring->tx_buffer_info); 6322 tx_ring->tx_buffer_info = NULL; 6323 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6324 return -ENOMEM; 6325 } 6326 6327 /** 6328 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6329 * @adapter: board private structure 6330 * 6331 * If this function returns with an error, then it's possible one or 6332 * more of the rings is populated (while the rest are not). It is the 6333 * callers duty to clean those orphaned rings. 6334 * 6335 * Return 0 on success, negative on failure 6336 **/ 6337 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6338 { 6339 int i, j = 0, err = 0; 6340 6341 for (i = 0; i < adapter->num_tx_queues; i++) { 6342 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6343 if (!err) 6344 continue; 6345 6346 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6347 goto err_setup_tx; 6348 } 6349 for (j = 0; j < adapter->num_xdp_queues; j++) { 6350 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6351 if (!err) 6352 continue; 6353 6354 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6355 goto err_setup_tx; 6356 } 6357 6358 return 0; 6359 err_setup_tx: 6360 /* rewind the index freeing the rings as we go */ 6361 while (j--) 6362 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6363 while (i--) 6364 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6365 return err; 6366 } 6367 6368 /** 6369 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6370 * @adapter: pointer to ixgbe_adapter 6371 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6372 * 6373 * Returns 0 on success, negative on failure 6374 **/ 6375 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6376 struct ixgbe_ring *rx_ring) 6377 { 6378 struct device *dev = rx_ring->dev; 6379 int orig_node = dev_to_node(dev); 6380 int ring_node = -1; 6381 int size, err; 6382 6383 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6384 6385 if (rx_ring->q_vector) 6386 ring_node = rx_ring->q_vector->numa_node; 6387 6388 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6389 if (!rx_ring->rx_buffer_info) 6390 rx_ring->rx_buffer_info = vmalloc(size); 6391 if (!rx_ring->rx_buffer_info) 6392 goto err; 6393 6394 /* Round up to nearest 4K */ 6395 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6396 rx_ring->size = ALIGN(rx_ring->size, 4096); 6397 6398 set_dev_node(dev, ring_node); 6399 rx_ring->desc = dma_alloc_coherent(dev, 6400 rx_ring->size, 6401 &rx_ring->dma, 6402 GFP_KERNEL); 6403 set_dev_node(dev, orig_node); 6404 if (!rx_ring->desc) 6405 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6406 &rx_ring->dma, GFP_KERNEL); 6407 if (!rx_ring->desc) 6408 goto err; 6409 6410 rx_ring->next_to_clean = 0; 6411 rx_ring->next_to_use = 0; 6412 6413 /* XDP RX-queue info */ 6414 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6415 rx_ring->queue_index) < 0) 6416 goto err; 6417 6418 err = xdp_rxq_info_reg_mem_model(&rx_ring->xdp_rxq, 6419 MEM_TYPE_PAGE_SHARED, NULL); 6420 if (err) { 6421 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6422 goto err; 6423 } 6424 6425 rx_ring->xdp_prog = adapter->xdp_prog; 6426 6427 return 0; 6428 err: 6429 vfree(rx_ring->rx_buffer_info); 6430 rx_ring->rx_buffer_info = NULL; 6431 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6432 return -ENOMEM; 6433 } 6434 6435 /** 6436 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6437 * @adapter: board private structure 6438 * 6439 * If this function returns with an error, then it's possible one or 6440 * more of the rings is populated (while the rest are not). It is the 6441 * callers duty to clean those orphaned rings. 6442 * 6443 * Return 0 on success, negative on failure 6444 **/ 6445 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6446 { 6447 int i, err = 0; 6448 6449 for (i = 0; i < adapter->num_rx_queues; i++) { 6450 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6451 if (!err) 6452 continue; 6453 6454 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6455 goto err_setup_rx; 6456 } 6457 6458 #ifdef IXGBE_FCOE 6459 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6460 if (!err) 6461 #endif 6462 return 0; 6463 err_setup_rx: 6464 /* rewind the index freeing the rings as we go */ 6465 while (i--) 6466 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6467 return err; 6468 } 6469 6470 /** 6471 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6472 * @tx_ring: Tx descriptor ring for a specific queue 6473 * 6474 * Free all transmit software resources 6475 **/ 6476 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6477 { 6478 ixgbe_clean_tx_ring(tx_ring); 6479 6480 vfree(tx_ring->tx_buffer_info); 6481 tx_ring->tx_buffer_info = NULL; 6482 6483 /* if not set, then don't free */ 6484 if (!tx_ring->desc) 6485 return; 6486 6487 dma_free_coherent(tx_ring->dev, tx_ring->size, 6488 tx_ring->desc, tx_ring->dma); 6489 6490 tx_ring->desc = NULL; 6491 } 6492 6493 /** 6494 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6495 * @adapter: board private structure 6496 * 6497 * Free all transmit software resources 6498 **/ 6499 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6500 { 6501 int i; 6502 6503 for (i = 0; i < adapter->num_tx_queues; i++) 6504 if (adapter->tx_ring[i]->desc) 6505 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6506 for (i = 0; i < adapter->num_xdp_queues; i++) 6507 if (adapter->xdp_ring[i]->desc) 6508 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6509 } 6510 6511 /** 6512 * ixgbe_free_rx_resources - Free Rx Resources 6513 * @rx_ring: ring to clean the resources from 6514 * 6515 * Free all receive software resources 6516 **/ 6517 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6518 { 6519 ixgbe_clean_rx_ring(rx_ring); 6520 6521 rx_ring->xdp_prog = NULL; 6522 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6523 vfree(rx_ring->rx_buffer_info); 6524 rx_ring->rx_buffer_info = NULL; 6525 6526 /* if not set, then don't free */ 6527 if (!rx_ring->desc) 6528 return; 6529 6530 dma_free_coherent(rx_ring->dev, rx_ring->size, 6531 rx_ring->desc, rx_ring->dma); 6532 6533 rx_ring->desc = NULL; 6534 } 6535 6536 /** 6537 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6538 * @adapter: board private structure 6539 * 6540 * Free all receive software resources 6541 **/ 6542 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6543 { 6544 int i; 6545 6546 #ifdef IXGBE_FCOE 6547 ixgbe_free_fcoe_ddp_resources(adapter); 6548 6549 #endif 6550 for (i = 0; i < adapter->num_rx_queues; i++) 6551 if (adapter->rx_ring[i]->desc) 6552 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6553 } 6554 6555 /** 6556 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6557 * @netdev: network interface device structure 6558 * @new_mtu: new value for maximum frame size 6559 * 6560 * Returns 0 on success, negative on failure 6561 **/ 6562 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6563 { 6564 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6565 6566 /* 6567 * For 82599EB we cannot allow legacy VFs to enable their receive 6568 * paths when MTU greater than 1500 is configured. So display a 6569 * warning that legacy VFs will be disabled. 6570 */ 6571 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6572 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6573 (new_mtu > ETH_DATA_LEN)) 6574 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6575 6576 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6577 6578 /* must set new MTU before calling down or up */ 6579 netdev->mtu = new_mtu; 6580 6581 if (netif_running(netdev)) 6582 ixgbe_reinit_locked(adapter); 6583 6584 return 0; 6585 } 6586 6587 /** 6588 * ixgbe_open - Called when a network interface is made active 6589 * @netdev: network interface device structure 6590 * 6591 * Returns 0 on success, negative value on failure 6592 * 6593 * The open entry point is called when a network interface is made 6594 * active by the system (IFF_UP). At this point all resources needed 6595 * for transmit and receive operations are allocated, the interrupt 6596 * handler is registered with the OS, the watchdog timer is started, 6597 * and the stack is notified that the interface is ready. 6598 **/ 6599 int ixgbe_open(struct net_device *netdev) 6600 { 6601 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6602 struct ixgbe_hw *hw = &adapter->hw; 6603 int err, queues; 6604 6605 /* disallow open during test */ 6606 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6607 return -EBUSY; 6608 6609 netif_carrier_off(netdev); 6610 6611 /* allocate transmit descriptors */ 6612 err = ixgbe_setup_all_tx_resources(adapter); 6613 if (err) 6614 goto err_setup_tx; 6615 6616 /* allocate receive descriptors */ 6617 err = ixgbe_setup_all_rx_resources(adapter); 6618 if (err) 6619 goto err_setup_rx; 6620 6621 ixgbe_configure(adapter); 6622 6623 err = ixgbe_request_irq(adapter); 6624 if (err) 6625 goto err_req_irq; 6626 6627 /* Notify the stack of the actual queue counts. */ 6628 queues = adapter->num_tx_queues; 6629 err = netif_set_real_num_tx_queues(netdev, queues); 6630 if (err) 6631 goto err_set_queues; 6632 6633 queues = adapter->num_rx_queues; 6634 err = netif_set_real_num_rx_queues(netdev, queues); 6635 if (err) 6636 goto err_set_queues; 6637 6638 ixgbe_ptp_init(adapter); 6639 6640 ixgbe_up_complete(adapter); 6641 6642 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6643 udp_tunnel_get_rx_info(netdev); 6644 6645 return 0; 6646 6647 err_set_queues: 6648 ixgbe_free_irq(adapter); 6649 err_req_irq: 6650 ixgbe_free_all_rx_resources(adapter); 6651 if (hw->phy.ops.set_phy_power && !adapter->wol) 6652 hw->phy.ops.set_phy_power(&adapter->hw, false); 6653 err_setup_rx: 6654 ixgbe_free_all_tx_resources(adapter); 6655 err_setup_tx: 6656 ixgbe_reset(adapter); 6657 6658 return err; 6659 } 6660 6661 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6662 { 6663 ixgbe_ptp_suspend(adapter); 6664 6665 if (adapter->hw.phy.ops.enter_lplu) { 6666 adapter->hw.phy.reset_disable = true; 6667 ixgbe_down(adapter); 6668 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6669 adapter->hw.phy.reset_disable = false; 6670 } else { 6671 ixgbe_down(adapter); 6672 } 6673 6674 ixgbe_free_irq(adapter); 6675 6676 ixgbe_free_all_tx_resources(adapter); 6677 ixgbe_free_all_rx_resources(adapter); 6678 } 6679 6680 /** 6681 * ixgbe_close - Disables a network interface 6682 * @netdev: network interface device structure 6683 * 6684 * Returns 0, this is not allowed to fail 6685 * 6686 * The close entry point is called when an interface is de-activated 6687 * by the OS. The hardware is still under the drivers control, but 6688 * needs to be disabled. A global MAC reset is issued to stop the 6689 * hardware, and all transmit and receive resources are freed. 6690 **/ 6691 int ixgbe_close(struct net_device *netdev) 6692 { 6693 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6694 6695 ixgbe_ptp_stop(adapter); 6696 6697 if (netif_device_present(netdev)) 6698 ixgbe_close_suspend(adapter); 6699 6700 ixgbe_fdir_filter_exit(adapter); 6701 6702 ixgbe_release_hw_control(adapter); 6703 6704 return 0; 6705 } 6706 6707 #ifdef CONFIG_PM 6708 static int ixgbe_resume(struct pci_dev *pdev) 6709 { 6710 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6711 struct net_device *netdev = adapter->netdev; 6712 u32 err; 6713 6714 adapter->hw.hw_addr = adapter->io_addr; 6715 pci_set_power_state(pdev, PCI_D0); 6716 pci_restore_state(pdev); 6717 /* 6718 * pci_restore_state clears dev->state_saved so call 6719 * pci_save_state to restore it. 6720 */ 6721 pci_save_state(pdev); 6722 6723 err = pci_enable_device_mem(pdev); 6724 if (err) { 6725 e_dev_err("Cannot enable PCI device from suspend\n"); 6726 return err; 6727 } 6728 smp_mb__before_atomic(); 6729 clear_bit(__IXGBE_DISABLED, &adapter->state); 6730 pci_set_master(pdev); 6731 6732 pci_wake_from_d3(pdev, false); 6733 6734 ixgbe_reset(adapter); 6735 6736 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6737 6738 rtnl_lock(); 6739 err = ixgbe_init_interrupt_scheme(adapter); 6740 if (!err && netif_running(netdev)) 6741 err = ixgbe_open(netdev); 6742 6743 6744 if (!err) 6745 netif_device_attach(netdev); 6746 rtnl_unlock(); 6747 6748 return err; 6749 } 6750 #endif /* CONFIG_PM */ 6751 6752 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6753 { 6754 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6755 struct net_device *netdev = adapter->netdev; 6756 struct ixgbe_hw *hw = &adapter->hw; 6757 u32 ctrl; 6758 u32 wufc = adapter->wol; 6759 #ifdef CONFIG_PM 6760 int retval = 0; 6761 #endif 6762 6763 rtnl_lock(); 6764 netif_device_detach(netdev); 6765 6766 if (netif_running(netdev)) 6767 ixgbe_close_suspend(adapter); 6768 6769 ixgbe_clear_interrupt_scheme(adapter); 6770 rtnl_unlock(); 6771 6772 #ifdef CONFIG_PM 6773 retval = pci_save_state(pdev); 6774 if (retval) 6775 return retval; 6776 6777 #endif 6778 if (hw->mac.ops.stop_link_on_d3) 6779 hw->mac.ops.stop_link_on_d3(hw); 6780 6781 if (wufc) { 6782 u32 fctrl; 6783 6784 ixgbe_set_rx_mode(netdev); 6785 6786 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6787 if (hw->mac.ops.enable_tx_laser) 6788 hw->mac.ops.enable_tx_laser(hw); 6789 6790 /* enable the reception of multicast packets */ 6791 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6792 fctrl |= IXGBE_FCTRL_MPE; 6793 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6794 6795 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6796 ctrl |= IXGBE_CTRL_GIO_DIS; 6797 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6798 6799 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6800 } else { 6801 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6802 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6803 } 6804 6805 switch (hw->mac.type) { 6806 case ixgbe_mac_82598EB: 6807 pci_wake_from_d3(pdev, false); 6808 break; 6809 case ixgbe_mac_82599EB: 6810 case ixgbe_mac_X540: 6811 case ixgbe_mac_X550: 6812 case ixgbe_mac_X550EM_x: 6813 case ixgbe_mac_x550em_a: 6814 pci_wake_from_d3(pdev, !!wufc); 6815 break; 6816 default: 6817 break; 6818 } 6819 6820 *enable_wake = !!wufc; 6821 if (hw->phy.ops.set_phy_power && !*enable_wake) 6822 hw->phy.ops.set_phy_power(hw, false); 6823 6824 ixgbe_release_hw_control(adapter); 6825 6826 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6827 pci_disable_device(pdev); 6828 6829 return 0; 6830 } 6831 6832 #ifdef CONFIG_PM 6833 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6834 { 6835 int retval; 6836 bool wake; 6837 6838 retval = __ixgbe_shutdown(pdev, &wake); 6839 if (retval) 6840 return retval; 6841 6842 if (wake) { 6843 pci_prepare_to_sleep(pdev); 6844 } else { 6845 pci_wake_from_d3(pdev, false); 6846 pci_set_power_state(pdev, PCI_D3hot); 6847 } 6848 6849 return 0; 6850 } 6851 #endif /* CONFIG_PM */ 6852 6853 static void ixgbe_shutdown(struct pci_dev *pdev) 6854 { 6855 bool wake; 6856 6857 __ixgbe_shutdown(pdev, &wake); 6858 6859 if (system_state == SYSTEM_POWER_OFF) { 6860 pci_wake_from_d3(pdev, wake); 6861 pci_set_power_state(pdev, PCI_D3hot); 6862 } 6863 } 6864 6865 /** 6866 * ixgbe_update_stats - Update the board statistics counters. 6867 * @adapter: board private structure 6868 **/ 6869 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6870 { 6871 struct net_device *netdev = adapter->netdev; 6872 struct ixgbe_hw *hw = &adapter->hw; 6873 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6874 u64 total_mpc = 0; 6875 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6876 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6877 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6878 u64 alloc_rx_page = 0; 6879 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6880 6881 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6882 test_bit(__IXGBE_RESETTING, &adapter->state)) 6883 return; 6884 6885 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6886 u64 rsc_count = 0; 6887 u64 rsc_flush = 0; 6888 for (i = 0; i < adapter->num_rx_queues; i++) { 6889 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6890 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6891 } 6892 adapter->rsc_total_count = rsc_count; 6893 adapter->rsc_total_flush = rsc_flush; 6894 } 6895 6896 for (i = 0; i < adapter->num_rx_queues; i++) { 6897 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6898 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6899 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 6900 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6901 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6902 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6903 bytes += rx_ring->stats.bytes; 6904 packets += rx_ring->stats.packets; 6905 } 6906 adapter->non_eop_descs = non_eop_descs; 6907 adapter->alloc_rx_page = alloc_rx_page; 6908 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6909 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6910 adapter->hw_csum_rx_error = hw_csum_rx_error; 6911 netdev->stats.rx_bytes = bytes; 6912 netdev->stats.rx_packets = packets; 6913 6914 bytes = 0; 6915 packets = 0; 6916 /* gather some stats to the adapter struct that are per queue */ 6917 for (i = 0; i < adapter->num_tx_queues; i++) { 6918 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6919 restart_queue += tx_ring->tx_stats.restart_queue; 6920 tx_busy += tx_ring->tx_stats.tx_busy; 6921 bytes += tx_ring->stats.bytes; 6922 packets += tx_ring->stats.packets; 6923 } 6924 for (i = 0; i < adapter->num_xdp_queues; i++) { 6925 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6926 6927 restart_queue += xdp_ring->tx_stats.restart_queue; 6928 tx_busy += xdp_ring->tx_stats.tx_busy; 6929 bytes += xdp_ring->stats.bytes; 6930 packets += xdp_ring->stats.packets; 6931 } 6932 adapter->restart_queue = restart_queue; 6933 adapter->tx_busy = tx_busy; 6934 netdev->stats.tx_bytes = bytes; 6935 netdev->stats.tx_packets = packets; 6936 6937 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6938 6939 /* 8 register reads */ 6940 for (i = 0; i < 8; i++) { 6941 /* for packet buffers not used, the register should read 0 */ 6942 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6943 missed_rx += mpc; 6944 hwstats->mpc[i] += mpc; 6945 total_mpc += hwstats->mpc[i]; 6946 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6947 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6948 switch (hw->mac.type) { 6949 case ixgbe_mac_82598EB: 6950 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6951 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6952 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6953 hwstats->pxonrxc[i] += 6954 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6955 break; 6956 case ixgbe_mac_82599EB: 6957 case ixgbe_mac_X540: 6958 case ixgbe_mac_X550: 6959 case ixgbe_mac_X550EM_x: 6960 case ixgbe_mac_x550em_a: 6961 hwstats->pxonrxc[i] += 6962 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6963 break; 6964 default: 6965 break; 6966 } 6967 } 6968 6969 /*16 register reads */ 6970 for (i = 0; i < 16; i++) { 6971 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6972 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6973 if ((hw->mac.type == ixgbe_mac_82599EB) || 6974 (hw->mac.type == ixgbe_mac_X540) || 6975 (hw->mac.type == ixgbe_mac_X550) || 6976 (hw->mac.type == ixgbe_mac_X550EM_x) || 6977 (hw->mac.type == ixgbe_mac_x550em_a)) { 6978 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6979 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6980 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6981 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6982 } 6983 } 6984 6985 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6986 /* work around hardware counting issue */ 6987 hwstats->gprc -= missed_rx; 6988 6989 ixgbe_update_xoff_received(adapter); 6990 6991 /* 82598 hardware only has a 32 bit counter in the high register */ 6992 switch (hw->mac.type) { 6993 case ixgbe_mac_82598EB: 6994 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6995 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6996 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6997 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6998 break; 6999 case ixgbe_mac_X540: 7000 case ixgbe_mac_X550: 7001 case ixgbe_mac_X550EM_x: 7002 case ixgbe_mac_x550em_a: 7003 /* OS2BMC stats are X540 and later */ 7004 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7005 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7006 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7007 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7008 /* fall through */ 7009 case ixgbe_mac_82599EB: 7010 for (i = 0; i < 16; i++) 7011 adapter->hw_rx_no_dma_resources += 7012 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7013 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7014 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7015 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7016 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7017 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7018 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7019 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7020 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7021 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7022 #ifdef IXGBE_FCOE 7023 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7024 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7025 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7026 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7027 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7028 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7029 /* Add up per cpu counters for total ddp aloc fail */ 7030 if (adapter->fcoe.ddp_pool) { 7031 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7032 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7033 unsigned int cpu; 7034 u64 noddp = 0, noddp_ext_buff = 0; 7035 for_each_possible_cpu(cpu) { 7036 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7037 noddp += ddp_pool->noddp; 7038 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7039 } 7040 hwstats->fcoe_noddp = noddp; 7041 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7042 } 7043 #endif /* IXGBE_FCOE */ 7044 break; 7045 default: 7046 break; 7047 } 7048 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7049 hwstats->bprc += bprc; 7050 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7051 if (hw->mac.type == ixgbe_mac_82598EB) 7052 hwstats->mprc -= bprc; 7053 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7054 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7055 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7056 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7057 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7058 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7059 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7060 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7061 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7062 hwstats->lxontxc += lxon; 7063 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7064 hwstats->lxofftxc += lxoff; 7065 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7066 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7067 /* 7068 * 82598 errata - tx of flow control packets is included in tx counters 7069 */ 7070 xon_off_tot = lxon + lxoff; 7071 hwstats->gptc -= xon_off_tot; 7072 hwstats->mptc -= xon_off_tot; 7073 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7074 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7075 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7076 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7077 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7078 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7079 hwstats->ptc64 -= xon_off_tot; 7080 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7081 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7082 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7083 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7084 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7085 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7086 7087 /* Fill out the OS statistics structure */ 7088 netdev->stats.multicast = hwstats->mprc; 7089 7090 /* Rx Errors */ 7091 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7092 netdev->stats.rx_dropped = 0; 7093 netdev->stats.rx_length_errors = hwstats->rlec; 7094 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7095 netdev->stats.rx_missed_errors = total_mpc; 7096 } 7097 7098 /** 7099 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7100 * @adapter: pointer to the device adapter structure 7101 **/ 7102 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7103 { 7104 struct ixgbe_hw *hw = &adapter->hw; 7105 int i; 7106 7107 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7108 return; 7109 7110 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7111 7112 /* if interface is down do nothing */ 7113 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7114 return; 7115 7116 /* do nothing if we are not using signature filters */ 7117 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7118 return; 7119 7120 adapter->fdir_overflow++; 7121 7122 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7123 for (i = 0; i < adapter->num_tx_queues; i++) 7124 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7125 &(adapter->tx_ring[i]->state)); 7126 for (i = 0; i < adapter->num_xdp_queues; i++) 7127 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7128 &adapter->xdp_ring[i]->state); 7129 /* re-enable flow director interrupts */ 7130 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7131 } else { 7132 e_err(probe, "failed to finish FDIR re-initialization, " 7133 "ignored adding FDIR ATR filters\n"); 7134 } 7135 } 7136 7137 /** 7138 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7139 * @adapter: pointer to the device adapter structure 7140 * 7141 * This function serves two purposes. First it strobes the interrupt lines 7142 * in order to make certain interrupts are occurring. Secondly it sets the 7143 * bits needed to check for TX hangs. As a result we should immediately 7144 * determine if a hang has occurred. 7145 */ 7146 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7147 { 7148 struct ixgbe_hw *hw = &adapter->hw; 7149 u64 eics = 0; 7150 int i; 7151 7152 /* If we're down, removing or resetting, just bail */ 7153 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7154 test_bit(__IXGBE_REMOVING, &adapter->state) || 7155 test_bit(__IXGBE_RESETTING, &adapter->state)) 7156 return; 7157 7158 /* Force detection of hung controller */ 7159 if (netif_carrier_ok(adapter->netdev)) { 7160 for (i = 0; i < adapter->num_tx_queues; i++) 7161 set_check_for_tx_hang(adapter->tx_ring[i]); 7162 for (i = 0; i < adapter->num_xdp_queues; i++) 7163 set_check_for_tx_hang(adapter->xdp_ring[i]); 7164 } 7165 7166 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7167 /* 7168 * for legacy and MSI interrupts don't set any bits 7169 * that are enabled for EIAM, because this operation 7170 * would set *both* EIMS and EICS for any bit in EIAM 7171 */ 7172 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7173 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7174 } else { 7175 /* get one bit for every active tx/rx interrupt vector */ 7176 for (i = 0; i < adapter->num_q_vectors; i++) { 7177 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7178 if (qv->rx.ring || qv->tx.ring) 7179 eics |= BIT_ULL(i); 7180 } 7181 } 7182 7183 /* Cause software interrupt to ensure rings are cleaned */ 7184 ixgbe_irq_rearm_queues(adapter, eics); 7185 } 7186 7187 /** 7188 * ixgbe_watchdog_update_link - update the link status 7189 * @adapter: pointer to the device adapter structure 7190 **/ 7191 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7192 { 7193 struct ixgbe_hw *hw = &adapter->hw; 7194 u32 link_speed = adapter->link_speed; 7195 bool link_up = adapter->link_up; 7196 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7197 7198 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7199 return; 7200 7201 if (hw->mac.ops.check_link) { 7202 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7203 } else { 7204 /* always assume link is up, if no check link function */ 7205 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7206 link_up = true; 7207 } 7208 7209 if (adapter->ixgbe_ieee_pfc) 7210 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7211 7212 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7213 hw->mac.ops.fc_enable(hw); 7214 ixgbe_set_rx_drop_en(adapter); 7215 } 7216 7217 if (link_up || 7218 time_after(jiffies, (adapter->link_check_timeout + 7219 IXGBE_TRY_LINK_TIMEOUT))) { 7220 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7221 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7222 IXGBE_WRITE_FLUSH(hw); 7223 } 7224 7225 adapter->link_up = link_up; 7226 adapter->link_speed = link_speed; 7227 } 7228 7229 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7230 { 7231 #ifdef CONFIG_IXGBE_DCB 7232 struct net_device *netdev = adapter->netdev; 7233 struct dcb_app app = { 7234 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7235 .protocol = 0, 7236 }; 7237 u8 up = 0; 7238 7239 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7240 up = dcb_ieee_getapp_mask(netdev, &app); 7241 7242 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7243 #endif 7244 } 7245 7246 /** 7247 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7248 * print link up message 7249 * @adapter: pointer to the device adapter structure 7250 **/ 7251 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7252 { 7253 struct net_device *netdev = adapter->netdev; 7254 struct ixgbe_hw *hw = &adapter->hw; 7255 u32 link_speed = adapter->link_speed; 7256 const char *speed_str; 7257 bool flow_rx, flow_tx; 7258 7259 /* only continue if link was previously down */ 7260 if (netif_carrier_ok(netdev)) 7261 return; 7262 7263 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7264 7265 switch (hw->mac.type) { 7266 case ixgbe_mac_82598EB: { 7267 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7268 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7269 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7270 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7271 } 7272 break; 7273 case ixgbe_mac_X540: 7274 case ixgbe_mac_X550: 7275 case ixgbe_mac_X550EM_x: 7276 case ixgbe_mac_x550em_a: 7277 case ixgbe_mac_82599EB: { 7278 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7279 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7280 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7281 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7282 } 7283 break; 7284 default: 7285 flow_tx = false; 7286 flow_rx = false; 7287 break; 7288 } 7289 7290 adapter->last_rx_ptp_check = jiffies; 7291 7292 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7293 ixgbe_ptp_start_cyclecounter(adapter); 7294 7295 switch (link_speed) { 7296 case IXGBE_LINK_SPEED_10GB_FULL: 7297 speed_str = "10 Gbps"; 7298 break; 7299 case IXGBE_LINK_SPEED_5GB_FULL: 7300 speed_str = "5 Gbps"; 7301 break; 7302 case IXGBE_LINK_SPEED_2_5GB_FULL: 7303 speed_str = "2.5 Gbps"; 7304 break; 7305 case IXGBE_LINK_SPEED_1GB_FULL: 7306 speed_str = "1 Gbps"; 7307 break; 7308 case IXGBE_LINK_SPEED_100_FULL: 7309 speed_str = "100 Mbps"; 7310 break; 7311 case IXGBE_LINK_SPEED_10_FULL: 7312 speed_str = "10 Mbps"; 7313 break; 7314 default: 7315 speed_str = "unknown speed"; 7316 break; 7317 } 7318 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7319 ((flow_rx && flow_tx) ? "RX/TX" : 7320 (flow_rx ? "RX" : 7321 (flow_tx ? "TX" : "None")))); 7322 7323 netif_carrier_on(netdev); 7324 ixgbe_check_vf_rate_limit(adapter); 7325 7326 /* enable transmits */ 7327 netif_tx_wake_all_queues(adapter->netdev); 7328 7329 /* update the default user priority for VFs */ 7330 ixgbe_update_default_up(adapter); 7331 7332 /* ping all the active vfs to let them know link has changed */ 7333 ixgbe_ping_all_vfs(adapter); 7334 } 7335 7336 /** 7337 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7338 * print link down message 7339 * @adapter: pointer to the adapter structure 7340 **/ 7341 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7342 { 7343 struct net_device *netdev = adapter->netdev; 7344 struct ixgbe_hw *hw = &adapter->hw; 7345 7346 adapter->link_up = false; 7347 adapter->link_speed = 0; 7348 7349 /* only continue if link was up previously */ 7350 if (!netif_carrier_ok(netdev)) 7351 return; 7352 7353 /* poll for SFP+ cable when link is down */ 7354 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7355 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7356 7357 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7358 ixgbe_ptp_start_cyclecounter(adapter); 7359 7360 e_info(drv, "NIC Link is Down\n"); 7361 netif_carrier_off(netdev); 7362 7363 /* ping all the active vfs to let them know link has changed */ 7364 ixgbe_ping_all_vfs(adapter); 7365 } 7366 7367 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7368 { 7369 int i; 7370 7371 for (i = 0; i < adapter->num_tx_queues; i++) { 7372 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7373 7374 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7375 return true; 7376 } 7377 7378 for (i = 0; i < adapter->num_xdp_queues; i++) { 7379 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7380 7381 if (ring->next_to_use != ring->next_to_clean) 7382 return true; 7383 } 7384 7385 return false; 7386 } 7387 7388 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7389 { 7390 struct ixgbe_hw *hw = &adapter->hw; 7391 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7392 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7393 7394 int i, j; 7395 7396 if (!adapter->num_vfs) 7397 return false; 7398 7399 /* resetting the PF is only needed for MAC before X550 */ 7400 if (hw->mac.type >= ixgbe_mac_X550) 7401 return false; 7402 7403 for (i = 0; i < adapter->num_vfs; i++) { 7404 for (j = 0; j < q_per_pool; j++) { 7405 u32 h, t; 7406 7407 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7408 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7409 7410 if (h != t) 7411 return true; 7412 } 7413 } 7414 7415 return false; 7416 } 7417 7418 /** 7419 * ixgbe_watchdog_flush_tx - flush queues on link down 7420 * @adapter: pointer to the device adapter structure 7421 **/ 7422 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7423 { 7424 if (!netif_carrier_ok(adapter->netdev)) { 7425 if (ixgbe_ring_tx_pending(adapter) || 7426 ixgbe_vf_tx_pending(adapter)) { 7427 /* We've lost link, so the controller stops DMA, 7428 * but we've got queued Tx work that's never going 7429 * to get done, so reset controller to flush Tx. 7430 * (Do the reset outside of interrupt context). 7431 */ 7432 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7433 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7434 } 7435 } 7436 } 7437 7438 #ifdef CONFIG_PCI_IOV 7439 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7440 { 7441 struct ixgbe_hw *hw = &adapter->hw; 7442 struct pci_dev *pdev = adapter->pdev; 7443 unsigned int vf; 7444 u32 gpc; 7445 7446 if (!(netif_carrier_ok(adapter->netdev))) 7447 return; 7448 7449 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7450 if (gpc) /* If incrementing then no need for the check below */ 7451 return; 7452 /* Check to see if a bad DMA write target from an errant or 7453 * malicious VF has caused a PCIe error. If so then we can 7454 * issue a VFLR to the offending VF(s) and then resume without 7455 * requesting a full slot reset. 7456 */ 7457 7458 if (!pdev) 7459 return; 7460 7461 /* check status reg for all VFs owned by this PF */ 7462 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7463 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7464 u16 status_reg; 7465 7466 if (!vfdev) 7467 continue; 7468 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7469 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7470 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7471 pcie_flr(vfdev); 7472 } 7473 } 7474 7475 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7476 { 7477 u32 ssvpc; 7478 7479 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7480 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7481 adapter->num_vfs == 0) 7482 return; 7483 7484 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7485 7486 /* 7487 * ssvpc register is cleared on read, if zero then no 7488 * spoofed packets in the last interval. 7489 */ 7490 if (!ssvpc) 7491 return; 7492 7493 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7494 } 7495 #else 7496 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7497 { 7498 } 7499 7500 static void 7501 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7502 { 7503 } 7504 #endif /* CONFIG_PCI_IOV */ 7505 7506 7507 /** 7508 * ixgbe_watchdog_subtask - check and bring link up 7509 * @adapter: pointer to the device adapter structure 7510 **/ 7511 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7512 { 7513 /* if interface is down, removing or resetting, do nothing */ 7514 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7515 test_bit(__IXGBE_REMOVING, &adapter->state) || 7516 test_bit(__IXGBE_RESETTING, &adapter->state)) 7517 return; 7518 7519 ixgbe_watchdog_update_link(adapter); 7520 7521 if (adapter->link_up) 7522 ixgbe_watchdog_link_is_up(adapter); 7523 else 7524 ixgbe_watchdog_link_is_down(adapter); 7525 7526 ixgbe_check_for_bad_vf(adapter); 7527 ixgbe_spoof_check(adapter); 7528 ixgbe_update_stats(adapter); 7529 7530 ixgbe_watchdog_flush_tx(adapter); 7531 } 7532 7533 /** 7534 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7535 * @adapter: the ixgbe adapter structure 7536 **/ 7537 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7538 { 7539 struct ixgbe_hw *hw = &adapter->hw; 7540 s32 err; 7541 7542 /* not searching for SFP so there is nothing to do here */ 7543 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7544 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7545 return; 7546 7547 if (adapter->sfp_poll_time && 7548 time_after(adapter->sfp_poll_time, jiffies)) 7549 return; /* If not yet time to poll for SFP */ 7550 7551 /* someone else is in init, wait until next service event */ 7552 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7553 return; 7554 7555 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7556 7557 err = hw->phy.ops.identify_sfp(hw); 7558 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7559 goto sfp_out; 7560 7561 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7562 /* If no cable is present, then we need to reset 7563 * the next time we find a good cable. */ 7564 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7565 } 7566 7567 /* exit on error */ 7568 if (err) 7569 goto sfp_out; 7570 7571 /* exit if reset not needed */ 7572 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7573 goto sfp_out; 7574 7575 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7576 7577 /* 7578 * A module may be identified correctly, but the EEPROM may not have 7579 * support for that module. setup_sfp() will fail in that case, so 7580 * we should not allow that module to load. 7581 */ 7582 if (hw->mac.type == ixgbe_mac_82598EB) 7583 err = hw->phy.ops.reset(hw); 7584 else 7585 err = hw->mac.ops.setup_sfp(hw); 7586 7587 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7588 goto sfp_out; 7589 7590 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7591 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7592 7593 sfp_out: 7594 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7595 7596 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7597 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7598 e_dev_err("failed to initialize because an unsupported " 7599 "SFP+ module type was detected.\n"); 7600 e_dev_err("Reload the driver after installing a " 7601 "supported module.\n"); 7602 unregister_netdev(adapter->netdev); 7603 } 7604 } 7605 7606 /** 7607 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7608 * @adapter: the ixgbe adapter structure 7609 **/ 7610 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7611 { 7612 struct ixgbe_hw *hw = &adapter->hw; 7613 u32 cap_speed; 7614 u32 speed; 7615 bool autoneg = false; 7616 7617 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7618 return; 7619 7620 /* someone else is in init, wait until next service event */ 7621 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7622 return; 7623 7624 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7625 7626 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7627 7628 /* advertise highest capable link speed */ 7629 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7630 speed = IXGBE_LINK_SPEED_10GB_FULL; 7631 else 7632 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7633 IXGBE_LINK_SPEED_1GB_FULL); 7634 7635 if (hw->mac.ops.setup_link) 7636 hw->mac.ops.setup_link(hw, speed, true); 7637 7638 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7639 adapter->link_check_timeout = jiffies; 7640 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7641 } 7642 7643 /** 7644 * ixgbe_service_timer - Timer Call-back 7645 * @t: pointer to timer_list structure 7646 **/ 7647 static void ixgbe_service_timer(struct timer_list *t) 7648 { 7649 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7650 unsigned long next_event_offset; 7651 7652 /* poll faster when waiting for link */ 7653 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7654 next_event_offset = HZ / 10; 7655 else 7656 next_event_offset = HZ * 2; 7657 7658 /* Reset the timer */ 7659 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7660 7661 ixgbe_service_event_schedule(adapter); 7662 } 7663 7664 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7665 { 7666 struct ixgbe_hw *hw = &adapter->hw; 7667 u32 status; 7668 7669 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7670 return; 7671 7672 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7673 7674 if (!hw->phy.ops.handle_lasi) 7675 return; 7676 7677 status = hw->phy.ops.handle_lasi(&adapter->hw); 7678 if (status != IXGBE_ERR_OVERTEMP) 7679 return; 7680 7681 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7682 } 7683 7684 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7685 { 7686 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7687 return; 7688 7689 /* If we're already down, removing or resetting, just bail */ 7690 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7691 test_bit(__IXGBE_REMOVING, &adapter->state) || 7692 test_bit(__IXGBE_RESETTING, &adapter->state)) 7693 return; 7694 7695 ixgbe_dump(adapter); 7696 netdev_err(adapter->netdev, "Reset adapter\n"); 7697 adapter->tx_timeout_count++; 7698 7699 rtnl_lock(); 7700 ixgbe_reinit_locked(adapter); 7701 rtnl_unlock(); 7702 } 7703 7704 /** 7705 * ixgbe_service_task - manages and runs subtasks 7706 * @work: pointer to work_struct containing our data 7707 **/ 7708 static void ixgbe_service_task(struct work_struct *work) 7709 { 7710 struct ixgbe_adapter *adapter = container_of(work, 7711 struct ixgbe_adapter, 7712 service_task); 7713 if (ixgbe_removed(adapter->hw.hw_addr)) { 7714 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7715 rtnl_lock(); 7716 ixgbe_down(adapter); 7717 rtnl_unlock(); 7718 } 7719 ixgbe_service_event_complete(adapter); 7720 return; 7721 } 7722 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7723 rtnl_lock(); 7724 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7725 udp_tunnel_get_rx_info(adapter->netdev); 7726 rtnl_unlock(); 7727 } 7728 ixgbe_reset_subtask(adapter); 7729 ixgbe_phy_interrupt_subtask(adapter); 7730 ixgbe_sfp_detection_subtask(adapter); 7731 ixgbe_sfp_link_config_subtask(adapter); 7732 ixgbe_check_overtemp_subtask(adapter); 7733 ixgbe_watchdog_subtask(adapter); 7734 ixgbe_fdir_reinit_subtask(adapter); 7735 ixgbe_check_hang_subtask(adapter); 7736 7737 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7738 ixgbe_ptp_overflow_check(adapter); 7739 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7740 ixgbe_ptp_rx_hang(adapter); 7741 ixgbe_ptp_tx_hang(adapter); 7742 } 7743 7744 ixgbe_service_event_complete(adapter); 7745 } 7746 7747 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7748 struct ixgbe_tx_buffer *first, 7749 u8 *hdr_len, 7750 struct ixgbe_ipsec_tx_data *itd) 7751 { 7752 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7753 struct sk_buff *skb = first->skb; 7754 union { 7755 struct iphdr *v4; 7756 struct ipv6hdr *v6; 7757 unsigned char *hdr; 7758 } ip; 7759 union { 7760 struct tcphdr *tcp; 7761 unsigned char *hdr; 7762 } l4; 7763 u32 paylen, l4_offset; 7764 u32 fceof_saidx = 0; 7765 int err; 7766 7767 if (skb->ip_summed != CHECKSUM_PARTIAL) 7768 return 0; 7769 7770 if (!skb_is_gso(skb)) 7771 return 0; 7772 7773 err = skb_cow_head(skb, 0); 7774 if (err < 0) 7775 return err; 7776 7777 if (eth_p_mpls(first->protocol)) 7778 ip.hdr = skb_inner_network_header(skb); 7779 else 7780 ip.hdr = skb_network_header(skb); 7781 l4.hdr = skb_checksum_start(skb); 7782 7783 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7784 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7785 7786 /* initialize outer IP header fields */ 7787 if (ip.v4->version == 4) { 7788 unsigned char *csum_start = skb_checksum_start(skb); 7789 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7790 int len = csum_start - trans_start; 7791 7792 /* IP header will have to cancel out any data that 7793 * is not a part of the outer IP header, so set to 7794 * a reverse csum if needed, else init check to 0. 7795 */ 7796 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7797 csum_fold(csum_partial(trans_start, 7798 len, 0)) : 0; 7799 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7800 7801 ip.v4->tot_len = 0; 7802 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7803 IXGBE_TX_FLAGS_CSUM | 7804 IXGBE_TX_FLAGS_IPV4; 7805 } else { 7806 ip.v6->payload_len = 0; 7807 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7808 IXGBE_TX_FLAGS_CSUM; 7809 } 7810 7811 /* determine offset of inner transport header */ 7812 l4_offset = l4.hdr - skb->data; 7813 7814 /* compute length of segmentation header */ 7815 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7816 7817 /* remove payload length from inner checksum */ 7818 paylen = skb->len - l4_offset; 7819 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7820 7821 /* update gso size and bytecount with header size */ 7822 first->gso_segs = skb_shinfo(skb)->gso_segs; 7823 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7824 7825 /* mss_l4len_id: use 0 as index for TSO */ 7826 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7827 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7828 7829 fceof_saidx |= itd->sa_idx; 7830 type_tucmd |= itd->flags | itd->trailer_len; 7831 7832 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7833 vlan_macip_lens = l4.hdr - ip.hdr; 7834 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7835 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7836 7837 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 7838 mss_l4len_idx); 7839 7840 return 1; 7841 } 7842 7843 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7844 { 7845 unsigned int offset = 0; 7846 7847 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7848 7849 return offset == skb_checksum_start_offset(skb); 7850 } 7851 7852 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7853 struct ixgbe_tx_buffer *first, 7854 struct ixgbe_ipsec_tx_data *itd) 7855 { 7856 struct sk_buff *skb = first->skb; 7857 u32 vlan_macip_lens = 0; 7858 u32 fceof_saidx = 0; 7859 u32 type_tucmd = 0; 7860 7861 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7862 csum_failed: 7863 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7864 IXGBE_TX_FLAGS_CC))) 7865 return; 7866 goto no_csum; 7867 } 7868 7869 switch (skb->csum_offset) { 7870 case offsetof(struct tcphdr, check): 7871 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7872 /* fall through */ 7873 case offsetof(struct udphdr, check): 7874 break; 7875 case offsetof(struct sctphdr, checksum): 7876 /* validate that this is actually an SCTP request */ 7877 if (((first->protocol == htons(ETH_P_IP)) && 7878 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7879 ((first->protocol == htons(ETH_P_IPV6)) && 7880 ixgbe_ipv6_csum_is_sctp(skb))) { 7881 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7882 break; 7883 } 7884 /* fall through */ 7885 default: 7886 skb_checksum_help(skb); 7887 goto csum_failed; 7888 } 7889 7890 /* update TX checksum flag */ 7891 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7892 vlan_macip_lens = skb_checksum_start_offset(skb) - 7893 skb_network_offset(skb); 7894 no_csum: 7895 /* vlan_macip_lens: MACLEN, VLAN tag */ 7896 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7897 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7898 7899 fceof_saidx |= itd->sa_idx; 7900 type_tucmd |= itd->flags | itd->trailer_len; 7901 7902 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 7903 } 7904 7905 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7906 ((_flag <= _result) ? \ 7907 ((u32)(_input & _flag) * (_result / _flag)) : \ 7908 ((u32)(_input & _flag) / (_flag / _result))) 7909 7910 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7911 { 7912 /* set type for advanced descriptor with frame checksum insertion */ 7913 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7914 IXGBE_ADVTXD_DCMD_DEXT | 7915 IXGBE_ADVTXD_DCMD_IFCS; 7916 7917 /* set HW vlan bit if vlan is present */ 7918 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7919 IXGBE_ADVTXD_DCMD_VLE); 7920 7921 /* set segmentation enable bits for TSO/FSO */ 7922 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7923 IXGBE_ADVTXD_DCMD_TSE); 7924 7925 /* set timestamp bit if present */ 7926 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7927 IXGBE_ADVTXD_MAC_TSTAMP); 7928 7929 /* insert frame checksum */ 7930 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7931 7932 return cmd_type; 7933 } 7934 7935 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7936 u32 tx_flags, unsigned int paylen) 7937 { 7938 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7939 7940 /* enable L4 checksum for TSO and TX checksum offload */ 7941 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7942 IXGBE_TX_FLAGS_CSUM, 7943 IXGBE_ADVTXD_POPTS_TXSM); 7944 7945 /* enable IPv4 checksum for TSO */ 7946 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7947 IXGBE_TX_FLAGS_IPV4, 7948 IXGBE_ADVTXD_POPTS_IXSM); 7949 7950 /* enable IPsec */ 7951 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7952 IXGBE_TX_FLAGS_IPSEC, 7953 IXGBE_ADVTXD_POPTS_IPSEC); 7954 7955 /* 7956 * Check Context must be set if Tx switch is enabled, which it 7957 * always is for case where virtual functions are running 7958 */ 7959 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7960 IXGBE_TX_FLAGS_CC, 7961 IXGBE_ADVTXD_CC); 7962 7963 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7964 } 7965 7966 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7967 { 7968 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7969 7970 /* Herbert's original patch had: 7971 * smp_mb__after_netif_stop_queue(); 7972 * but since that doesn't exist yet, just open code it. 7973 */ 7974 smp_mb(); 7975 7976 /* We need to check again in a case another CPU has just 7977 * made room available. 7978 */ 7979 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7980 return -EBUSY; 7981 7982 /* A reprieve! - use start_queue because it doesn't call schedule */ 7983 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7984 ++tx_ring->tx_stats.restart_queue; 7985 return 0; 7986 } 7987 7988 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7989 { 7990 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7991 return 0; 7992 7993 return __ixgbe_maybe_stop_tx(tx_ring, size); 7994 } 7995 7996 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7997 IXGBE_TXD_CMD_RS) 7998 7999 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8000 struct ixgbe_tx_buffer *first, 8001 const u8 hdr_len) 8002 { 8003 struct sk_buff *skb = first->skb; 8004 struct ixgbe_tx_buffer *tx_buffer; 8005 union ixgbe_adv_tx_desc *tx_desc; 8006 struct skb_frag_struct *frag; 8007 dma_addr_t dma; 8008 unsigned int data_len, size; 8009 u32 tx_flags = first->tx_flags; 8010 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8011 u16 i = tx_ring->next_to_use; 8012 8013 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8014 8015 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8016 8017 size = skb_headlen(skb); 8018 data_len = skb->data_len; 8019 8020 #ifdef IXGBE_FCOE 8021 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8022 if (data_len < sizeof(struct fcoe_crc_eof)) { 8023 size -= sizeof(struct fcoe_crc_eof) - data_len; 8024 data_len = 0; 8025 } else { 8026 data_len -= sizeof(struct fcoe_crc_eof); 8027 } 8028 } 8029 8030 #endif 8031 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8032 8033 tx_buffer = first; 8034 8035 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8036 if (dma_mapping_error(tx_ring->dev, dma)) 8037 goto dma_error; 8038 8039 /* record length, and DMA address */ 8040 dma_unmap_len_set(tx_buffer, len, size); 8041 dma_unmap_addr_set(tx_buffer, dma, dma); 8042 8043 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8044 8045 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8046 tx_desc->read.cmd_type_len = 8047 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8048 8049 i++; 8050 tx_desc++; 8051 if (i == tx_ring->count) { 8052 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8053 i = 0; 8054 } 8055 tx_desc->read.olinfo_status = 0; 8056 8057 dma += IXGBE_MAX_DATA_PER_TXD; 8058 size -= IXGBE_MAX_DATA_PER_TXD; 8059 8060 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8061 } 8062 8063 if (likely(!data_len)) 8064 break; 8065 8066 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8067 8068 i++; 8069 tx_desc++; 8070 if (i == tx_ring->count) { 8071 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8072 i = 0; 8073 } 8074 tx_desc->read.olinfo_status = 0; 8075 8076 #ifdef IXGBE_FCOE 8077 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8078 #else 8079 size = skb_frag_size(frag); 8080 #endif 8081 data_len -= size; 8082 8083 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8084 DMA_TO_DEVICE); 8085 8086 tx_buffer = &tx_ring->tx_buffer_info[i]; 8087 } 8088 8089 /* write last descriptor with RS and EOP bits */ 8090 cmd_type |= size | IXGBE_TXD_CMD; 8091 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8092 8093 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8094 8095 /* set the timestamp */ 8096 first->time_stamp = jiffies; 8097 8098 /* 8099 * Force memory writes to complete before letting h/w know there 8100 * are new descriptors to fetch. (Only applicable for weak-ordered 8101 * memory model archs, such as IA-64). 8102 * 8103 * We also need this memory barrier to make certain all of the 8104 * status bits have been updated before next_to_watch is written. 8105 */ 8106 wmb(); 8107 8108 /* set next_to_watch value indicating a packet is present */ 8109 first->next_to_watch = tx_desc; 8110 8111 i++; 8112 if (i == tx_ring->count) 8113 i = 0; 8114 8115 tx_ring->next_to_use = i; 8116 8117 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8118 8119 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8120 writel(i, tx_ring->tail); 8121 8122 /* we need this if more than one processor can write to our tail 8123 * at a time, it synchronizes IO on IA64/Altix systems 8124 */ 8125 mmiowb(); 8126 } 8127 8128 return 0; 8129 dma_error: 8130 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8131 8132 /* clear dma mappings for failed tx_buffer_info map */ 8133 for (;;) { 8134 tx_buffer = &tx_ring->tx_buffer_info[i]; 8135 if (dma_unmap_len(tx_buffer, len)) 8136 dma_unmap_page(tx_ring->dev, 8137 dma_unmap_addr(tx_buffer, dma), 8138 dma_unmap_len(tx_buffer, len), 8139 DMA_TO_DEVICE); 8140 dma_unmap_len_set(tx_buffer, len, 0); 8141 if (tx_buffer == first) 8142 break; 8143 if (i == 0) 8144 i += tx_ring->count; 8145 i--; 8146 } 8147 8148 dev_kfree_skb_any(first->skb); 8149 first->skb = NULL; 8150 8151 tx_ring->next_to_use = i; 8152 8153 return -1; 8154 } 8155 8156 static void ixgbe_atr(struct ixgbe_ring *ring, 8157 struct ixgbe_tx_buffer *first) 8158 { 8159 struct ixgbe_q_vector *q_vector = ring->q_vector; 8160 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8161 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8162 union { 8163 unsigned char *network; 8164 struct iphdr *ipv4; 8165 struct ipv6hdr *ipv6; 8166 } hdr; 8167 struct tcphdr *th; 8168 unsigned int hlen; 8169 struct sk_buff *skb; 8170 __be16 vlan_id; 8171 int l4_proto; 8172 8173 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8174 if (!q_vector) 8175 return; 8176 8177 /* do nothing if sampling is disabled */ 8178 if (!ring->atr_sample_rate) 8179 return; 8180 8181 ring->atr_count++; 8182 8183 /* currently only IPv4/IPv6 with TCP is supported */ 8184 if ((first->protocol != htons(ETH_P_IP)) && 8185 (first->protocol != htons(ETH_P_IPV6))) 8186 return; 8187 8188 /* snag network header to get L4 type and address */ 8189 skb = first->skb; 8190 hdr.network = skb_network_header(skb); 8191 if (unlikely(hdr.network <= skb->data)) 8192 return; 8193 if (skb->encapsulation && 8194 first->protocol == htons(ETH_P_IP) && 8195 hdr.ipv4->protocol == IPPROTO_UDP) { 8196 struct ixgbe_adapter *adapter = q_vector->adapter; 8197 8198 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8199 VXLAN_HEADROOM)) 8200 return; 8201 8202 /* verify the port is recognized as VXLAN */ 8203 if (adapter->vxlan_port && 8204 udp_hdr(skb)->dest == adapter->vxlan_port) 8205 hdr.network = skb_inner_network_header(skb); 8206 8207 if (adapter->geneve_port && 8208 udp_hdr(skb)->dest == adapter->geneve_port) 8209 hdr.network = skb_inner_network_header(skb); 8210 } 8211 8212 /* Make sure we have at least [minimum IPv4 header + TCP] 8213 * or [IPv6 header] bytes 8214 */ 8215 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8216 return; 8217 8218 /* Currently only IPv4/IPv6 with TCP is supported */ 8219 switch (hdr.ipv4->version) { 8220 case IPVERSION: 8221 /* access ihl as u8 to avoid unaligned access on ia64 */ 8222 hlen = (hdr.network[0] & 0x0F) << 2; 8223 l4_proto = hdr.ipv4->protocol; 8224 break; 8225 case 6: 8226 hlen = hdr.network - skb->data; 8227 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8228 hlen -= hdr.network - skb->data; 8229 break; 8230 default: 8231 return; 8232 } 8233 8234 if (l4_proto != IPPROTO_TCP) 8235 return; 8236 8237 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8238 hlen + sizeof(struct tcphdr))) 8239 return; 8240 8241 th = (struct tcphdr *)(hdr.network + hlen); 8242 8243 /* skip this packet since the socket is closing */ 8244 if (th->fin) 8245 return; 8246 8247 /* sample on all syn packets or once every atr sample count */ 8248 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8249 return; 8250 8251 /* reset sample count */ 8252 ring->atr_count = 0; 8253 8254 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8255 8256 /* 8257 * src and dst are inverted, think how the receiver sees them 8258 * 8259 * The input is broken into two sections, a non-compressed section 8260 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8261 * is XORed together and stored in the compressed dword. 8262 */ 8263 input.formatted.vlan_id = vlan_id; 8264 8265 /* 8266 * since src port and flex bytes occupy the same word XOR them together 8267 * and write the value to source port portion of compressed dword 8268 */ 8269 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8270 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8271 else 8272 common.port.src ^= th->dest ^ first->protocol; 8273 common.port.dst ^= th->source; 8274 8275 switch (hdr.ipv4->version) { 8276 case IPVERSION: 8277 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8278 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8279 break; 8280 case 6: 8281 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8282 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8283 hdr.ipv6->saddr.s6_addr32[1] ^ 8284 hdr.ipv6->saddr.s6_addr32[2] ^ 8285 hdr.ipv6->saddr.s6_addr32[3] ^ 8286 hdr.ipv6->daddr.s6_addr32[0] ^ 8287 hdr.ipv6->daddr.s6_addr32[1] ^ 8288 hdr.ipv6->daddr.s6_addr32[2] ^ 8289 hdr.ipv6->daddr.s6_addr32[3]; 8290 break; 8291 default: 8292 break; 8293 } 8294 8295 if (hdr.network != skb_network_header(skb)) 8296 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8297 8298 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8299 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8300 input, common, ring->queue_index); 8301 } 8302 8303 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8304 void *accel_priv, select_queue_fallback_t fallback) 8305 { 8306 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8307 struct ixgbe_adapter *adapter; 8308 int txq; 8309 #ifdef IXGBE_FCOE 8310 struct ixgbe_ring_feature *f; 8311 #endif 8312 8313 if (fwd_adapter) { 8314 adapter = netdev_priv(dev); 8315 txq = reciprocal_scale(skb_get_hash(skb), 8316 adapter->num_rx_queues_per_pool); 8317 8318 return txq + fwd_adapter->tx_base_queue; 8319 } 8320 8321 #ifdef IXGBE_FCOE 8322 8323 /* 8324 * only execute the code below if protocol is FCoE 8325 * or FIP and we have FCoE enabled on the adapter 8326 */ 8327 switch (vlan_get_protocol(skb)) { 8328 case htons(ETH_P_FCOE): 8329 case htons(ETH_P_FIP): 8330 adapter = netdev_priv(dev); 8331 8332 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8333 break; 8334 /* fall through */ 8335 default: 8336 return fallback(dev, skb); 8337 } 8338 8339 f = &adapter->ring_feature[RING_F_FCOE]; 8340 8341 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8342 smp_processor_id(); 8343 8344 while (txq >= f->indices) 8345 txq -= f->indices; 8346 8347 return txq + f->offset; 8348 #else 8349 return fallback(dev, skb); 8350 #endif 8351 } 8352 8353 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8354 struct xdp_frame *xdpf) 8355 { 8356 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8357 struct ixgbe_tx_buffer *tx_buffer; 8358 union ixgbe_adv_tx_desc *tx_desc; 8359 u32 len, cmd_type; 8360 dma_addr_t dma; 8361 u16 i; 8362 8363 len = xdpf->len; 8364 8365 if (unlikely(!ixgbe_desc_unused(ring))) 8366 return IXGBE_XDP_CONSUMED; 8367 8368 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8369 if (dma_mapping_error(ring->dev, dma)) 8370 return IXGBE_XDP_CONSUMED; 8371 8372 /* record the location of the first descriptor for this packet */ 8373 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8374 tx_buffer->bytecount = len; 8375 tx_buffer->gso_segs = 1; 8376 tx_buffer->protocol = 0; 8377 8378 i = ring->next_to_use; 8379 tx_desc = IXGBE_TX_DESC(ring, i); 8380 8381 dma_unmap_len_set(tx_buffer, len, len); 8382 dma_unmap_addr_set(tx_buffer, dma, dma); 8383 tx_buffer->xdpf = xdpf; 8384 8385 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8386 8387 /* put descriptor type bits */ 8388 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8389 IXGBE_ADVTXD_DCMD_DEXT | 8390 IXGBE_ADVTXD_DCMD_IFCS; 8391 cmd_type |= len | IXGBE_TXD_CMD; 8392 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8393 tx_desc->read.olinfo_status = 8394 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8395 8396 /* Avoid any potential race with xdp_xmit and cleanup */ 8397 smp_wmb(); 8398 8399 /* set next_to_watch value indicating a packet is present */ 8400 i++; 8401 if (i == ring->count) 8402 i = 0; 8403 8404 tx_buffer->next_to_watch = tx_desc; 8405 ring->next_to_use = i; 8406 8407 return IXGBE_XDP_TX; 8408 } 8409 8410 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8411 struct ixgbe_adapter *adapter, 8412 struct ixgbe_ring *tx_ring) 8413 { 8414 struct ixgbe_tx_buffer *first; 8415 int tso; 8416 u32 tx_flags = 0; 8417 unsigned short f; 8418 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8419 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8420 __be16 protocol = skb->protocol; 8421 u8 hdr_len = 0; 8422 8423 /* 8424 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8425 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8426 * + 2 desc gap to keep tail from touching head, 8427 * + 1 desc for context descriptor, 8428 * otherwise try next time 8429 */ 8430 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8431 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8432 8433 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8434 tx_ring->tx_stats.tx_busy++; 8435 return NETDEV_TX_BUSY; 8436 } 8437 8438 /* record the location of the first descriptor for this packet */ 8439 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8440 first->skb = skb; 8441 first->bytecount = skb->len; 8442 first->gso_segs = 1; 8443 8444 /* if we have a HW VLAN tag being added default to the HW one */ 8445 if (skb_vlan_tag_present(skb)) { 8446 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8447 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8448 /* else if it is a SW VLAN check the next protocol and store the tag */ 8449 } else if (protocol == htons(ETH_P_8021Q)) { 8450 struct vlan_hdr *vhdr, _vhdr; 8451 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8452 if (!vhdr) 8453 goto out_drop; 8454 8455 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8456 IXGBE_TX_FLAGS_VLAN_SHIFT; 8457 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8458 } 8459 protocol = vlan_get_protocol(skb); 8460 8461 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8462 adapter->ptp_clock) { 8463 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8464 &adapter->state)) { 8465 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8466 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8467 8468 /* schedule check for Tx timestamp */ 8469 adapter->ptp_tx_skb = skb_get(skb); 8470 adapter->ptp_tx_start = jiffies; 8471 schedule_work(&adapter->ptp_tx_work); 8472 } else { 8473 adapter->tx_hwtstamp_skipped++; 8474 } 8475 } 8476 8477 skb_tx_timestamp(skb); 8478 8479 #ifdef CONFIG_PCI_IOV 8480 /* 8481 * Use the l2switch_enable flag - would be false if the DMA 8482 * Tx switch had been disabled. 8483 */ 8484 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8485 tx_flags |= IXGBE_TX_FLAGS_CC; 8486 8487 #endif 8488 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8489 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8490 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8491 (skb->priority != TC_PRIO_CONTROL))) { 8492 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8493 tx_flags |= (skb->priority & 0x7) << 8494 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8495 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8496 struct vlan_ethhdr *vhdr; 8497 8498 if (skb_cow_head(skb, 0)) 8499 goto out_drop; 8500 vhdr = (struct vlan_ethhdr *)skb->data; 8501 vhdr->h_vlan_TCI = htons(tx_flags >> 8502 IXGBE_TX_FLAGS_VLAN_SHIFT); 8503 } else { 8504 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8505 } 8506 } 8507 8508 /* record initial flags and protocol */ 8509 first->tx_flags = tx_flags; 8510 first->protocol = protocol; 8511 8512 #ifdef IXGBE_FCOE 8513 /* setup tx offload for FCoE */ 8514 if ((protocol == htons(ETH_P_FCOE)) && 8515 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8516 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8517 if (tso < 0) 8518 goto out_drop; 8519 8520 goto xmit_fcoe; 8521 } 8522 8523 #endif /* IXGBE_FCOE */ 8524 8525 #ifdef CONFIG_XFRM_OFFLOAD 8526 if (skb->sp && !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8527 goto out_drop; 8528 #endif 8529 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8530 if (tso < 0) 8531 goto out_drop; 8532 else if (!tso) 8533 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8534 8535 /* add the ATR filter if ATR is on */ 8536 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8537 ixgbe_atr(tx_ring, first); 8538 8539 #ifdef IXGBE_FCOE 8540 xmit_fcoe: 8541 #endif /* IXGBE_FCOE */ 8542 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8543 goto cleanup_tx_timestamp; 8544 8545 return NETDEV_TX_OK; 8546 8547 out_drop: 8548 dev_kfree_skb_any(first->skb); 8549 first->skb = NULL; 8550 cleanup_tx_timestamp: 8551 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8552 dev_kfree_skb_any(adapter->ptp_tx_skb); 8553 adapter->ptp_tx_skb = NULL; 8554 cancel_work_sync(&adapter->ptp_tx_work); 8555 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8556 } 8557 8558 return NETDEV_TX_OK; 8559 } 8560 8561 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8562 struct net_device *netdev, 8563 struct ixgbe_ring *ring) 8564 { 8565 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8566 struct ixgbe_ring *tx_ring; 8567 8568 /* 8569 * The minimum packet size for olinfo paylen is 17 so pad the skb 8570 * in order to meet this minimum size requirement. 8571 */ 8572 if (skb_put_padto(skb, 17)) 8573 return NETDEV_TX_OK; 8574 8575 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8576 8577 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8578 } 8579 8580 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8581 struct net_device *netdev) 8582 { 8583 return __ixgbe_xmit_frame(skb, netdev, NULL); 8584 } 8585 8586 /** 8587 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8588 * @netdev: network interface device structure 8589 * @p: pointer to an address structure 8590 * 8591 * Returns 0 on success, negative on failure 8592 **/ 8593 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8594 { 8595 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8596 struct ixgbe_hw *hw = &adapter->hw; 8597 struct sockaddr *addr = p; 8598 8599 if (!is_valid_ether_addr(addr->sa_data)) 8600 return -EADDRNOTAVAIL; 8601 8602 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8603 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8604 8605 ixgbe_mac_set_default_filter(adapter); 8606 8607 return 0; 8608 } 8609 8610 static int 8611 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8612 { 8613 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8614 struct ixgbe_hw *hw = &adapter->hw; 8615 u16 value; 8616 int rc; 8617 8618 if (prtad != hw->phy.mdio.prtad) 8619 return -EINVAL; 8620 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8621 if (!rc) 8622 rc = value; 8623 return rc; 8624 } 8625 8626 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8627 u16 addr, u16 value) 8628 { 8629 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8630 struct ixgbe_hw *hw = &adapter->hw; 8631 8632 if (prtad != hw->phy.mdio.prtad) 8633 return -EINVAL; 8634 return hw->phy.ops.write_reg(hw, addr, devad, value); 8635 } 8636 8637 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8638 { 8639 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8640 8641 switch (cmd) { 8642 case SIOCSHWTSTAMP: 8643 return ixgbe_ptp_set_ts_config(adapter, req); 8644 case SIOCGHWTSTAMP: 8645 return ixgbe_ptp_get_ts_config(adapter, req); 8646 case SIOCGMIIPHY: 8647 if (!adapter->hw.phy.ops.read_reg) 8648 return -EOPNOTSUPP; 8649 /* fall through */ 8650 default: 8651 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8652 } 8653 } 8654 8655 /** 8656 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8657 * netdev->dev_addrs 8658 * @dev: network interface device structure 8659 * 8660 * Returns non-zero on failure 8661 **/ 8662 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8663 { 8664 int err = 0; 8665 struct ixgbe_adapter *adapter = netdev_priv(dev); 8666 struct ixgbe_hw *hw = &adapter->hw; 8667 8668 if (is_valid_ether_addr(hw->mac.san_addr)) { 8669 rtnl_lock(); 8670 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8671 rtnl_unlock(); 8672 8673 /* update SAN MAC vmdq pool selection */ 8674 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8675 } 8676 return err; 8677 } 8678 8679 /** 8680 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8681 * netdev->dev_addrs 8682 * @dev: network interface device structure 8683 * 8684 * Returns non-zero on failure 8685 **/ 8686 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8687 { 8688 int err = 0; 8689 struct ixgbe_adapter *adapter = netdev_priv(dev); 8690 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8691 8692 if (is_valid_ether_addr(mac->san_addr)) { 8693 rtnl_lock(); 8694 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8695 rtnl_unlock(); 8696 } 8697 return err; 8698 } 8699 8700 #ifdef CONFIG_NET_POLL_CONTROLLER 8701 /* 8702 * Polling 'interrupt' - used by things like netconsole to send skbs 8703 * without having to re-enable interrupts. It's not called while 8704 * the interrupt routine is executing. 8705 */ 8706 static void ixgbe_netpoll(struct net_device *netdev) 8707 { 8708 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8709 int i; 8710 8711 /* if interface is down do nothing */ 8712 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8713 return; 8714 8715 /* loop through and schedule all active queues */ 8716 for (i = 0; i < adapter->num_q_vectors; i++) 8717 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8718 } 8719 8720 #endif 8721 8722 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8723 struct ixgbe_ring *ring) 8724 { 8725 u64 bytes, packets; 8726 unsigned int start; 8727 8728 if (ring) { 8729 do { 8730 start = u64_stats_fetch_begin_irq(&ring->syncp); 8731 packets = ring->stats.packets; 8732 bytes = ring->stats.bytes; 8733 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8734 stats->tx_packets += packets; 8735 stats->tx_bytes += bytes; 8736 } 8737 } 8738 8739 static void ixgbe_get_stats64(struct net_device *netdev, 8740 struct rtnl_link_stats64 *stats) 8741 { 8742 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8743 int i; 8744 8745 rcu_read_lock(); 8746 for (i = 0; i < adapter->num_rx_queues; i++) { 8747 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8748 u64 bytes, packets; 8749 unsigned int start; 8750 8751 if (ring) { 8752 do { 8753 start = u64_stats_fetch_begin_irq(&ring->syncp); 8754 packets = ring->stats.packets; 8755 bytes = ring->stats.bytes; 8756 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8757 stats->rx_packets += packets; 8758 stats->rx_bytes += bytes; 8759 } 8760 } 8761 8762 for (i = 0; i < adapter->num_tx_queues; i++) { 8763 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8764 8765 ixgbe_get_ring_stats64(stats, ring); 8766 } 8767 for (i = 0; i < adapter->num_xdp_queues; i++) { 8768 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8769 8770 ixgbe_get_ring_stats64(stats, ring); 8771 } 8772 rcu_read_unlock(); 8773 8774 /* following stats updated by ixgbe_watchdog_task() */ 8775 stats->multicast = netdev->stats.multicast; 8776 stats->rx_errors = netdev->stats.rx_errors; 8777 stats->rx_length_errors = netdev->stats.rx_length_errors; 8778 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8779 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8780 } 8781 8782 #ifdef CONFIG_IXGBE_DCB 8783 /** 8784 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8785 * @adapter: pointer to ixgbe_adapter 8786 * @tc: number of traffic classes currently enabled 8787 * 8788 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8789 * 802.1Q priority maps to a packet buffer that exists. 8790 */ 8791 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8792 { 8793 struct ixgbe_hw *hw = &adapter->hw; 8794 u32 reg, rsave; 8795 int i; 8796 8797 /* 82598 have a static priority to TC mapping that can not 8798 * be changed so no validation is needed. 8799 */ 8800 if (hw->mac.type == ixgbe_mac_82598EB) 8801 return; 8802 8803 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8804 rsave = reg; 8805 8806 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8807 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8808 8809 /* If up2tc is out of bounds default to zero */ 8810 if (up2tc > tc) 8811 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8812 } 8813 8814 if (reg != rsave) 8815 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8816 8817 return; 8818 } 8819 8820 /** 8821 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8822 * @adapter: Pointer to adapter struct 8823 * 8824 * Populate the netdev user priority to tc map 8825 */ 8826 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8827 { 8828 struct net_device *dev = adapter->netdev; 8829 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8830 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8831 u8 prio; 8832 8833 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8834 u8 tc = 0; 8835 8836 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8837 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8838 else if (ets) 8839 tc = ets->prio_tc[prio]; 8840 8841 netdev_set_prio_tc_map(dev, prio, tc); 8842 } 8843 } 8844 8845 #endif /* CONFIG_IXGBE_DCB */ 8846 /** 8847 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8848 * 8849 * @dev: net device to configure 8850 * @tc: number of traffic classes to enable 8851 */ 8852 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8853 { 8854 struct ixgbe_adapter *adapter = netdev_priv(dev); 8855 struct ixgbe_hw *hw = &adapter->hw; 8856 8857 /* Hardware supports up to 8 traffic classes */ 8858 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8859 return -EINVAL; 8860 8861 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8862 return -EINVAL; 8863 8864 /* Hardware has to reinitialize queues and interrupts to 8865 * match packet buffer alignment. Unfortunately, the 8866 * hardware is not flexible enough to do this dynamically. 8867 */ 8868 if (netif_running(dev)) 8869 ixgbe_close(dev); 8870 else 8871 ixgbe_reset(adapter); 8872 8873 ixgbe_clear_interrupt_scheme(adapter); 8874 8875 #ifdef CONFIG_IXGBE_DCB 8876 if (tc) { 8877 netdev_set_num_tc(dev, tc); 8878 ixgbe_set_prio_tc_map(adapter); 8879 8880 adapter->hw_tcs = tc; 8881 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8882 8883 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8884 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8885 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8886 } 8887 } else { 8888 netdev_reset_tc(dev); 8889 8890 /* To support macvlan offload we have to use num_tc to 8891 * restrict the queues that can be used by the device. 8892 * By doing this we can avoid reporting a false number of 8893 * queues. 8894 */ 8895 if (!tc && adapter->num_rx_pools > 1) 8896 netdev_set_num_tc(dev, 1); 8897 8898 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8899 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8900 8901 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8902 adapter->hw_tcs = tc; 8903 8904 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8905 adapter->dcb_cfg.pfc_mode_enable = false; 8906 } 8907 8908 ixgbe_validate_rtr(adapter, tc); 8909 8910 #endif /* CONFIG_IXGBE_DCB */ 8911 ixgbe_init_interrupt_scheme(adapter); 8912 8913 if (netif_running(dev)) 8914 return ixgbe_open(dev); 8915 8916 return 0; 8917 } 8918 8919 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8920 struct tc_cls_u32_offload *cls) 8921 { 8922 u32 hdl = cls->knode.handle; 8923 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8924 u32 loc = cls->knode.handle & 0xfffff; 8925 int err = 0, i, j; 8926 struct ixgbe_jump_table *jump = NULL; 8927 8928 if (loc > IXGBE_MAX_HW_ENTRIES) 8929 return -EINVAL; 8930 8931 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8932 return -EINVAL; 8933 8934 /* Clear this filter in the link data it is associated with */ 8935 if (uhtid != 0x800) { 8936 jump = adapter->jump_tables[uhtid]; 8937 if (!jump) 8938 return -EINVAL; 8939 if (!test_bit(loc - 1, jump->child_loc_map)) 8940 return -EINVAL; 8941 clear_bit(loc - 1, jump->child_loc_map); 8942 } 8943 8944 /* Check if the filter being deleted is a link */ 8945 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8946 jump = adapter->jump_tables[i]; 8947 if (jump && jump->link_hdl == hdl) { 8948 /* Delete filters in the hardware in the child hash 8949 * table associated with this link 8950 */ 8951 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8952 if (!test_bit(j, jump->child_loc_map)) 8953 continue; 8954 spin_lock(&adapter->fdir_perfect_lock); 8955 err = ixgbe_update_ethtool_fdir_entry(adapter, 8956 NULL, 8957 j + 1); 8958 spin_unlock(&adapter->fdir_perfect_lock); 8959 clear_bit(j, jump->child_loc_map); 8960 } 8961 /* Remove resources for this link */ 8962 kfree(jump->input); 8963 kfree(jump->mask); 8964 kfree(jump); 8965 adapter->jump_tables[i] = NULL; 8966 return err; 8967 } 8968 } 8969 8970 spin_lock(&adapter->fdir_perfect_lock); 8971 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8972 spin_unlock(&adapter->fdir_perfect_lock); 8973 return err; 8974 } 8975 8976 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8977 struct tc_cls_u32_offload *cls) 8978 { 8979 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8980 8981 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8982 return -EINVAL; 8983 8984 /* This ixgbe devices do not support hash tables at the moment 8985 * so abort when given hash tables. 8986 */ 8987 if (cls->hnode.divisor > 0) 8988 return -EINVAL; 8989 8990 set_bit(uhtid - 1, &adapter->tables); 8991 return 0; 8992 } 8993 8994 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8995 struct tc_cls_u32_offload *cls) 8996 { 8997 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8998 8999 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9000 return -EINVAL; 9001 9002 clear_bit(uhtid - 1, &adapter->tables); 9003 return 0; 9004 } 9005 9006 #ifdef CONFIG_NET_CLS_ACT 9007 struct upper_walk_data { 9008 struct ixgbe_adapter *adapter; 9009 u64 action; 9010 int ifindex; 9011 u8 queue; 9012 }; 9013 9014 static int get_macvlan_queue(struct net_device *upper, void *_data) 9015 { 9016 if (netif_is_macvlan(upper)) { 9017 struct macvlan_dev *dfwd = netdev_priv(upper); 9018 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 9019 struct upper_walk_data *data = _data; 9020 struct ixgbe_adapter *adapter = data->adapter; 9021 int ifindex = data->ifindex; 9022 9023 if (vadapter && vadapter->netdev->ifindex == ifindex) { 9024 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9025 data->action = data->queue; 9026 return 1; 9027 } 9028 } 9029 9030 return 0; 9031 } 9032 9033 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9034 u8 *queue, u64 *action) 9035 { 9036 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9037 unsigned int num_vfs = adapter->num_vfs, vf; 9038 struct upper_walk_data data; 9039 struct net_device *upper; 9040 9041 /* redirect to a SRIOV VF */ 9042 for (vf = 0; vf < num_vfs; ++vf) { 9043 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9044 if (upper->ifindex == ifindex) { 9045 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9046 *action = vf + 1; 9047 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9048 return 0; 9049 } 9050 } 9051 9052 /* redirect to a offloaded macvlan netdev */ 9053 data.adapter = adapter; 9054 data.ifindex = ifindex; 9055 data.action = 0; 9056 data.queue = 0; 9057 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9058 get_macvlan_queue, &data)) { 9059 *action = data.action; 9060 *queue = data.queue; 9061 9062 return 0; 9063 } 9064 9065 return -EINVAL; 9066 } 9067 9068 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9069 struct tcf_exts *exts, u64 *action, u8 *queue) 9070 { 9071 const struct tc_action *a; 9072 LIST_HEAD(actions); 9073 int err; 9074 9075 if (!tcf_exts_has_actions(exts)) 9076 return -EINVAL; 9077 9078 tcf_exts_to_list(exts, &actions); 9079 list_for_each_entry(a, &actions, list) { 9080 9081 /* Drop action */ 9082 if (is_tcf_gact_shot(a)) { 9083 *action = IXGBE_FDIR_DROP_QUEUE; 9084 *queue = IXGBE_FDIR_DROP_QUEUE; 9085 return 0; 9086 } 9087 9088 /* Redirect to a VF or a offloaded macvlan */ 9089 if (is_tcf_mirred_egress_redirect(a)) { 9090 struct net_device *dev = tcf_mirred_dev(a); 9091 9092 if (!dev) 9093 return -EINVAL; 9094 err = handle_redirect_action(adapter, dev->ifindex, queue, 9095 action); 9096 if (err == 0) 9097 return err; 9098 } 9099 } 9100 9101 return -EINVAL; 9102 } 9103 #else 9104 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9105 struct tcf_exts *exts, u64 *action, u8 *queue) 9106 { 9107 return -EINVAL; 9108 } 9109 #endif /* CONFIG_NET_CLS_ACT */ 9110 9111 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9112 union ixgbe_atr_input *mask, 9113 struct tc_cls_u32_offload *cls, 9114 struct ixgbe_mat_field *field_ptr, 9115 struct ixgbe_nexthdr *nexthdr) 9116 { 9117 int i, j, off; 9118 __be32 val, m; 9119 bool found_entry = false, found_jump_field = false; 9120 9121 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9122 off = cls->knode.sel->keys[i].off; 9123 val = cls->knode.sel->keys[i].val; 9124 m = cls->knode.sel->keys[i].mask; 9125 9126 for (j = 0; field_ptr[j].val; j++) { 9127 if (field_ptr[j].off == off) { 9128 field_ptr[j].val(input, mask, val, m); 9129 input->filter.formatted.flow_type |= 9130 field_ptr[j].type; 9131 found_entry = true; 9132 break; 9133 } 9134 } 9135 if (nexthdr) { 9136 if (nexthdr->off == cls->knode.sel->keys[i].off && 9137 nexthdr->val == cls->knode.sel->keys[i].val && 9138 nexthdr->mask == cls->knode.sel->keys[i].mask) 9139 found_jump_field = true; 9140 else 9141 continue; 9142 } 9143 } 9144 9145 if (nexthdr && !found_jump_field) 9146 return -EINVAL; 9147 9148 if (!found_entry) 9149 return 0; 9150 9151 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9152 IXGBE_ATR_L4TYPE_MASK; 9153 9154 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9155 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9156 9157 return 0; 9158 } 9159 9160 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9161 struct tc_cls_u32_offload *cls) 9162 { 9163 __be16 protocol = cls->common.protocol; 9164 u32 loc = cls->knode.handle & 0xfffff; 9165 struct ixgbe_hw *hw = &adapter->hw; 9166 struct ixgbe_mat_field *field_ptr; 9167 struct ixgbe_fdir_filter *input = NULL; 9168 union ixgbe_atr_input *mask = NULL; 9169 struct ixgbe_jump_table *jump = NULL; 9170 int i, err = -EINVAL; 9171 u8 queue; 9172 u32 uhtid, link_uhtid; 9173 9174 uhtid = TC_U32_USERHTID(cls->knode.handle); 9175 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9176 9177 /* At the moment cls_u32 jumps to network layer and skips past 9178 * L2 headers. The canonical method to match L2 frames is to use 9179 * negative values. However this is error prone at best but really 9180 * just broken because there is no way to "know" what sort of hdr 9181 * is in front of the network layer. Fix cls_u32 to support L2 9182 * headers when needed. 9183 */ 9184 if (protocol != htons(ETH_P_IP)) 9185 return err; 9186 9187 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9188 e_err(drv, "Location out of range\n"); 9189 return err; 9190 } 9191 9192 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9193 * links and also the fields used to advance the parser across each 9194 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9195 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9196 * To add support for new nodes update ixgbe_model.h parse structures 9197 * this function _should_ be generic try not to hardcode values here. 9198 */ 9199 if (uhtid == 0x800) { 9200 field_ptr = (adapter->jump_tables[0])->mat; 9201 } else { 9202 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9203 return err; 9204 if (!adapter->jump_tables[uhtid]) 9205 return err; 9206 field_ptr = (adapter->jump_tables[uhtid])->mat; 9207 } 9208 9209 if (!field_ptr) 9210 return err; 9211 9212 /* At this point we know the field_ptr is valid and need to either 9213 * build cls_u32 link or attach filter. Because adding a link to 9214 * a handle that does not exist is invalid and the same for adding 9215 * rules to handles that don't exist. 9216 */ 9217 9218 if (link_uhtid) { 9219 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9220 9221 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9222 return err; 9223 9224 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9225 return err; 9226 9227 /* Multiple filters as links to the same hash table are not 9228 * supported. To add a new filter with the same next header 9229 * but different match/jump conditions, create a new hash table 9230 * and link to it. 9231 */ 9232 if (adapter->jump_tables[link_uhtid] && 9233 (adapter->jump_tables[link_uhtid])->link_hdl) { 9234 e_err(drv, "Link filter exists for link: %x\n", 9235 link_uhtid); 9236 return err; 9237 } 9238 9239 for (i = 0; nexthdr[i].jump; i++) { 9240 if (nexthdr[i].o != cls->knode.sel->offoff || 9241 nexthdr[i].s != cls->knode.sel->offshift || 9242 nexthdr[i].m != cls->knode.sel->offmask) 9243 return err; 9244 9245 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9246 if (!jump) 9247 return -ENOMEM; 9248 input = kzalloc(sizeof(*input), GFP_KERNEL); 9249 if (!input) { 9250 err = -ENOMEM; 9251 goto free_jump; 9252 } 9253 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9254 if (!mask) { 9255 err = -ENOMEM; 9256 goto free_input; 9257 } 9258 jump->input = input; 9259 jump->mask = mask; 9260 jump->link_hdl = cls->knode.handle; 9261 9262 err = ixgbe_clsu32_build_input(input, mask, cls, 9263 field_ptr, &nexthdr[i]); 9264 if (!err) { 9265 jump->mat = nexthdr[i].jump; 9266 adapter->jump_tables[link_uhtid] = jump; 9267 break; 9268 } 9269 } 9270 return 0; 9271 } 9272 9273 input = kzalloc(sizeof(*input), GFP_KERNEL); 9274 if (!input) 9275 return -ENOMEM; 9276 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9277 if (!mask) { 9278 err = -ENOMEM; 9279 goto free_input; 9280 } 9281 9282 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9283 if ((adapter->jump_tables[uhtid])->input) 9284 memcpy(input, (adapter->jump_tables[uhtid])->input, 9285 sizeof(*input)); 9286 if ((adapter->jump_tables[uhtid])->mask) 9287 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9288 sizeof(*mask)); 9289 9290 /* Lookup in all child hash tables if this location is already 9291 * filled with a filter 9292 */ 9293 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9294 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9295 9296 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9297 e_err(drv, "Filter exists in location: %x\n", 9298 loc); 9299 err = -EINVAL; 9300 goto err_out; 9301 } 9302 } 9303 } 9304 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9305 if (err) 9306 goto err_out; 9307 9308 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9309 &queue); 9310 if (err < 0) 9311 goto err_out; 9312 9313 input->sw_idx = loc; 9314 9315 spin_lock(&adapter->fdir_perfect_lock); 9316 9317 if (hlist_empty(&adapter->fdir_filter_list)) { 9318 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9319 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9320 if (err) 9321 goto err_out_w_lock; 9322 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9323 err = -EINVAL; 9324 goto err_out_w_lock; 9325 } 9326 9327 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9328 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9329 input->sw_idx, queue); 9330 if (!err) 9331 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9332 spin_unlock(&adapter->fdir_perfect_lock); 9333 9334 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9335 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9336 9337 kfree(mask); 9338 return err; 9339 err_out_w_lock: 9340 spin_unlock(&adapter->fdir_perfect_lock); 9341 err_out: 9342 kfree(mask); 9343 free_input: 9344 kfree(input); 9345 free_jump: 9346 kfree(jump); 9347 return err; 9348 } 9349 9350 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9351 struct tc_cls_u32_offload *cls_u32) 9352 { 9353 switch (cls_u32->command) { 9354 case TC_CLSU32_NEW_KNODE: 9355 case TC_CLSU32_REPLACE_KNODE: 9356 return ixgbe_configure_clsu32(adapter, cls_u32); 9357 case TC_CLSU32_DELETE_KNODE: 9358 return ixgbe_delete_clsu32(adapter, cls_u32); 9359 case TC_CLSU32_NEW_HNODE: 9360 case TC_CLSU32_REPLACE_HNODE: 9361 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9362 case TC_CLSU32_DELETE_HNODE: 9363 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9364 default: 9365 return -EOPNOTSUPP; 9366 } 9367 } 9368 9369 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9370 void *cb_priv) 9371 { 9372 struct ixgbe_adapter *adapter = cb_priv; 9373 9374 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9375 return -EOPNOTSUPP; 9376 9377 switch (type) { 9378 case TC_SETUP_CLSU32: 9379 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9380 default: 9381 return -EOPNOTSUPP; 9382 } 9383 } 9384 9385 static int ixgbe_setup_tc_block(struct net_device *dev, 9386 struct tc_block_offload *f) 9387 { 9388 struct ixgbe_adapter *adapter = netdev_priv(dev); 9389 9390 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9391 return -EOPNOTSUPP; 9392 9393 switch (f->command) { 9394 case TC_BLOCK_BIND: 9395 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9396 adapter, adapter); 9397 case TC_BLOCK_UNBIND: 9398 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9399 adapter); 9400 return 0; 9401 default: 9402 return -EOPNOTSUPP; 9403 } 9404 } 9405 9406 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9407 struct tc_mqprio_qopt *mqprio) 9408 { 9409 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9410 return ixgbe_setup_tc(dev, mqprio->num_tc); 9411 } 9412 9413 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9414 void *type_data) 9415 { 9416 switch (type) { 9417 case TC_SETUP_BLOCK: 9418 return ixgbe_setup_tc_block(dev, type_data); 9419 case TC_SETUP_QDISC_MQPRIO: 9420 return ixgbe_setup_tc_mqprio(dev, type_data); 9421 default: 9422 return -EOPNOTSUPP; 9423 } 9424 } 9425 9426 #ifdef CONFIG_PCI_IOV 9427 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9428 { 9429 struct net_device *netdev = adapter->netdev; 9430 9431 rtnl_lock(); 9432 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9433 rtnl_unlock(); 9434 } 9435 9436 #endif 9437 void ixgbe_do_reset(struct net_device *netdev) 9438 { 9439 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9440 9441 if (netif_running(netdev)) 9442 ixgbe_reinit_locked(adapter); 9443 else 9444 ixgbe_reset(adapter); 9445 } 9446 9447 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9448 netdev_features_t features) 9449 { 9450 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9451 9452 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9453 if (!(features & NETIF_F_RXCSUM)) 9454 features &= ~NETIF_F_LRO; 9455 9456 /* Turn off LRO if not RSC capable */ 9457 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9458 features &= ~NETIF_F_LRO; 9459 9460 return features; 9461 } 9462 9463 static int ixgbe_set_features(struct net_device *netdev, 9464 netdev_features_t features) 9465 { 9466 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9467 netdev_features_t changed = netdev->features ^ features; 9468 bool need_reset = false; 9469 9470 /* Make sure RSC matches LRO, reset if change */ 9471 if (!(features & NETIF_F_LRO)) { 9472 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9473 need_reset = true; 9474 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9475 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9476 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9477 if (adapter->rx_itr_setting == 1 || 9478 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9479 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9480 need_reset = true; 9481 } else if ((changed ^ features) & NETIF_F_LRO) { 9482 e_info(probe, "rx-usecs set too low, " 9483 "disabling RSC\n"); 9484 } 9485 } 9486 9487 /* 9488 * Check if Flow Director n-tuple support or hw_tc support was 9489 * enabled or disabled. If the state changed, we need to reset. 9490 */ 9491 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9492 /* turn off ATR, enable perfect filters and reset */ 9493 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9494 need_reset = true; 9495 9496 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9497 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9498 } else { 9499 /* turn off perfect filters, enable ATR and reset */ 9500 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9501 need_reset = true; 9502 9503 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9504 9505 /* We cannot enable ATR if SR-IOV is enabled */ 9506 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9507 /* We cannot enable ATR if we have 2 or more tcs */ 9508 (adapter->hw_tcs > 1) || 9509 /* We cannot enable ATR if RSS is disabled */ 9510 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9511 /* A sample rate of 0 indicates ATR disabled */ 9512 (!adapter->atr_sample_rate)) 9513 ; /* do nothing not supported */ 9514 else /* otherwise supported and set the flag */ 9515 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9516 } 9517 9518 if (changed & NETIF_F_RXALL) 9519 need_reset = true; 9520 9521 netdev->features = features; 9522 9523 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9524 if (features & NETIF_F_RXCSUM) { 9525 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9526 } else { 9527 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9528 9529 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9530 } 9531 } 9532 9533 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9534 if (features & NETIF_F_RXCSUM) { 9535 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9536 } else { 9537 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9538 9539 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9540 } 9541 } 9542 9543 if (need_reset) 9544 ixgbe_do_reset(netdev); 9545 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9546 NETIF_F_HW_VLAN_CTAG_FILTER)) 9547 ixgbe_set_rx_mode(netdev); 9548 9549 return 0; 9550 } 9551 9552 /** 9553 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9554 * @dev: The port's netdev 9555 * @ti: Tunnel endpoint information 9556 **/ 9557 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9558 struct udp_tunnel_info *ti) 9559 { 9560 struct ixgbe_adapter *adapter = netdev_priv(dev); 9561 struct ixgbe_hw *hw = &adapter->hw; 9562 __be16 port = ti->port; 9563 u32 port_shift = 0; 9564 u32 reg; 9565 9566 if (ti->sa_family != AF_INET) 9567 return; 9568 9569 switch (ti->type) { 9570 case UDP_TUNNEL_TYPE_VXLAN: 9571 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9572 return; 9573 9574 if (adapter->vxlan_port == port) 9575 return; 9576 9577 if (adapter->vxlan_port) { 9578 netdev_info(dev, 9579 "VXLAN port %d set, not adding port %d\n", 9580 ntohs(adapter->vxlan_port), 9581 ntohs(port)); 9582 return; 9583 } 9584 9585 adapter->vxlan_port = port; 9586 break; 9587 case UDP_TUNNEL_TYPE_GENEVE: 9588 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9589 return; 9590 9591 if (adapter->geneve_port == port) 9592 return; 9593 9594 if (adapter->geneve_port) { 9595 netdev_info(dev, 9596 "GENEVE port %d set, not adding port %d\n", 9597 ntohs(adapter->geneve_port), 9598 ntohs(port)); 9599 return; 9600 } 9601 9602 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9603 adapter->geneve_port = port; 9604 break; 9605 default: 9606 return; 9607 } 9608 9609 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9610 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9611 } 9612 9613 /** 9614 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9615 * @dev: The port's netdev 9616 * @ti: Tunnel endpoint information 9617 **/ 9618 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9619 struct udp_tunnel_info *ti) 9620 { 9621 struct ixgbe_adapter *adapter = netdev_priv(dev); 9622 u32 port_mask; 9623 9624 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9625 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9626 return; 9627 9628 if (ti->sa_family != AF_INET) 9629 return; 9630 9631 switch (ti->type) { 9632 case UDP_TUNNEL_TYPE_VXLAN: 9633 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9634 return; 9635 9636 if (adapter->vxlan_port != ti->port) { 9637 netdev_info(dev, "VXLAN port %d not found\n", 9638 ntohs(ti->port)); 9639 return; 9640 } 9641 9642 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9643 break; 9644 case UDP_TUNNEL_TYPE_GENEVE: 9645 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9646 return; 9647 9648 if (adapter->geneve_port != ti->port) { 9649 netdev_info(dev, "GENEVE port %d not found\n", 9650 ntohs(ti->port)); 9651 return; 9652 } 9653 9654 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9655 break; 9656 default: 9657 return; 9658 } 9659 9660 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9661 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9662 } 9663 9664 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9665 struct net_device *dev, 9666 const unsigned char *addr, u16 vid, 9667 u16 flags) 9668 { 9669 /* guarantee we can provide a unique filter for the unicast address */ 9670 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9671 struct ixgbe_adapter *adapter = netdev_priv(dev); 9672 u16 pool = VMDQ_P(0); 9673 9674 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9675 return -ENOMEM; 9676 } 9677 9678 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9679 } 9680 9681 /** 9682 * ixgbe_configure_bridge_mode - set various bridge modes 9683 * @adapter: the private structure 9684 * @mode: requested bridge mode 9685 * 9686 * Configure some settings require for various bridge modes. 9687 **/ 9688 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9689 __u16 mode) 9690 { 9691 struct ixgbe_hw *hw = &adapter->hw; 9692 unsigned int p, num_pools; 9693 u32 vmdctl; 9694 9695 switch (mode) { 9696 case BRIDGE_MODE_VEPA: 9697 /* disable Tx loopback, rely on switch hairpin mode */ 9698 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9699 9700 /* must enable Rx switching replication to allow multicast 9701 * packet reception on all VFs, and to enable source address 9702 * pruning. 9703 */ 9704 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9705 vmdctl |= IXGBE_VT_CTL_REPLEN; 9706 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9707 9708 /* enable Rx source address pruning. Note, this requires 9709 * replication to be enabled or else it does nothing. 9710 */ 9711 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9712 for (p = 0; p < num_pools; p++) { 9713 if (hw->mac.ops.set_source_address_pruning) 9714 hw->mac.ops.set_source_address_pruning(hw, 9715 true, 9716 p); 9717 } 9718 break; 9719 case BRIDGE_MODE_VEB: 9720 /* enable Tx loopback for internal VF/PF communication */ 9721 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9722 IXGBE_PFDTXGSWC_VT_LBEN); 9723 9724 /* disable Rx switching replication unless we have SR-IOV 9725 * virtual functions 9726 */ 9727 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9728 if (!adapter->num_vfs) 9729 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9730 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9731 9732 /* disable Rx source address pruning, since we don't expect to 9733 * be receiving external loopback of our transmitted frames. 9734 */ 9735 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9736 for (p = 0; p < num_pools; p++) { 9737 if (hw->mac.ops.set_source_address_pruning) 9738 hw->mac.ops.set_source_address_pruning(hw, 9739 false, 9740 p); 9741 } 9742 break; 9743 default: 9744 return -EINVAL; 9745 } 9746 9747 adapter->bridge_mode = mode; 9748 9749 e_info(drv, "enabling bridge mode: %s\n", 9750 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9751 9752 return 0; 9753 } 9754 9755 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9756 struct nlmsghdr *nlh, u16 flags) 9757 { 9758 struct ixgbe_adapter *adapter = netdev_priv(dev); 9759 struct nlattr *attr, *br_spec; 9760 int rem; 9761 9762 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9763 return -EOPNOTSUPP; 9764 9765 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9766 if (!br_spec) 9767 return -EINVAL; 9768 9769 nla_for_each_nested(attr, br_spec, rem) { 9770 int status; 9771 __u16 mode; 9772 9773 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9774 continue; 9775 9776 if (nla_len(attr) < sizeof(mode)) 9777 return -EINVAL; 9778 9779 mode = nla_get_u16(attr); 9780 status = ixgbe_configure_bridge_mode(adapter, mode); 9781 if (status) 9782 return status; 9783 9784 break; 9785 } 9786 9787 return 0; 9788 } 9789 9790 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9791 struct net_device *dev, 9792 u32 filter_mask, int nlflags) 9793 { 9794 struct ixgbe_adapter *adapter = netdev_priv(dev); 9795 9796 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9797 return 0; 9798 9799 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9800 adapter->bridge_mode, 0, 0, nlflags, 9801 filter_mask, NULL); 9802 } 9803 9804 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9805 { 9806 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 9807 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9808 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 9809 int tcs = adapter->hw_tcs ? : 1; 9810 unsigned int limit; 9811 int pool, err; 9812 9813 /* Hardware has a limited number of available pools. Each VF, and the 9814 * PF require a pool. Check to ensure we don't attempt to use more 9815 * then the available number of pools. 9816 */ 9817 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9818 return ERR_PTR(-EINVAL); 9819 9820 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9821 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 9822 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 9823 return ERR_PTR(-EBUSY); 9824 9825 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 9826 if (!fwd_adapter) 9827 return ERR_PTR(-ENOMEM); 9828 9829 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9830 set_bit(pool, adapter->fwd_bitmask); 9831 limit = find_last_bit(adapter->fwd_bitmask, adapter->num_rx_pools + 1); 9832 9833 /* Enable VMDq flag so device will be set in VM mode */ 9834 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 9835 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9836 9837 fwd_adapter->pool = pool; 9838 fwd_adapter->real_adapter = adapter; 9839 9840 /* Force reinit of ring allocation with VMDQ enabled */ 9841 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 9842 9843 if (!err && netif_running(pdev)) 9844 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 9845 9846 if (!err) 9847 return fwd_adapter; 9848 9849 /* unwind counter and free adapter struct */ 9850 netdev_info(pdev, 9851 "%s: dfwd hardware acceleration failed\n", vdev->name); 9852 clear_bit(pool, adapter->fwd_bitmask); 9853 kfree(fwd_adapter); 9854 return ERR_PTR(err); 9855 } 9856 9857 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9858 { 9859 struct ixgbe_fwd_adapter *accel = priv; 9860 struct ixgbe_adapter *adapter = accel->real_adapter; 9861 unsigned int rxbase = accel->rx_base_queue; 9862 unsigned int limit, i; 9863 9864 /* delete unicast filter associated with offloaded interface */ 9865 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 9866 VMDQ_P(accel->pool)); 9867 9868 /* disable ability to receive packets for this pool */ 9869 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VMOLR(accel->pool), 0); 9870 9871 /* Allow remaining Rx packets to get flushed out of the 9872 * Rx FIFO before we drop the netdev for the ring. 9873 */ 9874 usleep_range(10000, 20000); 9875 9876 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 9877 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 9878 struct ixgbe_q_vector *qv = ring->q_vector; 9879 9880 /* Make sure we aren't processing any packets and clear 9881 * netdev to shut down the ring. 9882 */ 9883 if (netif_running(adapter->netdev)) 9884 napi_synchronize(&qv->napi); 9885 ring->netdev = NULL; 9886 } 9887 9888 clear_bit(accel->pool, adapter->fwd_bitmask); 9889 limit = find_last_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9890 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9891 9892 /* go back to full RSS if we're done with our VMQs */ 9893 if (adapter->ring_feature[RING_F_VMDQ].limit == 1) { 9894 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9895 num_online_cpus()); 9896 9897 adapter->flags &= ~IXGBE_FLAG_VMDQ_ENABLED; 9898 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; 9899 adapter->ring_feature[RING_F_RSS].limit = rss; 9900 } 9901 9902 ixgbe_setup_tc(pdev, adapter->hw_tcs); 9903 netdev_dbg(pdev, "pool %i:%i queues %i:%i\n", 9904 accel->pool, adapter->num_rx_pools, 9905 accel->rx_base_queue, 9906 accel->rx_base_queue + 9907 adapter->num_rx_queues_per_pool); 9908 kfree(accel); 9909 } 9910 9911 #define IXGBE_MAX_MAC_HDR_LEN 127 9912 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9913 9914 static netdev_features_t 9915 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9916 netdev_features_t features) 9917 { 9918 unsigned int network_hdr_len, mac_hdr_len; 9919 9920 /* Make certain the headers can be described by a context descriptor */ 9921 mac_hdr_len = skb_network_header(skb) - skb->data; 9922 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9923 return features & ~(NETIF_F_HW_CSUM | 9924 NETIF_F_SCTP_CRC | 9925 NETIF_F_HW_VLAN_CTAG_TX | 9926 NETIF_F_TSO | 9927 NETIF_F_TSO6); 9928 9929 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9930 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9931 return features & ~(NETIF_F_HW_CSUM | 9932 NETIF_F_SCTP_CRC | 9933 NETIF_F_TSO | 9934 NETIF_F_TSO6); 9935 9936 /* We can only support IPV4 TSO in tunnels if we can mangle the 9937 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9938 * IPsec offoad sets skb->encapsulation but still can handle 9939 * the TSO, so it's the exception. 9940 */ 9941 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 9942 #ifdef CONFIG_XFRM 9943 if (!skb->sp) 9944 #endif 9945 features &= ~NETIF_F_TSO; 9946 } 9947 9948 return features; 9949 } 9950 9951 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9952 { 9953 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9954 struct ixgbe_adapter *adapter = netdev_priv(dev); 9955 struct bpf_prog *old_prog; 9956 9957 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9958 return -EINVAL; 9959 9960 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9961 return -EINVAL; 9962 9963 /* verify ixgbe ring attributes are sufficient for XDP */ 9964 for (i = 0; i < adapter->num_rx_queues; i++) { 9965 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9966 9967 if (ring_is_rsc_enabled(ring)) 9968 return -EINVAL; 9969 9970 if (frame_size > ixgbe_rx_bufsz(ring)) 9971 return -EINVAL; 9972 } 9973 9974 if (nr_cpu_ids > MAX_XDP_QUEUES) 9975 return -ENOMEM; 9976 9977 old_prog = xchg(&adapter->xdp_prog, prog); 9978 9979 /* If transitioning XDP modes reconfigure rings */ 9980 if (!!prog != !!old_prog) { 9981 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 9982 9983 if (err) { 9984 rcu_assign_pointer(adapter->xdp_prog, old_prog); 9985 return -EINVAL; 9986 } 9987 } else { 9988 for (i = 0; i < adapter->num_rx_queues; i++) 9989 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); 9990 } 9991 9992 if (old_prog) 9993 bpf_prog_put(old_prog); 9994 9995 return 0; 9996 } 9997 9998 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 9999 { 10000 struct ixgbe_adapter *adapter = netdev_priv(dev); 10001 10002 switch (xdp->command) { 10003 case XDP_SETUP_PROG: 10004 return ixgbe_xdp_setup(dev, xdp->prog); 10005 case XDP_QUERY_PROG: 10006 xdp->prog_attached = !!(adapter->xdp_prog); 10007 xdp->prog_id = adapter->xdp_prog ? 10008 adapter->xdp_prog->aux->id : 0; 10009 return 0; 10010 default: 10011 return -EINVAL; 10012 } 10013 } 10014 10015 static int ixgbe_xdp_xmit(struct net_device *dev, struct xdp_frame *xdpf) 10016 { 10017 struct ixgbe_adapter *adapter = netdev_priv(dev); 10018 struct ixgbe_ring *ring; 10019 int err; 10020 10021 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10022 return -ENETDOWN; 10023 10024 /* During program transitions its possible adapter->xdp_prog is assigned 10025 * but ring has not been configured yet. In this case simply abort xmit. 10026 */ 10027 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10028 if (unlikely(!ring)) 10029 return -ENXIO; 10030 10031 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10032 if (err != IXGBE_XDP_TX) 10033 return -ENOSPC; 10034 10035 return 0; 10036 } 10037 10038 static void ixgbe_xdp_flush(struct net_device *dev) 10039 { 10040 struct ixgbe_adapter *adapter = netdev_priv(dev); 10041 struct ixgbe_ring *ring; 10042 10043 /* Its possible the device went down between xdp xmit and flush so 10044 * we need to ensure device is still up. 10045 */ 10046 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10047 return; 10048 10049 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10050 if (unlikely(!ring)) 10051 return; 10052 10053 /* Force memory writes to complete before letting h/w know there 10054 * are new descriptors to fetch. 10055 */ 10056 wmb(); 10057 writel(ring->next_to_use, ring->tail); 10058 10059 return; 10060 } 10061 10062 static const struct net_device_ops ixgbe_netdev_ops = { 10063 .ndo_open = ixgbe_open, 10064 .ndo_stop = ixgbe_close, 10065 .ndo_start_xmit = ixgbe_xmit_frame, 10066 .ndo_select_queue = ixgbe_select_queue, 10067 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10068 .ndo_validate_addr = eth_validate_addr, 10069 .ndo_set_mac_address = ixgbe_set_mac, 10070 .ndo_change_mtu = ixgbe_change_mtu, 10071 .ndo_tx_timeout = ixgbe_tx_timeout, 10072 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10073 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10074 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10075 .ndo_do_ioctl = ixgbe_ioctl, 10076 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10077 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10078 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10079 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10080 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10081 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10082 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10083 .ndo_get_stats64 = ixgbe_get_stats64, 10084 .ndo_setup_tc = __ixgbe_setup_tc, 10085 #ifdef CONFIG_NET_POLL_CONTROLLER 10086 .ndo_poll_controller = ixgbe_netpoll, 10087 #endif 10088 #ifdef IXGBE_FCOE 10089 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10090 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10091 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10092 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10093 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10094 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10095 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10096 #endif /* IXGBE_FCOE */ 10097 .ndo_set_features = ixgbe_set_features, 10098 .ndo_fix_features = ixgbe_fix_features, 10099 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10100 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10101 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10102 .ndo_dfwd_add_station = ixgbe_fwd_add, 10103 .ndo_dfwd_del_station = ixgbe_fwd_del, 10104 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10105 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10106 .ndo_features_check = ixgbe_features_check, 10107 .ndo_bpf = ixgbe_xdp, 10108 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10109 .ndo_xdp_flush = ixgbe_xdp_flush, 10110 }; 10111 10112 /** 10113 * ixgbe_enumerate_functions - Get the number of ports this device has 10114 * @adapter: adapter structure 10115 * 10116 * This function enumerates the phsyical functions co-located on a single slot, 10117 * in order to determine how many ports a device has. This is most useful in 10118 * determining the required GT/s of PCIe bandwidth necessary for optimal 10119 * performance. 10120 **/ 10121 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10122 { 10123 struct pci_dev *entry, *pdev = adapter->pdev; 10124 int physfns = 0; 10125 10126 /* Some cards can not use the generic count PCIe functions method, 10127 * because they are behind a parent switch, so we hardcode these with 10128 * the correct number of functions. 10129 */ 10130 if (ixgbe_pcie_from_parent(&adapter->hw)) 10131 physfns = 4; 10132 10133 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10134 /* don't count virtual functions */ 10135 if (entry->is_virtfn) 10136 continue; 10137 10138 /* When the devices on the bus don't all match our device ID, 10139 * we can't reliably determine the correct number of 10140 * functions. This can occur if a function has been direct 10141 * attached to a virtual machine using VT-d, for example. In 10142 * this case, simply return -1 to indicate this. 10143 */ 10144 if ((entry->vendor != pdev->vendor) || 10145 (entry->device != pdev->device)) 10146 return -1; 10147 10148 physfns++; 10149 } 10150 10151 return physfns; 10152 } 10153 10154 /** 10155 * ixgbe_wol_supported - Check whether device supports WoL 10156 * @adapter: the adapter private structure 10157 * @device_id: the device ID 10158 * @subdevice_id: the subsystem device ID 10159 * 10160 * This function is used by probe and ethtool to determine 10161 * which devices have WoL support 10162 * 10163 **/ 10164 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10165 u16 subdevice_id) 10166 { 10167 struct ixgbe_hw *hw = &adapter->hw; 10168 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10169 10170 /* WOL not supported on 82598 */ 10171 if (hw->mac.type == ixgbe_mac_82598EB) 10172 return false; 10173 10174 /* check eeprom to see if WOL is enabled for X540 and newer */ 10175 if (hw->mac.type >= ixgbe_mac_X540) { 10176 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10177 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10178 (hw->bus.func == 0))) 10179 return true; 10180 } 10181 10182 /* WOL is determined based on device IDs for 82599 MACs */ 10183 switch (device_id) { 10184 case IXGBE_DEV_ID_82599_SFP: 10185 /* Only these subdevices could supports WOL */ 10186 switch (subdevice_id) { 10187 case IXGBE_SUBDEV_ID_82599_560FLR: 10188 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10189 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10190 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10191 /* only support first port */ 10192 if (hw->bus.func != 0) 10193 break; 10194 /* fall through */ 10195 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10196 case IXGBE_SUBDEV_ID_82599_SFP: 10197 case IXGBE_SUBDEV_ID_82599_RNDC: 10198 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10199 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10200 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10201 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10202 return true; 10203 } 10204 break; 10205 case IXGBE_DEV_ID_82599EN_SFP: 10206 /* Only these subdevices support WOL */ 10207 switch (subdevice_id) { 10208 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10209 return true; 10210 } 10211 break; 10212 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10213 /* All except this subdevice support WOL */ 10214 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10215 return true; 10216 break; 10217 case IXGBE_DEV_ID_82599_KX4: 10218 return true; 10219 default: 10220 break; 10221 } 10222 10223 return false; 10224 } 10225 10226 /** 10227 * ixgbe_set_fw_version - Set FW version 10228 * @adapter: the adapter private structure 10229 * 10230 * This function is used by probe and ethtool to determine the FW version to 10231 * format to display. The FW version is taken from the EEPROM/NVM. 10232 */ 10233 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10234 { 10235 struct ixgbe_hw *hw = &adapter->hw; 10236 struct ixgbe_nvm_version nvm_ver; 10237 10238 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10239 if (nvm_ver.oem_valid) { 10240 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10241 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10242 nvm_ver.oem_release); 10243 return; 10244 } 10245 10246 ixgbe_get_etk_id(hw, &nvm_ver); 10247 ixgbe_get_orom_version(hw, &nvm_ver); 10248 10249 if (nvm_ver.or_valid) { 10250 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10251 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10252 nvm_ver.or_build, nvm_ver.or_patch); 10253 return; 10254 } 10255 10256 /* Set ETrack ID format */ 10257 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10258 "0x%08x", nvm_ver.etk_id); 10259 } 10260 10261 /** 10262 * ixgbe_probe - Device Initialization Routine 10263 * @pdev: PCI device information struct 10264 * @ent: entry in ixgbe_pci_tbl 10265 * 10266 * Returns 0 on success, negative on failure 10267 * 10268 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10269 * The OS initialization, configuring of the adapter private structure, 10270 * and a hardware reset occur. 10271 **/ 10272 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10273 { 10274 struct net_device *netdev; 10275 struct ixgbe_adapter *adapter = NULL; 10276 struct ixgbe_hw *hw; 10277 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10278 int i, err, pci_using_dac, expected_gts; 10279 unsigned int indices = MAX_TX_QUEUES; 10280 u8 part_str[IXGBE_PBANUM_LENGTH]; 10281 bool disable_dev = false; 10282 #ifdef IXGBE_FCOE 10283 u16 device_caps; 10284 #endif 10285 u32 eec; 10286 10287 /* Catch broken hardware that put the wrong VF device ID in 10288 * the PCIe SR-IOV capability. 10289 */ 10290 if (pdev->is_virtfn) { 10291 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10292 pci_name(pdev), pdev->vendor, pdev->device); 10293 return -EINVAL; 10294 } 10295 10296 err = pci_enable_device_mem(pdev); 10297 if (err) 10298 return err; 10299 10300 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10301 pci_using_dac = 1; 10302 } else { 10303 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10304 if (err) { 10305 dev_err(&pdev->dev, 10306 "No usable DMA configuration, aborting\n"); 10307 goto err_dma; 10308 } 10309 pci_using_dac = 0; 10310 } 10311 10312 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10313 if (err) { 10314 dev_err(&pdev->dev, 10315 "pci_request_selected_regions failed 0x%x\n", err); 10316 goto err_pci_reg; 10317 } 10318 10319 pci_enable_pcie_error_reporting(pdev); 10320 10321 pci_set_master(pdev); 10322 pci_save_state(pdev); 10323 10324 if (ii->mac == ixgbe_mac_82598EB) { 10325 #ifdef CONFIG_IXGBE_DCB 10326 /* 8 TC w/ 4 queues per TC */ 10327 indices = 4 * MAX_TRAFFIC_CLASS; 10328 #else 10329 indices = IXGBE_MAX_RSS_INDICES; 10330 #endif 10331 } 10332 10333 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10334 if (!netdev) { 10335 err = -ENOMEM; 10336 goto err_alloc_etherdev; 10337 } 10338 10339 SET_NETDEV_DEV(netdev, &pdev->dev); 10340 10341 adapter = netdev_priv(netdev); 10342 10343 adapter->netdev = netdev; 10344 adapter->pdev = pdev; 10345 hw = &adapter->hw; 10346 hw->back = adapter; 10347 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10348 10349 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10350 pci_resource_len(pdev, 0)); 10351 adapter->io_addr = hw->hw_addr; 10352 if (!hw->hw_addr) { 10353 err = -EIO; 10354 goto err_ioremap; 10355 } 10356 10357 netdev->netdev_ops = &ixgbe_netdev_ops; 10358 ixgbe_set_ethtool_ops(netdev); 10359 netdev->watchdog_timeo = 5 * HZ; 10360 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10361 10362 /* Setup hw api */ 10363 hw->mac.ops = *ii->mac_ops; 10364 hw->mac.type = ii->mac; 10365 hw->mvals = ii->mvals; 10366 if (ii->link_ops) 10367 hw->link.ops = *ii->link_ops; 10368 10369 /* EEPROM */ 10370 hw->eeprom.ops = *ii->eeprom_ops; 10371 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10372 if (ixgbe_removed(hw->hw_addr)) { 10373 err = -EIO; 10374 goto err_ioremap; 10375 } 10376 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10377 if (!(eec & BIT(8))) 10378 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10379 10380 /* PHY */ 10381 hw->phy.ops = *ii->phy_ops; 10382 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10383 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10384 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10385 hw->phy.mdio.mmds = 0; 10386 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10387 hw->phy.mdio.dev = netdev; 10388 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10389 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10390 10391 /* setup the private structure */ 10392 err = ixgbe_sw_init(adapter, ii); 10393 if (err) 10394 goto err_sw_init; 10395 10396 /* Make sure the SWFW semaphore is in a valid state */ 10397 if (hw->mac.ops.init_swfw_sync) 10398 hw->mac.ops.init_swfw_sync(hw); 10399 10400 /* Make it possible the adapter to be woken up via WOL */ 10401 switch (adapter->hw.mac.type) { 10402 case ixgbe_mac_82599EB: 10403 case ixgbe_mac_X540: 10404 case ixgbe_mac_X550: 10405 case ixgbe_mac_X550EM_x: 10406 case ixgbe_mac_x550em_a: 10407 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10408 break; 10409 default: 10410 break; 10411 } 10412 10413 /* 10414 * If there is a fan on this device and it has failed log the 10415 * failure. 10416 */ 10417 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10418 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10419 if (esdp & IXGBE_ESDP_SDP1) 10420 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10421 } 10422 10423 if (allow_unsupported_sfp) 10424 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10425 10426 /* reset_hw fills in the perm_addr as well */ 10427 hw->phy.reset_if_overtemp = true; 10428 err = hw->mac.ops.reset_hw(hw); 10429 hw->phy.reset_if_overtemp = false; 10430 ixgbe_set_eee_capable(adapter); 10431 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10432 err = 0; 10433 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10434 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10435 e_dev_err("Reload the driver after installing a supported module.\n"); 10436 goto err_sw_init; 10437 } else if (err) { 10438 e_dev_err("HW Init failed: %d\n", err); 10439 goto err_sw_init; 10440 } 10441 10442 #ifdef CONFIG_PCI_IOV 10443 /* SR-IOV not supported on the 82598 */ 10444 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10445 goto skip_sriov; 10446 /* Mailbox */ 10447 ixgbe_init_mbx_params_pf(hw); 10448 hw->mbx.ops = ii->mbx_ops; 10449 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10450 ixgbe_enable_sriov(adapter, max_vfs); 10451 skip_sriov: 10452 10453 #endif 10454 netdev->features = NETIF_F_SG | 10455 NETIF_F_TSO | 10456 NETIF_F_TSO6 | 10457 NETIF_F_RXHASH | 10458 NETIF_F_RXCSUM | 10459 NETIF_F_HW_CSUM; 10460 10461 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10462 NETIF_F_GSO_GRE_CSUM | \ 10463 NETIF_F_GSO_IPXIP4 | \ 10464 NETIF_F_GSO_IPXIP6 | \ 10465 NETIF_F_GSO_UDP_TUNNEL | \ 10466 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10467 10468 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10469 netdev->features |= NETIF_F_GSO_PARTIAL | 10470 IXGBE_GSO_PARTIAL_FEATURES; 10471 10472 if (hw->mac.type >= ixgbe_mac_82599EB) 10473 netdev->features |= NETIF_F_SCTP_CRC; 10474 10475 /* copy netdev features into list of user selectable features */ 10476 netdev->hw_features |= netdev->features | 10477 NETIF_F_HW_VLAN_CTAG_FILTER | 10478 NETIF_F_HW_VLAN_CTAG_RX | 10479 NETIF_F_HW_VLAN_CTAG_TX | 10480 NETIF_F_RXALL | 10481 NETIF_F_HW_L2FW_DOFFLOAD; 10482 10483 if (hw->mac.type >= ixgbe_mac_82599EB) 10484 netdev->hw_features |= NETIF_F_NTUPLE | 10485 NETIF_F_HW_TC; 10486 10487 if (pci_using_dac) 10488 netdev->features |= NETIF_F_HIGHDMA; 10489 10490 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10491 netdev->hw_enc_features |= netdev->vlan_features; 10492 netdev->mpls_features |= NETIF_F_SG | 10493 NETIF_F_TSO | 10494 NETIF_F_TSO6 | 10495 NETIF_F_HW_CSUM; 10496 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10497 10498 /* set this bit last since it cannot be part of vlan_features */ 10499 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10500 NETIF_F_HW_VLAN_CTAG_RX | 10501 NETIF_F_HW_VLAN_CTAG_TX; 10502 10503 netdev->priv_flags |= IFF_UNICAST_FLT; 10504 netdev->priv_flags |= IFF_SUPP_NOFCS; 10505 10506 /* MTU range: 68 - 9710 */ 10507 netdev->min_mtu = ETH_MIN_MTU; 10508 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10509 10510 #ifdef CONFIG_IXGBE_DCB 10511 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10512 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10513 #endif 10514 10515 #ifdef IXGBE_FCOE 10516 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10517 unsigned int fcoe_l; 10518 10519 if (hw->mac.ops.get_device_caps) { 10520 hw->mac.ops.get_device_caps(hw, &device_caps); 10521 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10522 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10523 } 10524 10525 10526 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10527 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10528 10529 netdev->features |= NETIF_F_FSO | 10530 NETIF_F_FCOE_CRC; 10531 10532 netdev->vlan_features |= NETIF_F_FSO | 10533 NETIF_F_FCOE_CRC | 10534 NETIF_F_FCOE_MTU; 10535 } 10536 #endif /* IXGBE_FCOE */ 10537 ixgbe_init_ipsec_offload(adapter); 10538 10539 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10540 netdev->hw_features |= NETIF_F_LRO; 10541 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10542 netdev->features |= NETIF_F_LRO; 10543 10544 /* make sure the EEPROM is good */ 10545 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10546 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10547 err = -EIO; 10548 goto err_sw_init; 10549 } 10550 10551 eth_platform_get_mac_address(&adapter->pdev->dev, 10552 adapter->hw.mac.perm_addr); 10553 10554 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10555 10556 if (!is_valid_ether_addr(netdev->dev_addr)) { 10557 e_dev_err("invalid MAC address\n"); 10558 err = -EIO; 10559 goto err_sw_init; 10560 } 10561 10562 /* Set hw->mac.addr to permanent MAC address */ 10563 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10564 ixgbe_mac_set_default_filter(adapter); 10565 10566 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10567 10568 if (ixgbe_removed(hw->hw_addr)) { 10569 err = -EIO; 10570 goto err_sw_init; 10571 } 10572 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10573 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10574 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10575 10576 err = ixgbe_init_interrupt_scheme(adapter); 10577 if (err) 10578 goto err_sw_init; 10579 10580 for (i = 0; i < adapter->num_rx_queues; i++) 10581 u64_stats_init(&adapter->rx_ring[i]->syncp); 10582 for (i = 0; i < adapter->num_tx_queues; i++) 10583 u64_stats_init(&adapter->tx_ring[i]->syncp); 10584 for (i = 0; i < adapter->num_xdp_queues; i++) 10585 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10586 10587 /* WOL not supported for all devices */ 10588 adapter->wol = 0; 10589 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10590 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10591 pdev->subsystem_device); 10592 if (hw->wol_enabled) 10593 adapter->wol = IXGBE_WUFC_MAG; 10594 10595 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10596 10597 /* save off EEPROM version number */ 10598 ixgbe_set_fw_version(adapter); 10599 10600 /* pick up the PCI bus settings for reporting later */ 10601 if (ixgbe_pcie_from_parent(hw)) 10602 ixgbe_get_parent_bus_info(adapter); 10603 else 10604 hw->mac.ops.get_bus_info(hw); 10605 10606 /* calculate the expected PCIe bandwidth required for optimal 10607 * performance. Note that some older parts will never have enough 10608 * bandwidth due to being older generation PCIe parts. We clamp these 10609 * parts to ensure no warning is displayed if it can't be fixed. 10610 */ 10611 switch (hw->mac.type) { 10612 case ixgbe_mac_82598EB: 10613 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10614 break; 10615 default: 10616 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10617 break; 10618 } 10619 10620 /* don't check link if we failed to enumerate functions */ 10621 if (expected_gts > 0) 10622 ixgbe_check_minimum_link(adapter, expected_gts); 10623 10624 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10625 if (err) 10626 strlcpy(part_str, "Unknown", sizeof(part_str)); 10627 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10628 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10629 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10630 part_str); 10631 else 10632 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10633 hw->mac.type, hw->phy.type, part_str); 10634 10635 e_dev_info("%pM\n", netdev->dev_addr); 10636 10637 /* reset the hardware with the new settings */ 10638 err = hw->mac.ops.start_hw(hw); 10639 if (err == IXGBE_ERR_EEPROM_VERSION) { 10640 /* We are running on a pre-production device, log a warning */ 10641 e_dev_warn("This device is a pre-production adapter/LOM. " 10642 "Please be aware there may be issues associated " 10643 "with your hardware. If you are experiencing " 10644 "problems please contact your Intel or hardware " 10645 "representative who provided you with this " 10646 "hardware.\n"); 10647 } 10648 strcpy(netdev->name, "eth%d"); 10649 pci_set_drvdata(pdev, adapter); 10650 err = register_netdev(netdev); 10651 if (err) 10652 goto err_register; 10653 10654 10655 /* power down the optics for 82599 SFP+ fiber */ 10656 if (hw->mac.ops.disable_tx_laser) 10657 hw->mac.ops.disable_tx_laser(hw); 10658 10659 /* carrier off reporting is important to ethtool even BEFORE open */ 10660 netif_carrier_off(netdev); 10661 10662 #ifdef CONFIG_IXGBE_DCA 10663 if (dca_add_requester(&pdev->dev) == 0) { 10664 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10665 ixgbe_setup_dca(adapter); 10666 } 10667 #endif 10668 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10669 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10670 for (i = 0; i < adapter->num_vfs; i++) 10671 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10672 } 10673 10674 /* firmware requires driver version to be 0xFFFFFFFF 10675 * since os does not support feature 10676 */ 10677 if (hw->mac.ops.set_fw_drv_ver) 10678 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10679 sizeof(ixgbe_driver_version) - 1, 10680 ixgbe_driver_version); 10681 10682 /* add san mac addr to netdev */ 10683 ixgbe_add_sanmac_netdev(netdev); 10684 10685 e_dev_info("%s\n", ixgbe_default_device_descr); 10686 10687 #ifdef CONFIG_IXGBE_HWMON 10688 if (ixgbe_sysfs_init(adapter)) 10689 e_err(probe, "failed to allocate sysfs resources\n"); 10690 #endif /* CONFIG_IXGBE_HWMON */ 10691 10692 ixgbe_dbg_adapter_init(adapter); 10693 10694 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10695 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10696 hw->mac.ops.setup_link(hw, 10697 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10698 true); 10699 10700 return 0; 10701 10702 err_register: 10703 ixgbe_release_hw_control(adapter); 10704 ixgbe_clear_interrupt_scheme(adapter); 10705 err_sw_init: 10706 ixgbe_disable_sriov(adapter); 10707 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10708 iounmap(adapter->io_addr); 10709 kfree(adapter->jump_tables[0]); 10710 kfree(adapter->mac_table); 10711 kfree(adapter->rss_key); 10712 err_ioremap: 10713 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10714 free_netdev(netdev); 10715 err_alloc_etherdev: 10716 pci_release_mem_regions(pdev); 10717 err_pci_reg: 10718 err_dma: 10719 if (!adapter || disable_dev) 10720 pci_disable_device(pdev); 10721 return err; 10722 } 10723 10724 /** 10725 * ixgbe_remove - Device Removal Routine 10726 * @pdev: PCI device information struct 10727 * 10728 * ixgbe_remove is called by the PCI subsystem to alert the driver 10729 * that it should release a PCI device. The could be caused by a 10730 * Hot-Plug event, or because the driver is going to be removed from 10731 * memory. 10732 **/ 10733 static void ixgbe_remove(struct pci_dev *pdev) 10734 { 10735 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10736 struct net_device *netdev; 10737 bool disable_dev; 10738 int i; 10739 10740 /* if !adapter then we already cleaned up in probe */ 10741 if (!adapter) 10742 return; 10743 10744 netdev = adapter->netdev; 10745 ixgbe_dbg_adapter_exit(adapter); 10746 10747 set_bit(__IXGBE_REMOVING, &adapter->state); 10748 cancel_work_sync(&adapter->service_task); 10749 10750 10751 #ifdef CONFIG_IXGBE_DCA 10752 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10753 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10754 dca_remove_requester(&pdev->dev); 10755 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10756 IXGBE_DCA_CTRL_DCA_DISABLE); 10757 } 10758 10759 #endif 10760 #ifdef CONFIG_IXGBE_HWMON 10761 ixgbe_sysfs_exit(adapter); 10762 #endif /* CONFIG_IXGBE_HWMON */ 10763 10764 /* remove the added san mac */ 10765 ixgbe_del_sanmac_netdev(netdev); 10766 10767 #ifdef CONFIG_PCI_IOV 10768 ixgbe_disable_sriov(adapter); 10769 #endif 10770 if (netdev->reg_state == NETREG_REGISTERED) 10771 unregister_netdev(netdev); 10772 10773 ixgbe_stop_ipsec_offload(adapter); 10774 ixgbe_clear_interrupt_scheme(adapter); 10775 10776 ixgbe_release_hw_control(adapter); 10777 10778 #ifdef CONFIG_DCB 10779 kfree(adapter->ixgbe_ieee_pfc); 10780 kfree(adapter->ixgbe_ieee_ets); 10781 10782 #endif 10783 iounmap(adapter->io_addr); 10784 pci_release_mem_regions(pdev); 10785 10786 e_dev_info("complete\n"); 10787 10788 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10789 if (adapter->jump_tables[i]) { 10790 kfree(adapter->jump_tables[i]->input); 10791 kfree(adapter->jump_tables[i]->mask); 10792 } 10793 kfree(adapter->jump_tables[i]); 10794 } 10795 10796 kfree(adapter->mac_table); 10797 kfree(adapter->rss_key); 10798 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10799 free_netdev(netdev); 10800 10801 pci_disable_pcie_error_reporting(pdev); 10802 10803 if (disable_dev) 10804 pci_disable_device(pdev); 10805 } 10806 10807 /** 10808 * ixgbe_io_error_detected - called when PCI error is detected 10809 * @pdev: Pointer to PCI device 10810 * @state: The current pci connection state 10811 * 10812 * This function is called after a PCI bus error affecting 10813 * this device has been detected. 10814 */ 10815 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10816 pci_channel_state_t state) 10817 { 10818 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10819 struct net_device *netdev = adapter->netdev; 10820 10821 #ifdef CONFIG_PCI_IOV 10822 struct ixgbe_hw *hw = &adapter->hw; 10823 struct pci_dev *bdev, *vfdev; 10824 u32 dw0, dw1, dw2, dw3; 10825 int vf, pos; 10826 u16 req_id, pf_func; 10827 10828 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10829 adapter->num_vfs == 0) 10830 goto skip_bad_vf_detection; 10831 10832 bdev = pdev->bus->self; 10833 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10834 bdev = bdev->bus->self; 10835 10836 if (!bdev) 10837 goto skip_bad_vf_detection; 10838 10839 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10840 if (!pos) 10841 goto skip_bad_vf_detection; 10842 10843 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10844 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10845 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10846 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10847 if (ixgbe_removed(hw->hw_addr)) 10848 goto skip_bad_vf_detection; 10849 10850 req_id = dw1 >> 16; 10851 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10852 if (!(req_id & 0x0080)) 10853 goto skip_bad_vf_detection; 10854 10855 pf_func = req_id & 0x01; 10856 if ((pf_func & 1) == (pdev->devfn & 1)) { 10857 unsigned int device_id; 10858 10859 vf = (req_id & 0x7F) >> 1; 10860 e_dev_err("VF %d has caused a PCIe error\n", vf); 10861 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10862 "%8.8x\tdw3: %8.8x\n", 10863 dw0, dw1, dw2, dw3); 10864 switch (adapter->hw.mac.type) { 10865 case ixgbe_mac_82599EB: 10866 device_id = IXGBE_82599_VF_DEVICE_ID; 10867 break; 10868 case ixgbe_mac_X540: 10869 device_id = IXGBE_X540_VF_DEVICE_ID; 10870 break; 10871 case ixgbe_mac_X550: 10872 device_id = IXGBE_DEV_ID_X550_VF; 10873 break; 10874 case ixgbe_mac_X550EM_x: 10875 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10876 break; 10877 case ixgbe_mac_x550em_a: 10878 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10879 break; 10880 default: 10881 device_id = 0; 10882 break; 10883 } 10884 10885 /* Find the pci device of the offending VF */ 10886 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10887 while (vfdev) { 10888 if (vfdev->devfn == (req_id & 0xFF)) 10889 break; 10890 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10891 device_id, vfdev); 10892 } 10893 /* 10894 * There's a slim chance the VF could have been hot plugged, 10895 * so if it is no longer present we don't need to issue the 10896 * VFLR. Just clean up the AER in that case. 10897 */ 10898 if (vfdev) { 10899 pcie_flr(vfdev); 10900 /* Free device reference count */ 10901 pci_dev_put(vfdev); 10902 } 10903 10904 pci_cleanup_aer_uncorrect_error_status(pdev); 10905 } 10906 10907 /* 10908 * Even though the error may have occurred on the other port 10909 * we still need to increment the vf error reference count for 10910 * both ports because the I/O resume function will be called 10911 * for both of them. 10912 */ 10913 adapter->vferr_refcount++; 10914 10915 return PCI_ERS_RESULT_RECOVERED; 10916 10917 skip_bad_vf_detection: 10918 #endif /* CONFIG_PCI_IOV */ 10919 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10920 return PCI_ERS_RESULT_DISCONNECT; 10921 10922 if (!netif_device_present(netdev)) 10923 return PCI_ERS_RESULT_DISCONNECT; 10924 10925 rtnl_lock(); 10926 netif_device_detach(netdev); 10927 10928 if (state == pci_channel_io_perm_failure) { 10929 rtnl_unlock(); 10930 return PCI_ERS_RESULT_DISCONNECT; 10931 } 10932 10933 if (netif_running(netdev)) 10934 ixgbe_close_suspend(adapter); 10935 10936 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10937 pci_disable_device(pdev); 10938 rtnl_unlock(); 10939 10940 /* Request a slot reset. */ 10941 return PCI_ERS_RESULT_NEED_RESET; 10942 } 10943 10944 /** 10945 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10946 * @pdev: Pointer to PCI device 10947 * 10948 * Restart the card from scratch, as if from a cold-boot. 10949 */ 10950 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10951 { 10952 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10953 pci_ers_result_t result; 10954 int err; 10955 10956 if (pci_enable_device_mem(pdev)) { 10957 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10958 result = PCI_ERS_RESULT_DISCONNECT; 10959 } else { 10960 smp_mb__before_atomic(); 10961 clear_bit(__IXGBE_DISABLED, &adapter->state); 10962 adapter->hw.hw_addr = adapter->io_addr; 10963 pci_set_master(pdev); 10964 pci_restore_state(pdev); 10965 pci_save_state(pdev); 10966 10967 pci_wake_from_d3(pdev, false); 10968 10969 ixgbe_reset(adapter); 10970 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10971 result = PCI_ERS_RESULT_RECOVERED; 10972 } 10973 10974 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10975 if (err) { 10976 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10977 "failed 0x%0x\n", err); 10978 /* non-fatal, continue */ 10979 } 10980 10981 return result; 10982 } 10983 10984 /** 10985 * ixgbe_io_resume - called when traffic can start flowing again. 10986 * @pdev: Pointer to PCI device 10987 * 10988 * This callback is called when the error recovery driver tells us that 10989 * its OK to resume normal operation. 10990 */ 10991 static void ixgbe_io_resume(struct pci_dev *pdev) 10992 { 10993 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10994 struct net_device *netdev = adapter->netdev; 10995 10996 #ifdef CONFIG_PCI_IOV 10997 if (adapter->vferr_refcount) { 10998 e_info(drv, "Resuming after VF err\n"); 10999 adapter->vferr_refcount--; 11000 return; 11001 } 11002 11003 #endif 11004 rtnl_lock(); 11005 if (netif_running(netdev)) 11006 ixgbe_open(netdev); 11007 11008 netif_device_attach(netdev); 11009 rtnl_unlock(); 11010 } 11011 11012 static const struct pci_error_handlers ixgbe_err_handler = { 11013 .error_detected = ixgbe_io_error_detected, 11014 .slot_reset = ixgbe_io_slot_reset, 11015 .resume = ixgbe_io_resume, 11016 }; 11017 11018 static struct pci_driver ixgbe_driver = { 11019 .name = ixgbe_driver_name, 11020 .id_table = ixgbe_pci_tbl, 11021 .probe = ixgbe_probe, 11022 .remove = ixgbe_remove, 11023 #ifdef CONFIG_PM 11024 .suspend = ixgbe_suspend, 11025 .resume = ixgbe_resume, 11026 #endif 11027 .shutdown = ixgbe_shutdown, 11028 .sriov_configure = ixgbe_pci_sriov_configure, 11029 .err_handler = &ixgbe_err_handler 11030 }; 11031 11032 /** 11033 * ixgbe_init_module - Driver Registration Routine 11034 * 11035 * ixgbe_init_module is the first routine called when the driver is 11036 * loaded. All it does is register with the PCI subsystem. 11037 **/ 11038 static int __init ixgbe_init_module(void) 11039 { 11040 int ret; 11041 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11042 pr_info("%s\n", ixgbe_copyright); 11043 11044 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11045 if (!ixgbe_wq) { 11046 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11047 return -ENOMEM; 11048 } 11049 11050 ixgbe_dbg_init(); 11051 11052 ret = pci_register_driver(&ixgbe_driver); 11053 if (ret) { 11054 destroy_workqueue(ixgbe_wq); 11055 ixgbe_dbg_exit(); 11056 return ret; 11057 } 11058 11059 #ifdef CONFIG_IXGBE_DCA 11060 dca_register_notify(&dca_notifier); 11061 #endif 11062 11063 return 0; 11064 } 11065 11066 module_init(ixgbe_init_module); 11067 11068 /** 11069 * ixgbe_exit_module - Driver Exit Cleanup Routine 11070 * 11071 * ixgbe_exit_module is called just before the driver is removed 11072 * from memory. 11073 **/ 11074 static void __exit ixgbe_exit_module(void) 11075 { 11076 #ifdef CONFIG_IXGBE_DCA 11077 dca_unregister_notify(&dca_notifier); 11078 #endif 11079 pci_unregister_driver(&ixgbe_driver); 11080 11081 ixgbe_dbg_exit(); 11082 if (ixgbe_wq) { 11083 destroy_workqueue(ixgbe_wq); 11084 ixgbe_wq = NULL; 11085 } 11086 } 11087 11088 #ifdef CONFIG_IXGBE_DCA 11089 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11090 void *p) 11091 { 11092 int ret_val; 11093 11094 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11095 __ixgbe_notify_dca); 11096 11097 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11098 } 11099 11100 #endif /* CONFIG_IXGBE_DCA */ 11101 11102 module_exit(ixgbe_exit_module); 11103 11104 /* ixgbe_main.c */ 11105