1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <scsi/fc/fc_fcoe.h> 53 #include <net/vxlan.h> 54 55 #ifdef CONFIG_OF 56 #include <linux/of_net.h> 57 #endif 58 59 #ifdef CONFIG_SPARC 60 #include <asm/idprom.h> 61 #include <asm/prom.h> 62 #endif 63 64 #include "ixgbe.h" 65 #include "ixgbe_common.h" 66 #include "ixgbe_dcb_82599.h" 67 #include "ixgbe_sriov.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "4.0.1-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2014 Intel Corporation."; 83 84 static const struct ixgbe_info *ixgbe_info_tbl[] = { 85 [board_82598] = &ixgbe_82598_info, 86 [board_82599] = &ixgbe_82599_info, 87 [board_X540] = &ixgbe_X540_info, 88 [board_X550] = &ixgbe_X550_info, 89 [board_X550EM_x] = &ixgbe_X550EM_x_info, 90 }; 91 92 /* ixgbe_pci_tbl - PCI Device ID Table 93 * 94 * Wildcard entries (PCI_ANY_ID) should come last 95 * Last entry must be all 0s 96 * 97 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 98 * Class, Class Mask, private data (not used) } 99 */ 100 static const struct pci_device_id ixgbe_pci_tbl[] = { 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 134 /* required last entry */ 135 {0, } 136 }; 137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 138 139 #ifdef CONFIG_IXGBE_DCA 140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 141 void *p); 142 static struct notifier_block dca_notifier = { 143 .notifier_call = ixgbe_notify_dca, 144 .next = NULL, 145 .priority = 0 146 }; 147 #endif 148 149 #ifdef CONFIG_PCI_IOV 150 static unsigned int max_vfs; 151 module_param(max_vfs, uint, 0); 152 MODULE_PARM_DESC(max_vfs, 153 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 154 #endif /* CONFIG_PCI_IOV */ 155 156 static unsigned int allow_unsupported_sfp; 157 module_param(allow_unsupported_sfp, uint, 0); 158 MODULE_PARM_DESC(allow_unsupported_sfp, 159 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 160 161 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 162 static int debug = -1; 163 module_param(debug, int, 0); 164 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 165 166 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 167 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 168 MODULE_LICENSE("GPL"); 169 MODULE_VERSION(DRV_VERSION); 170 171 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 172 173 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 174 u32 reg, u16 *value) 175 { 176 struct pci_dev *parent_dev; 177 struct pci_bus *parent_bus; 178 179 parent_bus = adapter->pdev->bus->parent; 180 if (!parent_bus) 181 return -1; 182 183 parent_dev = parent_bus->self; 184 if (!parent_dev) 185 return -1; 186 187 if (!pci_is_pcie(parent_dev)) 188 return -1; 189 190 pcie_capability_read_word(parent_dev, reg, value); 191 if (*value == IXGBE_FAILED_READ_CFG_WORD && 192 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 193 return -1; 194 return 0; 195 } 196 197 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 198 { 199 struct ixgbe_hw *hw = &adapter->hw; 200 u16 link_status = 0; 201 int err; 202 203 hw->bus.type = ixgbe_bus_type_pci_express; 204 205 /* Get the negotiated link width and speed from PCI config space of the 206 * parent, as this device is behind a switch 207 */ 208 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 209 210 /* assume caller will handle error case */ 211 if (err) 212 return err; 213 214 hw->bus.width = ixgbe_convert_bus_width(link_status); 215 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 216 217 return 0; 218 } 219 220 /** 221 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 222 * @hw: hw specific details 223 * 224 * This function is used by probe to determine whether a device's PCI-Express 225 * bandwidth details should be gathered from the parent bus instead of from the 226 * device. Used to ensure that various locations all have the correct device ID 227 * checks. 228 */ 229 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 230 { 231 switch (hw->device_id) { 232 case IXGBE_DEV_ID_82599_SFP_SF_QP: 233 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 234 return true; 235 default: 236 return false; 237 } 238 } 239 240 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 241 int expected_gts) 242 { 243 int max_gts = 0; 244 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 245 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 246 struct pci_dev *pdev; 247 248 /* determine whether to use the the parent device 249 */ 250 if (ixgbe_pcie_from_parent(&adapter->hw)) 251 pdev = adapter->pdev->bus->parent->self; 252 else 253 pdev = adapter->pdev; 254 255 if (pcie_get_minimum_link(pdev, &speed, &width) || 256 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 257 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 258 return; 259 } 260 261 switch (speed) { 262 case PCIE_SPEED_2_5GT: 263 /* 8b/10b encoding reduces max throughput by 20% */ 264 max_gts = 2 * width; 265 break; 266 case PCIE_SPEED_5_0GT: 267 /* 8b/10b encoding reduces max throughput by 20% */ 268 max_gts = 4 * width; 269 break; 270 case PCIE_SPEED_8_0GT: 271 /* 128b/130b encoding reduces throughput by less than 2% */ 272 max_gts = 8 * width; 273 break; 274 default: 275 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 276 return; 277 } 278 279 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 280 max_gts); 281 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 282 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 283 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 284 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 285 "Unknown"), 286 width, 287 (speed == PCIE_SPEED_2_5GT ? "20%" : 288 speed == PCIE_SPEED_5_0GT ? "20%" : 289 speed == PCIE_SPEED_8_0GT ? "<2%" : 290 "Unknown")); 291 292 if (max_gts < expected_gts) { 293 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 294 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 295 expected_gts); 296 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 297 } 298 } 299 300 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 301 { 302 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 303 !test_bit(__IXGBE_REMOVING, &adapter->state) && 304 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 305 schedule_work(&adapter->service_task); 306 } 307 308 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 309 { 310 struct ixgbe_adapter *adapter = hw->back; 311 312 if (!hw->hw_addr) 313 return; 314 hw->hw_addr = NULL; 315 e_dev_err("Adapter removed\n"); 316 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 317 ixgbe_service_event_schedule(adapter); 318 } 319 320 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 321 { 322 u32 value; 323 324 /* The following check not only optimizes a bit by not 325 * performing a read on the status register when the 326 * register just read was a status register read that 327 * returned IXGBE_FAILED_READ_REG. It also blocks any 328 * potential recursion. 329 */ 330 if (reg == IXGBE_STATUS) { 331 ixgbe_remove_adapter(hw); 332 return; 333 } 334 value = ixgbe_read_reg(hw, IXGBE_STATUS); 335 if (value == IXGBE_FAILED_READ_REG) 336 ixgbe_remove_adapter(hw); 337 } 338 339 /** 340 * ixgbe_read_reg - Read from device register 341 * @hw: hw specific details 342 * @reg: offset of register to read 343 * 344 * Returns : value read or IXGBE_FAILED_READ_REG if removed 345 * 346 * This function is used to read device registers. It checks for device 347 * removal by confirming any read that returns all ones by checking the 348 * status register value for all ones. This function avoids reading from 349 * the hardware if a removal was previously detected in which case it 350 * returns IXGBE_FAILED_READ_REG (all ones). 351 */ 352 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 353 { 354 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 355 u32 value; 356 357 if (ixgbe_removed(reg_addr)) 358 return IXGBE_FAILED_READ_REG; 359 value = readl(reg_addr + reg); 360 if (unlikely(value == IXGBE_FAILED_READ_REG)) 361 ixgbe_check_remove(hw, reg); 362 return value; 363 } 364 365 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 366 { 367 u16 value; 368 369 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 370 if (value == IXGBE_FAILED_READ_CFG_WORD) { 371 ixgbe_remove_adapter(hw); 372 return true; 373 } 374 return false; 375 } 376 377 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 378 { 379 struct ixgbe_adapter *adapter = hw->back; 380 u16 value; 381 382 if (ixgbe_removed(hw->hw_addr)) 383 return IXGBE_FAILED_READ_CFG_WORD; 384 pci_read_config_word(adapter->pdev, reg, &value); 385 if (value == IXGBE_FAILED_READ_CFG_WORD && 386 ixgbe_check_cfg_remove(hw, adapter->pdev)) 387 return IXGBE_FAILED_READ_CFG_WORD; 388 return value; 389 } 390 391 #ifdef CONFIG_PCI_IOV 392 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 393 { 394 struct ixgbe_adapter *adapter = hw->back; 395 u32 value; 396 397 if (ixgbe_removed(hw->hw_addr)) 398 return IXGBE_FAILED_READ_CFG_DWORD; 399 pci_read_config_dword(adapter->pdev, reg, &value); 400 if (value == IXGBE_FAILED_READ_CFG_DWORD && 401 ixgbe_check_cfg_remove(hw, adapter->pdev)) 402 return IXGBE_FAILED_READ_CFG_DWORD; 403 return value; 404 } 405 #endif /* CONFIG_PCI_IOV */ 406 407 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 408 { 409 struct ixgbe_adapter *adapter = hw->back; 410 411 if (ixgbe_removed(hw->hw_addr)) 412 return; 413 pci_write_config_word(adapter->pdev, reg, value); 414 } 415 416 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 417 { 418 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 419 420 /* flush memory to make sure state is correct before next watchdog */ 421 smp_mb__before_atomic(); 422 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 423 } 424 425 struct ixgbe_reg_info { 426 u32 ofs; 427 char *name; 428 }; 429 430 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 431 432 /* General Registers */ 433 {IXGBE_CTRL, "CTRL"}, 434 {IXGBE_STATUS, "STATUS"}, 435 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 436 437 /* Interrupt Registers */ 438 {IXGBE_EICR, "EICR"}, 439 440 /* RX Registers */ 441 {IXGBE_SRRCTL(0), "SRRCTL"}, 442 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 443 {IXGBE_RDLEN(0), "RDLEN"}, 444 {IXGBE_RDH(0), "RDH"}, 445 {IXGBE_RDT(0), "RDT"}, 446 {IXGBE_RXDCTL(0), "RXDCTL"}, 447 {IXGBE_RDBAL(0), "RDBAL"}, 448 {IXGBE_RDBAH(0), "RDBAH"}, 449 450 /* TX Registers */ 451 {IXGBE_TDBAL(0), "TDBAL"}, 452 {IXGBE_TDBAH(0), "TDBAH"}, 453 {IXGBE_TDLEN(0), "TDLEN"}, 454 {IXGBE_TDH(0), "TDH"}, 455 {IXGBE_TDT(0), "TDT"}, 456 {IXGBE_TXDCTL(0), "TXDCTL"}, 457 458 /* List Terminator */ 459 { .name = NULL } 460 }; 461 462 463 /* 464 * ixgbe_regdump - register printout routine 465 */ 466 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 467 { 468 int i = 0, j = 0; 469 char rname[16]; 470 u32 regs[64]; 471 472 switch (reginfo->ofs) { 473 case IXGBE_SRRCTL(0): 474 for (i = 0; i < 64; i++) 475 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 476 break; 477 case IXGBE_DCA_RXCTRL(0): 478 for (i = 0; i < 64; i++) 479 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 480 break; 481 case IXGBE_RDLEN(0): 482 for (i = 0; i < 64; i++) 483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 484 break; 485 case IXGBE_RDH(0): 486 for (i = 0; i < 64; i++) 487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 488 break; 489 case IXGBE_RDT(0): 490 for (i = 0; i < 64; i++) 491 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 492 break; 493 case IXGBE_RXDCTL(0): 494 for (i = 0; i < 64; i++) 495 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 496 break; 497 case IXGBE_RDBAL(0): 498 for (i = 0; i < 64; i++) 499 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 500 break; 501 case IXGBE_RDBAH(0): 502 for (i = 0; i < 64; i++) 503 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 504 break; 505 case IXGBE_TDBAL(0): 506 for (i = 0; i < 64; i++) 507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 508 break; 509 case IXGBE_TDBAH(0): 510 for (i = 0; i < 64; i++) 511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 512 break; 513 case IXGBE_TDLEN(0): 514 for (i = 0; i < 64; i++) 515 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 516 break; 517 case IXGBE_TDH(0): 518 for (i = 0; i < 64; i++) 519 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 520 break; 521 case IXGBE_TDT(0): 522 for (i = 0; i < 64; i++) 523 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 524 break; 525 case IXGBE_TXDCTL(0): 526 for (i = 0; i < 64; i++) 527 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 528 break; 529 default: 530 pr_info("%-15s %08x\n", reginfo->name, 531 IXGBE_READ_REG(hw, reginfo->ofs)); 532 return; 533 } 534 535 for (i = 0; i < 8; i++) { 536 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 537 pr_err("%-15s", rname); 538 for (j = 0; j < 8; j++) 539 pr_cont(" %08x", regs[i*8+j]); 540 pr_cont("\n"); 541 } 542 543 } 544 545 /* 546 * ixgbe_dump - Print registers, tx-rings and rx-rings 547 */ 548 static void ixgbe_dump(struct ixgbe_adapter *adapter) 549 { 550 struct net_device *netdev = adapter->netdev; 551 struct ixgbe_hw *hw = &adapter->hw; 552 struct ixgbe_reg_info *reginfo; 553 int n = 0; 554 struct ixgbe_ring *tx_ring; 555 struct ixgbe_tx_buffer *tx_buffer; 556 union ixgbe_adv_tx_desc *tx_desc; 557 struct my_u0 { u64 a; u64 b; } *u0; 558 struct ixgbe_ring *rx_ring; 559 union ixgbe_adv_rx_desc *rx_desc; 560 struct ixgbe_rx_buffer *rx_buffer_info; 561 u32 staterr; 562 int i = 0; 563 564 if (!netif_msg_hw(adapter)) 565 return; 566 567 /* Print netdevice Info */ 568 if (netdev) { 569 dev_info(&adapter->pdev->dev, "Net device Info\n"); 570 pr_info("Device Name state " 571 "trans_start last_rx\n"); 572 pr_info("%-15s %016lX %016lX %016lX\n", 573 netdev->name, 574 netdev->state, 575 netdev->trans_start, 576 netdev->last_rx); 577 } 578 579 /* Print Registers */ 580 dev_info(&adapter->pdev->dev, "Register Dump\n"); 581 pr_info(" Register Name Value\n"); 582 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 583 reginfo->name; reginfo++) { 584 ixgbe_regdump(hw, reginfo); 585 } 586 587 /* Print TX Ring Summary */ 588 if (!netdev || !netif_running(netdev)) 589 return; 590 591 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 592 pr_info(" %s %s %s %s\n", 593 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 594 "leng", "ntw", "timestamp"); 595 for (n = 0; n < adapter->num_tx_queues; n++) { 596 tx_ring = adapter->tx_ring[n]; 597 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 598 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 599 n, tx_ring->next_to_use, tx_ring->next_to_clean, 600 (u64)dma_unmap_addr(tx_buffer, dma), 601 dma_unmap_len(tx_buffer, len), 602 tx_buffer->next_to_watch, 603 (u64)tx_buffer->time_stamp); 604 } 605 606 /* Print TX Rings */ 607 if (!netif_msg_tx_done(adapter)) 608 goto rx_ring_summary; 609 610 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 611 612 /* Transmit Descriptor Formats 613 * 614 * 82598 Advanced Transmit Descriptor 615 * +--------------------------------------------------------------+ 616 * 0 | Buffer Address [63:0] | 617 * +--------------------------------------------------------------+ 618 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 619 * +--------------------------------------------------------------+ 620 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 621 * 622 * 82598 Advanced Transmit Descriptor (Write-Back Format) 623 * +--------------------------------------------------------------+ 624 * 0 | RSV [63:0] | 625 * +--------------------------------------------------------------+ 626 * 8 | RSV | STA | NXTSEQ | 627 * +--------------------------------------------------------------+ 628 * 63 36 35 32 31 0 629 * 630 * 82599+ Advanced Transmit Descriptor 631 * +--------------------------------------------------------------+ 632 * 0 | Buffer Address [63:0] | 633 * +--------------------------------------------------------------+ 634 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 635 * +--------------------------------------------------------------+ 636 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 637 * 638 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 639 * +--------------------------------------------------------------+ 640 * 0 | RSV [63:0] | 641 * +--------------------------------------------------------------+ 642 * 8 | RSV | STA | RSV | 643 * +--------------------------------------------------------------+ 644 * 63 36 35 32 31 0 645 */ 646 647 for (n = 0; n < adapter->num_tx_queues; n++) { 648 tx_ring = adapter->tx_ring[n]; 649 pr_info("------------------------------------\n"); 650 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 651 pr_info("------------------------------------\n"); 652 pr_info("%s%s %s %s %s %s\n", 653 "T [desc] [address 63:0 ] ", 654 "[PlPOIdStDDt Ln] [bi->dma ] ", 655 "leng", "ntw", "timestamp", "bi->skb"); 656 657 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 658 tx_desc = IXGBE_TX_DESC(tx_ring, i); 659 tx_buffer = &tx_ring->tx_buffer_info[i]; 660 u0 = (struct my_u0 *)tx_desc; 661 if (dma_unmap_len(tx_buffer, len) > 0) { 662 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 663 i, 664 le64_to_cpu(u0->a), 665 le64_to_cpu(u0->b), 666 (u64)dma_unmap_addr(tx_buffer, dma), 667 dma_unmap_len(tx_buffer, len), 668 tx_buffer->next_to_watch, 669 (u64)tx_buffer->time_stamp, 670 tx_buffer->skb); 671 if (i == tx_ring->next_to_use && 672 i == tx_ring->next_to_clean) 673 pr_cont(" NTC/U\n"); 674 else if (i == tx_ring->next_to_use) 675 pr_cont(" NTU\n"); 676 else if (i == tx_ring->next_to_clean) 677 pr_cont(" NTC\n"); 678 else 679 pr_cont("\n"); 680 681 if (netif_msg_pktdata(adapter) && 682 tx_buffer->skb) 683 print_hex_dump(KERN_INFO, "", 684 DUMP_PREFIX_ADDRESS, 16, 1, 685 tx_buffer->skb->data, 686 dma_unmap_len(tx_buffer, len), 687 true); 688 } 689 } 690 } 691 692 /* Print RX Rings Summary */ 693 rx_ring_summary: 694 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 695 pr_info("Queue [NTU] [NTC]\n"); 696 for (n = 0; n < adapter->num_rx_queues; n++) { 697 rx_ring = adapter->rx_ring[n]; 698 pr_info("%5d %5X %5X\n", 699 n, rx_ring->next_to_use, rx_ring->next_to_clean); 700 } 701 702 /* Print RX Rings */ 703 if (!netif_msg_rx_status(adapter)) 704 return; 705 706 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 707 708 /* Receive Descriptor Formats 709 * 710 * 82598 Advanced Receive Descriptor (Read) Format 711 * 63 1 0 712 * +-----------------------------------------------------+ 713 * 0 | Packet Buffer Address [63:1] |A0/NSE| 714 * +----------------------------------------------+------+ 715 * 8 | Header Buffer Address [63:1] | DD | 716 * +-----------------------------------------------------+ 717 * 718 * 719 * 82598 Advanced Receive Descriptor (Write-Back) Format 720 * 721 * 63 48 47 32 31 30 21 20 16 15 4 3 0 722 * +------------------------------------------------------+ 723 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 724 * | Packet | IP | | | | Type | Type | 725 * | Checksum | Ident | | | | | | 726 * +------------------------------------------------------+ 727 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 728 * +------------------------------------------------------+ 729 * 63 48 47 32 31 20 19 0 730 * 731 * 82599+ Advanced Receive Descriptor (Read) Format 732 * 63 1 0 733 * +-----------------------------------------------------+ 734 * 0 | Packet Buffer Address [63:1] |A0/NSE| 735 * +----------------------------------------------+------+ 736 * 8 | Header Buffer Address [63:1] | DD | 737 * +-----------------------------------------------------+ 738 * 739 * 740 * 82599+ Advanced Receive Descriptor (Write-Back) Format 741 * 742 * 63 48 47 32 31 30 21 20 17 16 4 3 0 743 * +------------------------------------------------------+ 744 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 745 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 746 * |/ Flow Dir Flt ID | | | | | | 747 * +------------------------------------------------------+ 748 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 749 * +------------------------------------------------------+ 750 * 63 48 47 32 31 20 19 0 751 */ 752 753 for (n = 0; n < adapter->num_rx_queues; n++) { 754 rx_ring = adapter->rx_ring[n]; 755 pr_info("------------------------------------\n"); 756 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 757 pr_info("------------------------------------\n"); 758 pr_info("%s%s%s", 759 "R [desc] [ PktBuf A0] ", 760 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 761 "<-- Adv Rx Read format\n"); 762 pr_info("%s%s%s", 763 "RWB[desc] [PcsmIpSHl PtRs] ", 764 "[vl er S cks ln] ---------------- [bi->skb ] ", 765 "<-- Adv Rx Write-Back format\n"); 766 767 for (i = 0; i < rx_ring->count; i++) { 768 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 769 rx_desc = IXGBE_RX_DESC(rx_ring, i); 770 u0 = (struct my_u0 *)rx_desc; 771 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 772 if (staterr & IXGBE_RXD_STAT_DD) { 773 /* Descriptor Done */ 774 pr_info("RWB[0x%03X] %016llX " 775 "%016llX ---------------- %p", i, 776 le64_to_cpu(u0->a), 777 le64_to_cpu(u0->b), 778 rx_buffer_info->skb); 779 } else { 780 pr_info("R [0x%03X] %016llX " 781 "%016llX %016llX %p", i, 782 le64_to_cpu(u0->a), 783 le64_to_cpu(u0->b), 784 (u64)rx_buffer_info->dma, 785 rx_buffer_info->skb); 786 787 if (netif_msg_pktdata(adapter) && 788 rx_buffer_info->dma) { 789 print_hex_dump(KERN_INFO, "", 790 DUMP_PREFIX_ADDRESS, 16, 1, 791 page_address(rx_buffer_info->page) + 792 rx_buffer_info->page_offset, 793 ixgbe_rx_bufsz(rx_ring), true); 794 } 795 } 796 797 if (i == rx_ring->next_to_use) 798 pr_cont(" NTU\n"); 799 else if (i == rx_ring->next_to_clean) 800 pr_cont(" NTC\n"); 801 else 802 pr_cont("\n"); 803 804 } 805 } 806 } 807 808 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 809 { 810 u32 ctrl_ext; 811 812 /* Let firmware take over control of h/w */ 813 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 814 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 815 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 816 } 817 818 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 819 { 820 u32 ctrl_ext; 821 822 /* Let firmware know the driver has taken over */ 823 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 825 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 826 } 827 828 /** 829 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 830 * @adapter: pointer to adapter struct 831 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 832 * @queue: queue to map the corresponding interrupt to 833 * @msix_vector: the vector to map to the corresponding queue 834 * 835 */ 836 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 837 u8 queue, u8 msix_vector) 838 { 839 u32 ivar, index; 840 struct ixgbe_hw *hw = &adapter->hw; 841 switch (hw->mac.type) { 842 case ixgbe_mac_82598EB: 843 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 844 if (direction == -1) 845 direction = 0; 846 index = (((direction * 64) + queue) >> 2) & 0x1F; 847 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 848 ivar &= ~(0xFF << (8 * (queue & 0x3))); 849 ivar |= (msix_vector << (8 * (queue & 0x3))); 850 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 851 break; 852 case ixgbe_mac_82599EB: 853 case ixgbe_mac_X540: 854 case ixgbe_mac_X550: 855 case ixgbe_mac_X550EM_x: 856 if (direction == -1) { 857 /* other causes */ 858 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 859 index = ((queue & 1) * 8); 860 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 861 ivar &= ~(0xFF << index); 862 ivar |= (msix_vector << index); 863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 864 break; 865 } else { 866 /* tx or rx causes */ 867 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 868 index = ((16 * (queue & 1)) + (8 * direction)); 869 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 870 ivar &= ~(0xFF << index); 871 ivar |= (msix_vector << index); 872 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 873 break; 874 } 875 default: 876 break; 877 } 878 } 879 880 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 881 u64 qmask) 882 { 883 u32 mask; 884 885 switch (adapter->hw.mac.type) { 886 case ixgbe_mac_82598EB: 887 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 889 break; 890 case ixgbe_mac_82599EB: 891 case ixgbe_mac_X540: 892 case ixgbe_mac_X550: 893 case ixgbe_mac_X550EM_x: 894 mask = (qmask & 0xFFFFFFFF); 895 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 896 mask = (qmask >> 32); 897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 898 break; 899 default: 900 break; 901 } 902 } 903 904 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 905 struct ixgbe_tx_buffer *tx_buffer) 906 { 907 if (tx_buffer->skb) { 908 dev_kfree_skb_any(tx_buffer->skb); 909 if (dma_unmap_len(tx_buffer, len)) 910 dma_unmap_single(ring->dev, 911 dma_unmap_addr(tx_buffer, dma), 912 dma_unmap_len(tx_buffer, len), 913 DMA_TO_DEVICE); 914 } else if (dma_unmap_len(tx_buffer, len)) { 915 dma_unmap_page(ring->dev, 916 dma_unmap_addr(tx_buffer, dma), 917 dma_unmap_len(tx_buffer, len), 918 DMA_TO_DEVICE); 919 } 920 tx_buffer->next_to_watch = NULL; 921 tx_buffer->skb = NULL; 922 dma_unmap_len_set(tx_buffer, len, 0); 923 /* tx_buffer must be completely set up in the transmit path */ 924 } 925 926 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 927 { 928 struct ixgbe_hw *hw = &adapter->hw; 929 struct ixgbe_hw_stats *hwstats = &adapter->stats; 930 int i; 931 u32 data; 932 933 if ((hw->fc.current_mode != ixgbe_fc_full) && 934 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 935 return; 936 937 switch (hw->mac.type) { 938 case ixgbe_mac_82598EB: 939 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 940 break; 941 default: 942 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 943 } 944 hwstats->lxoffrxc += data; 945 946 /* refill credits (no tx hang) if we received xoff */ 947 if (!data) 948 return; 949 950 for (i = 0; i < adapter->num_tx_queues; i++) 951 clear_bit(__IXGBE_HANG_CHECK_ARMED, 952 &adapter->tx_ring[i]->state); 953 } 954 955 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 956 { 957 struct ixgbe_hw *hw = &adapter->hw; 958 struct ixgbe_hw_stats *hwstats = &adapter->stats; 959 u32 xoff[8] = {0}; 960 u8 tc; 961 int i; 962 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 963 964 if (adapter->ixgbe_ieee_pfc) 965 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 966 967 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 968 ixgbe_update_xoff_rx_lfc(adapter); 969 return; 970 } 971 972 /* update stats for each tc, only valid with PFC enabled */ 973 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 974 u32 pxoffrxc; 975 976 switch (hw->mac.type) { 977 case ixgbe_mac_82598EB: 978 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 979 break; 980 default: 981 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 982 } 983 hwstats->pxoffrxc[i] += pxoffrxc; 984 /* Get the TC for given UP */ 985 tc = netdev_get_prio_tc_map(adapter->netdev, i); 986 xoff[tc] += pxoffrxc; 987 } 988 989 /* disarm tx queues that have received xoff frames */ 990 for (i = 0; i < adapter->num_tx_queues; i++) { 991 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 992 993 tc = tx_ring->dcb_tc; 994 if (xoff[tc]) 995 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 996 } 997 } 998 999 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1000 { 1001 return ring->stats.packets; 1002 } 1003 1004 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1005 { 1006 struct ixgbe_adapter *adapter; 1007 struct ixgbe_hw *hw; 1008 u32 head, tail; 1009 1010 if (ring->l2_accel_priv) 1011 adapter = ring->l2_accel_priv->real_adapter; 1012 else 1013 adapter = netdev_priv(ring->netdev); 1014 1015 hw = &adapter->hw; 1016 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1017 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1018 1019 if (head != tail) 1020 return (head < tail) ? 1021 tail - head : (tail + ring->count - head); 1022 1023 return 0; 1024 } 1025 1026 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1027 { 1028 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1029 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1030 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1031 1032 clear_check_for_tx_hang(tx_ring); 1033 1034 /* 1035 * Check for a hung queue, but be thorough. This verifies 1036 * that a transmit has been completed since the previous 1037 * check AND there is at least one packet pending. The 1038 * ARMED bit is set to indicate a potential hang. The 1039 * bit is cleared if a pause frame is received to remove 1040 * false hang detection due to PFC or 802.3x frames. By 1041 * requiring this to fail twice we avoid races with 1042 * pfc clearing the ARMED bit and conditions where we 1043 * run the check_tx_hang logic with a transmit completion 1044 * pending but without time to complete it yet. 1045 */ 1046 if (tx_done_old == tx_done && tx_pending) 1047 /* make sure it is true for two checks in a row */ 1048 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1049 &tx_ring->state); 1050 /* update completed stats and continue */ 1051 tx_ring->tx_stats.tx_done_old = tx_done; 1052 /* reset the countdown */ 1053 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1054 1055 return false; 1056 } 1057 1058 /** 1059 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1060 * @adapter: driver private struct 1061 **/ 1062 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1063 { 1064 1065 /* Do the reset outside of interrupt context */ 1066 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1067 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 1068 e_warn(drv, "initiating reset due to tx timeout\n"); 1069 ixgbe_service_event_schedule(adapter); 1070 } 1071 } 1072 1073 /** 1074 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1075 * @q_vector: structure containing interrupt and ring information 1076 * @tx_ring: tx ring to clean 1077 **/ 1078 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1079 struct ixgbe_ring *tx_ring) 1080 { 1081 struct ixgbe_adapter *adapter = q_vector->adapter; 1082 struct ixgbe_tx_buffer *tx_buffer; 1083 union ixgbe_adv_tx_desc *tx_desc; 1084 unsigned int total_bytes = 0, total_packets = 0; 1085 unsigned int budget = q_vector->tx.work_limit; 1086 unsigned int i = tx_ring->next_to_clean; 1087 1088 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1089 return true; 1090 1091 tx_buffer = &tx_ring->tx_buffer_info[i]; 1092 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1093 i -= tx_ring->count; 1094 1095 do { 1096 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1097 1098 /* if next_to_watch is not set then there is no work pending */ 1099 if (!eop_desc) 1100 break; 1101 1102 /* prevent any other reads prior to eop_desc */ 1103 read_barrier_depends(); 1104 1105 /* if DD is not set pending work has not been completed */ 1106 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1107 break; 1108 1109 /* clear next_to_watch to prevent false hangs */ 1110 tx_buffer->next_to_watch = NULL; 1111 1112 /* update the statistics for this packet */ 1113 total_bytes += tx_buffer->bytecount; 1114 total_packets += tx_buffer->gso_segs; 1115 1116 /* free the skb */ 1117 dev_consume_skb_any(tx_buffer->skb); 1118 1119 /* unmap skb header data */ 1120 dma_unmap_single(tx_ring->dev, 1121 dma_unmap_addr(tx_buffer, dma), 1122 dma_unmap_len(tx_buffer, len), 1123 DMA_TO_DEVICE); 1124 1125 /* clear tx_buffer data */ 1126 tx_buffer->skb = NULL; 1127 dma_unmap_len_set(tx_buffer, len, 0); 1128 1129 /* unmap remaining buffers */ 1130 while (tx_desc != eop_desc) { 1131 tx_buffer++; 1132 tx_desc++; 1133 i++; 1134 if (unlikely(!i)) { 1135 i -= tx_ring->count; 1136 tx_buffer = tx_ring->tx_buffer_info; 1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1138 } 1139 1140 /* unmap any remaining paged data */ 1141 if (dma_unmap_len(tx_buffer, len)) { 1142 dma_unmap_page(tx_ring->dev, 1143 dma_unmap_addr(tx_buffer, dma), 1144 dma_unmap_len(tx_buffer, len), 1145 DMA_TO_DEVICE); 1146 dma_unmap_len_set(tx_buffer, len, 0); 1147 } 1148 } 1149 1150 /* move us one more past the eop_desc for start of next pkt */ 1151 tx_buffer++; 1152 tx_desc++; 1153 i++; 1154 if (unlikely(!i)) { 1155 i -= tx_ring->count; 1156 tx_buffer = tx_ring->tx_buffer_info; 1157 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1158 } 1159 1160 /* issue prefetch for next Tx descriptor */ 1161 prefetch(tx_desc); 1162 1163 /* update budget accounting */ 1164 budget--; 1165 } while (likely(budget)); 1166 1167 i += tx_ring->count; 1168 tx_ring->next_to_clean = i; 1169 u64_stats_update_begin(&tx_ring->syncp); 1170 tx_ring->stats.bytes += total_bytes; 1171 tx_ring->stats.packets += total_packets; 1172 u64_stats_update_end(&tx_ring->syncp); 1173 q_vector->tx.total_bytes += total_bytes; 1174 q_vector->tx.total_packets += total_packets; 1175 1176 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1177 /* schedule immediate reset if we believe we hung */ 1178 struct ixgbe_hw *hw = &adapter->hw; 1179 e_err(drv, "Detected Tx Unit Hang\n" 1180 " Tx Queue <%d>\n" 1181 " TDH, TDT <%x>, <%x>\n" 1182 " next_to_use <%x>\n" 1183 " next_to_clean <%x>\n" 1184 "tx_buffer_info[next_to_clean]\n" 1185 " time_stamp <%lx>\n" 1186 " jiffies <%lx>\n", 1187 tx_ring->queue_index, 1188 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1189 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1190 tx_ring->next_to_use, i, 1191 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1192 1193 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 1194 1195 e_info(probe, 1196 "tx hang %d detected on queue %d, resetting adapter\n", 1197 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1198 1199 /* schedule immediate reset if we believe we hung */ 1200 ixgbe_tx_timeout_reset(adapter); 1201 1202 /* the adapter is about to reset, no point in enabling stuff */ 1203 return true; 1204 } 1205 1206 netdev_tx_completed_queue(txring_txq(tx_ring), 1207 total_packets, total_bytes); 1208 1209 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1210 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1211 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1212 /* Make sure that anybody stopping the queue after this 1213 * sees the new next_to_clean. 1214 */ 1215 smp_mb(); 1216 if (__netif_subqueue_stopped(tx_ring->netdev, 1217 tx_ring->queue_index) 1218 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1219 netif_wake_subqueue(tx_ring->netdev, 1220 tx_ring->queue_index); 1221 ++tx_ring->tx_stats.restart_queue; 1222 } 1223 } 1224 1225 return !!budget; 1226 } 1227 1228 #ifdef CONFIG_IXGBE_DCA 1229 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1230 struct ixgbe_ring *tx_ring, 1231 int cpu) 1232 { 1233 struct ixgbe_hw *hw = &adapter->hw; 1234 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1235 u16 reg_offset; 1236 1237 switch (hw->mac.type) { 1238 case ixgbe_mac_82598EB: 1239 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1240 break; 1241 case ixgbe_mac_82599EB: 1242 case ixgbe_mac_X540: 1243 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1244 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1245 break; 1246 default: 1247 /* for unknown hardware do not write register */ 1248 return; 1249 } 1250 1251 /* 1252 * We can enable relaxed ordering for reads, but not writes when 1253 * DCA is enabled. This is due to a known issue in some chipsets 1254 * which will cause the DCA tag to be cleared. 1255 */ 1256 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1257 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1258 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1259 1260 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1261 } 1262 1263 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1264 struct ixgbe_ring *rx_ring, 1265 int cpu) 1266 { 1267 struct ixgbe_hw *hw = &adapter->hw; 1268 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1269 u8 reg_idx = rx_ring->reg_idx; 1270 1271 1272 switch (hw->mac.type) { 1273 case ixgbe_mac_82599EB: 1274 case ixgbe_mac_X540: 1275 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1276 break; 1277 default: 1278 break; 1279 } 1280 1281 /* 1282 * We can enable relaxed ordering for reads, but not writes when 1283 * DCA is enabled. This is due to a known issue in some chipsets 1284 * which will cause the DCA tag to be cleared. 1285 */ 1286 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1287 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1288 1289 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1290 } 1291 1292 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1293 { 1294 struct ixgbe_adapter *adapter = q_vector->adapter; 1295 struct ixgbe_ring *ring; 1296 int cpu = get_cpu(); 1297 1298 if (q_vector->cpu == cpu) 1299 goto out_no_update; 1300 1301 ixgbe_for_each_ring(ring, q_vector->tx) 1302 ixgbe_update_tx_dca(adapter, ring, cpu); 1303 1304 ixgbe_for_each_ring(ring, q_vector->rx) 1305 ixgbe_update_rx_dca(adapter, ring, cpu); 1306 1307 q_vector->cpu = cpu; 1308 out_no_update: 1309 put_cpu(); 1310 } 1311 1312 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1313 { 1314 int i; 1315 1316 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) 1317 return; 1318 1319 /* always use CB2 mode, difference is masked in the CB driver */ 1320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1321 1322 for (i = 0; i < adapter->num_q_vectors; i++) { 1323 adapter->q_vector[i]->cpu = -1; 1324 ixgbe_update_dca(adapter->q_vector[i]); 1325 } 1326 } 1327 1328 static int __ixgbe_notify_dca(struct device *dev, void *data) 1329 { 1330 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1331 unsigned long event = *(unsigned long *)data; 1332 1333 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1334 return 0; 1335 1336 switch (event) { 1337 case DCA_PROVIDER_ADD: 1338 /* if we're already enabled, don't do it again */ 1339 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1340 break; 1341 if (dca_add_requester(dev) == 0) { 1342 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1343 ixgbe_setup_dca(adapter); 1344 break; 1345 } 1346 /* Fall Through since DCA is disabled. */ 1347 case DCA_PROVIDER_REMOVE: 1348 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1349 dca_remove_requester(dev); 1350 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1352 } 1353 break; 1354 } 1355 1356 return 0; 1357 } 1358 1359 #endif /* CONFIG_IXGBE_DCA */ 1360 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1361 union ixgbe_adv_rx_desc *rx_desc, 1362 struct sk_buff *skb) 1363 { 1364 if (ring->netdev->features & NETIF_F_RXHASH) 1365 skb_set_hash(skb, 1366 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1367 PKT_HASH_TYPE_L3); 1368 } 1369 1370 #ifdef IXGBE_FCOE 1371 /** 1372 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1373 * @ring: structure containing ring specific data 1374 * @rx_desc: advanced rx descriptor 1375 * 1376 * Returns : true if it is FCoE pkt 1377 */ 1378 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1379 union ixgbe_adv_rx_desc *rx_desc) 1380 { 1381 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1382 1383 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1384 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1385 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1386 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1387 } 1388 1389 #endif /* IXGBE_FCOE */ 1390 /** 1391 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1392 * @ring: structure containing ring specific data 1393 * @rx_desc: current Rx descriptor being processed 1394 * @skb: skb currently being received and modified 1395 **/ 1396 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1397 union ixgbe_adv_rx_desc *rx_desc, 1398 struct sk_buff *skb) 1399 { 1400 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1401 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; 1402 bool encap_pkt = false; 1403 1404 skb_checksum_none_assert(skb); 1405 1406 /* Rx csum disabled */ 1407 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1408 return; 1409 1410 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) && 1411 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) { 1412 encap_pkt = true; 1413 skb->encapsulation = 1; 1414 skb->ip_summed = CHECKSUM_NONE; 1415 } 1416 1417 /* if IP and error */ 1418 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1419 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1420 ring->rx_stats.csum_err++; 1421 return; 1422 } 1423 1424 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1425 return; 1426 1427 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1428 /* 1429 * 82599 errata, UDP frames with a 0 checksum can be marked as 1430 * checksum errors. 1431 */ 1432 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1433 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1434 return; 1435 1436 ring->rx_stats.csum_err++; 1437 return; 1438 } 1439 1440 /* It must be a TCP or UDP packet with a valid checksum */ 1441 skb->ip_summed = CHECKSUM_UNNECESSARY; 1442 if (encap_pkt) { 1443 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1444 return; 1445 1446 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1447 ring->rx_stats.csum_err++; 1448 return; 1449 } 1450 /* If we checked the outer header let the stack know */ 1451 skb->csum_level = 1; 1452 } 1453 } 1454 1455 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1456 struct ixgbe_rx_buffer *bi) 1457 { 1458 struct page *page = bi->page; 1459 dma_addr_t dma; 1460 1461 /* since we are recycling buffers we should seldom need to alloc */ 1462 if (likely(page)) 1463 return true; 1464 1465 /* alloc new page for storage */ 1466 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1467 if (unlikely(!page)) { 1468 rx_ring->rx_stats.alloc_rx_page_failed++; 1469 return false; 1470 } 1471 1472 /* map page for use */ 1473 dma = dma_map_page(rx_ring->dev, page, 0, 1474 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1475 1476 /* 1477 * if mapping failed free memory back to system since 1478 * there isn't much point in holding memory we can't use 1479 */ 1480 if (dma_mapping_error(rx_ring->dev, dma)) { 1481 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1482 1483 rx_ring->rx_stats.alloc_rx_page_failed++; 1484 return false; 1485 } 1486 1487 bi->dma = dma; 1488 bi->page = page; 1489 bi->page_offset = 0; 1490 1491 return true; 1492 } 1493 1494 /** 1495 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1496 * @rx_ring: ring to place buffers on 1497 * @cleaned_count: number of buffers to replace 1498 **/ 1499 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1500 { 1501 union ixgbe_adv_rx_desc *rx_desc; 1502 struct ixgbe_rx_buffer *bi; 1503 u16 i = rx_ring->next_to_use; 1504 1505 /* nothing to do */ 1506 if (!cleaned_count) 1507 return; 1508 1509 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1510 bi = &rx_ring->rx_buffer_info[i]; 1511 i -= rx_ring->count; 1512 1513 do { 1514 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1515 break; 1516 1517 /* 1518 * Refresh the desc even if buffer_addrs didn't change 1519 * because each write-back erases this info. 1520 */ 1521 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1522 1523 rx_desc++; 1524 bi++; 1525 i++; 1526 if (unlikely(!i)) { 1527 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1528 bi = rx_ring->rx_buffer_info; 1529 i -= rx_ring->count; 1530 } 1531 1532 /* clear the status bits for the next_to_use descriptor */ 1533 rx_desc->wb.upper.status_error = 0; 1534 1535 cleaned_count--; 1536 } while (cleaned_count); 1537 1538 i += rx_ring->count; 1539 1540 if (rx_ring->next_to_use != i) { 1541 rx_ring->next_to_use = i; 1542 1543 /* update next to alloc since we have filled the ring */ 1544 rx_ring->next_to_alloc = i; 1545 1546 /* Force memory writes to complete before letting h/w 1547 * know there are new descriptors to fetch. (Only 1548 * applicable for weak-ordered memory model archs, 1549 * such as IA-64). 1550 */ 1551 wmb(); 1552 writel(i, rx_ring->tail); 1553 } 1554 } 1555 1556 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1557 struct sk_buff *skb) 1558 { 1559 u16 hdr_len = skb_headlen(skb); 1560 1561 /* set gso_size to avoid messing up TCP MSS */ 1562 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1563 IXGBE_CB(skb)->append_cnt); 1564 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1565 } 1566 1567 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1568 struct sk_buff *skb) 1569 { 1570 /* if append_cnt is 0 then frame is not RSC */ 1571 if (!IXGBE_CB(skb)->append_cnt) 1572 return; 1573 1574 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1575 rx_ring->rx_stats.rsc_flush++; 1576 1577 ixgbe_set_rsc_gso_size(rx_ring, skb); 1578 1579 /* gso_size is computed using append_cnt so always clear it last */ 1580 IXGBE_CB(skb)->append_cnt = 0; 1581 } 1582 1583 /** 1584 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1585 * @rx_ring: rx descriptor ring packet is being transacted on 1586 * @rx_desc: pointer to the EOP Rx descriptor 1587 * @skb: pointer to current skb being populated 1588 * 1589 * This function checks the ring, descriptor, and packet information in 1590 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1591 * other fields within the skb. 1592 **/ 1593 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1594 union ixgbe_adv_rx_desc *rx_desc, 1595 struct sk_buff *skb) 1596 { 1597 struct net_device *dev = rx_ring->netdev; 1598 1599 ixgbe_update_rsc_stats(rx_ring, skb); 1600 1601 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1602 1603 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1604 1605 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1606 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb); 1607 1608 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1609 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1610 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1611 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1612 } 1613 1614 skb_record_rx_queue(skb, rx_ring->queue_index); 1615 1616 skb->protocol = eth_type_trans(skb, dev); 1617 } 1618 1619 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1620 struct sk_buff *skb) 1621 { 1622 if (ixgbe_qv_busy_polling(q_vector)) 1623 netif_receive_skb(skb); 1624 else 1625 napi_gro_receive(&q_vector->napi, skb); 1626 } 1627 1628 /** 1629 * ixgbe_is_non_eop - process handling of non-EOP buffers 1630 * @rx_ring: Rx ring being processed 1631 * @rx_desc: Rx descriptor for current buffer 1632 * @skb: Current socket buffer containing buffer in progress 1633 * 1634 * This function updates next to clean. If the buffer is an EOP buffer 1635 * this function exits returning false, otherwise it will place the 1636 * sk_buff in the next buffer to be chained and return true indicating 1637 * that this is in fact a non-EOP buffer. 1638 **/ 1639 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1640 union ixgbe_adv_rx_desc *rx_desc, 1641 struct sk_buff *skb) 1642 { 1643 u32 ntc = rx_ring->next_to_clean + 1; 1644 1645 /* fetch, update, and store next to clean */ 1646 ntc = (ntc < rx_ring->count) ? ntc : 0; 1647 rx_ring->next_to_clean = ntc; 1648 1649 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1650 1651 /* update RSC append count if present */ 1652 if (ring_is_rsc_enabled(rx_ring)) { 1653 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1654 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1655 1656 if (unlikely(rsc_enabled)) { 1657 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1658 1659 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1660 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1661 1662 /* update ntc based on RSC value */ 1663 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1664 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1665 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1666 } 1667 } 1668 1669 /* if we are the last buffer then there is nothing else to do */ 1670 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1671 return false; 1672 1673 /* place skb in next buffer to be received */ 1674 rx_ring->rx_buffer_info[ntc].skb = skb; 1675 rx_ring->rx_stats.non_eop_descs++; 1676 1677 return true; 1678 } 1679 1680 /** 1681 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1682 * @rx_ring: rx descriptor ring packet is being transacted on 1683 * @skb: pointer to current skb being adjusted 1684 * 1685 * This function is an ixgbe specific version of __pskb_pull_tail. The 1686 * main difference between this version and the original function is that 1687 * this function can make several assumptions about the state of things 1688 * that allow for significant optimizations versus the standard function. 1689 * As a result we can do things like drop a frag and maintain an accurate 1690 * truesize for the skb. 1691 */ 1692 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1693 struct sk_buff *skb) 1694 { 1695 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1696 unsigned char *va; 1697 unsigned int pull_len; 1698 1699 /* 1700 * it is valid to use page_address instead of kmap since we are 1701 * working with pages allocated out of the lomem pool per 1702 * alloc_page(GFP_ATOMIC) 1703 */ 1704 va = skb_frag_address(frag); 1705 1706 /* 1707 * we need the header to contain the greater of either ETH_HLEN or 1708 * 60 bytes if the skb->len is less than 60 for skb_pad. 1709 */ 1710 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1711 1712 /* align pull length to size of long to optimize memcpy performance */ 1713 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1714 1715 /* update all of the pointers */ 1716 skb_frag_size_sub(frag, pull_len); 1717 frag->page_offset += pull_len; 1718 skb->data_len -= pull_len; 1719 skb->tail += pull_len; 1720 } 1721 1722 /** 1723 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1724 * @rx_ring: rx descriptor ring packet is being transacted on 1725 * @skb: pointer to current skb being updated 1726 * 1727 * This function provides a basic DMA sync up for the first fragment of an 1728 * skb. The reason for doing this is that the first fragment cannot be 1729 * unmapped until we have reached the end of packet descriptor for a buffer 1730 * chain. 1731 */ 1732 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1733 struct sk_buff *skb) 1734 { 1735 /* if the page was released unmap it, else just sync our portion */ 1736 if (unlikely(IXGBE_CB(skb)->page_released)) { 1737 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1738 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1739 IXGBE_CB(skb)->page_released = false; 1740 } else { 1741 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1742 1743 dma_sync_single_range_for_cpu(rx_ring->dev, 1744 IXGBE_CB(skb)->dma, 1745 frag->page_offset, 1746 ixgbe_rx_bufsz(rx_ring), 1747 DMA_FROM_DEVICE); 1748 } 1749 IXGBE_CB(skb)->dma = 0; 1750 } 1751 1752 /** 1753 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1754 * @rx_ring: rx descriptor ring packet is being transacted on 1755 * @rx_desc: pointer to the EOP Rx descriptor 1756 * @skb: pointer to current skb being fixed 1757 * 1758 * Check for corrupted packet headers caused by senders on the local L2 1759 * embedded NIC switch not setting up their Tx Descriptors right. These 1760 * should be very rare. 1761 * 1762 * Also address the case where we are pulling data in on pages only 1763 * and as such no data is present in the skb header. 1764 * 1765 * In addition if skb is not at least 60 bytes we need to pad it so that 1766 * it is large enough to qualify as a valid Ethernet frame. 1767 * 1768 * Returns true if an error was encountered and skb was freed. 1769 **/ 1770 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1771 union ixgbe_adv_rx_desc *rx_desc, 1772 struct sk_buff *skb) 1773 { 1774 struct net_device *netdev = rx_ring->netdev; 1775 1776 /* verify that the packet does not have any known errors */ 1777 if (unlikely(ixgbe_test_staterr(rx_desc, 1778 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1779 !(netdev->features & NETIF_F_RXALL))) { 1780 dev_kfree_skb_any(skb); 1781 return true; 1782 } 1783 1784 /* place header in linear portion of buffer */ 1785 if (skb_is_nonlinear(skb)) 1786 ixgbe_pull_tail(rx_ring, skb); 1787 1788 #ifdef IXGBE_FCOE 1789 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1790 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1791 return false; 1792 1793 #endif 1794 /* if eth_skb_pad returns an error the skb was freed */ 1795 if (eth_skb_pad(skb)) 1796 return true; 1797 1798 return false; 1799 } 1800 1801 /** 1802 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1803 * @rx_ring: rx descriptor ring to store buffers on 1804 * @old_buff: donor buffer to have page reused 1805 * 1806 * Synchronizes page for reuse by the adapter 1807 **/ 1808 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1809 struct ixgbe_rx_buffer *old_buff) 1810 { 1811 struct ixgbe_rx_buffer *new_buff; 1812 u16 nta = rx_ring->next_to_alloc; 1813 1814 new_buff = &rx_ring->rx_buffer_info[nta]; 1815 1816 /* update, and store next to alloc */ 1817 nta++; 1818 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1819 1820 /* transfer page from old buffer to new buffer */ 1821 *new_buff = *old_buff; 1822 1823 /* sync the buffer for use by the device */ 1824 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1825 new_buff->page_offset, 1826 ixgbe_rx_bufsz(rx_ring), 1827 DMA_FROM_DEVICE); 1828 } 1829 1830 static inline bool ixgbe_page_is_reserved(struct page *page) 1831 { 1832 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc; 1833 } 1834 1835 /** 1836 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1837 * @rx_ring: rx descriptor ring to transact packets on 1838 * @rx_buffer: buffer containing page to add 1839 * @rx_desc: descriptor containing length of buffer written by hardware 1840 * @skb: sk_buff to place the data into 1841 * 1842 * This function will add the data contained in rx_buffer->page to the skb. 1843 * This is done either through a direct copy if the data in the buffer is 1844 * less than the skb header size, otherwise it will just attach the page as 1845 * a frag to the skb. 1846 * 1847 * The function will then update the page offset if necessary and return 1848 * true if the buffer can be reused by the adapter. 1849 **/ 1850 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1851 struct ixgbe_rx_buffer *rx_buffer, 1852 union ixgbe_adv_rx_desc *rx_desc, 1853 struct sk_buff *skb) 1854 { 1855 struct page *page = rx_buffer->page; 1856 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1857 #if (PAGE_SIZE < 8192) 1858 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1859 #else 1860 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1861 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1862 ixgbe_rx_bufsz(rx_ring); 1863 #endif 1864 1865 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1866 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1867 1868 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1869 1870 /* page is not reserved, we can reuse buffer as-is */ 1871 if (likely(!ixgbe_page_is_reserved(page))) 1872 return true; 1873 1874 /* this page cannot be reused so discard it */ 1875 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1876 return false; 1877 } 1878 1879 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1880 rx_buffer->page_offset, size, truesize); 1881 1882 /* avoid re-using remote pages */ 1883 if (unlikely(ixgbe_page_is_reserved(page))) 1884 return false; 1885 1886 #if (PAGE_SIZE < 8192) 1887 /* if we are only owner of page we can reuse it */ 1888 if (unlikely(page_count(page) != 1)) 1889 return false; 1890 1891 /* flip page offset to other buffer */ 1892 rx_buffer->page_offset ^= truesize; 1893 #else 1894 /* move offset up to the next cache line */ 1895 rx_buffer->page_offset += truesize; 1896 1897 if (rx_buffer->page_offset > last_offset) 1898 return false; 1899 #endif 1900 1901 /* Even if we own the page, we are not allowed to use atomic_set() 1902 * This would break get_page_unless_zero() users. 1903 */ 1904 atomic_inc(&page->_count); 1905 1906 return true; 1907 } 1908 1909 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 1910 union ixgbe_adv_rx_desc *rx_desc) 1911 { 1912 struct ixgbe_rx_buffer *rx_buffer; 1913 struct sk_buff *skb; 1914 struct page *page; 1915 1916 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1917 page = rx_buffer->page; 1918 prefetchw(page); 1919 1920 skb = rx_buffer->skb; 1921 1922 if (likely(!skb)) { 1923 void *page_addr = page_address(page) + 1924 rx_buffer->page_offset; 1925 1926 /* prefetch first cache line of first page */ 1927 prefetch(page_addr); 1928 #if L1_CACHE_BYTES < 128 1929 prefetch(page_addr + L1_CACHE_BYTES); 1930 #endif 1931 1932 /* allocate a skb to store the frags */ 1933 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1934 IXGBE_RX_HDR_SIZE); 1935 if (unlikely(!skb)) { 1936 rx_ring->rx_stats.alloc_rx_buff_failed++; 1937 return NULL; 1938 } 1939 1940 /* 1941 * we will be copying header into skb->data in 1942 * pskb_may_pull so it is in our interest to prefetch 1943 * it now to avoid a possible cache miss 1944 */ 1945 prefetchw(skb->data); 1946 1947 /* 1948 * Delay unmapping of the first packet. It carries the 1949 * header information, HW may still access the header 1950 * after the writeback. Only unmap it when EOP is 1951 * reached 1952 */ 1953 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1954 goto dma_sync; 1955 1956 IXGBE_CB(skb)->dma = rx_buffer->dma; 1957 } else { 1958 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 1959 ixgbe_dma_sync_frag(rx_ring, skb); 1960 1961 dma_sync: 1962 /* we are reusing so sync this buffer for CPU use */ 1963 dma_sync_single_range_for_cpu(rx_ring->dev, 1964 rx_buffer->dma, 1965 rx_buffer->page_offset, 1966 ixgbe_rx_bufsz(rx_ring), 1967 DMA_FROM_DEVICE); 1968 1969 rx_buffer->skb = NULL; 1970 } 1971 1972 /* pull page into skb */ 1973 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 1974 /* hand second half of page back to the ring */ 1975 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 1976 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 1977 /* the page has been released from the ring */ 1978 IXGBE_CB(skb)->page_released = true; 1979 } else { 1980 /* we are not reusing the buffer so unmap it */ 1981 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 1982 ixgbe_rx_pg_size(rx_ring), 1983 DMA_FROM_DEVICE); 1984 } 1985 1986 /* clear contents of buffer_info */ 1987 rx_buffer->page = NULL; 1988 1989 return skb; 1990 } 1991 1992 /** 1993 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1994 * @q_vector: structure containing interrupt and ring information 1995 * @rx_ring: rx descriptor ring to transact packets on 1996 * @budget: Total limit on number of packets to process 1997 * 1998 * This function provides a "bounce buffer" approach to Rx interrupt 1999 * processing. The advantage to this is that on systems that have 2000 * expensive overhead for IOMMU access this provides a means of avoiding 2001 * it by maintaining the mapping of the page to the syste. 2002 * 2003 * Returns amount of work completed 2004 **/ 2005 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2006 struct ixgbe_ring *rx_ring, 2007 const int budget) 2008 { 2009 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2010 #ifdef IXGBE_FCOE 2011 struct ixgbe_adapter *adapter = q_vector->adapter; 2012 int ddp_bytes; 2013 unsigned int mss = 0; 2014 #endif /* IXGBE_FCOE */ 2015 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2016 2017 while (likely(total_rx_packets < budget)) { 2018 union ixgbe_adv_rx_desc *rx_desc; 2019 struct sk_buff *skb; 2020 2021 /* return some buffers to hardware, one at a time is too slow */ 2022 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2023 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2024 cleaned_count = 0; 2025 } 2026 2027 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2028 2029 if (!rx_desc->wb.upper.status_error) 2030 break; 2031 2032 /* This memory barrier is needed to keep us from reading 2033 * any other fields out of the rx_desc until we know the 2034 * descriptor has been written back 2035 */ 2036 dma_rmb(); 2037 2038 /* retrieve a buffer from the ring */ 2039 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 2040 2041 /* exit if we failed to retrieve a buffer */ 2042 if (!skb) 2043 break; 2044 2045 cleaned_count++; 2046 2047 /* place incomplete frames back on ring for completion */ 2048 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2049 continue; 2050 2051 /* verify the packet layout is correct */ 2052 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2053 continue; 2054 2055 /* probably a little skewed due to removing CRC */ 2056 total_rx_bytes += skb->len; 2057 2058 /* populate checksum, timestamp, VLAN, and protocol */ 2059 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2060 2061 #ifdef IXGBE_FCOE 2062 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2063 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2064 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2065 /* include DDPed FCoE data */ 2066 if (ddp_bytes > 0) { 2067 if (!mss) { 2068 mss = rx_ring->netdev->mtu - 2069 sizeof(struct fcoe_hdr) - 2070 sizeof(struct fc_frame_header) - 2071 sizeof(struct fcoe_crc_eof); 2072 if (mss > 512) 2073 mss &= ~511; 2074 } 2075 total_rx_bytes += ddp_bytes; 2076 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2077 mss); 2078 } 2079 if (!ddp_bytes) { 2080 dev_kfree_skb_any(skb); 2081 continue; 2082 } 2083 } 2084 2085 #endif /* IXGBE_FCOE */ 2086 skb_mark_napi_id(skb, &q_vector->napi); 2087 ixgbe_rx_skb(q_vector, skb); 2088 2089 /* update budget accounting */ 2090 total_rx_packets++; 2091 } 2092 2093 u64_stats_update_begin(&rx_ring->syncp); 2094 rx_ring->stats.packets += total_rx_packets; 2095 rx_ring->stats.bytes += total_rx_bytes; 2096 u64_stats_update_end(&rx_ring->syncp); 2097 q_vector->rx.total_packets += total_rx_packets; 2098 q_vector->rx.total_bytes += total_rx_bytes; 2099 2100 return total_rx_packets; 2101 } 2102 2103 #ifdef CONFIG_NET_RX_BUSY_POLL 2104 /* must be called with local_bh_disable()d */ 2105 static int ixgbe_low_latency_recv(struct napi_struct *napi) 2106 { 2107 struct ixgbe_q_vector *q_vector = 2108 container_of(napi, struct ixgbe_q_vector, napi); 2109 struct ixgbe_adapter *adapter = q_vector->adapter; 2110 struct ixgbe_ring *ring; 2111 int found = 0; 2112 2113 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2114 return LL_FLUSH_FAILED; 2115 2116 if (!ixgbe_qv_lock_poll(q_vector)) 2117 return LL_FLUSH_BUSY; 2118 2119 ixgbe_for_each_ring(ring, q_vector->rx) { 2120 found = ixgbe_clean_rx_irq(q_vector, ring, 4); 2121 #ifdef BP_EXTENDED_STATS 2122 if (found) 2123 ring->stats.cleaned += found; 2124 else 2125 ring->stats.misses++; 2126 #endif 2127 if (found) 2128 break; 2129 } 2130 2131 ixgbe_qv_unlock_poll(q_vector); 2132 2133 return found; 2134 } 2135 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2136 2137 /** 2138 * ixgbe_configure_msix - Configure MSI-X hardware 2139 * @adapter: board private structure 2140 * 2141 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2142 * interrupts. 2143 **/ 2144 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2145 { 2146 struct ixgbe_q_vector *q_vector; 2147 int v_idx; 2148 u32 mask; 2149 2150 /* Populate MSIX to EITR Select */ 2151 if (adapter->num_vfs > 32) { 2152 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 2153 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2154 } 2155 2156 /* 2157 * Populate the IVAR table and set the ITR values to the 2158 * corresponding register. 2159 */ 2160 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2161 struct ixgbe_ring *ring; 2162 q_vector = adapter->q_vector[v_idx]; 2163 2164 ixgbe_for_each_ring(ring, q_vector->rx) 2165 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2166 2167 ixgbe_for_each_ring(ring, q_vector->tx) 2168 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2169 2170 ixgbe_write_eitr(q_vector); 2171 } 2172 2173 switch (adapter->hw.mac.type) { 2174 case ixgbe_mac_82598EB: 2175 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2176 v_idx); 2177 break; 2178 case ixgbe_mac_82599EB: 2179 case ixgbe_mac_X540: 2180 case ixgbe_mac_X550: 2181 case ixgbe_mac_X550EM_x: 2182 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2183 break; 2184 default: 2185 break; 2186 } 2187 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2188 2189 /* set up to autoclear timer, and the vectors */ 2190 mask = IXGBE_EIMS_ENABLE_MASK; 2191 mask &= ~(IXGBE_EIMS_OTHER | 2192 IXGBE_EIMS_MAILBOX | 2193 IXGBE_EIMS_LSC); 2194 2195 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2196 } 2197 2198 enum latency_range { 2199 lowest_latency = 0, 2200 low_latency = 1, 2201 bulk_latency = 2, 2202 latency_invalid = 255 2203 }; 2204 2205 /** 2206 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2207 * @q_vector: structure containing interrupt and ring information 2208 * @ring_container: structure containing ring performance data 2209 * 2210 * Stores a new ITR value based on packets and byte 2211 * counts during the last interrupt. The advantage of per interrupt 2212 * computation is faster updates and more accurate ITR for the current 2213 * traffic pattern. Constants in this function were computed 2214 * based on theoretical maximum wire speed and thresholds were set based 2215 * on testing data as well as attempting to minimize response time 2216 * while increasing bulk throughput. 2217 * this functionality is controlled by the InterruptThrottleRate module 2218 * parameter (see ixgbe_param.c) 2219 **/ 2220 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2221 struct ixgbe_ring_container *ring_container) 2222 { 2223 int bytes = ring_container->total_bytes; 2224 int packets = ring_container->total_packets; 2225 u32 timepassed_us; 2226 u64 bytes_perint; 2227 u8 itr_setting = ring_container->itr; 2228 2229 if (packets == 0) 2230 return; 2231 2232 /* simple throttlerate management 2233 * 0-10MB/s lowest (100000 ints/s) 2234 * 10-20MB/s low (20000 ints/s) 2235 * 20-1249MB/s bulk (8000 ints/s) 2236 */ 2237 /* what was last interrupt timeslice? */ 2238 timepassed_us = q_vector->itr >> 2; 2239 if (timepassed_us == 0) 2240 return; 2241 2242 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2243 2244 switch (itr_setting) { 2245 case lowest_latency: 2246 if (bytes_perint > 10) 2247 itr_setting = low_latency; 2248 break; 2249 case low_latency: 2250 if (bytes_perint > 20) 2251 itr_setting = bulk_latency; 2252 else if (bytes_perint <= 10) 2253 itr_setting = lowest_latency; 2254 break; 2255 case bulk_latency: 2256 if (bytes_perint <= 20) 2257 itr_setting = low_latency; 2258 break; 2259 } 2260 2261 /* clear work counters since we have the values we need */ 2262 ring_container->total_bytes = 0; 2263 ring_container->total_packets = 0; 2264 2265 /* write updated itr to ring container */ 2266 ring_container->itr = itr_setting; 2267 } 2268 2269 /** 2270 * ixgbe_write_eitr - write EITR register in hardware specific way 2271 * @q_vector: structure containing interrupt and ring information 2272 * 2273 * This function is made to be called by ethtool and by the driver 2274 * when it needs to update EITR registers at runtime. Hardware 2275 * specific quirks/differences are taken care of here. 2276 */ 2277 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2278 { 2279 struct ixgbe_adapter *adapter = q_vector->adapter; 2280 struct ixgbe_hw *hw = &adapter->hw; 2281 int v_idx = q_vector->v_idx; 2282 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2283 2284 switch (adapter->hw.mac.type) { 2285 case ixgbe_mac_82598EB: 2286 /* must write high and low 16 bits to reset counter */ 2287 itr_reg |= (itr_reg << 16); 2288 break; 2289 case ixgbe_mac_82599EB: 2290 case ixgbe_mac_X540: 2291 case ixgbe_mac_X550: 2292 case ixgbe_mac_X550EM_x: 2293 /* 2294 * set the WDIS bit to not clear the timer bits and cause an 2295 * immediate assertion of the interrupt 2296 */ 2297 itr_reg |= IXGBE_EITR_CNT_WDIS; 2298 break; 2299 default: 2300 break; 2301 } 2302 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2303 } 2304 2305 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2306 { 2307 u32 new_itr = q_vector->itr; 2308 u8 current_itr; 2309 2310 ixgbe_update_itr(q_vector, &q_vector->tx); 2311 ixgbe_update_itr(q_vector, &q_vector->rx); 2312 2313 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2314 2315 switch (current_itr) { 2316 /* counts and packets in update_itr are dependent on these numbers */ 2317 case lowest_latency: 2318 new_itr = IXGBE_100K_ITR; 2319 break; 2320 case low_latency: 2321 new_itr = IXGBE_20K_ITR; 2322 break; 2323 case bulk_latency: 2324 new_itr = IXGBE_8K_ITR; 2325 break; 2326 default: 2327 break; 2328 } 2329 2330 if (new_itr != q_vector->itr) { 2331 /* do an exponential smoothing */ 2332 new_itr = (10 * new_itr * q_vector->itr) / 2333 ((9 * new_itr) + q_vector->itr); 2334 2335 /* save the algorithm value here */ 2336 q_vector->itr = new_itr; 2337 2338 ixgbe_write_eitr(q_vector); 2339 } 2340 } 2341 2342 /** 2343 * ixgbe_check_overtemp_subtask - check for over temperature 2344 * @adapter: pointer to adapter 2345 **/ 2346 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2347 { 2348 struct ixgbe_hw *hw = &adapter->hw; 2349 u32 eicr = adapter->interrupt_event; 2350 2351 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2352 return; 2353 2354 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2355 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2356 return; 2357 2358 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2359 2360 switch (hw->device_id) { 2361 case IXGBE_DEV_ID_82599_T3_LOM: 2362 /* 2363 * Since the warning interrupt is for both ports 2364 * we don't have to check if: 2365 * - This interrupt wasn't for our port. 2366 * - We may have missed the interrupt so always have to 2367 * check if we got a LSC 2368 */ 2369 if (!(eicr & IXGBE_EICR_GPI_SDP0) && 2370 !(eicr & IXGBE_EICR_LSC)) 2371 return; 2372 2373 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2374 u32 speed; 2375 bool link_up = false; 2376 2377 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2378 2379 if (link_up) 2380 return; 2381 } 2382 2383 /* Check if this is not due to overtemp */ 2384 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2385 return; 2386 2387 break; 2388 default: 2389 if (!(eicr & IXGBE_EICR_GPI_SDP0)) 2390 return; 2391 break; 2392 } 2393 e_crit(drv, 2394 "Network adapter has been stopped because it has over heated. " 2395 "Restart the computer. If the problem persists, " 2396 "power off the system and replace the adapter\n"); 2397 2398 adapter->interrupt_event = 0; 2399 } 2400 2401 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2402 { 2403 struct ixgbe_hw *hw = &adapter->hw; 2404 2405 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2406 (eicr & IXGBE_EICR_GPI_SDP1)) { 2407 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2408 /* write to clear the interrupt */ 2409 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2410 } 2411 } 2412 2413 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2414 { 2415 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2416 return; 2417 2418 switch (adapter->hw.mac.type) { 2419 case ixgbe_mac_82599EB: 2420 /* 2421 * Need to check link state so complete overtemp check 2422 * on service task 2423 */ 2424 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && 2425 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2426 adapter->interrupt_event = eicr; 2427 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2428 ixgbe_service_event_schedule(adapter); 2429 return; 2430 } 2431 return; 2432 case ixgbe_mac_X540: 2433 if (!(eicr & IXGBE_EICR_TS)) 2434 return; 2435 break; 2436 default: 2437 return; 2438 } 2439 2440 e_crit(drv, 2441 "Network adapter has been stopped because it has over heated. " 2442 "Restart the computer. If the problem persists, " 2443 "power off the system and replace the adapter\n"); 2444 } 2445 2446 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2447 { 2448 struct ixgbe_hw *hw = &adapter->hw; 2449 2450 if (eicr & IXGBE_EICR_GPI_SDP2) { 2451 /* Clear the interrupt */ 2452 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); 2453 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2454 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2455 ixgbe_service_event_schedule(adapter); 2456 } 2457 } 2458 2459 if (eicr & IXGBE_EICR_GPI_SDP1) { 2460 /* Clear the interrupt */ 2461 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); 2462 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2463 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2464 ixgbe_service_event_schedule(adapter); 2465 } 2466 } 2467 } 2468 2469 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2470 { 2471 struct ixgbe_hw *hw = &adapter->hw; 2472 2473 adapter->lsc_int++; 2474 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2475 adapter->link_check_timeout = jiffies; 2476 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2477 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2478 IXGBE_WRITE_FLUSH(hw); 2479 ixgbe_service_event_schedule(adapter); 2480 } 2481 } 2482 2483 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2484 u64 qmask) 2485 { 2486 u32 mask; 2487 struct ixgbe_hw *hw = &adapter->hw; 2488 2489 switch (hw->mac.type) { 2490 case ixgbe_mac_82598EB: 2491 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2492 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2493 break; 2494 case ixgbe_mac_82599EB: 2495 case ixgbe_mac_X540: 2496 case ixgbe_mac_X550: 2497 case ixgbe_mac_X550EM_x: 2498 mask = (qmask & 0xFFFFFFFF); 2499 if (mask) 2500 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2501 mask = (qmask >> 32); 2502 if (mask) 2503 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2504 break; 2505 default: 2506 break; 2507 } 2508 /* skip the flush */ 2509 } 2510 2511 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2512 u64 qmask) 2513 { 2514 u32 mask; 2515 struct ixgbe_hw *hw = &adapter->hw; 2516 2517 switch (hw->mac.type) { 2518 case ixgbe_mac_82598EB: 2519 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2520 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2521 break; 2522 case ixgbe_mac_82599EB: 2523 case ixgbe_mac_X540: 2524 case ixgbe_mac_X550: 2525 case ixgbe_mac_X550EM_x: 2526 mask = (qmask & 0xFFFFFFFF); 2527 if (mask) 2528 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2529 mask = (qmask >> 32); 2530 if (mask) 2531 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2532 break; 2533 default: 2534 break; 2535 } 2536 /* skip the flush */ 2537 } 2538 2539 /** 2540 * ixgbe_irq_enable - Enable default interrupt generation settings 2541 * @adapter: board private structure 2542 **/ 2543 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2544 bool flush) 2545 { 2546 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2547 2548 /* don't reenable LSC while waiting for link */ 2549 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2550 mask &= ~IXGBE_EIMS_LSC; 2551 2552 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2553 switch (adapter->hw.mac.type) { 2554 case ixgbe_mac_82599EB: 2555 mask |= IXGBE_EIMS_GPI_SDP0; 2556 break; 2557 case ixgbe_mac_X540: 2558 case ixgbe_mac_X550: 2559 case ixgbe_mac_X550EM_x: 2560 mask |= IXGBE_EIMS_TS; 2561 break; 2562 default: 2563 break; 2564 } 2565 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2566 mask |= IXGBE_EIMS_GPI_SDP1; 2567 switch (adapter->hw.mac.type) { 2568 case ixgbe_mac_82599EB: 2569 mask |= IXGBE_EIMS_GPI_SDP1; 2570 mask |= IXGBE_EIMS_GPI_SDP2; 2571 /* fall through */ 2572 case ixgbe_mac_X540: 2573 case ixgbe_mac_X550: 2574 case ixgbe_mac_X550EM_x: 2575 mask |= IXGBE_EIMS_ECC; 2576 mask |= IXGBE_EIMS_MAILBOX; 2577 break; 2578 default: 2579 break; 2580 } 2581 2582 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2583 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2584 mask |= IXGBE_EIMS_FLOW_DIR; 2585 2586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2587 if (queues) 2588 ixgbe_irq_enable_queues(adapter, ~0); 2589 if (flush) 2590 IXGBE_WRITE_FLUSH(&adapter->hw); 2591 } 2592 2593 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2594 { 2595 struct ixgbe_adapter *adapter = data; 2596 struct ixgbe_hw *hw = &adapter->hw; 2597 u32 eicr; 2598 2599 /* 2600 * Workaround for Silicon errata. Use clear-by-write instead 2601 * of clear-by-read. Reading with EICS will return the 2602 * interrupt causes without clearing, which later be done 2603 * with the write to EICR. 2604 */ 2605 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2606 2607 /* The lower 16bits of the EICR register are for the queue interrupts 2608 * which should be masked here in order to not accidentally clear them if 2609 * the bits are high when ixgbe_msix_other is called. There is a race 2610 * condition otherwise which results in possible performance loss 2611 * especially if the ixgbe_msix_other interrupt is triggering 2612 * consistently (as it would when PPS is turned on for the X540 device) 2613 */ 2614 eicr &= 0xFFFF0000; 2615 2616 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2617 2618 if (eicr & IXGBE_EICR_LSC) 2619 ixgbe_check_lsc(adapter); 2620 2621 if (eicr & IXGBE_EICR_MAILBOX) 2622 ixgbe_msg_task(adapter); 2623 2624 switch (hw->mac.type) { 2625 case ixgbe_mac_82599EB: 2626 case ixgbe_mac_X540: 2627 case ixgbe_mac_X550: 2628 case ixgbe_mac_X550EM_x: 2629 if (eicr & IXGBE_EICR_ECC) { 2630 e_info(link, "Received ECC Err, initiating reset\n"); 2631 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2632 ixgbe_service_event_schedule(adapter); 2633 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2634 } 2635 /* Handle Flow Director Full threshold interrupt */ 2636 if (eicr & IXGBE_EICR_FLOW_DIR) { 2637 int reinit_count = 0; 2638 int i; 2639 for (i = 0; i < adapter->num_tx_queues; i++) { 2640 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2641 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2642 &ring->state)) 2643 reinit_count++; 2644 } 2645 if (reinit_count) { 2646 /* no more flow director interrupts until after init */ 2647 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2648 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2649 ixgbe_service_event_schedule(adapter); 2650 } 2651 } 2652 ixgbe_check_sfp_event(adapter, eicr); 2653 ixgbe_check_overtemp_event(adapter, eicr); 2654 break; 2655 default: 2656 break; 2657 } 2658 2659 ixgbe_check_fan_failure(adapter, eicr); 2660 2661 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2662 ixgbe_ptp_check_pps_event(adapter, eicr); 2663 2664 /* re-enable the original interrupt state, no lsc, no queues */ 2665 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2666 ixgbe_irq_enable(adapter, false, false); 2667 2668 return IRQ_HANDLED; 2669 } 2670 2671 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2672 { 2673 struct ixgbe_q_vector *q_vector = data; 2674 2675 /* EIAM disabled interrupts (on this vector) for us */ 2676 2677 if (q_vector->rx.ring || q_vector->tx.ring) 2678 napi_schedule(&q_vector->napi); 2679 2680 return IRQ_HANDLED; 2681 } 2682 2683 /** 2684 * ixgbe_poll - NAPI Rx polling callback 2685 * @napi: structure for representing this polling device 2686 * @budget: how many packets driver is allowed to clean 2687 * 2688 * This function is used for legacy and MSI, NAPI mode 2689 **/ 2690 int ixgbe_poll(struct napi_struct *napi, int budget) 2691 { 2692 struct ixgbe_q_vector *q_vector = 2693 container_of(napi, struct ixgbe_q_vector, napi); 2694 struct ixgbe_adapter *adapter = q_vector->adapter; 2695 struct ixgbe_ring *ring; 2696 int per_ring_budget; 2697 bool clean_complete = true; 2698 2699 #ifdef CONFIG_IXGBE_DCA 2700 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2701 ixgbe_update_dca(q_vector); 2702 #endif 2703 2704 ixgbe_for_each_ring(ring, q_vector->tx) 2705 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); 2706 2707 if (!ixgbe_qv_lock_napi(q_vector)) 2708 return budget; 2709 2710 /* attempt to distribute budget to each queue fairly, but don't allow 2711 * the budget to go below 1 because we'll exit polling */ 2712 if (q_vector->rx.count > 1) 2713 per_ring_budget = max(budget/q_vector->rx.count, 1); 2714 else 2715 per_ring_budget = budget; 2716 2717 ixgbe_for_each_ring(ring, q_vector->rx) 2718 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring, 2719 per_ring_budget) < per_ring_budget); 2720 2721 ixgbe_qv_unlock_napi(q_vector); 2722 /* If all work not completed, return budget and keep polling */ 2723 if (!clean_complete) 2724 return budget; 2725 2726 /* all work done, exit the polling mode */ 2727 napi_complete(napi); 2728 if (adapter->rx_itr_setting & 1) 2729 ixgbe_set_itr(q_vector); 2730 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2731 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2732 2733 return 0; 2734 } 2735 2736 /** 2737 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2738 * @adapter: board private structure 2739 * 2740 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2741 * interrupts from the kernel. 2742 **/ 2743 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2744 { 2745 struct net_device *netdev = adapter->netdev; 2746 int vector, err; 2747 int ri = 0, ti = 0; 2748 2749 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2750 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2751 struct msix_entry *entry = &adapter->msix_entries[vector]; 2752 2753 if (q_vector->tx.ring && q_vector->rx.ring) { 2754 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2755 "%s-%s-%d", netdev->name, "TxRx", ri++); 2756 ti++; 2757 } else if (q_vector->rx.ring) { 2758 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2759 "%s-%s-%d", netdev->name, "rx", ri++); 2760 } else if (q_vector->tx.ring) { 2761 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2762 "%s-%s-%d", netdev->name, "tx", ti++); 2763 } else { 2764 /* skip this unused q_vector */ 2765 continue; 2766 } 2767 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2768 q_vector->name, q_vector); 2769 if (err) { 2770 e_err(probe, "request_irq failed for MSIX interrupt " 2771 "Error: %d\n", err); 2772 goto free_queue_irqs; 2773 } 2774 /* If Flow Director is enabled, set interrupt affinity */ 2775 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2776 /* assign the mask for this irq */ 2777 irq_set_affinity_hint(entry->vector, 2778 &q_vector->affinity_mask); 2779 } 2780 } 2781 2782 err = request_irq(adapter->msix_entries[vector].vector, 2783 ixgbe_msix_other, 0, netdev->name, adapter); 2784 if (err) { 2785 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2786 goto free_queue_irqs; 2787 } 2788 2789 return 0; 2790 2791 free_queue_irqs: 2792 while (vector) { 2793 vector--; 2794 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2795 NULL); 2796 free_irq(adapter->msix_entries[vector].vector, 2797 adapter->q_vector[vector]); 2798 } 2799 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2800 pci_disable_msix(adapter->pdev); 2801 kfree(adapter->msix_entries); 2802 adapter->msix_entries = NULL; 2803 return err; 2804 } 2805 2806 /** 2807 * ixgbe_intr - legacy mode Interrupt Handler 2808 * @irq: interrupt number 2809 * @data: pointer to a network interface device structure 2810 **/ 2811 static irqreturn_t ixgbe_intr(int irq, void *data) 2812 { 2813 struct ixgbe_adapter *adapter = data; 2814 struct ixgbe_hw *hw = &adapter->hw; 2815 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2816 u32 eicr; 2817 2818 /* 2819 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2820 * before the read of EICR. 2821 */ 2822 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2823 2824 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2825 * therefore no explicit interrupt disable is necessary */ 2826 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2827 if (!eicr) { 2828 /* 2829 * shared interrupt alert! 2830 * make sure interrupts are enabled because the read will 2831 * have disabled interrupts due to EIAM 2832 * finish the workaround of silicon errata on 82598. Unmask 2833 * the interrupt that we masked before the EICR read. 2834 */ 2835 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2836 ixgbe_irq_enable(adapter, true, true); 2837 return IRQ_NONE; /* Not our interrupt */ 2838 } 2839 2840 if (eicr & IXGBE_EICR_LSC) 2841 ixgbe_check_lsc(adapter); 2842 2843 switch (hw->mac.type) { 2844 case ixgbe_mac_82599EB: 2845 ixgbe_check_sfp_event(adapter, eicr); 2846 /* Fall through */ 2847 case ixgbe_mac_X540: 2848 case ixgbe_mac_X550: 2849 case ixgbe_mac_X550EM_x: 2850 if (eicr & IXGBE_EICR_ECC) { 2851 e_info(link, "Received ECC Err, initiating reset\n"); 2852 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2853 ixgbe_service_event_schedule(adapter); 2854 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2855 } 2856 ixgbe_check_overtemp_event(adapter, eicr); 2857 break; 2858 default: 2859 break; 2860 } 2861 2862 ixgbe_check_fan_failure(adapter, eicr); 2863 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2864 ixgbe_ptp_check_pps_event(adapter, eicr); 2865 2866 /* would disable interrupts here but EIAM disabled it */ 2867 napi_schedule(&q_vector->napi); 2868 2869 /* 2870 * re-enable link(maybe) and non-queue interrupts, no flush. 2871 * ixgbe_poll will re-enable the queue interrupts 2872 */ 2873 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2874 ixgbe_irq_enable(adapter, false, false); 2875 2876 return IRQ_HANDLED; 2877 } 2878 2879 /** 2880 * ixgbe_request_irq - initialize interrupts 2881 * @adapter: board private structure 2882 * 2883 * Attempts to configure interrupts using the best available 2884 * capabilities of the hardware and kernel. 2885 **/ 2886 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 2887 { 2888 struct net_device *netdev = adapter->netdev; 2889 int err; 2890 2891 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2892 err = ixgbe_request_msix_irqs(adapter); 2893 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 2894 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 2895 netdev->name, adapter); 2896 else 2897 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 2898 netdev->name, adapter); 2899 2900 if (err) 2901 e_err(probe, "request_irq failed, Error %d\n", err); 2902 2903 return err; 2904 } 2905 2906 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 2907 { 2908 int vector; 2909 2910 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2911 free_irq(adapter->pdev->irq, adapter); 2912 return; 2913 } 2914 2915 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2916 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2917 struct msix_entry *entry = &adapter->msix_entries[vector]; 2918 2919 /* free only the irqs that were actually requested */ 2920 if (!q_vector->rx.ring && !q_vector->tx.ring) 2921 continue; 2922 2923 /* clear the affinity_mask in the IRQ descriptor */ 2924 irq_set_affinity_hint(entry->vector, NULL); 2925 2926 free_irq(entry->vector, q_vector); 2927 } 2928 2929 free_irq(adapter->msix_entries[vector++].vector, adapter); 2930 } 2931 2932 /** 2933 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 2934 * @adapter: board private structure 2935 **/ 2936 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 2937 { 2938 switch (adapter->hw.mac.type) { 2939 case ixgbe_mac_82598EB: 2940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 2941 break; 2942 case ixgbe_mac_82599EB: 2943 case ixgbe_mac_X540: 2944 case ixgbe_mac_X550: 2945 case ixgbe_mac_X550EM_x: 2946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 2947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 2948 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 2949 break; 2950 default: 2951 break; 2952 } 2953 IXGBE_WRITE_FLUSH(&adapter->hw); 2954 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2955 int vector; 2956 2957 for (vector = 0; vector < adapter->num_q_vectors; vector++) 2958 synchronize_irq(adapter->msix_entries[vector].vector); 2959 2960 synchronize_irq(adapter->msix_entries[vector++].vector); 2961 } else { 2962 synchronize_irq(adapter->pdev->irq); 2963 } 2964 } 2965 2966 /** 2967 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 2968 * 2969 **/ 2970 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 2971 { 2972 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2973 2974 ixgbe_write_eitr(q_vector); 2975 2976 ixgbe_set_ivar(adapter, 0, 0, 0); 2977 ixgbe_set_ivar(adapter, 1, 0, 0); 2978 2979 e_info(hw, "Legacy interrupt IVAR setup done\n"); 2980 } 2981 2982 /** 2983 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 2984 * @adapter: board private structure 2985 * @ring: structure containing ring specific data 2986 * 2987 * Configure the Tx descriptor ring after a reset. 2988 **/ 2989 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 2990 struct ixgbe_ring *ring) 2991 { 2992 struct ixgbe_hw *hw = &adapter->hw; 2993 u64 tdba = ring->dma; 2994 int wait_loop = 10; 2995 u32 txdctl = IXGBE_TXDCTL_ENABLE; 2996 u8 reg_idx = ring->reg_idx; 2997 2998 /* disable queue to avoid issues while updating state */ 2999 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3000 IXGBE_WRITE_FLUSH(hw); 3001 3002 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3003 (tdba & DMA_BIT_MASK(32))); 3004 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3005 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3006 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3007 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3008 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3009 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3010 3011 /* 3012 * set WTHRESH to encourage burst writeback, it should not be set 3013 * higher than 1 when: 3014 * - ITR is 0 as it could cause false TX hangs 3015 * - ITR is set to > 100k int/sec and BQL is enabled 3016 * 3017 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3018 * to or less than the number of on chip descriptors, which is 3019 * currently 40. 3020 */ 3021 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3022 txdctl |= (1 << 16); /* WTHRESH = 1 */ 3023 else 3024 txdctl |= (8 << 16); /* WTHRESH = 8 */ 3025 3026 /* 3027 * Setting PTHRESH to 32 both improves performance 3028 * and avoids a TX hang with DFP enabled 3029 */ 3030 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 3031 32; /* PTHRESH = 32 */ 3032 3033 /* reinitialize flowdirector state */ 3034 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3035 ring->atr_sample_rate = adapter->atr_sample_rate; 3036 ring->atr_count = 0; 3037 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3038 } else { 3039 ring->atr_sample_rate = 0; 3040 } 3041 3042 /* initialize XPS */ 3043 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3044 struct ixgbe_q_vector *q_vector = ring->q_vector; 3045 3046 if (q_vector) 3047 netif_set_xps_queue(ring->netdev, 3048 &q_vector->affinity_mask, 3049 ring->queue_index); 3050 } 3051 3052 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3053 3054 /* enable queue */ 3055 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3056 3057 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3058 if (hw->mac.type == ixgbe_mac_82598EB && 3059 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3060 return; 3061 3062 /* poll to verify queue is enabled */ 3063 do { 3064 usleep_range(1000, 2000); 3065 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3066 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3067 if (!wait_loop) 3068 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); 3069 } 3070 3071 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3072 { 3073 struct ixgbe_hw *hw = &adapter->hw; 3074 u32 rttdcs, mtqc; 3075 u8 tcs = netdev_get_num_tc(adapter->netdev); 3076 3077 if (hw->mac.type == ixgbe_mac_82598EB) 3078 return; 3079 3080 /* disable the arbiter while setting MTQC */ 3081 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3082 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3083 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3084 3085 /* set transmit pool layout */ 3086 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3087 mtqc = IXGBE_MTQC_VT_ENA; 3088 if (tcs > 4) 3089 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3090 else if (tcs > 1) 3091 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3092 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3093 mtqc |= IXGBE_MTQC_32VF; 3094 else 3095 mtqc |= IXGBE_MTQC_64VF; 3096 } else { 3097 if (tcs > 4) 3098 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3099 else if (tcs > 1) 3100 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3101 else 3102 mtqc = IXGBE_MTQC_64Q_1PB; 3103 } 3104 3105 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3106 3107 /* Enable Security TX Buffer IFG for multiple pb */ 3108 if (tcs) { 3109 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3110 sectx |= IXGBE_SECTX_DCB; 3111 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3112 } 3113 3114 /* re-enable the arbiter */ 3115 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3116 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3117 } 3118 3119 /** 3120 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3121 * @adapter: board private structure 3122 * 3123 * Configure the Tx unit of the MAC after a reset. 3124 **/ 3125 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3126 { 3127 struct ixgbe_hw *hw = &adapter->hw; 3128 u32 dmatxctl; 3129 u32 i; 3130 3131 ixgbe_setup_mtqc(adapter); 3132 3133 if (hw->mac.type != ixgbe_mac_82598EB) { 3134 /* DMATXCTL.EN must be before Tx queues are enabled */ 3135 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3136 dmatxctl |= IXGBE_DMATXCTL_TE; 3137 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3138 } 3139 3140 /* Setup the HW Tx Head and Tail descriptor pointers */ 3141 for (i = 0; i < adapter->num_tx_queues; i++) 3142 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3143 } 3144 3145 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3146 struct ixgbe_ring *ring) 3147 { 3148 struct ixgbe_hw *hw = &adapter->hw; 3149 u8 reg_idx = ring->reg_idx; 3150 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3151 3152 srrctl |= IXGBE_SRRCTL_DROP_EN; 3153 3154 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3155 } 3156 3157 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3158 struct ixgbe_ring *ring) 3159 { 3160 struct ixgbe_hw *hw = &adapter->hw; 3161 u8 reg_idx = ring->reg_idx; 3162 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3163 3164 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3165 3166 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3167 } 3168 3169 #ifdef CONFIG_IXGBE_DCB 3170 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3171 #else 3172 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3173 #endif 3174 { 3175 int i; 3176 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3177 3178 if (adapter->ixgbe_ieee_pfc) 3179 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3180 3181 /* 3182 * We should set the drop enable bit if: 3183 * SR-IOV is enabled 3184 * or 3185 * Number of Rx queues > 1 and flow control is disabled 3186 * 3187 * This allows us to avoid head of line blocking for security 3188 * and performance reasons. 3189 */ 3190 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3191 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3192 for (i = 0; i < adapter->num_rx_queues; i++) 3193 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3194 } else { 3195 for (i = 0; i < adapter->num_rx_queues; i++) 3196 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3197 } 3198 } 3199 3200 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3201 3202 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3203 struct ixgbe_ring *rx_ring) 3204 { 3205 struct ixgbe_hw *hw = &adapter->hw; 3206 u32 srrctl; 3207 u8 reg_idx = rx_ring->reg_idx; 3208 3209 if (hw->mac.type == ixgbe_mac_82598EB) { 3210 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3211 3212 /* 3213 * if VMDq is not active we must program one srrctl register 3214 * per RSS queue since we have enabled RDRXCTL.MVMEN 3215 */ 3216 reg_idx &= mask; 3217 } 3218 3219 /* configure header buffer length, needed for RSC */ 3220 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3221 3222 /* configure the packet buffer length */ 3223 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3224 3225 /* configure descriptor type */ 3226 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3227 3228 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3229 } 3230 3231 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter, const u32 *seed) 3232 { 3233 struct ixgbe_hw *hw = &adapter->hw; 3234 u32 reta = 0; 3235 int i, j; 3236 int reta_entries = 128; 3237 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3238 int indices_multi; 3239 3240 /* 3241 * Program table for at least 2 queues w/ SR-IOV so that VFs can 3242 * make full use of any rings they may have. We will use the 3243 * PSRTYPE register to control how many rings we use within the PF. 3244 */ 3245 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3246 rss_i = 2; 3247 3248 /* Fill out hash function seeds */ 3249 for (i = 0; i < 10; i++) 3250 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); 3251 3252 /* Fill out the redirection table as follows: 3253 * 82598: 128 (8 bit wide) entries containing pair of 4 bit RSS indices 3254 * 82599/X540: 128 (8 bit wide) entries containing 4 bit RSS index 3255 * X550: 512 (8 bit wide) entries containing 6 bit RSS index 3256 */ 3257 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3258 indices_multi = 0x11; 3259 else 3260 indices_multi = 0x1; 3261 3262 switch (adapter->hw.mac.type) { 3263 case ixgbe_mac_X550: 3264 case ixgbe_mac_X550EM_x: 3265 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3266 reta_entries = 512; 3267 default: 3268 break; 3269 } 3270 3271 /* Fill out redirection table */ 3272 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3273 if (j == rss_i) 3274 j = 0; 3275 reta = (reta << 8) | (j * indices_multi); 3276 if ((i & 3) == 3) { 3277 if (i < 128) 3278 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3279 else 3280 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3281 reta); 3282 } 3283 } 3284 } 3285 3286 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter, const u32 *seed) 3287 { 3288 struct ixgbe_hw *hw = &adapter->hw; 3289 u32 vfreta = 0; 3290 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3291 unsigned int pf_pool = adapter->num_vfs; 3292 int i, j; 3293 3294 /* Fill out hash function seeds */ 3295 for (i = 0; i < 10; i++) 3296 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), seed[i]); 3297 3298 /* Fill out the redirection table */ 3299 for (i = 0, j = 0; i < 64; i++, j++) { 3300 if (j == rss_i) 3301 j = 0; 3302 vfreta = (vfreta << 8) | j; 3303 if ((i & 3) == 3) 3304 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3305 vfreta); 3306 } 3307 } 3308 3309 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3310 { 3311 struct ixgbe_hw *hw = &adapter->hw; 3312 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3313 u32 rss_key[10]; 3314 u32 rxcsum; 3315 3316 /* Disable indicating checksum in descriptor, enables RSS hash */ 3317 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3318 rxcsum |= IXGBE_RXCSUM_PCSD; 3319 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3320 3321 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3322 if (adapter->ring_feature[RING_F_RSS].mask) 3323 mrqc = IXGBE_MRQC_RSSEN; 3324 } else { 3325 u8 tcs = netdev_get_num_tc(adapter->netdev); 3326 3327 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3328 if (tcs > 4) 3329 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3330 else if (tcs > 1) 3331 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3332 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3333 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3334 else 3335 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3336 } else { 3337 if (tcs > 4) 3338 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3339 else if (tcs > 1) 3340 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3341 else 3342 mrqc = IXGBE_MRQC_RSSEN; 3343 } 3344 } 3345 3346 /* Perform hash on these packet types */ 3347 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3348 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3349 IXGBE_MRQC_RSS_FIELD_IPV6 | 3350 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3351 3352 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3353 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3354 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3355 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3356 3357 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 3358 if ((hw->mac.type >= ixgbe_mac_X550) && 3359 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3360 unsigned int pf_pool = adapter->num_vfs; 3361 3362 /* Enable VF RSS mode */ 3363 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3364 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3365 3366 /* Setup RSS through the VF registers */ 3367 ixgbe_setup_vfreta(adapter, rss_key); 3368 vfmrqc = IXGBE_MRQC_RSSEN; 3369 vfmrqc |= rss_field; 3370 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3371 } else { 3372 ixgbe_setup_reta(adapter, rss_key); 3373 mrqc |= rss_field; 3374 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3375 } 3376 } 3377 3378 /** 3379 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3380 * @adapter: address of board private structure 3381 * @index: index of ring to set 3382 **/ 3383 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3384 struct ixgbe_ring *ring) 3385 { 3386 struct ixgbe_hw *hw = &adapter->hw; 3387 u32 rscctrl; 3388 u8 reg_idx = ring->reg_idx; 3389 3390 if (!ring_is_rsc_enabled(ring)) 3391 return; 3392 3393 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3394 rscctrl |= IXGBE_RSCCTL_RSCEN; 3395 /* 3396 * we must limit the number of descriptors so that the 3397 * total size of max desc * buf_len is not greater 3398 * than 65536 3399 */ 3400 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3401 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3402 } 3403 3404 #define IXGBE_MAX_RX_DESC_POLL 10 3405 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3406 struct ixgbe_ring *ring) 3407 { 3408 struct ixgbe_hw *hw = &adapter->hw; 3409 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3410 u32 rxdctl; 3411 u8 reg_idx = ring->reg_idx; 3412 3413 if (ixgbe_removed(hw->hw_addr)) 3414 return; 3415 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3416 if (hw->mac.type == ixgbe_mac_82598EB && 3417 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3418 return; 3419 3420 do { 3421 usleep_range(1000, 2000); 3422 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3423 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3424 3425 if (!wait_loop) { 3426 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3427 "the polling period\n", reg_idx); 3428 } 3429 } 3430 3431 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3432 struct ixgbe_ring *ring) 3433 { 3434 struct ixgbe_hw *hw = &adapter->hw; 3435 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3436 u32 rxdctl; 3437 u8 reg_idx = ring->reg_idx; 3438 3439 if (ixgbe_removed(hw->hw_addr)) 3440 return; 3441 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3442 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3443 3444 /* write value back with RXDCTL.ENABLE bit cleared */ 3445 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3446 3447 if (hw->mac.type == ixgbe_mac_82598EB && 3448 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3449 return; 3450 3451 /* the hardware may take up to 100us to really disable the rx queue */ 3452 do { 3453 udelay(10); 3454 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3455 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3456 3457 if (!wait_loop) { 3458 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3459 "the polling period\n", reg_idx); 3460 } 3461 } 3462 3463 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3464 struct ixgbe_ring *ring) 3465 { 3466 struct ixgbe_hw *hw = &adapter->hw; 3467 u64 rdba = ring->dma; 3468 u32 rxdctl; 3469 u8 reg_idx = ring->reg_idx; 3470 3471 /* disable queue to avoid issues while updating state */ 3472 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3473 ixgbe_disable_rx_queue(adapter, ring); 3474 3475 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3476 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3477 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3478 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3479 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3480 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3481 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3482 3483 ixgbe_configure_srrctl(adapter, ring); 3484 ixgbe_configure_rscctl(adapter, ring); 3485 3486 if (hw->mac.type == ixgbe_mac_82598EB) { 3487 /* 3488 * enable cache line friendly hardware writes: 3489 * PTHRESH=32 descriptors (half the internal cache), 3490 * this also removes ugly rx_no_buffer_count increment 3491 * HTHRESH=4 descriptors (to minimize latency on fetch) 3492 * WTHRESH=8 burst writeback up to two cache lines 3493 */ 3494 rxdctl &= ~0x3FFFFF; 3495 rxdctl |= 0x080420; 3496 } 3497 3498 /* enable receive descriptor ring */ 3499 rxdctl |= IXGBE_RXDCTL_ENABLE; 3500 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3501 3502 ixgbe_rx_desc_queue_enable(adapter, ring); 3503 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3504 } 3505 3506 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3507 { 3508 struct ixgbe_hw *hw = &adapter->hw; 3509 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3510 u16 pool; 3511 3512 /* PSRTYPE must be initialized in non 82598 adapters */ 3513 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3514 IXGBE_PSRTYPE_UDPHDR | 3515 IXGBE_PSRTYPE_IPV4HDR | 3516 IXGBE_PSRTYPE_L2HDR | 3517 IXGBE_PSRTYPE_IPV6HDR; 3518 3519 if (hw->mac.type == ixgbe_mac_82598EB) 3520 return; 3521 3522 if (rss_i > 3) 3523 psrtype |= 2 << 29; 3524 else if (rss_i > 1) 3525 psrtype |= 1 << 29; 3526 3527 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3528 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3529 } 3530 3531 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3532 { 3533 struct ixgbe_hw *hw = &adapter->hw; 3534 u32 reg_offset, vf_shift; 3535 u32 gcr_ext, vmdctl; 3536 int i; 3537 3538 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3539 return; 3540 3541 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3542 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3543 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3544 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3545 vmdctl |= IXGBE_VT_CTL_REPLEN; 3546 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3547 3548 vf_shift = VMDQ_P(0) % 32; 3549 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3550 3551 /* Enable only the PF's pool for Tx/Rx */ 3552 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3553 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3554 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3555 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3556 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 3557 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3558 3559 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3560 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3561 3562 /* 3563 * Set up VF register offsets for selected VT Mode, 3564 * i.e. 32 or 64 VFs for SR-IOV 3565 */ 3566 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3567 case IXGBE_82599_VMDQ_8Q_MASK: 3568 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3569 break; 3570 case IXGBE_82599_VMDQ_4Q_MASK: 3571 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3572 break; 3573 default: 3574 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3575 break; 3576 } 3577 3578 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3579 3580 3581 /* Enable MAC Anti-Spoofing */ 3582 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), 3583 adapter->num_vfs); 3584 3585 /* Ensure LLDP is set for Ethertype Antispoofing if we will be 3586 * calling set_ethertype_anti_spoofing for each VF in loop below 3587 */ 3588 if (hw->mac.ops.set_ethertype_anti_spoofing) 3589 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP), 3590 (IXGBE_ETQF_FILTER_EN | /* enable filter */ 3591 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */ 3592 IXGBE_ETH_P_LLDP)); /* LLDP eth type */ 3593 3594 /* For VFs that have spoof checking turned off */ 3595 for (i = 0; i < adapter->num_vfs; i++) { 3596 if (!adapter->vfinfo[i].spoofchk_enabled) 3597 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3598 3599 /* enable ethertype anti spoofing if hw supports it */ 3600 if (hw->mac.ops.set_ethertype_anti_spoofing) 3601 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i); 3602 } 3603 } 3604 3605 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3606 { 3607 struct ixgbe_hw *hw = &adapter->hw; 3608 struct net_device *netdev = adapter->netdev; 3609 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3610 struct ixgbe_ring *rx_ring; 3611 int i; 3612 u32 mhadd, hlreg0; 3613 3614 #ifdef IXGBE_FCOE 3615 /* adjust max frame to be able to do baby jumbo for FCoE */ 3616 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3617 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3618 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3619 3620 #endif /* IXGBE_FCOE */ 3621 3622 /* adjust max frame to be at least the size of a standard frame */ 3623 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3624 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3625 3626 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3627 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3628 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3629 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3630 3631 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3632 } 3633 3634 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3635 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3636 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3637 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3638 3639 /* 3640 * Setup the HW Rx Head and Tail Descriptor Pointers and 3641 * the Base and Length of the Rx Descriptor Ring 3642 */ 3643 for (i = 0; i < adapter->num_rx_queues; i++) { 3644 rx_ring = adapter->rx_ring[i]; 3645 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3646 set_ring_rsc_enabled(rx_ring); 3647 else 3648 clear_ring_rsc_enabled(rx_ring); 3649 } 3650 } 3651 3652 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3653 { 3654 struct ixgbe_hw *hw = &adapter->hw; 3655 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3656 3657 switch (hw->mac.type) { 3658 case ixgbe_mac_X550: 3659 case ixgbe_mac_X550EM_x: 3660 case ixgbe_mac_82598EB: 3661 /* 3662 * For VMDq support of different descriptor types or 3663 * buffer sizes through the use of multiple SRRCTL 3664 * registers, RDRXCTL.MVMEN must be set to 1 3665 * 3666 * also, the manual doesn't mention it clearly but DCA hints 3667 * will only use queue 0's tags unless this bit is set. Side 3668 * effects of setting this bit are only that SRRCTL must be 3669 * fully programmed [0..15] 3670 */ 3671 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3672 break; 3673 case ixgbe_mac_82599EB: 3674 case ixgbe_mac_X540: 3675 /* Disable RSC for ACK packets */ 3676 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3677 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3678 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3679 /* hardware requires some bits to be set by default */ 3680 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3681 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3682 break; 3683 default: 3684 /* We should do nothing since we don't know this hardware */ 3685 return; 3686 } 3687 3688 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3689 } 3690 3691 /** 3692 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3693 * @adapter: board private structure 3694 * 3695 * Configure the Rx unit of the MAC after a reset. 3696 **/ 3697 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3698 { 3699 struct ixgbe_hw *hw = &adapter->hw; 3700 int i; 3701 u32 rxctrl, rfctl; 3702 3703 /* disable receives while setting up the descriptors */ 3704 hw->mac.ops.disable_rx(hw); 3705 3706 ixgbe_setup_psrtype(adapter); 3707 ixgbe_setup_rdrxctl(adapter); 3708 3709 /* RSC Setup */ 3710 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 3711 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 3712 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 3713 rfctl |= IXGBE_RFCTL_RSC_DIS; 3714 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 3715 3716 /* Program registers for the distribution of queues */ 3717 ixgbe_setup_mrqc(adapter); 3718 3719 /* set_rx_buffer_len must be called before ring initialization */ 3720 ixgbe_set_rx_buffer_len(adapter); 3721 3722 /* 3723 * Setup the HW Rx Head and Tail Descriptor Pointers and 3724 * the Base and Length of the Rx Descriptor Ring 3725 */ 3726 for (i = 0; i < adapter->num_rx_queues; i++) 3727 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3728 3729 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3730 /* disable drop enable for 82598 parts */ 3731 if (hw->mac.type == ixgbe_mac_82598EB) 3732 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3733 3734 /* enable all receives */ 3735 rxctrl |= IXGBE_RXCTRL_RXEN; 3736 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3737 } 3738 3739 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 3740 __be16 proto, u16 vid) 3741 { 3742 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3743 struct ixgbe_hw *hw = &adapter->hw; 3744 3745 /* add VID to filter table */ 3746 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); 3747 set_bit(vid, adapter->active_vlans); 3748 3749 return 0; 3750 } 3751 3752 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 3753 __be16 proto, u16 vid) 3754 { 3755 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3756 struct ixgbe_hw *hw = &adapter->hw; 3757 3758 /* remove VID from filter table */ 3759 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); 3760 clear_bit(vid, adapter->active_vlans); 3761 3762 return 0; 3763 } 3764 3765 /** 3766 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 3767 * @adapter: driver data 3768 */ 3769 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 3770 { 3771 struct ixgbe_hw *hw = &adapter->hw; 3772 u32 vlnctrl; 3773 int i, j; 3774 3775 switch (hw->mac.type) { 3776 case ixgbe_mac_82598EB: 3777 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3778 vlnctrl &= ~IXGBE_VLNCTRL_VME; 3779 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3780 break; 3781 case ixgbe_mac_82599EB: 3782 case ixgbe_mac_X540: 3783 case ixgbe_mac_X550: 3784 case ixgbe_mac_X550EM_x: 3785 for (i = 0; i < adapter->num_rx_queues; i++) { 3786 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3787 3788 if (ring->l2_accel_priv) 3789 continue; 3790 j = ring->reg_idx; 3791 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3792 vlnctrl &= ~IXGBE_RXDCTL_VME; 3793 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3794 } 3795 break; 3796 default: 3797 break; 3798 } 3799 } 3800 3801 /** 3802 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 3803 * @adapter: driver data 3804 */ 3805 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 3806 { 3807 struct ixgbe_hw *hw = &adapter->hw; 3808 u32 vlnctrl; 3809 int i, j; 3810 3811 switch (hw->mac.type) { 3812 case ixgbe_mac_82598EB: 3813 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3814 vlnctrl |= IXGBE_VLNCTRL_VME; 3815 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3816 break; 3817 case ixgbe_mac_82599EB: 3818 case ixgbe_mac_X540: 3819 case ixgbe_mac_X550: 3820 case ixgbe_mac_X550EM_x: 3821 for (i = 0; i < adapter->num_rx_queues; i++) { 3822 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3823 3824 if (ring->l2_accel_priv) 3825 continue; 3826 j = ring->reg_idx; 3827 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3828 vlnctrl |= IXGBE_RXDCTL_VME; 3829 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3830 } 3831 break; 3832 default: 3833 break; 3834 } 3835 } 3836 3837 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 3838 { 3839 u16 vid; 3840 3841 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 3842 3843 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 3844 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 3845 } 3846 3847 /** 3848 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 3849 * @netdev: network interface device structure 3850 * 3851 * Writes multicast address list to the MTA hash table. 3852 * Returns: -ENOMEM on failure 3853 * 0 on no addresses written 3854 * X on writing X addresses to MTA 3855 **/ 3856 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 3857 { 3858 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3859 struct ixgbe_hw *hw = &adapter->hw; 3860 3861 if (!netif_running(netdev)) 3862 return 0; 3863 3864 if (hw->mac.ops.update_mc_addr_list) 3865 hw->mac.ops.update_mc_addr_list(hw, netdev); 3866 else 3867 return -ENOMEM; 3868 3869 #ifdef CONFIG_PCI_IOV 3870 ixgbe_restore_vf_multicasts(adapter); 3871 #endif 3872 3873 return netdev_mc_count(netdev); 3874 } 3875 3876 #ifdef CONFIG_PCI_IOV 3877 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 3878 { 3879 struct ixgbe_hw *hw = &adapter->hw; 3880 int i; 3881 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3882 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3883 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr, 3884 adapter->mac_table[i].queue, 3885 IXGBE_RAH_AV); 3886 else 3887 hw->mac.ops.clear_rar(hw, i); 3888 3889 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED); 3890 } 3891 } 3892 #endif 3893 3894 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 3895 { 3896 struct ixgbe_hw *hw = &adapter->hw; 3897 int i; 3898 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3899 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) { 3900 if (adapter->mac_table[i].state & 3901 IXGBE_MAC_STATE_IN_USE) 3902 hw->mac.ops.set_rar(hw, i, 3903 adapter->mac_table[i].addr, 3904 adapter->mac_table[i].queue, 3905 IXGBE_RAH_AV); 3906 else 3907 hw->mac.ops.clear_rar(hw, i); 3908 3909 adapter->mac_table[i].state &= 3910 ~(IXGBE_MAC_STATE_MODIFIED); 3911 } 3912 } 3913 } 3914 3915 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 3916 { 3917 int i; 3918 struct ixgbe_hw *hw = &adapter->hw; 3919 3920 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3921 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3922 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3923 eth_zero_addr(adapter->mac_table[i].addr); 3924 adapter->mac_table[i].queue = 0; 3925 } 3926 ixgbe_sync_mac_table(adapter); 3927 } 3928 3929 static int ixgbe_available_rars(struct ixgbe_adapter *adapter) 3930 { 3931 struct ixgbe_hw *hw = &adapter->hw; 3932 int i, count = 0; 3933 3934 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3935 if (adapter->mac_table[i].state == 0) 3936 count++; 3937 } 3938 return count; 3939 } 3940 3941 /* this function destroys the first RAR entry */ 3942 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter, 3943 u8 *addr) 3944 { 3945 struct ixgbe_hw *hw = &adapter->hw; 3946 3947 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN); 3948 adapter->mac_table[0].queue = VMDQ_P(0); 3949 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT | 3950 IXGBE_MAC_STATE_IN_USE); 3951 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr, 3952 adapter->mac_table[0].queue, 3953 IXGBE_RAH_AV); 3954 } 3955 3956 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3957 { 3958 struct ixgbe_hw *hw = &adapter->hw; 3959 int i; 3960 3961 if (is_zero_ether_addr(addr)) 3962 return -EINVAL; 3963 3964 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3965 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 3966 continue; 3967 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED | 3968 IXGBE_MAC_STATE_IN_USE); 3969 ether_addr_copy(adapter->mac_table[i].addr, addr); 3970 adapter->mac_table[i].queue = queue; 3971 ixgbe_sync_mac_table(adapter); 3972 return i; 3973 } 3974 return -ENOMEM; 3975 } 3976 3977 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 3978 { 3979 /* search table for addr, if found, set to 0 and sync */ 3980 int i; 3981 struct ixgbe_hw *hw = &adapter->hw; 3982 3983 if (is_zero_ether_addr(addr)) 3984 return -EINVAL; 3985 3986 for (i = 0; i < hw->mac.num_rar_entries; i++) { 3987 if (ether_addr_equal(addr, adapter->mac_table[i].addr) && 3988 adapter->mac_table[i].queue == queue) { 3989 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 3990 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 3991 eth_zero_addr(adapter->mac_table[i].addr); 3992 adapter->mac_table[i].queue = 0; 3993 ixgbe_sync_mac_table(adapter); 3994 return 0; 3995 } 3996 } 3997 return -ENOMEM; 3998 } 3999 /** 4000 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4001 * @netdev: network interface device structure 4002 * 4003 * Writes unicast address list to the RAR table. 4004 * Returns: -ENOMEM on failure/insufficient address space 4005 * 0 on no addresses written 4006 * X on writing X addresses to the RAR table 4007 **/ 4008 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4009 { 4010 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4011 int count = 0; 4012 4013 /* return ENOMEM indicating insufficient memory for addresses */ 4014 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter)) 4015 return -ENOMEM; 4016 4017 if (!netdev_uc_empty(netdev)) { 4018 struct netdev_hw_addr *ha; 4019 netdev_for_each_uc_addr(ha, netdev) { 4020 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4021 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4022 count++; 4023 } 4024 } 4025 return count; 4026 } 4027 4028 /** 4029 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4030 * @netdev: network interface device structure 4031 * 4032 * The set_rx_method entry point is called whenever the unicast/multicast 4033 * address list or the network interface flags are updated. This routine is 4034 * responsible for configuring the hardware for proper unicast, multicast and 4035 * promiscuous mode. 4036 **/ 4037 void ixgbe_set_rx_mode(struct net_device *netdev) 4038 { 4039 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4040 struct ixgbe_hw *hw = &adapter->hw; 4041 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4042 u32 vlnctrl; 4043 int count; 4044 4045 /* Check for Promiscuous and All Multicast modes */ 4046 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4047 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4048 4049 /* set all bits that we expect to always be set */ 4050 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4051 fctrl |= IXGBE_FCTRL_BAM; 4052 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4053 fctrl |= IXGBE_FCTRL_PMCF; 4054 4055 /* clear the bits we are changing the status of */ 4056 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4057 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4058 if (netdev->flags & IFF_PROMISC) { 4059 hw->addr_ctrl.user_set_promisc = true; 4060 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4061 vmolr |= IXGBE_VMOLR_MPE; 4062 /* Only disable hardware filter vlans in promiscuous mode 4063 * if SR-IOV and VMDQ are disabled - otherwise ensure 4064 * that hardware VLAN filters remain enabled. 4065 */ 4066 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED | 4067 IXGBE_FLAG_SRIOV_ENABLED)) 4068 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4069 } else { 4070 if (netdev->flags & IFF_ALLMULTI) { 4071 fctrl |= IXGBE_FCTRL_MPE; 4072 vmolr |= IXGBE_VMOLR_MPE; 4073 } 4074 vlnctrl |= IXGBE_VLNCTRL_VFE; 4075 hw->addr_ctrl.user_set_promisc = false; 4076 } 4077 4078 /* 4079 * Write addresses to available RAR registers, if there is not 4080 * sufficient space to store all the addresses then enable 4081 * unicast promiscuous mode 4082 */ 4083 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0)); 4084 if (count < 0) { 4085 fctrl |= IXGBE_FCTRL_UPE; 4086 vmolr |= IXGBE_VMOLR_ROPE; 4087 } 4088 4089 /* Write addresses to the MTA, if the attempt fails 4090 * then we should just turn on promiscuous mode so 4091 * that we can at least receive multicast traffic 4092 */ 4093 count = ixgbe_write_mc_addr_list(netdev); 4094 if (count < 0) { 4095 fctrl |= IXGBE_FCTRL_MPE; 4096 vmolr |= IXGBE_VMOLR_MPE; 4097 } else if (count) { 4098 vmolr |= IXGBE_VMOLR_ROMPE; 4099 } 4100 4101 if (hw->mac.type != ixgbe_mac_82598EB) { 4102 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4103 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4104 IXGBE_VMOLR_ROPE); 4105 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4106 } 4107 4108 /* This is useful for sniffing bad packets. */ 4109 if (adapter->netdev->features & NETIF_F_RXALL) { 4110 /* UPE and MPE will be handled by normal PROMISC logic 4111 * in e1000e_set_rx_mode */ 4112 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4113 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4114 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4115 4116 fctrl &= ~(IXGBE_FCTRL_DPF); 4117 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4118 } 4119 4120 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4121 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4122 4123 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 4124 ixgbe_vlan_strip_enable(adapter); 4125 else 4126 ixgbe_vlan_strip_disable(adapter); 4127 } 4128 4129 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4130 { 4131 int q_idx; 4132 4133 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4134 ixgbe_qv_init_lock(adapter->q_vector[q_idx]); 4135 napi_enable(&adapter->q_vector[q_idx]->napi); 4136 } 4137 } 4138 4139 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4140 { 4141 int q_idx; 4142 4143 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4144 napi_disable(&adapter->q_vector[q_idx]->napi); 4145 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { 4146 pr_info("QV %d locked\n", q_idx); 4147 usleep_range(1000, 20000); 4148 } 4149 } 4150 } 4151 4152 #ifdef CONFIG_IXGBE_DCB 4153 /** 4154 * ixgbe_configure_dcb - Configure DCB hardware 4155 * @adapter: ixgbe adapter struct 4156 * 4157 * This is called by the driver on open to configure the DCB hardware. 4158 * This is also called by the gennetlink interface when reconfiguring 4159 * the DCB state. 4160 */ 4161 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4162 { 4163 struct ixgbe_hw *hw = &adapter->hw; 4164 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4165 4166 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4167 if (hw->mac.type == ixgbe_mac_82598EB) 4168 netif_set_gso_max_size(adapter->netdev, 65536); 4169 return; 4170 } 4171 4172 if (hw->mac.type == ixgbe_mac_82598EB) 4173 netif_set_gso_max_size(adapter->netdev, 32768); 4174 4175 #ifdef IXGBE_FCOE 4176 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4177 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4178 #endif 4179 4180 /* reconfigure the hardware */ 4181 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4182 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4183 DCB_TX_CONFIG); 4184 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4185 DCB_RX_CONFIG); 4186 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4187 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4188 ixgbe_dcb_hw_ets(&adapter->hw, 4189 adapter->ixgbe_ieee_ets, 4190 max_frame); 4191 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4192 adapter->ixgbe_ieee_pfc->pfc_en, 4193 adapter->ixgbe_ieee_ets->prio_tc); 4194 } 4195 4196 /* Enable RSS Hash per TC */ 4197 if (hw->mac.type != ixgbe_mac_82598EB) { 4198 u32 msb = 0; 4199 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4200 4201 while (rss_i) { 4202 msb++; 4203 rss_i >>= 1; 4204 } 4205 4206 /* write msb to all 8 TCs in one write */ 4207 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4208 } 4209 } 4210 #endif 4211 4212 /* Additional bittime to account for IXGBE framing */ 4213 #define IXGBE_ETH_FRAMING 20 4214 4215 /** 4216 * ixgbe_hpbthresh - calculate high water mark for flow control 4217 * 4218 * @adapter: board private structure to calculate for 4219 * @pb: packet buffer to calculate 4220 */ 4221 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4222 { 4223 struct ixgbe_hw *hw = &adapter->hw; 4224 struct net_device *dev = adapter->netdev; 4225 int link, tc, kb, marker; 4226 u32 dv_id, rx_pba; 4227 4228 /* Calculate max LAN frame size */ 4229 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4230 4231 #ifdef IXGBE_FCOE 4232 /* FCoE traffic class uses FCOE jumbo frames */ 4233 if ((dev->features & NETIF_F_FCOE_MTU) && 4234 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4235 (pb == ixgbe_fcoe_get_tc(adapter))) 4236 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4237 #endif 4238 4239 /* Calculate delay value for device */ 4240 switch (hw->mac.type) { 4241 case ixgbe_mac_X540: 4242 case ixgbe_mac_X550: 4243 case ixgbe_mac_X550EM_x: 4244 dv_id = IXGBE_DV_X540(link, tc); 4245 break; 4246 default: 4247 dv_id = IXGBE_DV(link, tc); 4248 break; 4249 } 4250 4251 /* Loopback switch introduces additional latency */ 4252 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4253 dv_id += IXGBE_B2BT(tc); 4254 4255 /* Delay value is calculated in bit times convert to KB */ 4256 kb = IXGBE_BT2KB(dv_id); 4257 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4258 4259 marker = rx_pba - kb; 4260 4261 /* It is possible that the packet buffer is not large enough 4262 * to provide required headroom. In this case throw an error 4263 * to user and a do the best we can. 4264 */ 4265 if (marker < 0) { 4266 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4267 "headroom to support flow control." 4268 "Decrease MTU or number of traffic classes\n", pb); 4269 marker = tc + 1; 4270 } 4271 4272 return marker; 4273 } 4274 4275 /** 4276 * ixgbe_lpbthresh - calculate low water mark for for flow control 4277 * 4278 * @adapter: board private structure to calculate for 4279 * @pb: packet buffer to calculate 4280 */ 4281 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 4282 { 4283 struct ixgbe_hw *hw = &adapter->hw; 4284 struct net_device *dev = adapter->netdev; 4285 int tc; 4286 u32 dv_id; 4287 4288 /* Calculate max LAN frame size */ 4289 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 4290 4291 #ifdef IXGBE_FCOE 4292 /* FCoE traffic class uses FCOE jumbo frames */ 4293 if ((dev->features & NETIF_F_FCOE_MTU) && 4294 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4295 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 4296 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4297 #endif 4298 4299 /* Calculate delay value for device */ 4300 switch (hw->mac.type) { 4301 case ixgbe_mac_X540: 4302 case ixgbe_mac_X550: 4303 case ixgbe_mac_X550EM_x: 4304 dv_id = IXGBE_LOW_DV_X540(tc); 4305 break; 4306 default: 4307 dv_id = IXGBE_LOW_DV(tc); 4308 break; 4309 } 4310 4311 /* Delay value is calculated in bit times convert to KB */ 4312 return IXGBE_BT2KB(dv_id); 4313 } 4314 4315 /* 4316 * ixgbe_pbthresh_setup - calculate and setup high low water marks 4317 */ 4318 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 4319 { 4320 struct ixgbe_hw *hw = &adapter->hw; 4321 int num_tc = netdev_get_num_tc(adapter->netdev); 4322 int i; 4323 4324 if (!num_tc) 4325 num_tc = 1; 4326 4327 for (i = 0; i < num_tc; i++) { 4328 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 4329 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 4330 4331 /* Low water marks must not be larger than high water marks */ 4332 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 4333 hw->fc.low_water[i] = 0; 4334 } 4335 4336 for (; i < MAX_TRAFFIC_CLASS; i++) 4337 hw->fc.high_water[i] = 0; 4338 } 4339 4340 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 4341 { 4342 struct ixgbe_hw *hw = &adapter->hw; 4343 int hdrm; 4344 u8 tc = netdev_get_num_tc(adapter->netdev); 4345 4346 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4347 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 4348 hdrm = 32 << adapter->fdir_pballoc; 4349 else 4350 hdrm = 0; 4351 4352 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 4353 ixgbe_pbthresh_setup(adapter); 4354 } 4355 4356 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 4357 { 4358 struct ixgbe_hw *hw = &adapter->hw; 4359 struct hlist_node *node2; 4360 struct ixgbe_fdir_filter *filter; 4361 4362 spin_lock(&adapter->fdir_perfect_lock); 4363 4364 if (!hlist_empty(&adapter->fdir_filter_list)) 4365 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 4366 4367 hlist_for_each_entry_safe(filter, node2, 4368 &adapter->fdir_filter_list, fdir_node) { 4369 ixgbe_fdir_write_perfect_filter_82599(hw, 4370 &filter->filter, 4371 filter->sw_idx, 4372 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 4373 IXGBE_FDIR_DROP_QUEUE : 4374 adapter->rx_ring[filter->action]->reg_idx); 4375 } 4376 4377 spin_unlock(&adapter->fdir_perfect_lock); 4378 } 4379 4380 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 4381 struct ixgbe_adapter *adapter) 4382 { 4383 struct ixgbe_hw *hw = &adapter->hw; 4384 u32 vmolr; 4385 4386 /* No unicast promiscuous support for VMDQ devices. */ 4387 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 4388 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 4389 4390 /* clear the affected bit */ 4391 vmolr &= ~IXGBE_VMOLR_MPE; 4392 4393 if (dev->flags & IFF_ALLMULTI) { 4394 vmolr |= IXGBE_VMOLR_MPE; 4395 } else { 4396 vmolr |= IXGBE_VMOLR_ROMPE; 4397 hw->mac.ops.update_mc_addr_list(hw, dev); 4398 } 4399 ixgbe_write_uc_addr_list(adapter->netdev, pool); 4400 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 4401 } 4402 4403 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 4404 { 4405 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4406 int rss_i = adapter->num_rx_queues_per_pool; 4407 struct ixgbe_hw *hw = &adapter->hw; 4408 u16 pool = vadapter->pool; 4409 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4410 IXGBE_PSRTYPE_UDPHDR | 4411 IXGBE_PSRTYPE_IPV4HDR | 4412 IXGBE_PSRTYPE_L2HDR | 4413 IXGBE_PSRTYPE_IPV6HDR; 4414 4415 if (hw->mac.type == ixgbe_mac_82598EB) 4416 return; 4417 4418 if (rss_i > 3) 4419 psrtype |= 2 << 29; 4420 else if (rss_i > 1) 4421 psrtype |= 1 << 29; 4422 4423 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4424 } 4425 4426 /** 4427 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4428 * @rx_ring: ring to free buffers from 4429 **/ 4430 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4431 { 4432 struct device *dev = rx_ring->dev; 4433 unsigned long size; 4434 u16 i; 4435 4436 /* ring already cleared, nothing to do */ 4437 if (!rx_ring->rx_buffer_info) 4438 return; 4439 4440 /* Free all the Rx ring sk_buffs */ 4441 for (i = 0; i < rx_ring->count; i++) { 4442 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 4443 4444 if (rx_buffer->skb) { 4445 struct sk_buff *skb = rx_buffer->skb; 4446 if (IXGBE_CB(skb)->page_released) 4447 dma_unmap_page(dev, 4448 IXGBE_CB(skb)->dma, 4449 ixgbe_rx_bufsz(rx_ring), 4450 DMA_FROM_DEVICE); 4451 dev_kfree_skb(skb); 4452 rx_buffer->skb = NULL; 4453 } 4454 4455 if (!rx_buffer->page) 4456 continue; 4457 4458 dma_unmap_page(dev, rx_buffer->dma, 4459 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 4460 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); 4461 4462 rx_buffer->page = NULL; 4463 } 4464 4465 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4466 memset(rx_ring->rx_buffer_info, 0, size); 4467 4468 /* Zero out the descriptor ring */ 4469 memset(rx_ring->desc, 0, rx_ring->size); 4470 4471 rx_ring->next_to_alloc = 0; 4472 rx_ring->next_to_clean = 0; 4473 rx_ring->next_to_use = 0; 4474 } 4475 4476 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 4477 struct ixgbe_ring *rx_ring) 4478 { 4479 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4480 int index = rx_ring->queue_index + vadapter->rx_base_queue; 4481 4482 /* shutdown specific queue receive and wait for dma to settle */ 4483 ixgbe_disable_rx_queue(adapter, rx_ring); 4484 usleep_range(10000, 20000); 4485 ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); 4486 ixgbe_clean_rx_ring(rx_ring); 4487 rx_ring->l2_accel_priv = NULL; 4488 } 4489 4490 static int ixgbe_fwd_ring_down(struct net_device *vdev, 4491 struct ixgbe_fwd_adapter *accel) 4492 { 4493 struct ixgbe_adapter *adapter = accel->real_adapter; 4494 unsigned int rxbase = accel->rx_base_queue; 4495 unsigned int txbase = accel->tx_base_queue; 4496 int i; 4497 4498 netif_tx_stop_all_queues(vdev); 4499 4500 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4501 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4502 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 4503 } 4504 4505 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4506 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 4507 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 4508 } 4509 4510 4511 return 0; 4512 } 4513 4514 static int ixgbe_fwd_ring_up(struct net_device *vdev, 4515 struct ixgbe_fwd_adapter *accel) 4516 { 4517 struct ixgbe_adapter *adapter = accel->real_adapter; 4518 unsigned int rxbase, txbase, queues; 4519 int i, baseq, err = 0; 4520 4521 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 4522 return 0; 4523 4524 baseq = accel->pool * adapter->num_rx_queues_per_pool; 4525 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 4526 accel->pool, adapter->num_rx_pools, 4527 baseq, baseq + adapter->num_rx_queues_per_pool, 4528 adapter->fwd_bitmask); 4529 4530 accel->netdev = vdev; 4531 accel->rx_base_queue = rxbase = baseq; 4532 accel->tx_base_queue = txbase = baseq; 4533 4534 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 4535 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4536 4537 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4538 adapter->rx_ring[rxbase + i]->netdev = vdev; 4539 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 4540 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 4541 } 4542 4543 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4544 adapter->tx_ring[txbase + i]->netdev = vdev; 4545 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 4546 } 4547 4548 queues = min_t(unsigned int, 4549 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 4550 err = netif_set_real_num_tx_queues(vdev, queues); 4551 if (err) 4552 goto fwd_queue_err; 4553 4554 err = netif_set_real_num_rx_queues(vdev, queues); 4555 if (err) 4556 goto fwd_queue_err; 4557 4558 if (is_valid_ether_addr(vdev->dev_addr)) 4559 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 4560 4561 ixgbe_fwd_psrtype(accel); 4562 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 4563 return err; 4564 fwd_queue_err: 4565 ixgbe_fwd_ring_down(vdev, accel); 4566 return err; 4567 } 4568 4569 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 4570 { 4571 struct net_device *upper; 4572 struct list_head *iter; 4573 int err; 4574 4575 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 4576 if (netif_is_macvlan(upper)) { 4577 struct macvlan_dev *dfwd = netdev_priv(upper); 4578 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 4579 4580 if (dfwd->fwd_priv) { 4581 err = ixgbe_fwd_ring_up(upper, vadapter); 4582 if (err) 4583 continue; 4584 } 4585 } 4586 } 4587 } 4588 4589 static void ixgbe_configure(struct ixgbe_adapter *adapter) 4590 { 4591 struct ixgbe_hw *hw = &adapter->hw; 4592 4593 ixgbe_configure_pb(adapter); 4594 #ifdef CONFIG_IXGBE_DCB 4595 ixgbe_configure_dcb(adapter); 4596 #endif 4597 /* 4598 * We must restore virtualization before VLANs or else 4599 * the VLVF registers will not be populated 4600 */ 4601 ixgbe_configure_virtualization(adapter); 4602 4603 ixgbe_set_rx_mode(adapter->netdev); 4604 ixgbe_restore_vlan(adapter); 4605 4606 switch (hw->mac.type) { 4607 case ixgbe_mac_82599EB: 4608 case ixgbe_mac_X540: 4609 hw->mac.ops.disable_rx_buff(hw); 4610 break; 4611 default: 4612 break; 4613 } 4614 4615 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 4616 ixgbe_init_fdir_signature_82599(&adapter->hw, 4617 adapter->fdir_pballoc); 4618 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 4619 ixgbe_init_fdir_perfect_82599(&adapter->hw, 4620 adapter->fdir_pballoc); 4621 ixgbe_fdir_filter_restore(adapter); 4622 } 4623 4624 switch (hw->mac.type) { 4625 case ixgbe_mac_82599EB: 4626 case ixgbe_mac_X540: 4627 hw->mac.ops.enable_rx_buff(hw); 4628 break; 4629 default: 4630 break; 4631 } 4632 4633 #ifdef IXGBE_FCOE 4634 /* configure FCoE L2 filters, redirection table, and Rx control */ 4635 ixgbe_configure_fcoe(adapter); 4636 4637 #endif /* IXGBE_FCOE */ 4638 ixgbe_configure_tx(adapter); 4639 ixgbe_configure_rx(adapter); 4640 ixgbe_configure_dfwd(adapter); 4641 } 4642 4643 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 4644 { 4645 switch (hw->phy.type) { 4646 case ixgbe_phy_sfp_avago: 4647 case ixgbe_phy_sfp_ftl: 4648 case ixgbe_phy_sfp_intel: 4649 case ixgbe_phy_sfp_unknown: 4650 case ixgbe_phy_sfp_passive_tyco: 4651 case ixgbe_phy_sfp_passive_unknown: 4652 case ixgbe_phy_sfp_active_unknown: 4653 case ixgbe_phy_sfp_ftl_active: 4654 case ixgbe_phy_qsfp_passive_unknown: 4655 case ixgbe_phy_qsfp_active_unknown: 4656 case ixgbe_phy_qsfp_intel: 4657 case ixgbe_phy_qsfp_unknown: 4658 /* ixgbe_phy_none is set when no SFP module is present */ 4659 case ixgbe_phy_none: 4660 return true; 4661 case ixgbe_phy_nl: 4662 if (hw->mac.type == ixgbe_mac_82598EB) 4663 return true; 4664 default: 4665 return false; 4666 } 4667 } 4668 4669 /** 4670 * ixgbe_sfp_link_config - set up SFP+ link 4671 * @adapter: pointer to private adapter struct 4672 **/ 4673 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 4674 { 4675 /* 4676 * We are assuming the worst case scenario here, and that 4677 * is that an SFP was inserted/removed after the reset 4678 * but before SFP detection was enabled. As such the best 4679 * solution is to just start searching as soon as we start 4680 */ 4681 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4682 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 4683 4684 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 4685 } 4686 4687 /** 4688 * ixgbe_non_sfp_link_config - set up non-SFP+ link 4689 * @hw: pointer to private hardware struct 4690 * 4691 * Returns 0 on success, negative on failure 4692 **/ 4693 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 4694 { 4695 u32 speed; 4696 bool autoneg, link_up = false; 4697 u32 ret = IXGBE_ERR_LINK_SETUP; 4698 4699 if (hw->mac.ops.check_link) 4700 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 4701 4702 if (ret) 4703 return ret; 4704 4705 speed = hw->phy.autoneg_advertised; 4706 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 4707 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 4708 &autoneg); 4709 if (ret) 4710 return ret; 4711 4712 if (hw->mac.ops.setup_link) 4713 ret = hw->mac.ops.setup_link(hw, speed, link_up); 4714 4715 return ret; 4716 } 4717 4718 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 4719 { 4720 struct ixgbe_hw *hw = &adapter->hw; 4721 u32 gpie = 0; 4722 4723 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 4724 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 4725 IXGBE_GPIE_OCD; 4726 gpie |= IXGBE_GPIE_EIAME; 4727 /* 4728 * use EIAM to auto-mask when MSI-X interrupt is asserted 4729 * this saves a register write for every interrupt 4730 */ 4731 switch (hw->mac.type) { 4732 case ixgbe_mac_82598EB: 4733 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4734 break; 4735 case ixgbe_mac_82599EB: 4736 case ixgbe_mac_X540: 4737 case ixgbe_mac_X550: 4738 case ixgbe_mac_X550EM_x: 4739 default: 4740 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4741 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4742 break; 4743 } 4744 } else { 4745 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 4746 * specifically only auto mask tx and rx interrupts */ 4747 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4748 } 4749 4750 /* XXX: to interrupt immediately for EICS writes, enable this */ 4751 /* gpie |= IXGBE_GPIE_EIMEN; */ 4752 4753 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4754 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 4755 4756 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4757 case IXGBE_82599_VMDQ_8Q_MASK: 4758 gpie |= IXGBE_GPIE_VTMODE_16; 4759 break; 4760 case IXGBE_82599_VMDQ_4Q_MASK: 4761 gpie |= IXGBE_GPIE_VTMODE_32; 4762 break; 4763 default: 4764 gpie |= IXGBE_GPIE_VTMODE_64; 4765 break; 4766 } 4767 } 4768 4769 /* Enable Thermal over heat sensor interrupt */ 4770 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 4771 switch (adapter->hw.mac.type) { 4772 case ixgbe_mac_82599EB: 4773 gpie |= IXGBE_SDP0_GPIEN; 4774 break; 4775 case ixgbe_mac_X540: 4776 gpie |= IXGBE_EIMS_TS; 4777 break; 4778 default: 4779 break; 4780 } 4781 } 4782 4783 /* Enable fan failure interrupt */ 4784 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 4785 gpie |= IXGBE_SDP1_GPIEN; 4786 4787 if (hw->mac.type == ixgbe_mac_82599EB) { 4788 gpie |= IXGBE_SDP1_GPIEN; 4789 gpie |= IXGBE_SDP2_GPIEN; 4790 } 4791 4792 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4793 } 4794 4795 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 4796 { 4797 struct ixgbe_hw *hw = &adapter->hw; 4798 int err; 4799 u32 ctrl_ext; 4800 4801 ixgbe_get_hw_control(adapter); 4802 ixgbe_setup_gpie(adapter); 4803 4804 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 4805 ixgbe_configure_msix(adapter); 4806 else 4807 ixgbe_configure_msi_and_legacy(adapter); 4808 4809 /* enable the optics for 82599 SFP+ fiber */ 4810 if (hw->mac.ops.enable_tx_laser) 4811 hw->mac.ops.enable_tx_laser(hw); 4812 4813 smp_mb__before_atomic(); 4814 clear_bit(__IXGBE_DOWN, &adapter->state); 4815 ixgbe_napi_enable_all(adapter); 4816 4817 if (ixgbe_is_sfp(hw)) { 4818 ixgbe_sfp_link_config(adapter); 4819 } else { 4820 err = ixgbe_non_sfp_link_config(hw); 4821 if (err) 4822 e_err(probe, "link_config FAILED %d\n", err); 4823 } 4824 4825 /* clear any pending interrupts, may auto mask */ 4826 IXGBE_READ_REG(hw, IXGBE_EICR); 4827 ixgbe_irq_enable(adapter, true, true); 4828 4829 /* 4830 * If this adapter has a fan, check to see if we had a failure 4831 * before we enabled the interrupt. 4832 */ 4833 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 4834 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4835 if (esdp & IXGBE_ESDP_SDP1) 4836 e_crit(drv, "Fan has stopped, replace the adapter\n"); 4837 } 4838 4839 /* bring the link up in the watchdog, this could race with our first 4840 * link up interrupt but shouldn't be a problem */ 4841 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4842 adapter->link_check_timeout = jiffies; 4843 mod_timer(&adapter->service_timer, jiffies); 4844 4845 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 4846 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4847 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4848 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4849 } 4850 4851 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 4852 { 4853 WARN_ON(in_interrupt()); 4854 /* put off any impending NetWatchDogTimeout */ 4855 adapter->netdev->trans_start = jiffies; 4856 4857 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 4858 usleep_range(1000, 2000); 4859 ixgbe_down(adapter); 4860 /* 4861 * If SR-IOV enabled then wait a bit before bringing the adapter 4862 * back up to give the VFs time to respond to the reset. The 4863 * two second wait is based upon the watchdog timer cycle in 4864 * the VF driver. 4865 */ 4866 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4867 msleep(2000); 4868 ixgbe_up(adapter); 4869 clear_bit(__IXGBE_RESETTING, &adapter->state); 4870 } 4871 4872 void ixgbe_up(struct ixgbe_adapter *adapter) 4873 { 4874 /* hardware has been reset, we need to reload some things */ 4875 ixgbe_configure(adapter); 4876 4877 ixgbe_up_complete(adapter); 4878 } 4879 4880 void ixgbe_reset(struct ixgbe_adapter *adapter) 4881 { 4882 struct ixgbe_hw *hw = &adapter->hw; 4883 struct net_device *netdev = adapter->netdev; 4884 int err; 4885 u8 old_addr[ETH_ALEN]; 4886 4887 if (ixgbe_removed(hw->hw_addr)) 4888 return; 4889 /* lock SFP init bit to prevent race conditions with the watchdog */ 4890 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 4891 usleep_range(1000, 2000); 4892 4893 /* clear all SFP and link config related flags while holding SFP_INIT */ 4894 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 4895 IXGBE_FLAG2_SFP_NEEDS_RESET); 4896 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 4897 4898 err = hw->mac.ops.init_hw(hw); 4899 switch (err) { 4900 case 0: 4901 case IXGBE_ERR_SFP_NOT_PRESENT: 4902 case IXGBE_ERR_SFP_NOT_SUPPORTED: 4903 break; 4904 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 4905 e_dev_err("master disable timed out\n"); 4906 break; 4907 case IXGBE_ERR_EEPROM_VERSION: 4908 /* We are running on a pre-production device, log a warning */ 4909 e_dev_warn("This device is a pre-production adapter/LOM. " 4910 "Please be aware there may be issues associated with " 4911 "your hardware. If you are experiencing problems " 4912 "please contact your Intel or hardware " 4913 "representative who provided you with this " 4914 "hardware.\n"); 4915 break; 4916 default: 4917 e_dev_err("Hardware Error: %d\n", err); 4918 } 4919 4920 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 4921 /* do not flush user set addresses */ 4922 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len); 4923 ixgbe_flush_sw_mac_table(adapter); 4924 ixgbe_mac_set_default_filter(adapter, old_addr); 4925 4926 /* update SAN MAC vmdq pool selection */ 4927 if (hw->mac.san_mac_rar_index) 4928 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 4929 4930 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 4931 ixgbe_ptp_reset(adapter); 4932 } 4933 4934 /** 4935 * ixgbe_clean_tx_ring - Free Tx Buffers 4936 * @tx_ring: ring to be cleaned 4937 **/ 4938 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 4939 { 4940 struct ixgbe_tx_buffer *tx_buffer_info; 4941 unsigned long size; 4942 u16 i; 4943 4944 /* ring already cleared, nothing to do */ 4945 if (!tx_ring->tx_buffer_info) 4946 return; 4947 4948 /* Free all the Tx ring sk_buffs */ 4949 for (i = 0; i < tx_ring->count; i++) { 4950 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 4951 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 4952 } 4953 4954 netdev_tx_reset_queue(txring_txq(tx_ring)); 4955 4956 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 4957 memset(tx_ring->tx_buffer_info, 0, size); 4958 4959 /* Zero out the descriptor ring */ 4960 memset(tx_ring->desc, 0, tx_ring->size); 4961 4962 tx_ring->next_to_use = 0; 4963 tx_ring->next_to_clean = 0; 4964 } 4965 4966 /** 4967 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 4968 * @adapter: board private structure 4969 **/ 4970 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 4971 { 4972 int i; 4973 4974 for (i = 0; i < adapter->num_rx_queues; i++) 4975 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 4976 } 4977 4978 /** 4979 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 4980 * @adapter: board private structure 4981 **/ 4982 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 4983 { 4984 int i; 4985 4986 for (i = 0; i < adapter->num_tx_queues; i++) 4987 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 4988 } 4989 4990 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 4991 { 4992 struct hlist_node *node2; 4993 struct ixgbe_fdir_filter *filter; 4994 4995 spin_lock(&adapter->fdir_perfect_lock); 4996 4997 hlist_for_each_entry_safe(filter, node2, 4998 &adapter->fdir_filter_list, fdir_node) { 4999 hlist_del(&filter->fdir_node); 5000 kfree(filter); 5001 } 5002 adapter->fdir_filter_count = 0; 5003 5004 spin_unlock(&adapter->fdir_perfect_lock); 5005 } 5006 5007 void ixgbe_down(struct ixgbe_adapter *adapter) 5008 { 5009 struct net_device *netdev = adapter->netdev; 5010 struct ixgbe_hw *hw = &adapter->hw; 5011 struct net_device *upper; 5012 struct list_head *iter; 5013 int i; 5014 5015 /* signal that we are down to the interrupt handler */ 5016 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5017 return; /* do nothing if already down */ 5018 5019 /* disable receives */ 5020 hw->mac.ops.disable_rx(hw); 5021 5022 /* disable all enabled rx queues */ 5023 for (i = 0; i < adapter->num_rx_queues; i++) 5024 /* this call also flushes the previous write */ 5025 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5026 5027 usleep_range(10000, 20000); 5028 5029 netif_tx_stop_all_queues(netdev); 5030 5031 /* call carrier off first to avoid false dev_watchdog timeouts */ 5032 netif_carrier_off(netdev); 5033 netif_tx_disable(netdev); 5034 5035 /* disable any upper devices */ 5036 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5037 if (netif_is_macvlan(upper)) { 5038 struct macvlan_dev *vlan = netdev_priv(upper); 5039 5040 if (vlan->fwd_priv) { 5041 netif_tx_stop_all_queues(upper); 5042 netif_carrier_off(upper); 5043 netif_tx_disable(upper); 5044 } 5045 } 5046 } 5047 5048 ixgbe_irq_disable(adapter); 5049 5050 ixgbe_napi_disable_all(adapter); 5051 5052 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | 5053 IXGBE_FLAG2_RESET_REQUESTED); 5054 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5055 5056 del_timer_sync(&adapter->service_timer); 5057 5058 if (adapter->num_vfs) { 5059 /* Clear EITR Select mapping */ 5060 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5061 5062 /* Mark all the VFs as inactive */ 5063 for (i = 0 ; i < adapter->num_vfs; i++) 5064 adapter->vfinfo[i].clear_to_send = false; 5065 5066 /* ping all the active vfs to let them know we are going down */ 5067 ixgbe_ping_all_vfs(adapter); 5068 5069 /* Disable all VFTE/VFRE TX/RX */ 5070 ixgbe_disable_tx_rx(adapter); 5071 } 5072 5073 /* disable transmits in the hardware now that interrupts are off */ 5074 for (i = 0; i < adapter->num_tx_queues; i++) { 5075 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5076 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5077 } 5078 5079 /* Disable the Tx DMA engine on 82599 and later MAC */ 5080 switch (hw->mac.type) { 5081 case ixgbe_mac_82599EB: 5082 case ixgbe_mac_X540: 5083 case ixgbe_mac_X550: 5084 case ixgbe_mac_X550EM_x: 5085 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5086 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5087 ~IXGBE_DMATXCTL_TE)); 5088 break; 5089 default: 5090 break; 5091 } 5092 5093 if (!pci_channel_offline(adapter->pdev)) 5094 ixgbe_reset(adapter); 5095 5096 /* power down the optics for 82599 SFP+ fiber */ 5097 if (hw->mac.ops.disable_tx_laser) 5098 hw->mac.ops.disable_tx_laser(hw); 5099 5100 ixgbe_clean_all_tx_rings(adapter); 5101 ixgbe_clean_all_rx_rings(adapter); 5102 5103 #ifdef CONFIG_IXGBE_DCA 5104 /* since we reset the hardware DCA settings were cleared */ 5105 ixgbe_setup_dca(adapter); 5106 #endif 5107 } 5108 5109 /** 5110 * ixgbe_tx_timeout - Respond to a Tx Hang 5111 * @netdev: network interface device structure 5112 **/ 5113 static void ixgbe_tx_timeout(struct net_device *netdev) 5114 { 5115 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5116 5117 /* Do the reset outside of interrupt context */ 5118 ixgbe_tx_timeout_reset(adapter); 5119 } 5120 5121 /** 5122 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5123 * @adapter: board private structure to initialize 5124 * 5125 * ixgbe_sw_init initializes the Adapter private data structure. 5126 * Fields are initialized based on PCI device information and 5127 * OS network device settings (MTU size). 5128 **/ 5129 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 5130 { 5131 struct ixgbe_hw *hw = &adapter->hw; 5132 struct pci_dev *pdev = adapter->pdev; 5133 unsigned int rss, fdir; 5134 u32 fwsm; 5135 #ifdef CONFIG_IXGBE_DCB 5136 int j; 5137 struct tc_configuration *tc; 5138 #endif 5139 5140 /* PCI config space info */ 5141 5142 hw->vendor_id = pdev->vendor; 5143 hw->device_id = pdev->device; 5144 hw->revision_id = pdev->revision; 5145 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5146 hw->subsystem_device_id = pdev->subsystem_device; 5147 5148 /* Set common capability flags and settings */ 5149 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 5150 adapter->ring_feature[RING_F_RSS].limit = rss; 5151 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 5152 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 5153 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 5154 adapter->atr_sample_rate = 20; 5155 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 5156 adapter->ring_feature[RING_F_FDIR].limit = fdir; 5157 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 5158 #ifdef CONFIG_IXGBE_DCA 5159 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 5160 #endif 5161 #ifdef IXGBE_FCOE 5162 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5163 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5164 #ifdef CONFIG_IXGBE_DCB 5165 /* Default traffic class to use for FCoE */ 5166 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 5167 #endif /* CONFIG_IXGBE_DCB */ 5168 #endif /* IXGBE_FCOE */ 5169 5170 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 5171 hw->mac.num_rar_entries, 5172 GFP_ATOMIC); 5173 5174 /* Set MAC specific capability flags and exceptions */ 5175 switch (hw->mac.type) { 5176 case ixgbe_mac_82598EB: 5177 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 5178 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 5179 5180 if (hw->device_id == IXGBE_DEV_ID_82598AT) 5181 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 5182 5183 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 5184 adapter->ring_feature[RING_F_FDIR].limit = 0; 5185 adapter->atr_sample_rate = 0; 5186 adapter->fdir_pballoc = 0; 5187 #ifdef IXGBE_FCOE 5188 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5189 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5190 #ifdef CONFIG_IXGBE_DCB 5191 adapter->fcoe.up = 0; 5192 #endif /* IXGBE_DCB */ 5193 #endif /* IXGBE_FCOE */ 5194 break; 5195 case ixgbe_mac_82599EB: 5196 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 5197 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5198 break; 5199 case ixgbe_mac_X540: 5200 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM); 5201 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5202 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5203 break; 5204 case ixgbe_mac_X550EM_x: 5205 case ixgbe_mac_X550: 5206 #ifdef CONFIG_IXGBE_DCA 5207 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 5208 #endif 5209 break; 5210 default: 5211 break; 5212 } 5213 5214 #ifdef IXGBE_FCOE 5215 /* FCoE support exists, always init the FCoE lock */ 5216 spin_lock_init(&adapter->fcoe.lock); 5217 5218 #endif 5219 /* n-tuple support exists, always init our spinlock */ 5220 spin_lock_init(&adapter->fdir_perfect_lock); 5221 5222 #ifdef CONFIG_IXGBE_DCB 5223 switch (hw->mac.type) { 5224 case ixgbe_mac_X540: 5225 case ixgbe_mac_X550: 5226 case ixgbe_mac_X550EM_x: 5227 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5228 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5229 break; 5230 default: 5231 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5232 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5233 break; 5234 } 5235 5236 /* Configure DCB traffic classes */ 5237 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5238 tc = &adapter->dcb_cfg.tc_config[j]; 5239 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5240 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5241 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5242 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5243 tc->dcb_pfc = pfc_disabled; 5244 } 5245 5246 /* Initialize default user to priority mapping, UPx->TC0 */ 5247 tc = &adapter->dcb_cfg.tc_config[0]; 5248 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5249 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5250 5251 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5252 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5253 adapter->dcb_cfg.pfc_mode_enable = false; 5254 adapter->dcb_set_bitmap = 0x00; 5255 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5256 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5257 sizeof(adapter->temp_dcb_cfg)); 5258 5259 #endif 5260 5261 /* default flow control settings */ 5262 hw->fc.requested_mode = ixgbe_fc_full; 5263 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 5264 ixgbe_pbthresh_setup(adapter); 5265 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 5266 hw->fc.send_xon = true; 5267 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 5268 5269 #ifdef CONFIG_PCI_IOV 5270 if (max_vfs > 0) 5271 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 5272 5273 /* assign number of SR-IOV VFs */ 5274 if (hw->mac.type != ixgbe_mac_82598EB) { 5275 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 5276 adapter->num_vfs = 0; 5277 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 5278 } else { 5279 adapter->num_vfs = max_vfs; 5280 } 5281 } 5282 #endif /* CONFIG_PCI_IOV */ 5283 5284 /* enable itr by default in dynamic mode */ 5285 adapter->rx_itr_setting = 1; 5286 adapter->tx_itr_setting = 1; 5287 5288 /* set default ring sizes */ 5289 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5290 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5291 5292 /* set default work limits */ 5293 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5294 5295 /* initialize eeprom parameters */ 5296 if (ixgbe_init_eeprom_params_generic(hw)) { 5297 e_dev_err("EEPROM initialization failed\n"); 5298 return -EIO; 5299 } 5300 5301 /* PF holds first pool slot */ 5302 set_bit(0, &adapter->fwd_bitmask); 5303 set_bit(__IXGBE_DOWN, &adapter->state); 5304 5305 return 0; 5306 } 5307 5308 /** 5309 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 5310 * @tx_ring: tx descriptor ring (for a specific queue) to setup 5311 * 5312 * Return 0 on success, negative on failure 5313 **/ 5314 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 5315 { 5316 struct device *dev = tx_ring->dev; 5317 int orig_node = dev_to_node(dev); 5318 int ring_node = -1; 5319 int size; 5320 5321 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5322 5323 if (tx_ring->q_vector) 5324 ring_node = tx_ring->q_vector->numa_node; 5325 5326 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); 5327 if (!tx_ring->tx_buffer_info) 5328 tx_ring->tx_buffer_info = vzalloc(size); 5329 if (!tx_ring->tx_buffer_info) 5330 goto err; 5331 5332 u64_stats_init(&tx_ring->syncp); 5333 5334 /* round up to nearest 4K */ 5335 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 5336 tx_ring->size = ALIGN(tx_ring->size, 4096); 5337 5338 set_dev_node(dev, ring_node); 5339 tx_ring->desc = dma_alloc_coherent(dev, 5340 tx_ring->size, 5341 &tx_ring->dma, 5342 GFP_KERNEL); 5343 set_dev_node(dev, orig_node); 5344 if (!tx_ring->desc) 5345 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 5346 &tx_ring->dma, GFP_KERNEL); 5347 if (!tx_ring->desc) 5348 goto err; 5349 5350 tx_ring->next_to_use = 0; 5351 tx_ring->next_to_clean = 0; 5352 return 0; 5353 5354 err: 5355 vfree(tx_ring->tx_buffer_info); 5356 tx_ring->tx_buffer_info = NULL; 5357 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 5358 return -ENOMEM; 5359 } 5360 5361 /** 5362 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 5363 * @adapter: board private structure 5364 * 5365 * If this function returns with an error, then it's possible one or 5366 * more of the rings is populated (while the rest are not). It is the 5367 * callers duty to clean those orphaned rings. 5368 * 5369 * Return 0 on success, negative on failure 5370 **/ 5371 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 5372 { 5373 int i, err = 0; 5374 5375 for (i = 0; i < adapter->num_tx_queues; i++) { 5376 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 5377 if (!err) 5378 continue; 5379 5380 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 5381 goto err_setup_tx; 5382 } 5383 5384 return 0; 5385 err_setup_tx: 5386 /* rewind the index freeing the rings as we go */ 5387 while (i--) 5388 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5389 return err; 5390 } 5391 5392 /** 5393 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 5394 * @rx_ring: rx descriptor ring (for a specific queue) to setup 5395 * 5396 * Returns 0 on success, negative on failure 5397 **/ 5398 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 5399 { 5400 struct device *dev = rx_ring->dev; 5401 int orig_node = dev_to_node(dev); 5402 int ring_node = -1; 5403 int size; 5404 5405 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 5406 5407 if (rx_ring->q_vector) 5408 ring_node = rx_ring->q_vector->numa_node; 5409 5410 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); 5411 if (!rx_ring->rx_buffer_info) 5412 rx_ring->rx_buffer_info = vzalloc(size); 5413 if (!rx_ring->rx_buffer_info) 5414 goto err; 5415 5416 u64_stats_init(&rx_ring->syncp); 5417 5418 /* Round up to nearest 4K */ 5419 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 5420 rx_ring->size = ALIGN(rx_ring->size, 4096); 5421 5422 set_dev_node(dev, ring_node); 5423 rx_ring->desc = dma_alloc_coherent(dev, 5424 rx_ring->size, 5425 &rx_ring->dma, 5426 GFP_KERNEL); 5427 set_dev_node(dev, orig_node); 5428 if (!rx_ring->desc) 5429 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 5430 &rx_ring->dma, GFP_KERNEL); 5431 if (!rx_ring->desc) 5432 goto err; 5433 5434 rx_ring->next_to_clean = 0; 5435 rx_ring->next_to_use = 0; 5436 5437 return 0; 5438 err: 5439 vfree(rx_ring->rx_buffer_info); 5440 rx_ring->rx_buffer_info = NULL; 5441 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 5442 return -ENOMEM; 5443 } 5444 5445 /** 5446 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 5447 * @adapter: board private structure 5448 * 5449 * If this function returns with an error, then it's possible one or 5450 * more of the rings is populated (while the rest are not). It is the 5451 * callers duty to clean those orphaned rings. 5452 * 5453 * Return 0 on success, negative on failure 5454 **/ 5455 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 5456 { 5457 int i, err = 0; 5458 5459 for (i = 0; i < adapter->num_rx_queues; i++) { 5460 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 5461 if (!err) 5462 continue; 5463 5464 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 5465 goto err_setup_rx; 5466 } 5467 5468 #ifdef IXGBE_FCOE 5469 err = ixgbe_setup_fcoe_ddp_resources(adapter); 5470 if (!err) 5471 #endif 5472 return 0; 5473 err_setup_rx: 5474 /* rewind the index freeing the rings as we go */ 5475 while (i--) 5476 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5477 return err; 5478 } 5479 5480 /** 5481 * ixgbe_free_tx_resources - Free Tx Resources per Queue 5482 * @tx_ring: Tx descriptor ring for a specific queue 5483 * 5484 * Free all transmit software resources 5485 **/ 5486 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 5487 { 5488 ixgbe_clean_tx_ring(tx_ring); 5489 5490 vfree(tx_ring->tx_buffer_info); 5491 tx_ring->tx_buffer_info = NULL; 5492 5493 /* if not set, then don't free */ 5494 if (!tx_ring->desc) 5495 return; 5496 5497 dma_free_coherent(tx_ring->dev, tx_ring->size, 5498 tx_ring->desc, tx_ring->dma); 5499 5500 tx_ring->desc = NULL; 5501 } 5502 5503 /** 5504 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 5505 * @adapter: board private structure 5506 * 5507 * Free all transmit software resources 5508 **/ 5509 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 5510 { 5511 int i; 5512 5513 for (i = 0; i < adapter->num_tx_queues; i++) 5514 if (adapter->tx_ring[i]->desc) 5515 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5516 } 5517 5518 /** 5519 * ixgbe_free_rx_resources - Free Rx Resources 5520 * @rx_ring: ring to clean the resources from 5521 * 5522 * Free all receive software resources 5523 **/ 5524 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 5525 { 5526 ixgbe_clean_rx_ring(rx_ring); 5527 5528 vfree(rx_ring->rx_buffer_info); 5529 rx_ring->rx_buffer_info = NULL; 5530 5531 /* if not set, then don't free */ 5532 if (!rx_ring->desc) 5533 return; 5534 5535 dma_free_coherent(rx_ring->dev, rx_ring->size, 5536 rx_ring->desc, rx_ring->dma); 5537 5538 rx_ring->desc = NULL; 5539 } 5540 5541 /** 5542 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 5543 * @adapter: board private structure 5544 * 5545 * Free all receive software resources 5546 **/ 5547 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 5548 { 5549 int i; 5550 5551 #ifdef IXGBE_FCOE 5552 ixgbe_free_fcoe_ddp_resources(adapter); 5553 5554 #endif 5555 for (i = 0; i < adapter->num_rx_queues; i++) 5556 if (adapter->rx_ring[i]->desc) 5557 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5558 } 5559 5560 /** 5561 * ixgbe_change_mtu - Change the Maximum Transfer Unit 5562 * @netdev: network interface device structure 5563 * @new_mtu: new value for maximum frame size 5564 * 5565 * Returns 0 on success, negative on failure 5566 **/ 5567 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 5568 { 5569 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5570 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 5571 5572 /* MTU < 68 is an error and causes problems on some kernels */ 5573 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 5574 return -EINVAL; 5575 5576 /* 5577 * For 82599EB we cannot allow legacy VFs to enable their receive 5578 * paths when MTU greater than 1500 is configured. So display a 5579 * warning that legacy VFs will be disabled. 5580 */ 5581 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 5582 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 5583 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 5584 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 5585 5586 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5587 5588 /* must set new MTU before calling down or up */ 5589 netdev->mtu = new_mtu; 5590 5591 if (netif_running(netdev)) 5592 ixgbe_reinit_locked(adapter); 5593 5594 return 0; 5595 } 5596 5597 /** 5598 * ixgbe_open - Called when a network interface is made active 5599 * @netdev: network interface device structure 5600 * 5601 * Returns 0 on success, negative value on failure 5602 * 5603 * The open entry point is called when a network interface is made 5604 * active by the system (IFF_UP). At this point all resources needed 5605 * for transmit and receive operations are allocated, the interrupt 5606 * handler is registered with the OS, the watchdog timer is started, 5607 * and the stack is notified that the interface is ready. 5608 **/ 5609 static int ixgbe_open(struct net_device *netdev) 5610 { 5611 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5612 int err, queues; 5613 5614 /* disallow open during test */ 5615 if (test_bit(__IXGBE_TESTING, &adapter->state)) 5616 return -EBUSY; 5617 5618 netif_carrier_off(netdev); 5619 5620 /* allocate transmit descriptors */ 5621 err = ixgbe_setup_all_tx_resources(adapter); 5622 if (err) 5623 goto err_setup_tx; 5624 5625 /* allocate receive descriptors */ 5626 err = ixgbe_setup_all_rx_resources(adapter); 5627 if (err) 5628 goto err_setup_rx; 5629 5630 ixgbe_configure(adapter); 5631 5632 err = ixgbe_request_irq(adapter); 5633 if (err) 5634 goto err_req_irq; 5635 5636 /* Notify the stack of the actual queue counts. */ 5637 if (adapter->num_rx_pools > 1) 5638 queues = adapter->num_rx_queues_per_pool; 5639 else 5640 queues = adapter->num_tx_queues; 5641 5642 err = netif_set_real_num_tx_queues(netdev, queues); 5643 if (err) 5644 goto err_set_queues; 5645 5646 if (adapter->num_rx_pools > 1 && 5647 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 5648 queues = IXGBE_MAX_L2A_QUEUES; 5649 else 5650 queues = adapter->num_rx_queues; 5651 err = netif_set_real_num_rx_queues(netdev, queues); 5652 if (err) 5653 goto err_set_queues; 5654 5655 ixgbe_ptp_init(adapter); 5656 5657 ixgbe_up_complete(adapter); 5658 5659 #if IS_ENABLED(CONFIG_IXGBE_VXLAN) 5660 vxlan_get_rx_port(netdev); 5661 5662 #endif 5663 return 0; 5664 5665 err_set_queues: 5666 ixgbe_free_irq(adapter); 5667 err_req_irq: 5668 ixgbe_free_all_rx_resources(adapter); 5669 err_setup_rx: 5670 ixgbe_free_all_tx_resources(adapter); 5671 err_setup_tx: 5672 ixgbe_reset(adapter); 5673 5674 return err; 5675 } 5676 5677 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 5678 { 5679 ixgbe_ptp_suspend(adapter); 5680 5681 ixgbe_down(adapter); 5682 ixgbe_free_irq(adapter); 5683 5684 ixgbe_free_all_tx_resources(adapter); 5685 ixgbe_free_all_rx_resources(adapter); 5686 } 5687 5688 /** 5689 * ixgbe_close - Disables a network interface 5690 * @netdev: network interface device structure 5691 * 5692 * Returns 0, this is not allowed to fail 5693 * 5694 * The close entry point is called when an interface is de-activated 5695 * by the OS. The hardware is still under the drivers control, but 5696 * needs to be disabled. A global MAC reset is issued to stop the 5697 * hardware, and all transmit and receive resources are freed. 5698 **/ 5699 static int ixgbe_close(struct net_device *netdev) 5700 { 5701 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5702 5703 ixgbe_ptp_stop(adapter); 5704 5705 ixgbe_close_suspend(adapter); 5706 5707 ixgbe_fdir_filter_exit(adapter); 5708 5709 ixgbe_release_hw_control(adapter); 5710 5711 return 0; 5712 } 5713 5714 #ifdef CONFIG_PM 5715 static int ixgbe_resume(struct pci_dev *pdev) 5716 { 5717 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5718 struct net_device *netdev = adapter->netdev; 5719 u32 err; 5720 5721 adapter->hw.hw_addr = adapter->io_addr; 5722 pci_set_power_state(pdev, PCI_D0); 5723 pci_restore_state(pdev); 5724 /* 5725 * pci_restore_state clears dev->state_saved so call 5726 * pci_save_state to restore it. 5727 */ 5728 pci_save_state(pdev); 5729 5730 err = pci_enable_device_mem(pdev); 5731 if (err) { 5732 e_dev_err("Cannot enable PCI device from suspend\n"); 5733 return err; 5734 } 5735 smp_mb__before_atomic(); 5736 clear_bit(__IXGBE_DISABLED, &adapter->state); 5737 pci_set_master(pdev); 5738 5739 pci_wake_from_d3(pdev, false); 5740 5741 ixgbe_reset(adapter); 5742 5743 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 5744 5745 rtnl_lock(); 5746 err = ixgbe_init_interrupt_scheme(adapter); 5747 if (!err && netif_running(netdev)) 5748 err = ixgbe_open(netdev); 5749 5750 rtnl_unlock(); 5751 5752 if (err) 5753 return err; 5754 5755 netif_device_attach(netdev); 5756 5757 return 0; 5758 } 5759 #endif /* CONFIG_PM */ 5760 5761 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 5762 { 5763 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5764 struct net_device *netdev = adapter->netdev; 5765 struct ixgbe_hw *hw = &adapter->hw; 5766 u32 ctrl, fctrl; 5767 u32 wufc = adapter->wol; 5768 #ifdef CONFIG_PM 5769 int retval = 0; 5770 #endif 5771 5772 netif_device_detach(netdev); 5773 5774 rtnl_lock(); 5775 if (netif_running(netdev)) 5776 ixgbe_close_suspend(adapter); 5777 rtnl_unlock(); 5778 5779 ixgbe_clear_interrupt_scheme(adapter); 5780 5781 #ifdef CONFIG_PM 5782 retval = pci_save_state(pdev); 5783 if (retval) 5784 return retval; 5785 5786 #endif 5787 if (hw->mac.ops.stop_link_on_d3) 5788 hw->mac.ops.stop_link_on_d3(hw); 5789 5790 if (wufc) { 5791 ixgbe_set_rx_mode(netdev); 5792 5793 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 5794 if (hw->mac.ops.enable_tx_laser) 5795 hw->mac.ops.enable_tx_laser(hw); 5796 5797 /* turn on all-multi mode if wake on multicast is enabled */ 5798 if (wufc & IXGBE_WUFC_MC) { 5799 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5800 fctrl |= IXGBE_FCTRL_MPE; 5801 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5802 } 5803 5804 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 5805 ctrl |= IXGBE_CTRL_GIO_DIS; 5806 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 5807 5808 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 5809 } else { 5810 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 5811 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 5812 } 5813 5814 switch (hw->mac.type) { 5815 case ixgbe_mac_82598EB: 5816 pci_wake_from_d3(pdev, false); 5817 break; 5818 case ixgbe_mac_82599EB: 5819 case ixgbe_mac_X540: 5820 case ixgbe_mac_X550: 5821 case ixgbe_mac_X550EM_x: 5822 pci_wake_from_d3(pdev, !!wufc); 5823 break; 5824 default: 5825 break; 5826 } 5827 5828 *enable_wake = !!wufc; 5829 5830 ixgbe_release_hw_control(adapter); 5831 5832 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 5833 pci_disable_device(pdev); 5834 5835 return 0; 5836 } 5837 5838 #ifdef CONFIG_PM 5839 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 5840 { 5841 int retval; 5842 bool wake; 5843 5844 retval = __ixgbe_shutdown(pdev, &wake); 5845 if (retval) 5846 return retval; 5847 5848 if (wake) { 5849 pci_prepare_to_sleep(pdev); 5850 } else { 5851 pci_wake_from_d3(pdev, false); 5852 pci_set_power_state(pdev, PCI_D3hot); 5853 } 5854 5855 return 0; 5856 } 5857 #endif /* CONFIG_PM */ 5858 5859 static void ixgbe_shutdown(struct pci_dev *pdev) 5860 { 5861 bool wake; 5862 5863 __ixgbe_shutdown(pdev, &wake); 5864 5865 if (system_state == SYSTEM_POWER_OFF) { 5866 pci_wake_from_d3(pdev, wake); 5867 pci_set_power_state(pdev, PCI_D3hot); 5868 } 5869 } 5870 5871 /** 5872 * ixgbe_update_stats - Update the board statistics counters. 5873 * @adapter: board private structure 5874 **/ 5875 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 5876 { 5877 struct net_device *netdev = adapter->netdev; 5878 struct ixgbe_hw *hw = &adapter->hw; 5879 struct ixgbe_hw_stats *hwstats = &adapter->stats; 5880 u64 total_mpc = 0; 5881 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 5882 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 5883 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 5884 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 5885 5886 if (test_bit(__IXGBE_DOWN, &adapter->state) || 5887 test_bit(__IXGBE_RESETTING, &adapter->state)) 5888 return; 5889 5890 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 5891 u64 rsc_count = 0; 5892 u64 rsc_flush = 0; 5893 for (i = 0; i < adapter->num_rx_queues; i++) { 5894 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 5895 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 5896 } 5897 adapter->rsc_total_count = rsc_count; 5898 adapter->rsc_total_flush = rsc_flush; 5899 } 5900 5901 for (i = 0; i < adapter->num_rx_queues; i++) { 5902 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 5903 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 5904 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 5905 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 5906 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 5907 bytes += rx_ring->stats.bytes; 5908 packets += rx_ring->stats.packets; 5909 } 5910 adapter->non_eop_descs = non_eop_descs; 5911 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 5912 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 5913 adapter->hw_csum_rx_error = hw_csum_rx_error; 5914 netdev->stats.rx_bytes = bytes; 5915 netdev->stats.rx_packets = packets; 5916 5917 bytes = 0; 5918 packets = 0; 5919 /* gather some stats to the adapter struct that are per queue */ 5920 for (i = 0; i < adapter->num_tx_queues; i++) { 5921 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 5922 restart_queue += tx_ring->tx_stats.restart_queue; 5923 tx_busy += tx_ring->tx_stats.tx_busy; 5924 bytes += tx_ring->stats.bytes; 5925 packets += tx_ring->stats.packets; 5926 } 5927 adapter->restart_queue = restart_queue; 5928 adapter->tx_busy = tx_busy; 5929 netdev->stats.tx_bytes = bytes; 5930 netdev->stats.tx_packets = packets; 5931 5932 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 5933 5934 /* 8 register reads */ 5935 for (i = 0; i < 8; i++) { 5936 /* for packet buffers not used, the register should read 0 */ 5937 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 5938 missed_rx += mpc; 5939 hwstats->mpc[i] += mpc; 5940 total_mpc += hwstats->mpc[i]; 5941 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 5942 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 5943 switch (hw->mac.type) { 5944 case ixgbe_mac_82598EB: 5945 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 5946 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 5947 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 5948 hwstats->pxonrxc[i] += 5949 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 5950 break; 5951 case ixgbe_mac_82599EB: 5952 case ixgbe_mac_X540: 5953 case ixgbe_mac_X550: 5954 case ixgbe_mac_X550EM_x: 5955 hwstats->pxonrxc[i] += 5956 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 5957 break; 5958 default: 5959 break; 5960 } 5961 } 5962 5963 /*16 register reads */ 5964 for (i = 0; i < 16; i++) { 5965 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 5966 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 5967 if ((hw->mac.type == ixgbe_mac_82599EB) || 5968 (hw->mac.type == ixgbe_mac_X540) || 5969 (hw->mac.type == ixgbe_mac_X550) || 5970 (hw->mac.type == ixgbe_mac_X550EM_x)) { 5971 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 5972 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 5973 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 5974 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 5975 } 5976 } 5977 5978 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 5979 /* work around hardware counting issue */ 5980 hwstats->gprc -= missed_rx; 5981 5982 ixgbe_update_xoff_received(adapter); 5983 5984 /* 82598 hardware only has a 32 bit counter in the high register */ 5985 switch (hw->mac.type) { 5986 case ixgbe_mac_82598EB: 5987 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 5988 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 5989 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 5990 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 5991 break; 5992 case ixgbe_mac_X540: 5993 case ixgbe_mac_X550: 5994 case ixgbe_mac_X550EM_x: 5995 /* OS2BMC stats are X540 and later */ 5996 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 5997 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 5998 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 5999 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6000 case ixgbe_mac_82599EB: 6001 for (i = 0; i < 16; i++) 6002 adapter->hw_rx_no_dma_resources += 6003 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6004 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6005 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6006 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6007 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6008 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6009 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6010 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6011 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6012 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6013 #ifdef IXGBE_FCOE 6014 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6015 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6016 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6017 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6018 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6019 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6020 /* Add up per cpu counters for total ddp aloc fail */ 6021 if (adapter->fcoe.ddp_pool) { 6022 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6023 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6024 unsigned int cpu; 6025 u64 noddp = 0, noddp_ext_buff = 0; 6026 for_each_possible_cpu(cpu) { 6027 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6028 noddp += ddp_pool->noddp; 6029 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6030 } 6031 hwstats->fcoe_noddp = noddp; 6032 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6033 } 6034 #endif /* IXGBE_FCOE */ 6035 break; 6036 default: 6037 break; 6038 } 6039 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6040 hwstats->bprc += bprc; 6041 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6042 if (hw->mac.type == ixgbe_mac_82598EB) 6043 hwstats->mprc -= bprc; 6044 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6045 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6046 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6047 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6048 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6049 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6050 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6051 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6052 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6053 hwstats->lxontxc += lxon; 6054 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6055 hwstats->lxofftxc += lxoff; 6056 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6057 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6058 /* 6059 * 82598 errata - tx of flow control packets is included in tx counters 6060 */ 6061 xon_off_tot = lxon + lxoff; 6062 hwstats->gptc -= xon_off_tot; 6063 hwstats->mptc -= xon_off_tot; 6064 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6065 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6066 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6067 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6068 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6069 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6070 hwstats->ptc64 -= xon_off_tot; 6071 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6072 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6073 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6074 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6075 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6076 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6077 6078 /* Fill out the OS statistics structure */ 6079 netdev->stats.multicast = hwstats->mprc; 6080 6081 /* Rx Errors */ 6082 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6083 netdev->stats.rx_dropped = 0; 6084 netdev->stats.rx_length_errors = hwstats->rlec; 6085 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6086 netdev->stats.rx_missed_errors = total_mpc; 6087 } 6088 6089 /** 6090 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6091 * @adapter: pointer to the device adapter structure 6092 **/ 6093 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6094 { 6095 struct ixgbe_hw *hw = &adapter->hw; 6096 int i; 6097 6098 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6099 return; 6100 6101 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6102 6103 /* if interface is down do nothing */ 6104 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6105 return; 6106 6107 /* do nothing if we are not using signature filters */ 6108 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6109 return; 6110 6111 adapter->fdir_overflow++; 6112 6113 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 6114 for (i = 0; i < adapter->num_tx_queues; i++) 6115 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 6116 &(adapter->tx_ring[i]->state)); 6117 /* re-enable flow director interrupts */ 6118 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 6119 } else { 6120 e_err(probe, "failed to finish FDIR re-initialization, " 6121 "ignored adding FDIR ATR filters\n"); 6122 } 6123 } 6124 6125 /** 6126 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 6127 * @adapter: pointer to the device adapter structure 6128 * 6129 * This function serves two purposes. First it strobes the interrupt lines 6130 * in order to make certain interrupts are occurring. Secondly it sets the 6131 * bits needed to check for TX hangs. As a result we should immediately 6132 * determine if a hang has occurred. 6133 */ 6134 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 6135 { 6136 struct ixgbe_hw *hw = &adapter->hw; 6137 u64 eics = 0; 6138 int i; 6139 6140 /* If we're down, removing or resetting, just bail */ 6141 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6142 test_bit(__IXGBE_REMOVING, &adapter->state) || 6143 test_bit(__IXGBE_RESETTING, &adapter->state)) 6144 return; 6145 6146 /* Force detection of hung controller */ 6147 if (netif_carrier_ok(adapter->netdev)) { 6148 for (i = 0; i < adapter->num_tx_queues; i++) 6149 set_check_for_tx_hang(adapter->tx_ring[i]); 6150 } 6151 6152 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 6153 /* 6154 * for legacy and MSI interrupts don't set any bits 6155 * that are enabled for EIAM, because this operation 6156 * would set *both* EIMS and EICS for any bit in EIAM 6157 */ 6158 IXGBE_WRITE_REG(hw, IXGBE_EICS, 6159 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 6160 } else { 6161 /* get one bit for every active tx/rx interrupt vector */ 6162 for (i = 0; i < adapter->num_q_vectors; i++) { 6163 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6164 if (qv->rx.ring || qv->tx.ring) 6165 eics |= ((u64)1 << i); 6166 } 6167 } 6168 6169 /* Cause software interrupt to ensure rings are cleaned */ 6170 ixgbe_irq_rearm_queues(adapter, eics); 6171 } 6172 6173 /** 6174 * ixgbe_watchdog_update_link - update the link status 6175 * @adapter: pointer to the device adapter structure 6176 * @link_speed: pointer to a u32 to store the link_speed 6177 **/ 6178 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 6179 { 6180 struct ixgbe_hw *hw = &adapter->hw; 6181 u32 link_speed = adapter->link_speed; 6182 bool link_up = adapter->link_up; 6183 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 6184 6185 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 6186 return; 6187 6188 if (hw->mac.ops.check_link) { 6189 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 6190 } else { 6191 /* always assume link is up, if no check link function */ 6192 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 6193 link_up = true; 6194 } 6195 6196 if (adapter->ixgbe_ieee_pfc) 6197 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6198 6199 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 6200 hw->mac.ops.fc_enable(hw); 6201 ixgbe_set_rx_drop_en(adapter); 6202 } 6203 6204 if (link_up || 6205 time_after(jiffies, (adapter->link_check_timeout + 6206 IXGBE_TRY_LINK_TIMEOUT))) { 6207 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6208 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 6209 IXGBE_WRITE_FLUSH(hw); 6210 } 6211 6212 adapter->link_up = link_up; 6213 adapter->link_speed = link_speed; 6214 } 6215 6216 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 6217 { 6218 #ifdef CONFIG_IXGBE_DCB 6219 struct net_device *netdev = adapter->netdev; 6220 struct dcb_app app = { 6221 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 6222 .protocol = 0, 6223 }; 6224 u8 up = 0; 6225 6226 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 6227 up = dcb_ieee_getapp_mask(netdev, &app); 6228 6229 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 6230 #endif 6231 } 6232 6233 /** 6234 * ixgbe_watchdog_link_is_up - update netif_carrier status and 6235 * print link up message 6236 * @adapter: pointer to the device adapter structure 6237 **/ 6238 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 6239 { 6240 struct net_device *netdev = adapter->netdev; 6241 struct ixgbe_hw *hw = &adapter->hw; 6242 struct net_device *upper; 6243 struct list_head *iter; 6244 u32 link_speed = adapter->link_speed; 6245 bool flow_rx, flow_tx; 6246 6247 /* only continue if link was previously down */ 6248 if (netif_carrier_ok(netdev)) 6249 return; 6250 6251 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 6252 6253 switch (hw->mac.type) { 6254 case ixgbe_mac_82598EB: { 6255 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6256 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 6257 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 6258 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 6259 } 6260 break; 6261 case ixgbe_mac_X540: 6262 case ixgbe_mac_X550: 6263 case ixgbe_mac_X550EM_x: 6264 case ixgbe_mac_82599EB: { 6265 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 6266 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 6267 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 6268 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 6269 } 6270 break; 6271 default: 6272 flow_tx = false; 6273 flow_rx = false; 6274 break; 6275 } 6276 6277 adapter->last_rx_ptp_check = jiffies; 6278 6279 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6280 ixgbe_ptp_start_cyclecounter(adapter); 6281 6282 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", 6283 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? 6284 "10 Gbps" : 6285 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? 6286 "1 Gbps" : 6287 (link_speed == IXGBE_LINK_SPEED_100_FULL ? 6288 "100 Mbps" : 6289 "unknown speed"))), 6290 ((flow_rx && flow_tx) ? "RX/TX" : 6291 (flow_rx ? "RX" : 6292 (flow_tx ? "TX" : "None")))); 6293 6294 netif_carrier_on(netdev); 6295 ixgbe_check_vf_rate_limit(adapter); 6296 6297 /* enable transmits */ 6298 netif_tx_wake_all_queues(adapter->netdev); 6299 6300 /* enable any upper devices */ 6301 rtnl_lock(); 6302 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 6303 if (netif_is_macvlan(upper)) { 6304 struct macvlan_dev *vlan = netdev_priv(upper); 6305 6306 if (vlan->fwd_priv) 6307 netif_tx_wake_all_queues(upper); 6308 } 6309 } 6310 rtnl_unlock(); 6311 6312 /* update the default user priority for VFs */ 6313 ixgbe_update_default_up(adapter); 6314 6315 /* ping all the active vfs to let them know link has changed */ 6316 ixgbe_ping_all_vfs(adapter); 6317 } 6318 6319 /** 6320 * ixgbe_watchdog_link_is_down - update netif_carrier status and 6321 * print link down message 6322 * @adapter: pointer to the adapter structure 6323 **/ 6324 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 6325 { 6326 struct net_device *netdev = adapter->netdev; 6327 struct ixgbe_hw *hw = &adapter->hw; 6328 6329 adapter->link_up = false; 6330 adapter->link_speed = 0; 6331 6332 /* only continue if link was up previously */ 6333 if (!netif_carrier_ok(netdev)) 6334 return; 6335 6336 /* poll for SFP+ cable when link is down */ 6337 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 6338 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 6339 6340 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6341 ixgbe_ptp_start_cyclecounter(adapter); 6342 6343 e_info(drv, "NIC Link is Down\n"); 6344 netif_carrier_off(netdev); 6345 6346 /* ping all the active vfs to let them know link has changed */ 6347 ixgbe_ping_all_vfs(adapter); 6348 } 6349 6350 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 6351 { 6352 int i; 6353 6354 for (i = 0; i < adapter->num_tx_queues; i++) { 6355 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6356 6357 if (tx_ring->next_to_use != tx_ring->next_to_clean) 6358 return true; 6359 } 6360 6361 return false; 6362 } 6363 6364 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 6365 { 6366 struct ixgbe_hw *hw = &adapter->hw; 6367 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 6368 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 6369 6370 int i, j; 6371 6372 if (!adapter->num_vfs) 6373 return false; 6374 6375 /* resetting the PF is only needed for MAC before X550 */ 6376 if (hw->mac.type >= ixgbe_mac_X550) 6377 return false; 6378 6379 for (i = 0; i < adapter->num_vfs; i++) { 6380 for (j = 0; j < q_per_pool; j++) { 6381 u32 h, t; 6382 6383 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 6384 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 6385 6386 if (h != t) 6387 return true; 6388 } 6389 } 6390 6391 return false; 6392 } 6393 6394 /** 6395 * ixgbe_watchdog_flush_tx - flush queues on link down 6396 * @adapter: pointer to the device adapter structure 6397 **/ 6398 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 6399 { 6400 if (!netif_carrier_ok(adapter->netdev)) { 6401 if (ixgbe_ring_tx_pending(adapter) || 6402 ixgbe_vf_tx_pending(adapter)) { 6403 /* We've lost link, so the controller stops DMA, 6404 * but we've got queued Tx work that's never going 6405 * to get done, so reset controller to flush Tx. 6406 * (Do the reset outside of interrupt context). 6407 */ 6408 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 6409 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 6410 } 6411 } 6412 } 6413 6414 #ifdef CONFIG_PCI_IOV 6415 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 6416 struct pci_dev *vfdev) 6417 { 6418 if (!pci_wait_for_pending_transaction(vfdev)) 6419 e_dev_warn("Issuing VFLR with pending transactions\n"); 6420 6421 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 6422 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 6423 6424 msleep(100); 6425 } 6426 6427 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 6428 { 6429 struct ixgbe_hw *hw = &adapter->hw; 6430 struct pci_dev *pdev = adapter->pdev; 6431 struct pci_dev *vfdev; 6432 u32 gpc; 6433 int pos; 6434 unsigned short vf_id; 6435 6436 if (!(netif_carrier_ok(adapter->netdev))) 6437 return; 6438 6439 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 6440 if (gpc) /* If incrementing then no need for the check below */ 6441 return; 6442 /* Check to see if a bad DMA write target from an errant or 6443 * malicious VF has caused a PCIe error. If so then we can 6444 * issue a VFLR to the offending VF(s) and then resume without 6445 * requesting a full slot reset. 6446 */ 6447 6448 if (!pdev) 6449 return; 6450 6451 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 6452 if (!pos) 6453 return; 6454 6455 /* get the device ID for the VF */ 6456 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id); 6457 6458 /* check status reg for all VFs owned by this PF */ 6459 vfdev = pci_get_device(pdev->vendor, vf_id, NULL); 6460 while (vfdev) { 6461 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) { 6462 u16 status_reg; 6463 6464 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 6465 if (status_reg & PCI_STATUS_REC_MASTER_ABORT) 6466 /* issue VFLR */ 6467 ixgbe_issue_vf_flr(adapter, vfdev); 6468 } 6469 6470 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev); 6471 } 6472 } 6473 6474 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 6475 { 6476 u32 ssvpc; 6477 6478 /* Do not perform spoof check for 82598 or if not in IOV mode */ 6479 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 6480 adapter->num_vfs == 0) 6481 return; 6482 6483 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 6484 6485 /* 6486 * ssvpc register is cleared on read, if zero then no 6487 * spoofed packets in the last interval. 6488 */ 6489 if (!ssvpc) 6490 return; 6491 6492 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 6493 } 6494 #else 6495 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 6496 { 6497 } 6498 6499 static void 6500 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 6501 { 6502 } 6503 #endif /* CONFIG_PCI_IOV */ 6504 6505 6506 /** 6507 * ixgbe_watchdog_subtask - check and bring link up 6508 * @adapter: pointer to the device adapter structure 6509 **/ 6510 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 6511 { 6512 /* if interface is down, removing or resetting, do nothing */ 6513 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6514 test_bit(__IXGBE_REMOVING, &adapter->state) || 6515 test_bit(__IXGBE_RESETTING, &adapter->state)) 6516 return; 6517 6518 ixgbe_watchdog_update_link(adapter); 6519 6520 if (adapter->link_up) 6521 ixgbe_watchdog_link_is_up(adapter); 6522 else 6523 ixgbe_watchdog_link_is_down(adapter); 6524 6525 ixgbe_check_for_bad_vf(adapter); 6526 ixgbe_spoof_check(adapter); 6527 ixgbe_update_stats(adapter); 6528 6529 ixgbe_watchdog_flush_tx(adapter); 6530 } 6531 6532 /** 6533 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 6534 * @adapter: the ixgbe adapter structure 6535 **/ 6536 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 6537 { 6538 struct ixgbe_hw *hw = &adapter->hw; 6539 s32 err; 6540 6541 /* not searching for SFP so there is nothing to do here */ 6542 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 6543 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6544 return; 6545 6546 /* someone else is in init, wait until next service event */ 6547 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6548 return; 6549 6550 err = hw->phy.ops.identify_sfp(hw); 6551 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6552 goto sfp_out; 6553 6554 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 6555 /* If no cable is present, then we need to reset 6556 * the next time we find a good cable. */ 6557 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 6558 } 6559 6560 /* exit on error */ 6561 if (err) 6562 goto sfp_out; 6563 6564 /* exit if reset not needed */ 6565 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6566 goto sfp_out; 6567 6568 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 6569 6570 /* 6571 * A module may be identified correctly, but the EEPROM may not have 6572 * support for that module. setup_sfp() will fail in that case, so 6573 * we should not allow that module to load. 6574 */ 6575 if (hw->mac.type == ixgbe_mac_82598EB) 6576 err = hw->phy.ops.reset(hw); 6577 else 6578 err = hw->mac.ops.setup_sfp(hw); 6579 6580 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6581 goto sfp_out; 6582 6583 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 6584 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 6585 6586 sfp_out: 6587 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6588 6589 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 6590 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 6591 e_dev_err("failed to initialize because an unsupported " 6592 "SFP+ module type was detected.\n"); 6593 e_dev_err("Reload the driver after installing a " 6594 "supported module.\n"); 6595 unregister_netdev(adapter->netdev); 6596 } 6597 } 6598 6599 /** 6600 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 6601 * @adapter: the ixgbe adapter structure 6602 **/ 6603 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 6604 { 6605 struct ixgbe_hw *hw = &adapter->hw; 6606 u32 speed; 6607 bool autoneg = false; 6608 6609 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 6610 return; 6611 6612 /* someone else is in init, wait until next service event */ 6613 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6614 return; 6615 6616 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6617 6618 speed = hw->phy.autoneg_advertised; 6619 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 6620 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 6621 6622 /* setup the highest link when no autoneg */ 6623 if (!autoneg) { 6624 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 6625 speed = IXGBE_LINK_SPEED_10GB_FULL; 6626 } 6627 } 6628 6629 if (hw->mac.ops.setup_link) 6630 hw->mac.ops.setup_link(hw, speed, true); 6631 6632 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6633 adapter->link_check_timeout = jiffies; 6634 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6635 } 6636 6637 /** 6638 * ixgbe_service_timer - Timer Call-back 6639 * @data: pointer to adapter cast into an unsigned long 6640 **/ 6641 static void ixgbe_service_timer(unsigned long data) 6642 { 6643 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 6644 unsigned long next_event_offset; 6645 6646 /* poll faster when waiting for link */ 6647 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 6648 next_event_offset = HZ / 10; 6649 else 6650 next_event_offset = HZ * 2; 6651 6652 /* Reset the timer */ 6653 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 6654 6655 ixgbe_service_event_schedule(adapter); 6656 } 6657 6658 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 6659 { 6660 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) 6661 return; 6662 6663 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; 6664 6665 /* If we're already down, removing or resetting, just bail */ 6666 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6667 test_bit(__IXGBE_REMOVING, &adapter->state) || 6668 test_bit(__IXGBE_RESETTING, &adapter->state)) 6669 return; 6670 6671 ixgbe_dump(adapter); 6672 netdev_err(adapter->netdev, "Reset adapter\n"); 6673 adapter->tx_timeout_count++; 6674 6675 rtnl_lock(); 6676 ixgbe_reinit_locked(adapter); 6677 rtnl_unlock(); 6678 } 6679 6680 /** 6681 * ixgbe_service_task - manages and runs subtasks 6682 * @work: pointer to work_struct containing our data 6683 **/ 6684 static void ixgbe_service_task(struct work_struct *work) 6685 { 6686 struct ixgbe_adapter *adapter = container_of(work, 6687 struct ixgbe_adapter, 6688 service_task); 6689 if (ixgbe_removed(adapter->hw.hw_addr)) { 6690 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 6691 rtnl_lock(); 6692 ixgbe_down(adapter); 6693 rtnl_unlock(); 6694 } 6695 ixgbe_service_event_complete(adapter); 6696 return; 6697 } 6698 ixgbe_reset_subtask(adapter); 6699 ixgbe_sfp_detection_subtask(adapter); 6700 ixgbe_sfp_link_config_subtask(adapter); 6701 ixgbe_check_overtemp_subtask(adapter); 6702 ixgbe_watchdog_subtask(adapter); 6703 ixgbe_fdir_reinit_subtask(adapter); 6704 ixgbe_check_hang_subtask(adapter); 6705 6706 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 6707 ixgbe_ptp_overflow_check(adapter); 6708 ixgbe_ptp_rx_hang(adapter); 6709 } 6710 6711 ixgbe_service_event_complete(adapter); 6712 } 6713 6714 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 6715 struct ixgbe_tx_buffer *first, 6716 u8 *hdr_len) 6717 { 6718 struct sk_buff *skb = first->skb; 6719 u32 vlan_macip_lens, type_tucmd; 6720 u32 mss_l4len_idx, l4len; 6721 int err; 6722 6723 if (skb->ip_summed != CHECKSUM_PARTIAL) 6724 return 0; 6725 6726 if (!skb_is_gso(skb)) 6727 return 0; 6728 6729 err = skb_cow_head(skb, 0); 6730 if (err < 0) 6731 return err; 6732 6733 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6734 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 6735 6736 if (first->protocol == htons(ETH_P_IP)) { 6737 struct iphdr *iph = ip_hdr(skb); 6738 iph->tot_len = 0; 6739 iph->check = 0; 6740 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 6741 iph->daddr, 0, 6742 IPPROTO_TCP, 6743 0); 6744 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6745 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6746 IXGBE_TX_FLAGS_CSUM | 6747 IXGBE_TX_FLAGS_IPV4; 6748 } else if (skb_is_gso_v6(skb)) { 6749 ipv6_hdr(skb)->payload_len = 0; 6750 tcp_hdr(skb)->check = 6751 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 6752 &ipv6_hdr(skb)->daddr, 6753 0, IPPROTO_TCP, 0); 6754 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6755 IXGBE_TX_FLAGS_CSUM; 6756 } 6757 6758 /* compute header lengths */ 6759 l4len = tcp_hdrlen(skb); 6760 *hdr_len = skb_transport_offset(skb) + l4len; 6761 6762 /* update gso size and bytecount with header size */ 6763 first->gso_segs = skb_shinfo(skb)->gso_segs; 6764 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6765 6766 /* mss_l4len_id: use 0 as index for TSO */ 6767 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 6768 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 6769 6770 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 6771 vlan_macip_lens = skb_network_header_len(skb); 6772 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6773 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6774 6775 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 6776 mss_l4len_idx); 6777 6778 return 1; 6779 } 6780 6781 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 6782 struct ixgbe_tx_buffer *first) 6783 { 6784 struct sk_buff *skb = first->skb; 6785 u32 vlan_macip_lens = 0; 6786 u32 mss_l4len_idx = 0; 6787 u32 type_tucmd = 0; 6788 6789 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6790 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && 6791 !(first->tx_flags & IXGBE_TX_FLAGS_CC)) 6792 return; 6793 } else { 6794 u8 l4_hdr = 0; 6795 switch (first->protocol) { 6796 case htons(ETH_P_IP): 6797 vlan_macip_lens |= skb_network_header_len(skb); 6798 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6799 l4_hdr = ip_hdr(skb)->protocol; 6800 break; 6801 case htons(ETH_P_IPV6): 6802 vlan_macip_lens |= skb_network_header_len(skb); 6803 l4_hdr = ipv6_hdr(skb)->nexthdr; 6804 break; 6805 default: 6806 if (unlikely(net_ratelimit())) { 6807 dev_warn(tx_ring->dev, 6808 "partial checksum but proto=%x!\n", 6809 first->protocol); 6810 } 6811 break; 6812 } 6813 6814 switch (l4_hdr) { 6815 case IPPROTO_TCP: 6816 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 6817 mss_l4len_idx = tcp_hdrlen(skb) << 6818 IXGBE_ADVTXD_L4LEN_SHIFT; 6819 break; 6820 case IPPROTO_SCTP: 6821 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; 6822 mss_l4len_idx = sizeof(struct sctphdr) << 6823 IXGBE_ADVTXD_L4LEN_SHIFT; 6824 break; 6825 case IPPROTO_UDP: 6826 mss_l4len_idx = sizeof(struct udphdr) << 6827 IXGBE_ADVTXD_L4LEN_SHIFT; 6828 break; 6829 default: 6830 if (unlikely(net_ratelimit())) { 6831 dev_warn(tx_ring->dev, 6832 "partial checksum but l4 proto=%x!\n", 6833 l4_hdr); 6834 } 6835 break; 6836 } 6837 6838 /* update TX checksum flag */ 6839 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 6840 } 6841 6842 /* vlan_macip_lens: MACLEN, VLAN tag */ 6843 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6844 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6845 6846 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, 6847 type_tucmd, mss_l4len_idx); 6848 } 6849 6850 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 6851 ((_flag <= _result) ? \ 6852 ((u32)(_input & _flag) * (_result / _flag)) : \ 6853 ((u32)(_input & _flag) / (_flag / _result))) 6854 6855 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 6856 { 6857 /* set type for advanced descriptor with frame checksum insertion */ 6858 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 6859 IXGBE_ADVTXD_DCMD_DEXT | 6860 IXGBE_ADVTXD_DCMD_IFCS; 6861 6862 /* set HW vlan bit if vlan is present */ 6863 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 6864 IXGBE_ADVTXD_DCMD_VLE); 6865 6866 /* set segmentation enable bits for TSO/FSO */ 6867 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 6868 IXGBE_ADVTXD_DCMD_TSE); 6869 6870 /* set timestamp bit if present */ 6871 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 6872 IXGBE_ADVTXD_MAC_TSTAMP); 6873 6874 /* insert frame checksum */ 6875 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 6876 6877 return cmd_type; 6878 } 6879 6880 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 6881 u32 tx_flags, unsigned int paylen) 6882 { 6883 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 6884 6885 /* enable L4 checksum for TSO and TX checksum offload */ 6886 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6887 IXGBE_TX_FLAGS_CSUM, 6888 IXGBE_ADVTXD_POPTS_TXSM); 6889 6890 /* enble IPv4 checksum for TSO */ 6891 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6892 IXGBE_TX_FLAGS_IPV4, 6893 IXGBE_ADVTXD_POPTS_IXSM); 6894 6895 /* 6896 * Check Context must be set if Tx switch is enabled, which it 6897 * always is for case where virtual functions are running 6898 */ 6899 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 6900 IXGBE_TX_FLAGS_CC, 6901 IXGBE_ADVTXD_CC); 6902 6903 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 6904 } 6905 6906 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6907 { 6908 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 6909 6910 /* Herbert's original patch had: 6911 * smp_mb__after_netif_stop_queue(); 6912 * but since that doesn't exist yet, just open code it. 6913 */ 6914 smp_mb(); 6915 6916 /* We need to check again in a case another CPU has just 6917 * made room available. 6918 */ 6919 if (likely(ixgbe_desc_unused(tx_ring) < size)) 6920 return -EBUSY; 6921 6922 /* A reprieve! - use start_queue because it doesn't call schedule */ 6923 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 6924 ++tx_ring->tx_stats.restart_queue; 6925 return 0; 6926 } 6927 6928 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 6929 { 6930 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 6931 return 0; 6932 6933 return __ixgbe_maybe_stop_tx(tx_ring, size); 6934 } 6935 6936 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 6937 IXGBE_TXD_CMD_RS) 6938 6939 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 6940 struct ixgbe_tx_buffer *first, 6941 const u8 hdr_len) 6942 { 6943 struct sk_buff *skb = first->skb; 6944 struct ixgbe_tx_buffer *tx_buffer; 6945 union ixgbe_adv_tx_desc *tx_desc; 6946 struct skb_frag_struct *frag; 6947 dma_addr_t dma; 6948 unsigned int data_len, size; 6949 u32 tx_flags = first->tx_flags; 6950 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 6951 u16 i = tx_ring->next_to_use; 6952 6953 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6954 6955 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 6956 6957 size = skb_headlen(skb); 6958 data_len = skb->data_len; 6959 6960 #ifdef IXGBE_FCOE 6961 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 6962 if (data_len < sizeof(struct fcoe_crc_eof)) { 6963 size -= sizeof(struct fcoe_crc_eof) - data_len; 6964 data_len = 0; 6965 } else { 6966 data_len -= sizeof(struct fcoe_crc_eof); 6967 } 6968 } 6969 6970 #endif 6971 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 6972 6973 tx_buffer = first; 6974 6975 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 6976 if (dma_mapping_error(tx_ring->dev, dma)) 6977 goto dma_error; 6978 6979 /* record length, and DMA address */ 6980 dma_unmap_len_set(tx_buffer, len, size); 6981 dma_unmap_addr_set(tx_buffer, dma, dma); 6982 6983 tx_desc->read.buffer_addr = cpu_to_le64(dma); 6984 6985 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 6986 tx_desc->read.cmd_type_len = 6987 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 6988 6989 i++; 6990 tx_desc++; 6991 if (i == tx_ring->count) { 6992 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6993 i = 0; 6994 } 6995 tx_desc->read.olinfo_status = 0; 6996 6997 dma += IXGBE_MAX_DATA_PER_TXD; 6998 size -= IXGBE_MAX_DATA_PER_TXD; 6999 7000 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7001 } 7002 7003 if (likely(!data_len)) 7004 break; 7005 7006 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7007 7008 i++; 7009 tx_desc++; 7010 if (i == tx_ring->count) { 7011 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7012 i = 0; 7013 } 7014 tx_desc->read.olinfo_status = 0; 7015 7016 #ifdef IXGBE_FCOE 7017 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7018 #else 7019 size = skb_frag_size(frag); 7020 #endif 7021 data_len -= size; 7022 7023 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7024 DMA_TO_DEVICE); 7025 7026 tx_buffer = &tx_ring->tx_buffer_info[i]; 7027 } 7028 7029 /* write last descriptor with RS and EOP bits */ 7030 cmd_type |= size | IXGBE_TXD_CMD; 7031 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7032 7033 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7034 7035 /* set the timestamp */ 7036 first->time_stamp = jiffies; 7037 7038 /* 7039 * Force memory writes to complete before letting h/w know there 7040 * are new descriptors to fetch. (Only applicable for weak-ordered 7041 * memory model archs, such as IA-64). 7042 * 7043 * We also need this memory barrier to make certain all of the 7044 * status bits have been updated before next_to_watch is written. 7045 */ 7046 wmb(); 7047 7048 /* set next_to_watch value indicating a packet is present */ 7049 first->next_to_watch = tx_desc; 7050 7051 i++; 7052 if (i == tx_ring->count) 7053 i = 0; 7054 7055 tx_ring->next_to_use = i; 7056 7057 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7058 7059 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 7060 writel(i, tx_ring->tail); 7061 7062 /* we need this if more than one processor can write to our tail 7063 * at a time, it synchronizes IO on IA64/Altix systems 7064 */ 7065 mmiowb(); 7066 } 7067 7068 return; 7069 dma_error: 7070 dev_err(tx_ring->dev, "TX DMA map failed\n"); 7071 7072 /* clear dma mappings for failed tx_buffer_info map */ 7073 for (;;) { 7074 tx_buffer = &tx_ring->tx_buffer_info[i]; 7075 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 7076 if (tx_buffer == first) 7077 break; 7078 if (i == 0) 7079 i = tx_ring->count; 7080 i--; 7081 } 7082 7083 tx_ring->next_to_use = i; 7084 } 7085 7086 static void ixgbe_atr(struct ixgbe_ring *ring, 7087 struct ixgbe_tx_buffer *first) 7088 { 7089 struct ixgbe_q_vector *q_vector = ring->q_vector; 7090 union ixgbe_atr_hash_dword input = { .dword = 0 }; 7091 union ixgbe_atr_hash_dword common = { .dword = 0 }; 7092 union { 7093 unsigned char *network; 7094 struct iphdr *ipv4; 7095 struct ipv6hdr *ipv6; 7096 } hdr; 7097 struct tcphdr *th; 7098 __be16 vlan_id; 7099 7100 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 7101 if (!q_vector) 7102 return; 7103 7104 /* do nothing if sampling is disabled */ 7105 if (!ring->atr_sample_rate) 7106 return; 7107 7108 ring->atr_count++; 7109 7110 /* snag network header to get L4 type and address */ 7111 hdr.network = skb_network_header(first->skb); 7112 7113 /* Currently only IPv4/IPv6 with TCP is supported */ 7114 if ((first->protocol != htons(ETH_P_IPV6) || 7115 hdr.ipv6->nexthdr != IPPROTO_TCP) && 7116 (first->protocol != htons(ETH_P_IP) || 7117 hdr.ipv4->protocol != IPPROTO_TCP)) 7118 return; 7119 7120 th = tcp_hdr(first->skb); 7121 7122 /* skip this packet since it is invalid or the socket is closing */ 7123 if (!th || th->fin) 7124 return; 7125 7126 /* sample on all syn packets or once every atr sample count */ 7127 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 7128 return; 7129 7130 /* reset sample count */ 7131 ring->atr_count = 0; 7132 7133 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 7134 7135 /* 7136 * src and dst are inverted, think how the receiver sees them 7137 * 7138 * The input is broken into two sections, a non-compressed section 7139 * containing vm_pool, vlan_id, and flow_type. The rest of the data 7140 * is XORed together and stored in the compressed dword. 7141 */ 7142 input.formatted.vlan_id = vlan_id; 7143 7144 /* 7145 * since src port and flex bytes occupy the same word XOR them together 7146 * and write the value to source port portion of compressed dword 7147 */ 7148 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 7149 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 7150 else 7151 common.port.src ^= th->dest ^ first->protocol; 7152 common.port.dst ^= th->source; 7153 7154 if (first->protocol == htons(ETH_P_IP)) { 7155 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 7156 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 7157 } else { 7158 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 7159 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 7160 hdr.ipv6->saddr.s6_addr32[1] ^ 7161 hdr.ipv6->saddr.s6_addr32[2] ^ 7162 hdr.ipv6->saddr.s6_addr32[3] ^ 7163 hdr.ipv6->daddr.s6_addr32[0] ^ 7164 hdr.ipv6->daddr.s6_addr32[1] ^ 7165 hdr.ipv6->daddr.s6_addr32[2] ^ 7166 hdr.ipv6->daddr.s6_addr32[3]; 7167 } 7168 7169 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 7170 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 7171 input, common, ring->queue_index); 7172 } 7173 7174 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 7175 void *accel_priv, select_queue_fallback_t fallback) 7176 { 7177 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 7178 #ifdef IXGBE_FCOE 7179 struct ixgbe_adapter *adapter; 7180 struct ixgbe_ring_feature *f; 7181 int txq; 7182 #endif 7183 7184 if (fwd_adapter) 7185 return skb->queue_mapping + fwd_adapter->tx_base_queue; 7186 7187 #ifdef IXGBE_FCOE 7188 7189 /* 7190 * only execute the code below if protocol is FCoE 7191 * or FIP and we have FCoE enabled on the adapter 7192 */ 7193 switch (vlan_get_protocol(skb)) { 7194 case htons(ETH_P_FCOE): 7195 case htons(ETH_P_FIP): 7196 adapter = netdev_priv(dev); 7197 7198 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 7199 break; 7200 default: 7201 return fallback(dev, skb); 7202 } 7203 7204 f = &adapter->ring_feature[RING_F_FCOE]; 7205 7206 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 7207 smp_processor_id(); 7208 7209 while (txq >= f->indices) 7210 txq -= f->indices; 7211 7212 return txq + f->offset; 7213 #else 7214 return fallback(dev, skb); 7215 #endif 7216 } 7217 7218 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 7219 struct ixgbe_adapter *adapter, 7220 struct ixgbe_ring *tx_ring) 7221 { 7222 struct ixgbe_tx_buffer *first; 7223 int tso; 7224 u32 tx_flags = 0; 7225 unsigned short f; 7226 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 7227 __be16 protocol = skb->protocol; 7228 u8 hdr_len = 0; 7229 7230 /* 7231 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 7232 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 7233 * + 2 desc gap to keep tail from touching head, 7234 * + 1 desc for context descriptor, 7235 * otherwise try next time 7236 */ 7237 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 7238 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 7239 7240 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 7241 tx_ring->tx_stats.tx_busy++; 7242 return NETDEV_TX_BUSY; 7243 } 7244 7245 /* record the location of the first descriptor for this packet */ 7246 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 7247 first->skb = skb; 7248 first->bytecount = skb->len; 7249 first->gso_segs = 1; 7250 7251 /* if we have a HW VLAN tag being added default to the HW one */ 7252 if (skb_vlan_tag_present(skb)) { 7253 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 7254 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7255 /* else if it is a SW VLAN check the next protocol and store the tag */ 7256 } else if (protocol == htons(ETH_P_8021Q)) { 7257 struct vlan_hdr *vhdr, _vhdr; 7258 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 7259 if (!vhdr) 7260 goto out_drop; 7261 7262 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 7263 IXGBE_TX_FLAGS_VLAN_SHIFT; 7264 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 7265 } 7266 protocol = vlan_get_protocol(skb); 7267 7268 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 7269 adapter->ptp_clock && 7270 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 7271 &adapter->state)) { 7272 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7273 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 7274 7275 /* schedule check for Tx timestamp */ 7276 adapter->ptp_tx_skb = skb_get(skb); 7277 adapter->ptp_tx_start = jiffies; 7278 schedule_work(&adapter->ptp_tx_work); 7279 } 7280 7281 skb_tx_timestamp(skb); 7282 7283 #ifdef CONFIG_PCI_IOV 7284 /* 7285 * Use the l2switch_enable flag - would be false if the DMA 7286 * Tx switch had been disabled. 7287 */ 7288 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7289 tx_flags |= IXGBE_TX_FLAGS_CC; 7290 7291 #endif 7292 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 7293 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7294 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 7295 (skb->priority != TC_PRIO_CONTROL))) { 7296 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 7297 tx_flags |= (skb->priority & 0x7) << 7298 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 7299 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 7300 struct vlan_ethhdr *vhdr; 7301 7302 if (skb_cow_head(skb, 0)) 7303 goto out_drop; 7304 vhdr = (struct vlan_ethhdr *)skb->data; 7305 vhdr->h_vlan_TCI = htons(tx_flags >> 7306 IXGBE_TX_FLAGS_VLAN_SHIFT); 7307 } else { 7308 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7309 } 7310 } 7311 7312 /* record initial flags and protocol */ 7313 first->tx_flags = tx_flags; 7314 first->protocol = protocol; 7315 7316 #ifdef IXGBE_FCOE 7317 /* setup tx offload for FCoE */ 7318 if ((protocol == htons(ETH_P_FCOE)) && 7319 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 7320 tso = ixgbe_fso(tx_ring, first, &hdr_len); 7321 if (tso < 0) 7322 goto out_drop; 7323 7324 goto xmit_fcoe; 7325 } 7326 7327 #endif /* IXGBE_FCOE */ 7328 tso = ixgbe_tso(tx_ring, first, &hdr_len); 7329 if (tso < 0) 7330 goto out_drop; 7331 else if (!tso) 7332 ixgbe_tx_csum(tx_ring, first); 7333 7334 /* add the ATR filter if ATR is on */ 7335 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 7336 ixgbe_atr(tx_ring, first); 7337 7338 #ifdef IXGBE_FCOE 7339 xmit_fcoe: 7340 #endif /* IXGBE_FCOE */ 7341 ixgbe_tx_map(tx_ring, first, hdr_len); 7342 7343 return NETDEV_TX_OK; 7344 7345 out_drop: 7346 dev_kfree_skb_any(first->skb); 7347 first->skb = NULL; 7348 7349 return NETDEV_TX_OK; 7350 } 7351 7352 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 7353 struct net_device *netdev, 7354 struct ixgbe_ring *ring) 7355 { 7356 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7357 struct ixgbe_ring *tx_ring; 7358 7359 /* 7360 * The minimum packet size for olinfo paylen is 17 so pad the skb 7361 * in order to meet this minimum size requirement. 7362 */ 7363 if (skb_put_padto(skb, 17)) 7364 return NETDEV_TX_OK; 7365 7366 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 7367 7368 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 7369 } 7370 7371 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 7372 struct net_device *netdev) 7373 { 7374 return __ixgbe_xmit_frame(skb, netdev, NULL); 7375 } 7376 7377 /** 7378 * ixgbe_set_mac - Change the Ethernet Address of the NIC 7379 * @netdev: network interface device structure 7380 * @p: pointer to an address structure 7381 * 7382 * Returns 0 on success, negative on failure 7383 **/ 7384 static int ixgbe_set_mac(struct net_device *netdev, void *p) 7385 { 7386 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7387 struct ixgbe_hw *hw = &adapter->hw; 7388 struct sockaddr *addr = p; 7389 int ret; 7390 7391 if (!is_valid_ether_addr(addr->sa_data)) 7392 return -EADDRNOTAVAIL; 7393 7394 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7395 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 7396 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 7397 7398 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7399 return ret > 0 ? 0 : ret; 7400 } 7401 7402 static int 7403 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 7404 { 7405 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7406 struct ixgbe_hw *hw = &adapter->hw; 7407 u16 value; 7408 int rc; 7409 7410 if (prtad != hw->phy.mdio.prtad) 7411 return -EINVAL; 7412 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 7413 if (!rc) 7414 rc = value; 7415 return rc; 7416 } 7417 7418 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 7419 u16 addr, u16 value) 7420 { 7421 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7422 struct ixgbe_hw *hw = &adapter->hw; 7423 7424 if (prtad != hw->phy.mdio.prtad) 7425 return -EINVAL; 7426 return hw->phy.ops.write_reg(hw, addr, devad, value); 7427 } 7428 7429 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 7430 { 7431 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7432 7433 switch (cmd) { 7434 case SIOCSHWTSTAMP: 7435 return ixgbe_ptp_set_ts_config(adapter, req); 7436 case SIOCGHWTSTAMP: 7437 return ixgbe_ptp_get_ts_config(adapter, req); 7438 default: 7439 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 7440 } 7441 } 7442 7443 /** 7444 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 7445 * netdev->dev_addrs 7446 * @netdev: network interface device structure 7447 * 7448 * Returns non-zero on failure 7449 **/ 7450 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 7451 { 7452 int err = 0; 7453 struct ixgbe_adapter *adapter = netdev_priv(dev); 7454 struct ixgbe_hw *hw = &adapter->hw; 7455 7456 if (is_valid_ether_addr(hw->mac.san_addr)) { 7457 rtnl_lock(); 7458 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 7459 rtnl_unlock(); 7460 7461 /* update SAN MAC vmdq pool selection */ 7462 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 7463 } 7464 return err; 7465 } 7466 7467 /** 7468 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 7469 * netdev->dev_addrs 7470 * @netdev: network interface device structure 7471 * 7472 * Returns non-zero on failure 7473 **/ 7474 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 7475 { 7476 int err = 0; 7477 struct ixgbe_adapter *adapter = netdev_priv(dev); 7478 struct ixgbe_mac_info *mac = &adapter->hw.mac; 7479 7480 if (is_valid_ether_addr(mac->san_addr)) { 7481 rtnl_lock(); 7482 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 7483 rtnl_unlock(); 7484 } 7485 return err; 7486 } 7487 7488 #ifdef CONFIG_NET_POLL_CONTROLLER 7489 /* 7490 * Polling 'interrupt' - used by things like netconsole to send skbs 7491 * without having to re-enable interrupts. It's not called while 7492 * the interrupt routine is executing. 7493 */ 7494 static void ixgbe_netpoll(struct net_device *netdev) 7495 { 7496 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7497 int i; 7498 7499 /* if interface is down do nothing */ 7500 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7501 return; 7502 7503 /* loop through and schedule all active queues */ 7504 for (i = 0; i < adapter->num_q_vectors; i++) 7505 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 7506 } 7507 7508 #endif 7509 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 7510 struct rtnl_link_stats64 *stats) 7511 { 7512 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7513 int i; 7514 7515 rcu_read_lock(); 7516 for (i = 0; i < adapter->num_rx_queues; i++) { 7517 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 7518 u64 bytes, packets; 7519 unsigned int start; 7520 7521 if (ring) { 7522 do { 7523 start = u64_stats_fetch_begin_irq(&ring->syncp); 7524 packets = ring->stats.packets; 7525 bytes = ring->stats.bytes; 7526 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7527 stats->rx_packets += packets; 7528 stats->rx_bytes += bytes; 7529 } 7530 } 7531 7532 for (i = 0; i < adapter->num_tx_queues; i++) { 7533 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 7534 u64 bytes, packets; 7535 unsigned int start; 7536 7537 if (ring) { 7538 do { 7539 start = u64_stats_fetch_begin_irq(&ring->syncp); 7540 packets = ring->stats.packets; 7541 bytes = ring->stats.bytes; 7542 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7543 stats->tx_packets += packets; 7544 stats->tx_bytes += bytes; 7545 } 7546 } 7547 rcu_read_unlock(); 7548 /* following stats updated by ixgbe_watchdog_task() */ 7549 stats->multicast = netdev->stats.multicast; 7550 stats->rx_errors = netdev->stats.rx_errors; 7551 stats->rx_length_errors = netdev->stats.rx_length_errors; 7552 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 7553 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 7554 return stats; 7555 } 7556 7557 #ifdef CONFIG_IXGBE_DCB 7558 /** 7559 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 7560 * @adapter: pointer to ixgbe_adapter 7561 * @tc: number of traffic classes currently enabled 7562 * 7563 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 7564 * 802.1Q priority maps to a packet buffer that exists. 7565 */ 7566 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 7567 { 7568 struct ixgbe_hw *hw = &adapter->hw; 7569 u32 reg, rsave; 7570 int i; 7571 7572 /* 82598 have a static priority to TC mapping that can not 7573 * be changed so no validation is needed. 7574 */ 7575 if (hw->mac.type == ixgbe_mac_82598EB) 7576 return; 7577 7578 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 7579 rsave = reg; 7580 7581 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 7582 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 7583 7584 /* If up2tc is out of bounds default to zero */ 7585 if (up2tc > tc) 7586 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 7587 } 7588 7589 if (reg != rsave) 7590 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 7591 7592 return; 7593 } 7594 7595 /** 7596 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 7597 * @adapter: Pointer to adapter struct 7598 * 7599 * Populate the netdev user priority to tc map 7600 */ 7601 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 7602 { 7603 struct net_device *dev = adapter->netdev; 7604 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 7605 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 7606 u8 prio; 7607 7608 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 7609 u8 tc = 0; 7610 7611 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 7612 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 7613 else if (ets) 7614 tc = ets->prio_tc[prio]; 7615 7616 netdev_set_prio_tc_map(dev, prio, tc); 7617 } 7618 } 7619 7620 #endif /* CONFIG_IXGBE_DCB */ 7621 /** 7622 * ixgbe_setup_tc - configure net_device for multiple traffic classes 7623 * 7624 * @netdev: net device to configure 7625 * @tc: number of traffic classes to enable 7626 */ 7627 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 7628 { 7629 struct ixgbe_adapter *adapter = netdev_priv(dev); 7630 struct ixgbe_hw *hw = &adapter->hw; 7631 bool pools; 7632 7633 /* Hardware supports up to 8 traffic classes */ 7634 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || 7635 (hw->mac.type == ixgbe_mac_82598EB && 7636 tc < MAX_TRAFFIC_CLASS)) 7637 return -EINVAL; 7638 7639 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 7640 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 7641 return -EBUSY; 7642 7643 /* Hardware has to reinitialize queues and interrupts to 7644 * match packet buffer alignment. Unfortunately, the 7645 * hardware is not flexible enough to do this dynamically. 7646 */ 7647 if (netif_running(dev)) 7648 ixgbe_close(dev); 7649 ixgbe_clear_interrupt_scheme(adapter); 7650 7651 #ifdef CONFIG_IXGBE_DCB 7652 if (tc) { 7653 netdev_set_num_tc(dev, tc); 7654 ixgbe_set_prio_tc_map(adapter); 7655 7656 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 7657 7658 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 7659 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 7660 adapter->hw.fc.requested_mode = ixgbe_fc_none; 7661 } 7662 } else { 7663 netdev_reset_tc(dev); 7664 7665 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 7666 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 7667 7668 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 7669 7670 adapter->temp_dcb_cfg.pfc_mode_enable = false; 7671 adapter->dcb_cfg.pfc_mode_enable = false; 7672 } 7673 7674 ixgbe_validate_rtr(adapter, tc); 7675 7676 #endif /* CONFIG_IXGBE_DCB */ 7677 ixgbe_init_interrupt_scheme(adapter); 7678 7679 if (netif_running(dev)) 7680 return ixgbe_open(dev); 7681 7682 return 0; 7683 } 7684 7685 #ifdef CONFIG_PCI_IOV 7686 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 7687 { 7688 struct net_device *netdev = adapter->netdev; 7689 7690 rtnl_lock(); 7691 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 7692 rtnl_unlock(); 7693 } 7694 7695 #endif 7696 void ixgbe_do_reset(struct net_device *netdev) 7697 { 7698 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7699 7700 if (netif_running(netdev)) 7701 ixgbe_reinit_locked(adapter); 7702 else 7703 ixgbe_reset(adapter); 7704 } 7705 7706 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 7707 netdev_features_t features) 7708 { 7709 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7710 7711 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 7712 if (!(features & NETIF_F_RXCSUM)) 7713 features &= ~NETIF_F_LRO; 7714 7715 /* Turn off LRO if not RSC capable */ 7716 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 7717 features &= ~NETIF_F_LRO; 7718 7719 return features; 7720 } 7721 7722 static int ixgbe_set_features(struct net_device *netdev, 7723 netdev_features_t features) 7724 { 7725 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7726 netdev_features_t changed = netdev->features ^ features; 7727 bool need_reset = false; 7728 7729 /* Make sure RSC matches LRO, reset if change */ 7730 if (!(features & NETIF_F_LRO)) { 7731 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 7732 need_reset = true; 7733 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 7734 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 7735 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 7736 if (adapter->rx_itr_setting == 1 || 7737 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 7738 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 7739 need_reset = true; 7740 } else if ((changed ^ features) & NETIF_F_LRO) { 7741 e_info(probe, "rx-usecs set too low, " 7742 "disabling RSC\n"); 7743 } 7744 } 7745 7746 /* 7747 * Check if Flow Director n-tuple support was enabled or disabled. If 7748 * the state changed, we need to reset. 7749 */ 7750 switch (features & NETIF_F_NTUPLE) { 7751 case NETIF_F_NTUPLE: 7752 /* turn off ATR, enable perfect filters and reset */ 7753 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 7754 need_reset = true; 7755 7756 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 7757 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7758 break; 7759 default: 7760 /* turn off perfect filters, enable ATR and reset */ 7761 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 7762 need_reset = true; 7763 7764 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7765 7766 /* We cannot enable ATR if SR-IOV is enabled */ 7767 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7768 break; 7769 7770 /* We cannot enable ATR if we have 2 or more traffic classes */ 7771 if (netdev_get_num_tc(netdev) > 1) 7772 break; 7773 7774 /* We cannot enable ATR if RSS is disabled */ 7775 if (adapter->ring_feature[RING_F_RSS].limit <= 1) 7776 break; 7777 7778 /* A sample rate of 0 indicates ATR disabled */ 7779 if (!adapter->atr_sample_rate) 7780 break; 7781 7782 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 7783 break; 7784 } 7785 7786 if (features & NETIF_F_HW_VLAN_CTAG_RX) 7787 ixgbe_vlan_strip_enable(adapter); 7788 else 7789 ixgbe_vlan_strip_disable(adapter); 7790 7791 if (changed & NETIF_F_RXALL) 7792 need_reset = true; 7793 7794 netdev->features = features; 7795 if (need_reset) 7796 ixgbe_do_reset(netdev); 7797 7798 return 0; 7799 } 7800 7801 /** 7802 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up 7803 * @dev: The port's netdev 7804 * @sa_family: Socket Family that VXLAN is notifiying us about 7805 * @port: New UDP port number that VXLAN started listening to 7806 **/ 7807 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, 7808 __be16 port) 7809 { 7810 struct ixgbe_adapter *adapter = netdev_priv(dev); 7811 struct ixgbe_hw *hw = &adapter->hw; 7812 u16 new_port = ntohs(port); 7813 7814 if (sa_family == AF_INET6) 7815 return; 7816 7817 if (adapter->vxlan_port == new_port) { 7818 netdev_info(dev, "Port %d already offloaded\n", new_port); 7819 return; 7820 } 7821 7822 if (adapter->vxlan_port) { 7823 netdev_info(dev, 7824 "Hit Max num of UDP ports, not adding port %d\n", 7825 new_port); 7826 return; 7827 } 7828 7829 adapter->vxlan_port = new_port; 7830 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port); 7831 } 7832 7833 /** 7834 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away 7835 * @dev: The port's netdev 7836 * @sa_family: Socket Family that VXLAN is notifying us about 7837 * @port: UDP port number that VXLAN stopped listening to 7838 **/ 7839 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, 7840 __be16 port) 7841 { 7842 struct ixgbe_adapter *adapter = netdev_priv(dev); 7843 struct ixgbe_hw *hw = &adapter->hw; 7844 u16 new_port = ntohs(port); 7845 7846 if (sa_family == AF_INET6) 7847 return; 7848 7849 if (adapter->vxlan_port != new_port) { 7850 netdev_info(dev, "Port %d was not found, not deleting\n", 7851 new_port); 7852 return; 7853 } 7854 7855 adapter->vxlan_port = 0; 7856 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 0); 7857 } 7858 7859 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 7860 struct net_device *dev, 7861 const unsigned char *addr, u16 vid, 7862 u16 flags) 7863 { 7864 /* guarantee we can provide a unique filter for the unicast address */ 7865 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 7866 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev)) 7867 return -ENOMEM; 7868 } 7869 7870 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 7871 } 7872 7873 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 7874 struct nlmsghdr *nlh, u16 flags) 7875 { 7876 struct ixgbe_adapter *adapter = netdev_priv(dev); 7877 struct nlattr *attr, *br_spec; 7878 int rem; 7879 7880 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7881 return -EOPNOTSUPP; 7882 7883 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 7884 if (!br_spec) 7885 return -EINVAL; 7886 7887 nla_for_each_nested(attr, br_spec, rem) { 7888 __u16 mode; 7889 u32 reg = 0; 7890 7891 if (nla_type(attr) != IFLA_BRIDGE_MODE) 7892 continue; 7893 7894 if (nla_len(attr) < sizeof(mode)) 7895 return -EINVAL; 7896 7897 mode = nla_get_u16(attr); 7898 if (mode == BRIDGE_MODE_VEPA) { 7899 reg = 0; 7900 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB; 7901 } else if (mode == BRIDGE_MODE_VEB) { 7902 reg = IXGBE_PFDTXGSWC_VT_LBEN; 7903 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB; 7904 } else 7905 return -EINVAL; 7906 7907 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg); 7908 7909 e_info(drv, "enabling bridge mode: %s\n", 7910 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 7911 } 7912 7913 return 0; 7914 } 7915 7916 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 7917 struct net_device *dev, 7918 u32 filter_mask) 7919 { 7920 struct ixgbe_adapter *adapter = netdev_priv(dev); 7921 u16 mode; 7922 7923 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 7924 return 0; 7925 7926 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB) 7927 mode = BRIDGE_MODE_VEB; 7928 else 7929 mode = BRIDGE_MODE_VEPA; 7930 7931 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0); 7932 } 7933 7934 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 7935 { 7936 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 7937 struct ixgbe_adapter *adapter = netdev_priv(pdev); 7938 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 7939 unsigned int limit; 7940 int pool, err; 7941 7942 /* Hardware has a limited number of available pools. Each VF, and the 7943 * PF require a pool. Check to ensure we don't attempt to use more 7944 * then the available number of pools. 7945 */ 7946 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 7947 return ERR_PTR(-EINVAL); 7948 7949 #ifdef CONFIG_RPS 7950 if (vdev->num_rx_queues != vdev->num_tx_queues) { 7951 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 7952 vdev->name); 7953 return ERR_PTR(-EINVAL); 7954 } 7955 #endif 7956 /* Check for hardware restriction on number of rx/tx queues */ 7957 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 7958 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 7959 netdev_info(pdev, 7960 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 7961 pdev->name); 7962 return ERR_PTR(-EINVAL); 7963 } 7964 7965 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7966 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 7967 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 7968 return ERR_PTR(-EBUSY); 7969 7970 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL); 7971 if (!fwd_adapter) 7972 return ERR_PTR(-ENOMEM); 7973 7974 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 7975 adapter->num_rx_pools++; 7976 set_bit(pool, &adapter->fwd_bitmask); 7977 limit = find_last_bit(&adapter->fwd_bitmask, 32); 7978 7979 /* Enable VMDq flag so device will be set in VM mode */ 7980 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 7981 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 7982 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 7983 7984 /* Force reinit of ring allocation with VMDQ enabled */ 7985 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 7986 if (err) 7987 goto fwd_add_err; 7988 fwd_adapter->pool = pool; 7989 fwd_adapter->real_adapter = adapter; 7990 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 7991 if (err) 7992 goto fwd_add_err; 7993 netif_tx_start_all_queues(vdev); 7994 return fwd_adapter; 7995 fwd_add_err: 7996 /* unwind counter and free adapter struct */ 7997 netdev_info(pdev, 7998 "%s: dfwd hardware acceleration failed\n", vdev->name); 7999 clear_bit(pool, &adapter->fwd_bitmask); 8000 adapter->num_rx_pools--; 8001 kfree(fwd_adapter); 8002 return ERR_PTR(err); 8003 } 8004 8005 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 8006 { 8007 struct ixgbe_fwd_adapter *fwd_adapter = priv; 8008 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 8009 unsigned int limit; 8010 8011 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 8012 adapter->num_rx_pools--; 8013 8014 limit = find_last_bit(&adapter->fwd_bitmask, 32); 8015 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 8016 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 8017 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 8018 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 8019 fwd_adapter->pool, adapter->num_rx_pools, 8020 fwd_adapter->rx_base_queue, 8021 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 8022 adapter->fwd_bitmask); 8023 kfree(fwd_adapter); 8024 } 8025 8026 static const struct net_device_ops ixgbe_netdev_ops = { 8027 .ndo_open = ixgbe_open, 8028 .ndo_stop = ixgbe_close, 8029 .ndo_start_xmit = ixgbe_xmit_frame, 8030 .ndo_select_queue = ixgbe_select_queue, 8031 .ndo_set_rx_mode = ixgbe_set_rx_mode, 8032 .ndo_validate_addr = eth_validate_addr, 8033 .ndo_set_mac_address = ixgbe_set_mac, 8034 .ndo_change_mtu = ixgbe_change_mtu, 8035 .ndo_tx_timeout = ixgbe_tx_timeout, 8036 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 8037 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 8038 .ndo_do_ioctl = ixgbe_ioctl, 8039 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 8040 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 8041 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 8042 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 8043 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 8044 .ndo_get_stats64 = ixgbe_get_stats64, 8045 #ifdef CONFIG_IXGBE_DCB 8046 .ndo_setup_tc = ixgbe_setup_tc, 8047 #endif 8048 #ifdef CONFIG_NET_POLL_CONTROLLER 8049 .ndo_poll_controller = ixgbe_netpoll, 8050 #endif 8051 #ifdef CONFIG_NET_RX_BUSY_POLL 8052 .ndo_busy_poll = ixgbe_low_latency_recv, 8053 #endif 8054 #ifdef IXGBE_FCOE 8055 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 8056 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 8057 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 8058 .ndo_fcoe_enable = ixgbe_fcoe_enable, 8059 .ndo_fcoe_disable = ixgbe_fcoe_disable, 8060 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 8061 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 8062 #endif /* IXGBE_FCOE */ 8063 .ndo_set_features = ixgbe_set_features, 8064 .ndo_fix_features = ixgbe_fix_features, 8065 .ndo_fdb_add = ixgbe_ndo_fdb_add, 8066 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 8067 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 8068 .ndo_dfwd_add_station = ixgbe_fwd_add, 8069 .ndo_dfwd_del_station = ixgbe_fwd_del, 8070 .ndo_add_vxlan_port = ixgbe_add_vxlan_port, 8071 .ndo_del_vxlan_port = ixgbe_del_vxlan_port, 8072 }; 8073 8074 /** 8075 * ixgbe_enumerate_functions - Get the number of ports this device has 8076 * @adapter: adapter structure 8077 * 8078 * This function enumerates the phsyical functions co-located on a single slot, 8079 * in order to determine how many ports a device has. This is most useful in 8080 * determining the required GT/s of PCIe bandwidth necessary for optimal 8081 * performance. 8082 **/ 8083 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 8084 { 8085 struct pci_dev *entry, *pdev = adapter->pdev; 8086 int physfns = 0; 8087 8088 /* Some cards can not use the generic count PCIe functions method, 8089 * because they are behind a parent switch, so we hardcode these with 8090 * the correct number of functions. 8091 */ 8092 if (ixgbe_pcie_from_parent(&adapter->hw)) 8093 physfns = 4; 8094 8095 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 8096 /* don't count virtual functions */ 8097 if (entry->is_virtfn) 8098 continue; 8099 8100 /* When the devices on the bus don't all match our device ID, 8101 * we can't reliably determine the correct number of 8102 * functions. This can occur if a function has been direct 8103 * attached to a virtual machine using VT-d, for example. In 8104 * this case, simply return -1 to indicate this. 8105 */ 8106 if ((entry->vendor != pdev->vendor) || 8107 (entry->device != pdev->device)) 8108 return -1; 8109 8110 physfns++; 8111 } 8112 8113 return physfns; 8114 } 8115 8116 /** 8117 * ixgbe_wol_supported - Check whether device supports WoL 8118 * @hw: hw specific details 8119 * @device_id: the device ID 8120 * @subdev_id: the subsystem device ID 8121 * 8122 * This function is used by probe and ethtool to determine 8123 * which devices have WoL support 8124 * 8125 **/ 8126 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 8127 u16 subdevice_id) 8128 { 8129 struct ixgbe_hw *hw = &adapter->hw; 8130 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 8131 int is_wol_supported = 0; 8132 8133 switch (device_id) { 8134 case IXGBE_DEV_ID_82599_SFP: 8135 /* Only these subdevices could supports WOL */ 8136 switch (subdevice_id) { 8137 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 8138 case IXGBE_SUBDEV_ID_82599_560FLR: 8139 /* only support first port */ 8140 if (hw->bus.func != 0) 8141 break; 8142 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 8143 case IXGBE_SUBDEV_ID_82599_SFP: 8144 case IXGBE_SUBDEV_ID_82599_RNDC: 8145 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 8146 case IXGBE_SUBDEV_ID_82599_LOM_SFP: 8147 is_wol_supported = 1; 8148 break; 8149 } 8150 break; 8151 case IXGBE_DEV_ID_82599EN_SFP: 8152 /* Only this subdevice supports WOL */ 8153 switch (subdevice_id) { 8154 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 8155 is_wol_supported = 1; 8156 break; 8157 } 8158 break; 8159 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 8160 /* All except this subdevice support WOL */ 8161 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 8162 is_wol_supported = 1; 8163 break; 8164 case IXGBE_DEV_ID_82599_KX4: 8165 is_wol_supported = 1; 8166 break; 8167 case IXGBE_DEV_ID_X540T: 8168 case IXGBE_DEV_ID_X540T1: 8169 /* check eeprom to see if enabled wol */ 8170 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 8171 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 8172 (hw->bus.func == 0))) { 8173 is_wol_supported = 1; 8174 } 8175 break; 8176 } 8177 8178 return is_wol_supported; 8179 } 8180 8181 /** 8182 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM 8183 * @adapter: Pointer to adapter struct 8184 */ 8185 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter) 8186 { 8187 #ifdef CONFIG_OF 8188 struct device_node *dp = pci_device_to_OF_node(adapter->pdev); 8189 struct ixgbe_hw *hw = &adapter->hw; 8190 const unsigned char *addr; 8191 8192 addr = of_get_mac_address(dp); 8193 if (addr) { 8194 ether_addr_copy(hw->mac.perm_addr, addr); 8195 return; 8196 } 8197 #endif /* CONFIG_OF */ 8198 8199 #ifdef CONFIG_SPARC 8200 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr); 8201 #endif /* CONFIG_SPARC */ 8202 } 8203 8204 /** 8205 * ixgbe_probe - Device Initialization Routine 8206 * @pdev: PCI device information struct 8207 * @ent: entry in ixgbe_pci_tbl 8208 * 8209 * Returns 0 on success, negative on failure 8210 * 8211 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 8212 * The OS initialization, configuring of the adapter private structure, 8213 * and a hardware reset occur. 8214 **/ 8215 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 8216 { 8217 struct net_device *netdev; 8218 struct ixgbe_adapter *adapter = NULL; 8219 struct ixgbe_hw *hw; 8220 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 8221 int i, err, pci_using_dac, expected_gts; 8222 unsigned int indices = MAX_TX_QUEUES; 8223 u8 part_str[IXGBE_PBANUM_LENGTH]; 8224 bool disable_dev = false; 8225 #ifdef IXGBE_FCOE 8226 u16 device_caps; 8227 #endif 8228 u32 eec; 8229 8230 /* Catch broken hardware that put the wrong VF device ID in 8231 * the PCIe SR-IOV capability. 8232 */ 8233 if (pdev->is_virtfn) { 8234 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 8235 pci_name(pdev), pdev->vendor, pdev->device); 8236 return -EINVAL; 8237 } 8238 8239 err = pci_enable_device_mem(pdev); 8240 if (err) 8241 return err; 8242 8243 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 8244 pci_using_dac = 1; 8245 } else { 8246 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 8247 if (err) { 8248 dev_err(&pdev->dev, 8249 "No usable DMA configuration, aborting\n"); 8250 goto err_dma; 8251 } 8252 pci_using_dac = 0; 8253 } 8254 8255 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 8256 IORESOURCE_MEM), ixgbe_driver_name); 8257 if (err) { 8258 dev_err(&pdev->dev, 8259 "pci_request_selected_regions failed 0x%x\n", err); 8260 goto err_pci_reg; 8261 } 8262 8263 pci_enable_pcie_error_reporting(pdev); 8264 8265 pci_set_master(pdev); 8266 pci_save_state(pdev); 8267 8268 if (ii->mac == ixgbe_mac_82598EB) { 8269 #ifdef CONFIG_IXGBE_DCB 8270 /* 8 TC w/ 4 queues per TC */ 8271 indices = 4 * MAX_TRAFFIC_CLASS; 8272 #else 8273 indices = IXGBE_MAX_RSS_INDICES; 8274 #endif 8275 } 8276 8277 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 8278 if (!netdev) { 8279 err = -ENOMEM; 8280 goto err_alloc_etherdev; 8281 } 8282 8283 SET_NETDEV_DEV(netdev, &pdev->dev); 8284 8285 adapter = netdev_priv(netdev); 8286 8287 adapter->netdev = netdev; 8288 adapter->pdev = pdev; 8289 hw = &adapter->hw; 8290 hw->back = adapter; 8291 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 8292 8293 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 8294 pci_resource_len(pdev, 0)); 8295 adapter->io_addr = hw->hw_addr; 8296 if (!hw->hw_addr) { 8297 err = -EIO; 8298 goto err_ioremap; 8299 } 8300 8301 netdev->netdev_ops = &ixgbe_netdev_ops; 8302 ixgbe_set_ethtool_ops(netdev); 8303 netdev->watchdog_timeo = 5 * HZ; 8304 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 8305 8306 /* Setup hw api */ 8307 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); 8308 hw->mac.type = ii->mac; 8309 8310 /* EEPROM */ 8311 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); 8312 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 8313 if (ixgbe_removed(hw->hw_addr)) { 8314 err = -EIO; 8315 goto err_ioremap; 8316 } 8317 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 8318 if (!(eec & (1 << 8))) 8319 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 8320 8321 /* PHY */ 8322 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 8323 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 8324 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 8325 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 8326 hw->phy.mdio.mmds = 0; 8327 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 8328 hw->phy.mdio.dev = netdev; 8329 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 8330 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 8331 8332 ii->get_invariants(hw); 8333 8334 /* setup the private structure */ 8335 err = ixgbe_sw_init(adapter); 8336 if (err) 8337 goto err_sw_init; 8338 8339 /* Make it possible the adapter to be woken up via WOL */ 8340 switch (adapter->hw.mac.type) { 8341 case ixgbe_mac_82599EB: 8342 case ixgbe_mac_X540: 8343 case ixgbe_mac_X550: 8344 case ixgbe_mac_X550EM_x: 8345 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8346 break; 8347 default: 8348 break; 8349 } 8350 8351 /* 8352 * If there is a fan on this device and it has failed log the 8353 * failure. 8354 */ 8355 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 8356 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 8357 if (esdp & IXGBE_ESDP_SDP1) 8358 e_crit(probe, "Fan has stopped, replace the adapter\n"); 8359 } 8360 8361 if (allow_unsupported_sfp) 8362 hw->allow_unsupported_sfp = allow_unsupported_sfp; 8363 8364 /* reset_hw fills in the perm_addr as well */ 8365 hw->phy.reset_if_overtemp = true; 8366 err = hw->mac.ops.reset_hw(hw); 8367 hw->phy.reset_if_overtemp = false; 8368 if (err == IXGBE_ERR_SFP_NOT_PRESENT && 8369 hw->mac.type == ixgbe_mac_82598EB) { 8370 err = 0; 8371 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 8372 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 8373 e_dev_err("Reload the driver after installing a supported module.\n"); 8374 goto err_sw_init; 8375 } else if (err) { 8376 e_dev_err("HW Init failed: %d\n", err); 8377 goto err_sw_init; 8378 } 8379 8380 #ifdef CONFIG_PCI_IOV 8381 /* SR-IOV not supported on the 82598 */ 8382 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8383 goto skip_sriov; 8384 /* Mailbox */ 8385 ixgbe_init_mbx_params_pf(hw); 8386 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops)); 8387 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 8388 ixgbe_enable_sriov(adapter); 8389 skip_sriov: 8390 8391 #endif 8392 netdev->features = NETIF_F_SG | 8393 NETIF_F_IP_CSUM | 8394 NETIF_F_IPV6_CSUM | 8395 NETIF_F_HW_VLAN_CTAG_TX | 8396 NETIF_F_HW_VLAN_CTAG_RX | 8397 NETIF_F_HW_VLAN_CTAG_FILTER | 8398 NETIF_F_TSO | 8399 NETIF_F_TSO6 | 8400 NETIF_F_RXHASH | 8401 NETIF_F_RXCSUM; 8402 8403 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD; 8404 8405 switch (adapter->hw.mac.type) { 8406 case ixgbe_mac_82599EB: 8407 case ixgbe_mac_X540: 8408 case ixgbe_mac_X550: 8409 case ixgbe_mac_X550EM_x: 8410 netdev->features |= NETIF_F_SCTP_CSUM; 8411 netdev->hw_features |= NETIF_F_SCTP_CSUM | 8412 NETIF_F_NTUPLE; 8413 break; 8414 default: 8415 break; 8416 } 8417 8418 netdev->hw_features |= NETIF_F_RXALL; 8419 8420 netdev->vlan_features |= NETIF_F_TSO; 8421 netdev->vlan_features |= NETIF_F_TSO6; 8422 netdev->vlan_features |= NETIF_F_IP_CSUM; 8423 netdev->vlan_features |= NETIF_F_IPV6_CSUM; 8424 netdev->vlan_features |= NETIF_F_SG; 8425 8426 netdev->priv_flags |= IFF_UNICAST_FLT; 8427 netdev->priv_flags |= IFF_SUPP_NOFCS; 8428 8429 switch (adapter->hw.mac.type) { 8430 case ixgbe_mac_X550: 8431 case ixgbe_mac_X550EM_x: 8432 netdev->hw_enc_features |= NETIF_F_RXCSUM; 8433 break; 8434 default: 8435 break; 8436 } 8437 8438 #ifdef CONFIG_IXGBE_DCB 8439 netdev->dcbnl_ops = &dcbnl_ops; 8440 #endif 8441 8442 #ifdef IXGBE_FCOE 8443 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 8444 unsigned int fcoe_l; 8445 8446 if (hw->mac.ops.get_device_caps) { 8447 hw->mac.ops.get_device_caps(hw, &device_caps); 8448 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 8449 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 8450 } 8451 8452 8453 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 8454 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 8455 8456 netdev->features |= NETIF_F_FSO | 8457 NETIF_F_FCOE_CRC; 8458 8459 netdev->vlan_features |= NETIF_F_FSO | 8460 NETIF_F_FCOE_CRC | 8461 NETIF_F_FCOE_MTU; 8462 } 8463 #endif /* IXGBE_FCOE */ 8464 if (pci_using_dac) { 8465 netdev->features |= NETIF_F_HIGHDMA; 8466 netdev->vlan_features |= NETIF_F_HIGHDMA; 8467 } 8468 8469 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 8470 netdev->hw_features |= NETIF_F_LRO; 8471 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 8472 netdev->features |= NETIF_F_LRO; 8473 8474 /* make sure the EEPROM is good */ 8475 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 8476 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 8477 err = -EIO; 8478 goto err_sw_init; 8479 } 8480 8481 ixgbe_get_platform_mac_addr(adapter); 8482 8483 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 8484 8485 if (!is_valid_ether_addr(netdev->dev_addr)) { 8486 e_dev_err("invalid MAC address\n"); 8487 err = -EIO; 8488 goto err_sw_init; 8489 } 8490 8491 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr); 8492 8493 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 8494 (unsigned long) adapter); 8495 8496 if (ixgbe_removed(hw->hw_addr)) { 8497 err = -EIO; 8498 goto err_sw_init; 8499 } 8500 INIT_WORK(&adapter->service_task, ixgbe_service_task); 8501 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 8502 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 8503 8504 err = ixgbe_init_interrupt_scheme(adapter); 8505 if (err) 8506 goto err_sw_init; 8507 8508 /* WOL not supported for all devices */ 8509 adapter->wol = 0; 8510 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 8511 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 8512 pdev->subsystem_device); 8513 if (hw->wol_enabled) 8514 adapter->wol = IXGBE_WUFC_MAG; 8515 8516 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 8517 8518 /* save off EEPROM version number */ 8519 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 8520 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 8521 8522 /* pick up the PCI bus settings for reporting later */ 8523 hw->mac.ops.get_bus_info(hw); 8524 if (ixgbe_pcie_from_parent(hw)) 8525 ixgbe_get_parent_bus_info(adapter); 8526 8527 /* calculate the expected PCIe bandwidth required for optimal 8528 * performance. Note that some older parts will never have enough 8529 * bandwidth due to being older generation PCIe parts. We clamp these 8530 * parts to ensure no warning is displayed if it can't be fixed. 8531 */ 8532 switch (hw->mac.type) { 8533 case ixgbe_mac_82598EB: 8534 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 8535 break; 8536 default: 8537 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 8538 break; 8539 } 8540 8541 /* don't check link if we failed to enumerate functions */ 8542 if (expected_gts > 0) 8543 ixgbe_check_minimum_link(adapter, expected_gts); 8544 8545 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 8546 if (err) 8547 strlcpy(part_str, "Unknown", sizeof(part_str)); 8548 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 8549 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 8550 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 8551 part_str); 8552 else 8553 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 8554 hw->mac.type, hw->phy.type, part_str); 8555 8556 e_dev_info("%pM\n", netdev->dev_addr); 8557 8558 /* reset the hardware with the new settings */ 8559 err = hw->mac.ops.start_hw(hw); 8560 if (err == IXGBE_ERR_EEPROM_VERSION) { 8561 /* We are running on a pre-production device, log a warning */ 8562 e_dev_warn("This device is a pre-production adapter/LOM. " 8563 "Please be aware there may be issues associated " 8564 "with your hardware. If you are experiencing " 8565 "problems please contact your Intel or hardware " 8566 "representative who provided you with this " 8567 "hardware.\n"); 8568 } 8569 strcpy(netdev->name, "eth%d"); 8570 err = register_netdev(netdev); 8571 if (err) 8572 goto err_register; 8573 8574 pci_set_drvdata(pdev, adapter); 8575 8576 /* power down the optics for 82599 SFP+ fiber */ 8577 if (hw->mac.ops.disable_tx_laser) 8578 hw->mac.ops.disable_tx_laser(hw); 8579 8580 /* carrier off reporting is important to ethtool even BEFORE open */ 8581 netif_carrier_off(netdev); 8582 8583 #ifdef CONFIG_IXGBE_DCA 8584 if (dca_add_requester(&pdev->dev) == 0) { 8585 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 8586 ixgbe_setup_dca(adapter); 8587 } 8588 #endif 8589 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 8590 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 8591 for (i = 0; i < adapter->num_vfs; i++) 8592 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 8593 } 8594 8595 /* firmware requires driver version to be 0xFFFFFFFF 8596 * since os does not support feature 8597 */ 8598 if (hw->mac.ops.set_fw_drv_ver) 8599 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 8600 0xFF); 8601 8602 /* add san mac addr to netdev */ 8603 ixgbe_add_sanmac_netdev(netdev); 8604 8605 e_dev_info("%s\n", ixgbe_default_device_descr); 8606 8607 #ifdef CONFIG_IXGBE_HWMON 8608 if (ixgbe_sysfs_init(adapter)) 8609 e_err(probe, "failed to allocate sysfs resources\n"); 8610 #endif /* CONFIG_IXGBE_HWMON */ 8611 8612 ixgbe_dbg_adapter_init(adapter); 8613 8614 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 8615 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 8616 hw->mac.ops.setup_link(hw, 8617 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 8618 true); 8619 8620 return 0; 8621 8622 err_register: 8623 ixgbe_release_hw_control(adapter); 8624 ixgbe_clear_interrupt_scheme(adapter); 8625 err_sw_init: 8626 ixgbe_disable_sriov(adapter); 8627 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 8628 iounmap(adapter->io_addr); 8629 kfree(adapter->mac_table); 8630 err_ioremap: 8631 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8632 free_netdev(netdev); 8633 err_alloc_etherdev: 8634 pci_release_selected_regions(pdev, 8635 pci_select_bars(pdev, IORESOURCE_MEM)); 8636 err_pci_reg: 8637 err_dma: 8638 if (!adapter || disable_dev) 8639 pci_disable_device(pdev); 8640 return err; 8641 } 8642 8643 /** 8644 * ixgbe_remove - Device Removal Routine 8645 * @pdev: PCI device information struct 8646 * 8647 * ixgbe_remove is called by the PCI subsystem to alert the driver 8648 * that it should release a PCI device. The could be caused by a 8649 * Hot-Plug event, or because the driver is going to be removed from 8650 * memory. 8651 **/ 8652 static void ixgbe_remove(struct pci_dev *pdev) 8653 { 8654 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8655 struct net_device *netdev; 8656 bool disable_dev; 8657 8658 /* if !adapter then we already cleaned up in probe */ 8659 if (!adapter) 8660 return; 8661 8662 netdev = adapter->netdev; 8663 ixgbe_dbg_adapter_exit(adapter); 8664 8665 set_bit(__IXGBE_REMOVING, &adapter->state); 8666 cancel_work_sync(&adapter->service_task); 8667 8668 8669 #ifdef CONFIG_IXGBE_DCA 8670 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 8671 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 8672 dca_remove_requester(&pdev->dev); 8673 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 8674 } 8675 8676 #endif 8677 #ifdef CONFIG_IXGBE_HWMON 8678 ixgbe_sysfs_exit(adapter); 8679 #endif /* CONFIG_IXGBE_HWMON */ 8680 8681 /* remove the added san mac */ 8682 ixgbe_del_sanmac_netdev(netdev); 8683 8684 if (netdev->reg_state == NETREG_REGISTERED) 8685 unregister_netdev(netdev); 8686 8687 #ifdef CONFIG_PCI_IOV 8688 /* 8689 * Only disable SR-IOV on unload if the user specified the now 8690 * deprecated max_vfs module parameter. 8691 */ 8692 if (max_vfs) 8693 ixgbe_disable_sriov(adapter); 8694 #endif 8695 ixgbe_clear_interrupt_scheme(adapter); 8696 8697 ixgbe_release_hw_control(adapter); 8698 8699 #ifdef CONFIG_DCB 8700 kfree(adapter->ixgbe_ieee_pfc); 8701 kfree(adapter->ixgbe_ieee_ets); 8702 8703 #endif 8704 iounmap(adapter->io_addr); 8705 pci_release_selected_regions(pdev, pci_select_bars(pdev, 8706 IORESOURCE_MEM)); 8707 8708 e_dev_info("complete\n"); 8709 8710 kfree(adapter->mac_table); 8711 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8712 free_netdev(netdev); 8713 8714 pci_disable_pcie_error_reporting(pdev); 8715 8716 if (disable_dev) 8717 pci_disable_device(pdev); 8718 } 8719 8720 /** 8721 * ixgbe_io_error_detected - called when PCI error is detected 8722 * @pdev: Pointer to PCI device 8723 * @state: The current pci connection state 8724 * 8725 * This function is called after a PCI bus error affecting 8726 * this device has been detected. 8727 */ 8728 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 8729 pci_channel_state_t state) 8730 { 8731 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8732 struct net_device *netdev = adapter->netdev; 8733 8734 #ifdef CONFIG_PCI_IOV 8735 struct ixgbe_hw *hw = &adapter->hw; 8736 struct pci_dev *bdev, *vfdev; 8737 u32 dw0, dw1, dw2, dw3; 8738 int vf, pos; 8739 u16 req_id, pf_func; 8740 8741 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 8742 adapter->num_vfs == 0) 8743 goto skip_bad_vf_detection; 8744 8745 bdev = pdev->bus->self; 8746 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 8747 bdev = bdev->bus->self; 8748 8749 if (!bdev) 8750 goto skip_bad_vf_detection; 8751 8752 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 8753 if (!pos) 8754 goto skip_bad_vf_detection; 8755 8756 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 8757 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 8758 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 8759 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 8760 if (ixgbe_removed(hw->hw_addr)) 8761 goto skip_bad_vf_detection; 8762 8763 req_id = dw1 >> 16; 8764 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 8765 if (!(req_id & 0x0080)) 8766 goto skip_bad_vf_detection; 8767 8768 pf_func = req_id & 0x01; 8769 if ((pf_func & 1) == (pdev->devfn & 1)) { 8770 unsigned int device_id; 8771 8772 vf = (req_id & 0x7F) >> 1; 8773 e_dev_err("VF %d has caused a PCIe error\n", vf); 8774 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 8775 "%8.8x\tdw3: %8.8x\n", 8776 dw0, dw1, dw2, dw3); 8777 switch (adapter->hw.mac.type) { 8778 case ixgbe_mac_82599EB: 8779 device_id = IXGBE_82599_VF_DEVICE_ID; 8780 break; 8781 case ixgbe_mac_X540: 8782 device_id = IXGBE_X540_VF_DEVICE_ID; 8783 break; 8784 case ixgbe_mac_X550: 8785 device_id = IXGBE_DEV_ID_X550_VF; 8786 break; 8787 case ixgbe_mac_X550EM_x: 8788 device_id = IXGBE_DEV_ID_X550EM_X_VF; 8789 break; 8790 default: 8791 device_id = 0; 8792 break; 8793 } 8794 8795 /* Find the pci device of the offending VF */ 8796 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 8797 while (vfdev) { 8798 if (vfdev->devfn == (req_id & 0xFF)) 8799 break; 8800 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 8801 device_id, vfdev); 8802 } 8803 /* 8804 * There's a slim chance the VF could have been hot plugged, 8805 * so if it is no longer present we don't need to issue the 8806 * VFLR. Just clean up the AER in that case. 8807 */ 8808 if (vfdev) { 8809 ixgbe_issue_vf_flr(adapter, vfdev); 8810 /* Free device reference count */ 8811 pci_dev_put(vfdev); 8812 } 8813 8814 pci_cleanup_aer_uncorrect_error_status(pdev); 8815 } 8816 8817 /* 8818 * Even though the error may have occurred on the other port 8819 * we still need to increment the vf error reference count for 8820 * both ports because the I/O resume function will be called 8821 * for both of them. 8822 */ 8823 adapter->vferr_refcount++; 8824 8825 return PCI_ERS_RESULT_RECOVERED; 8826 8827 skip_bad_vf_detection: 8828 #endif /* CONFIG_PCI_IOV */ 8829 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 8830 return PCI_ERS_RESULT_DISCONNECT; 8831 8832 rtnl_lock(); 8833 netif_device_detach(netdev); 8834 8835 if (state == pci_channel_io_perm_failure) { 8836 rtnl_unlock(); 8837 return PCI_ERS_RESULT_DISCONNECT; 8838 } 8839 8840 if (netif_running(netdev)) 8841 ixgbe_down(adapter); 8842 8843 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 8844 pci_disable_device(pdev); 8845 rtnl_unlock(); 8846 8847 /* Request a slot reset. */ 8848 return PCI_ERS_RESULT_NEED_RESET; 8849 } 8850 8851 /** 8852 * ixgbe_io_slot_reset - called after the pci bus has been reset. 8853 * @pdev: Pointer to PCI device 8854 * 8855 * Restart the card from scratch, as if from a cold-boot. 8856 */ 8857 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 8858 { 8859 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8860 pci_ers_result_t result; 8861 int err; 8862 8863 if (pci_enable_device_mem(pdev)) { 8864 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 8865 result = PCI_ERS_RESULT_DISCONNECT; 8866 } else { 8867 smp_mb__before_atomic(); 8868 clear_bit(__IXGBE_DISABLED, &adapter->state); 8869 adapter->hw.hw_addr = adapter->io_addr; 8870 pci_set_master(pdev); 8871 pci_restore_state(pdev); 8872 pci_save_state(pdev); 8873 8874 pci_wake_from_d3(pdev, false); 8875 8876 ixgbe_reset(adapter); 8877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8878 result = PCI_ERS_RESULT_RECOVERED; 8879 } 8880 8881 err = pci_cleanup_aer_uncorrect_error_status(pdev); 8882 if (err) { 8883 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 8884 "failed 0x%0x\n", err); 8885 /* non-fatal, continue */ 8886 } 8887 8888 return result; 8889 } 8890 8891 /** 8892 * ixgbe_io_resume - called when traffic can start flowing again. 8893 * @pdev: Pointer to PCI device 8894 * 8895 * This callback is called when the error recovery driver tells us that 8896 * its OK to resume normal operation. 8897 */ 8898 static void ixgbe_io_resume(struct pci_dev *pdev) 8899 { 8900 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 8901 struct net_device *netdev = adapter->netdev; 8902 8903 #ifdef CONFIG_PCI_IOV 8904 if (adapter->vferr_refcount) { 8905 e_info(drv, "Resuming after VF err\n"); 8906 adapter->vferr_refcount--; 8907 return; 8908 } 8909 8910 #endif 8911 if (netif_running(netdev)) 8912 ixgbe_up(adapter); 8913 8914 netif_device_attach(netdev); 8915 } 8916 8917 static const struct pci_error_handlers ixgbe_err_handler = { 8918 .error_detected = ixgbe_io_error_detected, 8919 .slot_reset = ixgbe_io_slot_reset, 8920 .resume = ixgbe_io_resume, 8921 }; 8922 8923 static struct pci_driver ixgbe_driver = { 8924 .name = ixgbe_driver_name, 8925 .id_table = ixgbe_pci_tbl, 8926 .probe = ixgbe_probe, 8927 .remove = ixgbe_remove, 8928 #ifdef CONFIG_PM 8929 .suspend = ixgbe_suspend, 8930 .resume = ixgbe_resume, 8931 #endif 8932 .shutdown = ixgbe_shutdown, 8933 .sriov_configure = ixgbe_pci_sriov_configure, 8934 .err_handler = &ixgbe_err_handler 8935 }; 8936 8937 /** 8938 * ixgbe_init_module - Driver Registration Routine 8939 * 8940 * ixgbe_init_module is the first routine called when the driver is 8941 * loaded. All it does is register with the PCI subsystem. 8942 **/ 8943 static int __init ixgbe_init_module(void) 8944 { 8945 int ret; 8946 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 8947 pr_info("%s\n", ixgbe_copyright); 8948 8949 ixgbe_dbg_init(); 8950 8951 ret = pci_register_driver(&ixgbe_driver); 8952 if (ret) { 8953 ixgbe_dbg_exit(); 8954 return ret; 8955 } 8956 8957 #ifdef CONFIG_IXGBE_DCA 8958 dca_register_notify(&dca_notifier); 8959 #endif 8960 8961 return 0; 8962 } 8963 8964 module_init(ixgbe_init_module); 8965 8966 /** 8967 * ixgbe_exit_module - Driver Exit Cleanup Routine 8968 * 8969 * ixgbe_exit_module is called just before the driver is removed 8970 * from memory. 8971 **/ 8972 static void __exit ixgbe_exit_module(void) 8973 { 8974 #ifdef CONFIG_IXGBE_DCA 8975 dca_unregister_notify(&dca_notifier); 8976 #endif 8977 pci_unregister_driver(&ixgbe_driver); 8978 8979 ixgbe_dbg_exit(); 8980 8981 rcu_barrier(); /* Wait for completion of call_rcu()'s */ 8982 } 8983 8984 #ifdef CONFIG_IXGBE_DCA 8985 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 8986 void *p) 8987 { 8988 int ret_val; 8989 8990 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 8991 __ixgbe_notify_dca); 8992 8993 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 8994 } 8995 8996 #endif /* CONFIG_IXGBE_DCA */ 8997 8998 module_exit(ixgbe_exit_module); 8999 9000 /* ixgbe_main.c */ 9001