1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/ip.h> 13 #include <linux/tcp.h> 14 #include <linux/sctp.h> 15 #include <linux/pkt_sched.h> 16 #include <linux/ipv6.h> 17 #include <linux/slab.h> 18 #include <net/checksum.h> 19 #include <net/ip6_checksum.h> 20 #include <linux/etherdevice.h> 21 #include <linux/ethtool.h> 22 #include <linux/if.h> 23 #include <linux/if_vlan.h> 24 #include <linux/if_macvlan.h> 25 #include <linux/if_bridge.h> 26 #include <linux/prefetch.h> 27 #include <linux/bpf.h> 28 #include <linux/bpf_trace.h> 29 #include <linux/atomic.h> 30 #include <linux/numa.h> 31 #include <scsi/fc/fc_fcoe.h> 32 #include <net/udp_tunnel.h> 33 #include <net/pkt_cls.h> 34 #include <net/tc_act/tc_gact.h> 35 #include <net/tc_act/tc_mirred.h> 36 #include <net/vxlan.h> 37 #include <net/mpls.h> 38 #include <net/xdp_sock_drv.h> 39 #include <net/xfrm.h> 40 41 #include "ixgbe.h" 42 #include "ixgbe_common.h" 43 #include "ixgbe_dcb_82599.h" 44 #include "ixgbe_phy.h" 45 #include "ixgbe_sriov.h" 46 #include "ixgbe_model.h" 47 #include "ixgbe_txrx_common.h" 48 49 char ixgbe_driver_name[] = "ixgbe"; 50 static const char ixgbe_driver_string[] = 51 "Intel(R) 10 Gigabit PCI Express Network Driver"; 52 #ifdef IXGBE_FCOE 53 char ixgbe_default_device_descr[] = 54 "Intel(R) 10 Gigabit Network Connection"; 55 #else 56 static char ixgbe_default_device_descr[] = 57 "Intel(R) 10 Gigabit Network Connection"; 58 #endif 59 #define DRV_VERSION "5.1.0-k" 60 const char ixgbe_driver_version[] = DRV_VERSION; 61 static const char ixgbe_copyright[] = 62 "Copyright (c) 1999-2016 Intel Corporation."; 63 64 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 65 66 static const struct ixgbe_info *ixgbe_info_tbl[] = { 67 [board_82598] = &ixgbe_82598_info, 68 [board_82599] = &ixgbe_82599_info, 69 [board_X540] = &ixgbe_X540_info, 70 [board_X550] = &ixgbe_X550_info, 71 [board_X550EM_x] = &ixgbe_X550EM_x_info, 72 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 73 [board_x550em_a] = &ixgbe_x550em_a_info, 74 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 75 }; 76 77 /* ixgbe_pci_tbl - PCI Device ID Table 78 * 79 * Wildcard entries (PCI_ANY_ID) should come last 80 * Last entry must be all 0s 81 * 82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 83 * Class, Class Mask, private data (not used) } 84 */ 85 static const struct pci_device_id ixgbe_pci_tbl[] = { 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 133 /* required last entry */ 134 {0, } 135 }; 136 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 137 138 #ifdef CONFIG_IXGBE_DCA 139 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 140 void *p); 141 static struct notifier_block dca_notifier = { 142 .notifier_call = ixgbe_notify_dca, 143 .next = NULL, 144 .priority = 0 145 }; 146 #endif 147 148 #ifdef CONFIG_PCI_IOV 149 static unsigned int max_vfs; 150 module_param(max_vfs, uint, 0); 151 MODULE_PARM_DESC(max_vfs, 152 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 153 #endif /* CONFIG_PCI_IOV */ 154 155 static unsigned int allow_unsupported_sfp; 156 module_param(allow_unsupported_sfp, uint, 0); 157 MODULE_PARM_DESC(allow_unsupported_sfp, 158 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 159 160 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 161 static int debug = -1; 162 module_param(debug, int, 0); 163 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 164 165 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 166 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 167 MODULE_LICENSE("GPL v2"); 168 MODULE_VERSION(DRV_VERSION); 169 170 static struct workqueue_struct *ixgbe_wq; 171 172 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 173 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 174 175 static const struct net_device_ops ixgbe_netdev_ops; 176 177 static bool netif_is_ixgbe(struct net_device *dev) 178 { 179 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 180 } 181 182 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 183 u32 reg, u16 *value) 184 { 185 struct pci_dev *parent_dev; 186 struct pci_bus *parent_bus; 187 188 parent_bus = adapter->pdev->bus->parent; 189 if (!parent_bus) 190 return -1; 191 192 parent_dev = parent_bus->self; 193 if (!parent_dev) 194 return -1; 195 196 if (!pci_is_pcie(parent_dev)) 197 return -1; 198 199 pcie_capability_read_word(parent_dev, reg, value); 200 if (*value == IXGBE_FAILED_READ_CFG_WORD && 201 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 202 return -1; 203 return 0; 204 } 205 206 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 207 { 208 struct ixgbe_hw *hw = &adapter->hw; 209 u16 link_status = 0; 210 int err; 211 212 hw->bus.type = ixgbe_bus_type_pci_express; 213 214 /* Get the negotiated link width and speed from PCI config space of the 215 * parent, as this device is behind a switch 216 */ 217 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 218 219 /* assume caller will handle error case */ 220 if (err) 221 return err; 222 223 hw->bus.width = ixgbe_convert_bus_width(link_status); 224 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 225 226 return 0; 227 } 228 229 /** 230 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 231 * @hw: hw specific details 232 * 233 * This function is used by probe to determine whether a device's PCI-Express 234 * bandwidth details should be gathered from the parent bus instead of from the 235 * device. Used to ensure that various locations all have the correct device ID 236 * checks. 237 */ 238 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 239 { 240 switch (hw->device_id) { 241 case IXGBE_DEV_ID_82599_SFP_SF_QP: 242 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 243 return true; 244 default: 245 return false; 246 } 247 } 248 249 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 250 int expected_gts) 251 { 252 struct ixgbe_hw *hw = &adapter->hw; 253 struct pci_dev *pdev; 254 255 /* Some devices are not connected over PCIe and thus do not negotiate 256 * speed. These devices do not have valid bus info, and thus any report 257 * we generate may not be correct. 258 */ 259 if (hw->bus.type == ixgbe_bus_type_internal) 260 return; 261 262 /* determine whether to use the parent device */ 263 if (ixgbe_pcie_from_parent(&adapter->hw)) 264 pdev = adapter->pdev->bus->parent->self; 265 else 266 pdev = adapter->pdev; 267 268 pcie_print_link_status(pdev); 269 } 270 271 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 272 { 273 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 274 !test_bit(__IXGBE_REMOVING, &adapter->state) && 275 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 276 queue_work(ixgbe_wq, &adapter->service_task); 277 } 278 279 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 280 { 281 struct ixgbe_adapter *adapter = hw->back; 282 283 if (!hw->hw_addr) 284 return; 285 hw->hw_addr = NULL; 286 e_dev_err("Adapter removed\n"); 287 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 288 ixgbe_service_event_schedule(adapter); 289 } 290 291 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 292 { 293 u8 __iomem *reg_addr; 294 u32 value; 295 int i; 296 297 reg_addr = READ_ONCE(hw->hw_addr); 298 if (ixgbe_removed(reg_addr)) 299 return IXGBE_FAILED_READ_REG; 300 301 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 302 * so perform several status register reads to determine if the adapter 303 * has been removed. 304 */ 305 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 306 value = readl(reg_addr + IXGBE_STATUS); 307 if (value != IXGBE_FAILED_READ_REG) 308 break; 309 mdelay(3); 310 } 311 312 if (value == IXGBE_FAILED_READ_REG) 313 ixgbe_remove_adapter(hw); 314 else 315 value = readl(reg_addr + reg); 316 return value; 317 } 318 319 /** 320 * ixgbe_read_reg - Read from device register 321 * @hw: hw specific details 322 * @reg: offset of register to read 323 * 324 * Returns : value read or IXGBE_FAILED_READ_REG if removed 325 * 326 * This function is used to read device registers. It checks for device 327 * removal by confirming any read that returns all ones by checking the 328 * status register value for all ones. This function avoids reading from 329 * the hardware if a removal was previously detected in which case it 330 * returns IXGBE_FAILED_READ_REG (all ones). 331 */ 332 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 333 { 334 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 335 u32 value; 336 337 if (ixgbe_removed(reg_addr)) 338 return IXGBE_FAILED_READ_REG; 339 if (unlikely(hw->phy.nw_mng_if_sel & 340 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 341 struct ixgbe_adapter *adapter; 342 int i; 343 344 for (i = 0; i < 200; ++i) { 345 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 346 if (likely(!value)) 347 goto writes_completed; 348 if (value == IXGBE_FAILED_READ_REG) { 349 ixgbe_remove_adapter(hw); 350 return IXGBE_FAILED_READ_REG; 351 } 352 udelay(5); 353 } 354 355 adapter = hw->back; 356 e_warn(hw, "register writes incomplete %08x\n", value); 357 } 358 359 writes_completed: 360 value = readl(reg_addr + reg); 361 if (unlikely(value == IXGBE_FAILED_READ_REG)) 362 value = ixgbe_check_remove(hw, reg); 363 return value; 364 } 365 366 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 367 { 368 u16 value; 369 370 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 371 if (value == IXGBE_FAILED_READ_CFG_WORD) { 372 ixgbe_remove_adapter(hw); 373 return true; 374 } 375 return false; 376 } 377 378 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 379 { 380 struct ixgbe_adapter *adapter = hw->back; 381 u16 value; 382 383 if (ixgbe_removed(hw->hw_addr)) 384 return IXGBE_FAILED_READ_CFG_WORD; 385 pci_read_config_word(adapter->pdev, reg, &value); 386 if (value == IXGBE_FAILED_READ_CFG_WORD && 387 ixgbe_check_cfg_remove(hw, adapter->pdev)) 388 return IXGBE_FAILED_READ_CFG_WORD; 389 return value; 390 } 391 392 #ifdef CONFIG_PCI_IOV 393 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 394 { 395 struct ixgbe_adapter *adapter = hw->back; 396 u32 value; 397 398 if (ixgbe_removed(hw->hw_addr)) 399 return IXGBE_FAILED_READ_CFG_DWORD; 400 pci_read_config_dword(adapter->pdev, reg, &value); 401 if (value == IXGBE_FAILED_READ_CFG_DWORD && 402 ixgbe_check_cfg_remove(hw, adapter->pdev)) 403 return IXGBE_FAILED_READ_CFG_DWORD; 404 return value; 405 } 406 #endif /* CONFIG_PCI_IOV */ 407 408 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 409 { 410 struct ixgbe_adapter *adapter = hw->back; 411 412 if (ixgbe_removed(hw->hw_addr)) 413 return; 414 pci_write_config_word(adapter->pdev, reg, value); 415 } 416 417 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 418 { 419 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 420 421 /* flush memory to make sure state is correct before next watchdog */ 422 smp_mb__before_atomic(); 423 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 424 } 425 426 struct ixgbe_reg_info { 427 u32 ofs; 428 char *name; 429 }; 430 431 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 432 433 /* General Registers */ 434 {IXGBE_CTRL, "CTRL"}, 435 {IXGBE_STATUS, "STATUS"}, 436 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 437 438 /* Interrupt Registers */ 439 {IXGBE_EICR, "EICR"}, 440 441 /* RX Registers */ 442 {IXGBE_SRRCTL(0), "SRRCTL"}, 443 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 444 {IXGBE_RDLEN(0), "RDLEN"}, 445 {IXGBE_RDH(0), "RDH"}, 446 {IXGBE_RDT(0), "RDT"}, 447 {IXGBE_RXDCTL(0), "RXDCTL"}, 448 {IXGBE_RDBAL(0), "RDBAL"}, 449 {IXGBE_RDBAH(0), "RDBAH"}, 450 451 /* TX Registers */ 452 {IXGBE_TDBAL(0), "TDBAL"}, 453 {IXGBE_TDBAH(0), "TDBAH"}, 454 {IXGBE_TDLEN(0), "TDLEN"}, 455 {IXGBE_TDH(0), "TDH"}, 456 {IXGBE_TDT(0), "TDT"}, 457 {IXGBE_TXDCTL(0), "TXDCTL"}, 458 459 /* List Terminator */ 460 { .name = NULL } 461 }; 462 463 464 /* 465 * ixgbe_regdump - register printout routine 466 */ 467 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 468 { 469 int i; 470 char rname[16]; 471 u32 regs[64]; 472 473 switch (reginfo->ofs) { 474 case IXGBE_SRRCTL(0): 475 for (i = 0; i < 64; i++) 476 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 477 break; 478 case IXGBE_DCA_RXCTRL(0): 479 for (i = 0; i < 64; i++) 480 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 481 break; 482 case IXGBE_RDLEN(0): 483 for (i = 0; i < 64; i++) 484 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 485 break; 486 case IXGBE_RDH(0): 487 for (i = 0; i < 64; i++) 488 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 489 break; 490 case IXGBE_RDT(0): 491 for (i = 0; i < 64; i++) 492 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 493 break; 494 case IXGBE_RXDCTL(0): 495 for (i = 0; i < 64; i++) 496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 497 break; 498 case IXGBE_RDBAL(0): 499 for (i = 0; i < 64; i++) 500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 501 break; 502 case IXGBE_RDBAH(0): 503 for (i = 0; i < 64; i++) 504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 505 break; 506 case IXGBE_TDBAL(0): 507 for (i = 0; i < 64; i++) 508 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 509 break; 510 case IXGBE_TDBAH(0): 511 for (i = 0; i < 64; i++) 512 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 513 break; 514 case IXGBE_TDLEN(0): 515 for (i = 0; i < 64; i++) 516 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 517 break; 518 case IXGBE_TDH(0): 519 for (i = 0; i < 64; i++) 520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 521 break; 522 case IXGBE_TDT(0): 523 for (i = 0; i < 64; i++) 524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 525 break; 526 case IXGBE_TXDCTL(0): 527 for (i = 0; i < 64; i++) 528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 529 break; 530 default: 531 pr_info("%-15s %08x\n", 532 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 533 return; 534 } 535 536 i = 0; 537 while (i < 64) { 538 int j; 539 char buf[9 * 8 + 1]; 540 char *p = buf; 541 542 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 543 for (j = 0; j < 8; j++) 544 p += sprintf(p, " %08x", regs[i++]); 545 pr_err("%-15s%s\n", rname, buf); 546 } 547 548 } 549 550 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 551 { 552 struct ixgbe_tx_buffer *tx_buffer; 553 554 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 555 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 556 n, ring->next_to_use, ring->next_to_clean, 557 (u64)dma_unmap_addr(tx_buffer, dma), 558 dma_unmap_len(tx_buffer, len), 559 tx_buffer->next_to_watch, 560 (u64)tx_buffer->time_stamp); 561 } 562 563 /* 564 * ixgbe_dump - Print registers, tx-rings and rx-rings 565 */ 566 static void ixgbe_dump(struct ixgbe_adapter *adapter) 567 { 568 struct net_device *netdev = adapter->netdev; 569 struct ixgbe_hw *hw = &adapter->hw; 570 struct ixgbe_reg_info *reginfo; 571 int n = 0; 572 struct ixgbe_ring *ring; 573 struct ixgbe_tx_buffer *tx_buffer; 574 union ixgbe_adv_tx_desc *tx_desc; 575 struct my_u0 { u64 a; u64 b; } *u0; 576 struct ixgbe_ring *rx_ring; 577 union ixgbe_adv_rx_desc *rx_desc; 578 struct ixgbe_rx_buffer *rx_buffer_info; 579 int i = 0; 580 581 if (!netif_msg_hw(adapter)) 582 return; 583 584 /* Print netdevice Info */ 585 if (netdev) { 586 dev_info(&adapter->pdev->dev, "Net device Info\n"); 587 pr_info("Device Name state " 588 "trans_start\n"); 589 pr_info("%-15s %016lX %016lX\n", 590 netdev->name, 591 netdev->state, 592 dev_trans_start(netdev)); 593 } 594 595 /* Print Registers */ 596 dev_info(&adapter->pdev->dev, "Register Dump\n"); 597 pr_info(" Register Name Value\n"); 598 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 599 reginfo->name; reginfo++) { 600 ixgbe_regdump(hw, reginfo); 601 } 602 603 /* Print TX Ring Summary */ 604 if (!netdev || !netif_running(netdev)) 605 return; 606 607 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 608 pr_info(" %s %s %s %s\n", 609 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 610 "leng", "ntw", "timestamp"); 611 for (n = 0; n < adapter->num_tx_queues; n++) { 612 ring = adapter->tx_ring[n]; 613 ixgbe_print_buffer(ring, n); 614 } 615 616 for (n = 0; n < adapter->num_xdp_queues; n++) { 617 ring = adapter->xdp_ring[n]; 618 ixgbe_print_buffer(ring, n); 619 } 620 621 /* Print TX Rings */ 622 if (!netif_msg_tx_done(adapter)) 623 goto rx_ring_summary; 624 625 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 626 627 /* Transmit Descriptor Formats 628 * 629 * 82598 Advanced Transmit Descriptor 630 * +--------------------------------------------------------------+ 631 * 0 | Buffer Address [63:0] | 632 * +--------------------------------------------------------------+ 633 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 634 * +--------------------------------------------------------------+ 635 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 636 * 637 * 82598 Advanced Transmit Descriptor (Write-Back Format) 638 * +--------------------------------------------------------------+ 639 * 0 | RSV [63:0] | 640 * +--------------------------------------------------------------+ 641 * 8 | RSV | STA | NXTSEQ | 642 * +--------------------------------------------------------------+ 643 * 63 36 35 32 31 0 644 * 645 * 82599+ Advanced Transmit Descriptor 646 * +--------------------------------------------------------------+ 647 * 0 | Buffer Address [63:0] | 648 * +--------------------------------------------------------------+ 649 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 650 * +--------------------------------------------------------------+ 651 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 652 * 653 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 654 * +--------------------------------------------------------------+ 655 * 0 | RSV [63:0] | 656 * +--------------------------------------------------------------+ 657 * 8 | RSV | STA | RSV | 658 * +--------------------------------------------------------------+ 659 * 63 36 35 32 31 0 660 */ 661 662 for (n = 0; n < adapter->num_tx_queues; n++) { 663 ring = adapter->tx_ring[n]; 664 pr_info("------------------------------------\n"); 665 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 666 pr_info("------------------------------------\n"); 667 pr_info("%s%s %s %s %s %s\n", 668 "T [desc] [address 63:0 ] ", 669 "[PlPOIdStDDt Ln] [bi->dma ] ", 670 "leng", "ntw", "timestamp", "bi->skb"); 671 672 for (i = 0; ring->desc && (i < ring->count); i++) { 673 tx_desc = IXGBE_TX_DESC(ring, i); 674 tx_buffer = &ring->tx_buffer_info[i]; 675 u0 = (struct my_u0 *)tx_desc; 676 if (dma_unmap_len(tx_buffer, len) > 0) { 677 const char *ring_desc; 678 679 if (i == ring->next_to_use && 680 i == ring->next_to_clean) 681 ring_desc = " NTC/U"; 682 else if (i == ring->next_to_use) 683 ring_desc = " NTU"; 684 else if (i == ring->next_to_clean) 685 ring_desc = " NTC"; 686 else 687 ring_desc = ""; 688 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 689 i, 690 le64_to_cpu((__force __le64)u0->a), 691 le64_to_cpu((__force __le64)u0->b), 692 (u64)dma_unmap_addr(tx_buffer, dma), 693 dma_unmap_len(tx_buffer, len), 694 tx_buffer->next_to_watch, 695 (u64)tx_buffer->time_stamp, 696 tx_buffer->skb, 697 ring_desc); 698 699 if (netif_msg_pktdata(adapter) && 700 tx_buffer->skb) 701 print_hex_dump(KERN_INFO, "", 702 DUMP_PREFIX_ADDRESS, 16, 1, 703 tx_buffer->skb->data, 704 dma_unmap_len(tx_buffer, len), 705 true); 706 } 707 } 708 } 709 710 /* Print RX Rings Summary */ 711 rx_ring_summary: 712 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 713 pr_info("Queue [NTU] [NTC]\n"); 714 for (n = 0; n < adapter->num_rx_queues; n++) { 715 rx_ring = adapter->rx_ring[n]; 716 pr_info("%5d %5X %5X\n", 717 n, rx_ring->next_to_use, rx_ring->next_to_clean); 718 } 719 720 /* Print RX Rings */ 721 if (!netif_msg_rx_status(adapter)) 722 return; 723 724 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 725 726 /* Receive Descriptor Formats 727 * 728 * 82598 Advanced Receive Descriptor (Read) Format 729 * 63 1 0 730 * +-----------------------------------------------------+ 731 * 0 | Packet Buffer Address [63:1] |A0/NSE| 732 * +----------------------------------------------+------+ 733 * 8 | Header Buffer Address [63:1] | DD | 734 * +-----------------------------------------------------+ 735 * 736 * 737 * 82598 Advanced Receive Descriptor (Write-Back) Format 738 * 739 * 63 48 47 32 31 30 21 20 16 15 4 3 0 740 * +------------------------------------------------------+ 741 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 742 * | Packet | IP | | | | Type | Type | 743 * | Checksum | Ident | | | | | | 744 * +------------------------------------------------------+ 745 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 746 * +------------------------------------------------------+ 747 * 63 48 47 32 31 20 19 0 748 * 749 * 82599+ Advanced Receive Descriptor (Read) Format 750 * 63 1 0 751 * +-----------------------------------------------------+ 752 * 0 | Packet Buffer Address [63:1] |A0/NSE| 753 * +----------------------------------------------+------+ 754 * 8 | Header Buffer Address [63:1] | DD | 755 * +-----------------------------------------------------+ 756 * 757 * 758 * 82599+ Advanced Receive Descriptor (Write-Back) Format 759 * 760 * 63 48 47 32 31 30 21 20 17 16 4 3 0 761 * +------------------------------------------------------+ 762 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 763 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 764 * |/ Flow Dir Flt ID | | | | | | 765 * +------------------------------------------------------+ 766 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 767 * +------------------------------------------------------+ 768 * 63 48 47 32 31 20 19 0 769 */ 770 771 for (n = 0; n < adapter->num_rx_queues; n++) { 772 rx_ring = adapter->rx_ring[n]; 773 pr_info("------------------------------------\n"); 774 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 775 pr_info("------------------------------------\n"); 776 pr_info("%s%s%s\n", 777 "R [desc] [ PktBuf A0] ", 778 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 779 "<-- Adv Rx Read format"); 780 pr_info("%s%s%s\n", 781 "RWB[desc] [PcsmIpSHl PtRs] ", 782 "[vl er S cks ln] ---------------- [bi->skb ] ", 783 "<-- Adv Rx Write-Back format"); 784 785 for (i = 0; i < rx_ring->count; i++) { 786 const char *ring_desc; 787 788 if (i == rx_ring->next_to_use) 789 ring_desc = " NTU"; 790 else if (i == rx_ring->next_to_clean) 791 ring_desc = " NTC"; 792 else 793 ring_desc = ""; 794 795 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 796 rx_desc = IXGBE_RX_DESC(rx_ring, i); 797 u0 = (struct my_u0 *)rx_desc; 798 if (rx_desc->wb.upper.length) { 799 /* Descriptor Done */ 800 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 801 i, 802 le64_to_cpu((__force __le64)u0->a), 803 le64_to_cpu((__force __le64)u0->b), 804 rx_buffer_info->skb, 805 ring_desc); 806 } else { 807 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 808 i, 809 le64_to_cpu((__force __le64)u0->a), 810 le64_to_cpu((__force __le64)u0->b), 811 (u64)rx_buffer_info->dma, 812 rx_buffer_info->skb, 813 ring_desc); 814 815 if (netif_msg_pktdata(adapter) && 816 rx_buffer_info->dma) { 817 print_hex_dump(KERN_INFO, "", 818 DUMP_PREFIX_ADDRESS, 16, 1, 819 page_address(rx_buffer_info->page) + 820 rx_buffer_info->page_offset, 821 ixgbe_rx_bufsz(rx_ring), true); 822 } 823 } 824 } 825 } 826 } 827 828 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 829 { 830 u32 ctrl_ext; 831 832 /* Let firmware take over control of h/w */ 833 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 834 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 835 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 836 } 837 838 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 839 { 840 u32 ctrl_ext; 841 842 /* Let firmware know the driver has taken over */ 843 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 845 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 846 } 847 848 /** 849 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 850 * @adapter: pointer to adapter struct 851 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 852 * @queue: queue to map the corresponding interrupt to 853 * @msix_vector: the vector to map to the corresponding queue 854 * 855 */ 856 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 857 u8 queue, u8 msix_vector) 858 { 859 u32 ivar, index; 860 struct ixgbe_hw *hw = &adapter->hw; 861 switch (hw->mac.type) { 862 case ixgbe_mac_82598EB: 863 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 864 if (direction == -1) 865 direction = 0; 866 index = (((direction * 64) + queue) >> 2) & 0x1F; 867 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 868 ivar &= ~(0xFF << (8 * (queue & 0x3))); 869 ivar |= (msix_vector << (8 * (queue & 0x3))); 870 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 871 break; 872 case ixgbe_mac_82599EB: 873 case ixgbe_mac_X540: 874 case ixgbe_mac_X550: 875 case ixgbe_mac_X550EM_x: 876 case ixgbe_mac_x550em_a: 877 if (direction == -1) { 878 /* other causes */ 879 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 880 index = ((queue & 1) * 8); 881 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 882 ivar &= ~(0xFF << index); 883 ivar |= (msix_vector << index); 884 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 885 break; 886 } else { 887 /* tx or rx causes */ 888 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 889 index = ((16 * (queue & 1)) + (8 * direction)); 890 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 891 ivar &= ~(0xFF << index); 892 ivar |= (msix_vector << index); 893 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 894 break; 895 } 896 default: 897 break; 898 } 899 } 900 901 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 902 u64 qmask) 903 { 904 u32 mask; 905 906 switch (adapter->hw.mac.type) { 907 case ixgbe_mac_82598EB: 908 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 910 break; 911 case ixgbe_mac_82599EB: 912 case ixgbe_mac_X540: 913 case ixgbe_mac_X550: 914 case ixgbe_mac_X550EM_x: 915 case ixgbe_mac_x550em_a: 916 mask = (qmask & 0xFFFFFFFF); 917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 918 mask = (qmask >> 32); 919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 920 break; 921 default: 922 break; 923 } 924 } 925 926 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 927 { 928 struct ixgbe_hw *hw = &adapter->hw; 929 struct ixgbe_hw_stats *hwstats = &adapter->stats; 930 int i; 931 u32 data; 932 933 if ((hw->fc.current_mode != ixgbe_fc_full) && 934 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 935 return; 936 937 switch (hw->mac.type) { 938 case ixgbe_mac_82598EB: 939 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 940 break; 941 default: 942 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 943 } 944 hwstats->lxoffrxc += data; 945 946 /* refill credits (no tx hang) if we received xoff */ 947 if (!data) 948 return; 949 950 for (i = 0; i < adapter->num_tx_queues; i++) 951 clear_bit(__IXGBE_HANG_CHECK_ARMED, 952 &adapter->tx_ring[i]->state); 953 954 for (i = 0; i < adapter->num_xdp_queues; i++) 955 clear_bit(__IXGBE_HANG_CHECK_ARMED, 956 &adapter->xdp_ring[i]->state); 957 } 958 959 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 960 { 961 struct ixgbe_hw *hw = &adapter->hw; 962 struct ixgbe_hw_stats *hwstats = &adapter->stats; 963 u32 xoff[8] = {0}; 964 u8 tc; 965 int i; 966 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 967 968 if (adapter->ixgbe_ieee_pfc) 969 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 970 971 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 972 ixgbe_update_xoff_rx_lfc(adapter); 973 return; 974 } 975 976 /* update stats for each tc, only valid with PFC enabled */ 977 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 978 u32 pxoffrxc; 979 980 switch (hw->mac.type) { 981 case ixgbe_mac_82598EB: 982 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 983 break; 984 default: 985 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 986 } 987 hwstats->pxoffrxc[i] += pxoffrxc; 988 /* Get the TC for given UP */ 989 tc = netdev_get_prio_tc_map(adapter->netdev, i); 990 xoff[tc] += pxoffrxc; 991 } 992 993 /* disarm tx queues that have received xoff frames */ 994 for (i = 0; i < adapter->num_tx_queues; i++) { 995 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 996 997 tc = tx_ring->dcb_tc; 998 if (xoff[tc]) 999 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1000 } 1001 1002 for (i = 0; i < adapter->num_xdp_queues; i++) { 1003 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1004 1005 tc = xdp_ring->dcb_tc; 1006 if (xoff[tc]) 1007 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1008 } 1009 } 1010 1011 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1012 { 1013 return ring->stats.packets; 1014 } 1015 1016 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1017 { 1018 unsigned int head, tail; 1019 1020 head = ring->next_to_clean; 1021 tail = ring->next_to_use; 1022 1023 return ((head <= tail) ? tail : tail + ring->count) - head; 1024 } 1025 1026 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1027 { 1028 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1029 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1030 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1031 1032 clear_check_for_tx_hang(tx_ring); 1033 1034 /* 1035 * Check for a hung queue, but be thorough. This verifies 1036 * that a transmit has been completed since the previous 1037 * check AND there is at least one packet pending. The 1038 * ARMED bit is set to indicate a potential hang. The 1039 * bit is cleared if a pause frame is received to remove 1040 * false hang detection due to PFC or 802.3x frames. By 1041 * requiring this to fail twice we avoid races with 1042 * pfc clearing the ARMED bit and conditions where we 1043 * run the check_tx_hang logic with a transmit completion 1044 * pending but without time to complete it yet. 1045 */ 1046 if (tx_done_old == tx_done && tx_pending) 1047 /* make sure it is true for two checks in a row */ 1048 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1049 &tx_ring->state); 1050 /* update completed stats and continue */ 1051 tx_ring->tx_stats.tx_done_old = tx_done; 1052 /* reset the countdown */ 1053 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1054 1055 return false; 1056 } 1057 1058 /** 1059 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1060 * @adapter: driver private struct 1061 **/ 1062 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1063 { 1064 1065 /* Do the reset outside of interrupt context */ 1066 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1067 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1068 e_warn(drv, "initiating reset due to tx timeout\n"); 1069 ixgbe_service_event_schedule(adapter); 1070 } 1071 } 1072 1073 /** 1074 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1075 * @netdev: network interface device structure 1076 * @queue_index: Tx queue to set 1077 * @maxrate: desired maximum transmit bitrate 1078 **/ 1079 static int ixgbe_tx_maxrate(struct net_device *netdev, 1080 int queue_index, u32 maxrate) 1081 { 1082 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1083 struct ixgbe_hw *hw = &adapter->hw; 1084 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1085 1086 if (!maxrate) 1087 return 0; 1088 1089 /* Calculate the rate factor values to set */ 1090 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1091 bcnrc_val /= maxrate; 1092 1093 /* clear everything but the rate factor */ 1094 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1095 IXGBE_RTTBCNRC_RF_DEC_MASK; 1096 1097 /* enable the rate scheduler */ 1098 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1099 1100 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1101 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1102 1103 return 0; 1104 } 1105 1106 /** 1107 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1108 * @q_vector: structure containing interrupt and ring information 1109 * @tx_ring: tx ring to clean 1110 * @napi_budget: Used to determine if we are in netpoll 1111 **/ 1112 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1113 struct ixgbe_ring *tx_ring, int napi_budget) 1114 { 1115 struct ixgbe_adapter *adapter = q_vector->adapter; 1116 struct ixgbe_tx_buffer *tx_buffer; 1117 union ixgbe_adv_tx_desc *tx_desc; 1118 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1119 unsigned int budget = q_vector->tx.work_limit; 1120 unsigned int i = tx_ring->next_to_clean; 1121 1122 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1123 return true; 1124 1125 tx_buffer = &tx_ring->tx_buffer_info[i]; 1126 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1127 i -= tx_ring->count; 1128 1129 do { 1130 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1131 1132 /* if next_to_watch is not set then there is no work pending */ 1133 if (!eop_desc) 1134 break; 1135 1136 /* prevent any other reads prior to eop_desc */ 1137 smp_rmb(); 1138 1139 /* if DD is not set pending work has not been completed */ 1140 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1141 break; 1142 1143 /* clear next_to_watch to prevent false hangs */ 1144 tx_buffer->next_to_watch = NULL; 1145 1146 /* update the statistics for this packet */ 1147 total_bytes += tx_buffer->bytecount; 1148 total_packets += tx_buffer->gso_segs; 1149 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1150 total_ipsec++; 1151 1152 /* free the skb */ 1153 if (ring_is_xdp(tx_ring)) 1154 xdp_return_frame(tx_buffer->xdpf); 1155 else 1156 napi_consume_skb(tx_buffer->skb, napi_budget); 1157 1158 /* unmap skb header data */ 1159 dma_unmap_single(tx_ring->dev, 1160 dma_unmap_addr(tx_buffer, dma), 1161 dma_unmap_len(tx_buffer, len), 1162 DMA_TO_DEVICE); 1163 1164 /* clear tx_buffer data */ 1165 dma_unmap_len_set(tx_buffer, len, 0); 1166 1167 /* unmap remaining buffers */ 1168 while (tx_desc != eop_desc) { 1169 tx_buffer++; 1170 tx_desc++; 1171 i++; 1172 if (unlikely(!i)) { 1173 i -= tx_ring->count; 1174 tx_buffer = tx_ring->tx_buffer_info; 1175 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1176 } 1177 1178 /* unmap any remaining paged data */ 1179 if (dma_unmap_len(tx_buffer, len)) { 1180 dma_unmap_page(tx_ring->dev, 1181 dma_unmap_addr(tx_buffer, dma), 1182 dma_unmap_len(tx_buffer, len), 1183 DMA_TO_DEVICE); 1184 dma_unmap_len_set(tx_buffer, len, 0); 1185 } 1186 } 1187 1188 /* move us one more past the eop_desc for start of next pkt */ 1189 tx_buffer++; 1190 tx_desc++; 1191 i++; 1192 if (unlikely(!i)) { 1193 i -= tx_ring->count; 1194 tx_buffer = tx_ring->tx_buffer_info; 1195 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1196 } 1197 1198 /* issue prefetch for next Tx descriptor */ 1199 prefetch(tx_desc); 1200 1201 /* update budget accounting */ 1202 budget--; 1203 } while (likely(budget)); 1204 1205 i += tx_ring->count; 1206 tx_ring->next_to_clean = i; 1207 u64_stats_update_begin(&tx_ring->syncp); 1208 tx_ring->stats.bytes += total_bytes; 1209 tx_ring->stats.packets += total_packets; 1210 u64_stats_update_end(&tx_ring->syncp); 1211 q_vector->tx.total_bytes += total_bytes; 1212 q_vector->tx.total_packets += total_packets; 1213 adapter->tx_ipsec += total_ipsec; 1214 1215 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1216 /* schedule immediate reset if we believe we hung */ 1217 struct ixgbe_hw *hw = &adapter->hw; 1218 e_err(drv, "Detected Tx Unit Hang %s\n" 1219 " Tx Queue <%d>\n" 1220 " TDH, TDT <%x>, <%x>\n" 1221 " next_to_use <%x>\n" 1222 " next_to_clean <%x>\n" 1223 "tx_buffer_info[next_to_clean]\n" 1224 " time_stamp <%lx>\n" 1225 " jiffies <%lx>\n", 1226 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1227 tx_ring->queue_index, 1228 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1229 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1230 tx_ring->next_to_use, i, 1231 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1232 1233 if (!ring_is_xdp(tx_ring)) 1234 netif_stop_subqueue(tx_ring->netdev, 1235 tx_ring->queue_index); 1236 1237 e_info(probe, 1238 "tx hang %d detected on queue %d, resetting adapter\n", 1239 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1240 1241 /* schedule immediate reset if we believe we hung */ 1242 ixgbe_tx_timeout_reset(adapter); 1243 1244 /* the adapter is about to reset, no point in enabling stuff */ 1245 return true; 1246 } 1247 1248 if (ring_is_xdp(tx_ring)) 1249 return !!budget; 1250 1251 netdev_tx_completed_queue(txring_txq(tx_ring), 1252 total_packets, total_bytes); 1253 1254 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1255 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1256 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1257 /* Make sure that anybody stopping the queue after this 1258 * sees the new next_to_clean. 1259 */ 1260 smp_mb(); 1261 if (__netif_subqueue_stopped(tx_ring->netdev, 1262 tx_ring->queue_index) 1263 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1264 netif_wake_subqueue(tx_ring->netdev, 1265 tx_ring->queue_index); 1266 ++tx_ring->tx_stats.restart_queue; 1267 } 1268 } 1269 1270 return !!budget; 1271 } 1272 1273 #ifdef CONFIG_IXGBE_DCA 1274 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1275 struct ixgbe_ring *tx_ring, 1276 int cpu) 1277 { 1278 struct ixgbe_hw *hw = &adapter->hw; 1279 u32 txctrl = 0; 1280 u16 reg_offset; 1281 1282 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1283 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1284 1285 switch (hw->mac.type) { 1286 case ixgbe_mac_82598EB: 1287 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1288 break; 1289 case ixgbe_mac_82599EB: 1290 case ixgbe_mac_X540: 1291 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1292 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1293 break; 1294 default: 1295 /* for unknown hardware do not write register */ 1296 return; 1297 } 1298 1299 /* 1300 * We can enable relaxed ordering for reads, but not writes when 1301 * DCA is enabled. This is due to a known issue in some chipsets 1302 * which will cause the DCA tag to be cleared. 1303 */ 1304 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1305 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1306 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1307 1308 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1309 } 1310 1311 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1312 struct ixgbe_ring *rx_ring, 1313 int cpu) 1314 { 1315 struct ixgbe_hw *hw = &adapter->hw; 1316 u32 rxctrl = 0; 1317 u8 reg_idx = rx_ring->reg_idx; 1318 1319 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1320 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1321 1322 switch (hw->mac.type) { 1323 case ixgbe_mac_82599EB: 1324 case ixgbe_mac_X540: 1325 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1326 break; 1327 default: 1328 break; 1329 } 1330 1331 /* 1332 * We can enable relaxed ordering for reads, but not writes when 1333 * DCA is enabled. This is due to a known issue in some chipsets 1334 * which will cause the DCA tag to be cleared. 1335 */ 1336 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1337 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1338 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1339 1340 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1341 } 1342 1343 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1344 { 1345 struct ixgbe_adapter *adapter = q_vector->adapter; 1346 struct ixgbe_ring *ring; 1347 int cpu = get_cpu(); 1348 1349 if (q_vector->cpu == cpu) 1350 goto out_no_update; 1351 1352 ixgbe_for_each_ring(ring, q_vector->tx) 1353 ixgbe_update_tx_dca(adapter, ring, cpu); 1354 1355 ixgbe_for_each_ring(ring, q_vector->rx) 1356 ixgbe_update_rx_dca(adapter, ring, cpu); 1357 1358 q_vector->cpu = cpu; 1359 out_no_update: 1360 put_cpu(); 1361 } 1362 1363 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1364 { 1365 int i; 1366 1367 /* always use CB2 mode, difference is masked in the CB driver */ 1368 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1369 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1370 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1371 else 1372 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1373 IXGBE_DCA_CTRL_DCA_DISABLE); 1374 1375 for (i = 0; i < adapter->num_q_vectors; i++) { 1376 adapter->q_vector[i]->cpu = -1; 1377 ixgbe_update_dca(adapter->q_vector[i]); 1378 } 1379 } 1380 1381 static int __ixgbe_notify_dca(struct device *dev, void *data) 1382 { 1383 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1384 unsigned long event = *(unsigned long *)data; 1385 1386 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1387 return 0; 1388 1389 switch (event) { 1390 case DCA_PROVIDER_ADD: 1391 /* if we're already enabled, don't do it again */ 1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1393 break; 1394 if (dca_add_requester(dev) == 0) { 1395 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1397 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1398 break; 1399 } 1400 /* fall through - DCA is disabled. */ 1401 case DCA_PROVIDER_REMOVE: 1402 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1403 dca_remove_requester(dev); 1404 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1405 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1406 IXGBE_DCA_CTRL_DCA_DISABLE); 1407 } 1408 break; 1409 } 1410 1411 return 0; 1412 } 1413 1414 #endif /* CONFIG_IXGBE_DCA */ 1415 1416 #define IXGBE_RSS_L4_TYPES_MASK \ 1417 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1418 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1419 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1420 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1421 1422 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1423 union ixgbe_adv_rx_desc *rx_desc, 1424 struct sk_buff *skb) 1425 { 1426 u16 rss_type; 1427 1428 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1429 return; 1430 1431 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1432 IXGBE_RXDADV_RSSTYPE_MASK; 1433 1434 if (!rss_type) 1435 return; 1436 1437 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1438 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1439 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1440 } 1441 1442 #ifdef IXGBE_FCOE 1443 /** 1444 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1445 * @ring: structure containing ring specific data 1446 * @rx_desc: advanced rx descriptor 1447 * 1448 * Returns : true if it is FCoE pkt 1449 */ 1450 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1451 union ixgbe_adv_rx_desc *rx_desc) 1452 { 1453 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1454 1455 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1456 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1457 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1458 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1459 } 1460 1461 #endif /* IXGBE_FCOE */ 1462 /** 1463 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1464 * @ring: structure containing ring specific data 1465 * @rx_desc: current Rx descriptor being processed 1466 * @skb: skb currently being received and modified 1467 **/ 1468 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1469 union ixgbe_adv_rx_desc *rx_desc, 1470 struct sk_buff *skb) 1471 { 1472 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1473 bool encap_pkt = false; 1474 1475 skb_checksum_none_assert(skb); 1476 1477 /* Rx csum disabled */ 1478 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1479 return; 1480 1481 /* check for VXLAN and Geneve packets */ 1482 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1483 encap_pkt = true; 1484 skb->encapsulation = 1; 1485 } 1486 1487 /* if IP and error */ 1488 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1489 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1490 ring->rx_stats.csum_err++; 1491 return; 1492 } 1493 1494 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1495 return; 1496 1497 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1498 /* 1499 * 82599 errata, UDP frames with a 0 checksum can be marked as 1500 * checksum errors. 1501 */ 1502 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1503 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1504 return; 1505 1506 ring->rx_stats.csum_err++; 1507 return; 1508 } 1509 1510 /* It must be a TCP or UDP packet with a valid checksum */ 1511 skb->ip_summed = CHECKSUM_UNNECESSARY; 1512 if (encap_pkt) { 1513 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1514 return; 1515 1516 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1517 skb->ip_summed = CHECKSUM_NONE; 1518 return; 1519 } 1520 /* If we checked the outer header let the stack know */ 1521 skb->csum_level = 1; 1522 } 1523 } 1524 1525 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1526 { 1527 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1528 } 1529 1530 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1531 struct ixgbe_rx_buffer *bi) 1532 { 1533 struct page *page = bi->page; 1534 dma_addr_t dma; 1535 1536 /* since we are recycling buffers we should seldom need to alloc */ 1537 if (likely(page)) 1538 return true; 1539 1540 /* alloc new page for storage */ 1541 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1542 if (unlikely(!page)) { 1543 rx_ring->rx_stats.alloc_rx_page_failed++; 1544 return false; 1545 } 1546 1547 /* map page for use */ 1548 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1549 ixgbe_rx_pg_size(rx_ring), 1550 DMA_FROM_DEVICE, 1551 IXGBE_RX_DMA_ATTR); 1552 1553 /* 1554 * if mapping failed free memory back to system since 1555 * there isn't much point in holding memory we can't use 1556 */ 1557 if (dma_mapping_error(rx_ring->dev, dma)) { 1558 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1559 1560 rx_ring->rx_stats.alloc_rx_page_failed++; 1561 return false; 1562 } 1563 1564 bi->dma = dma; 1565 bi->page = page; 1566 bi->page_offset = ixgbe_rx_offset(rx_ring); 1567 page_ref_add(page, USHRT_MAX - 1); 1568 bi->pagecnt_bias = USHRT_MAX; 1569 rx_ring->rx_stats.alloc_rx_page++; 1570 1571 return true; 1572 } 1573 1574 /** 1575 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1576 * @rx_ring: ring to place buffers on 1577 * @cleaned_count: number of buffers to replace 1578 **/ 1579 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1580 { 1581 union ixgbe_adv_rx_desc *rx_desc; 1582 struct ixgbe_rx_buffer *bi; 1583 u16 i = rx_ring->next_to_use; 1584 u16 bufsz; 1585 1586 /* nothing to do */ 1587 if (!cleaned_count) 1588 return; 1589 1590 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1591 bi = &rx_ring->rx_buffer_info[i]; 1592 i -= rx_ring->count; 1593 1594 bufsz = ixgbe_rx_bufsz(rx_ring); 1595 1596 do { 1597 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1598 break; 1599 1600 /* sync the buffer for use by the device */ 1601 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1602 bi->page_offset, bufsz, 1603 DMA_FROM_DEVICE); 1604 1605 /* 1606 * Refresh the desc even if buffer_addrs didn't change 1607 * because each write-back erases this info. 1608 */ 1609 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1610 1611 rx_desc++; 1612 bi++; 1613 i++; 1614 if (unlikely(!i)) { 1615 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1616 bi = rx_ring->rx_buffer_info; 1617 i -= rx_ring->count; 1618 } 1619 1620 /* clear the length for the next_to_use descriptor */ 1621 rx_desc->wb.upper.length = 0; 1622 1623 cleaned_count--; 1624 } while (cleaned_count); 1625 1626 i += rx_ring->count; 1627 1628 if (rx_ring->next_to_use != i) { 1629 rx_ring->next_to_use = i; 1630 1631 /* update next to alloc since we have filled the ring */ 1632 rx_ring->next_to_alloc = i; 1633 1634 /* Force memory writes to complete before letting h/w 1635 * know there are new descriptors to fetch. (Only 1636 * applicable for weak-ordered memory model archs, 1637 * such as IA-64). 1638 */ 1639 wmb(); 1640 writel(i, rx_ring->tail); 1641 } 1642 } 1643 1644 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1645 struct sk_buff *skb) 1646 { 1647 u16 hdr_len = skb_headlen(skb); 1648 1649 /* set gso_size to avoid messing up TCP MSS */ 1650 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1651 IXGBE_CB(skb)->append_cnt); 1652 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1653 } 1654 1655 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1656 struct sk_buff *skb) 1657 { 1658 /* if append_cnt is 0 then frame is not RSC */ 1659 if (!IXGBE_CB(skb)->append_cnt) 1660 return; 1661 1662 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1663 rx_ring->rx_stats.rsc_flush++; 1664 1665 ixgbe_set_rsc_gso_size(rx_ring, skb); 1666 1667 /* gso_size is computed using append_cnt so always clear it last */ 1668 IXGBE_CB(skb)->append_cnt = 0; 1669 } 1670 1671 /** 1672 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1673 * @rx_ring: rx descriptor ring packet is being transacted on 1674 * @rx_desc: pointer to the EOP Rx descriptor 1675 * @skb: pointer to current skb being populated 1676 * 1677 * This function checks the ring, descriptor, and packet information in 1678 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1679 * other fields within the skb. 1680 **/ 1681 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1682 union ixgbe_adv_rx_desc *rx_desc, 1683 struct sk_buff *skb) 1684 { 1685 struct net_device *dev = rx_ring->netdev; 1686 u32 flags = rx_ring->q_vector->adapter->flags; 1687 1688 ixgbe_update_rsc_stats(rx_ring, skb); 1689 1690 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1691 1692 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1693 1694 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1695 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1696 1697 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1698 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1699 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1700 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1701 } 1702 1703 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1704 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1705 1706 /* record Rx queue, or update MACVLAN statistics */ 1707 if (netif_is_ixgbe(dev)) 1708 skb_record_rx_queue(skb, rx_ring->queue_index); 1709 else 1710 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1711 false); 1712 1713 skb->protocol = eth_type_trans(skb, dev); 1714 } 1715 1716 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1717 struct sk_buff *skb) 1718 { 1719 napi_gro_receive(&q_vector->napi, skb); 1720 } 1721 1722 /** 1723 * ixgbe_is_non_eop - process handling of non-EOP buffers 1724 * @rx_ring: Rx ring being processed 1725 * @rx_desc: Rx descriptor for current buffer 1726 * @skb: Current socket buffer containing buffer in progress 1727 * 1728 * This function updates next to clean. If the buffer is an EOP buffer 1729 * this function exits returning false, otherwise it will place the 1730 * sk_buff in the next buffer to be chained and return true indicating 1731 * that this is in fact a non-EOP buffer. 1732 **/ 1733 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1734 union ixgbe_adv_rx_desc *rx_desc, 1735 struct sk_buff *skb) 1736 { 1737 u32 ntc = rx_ring->next_to_clean + 1; 1738 1739 /* fetch, update, and store next to clean */ 1740 ntc = (ntc < rx_ring->count) ? ntc : 0; 1741 rx_ring->next_to_clean = ntc; 1742 1743 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1744 1745 /* update RSC append count if present */ 1746 if (ring_is_rsc_enabled(rx_ring)) { 1747 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1748 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1749 1750 if (unlikely(rsc_enabled)) { 1751 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1752 1753 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1754 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1755 1756 /* update ntc based on RSC value */ 1757 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1758 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1759 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1760 } 1761 } 1762 1763 /* if we are the last buffer then there is nothing else to do */ 1764 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1765 return false; 1766 1767 /* place skb in next buffer to be received */ 1768 rx_ring->rx_buffer_info[ntc].skb = skb; 1769 rx_ring->rx_stats.non_eop_descs++; 1770 1771 return true; 1772 } 1773 1774 /** 1775 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1776 * @rx_ring: rx descriptor ring packet is being transacted on 1777 * @skb: pointer to current skb being adjusted 1778 * 1779 * This function is an ixgbe specific version of __pskb_pull_tail. The 1780 * main difference between this version and the original function is that 1781 * this function can make several assumptions about the state of things 1782 * that allow for significant optimizations versus the standard function. 1783 * As a result we can do things like drop a frag and maintain an accurate 1784 * truesize for the skb. 1785 */ 1786 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1787 struct sk_buff *skb) 1788 { 1789 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1790 unsigned char *va; 1791 unsigned int pull_len; 1792 1793 /* 1794 * it is valid to use page_address instead of kmap since we are 1795 * working with pages allocated out of the lomem pool per 1796 * alloc_page(GFP_ATOMIC) 1797 */ 1798 va = skb_frag_address(frag); 1799 1800 /* 1801 * we need the header to contain the greater of either ETH_HLEN or 1802 * 60 bytes if the skb->len is less than 60 for skb_pad. 1803 */ 1804 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1805 1806 /* align pull length to size of long to optimize memcpy performance */ 1807 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1808 1809 /* update all of the pointers */ 1810 skb_frag_size_sub(frag, pull_len); 1811 skb_frag_off_add(frag, pull_len); 1812 skb->data_len -= pull_len; 1813 skb->tail += pull_len; 1814 } 1815 1816 /** 1817 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1818 * @rx_ring: rx descriptor ring packet is being transacted on 1819 * @skb: pointer to current skb being updated 1820 * 1821 * This function provides a basic DMA sync up for the first fragment of an 1822 * skb. The reason for doing this is that the first fragment cannot be 1823 * unmapped until we have reached the end of packet descriptor for a buffer 1824 * chain. 1825 */ 1826 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1827 struct sk_buff *skb) 1828 { 1829 if (ring_uses_build_skb(rx_ring)) { 1830 unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK; 1831 1832 dma_sync_single_range_for_cpu(rx_ring->dev, 1833 IXGBE_CB(skb)->dma, 1834 offset, 1835 skb_headlen(skb), 1836 DMA_FROM_DEVICE); 1837 } else { 1838 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1839 1840 dma_sync_single_range_for_cpu(rx_ring->dev, 1841 IXGBE_CB(skb)->dma, 1842 skb_frag_off(frag), 1843 skb_frag_size(frag), 1844 DMA_FROM_DEVICE); 1845 } 1846 1847 /* If the page was released, just unmap it. */ 1848 if (unlikely(IXGBE_CB(skb)->page_released)) { 1849 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1850 ixgbe_rx_pg_size(rx_ring), 1851 DMA_FROM_DEVICE, 1852 IXGBE_RX_DMA_ATTR); 1853 } 1854 } 1855 1856 /** 1857 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1858 * @rx_ring: rx descriptor ring packet is being transacted on 1859 * @rx_desc: pointer to the EOP Rx descriptor 1860 * @skb: pointer to current skb being fixed 1861 * 1862 * Check if the skb is valid in the XDP case it will be an error pointer. 1863 * Return true in this case to abort processing and advance to next 1864 * descriptor. 1865 * 1866 * Check for corrupted packet headers caused by senders on the local L2 1867 * embedded NIC switch not setting up their Tx Descriptors right. These 1868 * should be very rare. 1869 * 1870 * Also address the case where we are pulling data in on pages only 1871 * and as such no data is present in the skb header. 1872 * 1873 * In addition if skb is not at least 60 bytes we need to pad it so that 1874 * it is large enough to qualify as a valid Ethernet frame. 1875 * 1876 * Returns true if an error was encountered and skb was freed. 1877 **/ 1878 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1879 union ixgbe_adv_rx_desc *rx_desc, 1880 struct sk_buff *skb) 1881 { 1882 struct net_device *netdev = rx_ring->netdev; 1883 1884 /* XDP packets use error pointer so abort at this point */ 1885 if (IS_ERR(skb)) 1886 return true; 1887 1888 /* Verify netdev is present, and that packet does not have any 1889 * errors that would be unacceptable to the netdev. 1890 */ 1891 if (!netdev || 1892 (unlikely(ixgbe_test_staterr(rx_desc, 1893 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1894 !(netdev->features & NETIF_F_RXALL)))) { 1895 dev_kfree_skb_any(skb); 1896 return true; 1897 } 1898 1899 /* place header in linear portion of buffer */ 1900 if (!skb_headlen(skb)) 1901 ixgbe_pull_tail(rx_ring, skb); 1902 1903 #ifdef IXGBE_FCOE 1904 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1905 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1906 return false; 1907 1908 #endif 1909 /* if eth_skb_pad returns an error the skb was freed */ 1910 if (eth_skb_pad(skb)) 1911 return true; 1912 1913 return false; 1914 } 1915 1916 /** 1917 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1918 * @rx_ring: rx descriptor ring to store buffers on 1919 * @old_buff: donor buffer to have page reused 1920 * 1921 * Synchronizes page for reuse by the adapter 1922 **/ 1923 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1924 struct ixgbe_rx_buffer *old_buff) 1925 { 1926 struct ixgbe_rx_buffer *new_buff; 1927 u16 nta = rx_ring->next_to_alloc; 1928 1929 new_buff = &rx_ring->rx_buffer_info[nta]; 1930 1931 /* update, and store next to alloc */ 1932 nta++; 1933 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1934 1935 /* Transfer page from old buffer to new buffer. 1936 * Move each member individually to avoid possible store 1937 * forwarding stalls and unnecessary copy of skb. 1938 */ 1939 new_buff->dma = old_buff->dma; 1940 new_buff->page = old_buff->page; 1941 new_buff->page_offset = old_buff->page_offset; 1942 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1943 } 1944 1945 static inline bool ixgbe_page_is_reserved(struct page *page) 1946 { 1947 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1948 } 1949 1950 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1951 { 1952 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1953 struct page *page = rx_buffer->page; 1954 1955 /* avoid re-using remote pages */ 1956 if (unlikely(ixgbe_page_is_reserved(page))) 1957 return false; 1958 1959 #if (PAGE_SIZE < 8192) 1960 /* if we are only owner of page we can reuse it */ 1961 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1962 return false; 1963 #else 1964 /* The last offset is a bit aggressive in that we assume the 1965 * worst case of FCoE being enabled and using a 3K buffer. 1966 * However this should have minimal impact as the 1K extra is 1967 * still less than one buffer in size. 1968 */ 1969 #define IXGBE_LAST_OFFSET \ 1970 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1971 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1972 return false; 1973 #endif 1974 1975 /* If we have drained the page fragment pool we need to update 1976 * the pagecnt_bias and page count so that we fully restock the 1977 * number of references the driver holds. 1978 */ 1979 if (unlikely(pagecnt_bias == 1)) { 1980 page_ref_add(page, USHRT_MAX - 1); 1981 rx_buffer->pagecnt_bias = USHRT_MAX; 1982 } 1983 1984 return true; 1985 } 1986 1987 /** 1988 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1989 * @rx_ring: rx descriptor ring to transact packets on 1990 * @rx_buffer: buffer containing page to add 1991 * @skb: sk_buff to place the data into 1992 * @size: size of data in rx_buffer 1993 * 1994 * This function will add the data contained in rx_buffer->page to the skb. 1995 * This is done either through a direct copy if the data in the buffer is 1996 * less than the skb header size, otherwise it will just attach the page as 1997 * a frag to the skb. 1998 * 1999 * The function will then update the page offset if necessary and return 2000 * true if the buffer can be reused by the adapter. 2001 **/ 2002 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2003 struct ixgbe_rx_buffer *rx_buffer, 2004 struct sk_buff *skb, 2005 unsigned int size) 2006 { 2007 #if (PAGE_SIZE < 8192) 2008 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2009 #else 2010 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2011 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2012 SKB_DATA_ALIGN(size); 2013 #endif 2014 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2015 rx_buffer->page_offset, size, truesize); 2016 #if (PAGE_SIZE < 8192) 2017 rx_buffer->page_offset ^= truesize; 2018 #else 2019 rx_buffer->page_offset += truesize; 2020 #endif 2021 } 2022 2023 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2024 union ixgbe_adv_rx_desc *rx_desc, 2025 struct sk_buff **skb, 2026 const unsigned int size) 2027 { 2028 struct ixgbe_rx_buffer *rx_buffer; 2029 2030 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2031 prefetchw(rx_buffer->page); 2032 *skb = rx_buffer->skb; 2033 2034 /* Delay unmapping of the first packet. It carries the header 2035 * information, HW may still access the header after the writeback. 2036 * Only unmap it when EOP is reached 2037 */ 2038 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2039 if (!*skb) 2040 goto skip_sync; 2041 } else { 2042 if (*skb) 2043 ixgbe_dma_sync_frag(rx_ring, *skb); 2044 } 2045 2046 /* we are reusing so sync this buffer for CPU use */ 2047 dma_sync_single_range_for_cpu(rx_ring->dev, 2048 rx_buffer->dma, 2049 rx_buffer->page_offset, 2050 size, 2051 DMA_FROM_DEVICE); 2052 skip_sync: 2053 rx_buffer->pagecnt_bias--; 2054 2055 return rx_buffer; 2056 } 2057 2058 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2059 struct ixgbe_rx_buffer *rx_buffer, 2060 struct sk_buff *skb) 2061 { 2062 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2063 /* hand second half of page back to the ring */ 2064 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2065 } else { 2066 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2067 /* the page has been released from the ring */ 2068 IXGBE_CB(skb)->page_released = true; 2069 } else { 2070 /* we are not reusing the buffer so unmap it */ 2071 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2072 ixgbe_rx_pg_size(rx_ring), 2073 DMA_FROM_DEVICE, 2074 IXGBE_RX_DMA_ATTR); 2075 } 2076 __page_frag_cache_drain(rx_buffer->page, 2077 rx_buffer->pagecnt_bias); 2078 } 2079 2080 /* clear contents of rx_buffer */ 2081 rx_buffer->page = NULL; 2082 rx_buffer->skb = NULL; 2083 } 2084 2085 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2086 struct ixgbe_rx_buffer *rx_buffer, 2087 struct xdp_buff *xdp, 2088 union ixgbe_adv_rx_desc *rx_desc) 2089 { 2090 unsigned int size = xdp->data_end - xdp->data; 2091 #if (PAGE_SIZE < 8192) 2092 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2093 #else 2094 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2095 xdp->data_hard_start); 2096 #endif 2097 struct sk_buff *skb; 2098 2099 /* prefetch first cache line of first page */ 2100 prefetch(xdp->data); 2101 #if L1_CACHE_BYTES < 128 2102 prefetch(xdp->data + L1_CACHE_BYTES); 2103 #endif 2104 /* Note, we get here by enabling legacy-rx via: 2105 * 2106 * ethtool --set-priv-flags <dev> legacy-rx on 2107 * 2108 * In this mode, we currently get 0 extra XDP headroom as 2109 * opposed to having legacy-rx off, where we process XDP 2110 * packets going to stack via ixgbe_build_skb(). The latter 2111 * provides us currently with 192 bytes of headroom. 2112 * 2113 * For ixgbe_construct_skb() mode it means that the 2114 * xdp->data_meta will always point to xdp->data, since 2115 * the helper cannot expand the head. Should this ever 2116 * change in future for legacy-rx mode on, then lets also 2117 * add xdp->data_meta handling here. 2118 */ 2119 2120 /* allocate a skb to store the frags */ 2121 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2122 if (unlikely(!skb)) 2123 return NULL; 2124 2125 if (size > IXGBE_RX_HDR_SIZE) { 2126 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2127 IXGBE_CB(skb)->dma = rx_buffer->dma; 2128 2129 skb_add_rx_frag(skb, 0, rx_buffer->page, 2130 xdp->data - page_address(rx_buffer->page), 2131 size, truesize); 2132 #if (PAGE_SIZE < 8192) 2133 rx_buffer->page_offset ^= truesize; 2134 #else 2135 rx_buffer->page_offset += truesize; 2136 #endif 2137 } else { 2138 memcpy(__skb_put(skb, size), 2139 xdp->data, ALIGN(size, sizeof(long))); 2140 rx_buffer->pagecnt_bias++; 2141 } 2142 2143 return skb; 2144 } 2145 2146 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2147 struct ixgbe_rx_buffer *rx_buffer, 2148 struct xdp_buff *xdp, 2149 union ixgbe_adv_rx_desc *rx_desc) 2150 { 2151 unsigned int metasize = xdp->data - xdp->data_meta; 2152 #if (PAGE_SIZE < 8192) 2153 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2154 #else 2155 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2156 SKB_DATA_ALIGN(xdp->data_end - 2157 xdp->data_hard_start); 2158 #endif 2159 struct sk_buff *skb; 2160 2161 /* Prefetch first cache line of first page. If xdp->data_meta 2162 * is unused, this points extactly as xdp->data, otherwise we 2163 * likely have a consumer accessing first few bytes of meta 2164 * data, and then actual data. 2165 */ 2166 prefetch(xdp->data_meta); 2167 #if L1_CACHE_BYTES < 128 2168 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2169 #endif 2170 2171 /* build an skb to around the page buffer */ 2172 skb = build_skb(xdp->data_hard_start, truesize); 2173 if (unlikely(!skb)) 2174 return NULL; 2175 2176 /* update pointers within the skb to store the data */ 2177 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2178 __skb_put(skb, xdp->data_end - xdp->data); 2179 if (metasize) 2180 skb_metadata_set(skb, metasize); 2181 2182 /* record DMA address if this is the start of a chain of buffers */ 2183 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2184 IXGBE_CB(skb)->dma = rx_buffer->dma; 2185 2186 /* update buffer offset */ 2187 #if (PAGE_SIZE < 8192) 2188 rx_buffer->page_offset ^= truesize; 2189 #else 2190 rx_buffer->page_offset += truesize; 2191 #endif 2192 2193 return skb; 2194 } 2195 2196 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2197 struct ixgbe_ring *rx_ring, 2198 struct xdp_buff *xdp) 2199 { 2200 int err, result = IXGBE_XDP_PASS; 2201 struct bpf_prog *xdp_prog; 2202 struct xdp_frame *xdpf; 2203 u32 act; 2204 2205 rcu_read_lock(); 2206 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2207 2208 if (!xdp_prog) 2209 goto xdp_out; 2210 2211 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2212 2213 act = bpf_prog_run_xdp(xdp_prog, xdp); 2214 switch (act) { 2215 case XDP_PASS: 2216 break; 2217 case XDP_TX: 2218 xdpf = xdp_convert_buff_to_frame(xdp); 2219 if (unlikely(!xdpf)) { 2220 result = IXGBE_XDP_CONSUMED; 2221 break; 2222 } 2223 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 2224 break; 2225 case XDP_REDIRECT: 2226 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2227 if (!err) 2228 result = IXGBE_XDP_REDIR; 2229 else 2230 result = IXGBE_XDP_CONSUMED; 2231 break; 2232 default: 2233 bpf_warn_invalid_xdp_action(act); 2234 /* fallthrough */ 2235 case XDP_ABORTED: 2236 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2237 /* fallthrough -- handle aborts by dropping packet */ 2238 case XDP_DROP: 2239 result = IXGBE_XDP_CONSUMED; 2240 break; 2241 } 2242 xdp_out: 2243 rcu_read_unlock(); 2244 return ERR_PTR(-result); 2245 } 2246 2247 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2248 unsigned int size) 2249 { 2250 unsigned int truesize; 2251 2252 #if (PAGE_SIZE < 8192) 2253 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2254 #else 2255 truesize = ring_uses_build_skb(rx_ring) ? 2256 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) + 2257 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2258 SKB_DATA_ALIGN(size); 2259 #endif 2260 return truesize; 2261 } 2262 2263 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2264 struct ixgbe_rx_buffer *rx_buffer, 2265 unsigned int size) 2266 { 2267 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2268 #if (PAGE_SIZE < 8192) 2269 rx_buffer->page_offset ^= truesize; 2270 #else 2271 rx_buffer->page_offset += truesize; 2272 #endif 2273 } 2274 2275 /** 2276 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2277 * @q_vector: structure containing interrupt and ring information 2278 * @rx_ring: rx descriptor ring to transact packets on 2279 * @budget: Total limit on number of packets to process 2280 * 2281 * This function provides a "bounce buffer" approach to Rx interrupt 2282 * processing. The advantage to this is that on systems that have 2283 * expensive overhead for IOMMU access this provides a means of avoiding 2284 * it by maintaining the mapping of the page to the syste. 2285 * 2286 * Returns amount of work completed 2287 **/ 2288 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2289 struct ixgbe_ring *rx_ring, 2290 const int budget) 2291 { 2292 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2293 struct ixgbe_adapter *adapter = q_vector->adapter; 2294 #ifdef IXGBE_FCOE 2295 int ddp_bytes; 2296 unsigned int mss = 0; 2297 #endif /* IXGBE_FCOE */ 2298 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2299 unsigned int xdp_xmit = 0; 2300 struct xdp_buff xdp; 2301 2302 xdp.rxq = &rx_ring->xdp_rxq; 2303 2304 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2305 #if (PAGE_SIZE < 8192) 2306 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2307 #endif 2308 2309 while (likely(total_rx_packets < budget)) { 2310 union ixgbe_adv_rx_desc *rx_desc; 2311 struct ixgbe_rx_buffer *rx_buffer; 2312 struct sk_buff *skb; 2313 unsigned int size; 2314 2315 /* return some buffers to hardware, one at a time is too slow */ 2316 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2317 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2318 cleaned_count = 0; 2319 } 2320 2321 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2322 size = le16_to_cpu(rx_desc->wb.upper.length); 2323 if (!size) 2324 break; 2325 2326 /* This memory barrier is needed to keep us from reading 2327 * any other fields out of the rx_desc until we know the 2328 * descriptor has been written back 2329 */ 2330 dma_rmb(); 2331 2332 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2333 2334 /* retrieve a buffer from the ring */ 2335 if (!skb) { 2336 xdp.data = page_address(rx_buffer->page) + 2337 rx_buffer->page_offset; 2338 xdp.data_meta = xdp.data; 2339 xdp.data_hard_start = xdp.data - 2340 ixgbe_rx_offset(rx_ring); 2341 xdp.data_end = xdp.data + size; 2342 #if (PAGE_SIZE > 4096) 2343 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2344 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2345 #endif 2346 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2347 } 2348 2349 if (IS_ERR(skb)) { 2350 unsigned int xdp_res = -PTR_ERR(skb); 2351 2352 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2353 xdp_xmit |= xdp_res; 2354 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2355 } else { 2356 rx_buffer->pagecnt_bias++; 2357 } 2358 total_rx_packets++; 2359 total_rx_bytes += size; 2360 } else if (skb) { 2361 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2362 } else if (ring_uses_build_skb(rx_ring)) { 2363 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2364 &xdp, rx_desc); 2365 } else { 2366 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2367 &xdp, rx_desc); 2368 } 2369 2370 /* exit if we failed to retrieve a buffer */ 2371 if (!skb) { 2372 rx_ring->rx_stats.alloc_rx_buff_failed++; 2373 rx_buffer->pagecnt_bias++; 2374 break; 2375 } 2376 2377 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2378 cleaned_count++; 2379 2380 /* place incomplete frames back on ring for completion */ 2381 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2382 continue; 2383 2384 /* verify the packet layout is correct */ 2385 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2386 continue; 2387 2388 /* probably a little skewed due to removing CRC */ 2389 total_rx_bytes += skb->len; 2390 2391 /* populate checksum, timestamp, VLAN, and protocol */ 2392 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2393 2394 #ifdef IXGBE_FCOE 2395 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2396 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2397 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2398 /* include DDPed FCoE data */ 2399 if (ddp_bytes > 0) { 2400 if (!mss) { 2401 mss = rx_ring->netdev->mtu - 2402 sizeof(struct fcoe_hdr) - 2403 sizeof(struct fc_frame_header) - 2404 sizeof(struct fcoe_crc_eof); 2405 if (mss > 512) 2406 mss &= ~511; 2407 } 2408 total_rx_bytes += ddp_bytes; 2409 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2410 mss); 2411 } 2412 if (!ddp_bytes) { 2413 dev_kfree_skb_any(skb); 2414 continue; 2415 } 2416 } 2417 2418 #endif /* IXGBE_FCOE */ 2419 ixgbe_rx_skb(q_vector, skb); 2420 2421 /* update budget accounting */ 2422 total_rx_packets++; 2423 } 2424 2425 if (xdp_xmit & IXGBE_XDP_REDIR) 2426 xdp_do_flush_map(); 2427 2428 if (xdp_xmit & IXGBE_XDP_TX) { 2429 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2430 2431 /* Force memory writes to complete before letting h/w 2432 * know there are new descriptors to fetch. 2433 */ 2434 wmb(); 2435 writel(ring->next_to_use, ring->tail); 2436 } 2437 2438 u64_stats_update_begin(&rx_ring->syncp); 2439 rx_ring->stats.packets += total_rx_packets; 2440 rx_ring->stats.bytes += total_rx_bytes; 2441 u64_stats_update_end(&rx_ring->syncp); 2442 q_vector->rx.total_packets += total_rx_packets; 2443 q_vector->rx.total_bytes += total_rx_bytes; 2444 2445 return total_rx_packets; 2446 } 2447 2448 /** 2449 * ixgbe_configure_msix - Configure MSI-X hardware 2450 * @adapter: board private structure 2451 * 2452 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2453 * interrupts. 2454 **/ 2455 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2456 { 2457 struct ixgbe_q_vector *q_vector; 2458 int v_idx; 2459 u32 mask; 2460 2461 /* Populate MSIX to EITR Select */ 2462 if (adapter->num_vfs > 32) { 2463 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2464 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2465 } 2466 2467 /* 2468 * Populate the IVAR table and set the ITR values to the 2469 * corresponding register. 2470 */ 2471 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2472 struct ixgbe_ring *ring; 2473 q_vector = adapter->q_vector[v_idx]; 2474 2475 ixgbe_for_each_ring(ring, q_vector->rx) 2476 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2477 2478 ixgbe_for_each_ring(ring, q_vector->tx) 2479 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2480 2481 ixgbe_write_eitr(q_vector); 2482 } 2483 2484 switch (adapter->hw.mac.type) { 2485 case ixgbe_mac_82598EB: 2486 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2487 v_idx); 2488 break; 2489 case ixgbe_mac_82599EB: 2490 case ixgbe_mac_X540: 2491 case ixgbe_mac_X550: 2492 case ixgbe_mac_X550EM_x: 2493 case ixgbe_mac_x550em_a: 2494 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2495 break; 2496 default: 2497 break; 2498 } 2499 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2500 2501 /* set up to autoclear timer, and the vectors */ 2502 mask = IXGBE_EIMS_ENABLE_MASK; 2503 mask &= ~(IXGBE_EIMS_OTHER | 2504 IXGBE_EIMS_MAILBOX | 2505 IXGBE_EIMS_LSC); 2506 2507 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2508 } 2509 2510 /** 2511 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2512 * @q_vector: structure containing interrupt and ring information 2513 * @ring_container: structure containing ring performance data 2514 * 2515 * Stores a new ITR value based on packets and byte 2516 * counts during the last interrupt. The advantage of per interrupt 2517 * computation is faster updates and more accurate ITR for the current 2518 * traffic pattern. Constants in this function were computed 2519 * based on theoretical maximum wire speed and thresholds were set based 2520 * on testing data as well as attempting to minimize response time 2521 * while increasing bulk throughput. 2522 **/ 2523 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2524 struct ixgbe_ring_container *ring_container) 2525 { 2526 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2527 IXGBE_ITR_ADAPTIVE_LATENCY; 2528 unsigned int avg_wire_size, packets, bytes; 2529 unsigned long next_update = jiffies; 2530 2531 /* If we don't have any rings just leave ourselves set for maximum 2532 * possible latency so we take ourselves out of the equation. 2533 */ 2534 if (!ring_container->ring) 2535 return; 2536 2537 /* If we didn't update within up to 1 - 2 jiffies we can assume 2538 * that either packets are coming in so slow there hasn't been 2539 * any work, or that there is so much work that NAPI is dealing 2540 * with interrupt moderation and we don't need to do anything. 2541 */ 2542 if (time_after(next_update, ring_container->next_update)) 2543 goto clear_counts; 2544 2545 packets = ring_container->total_packets; 2546 2547 /* We have no packets to actually measure against. This means 2548 * either one of the other queues on this vector is active or 2549 * we are a Tx queue doing TSO with too high of an interrupt rate. 2550 * 2551 * When this occurs just tick up our delay by the minimum value 2552 * and hope that this extra delay will prevent us from being called 2553 * without any work on our queue. 2554 */ 2555 if (!packets) { 2556 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2557 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2558 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2559 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2560 goto clear_counts; 2561 } 2562 2563 bytes = ring_container->total_bytes; 2564 2565 /* If packets are less than 4 or bytes are less than 9000 assume 2566 * insufficient data to use bulk rate limiting approach. We are 2567 * likely latency driven. 2568 */ 2569 if (packets < 4 && bytes < 9000) { 2570 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2571 goto adjust_by_size; 2572 } 2573 2574 /* Between 4 and 48 we can assume that our current interrupt delay 2575 * is only slightly too low. As such we should increase it by a small 2576 * fixed amount. 2577 */ 2578 if (packets < 48) { 2579 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2580 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2581 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2582 goto clear_counts; 2583 } 2584 2585 /* Between 48 and 96 is our "goldilocks" zone where we are working 2586 * out "just right". Just report that our current ITR is good for us. 2587 */ 2588 if (packets < 96) { 2589 itr = q_vector->itr >> 2; 2590 goto clear_counts; 2591 } 2592 2593 /* If packet count is 96 or greater we are likely looking at a slight 2594 * overrun of the delay we want. Try halving our delay to see if that 2595 * will cut the number of packets in half per interrupt. 2596 */ 2597 if (packets < 256) { 2598 itr = q_vector->itr >> 3; 2599 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2600 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2601 goto clear_counts; 2602 } 2603 2604 /* The paths below assume we are dealing with a bulk ITR since number 2605 * of packets is 256 or greater. We are just going to have to compute 2606 * a value and try to bring the count under control, though for smaller 2607 * packet sizes there isn't much we can do as NAPI polling will likely 2608 * be kicking in sooner rather than later. 2609 */ 2610 itr = IXGBE_ITR_ADAPTIVE_BULK; 2611 2612 adjust_by_size: 2613 /* If packet counts are 256 or greater we can assume we have a gross 2614 * overestimation of what the rate should be. Instead of trying to fine 2615 * tune it just use the formula below to try and dial in an exact value 2616 * give the current packet size of the frame. 2617 */ 2618 avg_wire_size = bytes / packets; 2619 2620 /* The following is a crude approximation of: 2621 * wmem_default / (size + overhead) = desired_pkts_per_int 2622 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2623 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2624 * 2625 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2626 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2627 * formula down to 2628 * 2629 * (170 * (size + 24)) / (size + 640) = ITR 2630 * 2631 * We first do some math on the packet size and then finally bitshift 2632 * by 8 after rounding up. We also have to account for PCIe link speed 2633 * difference as ITR scales based on this. 2634 */ 2635 if (avg_wire_size <= 60) { 2636 /* Start at 50k ints/sec */ 2637 avg_wire_size = 5120; 2638 } else if (avg_wire_size <= 316) { 2639 /* 50K ints/sec to 16K ints/sec */ 2640 avg_wire_size *= 40; 2641 avg_wire_size += 2720; 2642 } else if (avg_wire_size <= 1084) { 2643 /* 16K ints/sec to 9.2K ints/sec */ 2644 avg_wire_size *= 15; 2645 avg_wire_size += 11452; 2646 } else if (avg_wire_size < 1968) { 2647 /* 9.2K ints/sec to 8K ints/sec */ 2648 avg_wire_size *= 5; 2649 avg_wire_size += 22420; 2650 } else { 2651 /* plateau at a limit of 8K ints/sec */ 2652 avg_wire_size = 32256; 2653 } 2654 2655 /* If we are in low latency mode half our delay which doubles the rate 2656 * to somewhere between 100K to 16K ints/sec 2657 */ 2658 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2659 avg_wire_size >>= 1; 2660 2661 /* Resultant value is 256 times larger than it needs to be. This 2662 * gives us room to adjust the value as needed to either increase 2663 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2664 * 2665 * Use addition as we have already recorded the new latency flag 2666 * for the ITR value. 2667 */ 2668 switch (q_vector->adapter->link_speed) { 2669 case IXGBE_LINK_SPEED_10GB_FULL: 2670 case IXGBE_LINK_SPEED_100_FULL: 2671 default: 2672 itr += DIV_ROUND_UP(avg_wire_size, 2673 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2674 IXGBE_ITR_ADAPTIVE_MIN_INC; 2675 break; 2676 case IXGBE_LINK_SPEED_2_5GB_FULL: 2677 case IXGBE_LINK_SPEED_1GB_FULL: 2678 case IXGBE_LINK_SPEED_10_FULL: 2679 if (avg_wire_size > 8064) 2680 avg_wire_size = 8064; 2681 itr += DIV_ROUND_UP(avg_wire_size, 2682 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2683 IXGBE_ITR_ADAPTIVE_MIN_INC; 2684 break; 2685 } 2686 2687 clear_counts: 2688 /* write back value */ 2689 ring_container->itr = itr; 2690 2691 /* next update should occur within next jiffy */ 2692 ring_container->next_update = next_update + 1; 2693 2694 ring_container->total_bytes = 0; 2695 ring_container->total_packets = 0; 2696 } 2697 2698 /** 2699 * ixgbe_write_eitr - write EITR register in hardware specific way 2700 * @q_vector: structure containing interrupt and ring information 2701 * 2702 * This function is made to be called by ethtool and by the driver 2703 * when it needs to update EITR registers at runtime. Hardware 2704 * specific quirks/differences are taken care of here. 2705 */ 2706 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2707 { 2708 struct ixgbe_adapter *adapter = q_vector->adapter; 2709 struct ixgbe_hw *hw = &adapter->hw; 2710 int v_idx = q_vector->v_idx; 2711 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2712 2713 switch (adapter->hw.mac.type) { 2714 case ixgbe_mac_82598EB: 2715 /* must write high and low 16 bits to reset counter */ 2716 itr_reg |= (itr_reg << 16); 2717 break; 2718 case ixgbe_mac_82599EB: 2719 case ixgbe_mac_X540: 2720 case ixgbe_mac_X550: 2721 case ixgbe_mac_X550EM_x: 2722 case ixgbe_mac_x550em_a: 2723 /* 2724 * set the WDIS bit to not clear the timer bits and cause an 2725 * immediate assertion of the interrupt 2726 */ 2727 itr_reg |= IXGBE_EITR_CNT_WDIS; 2728 break; 2729 default: 2730 break; 2731 } 2732 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2733 } 2734 2735 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2736 { 2737 u32 new_itr; 2738 2739 ixgbe_update_itr(q_vector, &q_vector->tx); 2740 ixgbe_update_itr(q_vector, &q_vector->rx); 2741 2742 /* use the smallest value of new ITR delay calculations */ 2743 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2744 2745 /* Clear latency flag if set, shift into correct position */ 2746 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2747 new_itr <<= 2; 2748 2749 if (new_itr != q_vector->itr) { 2750 /* save the algorithm value here */ 2751 q_vector->itr = new_itr; 2752 2753 ixgbe_write_eitr(q_vector); 2754 } 2755 } 2756 2757 /** 2758 * ixgbe_check_overtemp_subtask - check for over temperature 2759 * @adapter: pointer to adapter 2760 **/ 2761 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2762 { 2763 struct ixgbe_hw *hw = &adapter->hw; 2764 u32 eicr = adapter->interrupt_event; 2765 s32 rc; 2766 2767 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2768 return; 2769 2770 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2771 return; 2772 2773 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2774 2775 switch (hw->device_id) { 2776 case IXGBE_DEV_ID_82599_T3_LOM: 2777 /* 2778 * Since the warning interrupt is for both ports 2779 * we don't have to check if: 2780 * - This interrupt wasn't for our port. 2781 * - We may have missed the interrupt so always have to 2782 * check if we got a LSC 2783 */ 2784 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2785 !(eicr & IXGBE_EICR_LSC)) 2786 return; 2787 2788 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2789 u32 speed; 2790 bool link_up = false; 2791 2792 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2793 2794 if (link_up) 2795 return; 2796 } 2797 2798 /* Check if this is not due to overtemp */ 2799 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2800 return; 2801 2802 break; 2803 case IXGBE_DEV_ID_X550EM_A_1G_T: 2804 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2805 rc = hw->phy.ops.check_overtemp(hw); 2806 if (rc != IXGBE_ERR_OVERTEMP) 2807 return; 2808 break; 2809 default: 2810 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2811 return; 2812 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2813 return; 2814 break; 2815 } 2816 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2817 2818 adapter->interrupt_event = 0; 2819 } 2820 2821 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2822 { 2823 struct ixgbe_hw *hw = &adapter->hw; 2824 2825 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2826 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2827 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2828 /* write to clear the interrupt */ 2829 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2830 } 2831 } 2832 2833 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2834 { 2835 struct ixgbe_hw *hw = &adapter->hw; 2836 2837 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2838 return; 2839 2840 switch (adapter->hw.mac.type) { 2841 case ixgbe_mac_82599EB: 2842 /* 2843 * Need to check link state so complete overtemp check 2844 * on service task 2845 */ 2846 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2847 (eicr & IXGBE_EICR_LSC)) && 2848 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2849 adapter->interrupt_event = eicr; 2850 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2851 ixgbe_service_event_schedule(adapter); 2852 return; 2853 } 2854 return; 2855 case ixgbe_mac_x550em_a: 2856 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2857 adapter->interrupt_event = eicr; 2858 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2859 ixgbe_service_event_schedule(adapter); 2860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2861 IXGBE_EICR_GPI_SDP0_X550EM_a); 2862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2863 IXGBE_EICR_GPI_SDP0_X550EM_a); 2864 } 2865 return; 2866 case ixgbe_mac_X550: 2867 case ixgbe_mac_X540: 2868 if (!(eicr & IXGBE_EICR_TS)) 2869 return; 2870 break; 2871 default: 2872 return; 2873 } 2874 2875 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2876 } 2877 2878 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2879 { 2880 switch (hw->mac.type) { 2881 case ixgbe_mac_82598EB: 2882 if (hw->phy.type == ixgbe_phy_nl) 2883 return true; 2884 return false; 2885 case ixgbe_mac_82599EB: 2886 case ixgbe_mac_X550EM_x: 2887 case ixgbe_mac_x550em_a: 2888 switch (hw->mac.ops.get_media_type(hw)) { 2889 case ixgbe_media_type_fiber: 2890 case ixgbe_media_type_fiber_qsfp: 2891 return true; 2892 default: 2893 return false; 2894 } 2895 default: 2896 return false; 2897 } 2898 } 2899 2900 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2901 { 2902 struct ixgbe_hw *hw = &adapter->hw; 2903 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2904 2905 if (!ixgbe_is_sfp(hw)) 2906 return; 2907 2908 /* Later MAC's use different SDP */ 2909 if (hw->mac.type >= ixgbe_mac_X540) 2910 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2911 2912 if (eicr & eicr_mask) { 2913 /* Clear the interrupt */ 2914 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2915 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2916 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2917 adapter->sfp_poll_time = 0; 2918 ixgbe_service_event_schedule(adapter); 2919 } 2920 } 2921 2922 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2923 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2924 /* Clear the interrupt */ 2925 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2926 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2927 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2928 ixgbe_service_event_schedule(adapter); 2929 } 2930 } 2931 } 2932 2933 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2934 { 2935 struct ixgbe_hw *hw = &adapter->hw; 2936 2937 adapter->lsc_int++; 2938 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2939 adapter->link_check_timeout = jiffies; 2940 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2941 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2942 IXGBE_WRITE_FLUSH(hw); 2943 ixgbe_service_event_schedule(adapter); 2944 } 2945 } 2946 2947 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2948 u64 qmask) 2949 { 2950 u32 mask; 2951 struct ixgbe_hw *hw = &adapter->hw; 2952 2953 switch (hw->mac.type) { 2954 case ixgbe_mac_82598EB: 2955 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2956 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2957 break; 2958 case ixgbe_mac_82599EB: 2959 case ixgbe_mac_X540: 2960 case ixgbe_mac_X550: 2961 case ixgbe_mac_X550EM_x: 2962 case ixgbe_mac_x550em_a: 2963 mask = (qmask & 0xFFFFFFFF); 2964 if (mask) 2965 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2966 mask = (qmask >> 32); 2967 if (mask) 2968 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2969 break; 2970 default: 2971 break; 2972 } 2973 /* skip the flush */ 2974 } 2975 2976 /** 2977 * ixgbe_irq_enable - Enable default interrupt generation settings 2978 * @adapter: board private structure 2979 * @queues: enable irqs for queues 2980 * @flush: flush register write 2981 **/ 2982 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2983 bool flush) 2984 { 2985 struct ixgbe_hw *hw = &adapter->hw; 2986 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2987 2988 /* don't reenable LSC while waiting for link */ 2989 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2990 mask &= ~IXGBE_EIMS_LSC; 2991 2992 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2993 switch (adapter->hw.mac.type) { 2994 case ixgbe_mac_82599EB: 2995 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2996 break; 2997 case ixgbe_mac_X540: 2998 case ixgbe_mac_X550: 2999 case ixgbe_mac_X550EM_x: 3000 case ixgbe_mac_x550em_a: 3001 mask |= IXGBE_EIMS_TS; 3002 break; 3003 default: 3004 break; 3005 } 3006 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3007 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3008 switch (adapter->hw.mac.type) { 3009 case ixgbe_mac_82599EB: 3010 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3011 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3012 /* fall through */ 3013 case ixgbe_mac_X540: 3014 case ixgbe_mac_X550: 3015 case ixgbe_mac_X550EM_x: 3016 case ixgbe_mac_x550em_a: 3017 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3018 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3019 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3020 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3021 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3022 mask |= IXGBE_EICR_GPI_SDP0_X540; 3023 mask |= IXGBE_EIMS_ECC; 3024 mask |= IXGBE_EIMS_MAILBOX; 3025 break; 3026 default: 3027 break; 3028 } 3029 3030 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3031 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3032 mask |= IXGBE_EIMS_FLOW_DIR; 3033 3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3035 if (queues) 3036 ixgbe_irq_enable_queues(adapter, ~0); 3037 if (flush) 3038 IXGBE_WRITE_FLUSH(&adapter->hw); 3039 } 3040 3041 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3042 { 3043 struct ixgbe_adapter *adapter = data; 3044 struct ixgbe_hw *hw = &adapter->hw; 3045 u32 eicr; 3046 3047 /* 3048 * Workaround for Silicon errata. Use clear-by-write instead 3049 * of clear-by-read. Reading with EICS will return the 3050 * interrupt causes without clearing, which later be done 3051 * with the write to EICR. 3052 */ 3053 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3054 3055 /* The lower 16bits of the EICR register are for the queue interrupts 3056 * which should be masked here in order to not accidentally clear them if 3057 * the bits are high when ixgbe_msix_other is called. There is a race 3058 * condition otherwise which results in possible performance loss 3059 * especially if the ixgbe_msix_other interrupt is triggering 3060 * consistently (as it would when PPS is turned on for the X540 device) 3061 */ 3062 eicr &= 0xFFFF0000; 3063 3064 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3065 3066 if (eicr & IXGBE_EICR_LSC) 3067 ixgbe_check_lsc(adapter); 3068 3069 if (eicr & IXGBE_EICR_MAILBOX) 3070 ixgbe_msg_task(adapter); 3071 3072 switch (hw->mac.type) { 3073 case ixgbe_mac_82599EB: 3074 case ixgbe_mac_X540: 3075 case ixgbe_mac_X550: 3076 case ixgbe_mac_X550EM_x: 3077 case ixgbe_mac_x550em_a: 3078 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3079 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3080 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3081 ixgbe_service_event_schedule(adapter); 3082 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3083 IXGBE_EICR_GPI_SDP0_X540); 3084 } 3085 if (eicr & IXGBE_EICR_ECC) { 3086 e_info(link, "Received ECC Err, initiating reset\n"); 3087 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3088 ixgbe_service_event_schedule(adapter); 3089 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3090 } 3091 /* Handle Flow Director Full threshold interrupt */ 3092 if (eicr & IXGBE_EICR_FLOW_DIR) { 3093 int reinit_count = 0; 3094 int i; 3095 for (i = 0; i < adapter->num_tx_queues; i++) { 3096 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3097 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3098 &ring->state)) 3099 reinit_count++; 3100 } 3101 if (reinit_count) { 3102 /* no more flow director interrupts until after init */ 3103 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3104 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3105 ixgbe_service_event_schedule(adapter); 3106 } 3107 } 3108 ixgbe_check_sfp_event(adapter, eicr); 3109 ixgbe_check_overtemp_event(adapter, eicr); 3110 break; 3111 default: 3112 break; 3113 } 3114 3115 ixgbe_check_fan_failure(adapter, eicr); 3116 3117 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3118 ixgbe_ptp_check_pps_event(adapter); 3119 3120 /* re-enable the original interrupt state, no lsc, no queues */ 3121 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3122 ixgbe_irq_enable(adapter, false, false); 3123 3124 return IRQ_HANDLED; 3125 } 3126 3127 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3128 { 3129 struct ixgbe_q_vector *q_vector = data; 3130 3131 /* EIAM disabled interrupts (on this vector) for us */ 3132 3133 if (q_vector->rx.ring || q_vector->tx.ring) 3134 napi_schedule_irqoff(&q_vector->napi); 3135 3136 return IRQ_HANDLED; 3137 } 3138 3139 /** 3140 * ixgbe_poll - NAPI Rx polling callback 3141 * @napi: structure for representing this polling device 3142 * @budget: how many packets driver is allowed to clean 3143 * 3144 * This function is used for legacy and MSI, NAPI mode 3145 **/ 3146 int ixgbe_poll(struct napi_struct *napi, int budget) 3147 { 3148 struct ixgbe_q_vector *q_vector = 3149 container_of(napi, struct ixgbe_q_vector, napi); 3150 struct ixgbe_adapter *adapter = q_vector->adapter; 3151 struct ixgbe_ring *ring; 3152 int per_ring_budget, work_done = 0; 3153 bool clean_complete = true; 3154 3155 #ifdef CONFIG_IXGBE_DCA 3156 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3157 ixgbe_update_dca(q_vector); 3158 #endif 3159 3160 ixgbe_for_each_ring(ring, q_vector->tx) { 3161 bool wd = ring->xsk_umem ? 3162 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3163 ixgbe_clean_tx_irq(q_vector, ring, budget); 3164 3165 if (!wd) 3166 clean_complete = false; 3167 } 3168 3169 /* Exit if we are called by netpoll */ 3170 if (budget <= 0) 3171 return budget; 3172 3173 /* attempt to distribute budget to each queue fairly, but don't allow 3174 * the budget to go below 1 because we'll exit polling */ 3175 if (q_vector->rx.count > 1) 3176 per_ring_budget = max(budget/q_vector->rx.count, 1); 3177 else 3178 per_ring_budget = budget; 3179 3180 ixgbe_for_each_ring(ring, q_vector->rx) { 3181 int cleaned = ring->xsk_umem ? 3182 ixgbe_clean_rx_irq_zc(q_vector, ring, 3183 per_ring_budget) : 3184 ixgbe_clean_rx_irq(q_vector, ring, 3185 per_ring_budget); 3186 3187 work_done += cleaned; 3188 if (cleaned >= per_ring_budget) 3189 clean_complete = false; 3190 } 3191 3192 /* If all work not completed, return budget and keep polling */ 3193 if (!clean_complete) 3194 return budget; 3195 3196 /* all work done, exit the polling mode */ 3197 if (likely(napi_complete_done(napi, work_done))) { 3198 if (adapter->rx_itr_setting & 1) 3199 ixgbe_set_itr(q_vector); 3200 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3201 ixgbe_irq_enable_queues(adapter, 3202 BIT_ULL(q_vector->v_idx)); 3203 } 3204 3205 return min(work_done, budget - 1); 3206 } 3207 3208 /** 3209 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3210 * @adapter: board private structure 3211 * 3212 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3213 * interrupts from the kernel. 3214 **/ 3215 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3216 { 3217 struct net_device *netdev = adapter->netdev; 3218 unsigned int ri = 0, ti = 0; 3219 int vector, err; 3220 3221 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3222 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3223 struct msix_entry *entry = &adapter->msix_entries[vector]; 3224 3225 if (q_vector->tx.ring && q_vector->rx.ring) { 3226 snprintf(q_vector->name, sizeof(q_vector->name), 3227 "%s-TxRx-%u", netdev->name, ri++); 3228 ti++; 3229 } else if (q_vector->rx.ring) { 3230 snprintf(q_vector->name, sizeof(q_vector->name), 3231 "%s-rx-%u", netdev->name, ri++); 3232 } else if (q_vector->tx.ring) { 3233 snprintf(q_vector->name, sizeof(q_vector->name), 3234 "%s-tx-%u", netdev->name, ti++); 3235 } else { 3236 /* skip this unused q_vector */ 3237 continue; 3238 } 3239 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3240 q_vector->name, q_vector); 3241 if (err) { 3242 e_err(probe, "request_irq failed for MSIX interrupt " 3243 "Error: %d\n", err); 3244 goto free_queue_irqs; 3245 } 3246 /* If Flow Director is enabled, set interrupt affinity */ 3247 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3248 /* assign the mask for this irq */ 3249 irq_set_affinity_hint(entry->vector, 3250 &q_vector->affinity_mask); 3251 } 3252 } 3253 3254 err = request_irq(adapter->msix_entries[vector].vector, 3255 ixgbe_msix_other, 0, netdev->name, adapter); 3256 if (err) { 3257 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3258 goto free_queue_irqs; 3259 } 3260 3261 return 0; 3262 3263 free_queue_irqs: 3264 while (vector) { 3265 vector--; 3266 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3267 NULL); 3268 free_irq(adapter->msix_entries[vector].vector, 3269 adapter->q_vector[vector]); 3270 } 3271 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3272 pci_disable_msix(adapter->pdev); 3273 kfree(adapter->msix_entries); 3274 adapter->msix_entries = NULL; 3275 return err; 3276 } 3277 3278 /** 3279 * ixgbe_intr - legacy mode Interrupt Handler 3280 * @irq: interrupt number 3281 * @data: pointer to a network interface device structure 3282 **/ 3283 static irqreturn_t ixgbe_intr(int irq, void *data) 3284 { 3285 struct ixgbe_adapter *adapter = data; 3286 struct ixgbe_hw *hw = &adapter->hw; 3287 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3288 u32 eicr; 3289 3290 /* 3291 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3292 * before the read of EICR. 3293 */ 3294 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3295 3296 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3297 * therefore no explicit interrupt disable is necessary */ 3298 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3299 if (!eicr) { 3300 /* 3301 * shared interrupt alert! 3302 * make sure interrupts are enabled because the read will 3303 * have disabled interrupts due to EIAM 3304 * finish the workaround of silicon errata on 82598. Unmask 3305 * the interrupt that we masked before the EICR read. 3306 */ 3307 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3308 ixgbe_irq_enable(adapter, true, true); 3309 return IRQ_NONE; /* Not our interrupt */ 3310 } 3311 3312 if (eicr & IXGBE_EICR_LSC) 3313 ixgbe_check_lsc(adapter); 3314 3315 switch (hw->mac.type) { 3316 case ixgbe_mac_82599EB: 3317 ixgbe_check_sfp_event(adapter, eicr); 3318 /* Fall through */ 3319 case ixgbe_mac_X540: 3320 case ixgbe_mac_X550: 3321 case ixgbe_mac_X550EM_x: 3322 case ixgbe_mac_x550em_a: 3323 if (eicr & IXGBE_EICR_ECC) { 3324 e_info(link, "Received ECC Err, initiating reset\n"); 3325 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3326 ixgbe_service_event_schedule(adapter); 3327 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3328 } 3329 ixgbe_check_overtemp_event(adapter, eicr); 3330 break; 3331 default: 3332 break; 3333 } 3334 3335 ixgbe_check_fan_failure(adapter, eicr); 3336 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3337 ixgbe_ptp_check_pps_event(adapter); 3338 3339 /* would disable interrupts here but EIAM disabled it */ 3340 napi_schedule_irqoff(&q_vector->napi); 3341 3342 /* 3343 * re-enable link(maybe) and non-queue interrupts, no flush. 3344 * ixgbe_poll will re-enable the queue interrupts 3345 */ 3346 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3347 ixgbe_irq_enable(adapter, false, false); 3348 3349 return IRQ_HANDLED; 3350 } 3351 3352 /** 3353 * ixgbe_request_irq - initialize interrupts 3354 * @adapter: board private structure 3355 * 3356 * Attempts to configure interrupts using the best available 3357 * capabilities of the hardware and kernel. 3358 **/ 3359 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3360 { 3361 struct net_device *netdev = adapter->netdev; 3362 int err; 3363 3364 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3365 err = ixgbe_request_msix_irqs(adapter); 3366 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3367 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3368 netdev->name, adapter); 3369 else 3370 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3371 netdev->name, adapter); 3372 3373 if (err) 3374 e_err(probe, "request_irq failed, Error %d\n", err); 3375 3376 return err; 3377 } 3378 3379 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3380 { 3381 int vector; 3382 3383 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3384 free_irq(adapter->pdev->irq, adapter); 3385 return; 3386 } 3387 3388 if (!adapter->msix_entries) 3389 return; 3390 3391 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3392 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3393 struct msix_entry *entry = &adapter->msix_entries[vector]; 3394 3395 /* free only the irqs that were actually requested */ 3396 if (!q_vector->rx.ring && !q_vector->tx.ring) 3397 continue; 3398 3399 /* clear the affinity_mask in the IRQ descriptor */ 3400 irq_set_affinity_hint(entry->vector, NULL); 3401 3402 free_irq(entry->vector, q_vector); 3403 } 3404 3405 free_irq(adapter->msix_entries[vector].vector, adapter); 3406 } 3407 3408 /** 3409 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3410 * @adapter: board private structure 3411 **/ 3412 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3413 { 3414 switch (adapter->hw.mac.type) { 3415 case ixgbe_mac_82598EB: 3416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3417 break; 3418 case ixgbe_mac_82599EB: 3419 case ixgbe_mac_X540: 3420 case ixgbe_mac_X550: 3421 case ixgbe_mac_X550EM_x: 3422 case ixgbe_mac_x550em_a: 3423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3426 break; 3427 default: 3428 break; 3429 } 3430 IXGBE_WRITE_FLUSH(&adapter->hw); 3431 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3432 int vector; 3433 3434 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3435 synchronize_irq(adapter->msix_entries[vector].vector); 3436 3437 synchronize_irq(adapter->msix_entries[vector++].vector); 3438 } else { 3439 synchronize_irq(adapter->pdev->irq); 3440 } 3441 } 3442 3443 /** 3444 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3445 * @adapter: board private structure 3446 * 3447 **/ 3448 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3449 { 3450 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3451 3452 ixgbe_write_eitr(q_vector); 3453 3454 ixgbe_set_ivar(adapter, 0, 0, 0); 3455 ixgbe_set_ivar(adapter, 1, 0, 0); 3456 3457 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3458 } 3459 3460 /** 3461 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3462 * @adapter: board private structure 3463 * @ring: structure containing ring specific data 3464 * 3465 * Configure the Tx descriptor ring after a reset. 3466 **/ 3467 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3468 struct ixgbe_ring *ring) 3469 { 3470 struct ixgbe_hw *hw = &adapter->hw; 3471 u64 tdba = ring->dma; 3472 int wait_loop = 10; 3473 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3474 u8 reg_idx = ring->reg_idx; 3475 3476 ring->xsk_umem = NULL; 3477 if (ring_is_xdp(ring)) 3478 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 3479 3480 /* disable queue to avoid issues while updating state */ 3481 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3482 IXGBE_WRITE_FLUSH(hw); 3483 3484 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3485 (tdba & DMA_BIT_MASK(32))); 3486 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3487 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3488 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3489 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3490 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3491 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3492 3493 /* 3494 * set WTHRESH to encourage burst writeback, it should not be set 3495 * higher than 1 when: 3496 * - ITR is 0 as it could cause false TX hangs 3497 * - ITR is set to > 100k int/sec and BQL is enabled 3498 * 3499 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3500 * to or less than the number of on chip descriptors, which is 3501 * currently 40. 3502 */ 3503 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3504 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3505 else 3506 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3507 3508 /* 3509 * Setting PTHRESH to 32 both improves performance 3510 * and avoids a TX hang with DFP enabled 3511 */ 3512 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3513 32; /* PTHRESH = 32 */ 3514 3515 /* reinitialize flowdirector state */ 3516 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3517 ring->atr_sample_rate = adapter->atr_sample_rate; 3518 ring->atr_count = 0; 3519 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3520 } else { 3521 ring->atr_sample_rate = 0; 3522 } 3523 3524 /* initialize XPS */ 3525 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3526 struct ixgbe_q_vector *q_vector = ring->q_vector; 3527 3528 if (q_vector) 3529 netif_set_xps_queue(ring->netdev, 3530 &q_vector->affinity_mask, 3531 ring->queue_index); 3532 } 3533 3534 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3535 3536 /* reinitialize tx_buffer_info */ 3537 memset(ring->tx_buffer_info, 0, 3538 sizeof(struct ixgbe_tx_buffer) * ring->count); 3539 3540 /* enable queue */ 3541 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3542 3543 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3544 if (hw->mac.type == ixgbe_mac_82598EB && 3545 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3546 return; 3547 3548 /* poll to verify queue is enabled */ 3549 do { 3550 usleep_range(1000, 2000); 3551 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3552 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3553 if (!wait_loop) 3554 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3555 } 3556 3557 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3558 { 3559 struct ixgbe_hw *hw = &adapter->hw; 3560 u32 rttdcs, mtqc; 3561 u8 tcs = adapter->hw_tcs; 3562 3563 if (hw->mac.type == ixgbe_mac_82598EB) 3564 return; 3565 3566 /* disable the arbiter while setting MTQC */ 3567 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3568 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3569 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3570 3571 /* set transmit pool layout */ 3572 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3573 mtqc = IXGBE_MTQC_VT_ENA; 3574 if (tcs > 4) 3575 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3576 else if (tcs > 1) 3577 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3578 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3579 IXGBE_82599_VMDQ_4Q_MASK) 3580 mtqc |= IXGBE_MTQC_32VF; 3581 else 3582 mtqc |= IXGBE_MTQC_64VF; 3583 } else { 3584 if (tcs > 4) { 3585 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3586 } else if (tcs > 1) { 3587 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3588 } else { 3589 u8 max_txq = adapter->num_tx_queues + 3590 adapter->num_xdp_queues; 3591 if (max_txq > 63) 3592 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3593 else 3594 mtqc = IXGBE_MTQC_64Q_1PB; 3595 } 3596 } 3597 3598 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3599 3600 /* Enable Security TX Buffer IFG for multiple pb */ 3601 if (tcs) { 3602 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3603 sectx |= IXGBE_SECTX_DCB; 3604 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3605 } 3606 3607 /* re-enable the arbiter */ 3608 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3609 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3610 } 3611 3612 /** 3613 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3614 * @adapter: board private structure 3615 * 3616 * Configure the Tx unit of the MAC after a reset. 3617 **/ 3618 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3619 { 3620 struct ixgbe_hw *hw = &adapter->hw; 3621 u32 dmatxctl; 3622 u32 i; 3623 3624 ixgbe_setup_mtqc(adapter); 3625 3626 if (hw->mac.type != ixgbe_mac_82598EB) { 3627 /* DMATXCTL.EN must be before Tx queues are enabled */ 3628 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3629 dmatxctl |= IXGBE_DMATXCTL_TE; 3630 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3631 } 3632 3633 /* Setup the HW Tx Head and Tail descriptor pointers */ 3634 for (i = 0; i < adapter->num_tx_queues; i++) 3635 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3636 for (i = 0; i < adapter->num_xdp_queues; i++) 3637 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3638 } 3639 3640 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3641 struct ixgbe_ring *ring) 3642 { 3643 struct ixgbe_hw *hw = &adapter->hw; 3644 u8 reg_idx = ring->reg_idx; 3645 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3646 3647 srrctl |= IXGBE_SRRCTL_DROP_EN; 3648 3649 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3650 } 3651 3652 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3653 struct ixgbe_ring *ring) 3654 { 3655 struct ixgbe_hw *hw = &adapter->hw; 3656 u8 reg_idx = ring->reg_idx; 3657 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3658 3659 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3660 3661 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3662 } 3663 3664 #ifdef CONFIG_IXGBE_DCB 3665 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3666 #else 3667 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3668 #endif 3669 { 3670 int i; 3671 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3672 3673 if (adapter->ixgbe_ieee_pfc) 3674 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3675 3676 /* 3677 * We should set the drop enable bit if: 3678 * SR-IOV is enabled 3679 * or 3680 * Number of Rx queues > 1 and flow control is disabled 3681 * 3682 * This allows us to avoid head of line blocking for security 3683 * and performance reasons. 3684 */ 3685 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3686 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3687 for (i = 0; i < adapter->num_rx_queues; i++) 3688 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3689 } else { 3690 for (i = 0; i < adapter->num_rx_queues; i++) 3691 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3692 } 3693 } 3694 3695 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3696 3697 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3698 struct ixgbe_ring *rx_ring) 3699 { 3700 struct ixgbe_hw *hw = &adapter->hw; 3701 u32 srrctl; 3702 u8 reg_idx = rx_ring->reg_idx; 3703 3704 if (hw->mac.type == ixgbe_mac_82598EB) { 3705 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3706 3707 /* 3708 * if VMDq is not active we must program one srrctl register 3709 * per RSS queue since we have enabled RDRXCTL.MVMEN 3710 */ 3711 reg_idx &= mask; 3712 } 3713 3714 /* configure header buffer length, needed for RSC */ 3715 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3716 3717 /* configure the packet buffer length */ 3718 if (rx_ring->xsk_umem) { 3719 u32 xsk_buf_len = xsk_umem_get_rx_frame_size(rx_ring->xsk_umem); 3720 3721 /* If the MAC support setting RXDCTL.RLPML, the 3722 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3723 * RXDCTL.RLPML is set to the actual UMEM buffer 3724 * size. If not, then we are stuck with a 1k buffer 3725 * size resolution. In this case frames larger than 3726 * the UMEM buffer size viewed in a 1k resolution will 3727 * be dropped. 3728 */ 3729 if (hw->mac.type != ixgbe_mac_82599EB) 3730 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3731 else 3732 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3733 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3734 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3735 } else { 3736 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3737 } 3738 3739 /* configure descriptor type */ 3740 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3741 3742 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3743 } 3744 3745 /** 3746 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3747 * @adapter: device handle 3748 * 3749 * - 82598/82599/X540: 128 3750 * - X550(non-SRIOV mode): 512 3751 * - X550(SRIOV mode): 64 3752 */ 3753 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3754 { 3755 if (adapter->hw.mac.type < ixgbe_mac_X550) 3756 return 128; 3757 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3758 return 64; 3759 else 3760 return 512; 3761 } 3762 3763 /** 3764 * ixgbe_store_key - Write the RSS key to HW 3765 * @adapter: device handle 3766 * 3767 * Write the RSS key stored in adapter.rss_key to HW. 3768 */ 3769 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3770 { 3771 struct ixgbe_hw *hw = &adapter->hw; 3772 int i; 3773 3774 for (i = 0; i < 10; i++) 3775 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3776 } 3777 3778 /** 3779 * ixgbe_init_rss_key - Initialize adapter RSS key 3780 * @adapter: device handle 3781 * 3782 * Allocates and initializes the RSS key if it is not allocated. 3783 **/ 3784 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3785 { 3786 u32 *rss_key; 3787 3788 if (!adapter->rss_key) { 3789 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3790 if (unlikely(!rss_key)) 3791 return -ENOMEM; 3792 3793 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3794 adapter->rss_key = rss_key; 3795 } 3796 3797 return 0; 3798 } 3799 3800 /** 3801 * ixgbe_store_reta - Write the RETA table to HW 3802 * @adapter: device handle 3803 * 3804 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3805 */ 3806 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3807 { 3808 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3809 struct ixgbe_hw *hw = &adapter->hw; 3810 u32 reta = 0; 3811 u32 indices_multi; 3812 u8 *indir_tbl = adapter->rss_indir_tbl; 3813 3814 /* Fill out the redirection table as follows: 3815 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3816 * indices. 3817 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3818 * - X550: 8 bit wide entries containing 6 bit RSS index 3819 */ 3820 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3821 indices_multi = 0x11; 3822 else 3823 indices_multi = 0x1; 3824 3825 /* Write redirection table to HW */ 3826 for (i = 0; i < reta_entries; i++) { 3827 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3828 if ((i & 3) == 3) { 3829 if (i < 128) 3830 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3831 else 3832 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3833 reta); 3834 reta = 0; 3835 } 3836 } 3837 } 3838 3839 /** 3840 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3841 * @adapter: device handle 3842 * 3843 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3844 */ 3845 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3846 { 3847 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3848 struct ixgbe_hw *hw = &adapter->hw; 3849 u32 vfreta = 0; 3850 3851 /* Write redirection table to HW */ 3852 for (i = 0; i < reta_entries; i++) { 3853 u16 pool = adapter->num_rx_pools; 3854 3855 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3856 if ((i & 3) != 3) 3857 continue; 3858 3859 while (pool--) 3860 IXGBE_WRITE_REG(hw, 3861 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3862 vfreta); 3863 vfreta = 0; 3864 } 3865 } 3866 3867 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3868 { 3869 u32 i, j; 3870 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3871 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3872 3873 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3874 * make full use of any rings they may have. We will use the 3875 * PSRTYPE register to control how many rings we use within the PF. 3876 */ 3877 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3878 rss_i = 4; 3879 3880 /* Fill out hash function seeds */ 3881 ixgbe_store_key(adapter); 3882 3883 /* Fill out redirection table */ 3884 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3885 3886 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3887 if (j == rss_i) 3888 j = 0; 3889 3890 adapter->rss_indir_tbl[i] = j; 3891 } 3892 3893 ixgbe_store_reta(adapter); 3894 } 3895 3896 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3897 { 3898 struct ixgbe_hw *hw = &adapter->hw; 3899 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3900 int i, j; 3901 3902 /* Fill out hash function seeds */ 3903 for (i = 0; i < 10; i++) { 3904 u16 pool = adapter->num_rx_pools; 3905 3906 while (pool--) 3907 IXGBE_WRITE_REG(hw, 3908 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3909 *(adapter->rss_key + i)); 3910 } 3911 3912 /* Fill out the redirection table */ 3913 for (i = 0, j = 0; i < 64; i++, j++) { 3914 if (j == rss_i) 3915 j = 0; 3916 3917 adapter->rss_indir_tbl[i] = j; 3918 } 3919 3920 ixgbe_store_vfreta(adapter); 3921 } 3922 3923 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3924 { 3925 struct ixgbe_hw *hw = &adapter->hw; 3926 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3927 u32 rxcsum; 3928 3929 /* Disable indicating checksum in descriptor, enables RSS hash */ 3930 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3931 rxcsum |= IXGBE_RXCSUM_PCSD; 3932 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3933 3934 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3935 if (adapter->ring_feature[RING_F_RSS].mask) 3936 mrqc = IXGBE_MRQC_RSSEN; 3937 } else { 3938 u8 tcs = adapter->hw_tcs; 3939 3940 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3941 if (tcs > 4) 3942 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3943 else if (tcs > 1) 3944 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3945 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3946 IXGBE_82599_VMDQ_4Q_MASK) 3947 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3948 else 3949 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3950 3951 /* Enable L3/L4 for Tx Switched packets only for X550, 3952 * older devices do not support this feature 3953 */ 3954 if (hw->mac.type >= ixgbe_mac_X550) 3955 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3956 } else { 3957 if (tcs > 4) 3958 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3959 else if (tcs > 1) 3960 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3961 else 3962 mrqc = IXGBE_MRQC_RSSEN; 3963 } 3964 } 3965 3966 /* Perform hash on these packet types */ 3967 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3968 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3969 IXGBE_MRQC_RSS_FIELD_IPV6 | 3970 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3971 3972 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3973 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3974 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3975 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3976 3977 if ((hw->mac.type >= ixgbe_mac_X550) && 3978 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3979 u16 pool = adapter->num_rx_pools; 3980 3981 /* Enable VF RSS mode */ 3982 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3983 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3984 3985 /* Setup RSS through the VF registers */ 3986 ixgbe_setup_vfreta(adapter); 3987 vfmrqc = IXGBE_MRQC_RSSEN; 3988 vfmrqc |= rss_field; 3989 3990 while (pool--) 3991 IXGBE_WRITE_REG(hw, 3992 IXGBE_PFVFMRQC(VMDQ_P(pool)), 3993 vfmrqc); 3994 } else { 3995 ixgbe_setup_reta(adapter); 3996 mrqc |= rss_field; 3997 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3998 } 3999 } 4000 4001 /** 4002 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4003 * @adapter: address of board private structure 4004 * @ring: structure containing ring specific data 4005 **/ 4006 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4007 struct ixgbe_ring *ring) 4008 { 4009 struct ixgbe_hw *hw = &adapter->hw; 4010 u32 rscctrl; 4011 u8 reg_idx = ring->reg_idx; 4012 4013 if (!ring_is_rsc_enabled(ring)) 4014 return; 4015 4016 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4017 rscctrl |= IXGBE_RSCCTL_RSCEN; 4018 /* 4019 * we must limit the number of descriptors so that the 4020 * total size of max desc * buf_len is not greater 4021 * than 65536 4022 */ 4023 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4024 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4025 } 4026 4027 #define IXGBE_MAX_RX_DESC_POLL 10 4028 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4029 struct ixgbe_ring *ring) 4030 { 4031 struct ixgbe_hw *hw = &adapter->hw; 4032 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4033 u32 rxdctl; 4034 u8 reg_idx = ring->reg_idx; 4035 4036 if (ixgbe_removed(hw->hw_addr)) 4037 return; 4038 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4039 if (hw->mac.type == ixgbe_mac_82598EB && 4040 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4041 return; 4042 4043 do { 4044 usleep_range(1000, 2000); 4045 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4046 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4047 4048 if (!wait_loop) { 4049 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4050 "the polling period\n", reg_idx); 4051 } 4052 } 4053 4054 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4055 struct ixgbe_ring *ring) 4056 { 4057 struct ixgbe_hw *hw = &adapter->hw; 4058 union ixgbe_adv_rx_desc *rx_desc; 4059 u64 rdba = ring->dma; 4060 u32 rxdctl; 4061 u8 reg_idx = ring->reg_idx; 4062 4063 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4064 ring->xsk_umem = ixgbe_xsk_umem(adapter, ring); 4065 if (ring->xsk_umem) { 4066 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4067 MEM_TYPE_XSK_BUFF_POOL, 4068 NULL)); 4069 xsk_buff_set_rxq_info(ring->xsk_umem, &ring->xdp_rxq); 4070 } else { 4071 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4072 MEM_TYPE_PAGE_SHARED, NULL)); 4073 } 4074 4075 /* disable queue to avoid use of these values while updating state */ 4076 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4077 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4078 4079 /* write value back with RXDCTL.ENABLE bit cleared */ 4080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4081 IXGBE_WRITE_FLUSH(hw); 4082 4083 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4084 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4085 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4086 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4087 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4088 IXGBE_WRITE_FLUSH(hw); 4089 4090 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4091 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4092 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4093 4094 ixgbe_configure_srrctl(adapter, ring); 4095 ixgbe_configure_rscctl(adapter, ring); 4096 4097 if (hw->mac.type == ixgbe_mac_82598EB) { 4098 /* 4099 * enable cache line friendly hardware writes: 4100 * PTHRESH=32 descriptors (half the internal cache), 4101 * this also removes ugly rx_no_buffer_count increment 4102 * HTHRESH=4 descriptors (to minimize latency on fetch) 4103 * WTHRESH=8 burst writeback up to two cache lines 4104 */ 4105 rxdctl &= ~0x3FFFFF; 4106 rxdctl |= 0x080420; 4107 #if (PAGE_SIZE < 8192) 4108 /* RXDCTL.RLPML does not work on 82599 */ 4109 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4110 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4111 IXGBE_RXDCTL_RLPML_EN); 4112 4113 /* Limit the maximum frame size so we don't overrun the skb. 4114 * This can happen in SRIOV mode when the MTU of the VF is 4115 * higher than the MTU of the PF. 4116 */ 4117 if (ring_uses_build_skb(ring) && 4118 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4119 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4120 IXGBE_RXDCTL_RLPML_EN; 4121 #endif 4122 } 4123 4124 if (ring->xsk_umem && hw->mac.type != ixgbe_mac_82599EB) { 4125 u32 xsk_buf_len = xsk_umem_get_rx_frame_size(ring->xsk_umem); 4126 4127 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4128 IXGBE_RXDCTL_RLPML_EN); 4129 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4130 4131 ring->rx_buf_len = xsk_buf_len; 4132 } 4133 4134 /* initialize rx_buffer_info */ 4135 memset(ring->rx_buffer_info, 0, 4136 sizeof(struct ixgbe_rx_buffer) * ring->count); 4137 4138 /* initialize Rx descriptor 0 */ 4139 rx_desc = IXGBE_RX_DESC(ring, 0); 4140 rx_desc->wb.upper.length = 0; 4141 4142 /* enable receive descriptor ring */ 4143 rxdctl |= IXGBE_RXDCTL_ENABLE; 4144 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4145 4146 ixgbe_rx_desc_queue_enable(adapter, ring); 4147 if (ring->xsk_umem) 4148 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4149 else 4150 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4151 } 4152 4153 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4154 { 4155 struct ixgbe_hw *hw = &adapter->hw; 4156 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4157 u16 pool = adapter->num_rx_pools; 4158 4159 /* PSRTYPE must be initialized in non 82598 adapters */ 4160 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4161 IXGBE_PSRTYPE_UDPHDR | 4162 IXGBE_PSRTYPE_IPV4HDR | 4163 IXGBE_PSRTYPE_L2HDR | 4164 IXGBE_PSRTYPE_IPV6HDR; 4165 4166 if (hw->mac.type == ixgbe_mac_82598EB) 4167 return; 4168 4169 if (rss_i > 3) 4170 psrtype |= 2u << 29; 4171 else if (rss_i > 1) 4172 psrtype |= 1u << 29; 4173 4174 while (pool--) 4175 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4176 } 4177 4178 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4179 { 4180 struct ixgbe_hw *hw = &adapter->hw; 4181 u16 pool = adapter->num_rx_pools; 4182 u32 reg_offset, vf_shift, vmolr; 4183 u32 gcr_ext, vmdctl; 4184 int i; 4185 4186 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4187 return; 4188 4189 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4190 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4191 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4192 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4193 vmdctl |= IXGBE_VT_CTL_REPLEN; 4194 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4195 4196 /* accept untagged packets until a vlan tag is 4197 * specifically set for the VMDQ queue/pool 4198 */ 4199 vmolr = IXGBE_VMOLR_AUPE; 4200 while (pool--) 4201 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4202 4203 vf_shift = VMDQ_P(0) % 32; 4204 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4205 4206 /* Enable only the PF's pool for Tx/Rx */ 4207 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4208 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4209 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4210 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4211 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4212 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4213 4214 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4215 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4216 4217 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4218 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4219 4220 /* 4221 * Set up VF register offsets for selected VT Mode, 4222 * i.e. 32 or 64 VFs for SR-IOV 4223 */ 4224 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4225 case IXGBE_82599_VMDQ_8Q_MASK: 4226 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4227 break; 4228 case IXGBE_82599_VMDQ_4Q_MASK: 4229 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4230 break; 4231 default: 4232 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4233 break; 4234 } 4235 4236 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4237 4238 for (i = 0; i < adapter->num_vfs; i++) { 4239 /* configure spoof checking */ 4240 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4241 adapter->vfinfo[i].spoofchk_enabled); 4242 4243 /* Enable/Disable RSS query feature */ 4244 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4245 adapter->vfinfo[i].rss_query_enabled); 4246 } 4247 } 4248 4249 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4250 { 4251 struct ixgbe_hw *hw = &adapter->hw; 4252 struct net_device *netdev = adapter->netdev; 4253 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4254 struct ixgbe_ring *rx_ring; 4255 int i; 4256 u32 mhadd, hlreg0; 4257 4258 #ifdef IXGBE_FCOE 4259 /* adjust max frame to be able to do baby jumbo for FCoE */ 4260 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4261 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4262 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4263 4264 #endif /* IXGBE_FCOE */ 4265 4266 /* adjust max frame to be at least the size of a standard frame */ 4267 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4268 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4269 4270 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4271 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4272 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4273 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4274 4275 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4276 } 4277 4278 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4279 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4280 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4281 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4282 4283 /* 4284 * Setup the HW Rx Head and Tail Descriptor Pointers and 4285 * the Base and Length of the Rx Descriptor Ring 4286 */ 4287 for (i = 0; i < adapter->num_rx_queues; i++) { 4288 rx_ring = adapter->rx_ring[i]; 4289 4290 clear_ring_rsc_enabled(rx_ring); 4291 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4292 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4293 4294 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4295 set_ring_rsc_enabled(rx_ring); 4296 4297 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4298 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4299 4300 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4301 continue; 4302 4303 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4304 4305 #if (PAGE_SIZE < 8192) 4306 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4307 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4308 4309 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4310 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4311 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4312 #endif 4313 } 4314 } 4315 4316 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4317 { 4318 struct ixgbe_hw *hw = &adapter->hw; 4319 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4320 4321 switch (hw->mac.type) { 4322 case ixgbe_mac_82598EB: 4323 /* 4324 * For VMDq support of different descriptor types or 4325 * buffer sizes through the use of multiple SRRCTL 4326 * registers, RDRXCTL.MVMEN must be set to 1 4327 * 4328 * also, the manual doesn't mention it clearly but DCA hints 4329 * will only use queue 0's tags unless this bit is set. Side 4330 * effects of setting this bit are only that SRRCTL must be 4331 * fully programmed [0..15] 4332 */ 4333 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4334 break; 4335 case ixgbe_mac_X550: 4336 case ixgbe_mac_X550EM_x: 4337 case ixgbe_mac_x550em_a: 4338 if (adapter->num_vfs) 4339 rdrxctl |= IXGBE_RDRXCTL_PSP; 4340 /* fall through */ 4341 case ixgbe_mac_82599EB: 4342 case ixgbe_mac_X540: 4343 /* Disable RSC for ACK packets */ 4344 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4345 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4346 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4347 /* hardware requires some bits to be set by default */ 4348 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4349 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4350 break; 4351 default: 4352 /* We should do nothing since we don't know this hardware */ 4353 return; 4354 } 4355 4356 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4357 } 4358 4359 /** 4360 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4361 * @adapter: board private structure 4362 * 4363 * Configure the Rx unit of the MAC after a reset. 4364 **/ 4365 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4366 { 4367 struct ixgbe_hw *hw = &adapter->hw; 4368 int i; 4369 u32 rxctrl, rfctl; 4370 4371 /* disable receives while setting up the descriptors */ 4372 hw->mac.ops.disable_rx(hw); 4373 4374 ixgbe_setup_psrtype(adapter); 4375 ixgbe_setup_rdrxctl(adapter); 4376 4377 /* RSC Setup */ 4378 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4379 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4380 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4381 rfctl |= IXGBE_RFCTL_RSC_DIS; 4382 4383 /* disable NFS filtering */ 4384 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4385 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4386 4387 /* Program registers for the distribution of queues */ 4388 ixgbe_setup_mrqc(adapter); 4389 4390 /* set_rx_buffer_len must be called before ring initialization */ 4391 ixgbe_set_rx_buffer_len(adapter); 4392 4393 /* 4394 * Setup the HW Rx Head and Tail Descriptor Pointers and 4395 * the Base and Length of the Rx Descriptor Ring 4396 */ 4397 for (i = 0; i < adapter->num_rx_queues; i++) 4398 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4399 4400 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4401 /* disable drop enable for 82598 parts */ 4402 if (hw->mac.type == ixgbe_mac_82598EB) 4403 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4404 4405 /* enable all receives */ 4406 rxctrl |= IXGBE_RXCTRL_RXEN; 4407 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4408 } 4409 4410 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4411 __be16 proto, u16 vid) 4412 { 4413 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4414 struct ixgbe_hw *hw = &adapter->hw; 4415 4416 /* add VID to filter table */ 4417 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4418 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4419 4420 set_bit(vid, adapter->active_vlans); 4421 4422 return 0; 4423 } 4424 4425 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4426 { 4427 u32 vlvf; 4428 int idx; 4429 4430 /* short cut the special case */ 4431 if (vlan == 0) 4432 return 0; 4433 4434 /* Search for the vlan id in the VLVF entries */ 4435 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4436 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4437 if ((vlvf & VLAN_VID_MASK) == vlan) 4438 break; 4439 } 4440 4441 return idx; 4442 } 4443 4444 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4445 { 4446 struct ixgbe_hw *hw = &adapter->hw; 4447 u32 bits, word; 4448 int idx; 4449 4450 idx = ixgbe_find_vlvf_entry(hw, vid); 4451 if (!idx) 4452 return; 4453 4454 /* See if any other pools are set for this VLAN filter 4455 * entry other than the PF. 4456 */ 4457 word = idx * 2 + (VMDQ_P(0) / 32); 4458 bits = ~BIT(VMDQ_P(0) % 32); 4459 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4460 4461 /* Disable the filter so this falls into the default pool. */ 4462 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4463 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4464 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4465 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4466 } 4467 } 4468 4469 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4470 __be16 proto, u16 vid) 4471 { 4472 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4473 struct ixgbe_hw *hw = &adapter->hw; 4474 4475 /* remove VID from filter table */ 4476 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4477 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4478 4479 clear_bit(vid, adapter->active_vlans); 4480 4481 return 0; 4482 } 4483 4484 /** 4485 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4486 * @adapter: driver data 4487 */ 4488 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4489 { 4490 struct ixgbe_hw *hw = &adapter->hw; 4491 u32 vlnctrl; 4492 int i, j; 4493 4494 switch (hw->mac.type) { 4495 case ixgbe_mac_82598EB: 4496 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4497 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4498 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4499 break; 4500 case ixgbe_mac_82599EB: 4501 case ixgbe_mac_X540: 4502 case ixgbe_mac_X550: 4503 case ixgbe_mac_X550EM_x: 4504 case ixgbe_mac_x550em_a: 4505 for (i = 0; i < adapter->num_rx_queues; i++) { 4506 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4507 4508 if (!netif_is_ixgbe(ring->netdev)) 4509 continue; 4510 4511 j = ring->reg_idx; 4512 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4513 vlnctrl &= ~IXGBE_RXDCTL_VME; 4514 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4515 } 4516 break; 4517 default: 4518 break; 4519 } 4520 } 4521 4522 /** 4523 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4524 * @adapter: driver data 4525 */ 4526 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4527 { 4528 struct ixgbe_hw *hw = &adapter->hw; 4529 u32 vlnctrl; 4530 int i, j; 4531 4532 switch (hw->mac.type) { 4533 case ixgbe_mac_82598EB: 4534 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4535 vlnctrl |= IXGBE_VLNCTRL_VME; 4536 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4537 break; 4538 case ixgbe_mac_82599EB: 4539 case ixgbe_mac_X540: 4540 case ixgbe_mac_X550: 4541 case ixgbe_mac_X550EM_x: 4542 case ixgbe_mac_x550em_a: 4543 for (i = 0; i < adapter->num_rx_queues; i++) { 4544 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4545 4546 if (!netif_is_ixgbe(ring->netdev)) 4547 continue; 4548 4549 j = ring->reg_idx; 4550 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4551 vlnctrl |= IXGBE_RXDCTL_VME; 4552 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4553 } 4554 break; 4555 default: 4556 break; 4557 } 4558 } 4559 4560 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4561 { 4562 struct ixgbe_hw *hw = &adapter->hw; 4563 u32 vlnctrl, i; 4564 4565 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4566 4567 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4568 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4569 vlnctrl |= IXGBE_VLNCTRL_VFE; 4570 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4571 } else { 4572 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4573 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4574 return; 4575 } 4576 4577 /* Nothing to do for 82598 */ 4578 if (hw->mac.type == ixgbe_mac_82598EB) 4579 return; 4580 4581 /* We are already in VLAN promisc, nothing to do */ 4582 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4583 return; 4584 4585 /* Set flag so we don't redo unnecessary work */ 4586 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4587 4588 /* Add PF to all active pools */ 4589 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4590 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4591 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4592 4593 vlvfb |= BIT(VMDQ_P(0) % 32); 4594 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4595 } 4596 4597 /* Set all bits in the VLAN filter table array */ 4598 for (i = hw->mac.vft_size; i--;) 4599 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4600 } 4601 4602 #define VFTA_BLOCK_SIZE 8 4603 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4604 { 4605 struct ixgbe_hw *hw = &adapter->hw; 4606 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4607 u32 vid_start = vfta_offset * 32; 4608 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4609 u32 i, vid, word, bits; 4610 4611 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4612 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4613 4614 /* pull VLAN ID from VLVF */ 4615 vid = vlvf & VLAN_VID_MASK; 4616 4617 /* only concern outselves with a certain range */ 4618 if (vid < vid_start || vid >= vid_end) 4619 continue; 4620 4621 if (vlvf) { 4622 /* record VLAN ID in VFTA */ 4623 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4624 4625 /* if PF is part of this then continue */ 4626 if (test_bit(vid, adapter->active_vlans)) 4627 continue; 4628 } 4629 4630 /* remove PF from the pool */ 4631 word = i * 2 + VMDQ_P(0) / 32; 4632 bits = ~BIT(VMDQ_P(0) % 32); 4633 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4634 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4635 } 4636 4637 /* extract values from active_vlans and write back to VFTA */ 4638 for (i = VFTA_BLOCK_SIZE; i--;) { 4639 vid = (vfta_offset + i) * 32; 4640 word = vid / BITS_PER_LONG; 4641 bits = vid % BITS_PER_LONG; 4642 4643 vfta[i] |= adapter->active_vlans[word] >> bits; 4644 4645 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4646 } 4647 } 4648 4649 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4650 { 4651 struct ixgbe_hw *hw = &adapter->hw; 4652 u32 vlnctrl, i; 4653 4654 /* Set VLAN filtering to enabled */ 4655 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4656 vlnctrl |= IXGBE_VLNCTRL_VFE; 4657 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4658 4659 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4660 hw->mac.type == ixgbe_mac_82598EB) 4661 return; 4662 4663 /* We are not in VLAN promisc, nothing to do */ 4664 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4665 return; 4666 4667 /* Set flag so we don't redo unnecessary work */ 4668 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4669 4670 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4671 ixgbe_scrub_vfta(adapter, i); 4672 } 4673 4674 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4675 { 4676 u16 vid = 1; 4677 4678 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4679 4680 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4681 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4682 } 4683 4684 /** 4685 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4686 * @netdev: network interface device structure 4687 * 4688 * Writes multicast address list to the MTA hash table. 4689 * Returns: -ENOMEM on failure 4690 * 0 on no addresses written 4691 * X on writing X addresses to MTA 4692 **/ 4693 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4694 { 4695 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4696 struct ixgbe_hw *hw = &adapter->hw; 4697 4698 if (!netif_running(netdev)) 4699 return 0; 4700 4701 if (hw->mac.ops.update_mc_addr_list) 4702 hw->mac.ops.update_mc_addr_list(hw, netdev); 4703 else 4704 return -ENOMEM; 4705 4706 #ifdef CONFIG_PCI_IOV 4707 ixgbe_restore_vf_multicasts(adapter); 4708 #endif 4709 4710 return netdev_mc_count(netdev); 4711 } 4712 4713 #ifdef CONFIG_PCI_IOV 4714 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4715 { 4716 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4717 struct ixgbe_hw *hw = &adapter->hw; 4718 int i; 4719 4720 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4721 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4722 4723 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4724 hw->mac.ops.set_rar(hw, i, 4725 mac_table->addr, 4726 mac_table->pool, 4727 IXGBE_RAH_AV); 4728 else 4729 hw->mac.ops.clear_rar(hw, i); 4730 } 4731 } 4732 4733 #endif 4734 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4735 { 4736 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4737 struct ixgbe_hw *hw = &adapter->hw; 4738 int i; 4739 4740 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4741 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4742 continue; 4743 4744 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4745 4746 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4747 hw->mac.ops.set_rar(hw, i, 4748 mac_table->addr, 4749 mac_table->pool, 4750 IXGBE_RAH_AV); 4751 else 4752 hw->mac.ops.clear_rar(hw, i); 4753 } 4754 } 4755 4756 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4757 { 4758 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4759 struct ixgbe_hw *hw = &adapter->hw; 4760 int i; 4761 4762 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4763 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4764 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4765 } 4766 4767 ixgbe_sync_mac_table(adapter); 4768 } 4769 4770 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4771 { 4772 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4773 struct ixgbe_hw *hw = &adapter->hw; 4774 int i, count = 0; 4775 4776 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4777 /* do not count default RAR as available */ 4778 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4779 continue; 4780 4781 /* only count unused and addresses that belong to us */ 4782 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4783 if (mac_table->pool != pool) 4784 continue; 4785 } 4786 4787 count++; 4788 } 4789 4790 return count; 4791 } 4792 4793 /* this function destroys the first RAR entry */ 4794 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4795 { 4796 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4797 struct ixgbe_hw *hw = &adapter->hw; 4798 4799 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4800 mac_table->pool = VMDQ_P(0); 4801 4802 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4803 4804 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4805 IXGBE_RAH_AV); 4806 } 4807 4808 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4809 const u8 *addr, u16 pool) 4810 { 4811 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4812 struct ixgbe_hw *hw = &adapter->hw; 4813 int i; 4814 4815 if (is_zero_ether_addr(addr)) 4816 return -EINVAL; 4817 4818 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4819 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4820 continue; 4821 4822 ether_addr_copy(mac_table->addr, addr); 4823 mac_table->pool = pool; 4824 4825 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4826 IXGBE_MAC_STATE_IN_USE; 4827 4828 ixgbe_sync_mac_table(adapter); 4829 4830 return i; 4831 } 4832 4833 return -ENOMEM; 4834 } 4835 4836 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4837 const u8 *addr, u16 pool) 4838 { 4839 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4840 struct ixgbe_hw *hw = &adapter->hw; 4841 int i; 4842 4843 if (is_zero_ether_addr(addr)) 4844 return -EINVAL; 4845 4846 /* search table for addr, if found clear IN_USE flag and sync */ 4847 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4848 /* we can only delete an entry if it is in use */ 4849 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4850 continue; 4851 /* we only care about entries that belong to the given pool */ 4852 if (mac_table->pool != pool) 4853 continue; 4854 /* we only care about a specific MAC address */ 4855 if (!ether_addr_equal(addr, mac_table->addr)) 4856 continue; 4857 4858 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4859 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4860 4861 ixgbe_sync_mac_table(adapter); 4862 4863 return 0; 4864 } 4865 4866 return -ENOMEM; 4867 } 4868 4869 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4870 { 4871 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4872 int ret; 4873 4874 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4875 4876 return min_t(int, ret, 0); 4877 } 4878 4879 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4880 { 4881 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4882 4883 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4884 4885 return 0; 4886 } 4887 4888 /** 4889 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4890 * @netdev: network interface device structure 4891 * 4892 * The set_rx_method entry point is called whenever the unicast/multicast 4893 * address list or the network interface flags are updated. This routine is 4894 * responsible for configuring the hardware for proper unicast, multicast and 4895 * promiscuous mode. 4896 **/ 4897 void ixgbe_set_rx_mode(struct net_device *netdev) 4898 { 4899 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4900 struct ixgbe_hw *hw = &adapter->hw; 4901 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4902 netdev_features_t features = netdev->features; 4903 int count; 4904 4905 /* Check for Promiscuous and All Multicast modes */ 4906 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4907 4908 /* set all bits that we expect to always be set */ 4909 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4910 fctrl |= IXGBE_FCTRL_BAM; 4911 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4912 fctrl |= IXGBE_FCTRL_PMCF; 4913 4914 /* clear the bits we are changing the status of */ 4915 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4916 if (netdev->flags & IFF_PROMISC) { 4917 hw->addr_ctrl.user_set_promisc = true; 4918 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4919 vmolr |= IXGBE_VMOLR_MPE; 4920 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4921 } else { 4922 if (netdev->flags & IFF_ALLMULTI) { 4923 fctrl |= IXGBE_FCTRL_MPE; 4924 vmolr |= IXGBE_VMOLR_MPE; 4925 } 4926 hw->addr_ctrl.user_set_promisc = false; 4927 } 4928 4929 /* 4930 * Write addresses to available RAR registers, if there is not 4931 * sufficient space to store all the addresses then enable 4932 * unicast promiscuous mode 4933 */ 4934 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4935 fctrl |= IXGBE_FCTRL_UPE; 4936 vmolr |= IXGBE_VMOLR_ROPE; 4937 } 4938 4939 /* Write addresses to the MTA, if the attempt fails 4940 * then we should just turn on promiscuous mode so 4941 * that we can at least receive multicast traffic 4942 */ 4943 count = ixgbe_write_mc_addr_list(netdev); 4944 if (count < 0) { 4945 fctrl |= IXGBE_FCTRL_MPE; 4946 vmolr |= IXGBE_VMOLR_MPE; 4947 } else if (count) { 4948 vmolr |= IXGBE_VMOLR_ROMPE; 4949 } 4950 4951 if (hw->mac.type != ixgbe_mac_82598EB) { 4952 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4953 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4954 IXGBE_VMOLR_ROPE); 4955 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4956 } 4957 4958 /* This is useful for sniffing bad packets. */ 4959 if (features & NETIF_F_RXALL) { 4960 /* UPE and MPE will be handled by normal PROMISC logic 4961 * in e1000e_set_rx_mode */ 4962 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4963 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4964 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4965 4966 fctrl &= ~(IXGBE_FCTRL_DPF); 4967 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4968 } 4969 4970 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4971 4972 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4973 ixgbe_vlan_strip_enable(adapter); 4974 else 4975 ixgbe_vlan_strip_disable(adapter); 4976 4977 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4978 ixgbe_vlan_promisc_disable(adapter); 4979 else 4980 ixgbe_vlan_promisc_enable(adapter); 4981 } 4982 4983 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4984 { 4985 int q_idx; 4986 4987 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4988 napi_enable(&adapter->q_vector[q_idx]->napi); 4989 } 4990 4991 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4992 { 4993 int q_idx; 4994 4995 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4996 napi_disable(&adapter->q_vector[q_idx]->napi); 4997 } 4998 4999 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5000 { 5001 struct ixgbe_hw *hw = &adapter->hw; 5002 u32 vxlanctrl; 5003 5004 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5005 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5006 return; 5007 5008 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5009 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5010 5011 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5012 adapter->vxlan_port = 0; 5013 5014 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5015 adapter->geneve_port = 0; 5016 } 5017 5018 #ifdef CONFIG_IXGBE_DCB 5019 /** 5020 * ixgbe_configure_dcb - Configure DCB hardware 5021 * @adapter: ixgbe adapter struct 5022 * 5023 * This is called by the driver on open to configure the DCB hardware. 5024 * This is also called by the gennetlink interface when reconfiguring 5025 * the DCB state. 5026 */ 5027 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5028 { 5029 struct ixgbe_hw *hw = &adapter->hw; 5030 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5031 5032 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5033 if (hw->mac.type == ixgbe_mac_82598EB) 5034 netif_set_gso_max_size(adapter->netdev, 65536); 5035 return; 5036 } 5037 5038 if (hw->mac.type == ixgbe_mac_82598EB) 5039 netif_set_gso_max_size(adapter->netdev, 32768); 5040 5041 #ifdef IXGBE_FCOE 5042 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5043 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5044 #endif 5045 5046 /* reconfigure the hardware */ 5047 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5048 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5049 DCB_TX_CONFIG); 5050 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5051 DCB_RX_CONFIG); 5052 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5053 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5054 ixgbe_dcb_hw_ets(&adapter->hw, 5055 adapter->ixgbe_ieee_ets, 5056 max_frame); 5057 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5058 adapter->ixgbe_ieee_pfc->pfc_en, 5059 adapter->ixgbe_ieee_ets->prio_tc); 5060 } 5061 5062 /* Enable RSS Hash per TC */ 5063 if (hw->mac.type != ixgbe_mac_82598EB) { 5064 u32 msb = 0; 5065 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5066 5067 while (rss_i) { 5068 msb++; 5069 rss_i >>= 1; 5070 } 5071 5072 /* write msb to all 8 TCs in one write */ 5073 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5074 } 5075 } 5076 #endif 5077 5078 /* Additional bittime to account for IXGBE framing */ 5079 #define IXGBE_ETH_FRAMING 20 5080 5081 /** 5082 * ixgbe_hpbthresh - calculate high water mark for flow control 5083 * 5084 * @adapter: board private structure to calculate for 5085 * @pb: packet buffer to calculate 5086 */ 5087 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5088 { 5089 struct ixgbe_hw *hw = &adapter->hw; 5090 struct net_device *dev = adapter->netdev; 5091 int link, tc, kb, marker; 5092 u32 dv_id, rx_pba; 5093 5094 /* Calculate max LAN frame size */ 5095 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5096 5097 #ifdef IXGBE_FCOE 5098 /* FCoE traffic class uses FCOE jumbo frames */ 5099 if ((dev->features & NETIF_F_FCOE_MTU) && 5100 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5101 (pb == ixgbe_fcoe_get_tc(adapter))) 5102 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5103 #endif 5104 5105 /* Calculate delay value for device */ 5106 switch (hw->mac.type) { 5107 case ixgbe_mac_X540: 5108 case ixgbe_mac_X550: 5109 case ixgbe_mac_X550EM_x: 5110 case ixgbe_mac_x550em_a: 5111 dv_id = IXGBE_DV_X540(link, tc); 5112 break; 5113 default: 5114 dv_id = IXGBE_DV(link, tc); 5115 break; 5116 } 5117 5118 /* Loopback switch introduces additional latency */ 5119 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5120 dv_id += IXGBE_B2BT(tc); 5121 5122 /* Delay value is calculated in bit times convert to KB */ 5123 kb = IXGBE_BT2KB(dv_id); 5124 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5125 5126 marker = rx_pba - kb; 5127 5128 /* It is possible that the packet buffer is not large enough 5129 * to provide required headroom. In this case throw an error 5130 * to user and a do the best we can. 5131 */ 5132 if (marker < 0) { 5133 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5134 "headroom to support flow control." 5135 "Decrease MTU or number of traffic classes\n", pb); 5136 marker = tc + 1; 5137 } 5138 5139 return marker; 5140 } 5141 5142 /** 5143 * ixgbe_lpbthresh - calculate low water mark for for flow control 5144 * 5145 * @adapter: board private structure to calculate for 5146 * @pb: packet buffer to calculate 5147 */ 5148 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5149 { 5150 struct ixgbe_hw *hw = &adapter->hw; 5151 struct net_device *dev = adapter->netdev; 5152 int tc; 5153 u32 dv_id; 5154 5155 /* Calculate max LAN frame size */ 5156 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5157 5158 #ifdef IXGBE_FCOE 5159 /* FCoE traffic class uses FCOE jumbo frames */ 5160 if ((dev->features & NETIF_F_FCOE_MTU) && 5161 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5162 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5163 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5164 #endif 5165 5166 /* Calculate delay value for device */ 5167 switch (hw->mac.type) { 5168 case ixgbe_mac_X540: 5169 case ixgbe_mac_X550: 5170 case ixgbe_mac_X550EM_x: 5171 case ixgbe_mac_x550em_a: 5172 dv_id = IXGBE_LOW_DV_X540(tc); 5173 break; 5174 default: 5175 dv_id = IXGBE_LOW_DV(tc); 5176 break; 5177 } 5178 5179 /* Delay value is calculated in bit times convert to KB */ 5180 return IXGBE_BT2KB(dv_id); 5181 } 5182 5183 /* 5184 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5185 */ 5186 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5187 { 5188 struct ixgbe_hw *hw = &adapter->hw; 5189 int num_tc = adapter->hw_tcs; 5190 int i; 5191 5192 if (!num_tc) 5193 num_tc = 1; 5194 5195 for (i = 0; i < num_tc; i++) { 5196 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5197 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5198 5199 /* Low water marks must not be larger than high water marks */ 5200 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5201 hw->fc.low_water[i] = 0; 5202 } 5203 5204 for (; i < MAX_TRAFFIC_CLASS; i++) 5205 hw->fc.high_water[i] = 0; 5206 } 5207 5208 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5209 { 5210 struct ixgbe_hw *hw = &adapter->hw; 5211 int hdrm; 5212 u8 tc = adapter->hw_tcs; 5213 5214 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5215 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5216 hdrm = 32 << adapter->fdir_pballoc; 5217 else 5218 hdrm = 0; 5219 5220 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5221 ixgbe_pbthresh_setup(adapter); 5222 } 5223 5224 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5225 { 5226 struct ixgbe_hw *hw = &adapter->hw; 5227 struct hlist_node *node2; 5228 struct ixgbe_fdir_filter *filter; 5229 u8 queue; 5230 5231 spin_lock(&adapter->fdir_perfect_lock); 5232 5233 if (!hlist_empty(&adapter->fdir_filter_list)) 5234 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5235 5236 hlist_for_each_entry_safe(filter, node2, 5237 &adapter->fdir_filter_list, fdir_node) { 5238 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5239 queue = IXGBE_FDIR_DROP_QUEUE; 5240 } else { 5241 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5242 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5243 5244 if (!vf && (ring >= adapter->num_rx_queues)) { 5245 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5246 ring); 5247 continue; 5248 } else if (vf && 5249 ((vf > adapter->num_vfs) || 5250 ring >= adapter->num_rx_queues_per_pool)) { 5251 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5252 vf, ring); 5253 continue; 5254 } 5255 5256 /* Map the ring onto the absolute queue index */ 5257 if (!vf) 5258 queue = adapter->rx_ring[ring]->reg_idx; 5259 else 5260 queue = ((vf - 1) * 5261 adapter->num_rx_queues_per_pool) + ring; 5262 } 5263 5264 ixgbe_fdir_write_perfect_filter_82599(hw, 5265 &filter->filter, filter->sw_idx, queue); 5266 } 5267 5268 spin_unlock(&adapter->fdir_perfect_lock); 5269 } 5270 5271 /** 5272 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5273 * @rx_ring: ring to free buffers from 5274 **/ 5275 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5276 { 5277 u16 i = rx_ring->next_to_clean; 5278 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5279 5280 if (rx_ring->xsk_umem) { 5281 ixgbe_xsk_clean_rx_ring(rx_ring); 5282 goto skip_free; 5283 } 5284 5285 /* Free all the Rx ring sk_buffs */ 5286 while (i != rx_ring->next_to_alloc) { 5287 if (rx_buffer->skb) { 5288 struct sk_buff *skb = rx_buffer->skb; 5289 if (IXGBE_CB(skb)->page_released) 5290 dma_unmap_page_attrs(rx_ring->dev, 5291 IXGBE_CB(skb)->dma, 5292 ixgbe_rx_pg_size(rx_ring), 5293 DMA_FROM_DEVICE, 5294 IXGBE_RX_DMA_ATTR); 5295 dev_kfree_skb(skb); 5296 } 5297 5298 /* Invalidate cache lines that may have been written to by 5299 * device so that we avoid corrupting memory. 5300 */ 5301 dma_sync_single_range_for_cpu(rx_ring->dev, 5302 rx_buffer->dma, 5303 rx_buffer->page_offset, 5304 ixgbe_rx_bufsz(rx_ring), 5305 DMA_FROM_DEVICE); 5306 5307 /* free resources associated with mapping */ 5308 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5309 ixgbe_rx_pg_size(rx_ring), 5310 DMA_FROM_DEVICE, 5311 IXGBE_RX_DMA_ATTR); 5312 __page_frag_cache_drain(rx_buffer->page, 5313 rx_buffer->pagecnt_bias); 5314 5315 i++; 5316 rx_buffer++; 5317 if (i == rx_ring->count) { 5318 i = 0; 5319 rx_buffer = rx_ring->rx_buffer_info; 5320 } 5321 } 5322 5323 skip_free: 5324 rx_ring->next_to_alloc = 0; 5325 rx_ring->next_to_clean = 0; 5326 rx_ring->next_to_use = 0; 5327 } 5328 5329 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5330 struct ixgbe_fwd_adapter *accel) 5331 { 5332 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5333 int num_tc = netdev_get_num_tc(adapter->netdev); 5334 struct net_device *vdev = accel->netdev; 5335 int i, baseq, err; 5336 5337 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5338 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5339 accel->pool, adapter->num_rx_pools, 5340 baseq, baseq + adapter->num_rx_queues_per_pool); 5341 5342 accel->rx_base_queue = baseq; 5343 accel->tx_base_queue = baseq; 5344 5345 /* record configuration for macvlan interface in vdev */ 5346 for (i = 0; i < num_tc; i++) 5347 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5348 i, rss_i, baseq + (rss_i * i)); 5349 5350 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5351 adapter->rx_ring[baseq + i]->netdev = vdev; 5352 5353 /* Guarantee all rings are updated before we update the 5354 * MAC address filter. 5355 */ 5356 wmb(); 5357 5358 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5359 * need to only treat it as an error value if it is negative. 5360 */ 5361 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5362 VMDQ_P(accel->pool)); 5363 if (err >= 0) 5364 return 0; 5365 5366 /* if we cannot add the MAC rule then disable the offload */ 5367 macvlan_release_l2fw_offload(vdev); 5368 5369 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5370 adapter->rx_ring[baseq + i]->netdev = NULL; 5371 5372 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5373 5374 /* unbind the queues and drop the subordinate channel config */ 5375 netdev_unbind_sb_channel(adapter->netdev, vdev); 5376 netdev_set_sb_channel(vdev, 0); 5377 5378 clear_bit(accel->pool, adapter->fwd_bitmask); 5379 kfree(accel); 5380 5381 return err; 5382 } 5383 5384 static int ixgbe_macvlan_up(struct net_device *vdev, void *data) 5385 { 5386 struct ixgbe_adapter *adapter = data; 5387 struct ixgbe_fwd_adapter *accel; 5388 5389 if (!netif_is_macvlan(vdev)) 5390 return 0; 5391 5392 accel = macvlan_accel_priv(vdev); 5393 if (!accel) 5394 return 0; 5395 5396 ixgbe_fwd_ring_up(adapter, accel); 5397 5398 return 0; 5399 } 5400 5401 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5402 { 5403 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5404 ixgbe_macvlan_up, adapter); 5405 } 5406 5407 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5408 { 5409 struct ixgbe_hw *hw = &adapter->hw; 5410 5411 ixgbe_configure_pb(adapter); 5412 #ifdef CONFIG_IXGBE_DCB 5413 ixgbe_configure_dcb(adapter); 5414 #endif 5415 /* 5416 * We must restore virtualization before VLANs or else 5417 * the VLVF registers will not be populated 5418 */ 5419 ixgbe_configure_virtualization(adapter); 5420 5421 ixgbe_set_rx_mode(adapter->netdev); 5422 ixgbe_restore_vlan(adapter); 5423 ixgbe_ipsec_restore(adapter); 5424 5425 switch (hw->mac.type) { 5426 case ixgbe_mac_82599EB: 5427 case ixgbe_mac_X540: 5428 hw->mac.ops.disable_rx_buff(hw); 5429 break; 5430 default: 5431 break; 5432 } 5433 5434 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5435 ixgbe_init_fdir_signature_82599(&adapter->hw, 5436 adapter->fdir_pballoc); 5437 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5438 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5439 adapter->fdir_pballoc); 5440 ixgbe_fdir_filter_restore(adapter); 5441 } 5442 5443 switch (hw->mac.type) { 5444 case ixgbe_mac_82599EB: 5445 case ixgbe_mac_X540: 5446 hw->mac.ops.enable_rx_buff(hw); 5447 break; 5448 default: 5449 break; 5450 } 5451 5452 #ifdef CONFIG_IXGBE_DCA 5453 /* configure DCA */ 5454 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5455 ixgbe_setup_dca(adapter); 5456 #endif /* CONFIG_IXGBE_DCA */ 5457 5458 #ifdef IXGBE_FCOE 5459 /* configure FCoE L2 filters, redirection table, and Rx control */ 5460 ixgbe_configure_fcoe(adapter); 5461 5462 #endif /* IXGBE_FCOE */ 5463 ixgbe_configure_tx(adapter); 5464 ixgbe_configure_rx(adapter); 5465 ixgbe_configure_dfwd(adapter); 5466 } 5467 5468 /** 5469 * ixgbe_sfp_link_config - set up SFP+ link 5470 * @adapter: pointer to private adapter struct 5471 **/ 5472 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5473 { 5474 /* 5475 * We are assuming the worst case scenario here, and that 5476 * is that an SFP was inserted/removed after the reset 5477 * but before SFP detection was enabled. As such the best 5478 * solution is to just start searching as soon as we start 5479 */ 5480 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5481 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5482 5483 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5484 adapter->sfp_poll_time = 0; 5485 } 5486 5487 /** 5488 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5489 * @hw: pointer to private hardware struct 5490 * 5491 * Returns 0 on success, negative on failure 5492 **/ 5493 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5494 { 5495 u32 speed; 5496 bool autoneg, link_up = false; 5497 int ret = IXGBE_ERR_LINK_SETUP; 5498 5499 if (hw->mac.ops.check_link) 5500 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5501 5502 if (ret) 5503 return ret; 5504 5505 speed = hw->phy.autoneg_advertised; 5506 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5507 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5508 &autoneg); 5509 if (ret) 5510 return ret; 5511 5512 if (hw->mac.ops.setup_link) 5513 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5514 5515 return ret; 5516 } 5517 5518 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5519 { 5520 struct ixgbe_hw *hw = &adapter->hw; 5521 u32 gpie = 0; 5522 5523 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5524 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5525 IXGBE_GPIE_OCD; 5526 gpie |= IXGBE_GPIE_EIAME; 5527 /* 5528 * use EIAM to auto-mask when MSI-X interrupt is asserted 5529 * this saves a register write for every interrupt 5530 */ 5531 switch (hw->mac.type) { 5532 case ixgbe_mac_82598EB: 5533 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5534 break; 5535 case ixgbe_mac_82599EB: 5536 case ixgbe_mac_X540: 5537 case ixgbe_mac_X550: 5538 case ixgbe_mac_X550EM_x: 5539 case ixgbe_mac_x550em_a: 5540 default: 5541 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5542 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5543 break; 5544 } 5545 } else { 5546 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5547 * specifically only auto mask tx and rx interrupts */ 5548 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5549 } 5550 5551 /* XXX: to interrupt immediately for EICS writes, enable this */ 5552 /* gpie |= IXGBE_GPIE_EIMEN; */ 5553 5554 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5555 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5556 5557 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5558 case IXGBE_82599_VMDQ_8Q_MASK: 5559 gpie |= IXGBE_GPIE_VTMODE_16; 5560 break; 5561 case IXGBE_82599_VMDQ_4Q_MASK: 5562 gpie |= IXGBE_GPIE_VTMODE_32; 5563 break; 5564 default: 5565 gpie |= IXGBE_GPIE_VTMODE_64; 5566 break; 5567 } 5568 } 5569 5570 /* Enable Thermal over heat sensor interrupt */ 5571 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5572 switch (adapter->hw.mac.type) { 5573 case ixgbe_mac_82599EB: 5574 gpie |= IXGBE_SDP0_GPIEN_8259X; 5575 break; 5576 default: 5577 break; 5578 } 5579 } 5580 5581 /* Enable fan failure interrupt */ 5582 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5583 gpie |= IXGBE_SDP1_GPIEN(hw); 5584 5585 switch (hw->mac.type) { 5586 case ixgbe_mac_82599EB: 5587 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5588 break; 5589 case ixgbe_mac_X550EM_x: 5590 case ixgbe_mac_x550em_a: 5591 gpie |= IXGBE_SDP0_GPIEN_X540; 5592 break; 5593 default: 5594 break; 5595 } 5596 5597 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5598 } 5599 5600 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5601 { 5602 struct ixgbe_hw *hw = &adapter->hw; 5603 int err; 5604 u32 ctrl_ext; 5605 5606 ixgbe_get_hw_control(adapter); 5607 ixgbe_setup_gpie(adapter); 5608 5609 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5610 ixgbe_configure_msix(adapter); 5611 else 5612 ixgbe_configure_msi_and_legacy(adapter); 5613 5614 /* enable the optics for 82599 SFP+ fiber */ 5615 if (hw->mac.ops.enable_tx_laser) 5616 hw->mac.ops.enable_tx_laser(hw); 5617 5618 if (hw->phy.ops.set_phy_power) 5619 hw->phy.ops.set_phy_power(hw, true); 5620 5621 smp_mb__before_atomic(); 5622 clear_bit(__IXGBE_DOWN, &adapter->state); 5623 ixgbe_napi_enable_all(adapter); 5624 5625 if (ixgbe_is_sfp(hw)) { 5626 ixgbe_sfp_link_config(adapter); 5627 } else { 5628 err = ixgbe_non_sfp_link_config(hw); 5629 if (err) 5630 e_err(probe, "link_config FAILED %d\n", err); 5631 } 5632 5633 /* clear any pending interrupts, may auto mask */ 5634 IXGBE_READ_REG(hw, IXGBE_EICR); 5635 ixgbe_irq_enable(adapter, true, true); 5636 5637 /* 5638 * If this adapter has a fan, check to see if we had a failure 5639 * before we enabled the interrupt. 5640 */ 5641 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5642 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5643 if (esdp & IXGBE_ESDP_SDP1) 5644 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5645 } 5646 5647 /* bring the link up in the watchdog, this could race with our first 5648 * link up interrupt but shouldn't be a problem */ 5649 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5650 adapter->link_check_timeout = jiffies; 5651 mod_timer(&adapter->service_timer, jiffies); 5652 5653 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5654 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5655 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5656 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5657 } 5658 5659 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5660 { 5661 WARN_ON(in_interrupt()); 5662 /* put off any impending NetWatchDogTimeout */ 5663 netif_trans_update(adapter->netdev); 5664 5665 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5666 usleep_range(1000, 2000); 5667 if (adapter->hw.phy.type == ixgbe_phy_fw) 5668 ixgbe_watchdog_link_is_down(adapter); 5669 ixgbe_down(adapter); 5670 /* 5671 * If SR-IOV enabled then wait a bit before bringing the adapter 5672 * back up to give the VFs time to respond to the reset. The 5673 * two second wait is based upon the watchdog timer cycle in 5674 * the VF driver. 5675 */ 5676 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5677 msleep(2000); 5678 ixgbe_up(adapter); 5679 clear_bit(__IXGBE_RESETTING, &adapter->state); 5680 } 5681 5682 void ixgbe_up(struct ixgbe_adapter *adapter) 5683 { 5684 /* hardware has been reset, we need to reload some things */ 5685 ixgbe_configure(adapter); 5686 5687 ixgbe_up_complete(adapter); 5688 } 5689 5690 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5691 { 5692 u16 devctl2; 5693 5694 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5695 5696 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5697 case IXGBE_PCIDEVCTRL2_17_34s: 5698 case IXGBE_PCIDEVCTRL2_4_8s: 5699 /* For now we cap the upper limit on delay to 2 seconds 5700 * as we end up going up to 34 seconds of delay in worst 5701 * case timeout value. 5702 */ 5703 case IXGBE_PCIDEVCTRL2_1_2s: 5704 return 2000000ul; /* 2.0 s */ 5705 case IXGBE_PCIDEVCTRL2_260_520ms: 5706 return 520000ul; /* 520 ms */ 5707 case IXGBE_PCIDEVCTRL2_65_130ms: 5708 return 130000ul; /* 130 ms */ 5709 case IXGBE_PCIDEVCTRL2_16_32ms: 5710 return 32000ul; /* 32 ms */ 5711 case IXGBE_PCIDEVCTRL2_1_2ms: 5712 return 2000ul; /* 2 ms */ 5713 case IXGBE_PCIDEVCTRL2_50_100us: 5714 return 100ul; /* 100 us */ 5715 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5716 return 32000ul; /* 32 ms */ 5717 default: 5718 break; 5719 } 5720 5721 /* We shouldn't need to hit this path, but just in case default as 5722 * though completion timeout is not supported and support 32ms. 5723 */ 5724 return 32000ul; 5725 } 5726 5727 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5728 { 5729 unsigned long wait_delay, delay_interval; 5730 struct ixgbe_hw *hw = &adapter->hw; 5731 int i, wait_loop; 5732 u32 rxdctl; 5733 5734 /* disable receives */ 5735 hw->mac.ops.disable_rx(hw); 5736 5737 if (ixgbe_removed(hw->hw_addr)) 5738 return; 5739 5740 /* disable all enabled Rx queues */ 5741 for (i = 0; i < adapter->num_rx_queues; i++) { 5742 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5743 u8 reg_idx = ring->reg_idx; 5744 5745 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5746 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5747 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5748 5749 /* write value back with RXDCTL.ENABLE bit cleared */ 5750 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5751 } 5752 5753 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5754 if (hw->mac.type == ixgbe_mac_82598EB && 5755 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5756 return; 5757 5758 /* Determine our minimum delay interval. We will increase this value 5759 * with each subsequent test. This way if the device returns quickly 5760 * we should spend as little time as possible waiting, however as 5761 * the time increases we will wait for larger periods of time. 5762 * 5763 * The trick here is that we increase the interval using the 5764 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5765 * of that wait is that it totals up to 100x whatever interval we 5766 * choose. Since our minimum wait is 100us we can just divide the 5767 * total timeout by 100 to get our minimum delay interval. 5768 */ 5769 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5770 5771 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5772 wait_delay = delay_interval; 5773 5774 while (wait_loop--) { 5775 usleep_range(wait_delay, wait_delay + 10); 5776 wait_delay += delay_interval * 2; 5777 rxdctl = 0; 5778 5779 /* OR together the reading of all the active RXDCTL registers, 5780 * and then test the result. We need the disable to complete 5781 * before we start freeing the memory and invalidating the 5782 * DMA mappings. 5783 */ 5784 for (i = 0; i < adapter->num_rx_queues; i++) { 5785 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5786 u8 reg_idx = ring->reg_idx; 5787 5788 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5789 } 5790 5791 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5792 return; 5793 } 5794 5795 e_err(drv, 5796 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5797 } 5798 5799 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5800 { 5801 unsigned long wait_delay, delay_interval; 5802 struct ixgbe_hw *hw = &adapter->hw; 5803 int i, wait_loop; 5804 u32 txdctl; 5805 5806 if (ixgbe_removed(hw->hw_addr)) 5807 return; 5808 5809 /* disable all enabled Tx queues */ 5810 for (i = 0; i < adapter->num_tx_queues; i++) { 5811 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5812 u8 reg_idx = ring->reg_idx; 5813 5814 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5815 } 5816 5817 /* disable all enabled XDP Tx queues */ 5818 for (i = 0; i < adapter->num_xdp_queues; i++) { 5819 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5820 u8 reg_idx = ring->reg_idx; 5821 5822 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5823 } 5824 5825 /* If the link is not up there shouldn't be much in the way of 5826 * pending transactions. Those that are left will be flushed out 5827 * when the reset logic goes through the flush sequence to clean out 5828 * the pending Tx transactions. 5829 */ 5830 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5831 goto dma_engine_disable; 5832 5833 /* Determine our minimum delay interval. We will increase this value 5834 * with each subsequent test. This way if the device returns quickly 5835 * we should spend as little time as possible waiting, however as 5836 * the time increases we will wait for larger periods of time. 5837 * 5838 * The trick here is that we increase the interval using the 5839 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5840 * of that wait is that it totals up to 100x whatever interval we 5841 * choose. Since our minimum wait is 100us we can just divide the 5842 * total timeout by 100 to get our minimum delay interval. 5843 */ 5844 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5845 5846 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5847 wait_delay = delay_interval; 5848 5849 while (wait_loop--) { 5850 usleep_range(wait_delay, wait_delay + 10); 5851 wait_delay += delay_interval * 2; 5852 txdctl = 0; 5853 5854 /* OR together the reading of all the active TXDCTL registers, 5855 * and then test the result. We need the disable to complete 5856 * before we start freeing the memory and invalidating the 5857 * DMA mappings. 5858 */ 5859 for (i = 0; i < adapter->num_tx_queues; i++) { 5860 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5861 u8 reg_idx = ring->reg_idx; 5862 5863 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5864 } 5865 for (i = 0; i < adapter->num_xdp_queues; i++) { 5866 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5867 u8 reg_idx = ring->reg_idx; 5868 5869 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5870 } 5871 5872 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5873 goto dma_engine_disable; 5874 } 5875 5876 e_err(drv, 5877 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5878 5879 dma_engine_disable: 5880 /* Disable the Tx DMA engine on 82599 and later MAC */ 5881 switch (hw->mac.type) { 5882 case ixgbe_mac_82599EB: 5883 case ixgbe_mac_X540: 5884 case ixgbe_mac_X550: 5885 case ixgbe_mac_X550EM_x: 5886 case ixgbe_mac_x550em_a: 5887 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5888 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5889 ~IXGBE_DMATXCTL_TE)); 5890 /* fall through */ 5891 default: 5892 break; 5893 } 5894 } 5895 5896 void ixgbe_reset(struct ixgbe_adapter *adapter) 5897 { 5898 struct ixgbe_hw *hw = &adapter->hw; 5899 struct net_device *netdev = adapter->netdev; 5900 int err; 5901 5902 if (ixgbe_removed(hw->hw_addr)) 5903 return; 5904 /* lock SFP init bit to prevent race conditions with the watchdog */ 5905 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5906 usleep_range(1000, 2000); 5907 5908 /* clear all SFP and link config related flags while holding SFP_INIT */ 5909 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5910 IXGBE_FLAG2_SFP_NEEDS_RESET); 5911 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5912 5913 err = hw->mac.ops.init_hw(hw); 5914 switch (err) { 5915 case 0: 5916 case IXGBE_ERR_SFP_NOT_PRESENT: 5917 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5918 break; 5919 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5920 e_dev_err("master disable timed out\n"); 5921 break; 5922 case IXGBE_ERR_EEPROM_VERSION: 5923 /* We are running on a pre-production device, log a warning */ 5924 e_dev_warn("This device is a pre-production adapter/LOM. " 5925 "Please be aware there may be issues associated with " 5926 "your hardware. If you are experiencing problems " 5927 "please contact your Intel or hardware " 5928 "representative who provided you with this " 5929 "hardware.\n"); 5930 break; 5931 default: 5932 e_dev_err("Hardware Error: %d\n", err); 5933 } 5934 5935 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5936 5937 /* flush entries out of MAC table */ 5938 ixgbe_flush_sw_mac_table(adapter); 5939 __dev_uc_unsync(netdev, NULL); 5940 5941 /* do not flush user set addresses */ 5942 ixgbe_mac_set_default_filter(adapter); 5943 5944 /* update SAN MAC vmdq pool selection */ 5945 if (hw->mac.san_mac_rar_index) 5946 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5947 5948 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5949 ixgbe_ptp_reset(adapter); 5950 5951 if (hw->phy.ops.set_phy_power) { 5952 if (!netif_running(adapter->netdev) && !adapter->wol) 5953 hw->phy.ops.set_phy_power(hw, false); 5954 else 5955 hw->phy.ops.set_phy_power(hw, true); 5956 } 5957 } 5958 5959 /** 5960 * ixgbe_clean_tx_ring - Free Tx Buffers 5961 * @tx_ring: ring to be cleaned 5962 **/ 5963 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5964 { 5965 u16 i = tx_ring->next_to_clean; 5966 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5967 5968 if (tx_ring->xsk_umem) { 5969 ixgbe_xsk_clean_tx_ring(tx_ring); 5970 goto out; 5971 } 5972 5973 while (i != tx_ring->next_to_use) { 5974 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5975 5976 /* Free all the Tx ring sk_buffs */ 5977 if (ring_is_xdp(tx_ring)) 5978 xdp_return_frame(tx_buffer->xdpf); 5979 else 5980 dev_kfree_skb_any(tx_buffer->skb); 5981 5982 /* unmap skb header data */ 5983 dma_unmap_single(tx_ring->dev, 5984 dma_unmap_addr(tx_buffer, dma), 5985 dma_unmap_len(tx_buffer, len), 5986 DMA_TO_DEVICE); 5987 5988 /* check for eop_desc to determine the end of the packet */ 5989 eop_desc = tx_buffer->next_to_watch; 5990 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5991 5992 /* unmap remaining buffers */ 5993 while (tx_desc != eop_desc) { 5994 tx_buffer++; 5995 tx_desc++; 5996 i++; 5997 if (unlikely(i == tx_ring->count)) { 5998 i = 0; 5999 tx_buffer = tx_ring->tx_buffer_info; 6000 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6001 } 6002 6003 /* unmap any remaining paged data */ 6004 if (dma_unmap_len(tx_buffer, len)) 6005 dma_unmap_page(tx_ring->dev, 6006 dma_unmap_addr(tx_buffer, dma), 6007 dma_unmap_len(tx_buffer, len), 6008 DMA_TO_DEVICE); 6009 } 6010 6011 /* move us one more past the eop_desc for start of next pkt */ 6012 tx_buffer++; 6013 i++; 6014 if (unlikely(i == tx_ring->count)) { 6015 i = 0; 6016 tx_buffer = tx_ring->tx_buffer_info; 6017 } 6018 } 6019 6020 /* reset BQL for queue */ 6021 if (!ring_is_xdp(tx_ring)) 6022 netdev_tx_reset_queue(txring_txq(tx_ring)); 6023 6024 out: 6025 /* reset next_to_use and next_to_clean */ 6026 tx_ring->next_to_use = 0; 6027 tx_ring->next_to_clean = 0; 6028 } 6029 6030 /** 6031 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6032 * @adapter: board private structure 6033 **/ 6034 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6035 { 6036 int i; 6037 6038 for (i = 0; i < adapter->num_rx_queues; i++) 6039 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6040 } 6041 6042 /** 6043 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6044 * @adapter: board private structure 6045 **/ 6046 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6047 { 6048 int i; 6049 6050 for (i = 0; i < adapter->num_tx_queues; i++) 6051 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6052 for (i = 0; i < adapter->num_xdp_queues; i++) 6053 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6054 } 6055 6056 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6057 { 6058 struct hlist_node *node2; 6059 struct ixgbe_fdir_filter *filter; 6060 6061 spin_lock(&adapter->fdir_perfect_lock); 6062 6063 hlist_for_each_entry_safe(filter, node2, 6064 &adapter->fdir_filter_list, fdir_node) { 6065 hlist_del(&filter->fdir_node); 6066 kfree(filter); 6067 } 6068 adapter->fdir_filter_count = 0; 6069 6070 spin_unlock(&adapter->fdir_perfect_lock); 6071 } 6072 6073 void ixgbe_down(struct ixgbe_adapter *adapter) 6074 { 6075 struct net_device *netdev = adapter->netdev; 6076 struct ixgbe_hw *hw = &adapter->hw; 6077 int i; 6078 6079 /* signal that we are down to the interrupt handler */ 6080 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6081 return; /* do nothing if already down */ 6082 6083 /* Shut off incoming Tx traffic */ 6084 netif_tx_stop_all_queues(netdev); 6085 6086 /* call carrier off first to avoid false dev_watchdog timeouts */ 6087 netif_carrier_off(netdev); 6088 netif_tx_disable(netdev); 6089 6090 /* Disable Rx */ 6091 ixgbe_disable_rx(adapter); 6092 6093 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6094 if (adapter->xdp_ring[0]) 6095 synchronize_rcu(); 6096 6097 ixgbe_irq_disable(adapter); 6098 6099 ixgbe_napi_disable_all(adapter); 6100 6101 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6102 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6103 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6104 6105 del_timer_sync(&adapter->service_timer); 6106 6107 if (adapter->num_vfs) { 6108 /* Clear EITR Select mapping */ 6109 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6110 6111 /* Mark all the VFs as inactive */ 6112 for (i = 0 ; i < adapter->num_vfs; i++) 6113 adapter->vfinfo[i].clear_to_send = false; 6114 6115 /* ping all the active vfs to let them know we are going down */ 6116 ixgbe_ping_all_vfs(adapter); 6117 6118 /* Disable all VFTE/VFRE TX/RX */ 6119 ixgbe_disable_tx_rx(adapter); 6120 } 6121 6122 /* disable transmits in the hardware now that interrupts are off */ 6123 ixgbe_disable_tx(adapter); 6124 6125 if (!pci_channel_offline(adapter->pdev)) 6126 ixgbe_reset(adapter); 6127 6128 /* power down the optics for 82599 SFP+ fiber */ 6129 if (hw->mac.ops.disable_tx_laser) 6130 hw->mac.ops.disable_tx_laser(hw); 6131 6132 ixgbe_clean_all_tx_rings(adapter); 6133 ixgbe_clean_all_rx_rings(adapter); 6134 } 6135 6136 /** 6137 * ixgbe_eee_capable - helper function to determine EEE support on X550 6138 * @adapter: board private structure 6139 */ 6140 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6141 { 6142 struct ixgbe_hw *hw = &adapter->hw; 6143 6144 switch (hw->device_id) { 6145 case IXGBE_DEV_ID_X550EM_A_1G_T: 6146 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6147 if (!hw->phy.eee_speeds_supported) 6148 break; 6149 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6150 if (!hw->phy.eee_speeds_advertised) 6151 break; 6152 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6153 break; 6154 default: 6155 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6156 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6157 break; 6158 } 6159 } 6160 6161 /** 6162 * ixgbe_tx_timeout - Respond to a Tx Hang 6163 * @netdev: network interface device structure 6164 **/ 6165 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue) 6166 { 6167 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6168 6169 /* Do the reset outside of interrupt context */ 6170 ixgbe_tx_timeout_reset(adapter); 6171 } 6172 6173 #ifdef CONFIG_IXGBE_DCB 6174 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6175 { 6176 struct ixgbe_hw *hw = &adapter->hw; 6177 struct tc_configuration *tc; 6178 int j; 6179 6180 switch (hw->mac.type) { 6181 case ixgbe_mac_82598EB: 6182 case ixgbe_mac_82599EB: 6183 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6184 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6185 break; 6186 case ixgbe_mac_X540: 6187 case ixgbe_mac_X550: 6188 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6189 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6190 break; 6191 case ixgbe_mac_X550EM_x: 6192 case ixgbe_mac_x550em_a: 6193 default: 6194 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6195 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6196 break; 6197 } 6198 6199 /* Configure DCB traffic classes */ 6200 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6201 tc = &adapter->dcb_cfg.tc_config[j]; 6202 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6203 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6204 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6205 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6206 tc->dcb_pfc = pfc_disabled; 6207 } 6208 6209 /* Initialize default user to priority mapping, UPx->TC0 */ 6210 tc = &adapter->dcb_cfg.tc_config[0]; 6211 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6212 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6213 6214 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6215 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6216 adapter->dcb_cfg.pfc_mode_enable = false; 6217 adapter->dcb_set_bitmap = 0x00; 6218 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6219 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6220 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6221 sizeof(adapter->temp_dcb_cfg)); 6222 } 6223 #endif 6224 6225 /** 6226 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6227 * @adapter: board private structure to initialize 6228 * @ii: pointer to ixgbe_info for device 6229 * 6230 * ixgbe_sw_init initializes the Adapter private data structure. 6231 * Fields are initialized based on PCI device information and 6232 * OS network device settings (MTU size). 6233 **/ 6234 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6235 const struct ixgbe_info *ii) 6236 { 6237 struct ixgbe_hw *hw = &adapter->hw; 6238 struct pci_dev *pdev = adapter->pdev; 6239 unsigned int rss, fdir; 6240 u32 fwsm; 6241 int i; 6242 6243 /* PCI config space info */ 6244 6245 hw->vendor_id = pdev->vendor; 6246 hw->device_id = pdev->device; 6247 hw->revision_id = pdev->revision; 6248 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6249 hw->subsystem_device_id = pdev->subsystem_device; 6250 6251 /* get_invariants needs the device IDs */ 6252 ii->get_invariants(hw); 6253 6254 /* Set common capability flags and settings */ 6255 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6256 adapter->ring_feature[RING_F_RSS].limit = rss; 6257 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6258 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6259 adapter->atr_sample_rate = 20; 6260 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6261 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6262 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6263 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6264 #ifdef CONFIG_IXGBE_DCA 6265 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6266 #endif 6267 #ifdef CONFIG_IXGBE_DCB 6268 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6269 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6270 #endif 6271 #ifdef IXGBE_FCOE 6272 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6273 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6274 #ifdef CONFIG_IXGBE_DCB 6275 /* Default traffic class to use for FCoE */ 6276 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6277 #endif /* CONFIG_IXGBE_DCB */ 6278 #endif /* IXGBE_FCOE */ 6279 6280 /* initialize static ixgbe jump table entries */ 6281 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6282 GFP_KERNEL); 6283 if (!adapter->jump_tables[0]) 6284 return -ENOMEM; 6285 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6286 6287 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6288 adapter->jump_tables[i] = NULL; 6289 6290 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6291 sizeof(struct ixgbe_mac_addr), 6292 GFP_KERNEL); 6293 if (!adapter->mac_table) 6294 return -ENOMEM; 6295 6296 if (ixgbe_init_rss_key(adapter)) 6297 return -ENOMEM; 6298 6299 adapter->af_xdp_zc_qps = bitmap_zalloc(MAX_XDP_QUEUES, GFP_KERNEL); 6300 if (!adapter->af_xdp_zc_qps) 6301 return -ENOMEM; 6302 6303 /* Set MAC specific capability flags and exceptions */ 6304 switch (hw->mac.type) { 6305 case ixgbe_mac_82598EB: 6306 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6307 6308 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6309 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6310 6311 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6312 adapter->ring_feature[RING_F_FDIR].limit = 0; 6313 adapter->atr_sample_rate = 0; 6314 adapter->fdir_pballoc = 0; 6315 #ifdef IXGBE_FCOE 6316 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6317 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6318 #ifdef CONFIG_IXGBE_DCB 6319 adapter->fcoe.up = 0; 6320 #endif /* IXGBE_DCB */ 6321 #endif /* IXGBE_FCOE */ 6322 break; 6323 case ixgbe_mac_82599EB: 6324 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6325 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6326 break; 6327 case ixgbe_mac_X540: 6328 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6329 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6330 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6331 break; 6332 case ixgbe_mac_x550em_a: 6333 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6334 switch (hw->device_id) { 6335 case IXGBE_DEV_ID_X550EM_A_1G_T: 6336 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6337 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6338 break; 6339 default: 6340 break; 6341 } 6342 /* fall through */ 6343 case ixgbe_mac_X550EM_x: 6344 #ifdef CONFIG_IXGBE_DCB 6345 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6346 #endif 6347 #ifdef IXGBE_FCOE 6348 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6349 #ifdef CONFIG_IXGBE_DCB 6350 adapter->fcoe.up = 0; 6351 #endif /* IXGBE_DCB */ 6352 #endif /* IXGBE_FCOE */ 6353 /* Fall Through */ 6354 case ixgbe_mac_X550: 6355 if (hw->mac.type == ixgbe_mac_X550) 6356 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6357 #ifdef CONFIG_IXGBE_DCA 6358 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6359 #endif 6360 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6361 break; 6362 default: 6363 break; 6364 } 6365 6366 #ifdef IXGBE_FCOE 6367 /* FCoE support exists, always init the FCoE lock */ 6368 spin_lock_init(&adapter->fcoe.lock); 6369 6370 #endif 6371 /* n-tuple support exists, always init our spinlock */ 6372 spin_lock_init(&adapter->fdir_perfect_lock); 6373 6374 #ifdef CONFIG_IXGBE_DCB 6375 ixgbe_init_dcb(adapter); 6376 #endif 6377 ixgbe_init_ipsec_offload(adapter); 6378 6379 /* default flow control settings */ 6380 hw->fc.requested_mode = ixgbe_fc_full; 6381 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6382 ixgbe_pbthresh_setup(adapter); 6383 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6384 hw->fc.send_xon = true; 6385 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6386 6387 #ifdef CONFIG_PCI_IOV 6388 if (max_vfs > 0) 6389 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6390 6391 /* assign number of SR-IOV VFs */ 6392 if (hw->mac.type != ixgbe_mac_82598EB) { 6393 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6394 max_vfs = 0; 6395 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6396 } 6397 } 6398 #endif /* CONFIG_PCI_IOV */ 6399 6400 /* enable itr by default in dynamic mode */ 6401 adapter->rx_itr_setting = 1; 6402 adapter->tx_itr_setting = 1; 6403 6404 /* set default ring sizes */ 6405 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6406 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6407 6408 /* set default work limits */ 6409 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6410 6411 /* initialize eeprom parameters */ 6412 if (ixgbe_init_eeprom_params_generic(hw)) { 6413 e_dev_err("EEPROM initialization failed\n"); 6414 return -EIO; 6415 } 6416 6417 /* PF holds first pool slot */ 6418 set_bit(0, adapter->fwd_bitmask); 6419 set_bit(__IXGBE_DOWN, &adapter->state); 6420 6421 return 0; 6422 } 6423 6424 /** 6425 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6426 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6427 * 6428 * Return 0 on success, negative on failure 6429 **/ 6430 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6431 { 6432 struct device *dev = tx_ring->dev; 6433 int orig_node = dev_to_node(dev); 6434 int ring_node = NUMA_NO_NODE; 6435 int size; 6436 6437 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6438 6439 if (tx_ring->q_vector) 6440 ring_node = tx_ring->q_vector->numa_node; 6441 6442 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6443 if (!tx_ring->tx_buffer_info) 6444 tx_ring->tx_buffer_info = vmalloc(size); 6445 if (!tx_ring->tx_buffer_info) 6446 goto err; 6447 6448 /* round up to nearest 4K */ 6449 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6450 tx_ring->size = ALIGN(tx_ring->size, 4096); 6451 6452 set_dev_node(dev, ring_node); 6453 tx_ring->desc = dma_alloc_coherent(dev, 6454 tx_ring->size, 6455 &tx_ring->dma, 6456 GFP_KERNEL); 6457 set_dev_node(dev, orig_node); 6458 if (!tx_ring->desc) 6459 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6460 &tx_ring->dma, GFP_KERNEL); 6461 if (!tx_ring->desc) 6462 goto err; 6463 6464 tx_ring->next_to_use = 0; 6465 tx_ring->next_to_clean = 0; 6466 return 0; 6467 6468 err: 6469 vfree(tx_ring->tx_buffer_info); 6470 tx_ring->tx_buffer_info = NULL; 6471 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6472 return -ENOMEM; 6473 } 6474 6475 /** 6476 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6477 * @adapter: board private structure 6478 * 6479 * If this function returns with an error, then it's possible one or 6480 * more of the rings is populated (while the rest are not). It is the 6481 * callers duty to clean those orphaned rings. 6482 * 6483 * Return 0 on success, negative on failure 6484 **/ 6485 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6486 { 6487 int i, j = 0, err = 0; 6488 6489 for (i = 0; i < adapter->num_tx_queues; i++) { 6490 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6491 if (!err) 6492 continue; 6493 6494 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6495 goto err_setup_tx; 6496 } 6497 for (j = 0; j < adapter->num_xdp_queues; j++) { 6498 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6499 if (!err) 6500 continue; 6501 6502 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6503 goto err_setup_tx; 6504 } 6505 6506 return 0; 6507 err_setup_tx: 6508 /* rewind the index freeing the rings as we go */ 6509 while (j--) 6510 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6511 while (i--) 6512 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6513 return err; 6514 } 6515 6516 /** 6517 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6518 * @adapter: pointer to ixgbe_adapter 6519 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6520 * 6521 * Returns 0 on success, negative on failure 6522 **/ 6523 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6524 struct ixgbe_ring *rx_ring) 6525 { 6526 struct device *dev = rx_ring->dev; 6527 int orig_node = dev_to_node(dev); 6528 int ring_node = NUMA_NO_NODE; 6529 int size; 6530 6531 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6532 6533 if (rx_ring->q_vector) 6534 ring_node = rx_ring->q_vector->numa_node; 6535 6536 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6537 if (!rx_ring->rx_buffer_info) 6538 rx_ring->rx_buffer_info = vmalloc(size); 6539 if (!rx_ring->rx_buffer_info) 6540 goto err; 6541 6542 /* Round up to nearest 4K */ 6543 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6544 rx_ring->size = ALIGN(rx_ring->size, 4096); 6545 6546 set_dev_node(dev, ring_node); 6547 rx_ring->desc = dma_alloc_coherent(dev, 6548 rx_ring->size, 6549 &rx_ring->dma, 6550 GFP_KERNEL); 6551 set_dev_node(dev, orig_node); 6552 if (!rx_ring->desc) 6553 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6554 &rx_ring->dma, GFP_KERNEL); 6555 if (!rx_ring->desc) 6556 goto err; 6557 6558 rx_ring->next_to_clean = 0; 6559 rx_ring->next_to_use = 0; 6560 6561 /* XDP RX-queue info */ 6562 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6563 rx_ring->queue_index) < 0) 6564 goto err; 6565 6566 rx_ring->xdp_prog = adapter->xdp_prog; 6567 6568 return 0; 6569 err: 6570 vfree(rx_ring->rx_buffer_info); 6571 rx_ring->rx_buffer_info = NULL; 6572 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6573 return -ENOMEM; 6574 } 6575 6576 /** 6577 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6578 * @adapter: board private structure 6579 * 6580 * If this function returns with an error, then it's possible one or 6581 * more of the rings is populated (while the rest are not). It is the 6582 * callers duty to clean those orphaned rings. 6583 * 6584 * Return 0 on success, negative on failure 6585 **/ 6586 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6587 { 6588 int i, err = 0; 6589 6590 for (i = 0; i < adapter->num_rx_queues; i++) { 6591 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6592 if (!err) 6593 continue; 6594 6595 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6596 goto err_setup_rx; 6597 } 6598 6599 #ifdef IXGBE_FCOE 6600 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6601 if (!err) 6602 #endif 6603 return 0; 6604 err_setup_rx: 6605 /* rewind the index freeing the rings as we go */ 6606 while (i--) 6607 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6608 return err; 6609 } 6610 6611 /** 6612 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6613 * @tx_ring: Tx descriptor ring for a specific queue 6614 * 6615 * Free all transmit software resources 6616 **/ 6617 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6618 { 6619 ixgbe_clean_tx_ring(tx_ring); 6620 6621 vfree(tx_ring->tx_buffer_info); 6622 tx_ring->tx_buffer_info = NULL; 6623 6624 /* if not set, then don't free */ 6625 if (!tx_ring->desc) 6626 return; 6627 6628 dma_free_coherent(tx_ring->dev, tx_ring->size, 6629 tx_ring->desc, tx_ring->dma); 6630 6631 tx_ring->desc = NULL; 6632 } 6633 6634 /** 6635 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6636 * @adapter: board private structure 6637 * 6638 * Free all transmit software resources 6639 **/ 6640 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6641 { 6642 int i; 6643 6644 for (i = 0; i < adapter->num_tx_queues; i++) 6645 if (adapter->tx_ring[i]->desc) 6646 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6647 for (i = 0; i < adapter->num_xdp_queues; i++) 6648 if (adapter->xdp_ring[i]->desc) 6649 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6650 } 6651 6652 /** 6653 * ixgbe_free_rx_resources - Free Rx Resources 6654 * @rx_ring: ring to clean the resources from 6655 * 6656 * Free all receive software resources 6657 **/ 6658 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6659 { 6660 ixgbe_clean_rx_ring(rx_ring); 6661 6662 rx_ring->xdp_prog = NULL; 6663 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6664 vfree(rx_ring->rx_buffer_info); 6665 rx_ring->rx_buffer_info = NULL; 6666 6667 /* if not set, then don't free */ 6668 if (!rx_ring->desc) 6669 return; 6670 6671 dma_free_coherent(rx_ring->dev, rx_ring->size, 6672 rx_ring->desc, rx_ring->dma); 6673 6674 rx_ring->desc = NULL; 6675 } 6676 6677 /** 6678 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6679 * @adapter: board private structure 6680 * 6681 * Free all receive software resources 6682 **/ 6683 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6684 { 6685 int i; 6686 6687 #ifdef IXGBE_FCOE 6688 ixgbe_free_fcoe_ddp_resources(adapter); 6689 6690 #endif 6691 for (i = 0; i < adapter->num_rx_queues; i++) 6692 if (adapter->rx_ring[i]->desc) 6693 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6694 } 6695 6696 /** 6697 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6698 * @netdev: network interface device structure 6699 * @new_mtu: new value for maximum frame size 6700 * 6701 * Returns 0 on success, negative on failure 6702 **/ 6703 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6704 { 6705 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6706 6707 if (adapter->xdp_prog) { 6708 int new_frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 6709 VLAN_HLEN; 6710 int i; 6711 6712 for (i = 0; i < adapter->num_rx_queues; i++) { 6713 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6714 6715 if (new_frame_size > ixgbe_rx_bufsz(ring)) { 6716 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6717 return -EINVAL; 6718 } 6719 } 6720 } 6721 6722 /* 6723 * For 82599EB we cannot allow legacy VFs to enable their receive 6724 * paths when MTU greater than 1500 is configured. So display a 6725 * warning that legacy VFs will be disabled. 6726 */ 6727 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6728 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6729 (new_mtu > ETH_DATA_LEN)) 6730 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6731 6732 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6733 netdev->mtu, new_mtu); 6734 6735 /* must set new MTU before calling down or up */ 6736 netdev->mtu = new_mtu; 6737 6738 if (netif_running(netdev)) 6739 ixgbe_reinit_locked(adapter); 6740 6741 return 0; 6742 } 6743 6744 /** 6745 * ixgbe_open - Called when a network interface is made active 6746 * @netdev: network interface device structure 6747 * 6748 * Returns 0 on success, negative value on failure 6749 * 6750 * The open entry point is called when a network interface is made 6751 * active by the system (IFF_UP). At this point all resources needed 6752 * for transmit and receive operations are allocated, the interrupt 6753 * handler is registered with the OS, the watchdog timer is started, 6754 * and the stack is notified that the interface is ready. 6755 **/ 6756 int ixgbe_open(struct net_device *netdev) 6757 { 6758 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6759 struct ixgbe_hw *hw = &adapter->hw; 6760 int err, queues; 6761 6762 /* disallow open during test */ 6763 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6764 return -EBUSY; 6765 6766 netif_carrier_off(netdev); 6767 6768 /* allocate transmit descriptors */ 6769 err = ixgbe_setup_all_tx_resources(adapter); 6770 if (err) 6771 goto err_setup_tx; 6772 6773 /* allocate receive descriptors */ 6774 err = ixgbe_setup_all_rx_resources(adapter); 6775 if (err) 6776 goto err_setup_rx; 6777 6778 ixgbe_configure(adapter); 6779 6780 err = ixgbe_request_irq(adapter); 6781 if (err) 6782 goto err_req_irq; 6783 6784 /* Notify the stack of the actual queue counts. */ 6785 queues = adapter->num_tx_queues; 6786 err = netif_set_real_num_tx_queues(netdev, queues); 6787 if (err) 6788 goto err_set_queues; 6789 6790 queues = adapter->num_rx_queues; 6791 err = netif_set_real_num_rx_queues(netdev, queues); 6792 if (err) 6793 goto err_set_queues; 6794 6795 ixgbe_ptp_init(adapter); 6796 6797 ixgbe_up_complete(adapter); 6798 6799 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6800 udp_tunnel_get_rx_info(netdev); 6801 6802 return 0; 6803 6804 err_set_queues: 6805 ixgbe_free_irq(adapter); 6806 err_req_irq: 6807 ixgbe_free_all_rx_resources(adapter); 6808 if (hw->phy.ops.set_phy_power && !adapter->wol) 6809 hw->phy.ops.set_phy_power(&adapter->hw, false); 6810 err_setup_rx: 6811 ixgbe_free_all_tx_resources(adapter); 6812 err_setup_tx: 6813 ixgbe_reset(adapter); 6814 6815 return err; 6816 } 6817 6818 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6819 { 6820 ixgbe_ptp_suspend(adapter); 6821 6822 if (adapter->hw.phy.ops.enter_lplu) { 6823 adapter->hw.phy.reset_disable = true; 6824 ixgbe_down(adapter); 6825 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6826 adapter->hw.phy.reset_disable = false; 6827 } else { 6828 ixgbe_down(adapter); 6829 } 6830 6831 ixgbe_free_irq(adapter); 6832 6833 ixgbe_free_all_tx_resources(adapter); 6834 ixgbe_free_all_rx_resources(adapter); 6835 } 6836 6837 /** 6838 * ixgbe_close - Disables a network interface 6839 * @netdev: network interface device structure 6840 * 6841 * Returns 0, this is not allowed to fail 6842 * 6843 * The close entry point is called when an interface is de-activated 6844 * by the OS. The hardware is still under the drivers control, but 6845 * needs to be disabled. A global MAC reset is issued to stop the 6846 * hardware, and all transmit and receive resources are freed. 6847 **/ 6848 int ixgbe_close(struct net_device *netdev) 6849 { 6850 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6851 6852 ixgbe_ptp_stop(adapter); 6853 6854 if (netif_device_present(netdev)) 6855 ixgbe_close_suspend(adapter); 6856 6857 ixgbe_fdir_filter_exit(adapter); 6858 6859 ixgbe_release_hw_control(adapter); 6860 6861 return 0; 6862 } 6863 6864 #ifdef CONFIG_PM 6865 static int ixgbe_resume(struct pci_dev *pdev) 6866 { 6867 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6868 struct net_device *netdev = adapter->netdev; 6869 u32 err; 6870 6871 adapter->hw.hw_addr = adapter->io_addr; 6872 pci_set_power_state(pdev, PCI_D0); 6873 pci_restore_state(pdev); 6874 /* 6875 * pci_restore_state clears dev->state_saved so call 6876 * pci_save_state to restore it. 6877 */ 6878 pci_save_state(pdev); 6879 6880 err = pci_enable_device_mem(pdev); 6881 if (err) { 6882 e_dev_err("Cannot enable PCI device from suspend\n"); 6883 return err; 6884 } 6885 smp_mb__before_atomic(); 6886 clear_bit(__IXGBE_DISABLED, &adapter->state); 6887 pci_set_master(pdev); 6888 6889 pci_wake_from_d3(pdev, false); 6890 6891 ixgbe_reset(adapter); 6892 6893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6894 6895 rtnl_lock(); 6896 err = ixgbe_init_interrupt_scheme(adapter); 6897 if (!err && netif_running(netdev)) 6898 err = ixgbe_open(netdev); 6899 6900 6901 if (!err) 6902 netif_device_attach(netdev); 6903 rtnl_unlock(); 6904 6905 return err; 6906 } 6907 #endif /* CONFIG_PM */ 6908 6909 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6910 { 6911 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6912 struct net_device *netdev = adapter->netdev; 6913 struct ixgbe_hw *hw = &adapter->hw; 6914 u32 ctrl; 6915 u32 wufc = adapter->wol; 6916 #ifdef CONFIG_PM 6917 int retval = 0; 6918 #endif 6919 6920 rtnl_lock(); 6921 netif_device_detach(netdev); 6922 6923 if (netif_running(netdev)) 6924 ixgbe_close_suspend(adapter); 6925 6926 ixgbe_clear_interrupt_scheme(adapter); 6927 rtnl_unlock(); 6928 6929 #ifdef CONFIG_PM 6930 retval = pci_save_state(pdev); 6931 if (retval) 6932 return retval; 6933 6934 #endif 6935 if (hw->mac.ops.stop_link_on_d3) 6936 hw->mac.ops.stop_link_on_d3(hw); 6937 6938 if (wufc) { 6939 u32 fctrl; 6940 6941 ixgbe_set_rx_mode(netdev); 6942 6943 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6944 if (hw->mac.ops.enable_tx_laser) 6945 hw->mac.ops.enable_tx_laser(hw); 6946 6947 /* enable the reception of multicast packets */ 6948 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6949 fctrl |= IXGBE_FCTRL_MPE; 6950 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6951 6952 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6953 ctrl |= IXGBE_CTRL_GIO_DIS; 6954 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6955 6956 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6957 } else { 6958 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6959 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6960 } 6961 6962 switch (hw->mac.type) { 6963 case ixgbe_mac_82598EB: 6964 pci_wake_from_d3(pdev, false); 6965 break; 6966 case ixgbe_mac_82599EB: 6967 case ixgbe_mac_X540: 6968 case ixgbe_mac_X550: 6969 case ixgbe_mac_X550EM_x: 6970 case ixgbe_mac_x550em_a: 6971 pci_wake_from_d3(pdev, !!wufc); 6972 break; 6973 default: 6974 break; 6975 } 6976 6977 *enable_wake = !!wufc; 6978 if (hw->phy.ops.set_phy_power && !*enable_wake) 6979 hw->phy.ops.set_phy_power(hw, false); 6980 6981 ixgbe_release_hw_control(adapter); 6982 6983 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6984 pci_disable_device(pdev); 6985 6986 return 0; 6987 } 6988 6989 #ifdef CONFIG_PM 6990 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6991 { 6992 int retval; 6993 bool wake; 6994 6995 retval = __ixgbe_shutdown(pdev, &wake); 6996 if (retval) 6997 return retval; 6998 6999 if (wake) { 7000 pci_prepare_to_sleep(pdev); 7001 } else { 7002 pci_wake_from_d3(pdev, false); 7003 pci_set_power_state(pdev, PCI_D3hot); 7004 } 7005 7006 return 0; 7007 } 7008 #endif /* CONFIG_PM */ 7009 7010 static void ixgbe_shutdown(struct pci_dev *pdev) 7011 { 7012 bool wake; 7013 7014 __ixgbe_shutdown(pdev, &wake); 7015 7016 if (system_state == SYSTEM_POWER_OFF) { 7017 pci_wake_from_d3(pdev, wake); 7018 pci_set_power_state(pdev, PCI_D3hot); 7019 } 7020 } 7021 7022 /** 7023 * ixgbe_update_stats - Update the board statistics counters. 7024 * @adapter: board private structure 7025 **/ 7026 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7027 { 7028 struct net_device *netdev = adapter->netdev; 7029 struct ixgbe_hw *hw = &adapter->hw; 7030 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7031 u64 total_mpc = 0; 7032 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7033 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7034 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7035 u64 alloc_rx_page = 0; 7036 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7037 7038 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7039 test_bit(__IXGBE_RESETTING, &adapter->state)) 7040 return; 7041 7042 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7043 u64 rsc_count = 0; 7044 u64 rsc_flush = 0; 7045 for (i = 0; i < adapter->num_rx_queues; i++) { 7046 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7047 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7048 } 7049 adapter->rsc_total_count = rsc_count; 7050 adapter->rsc_total_flush = rsc_flush; 7051 } 7052 7053 for (i = 0; i < adapter->num_rx_queues; i++) { 7054 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 7055 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7056 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7057 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7058 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7059 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7060 bytes += rx_ring->stats.bytes; 7061 packets += rx_ring->stats.packets; 7062 } 7063 adapter->non_eop_descs = non_eop_descs; 7064 adapter->alloc_rx_page = alloc_rx_page; 7065 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7066 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7067 adapter->hw_csum_rx_error = hw_csum_rx_error; 7068 netdev->stats.rx_bytes = bytes; 7069 netdev->stats.rx_packets = packets; 7070 7071 bytes = 0; 7072 packets = 0; 7073 /* gather some stats to the adapter struct that are per queue */ 7074 for (i = 0; i < adapter->num_tx_queues; i++) { 7075 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7076 restart_queue += tx_ring->tx_stats.restart_queue; 7077 tx_busy += tx_ring->tx_stats.tx_busy; 7078 bytes += tx_ring->stats.bytes; 7079 packets += tx_ring->stats.packets; 7080 } 7081 for (i = 0; i < adapter->num_xdp_queues; i++) { 7082 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 7083 7084 restart_queue += xdp_ring->tx_stats.restart_queue; 7085 tx_busy += xdp_ring->tx_stats.tx_busy; 7086 bytes += xdp_ring->stats.bytes; 7087 packets += xdp_ring->stats.packets; 7088 } 7089 adapter->restart_queue = restart_queue; 7090 adapter->tx_busy = tx_busy; 7091 netdev->stats.tx_bytes = bytes; 7092 netdev->stats.tx_packets = packets; 7093 7094 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7095 7096 /* 8 register reads */ 7097 for (i = 0; i < 8; i++) { 7098 /* for packet buffers not used, the register should read 0 */ 7099 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7100 missed_rx += mpc; 7101 hwstats->mpc[i] += mpc; 7102 total_mpc += hwstats->mpc[i]; 7103 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7104 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7105 switch (hw->mac.type) { 7106 case ixgbe_mac_82598EB: 7107 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7108 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7109 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7110 hwstats->pxonrxc[i] += 7111 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7112 break; 7113 case ixgbe_mac_82599EB: 7114 case ixgbe_mac_X540: 7115 case ixgbe_mac_X550: 7116 case ixgbe_mac_X550EM_x: 7117 case ixgbe_mac_x550em_a: 7118 hwstats->pxonrxc[i] += 7119 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7120 break; 7121 default: 7122 break; 7123 } 7124 } 7125 7126 /*16 register reads */ 7127 for (i = 0; i < 16; i++) { 7128 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7129 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7130 if ((hw->mac.type == ixgbe_mac_82599EB) || 7131 (hw->mac.type == ixgbe_mac_X540) || 7132 (hw->mac.type == ixgbe_mac_X550) || 7133 (hw->mac.type == ixgbe_mac_X550EM_x) || 7134 (hw->mac.type == ixgbe_mac_x550em_a)) { 7135 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7136 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7137 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7138 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7139 } 7140 } 7141 7142 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7143 /* work around hardware counting issue */ 7144 hwstats->gprc -= missed_rx; 7145 7146 ixgbe_update_xoff_received(adapter); 7147 7148 /* 82598 hardware only has a 32 bit counter in the high register */ 7149 switch (hw->mac.type) { 7150 case ixgbe_mac_82598EB: 7151 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7152 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7153 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7154 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7155 break; 7156 case ixgbe_mac_X540: 7157 case ixgbe_mac_X550: 7158 case ixgbe_mac_X550EM_x: 7159 case ixgbe_mac_x550em_a: 7160 /* OS2BMC stats are X540 and later */ 7161 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7162 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7163 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7164 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7165 /* fall through */ 7166 case ixgbe_mac_82599EB: 7167 for (i = 0; i < 16; i++) 7168 adapter->hw_rx_no_dma_resources += 7169 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7170 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7171 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7172 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7173 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7174 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7175 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7176 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7177 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7178 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7179 #ifdef IXGBE_FCOE 7180 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7181 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7182 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7183 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7184 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7185 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7186 /* Add up per cpu counters for total ddp aloc fail */ 7187 if (adapter->fcoe.ddp_pool) { 7188 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7189 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7190 unsigned int cpu; 7191 u64 noddp = 0, noddp_ext_buff = 0; 7192 for_each_possible_cpu(cpu) { 7193 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7194 noddp += ddp_pool->noddp; 7195 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7196 } 7197 hwstats->fcoe_noddp = noddp; 7198 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7199 } 7200 #endif /* IXGBE_FCOE */ 7201 break; 7202 default: 7203 break; 7204 } 7205 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7206 hwstats->bprc += bprc; 7207 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7208 if (hw->mac.type == ixgbe_mac_82598EB) 7209 hwstats->mprc -= bprc; 7210 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7211 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7212 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7213 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7214 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7215 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7216 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7217 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7218 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7219 hwstats->lxontxc += lxon; 7220 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7221 hwstats->lxofftxc += lxoff; 7222 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7223 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7224 /* 7225 * 82598 errata - tx of flow control packets is included in tx counters 7226 */ 7227 xon_off_tot = lxon + lxoff; 7228 hwstats->gptc -= xon_off_tot; 7229 hwstats->mptc -= xon_off_tot; 7230 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7231 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7232 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7233 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7234 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7235 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7236 hwstats->ptc64 -= xon_off_tot; 7237 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7238 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7239 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7240 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7241 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7242 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7243 7244 /* Fill out the OS statistics structure */ 7245 netdev->stats.multicast = hwstats->mprc; 7246 7247 /* Rx Errors */ 7248 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7249 netdev->stats.rx_dropped = 0; 7250 netdev->stats.rx_length_errors = hwstats->rlec; 7251 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7252 netdev->stats.rx_missed_errors = total_mpc; 7253 } 7254 7255 /** 7256 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7257 * @adapter: pointer to the device adapter structure 7258 **/ 7259 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7260 { 7261 struct ixgbe_hw *hw = &adapter->hw; 7262 int i; 7263 7264 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7265 return; 7266 7267 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7268 7269 /* if interface is down do nothing */ 7270 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7271 return; 7272 7273 /* do nothing if we are not using signature filters */ 7274 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7275 return; 7276 7277 adapter->fdir_overflow++; 7278 7279 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7280 for (i = 0; i < adapter->num_tx_queues; i++) 7281 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7282 &(adapter->tx_ring[i]->state)); 7283 for (i = 0; i < adapter->num_xdp_queues; i++) 7284 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7285 &adapter->xdp_ring[i]->state); 7286 /* re-enable flow director interrupts */ 7287 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7288 } else { 7289 e_err(probe, "failed to finish FDIR re-initialization, " 7290 "ignored adding FDIR ATR filters\n"); 7291 } 7292 } 7293 7294 /** 7295 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7296 * @adapter: pointer to the device adapter structure 7297 * 7298 * This function serves two purposes. First it strobes the interrupt lines 7299 * in order to make certain interrupts are occurring. Secondly it sets the 7300 * bits needed to check for TX hangs. As a result we should immediately 7301 * determine if a hang has occurred. 7302 */ 7303 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7304 { 7305 struct ixgbe_hw *hw = &adapter->hw; 7306 u64 eics = 0; 7307 int i; 7308 7309 /* If we're down, removing or resetting, just bail */ 7310 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7311 test_bit(__IXGBE_REMOVING, &adapter->state) || 7312 test_bit(__IXGBE_RESETTING, &adapter->state)) 7313 return; 7314 7315 /* Force detection of hung controller */ 7316 if (netif_carrier_ok(adapter->netdev)) { 7317 for (i = 0; i < adapter->num_tx_queues; i++) 7318 set_check_for_tx_hang(adapter->tx_ring[i]); 7319 for (i = 0; i < adapter->num_xdp_queues; i++) 7320 set_check_for_tx_hang(adapter->xdp_ring[i]); 7321 } 7322 7323 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7324 /* 7325 * for legacy and MSI interrupts don't set any bits 7326 * that are enabled for EIAM, because this operation 7327 * would set *both* EIMS and EICS for any bit in EIAM 7328 */ 7329 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7330 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7331 } else { 7332 /* get one bit for every active tx/rx interrupt vector */ 7333 for (i = 0; i < adapter->num_q_vectors; i++) { 7334 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7335 if (qv->rx.ring || qv->tx.ring) 7336 eics |= BIT_ULL(i); 7337 } 7338 } 7339 7340 /* Cause software interrupt to ensure rings are cleaned */ 7341 ixgbe_irq_rearm_queues(adapter, eics); 7342 } 7343 7344 /** 7345 * ixgbe_watchdog_update_link - update the link status 7346 * @adapter: pointer to the device adapter structure 7347 **/ 7348 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7349 { 7350 struct ixgbe_hw *hw = &adapter->hw; 7351 u32 link_speed = adapter->link_speed; 7352 bool link_up = adapter->link_up; 7353 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7354 7355 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7356 return; 7357 7358 if (hw->mac.ops.check_link) { 7359 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7360 } else { 7361 /* always assume link is up, if no check link function */ 7362 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7363 link_up = true; 7364 } 7365 7366 if (adapter->ixgbe_ieee_pfc) 7367 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7368 7369 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7370 hw->mac.ops.fc_enable(hw); 7371 ixgbe_set_rx_drop_en(adapter); 7372 } 7373 7374 if (link_up || 7375 time_after(jiffies, (adapter->link_check_timeout + 7376 IXGBE_TRY_LINK_TIMEOUT))) { 7377 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7378 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7379 IXGBE_WRITE_FLUSH(hw); 7380 } 7381 7382 adapter->link_up = link_up; 7383 adapter->link_speed = link_speed; 7384 } 7385 7386 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7387 { 7388 #ifdef CONFIG_IXGBE_DCB 7389 struct net_device *netdev = adapter->netdev; 7390 struct dcb_app app = { 7391 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7392 .protocol = 0, 7393 }; 7394 u8 up = 0; 7395 7396 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7397 up = dcb_ieee_getapp_mask(netdev, &app); 7398 7399 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7400 #endif 7401 } 7402 7403 /** 7404 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7405 * print link up message 7406 * @adapter: pointer to the device adapter structure 7407 **/ 7408 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7409 { 7410 struct net_device *netdev = adapter->netdev; 7411 struct ixgbe_hw *hw = &adapter->hw; 7412 u32 link_speed = adapter->link_speed; 7413 const char *speed_str; 7414 bool flow_rx, flow_tx; 7415 7416 /* only continue if link was previously down */ 7417 if (netif_carrier_ok(netdev)) 7418 return; 7419 7420 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7421 7422 switch (hw->mac.type) { 7423 case ixgbe_mac_82598EB: { 7424 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7425 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7426 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7427 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7428 } 7429 break; 7430 case ixgbe_mac_X540: 7431 case ixgbe_mac_X550: 7432 case ixgbe_mac_X550EM_x: 7433 case ixgbe_mac_x550em_a: 7434 case ixgbe_mac_82599EB: { 7435 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7436 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7437 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7438 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7439 } 7440 break; 7441 default: 7442 flow_tx = false; 7443 flow_rx = false; 7444 break; 7445 } 7446 7447 adapter->last_rx_ptp_check = jiffies; 7448 7449 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7450 ixgbe_ptp_start_cyclecounter(adapter); 7451 7452 switch (link_speed) { 7453 case IXGBE_LINK_SPEED_10GB_FULL: 7454 speed_str = "10 Gbps"; 7455 break; 7456 case IXGBE_LINK_SPEED_5GB_FULL: 7457 speed_str = "5 Gbps"; 7458 break; 7459 case IXGBE_LINK_SPEED_2_5GB_FULL: 7460 speed_str = "2.5 Gbps"; 7461 break; 7462 case IXGBE_LINK_SPEED_1GB_FULL: 7463 speed_str = "1 Gbps"; 7464 break; 7465 case IXGBE_LINK_SPEED_100_FULL: 7466 speed_str = "100 Mbps"; 7467 break; 7468 case IXGBE_LINK_SPEED_10_FULL: 7469 speed_str = "10 Mbps"; 7470 break; 7471 default: 7472 speed_str = "unknown speed"; 7473 break; 7474 } 7475 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7476 ((flow_rx && flow_tx) ? "RX/TX" : 7477 (flow_rx ? "RX" : 7478 (flow_tx ? "TX" : "None")))); 7479 7480 netif_carrier_on(netdev); 7481 ixgbe_check_vf_rate_limit(adapter); 7482 7483 /* enable transmits */ 7484 netif_tx_wake_all_queues(adapter->netdev); 7485 7486 /* update the default user priority for VFs */ 7487 ixgbe_update_default_up(adapter); 7488 7489 /* ping all the active vfs to let them know link has changed */ 7490 ixgbe_ping_all_vfs(adapter); 7491 } 7492 7493 /** 7494 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7495 * print link down message 7496 * @adapter: pointer to the adapter structure 7497 **/ 7498 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7499 { 7500 struct net_device *netdev = adapter->netdev; 7501 struct ixgbe_hw *hw = &adapter->hw; 7502 7503 adapter->link_up = false; 7504 adapter->link_speed = 0; 7505 7506 /* only continue if link was up previously */ 7507 if (!netif_carrier_ok(netdev)) 7508 return; 7509 7510 /* poll for SFP+ cable when link is down */ 7511 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7512 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7513 7514 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7515 ixgbe_ptp_start_cyclecounter(adapter); 7516 7517 e_info(drv, "NIC Link is Down\n"); 7518 netif_carrier_off(netdev); 7519 7520 /* ping all the active vfs to let them know link has changed */ 7521 ixgbe_ping_all_vfs(adapter); 7522 } 7523 7524 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7525 { 7526 int i; 7527 7528 for (i = 0; i < adapter->num_tx_queues; i++) { 7529 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7530 7531 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7532 return true; 7533 } 7534 7535 for (i = 0; i < adapter->num_xdp_queues; i++) { 7536 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7537 7538 if (ring->next_to_use != ring->next_to_clean) 7539 return true; 7540 } 7541 7542 return false; 7543 } 7544 7545 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7546 { 7547 struct ixgbe_hw *hw = &adapter->hw; 7548 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7549 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7550 7551 int i, j; 7552 7553 if (!adapter->num_vfs) 7554 return false; 7555 7556 /* resetting the PF is only needed for MAC before X550 */ 7557 if (hw->mac.type >= ixgbe_mac_X550) 7558 return false; 7559 7560 for (i = 0; i < adapter->num_vfs; i++) { 7561 for (j = 0; j < q_per_pool; j++) { 7562 u32 h, t; 7563 7564 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7565 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7566 7567 if (h != t) 7568 return true; 7569 } 7570 } 7571 7572 return false; 7573 } 7574 7575 /** 7576 * ixgbe_watchdog_flush_tx - flush queues on link down 7577 * @adapter: pointer to the device adapter structure 7578 **/ 7579 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7580 { 7581 if (!netif_carrier_ok(adapter->netdev)) { 7582 if (ixgbe_ring_tx_pending(adapter) || 7583 ixgbe_vf_tx_pending(adapter)) { 7584 /* We've lost link, so the controller stops DMA, 7585 * but we've got queued Tx work that's never going 7586 * to get done, so reset controller to flush Tx. 7587 * (Do the reset outside of interrupt context). 7588 */ 7589 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7590 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7591 } 7592 } 7593 } 7594 7595 #ifdef CONFIG_PCI_IOV 7596 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7597 { 7598 struct ixgbe_hw *hw = &adapter->hw; 7599 struct pci_dev *pdev = adapter->pdev; 7600 unsigned int vf; 7601 u32 gpc; 7602 7603 if (!(netif_carrier_ok(adapter->netdev))) 7604 return; 7605 7606 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7607 if (gpc) /* If incrementing then no need for the check below */ 7608 return; 7609 /* Check to see if a bad DMA write target from an errant or 7610 * malicious VF has caused a PCIe error. If so then we can 7611 * issue a VFLR to the offending VF(s) and then resume without 7612 * requesting a full slot reset. 7613 */ 7614 7615 if (!pdev) 7616 return; 7617 7618 /* check status reg for all VFs owned by this PF */ 7619 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7620 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7621 u16 status_reg; 7622 7623 if (!vfdev) 7624 continue; 7625 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7626 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7627 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7628 pcie_flr(vfdev); 7629 } 7630 } 7631 7632 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7633 { 7634 u32 ssvpc; 7635 7636 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7637 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7638 adapter->num_vfs == 0) 7639 return; 7640 7641 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7642 7643 /* 7644 * ssvpc register is cleared on read, if zero then no 7645 * spoofed packets in the last interval. 7646 */ 7647 if (!ssvpc) 7648 return; 7649 7650 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7651 } 7652 #else 7653 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7654 { 7655 } 7656 7657 static void 7658 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7659 { 7660 } 7661 #endif /* CONFIG_PCI_IOV */ 7662 7663 7664 /** 7665 * ixgbe_watchdog_subtask - check and bring link up 7666 * @adapter: pointer to the device adapter structure 7667 **/ 7668 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7669 { 7670 /* if interface is down, removing or resetting, do nothing */ 7671 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7672 test_bit(__IXGBE_REMOVING, &adapter->state) || 7673 test_bit(__IXGBE_RESETTING, &adapter->state)) 7674 return; 7675 7676 ixgbe_watchdog_update_link(adapter); 7677 7678 if (adapter->link_up) 7679 ixgbe_watchdog_link_is_up(adapter); 7680 else 7681 ixgbe_watchdog_link_is_down(adapter); 7682 7683 ixgbe_check_for_bad_vf(adapter); 7684 ixgbe_spoof_check(adapter); 7685 ixgbe_update_stats(adapter); 7686 7687 ixgbe_watchdog_flush_tx(adapter); 7688 } 7689 7690 /** 7691 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7692 * @adapter: the ixgbe adapter structure 7693 **/ 7694 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7695 { 7696 struct ixgbe_hw *hw = &adapter->hw; 7697 s32 err; 7698 7699 /* not searching for SFP so there is nothing to do here */ 7700 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7701 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7702 return; 7703 7704 if (adapter->sfp_poll_time && 7705 time_after(adapter->sfp_poll_time, jiffies)) 7706 return; /* If not yet time to poll for SFP */ 7707 7708 /* someone else is in init, wait until next service event */ 7709 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7710 return; 7711 7712 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7713 7714 err = hw->phy.ops.identify_sfp(hw); 7715 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7716 goto sfp_out; 7717 7718 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7719 /* If no cable is present, then we need to reset 7720 * the next time we find a good cable. */ 7721 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7722 } 7723 7724 /* exit on error */ 7725 if (err) 7726 goto sfp_out; 7727 7728 /* exit if reset not needed */ 7729 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7730 goto sfp_out; 7731 7732 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7733 7734 /* 7735 * A module may be identified correctly, but the EEPROM may not have 7736 * support for that module. setup_sfp() will fail in that case, so 7737 * we should not allow that module to load. 7738 */ 7739 if (hw->mac.type == ixgbe_mac_82598EB) 7740 err = hw->phy.ops.reset(hw); 7741 else 7742 err = hw->mac.ops.setup_sfp(hw); 7743 7744 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7745 goto sfp_out; 7746 7747 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7748 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7749 7750 sfp_out: 7751 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7752 7753 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7754 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7755 e_dev_err("failed to initialize because an unsupported " 7756 "SFP+ module type was detected.\n"); 7757 e_dev_err("Reload the driver after installing a " 7758 "supported module.\n"); 7759 unregister_netdev(adapter->netdev); 7760 } 7761 } 7762 7763 /** 7764 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7765 * @adapter: the ixgbe adapter structure 7766 **/ 7767 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7768 { 7769 struct ixgbe_hw *hw = &adapter->hw; 7770 u32 cap_speed; 7771 u32 speed; 7772 bool autoneg = false; 7773 7774 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7775 return; 7776 7777 /* someone else is in init, wait until next service event */ 7778 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7779 return; 7780 7781 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7782 7783 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7784 7785 /* advertise highest capable link speed */ 7786 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7787 speed = IXGBE_LINK_SPEED_10GB_FULL; 7788 else 7789 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7790 IXGBE_LINK_SPEED_1GB_FULL); 7791 7792 if (hw->mac.ops.setup_link) 7793 hw->mac.ops.setup_link(hw, speed, true); 7794 7795 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7796 adapter->link_check_timeout = jiffies; 7797 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7798 } 7799 7800 /** 7801 * ixgbe_service_timer - Timer Call-back 7802 * @t: pointer to timer_list structure 7803 **/ 7804 static void ixgbe_service_timer(struct timer_list *t) 7805 { 7806 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7807 unsigned long next_event_offset; 7808 7809 /* poll faster when waiting for link */ 7810 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7811 next_event_offset = HZ / 10; 7812 else 7813 next_event_offset = HZ * 2; 7814 7815 /* Reset the timer */ 7816 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7817 7818 ixgbe_service_event_schedule(adapter); 7819 } 7820 7821 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7822 { 7823 struct ixgbe_hw *hw = &adapter->hw; 7824 u32 status; 7825 7826 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7827 return; 7828 7829 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7830 7831 if (!hw->phy.ops.handle_lasi) 7832 return; 7833 7834 status = hw->phy.ops.handle_lasi(&adapter->hw); 7835 if (status != IXGBE_ERR_OVERTEMP) 7836 return; 7837 7838 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7839 } 7840 7841 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7842 { 7843 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7844 return; 7845 7846 rtnl_lock(); 7847 /* If we're already down, removing or resetting, just bail */ 7848 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7849 test_bit(__IXGBE_REMOVING, &adapter->state) || 7850 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7851 rtnl_unlock(); 7852 return; 7853 } 7854 7855 ixgbe_dump(adapter); 7856 netdev_err(adapter->netdev, "Reset adapter\n"); 7857 adapter->tx_timeout_count++; 7858 7859 ixgbe_reinit_locked(adapter); 7860 rtnl_unlock(); 7861 } 7862 7863 /** 7864 * ixgbe_check_fw_error - Check firmware for errors 7865 * @adapter: the adapter private structure 7866 * 7867 * Check firmware errors in register FWSM 7868 */ 7869 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 7870 { 7871 struct ixgbe_hw *hw = &adapter->hw; 7872 u32 fwsm; 7873 7874 /* read fwsm.ext_err_ind register and log errors */ 7875 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 7876 7877 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 7878 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 7879 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 7880 fwsm); 7881 7882 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 7883 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 7884 return true; 7885 } 7886 7887 return false; 7888 } 7889 7890 /** 7891 * ixgbe_service_task - manages and runs subtasks 7892 * @work: pointer to work_struct containing our data 7893 **/ 7894 static void ixgbe_service_task(struct work_struct *work) 7895 { 7896 struct ixgbe_adapter *adapter = container_of(work, 7897 struct ixgbe_adapter, 7898 service_task); 7899 if (ixgbe_removed(adapter->hw.hw_addr)) { 7900 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7901 rtnl_lock(); 7902 ixgbe_down(adapter); 7903 rtnl_unlock(); 7904 } 7905 ixgbe_service_event_complete(adapter); 7906 return; 7907 } 7908 if (ixgbe_check_fw_error(adapter)) { 7909 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 7910 unregister_netdev(adapter->netdev); 7911 ixgbe_service_event_complete(adapter); 7912 return; 7913 } 7914 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7915 rtnl_lock(); 7916 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7917 udp_tunnel_get_rx_info(adapter->netdev); 7918 rtnl_unlock(); 7919 } 7920 ixgbe_reset_subtask(adapter); 7921 ixgbe_phy_interrupt_subtask(adapter); 7922 ixgbe_sfp_detection_subtask(adapter); 7923 ixgbe_sfp_link_config_subtask(adapter); 7924 ixgbe_check_overtemp_subtask(adapter); 7925 ixgbe_watchdog_subtask(adapter); 7926 ixgbe_fdir_reinit_subtask(adapter); 7927 ixgbe_check_hang_subtask(adapter); 7928 7929 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7930 ixgbe_ptp_overflow_check(adapter); 7931 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 7932 ixgbe_ptp_rx_hang(adapter); 7933 ixgbe_ptp_tx_hang(adapter); 7934 } 7935 7936 ixgbe_service_event_complete(adapter); 7937 } 7938 7939 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7940 struct ixgbe_tx_buffer *first, 7941 u8 *hdr_len, 7942 struct ixgbe_ipsec_tx_data *itd) 7943 { 7944 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7945 struct sk_buff *skb = first->skb; 7946 union { 7947 struct iphdr *v4; 7948 struct ipv6hdr *v6; 7949 unsigned char *hdr; 7950 } ip; 7951 union { 7952 struct tcphdr *tcp; 7953 struct udphdr *udp; 7954 unsigned char *hdr; 7955 } l4; 7956 u32 paylen, l4_offset; 7957 u32 fceof_saidx = 0; 7958 int err; 7959 7960 if (skb->ip_summed != CHECKSUM_PARTIAL) 7961 return 0; 7962 7963 if (!skb_is_gso(skb)) 7964 return 0; 7965 7966 err = skb_cow_head(skb, 0); 7967 if (err < 0) 7968 return err; 7969 7970 if (eth_p_mpls(first->protocol)) 7971 ip.hdr = skb_inner_network_header(skb); 7972 else 7973 ip.hdr = skb_network_header(skb); 7974 l4.hdr = skb_checksum_start(skb); 7975 7976 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7977 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 7978 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 7979 7980 /* initialize outer IP header fields */ 7981 if (ip.v4->version == 4) { 7982 unsigned char *csum_start = skb_checksum_start(skb); 7983 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7984 int len = csum_start - trans_start; 7985 7986 /* IP header will have to cancel out any data that 7987 * is not a part of the outer IP header, so set to 7988 * a reverse csum if needed, else init check to 0. 7989 */ 7990 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 7991 csum_fold(csum_partial(trans_start, 7992 len, 0)) : 0; 7993 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7994 7995 ip.v4->tot_len = 0; 7996 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7997 IXGBE_TX_FLAGS_CSUM | 7998 IXGBE_TX_FLAGS_IPV4; 7999 } else { 8000 ip.v6->payload_len = 0; 8001 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8002 IXGBE_TX_FLAGS_CSUM; 8003 } 8004 8005 /* determine offset of inner transport header */ 8006 l4_offset = l4.hdr - skb->data; 8007 8008 /* remove payload length from inner checksum */ 8009 paylen = skb->len - l4_offset; 8010 8011 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8012 /* compute length of segmentation header */ 8013 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8014 csum_replace_by_diff(&l4.tcp->check, 8015 (__force __wsum)htonl(paylen)); 8016 } else { 8017 /* compute length of segmentation header */ 8018 *hdr_len = sizeof(*l4.udp) + l4_offset; 8019 csum_replace_by_diff(&l4.udp->check, 8020 (__force __wsum)htonl(paylen)); 8021 } 8022 8023 /* update gso size and bytecount with header size */ 8024 first->gso_segs = skb_shinfo(skb)->gso_segs; 8025 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8026 8027 /* mss_l4len_id: use 0 as index for TSO */ 8028 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8029 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8030 8031 fceof_saidx |= itd->sa_idx; 8032 type_tucmd |= itd->flags | itd->trailer_len; 8033 8034 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8035 vlan_macip_lens = l4.hdr - ip.hdr; 8036 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8037 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8038 8039 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8040 mss_l4len_idx); 8041 8042 return 1; 8043 } 8044 8045 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 8046 { 8047 unsigned int offset = 0; 8048 8049 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 8050 8051 return offset == skb_checksum_start_offset(skb); 8052 } 8053 8054 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8055 struct ixgbe_tx_buffer *first, 8056 struct ixgbe_ipsec_tx_data *itd) 8057 { 8058 struct sk_buff *skb = first->skb; 8059 u32 vlan_macip_lens = 0; 8060 u32 fceof_saidx = 0; 8061 u32 type_tucmd = 0; 8062 8063 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8064 csum_failed: 8065 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8066 IXGBE_TX_FLAGS_CC))) 8067 return; 8068 goto no_csum; 8069 } 8070 8071 switch (skb->csum_offset) { 8072 case offsetof(struct tcphdr, check): 8073 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8074 /* fall through */ 8075 case offsetof(struct udphdr, check): 8076 break; 8077 case offsetof(struct sctphdr, checksum): 8078 /* validate that this is actually an SCTP request */ 8079 if (((first->protocol == htons(ETH_P_IP)) && 8080 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 8081 ((first->protocol == htons(ETH_P_IPV6)) && 8082 ixgbe_ipv6_csum_is_sctp(skb))) { 8083 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8084 break; 8085 } 8086 /* fall through */ 8087 default: 8088 skb_checksum_help(skb); 8089 goto csum_failed; 8090 } 8091 8092 /* update TX checksum flag */ 8093 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8094 vlan_macip_lens = skb_checksum_start_offset(skb) - 8095 skb_network_offset(skb); 8096 no_csum: 8097 /* vlan_macip_lens: MACLEN, VLAN tag */ 8098 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8099 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8100 8101 fceof_saidx |= itd->sa_idx; 8102 type_tucmd |= itd->flags | itd->trailer_len; 8103 8104 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8105 } 8106 8107 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8108 ((_flag <= _result) ? \ 8109 ((u32)(_input & _flag) * (_result / _flag)) : \ 8110 ((u32)(_input & _flag) / (_flag / _result))) 8111 8112 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8113 { 8114 /* set type for advanced descriptor with frame checksum insertion */ 8115 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8116 IXGBE_ADVTXD_DCMD_DEXT | 8117 IXGBE_ADVTXD_DCMD_IFCS; 8118 8119 /* set HW vlan bit if vlan is present */ 8120 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8121 IXGBE_ADVTXD_DCMD_VLE); 8122 8123 /* set segmentation enable bits for TSO/FSO */ 8124 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8125 IXGBE_ADVTXD_DCMD_TSE); 8126 8127 /* set timestamp bit if present */ 8128 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8129 IXGBE_ADVTXD_MAC_TSTAMP); 8130 8131 /* insert frame checksum */ 8132 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8133 8134 return cmd_type; 8135 } 8136 8137 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8138 u32 tx_flags, unsigned int paylen) 8139 { 8140 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8141 8142 /* enable L4 checksum for TSO and TX checksum offload */ 8143 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8144 IXGBE_TX_FLAGS_CSUM, 8145 IXGBE_ADVTXD_POPTS_TXSM); 8146 8147 /* enable IPv4 checksum for TSO */ 8148 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8149 IXGBE_TX_FLAGS_IPV4, 8150 IXGBE_ADVTXD_POPTS_IXSM); 8151 8152 /* enable IPsec */ 8153 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8154 IXGBE_TX_FLAGS_IPSEC, 8155 IXGBE_ADVTXD_POPTS_IPSEC); 8156 8157 /* 8158 * Check Context must be set if Tx switch is enabled, which it 8159 * always is for case where virtual functions are running 8160 */ 8161 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8162 IXGBE_TX_FLAGS_CC, 8163 IXGBE_ADVTXD_CC); 8164 8165 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8166 } 8167 8168 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8169 { 8170 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 8171 8172 /* Herbert's original patch had: 8173 * smp_mb__after_netif_stop_queue(); 8174 * but since that doesn't exist yet, just open code it. 8175 */ 8176 smp_mb(); 8177 8178 /* We need to check again in a case another CPU has just 8179 * made room available. 8180 */ 8181 if (likely(ixgbe_desc_unused(tx_ring) < size)) 8182 return -EBUSY; 8183 8184 /* A reprieve! - use start_queue because it doesn't call schedule */ 8185 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 8186 ++tx_ring->tx_stats.restart_queue; 8187 return 0; 8188 } 8189 8190 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8191 { 8192 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8193 return 0; 8194 8195 return __ixgbe_maybe_stop_tx(tx_ring, size); 8196 } 8197 8198 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8199 struct ixgbe_tx_buffer *first, 8200 const u8 hdr_len) 8201 { 8202 struct sk_buff *skb = first->skb; 8203 struct ixgbe_tx_buffer *tx_buffer; 8204 union ixgbe_adv_tx_desc *tx_desc; 8205 skb_frag_t *frag; 8206 dma_addr_t dma; 8207 unsigned int data_len, size; 8208 u32 tx_flags = first->tx_flags; 8209 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8210 u16 i = tx_ring->next_to_use; 8211 8212 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8213 8214 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8215 8216 size = skb_headlen(skb); 8217 data_len = skb->data_len; 8218 8219 #ifdef IXGBE_FCOE 8220 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8221 if (data_len < sizeof(struct fcoe_crc_eof)) { 8222 size -= sizeof(struct fcoe_crc_eof) - data_len; 8223 data_len = 0; 8224 } else { 8225 data_len -= sizeof(struct fcoe_crc_eof); 8226 } 8227 } 8228 8229 #endif 8230 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8231 8232 tx_buffer = first; 8233 8234 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8235 if (dma_mapping_error(tx_ring->dev, dma)) 8236 goto dma_error; 8237 8238 /* record length, and DMA address */ 8239 dma_unmap_len_set(tx_buffer, len, size); 8240 dma_unmap_addr_set(tx_buffer, dma, dma); 8241 8242 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8243 8244 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8245 tx_desc->read.cmd_type_len = 8246 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8247 8248 i++; 8249 tx_desc++; 8250 if (i == tx_ring->count) { 8251 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8252 i = 0; 8253 } 8254 tx_desc->read.olinfo_status = 0; 8255 8256 dma += IXGBE_MAX_DATA_PER_TXD; 8257 size -= IXGBE_MAX_DATA_PER_TXD; 8258 8259 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8260 } 8261 8262 if (likely(!data_len)) 8263 break; 8264 8265 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8266 8267 i++; 8268 tx_desc++; 8269 if (i == tx_ring->count) { 8270 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8271 i = 0; 8272 } 8273 tx_desc->read.olinfo_status = 0; 8274 8275 #ifdef IXGBE_FCOE 8276 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8277 #else 8278 size = skb_frag_size(frag); 8279 #endif 8280 data_len -= size; 8281 8282 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8283 DMA_TO_DEVICE); 8284 8285 tx_buffer = &tx_ring->tx_buffer_info[i]; 8286 } 8287 8288 /* write last descriptor with RS and EOP bits */ 8289 cmd_type |= size | IXGBE_TXD_CMD; 8290 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8291 8292 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8293 8294 /* set the timestamp */ 8295 first->time_stamp = jiffies; 8296 8297 skb_tx_timestamp(skb); 8298 8299 /* 8300 * Force memory writes to complete before letting h/w know there 8301 * are new descriptors to fetch. (Only applicable for weak-ordered 8302 * memory model archs, such as IA-64). 8303 * 8304 * We also need this memory barrier to make certain all of the 8305 * status bits have been updated before next_to_watch is written. 8306 */ 8307 wmb(); 8308 8309 /* set next_to_watch value indicating a packet is present */ 8310 first->next_to_watch = tx_desc; 8311 8312 i++; 8313 if (i == tx_ring->count) 8314 i = 0; 8315 8316 tx_ring->next_to_use = i; 8317 8318 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8319 8320 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8321 writel(i, tx_ring->tail); 8322 } 8323 8324 return 0; 8325 dma_error: 8326 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8327 8328 /* clear dma mappings for failed tx_buffer_info map */ 8329 for (;;) { 8330 tx_buffer = &tx_ring->tx_buffer_info[i]; 8331 if (dma_unmap_len(tx_buffer, len)) 8332 dma_unmap_page(tx_ring->dev, 8333 dma_unmap_addr(tx_buffer, dma), 8334 dma_unmap_len(tx_buffer, len), 8335 DMA_TO_DEVICE); 8336 dma_unmap_len_set(tx_buffer, len, 0); 8337 if (tx_buffer == first) 8338 break; 8339 if (i == 0) 8340 i += tx_ring->count; 8341 i--; 8342 } 8343 8344 dev_kfree_skb_any(first->skb); 8345 first->skb = NULL; 8346 8347 tx_ring->next_to_use = i; 8348 8349 return -1; 8350 } 8351 8352 static void ixgbe_atr(struct ixgbe_ring *ring, 8353 struct ixgbe_tx_buffer *first) 8354 { 8355 struct ixgbe_q_vector *q_vector = ring->q_vector; 8356 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8357 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8358 union { 8359 unsigned char *network; 8360 struct iphdr *ipv4; 8361 struct ipv6hdr *ipv6; 8362 } hdr; 8363 struct tcphdr *th; 8364 unsigned int hlen; 8365 struct sk_buff *skb; 8366 __be16 vlan_id; 8367 int l4_proto; 8368 8369 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8370 if (!q_vector) 8371 return; 8372 8373 /* do nothing if sampling is disabled */ 8374 if (!ring->atr_sample_rate) 8375 return; 8376 8377 ring->atr_count++; 8378 8379 /* currently only IPv4/IPv6 with TCP is supported */ 8380 if ((first->protocol != htons(ETH_P_IP)) && 8381 (first->protocol != htons(ETH_P_IPV6))) 8382 return; 8383 8384 /* snag network header to get L4 type and address */ 8385 skb = first->skb; 8386 hdr.network = skb_network_header(skb); 8387 if (unlikely(hdr.network <= skb->data)) 8388 return; 8389 if (skb->encapsulation && 8390 first->protocol == htons(ETH_P_IP) && 8391 hdr.ipv4->protocol == IPPROTO_UDP) { 8392 struct ixgbe_adapter *adapter = q_vector->adapter; 8393 8394 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8395 VXLAN_HEADROOM)) 8396 return; 8397 8398 /* verify the port is recognized as VXLAN */ 8399 if (adapter->vxlan_port && 8400 udp_hdr(skb)->dest == adapter->vxlan_port) 8401 hdr.network = skb_inner_network_header(skb); 8402 8403 if (adapter->geneve_port && 8404 udp_hdr(skb)->dest == adapter->geneve_port) 8405 hdr.network = skb_inner_network_header(skb); 8406 } 8407 8408 /* Make sure we have at least [minimum IPv4 header + TCP] 8409 * or [IPv6 header] bytes 8410 */ 8411 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8412 return; 8413 8414 /* Currently only IPv4/IPv6 with TCP is supported */ 8415 switch (hdr.ipv4->version) { 8416 case IPVERSION: 8417 /* access ihl as u8 to avoid unaligned access on ia64 */ 8418 hlen = (hdr.network[0] & 0x0F) << 2; 8419 l4_proto = hdr.ipv4->protocol; 8420 break; 8421 case 6: 8422 hlen = hdr.network - skb->data; 8423 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8424 hlen -= hdr.network - skb->data; 8425 break; 8426 default: 8427 return; 8428 } 8429 8430 if (l4_proto != IPPROTO_TCP) 8431 return; 8432 8433 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8434 hlen + sizeof(struct tcphdr))) 8435 return; 8436 8437 th = (struct tcphdr *)(hdr.network + hlen); 8438 8439 /* skip this packet since the socket is closing */ 8440 if (th->fin) 8441 return; 8442 8443 /* sample on all syn packets or once every atr sample count */ 8444 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8445 return; 8446 8447 /* reset sample count */ 8448 ring->atr_count = 0; 8449 8450 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8451 8452 /* 8453 * src and dst are inverted, think how the receiver sees them 8454 * 8455 * The input is broken into two sections, a non-compressed section 8456 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8457 * is XORed together and stored in the compressed dword. 8458 */ 8459 input.formatted.vlan_id = vlan_id; 8460 8461 /* 8462 * since src port and flex bytes occupy the same word XOR them together 8463 * and write the value to source port portion of compressed dword 8464 */ 8465 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8466 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8467 else 8468 common.port.src ^= th->dest ^ first->protocol; 8469 common.port.dst ^= th->source; 8470 8471 switch (hdr.ipv4->version) { 8472 case IPVERSION: 8473 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8474 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8475 break; 8476 case 6: 8477 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8478 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8479 hdr.ipv6->saddr.s6_addr32[1] ^ 8480 hdr.ipv6->saddr.s6_addr32[2] ^ 8481 hdr.ipv6->saddr.s6_addr32[3] ^ 8482 hdr.ipv6->daddr.s6_addr32[0] ^ 8483 hdr.ipv6->daddr.s6_addr32[1] ^ 8484 hdr.ipv6->daddr.s6_addr32[2] ^ 8485 hdr.ipv6->daddr.s6_addr32[3]; 8486 break; 8487 default: 8488 break; 8489 } 8490 8491 if (hdr.network != skb_network_header(skb)) 8492 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8493 8494 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8495 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8496 input, common, ring->queue_index); 8497 } 8498 8499 #ifdef IXGBE_FCOE 8500 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8501 struct net_device *sb_dev) 8502 { 8503 struct ixgbe_adapter *adapter; 8504 struct ixgbe_ring_feature *f; 8505 int txq; 8506 8507 if (sb_dev) { 8508 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8509 struct net_device *vdev = sb_dev; 8510 8511 txq = vdev->tc_to_txq[tc].offset; 8512 txq += reciprocal_scale(skb_get_hash(skb), 8513 vdev->tc_to_txq[tc].count); 8514 8515 return txq; 8516 } 8517 8518 /* 8519 * only execute the code below if protocol is FCoE 8520 * or FIP and we have FCoE enabled on the adapter 8521 */ 8522 switch (vlan_get_protocol(skb)) { 8523 case htons(ETH_P_FCOE): 8524 case htons(ETH_P_FIP): 8525 adapter = netdev_priv(dev); 8526 8527 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8528 break; 8529 /* fall through */ 8530 default: 8531 return netdev_pick_tx(dev, skb, sb_dev); 8532 } 8533 8534 f = &adapter->ring_feature[RING_F_FCOE]; 8535 8536 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8537 smp_processor_id(); 8538 8539 while (txq >= f->indices) 8540 txq -= f->indices; 8541 8542 return txq + f->offset; 8543 } 8544 8545 #endif 8546 int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8547 struct xdp_frame *xdpf) 8548 { 8549 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8550 struct ixgbe_tx_buffer *tx_buffer; 8551 union ixgbe_adv_tx_desc *tx_desc; 8552 u32 len, cmd_type; 8553 dma_addr_t dma; 8554 u16 i; 8555 8556 len = xdpf->len; 8557 8558 if (unlikely(!ixgbe_desc_unused(ring))) 8559 return IXGBE_XDP_CONSUMED; 8560 8561 dma = dma_map_single(ring->dev, xdpf->data, len, DMA_TO_DEVICE); 8562 if (dma_mapping_error(ring->dev, dma)) 8563 return IXGBE_XDP_CONSUMED; 8564 8565 /* record the location of the first descriptor for this packet */ 8566 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8567 tx_buffer->bytecount = len; 8568 tx_buffer->gso_segs = 1; 8569 tx_buffer->protocol = 0; 8570 8571 i = ring->next_to_use; 8572 tx_desc = IXGBE_TX_DESC(ring, i); 8573 8574 dma_unmap_len_set(tx_buffer, len, len); 8575 dma_unmap_addr_set(tx_buffer, dma, dma); 8576 tx_buffer->xdpf = xdpf; 8577 8578 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8579 8580 /* put descriptor type bits */ 8581 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8582 IXGBE_ADVTXD_DCMD_DEXT | 8583 IXGBE_ADVTXD_DCMD_IFCS; 8584 cmd_type |= len | IXGBE_TXD_CMD; 8585 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8586 tx_desc->read.olinfo_status = 8587 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8588 8589 /* Avoid any potential race with xdp_xmit and cleanup */ 8590 smp_wmb(); 8591 8592 /* set next_to_watch value indicating a packet is present */ 8593 i++; 8594 if (i == ring->count) 8595 i = 0; 8596 8597 tx_buffer->next_to_watch = tx_desc; 8598 ring->next_to_use = i; 8599 8600 return IXGBE_XDP_TX; 8601 } 8602 8603 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8604 struct ixgbe_adapter *adapter, 8605 struct ixgbe_ring *tx_ring) 8606 { 8607 struct ixgbe_tx_buffer *first; 8608 int tso; 8609 u32 tx_flags = 0; 8610 unsigned short f; 8611 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8612 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8613 __be16 protocol = skb->protocol; 8614 u8 hdr_len = 0; 8615 8616 /* 8617 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8618 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8619 * + 2 desc gap to keep tail from touching head, 8620 * + 1 desc for context descriptor, 8621 * otherwise try next time 8622 */ 8623 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8624 count += TXD_USE_COUNT(skb_frag_size( 8625 &skb_shinfo(skb)->frags[f])); 8626 8627 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8628 tx_ring->tx_stats.tx_busy++; 8629 return NETDEV_TX_BUSY; 8630 } 8631 8632 /* record the location of the first descriptor for this packet */ 8633 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8634 first->skb = skb; 8635 first->bytecount = skb->len; 8636 first->gso_segs = 1; 8637 8638 /* if we have a HW VLAN tag being added default to the HW one */ 8639 if (skb_vlan_tag_present(skb)) { 8640 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8641 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8642 /* else if it is a SW VLAN check the next protocol and store the tag */ 8643 } else if (protocol == htons(ETH_P_8021Q)) { 8644 struct vlan_hdr *vhdr, _vhdr; 8645 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8646 if (!vhdr) 8647 goto out_drop; 8648 8649 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8650 IXGBE_TX_FLAGS_VLAN_SHIFT; 8651 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8652 } 8653 protocol = vlan_get_protocol(skb); 8654 8655 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8656 adapter->ptp_clock) { 8657 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 8658 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8659 &adapter->state)) { 8660 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8661 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8662 8663 /* schedule check for Tx timestamp */ 8664 adapter->ptp_tx_skb = skb_get(skb); 8665 adapter->ptp_tx_start = jiffies; 8666 schedule_work(&adapter->ptp_tx_work); 8667 } else { 8668 adapter->tx_hwtstamp_skipped++; 8669 } 8670 } 8671 8672 #ifdef CONFIG_PCI_IOV 8673 /* 8674 * Use the l2switch_enable flag - would be false if the DMA 8675 * Tx switch had been disabled. 8676 */ 8677 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8678 tx_flags |= IXGBE_TX_FLAGS_CC; 8679 8680 #endif 8681 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8682 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8683 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8684 (skb->priority != TC_PRIO_CONTROL))) { 8685 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8686 tx_flags |= (skb->priority & 0x7) << 8687 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8688 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8689 struct vlan_ethhdr *vhdr; 8690 8691 if (skb_cow_head(skb, 0)) 8692 goto out_drop; 8693 vhdr = (struct vlan_ethhdr *)skb->data; 8694 vhdr->h_vlan_TCI = htons(tx_flags >> 8695 IXGBE_TX_FLAGS_VLAN_SHIFT); 8696 } else { 8697 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8698 } 8699 } 8700 8701 /* record initial flags and protocol */ 8702 first->tx_flags = tx_flags; 8703 first->protocol = protocol; 8704 8705 #ifdef IXGBE_FCOE 8706 /* setup tx offload for FCoE */ 8707 if ((protocol == htons(ETH_P_FCOE)) && 8708 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8709 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8710 if (tso < 0) 8711 goto out_drop; 8712 8713 goto xmit_fcoe; 8714 } 8715 8716 #endif /* IXGBE_FCOE */ 8717 8718 #ifdef CONFIG_IXGBE_IPSEC 8719 if (xfrm_offload(skb) && 8720 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8721 goto out_drop; 8722 #endif 8723 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8724 if (tso < 0) 8725 goto out_drop; 8726 else if (!tso) 8727 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8728 8729 /* add the ATR filter if ATR is on */ 8730 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8731 ixgbe_atr(tx_ring, first); 8732 8733 #ifdef IXGBE_FCOE 8734 xmit_fcoe: 8735 #endif /* IXGBE_FCOE */ 8736 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8737 goto cleanup_tx_timestamp; 8738 8739 return NETDEV_TX_OK; 8740 8741 out_drop: 8742 dev_kfree_skb_any(first->skb); 8743 first->skb = NULL; 8744 cleanup_tx_timestamp: 8745 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8746 dev_kfree_skb_any(adapter->ptp_tx_skb); 8747 adapter->ptp_tx_skb = NULL; 8748 cancel_work_sync(&adapter->ptp_tx_work); 8749 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8750 } 8751 8752 return NETDEV_TX_OK; 8753 } 8754 8755 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8756 struct net_device *netdev, 8757 struct ixgbe_ring *ring) 8758 { 8759 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8760 struct ixgbe_ring *tx_ring; 8761 8762 /* 8763 * The minimum packet size for olinfo paylen is 17 so pad the skb 8764 * in order to meet this minimum size requirement. 8765 */ 8766 if (skb_put_padto(skb, 17)) 8767 return NETDEV_TX_OK; 8768 8769 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 8770 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8771 return NETDEV_TX_BUSY; 8772 8773 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8774 } 8775 8776 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8777 struct net_device *netdev) 8778 { 8779 return __ixgbe_xmit_frame(skb, netdev, NULL); 8780 } 8781 8782 /** 8783 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8784 * @netdev: network interface device structure 8785 * @p: pointer to an address structure 8786 * 8787 * Returns 0 on success, negative on failure 8788 **/ 8789 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8790 { 8791 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8792 struct ixgbe_hw *hw = &adapter->hw; 8793 struct sockaddr *addr = p; 8794 8795 if (!is_valid_ether_addr(addr->sa_data)) 8796 return -EADDRNOTAVAIL; 8797 8798 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8799 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8800 8801 ixgbe_mac_set_default_filter(adapter); 8802 8803 return 0; 8804 } 8805 8806 static int 8807 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8808 { 8809 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8810 struct ixgbe_hw *hw = &adapter->hw; 8811 u16 value; 8812 int rc; 8813 8814 if (adapter->mii_bus) { 8815 int regnum = addr; 8816 8817 if (devad != MDIO_DEVAD_NONE) 8818 regnum |= (devad << 16) | MII_ADDR_C45; 8819 8820 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8821 } 8822 8823 if (prtad != hw->phy.mdio.prtad) 8824 return -EINVAL; 8825 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8826 if (!rc) 8827 rc = value; 8828 return rc; 8829 } 8830 8831 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8832 u16 addr, u16 value) 8833 { 8834 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8835 struct ixgbe_hw *hw = &adapter->hw; 8836 8837 if (adapter->mii_bus) { 8838 int regnum = addr; 8839 8840 if (devad != MDIO_DEVAD_NONE) 8841 regnum |= (devad << 16) | MII_ADDR_C45; 8842 8843 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8844 } 8845 8846 if (prtad != hw->phy.mdio.prtad) 8847 return -EINVAL; 8848 return hw->phy.ops.write_reg(hw, addr, devad, value); 8849 } 8850 8851 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8852 { 8853 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8854 8855 switch (cmd) { 8856 case SIOCSHWTSTAMP: 8857 return ixgbe_ptp_set_ts_config(adapter, req); 8858 case SIOCGHWTSTAMP: 8859 return ixgbe_ptp_get_ts_config(adapter, req); 8860 case SIOCGMIIPHY: 8861 if (!adapter->hw.phy.ops.read_reg) 8862 return -EOPNOTSUPP; 8863 /* fall through */ 8864 default: 8865 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8866 } 8867 } 8868 8869 /** 8870 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8871 * netdev->dev_addrs 8872 * @dev: network interface device structure 8873 * 8874 * Returns non-zero on failure 8875 **/ 8876 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8877 { 8878 int err = 0; 8879 struct ixgbe_adapter *adapter = netdev_priv(dev); 8880 struct ixgbe_hw *hw = &adapter->hw; 8881 8882 if (is_valid_ether_addr(hw->mac.san_addr)) { 8883 rtnl_lock(); 8884 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8885 rtnl_unlock(); 8886 8887 /* update SAN MAC vmdq pool selection */ 8888 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8889 } 8890 return err; 8891 } 8892 8893 /** 8894 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8895 * netdev->dev_addrs 8896 * @dev: network interface device structure 8897 * 8898 * Returns non-zero on failure 8899 **/ 8900 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8901 { 8902 int err = 0; 8903 struct ixgbe_adapter *adapter = netdev_priv(dev); 8904 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8905 8906 if (is_valid_ether_addr(mac->san_addr)) { 8907 rtnl_lock(); 8908 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8909 rtnl_unlock(); 8910 } 8911 return err; 8912 } 8913 8914 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8915 struct ixgbe_ring *ring) 8916 { 8917 u64 bytes, packets; 8918 unsigned int start; 8919 8920 if (ring) { 8921 do { 8922 start = u64_stats_fetch_begin_irq(&ring->syncp); 8923 packets = ring->stats.packets; 8924 bytes = ring->stats.bytes; 8925 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8926 stats->tx_packets += packets; 8927 stats->tx_bytes += bytes; 8928 } 8929 } 8930 8931 static void ixgbe_get_stats64(struct net_device *netdev, 8932 struct rtnl_link_stats64 *stats) 8933 { 8934 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8935 int i; 8936 8937 rcu_read_lock(); 8938 for (i = 0; i < adapter->num_rx_queues; i++) { 8939 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8940 u64 bytes, packets; 8941 unsigned int start; 8942 8943 if (ring) { 8944 do { 8945 start = u64_stats_fetch_begin_irq(&ring->syncp); 8946 packets = ring->stats.packets; 8947 bytes = ring->stats.bytes; 8948 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8949 stats->rx_packets += packets; 8950 stats->rx_bytes += bytes; 8951 } 8952 } 8953 8954 for (i = 0; i < adapter->num_tx_queues; i++) { 8955 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8956 8957 ixgbe_get_ring_stats64(stats, ring); 8958 } 8959 for (i = 0; i < adapter->num_xdp_queues; i++) { 8960 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8961 8962 ixgbe_get_ring_stats64(stats, ring); 8963 } 8964 rcu_read_unlock(); 8965 8966 /* following stats updated by ixgbe_watchdog_task() */ 8967 stats->multicast = netdev->stats.multicast; 8968 stats->rx_errors = netdev->stats.rx_errors; 8969 stats->rx_length_errors = netdev->stats.rx_length_errors; 8970 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8971 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8972 } 8973 8974 #ifdef CONFIG_IXGBE_DCB 8975 /** 8976 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8977 * @adapter: pointer to ixgbe_adapter 8978 * @tc: number of traffic classes currently enabled 8979 * 8980 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8981 * 802.1Q priority maps to a packet buffer that exists. 8982 */ 8983 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8984 { 8985 struct ixgbe_hw *hw = &adapter->hw; 8986 u32 reg, rsave; 8987 int i; 8988 8989 /* 82598 have a static priority to TC mapping that can not 8990 * be changed so no validation is needed. 8991 */ 8992 if (hw->mac.type == ixgbe_mac_82598EB) 8993 return; 8994 8995 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8996 rsave = reg; 8997 8998 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8999 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 9000 9001 /* If up2tc is out of bounds default to zero */ 9002 if (up2tc > tc) 9003 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9004 } 9005 9006 if (reg != rsave) 9007 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9008 9009 return; 9010 } 9011 9012 /** 9013 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9014 * @adapter: Pointer to adapter struct 9015 * 9016 * Populate the netdev user priority to tc map 9017 */ 9018 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9019 { 9020 struct net_device *dev = adapter->netdev; 9021 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9022 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9023 u8 prio; 9024 9025 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9026 u8 tc = 0; 9027 9028 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9029 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9030 else if (ets) 9031 tc = ets->prio_tc[prio]; 9032 9033 netdev_set_prio_tc_map(dev, prio, tc); 9034 } 9035 } 9036 9037 #endif /* CONFIG_IXGBE_DCB */ 9038 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, void *data) 9039 { 9040 struct ixgbe_adapter *adapter = data; 9041 struct ixgbe_fwd_adapter *accel; 9042 int pool; 9043 9044 /* we only care about macvlans... */ 9045 if (!netif_is_macvlan(vdev)) 9046 return 0; 9047 9048 /* that have hardware offload enabled... */ 9049 accel = macvlan_accel_priv(vdev); 9050 if (!accel) 9051 return 0; 9052 9053 /* If we can relocate to a different bit do so */ 9054 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9055 if (pool < adapter->num_rx_pools) { 9056 set_bit(pool, adapter->fwd_bitmask); 9057 accel->pool = pool; 9058 return 0; 9059 } 9060 9061 /* if we cannot find a free pool then disable the offload */ 9062 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9063 macvlan_release_l2fw_offload(vdev); 9064 9065 /* unbind the queues and drop the subordinate channel config */ 9066 netdev_unbind_sb_channel(adapter->netdev, vdev); 9067 netdev_set_sb_channel(vdev, 0); 9068 9069 kfree(accel); 9070 9071 return 0; 9072 } 9073 9074 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9075 { 9076 struct ixgbe_adapter *adapter = netdev_priv(dev); 9077 9078 /* flush any stale bits out of the fwd bitmask */ 9079 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9080 9081 /* walk through upper devices reassigning pools */ 9082 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9083 adapter); 9084 } 9085 9086 /** 9087 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9088 * 9089 * @dev: net device to configure 9090 * @tc: number of traffic classes to enable 9091 */ 9092 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9093 { 9094 struct ixgbe_adapter *adapter = netdev_priv(dev); 9095 struct ixgbe_hw *hw = &adapter->hw; 9096 9097 /* Hardware supports up to 8 traffic classes */ 9098 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9099 return -EINVAL; 9100 9101 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9102 return -EINVAL; 9103 9104 /* Hardware has to reinitialize queues and interrupts to 9105 * match packet buffer alignment. Unfortunately, the 9106 * hardware is not flexible enough to do this dynamically. 9107 */ 9108 if (netif_running(dev)) 9109 ixgbe_close(dev); 9110 else 9111 ixgbe_reset(adapter); 9112 9113 ixgbe_clear_interrupt_scheme(adapter); 9114 9115 #ifdef CONFIG_IXGBE_DCB 9116 if (tc) { 9117 if (adapter->xdp_prog) { 9118 e_warn(probe, "DCB is not supported with XDP\n"); 9119 9120 ixgbe_init_interrupt_scheme(adapter); 9121 if (netif_running(dev)) 9122 ixgbe_open(dev); 9123 return -EINVAL; 9124 } 9125 9126 netdev_set_num_tc(dev, tc); 9127 ixgbe_set_prio_tc_map(adapter); 9128 9129 adapter->hw_tcs = tc; 9130 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9131 9132 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9133 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9134 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9135 } 9136 } else { 9137 netdev_reset_tc(dev); 9138 9139 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9140 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9141 9142 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9143 adapter->hw_tcs = tc; 9144 9145 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9146 adapter->dcb_cfg.pfc_mode_enable = false; 9147 } 9148 9149 ixgbe_validate_rtr(adapter, tc); 9150 9151 #endif /* CONFIG_IXGBE_DCB */ 9152 ixgbe_init_interrupt_scheme(adapter); 9153 9154 ixgbe_defrag_macvlan_pools(dev); 9155 9156 if (netif_running(dev)) 9157 return ixgbe_open(dev); 9158 9159 return 0; 9160 } 9161 9162 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9163 struct tc_cls_u32_offload *cls) 9164 { 9165 u32 hdl = cls->knode.handle; 9166 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9167 u32 loc = cls->knode.handle & 0xfffff; 9168 int err = 0, i, j; 9169 struct ixgbe_jump_table *jump = NULL; 9170 9171 if (loc > IXGBE_MAX_HW_ENTRIES) 9172 return -EINVAL; 9173 9174 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9175 return -EINVAL; 9176 9177 /* Clear this filter in the link data it is associated with */ 9178 if (uhtid != 0x800) { 9179 jump = adapter->jump_tables[uhtid]; 9180 if (!jump) 9181 return -EINVAL; 9182 if (!test_bit(loc - 1, jump->child_loc_map)) 9183 return -EINVAL; 9184 clear_bit(loc - 1, jump->child_loc_map); 9185 } 9186 9187 /* Check if the filter being deleted is a link */ 9188 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9189 jump = adapter->jump_tables[i]; 9190 if (jump && jump->link_hdl == hdl) { 9191 /* Delete filters in the hardware in the child hash 9192 * table associated with this link 9193 */ 9194 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9195 if (!test_bit(j, jump->child_loc_map)) 9196 continue; 9197 spin_lock(&adapter->fdir_perfect_lock); 9198 err = ixgbe_update_ethtool_fdir_entry(adapter, 9199 NULL, 9200 j + 1); 9201 spin_unlock(&adapter->fdir_perfect_lock); 9202 clear_bit(j, jump->child_loc_map); 9203 } 9204 /* Remove resources for this link */ 9205 kfree(jump->input); 9206 kfree(jump->mask); 9207 kfree(jump); 9208 adapter->jump_tables[i] = NULL; 9209 return err; 9210 } 9211 } 9212 9213 spin_lock(&adapter->fdir_perfect_lock); 9214 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9215 spin_unlock(&adapter->fdir_perfect_lock); 9216 return err; 9217 } 9218 9219 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9220 struct tc_cls_u32_offload *cls) 9221 { 9222 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9223 9224 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9225 return -EINVAL; 9226 9227 /* This ixgbe devices do not support hash tables at the moment 9228 * so abort when given hash tables. 9229 */ 9230 if (cls->hnode.divisor > 0) 9231 return -EINVAL; 9232 9233 set_bit(uhtid - 1, &adapter->tables); 9234 return 0; 9235 } 9236 9237 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9238 struct tc_cls_u32_offload *cls) 9239 { 9240 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9241 9242 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9243 return -EINVAL; 9244 9245 clear_bit(uhtid - 1, &adapter->tables); 9246 return 0; 9247 } 9248 9249 #ifdef CONFIG_NET_CLS_ACT 9250 struct upper_walk_data { 9251 struct ixgbe_adapter *adapter; 9252 u64 action; 9253 int ifindex; 9254 u8 queue; 9255 }; 9256 9257 static int get_macvlan_queue(struct net_device *upper, void *_data) 9258 { 9259 if (netif_is_macvlan(upper)) { 9260 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9261 struct upper_walk_data *data = _data; 9262 struct ixgbe_adapter *adapter = data->adapter; 9263 int ifindex = data->ifindex; 9264 9265 if (vadapter && upper->ifindex == ifindex) { 9266 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9267 data->action = data->queue; 9268 return 1; 9269 } 9270 } 9271 9272 return 0; 9273 } 9274 9275 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9276 u8 *queue, u64 *action) 9277 { 9278 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9279 unsigned int num_vfs = adapter->num_vfs, vf; 9280 struct upper_walk_data data; 9281 struct net_device *upper; 9282 9283 /* redirect to a SRIOV VF */ 9284 for (vf = 0; vf < num_vfs; ++vf) { 9285 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9286 if (upper->ifindex == ifindex) { 9287 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9288 *action = vf + 1; 9289 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9290 return 0; 9291 } 9292 } 9293 9294 /* redirect to a offloaded macvlan netdev */ 9295 data.adapter = adapter; 9296 data.ifindex = ifindex; 9297 data.action = 0; 9298 data.queue = 0; 9299 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9300 get_macvlan_queue, &data)) { 9301 *action = data.action; 9302 *queue = data.queue; 9303 9304 return 0; 9305 } 9306 9307 return -EINVAL; 9308 } 9309 9310 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9311 struct tcf_exts *exts, u64 *action, u8 *queue) 9312 { 9313 const struct tc_action *a; 9314 int i; 9315 9316 if (!tcf_exts_has_actions(exts)) 9317 return -EINVAL; 9318 9319 tcf_exts_for_each_action(i, a, exts) { 9320 /* Drop action */ 9321 if (is_tcf_gact_shot(a)) { 9322 *action = IXGBE_FDIR_DROP_QUEUE; 9323 *queue = IXGBE_FDIR_DROP_QUEUE; 9324 return 0; 9325 } 9326 9327 /* Redirect to a VF or a offloaded macvlan */ 9328 if (is_tcf_mirred_egress_redirect(a)) { 9329 struct net_device *dev = tcf_mirred_dev(a); 9330 9331 if (!dev) 9332 return -EINVAL; 9333 return handle_redirect_action(adapter, dev->ifindex, 9334 queue, action); 9335 } 9336 9337 return -EINVAL; 9338 } 9339 9340 return -EINVAL; 9341 } 9342 #else 9343 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9344 struct tcf_exts *exts, u64 *action, u8 *queue) 9345 { 9346 return -EINVAL; 9347 } 9348 #endif /* CONFIG_NET_CLS_ACT */ 9349 9350 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9351 union ixgbe_atr_input *mask, 9352 struct tc_cls_u32_offload *cls, 9353 struct ixgbe_mat_field *field_ptr, 9354 struct ixgbe_nexthdr *nexthdr) 9355 { 9356 int i, j, off; 9357 __be32 val, m; 9358 bool found_entry = false, found_jump_field = false; 9359 9360 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9361 off = cls->knode.sel->keys[i].off; 9362 val = cls->knode.sel->keys[i].val; 9363 m = cls->knode.sel->keys[i].mask; 9364 9365 for (j = 0; field_ptr[j].val; j++) { 9366 if (field_ptr[j].off == off) { 9367 field_ptr[j].val(input, mask, (__force u32)val, 9368 (__force u32)m); 9369 input->filter.formatted.flow_type |= 9370 field_ptr[j].type; 9371 found_entry = true; 9372 break; 9373 } 9374 } 9375 if (nexthdr) { 9376 if (nexthdr->off == cls->knode.sel->keys[i].off && 9377 nexthdr->val == 9378 (__force u32)cls->knode.sel->keys[i].val && 9379 nexthdr->mask == 9380 (__force u32)cls->knode.sel->keys[i].mask) 9381 found_jump_field = true; 9382 else 9383 continue; 9384 } 9385 } 9386 9387 if (nexthdr && !found_jump_field) 9388 return -EINVAL; 9389 9390 if (!found_entry) 9391 return 0; 9392 9393 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9394 IXGBE_ATR_L4TYPE_MASK; 9395 9396 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9397 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9398 9399 return 0; 9400 } 9401 9402 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9403 struct tc_cls_u32_offload *cls) 9404 { 9405 __be16 protocol = cls->common.protocol; 9406 u32 loc = cls->knode.handle & 0xfffff; 9407 struct ixgbe_hw *hw = &adapter->hw; 9408 struct ixgbe_mat_field *field_ptr; 9409 struct ixgbe_fdir_filter *input = NULL; 9410 union ixgbe_atr_input *mask = NULL; 9411 struct ixgbe_jump_table *jump = NULL; 9412 int i, err = -EINVAL; 9413 u8 queue; 9414 u32 uhtid, link_uhtid; 9415 9416 uhtid = TC_U32_USERHTID(cls->knode.handle); 9417 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9418 9419 /* At the moment cls_u32 jumps to network layer and skips past 9420 * L2 headers. The canonical method to match L2 frames is to use 9421 * negative values. However this is error prone at best but really 9422 * just broken because there is no way to "know" what sort of hdr 9423 * is in front of the network layer. Fix cls_u32 to support L2 9424 * headers when needed. 9425 */ 9426 if (protocol != htons(ETH_P_IP)) 9427 return err; 9428 9429 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9430 e_err(drv, "Location out of range\n"); 9431 return err; 9432 } 9433 9434 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9435 * links and also the fields used to advance the parser across each 9436 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9437 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9438 * To add support for new nodes update ixgbe_model.h parse structures 9439 * this function _should_ be generic try not to hardcode values here. 9440 */ 9441 if (uhtid == 0x800) { 9442 field_ptr = (adapter->jump_tables[0])->mat; 9443 } else { 9444 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9445 return err; 9446 if (!adapter->jump_tables[uhtid]) 9447 return err; 9448 field_ptr = (adapter->jump_tables[uhtid])->mat; 9449 } 9450 9451 if (!field_ptr) 9452 return err; 9453 9454 /* At this point we know the field_ptr is valid and need to either 9455 * build cls_u32 link or attach filter. Because adding a link to 9456 * a handle that does not exist is invalid and the same for adding 9457 * rules to handles that don't exist. 9458 */ 9459 9460 if (link_uhtid) { 9461 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9462 9463 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9464 return err; 9465 9466 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9467 return err; 9468 9469 /* Multiple filters as links to the same hash table are not 9470 * supported. To add a new filter with the same next header 9471 * but different match/jump conditions, create a new hash table 9472 * and link to it. 9473 */ 9474 if (adapter->jump_tables[link_uhtid] && 9475 (adapter->jump_tables[link_uhtid])->link_hdl) { 9476 e_err(drv, "Link filter exists for link: %x\n", 9477 link_uhtid); 9478 return err; 9479 } 9480 9481 for (i = 0; nexthdr[i].jump; i++) { 9482 if (nexthdr[i].o != cls->knode.sel->offoff || 9483 nexthdr[i].s != cls->knode.sel->offshift || 9484 nexthdr[i].m != 9485 (__force u32)cls->knode.sel->offmask) 9486 return err; 9487 9488 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9489 if (!jump) 9490 return -ENOMEM; 9491 input = kzalloc(sizeof(*input), GFP_KERNEL); 9492 if (!input) { 9493 err = -ENOMEM; 9494 goto free_jump; 9495 } 9496 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9497 if (!mask) { 9498 err = -ENOMEM; 9499 goto free_input; 9500 } 9501 jump->input = input; 9502 jump->mask = mask; 9503 jump->link_hdl = cls->knode.handle; 9504 9505 err = ixgbe_clsu32_build_input(input, mask, cls, 9506 field_ptr, &nexthdr[i]); 9507 if (!err) { 9508 jump->mat = nexthdr[i].jump; 9509 adapter->jump_tables[link_uhtid] = jump; 9510 break; 9511 } else { 9512 kfree(mask); 9513 kfree(input); 9514 kfree(jump); 9515 } 9516 } 9517 return 0; 9518 } 9519 9520 input = kzalloc(sizeof(*input), GFP_KERNEL); 9521 if (!input) 9522 return -ENOMEM; 9523 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9524 if (!mask) { 9525 err = -ENOMEM; 9526 goto free_input; 9527 } 9528 9529 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9530 if ((adapter->jump_tables[uhtid])->input) 9531 memcpy(input, (adapter->jump_tables[uhtid])->input, 9532 sizeof(*input)); 9533 if ((adapter->jump_tables[uhtid])->mask) 9534 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9535 sizeof(*mask)); 9536 9537 /* Lookup in all child hash tables if this location is already 9538 * filled with a filter 9539 */ 9540 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9541 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9542 9543 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9544 e_err(drv, "Filter exists in location: %x\n", 9545 loc); 9546 err = -EINVAL; 9547 goto err_out; 9548 } 9549 } 9550 } 9551 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9552 if (err) 9553 goto err_out; 9554 9555 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9556 &queue); 9557 if (err < 0) 9558 goto err_out; 9559 9560 input->sw_idx = loc; 9561 9562 spin_lock(&adapter->fdir_perfect_lock); 9563 9564 if (hlist_empty(&adapter->fdir_filter_list)) { 9565 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9566 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9567 if (err) 9568 goto err_out_w_lock; 9569 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9570 err = -EINVAL; 9571 goto err_out_w_lock; 9572 } 9573 9574 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9575 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9576 input->sw_idx, queue); 9577 if (!err) 9578 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9579 spin_unlock(&adapter->fdir_perfect_lock); 9580 9581 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9582 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9583 9584 kfree(mask); 9585 return err; 9586 err_out_w_lock: 9587 spin_unlock(&adapter->fdir_perfect_lock); 9588 err_out: 9589 kfree(mask); 9590 free_input: 9591 kfree(input); 9592 free_jump: 9593 kfree(jump); 9594 return err; 9595 } 9596 9597 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9598 struct tc_cls_u32_offload *cls_u32) 9599 { 9600 switch (cls_u32->command) { 9601 case TC_CLSU32_NEW_KNODE: 9602 case TC_CLSU32_REPLACE_KNODE: 9603 return ixgbe_configure_clsu32(adapter, cls_u32); 9604 case TC_CLSU32_DELETE_KNODE: 9605 return ixgbe_delete_clsu32(adapter, cls_u32); 9606 case TC_CLSU32_NEW_HNODE: 9607 case TC_CLSU32_REPLACE_HNODE: 9608 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9609 case TC_CLSU32_DELETE_HNODE: 9610 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9611 default: 9612 return -EOPNOTSUPP; 9613 } 9614 } 9615 9616 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9617 void *cb_priv) 9618 { 9619 struct ixgbe_adapter *adapter = cb_priv; 9620 9621 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9622 return -EOPNOTSUPP; 9623 9624 switch (type) { 9625 case TC_SETUP_CLSU32: 9626 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9627 default: 9628 return -EOPNOTSUPP; 9629 } 9630 } 9631 9632 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9633 struct tc_mqprio_qopt *mqprio) 9634 { 9635 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9636 return ixgbe_setup_tc(dev, mqprio->num_tc); 9637 } 9638 9639 static LIST_HEAD(ixgbe_block_cb_list); 9640 9641 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9642 void *type_data) 9643 { 9644 struct ixgbe_adapter *adapter = netdev_priv(dev); 9645 9646 switch (type) { 9647 case TC_SETUP_BLOCK: 9648 return flow_block_cb_setup_simple(type_data, 9649 &ixgbe_block_cb_list, 9650 ixgbe_setup_tc_block_cb, 9651 adapter, adapter, true); 9652 case TC_SETUP_QDISC_MQPRIO: 9653 return ixgbe_setup_tc_mqprio(dev, type_data); 9654 default: 9655 return -EOPNOTSUPP; 9656 } 9657 } 9658 9659 #ifdef CONFIG_PCI_IOV 9660 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9661 { 9662 struct net_device *netdev = adapter->netdev; 9663 9664 rtnl_lock(); 9665 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9666 rtnl_unlock(); 9667 } 9668 9669 #endif 9670 void ixgbe_do_reset(struct net_device *netdev) 9671 { 9672 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9673 9674 if (netif_running(netdev)) 9675 ixgbe_reinit_locked(adapter); 9676 else 9677 ixgbe_reset(adapter); 9678 } 9679 9680 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9681 netdev_features_t features) 9682 { 9683 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9684 9685 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9686 if (!(features & NETIF_F_RXCSUM)) 9687 features &= ~NETIF_F_LRO; 9688 9689 /* Turn off LRO if not RSC capable */ 9690 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9691 features &= ~NETIF_F_LRO; 9692 9693 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9694 e_dev_err("LRO is not supported with XDP\n"); 9695 features &= ~NETIF_F_LRO; 9696 } 9697 9698 return features; 9699 } 9700 9701 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9702 { 9703 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9704 num_online_cpus()); 9705 9706 /* go back to full RSS if we're not running SR-IOV */ 9707 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9708 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9709 IXGBE_FLAG_SRIOV_ENABLED); 9710 9711 adapter->ring_feature[RING_F_RSS].limit = rss; 9712 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9713 9714 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9715 } 9716 9717 static int ixgbe_set_features(struct net_device *netdev, 9718 netdev_features_t features) 9719 { 9720 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9721 netdev_features_t changed = netdev->features ^ features; 9722 bool need_reset = false; 9723 9724 /* Make sure RSC matches LRO, reset if change */ 9725 if (!(features & NETIF_F_LRO)) { 9726 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9727 need_reset = true; 9728 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9729 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9730 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9731 if (adapter->rx_itr_setting == 1 || 9732 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9733 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9734 need_reset = true; 9735 } else if ((changed ^ features) & NETIF_F_LRO) { 9736 e_info(probe, "rx-usecs set too low, " 9737 "disabling RSC\n"); 9738 } 9739 } 9740 9741 /* 9742 * Check if Flow Director n-tuple support or hw_tc support was 9743 * enabled or disabled. If the state changed, we need to reset. 9744 */ 9745 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9746 /* turn off ATR, enable perfect filters and reset */ 9747 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9748 need_reset = true; 9749 9750 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9751 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9752 } else { 9753 /* turn off perfect filters, enable ATR and reset */ 9754 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9755 need_reset = true; 9756 9757 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9758 9759 /* We cannot enable ATR if SR-IOV is enabled */ 9760 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9761 /* We cannot enable ATR if we have 2 or more tcs */ 9762 (adapter->hw_tcs > 1) || 9763 /* We cannot enable ATR if RSS is disabled */ 9764 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9765 /* A sample rate of 0 indicates ATR disabled */ 9766 (!adapter->atr_sample_rate)) 9767 ; /* do nothing not supported */ 9768 else /* otherwise supported and set the flag */ 9769 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9770 } 9771 9772 if (changed & NETIF_F_RXALL) 9773 need_reset = true; 9774 9775 netdev->features = features; 9776 9777 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9778 if (features & NETIF_F_RXCSUM) { 9779 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9780 } else { 9781 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9782 9783 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9784 } 9785 } 9786 9787 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9788 if (features & NETIF_F_RXCSUM) { 9789 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9790 } else { 9791 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9792 9793 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9794 } 9795 } 9796 9797 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9798 ixgbe_reset_l2fw_offload(adapter); 9799 else if (need_reset) 9800 ixgbe_do_reset(netdev); 9801 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9802 NETIF_F_HW_VLAN_CTAG_FILTER)) 9803 ixgbe_set_rx_mode(netdev); 9804 9805 return 1; 9806 } 9807 9808 /** 9809 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9810 * @dev: The port's netdev 9811 * @ti: Tunnel endpoint information 9812 **/ 9813 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9814 struct udp_tunnel_info *ti) 9815 { 9816 struct ixgbe_adapter *adapter = netdev_priv(dev); 9817 struct ixgbe_hw *hw = &adapter->hw; 9818 __be16 port = ti->port; 9819 u32 port_shift = 0; 9820 u32 reg; 9821 9822 if (ti->sa_family != AF_INET) 9823 return; 9824 9825 switch (ti->type) { 9826 case UDP_TUNNEL_TYPE_VXLAN: 9827 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9828 return; 9829 9830 if (adapter->vxlan_port == port) 9831 return; 9832 9833 if (adapter->vxlan_port) { 9834 netdev_info(dev, 9835 "VXLAN port %d set, not adding port %d\n", 9836 ntohs(adapter->vxlan_port), 9837 ntohs(port)); 9838 return; 9839 } 9840 9841 adapter->vxlan_port = port; 9842 break; 9843 case UDP_TUNNEL_TYPE_GENEVE: 9844 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9845 return; 9846 9847 if (adapter->geneve_port == port) 9848 return; 9849 9850 if (adapter->geneve_port) { 9851 netdev_info(dev, 9852 "GENEVE port %d set, not adding port %d\n", 9853 ntohs(adapter->geneve_port), 9854 ntohs(port)); 9855 return; 9856 } 9857 9858 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9859 adapter->geneve_port = port; 9860 break; 9861 default: 9862 return; 9863 } 9864 9865 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9866 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9867 } 9868 9869 /** 9870 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9871 * @dev: The port's netdev 9872 * @ti: Tunnel endpoint information 9873 **/ 9874 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9875 struct udp_tunnel_info *ti) 9876 { 9877 struct ixgbe_adapter *adapter = netdev_priv(dev); 9878 u32 port_mask; 9879 9880 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9881 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9882 return; 9883 9884 if (ti->sa_family != AF_INET) 9885 return; 9886 9887 switch (ti->type) { 9888 case UDP_TUNNEL_TYPE_VXLAN: 9889 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9890 return; 9891 9892 if (adapter->vxlan_port != ti->port) { 9893 netdev_info(dev, "VXLAN port %d not found\n", 9894 ntohs(ti->port)); 9895 return; 9896 } 9897 9898 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9899 break; 9900 case UDP_TUNNEL_TYPE_GENEVE: 9901 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9902 return; 9903 9904 if (adapter->geneve_port != ti->port) { 9905 netdev_info(dev, "GENEVE port %d not found\n", 9906 ntohs(ti->port)); 9907 return; 9908 } 9909 9910 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9911 break; 9912 default: 9913 return; 9914 } 9915 9916 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9917 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9918 } 9919 9920 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9921 struct net_device *dev, 9922 const unsigned char *addr, u16 vid, 9923 u16 flags, 9924 struct netlink_ext_ack *extack) 9925 { 9926 /* guarantee we can provide a unique filter for the unicast address */ 9927 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9928 struct ixgbe_adapter *adapter = netdev_priv(dev); 9929 u16 pool = VMDQ_P(0); 9930 9931 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9932 return -ENOMEM; 9933 } 9934 9935 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9936 } 9937 9938 /** 9939 * ixgbe_configure_bridge_mode - set various bridge modes 9940 * @adapter: the private structure 9941 * @mode: requested bridge mode 9942 * 9943 * Configure some settings require for various bridge modes. 9944 **/ 9945 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9946 __u16 mode) 9947 { 9948 struct ixgbe_hw *hw = &adapter->hw; 9949 unsigned int p, num_pools; 9950 u32 vmdctl; 9951 9952 switch (mode) { 9953 case BRIDGE_MODE_VEPA: 9954 /* disable Tx loopback, rely on switch hairpin mode */ 9955 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9956 9957 /* must enable Rx switching replication to allow multicast 9958 * packet reception on all VFs, and to enable source address 9959 * pruning. 9960 */ 9961 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9962 vmdctl |= IXGBE_VT_CTL_REPLEN; 9963 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9964 9965 /* enable Rx source address pruning. Note, this requires 9966 * replication to be enabled or else it does nothing. 9967 */ 9968 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9969 for (p = 0; p < num_pools; p++) { 9970 if (hw->mac.ops.set_source_address_pruning) 9971 hw->mac.ops.set_source_address_pruning(hw, 9972 true, 9973 p); 9974 } 9975 break; 9976 case BRIDGE_MODE_VEB: 9977 /* enable Tx loopback for internal VF/PF communication */ 9978 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9979 IXGBE_PFDTXGSWC_VT_LBEN); 9980 9981 /* disable Rx switching replication unless we have SR-IOV 9982 * virtual functions 9983 */ 9984 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9985 if (!adapter->num_vfs) 9986 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9987 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9988 9989 /* disable Rx source address pruning, since we don't expect to 9990 * be receiving external loopback of our transmitted frames. 9991 */ 9992 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9993 for (p = 0; p < num_pools; p++) { 9994 if (hw->mac.ops.set_source_address_pruning) 9995 hw->mac.ops.set_source_address_pruning(hw, 9996 false, 9997 p); 9998 } 9999 break; 10000 default: 10001 return -EINVAL; 10002 } 10003 10004 adapter->bridge_mode = mode; 10005 10006 e_info(drv, "enabling bridge mode: %s\n", 10007 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10008 10009 return 0; 10010 } 10011 10012 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10013 struct nlmsghdr *nlh, u16 flags, 10014 struct netlink_ext_ack *extack) 10015 { 10016 struct ixgbe_adapter *adapter = netdev_priv(dev); 10017 struct nlattr *attr, *br_spec; 10018 int rem; 10019 10020 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10021 return -EOPNOTSUPP; 10022 10023 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10024 if (!br_spec) 10025 return -EINVAL; 10026 10027 nla_for_each_nested(attr, br_spec, rem) { 10028 int status; 10029 __u16 mode; 10030 10031 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10032 continue; 10033 10034 if (nla_len(attr) < sizeof(mode)) 10035 return -EINVAL; 10036 10037 mode = nla_get_u16(attr); 10038 status = ixgbe_configure_bridge_mode(adapter, mode); 10039 if (status) 10040 return status; 10041 10042 break; 10043 } 10044 10045 return 0; 10046 } 10047 10048 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10049 struct net_device *dev, 10050 u32 filter_mask, int nlflags) 10051 { 10052 struct ixgbe_adapter *adapter = netdev_priv(dev); 10053 10054 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10055 return 0; 10056 10057 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10058 adapter->bridge_mode, 0, 0, nlflags, 10059 filter_mask, NULL); 10060 } 10061 10062 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10063 { 10064 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10065 struct ixgbe_fwd_adapter *accel; 10066 int tcs = adapter->hw_tcs ? : 1; 10067 int pool, err; 10068 10069 if (adapter->xdp_prog) { 10070 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10071 return ERR_PTR(-EINVAL); 10072 } 10073 10074 /* The hardware supported by ixgbe only filters on the destination MAC 10075 * address. In order to avoid issues we only support offloading modes 10076 * where the hardware can actually provide the functionality. 10077 */ 10078 if (!macvlan_supports_dest_filter(vdev)) 10079 return ERR_PTR(-EMEDIUMTYPE); 10080 10081 /* We need to lock down the macvlan to be a single queue device so that 10082 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10083 * the queue mapping to our netdev. 10084 */ 10085 if (netif_is_multiqueue(vdev)) 10086 return ERR_PTR(-ERANGE); 10087 10088 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10089 if (pool == adapter->num_rx_pools) { 10090 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10091 u16 reserved_pools; 10092 10093 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10094 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10095 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10096 return ERR_PTR(-EBUSY); 10097 10098 /* Hardware has a limited number of available pools. Each VF, 10099 * and the PF require a pool. Check to ensure we don't 10100 * attempt to use more then the available number of pools. 10101 */ 10102 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10103 return ERR_PTR(-EBUSY); 10104 10105 /* Enable VMDq flag so device will be set in VM mode */ 10106 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10107 IXGBE_FLAG_SRIOV_ENABLED; 10108 10109 /* Try to reserve as many queues per pool as possible, 10110 * we start with the configurations that support 4 queues 10111 * per pools, followed by 2, and then by just 1 per pool. 10112 */ 10113 if (used_pools < 32 && adapter->num_rx_pools < 16) 10114 reserved_pools = min_t(u16, 10115 32 - used_pools, 10116 16 - adapter->num_rx_pools); 10117 else if (adapter->num_rx_pools < 32) 10118 reserved_pools = min_t(u16, 10119 64 - used_pools, 10120 32 - adapter->num_rx_pools); 10121 else 10122 reserved_pools = 64 - used_pools; 10123 10124 10125 if (!reserved_pools) 10126 return ERR_PTR(-EBUSY); 10127 10128 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10129 10130 /* Force reinit of ring allocation with VMDQ enabled */ 10131 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10132 if (err) 10133 return ERR_PTR(err); 10134 10135 if (pool >= adapter->num_rx_pools) 10136 return ERR_PTR(-ENOMEM); 10137 } 10138 10139 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10140 if (!accel) 10141 return ERR_PTR(-ENOMEM); 10142 10143 set_bit(pool, adapter->fwd_bitmask); 10144 netdev_set_sb_channel(vdev, pool); 10145 accel->pool = pool; 10146 accel->netdev = vdev; 10147 10148 if (!netif_running(pdev)) 10149 return accel; 10150 10151 err = ixgbe_fwd_ring_up(adapter, accel); 10152 if (err) 10153 return ERR_PTR(err); 10154 10155 return accel; 10156 } 10157 10158 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10159 { 10160 struct ixgbe_fwd_adapter *accel = priv; 10161 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10162 unsigned int rxbase = accel->rx_base_queue; 10163 unsigned int i; 10164 10165 /* delete unicast filter associated with offloaded interface */ 10166 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10167 VMDQ_P(accel->pool)); 10168 10169 /* Allow remaining Rx packets to get flushed out of the 10170 * Rx FIFO before we drop the netdev for the ring. 10171 */ 10172 usleep_range(10000, 20000); 10173 10174 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10175 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10176 struct ixgbe_q_vector *qv = ring->q_vector; 10177 10178 /* Make sure we aren't processing any packets and clear 10179 * netdev to shut down the ring. 10180 */ 10181 if (netif_running(adapter->netdev)) 10182 napi_synchronize(&qv->napi); 10183 ring->netdev = NULL; 10184 } 10185 10186 /* unbind the queues and drop the subordinate channel config */ 10187 netdev_unbind_sb_channel(pdev, accel->netdev); 10188 netdev_set_sb_channel(accel->netdev, 0); 10189 10190 clear_bit(accel->pool, adapter->fwd_bitmask); 10191 kfree(accel); 10192 } 10193 10194 #define IXGBE_MAX_MAC_HDR_LEN 127 10195 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10196 10197 static netdev_features_t 10198 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10199 netdev_features_t features) 10200 { 10201 unsigned int network_hdr_len, mac_hdr_len; 10202 10203 /* Make certain the headers can be described by a context descriptor */ 10204 mac_hdr_len = skb_network_header(skb) - skb->data; 10205 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10206 return features & ~(NETIF_F_HW_CSUM | 10207 NETIF_F_SCTP_CRC | 10208 NETIF_F_GSO_UDP_L4 | 10209 NETIF_F_HW_VLAN_CTAG_TX | 10210 NETIF_F_TSO | 10211 NETIF_F_TSO6); 10212 10213 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10214 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10215 return features & ~(NETIF_F_HW_CSUM | 10216 NETIF_F_SCTP_CRC | 10217 NETIF_F_GSO_UDP_L4 | 10218 NETIF_F_TSO | 10219 NETIF_F_TSO6); 10220 10221 /* We can only support IPV4 TSO in tunnels if we can mangle the 10222 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10223 * IPsec offoad sets skb->encapsulation but still can handle 10224 * the TSO, so it's the exception. 10225 */ 10226 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10227 #ifdef CONFIG_IXGBE_IPSEC 10228 if (!secpath_exists(skb)) 10229 #endif 10230 features &= ~NETIF_F_TSO; 10231 } 10232 10233 return features; 10234 } 10235 10236 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10237 { 10238 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10239 struct ixgbe_adapter *adapter = netdev_priv(dev); 10240 struct bpf_prog *old_prog; 10241 bool need_reset; 10242 10243 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10244 return -EINVAL; 10245 10246 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10247 return -EINVAL; 10248 10249 /* verify ixgbe ring attributes are sufficient for XDP */ 10250 for (i = 0; i < adapter->num_rx_queues; i++) { 10251 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10252 10253 if (ring_is_rsc_enabled(ring)) 10254 return -EINVAL; 10255 10256 if (frame_size > ixgbe_rx_bufsz(ring)) 10257 return -EINVAL; 10258 } 10259 10260 if (nr_cpu_ids > MAX_XDP_QUEUES) 10261 return -ENOMEM; 10262 10263 old_prog = xchg(&adapter->xdp_prog, prog); 10264 need_reset = (!!prog != !!old_prog); 10265 10266 /* If transitioning XDP modes reconfigure rings */ 10267 if (need_reset) { 10268 int err; 10269 10270 if (!prog) 10271 /* Wait until ndo_xsk_wakeup completes. */ 10272 synchronize_rcu(); 10273 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10274 10275 if (err) { 10276 rcu_assign_pointer(adapter->xdp_prog, old_prog); 10277 return -EINVAL; 10278 } 10279 } else { 10280 for (i = 0; i < adapter->num_rx_queues; i++) 10281 (void)xchg(&adapter->rx_ring[i]->xdp_prog, 10282 adapter->xdp_prog); 10283 } 10284 10285 if (old_prog) 10286 bpf_prog_put(old_prog); 10287 10288 /* Kick start the NAPI context if there is an AF_XDP socket open 10289 * on that queue id. This so that receiving will start. 10290 */ 10291 if (need_reset && prog) 10292 for (i = 0; i < adapter->num_rx_queues; i++) 10293 if (adapter->xdp_ring[i]->xsk_umem) 10294 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10295 XDP_WAKEUP_RX); 10296 10297 return 0; 10298 } 10299 10300 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10301 { 10302 struct ixgbe_adapter *adapter = netdev_priv(dev); 10303 10304 switch (xdp->command) { 10305 case XDP_SETUP_PROG: 10306 return ixgbe_xdp_setup(dev, xdp->prog); 10307 case XDP_QUERY_PROG: 10308 xdp->prog_id = adapter->xdp_prog ? 10309 adapter->xdp_prog->aux->id : 0; 10310 return 0; 10311 case XDP_SETUP_XSK_UMEM: 10312 return ixgbe_xsk_umem_setup(adapter, xdp->xsk.umem, 10313 xdp->xsk.queue_id); 10314 10315 default: 10316 return -EINVAL; 10317 } 10318 } 10319 10320 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10321 { 10322 /* Force memory writes to complete before letting h/w know there 10323 * are new descriptors to fetch. 10324 */ 10325 wmb(); 10326 writel(ring->next_to_use, ring->tail); 10327 } 10328 10329 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10330 struct xdp_frame **frames, u32 flags) 10331 { 10332 struct ixgbe_adapter *adapter = netdev_priv(dev); 10333 struct ixgbe_ring *ring; 10334 int drops = 0; 10335 int i; 10336 10337 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10338 return -ENETDOWN; 10339 10340 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10341 return -EINVAL; 10342 10343 /* During program transitions its possible adapter->xdp_prog is assigned 10344 * but ring has not been configured yet. In this case simply abort xmit. 10345 */ 10346 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10347 if (unlikely(!ring)) 10348 return -ENXIO; 10349 10350 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10351 return -ENXIO; 10352 10353 for (i = 0; i < n; i++) { 10354 struct xdp_frame *xdpf = frames[i]; 10355 int err; 10356 10357 err = ixgbe_xmit_xdp_ring(adapter, xdpf); 10358 if (err != IXGBE_XDP_TX) { 10359 xdp_return_frame_rx_napi(xdpf); 10360 drops++; 10361 } 10362 } 10363 10364 if (unlikely(flags & XDP_XMIT_FLUSH)) 10365 ixgbe_xdp_ring_update_tail(ring); 10366 10367 return n - drops; 10368 } 10369 10370 static const struct net_device_ops ixgbe_netdev_ops = { 10371 .ndo_open = ixgbe_open, 10372 .ndo_stop = ixgbe_close, 10373 .ndo_start_xmit = ixgbe_xmit_frame, 10374 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10375 .ndo_validate_addr = eth_validate_addr, 10376 .ndo_set_mac_address = ixgbe_set_mac, 10377 .ndo_change_mtu = ixgbe_change_mtu, 10378 .ndo_tx_timeout = ixgbe_tx_timeout, 10379 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10380 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10381 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10382 .ndo_do_ioctl = ixgbe_ioctl, 10383 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10384 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10385 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10386 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10387 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10388 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10389 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10390 .ndo_get_stats64 = ixgbe_get_stats64, 10391 .ndo_setup_tc = __ixgbe_setup_tc, 10392 #ifdef IXGBE_FCOE 10393 .ndo_select_queue = ixgbe_select_queue, 10394 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10395 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10396 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10397 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10398 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10399 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10400 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10401 #endif /* IXGBE_FCOE */ 10402 .ndo_set_features = ixgbe_set_features, 10403 .ndo_fix_features = ixgbe_fix_features, 10404 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10405 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10406 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10407 .ndo_dfwd_add_station = ixgbe_fwd_add, 10408 .ndo_dfwd_del_station = ixgbe_fwd_del, 10409 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10410 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10411 .ndo_features_check = ixgbe_features_check, 10412 .ndo_bpf = ixgbe_xdp, 10413 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10414 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10415 }; 10416 10417 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10418 struct ixgbe_ring *tx_ring) 10419 { 10420 unsigned long wait_delay, delay_interval; 10421 struct ixgbe_hw *hw = &adapter->hw; 10422 u8 reg_idx = tx_ring->reg_idx; 10423 int wait_loop; 10424 u32 txdctl; 10425 10426 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10427 10428 /* delay mechanism from ixgbe_disable_tx */ 10429 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10430 10431 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10432 wait_delay = delay_interval; 10433 10434 while (wait_loop--) { 10435 usleep_range(wait_delay, wait_delay + 10); 10436 wait_delay += delay_interval * 2; 10437 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10438 10439 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10440 return; 10441 } 10442 10443 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10444 } 10445 10446 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10447 struct ixgbe_ring *tx_ring) 10448 { 10449 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10450 ixgbe_disable_txr_hw(adapter, tx_ring); 10451 } 10452 10453 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10454 struct ixgbe_ring *rx_ring) 10455 { 10456 unsigned long wait_delay, delay_interval; 10457 struct ixgbe_hw *hw = &adapter->hw; 10458 u8 reg_idx = rx_ring->reg_idx; 10459 int wait_loop; 10460 u32 rxdctl; 10461 10462 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10463 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10464 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10465 10466 /* write value back with RXDCTL.ENABLE bit cleared */ 10467 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10468 10469 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10470 if (hw->mac.type == ixgbe_mac_82598EB && 10471 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10472 return; 10473 10474 /* delay mechanism from ixgbe_disable_rx */ 10475 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10476 10477 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10478 wait_delay = delay_interval; 10479 10480 while (wait_loop--) { 10481 usleep_range(wait_delay, wait_delay + 10); 10482 wait_delay += delay_interval * 2; 10483 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10484 10485 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10486 return; 10487 } 10488 10489 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10490 } 10491 10492 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10493 { 10494 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10495 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10496 } 10497 10498 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10499 { 10500 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10501 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10502 } 10503 10504 /** 10505 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10506 * @adapter: adapter structure 10507 * @ring: ring index 10508 * 10509 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10510 * assumes that the netdev is running. 10511 **/ 10512 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10513 { 10514 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10515 10516 rx_ring = adapter->rx_ring[ring]; 10517 tx_ring = adapter->tx_ring[ring]; 10518 xdp_ring = adapter->xdp_ring[ring]; 10519 10520 ixgbe_disable_txr(adapter, tx_ring); 10521 if (xdp_ring) 10522 ixgbe_disable_txr(adapter, xdp_ring); 10523 ixgbe_disable_rxr_hw(adapter, rx_ring); 10524 10525 if (xdp_ring) 10526 synchronize_rcu(); 10527 10528 /* Rx/Tx/XDP Tx share the same napi context. */ 10529 napi_disable(&rx_ring->q_vector->napi); 10530 10531 ixgbe_clean_tx_ring(tx_ring); 10532 if (xdp_ring) 10533 ixgbe_clean_tx_ring(xdp_ring); 10534 ixgbe_clean_rx_ring(rx_ring); 10535 10536 ixgbe_reset_txr_stats(tx_ring); 10537 if (xdp_ring) 10538 ixgbe_reset_txr_stats(xdp_ring); 10539 ixgbe_reset_rxr_stats(rx_ring); 10540 } 10541 10542 /** 10543 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10544 * @adapter: adapter structure 10545 * @ring: ring index 10546 * 10547 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10548 * assumes that the netdev is running. 10549 **/ 10550 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10551 { 10552 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10553 10554 rx_ring = adapter->rx_ring[ring]; 10555 tx_ring = adapter->tx_ring[ring]; 10556 xdp_ring = adapter->xdp_ring[ring]; 10557 10558 /* Rx/Tx/XDP Tx share the same napi context. */ 10559 napi_enable(&rx_ring->q_vector->napi); 10560 10561 ixgbe_configure_tx_ring(adapter, tx_ring); 10562 if (xdp_ring) 10563 ixgbe_configure_tx_ring(adapter, xdp_ring); 10564 ixgbe_configure_rx_ring(adapter, rx_ring); 10565 10566 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10567 if (xdp_ring) 10568 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10569 } 10570 10571 /** 10572 * ixgbe_enumerate_functions - Get the number of ports this device has 10573 * @adapter: adapter structure 10574 * 10575 * This function enumerates the phsyical functions co-located on a single slot, 10576 * in order to determine how many ports a device has. This is most useful in 10577 * determining the required GT/s of PCIe bandwidth necessary for optimal 10578 * performance. 10579 **/ 10580 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10581 { 10582 struct pci_dev *entry, *pdev = adapter->pdev; 10583 int physfns = 0; 10584 10585 /* Some cards can not use the generic count PCIe functions method, 10586 * because they are behind a parent switch, so we hardcode these with 10587 * the correct number of functions. 10588 */ 10589 if (ixgbe_pcie_from_parent(&adapter->hw)) 10590 physfns = 4; 10591 10592 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10593 /* don't count virtual functions */ 10594 if (entry->is_virtfn) 10595 continue; 10596 10597 /* When the devices on the bus don't all match our device ID, 10598 * we can't reliably determine the correct number of 10599 * functions. This can occur if a function has been direct 10600 * attached to a virtual machine using VT-d, for example. In 10601 * this case, simply return -1 to indicate this. 10602 */ 10603 if ((entry->vendor != pdev->vendor) || 10604 (entry->device != pdev->device)) 10605 return -1; 10606 10607 physfns++; 10608 } 10609 10610 return physfns; 10611 } 10612 10613 /** 10614 * ixgbe_wol_supported - Check whether device supports WoL 10615 * @adapter: the adapter private structure 10616 * @device_id: the device ID 10617 * @subdevice_id: the subsystem device ID 10618 * 10619 * This function is used by probe and ethtool to determine 10620 * which devices have WoL support 10621 * 10622 **/ 10623 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10624 u16 subdevice_id) 10625 { 10626 struct ixgbe_hw *hw = &adapter->hw; 10627 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10628 10629 /* WOL not supported on 82598 */ 10630 if (hw->mac.type == ixgbe_mac_82598EB) 10631 return false; 10632 10633 /* check eeprom to see if WOL is enabled for X540 and newer */ 10634 if (hw->mac.type >= ixgbe_mac_X540) { 10635 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10636 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10637 (hw->bus.func == 0))) 10638 return true; 10639 } 10640 10641 /* WOL is determined based on device IDs for 82599 MACs */ 10642 switch (device_id) { 10643 case IXGBE_DEV_ID_82599_SFP: 10644 /* Only these subdevices could supports WOL */ 10645 switch (subdevice_id) { 10646 case IXGBE_SUBDEV_ID_82599_560FLR: 10647 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10648 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10649 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10650 /* only support first port */ 10651 if (hw->bus.func != 0) 10652 break; 10653 /* fall through */ 10654 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10655 case IXGBE_SUBDEV_ID_82599_SFP: 10656 case IXGBE_SUBDEV_ID_82599_RNDC: 10657 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10658 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10659 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10660 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10661 return true; 10662 } 10663 break; 10664 case IXGBE_DEV_ID_82599EN_SFP: 10665 /* Only these subdevices support WOL */ 10666 switch (subdevice_id) { 10667 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10668 return true; 10669 } 10670 break; 10671 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10672 /* All except this subdevice support WOL */ 10673 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10674 return true; 10675 break; 10676 case IXGBE_DEV_ID_82599_KX4: 10677 return true; 10678 default: 10679 break; 10680 } 10681 10682 return false; 10683 } 10684 10685 /** 10686 * ixgbe_set_fw_version - Set FW version 10687 * @adapter: the adapter private structure 10688 * 10689 * This function is used by probe and ethtool to determine the FW version to 10690 * format to display. The FW version is taken from the EEPROM/NVM. 10691 */ 10692 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10693 { 10694 struct ixgbe_hw *hw = &adapter->hw; 10695 struct ixgbe_nvm_version nvm_ver; 10696 10697 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10698 if (nvm_ver.oem_valid) { 10699 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10700 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10701 nvm_ver.oem_release); 10702 return; 10703 } 10704 10705 ixgbe_get_etk_id(hw, &nvm_ver); 10706 ixgbe_get_orom_version(hw, &nvm_ver); 10707 10708 if (nvm_ver.or_valid) { 10709 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10710 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10711 nvm_ver.or_build, nvm_ver.or_patch); 10712 return; 10713 } 10714 10715 /* Set ETrack ID format */ 10716 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10717 "0x%08x", nvm_ver.etk_id); 10718 } 10719 10720 /** 10721 * ixgbe_probe - Device Initialization Routine 10722 * @pdev: PCI device information struct 10723 * @ent: entry in ixgbe_pci_tbl 10724 * 10725 * Returns 0 on success, negative on failure 10726 * 10727 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10728 * The OS initialization, configuring of the adapter private structure, 10729 * and a hardware reset occur. 10730 **/ 10731 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10732 { 10733 struct net_device *netdev; 10734 struct ixgbe_adapter *adapter = NULL; 10735 struct ixgbe_hw *hw; 10736 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10737 int i, err, pci_using_dac, expected_gts; 10738 unsigned int indices = MAX_TX_QUEUES; 10739 u8 part_str[IXGBE_PBANUM_LENGTH]; 10740 bool disable_dev = false; 10741 #ifdef IXGBE_FCOE 10742 u16 device_caps; 10743 #endif 10744 u32 eec; 10745 10746 /* Catch broken hardware that put the wrong VF device ID in 10747 * the PCIe SR-IOV capability. 10748 */ 10749 if (pdev->is_virtfn) { 10750 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10751 pci_name(pdev), pdev->vendor, pdev->device); 10752 return -EINVAL; 10753 } 10754 10755 err = pci_enable_device_mem(pdev); 10756 if (err) 10757 return err; 10758 10759 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10760 pci_using_dac = 1; 10761 } else { 10762 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10763 if (err) { 10764 dev_err(&pdev->dev, 10765 "No usable DMA configuration, aborting\n"); 10766 goto err_dma; 10767 } 10768 pci_using_dac = 0; 10769 } 10770 10771 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10772 if (err) { 10773 dev_err(&pdev->dev, 10774 "pci_request_selected_regions failed 0x%x\n", err); 10775 goto err_pci_reg; 10776 } 10777 10778 pci_enable_pcie_error_reporting(pdev); 10779 10780 pci_set_master(pdev); 10781 pci_save_state(pdev); 10782 10783 if (ii->mac == ixgbe_mac_82598EB) { 10784 #ifdef CONFIG_IXGBE_DCB 10785 /* 8 TC w/ 4 queues per TC */ 10786 indices = 4 * MAX_TRAFFIC_CLASS; 10787 #else 10788 indices = IXGBE_MAX_RSS_INDICES; 10789 #endif 10790 } 10791 10792 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10793 if (!netdev) { 10794 err = -ENOMEM; 10795 goto err_alloc_etherdev; 10796 } 10797 10798 SET_NETDEV_DEV(netdev, &pdev->dev); 10799 10800 adapter = netdev_priv(netdev); 10801 10802 adapter->netdev = netdev; 10803 adapter->pdev = pdev; 10804 hw = &adapter->hw; 10805 hw->back = adapter; 10806 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10807 10808 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10809 pci_resource_len(pdev, 0)); 10810 adapter->io_addr = hw->hw_addr; 10811 if (!hw->hw_addr) { 10812 err = -EIO; 10813 goto err_ioremap; 10814 } 10815 10816 netdev->netdev_ops = &ixgbe_netdev_ops; 10817 ixgbe_set_ethtool_ops(netdev); 10818 netdev->watchdog_timeo = 5 * HZ; 10819 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10820 10821 /* Setup hw api */ 10822 hw->mac.ops = *ii->mac_ops; 10823 hw->mac.type = ii->mac; 10824 hw->mvals = ii->mvals; 10825 if (ii->link_ops) 10826 hw->link.ops = *ii->link_ops; 10827 10828 /* EEPROM */ 10829 hw->eeprom.ops = *ii->eeprom_ops; 10830 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10831 if (ixgbe_removed(hw->hw_addr)) { 10832 err = -EIO; 10833 goto err_ioremap; 10834 } 10835 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10836 if (!(eec & BIT(8))) 10837 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10838 10839 /* PHY */ 10840 hw->phy.ops = *ii->phy_ops; 10841 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10842 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10843 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10844 hw->phy.mdio.mmds = 0; 10845 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10846 hw->phy.mdio.dev = netdev; 10847 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10848 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10849 10850 /* setup the private structure */ 10851 err = ixgbe_sw_init(adapter, ii); 10852 if (err) 10853 goto err_sw_init; 10854 10855 /* Make sure the SWFW semaphore is in a valid state */ 10856 if (hw->mac.ops.init_swfw_sync) 10857 hw->mac.ops.init_swfw_sync(hw); 10858 10859 /* Make it possible the adapter to be woken up via WOL */ 10860 switch (adapter->hw.mac.type) { 10861 case ixgbe_mac_82599EB: 10862 case ixgbe_mac_X540: 10863 case ixgbe_mac_X550: 10864 case ixgbe_mac_X550EM_x: 10865 case ixgbe_mac_x550em_a: 10866 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10867 break; 10868 default: 10869 break; 10870 } 10871 10872 /* 10873 * If there is a fan on this device and it has failed log the 10874 * failure. 10875 */ 10876 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10877 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10878 if (esdp & IXGBE_ESDP_SDP1) 10879 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10880 } 10881 10882 if (allow_unsupported_sfp) 10883 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10884 10885 /* reset_hw fills in the perm_addr as well */ 10886 hw->phy.reset_if_overtemp = true; 10887 err = hw->mac.ops.reset_hw(hw); 10888 hw->phy.reset_if_overtemp = false; 10889 ixgbe_set_eee_capable(adapter); 10890 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10891 err = 0; 10892 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10893 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10894 e_dev_err("Reload the driver after installing a supported module.\n"); 10895 goto err_sw_init; 10896 } else if (err) { 10897 e_dev_err("HW Init failed: %d\n", err); 10898 goto err_sw_init; 10899 } 10900 10901 #ifdef CONFIG_PCI_IOV 10902 /* SR-IOV not supported on the 82598 */ 10903 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10904 goto skip_sriov; 10905 /* Mailbox */ 10906 ixgbe_init_mbx_params_pf(hw); 10907 hw->mbx.ops = ii->mbx_ops; 10908 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10909 ixgbe_enable_sriov(adapter, max_vfs); 10910 skip_sriov: 10911 10912 #endif 10913 netdev->features = NETIF_F_SG | 10914 NETIF_F_TSO | 10915 NETIF_F_TSO6 | 10916 NETIF_F_RXHASH | 10917 NETIF_F_RXCSUM | 10918 NETIF_F_HW_CSUM; 10919 10920 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10921 NETIF_F_GSO_GRE_CSUM | \ 10922 NETIF_F_GSO_IPXIP4 | \ 10923 NETIF_F_GSO_IPXIP6 | \ 10924 NETIF_F_GSO_UDP_TUNNEL | \ 10925 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10926 10927 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10928 netdev->features |= NETIF_F_GSO_PARTIAL | 10929 IXGBE_GSO_PARTIAL_FEATURES; 10930 10931 if (hw->mac.type >= ixgbe_mac_82599EB) 10932 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 10933 10934 #ifdef CONFIG_IXGBE_IPSEC 10935 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 10936 NETIF_F_HW_ESP_TX_CSUM | \ 10937 NETIF_F_GSO_ESP) 10938 10939 if (adapter->ipsec) 10940 netdev->features |= IXGBE_ESP_FEATURES; 10941 #endif 10942 /* copy netdev features into list of user selectable features */ 10943 netdev->hw_features |= netdev->features | 10944 NETIF_F_HW_VLAN_CTAG_FILTER | 10945 NETIF_F_HW_VLAN_CTAG_RX | 10946 NETIF_F_HW_VLAN_CTAG_TX | 10947 NETIF_F_RXALL | 10948 NETIF_F_HW_L2FW_DOFFLOAD; 10949 10950 if (hw->mac.type >= ixgbe_mac_82599EB) 10951 netdev->hw_features |= NETIF_F_NTUPLE | 10952 NETIF_F_HW_TC; 10953 10954 if (pci_using_dac) 10955 netdev->features |= NETIF_F_HIGHDMA; 10956 10957 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10958 netdev->hw_enc_features |= netdev->vlan_features; 10959 netdev->mpls_features |= NETIF_F_SG | 10960 NETIF_F_TSO | 10961 NETIF_F_TSO6 | 10962 NETIF_F_HW_CSUM; 10963 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10964 10965 /* set this bit last since it cannot be part of vlan_features */ 10966 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10967 NETIF_F_HW_VLAN_CTAG_RX | 10968 NETIF_F_HW_VLAN_CTAG_TX; 10969 10970 netdev->priv_flags |= IFF_UNICAST_FLT; 10971 netdev->priv_flags |= IFF_SUPP_NOFCS; 10972 10973 /* MTU range: 68 - 9710 */ 10974 netdev->min_mtu = ETH_MIN_MTU; 10975 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10976 10977 #ifdef CONFIG_IXGBE_DCB 10978 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10979 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10980 #endif 10981 10982 #ifdef IXGBE_FCOE 10983 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10984 unsigned int fcoe_l; 10985 10986 if (hw->mac.ops.get_device_caps) { 10987 hw->mac.ops.get_device_caps(hw, &device_caps); 10988 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10989 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10990 } 10991 10992 10993 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10994 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10995 10996 netdev->features |= NETIF_F_FSO | 10997 NETIF_F_FCOE_CRC; 10998 10999 netdev->vlan_features |= NETIF_F_FSO | 11000 NETIF_F_FCOE_CRC | 11001 NETIF_F_FCOE_MTU; 11002 } 11003 #endif /* IXGBE_FCOE */ 11004 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 11005 netdev->hw_features |= NETIF_F_LRO; 11006 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 11007 netdev->features |= NETIF_F_LRO; 11008 11009 if (ixgbe_check_fw_error(adapter)) { 11010 err = -EIO; 11011 goto err_sw_init; 11012 } 11013 11014 /* make sure the EEPROM is good */ 11015 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11016 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11017 err = -EIO; 11018 goto err_sw_init; 11019 } 11020 11021 eth_platform_get_mac_address(&adapter->pdev->dev, 11022 adapter->hw.mac.perm_addr); 11023 11024 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 11025 11026 if (!is_valid_ether_addr(netdev->dev_addr)) { 11027 e_dev_err("invalid MAC address\n"); 11028 err = -EIO; 11029 goto err_sw_init; 11030 } 11031 11032 /* Set hw->mac.addr to permanent MAC address */ 11033 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11034 ixgbe_mac_set_default_filter(adapter); 11035 11036 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11037 11038 if (ixgbe_removed(hw->hw_addr)) { 11039 err = -EIO; 11040 goto err_sw_init; 11041 } 11042 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11043 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11044 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11045 11046 err = ixgbe_init_interrupt_scheme(adapter); 11047 if (err) 11048 goto err_sw_init; 11049 11050 for (i = 0; i < adapter->num_rx_queues; i++) 11051 u64_stats_init(&adapter->rx_ring[i]->syncp); 11052 for (i = 0; i < adapter->num_tx_queues; i++) 11053 u64_stats_init(&adapter->tx_ring[i]->syncp); 11054 for (i = 0; i < adapter->num_xdp_queues; i++) 11055 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11056 11057 /* WOL not supported for all devices */ 11058 adapter->wol = 0; 11059 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11060 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11061 pdev->subsystem_device); 11062 if (hw->wol_enabled) 11063 adapter->wol = IXGBE_WUFC_MAG; 11064 11065 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11066 11067 /* save off EEPROM version number */ 11068 ixgbe_set_fw_version(adapter); 11069 11070 /* pick up the PCI bus settings for reporting later */ 11071 if (ixgbe_pcie_from_parent(hw)) 11072 ixgbe_get_parent_bus_info(adapter); 11073 else 11074 hw->mac.ops.get_bus_info(hw); 11075 11076 /* calculate the expected PCIe bandwidth required for optimal 11077 * performance. Note that some older parts will never have enough 11078 * bandwidth due to being older generation PCIe parts. We clamp these 11079 * parts to ensure no warning is displayed if it can't be fixed. 11080 */ 11081 switch (hw->mac.type) { 11082 case ixgbe_mac_82598EB: 11083 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11084 break; 11085 default: 11086 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11087 break; 11088 } 11089 11090 /* don't check link if we failed to enumerate functions */ 11091 if (expected_gts > 0) 11092 ixgbe_check_minimum_link(adapter, expected_gts); 11093 11094 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11095 if (err) 11096 strlcpy(part_str, "Unknown", sizeof(part_str)); 11097 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11098 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11099 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11100 part_str); 11101 else 11102 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11103 hw->mac.type, hw->phy.type, part_str); 11104 11105 e_dev_info("%pM\n", netdev->dev_addr); 11106 11107 /* reset the hardware with the new settings */ 11108 err = hw->mac.ops.start_hw(hw); 11109 if (err == IXGBE_ERR_EEPROM_VERSION) { 11110 /* We are running on a pre-production device, log a warning */ 11111 e_dev_warn("This device is a pre-production adapter/LOM. " 11112 "Please be aware there may be issues associated " 11113 "with your hardware. If you are experiencing " 11114 "problems please contact your Intel or hardware " 11115 "representative who provided you with this " 11116 "hardware.\n"); 11117 } 11118 strcpy(netdev->name, "eth%d"); 11119 pci_set_drvdata(pdev, adapter); 11120 err = register_netdev(netdev); 11121 if (err) 11122 goto err_register; 11123 11124 11125 /* power down the optics for 82599 SFP+ fiber */ 11126 if (hw->mac.ops.disable_tx_laser) 11127 hw->mac.ops.disable_tx_laser(hw); 11128 11129 /* carrier off reporting is important to ethtool even BEFORE open */ 11130 netif_carrier_off(netdev); 11131 11132 #ifdef CONFIG_IXGBE_DCA 11133 if (dca_add_requester(&pdev->dev) == 0) { 11134 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11135 ixgbe_setup_dca(adapter); 11136 } 11137 #endif 11138 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11139 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11140 for (i = 0; i < adapter->num_vfs; i++) 11141 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11142 } 11143 11144 /* firmware requires driver version to be 0xFFFFFFFF 11145 * since os does not support feature 11146 */ 11147 if (hw->mac.ops.set_fw_drv_ver) 11148 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11149 sizeof(ixgbe_driver_version) - 1, 11150 ixgbe_driver_version); 11151 11152 /* add san mac addr to netdev */ 11153 ixgbe_add_sanmac_netdev(netdev); 11154 11155 e_dev_info("%s\n", ixgbe_default_device_descr); 11156 11157 #ifdef CONFIG_IXGBE_HWMON 11158 if (ixgbe_sysfs_init(adapter)) 11159 e_err(probe, "failed to allocate sysfs resources\n"); 11160 #endif /* CONFIG_IXGBE_HWMON */ 11161 11162 ixgbe_dbg_adapter_init(adapter); 11163 11164 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11165 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11166 hw->mac.ops.setup_link(hw, 11167 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11168 true); 11169 11170 ixgbe_mii_bus_init(hw); 11171 11172 return 0; 11173 11174 err_register: 11175 ixgbe_release_hw_control(adapter); 11176 ixgbe_clear_interrupt_scheme(adapter); 11177 err_sw_init: 11178 ixgbe_disable_sriov(adapter); 11179 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11180 iounmap(adapter->io_addr); 11181 kfree(adapter->jump_tables[0]); 11182 kfree(adapter->mac_table); 11183 kfree(adapter->rss_key); 11184 bitmap_free(adapter->af_xdp_zc_qps); 11185 err_ioremap: 11186 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11187 free_netdev(netdev); 11188 err_alloc_etherdev: 11189 pci_release_mem_regions(pdev); 11190 err_pci_reg: 11191 err_dma: 11192 if (!adapter || disable_dev) 11193 pci_disable_device(pdev); 11194 return err; 11195 } 11196 11197 /** 11198 * ixgbe_remove - Device Removal Routine 11199 * @pdev: PCI device information struct 11200 * 11201 * ixgbe_remove is called by the PCI subsystem to alert the driver 11202 * that it should release a PCI device. The could be caused by a 11203 * Hot-Plug event, or because the driver is going to be removed from 11204 * memory. 11205 **/ 11206 static void ixgbe_remove(struct pci_dev *pdev) 11207 { 11208 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11209 struct net_device *netdev; 11210 bool disable_dev; 11211 int i; 11212 11213 /* if !adapter then we already cleaned up in probe */ 11214 if (!adapter) 11215 return; 11216 11217 netdev = adapter->netdev; 11218 ixgbe_dbg_adapter_exit(adapter); 11219 11220 set_bit(__IXGBE_REMOVING, &adapter->state); 11221 cancel_work_sync(&adapter->service_task); 11222 11223 if (adapter->mii_bus) 11224 mdiobus_unregister(adapter->mii_bus); 11225 11226 #ifdef CONFIG_IXGBE_DCA 11227 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11228 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11229 dca_remove_requester(&pdev->dev); 11230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11231 IXGBE_DCA_CTRL_DCA_DISABLE); 11232 } 11233 11234 #endif 11235 #ifdef CONFIG_IXGBE_HWMON 11236 ixgbe_sysfs_exit(adapter); 11237 #endif /* CONFIG_IXGBE_HWMON */ 11238 11239 /* remove the added san mac */ 11240 ixgbe_del_sanmac_netdev(netdev); 11241 11242 #ifdef CONFIG_PCI_IOV 11243 ixgbe_disable_sriov(adapter); 11244 #endif 11245 if (netdev->reg_state == NETREG_REGISTERED) 11246 unregister_netdev(netdev); 11247 11248 ixgbe_stop_ipsec_offload(adapter); 11249 ixgbe_clear_interrupt_scheme(adapter); 11250 11251 ixgbe_release_hw_control(adapter); 11252 11253 #ifdef CONFIG_DCB 11254 kfree(adapter->ixgbe_ieee_pfc); 11255 kfree(adapter->ixgbe_ieee_ets); 11256 11257 #endif 11258 iounmap(adapter->io_addr); 11259 pci_release_mem_regions(pdev); 11260 11261 e_dev_info("complete\n"); 11262 11263 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11264 if (adapter->jump_tables[i]) { 11265 kfree(adapter->jump_tables[i]->input); 11266 kfree(adapter->jump_tables[i]->mask); 11267 } 11268 kfree(adapter->jump_tables[i]); 11269 } 11270 11271 kfree(adapter->mac_table); 11272 kfree(adapter->rss_key); 11273 bitmap_free(adapter->af_xdp_zc_qps); 11274 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11275 free_netdev(netdev); 11276 11277 pci_disable_pcie_error_reporting(pdev); 11278 11279 if (disable_dev) 11280 pci_disable_device(pdev); 11281 } 11282 11283 /** 11284 * ixgbe_io_error_detected - called when PCI error is detected 11285 * @pdev: Pointer to PCI device 11286 * @state: The current pci connection state 11287 * 11288 * This function is called after a PCI bus error affecting 11289 * this device has been detected. 11290 */ 11291 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11292 pci_channel_state_t state) 11293 { 11294 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11295 struct net_device *netdev = adapter->netdev; 11296 11297 #ifdef CONFIG_PCI_IOV 11298 struct ixgbe_hw *hw = &adapter->hw; 11299 struct pci_dev *bdev, *vfdev; 11300 u32 dw0, dw1, dw2, dw3; 11301 int vf, pos; 11302 u16 req_id, pf_func; 11303 11304 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11305 adapter->num_vfs == 0) 11306 goto skip_bad_vf_detection; 11307 11308 bdev = pdev->bus->self; 11309 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11310 bdev = bdev->bus->self; 11311 11312 if (!bdev) 11313 goto skip_bad_vf_detection; 11314 11315 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11316 if (!pos) 11317 goto skip_bad_vf_detection; 11318 11319 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11320 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11321 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11322 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11323 if (ixgbe_removed(hw->hw_addr)) 11324 goto skip_bad_vf_detection; 11325 11326 req_id = dw1 >> 16; 11327 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11328 if (!(req_id & 0x0080)) 11329 goto skip_bad_vf_detection; 11330 11331 pf_func = req_id & 0x01; 11332 if ((pf_func & 1) == (pdev->devfn & 1)) { 11333 unsigned int device_id; 11334 11335 vf = (req_id & 0x7F) >> 1; 11336 e_dev_err("VF %d has caused a PCIe error\n", vf); 11337 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11338 "%8.8x\tdw3: %8.8x\n", 11339 dw0, dw1, dw2, dw3); 11340 switch (adapter->hw.mac.type) { 11341 case ixgbe_mac_82599EB: 11342 device_id = IXGBE_82599_VF_DEVICE_ID; 11343 break; 11344 case ixgbe_mac_X540: 11345 device_id = IXGBE_X540_VF_DEVICE_ID; 11346 break; 11347 case ixgbe_mac_X550: 11348 device_id = IXGBE_DEV_ID_X550_VF; 11349 break; 11350 case ixgbe_mac_X550EM_x: 11351 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11352 break; 11353 case ixgbe_mac_x550em_a: 11354 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11355 break; 11356 default: 11357 device_id = 0; 11358 break; 11359 } 11360 11361 /* Find the pci device of the offending VF */ 11362 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11363 while (vfdev) { 11364 if (vfdev->devfn == (req_id & 0xFF)) 11365 break; 11366 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11367 device_id, vfdev); 11368 } 11369 /* 11370 * There's a slim chance the VF could have been hot plugged, 11371 * so if it is no longer present we don't need to issue the 11372 * VFLR. Just clean up the AER in that case. 11373 */ 11374 if (vfdev) { 11375 pcie_flr(vfdev); 11376 /* Free device reference count */ 11377 pci_dev_put(vfdev); 11378 } 11379 } 11380 11381 /* 11382 * Even though the error may have occurred on the other port 11383 * we still need to increment the vf error reference count for 11384 * both ports because the I/O resume function will be called 11385 * for both of them. 11386 */ 11387 adapter->vferr_refcount++; 11388 11389 return PCI_ERS_RESULT_RECOVERED; 11390 11391 skip_bad_vf_detection: 11392 #endif /* CONFIG_PCI_IOV */ 11393 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11394 return PCI_ERS_RESULT_DISCONNECT; 11395 11396 if (!netif_device_present(netdev)) 11397 return PCI_ERS_RESULT_DISCONNECT; 11398 11399 rtnl_lock(); 11400 netif_device_detach(netdev); 11401 11402 if (netif_running(netdev)) 11403 ixgbe_close_suspend(adapter); 11404 11405 if (state == pci_channel_io_perm_failure) { 11406 rtnl_unlock(); 11407 return PCI_ERS_RESULT_DISCONNECT; 11408 } 11409 11410 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11411 pci_disable_device(pdev); 11412 rtnl_unlock(); 11413 11414 /* Request a slot reset. */ 11415 return PCI_ERS_RESULT_NEED_RESET; 11416 } 11417 11418 /** 11419 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11420 * @pdev: Pointer to PCI device 11421 * 11422 * Restart the card from scratch, as if from a cold-boot. 11423 */ 11424 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11425 { 11426 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11427 pci_ers_result_t result; 11428 11429 if (pci_enable_device_mem(pdev)) { 11430 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11431 result = PCI_ERS_RESULT_DISCONNECT; 11432 } else { 11433 smp_mb__before_atomic(); 11434 clear_bit(__IXGBE_DISABLED, &adapter->state); 11435 adapter->hw.hw_addr = adapter->io_addr; 11436 pci_set_master(pdev); 11437 pci_restore_state(pdev); 11438 pci_save_state(pdev); 11439 11440 pci_wake_from_d3(pdev, false); 11441 11442 ixgbe_reset(adapter); 11443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11444 result = PCI_ERS_RESULT_RECOVERED; 11445 } 11446 11447 return result; 11448 } 11449 11450 /** 11451 * ixgbe_io_resume - called when traffic can start flowing again. 11452 * @pdev: Pointer to PCI device 11453 * 11454 * This callback is called when the error recovery driver tells us that 11455 * its OK to resume normal operation. 11456 */ 11457 static void ixgbe_io_resume(struct pci_dev *pdev) 11458 { 11459 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11460 struct net_device *netdev = adapter->netdev; 11461 11462 #ifdef CONFIG_PCI_IOV 11463 if (adapter->vferr_refcount) { 11464 e_info(drv, "Resuming after VF err\n"); 11465 adapter->vferr_refcount--; 11466 return; 11467 } 11468 11469 #endif 11470 rtnl_lock(); 11471 if (netif_running(netdev)) 11472 ixgbe_open(netdev); 11473 11474 netif_device_attach(netdev); 11475 rtnl_unlock(); 11476 } 11477 11478 static const struct pci_error_handlers ixgbe_err_handler = { 11479 .error_detected = ixgbe_io_error_detected, 11480 .slot_reset = ixgbe_io_slot_reset, 11481 .resume = ixgbe_io_resume, 11482 }; 11483 11484 static struct pci_driver ixgbe_driver = { 11485 .name = ixgbe_driver_name, 11486 .id_table = ixgbe_pci_tbl, 11487 .probe = ixgbe_probe, 11488 .remove = ixgbe_remove, 11489 #ifdef CONFIG_PM 11490 .suspend = ixgbe_suspend, 11491 .resume = ixgbe_resume, 11492 #endif 11493 .shutdown = ixgbe_shutdown, 11494 .sriov_configure = ixgbe_pci_sriov_configure, 11495 .err_handler = &ixgbe_err_handler 11496 }; 11497 11498 /** 11499 * ixgbe_init_module - Driver Registration Routine 11500 * 11501 * ixgbe_init_module is the first routine called when the driver is 11502 * loaded. All it does is register with the PCI subsystem. 11503 **/ 11504 static int __init ixgbe_init_module(void) 11505 { 11506 int ret; 11507 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11508 pr_info("%s\n", ixgbe_copyright); 11509 11510 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11511 if (!ixgbe_wq) { 11512 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11513 return -ENOMEM; 11514 } 11515 11516 ixgbe_dbg_init(); 11517 11518 ret = pci_register_driver(&ixgbe_driver); 11519 if (ret) { 11520 destroy_workqueue(ixgbe_wq); 11521 ixgbe_dbg_exit(); 11522 return ret; 11523 } 11524 11525 #ifdef CONFIG_IXGBE_DCA 11526 dca_register_notify(&dca_notifier); 11527 #endif 11528 11529 return 0; 11530 } 11531 11532 module_init(ixgbe_init_module); 11533 11534 /** 11535 * ixgbe_exit_module - Driver Exit Cleanup Routine 11536 * 11537 * ixgbe_exit_module is called just before the driver is removed 11538 * from memory. 11539 **/ 11540 static void __exit ixgbe_exit_module(void) 11541 { 11542 #ifdef CONFIG_IXGBE_DCA 11543 dca_unregister_notify(&dca_notifier); 11544 #endif 11545 pci_unregister_driver(&ixgbe_driver); 11546 11547 ixgbe_dbg_exit(); 11548 if (ixgbe_wq) { 11549 destroy_workqueue(ixgbe_wq); 11550 ixgbe_wq = NULL; 11551 } 11552 } 11553 11554 #ifdef CONFIG_IXGBE_DCA 11555 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11556 void *p) 11557 { 11558 int ret_val; 11559 11560 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11561 __ixgbe_notify_dca); 11562 11563 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11564 } 11565 11566 #endif /* CONFIG_IXGBE_DCA */ 11567 11568 module_exit(ixgbe_exit_module); 11569 11570 /* ixgbe_main.c */ 11571