1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <linux/bpf.h> 53 #include <linux/bpf_trace.h> 54 #include <linux/atomic.h> 55 #include <scsi/fc/fc_fcoe.h> 56 #include <net/udp_tunnel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/vxlan.h> 61 #include <net/mpls.h> 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 #include "ixgbe_model.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "5.1.0-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2016 Intel Corporation."; 83 84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 85 86 static const struct ixgbe_info *ixgbe_info_tbl[] = { 87 [board_82598] = &ixgbe_82598_info, 88 [board_82599] = &ixgbe_82599_info, 89 [board_X540] = &ixgbe_X540_info, 90 [board_X550] = &ixgbe_X550_info, 91 [board_X550EM_x] = &ixgbe_X550EM_x_info, 92 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 93 [board_x550em_a] = &ixgbe_x550em_a_info, 94 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 152 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 153 /* required last entry */ 154 {0, } 155 }; 156 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 157 158 #ifdef CONFIG_IXGBE_DCA 159 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 160 void *p); 161 static struct notifier_block dca_notifier = { 162 .notifier_call = ixgbe_notify_dca, 163 .next = NULL, 164 .priority = 0 165 }; 166 #endif 167 168 #ifdef CONFIG_PCI_IOV 169 static unsigned int max_vfs; 170 module_param(max_vfs, uint, 0); 171 MODULE_PARM_DESC(max_vfs, 172 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 173 #endif /* CONFIG_PCI_IOV */ 174 175 static unsigned int allow_unsupported_sfp; 176 module_param(allow_unsupported_sfp, uint, 0); 177 MODULE_PARM_DESC(allow_unsupported_sfp, 178 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 179 180 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 181 static int debug = -1; 182 module_param(debug, int, 0); 183 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 184 185 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 186 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 187 MODULE_LICENSE("GPL"); 188 MODULE_VERSION(DRV_VERSION); 189 190 static struct workqueue_struct *ixgbe_wq; 191 192 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 193 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 194 195 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 196 u32 reg, u16 *value) 197 { 198 struct pci_dev *parent_dev; 199 struct pci_bus *parent_bus; 200 201 parent_bus = adapter->pdev->bus->parent; 202 if (!parent_bus) 203 return -1; 204 205 parent_dev = parent_bus->self; 206 if (!parent_dev) 207 return -1; 208 209 if (!pci_is_pcie(parent_dev)) 210 return -1; 211 212 pcie_capability_read_word(parent_dev, reg, value); 213 if (*value == IXGBE_FAILED_READ_CFG_WORD && 214 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 215 return -1; 216 return 0; 217 } 218 219 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 220 { 221 struct ixgbe_hw *hw = &adapter->hw; 222 u16 link_status = 0; 223 int err; 224 225 hw->bus.type = ixgbe_bus_type_pci_express; 226 227 /* Get the negotiated link width and speed from PCI config space of the 228 * parent, as this device is behind a switch 229 */ 230 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 231 232 /* assume caller will handle error case */ 233 if (err) 234 return err; 235 236 hw->bus.width = ixgbe_convert_bus_width(link_status); 237 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 238 239 return 0; 240 } 241 242 /** 243 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 244 * @hw: hw specific details 245 * 246 * This function is used by probe to determine whether a device's PCI-Express 247 * bandwidth details should be gathered from the parent bus instead of from the 248 * device. Used to ensure that various locations all have the correct device ID 249 * checks. 250 */ 251 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 252 { 253 switch (hw->device_id) { 254 case IXGBE_DEV_ID_82599_SFP_SF_QP: 255 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 256 return true; 257 default: 258 return false; 259 } 260 } 261 262 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 263 int expected_gts) 264 { 265 struct ixgbe_hw *hw = &adapter->hw; 266 int max_gts = 0; 267 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 268 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 269 struct pci_dev *pdev; 270 271 /* Some devices are not connected over PCIe and thus do not negotiate 272 * speed. These devices do not have valid bus info, and thus any report 273 * we generate may not be correct. 274 */ 275 if (hw->bus.type == ixgbe_bus_type_internal) 276 return; 277 278 /* determine whether to use the parent device */ 279 if (ixgbe_pcie_from_parent(&adapter->hw)) 280 pdev = adapter->pdev->bus->parent->self; 281 else 282 pdev = adapter->pdev; 283 284 if (pcie_get_minimum_link(pdev, &speed, &width) || 285 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 286 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 287 return; 288 } 289 290 switch (speed) { 291 case PCIE_SPEED_2_5GT: 292 /* 8b/10b encoding reduces max throughput by 20% */ 293 max_gts = 2 * width; 294 break; 295 case PCIE_SPEED_5_0GT: 296 /* 8b/10b encoding reduces max throughput by 20% */ 297 max_gts = 4 * width; 298 break; 299 case PCIE_SPEED_8_0GT: 300 /* 128b/130b encoding reduces throughput by less than 2% */ 301 max_gts = 8 * width; 302 break; 303 default: 304 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 305 return; 306 } 307 308 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 309 max_gts); 310 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 311 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 312 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 313 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 314 "Unknown"), 315 width, 316 (speed == PCIE_SPEED_2_5GT ? "20%" : 317 speed == PCIE_SPEED_5_0GT ? "20%" : 318 speed == PCIE_SPEED_8_0GT ? "<2%" : 319 "Unknown")); 320 321 if (max_gts < expected_gts) { 322 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 323 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 324 expected_gts); 325 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 326 } 327 } 328 329 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 330 { 331 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 332 !test_bit(__IXGBE_REMOVING, &adapter->state) && 333 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 334 queue_work(ixgbe_wq, &adapter->service_task); 335 } 336 337 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 338 { 339 struct ixgbe_adapter *adapter = hw->back; 340 341 if (!hw->hw_addr) 342 return; 343 hw->hw_addr = NULL; 344 e_dev_err("Adapter removed\n"); 345 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 346 ixgbe_service_event_schedule(adapter); 347 } 348 349 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 350 { 351 u32 value; 352 353 /* The following check not only optimizes a bit by not 354 * performing a read on the status register when the 355 * register just read was a status register read that 356 * returned IXGBE_FAILED_READ_REG. It also blocks any 357 * potential recursion. 358 */ 359 if (reg == IXGBE_STATUS) { 360 ixgbe_remove_adapter(hw); 361 return; 362 } 363 value = ixgbe_read_reg(hw, IXGBE_STATUS); 364 if (value == IXGBE_FAILED_READ_REG) 365 ixgbe_remove_adapter(hw); 366 } 367 368 /** 369 * ixgbe_read_reg - Read from device register 370 * @hw: hw specific details 371 * @reg: offset of register to read 372 * 373 * Returns : value read or IXGBE_FAILED_READ_REG if removed 374 * 375 * This function is used to read device registers. It checks for device 376 * removal by confirming any read that returns all ones by checking the 377 * status register value for all ones. This function avoids reading from 378 * the hardware if a removal was previously detected in which case it 379 * returns IXGBE_FAILED_READ_REG (all ones). 380 */ 381 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 382 { 383 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 384 u32 value; 385 386 if (ixgbe_removed(reg_addr)) 387 return IXGBE_FAILED_READ_REG; 388 if (unlikely(hw->phy.nw_mng_if_sel & 389 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 390 struct ixgbe_adapter *adapter; 391 int i; 392 393 for (i = 0; i < 200; ++i) { 394 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 395 if (likely(!value)) 396 goto writes_completed; 397 if (value == IXGBE_FAILED_READ_REG) { 398 ixgbe_remove_adapter(hw); 399 return IXGBE_FAILED_READ_REG; 400 } 401 udelay(5); 402 } 403 404 adapter = hw->back; 405 e_warn(hw, "register writes incomplete %08x\n", value); 406 } 407 408 writes_completed: 409 value = readl(reg_addr + reg); 410 if (unlikely(value == IXGBE_FAILED_READ_REG)) 411 ixgbe_check_remove(hw, reg); 412 return value; 413 } 414 415 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 416 { 417 u16 value; 418 419 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 420 if (value == IXGBE_FAILED_READ_CFG_WORD) { 421 ixgbe_remove_adapter(hw); 422 return true; 423 } 424 return false; 425 } 426 427 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 428 { 429 struct ixgbe_adapter *adapter = hw->back; 430 u16 value; 431 432 if (ixgbe_removed(hw->hw_addr)) 433 return IXGBE_FAILED_READ_CFG_WORD; 434 pci_read_config_word(adapter->pdev, reg, &value); 435 if (value == IXGBE_FAILED_READ_CFG_WORD && 436 ixgbe_check_cfg_remove(hw, adapter->pdev)) 437 return IXGBE_FAILED_READ_CFG_WORD; 438 return value; 439 } 440 441 #ifdef CONFIG_PCI_IOV 442 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 443 { 444 struct ixgbe_adapter *adapter = hw->back; 445 u32 value; 446 447 if (ixgbe_removed(hw->hw_addr)) 448 return IXGBE_FAILED_READ_CFG_DWORD; 449 pci_read_config_dword(adapter->pdev, reg, &value); 450 if (value == IXGBE_FAILED_READ_CFG_DWORD && 451 ixgbe_check_cfg_remove(hw, adapter->pdev)) 452 return IXGBE_FAILED_READ_CFG_DWORD; 453 return value; 454 } 455 #endif /* CONFIG_PCI_IOV */ 456 457 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 458 { 459 struct ixgbe_adapter *adapter = hw->back; 460 461 if (ixgbe_removed(hw->hw_addr)) 462 return; 463 pci_write_config_word(adapter->pdev, reg, value); 464 } 465 466 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 467 { 468 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 469 470 /* flush memory to make sure state is correct before next watchdog */ 471 smp_mb__before_atomic(); 472 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 473 } 474 475 struct ixgbe_reg_info { 476 u32 ofs; 477 char *name; 478 }; 479 480 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 481 482 /* General Registers */ 483 {IXGBE_CTRL, "CTRL"}, 484 {IXGBE_STATUS, "STATUS"}, 485 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 486 487 /* Interrupt Registers */ 488 {IXGBE_EICR, "EICR"}, 489 490 /* RX Registers */ 491 {IXGBE_SRRCTL(0), "SRRCTL"}, 492 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 493 {IXGBE_RDLEN(0), "RDLEN"}, 494 {IXGBE_RDH(0), "RDH"}, 495 {IXGBE_RDT(0), "RDT"}, 496 {IXGBE_RXDCTL(0), "RXDCTL"}, 497 {IXGBE_RDBAL(0), "RDBAL"}, 498 {IXGBE_RDBAH(0), "RDBAH"}, 499 500 /* TX Registers */ 501 {IXGBE_TDBAL(0), "TDBAL"}, 502 {IXGBE_TDBAH(0), "TDBAH"}, 503 {IXGBE_TDLEN(0), "TDLEN"}, 504 {IXGBE_TDH(0), "TDH"}, 505 {IXGBE_TDT(0), "TDT"}, 506 {IXGBE_TXDCTL(0), "TXDCTL"}, 507 508 /* List Terminator */ 509 { .name = NULL } 510 }; 511 512 513 /* 514 * ixgbe_regdump - register printout routine 515 */ 516 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 517 { 518 int i; 519 char rname[16]; 520 u32 regs[64]; 521 522 switch (reginfo->ofs) { 523 case IXGBE_SRRCTL(0): 524 for (i = 0; i < 64; i++) 525 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 526 break; 527 case IXGBE_DCA_RXCTRL(0): 528 for (i = 0; i < 64; i++) 529 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 530 break; 531 case IXGBE_RDLEN(0): 532 for (i = 0; i < 64; i++) 533 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 534 break; 535 case IXGBE_RDH(0): 536 for (i = 0; i < 64; i++) 537 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 538 break; 539 case IXGBE_RDT(0): 540 for (i = 0; i < 64; i++) 541 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 542 break; 543 case IXGBE_RXDCTL(0): 544 for (i = 0; i < 64; i++) 545 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 546 break; 547 case IXGBE_RDBAL(0): 548 for (i = 0; i < 64; i++) 549 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 550 break; 551 case IXGBE_RDBAH(0): 552 for (i = 0; i < 64; i++) 553 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 554 break; 555 case IXGBE_TDBAL(0): 556 for (i = 0; i < 64; i++) 557 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 558 break; 559 case IXGBE_TDBAH(0): 560 for (i = 0; i < 64; i++) 561 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 562 break; 563 case IXGBE_TDLEN(0): 564 for (i = 0; i < 64; i++) 565 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 566 break; 567 case IXGBE_TDH(0): 568 for (i = 0; i < 64; i++) 569 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 570 break; 571 case IXGBE_TDT(0): 572 for (i = 0; i < 64; i++) 573 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 574 break; 575 case IXGBE_TXDCTL(0): 576 for (i = 0; i < 64; i++) 577 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 578 break; 579 default: 580 pr_info("%-15s %08x\n", 581 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 582 return; 583 } 584 585 i = 0; 586 while (i < 64) { 587 int j; 588 char buf[9 * 8 + 1]; 589 char *p = buf; 590 591 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 592 for (j = 0; j < 8; j++) 593 p += sprintf(p, " %08x", regs[i++]); 594 pr_err("%-15s%s\n", rname, buf); 595 } 596 597 } 598 599 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 600 { 601 struct ixgbe_tx_buffer *tx_buffer; 602 603 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 604 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 605 n, ring->next_to_use, ring->next_to_clean, 606 (u64)dma_unmap_addr(tx_buffer, dma), 607 dma_unmap_len(tx_buffer, len), 608 tx_buffer->next_to_watch, 609 (u64)tx_buffer->time_stamp); 610 } 611 612 /* 613 * ixgbe_dump - Print registers, tx-rings and rx-rings 614 */ 615 static void ixgbe_dump(struct ixgbe_adapter *adapter) 616 { 617 struct net_device *netdev = adapter->netdev; 618 struct ixgbe_hw *hw = &adapter->hw; 619 struct ixgbe_reg_info *reginfo; 620 int n = 0; 621 struct ixgbe_ring *ring; 622 struct ixgbe_tx_buffer *tx_buffer; 623 union ixgbe_adv_tx_desc *tx_desc; 624 struct my_u0 { u64 a; u64 b; } *u0; 625 struct ixgbe_ring *rx_ring; 626 union ixgbe_adv_rx_desc *rx_desc; 627 struct ixgbe_rx_buffer *rx_buffer_info; 628 int i = 0; 629 630 if (!netif_msg_hw(adapter)) 631 return; 632 633 /* Print netdevice Info */ 634 if (netdev) { 635 dev_info(&adapter->pdev->dev, "Net device Info\n"); 636 pr_info("Device Name state " 637 "trans_start\n"); 638 pr_info("%-15s %016lX %016lX\n", 639 netdev->name, 640 netdev->state, 641 dev_trans_start(netdev)); 642 } 643 644 /* Print Registers */ 645 dev_info(&adapter->pdev->dev, "Register Dump\n"); 646 pr_info(" Register Name Value\n"); 647 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 648 reginfo->name; reginfo++) { 649 ixgbe_regdump(hw, reginfo); 650 } 651 652 /* Print TX Ring Summary */ 653 if (!netdev || !netif_running(netdev)) 654 return; 655 656 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 657 pr_info(" %s %s %s %s\n", 658 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 659 "leng", "ntw", "timestamp"); 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 ring = adapter->tx_ring[n]; 662 ixgbe_print_buffer(ring, n); 663 } 664 665 for (n = 0; n < adapter->num_xdp_queues; n++) { 666 ring = adapter->xdp_ring[n]; 667 ixgbe_print_buffer(ring, n); 668 } 669 670 /* Print TX Rings */ 671 if (!netif_msg_tx_done(adapter)) 672 goto rx_ring_summary; 673 674 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 675 676 /* Transmit Descriptor Formats 677 * 678 * 82598 Advanced Transmit Descriptor 679 * +--------------------------------------------------------------+ 680 * 0 | Buffer Address [63:0] | 681 * +--------------------------------------------------------------+ 682 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 683 * +--------------------------------------------------------------+ 684 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 685 * 686 * 82598 Advanced Transmit Descriptor (Write-Back Format) 687 * +--------------------------------------------------------------+ 688 * 0 | RSV [63:0] | 689 * +--------------------------------------------------------------+ 690 * 8 | RSV | STA | NXTSEQ | 691 * +--------------------------------------------------------------+ 692 * 63 36 35 32 31 0 693 * 694 * 82599+ Advanced Transmit Descriptor 695 * +--------------------------------------------------------------+ 696 * 0 | Buffer Address [63:0] | 697 * +--------------------------------------------------------------+ 698 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 699 * +--------------------------------------------------------------+ 700 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 701 * 702 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 703 * +--------------------------------------------------------------+ 704 * 0 | RSV [63:0] | 705 * +--------------------------------------------------------------+ 706 * 8 | RSV | STA | RSV | 707 * +--------------------------------------------------------------+ 708 * 63 36 35 32 31 0 709 */ 710 711 for (n = 0; n < adapter->num_tx_queues; n++) { 712 ring = adapter->tx_ring[n]; 713 pr_info("------------------------------------\n"); 714 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 715 pr_info("------------------------------------\n"); 716 pr_info("%s%s %s %s %s %s\n", 717 "T [desc] [address 63:0 ] ", 718 "[PlPOIdStDDt Ln] [bi->dma ] ", 719 "leng", "ntw", "timestamp", "bi->skb"); 720 721 for (i = 0; ring->desc && (i < ring->count); i++) { 722 tx_desc = IXGBE_TX_DESC(ring, i); 723 tx_buffer = &ring->tx_buffer_info[i]; 724 u0 = (struct my_u0 *)tx_desc; 725 if (dma_unmap_len(tx_buffer, len) > 0) { 726 const char *ring_desc; 727 728 if (i == ring->next_to_use && 729 i == ring->next_to_clean) 730 ring_desc = " NTC/U"; 731 else if (i == ring->next_to_use) 732 ring_desc = " NTU"; 733 else if (i == ring->next_to_clean) 734 ring_desc = " NTC"; 735 else 736 ring_desc = ""; 737 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 738 i, 739 le64_to_cpu(u0->a), 740 le64_to_cpu(u0->b), 741 (u64)dma_unmap_addr(tx_buffer, dma), 742 dma_unmap_len(tx_buffer, len), 743 tx_buffer->next_to_watch, 744 (u64)tx_buffer->time_stamp, 745 tx_buffer->skb, 746 ring_desc); 747 748 if (netif_msg_pktdata(adapter) && 749 tx_buffer->skb) 750 print_hex_dump(KERN_INFO, "", 751 DUMP_PREFIX_ADDRESS, 16, 1, 752 tx_buffer->skb->data, 753 dma_unmap_len(tx_buffer, len), 754 true); 755 } 756 } 757 } 758 759 /* Print RX Rings Summary */ 760 rx_ring_summary: 761 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 762 pr_info("Queue [NTU] [NTC]\n"); 763 for (n = 0; n < adapter->num_rx_queues; n++) { 764 rx_ring = adapter->rx_ring[n]; 765 pr_info("%5d %5X %5X\n", 766 n, rx_ring->next_to_use, rx_ring->next_to_clean); 767 } 768 769 /* Print RX Rings */ 770 if (!netif_msg_rx_status(adapter)) 771 return; 772 773 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 774 775 /* Receive Descriptor Formats 776 * 777 * 82598 Advanced Receive Descriptor (Read) Format 778 * 63 1 0 779 * +-----------------------------------------------------+ 780 * 0 | Packet Buffer Address [63:1] |A0/NSE| 781 * +----------------------------------------------+------+ 782 * 8 | Header Buffer Address [63:1] | DD | 783 * +-----------------------------------------------------+ 784 * 785 * 786 * 82598 Advanced Receive Descriptor (Write-Back) Format 787 * 788 * 63 48 47 32 31 30 21 20 16 15 4 3 0 789 * +------------------------------------------------------+ 790 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 791 * | Packet | IP | | | | Type | Type | 792 * | Checksum | Ident | | | | | | 793 * +------------------------------------------------------+ 794 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 795 * +------------------------------------------------------+ 796 * 63 48 47 32 31 20 19 0 797 * 798 * 82599+ Advanced Receive Descriptor (Read) Format 799 * 63 1 0 800 * +-----------------------------------------------------+ 801 * 0 | Packet Buffer Address [63:1] |A0/NSE| 802 * +----------------------------------------------+------+ 803 * 8 | Header Buffer Address [63:1] | DD | 804 * +-----------------------------------------------------+ 805 * 806 * 807 * 82599+ Advanced Receive Descriptor (Write-Back) Format 808 * 809 * 63 48 47 32 31 30 21 20 17 16 4 3 0 810 * +------------------------------------------------------+ 811 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 812 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 813 * |/ Flow Dir Flt ID | | | | | | 814 * +------------------------------------------------------+ 815 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 816 * +------------------------------------------------------+ 817 * 63 48 47 32 31 20 19 0 818 */ 819 820 for (n = 0; n < adapter->num_rx_queues; n++) { 821 rx_ring = adapter->rx_ring[n]; 822 pr_info("------------------------------------\n"); 823 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 824 pr_info("------------------------------------\n"); 825 pr_info("%s%s%s\n", 826 "R [desc] [ PktBuf A0] ", 827 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 828 "<-- Adv Rx Read format"); 829 pr_info("%s%s%s\n", 830 "RWB[desc] [PcsmIpSHl PtRs] ", 831 "[vl er S cks ln] ---------------- [bi->skb ] ", 832 "<-- Adv Rx Write-Back format"); 833 834 for (i = 0; i < rx_ring->count; i++) { 835 const char *ring_desc; 836 837 if (i == rx_ring->next_to_use) 838 ring_desc = " NTU"; 839 else if (i == rx_ring->next_to_clean) 840 ring_desc = " NTC"; 841 else 842 ring_desc = ""; 843 844 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 845 rx_desc = IXGBE_RX_DESC(rx_ring, i); 846 u0 = (struct my_u0 *)rx_desc; 847 if (rx_desc->wb.upper.length) { 848 /* Descriptor Done */ 849 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 850 i, 851 le64_to_cpu(u0->a), 852 le64_to_cpu(u0->b), 853 rx_buffer_info->skb, 854 ring_desc); 855 } else { 856 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 857 i, 858 le64_to_cpu(u0->a), 859 le64_to_cpu(u0->b), 860 (u64)rx_buffer_info->dma, 861 rx_buffer_info->skb, 862 ring_desc); 863 864 if (netif_msg_pktdata(adapter) && 865 rx_buffer_info->dma) { 866 print_hex_dump(KERN_INFO, "", 867 DUMP_PREFIX_ADDRESS, 16, 1, 868 page_address(rx_buffer_info->page) + 869 rx_buffer_info->page_offset, 870 ixgbe_rx_bufsz(rx_ring), true); 871 } 872 } 873 } 874 } 875 } 876 877 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 878 { 879 u32 ctrl_ext; 880 881 /* Let firmware take over control of h/w */ 882 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 884 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 885 } 886 887 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 888 { 889 u32 ctrl_ext; 890 891 /* Let firmware know the driver has taken over */ 892 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 894 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 895 } 896 897 /** 898 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 899 * @adapter: pointer to adapter struct 900 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 901 * @queue: queue to map the corresponding interrupt to 902 * @msix_vector: the vector to map to the corresponding queue 903 * 904 */ 905 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 906 u8 queue, u8 msix_vector) 907 { 908 u32 ivar, index; 909 struct ixgbe_hw *hw = &adapter->hw; 910 switch (hw->mac.type) { 911 case ixgbe_mac_82598EB: 912 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 913 if (direction == -1) 914 direction = 0; 915 index = (((direction * 64) + queue) >> 2) & 0x1F; 916 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 917 ivar &= ~(0xFF << (8 * (queue & 0x3))); 918 ivar |= (msix_vector << (8 * (queue & 0x3))); 919 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 920 break; 921 case ixgbe_mac_82599EB: 922 case ixgbe_mac_X540: 923 case ixgbe_mac_X550: 924 case ixgbe_mac_X550EM_x: 925 case ixgbe_mac_x550em_a: 926 if (direction == -1) { 927 /* other causes */ 928 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 929 index = ((queue & 1) * 8); 930 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 931 ivar &= ~(0xFF << index); 932 ivar |= (msix_vector << index); 933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 934 break; 935 } else { 936 /* tx or rx causes */ 937 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 938 index = ((16 * (queue & 1)) + (8 * direction)); 939 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 940 ivar &= ~(0xFF << index); 941 ivar |= (msix_vector << index); 942 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 943 break; 944 } 945 default: 946 break; 947 } 948 } 949 950 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 951 u64 qmask) 952 { 953 u32 mask; 954 955 switch (adapter->hw.mac.type) { 956 case ixgbe_mac_82598EB: 957 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 959 break; 960 case ixgbe_mac_82599EB: 961 case ixgbe_mac_X540: 962 case ixgbe_mac_X550: 963 case ixgbe_mac_X550EM_x: 964 case ixgbe_mac_x550em_a: 965 mask = (qmask & 0xFFFFFFFF); 966 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 967 mask = (qmask >> 32); 968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 969 break; 970 default: 971 break; 972 } 973 } 974 975 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 976 { 977 struct ixgbe_hw *hw = &adapter->hw; 978 struct ixgbe_hw_stats *hwstats = &adapter->stats; 979 int i; 980 u32 data; 981 982 if ((hw->fc.current_mode != ixgbe_fc_full) && 983 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 984 return; 985 986 switch (hw->mac.type) { 987 case ixgbe_mac_82598EB: 988 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 989 break; 990 default: 991 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 992 } 993 hwstats->lxoffrxc += data; 994 995 /* refill credits (no tx hang) if we received xoff */ 996 if (!data) 997 return; 998 999 for (i = 0; i < adapter->num_tx_queues; i++) 1000 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1001 &adapter->tx_ring[i]->state); 1002 1003 for (i = 0; i < adapter->num_xdp_queues; i++) 1004 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1005 &adapter->xdp_ring[i]->state); 1006 } 1007 1008 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1009 { 1010 struct ixgbe_hw *hw = &adapter->hw; 1011 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1012 u32 xoff[8] = {0}; 1013 u8 tc; 1014 int i; 1015 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1016 1017 if (adapter->ixgbe_ieee_pfc) 1018 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1019 1020 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1021 ixgbe_update_xoff_rx_lfc(adapter); 1022 return; 1023 } 1024 1025 /* update stats for each tc, only valid with PFC enabled */ 1026 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1027 u32 pxoffrxc; 1028 1029 switch (hw->mac.type) { 1030 case ixgbe_mac_82598EB: 1031 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1032 break; 1033 default: 1034 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1035 } 1036 hwstats->pxoffrxc[i] += pxoffrxc; 1037 /* Get the TC for given UP */ 1038 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1039 xoff[tc] += pxoffrxc; 1040 } 1041 1042 /* disarm tx queues that have received xoff frames */ 1043 for (i = 0; i < adapter->num_tx_queues; i++) { 1044 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1045 1046 tc = tx_ring->dcb_tc; 1047 if (xoff[tc]) 1048 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1049 } 1050 1051 for (i = 0; i < adapter->num_xdp_queues; i++) { 1052 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1053 1054 tc = xdp_ring->dcb_tc; 1055 if (xoff[tc]) 1056 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1057 } 1058 } 1059 1060 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1061 { 1062 return ring->stats.packets; 1063 } 1064 1065 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1066 { 1067 struct ixgbe_adapter *adapter; 1068 struct ixgbe_hw *hw; 1069 u32 head, tail; 1070 1071 if (ring->l2_accel_priv) 1072 adapter = ring->l2_accel_priv->real_adapter; 1073 else 1074 adapter = netdev_priv(ring->netdev); 1075 1076 hw = &adapter->hw; 1077 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1078 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1079 1080 if (head != tail) 1081 return (head < tail) ? 1082 tail - head : (tail + ring->count - head); 1083 1084 return 0; 1085 } 1086 1087 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1088 { 1089 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1090 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1091 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1092 1093 clear_check_for_tx_hang(tx_ring); 1094 1095 /* 1096 * Check for a hung queue, but be thorough. This verifies 1097 * that a transmit has been completed since the previous 1098 * check AND there is at least one packet pending. The 1099 * ARMED bit is set to indicate a potential hang. The 1100 * bit is cleared if a pause frame is received to remove 1101 * false hang detection due to PFC or 802.3x frames. By 1102 * requiring this to fail twice we avoid races with 1103 * pfc clearing the ARMED bit and conditions where we 1104 * run the check_tx_hang logic with a transmit completion 1105 * pending but without time to complete it yet. 1106 */ 1107 if (tx_done_old == tx_done && tx_pending) 1108 /* make sure it is true for two checks in a row */ 1109 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1110 &tx_ring->state); 1111 /* update completed stats and continue */ 1112 tx_ring->tx_stats.tx_done_old = tx_done; 1113 /* reset the countdown */ 1114 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1115 1116 return false; 1117 } 1118 1119 /** 1120 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1121 * @adapter: driver private struct 1122 **/ 1123 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1124 { 1125 1126 /* Do the reset outside of interrupt context */ 1127 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1128 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1129 e_warn(drv, "initiating reset due to tx timeout\n"); 1130 ixgbe_service_event_schedule(adapter); 1131 } 1132 } 1133 1134 /** 1135 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1136 **/ 1137 static int ixgbe_tx_maxrate(struct net_device *netdev, 1138 int queue_index, u32 maxrate) 1139 { 1140 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1141 struct ixgbe_hw *hw = &adapter->hw; 1142 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1143 1144 if (!maxrate) 1145 return 0; 1146 1147 /* Calculate the rate factor values to set */ 1148 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1149 bcnrc_val /= maxrate; 1150 1151 /* clear everything but the rate factor */ 1152 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1153 IXGBE_RTTBCNRC_RF_DEC_MASK; 1154 1155 /* enable the rate scheduler */ 1156 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1157 1158 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1159 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1160 1161 return 0; 1162 } 1163 1164 /** 1165 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1166 * @q_vector: structure containing interrupt and ring information 1167 * @tx_ring: tx ring to clean 1168 * @napi_budget: Used to determine if we are in netpoll 1169 **/ 1170 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1171 struct ixgbe_ring *tx_ring, int napi_budget) 1172 { 1173 struct ixgbe_adapter *adapter = q_vector->adapter; 1174 struct ixgbe_tx_buffer *tx_buffer; 1175 union ixgbe_adv_tx_desc *tx_desc; 1176 unsigned int total_bytes = 0, total_packets = 0; 1177 unsigned int budget = q_vector->tx.work_limit; 1178 unsigned int i = tx_ring->next_to_clean; 1179 1180 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1181 return true; 1182 1183 tx_buffer = &tx_ring->tx_buffer_info[i]; 1184 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1185 i -= tx_ring->count; 1186 1187 do { 1188 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1189 1190 /* if next_to_watch is not set then there is no work pending */ 1191 if (!eop_desc) 1192 break; 1193 1194 /* prevent any other reads prior to eop_desc */ 1195 read_barrier_depends(); 1196 1197 /* if DD is not set pending work has not been completed */ 1198 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1199 break; 1200 1201 /* clear next_to_watch to prevent false hangs */ 1202 tx_buffer->next_to_watch = NULL; 1203 1204 /* update the statistics for this packet */ 1205 total_bytes += tx_buffer->bytecount; 1206 total_packets += tx_buffer->gso_segs; 1207 1208 /* free the skb */ 1209 if (ring_is_xdp(tx_ring)) 1210 page_frag_free(tx_buffer->data); 1211 else 1212 napi_consume_skb(tx_buffer->skb, napi_budget); 1213 1214 /* unmap skb header data */ 1215 dma_unmap_single(tx_ring->dev, 1216 dma_unmap_addr(tx_buffer, dma), 1217 dma_unmap_len(tx_buffer, len), 1218 DMA_TO_DEVICE); 1219 1220 /* clear tx_buffer data */ 1221 dma_unmap_len_set(tx_buffer, len, 0); 1222 1223 /* unmap remaining buffers */ 1224 while (tx_desc != eop_desc) { 1225 tx_buffer++; 1226 tx_desc++; 1227 i++; 1228 if (unlikely(!i)) { 1229 i -= tx_ring->count; 1230 tx_buffer = tx_ring->tx_buffer_info; 1231 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1232 } 1233 1234 /* unmap any remaining paged data */ 1235 if (dma_unmap_len(tx_buffer, len)) { 1236 dma_unmap_page(tx_ring->dev, 1237 dma_unmap_addr(tx_buffer, dma), 1238 dma_unmap_len(tx_buffer, len), 1239 DMA_TO_DEVICE); 1240 dma_unmap_len_set(tx_buffer, len, 0); 1241 } 1242 } 1243 1244 /* move us one more past the eop_desc for start of next pkt */ 1245 tx_buffer++; 1246 tx_desc++; 1247 i++; 1248 if (unlikely(!i)) { 1249 i -= tx_ring->count; 1250 tx_buffer = tx_ring->tx_buffer_info; 1251 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1252 } 1253 1254 /* issue prefetch for next Tx descriptor */ 1255 prefetch(tx_desc); 1256 1257 /* update budget accounting */ 1258 budget--; 1259 } while (likely(budget)); 1260 1261 i += tx_ring->count; 1262 tx_ring->next_to_clean = i; 1263 u64_stats_update_begin(&tx_ring->syncp); 1264 tx_ring->stats.bytes += total_bytes; 1265 tx_ring->stats.packets += total_packets; 1266 u64_stats_update_end(&tx_ring->syncp); 1267 q_vector->tx.total_bytes += total_bytes; 1268 q_vector->tx.total_packets += total_packets; 1269 1270 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1271 /* schedule immediate reset if we believe we hung */ 1272 struct ixgbe_hw *hw = &adapter->hw; 1273 e_err(drv, "Detected Tx Unit Hang %s\n" 1274 " Tx Queue <%d>\n" 1275 " TDH, TDT <%x>, <%x>\n" 1276 " next_to_use <%x>\n" 1277 " next_to_clean <%x>\n" 1278 "tx_buffer_info[next_to_clean]\n" 1279 " time_stamp <%lx>\n" 1280 " jiffies <%lx>\n", 1281 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1282 tx_ring->queue_index, 1283 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1284 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1285 tx_ring->next_to_use, i, 1286 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1287 1288 if (!ring_is_xdp(tx_ring)) 1289 netif_stop_subqueue(tx_ring->netdev, 1290 tx_ring->queue_index); 1291 1292 e_info(probe, 1293 "tx hang %d detected on queue %d, resetting adapter\n", 1294 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1295 1296 /* schedule immediate reset if we believe we hung */ 1297 ixgbe_tx_timeout_reset(adapter); 1298 1299 /* the adapter is about to reset, no point in enabling stuff */ 1300 return true; 1301 } 1302 1303 if (ring_is_xdp(tx_ring)) 1304 return !!budget; 1305 1306 netdev_tx_completed_queue(txring_txq(tx_ring), 1307 total_packets, total_bytes); 1308 1309 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1310 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1311 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1312 /* Make sure that anybody stopping the queue after this 1313 * sees the new next_to_clean. 1314 */ 1315 smp_mb(); 1316 if (__netif_subqueue_stopped(tx_ring->netdev, 1317 tx_ring->queue_index) 1318 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1319 netif_wake_subqueue(tx_ring->netdev, 1320 tx_ring->queue_index); 1321 ++tx_ring->tx_stats.restart_queue; 1322 } 1323 } 1324 1325 return !!budget; 1326 } 1327 1328 #ifdef CONFIG_IXGBE_DCA 1329 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1330 struct ixgbe_ring *tx_ring, 1331 int cpu) 1332 { 1333 struct ixgbe_hw *hw = &adapter->hw; 1334 u32 txctrl = 0; 1335 u16 reg_offset; 1336 1337 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1338 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1339 1340 switch (hw->mac.type) { 1341 case ixgbe_mac_82598EB: 1342 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1343 break; 1344 case ixgbe_mac_82599EB: 1345 case ixgbe_mac_X540: 1346 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1347 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1348 break; 1349 default: 1350 /* for unknown hardware do not write register */ 1351 return; 1352 } 1353 1354 /* 1355 * We can enable relaxed ordering for reads, but not writes when 1356 * DCA is enabled. This is due to a known issue in some chipsets 1357 * which will cause the DCA tag to be cleared. 1358 */ 1359 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1360 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1361 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1362 1363 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1364 } 1365 1366 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1367 struct ixgbe_ring *rx_ring, 1368 int cpu) 1369 { 1370 struct ixgbe_hw *hw = &adapter->hw; 1371 u32 rxctrl = 0; 1372 u8 reg_idx = rx_ring->reg_idx; 1373 1374 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1375 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1376 1377 switch (hw->mac.type) { 1378 case ixgbe_mac_82599EB: 1379 case ixgbe_mac_X540: 1380 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1381 break; 1382 default: 1383 break; 1384 } 1385 1386 /* 1387 * We can enable relaxed ordering for reads, but not writes when 1388 * DCA is enabled. This is due to a known issue in some chipsets 1389 * which will cause the DCA tag to be cleared. 1390 */ 1391 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1392 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1393 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1394 1395 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1396 } 1397 1398 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1399 { 1400 struct ixgbe_adapter *adapter = q_vector->adapter; 1401 struct ixgbe_ring *ring; 1402 int cpu = get_cpu(); 1403 1404 if (q_vector->cpu == cpu) 1405 goto out_no_update; 1406 1407 ixgbe_for_each_ring(ring, q_vector->tx) 1408 ixgbe_update_tx_dca(adapter, ring, cpu); 1409 1410 ixgbe_for_each_ring(ring, q_vector->rx) 1411 ixgbe_update_rx_dca(adapter, ring, cpu); 1412 1413 q_vector->cpu = cpu; 1414 out_no_update: 1415 put_cpu(); 1416 } 1417 1418 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1419 { 1420 int i; 1421 1422 /* always use CB2 mode, difference is masked in the CB driver */ 1423 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1425 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1426 else 1427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1428 IXGBE_DCA_CTRL_DCA_DISABLE); 1429 1430 for (i = 0; i < adapter->num_q_vectors; i++) { 1431 adapter->q_vector[i]->cpu = -1; 1432 ixgbe_update_dca(adapter->q_vector[i]); 1433 } 1434 } 1435 1436 static int __ixgbe_notify_dca(struct device *dev, void *data) 1437 { 1438 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1439 unsigned long event = *(unsigned long *)data; 1440 1441 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1442 return 0; 1443 1444 switch (event) { 1445 case DCA_PROVIDER_ADD: 1446 /* if we're already enabled, don't do it again */ 1447 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1448 break; 1449 if (dca_add_requester(dev) == 0) { 1450 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1452 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1453 break; 1454 } 1455 /* fall through - DCA is disabled. */ 1456 case DCA_PROVIDER_REMOVE: 1457 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1458 dca_remove_requester(dev); 1459 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1460 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1461 IXGBE_DCA_CTRL_DCA_DISABLE); 1462 } 1463 break; 1464 } 1465 1466 return 0; 1467 } 1468 1469 #endif /* CONFIG_IXGBE_DCA */ 1470 1471 #define IXGBE_RSS_L4_TYPES_MASK \ 1472 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1473 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1474 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1475 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1476 1477 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1478 union ixgbe_adv_rx_desc *rx_desc, 1479 struct sk_buff *skb) 1480 { 1481 u16 rss_type; 1482 1483 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1484 return; 1485 1486 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1487 IXGBE_RXDADV_RSSTYPE_MASK; 1488 1489 if (!rss_type) 1490 return; 1491 1492 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1493 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1494 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1495 } 1496 1497 #ifdef IXGBE_FCOE 1498 /** 1499 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1500 * @ring: structure containing ring specific data 1501 * @rx_desc: advanced rx descriptor 1502 * 1503 * Returns : true if it is FCoE pkt 1504 */ 1505 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1506 union ixgbe_adv_rx_desc *rx_desc) 1507 { 1508 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1509 1510 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1511 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1512 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1513 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1514 } 1515 1516 #endif /* IXGBE_FCOE */ 1517 /** 1518 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1519 * @ring: structure containing ring specific data 1520 * @rx_desc: current Rx descriptor being processed 1521 * @skb: skb currently being received and modified 1522 **/ 1523 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1524 union ixgbe_adv_rx_desc *rx_desc, 1525 struct sk_buff *skb) 1526 { 1527 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1528 bool encap_pkt = false; 1529 1530 skb_checksum_none_assert(skb); 1531 1532 /* Rx csum disabled */ 1533 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1534 return; 1535 1536 /* check for VXLAN and Geneve packets */ 1537 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1538 encap_pkt = true; 1539 skb->encapsulation = 1; 1540 } 1541 1542 /* if IP and error */ 1543 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1544 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1545 ring->rx_stats.csum_err++; 1546 return; 1547 } 1548 1549 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1550 return; 1551 1552 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1553 /* 1554 * 82599 errata, UDP frames with a 0 checksum can be marked as 1555 * checksum errors. 1556 */ 1557 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1558 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1559 return; 1560 1561 ring->rx_stats.csum_err++; 1562 return; 1563 } 1564 1565 /* It must be a TCP or UDP packet with a valid checksum */ 1566 skb->ip_summed = CHECKSUM_UNNECESSARY; 1567 if (encap_pkt) { 1568 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1569 return; 1570 1571 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1572 skb->ip_summed = CHECKSUM_NONE; 1573 return; 1574 } 1575 /* If we checked the outer header let the stack know */ 1576 skb->csum_level = 1; 1577 } 1578 } 1579 1580 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1581 { 1582 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1583 } 1584 1585 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1586 struct ixgbe_rx_buffer *bi) 1587 { 1588 struct page *page = bi->page; 1589 dma_addr_t dma; 1590 1591 /* since we are recycling buffers we should seldom need to alloc */ 1592 if (likely(page)) 1593 return true; 1594 1595 /* alloc new page for storage */ 1596 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1597 if (unlikely(!page)) { 1598 rx_ring->rx_stats.alloc_rx_page_failed++; 1599 return false; 1600 } 1601 1602 /* map page for use */ 1603 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1604 ixgbe_rx_pg_size(rx_ring), 1605 DMA_FROM_DEVICE, 1606 IXGBE_RX_DMA_ATTR); 1607 1608 /* 1609 * if mapping failed free memory back to system since 1610 * there isn't much point in holding memory we can't use 1611 */ 1612 if (dma_mapping_error(rx_ring->dev, dma)) { 1613 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1614 1615 rx_ring->rx_stats.alloc_rx_page_failed++; 1616 return false; 1617 } 1618 1619 bi->dma = dma; 1620 bi->page = page; 1621 bi->page_offset = ixgbe_rx_offset(rx_ring); 1622 bi->pagecnt_bias = 1; 1623 1624 return true; 1625 } 1626 1627 /** 1628 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1629 * @rx_ring: ring to place buffers on 1630 * @cleaned_count: number of buffers to replace 1631 **/ 1632 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1633 { 1634 union ixgbe_adv_rx_desc *rx_desc; 1635 struct ixgbe_rx_buffer *bi; 1636 u16 i = rx_ring->next_to_use; 1637 u16 bufsz; 1638 1639 /* nothing to do */ 1640 if (!cleaned_count) 1641 return; 1642 1643 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1644 bi = &rx_ring->rx_buffer_info[i]; 1645 i -= rx_ring->count; 1646 1647 bufsz = ixgbe_rx_bufsz(rx_ring); 1648 1649 do { 1650 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1651 break; 1652 1653 /* sync the buffer for use by the device */ 1654 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1655 bi->page_offset, bufsz, 1656 DMA_FROM_DEVICE); 1657 1658 /* 1659 * Refresh the desc even if buffer_addrs didn't change 1660 * because each write-back erases this info. 1661 */ 1662 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1663 1664 rx_desc++; 1665 bi++; 1666 i++; 1667 if (unlikely(!i)) { 1668 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1669 bi = rx_ring->rx_buffer_info; 1670 i -= rx_ring->count; 1671 } 1672 1673 /* clear the length for the next_to_use descriptor */ 1674 rx_desc->wb.upper.length = 0; 1675 1676 cleaned_count--; 1677 } while (cleaned_count); 1678 1679 i += rx_ring->count; 1680 1681 if (rx_ring->next_to_use != i) { 1682 rx_ring->next_to_use = i; 1683 1684 /* update next to alloc since we have filled the ring */ 1685 rx_ring->next_to_alloc = i; 1686 1687 /* Force memory writes to complete before letting h/w 1688 * know there are new descriptors to fetch. (Only 1689 * applicable for weak-ordered memory model archs, 1690 * such as IA-64). 1691 */ 1692 wmb(); 1693 writel(i, rx_ring->tail); 1694 } 1695 } 1696 1697 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1698 struct sk_buff *skb) 1699 { 1700 u16 hdr_len = skb_headlen(skb); 1701 1702 /* set gso_size to avoid messing up TCP MSS */ 1703 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1704 IXGBE_CB(skb)->append_cnt); 1705 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1706 } 1707 1708 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1709 struct sk_buff *skb) 1710 { 1711 /* if append_cnt is 0 then frame is not RSC */ 1712 if (!IXGBE_CB(skb)->append_cnt) 1713 return; 1714 1715 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1716 rx_ring->rx_stats.rsc_flush++; 1717 1718 ixgbe_set_rsc_gso_size(rx_ring, skb); 1719 1720 /* gso_size is computed using append_cnt so always clear it last */ 1721 IXGBE_CB(skb)->append_cnt = 0; 1722 } 1723 1724 /** 1725 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1726 * @rx_ring: rx descriptor ring packet is being transacted on 1727 * @rx_desc: pointer to the EOP Rx descriptor 1728 * @skb: pointer to current skb being populated 1729 * 1730 * This function checks the ring, descriptor, and packet information in 1731 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1732 * other fields within the skb. 1733 **/ 1734 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1735 union ixgbe_adv_rx_desc *rx_desc, 1736 struct sk_buff *skb) 1737 { 1738 struct net_device *dev = rx_ring->netdev; 1739 u32 flags = rx_ring->q_vector->adapter->flags; 1740 1741 ixgbe_update_rsc_stats(rx_ring, skb); 1742 1743 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1744 1745 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1746 1747 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1748 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1749 1750 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1751 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1752 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1753 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1754 } 1755 1756 skb_record_rx_queue(skb, rx_ring->queue_index); 1757 1758 skb->protocol = eth_type_trans(skb, dev); 1759 } 1760 1761 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1762 struct sk_buff *skb) 1763 { 1764 napi_gro_receive(&q_vector->napi, skb); 1765 } 1766 1767 /** 1768 * ixgbe_is_non_eop - process handling of non-EOP buffers 1769 * @rx_ring: Rx ring being processed 1770 * @rx_desc: Rx descriptor for current buffer 1771 * @skb: Current socket buffer containing buffer in progress 1772 * 1773 * This function updates next to clean. If the buffer is an EOP buffer 1774 * this function exits returning false, otherwise it will place the 1775 * sk_buff in the next buffer to be chained and return true indicating 1776 * that this is in fact a non-EOP buffer. 1777 **/ 1778 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1779 union ixgbe_adv_rx_desc *rx_desc, 1780 struct sk_buff *skb) 1781 { 1782 u32 ntc = rx_ring->next_to_clean + 1; 1783 1784 /* fetch, update, and store next to clean */ 1785 ntc = (ntc < rx_ring->count) ? ntc : 0; 1786 rx_ring->next_to_clean = ntc; 1787 1788 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1789 1790 /* update RSC append count if present */ 1791 if (ring_is_rsc_enabled(rx_ring)) { 1792 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1793 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1794 1795 if (unlikely(rsc_enabled)) { 1796 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1797 1798 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1799 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1800 1801 /* update ntc based on RSC value */ 1802 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1803 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1804 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1805 } 1806 } 1807 1808 /* if we are the last buffer then there is nothing else to do */ 1809 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1810 return false; 1811 1812 /* place skb in next buffer to be received */ 1813 rx_ring->rx_buffer_info[ntc].skb = skb; 1814 rx_ring->rx_stats.non_eop_descs++; 1815 1816 return true; 1817 } 1818 1819 /** 1820 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1821 * @rx_ring: rx descriptor ring packet is being transacted on 1822 * @skb: pointer to current skb being adjusted 1823 * 1824 * This function is an ixgbe specific version of __pskb_pull_tail. The 1825 * main difference between this version and the original function is that 1826 * this function can make several assumptions about the state of things 1827 * that allow for significant optimizations versus the standard function. 1828 * As a result we can do things like drop a frag and maintain an accurate 1829 * truesize for the skb. 1830 */ 1831 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1832 struct sk_buff *skb) 1833 { 1834 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1835 unsigned char *va; 1836 unsigned int pull_len; 1837 1838 /* 1839 * it is valid to use page_address instead of kmap since we are 1840 * working with pages allocated out of the lomem pool per 1841 * alloc_page(GFP_ATOMIC) 1842 */ 1843 va = skb_frag_address(frag); 1844 1845 /* 1846 * we need the header to contain the greater of either ETH_HLEN or 1847 * 60 bytes if the skb->len is less than 60 for skb_pad. 1848 */ 1849 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1850 1851 /* align pull length to size of long to optimize memcpy performance */ 1852 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1853 1854 /* update all of the pointers */ 1855 skb_frag_size_sub(frag, pull_len); 1856 frag->page_offset += pull_len; 1857 skb->data_len -= pull_len; 1858 skb->tail += pull_len; 1859 } 1860 1861 /** 1862 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1863 * @rx_ring: rx descriptor ring packet is being transacted on 1864 * @skb: pointer to current skb being updated 1865 * 1866 * This function provides a basic DMA sync up for the first fragment of an 1867 * skb. The reason for doing this is that the first fragment cannot be 1868 * unmapped until we have reached the end of packet descriptor for a buffer 1869 * chain. 1870 */ 1871 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1872 struct sk_buff *skb) 1873 { 1874 /* if the page was released unmap it, else just sync our portion */ 1875 if (unlikely(IXGBE_CB(skb)->page_released)) { 1876 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1877 ixgbe_rx_pg_size(rx_ring), 1878 DMA_FROM_DEVICE, 1879 IXGBE_RX_DMA_ATTR); 1880 } else { 1881 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1882 1883 dma_sync_single_range_for_cpu(rx_ring->dev, 1884 IXGBE_CB(skb)->dma, 1885 frag->page_offset, 1886 skb_frag_size(frag), 1887 DMA_FROM_DEVICE); 1888 } 1889 } 1890 1891 /** 1892 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1893 * @rx_ring: rx descriptor ring packet is being transacted on 1894 * @rx_desc: pointer to the EOP Rx descriptor 1895 * @skb: pointer to current skb being fixed 1896 * 1897 * Check if the skb is valid in the XDP case it will be an error pointer. 1898 * Return true in this case to abort processing and advance to next 1899 * descriptor. 1900 * 1901 * Check for corrupted packet headers caused by senders on the local L2 1902 * embedded NIC switch not setting up their Tx Descriptors right. These 1903 * should be very rare. 1904 * 1905 * Also address the case where we are pulling data in on pages only 1906 * and as such no data is present in the skb header. 1907 * 1908 * In addition if skb is not at least 60 bytes we need to pad it so that 1909 * it is large enough to qualify as a valid Ethernet frame. 1910 * 1911 * Returns true if an error was encountered and skb was freed. 1912 **/ 1913 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1914 union ixgbe_adv_rx_desc *rx_desc, 1915 struct sk_buff *skb) 1916 { 1917 struct net_device *netdev = rx_ring->netdev; 1918 1919 /* XDP packets use error pointer so abort at this point */ 1920 if (IS_ERR(skb)) 1921 return true; 1922 1923 /* verify that the packet does not have any known errors */ 1924 if (unlikely(ixgbe_test_staterr(rx_desc, 1925 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1926 !(netdev->features & NETIF_F_RXALL))) { 1927 dev_kfree_skb_any(skb); 1928 return true; 1929 } 1930 1931 /* place header in linear portion of buffer */ 1932 if (!skb_headlen(skb)) 1933 ixgbe_pull_tail(rx_ring, skb); 1934 1935 #ifdef IXGBE_FCOE 1936 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1937 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1938 return false; 1939 1940 #endif 1941 /* if eth_skb_pad returns an error the skb was freed */ 1942 if (eth_skb_pad(skb)) 1943 return true; 1944 1945 return false; 1946 } 1947 1948 /** 1949 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1950 * @rx_ring: rx descriptor ring to store buffers on 1951 * @old_buff: donor buffer to have page reused 1952 * 1953 * Synchronizes page for reuse by the adapter 1954 **/ 1955 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1956 struct ixgbe_rx_buffer *old_buff) 1957 { 1958 struct ixgbe_rx_buffer *new_buff; 1959 u16 nta = rx_ring->next_to_alloc; 1960 1961 new_buff = &rx_ring->rx_buffer_info[nta]; 1962 1963 /* update, and store next to alloc */ 1964 nta++; 1965 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1966 1967 /* Transfer page from old buffer to new buffer. 1968 * Move each member individually to avoid possible store 1969 * forwarding stalls and unnecessary copy of skb. 1970 */ 1971 new_buff->dma = old_buff->dma; 1972 new_buff->page = old_buff->page; 1973 new_buff->page_offset = old_buff->page_offset; 1974 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1975 } 1976 1977 static inline bool ixgbe_page_is_reserved(struct page *page) 1978 { 1979 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1980 } 1981 1982 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1983 { 1984 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1985 struct page *page = rx_buffer->page; 1986 1987 /* avoid re-using remote pages */ 1988 if (unlikely(ixgbe_page_is_reserved(page))) 1989 return false; 1990 1991 #if (PAGE_SIZE < 8192) 1992 /* if we are only owner of page we can reuse it */ 1993 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1994 return false; 1995 #else 1996 /* The last offset is a bit aggressive in that we assume the 1997 * worst case of FCoE being enabled and using a 3K buffer. 1998 * However this should have minimal impact as the 1K extra is 1999 * still less than one buffer in size. 2000 */ 2001 #define IXGBE_LAST_OFFSET \ 2002 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2003 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2004 return false; 2005 #endif 2006 2007 /* If we have drained the page fragment pool we need to update 2008 * the pagecnt_bias and page count so that we fully restock the 2009 * number of references the driver holds. 2010 */ 2011 if (unlikely(!pagecnt_bias)) { 2012 page_ref_add(page, USHRT_MAX); 2013 rx_buffer->pagecnt_bias = USHRT_MAX; 2014 } 2015 2016 return true; 2017 } 2018 2019 /** 2020 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2021 * @rx_ring: rx descriptor ring to transact packets on 2022 * @rx_buffer: buffer containing page to add 2023 * @rx_desc: descriptor containing length of buffer written by hardware 2024 * @skb: sk_buff to place the data into 2025 * 2026 * This function will add the data contained in rx_buffer->page to the skb. 2027 * This is done either through a direct copy if the data in the buffer is 2028 * less than the skb header size, otherwise it will just attach the page as 2029 * a frag to the skb. 2030 * 2031 * The function will then update the page offset if necessary and return 2032 * true if the buffer can be reused by the adapter. 2033 **/ 2034 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2035 struct ixgbe_rx_buffer *rx_buffer, 2036 struct sk_buff *skb, 2037 unsigned int size) 2038 { 2039 #if (PAGE_SIZE < 8192) 2040 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2041 #else 2042 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2043 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2044 SKB_DATA_ALIGN(size); 2045 #endif 2046 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2047 rx_buffer->page_offset, size, truesize); 2048 #if (PAGE_SIZE < 8192) 2049 rx_buffer->page_offset ^= truesize; 2050 #else 2051 rx_buffer->page_offset += truesize; 2052 #endif 2053 } 2054 2055 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2056 union ixgbe_adv_rx_desc *rx_desc, 2057 struct sk_buff **skb, 2058 const unsigned int size) 2059 { 2060 struct ixgbe_rx_buffer *rx_buffer; 2061 2062 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2063 prefetchw(rx_buffer->page); 2064 *skb = rx_buffer->skb; 2065 2066 /* Delay unmapping of the first packet. It carries the header 2067 * information, HW may still access the header after the writeback. 2068 * Only unmap it when EOP is reached 2069 */ 2070 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2071 if (!*skb) 2072 goto skip_sync; 2073 } else { 2074 if (*skb) 2075 ixgbe_dma_sync_frag(rx_ring, *skb); 2076 } 2077 2078 /* we are reusing so sync this buffer for CPU use */ 2079 dma_sync_single_range_for_cpu(rx_ring->dev, 2080 rx_buffer->dma, 2081 rx_buffer->page_offset, 2082 size, 2083 DMA_FROM_DEVICE); 2084 skip_sync: 2085 rx_buffer->pagecnt_bias--; 2086 2087 return rx_buffer; 2088 } 2089 2090 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2091 struct ixgbe_rx_buffer *rx_buffer, 2092 struct sk_buff *skb) 2093 { 2094 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2095 /* hand second half of page back to the ring */ 2096 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2097 } else { 2098 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2099 /* the page has been released from the ring */ 2100 IXGBE_CB(skb)->page_released = true; 2101 } else { 2102 /* we are not reusing the buffer so unmap it */ 2103 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2104 ixgbe_rx_pg_size(rx_ring), 2105 DMA_FROM_DEVICE, 2106 IXGBE_RX_DMA_ATTR); 2107 } 2108 __page_frag_cache_drain(rx_buffer->page, 2109 rx_buffer->pagecnt_bias); 2110 } 2111 2112 /* clear contents of rx_buffer */ 2113 rx_buffer->page = NULL; 2114 rx_buffer->skb = NULL; 2115 } 2116 2117 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2118 struct ixgbe_rx_buffer *rx_buffer, 2119 struct xdp_buff *xdp, 2120 union ixgbe_adv_rx_desc *rx_desc) 2121 { 2122 unsigned int size = xdp->data_end - xdp->data; 2123 #if (PAGE_SIZE < 8192) 2124 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2125 #else 2126 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2127 xdp->data_hard_start); 2128 #endif 2129 struct sk_buff *skb; 2130 2131 /* prefetch first cache line of first page */ 2132 prefetch(xdp->data); 2133 #if L1_CACHE_BYTES < 128 2134 prefetch(xdp->data + L1_CACHE_BYTES); 2135 #endif 2136 /* Note, we get here by enabling legacy-rx via: 2137 * 2138 * ethtool --set-priv-flags <dev> legacy-rx on 2139 * 2140 * In this mode, we currently get 0 extra XDP headroom as 2141 * opposed to having legacy-rx off, where we process XDP 2142 * packets going to stack via ixgbe_build_skb(). The latter 2143 * provides us currently with 192 bytes of headroom. 2144 * 2145 * For ixgbe_construct_skb() mode it means that the 2146 * xdp->data_meta will always point to xdp->data, since 2147 * the helper cannot expand the head. Should this ever 2148 * change in future for legacy-rx mode on, then lets also 2149 * add xdp->data_meta handling here. 2150 */ 2151 2152 /* allocate a skb to store the frags */ 2153 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2154 if (unlikely(!skb)) 2155 return NULL; 2156 2157 if (size > IXGBE_RX_HDR_SIZE) { 2158 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2159 IXGBE_CB(skb)->dma = rx_buffer->dma; 2160 2161 skb_add_rx_frag(skb, 0, rx_buffer->page, 2162 xdp->data - page_address(rx_buffer->page), 2163 size, truesize); 2164 #if (PAGE_SIZE < 8192) 2165 rx_buffer->page_offset ^= truesize; 2166 #else 2167 rx_buffer->page_offset += truesize; 2168 #endif 2169 } else { 2170 memcpy(__skb_put(skb, size), 2171 xdp->data, ALIGN(size, sizeof(long))); 2172 rx_buffer->pagecnt_bias++; 2173 } 2174 2175 return skb; 2176 } 2177 2178 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2179 struct ixgbe_rx_buffer *rx_buffer, 2180 struct xdp_buff *xdp, 2181 union ixgbe_adv_rx_desc *rx_desc) 2182 { 2183 unsigned int metasize = xdp->data - xdp->data_meta; 2184 #if (PAGE_SIZE < 8192) 2185 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2186 #else 2187 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2188 SKB_DATA_ALIGN(xdp->data_end - 2189 xdp->data_hard_start); 2190 #endif 2191 struct sk_buff *skb; 2192 2193 /* Prefetch first cache line of first page. If xdp->data_meta 2194 * is unused, this points extactly as xdp->data, otherwise we 2195 * likely have a consumer accessing first few bytes of meta 2196 * data, and then actual data. 2197 */ 2198 prefetch(xdp->data_meta); 2199 #if L1_CACHE_BYTES < 128 2200 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2201 #endif 2202 2203 /* build an skb to around the page buffer */ 2204 skb = build_skb(xdp->data_hard_start, truesize); 2205 if (unlikely(!skb)) 2206 return NULL; 2207 2208 /* update pointers within the skb to store the data */ 2209 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2210 __skb_put(skb, xdp->data_end - xdp->data); 2211 if (metasize) 2212 skb_metadata_set(skb, metasize); 2213 2214 /* record DMA address if this is the start of a chain of buffers */ 2215 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2216 IXGBE_CB(skb)->dma = rx_buffer->dma; 2217 2218 /* update buffer offset */ 2219 #if (PAGE_SIZE < 8192) 2220 rx_buffer->page_offset ^= truesize; 2221 #else 2222 rx_buffer->page_offset += truesize; 2223 #endif 2224 2225 return skb; 2226 } 2227 2228 #define IXGBE_XDP_PASS 0 2229 #define IXGBE_XDP_CONSUMED 1 2230 #define IXGBE_XDP_TX 2 2231 2232 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2233 struct xdp_buff *xdp); 2234 2235 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2236 struct ixgbe_ring *rx_ring, 2237 struct xdp_buff *xdp) 2238 { 2239 int err, result = IXGBE_XDP_PASS; 2240 struct bpf_prog *xdp_prog; 2241 u32 act; 2242 2243 rcu_read_lock(); 2244 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2245 2246 if (!xdp_prog) 2247 goto xdp_out; 2248 2249 act = bpf_prog_run_xdp(xdp_prog, xdp); 2250 switch (act) { 2251 case XDP_PASS: 2252 break; 2253 case XDP_TX: 2254 result = ixgbe_xmit_xdp_ring(adapter, xdp); 2255 break; 2256 case XDP_REDIRECT: 2257 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2258 if (!err) 2259 result = IXGBE_XDP_TX; 2260 else 2261 result = IXGBE_XDP_CONSUMED; 2262 break; 2263 default: 2264 bpf_warn_invalid_xdp_action(act); 2265 /* fallthrough */ 2266 case XDP_ABORTED: 2267 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2268 /* fallthrough -- handle aborts by dropping packet */ 2269 case XDP_DROP: 2270 result = IXGBE_XDP_CONSUMED; 2271 break; 2272 } 2273 xdp_out: 2274 rcu_read_unlock(); 2275 return ERR_PTR(-result); 2276 } 2277 2278 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2279 struct ixgbe_rx_buffer *rx_buffer, 2280 unsigned int size) 2281 { 2282 #if (PAGE_SIZE < 8192) 2283 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2284 2285 rx_buffer->page_offset ^= truesize; 2286 #else 2287 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2288 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2289 SKB_DATA_ALIGN(size); 2290 2291 rx_buffer->page_offset += truesize; 2292 #endif 2293 } 2294 2295 /** 2296 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2297 * @q_vector: structure containing interrupt and ring information 2298 * @rx_ring: rx descriptor ring to transact packets on 2299 * @budget: Total limit on number of packets to process 2300 * 2301 * This function provides a "bounce buffer" approach to Rx interrupt 2302 * processing. The advantage to this is that on systems that have 2303 * expensive overhead for IOMMU access this provides a means of avoiding 2304 * it by maintaining the mapping of the page to the syste. 2305 * 2306 * Returns amount of work completed 2307 **/ 2308 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2309 struct ixgbe_ring *rx_ring, 2310 const int budget) 2311 { 2312 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2313 struct ixgbe_adapter *adapter = q_vector->adapter; 2314 #ifdef IXGBE_FCOE 2315 int ddp_bytes; 2316 unsigned int mss = 0; 2317 #endif /* IXGBE_FCOE */ 2318 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2319 bool xdp_xmit = false; 2320 2321 while (likely(total_rx_packets < budget)) { 2322 union ixgbe_adv_rx_desc *rx_desc; 2323 struct ixgbe_rx_buffer *rx_buffer; 2324 struct sk_buff *skb; 2325 struct xdp_buff xdp; 2326 unsigned int size; 2327 2328 /* return some buffers to hardware, one at a time is too slow */ 2329 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2330 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2331 cleaned_count = 0; 2332 } 2333 2334 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2335 size = le16_to_cpu(rx_desc->wb.upper.length); 2336 if (!size) 2337 break; 2338 2339 /* This memory barrier is needed to keep us from reading 2340 * any other fields out of the rx_desc until we know the 2341 * descriptor has been written back 2342 */ 2343 dma_rmb(); 2344 2345 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2346 2347 /* retrieve a buffer from the ring */ 2348 if (!skb) { 2349 xdp.data = page_address(rx_buffer->page) + 2350 rx_buffer->page_offset; 2351 xdp.data_meta = xdp.data; 2352 xdp.data_hard_start = xdp.data - 2353 ixgbe_rx_offset(rx_ring); 2354 xdp.data_end = xdp.data + size; 2355 2356 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2357 } 2358 2359 if (IS_ERR(skb)) { 2360 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2361 xdp_xmit = true; 2362 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2363 } else { 2364 rx_buffer->pagecnt_bias++; 2365 } 2366 total_rx_packets++; 2367 total_rx_bytes += size; 2368 } else if (skb) { 2369 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2370 } else if (ring_uses_build_skb(rx_ring)) { 2371 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2372 &xdp, rx_desc); 2373 } else { 2374 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2375 &xdp, rx_desc); 2376 } 2377 2378 /* exit if we failed to retrieve a buffer */ 2379 if (!skb) { 2380 rx_ring->rx_stats.alloc_rx_buff_failed++; 2381 rx_buffer->pagecnt_bias++; 2382 break; 2383 } 2384 2385 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2386 cleaned_count++; 2387 2388 /* place incomplete frames back on ring for completion */ 2389 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2390 continue; 2391 2392 /* verify the packet layout is correct */ 2393 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2394 continue; 2395 2396 /* probably a little skewed due to removing CRC */ 2397 total_rx_bytes += skb->len; 2398 2399 /* populate checksum, timestamp, VLAN, and protocol */ 2400 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2401 2402 #ifdef IXGBE_FCOE 2403 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2404 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2405 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2406 /* include DDPed FCoE data */ 2407 if (ddp_bytes > 0) { 2408 if (!mss) { 2409 mss = rx_ring->netdev->mtu - 2410 sizeof(struct fcoe_hdr) - 2411 sizeof(struct fc_frame_header) - 2412 sizeof(struct fcoe_crc_eof); 2413 if (mss > 512) 2414 mss &= ~511; 2415 } 2416 total_rx_bytes += ddp_bytes; 2417 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2418 mss); 2419 } 2420 if (!ddp_bytes) { 2421 dev_kfree_skb_any(skb); 2422 continue; 2423 } 2424 } 2425 2426 #endif /* IXGBE_FCOE */ 2427 ixgbe_rx_skb(q_vector, skb); 2428 2429 /* update budget accounting */ 2430 total_rx_packets++; 2431 } 2432 2433 if (xdp_xmit) { 2434 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2435 2436 /* Force memory writes to complete before letting h/w 2437 * know there are new descriptors to fetch. 2438 */ 2439 wmb(); 2440 writel(ring->next_to_use, ring->tail); 2441 2442 xdp_do_flush_map(); 2443 } 2444 2445 u64_stats_update_begin(&rx_ring->syncp); 2446 rx_ring->stats.packets += total_rx_packets; 2447 rx_ring->stats.bytes += total_rx_bytes; 2448 u64_stats_update_end(&rx_ring->syncp); 2449 q_vector->rx.total_packets += total_rx_packets; 2450 q_vector->rx.total_bytes += total_rx_bytes; 2451 2452 return total_rx_packets; 2453 } 2454 2455 /** 2456 * ixgbe_configure_msix - Configure MSI-X hardware 2457 * @adapter: board private structure 2458 * 2459 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2460 * interrupts. 2461 **/ 2462 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2463 { 2464 struct ixgbe_q_vector *q_vector; 2465 int v_idx; 2466 u32 mask; 2467 2468 /* Populate MSIX to EITR Select */ 2469 if (adapter->num_vfs > 32) { 2470 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2472 } 2473 2474 /* 2475 * Populate the IVAR table and set the ITR values to the 2476 * corresponding register. 2477 */ 2478 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2479 struct ixgbe_ring *ring; 2480 q_vector = adapter->q_vector[v_idx]; 2481 2482 ixgbe_for_each_ring(ring, q_vector->rx) 2483 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2484 2485 ixgbe_for_each_ring(ring, q_vector->tx) 2486 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2487 2488 ixgbe_write_eitr(q_vector); 2489 } 2490 2491 switch (adapter->hw.mac.type) { 2492 case ixgbe_mac_82598EB: 2493 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2494 v_idx); 2495 break; 2496 case ixgbe_mac_82599EB: 2497 case ixgbe_mac_X540: 2498 case ixgbe_mac_X550: 2499 case ixgbe_mac_X550EM_x: 2500 case ixgbe_mac_x550em_a: 2501 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2502 break; 2503 default: 2504 break; 2505 } 2506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2507 2508 /* set up to autoclear timer, and the vectors */ 2509 mask = IXGBE_EIMS_ENABLE_MASK; 2510 mask &= ~(IXGBE_EIMS_OTHER | 2511 IXGBE_EIMS_MAILBOX | 2512 IXGBE_EIMS_LSC); 2513 2514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2515 } 2516 2517 enum latency_range { 2518 lowest_latency = 0, 2519 low_latency = 1, 2520 bulk_latency = 2, 2521 latency_invalid = 255 2522 }; 2523 2524 /** 2525 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2526 * @q_vector: structure containing interrupt and ring information 2527 * @ring_container: structure containing ring performance data 2528 * 2529 * Stores a new ITR value based on packets and byte 2530 * counts during the last interrupt. The advantage of per interrupt 2531 * computation is faster updates and more accurate ITR for the current 2532 * traffic pattern. Constants in this function were computed 2533 * based on theoretical maximum wire speed and thresholds were set based 2534 * on testing data as well as attempting to minimize response time 2535 * while increasing bulk throughput. 2536 * this functionality is controlled by the InterruptThrottleRate module 2537 * parameter (see ixgbe_param.c) 2538 **/ 2539 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2540 struct ixgbe_ring_container *ring_container) 2541 { 2542 int bytes = ring_container->total_bytes; 2543 int packets = ring_container->total_packets; 2544 u32 timepassed_us; 2545 u64 bytes_perint; 2546 u8 itr_setting = ring_container->itr; 2547 2548 if (packets == 0) 2549 return; 2550 2551 /* simple throttlerate management 2552 * 0-10MB/s lowest (100000 ints/s) 2553 * 10-20MB/s low (20000 ints/s) 2554 * 20-1249MB/s bulk (12000 ints/s) 2555 */ 2556 /* what was last interrupt timeslice? */ 2557 timepassed_us = q_vector->itr >> 2; 2558 if (timepassed_us == 0) 2559 return; 2560 2561 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2562 2563 switch (itr_setting) { 2564 case lowest_latency: 2565 if (bytes_perint > 10) 2566 itr_setting = low_latency; 2567 break; 2568 case low_latency: 2569 if (bytes_perint > 20) 2570 itr_setting = bulk_latency; 2571 else if (bytes_perint <= 10) 2572 itr_setting = lowest_latency; 2573 break; 2574 case bulk_latency: 2575 if (bytes_perint <= 20) 2576 itr_setting = low_latency; 2577 break; 2578 } 2579 2580 /* clear work counters since we have the values we need */ 2581 ring_container->total_bytes = 0; 2582 ring_container->total_packets = 0; 2583 2584 /* write updated itr to ring container */ 2585 ring_container->itr = itr_setting; 2586 } 2587 2588 /** 2589 * ixgbe_write_eitr - write EITR register in hardware specific way 2590 * @q_vector: structure containing interrupt and ring information 2591 * 2592 * This function is made to be called by ethtool and by the driver 2593 * when it needs to update EITR registers at runtime. Hardware 2594 * specific quirks/differences are taken care of here. 2595 */ 2596 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2597 { 2598 struct ixgbe_adapter *adapter = q_vector->adapter; 2599 struct ixgbe_hw *hw = &adapter->hw; 2600 int v_idx = q_vector->v_idx; 2601 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2602 2603 switch (adapter->hw.mac.type) { 2604 case ixgbe_mac_82598EB: 2605 /* must write high and low 16 bits to reset counter */ 2606 itr_reg |= (itr_reg << 16); 2607 break; 2608 case ixgbe_mac_82599EB: 2609 case ixgbe_mac_X540: 2610 case ixgbe_mac_X550: 2611 case ixgbe_mac_X550EM_x: 2612 case ixgbe_mac_x550em_a: 2613 /* 2614 * set the WDIS bit to not clear the timer bits and cause an 2615 * immediate assertion of the interrupt 2616 */ 2617 itr_reg |= IXGBE_EITR_CNT_WDIS; 2618 break; 2619 default: 2620 break; 2621 } 2622 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2623 } 2624 2625 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2626 { 2627 u32 new_itr = q_vector->itr; 2628 u8 current_itr; 2629 2630 ixgbe_update_itr(q_vector, &q_vector->tx); 2631 ixgbe_update_itr(q_vector, &q_vector->rx); 2632 2633 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2634 2635 switch (current_itr) { 2636 /* counts and packets in update_itr are dependent on these numbers */ 2637 case lowest_latency: 2638 new_itr = IXGBE_100K_ITR; 2639 break; 2640 case low_latency: 2641 new_itr = IXGBE_20K_ITR; 2642 break; 2643 case bulk_latency: 2644 new_itr = IXGBE_12K_ITR; 2645 break; 2646 default: 2647 break; 2648 } 2649 2650 if (new_itr != q_vector->itr) { 2651 /* do an exponential smoothing */ 2652 new_itr = (10 * new_itr * q_vector->itr) / 2653 ((9 * new_itr) + q_vector->itr); 2654 2655 /* save the algorithm value here */ 2656 q_vector->itr = new_itr; 2657 2658 ixgbe_write_eitr(q_vector); 2659 } 2660 } 2661 2662 /** 2663 * ixgbe_check_overtemp_subtask - check for over temperature 2664 * @adapter: pointer to adapter 2665 **/ 2666 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2667 { 2668 struct ixgbe_hw *hw = &adapter->hw; 2669 u32 eicr = adapter->interrupt_event; 2670 s32 rc; 2671 2672 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2673 return; 2674 2675 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2676 return; 2677 2678 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2679 2680 switch (hw->device_id) { 2681 case IXGBE_DEV_ID_82599_T3_LOM: 2682 /* 2683 * Since the warning interrupt is for both ports 2684 * we don't have to check if: 2685 * - This interrupt wasn't for our port. 2686 * - We may have missed the interrupt so always have to 2687 * check if we got a LSC 2688 */ 2689 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2690 !(eicr & IXGBE_EICR_LSC)) 2691 return; 2692 2693 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2694 u32 speed; 2695 bool link_up = false; 2696 2697 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2698 2699 if (link_up) 2700 return; 2701 } 2702 2703 /* Check if this is not due to overtemp */ 2704 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2705 return; 2706 2707 break; 2708 case IXGBE_DEV_ID_X550EM_A_1G_T: 2709 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2710 rc = hw->phy.ops.check_overtemp(hw); 2711 if (rc != IXGBE_ERR_OVERTEMP) 2712 return; 2713 break; 2714 default: 2715 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2716 return; 2717 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2718 return; 2719 break; 2720 } 2721 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2722 2723 adapter->interrupt_event = 0; 2724 } 2725 2726 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2727 { 2728 struct ixgbe_hw *hw = &adapter->hw; 2729 2730 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2731 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2732 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2733 /* write to clear the interrupt */ 2734 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2735 } 2736 } 2737 2738 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2739 { 2740 struct ixgbe_hw *hw = &adapter->hw; 2741 2742 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2743 return; 2744 2745 switch (adapter->hw.mac.type) { 2746 case ixgbe_mac_82599EB: 2747 /* 2748 * Need to check link state so complete overtemp check 2749 * on service task 2750 */ 2751 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2752 (eicr & IXGBE_EICR_LSC)) && 2753 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2754 adapter->interrupt_event = eicr; 2755 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2756 ixgbe_service_event_schedule(adapter); 2757 return; 2758 } 2759 return; 2760 case ixgbe_mac_x550em_a: 2761 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2762 adapter->interrupt_event = eicr; 2763 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2764 ixgbe_service_event_schedule(adapter); 2765 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2766 IXGBE_EICR_GPI_SDP0_X550EM_a); 2767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2768 IXGBE_EICR_GPI_SDP0_X550EM_a); 2769 } 2770 return; 2771 case ixgbe_mac_X550: 2772 case ixgbe_mac_X540: 2773 if (!(eicr & IXGBE_EICR_TS)) 2774 return; 2775 break; 2776 default: 2777 return; 2778 } 2779 2780 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2781 } 2782 2783 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2784 { 2785 switch (hw->mac.type) { 2786 case ixgbe_mac_82598EB: 2787 if (hw->phy.type == ixgbe_phy_nl) 2788 return true; 2789 return false; 2790 case ixgbe_mac_82599EB: 2791 case ixgbe_mac_X550EM_x: 2792 case ixgbe_mac_x550em_a: 2793 switch (hw->mac.ops.get_media_type(hw)) { 2794 case ixgbe_media_type_fiber: 2795 case ixgbe_media_type_fiber_qsfp: 2796 return true; 2797 default: 2798 return false; 2799 } 2800 default: 2801 return false; 2802 } 2803 } 2804 2805 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2806 { 2807 struct ixgbe_hw *hw = &adapter->hw; 2808 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2809 2810 if (!ixgbe_is_sfp(hw)) 2811 return; 2812 2813 /* Later MAC's use different SDP */ 2814 if (hw->mac.type >= ixgbe_mac_X540) 2815 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2816 2817 if (eicr & eicr_mask) { 2818 /* Clear the interrupt */ 2819 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2820 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2821 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2822 adapter->sfp_poll_time = 0; 2823 ixgbe_service_event_schedule(adapter); 2824 } 2825 } 2826 2827 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2828 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2829 /* Clear the interrupt */ 2830 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2831 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2832 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2833 ixgbe_service_event_schedule(adapter); 2834 } 2835 } 2836 } 2837 2838 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2839 { 2840 struct ixgbe_hw *hw = &adapter->hw; 2841 2842 adapter->lsc_int++; 2843 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2844 adapter->link_check_timeout = jiffies; 2845 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2846 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2847 IXGBE_WRITE_FLUSH(hw); 2848 ixgbe_service_event_schedule(adapter); 2849 } 2850 } 2851 2852 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2853 u64 qmask) 2854 { 2855 u32 mask; 2856 struct ixgbe_hw *hw = &adapter->hw; 2857 2858 switch (hw->mac.type) { 2859 case ixgbe_mac_82598EB: 2860 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2861 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2862 break; 2863 case ixgbe_mac_82599EB: 2864 case ixgbe_mac_X540: 2865 case ixgbe_mac_X550: 2866 case ixgbe_mac_X550EM_x: 2867 case ixgbe_mac_x550em_a: 2868 mask = (qmask & 0xFFFFFFFF); 2869 if (mask) 2870 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2871 mask = (qmask >> 32); 2872 if (mask) 2873 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2874 break; 2875 default: 2876 break; 2877 } 2878 /* skip the flush */ 2879 } 2880 2881 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2882 u64 qmask) 2883 { 2884 u32 mask; 2885 struct ixgbe_hw *hw = &adapter->hw; 2886 2887 switch (hw->mac.type) { 2888 case ixgbe_mac_82598EB: 2889 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2890 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2891 break; 2892 case ixgbe_mac_82599EB: 2893 case ixgbe_mac_X540: 2894 case ixgbe_mac_X550: 2895 case ixgbe_mac_X550EM_x: 2896 case ixgbe_mac_x550em_a: 2897 mask = (qmask & 0xFFFFFFFF); 2898 if (mask) 2899 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2900 mask = (qmask >> 32); 2901 if (mask) 2902 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2903 break; 2904 default: 2905 break; 2906 } 2907 /* skip the flush */ 2908 } 2909 2910 /** 2911 * ixgbe_irq_enable - Enable default interrupt generation settings 2912 * @adapter: board private structure 2913 **/ 2914 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2915 bool flush) 2916 { 2917 struct ixgbe_hw *hw = &adapter->hw; 2918 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2919 2920 /* don't reenable LSC while waiting for link */ 2921 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2922 mask &= ~IXGBE_EIMS_LSC; 2923 2924 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2925 switch (adapter->hw.mac.type) { 2926 case ixgbe_mac_82599EB: 2927 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2928 break; 2929 case ixgbe_mac_X540: 2930 case ixgbe_mac_X550: 2931 case ixgbe_mac_X550EM_x: 2932 case ixgbe_mac_x550em_a: 2933 mask |= IXGBE_EIMS_TS; 2934 break; 2935 default: 2936 break; 2937 } 2938 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2939 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2940 switch (adapter->hw.mac.type) { 2941 case ixgbe_mac_82599EB: 2942 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2943 mask |= IXGBE_EIMS_GPI_SDP2(hw); 2944 /* fall through */ 2945 case ixgbe_mac_X540: 2946 case ixgbe_mac_X550: 2947 case ixgbe_mac_X550EM_x: 2948 case ixgbe_mac_x550em_a: 2949 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 2950 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 2951 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 2952 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 2953 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 2954 mask |= IXGBE_EICR_GPI_SDP0_X540; 2955 mask |= IXGBE_EIMS_ECC; 2956 mask |= IXGBE_EIMS_MAILBOX; 2957 break; 2958 default: 2959 break; 2960 } 2961 2962 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2963 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2964 mask |= IXGBE_EIMS_FLOW_DIR; 2965 2966 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2967 if (queues) 2968 ixgbe_irq_enable_queues(adapter, ~0); 2969 if (flush) 2970 IXGBE_WRITE_FLUSH(&adapter->hw); 2971 } 2972 2973 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2974 { 2975 struct ixgbe_adapter *adapter = data; 2976 struct ixgbe_hw *hw = &adapter->hw; 2977 u32 eicr; 2978 2979 /* 2980 * Workaround for Silicon errata. Use clear-by-write instead 2981 * of clear-by-read. Reading with EICS will return the 2982 * interrupt causes without clearing, which later be done 2983 * with the write to EICR. 2984 */ 2985 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2986 2987 /* The lower 16bits of the EICR register are for the queue interrupts 2988 * which should be masked here in order to not accidentally clear them if 2989 * the bits are high when ixgbe_msix_other is called. There is a race 2990 * condition otherwise which results in possible performance loss 2991 * especially if the ixgbe_msix_other interrupt is triggering 2992 * consistently (as it would when PPS is turned on for the X540 device) 2993 */ 2994 eicr &= 0xFFFF0000; 2995 2996 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2997 2998 if (eicr & IXGBE_EICR_LSC) 2999 ixgbe_check_lsc(adapter); 3000 3001 if (eicr & IXGBE_EICR_MAILBOX) 3002 ixgbe_msg_task(adapter); 3003 3004 switch (hw->mac.type) { 3005 case ixgbe_mac_82599EB: 3006 case ixgbe_mac_X540: 3007 case ixgbe_mac_X550: 3008 case ixgbe_mac_X550EM_x: 3009 case ixgbe_mac_x550em_a: 3010 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3011 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3012 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3013 ixgbe_service_event_schedule(adapter); 3014 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3015 IXGBE_EICR_GPI_SDP0_X540); 3016 } 3017 if (eicr & IXGBE_EICR_ECC) { 3018 e_info(link, "Received ECC Err, initiating reset\n"); 3019 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3020 ixgbe_service_event_schedule(adapter); 3021 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3022 } 3023 /* Handle Flow Director Full threshold interrupt */ 3024 if (eicr & IXGBE_EICR_FLOW_DIR) { 3025 int reinit_count = 0; 3026 int i; 3027 for (i = 0; i < adapter->num_tx_queues; i++) { 3028 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3029 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3030 &ring->state)) 3031 reinit_count++; 3032 } 3033 if (reinit_count) { 3034 /* no more flow director interrupts until after init */ 3035 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3036 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3037 ixgbe_service_event_schedule(adapter); 3038 } 3039 } 3040 ixgbe_check_sfp_event(adapter, eicr); 3041 ixgbe_check_overtemp_event(adapter, eicr); 3042 break; 3043 default: 3044 break; 3045 } 3046 3047 ixgbe_check_fan_failure(adapter, eicr); 3048 3049 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3050 ixgbe_ptp_check_pps_event(adapter); 3051 3052 /* re-enable the original interrupt state, no lsc, no queues */ 3053 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3054 ixgbe_irq_enable(adapter, false, false); 3055 3056 return IRQ_HANDLED; 3057 } 3058 3059 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3060 { 3061 struct ixgbe_q_vector *q_vector = data; 3062 3063 /* EIAM disabled interrupts (on this vector) for us */ 3064 3065 if (q_vector->rx.ring || q_vector->tx.ring) 3066 napi_schedule_irqoff(&q_vector->napi); 3067 3068 return IRQ_HANDLED; 3069 } 3070 3071 /** 3072 * ixgbe_poll - NAPI Rx polling callback 3073 * @napi: structure for representing this polling device 3074 * @budget: how many packets driver is allowed to clean 3075 * 3076 * This function is used for legacy and MSI, NAPI mode 3077 **/ 3078 int ixgbe_poll(struct napi_struct *napi, int budget) 3079 { 3080 struct ixgbe_q_vector *q_vector = 3081 container_of(napi, struct ixgbe_q_vector, napi); 3082 struct ixgbe_adapter *adapter = q_vector->adapter; 3083 struct ixgbe_ring *ring; 3084 int per_ring_budget, work_done = 0; 3085 bool clean_complete = true; 3086 3087 #ifdef CONFIG_IXGBE_DCA 3088 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3089 ixgbe_update_dca(q_vector); 3090 #endif 3091 3092 ixgbe_for_each_ring(ring, q_vector->tx) { 3093 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3094 clean_complete = false; 3095 } 3096 3097 /* Exit if we are called by netpoll */ 3098 if (budget <= 0) 3099 return budget; 3100 3101 /* attempt to distribute budget to each queue fairly, but don't allow 3102 * the budget to go below 1 because we'll exit polling */ 3103 if (q_vector->rx.count > 1) 3104 per_ring_budget = max(budget/q_vector->rx.count, 1); 3105 else 3106 per_ring_budget = budget; 3107 3108 ixgbe_for_each_ring(ring, q_vector->rx) { 3109 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3110 per_ring_budget); 3111 3112 work_done += cleaned; 3113 if (cleaned >= per_ring_budget) 3114 clean_complete = false; 3115 } 3116 3117 /* If all work not completed, return budget and keep polling */ 3118 if (!clean_complete) 3119 return budget; 3120 3121 /* all work done, exit the polling mode */ 3122 napi_complete_done(napi, work_done); 3123 if (adapter->rx_itr_setting & 1) 3124 ixgbe_set_itr(q_vector); 3125 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3126 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3127 3128 return min(work_done, budget - 1); 3129 } 3130 3131 /** 3132 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3133 * @adapter: board private structure 3134 * 3135 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3136 * interrupts from the kernel. 3137 **/ 3138 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3139 { 3140 struct net_device *netdev = adapter->netdev; 3141 unsigned int ri = 0, ti = 0; 3142 int vector, err; 3143 3144 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3145 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3146 struct msix_entry *entry = &adapter->msix_entries[vector]; 3147 3148 if (q_vector->tx.ring && q_vector->rx.ring) { 3149 snprintf(q_vector->name, sizeof(q_vector->name), 3150 "%s-TxRx-%u", netdev->name, ri++); 3151 ti++; 3152 } else if (q_vector->rx.ring) { 3153 snprintf(q_vector->name, sizeof(q_vector->name), 3154 "%s-rx-%u", netdev->name, ri++); 3155 } else if (q_vector->tx.ring) { 3156 snprintf(q_vector->name, sizeof(q_vector->name), 3157 "%s-tx-%u", netdev->name, ti++); 3158 } else { 3159 /* skip this unused q_vector */ 3160 continue; 3161 } 3162 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3163 q_vector->name, q_vector); 3164 if (err) { 3165 e_err(probe, "request_irq failed for MSIX interrupt " 3166 "Error: %d\n", err); 3167 goto free_queue_irqs; 3168 } 3169 /* If Flow Director is enabled, set interrupt affinity */ 3170 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3171 /* assign the mask for this irq */ 3172 irq_set_affinity_hint(entry->vector, 3173 &q_vector->affinity_mask); 3174 } 3175 } 3176 3177 err = request_irq(adapter->msix_entries[vector].vector, 3178 ixgbe_msix_other, 0, netdev->name, adapter); 3179 if (err) { 3180 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3181 goto free_queue_irqs; 3182 } 3183 3184 return 0; 3185 3186 free_queue_irqs: 3187 while (vector) { 3188 vector--; 3189 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3190 NULL); 3191 free_irq(adapter->msix_entries[vector].vector, 3192 adapter->q_vector[vector]); 3193 } 3194 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3195 pci_disable_msix(adapter->pdev); 3196 kfree(adapter->msix_entries); 3197 adapter->msix_entries = NULL; 3198 return err; 3199 } 3200 3201 /** 3202 * ixgbe_intr - legacy mode Interrupt Handler 3203 * @irq: interrupt number 3204 * @data: pointer to a network interface device structure 3205 **/ 3206 static irqreturn_t ixgbe_intr(int irq, void *data) 3207 { 3208 struct ixgbe_adapter *adapter = data; 3209 struct ixgbe_hw *hw = &adapter->hw; 3210 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3211 u32 eicr; 3212 3213 /* 3214 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3215 * before the read of EICR. 3216 */ 3217 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3218 3219 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3220 * therefore no explicit interrupt disable is necessary */ 3221 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3222 if (!eicr) { 3223 /* 3224 * shared interrupt alert! 3225 * make sure interrupts are enabled because the read will 3226 * have disabled interrupts due to EIAM 3227 * finish the workaround of silicon errata on 82598. Unmask 3228 * the interrupt that we masked before the EICR read. 3229 */ 3230 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3231 ixgbe_irq_enable(adapter, true, true); 3232 return IRQ_NONE; /* Not our interrupt */ 3233 } 3234 3235 if (eicr & IXGBE_EICR_LSC) 3236 ixgbe_check_lsc(adapter); 3237 3238 switch (hw->mac.type) { 3239 case ixgbe_mac_82599EB: 3240 ixgbe_check_sfp_event(adapter, eicr); 3241 /* Fall through */ 3242 case ixgbe_mac_X540: 3243 case ixgbe_mac_X550: 3244 case ixgbe_mac_X550EM_x: 3245 case ixgbe_mac_x550em_a: 3246 if (eicr & IXGBE_EICR_ECC) { 3247 e_info(link, "Received ECC Err, initiating reset\n"); 3248 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3249 ixgbe_service_event_schedule(adapter); 3250 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3251 } 3252 ixgbe_check_overtemp_event(adapter, eicr); 3253 break; 3254 default: 3255 break; 3256 } 3257 3258 ixgbe_check_fan_failure(adapter, eicr); 3259 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3260 ixgbe_ptp_check_pps_event(adapter); 3261 3262 /* would disable interrupts here but EIAM disabled it */ 3263 napi_schedule_irqoff(&q_vector->napi); 3264 3265 /* 3266 * re-enable link(maybe) and non-queue interrupts, no flush. 3267 * ixgbe_poll will re-enable the queue interrupts 3268 */ 3269 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3270 ixgbe_irq_enable(adapter, false, false); 3271 3272 return IRQ_HANDLED; 3273 } 3274 3275 /** 3276 * ixgbe_request_irq - initialize interrupts 3277 * @adapter: board private structure 3278 * 3279 * Attempts to configure interrupts using the best available 3280 * capabilities of the hardware and kernel. 3281 **/ 3282 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3283 { 3284 struct net_device *netdev = adapter->netdev; 3285 int err; 3286 3287 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3288 err = ixgbe_request_msix_irqs(adapter); 3289 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3290 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3291 netdev->name, adapter); 3292 else 3293 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3294 netdev->name, adapter); 3295 3296 if (err) 3297 e_err(probe, "request_irq failed, Error %d\n", err); 3298 3299 return err; 3300 } 3301 3302 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3303 { 3304 int vector; 3305 3306 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3307 free_irq(adapter->pdev->irq, adapter); 3308 return; 3309 } 3310 3311 if (!adapter->msix_entries) 3312 return; 3313 3314 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3315 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3316 struct msix_entry *entry = &adapter->msix_entries[vector]; 3317 3318 /* free only the irqs that were actually requested */ 3319 if (!q_vector->rx.ring && !q_vector->tx.ring) 3320 continue; 3321 3322 /* clear the affinity_mask in the IRQ descriptor */ 3323 irq_set_affinity_hint(entry->vector, NULL); 3324 3325 free_irq(entry->vector, q_vector); 3326 } 3327 3328 free_irq(adapter->msix_entries[vector].vector, adapter); 3329 } 3330 3331 /** 3332 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3333 * @adapter: board private structure 3334 **/ 3335 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3336 { 3337 switch (adapter->hw.mac.type) { 3338 case ixgbe_mac_82598EB: 3339 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3340 break; 3341 case ixgbe_mac_82599EB: 3342 case ixgbe_mac_X540: 3343 case ixgbe_mac_X550: 3344 case ixgbe_mac_X550EM_x: 3345 case ixgbe_mac_x550em_a: 3346 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3347 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3348 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3349 break; 3350 default: 3351 break; 3352 } 3353 IXGBE_WRITE_FLUSH(&adapter->hw); 3354 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3355 int vector; 3356 3357 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3358 synchronize_irq(adapter->msix_entries[vector].vector); 3359 3360 synchronize_irq(adapter->msix_entries[vector++].vector); 3361 } else { 3362 synchronize_irq(adapter->pdev->irq); 3363 } 3364 } 3365 3366 /** 3367 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3368 * 3369 **/ 3370 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3371 { 3372 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3373 3374 ixgbe_write_eitr(q_vector); 3375 3376 ixgbe_set_ivar(adapter, 0, 0, 0); 3377 ixgbe_set_ivar(adapter, 1, 0, 0); 3378 3379 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3380 } 3381 3382 /** 3383 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3384 * @adapter: board private structure 3385 * @ring: structure containing ring specific data 3386 * 3387 * Configure the Tx descriptor ring after a reset. 3388 **/ 3389 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3390 struct ixgbe_ring *ring) 3391 { 3392 struct ixgbe_hw *hw = &adapter->hw; 3393 u64 tdba = ring->dma; 3394 int wait_loop = 10; 3395 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3396 u8 reg_idx = ring->reg_idx; 3397 3398 /* disable queue to avoid issues while updating state */ 3399 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3400 IXGBE_WRITE_FLUSH(hw); 3401 3402 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3403 (tdba & DMA_BIT_MASK(32))); 3404 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3405 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3406 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3407 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3408 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3409 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3410 3411 /* 3412 * set WTHRESH to encourage burst writeback, it should not be set 3413 * higher than 1 when: 3414 * - ITR is 0 as it could cause false TX hangs 3415 * - ITR is set to > 100k int/sec and BQL is enabled 3416 * 3417 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3418 * to or less than the number of on chip descriptors, which is 3419 * currently 40. 3420 */ 3421 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3422 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3423 else 3424 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3425 3426 /* 3427 * Setting PTHRESH to 32 both improves performance 3428 * and avoids a TX hang with DFP enabled 3429 */ 3430 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3431 32; /* PTHRESH = 32 */ 3432 3433 /* reinitialize flowdirector state */ 3434 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3435 ring->atr_sample_rate = adapter->atr_sample_rate; 3436 ring->atr_count = 0; 3437 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3438 } else { 3439 ring->atr_sample_rate = 0; 3440 } 3441 3442 /* initialize XPS */ 3443 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3444 struct ixgbe_q_vector *q_vector = ring->q_vector; 3445 3446 if (q_vector) 3447 netif_set_xps_queue(ring->netdev, 3448 &q_vector->affinity_mask, 3449 ring->queue_index); 3450 } 3451 3452 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3453 3454 /* reinitialize tx_buffer_info */ 3455 memset(ring->tx_buffer_info, 0, 3456 sizeof(struct ixgbe_tx_buffer) * ring->count); 3457 3458 /* enable queue */ 3459 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3460 3461 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3462 if (hw->mac.type == ixgbe_mac_82598EB && 3463 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3464 return; 3465 3466 /* poll to verify queue is enabled */ 3467 do { 3468 usleep_range(1000, 2000); 3469 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3470 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3471 if (!wait_loop) 3472 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3473 } 3474 3475 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3476 { 3477 struct ixgbe_hw *hw = &adapter->hw; 3478 u32 rttdcs, mtqc; 3479 u8 tcs = netdev_get_num_tc(adapter->netdev); 3480 3481 if (hw->mac.type == ixgbe_mac_82598EB) 3482 return; 3483 3484 /* disable the arbiter while setting MTQC */ 3485 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3486 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3487 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3488 3489 /* set transmit pool layout */ 3490 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3491 mtqc = IXGBE_MTQC_VT_ENA; 3492 if (tcs > 4) 3493 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3494 else if (tcs > 1) 3495 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3496 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3497 IXGBE_82599_VMDQ_4Q_MASK) 3498 mtqc |= IXGBE_MTQC_32VF; 3499 else 3500 mtqc |= IXGBE_MTQC_64VF; 3501 } else { 3502 if (tcs > 4) 3503 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3504 else if (tcs > 1) 3505 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3506 else 3507 mtqc = IXGBE_MTQC_64Q_1PB; 3508 } 3509 3510 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3511 3512 /* Enable Security TX Buffer IFG for multiple pb */ 3513 if (tcs) { 3514 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3515 sectx |= IXGBE_SECTX_DCB; 3516 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3517 } 3518 3519 /* re-enable the arbiter */ 3520 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3521 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3522 } 3523 3524 /** 3525 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3526 * @adapter: board private structure 3527 * 3528 * Configure the Tx unit of the MAC after a reset. 3529 **/ 3530 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3531 { 3532 struct ixgbe_hw *hw = &adapter->hw; 3533 u32 dmatxctl; 3534 u32 i; 3535 3536 ixgbe_setup_mtqc(adapter); 3537 3538 if (hw->mac.type != ixgbe_mac_82598EB) { 3539 /* DMATXCTL.EN must be before Tx queues are enabled */ 3540 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3541 dmatxctl |= IXGBE_DMATXCTL_TE; 3542 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3543 } 3544 3545 /* Setup the HW Tx Head and Tail descriptor pointers */ 3546 for (i = 0; i < adapter->num_tx_queues; i++) 3547 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3548 for (i = 0; i < adapter->num_xdp_queues; i++) 3549 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3550 } 3551 3552 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3553 struct ixgbe_ring *ring) 3554 { 3555 struct ixgbe_hw *hw = &adapter->hw; 3556 u8 reg_idx = ring->reg_idx; 3557 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3558 3559 srrctl |= IXGBE_SRRCTL_DROP_EN; 3560 3561 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3562 } 3563 3564 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3565 struct ixgbe_ring *ring) 3566 { 3567 struct ixgbe_hw *hw = &adapter->hw; 3568 u8 reg_idx = ring->reg_idx; 3569 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3570 3571 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3572 3573 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3574 } 3575 3576 #ifdef CONFIG_IXGBE_DCB 3577 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3578 #else 3579 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3580 #endif 3581 { 3582 int i; 3583 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3584 3585 if (adapter->ixgbe_ieee_pfc) 3586 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3587 3588 /* 3589 * We should set the drop enable bit if: 3590 * SR-IOV is enabled 3591 * or 3592 * Number of Rx queues > 1 and flow control is disabled 3593 * 3594 * This allows us to avoid head of line blocking for security 3595 * and performance reasons. 3596 */ 3597 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3598 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3599 for (i = 0; i < adapter->num_rx_queues; i++) 3600 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3601 } else { 3602 for (i = 0; i < adapter->num_rx_queues; i++) 3603 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3604 } 3605 } 3606 3607 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3608 3609 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3610 struct ixgbe_ring *rx_ring) 3611 { 3612 struct ixgbe_hw *hw = &adapter->hw; 3613 u32 srrctl; 3614 u8 reg_idx = rx_ring->reg_idx; 3615 3616 if (hw->mac.type == ixgbe_mac_82598EB) { 3617 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3618 3619 /* 3620 * if VMDq is not active we must program one srrctl register 3621 * per RSS queue since we have enabled RDRXCTL.MVMEN 3622 */ 3623 reg_idx &= mask; 3624 } 3625 3626 /* configure header buffer length, needed for RSC */ 3627 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3628 3629 /* configure the packet buffer length */ 3630 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3631 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3632 else 3633 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3634 3635 /* configure descriptor type */ 3636 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3637 3638 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3639 } 3640 3641 /** 3642 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3643 * @adapter: device handle 3644 * 3645 * - 82598/82599/X540: 128 3646 * - X550(non-SRIOV mode): 512 3647 * - X550(SRIOV mode): 64 3648 */ 3649 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3650 { 3651 if (adapter->hw.mac.type < ixgbe_mac_X550) 3652 return 128; 3653 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3654 return 64; 3655 else 3656 return 512; 3657 } 3658 3659 /** 3660 * ixgbe_store_key - Write the RSS key to HW 3661 * @adapter: device handle 3662 * 3663 * Write the RSS key stored in adapter.rss_key to HW. 3664 */ 3665 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3666 { 3667 struct ixgbe_hw *hw = &adapter->hw; 3668 int i; 3669 3670 for (i = 0; i < 10; i++) 3671 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3672 } 3673 3674 /** 3675 * ixgbe_init_rss_key - Initialize adapter RSS key 3676 * @adapter: device handle 3677 * 3678 * Allocates and initializes the RSS key if it is not allocated. 3679 **/ 3680 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3681 { 3682 u32 *rss_key; 3683 3684 if (!adapter->rss_key) { 3685 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3686 if (unlikely(!rss_key)) 3687 return -ENOMEM; 3688 3689 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3690 adapter->rss_key = rss_key; 3691 } 3692 3693 return 0; 3694 } 3695 3696 /** 3697 * ixgbe_store_reta - Write the RETA table to HW 3698 * @adapter: device handle 3699 * 3700 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3701 */ 3702 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3703 { 3704 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3705 struct ixgbe_hw *hw = &adapter->hw; 3706 u32 reta = 0; 3707 u32 indices_multi; 3708 u8 *indir_tbl = adapter->rss_indir_tbl; 3709 3710 /* Fill out the redirection table as follows: 3711 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3712 * indices. 3713 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3714 * - X550: 8 bit wide entries containing 6 bit RSS index 3715 */ 3716 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3717 indices_multi = 0x11; 3718 else 3719 indices_multi = 0x1; 3720 3721 /* Write redirection table to HW */ 3722 for (i = 0; i < reta_entries; i++) { 3723 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3724 if ((i & 3) == 3) { 3725 if (i < 128) 3726 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3727 else 3728 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3729 reta); 3730 reta = 0; 3731 } 3732 } 3733 } 3734 3735 /** 3736 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3737 * @adapter: device handle 3738 * 3739 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3740 */ 3741 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3742 { 3743 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3744 struct ixgbe_hw *hw = &adapter->hw; 3745 u32 vfreta = 0; 3746 unsigned int pf_pool = adapter->num_vfs; 3747 3748 /* Write redirection table to HW */ 3749 for (i = 0; i < reta_entries; i++) { 3750 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3751 if ((i & 3) == 3) { 3752 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3753 vfreta); 3754 vfreta = 0; 3755 } 3756 } 3757 } 3758 3759 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3760 { 3761 u32 i, j; 3762 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3763 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3764 3765 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3766 * make full use of any rings they may have. We will use the 3767 * PSRTYPE register to control how many rings we use within the PF. 3768 */ 3769 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3770 rss_i = 4; 3771 3772 /* Fill out hash function seeds */ 3773 ixgbe_store_key(adapter); 3774 3775 /* Fill out redirection table */ 3776 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3777 3778 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3779 if (j == rss_i) 3780 j = 0; 3781 3782 adapter->rss_indir_tbl[i] = j; 3783 } 3784 3785 ixgbe_store_reta(adapter); 3786 } 3787 3788 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3789 { 3790 struct ixgbe_hw *hw = &adapter->hw; 3791 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3792 unsigned int pf_pool = adapter->num_vfs; 3793 int i, j; 3794 3795 /* Fill out hash function seeds */ 3796 for (i = 0; i < 10; i++) 3797 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), 3798 *(adapter->rss_key + i)); 3799 3800 /* Fill out the redirection table */ 3801 for (i = 0, j = 0; i < 64; i++, j++) { 3802 if (j == rss_i) 3803 j = 0; 3804 3805 adapter->rss_indir_tbl[i] = j; 3806 } 3807 3808 ixgbe_store_vfreta(adapter); 3809 } 3810 3811 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3812 { 3813 struct ixgbe_hw *hw = &adapter->hw; 3814 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3815 u32 rxcsum; 3816 3817 /* Disable indicating checksum in descriptor, enables RSS hash */ 3818 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3819 rxcsum |= IXGBE_RXCSUM_PCSD; 3820 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3821 3822 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3823 if (adapter->ring_feature[RING_F_RSS].mask) 3824 mrqc = IXGBE_MRQC_RSSEN; 3825 } else { 3826 u8 tcs = netdev_get_num_tc(adapter->netdev); 3827 3828 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3829 if (tcs > 4) 3830 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3831 else if (tcs > 1) 3832 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3833 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3834 IXGBE_82599_VMDQ_4Q_MASK) 3835 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3836 else 3837 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3838 3839 /* Enable L3/L4 for Tx Switched packets */ 3840 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3841 } else { 3842 if (tcs > 4) 3843 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3844 else if (tcs > 1) 3845 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3846 else 3847 mrqc = IXGBE_MRQC_RSSEN; 3848 } 3849 } 3850 3851 /* Perform hash on these packet types */ 3852 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3853 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3854 IXGBE_MRQC_RSS_FIELD_IPV6 | 3855 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3856 3857 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3858 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3859 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3860 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3861 3862 if ((hw->mac.type >= ixgbe_mac_X550) && 3863 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3864 unsigned int pf_pool = adapter->num_vfs; 3865 3866 /* Enable VF RSS mode */ 3867 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3868 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3869 3870 /* Setup RSS through the VF registers */ 3871 ixgbe_setup_vfreta(adapter); 3872 vfmrqc = IXGBE_MRQC_RSSEN; 3873 vfmrqc |= rss_field; 3874 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3875 } else { 3876 ixgbe_setup_reta(adapter); 3877 mrqc |= rss_field; 3878 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3879 } 3880 } 3881 3882 /** 3883 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3884 * @adapter: address of board private structure 3885 * @index: index of ring to set 3886 **/ 3887 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3888 struct ixgbe_ring *ring) 3889 { 3890 struct ixgbe_hw *hw = &adapter->hw; 3891 u32 rscctrl; 3892 u8 reg_idx = ring->reg_idx; 3893 3894 if (!ring_is_rsc_enabled(ring)) 3895 return; 3896 3897 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3898 rscctrl |= IXGBE_RSCCTL_RSCEN; 3899 /* 3900 * we must limit the number of descriptors so that the 3901 * total size of max desc * buf_len is not greater 3902 * than 65536 3903 */ 3904 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3905 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3906 } 3907 3908 #define IXGBE_MAX_RX_DESC_POLL 10 3909 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3910 struct ixgbe_ring *ring) 3911 { 3912 struct ixgbe_hw *hw = &adapter->hw; 3913 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3914 u32 rxdctl; 3915 u8 reg_idx = ring->reg_idx; 3916 3917 if (ixgbe_removed(hw->hw_addr)) 3918 return; 3919 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3920 if (hw->mac.type == ixgbe_mac_82598EB && 3921 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3922 return; 3923 3924 do { 3925 usleep_range(1000, 2000); 3926 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3927 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3928 3929 if (!wait_loop) { 3930 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3931 "the polling period\n", reg_idx); 3932 } 3933 } 3934 3935 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3936 struct ixgbe_ring *ring) 3937 { 3938 struct ixgbe_hw *hw = &adapter->hw; 3939 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3940 u32 rxdctl; 3941 u8 reg_idx = ring->reg_idx; 3942 3943 if (ixgbe_removed(hw->hw_addr)) 3944 return; 3945 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3946 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3947 3948 /* write value back with RXDCTL.ENABLE bit cleared */ 3949 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3950 3951 if (hw->mac.type == ixgbe_mac_82598EB && 3952 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3953 return; 3954 3955 /* the hardware may take up to 100us to really disable the rx queue */ 3956 do { 3957 udelay(10); 3958 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3959 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3960 3961 if (!wait_loop) { 3962 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3963 "the polling period\n", reg_idx); 3964 } 3965 } 3966 3967 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3968 struct ixgbe_ring *ring) 3969 { 3970 struct ixgbe_hw *hw = &adapter->hw; 3971 union ixgbe_adv_rx_desc *rx_desc; 3972 u64 rdba = ring->dma; 3973 u32 rxdctl; 3974 u8 reg_idx = ring->reg_idx; 3975 3976 /* disable queue to avoid issues while updating state */ 3977 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3978 ixgbe_disable_rx_queue(adapter, ring); 3979 3980 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3981 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3982 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3983 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3984 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 3985 IXGBE_WRITE_FLUSH(hw); 3986 3987 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3988 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3989 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3990 3991 ixgbe_configure_srrctl(adapter, ring); 3992 ixgbe_configure_rscctl(adapter, ring); 3993 3994 if (hw->mac.type == ixgbe_mac_82598EB) { 3995 /* 3996 * enable cache line friendly hardware writes: 3997 * PTHRESH=32 descriptors (half the internal cache), 3998 * this also removes ugly rx_no_buffer_count increment 3999 * HTHRESH=4 descriptors (to minimize latency on fetch) 4000 * WTHRESH=8 burst writeback up to two cache lines 4001 */ 4002 rxdctl &= ~0x3FFFFF; 4003 rxdctl |= 0x080420; 4004 #if (PAGE_SIZE < 8192) 4005 } else { 4006 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4007 IXGBE_RXDCTL_RLPML_EN); 4008 4009 /* Limit the maximum frame size so we don't overrun the skb */ 4010 if (ring_uses_build_skb(ring) && 4011 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4012 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4013 IXGBE_RXDCTL_RLPML_EN; 4014 #endif 4015 } 4016 4017 /* initialize rx_buffer_info */ 4018 memset(ring->rx_buffer_info, 0, 4019 sizeof(struct ixgbe_rx_buffer) * ring->count); 4020 4021 /* initialize Rx descriptor 0 */ 4022 rx_desc = IXGBE_RX_DESC(ring, 0); 4023 rx_desc->wb.upper.length = 0; 4024 4025 /* enable receive descriptor ring */ 4026 rxdctl |= IXGBE_RXDCTL_ENABLE; 4027 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4028 4029 ixgbe_rx_desc_queue_enable(adapter, ring); 4030 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4031 } 4032 4033 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4034 { 4035 struct ixgbe_hw *hw = &adapter->hw; 4036 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4037 u16 pool; 4038 4039 /* PSRTYPE must be initialized in non 82598 adapters */ 4040 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4041 IXGBE_PSRTYPE_UDPHDR | 4042 IXGBE_PSRTYPE_IPV4HDR | 4043 IXGBE_PSRTYPE_L2HDR | 4044 IXGBE_PSRTYPE_IPV6HDR; 4045 4046 if (hw->mac.type == ixgbe_mac_82598EB) 4047 return; 4048 4049 if (rss_i > 3) 4050 psrtype |= 2u << 29; 4051 else if (rss_i > 1) 4052 psrtype |= 1u << 29; 4053 4054 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 4055 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4056 } 4057 4058 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4059 { 4060 struct ixgbe_hw *hw = &adapter->hw; 4061 u32 reg_offset, vf_shift; 4062 u32 gcr_ext, vmdctl; 4063 int i; 4064 4065 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4066 return; 4067 4068 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4069 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4070 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4071 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4072 vmdctl |= IXGBE_VT_CTL_REPLEN; 4073 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4074 4075 vf_shift = VMDQ_P(0) % 32; 4076 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4077 4078 /* Enable only the PF's pool for Tx/Rx */ 4079 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4080 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4081 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4082 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4083 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4084 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4085 4086 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4087 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4088 4089 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4090 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4091 4092 /* 4093 * Set up VF register offsets for selected VT Mode, 4094 * i.e. 32 or 64 VFs for SR-IOV 4095 */ 4096 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4097 case IXGBE_82599_VMDQ_8Q_MASK: 4098 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4099 break; 4100 case IXGBE_82599_VMDQ_4Q_MASK: 4101 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4102 break; 4103 default: 4104 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4105 break; 4106 } 4107 4108 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4109 4110 for (i = 0; i < adapter->num_vfs; i++) { 4111 /* configure spoof checking */ 4112 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4113 adapter->vfinfo[i].spoofchk_enabled); 4114 4115 /* Enable/Disable RSS query feature */ 4116 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4117 adapter->vfinfo[i].rss_query_enabled); 4118 } 4119 } 4120 4121 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4122 { 4123 struct ixgbe_hw *hw = &adapter->hw; 4124 struct net_device *netdev = adapter->netdev; 4125 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4126 struct ixgbe_ring *rx_ring; 4127 int i; 4128 u32 mhadd, hlreg0; 4129 4130 #ifdef IXGBE_FCOE 4131 /* adjust max frame to be able to do baby jumbo for FCoE */ 4132 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4133 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4134 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4135 4136 #endif /* IXGBE_FCOE */ 4137 4138 /* adjust max frame to be at least the size of a standard frame */ 4139 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4140 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4141 4142 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4143 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4144 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4145 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4146 4147 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4148 } 4149 4150 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4151 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4152 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4153 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4154 4155 /* 4156 * Setup the HW Rx Head and Tail Descriptor Pointers and 4157 * the Base and Length of the Rx Descriptor Ring 4158 */ 4159 for (i = 0; i < adapter->num_rx_queues; i++) { 4160 rx_ring = adapter->rx_ring[i]; 4161 4162 clear_ring_rsc_enabled(rx_ring); 4163 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4164 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4165 4166 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4167 set_ring_rsc_enabled(rx_ring); 4168 4169 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4170 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4171 4172 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4173 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4174 continue; 4175 4176 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4177 4178 #if (PAGE_SIZE < 8192) 4179 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4180 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4181 4182 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4183 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4184 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4185 #endif 4186 } 4187 } 4188 4189 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4190 { 4191 struct ixgbe_hw *hw = &adapter->hw; 4192 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4193 4194 switch (hw->mac.type) { 4195 case ixgbe_mac_82598EB: 4196 /* 4197 * For VMDq support of different descriptor types or 4198 * buffer sizes through the use of multiple SRRCTL 4199 * registers, RDRXCTL.MVMEN must be set to 1 4200 * 4201 * also, the manual doesn't mention it clearly but DCA hints 4202 * will only use queue 0's tags unless this bit is set. Side 4203 * effects of setting this bit are only that SRRCTL must be 4204 * fully programmed [0..15] 4205 */ 4206 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4207 break; 4208 case ixgbe_mac_X550: 4209 case ixgbe_mac_X550EM_x: 4210 case ixgbe_mac_x550em_a: 4211 if (adapter->num_vfs) 4212 rdrxctl |= IXGBE_RDRXCTL_PSP; 4213 /* fall through */ 4214 case ixgbe_mac_82599EB: 4215 case ixgbe_mac_X540: 4216 /* Disable RSC for ACK packets */ 4217 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4218 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4219 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4220 /* hardware requires some bits to be set by default */ 4221 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4222 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4223 break; 4224 default: 4225 /* We should do nothing since we don't know this hardware */ 4226 return; 4227 } 4228 4229 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4230 } 4231 4232 /** 4233 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4234 * @adapter: board private structure 4235 * 4236 * Configure the Rx unit of the MAC after a reset. 4237 **/ 4238 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4239 { 4240 struct ixgbe_hw *hw = &adapter->hw; 4241 int i; 4242 u32 rxctrl, rfctl; 4243 4244 /* disable receives while setting up the descriptors */ 4245 hw->mac.ops.disable_rx(hw); 4246 4247 ixgbe_setup_psrtype(adapter); 4248 ixgbe_setup_rdrxctl(adapter); 4249 4250 /* RSC Setup */ 4251 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4252 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4253 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4254 rfctl |= IXGBE_RFCTL_RSC_DIS; 4255 4256 /* disable NFS filtering */ 4257 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4258 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4259 4260 /* Program registers for the distribution of queues */ 4261 ixgbe_setup_mrqc(adapter); 4262 4263 /* set_rx_buffer_len must be called before ring initialization */ 4264 ixgbe_set_rx_buffer_len(adapter); 4265 4266 /* 4267 * Setup the HW Rx Head and Tail Descriptor Pointers and 4268 * the Base and Length of the Rx Descriptor Ring 4269 */ 4270 for (i = 0; i < adapter->num_rx_queues; i++) 4271 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4272 4273 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4274 /* disable drop enable for 82598 parts */ 4275 if (hw->mac.type == ixgbe_mac_82598EB) 4276 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4277 4278 /* enable all receives */ 4279 rxctrl |= IXGBE_RXCTRL_RXEN; 4280 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4281 } 4282 4283 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4284 __be16 proto, u16 vid) 4285 { 4286 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4287 struct ixgbe_hw *hw = &adapter->hw; 4288 4289 /* add VID to filter table */ 4290 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4291 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4292 4293 set_bit(vid, adapter->active_vlans); 4294 4295 return 0; 4296 } 4297 4298 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4299 { 4300 u32 vlvf; 4301 int idx; 4302 4303 /* short cut the special case */ 4304 if (vlan == 0) 4305 return 0; 4306 4307 /* Search for the vlan id in the VLVF entries */ 4308 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4309 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4310 if ((vlvf & VLAN_VID_MASK) == vlan) 4311 break; 4312 } 4313 4314 return idx; 4315 } 4316 4317 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4318 { 4319 struct ixgbe_hw *hw = &adapter->hw; 4320 u32 bits, word; 4321 int idx; 4322 4323 idx = ixgbe_find_vlvf_entry(hw, vid); 4324 if (!idx) 4325 return; 4326 4327 /* See if any other pools are set for this VLAN filter 4328 * entry other than the PF. 4329 */ 4330 word = idx * 2 + (VMDQ_P(0) / 32); 4331 bits = ~BIT(VMDQ_P(0) % 32); 4332 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4333 4334 /* Disable the filter so this falls into the default pool. */ 4335 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4336 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4337 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4338 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4339 } 4340 } 4341 4342 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4343 __be16 proto, u16 vid) 4344 { 4345 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4346 struct ixgbe_hw *hw = &adapter->hw; 4347 4348 /* remove VID from filter table */ 4349 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4350 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4351 4352 clear_bit(vid, adapter->active_vlans); 4353 4354 return 0; 4355 } 4356 4357 /** 4358 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4359 * @adapter: driver data 4360 */ 4361 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4362 { 4363 struct ixgbe_hw *hw = &adapter->hw; 4364 u32 vlnctrl; 4365 int i, j; 4366 4367 switch (hw->mac.type) { 4368 case ixgbe_mac_82598EB: 4369 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4370 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4371 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4372 break; 4373 case ixgbe_mac_82599EB: 4374 case ixgbe_mac_X540: 4375 case ixgbe_mac_X550: 4376 case ixgbe_mac_X550EM_x: 4377 case ixgbe_mac_x550em_a: 4378 for (i = 0; i < adapter->num_rx_queues; i++) { 4379 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4380 4381 if (ring->l2_accel_priv) 4382 continue; 4383 j = ring->reg_idx; 4384 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4385 vlnctrl &= ~IXGBE_RXDCTL_VME; 4386 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4387 } 4388 break; 4389 default: 4390 break; 4391 } 4392 } 4393 4394 /** 4395 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4396 * @adapter: driver data 4397 */ 4398 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4399 { 4400 struct ixgbe_hw *hw = &adapter->hw; 4401 u32 vlnctrl; 4402 int i, j; 4403 4404 switch (hw->mac.type) { 4405 case ixgbe_mac_82598EB: 4406 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4407 vlnctrl |= IXGBE_VLNCTRL_VME; 4408 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4409 break; 4410 case ixgbe_mac_82599EB: 4411 case ixgbe_mac_X540: 4412 case ixgbe_mac_X550: 4413 case ixgbe_mac_X550EM_x: 4414 case ixgbe_mac_x550em_a: 4415 for (i = 0; i < adapter->num_rx_queues; i++) { 4416 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4417 4418 if (ring->l2_accel_priv) 4419 continue; 4420 j = ring->reg_idx; 4421 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4422 vlnctrl |= IXGBE_RXDCTL_VME; 4423 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4424 } 4425 break; 4426 default: 4427 break; 4428 } 4429 } 4430 4431 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4432 { 4433 struct ixgbe_hw *hw = &adapter->hw; 4434 u32 vlnctrl, i; 4435 4436 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4437 4438 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4439 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4440 vlnctrl |= IXGBE_VLNCTRL_VFE; 4441 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4442 } else { 4443 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4444 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4445 return; 4446 } 4447 4448 /* Nothing to do for 82598 */ 4449 if (hw->mac.type == ixgbe_mac_82598EB) 4450 return; 4451 4452 /* We are already in VLAN promisc, nothing to do */ 4453 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4454 return; 4455 4456 /* Set flag so we don't redo unnecessary work */ 4457 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4458 4459 /* Add PF to all active pools */ 4460 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4461 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4462 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4463 4464 vlvfb |= BIT(VMDQ_P(0) % 32); 4465 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4466 } 4467 4468 /* Set all bits in the VLAN filter table array */ 4469 for (i = hw->mac.vft_size; i--;) 4470 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4471 } 4472 4473 #define VFTA_BLOCK_SIZE 8 4474 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4475 { 4476 struct ixgbe_hw *hw = &adapter->hw; 4477 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4478 u32 vid_start = vfta_offset * 32; 4479 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4480 u32 i, vid, word, bits; 4481 4482 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4483 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4484 4485 /* pull VLAN ID from VLVF */ 4486 vid = vlvf & VLAN_VID_MASK; 4487 4488 /* only concern outselves with a certain range */ 4489 if (vid < vid_start || vid >= vid_end) 4490 continue; 4491 4492 if (vlvf) { 4493 /* record VLAN ID in VFTA */ 4494 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4495 4496 /* if PF is part of this then continue */ 4497 if (test_bit(vid, adapter->active_vlans)) 4498 continue; 4499 } 4500 4501 /* remove PF from the pool */ 4502 word = i * 2 + VMDQ_P(0) / 32; 4503 bits = ~BIT(VMDQ_P(0) % 32); 4504 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4505 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4506 } 4507 4508 /* extract values from active_vlans and write back to VFTA */ 4509 for (i = VFTA_BLOCK_SIZE; i--;) { 4510 vid = (vfta_offset + i) * 32; 4511 word = vid / BITS_PER_LONG; 4512 bits = vid % BITS_PER_LONG; 4513 4514 vfta[i] |= adapter->active_vlans[word] >> bits; 4515 4516 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4517 } 4518 } 4519 4520 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4521 { 4522 struct ixgbe_hw *hw = &adapter->hw; 4523 u32 vlnctrl, i; 4524 4525 /* Set VLAN filtering to enabled */ 4526 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4527 vlnctrl |= IXGBE_VLNCTRL_VFE; 4528 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4529 4530 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4531 hw->mac.type == ixgbe_mac_82598EB) 4532 return; 4533 4534 /* We are not in VLAN promisc, nothing to do */ 4535 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4536 return; 4537 4538 /* Set flag so we don't redo unnecessary work */ 4539 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4540 4541 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4542 ixgbe_scrub_vfta(adapter, i); 4543 } 4544 4545 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4546 { 4547 u16 vid = 1; 4548 4549 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4550 4551 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4552 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4553 } 4554 4555 /** 4556 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4557 * @netdev: network interface device structure 4558 * 4559 * Writes multicast address list to the MTA hash table. 4560 * Returns: -ENOMEM on failure 4561 * 0 on no addresses written 4562 * X on writing X addresses to MTA 4563 **/ 4564 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4565 { 4566 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4567 struct ixgbe_hw *hw = &adapter->hw; 4568 4569 if (!netif_running(netdev)) 4570 return 0; 4571 4572 if (hw->mac.ops.update_mc_addr_list) 4573 hw->mac.ops.update_mc_addr_list(hw, netdev); 4574 else 4575 return -ENOMEM; 4576 4577 #ifdef CONFIG_PCI_IOV 4578 ixgbe_restore_vf_multicasts(adapter); 4579 #endif 4580 4581 return netdev_mc_count(netdev); 4582 } 4583 4584 #ifdef CONFIG_PCI_IOV 4585 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4586 { 4587 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4588 struct ixgbe_hw *hw = &adapter->hw; 4589 int i; 4590 4591 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4592 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4593 4594 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4595 hw->mac.ops.set_rar(hw, i, 4596 mac_table->addr, 4597 mac_table->pool, 4598 IXGBE_RAH_AV); 4599 else 4600 hw->mac.ops.clear_rar(hw, i); 4601 } 4602 } 4603 4604 #endif 4605 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4606 { 4607 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4608 struct ixgbe_hw *hw = &adapter->hw; 4609 int i; 4610 4611 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4612 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4613 continue; 4614 4615 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4616 4617 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4618 hw->mac.ops.set_rar(hw, i, 4619 mac_table->addr, 4620 mac_table->pool, 4621 IXGBE_RAH_AV); 4622 else 4623 hw->mac.ops.clear_rar(hw, i); 4624 } 4625 } 4626 4627 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4628 { 4629 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4630 struct ixgbe_hw *hw = &adapter->hw; 4631 int i; 4632 4633 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4634 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4635 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4636 } 4637 4638 ixgbe_sync_mac_table(adapter); 4639 } 4640 4641 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4642 { 4643 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4644 struct ixgbe_hw *hw = &adapter->hw; 4645 int i, count = 0; 4646 4647 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4648 /* do not count default RAR as available */ 4649 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4650 continue; 4651 4652 /* only count unused and addresses that belong to us */ 4653 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4654 if (mac_table->pool != pool) 4655 continue; 4656 } 4657 4658 count++; 4659 } 4660 4661 return count; 4662 } 4663 4664 /* this function destroys the first RAR entry */ 4665 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4666 { 4667 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4668 struct ixgbe_hw *hw = &adapter->hw; 4669 4670 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4671 mac_table->pool = VMDQ_P(0); 4672 4673 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4674 4675 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4676 IXGBE_RAH_AV); 4677 } 4678 4679 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4680 const u8 *addr, u16 pool) 4681 { 4682 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4683 struct ixgbe_hw *hw = &adapter->hw; 4684 int i; 4685 4686 if (is_zero_ether_addr(addr)) 4687 return -EINVAL; 4688 4689 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4690 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4691 continue; 4692 4693 ether_addr_copy(mac_table->addr, addr); 4694 mac_table->pool = pool; 4695 4696 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4697 IXGBE_MAC_STATE_IN_USE; 4698 4699 ixgbe_sync_mac_table(adapter); 4700 4701 return i; 4702 } 4703 4704 return -ENOMEM; 4705 } 4706 4707 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4708 const u8 *addr, u16 pool) 4709 { 4710 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4711 struct ixgbe_hw *hw = &adapter->hw; 4712 int i; 4713 4714 if (is_zero_ether_addr(addr)) 4715 return -EINVAL; 4716 4717 /* search table for addr, if found clear IN_USE flag and sync */ 4718 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4719 /* we can only delete an entry if it is in use */ 4720 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4721 continue; 4722 /* we only care about entries that belong to the given pool */ 4723 if (mac_table->pool != pool) 4724 continue; 4725 /* we only care about a specific MAC address */ 4726 if (!ether_addr_equal(addr, mac_table->addr)) 4727 continue; 4728 4729 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4730 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4731 4732 ixgbe_sync_mac_table(adapter); 4733 4734 return 0; 4735 } 4736 4737 return -ENOMEM; 4738 } 4739 /** 4740 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4741 * @netdev: network interface device structure 4742 * 4743 * Writes unicast address list to the RAR table. 4744 * Returns: -ENOMEM on failure/insufficient address space 4745 * 0 on no addresses written 4746 * X on writing X addresses to the RAR table 4747 **/ 4748 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4749 { 4750 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4751 int count = 0; 4752 4753 /* return ENOMEM indicating insufficient memory for addresses */ 4754 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) 4755 return -ENOMEM; 4756 4757 if (!netdev_uc_empty(netdev)) { 4758 struct netdev_hw_addr *ha; 4759 netdev_for_each_uc_addr(ha, netdev) { 4760 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4761 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4762 count++; 4763 } 4764 } 4765 return count; 4766 } 4767 4768 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4769 { 4770 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4771 int ret; 4772 4773 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4774 4775 return min_t(int, ret, 0); 4776 } 4777 4778 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4779 { 4780 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4781 4782 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4783 4784 return 0; 4785 } 4786 4787 /** 4788 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4789 * @netdev: network interface device structure 4790 * 4791 * The set_rx_method entry point is called whenever the unicast/multicast 4792 * address list or the network interface flags are updated. This routine is 4793 * responsible for configuring the hardware for proper unicast, multicast and 4794 * promiscuous mode. 4795 **/ 4796 void ixgbe_set_rx_mode(struct net_device *netdev) 4797 { 4798 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4799 struct ixgbe_hw *hw = &adapter->hw; 4800 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4801 netdev_features_t features = netdev->features; 4802 int count; 4803 4804 /* Check for Promiscuous and All Multicast modes */ 4805 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4806 4807 /* set all bits that we expect to always be set */ 4808 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4809 fctrl |= IXGBE_FCTRL_BAM; 4810 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4811 fctrl |= IXGBE_FCTRL_PMCF; 4812 4813 /* clear the bits we are changing the status of */ 4814 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4815 if (netdev->flags & IFF_PROMISC) { 4816 hw->addr_ctrl.user_set_promisc = true; 4817 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4818 vmolr |= IXGBE_VMOLR_MPE; 4819 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4820 } else { 4821 if (netdev->flags & IFF_ALLMULTI) { 4822 fctrl |= IXGBE_FCTRL_MPE; 4823 vmolr |= IXGBE_VMOLR_MPE; 4824 } 4825 hw->addr_ctrl.user_set_promisc = false; 4826 } 4827 4828 /* 4829 * Write addresses to available RAR registers, if there is not 4830 * sufficient space to store all the addresses then enable 4831 * unicast promiscuous mode 4832 */ 4833 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4834 fctrl |= IXGBE_FCTRL_UPE; 4835 vmolr |= IXGBE_VMOLR_ROPE; 4836 } 4837 4838 /* Write addresses to the MTA, if the attempt fails 4839 * then we should just turn on promiscuous mode so 4840 * that we can at least receive multicast traffic 4841 */ 4842 count = ixgbe_write_mc_addr_list(netdev); 4843 if (count < 0) { 4844 fctrl |= IXGBE_FCTRL_MPE; 4845 vmolr |= IXGBE_VMOLR_MPE; 4846 } else if (count) { 4847 vmolr |= IXGBE_VMOLR_ROMPE; 4848 } 4849 4850 if (hw->mac.type != ixgbe_mac_82598EB) { 4851 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4852 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4853 IXGBE_VMOLR_ROPE); 4854 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4855 } 4856 4857 /* This is useful for sniffing bad packets. */ 4858 if (features & NETIF_F_RXALL) { 4859 /* UPE and MPE will be handled by normal PROMISC logic 4860 * in e1000e_set_rx_mode */ 4861 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4862 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4863 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4864 4865 fctrl &= ~(IXGBE_FCTRL_DPF); 4866 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4867 } 4868 4869 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4870 4871 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4872 ixgbe_vlan_strip_enable(adapter); 4873 else 4874 ixgbe_vlan_strip_disable(adapter); 4875 4876 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4877 ixgbe_vlan_promisc_disable(adapter); 4878 else 4879 ixgbe_vlan_promisc_enable(adapter); 4880 } 4881 4882 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4883 { 4884 int q_idx; 4885 4886 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4887 napi_enable(&adapter->q_vector[q_idx]->napi); 4888 } 4889 4890 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4891 { 4892 int q_idx; 4893 4894 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4895 napi_disable(&adapter->q_vector[q_idx]->napi); 4896 } 4897 4898 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 4899 { 4900 struct ixgbe_hw *hw = &adapter->hw; 4901 u32 vxlanctrl; 4902 4903 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 4904 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 4905 return; 4906 4907 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask; 4908 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 4909 4910 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 4911 adapter->vxlan_port = 0; 4912 4913 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 4914 adapter->geneve_port = 0; 4915 } 4916 4917 #ifdef CONFIG_IXGBE_DCB 4918 /** 4919 * ixgbe_configure_dcb - Configure DCB hardware 4920 * @adapter: ixgbe adapter struct 4921 * 4922 * This is called by the driver on open to configure the DCB hardware. 4923 * This is also called by the gennetlink interface when reconfiguring 4924 * the DCB state. 4925 */ 4926 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4927 { 4928 struct ixgbe_hw *hw = &adapter->hw; 4929 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4930 4931 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4932 if (hw->mac.type == ixgbe_mac_82598EB) 4933 netif_set_gso_max_size(adapter->netdev, 65536); 4934 return; 4935 } 4936 4937 if (hw->mac.type == ixgbe_mac_82598EB) 4938 netif_set_gso_max_size(adapter->netdev, 32768); 4939 4940 #ifdef IXGBE_FCOE 4941 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4942 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4943 #endif 4944 4945 /* reconfigure the hardware */ 4946 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4947 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4948 DCB_TX_CONFIG); 4949 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4950 DCB_RX_CONFIG); 4951 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4952 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4953 ixgbe_dcb_hw_ets(&adapter->hw, 4954 adapter->ixgbe_ieee_ets, 4955 max_frame); 4956 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4957 adapter->ixgbe_ieee_pfc->pfc_en, 4958 adapter->ixgbe_ieee_ets->prio_tc); 4959 } 4960 4961 /* Enable RSS Hash per TC */ 4962 if (hw->mac.type != ixgbe_mac_82598EB) { 4963 u32 msb = 0; 4964 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4965 4966 while (rss_i) { 4967 msb++; 4968 rss_i >>= 1; 4969 } 4970 4971 /* write msb to all 8 TCs in one write */ 4972 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4973 } 4974 } 4975 #endif 4976 4977 /* Additional bittime to account for IXGBE framing */ 4978 #define IXGBE_ETH_FRAMING 20 4979 4980 /** 4981 * ixgbe_hpbthresh - calculate high water mark for flow control 4982 * 4983 * @adapter: board private structure to calculate for 4984 * @pb: packet buffer to calculate 4985 */ 4986 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4987 { 4988 struct ixgbe_hw *hw = &adapter->hw; 4989 struct net_device *dev = adapter->netdev; 4990 int link, tc, kb, marker; 4991 u32 dv_id, rx_pba; 4992 4993 /* Calculate max LAN frame size */ 4994 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4995 4996 #ifdef IXGBE_FCOE 4997 /* FCoE traffic class uses FCOE jumbo frames */ 4998 if ((dev->features & NETIF_F_FCOE_MTU) && 4999 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5000 (pb == ixgbe_fcoe_get_tc(adapter))) 5001 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5002 #endif 5003 5004 /* Calculate delay value for device */ 5005 switch (hw->mac.type) { 5006 case ixgbe_mac_X540: 5007 case ixgbe_mac_X550: 5008 case ixgbe_mac_X550EM_x: 5009 case ixgbe_mac_x550em_a: 5010 dv_id = IXGBE_DV_X540(link, tc); 5011 break; 5012 default: 5013 dv_id = IXGBE_DV(link, tc); 5014 break; 5015 } 5016 5017 /* Loopback switch introduces additional latency */ 5018 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5019 dv_id += IXGBE_B2BT(tc); 5020 5021 /* Delay value is calculated in bit times convert to KB */ 5022 kb = IXGBE_BT2KB(dv_id); 5023 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5024 5025 marker = rx_pba - kb; 5026 5027 /* It is possible that the packet buffer is not large enough 5028 * to provide required headroom. In this case throw an error 5029 * to user and a do the best we can. 5030 */ 5031 if (marker < 0) { 5032 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5033 "headroom to support flow control." 5034 "Decrease MTU or number of traffic classes\n", pb); 5035 marker = tc + 1; 5036 } 5037 5038 return marker; 5039 } 5040 5041 /** 5042 * ixgbe_lpbthresh - calculate low water mark for for flow control 5043 * 5044 * @adapter: board private structure to calculate for 5045 * @pb: packet buffer to calculate 5046 */ 5047 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5048 { 5049 struct ixgbe_hw *hw = &adapter->hw; 5050 struct net_device *dev = adapter->netdev; 5051 int tc; 5052 u32 dv_id; 5053 5054 /* Calculate max LAN frame size */ 5055 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5056 5057 #ifdef IXGBE_FCOE 5058 /* FCoE traffic class uses FCOE jumbo frames */ 5059 if ((dev->features & NETIF_F_FCOE_MTU) && 5060 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5061 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5062 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5063 #endif 5064 5065 /* Calculate delay value for device */ 5066 switch (hw->mac.type) { 5067 case ixgbe_mac_X540: 5068 case ixgbe_mac_X550: 5069 case ixgbe_mac_X550EM_x: 5070 case ixgbe_mac_x550em_a: 5071 dv_id = IXGBE_LOW_DV_X540(tc); 5072 break; 5073 default: 5074 dv_id = IXGBE_LOW_DV(tc); 5075 break; 5076 } 5077 5078 /* Delay value is calculated in bit times convert to KB */ 5079 return IXGBE_BT2KB(dv_id); 5080 } 5081 5082 /* 5083 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5084 */ 5085 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5086 { 5087 struct ixgbe_hw *hw = &adapter->hw; 5088 int num_tc = netdev_get_num_tc(adapter->netdev); 5089 int i; 5090 5091 if (!num_tc) 5092 num_tc = 1; 5093 5094 for (i = 0; i < num_tc; i++) { 5095 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5096 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5097 5098 /* Low water marks must not be larger than high water marks */ 5099 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5100 hw->fc.low_water[i] = 0; 5101 } 5102 5103 for (; i < MAX_TRAFFIC_CLASS; i++) 5104 hw->fc.high_water[i] = 0; 5105 } 5106 5107 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5108 { 5109 struct ixgbe_hw *hw = &adapter->hw; 5110 int hdrm; 5111 u8 tc = netdev_get_num_tc(adapter->netdev); 5112 5113 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5114 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5115 hdrm = 32 << adapter->fdir_pballoc; 5116 else 5117 hdrm = 0; 5118 5119 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5120 ixgbe_pbthresh_setup(adapter); 5121 } 5122 5123 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5124 { 5125 struct ixgbe_hw *hw = &adapter->hw; 5126 struct hlist_node *node2; 5127 struct ixgbe_fdir_filter *filter; 5128 5129 spin_lock(&adapter->fdir_perfect_lock); 5130 5131 if (!hlist_empty(&adapter->fdir_filter_list)) 5132 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5133 5134 hlist_for_each_entry_safe(filter, node2, 5135 &adapter->fdir_filter_list, fdir_node) { 5136 ixgbe_fdir_write_perfect_filter_82599(hw, 5137 &filter->filter, 5138 filter->sw_idx, 5139 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5140 IXGBE_FDIR_DROP_QUEUE : 5141 adapter->rx_ring[filter->action]->reg_idx); 5142 } 5143 5144 spin_unlock(&adapter->fdir_perfect_lock); 5145 } 5146 5147 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 5148 struct ixgbe_adapter *adapter) 5149 { 5150 struct ixgbe_hw *hw = &adapter->hw; 5151 u32 vmolr; 5152 5153 /* No unicast promiscuous support for VMDQ devices. */ 5154 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 5155 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 5156 5157 /* clear the affected bit */ 5158 vmolr &= ~IXGBE_VMOLR_MPE; 5159 5160 if (dev->flags & IFF_ALLMULTI) { 5161 vmolr |= IXGBE_VMOLR_MPE; 5162 } else { 5163 vmolr |= IXGBE_VMOLR_ROMPE; 5164 hw->mac.ops.update_mc_addr_list(hw, dev); 5165 } 5166 ixgbe_write_uc_addr_list(adapter->netdev, pool); 5167 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 5168 } 5169 5170 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 5171 { 5172 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5173 int rss_i = adapter->num_rx_queues_per_pool; 5174 struct ixgbe_hw *hw = &adapter->hw; 5175 u16 pool = vadapter->pool; 5176 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 5177 IXGBE_PSRTYPE_UDPHDR | 5178 IXGBE_PSRTYPE_IPV4HDR | 5179 IXGBE_PSRTYPE_L2HDR | 5180 IXGBE_PSRTYPE_IPV6HDR; 5181 5182 if (hw->mac.type == ixgbe_mac_82598EB) 5183 return; 5184 5185 if (rss_i > 3) 5186 psrtype |= 2u << 29; 5187 else if (rss_i > 1) 5188 psrtype |= 1u << 29; 5189 5190 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 5191 } 5192 5193 /** 5194 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5195 * @rx_ring: ring to free buffers from 5196 **/ 5197 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5198 { 5199 u16 i = rx_ring->next_to_clean; 5200 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5201 5202 /* Free all the Rx ring sk_buffs */ 5203 while (i != rx_ring->next_to_alloc) { 5204 if (rx_buffer->skb) { 5205 struct sk_buff *skb = rx_buffer->skb; 5206 if (IXGBE_CB(skb)->page_released) 5207 dma_unmap_page_attrs(rx_ring->dev, 5208 IXGBE_CB(skb)->dma, 5209 ixgbe_rx_pg_size(rx_ring), 5210 DMA_FROM_DEVICE, 5211 IXGBE_RX_DMA_ATTR); 5212 dev_kfree_skb(skb); 5213 } 5214 5215 /* Invalidate cache lines that may have been written to by 5216 * device so that we avoid corrupting memory. 5217 */ 5218 dma_sync_single_range_for_cpu(rx_ring->dev, 5219 rx_buffer->dma, 5220 rx_buffer->page_offset, 5221 ixgbe_rx_bufsz(rx_ring), 5222 DMA_FROM_DEVICE); 5223 5224 /* free resources associated with mapping */ 5225 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5226 ixgbe_rx_pg_size(rx_ring), 5227 DMA_FROM_DEVICE, 5228 IXGBE_RX_DMA_ATTR); 5229 __page_frag_cache_drain(rx_buffer->page, 5230 rx_buffer->pagecnt_bias); 5231 5232 i++; 5233 rx_buffer++; 5234 if (i == rx_ring->count) { 5235 i = 0; 5236 rx_buffer = rx_ring->rx_buffer_info; 5237 } 5238 } 5239 5240 rx_ring->next_to_alloc = 0; 5241 rx_ring->next_to_clean = 0; 5242 rx_ring->next_to_use = 0; 5243 } 5244 5245 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 5246 struct ixgbe_ring *rx_ring) 5247 { 5248 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5249 int index = rx_ring->queue_index + vadapter->rx_base_queue; 5250 5251 /* shutdown specific queue receive and wait for dma to settle */ 5252 ixgbe_disable_rx_queue(adapter, rx_ring); 5253 usleep_range(10000, 20000); 5254 ixgbe_irq_disable_queues(adapter, BIT_ULL(index)); 5255 ixgbe_clean_rx_ring(rx_ring); 5256 rx_ring->l2_accel_priv = NULL; 5257 } 5258 5259 static int ixgbe_fwd_ring_down(struct net_device *vdev, 5260 struct ixgbe_fwd_adapter *accel) 5261 { 5262 struct ixgbe_adapter *adapter = accel->real_adapter; 5263 unsigned int rxbase = accel->rx_base_queue; 5264 unsigned int txbase = accel->tx_base_queue; 5265 int i; 5266 5267 netif_tx_stop_all_queues(vdev); 5268 5269 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5270 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5271 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 5272 } 5273 5274 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5275 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 5276 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 5277 } 5278 5279 5280 return 0; 5281 } 5282 5283 static int ixgbe_fwd_ring_up(struct net_device *vdev, 5284 struct ixgbe_fwd_adapter *accel) 5285 { 5286 struct ixgbe_adapter *adapter = accel->real_adapter; 5287 unsigned int rxbase, txbase, queues; 5288 int i, baseq, err = 0; 5289 5290 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 5291 return 0; 5292 5293 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5294 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 5295 accel->pool, adapter->num_rx_pools, 5296 baseq, baseq + adapter->num_rx_queues_per_pool, 5297 adapter->fwd_bitmask); 5298 5299 accel->netdev = vdev; 5300 accel->rx_base_queue = rxbase = baseq; 5301 accel->tx_base_queue = txbase = baseq; 5302 5303 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5304 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5305 5306 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5307 adapter->rx_ring[rxbase + i]->netdev = vdev; 5308 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 5309 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 5310 } 5311 5312 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5313 adapter->tx_ring[txbase + i]->netdev = vdev; 5314 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 5315 } 5316 5317 queues = min_t(unsigned int, 5318 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 5319 err = netif_set_real_num_tx_queues(vdev, queues); 5320 if (err) 5321 goto fwd_queue_err; 5322 5323 err = netif_set_real_num_rx_queues(vdev, queues); 5324 if (err) 5325 goto fwd_queue_err; 5326 5327 if (is_valid_ether_addr(vdev->dev_addr)) 5328 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 5329 5330 ixgbe_fwd_psrtype(accel); 5331 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 5332 return err; 5333 fwd_queue_err: 5334 ixgbe_fwd_ring_down(vdev, accel); 5335 return err; 5336 } 5337 5338 static int ixgbe_upper_dev_walk(struct net_device *upper, void *data) 5339 { 5340 if (netif_is_macvlan(upper)) { 5341 struct macvlan_dev *dfwd = netdev_priv(upper); 5342 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 5343 5344 if (dfwd->fwd_priv) 5345 ixgbe_fwd_ring_up(upper, vadapter); 5346 } 5347 5348 return 0; 5349 } 5350 5351 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5352 { 5353 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5354 ixgbe_upper_dev_walk, NULL); 5355 } 5356 5357 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5358 { 5359 struct ixgbe_hw *hw = &adapter->hw; 5360 5361 ixgbe_configure_pb(adapter); 5362 #ifdef CONFIG_IXGBE_DCB 5363 ixgbe_configure_dcb(adapter); 5364 #endif 5365 /* 5366 * We must restore virtualization before VLANs or else 5367 * the VLVF registers will not be populated 5368 */ 5369 ixgbe_configure_virtualization(adapter); 5370 5371 ixgbe_set_rx_mode(adapter->netdev); 5372 ixgbe_restore_vlan(adapter); 5373 5374 switch (hw->mac.type) { 5375 case ixgbe_mac_82599EB: 5376 case ixgbe_mac_X540: 5377 hw->mac.ops.disable_rx_buff(hw); 5378 break; 5379 default: 5380 break; 5381 } 5382 5383 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5384 ixgbe_init_fdir_signature_82599(&adapter->hw, 5385 adapter->fdir_pballoc); 5386 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5387 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5388 adapter->fdir_pballoc); 5389 ixgbe_fdir_filter_restore(adapter); 5390 } 5391 5392 switch (hw->mac.type) { 5393 case ixgbe_mac_82599EB: 5394 case ixgbe_mac_X540: 5395 hw->mac.ops.enable_rx_buff(hw); 5396 break; 5397 default: 5398 break; 5399 } 5400 5401 #ifdef CONFIG_IXGBE_DCA 5402 /* configure DCA */ 5403 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5404 ixgbe_setup_dca(adapter); 5405 #endif /* CONFIG_IXGBE_DCA */ 5406 5407 #ifdef IXGBE_FCOE 5408 /* configure FCoE L2 filters, redirection table, and Rx control */ 5409 ixgbe_configure_fcoe(adapter); 5410 5411 #endif /* IXGBE_FCOE */ 5412 ixgbe_configure_tx(adapter); 5413 ixgbe_configure_rx(adapter); 5414 ixgbe_configure_dfwd(adapter); 5415 } 5416 5417 /** 5418 * ixgbe_sfp_link_config - set up SFP+ link 5419 * @adapter: pointer to private adapter struct 5420 **/ 5421 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5422 { 5423 /* 5424 * We are assuming the worst case scenario here, and that 5425 * is that an SFP was inserted/removed after the reset 5426 * but before SFP detection was enabled. As such the best 5427 * solution is to just start searching as soon as we start 5428 */ 5429 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5430 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5431 5432 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5433 adapter->sfp_poll_time = 0; 5434 } 5435 5436 /** 5437 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5438 * @hw: pointer to private hardware struct 5439 * 5440 * Returns 0 on success, negative on failure 5441 **/ 5442 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5443 { 5444 u32 speed; 5445 bool autoneg, link_up = false; 5446 int ret = IXGBE_ERR_LINK_SETUP; 5447 5448 if (hw->mac.ops.check_link) 5449 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5450 5451 if (ret) 5452 return ret; 5453 5454 speed = hw->phy.autoneg_advertised; 5455 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5456 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5457 &autoneg); 5458 if (ret) 5459 return ret; 5460 5461 if (hw->mac.ops.setup_link) 5462 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5463 5464 return ret; 5465 } 5466 5467 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5468 { 5469 struct ixgbe_hw *hw = &adapter->hw; 5470 u32 gpie = 0; 5471 5472 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5473 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5474 IXGBE_GPIE_OCD; 5475 gpie |= IXGBE_GPIE_EIAME; 5476 /* 5477 * use EIAM to auto-mask when MSI-X interrupt is asserted 5478 * this saves a register write for every interrupt 5479 */ 5480 switch (hw->mac.type) { 5481 case ixgbe_mac_82598EB: 5482 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5483 break; 5484 case ixgbe_mac_82599EB: 5485 case ixgbe_mac_X540: 5486 case ixgbe_mac_X550: 5487 case ixgbe_mac_X550EM_x: 5488 case ixgbe_mac_x550em_a: 5489 default: 5490 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5491 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5492 break; 5493 } 5494 } else { 5495 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5496 * specifically only auto mask tx and rx interrupts */ 5497 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5498 } 5499 5500 /* XXX: to interrupt immediately for EICS writes, enable this */ 5501 /* gpie |= IXGBE_GPIE_EIMEN; */ 5502 5503 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5504 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5505 5506 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5507 case IXGBE_82599_VMDQ_8Q_MASK: 5508 gpie |= IXGBE_GPIE_VTMODE_16; 5509 break; 5510 case IXGBE_82599_VMDQ_4Q_MASK: 5511 gpie |= IXGBE_GPIE_VTMODE_32; 5512 break; 5513 default: 5514 gpie |= IXGBE_GPIE_VTMODE_64; 5515 break; 5516 } 5517 } 5518 5519 /* Enable Thermal over heat sensor interrupt */ 5520 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5521 switch (adapter->hw.mac.type) { 5522 case ixgbe_mac_82599EB: 5523 gpie |= IXGBE_SDP0_GPIEN_8259X; 5524 break; 5525 default: 5526 break; 5527 } 5528 } 5529 5530 /* Enable fan failure interrupt */ 5531 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5532 gpie |= IXGBE_SDP1_GPIEN(hw); 5533 5534 switch (hw->mac.type) { 5535 case ixgbe_mac_82599EB: 5536 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5537 break; 5538 case ixgbe_mac_X550EM_x: 5539 case ixgbe_mac_x550em_a: 5540 gpie |= IXGBE_SDP0_GPIEN_X540; 5541 break; 5542 default: 5543 break; 5544 } 5545 5546 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5547 } 5548 5549 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5550 { 5551 struct ixgbe_hw *hw = &adapter->hw; 5552 int err; 5553 u32 ctrl_ext; 5554 5555 ixgbe_get_hw_control(adapter); 5556 ixgbe_setup_gpie(adapter); 5557 5558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5559 ixgbe_configure_msix(adapter); 5560 else 5561 ixgbe_configure_msi_and_legacy(adapter); 5562 5563 /* enable the optics for 82599 SFP+ fiber */ 5564 if (hw->mac.ops.enable_tx_laser) 5565 hw->mac.ops.enable_tx_laser(hw); 5566 5567 if (hw->phy.ops.set_phy_power) 5568 hw->phy.ops.set_phy_power(hw, true); 5569 5570 smp_mb__before_atomic(); 5571 clear_bit(__IXGBE_DOWN, &adapter->state); 5572 ixgbe_napi_enable_all(adapter); 5573 5574 if (ixgbe_is_sfp(hw)) { 5575 ixgbe_sfp_link_config(adapter); 5576 } else { 5577 err = ixgbe_non_sfp_link_config(hw); 5578 if (err) 5579 e_err(probe, "link_config FAILED %d\n", err); 5580 } 5581 5582 /* clear any pending interrupts, may auto mask */ 5583 IXGBE_READ_REG(hw, IXGBE_EICR); 5584 ixgbe_irq_enable(adapter, true, true); 5585 5586 /* 5587 * If this adapter has a fan, check to see if we had a failure 5588 * before we enabled the interrupt. 5589 */ 5590 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5591 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5592 if (esdp & IXGBE_ESDP_SDP1) 5593 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5594 } 5595 5596 /* bring the link up in the watchdog, this could race with our first 5597 * link up interrupt but shouldn't be a problem */ 5598 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5599 adapter->link_check_timeout = jiffies; 5600 mod_timer(&adapter->service_timer, jiffies); 5601 5602 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5603 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5604 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5605 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5606 } 5607 5608 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5609 { 5610 WARN_ON(in_interrupt()); 5611 /* put off any impending NetWatchDogTimeout */ 5612 netif_trans_update(adapter->netdev); 5613 5614 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5615 usleep_range(1000, 2000); 5616 if (adapter->hw.phy.type == ixgbe_phy_fw) 5617 ixgbe_watchdog_link_is_down(adapter); 5618 ixgbe_down(adapter); 5619 /* 5620 * If SR-IOV enabled then wait a bit before bringing the adapter 5621 * back up to give the VFs time to respond to the reset. The 5622 * two second wait is based upon the watchdog timer cycle in 5623 * the VF driver. 5624 */ 5625 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5626 msleep(2000); 5627 ixgbe_up(adapter); 5628 clear_bit(__IXGBE_RESETTING, &adapter->state); 5629 } 5630 5631 void ixgbe_up(struct ixgbe_adapter *adapter) 5632 { 5633 /* hardware has been reset, we need to reload some things */ 5634 ixgbe_configure(adapter); 5635 5636 ixgbe_up_complete(adapter); 5637 } 5638 5639 void ixgbe_reset(struct ixgbe_adapter *adapter) 5640 { 5641 struct ixgbe_hw *hw = &adapter->hw; 5642 struct net_device *netdev = adapter->netdev; 5643 int err; 5644 5645 if (ixgbe_removed(hw->hw_addr)) 5646 return; 5647 /* lock SFP init bit to prevent race conditions with the watchdog */ 5648 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5649 usleep_range(1000, 2000); 5650 5651 /* clear all SFP and link config related flags while holding SFP_INIT */ 5652 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5653 IXGBE_FLAG2_SFP_NEEDS_RESET); 5654 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5655 5656 err = hw->mac.ops.init_hw(hw); 5657 switch (err) { 5658 case 0: 5659 case IXGBE_ERR_SFP_NOT_PRESENT: 5660 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5661 break; 5662 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5663 e_dev_err("master disable timed out\n"); 5664 break; 5665 case IXGBE_ERR_EEPROM_VERSION: 5666 /* We are running on a pre-production device, log a warning */ 5667 e_dev_warn("This device is a pre-production adapter/LOM. " 5668 "Please be aware there may be issues associated with " 5669 "your hardware. If you are experiencing problems " 5670 "please contact your Intel or hardware " 5671 "representative who provided you with this " 5672 "hardware.\n"); 5673 break; 5674 default: 5675 e_dev_err("Hardware Error: %d\n", err); 5676 } 5677 5678 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5679 5680 /* flush entries out of MAC table */ 5681 ixgbe_flush_sw_mac_table(adapter); 5682 __dev_uc_unsync(netdev, NULL); 5683 5684 /* do not flush user set addresses */ 5685 ixgbe_mac_set_default_filter(adapter); 5686 5687 /* update SAN MAC vmdq pool selection */ 5688 if (hw->mac.san_mac_rar_index) 5689 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5690 5691 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5692 ixgbe_ptp_reset(adapter); 5693 5694 if (hw->phy.ops.set_phy_power) { 5695 if (!netif_running(adapter->netdev) && !adapter->wol) 5696 hw->phy.ops.set_phy_power(hw, false); 5697 else 5698 hw->phy.ops.set_phy_power(hw, true); 5699 } 5700 } 5701 5702 /** 5703 * ixgbe_clean_tx_ring - Free Tx Buffers 5704 * @tx_ring: ring to be cleaned 5705 **/ 5706 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5707 { 5708 u16 i = tx_ring->next_to_clean; 5709 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5710 5711 while (i != tx_ring->next_to_use) { 5712 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5713 5714 /* Free all the Tx ring sk_buffs */ 5715 if (ring_is_xdp(tx_ring)) 5716 page_frag_free(tx_buffer->data); 5717 else 5718 dev_kfree_skb_any(tx_buffer->skb); 5719 5720 /* unmap skb header data */ 5721 dma_unmap_single(tx_ring->dev, 5722 dma_unmap_addr(tx_buffer, dma), 5723 dma_unmap_len(tx_buffer, len), 5724 DMA_TO_DEVICE); 5725 5726 /* check for eop_desc to determine the end of the packet */ 5727 eop_desc = tx_buffer->next_to_watch; 5728 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5729 5730 /* unmap remaining buffers */ 5731 while (tx_desc != eop_desc) { 5732 tx_buffer++; 5733 tx_desc++; 5734 i++; 5735 if (unlikely(i == tx_ring->count)) { 5736 i = 0; 5737 tx_buffer = tx_ring->tx_buffer_info; 5738 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5739 } 5740 5741 /* unmap any remaining paged data */ 5742 if (dma_unmap_len(tx_buffer, len)) 5743 dma_unmap_page(tx_ring->dev, 5744 dma_unmap_addr(tx_buffer, dma), 5745 dma_unmap_len(tx_buffer, len), 5746 DMA_TO_DEVICE); 5747 } 5748 5749 /* move us one more past the eop_desc for start of next pkt */ 5750 tx_buffer++; 5751 i++; 5752 if (unlikely(i == tx_ring->count)) { 5753 i = 0; 5754 tx_buffer = tx_ring->tx_buffer_info; 5755 } 5756 } 5757 5758 /* reset BQL for queue */ 5759 if (!ring_is_xdp(tx_ring)) 5760 netdev_tx_reset_queue(txring_txq(tx_ring)); 5761 5762 /* reset next_to_use and next_to_clean */ 5763 tx_ring->next_to_use = 0; 5764 tx_ring->next_to_clean = 0; 5765 } 5766 5767 /** 5768 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5769 * @adapter: board private structure 5770 **/ 5771 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5772 { 5773 int i; 5774 5775 for (i = 0; i < adapter->num_rx_queues; i++) 5776 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5777 } 5778 5779 /** 5780 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5781 * @adapter: board private structure 5782 **/ 5783 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5784 { 5785 int i; 5786 5787 for (i = 0; i < adapter->num_tx_queues; i++) 5788 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5789 for (i = 0; i < adapter->num_xdp_queues; i++) 5790 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5791 } 5792 5793 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5794 { 5795 struct hlist_node *node2; 5796 struct ixgbe_fdir_filter *filter; 5797 5798 spin_lock(&adapter->fdir_perfect_lock); 5799 5800 hlist_for_each_entry_safe(filter, node2, 5801 &adapter->fdir_filter_list, fdir_node) { 5802 hlist_del(&filter->fdir_node); 5803 kfree(filter); 5804 } 5805 adapter->fdir_filter_count = 0; 5806 5807 spin_unlock(&adapter->fdir_perfect_lock); 5808 } 5809 5810 static int ixgbe_disable_macvlan(struct net_device *upper, void *data) 5811 { 5812 if (netif_is_macvlan(upper)) { 5813 struct macvlan_dev *vlan = netdev_priv(upper); 5814 5815 if (vlan->fwd_priv) { 5816 netif_tx_stop_all_queues(upper); 5817 netif_carrier_off(upper); 5818 netif_tx_disable(upper); 5819 } 5820 } 5821 5822 return 0; 5823 } 5824 5825 void ixgbe_down(struct ixgbe_adapter *adapter) 5826 { 5827 struct net_device *netdev = adapter->netdev; 5828 struct ixgbe_hw *hw = &adapter->hw; 5829 int i; 5830 5831 /* signal that we are down to the interrupt handler */ 5832 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5833 return; /* do nothing if already down */ 5834 5835 /* disable receives */ 5836 hw->mac.ops.disable_rx(hw); 5837 5838 /* disable all enabled rx queues */ 5839 for (i = 0; i < adapter->num_rx_queues; i++) 5840 /* this call also flushes the previous write */ 5841 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5842 5843 usleep_range(10000, 20000); 5844 5845 /* synchronize_sched() needed for pending XDP buffers to drain */ 5846 if (adapter->xdp_ring[0]) 5847 synchronize_sched(); 5848 netif_tx_stop_all_queues(netdev); 5849 5850 /* call carrier off first to avoid false dev_watchdog timeouts */ 5851 netif_carrier_off(netdev); 5852 netif_tx_disable(netdev); 5853 5854 /* disable any upper devices */ 5855 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5856 ixgbe_disable_macvlan, NULL); 5857 5858 ixgbe_irq_disable(adapter); 5859 5860 ixgbe_napi_disable_all(adapter); 5861 5862 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5863 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5864 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5865 5866 del_timer_sync(&adapter->service_timer); 5867 5868 if (adapter->num_vfs) { 5869 /* Clear EITR Select mapping */ 5870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5871 5872 /* Mark all the VFs as inactive */ 5873 for (i = 0 ; i < adapter->num_vfs; i++) 5874 adapter->vfinfo[i].clear_to_send = false; 5875 5876 /* ping all the active vfs to let them know we are going down */ 5877 ixgbe_ping_all_vfs(adapter); 5878 5879 /* Disable all VFTE/VFRE TX/RX */ 5880 ixgbe_disable_tx_rx(adapter); 5881 } 5882 5883 /* disable transmits in the hardware now that interrupts are off */ 5884 for (i = 0; i < adapter->num_tx_queues; i++) { 5885 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5886 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5887 } 5888 for (i = 0; i < adapter->num_xdp_queues; i++) { 5889 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5890 5891 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5892 } 5893 5894 /* Disable the Tx DMA engine on 82599 and later MAC */ 5895 switch (hw->mac.type) { 5896 case ixgbe_mac_82599EB: 5897 case ixgbe_mac_X540: 5898 case ixgbe_mac_X550: 5899 case ixgbe_mac_X550EM_x: 5900 case ixgbe_mac_x550em_a: 5901 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5902 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5903 ~IXGBE_DMATXCTL_TE)); 5904 break; 5905 default: 5906 break; 5907 } 5908 5909 if (!pci_channel_offline(adapter->pdev)) 5910 ixgbe_reset(adapter); 5911 5912 /* power down the optics for 82599 SFP+ fiber */ 5913 if (hw->mac.ops.disable_tx_laser) 5914 hw->mac.ops.disable_tx_laser(hw); 5915 5916 ixgbe_clean_all_tx_rings(adapter); 5917 ixgbe_clean_all_rx_rings(adapter); 5918 } 5919 5920 /** 5921 * ixgbe_eee_capable - helper function to determine EEE support on X550 5922 * @adapter: board private structure 5923 */ 5924 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5925 { 5926 struct ixgbe_hw *hw = &adapter->hw; 5927 5928 switch (hw->device_id) { 5929 case IXGBE_DEV_ID_X550EM_A_1G_T: 5930 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 5931 if (!hw->phy.eee_speeds_supported) 5932 break; 5933 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 5934 if (!hw->phy.eee_speeds_advertised) 5935 break; 5936 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 5937 break; 5938 default: 5939 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 5940 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 5941 break; 5942 } 5943 } 5944 5945 /** 5946 * ixgbe_tx_timeout - Respond to a Tx Hang 5947 * @netdev: network interface device structure 5948 **/ 5949 static void ixgbe_tx_timeout(struct net_device *netdev) 5950 { 5951 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5952 5953 /* Do the reset outside of interrupt context */ 5954 ixgbe_tx_timeout_reset(adapter); 5955 } 5956 5957 #ifdef CONFIG_IXGBE_DCB 5958 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 5959 { 5960 struct ixgbe_hw *hw = &adapter->hw; 5961 struct tc_configuration *tc; 5962 int j; 5963 5964 switch (hw->mac.type) { 5965 case ixgbe_mac_82598EB: 5966 case ixgbe_mac_82599EB: 5967 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5968 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5969 break; 5970 case ixgbe_mac_X540: 5971 case ixgbe_mac_X550: 5972 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5973 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5974 break; 5975 case ixgbe_mac_X550EM_x: 5976 case ixgbe_mac_x550em_a: 5977 default: 5978 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 5979 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 5980 break; 5981 } 5982 5983 /* Configure DCB traffic classes */ 5984 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5985 tc = &adapter->dcb_cfg.tc_config[j]; 5986 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5987 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5988 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5989 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5990 tc->dcb_pfc = pfc_disabled; 5991 } 5992 5993 /* Initialize default user to priority mapping, UPx->TC0 */ 5994 tc = &adapter->dcb_cfg.tc_config[0]; 5995 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5996 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5997 5998 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5999 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6000 adapter->dcb_cfg.pfc_mode_enable = false; 6001 adapter->dcb_set_bitmap = 0x00; 6002 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6003 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6004 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6005 sizeof(adapter->temp_dcb_cfg)); 6006 } 6007 #endif 6008 6009 /** 6010 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6011 * @adapter: board private structure to initialize 6012 * 6013 * ixgbe_sw_init initializes the Adapter private data structure. 6014 * Fields are initialized based on PCI device information and 6015 * OS network device settings (MTU size). 6016 **/ 6017 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6018 const struct ixgbe_info *ii) 6019 { 6020 struct ixgbe_hw *hw = &adapter->hw; 6021 struct pci_dev *pdev = adapter->pdev; 6022 unsigned int rss, fdir; 6023 u32 fwsm; 6024 int i; 6025 6026 /* PCI config space info */ 6027 6028 hw->vendor_id = pdev->vendor; 6029 hw->device_id = pdev->device; 6030 hw->revision_id = pdev->revision; 6031 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6032 hw->subsystem_device_id = pdev->subsystem_device; 6033 6034 /* get_invariants needs the device IDs */ 6035 ii->get_invariants(hw); 6036 6037 /* Set common capability flags and settings */ 6038 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6039 adapter->ring_feature[RING_F_RSS].limit = rss; 6040 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6041 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6042 adapter->atr_sample_rate = 20; 6043 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6044 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6045 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6046 #ifdef CONFIG_IXGBE_DCA 6047 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6048 #endif 6049 #ifdef CONFIG_IXGBE_DCB 6050 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6051 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6052 #endif 6053 #ifdef IXGBE_FCOE 6054 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6055 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6056 #ifdef CONFIG_IXGBE_DCB 6057 /* Default traffic class to use for FCoE */ 6058 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6059 #endif /* CONFIG_IXGBE_DCB */ 6060 #endif /* IXGBE_FCOE */ 6061 6062 /* initialize static ixgbe jump table entries */ 6063 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6064 GFP_KERNEL); 6065 if (!adapter->jump_tables[0]) 6066 return -ENOMEM; 6067 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6068 6069 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6070 adapter->jump_tables[i] = NULL; 6071 6072 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6073 hw->mac.num_rar_entries, 6074 GFP_ATOMIC); 6075 if (!adapter->mac_table) 6076 return -ENOMEM; 6077 6078 if (ixgbe_init_rss_key(adapter)) 6079 return -ENOMEM; 6080 6081 /* Set MAC specific capability flags and exceptions */ 6082 switch (hw->mac.type) { 6083 case ixgbe_mac_82598EB: 6084 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6085 6086 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6087 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6088 6089 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6090 adapter->ring_feature[RING_F_FDIR].limit = 0; 6091 adapter->atr_sample_rate = 0; 6092 adapter->fdir_pballoc = 0; 6093 #ifdef IXGBE_FCOE 6094 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6095 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6096 #ifdef CONFIG_IXGBE_DCB 6097 adapter->fcoe.up = 0; 6098 #endif /* IXGBE_DCB */ 6099 #endif /* IXGBE_FCOE */ 6100 break; 6101 case ixgbe_mac_82599EB: 6102 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6103 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6104 break; 6105 case ixgbe_mac_X540: 6106 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6107 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6108 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6109 break; 6110 case ixgbe_mac_x550em_a: 6111 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6112 switch (hw->device_id) { 6113 case IXGBE_DEV_ID_X550EM_A_1G_T: 6114 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6115 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6116 break; 6117 default: 6118 break; 6119 } 6120 /* fall through */ 6121 case ixgbe_mac_X550EM_x: 6122 #ifdef CONFIG_IXGBE_DCB 6123 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6124 #endif 6125 #ifdef IXGBE_FCOE 6126 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6127 #ifdef CONFIG_IXGBE_DCB 6128 adapter->fcoe.up = 0; 6129 #endif /* IXGBE_DCB */ 6130 #endif /* IXGBE_FCOE */ 6131 /* Fall Through */ 6132 case ixgbe_mac_X550: 6133 if (hw->mac.type == ixgbe_mac_X550) 6134 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6135 #ifdef CONFIG_IXGBE_DCA 6136 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6137 #endif 6138 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6139 break; 6140 default: 6141 break; 6142 } 6143 6144 #ifdef IXGBE_FCOE 6145 /* FCoE support exists, always init the FCoE lock */ 6146 spin_lock_init(&adapter->fcoe.lock); 6147 6148 #endif 6149 /* n-tuple support exists, always init our spinlock */ 6150 spin_lock_init(&adapter->fdir_perfect_lock); 6151 6152 #ifdef CONFIG_IXGBE_DCB 6153 ixgbe_init_dcb(adapter); 6154 #endif 6155 6156 /* default flow control settings */ 6157 hw->fc.requested_mode = ixgbe_fc_full; 6158 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6159 ixgbe_pbthresh_setup(adapter); 6160 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6161 hw->fc.send_xon = true; 6162 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6163 6164 #ifdef CONFIG_PCI_IOV 6165 if (max_vfs > 0) 6166 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6167 6168 /* assign number of SR-IOV VFs */ 6169 if (hw->mac.type != ixgbe_mac_82598EB) { 6170 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6171 max_vfs = 0; 6172 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6173 } 6174 } 6175 #endif /* CONFIG_PCI_IOV */ 6176 6177 /* enable itr by default in dynamic mode */ 6178 adapter->rx_itr_setting = 1; 6179 adapter->tx_itr_setting = 1; 6180 6181 /* set default ring sizes */ 6182 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6183 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6184 6185 /* set default work limits */ 6186 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6187 6188 /* initialize eeprom parameters */ 6189 if (ixgbe_init_eeprom_params_generic(hw)) { 6190 e_dev_err("EEPROM initialization failed\n"); 6191 return -EIO; 6192 } 6193 6194 /* PF holds first pool slot */ 6195 set_bit(0, &adapter->fwd_bitmask); 6196 set_bit(__IXGBE_DOWN, &adapter->state); 6197 6198 return 0; 6199 } 6200 6201 /** 6202 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6203 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6204 * 6205 * Return 0 on success, negative on failure 6206 **/ 6207 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6208 { 6209 struct device *dev = tx_ring->dev; 6210 int orig_node = dev_to_node(dev); 6211 int ring_node = -1; 6212 int size; 6213 6214 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6215 6216 if (tx_ring->q_vector) 6217 ring_node = tx_ring->q_vector->numa_node; 6218 6219 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6220 if (!tx_ring->tx_buffer_info) 6221 tx_ring->tx_buffer_info = vmalloc(size); 6222 if (!tx_ring->tx_buffer_info) 6223 goto err; 6224 6225 /* round up to nearest 4K */ 6226 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6227 tx_ring->size = ALIGN(tx_ring->size, 4096); 6228 6229 set_dev_node(dev, ring_node); 6230 tx_ring->desc = dma_alloc_coherent(dev, 6231 tx_ring->size, 6232 &tx_ring->dma, 6233 GFP_KERNEL); 6234 set_dev_node(dev, orig_node); 6235 if (!tx_ring->desc) 6236 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6237 &tx_ring->dma, GFP_KERNEL); 6238 if (!tx_ring->desc) 6239 goto err; 6240 6241 tx_ring->next_to_use = 0; 6242 tx_ring->next_to_clean = 0; 6243 return 0; 6244 6245 err: 6246 vfree(tx_ring->tx_buffer_info); 6247 tx_ring->tx_buffer_info = NULL; 6248 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6249 return -ENOMEM; 6250 } 6251 6252 /** 6253 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6254 * @adapter: board private structure 6255 * 6256 * If this function returns with an error, then it's possible one or 6257 * more of the rings is populated (while the rest are not). It is the 6258 * callers duty to clean those orphaned rings. 6259 * 6260 * Return 0 on success, negative on failure 6261 **/ 6262 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6263 { 6264 int i, j = 0, err = 0; 6265 6266 for (i = 0; i < adapter->num_tx_queues; i++) { 6267 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6268 if (!err) 6269 continue; 6270 6271 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6272 goto err_setup_tx; 6273 } 6274 for (j = 0; j < adapter->num_xdp_queues; j++) { 6275 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6276 if (!err) 6277 continue; 6278 6279 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6280 goto err_setup_tx; 6281 } 6282 6283 return 0; 6284 err_setup_tx: 6285 /* rewind the index freeing the rings as we go */ 6286 while (j--) 6287 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6288 while (i--) 6289 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6290 return err; 6291 } 6292 6293 /** 6294 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6295 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6296 * 6297 * Returns 0 on success, negative on failure 6298 **/ 6299 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6300 struct ixgbe_ring *rx_ring) 6301 { 6302 struct device *dev = rx_ring->dev; 6303 int orig_node = dev_to_node(dev); 6304 int ring_node = -1; 6305 int size; 6306 6307 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6308 6309 if (rx_ring->q_vector) 6310 ring_node = rx_ring->q_vector->numa_node; 6311 6312 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6313 if (!rx_ring->rx_buffer_info) 6314 rx_ring->rx_buffer_info = vmalloc(size); 6315 if (!rx_ring->rx_buffer_info) 6316 goto err; 6317 6318 /* Round up to nearest 4K */ 6319 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6320 rx_ring->size = ALIGN(rx_ring->size, 4096); 6321 6322 set_dev_node(dev, ring_node); 6323 rx_ring->desc = dma_alloc_coherent(dev, 6324 rx_ring->size, 6325 &rx_ring->dma, 6326 GFP_KERNEL); 6327 set_dev_node(dev, orig_node); 6328 if (!rx_ring->desc) 6329 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6330 &rx_ring->dma, GFP_KERNEL); 6331 if (!rx_ring->desc) 6332 goto err; 6333 6334 rx_ring->next_to_clean = 0; 6335 rx_ring->next_to_use = 0; 6336 6337 rx_ring->xdp_prog = adapter->xdp_prog; 6338 6339 return 0; 6340 err: 6341 vfree(rx_ring->rx_buffer_info); 6342 rx_ring->rx_buffer_info = NULL; 6343 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6344 return -ENOMEM; 6345 } 6346 6347 /** 6348 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6349 * @adapter: board private structure 6350 * 6351 * If this function returns with an error, then it's possible one or 6352 * more of the rings is populated (while the rest are not). It is the 6353 * callers duty to clean those orphaned rings. 6354 * 6355 * Return 0 on success, negative on failure 6356 **/ 6357 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6358 { 6359 int i, err = 0; 6360 6361 for (i = 0; i < adapter->num_rx_queues; i++) { 6362 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6363 if (!err) 6364 continue; 6365 6366 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6367 goto err_setup_rx; 6368 } 6369 6370 #ifdef IXGBE_FCOE 6371 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6372 if (!err) 6373 #endif 6374 return 0; 6375 err_setup_rx: 6376 /* rewind the index freeing the rings as we go */ 6377 while (i--) 6378 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6379 return err; 6380 } 6381 6382 /** 6383 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6384 * @tx_ring: Tx descriptor ring for a specific queue 6385 * 6386 * Free all transmit software resources 6387 **/ 6388 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6389 { 6390 ixgbe_clean_tx_ring(tx_ring); 6391 6392 vfree(tx_ring->tx_buffer_info); 6393 tx_ring->tx_buffer_info = NULL; 6394 6395 /* if not set, then don't free */ 6396 if (!tx_ring->desc) 6397 return; 6398 6399 dma_free_coherent(tx_ring->dev, tx_ring->size, 6400 tx_ring->desc, tx_ring->dma); 6401 6402 tx_ring->desc = NULL; 6403 } 6404 6405 /** 6406 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6407 * @adapter: board private structure 6408 * 6409 * Free all transmit software resources 6410 **/ 6411 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6412 { 6413 int i; 6414 6415 for (i = 0; i < adapter->num_tx_queues; i++) 6416 if (adapter->tx_ring[i]->desc) 6417 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6418 for (i = 0; i < adapter->num_xdp_queues; i++) 6419 if (adapter->xdp_ring[i]->desc) 6420 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6421 } 6422 6423 /** 6424 * ixgbe_free_rx_resources - Free Rx Resources 6425 * @rx_ring: ring to clean the resources from 6426 * 6427 * Free all receive software resources 6428 **/ 6429 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6430 { 6431 ixgbe_clean_rx_ring(rx_ring); 6432 6433 rx_ring->xdp_prog = NULL; 6434 vfree(rx_ring->rx_buffer_info); 6435 rx_ring->rx_buffer_info = NULL; 6436 6437 /* if not set, then don't free */ 6438 if (!rx_ring->desc) 6439 return; 6440 6441 dma_free_coherent(rx_ring->dev, rx_ring->size, 6442 rx_ring->desc, rx_ring->dma); 6443 6444 rx_ring->desc = NULL; 6445 } 6446 6447 /** 6448 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6449 * @adapter: board private structure 6450 * 6451 * Free all receive software resources 6452 **/ 6453 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6454 { 6455 int i; 6456 6457 #ifdef IXGBE_FCOE 6458 ixgbe_free_fcoe_ddp_resources(adapter); 6459 6460 #endif 6461 for (i = 0; i < adapter->num_rx_queues; i++) 6462 if (adapter->rx_ring[i]->desc) 6463 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6464 } 6465 6466 /** 6467 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6468 * @netdev: network interface device structure 6469 * @new_mtu: new value for maximum frame size 6470 * 6471 * Returns 0 on success, negative on failure 6472 **/ 6473 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6474 { 6475 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6476 6477 /* 6478 * For 82599EB we cannot allow legacy VFs to enable their receive 6479 * paths when MTU greater than 1500 is configured. So display a 6480 * warning that legacy VFs will be disabled. 6481 */ 6482 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6483 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6484 (new_mtu > ETH_DATA_LEN)) 6485 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6486 6487 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6488 6489 /* must set new MTU before calling down or up */ 6490 netdev->mtu = new_mtu; 6491 6492 if (netif_running(netdev)) 6493 ixgbe_reinit_locked(adapter); 6494 6495 return 0; 6496 } 6497 6498 /** 6499 * ixgbe_open - Called when a network interface is made active 6500 * @netdev: network interface device structure 6501 * 6502 * Returns 0 on success, negative value on failure 6503 * 6504 * The open entry point is called when a network interface is made 6505 * active by the system (IFF_UP). At this point all resources needed 6506 * for transmit and receive operations are allocated, the interrupt 6507 * handler is registered with the OS, the watchdog timer is started, 6508 * and the stack is notified that the interface is ready. 6509 **/ 6510 int ixgbe_open(struct net_device *netdev) 6511 { 6512 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6513 struct ixgbe_hw *hw = &adapter->hw; 6514 int err, queues; 6515 6516 /* disallow open during test */ 6517 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6518 return -EBUSY; 6519 6520 netif_carrier_off(netdev); 6521 6522 /* allocate transmit descriptors */ 6523 err = ixgbe_setup_all_tx_resources(adapter); 6524 if (err) 6525 goto err_setup_tx; 6526 6527 /* allocate receive descriptors */ 6528 err = ixgbe_setup_all_rx_resources(adapter); 6529 if (err) 6530 goto err_setup_rx; 6531 6532 ixgbe_configure(adapter); 6533 6534 err = ixgbe_request_irq(adapter); 6535 if (err) 6536 goto err_req_irq; 6537 6538 /* Notify the stack of the actual queue counts. */ 6539 if (adapter->num_rx_pools > 1) 6540 queues = adapter->num_rx_queues_per_pool; 6541 else 6542 queues = adapter->num_tx_queues; 6543 6544 err = netif_set_real_num_tx_queues(netdev, queues); 6545 if (err) 6546 goto err_set_queues; 6547 6548 if (adapter->num_rx_pools > 1 && 6549 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 6550 queues = IXGBE_MAX_L2A_QUEUES; 6551 else 6552 queues = adapter->num_rx_queues; 6553 err = netif_set_real_num_rx_queues(netdev, queues); 6554 if (err) 6555 goto err_set_queues; 6556 6557 ixgbe_ptp_init(adapter); 6558 6559 ixgbe_up_complete(adapter); 6560 6561 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6562 udp_tunnel_get_rx_info(netdev); 6563 6564 return 0; 6565 6566 err_set_queues: 6567 ixgbe_free_irq(adapter); 6568 err_req_irq: 6569 ixgbe_free_all_rx_resources(adapter); 6570 if (hw->phy.ops.set_phy_power && !adapter->wol) 6571 hw->phy.ops.set_phy_power(&adapter->hw, false); 6572 err_setup_rx: 6573 ixgbe_free_all_tx_resources(adapter); 6574 err_setup_tx: 6575 ixgbe_reset(adapter); 6576 6577 return err; 6578 } 6579 6580 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6581 { 6582 ixgbe_ptp_suspend(adapter); 6583 6584 if (adapter->hw.phy.ops.enter_lplu) { 6585 adapter->hw.phy.reset_disable = true; 6586 ixgbe_down(adapter); 6587 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6588 adapter->hw.phy.reset_disable = false; 6589 } else { 6590 ixgbe_down(adapter); 6591 } 6592 6593 ixgbe_free_irq(adapter); 6594 6595 ixgbe_free_all_tx_resources(adapter); 6596 ixgbe_free_all_rx_resources(adapter); 6597 } 6598 6599 /** 6600 * ixgbe_close - Disables a network interface 6601 * @netdev: network interface device structure 6602 * 6603 * Returns 0, this is not allowed to fail 6604 * 6605 * The close entry point is called when an interface is de-activated 6606 * by the OS. The hardware is still under the drivers control, but 6607 * needs to be disabled. A global MAC reset is issued to stop the 6608 * hardware, and all transmit and receive resources are freed. 6609 **/ 6610 int ixgbe_close(struct net_device *netdev) 6611 { 6612 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6613 6614 ixgbe_ptp_stop(adapter); 6615 6616 if (netif_device_present(netdev)) 6617 ixgbe_close_suspend(adapter); 6618 6619 ixgbe_fdir_filter_exit(adapter); 6620 6621 ixgbe_release_hw_control(adapter); 6622 6623 return 0; 6624 } 6625 6626 #ifdef CONFIG_PM 6627 static int ixgbe_resume(struct pci_dev *pdev) 6628 { 6629 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6630 struct net_device *netdev = adapter->netdev; 6631 u32 err; 6632 6633 adapter->hw.hw_addr = adapter->io_addr; 6634 pci_set_power_state(pdev, PCI_D0); 6635 pci_restore_state(pdev); 6636 /* 6637 * pci_restore_state clears dev->state_saved so call 6638 * pci_save_state to restore it. 6639 */ 6640 pci_save_state(pdev); 6641 6642 err = pci_enable_device_mem(pdev); 6643 if (err) { 6644 e_dev_err("Cannot enable PCI device from suspend\n"); 6645 return err; 6646 } 6647 smp_mb__before_atomic(); 6648 clear_bit(__IXGBE_DISABLED, &adapter->state); 6649 pci_set_master(pdev); 6650 6651 pci_wake_from_d3(pdev, false); 6652 6653 ixgbe_reset(adapter); 6654 6655 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6656 6657 rtnl_lock(); 6658 err = ixgbe_init_interrupt_scheme(adapter); 6659 if (!err && netif_running(netdev)) 6660 err = ixgbe_open(netdev); 6661 6662 6663 if (!err) 6664 netif_device_attach(netdev); 6665 rtnl_unlock(); 6666 6667 return err; 6668 } 6669 #endif /* CONFIG_PM */ 6670 6671 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6672 { 6673 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6674 struct net_device *netdev = adapter->netdev; 6675 struct ixgbe_hw *hw = &adapter->hw; 6676 u32 ctrl, fctrl; 6677 u32 wufc = adapter->wol; 6678 #ifdef CONFIG_PM 6679 int retval = 0; 6680 #endif 6681 6682 rtnl_lock(); 6683 netif_device_detach(netdev); 6684 6685 if (netif_running(netdev)) 6686 ixgbe_close_suspend(adapter); 6687 6688 ixgbe_clear_interrupt_scheme(adapter); 6689 rtnl_unlock(); 6690 6691 #ifdef CONFIG_PM 6692 retval = pci_save_state(pdev); 6693 if (retval) 6694 return retval; 6695 6696 #endif 6697 if (hw->mac.ops.stop_link_on_d3) 6698 hw->mac.ops.stop_link_on_d3(hw); 6699 6700 if (wufc) { 6701 ixgbe_set_rx_mode(netdev); 6702 6703 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6704 if (hw->mac.ops.enable_tx_laser) 6705 hw->mac.ops.enable_tx_laser(hw); 6706 6707 /* turn on all-multi mode if wake on multicast is enabled */ 6708 if (wufc & IXGBE_WUFC_MC) { 6709 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6710 fctrl |= IXGBE_FCTRL_MPE; 6711 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6712 } 6713 6714 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6715 ctrl |= IXGBE_CTRL_GIO_DIS; 6716 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6717 6718 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6719 } else { 6720 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6721 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6722 } 6723 6724 switch (hw->mac.type) { 6725 case ixgbe_mac_82598EB: 6726 pci_wake_from_d3(pdev, false); 6727 break; 6728 case ixgbe_mac_82599EB: 6729 case ixgbe_mac_X540: 6730 case ixgbe_mac_X550: 6731 case ixgbe_mac_X550EM_x: 6732 case ixgbe_mac_x550em_a: 6733 pci_wake_from_d3(pdev, !!wufc); 6734 break; 6735 default: 6736 break; 6737 } 6738 6739 *enable_wake = !!wufc; 6740 if (hw->phy.ops.set_phy_power && !*enable_wake) 6741 hw->phy.ops.set_phy_power(hw, false); 6742 6743 ixgbe_release_hw_control(adapter); 6744 6745 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6746 pci_disable_device(pdev); 6747 6748 return 0; 6749 } 6750 6751 #ifdef CONFIG_PM 6752 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6753 { 6754 int retval; 6755 bool wake; 6756 6757 retval = __ixgbe_shutdown(pdev, &wake); 6758 if (retval) 6759 return retval; 6760 6761 if (wake) { 6762 pci_prepare_to_sleep(pdev); 6763 } else { 6764 pci_wake_from_d3(pdev, false); 6765 pci_set_power_state(pdev, PCI_D3hot); 6766 } 6767 6768 return 0; 6769 } 6770 #endif /* CONFIG_PM */ 6771 6772 static void ixgbe_shutdown(struct pci_dev *pdev) 6773 { 6774 bool wake; 6775 6776 __ixgbe_shutdown(pdev, &wake); 6777 6778 if (system_state == SYSTEM_POWER_OFF) { 6779 pci_wake_from_d3(pdev, wake); 6780 pci_set_power_state(pdev, PCI_D3hot); 6781 } 6782 } 6783 6784 /** 6785 * ixgbe_update_stats - Update the board statistics counters. 6786 * @adapter: board private structure 6787 **/ 6788 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6789 { 6790 struct net_device *netdev = adapter->netdev; 6791 struct ixgbe_hw *hw = &adapter->hw; 6792 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6793 u64 total_mpc = 0; 6794 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6795 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6796 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6797 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6798 6799 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6800 test_bit(__IXGBE_RESETTING, &adapter->state)) 6801 return; 6802 6803 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6804 u64 rsc_count = 0; 6805 u64 rsc_flush = 0; 6806 for (i = 0; i < adapter->num_rx_queues; i++) { 6807 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6808 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6809 } 6810 adapter->rsc_total_count = rsc_count; 6811 adapter->rsc_total_flush = rsc_flush; 6812 } 6813 6814 for (i = 0; i < adapter->num_rx_queues; i++) { 6815 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6816 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6817 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6818 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6819 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6820 bytes += rx_ring->stats.bytes; 6821 packets += rx_ring->stats.packets; 6822 } 6823 adapter->non_eop_descs = non_eop_descs; 6824 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6825 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6826 adapter->hw_csum_rx_error = hw_csum_rx_error; 6827 netdev->stats.rx_bytes = bytes; 6828 netdev->stats.rx_packets = packets; 6829 6830 bytes = 0; 6831 packets = 0; 6832 /* gather some stats to the adapter struct that are per queue */ 6833 for (i = 0; i < adapter->num_tx_queues; i++) { 6834 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6835 restart_queue += tx_ring->tx_stats.restart_queue; 6836 tx_busy += tx_ring->tx_stats.tx_busy; 6837 bytes += tx_ring->stats.bytes; 6838 packets += tx_ring->stats.packets; 6839 } 6840 for (i = 0; i < adapter->num_xdp_queues; i++) { 6841 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6842 6843 restart_queue += xdp_ring->tx_stats.restart_queue; 6844 tx_busy += xdp_ring->tx_stats.tx_busy; 6845 bytes += xdp_ring->stats.bytes; 6846 packets += xdp_ring->stats.packets; 6847 } 6848 adapter->restart_queue = restart_queue; 6849 adapter->tx_busy = tx_busy; 6850 netdev->stats.tx_bytes = bytes; 6851 netdev->stats.tx_packets = packets; 6852 6853 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6854 6855 /* 8 register reads */ 6856 for (i = 0; i < 8; i++) { 6857 /* for packet buffers not used, the register should read 0 */ 6858 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6859 missed_rx += mpc; 6860 hwstats->mpc[i] += mpc; 6861 total_mpc += hwstats->mpc[i]; 6862 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6863 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6864 switch (hw->mac.type) { 6865 case ixgbe_mac_82598EB: 6866 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6867 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6868 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6869 hwstats->pxonrxc[i] += 6870 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6871 break; 6872 case ixgbe_mac_82599EB: 6873 case ixgbe_mac_X540: 6874 case ixgbe_mac_X550: 6875 case ixgbe_mac_X550EM_x: 6876 case ixgbe_mac_x550em_a: 6877 hwstats->pxonrxc[i] += 6878 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6879 break; 6880 default: 6881 break; 6882 } 6883 } 6884 6885 /*16 register reads */ 6886 for (i = 0; i < 16; i++) { 6887 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6888 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6889 if ((hw->mac.type == ixgbe_mac_82599EB) || 6890 (hw->mac.type == ixgbe_mac_X540) || 6891 (hw->mac.type == ixgbe_mac_X550) || 6892 (hw->mac.type == ixgbe_mac_X550EM_x) || 6893 (hw->mac.type == ixgbe_mac_x550em_a)) { 6894 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6895 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6896 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6897 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6898 } 6899 } 6900 6901 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6902 /* work around hardware counting issue */ 6903 hwstats->gprc -= missed_rx; 6904 6905 ixgbe_update_xoff_received(adapter); 6906 6907 /* 82598 hardware only has a 32 bit counter in the high register */ 6908 switch (hw->mac.type) { 6909 case ixgbe_mac_82598EB: 6910 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6911 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6912 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6913 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6914 break; 6915 case ixgbe_mac_X540: 6916 case ixgbe_mac_X550: 6917 case ixgbe_mac_X550EM_x: 6918 case ixgbe_mac_x550em_a: 6919 /* OS2BMC stats are X540 and later */ 6920 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6921 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6922 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6923 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6924 /* fall through */ 6925 case ixgbe_mac_82599EB: 6926 for (i = 0; i < 16; i++) 6927 adapter->hw_rx_no_dma_resources += 6928 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6929 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6930 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6931 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6932 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6933 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6934 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6935 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6936 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6937 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6938 #ifdef IXGBE_FCOE 6939 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6940 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6941 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6942 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6943 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6944 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6945 /* Add up per cpu counters for total ddp aloc fail */ 6946 if (adapter->fcoe.ddp_pool) { 6947 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6948 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6949 unsigned int cpu; 6950 u64 noddp = 0, noddp_ext_buff = 0; 6951 for_each_possible_cpu(cpu) { 6952 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6953 noddp += ddp_pool->noddp; 6954 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6955 } 6956 hwstats->fcoe_noddp = noddp; 6957 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6958 } 6959 #endif /* IXGBE_FCOE */ 6960 break; 6961 default: 6962 break; 6963 } 6964 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6965 hwstats->bprc += bprc; 6966 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6967 if (hw->mac.type == ixgbe_mac_82598EB) 6968 hwstats->mprc -= bprc; 6969 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6970 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6971 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6972 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6973 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6974 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6975 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6976 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6977 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6978 hwstats->lxontxc += lxon; 6979 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6980 hwstats->lxofftxc += lxoff; 6981 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6982 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6983 /* 6984 * 82598 errata - tx of flow control packets is included in tx counters 6985 */ 6986 xon_off_tot = lxon + lxoff; 6987 hwstats->gptc -= xon_off_tot; 6988 hwstats->mptc -= xon_off_tot; 6989 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6990 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6991 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6992 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6993 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6994 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6995 hwstats->ptc64 -= xon_off_tot; 6996 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6997 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6998 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6999 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7000 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7001 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7002 7003 /* Fill out the OS statistics structure */ 7004 netdev->stats.multicast = hwstats->mprc; 7005 7006 /* Rx Errors */ 7007 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7008 netdev->stats.rx_dropped = 0; 7009 netdev->stats.rx_length_errors = hwstats->rlec; 7010 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7011 netdev->stats.rx_missed_errors = total_mpc; 7012 } 7013 7014 /** 7015 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7016 * @adapter: pointer to the device adapter structure 7017 **/ 7018 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7019 { 7020 struct ixgbe_hw *hw = &adapter->hw; 7021 int i; 7022 7023 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7024 return; 7025 7026 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7027 7028 /* if interface is down do nothing */ 7029 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7030 return; 7031 7032 /* do nothing if we are not using signature filters */ 7033 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7034 return; 7035 7036 adapter->fdir_overflow++; 7037 7038 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7039 for (i = 0; i < adapter->num_tx_queues; i++) 7040 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7041 &(adapter->tx_ring[i]->state)); 7042 for (i = 0; i < adapter->num_xdp_queues; i++) 7043 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7044 &adapter->xdp_ring[i]->state); 7045 /* re-enable flow director interrupts */ 7046 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7047 } else { 7048 e_err(probe, "failed to finish FDIR re-initialization, " 7049 "ignored adding FDIR ATR filters\n"); 7050 } 7051 } 7052 7053 /** 7054 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7055 * @adapter: pointer to the device adapter structure 7056 * 7057 * This function serves two purposes. First it strobes the interrupt lines 7058 * in order to make certain interrupts are occurring. Secondly it sets the 7059 * bits needed to check for TX hangs. As a result we should immediately 7060 * determine if a hang has occurred. 7061 */ 7062 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7063 { 7064 struct ixgbe_hw *hw = &adapter->hw; 7065 u64 eics = 0; 7066 int i; 7067 7068 /* If we're down, removing or resetting, just bail */ 7069 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7070 test_bit(__IXGBE_REMOVING, &adapter->state) || 7071 test_bit(__IXGBE_RESETTING, &adapter->state)) 7072 return; 7073 7074 /* Force detection of hung controller */ 7075 if (netif_carrier_ok(adapter->netdev)) { 7076 for (i = 0; i < adapter->num_tx_queues; i++) 7077 set_check_for_tx_hang(adapter->tx_ring[i]); 7078 for (i = 0; i < adapter->num_xdp_queues; i++) 7079 set_check_for_tx_hang(adapter->xdp_ring[i]); 7080 } 7081 7082 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7083 /* 7084 * for legacy and MSI interrupts don't set any bits 7085 * that are enabled for EIAM, because this operation 7086 * would set *both* EIMS and EICS for any bit in EIAM 7087 */ 7088 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7089 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7090 } else { 7091 /* get one bit for every active tx/rx interrupt vector */ 7092 for (i = 0; i < adapter->num_q_vectors; i++) { 7093 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7094 if (qv->rx.ring || qv->tx.ring) 7095 eics |= BIT_ULL(i); 7096 } 7097 } 7098 7099 /* Cause software interrupt to ensure rings are cleaned */ 7100 ixgbe_irq_rearm_queues(adapter, eics); 7101 } 7102 7103 /** 7104 * ixgbe_watchdog_update_link - update the link status 7105 * @adapter: pointer to the device adapter structure 7106 * @link_speed: pointer to a u32 to store the link_speed 7107 **/ 7108 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7109 { 7110 struct ixgbe_hw *hw = &adapter->hw; 7111 u32 link_speed = adapter->link_speed; 7112 bool link_up = adapter->link_up; 7113 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7114 7115 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7116 return; 7117 7118 if (hw->mac.ops.check_link) { 7119 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7120 } else { 7121 /* always assume link is up, if no check link function */ 7122 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7123 link_up = true; 7124 } 7125 7126 if (adapter->ixgbe_ieee_pfc) 7127 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7128 7129 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7130 hw->mac.ops.fc_enable(hw); 7131 ixgbe_set_rx_drop_en(adapter); 7132 } 7133 7134 if (link_up || 7135 time_after(jiffies, (adapter->link_check_timeout + 7136 IXGBE_TRY_LINK_TIMEOUT))) { 7137 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7138 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7139 IXGBE_WRITE_FLUSH(hw); 7140 } 7141 7142 adapter->link_up = link_up; 7143 adapter->link_speed = link_speed; 7144 } 7145 7146 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7147 { 7148 #ifdef CONFIG_IXGBE_DCB 7149 struct net_device *netdev = adapter->netdev; 7150 struct dcb_app app = { 7151 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7152 .protocol = 0, 7153 }; 7154 u8 up = 0; 7155 7156 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7157 up = dcb_ieee_getapp_mask(netdev, &app); 7158 7159 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7160 #endif 7161 } 7162 7163 static int ixgbe_enable_macvlan(struct net_device *upper, void *data) 7164 { 7165 if (netif_is_macvlan(upper)) { 7166 struct macvlan_dev *vlan = netdev_priv(upper); 7167 7168 if (vlan->fwd_priv) 7169 netif_tx_wake_all_queues(upper); 7170 } 7171 7172 return 0; 7173 } 7174 7175 /** 7176 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7177 * print link up message 7178 * @adapter: pointer to the device adapter structure 7179 **/ 7180 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7181 { 7182 struct net_device *netdev = adapter->netdev; 7183 struct ixgbe_hw *hw = &adapter->hw; 7184 u32 link_speed = adapter->link_speed; 7185 const char *speed_str; 7186 bool flow_rx, flow_tx; 7187 7188 /* only continue if link was previously down */ 7189 if (netif_carrier_ok(netdev)) 7190 return; 7191 7192 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7193 7194 switch (hw->mac.type) { 7195 case ixgbe_mac_82598EB: { 7196 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7197 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7198 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7199 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7200 } 7201 break; 7202 case ixgbe_mac_X540: 7203 case ixgbe_mac_X550: 7204 case ixgbe_mac_X550EM_x: 7205 case ixgbe_mac_x550em_a: 7206 case ixgbe_mac_82599EB: { 7207 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7208 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7209 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7210 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7211 } 7212 break; 7213 default: 7214 flow_tx = false; 7215 flow_rx = false; 7216 break; 7217 } 7218 7219 adapter->last_rx_ptp_check = jiffies; 7220 7221 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7222 ixgbe_ptp_start_cyclecounter(adapter); 7223 7224 switch (link_speed) { 7225 case IXGBE_LINK_SPEED_10GB_FULL: 7226 speed_str = "10 Gbps"; 7227 break; 7228 case IXGBE_LINK_SPEED_2_5GB_FULL: 7229 speed_str = "2.5 Gbps"; 7230 break; 7231 case IXGBE_LINK_SPEED_1GB_FULL: 7232 speed_str = "1 Gbps"; 7233 break; 7234 case IXGBE_LINK_SPEED_100_FULL: 7235 speed_str = "100 Mbps"; 7236 break; 7237 case IXGBE_LINK_SPEED_10_FULL: 7238 speed_str = "10 Mbps"; 7239 break; 7240 default: 7241 speed_str = "unknown speed"; 7242 break; 7243 } 7244 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7245 ((flow_rx && flow_tx) ? "RX/TX" : 7246 (flow_rx ? "RX" : 7247 (flow_tx ? "TX" : "None")))); 7248 7249 netif_carrier_on(netdev); 7250 ixgbe_check_vf_rate_limit(adapter); 7251 7252 /* enable transmits */ 7253 netif_tx_wake_all_queues(adapter->netdev); 7254 7255 /* enable any upper devices */ 7256 rtnl_lock(); 7257 netdev_walk_all_upper_dev_rcu(adapter->netdev, 7258 ixgbe_enable_macvlan, NULL); 7259 rtnl_unlock(); 7260 7261 /* update the default user priority for VFs */ 7262 ixgbe_update_default_up(adapter); 7263 7264 /* ping all the active vfs to let them know link has changed */ 7265 ixgbe_ping_all_vfs(adapter); 7266 } 7267 7268 /** 7269 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7270 * print link down message 7271 * @adapter: pointer to the adapter structure 7272 **/ 7273 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7274 { 7275 struct net_device *netdev = adapter->netdev; 7276 struct ixgbe_hw *hw = &adapter->hw; 7277 7278 adapter->link_up = false; 7279 adapter->link_speed = 0; 7280 7281 /* only continue if link was up previously */ 7282 if (!netif_carrier_ok(netdev)) 7283 return; 7284 7285 /* poll for SFP+ cable when link is down */ 7286 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7287 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7288 7289 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7290 ixgbe_ptp_start_cyclecounter(adapter); 7291 7292 e_info(drv, "NIC Link is Down\n"); 7293 netif_carrier_off(netdev); 7294 7295 /* ping all the active vfs to let them know link has changed */ 7296 ixgbe_ping_all_vfs(adapter); 7297 } 7298 7299 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7300 { 7301 int i; 7302 7303 for (i = 0; i < adapter->num_tx_queues; i++) { 7304 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7305 7306 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7307 return true; 7308 } 7309 7310 for (i = 0; i < adapter->num_xdp_queues; i++) { 7311 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7312 7313 if (ring->next_to_use != ring->next_to_clean) 7314 return true; 7315 } 7316 7317 return false; 7318 } 7319 7320 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7321 { 7322 struct ixgbe_hw *hw = &adapter->hw; 7323 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7324 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7325 7326 int i, j; 7327 7328 if (!adapter->num_vfs) 7329 return false; 7330 7331 /* resetting the PF is only needed for MAC before X550 */ 7332 if (hw->mac.type >= ixgbe_mac_X550) 7333 return false; 7334 7335 for (i = 0; i < adapter->num_vfs; i++) { 7336 for (j = 0; j < q_per_pool; j++) { 7337 u32 h, t; 7338 7339 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7340 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7341 7342 if (h != t) 7343 return true; 7344 } 7345 } 7346 7347 return false; 7348 } 7349 7350 /** 7351 * ixgbe_watchdog_flush_tx - flush queues on link down 7352 * @adapter: pointer to the device adapter structure 7353 **/ 7354 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7355 { 7356 if (!netif_carrier_ok(adapter->netdev)) { 7357 if (ixgbe_ring_tx_pending(adapter) || 7358 ixgbe_vf_tx_pending(adapter)) { 7359 /* We've lost link, so the controller stops DMA, 7360 * but we've got queued Tx work that's never going 7361 * to get done, so reset controller to flush Tx. 7362 * (Do the reset outside of interrupt context). 7363 */ 7364 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7365 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7366 } 7367 } 7368 } 7369 7370 #ifdef CONFIG_PCI_IOV 7371 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7372 { 7373 struct ixgbe_hw *hw = &adapter->hw; 7374 struct pci_dev *pdev = adapter->pdev; 7375 unsigned int vf; 7376 u32 gpc; 7377 7378 if (!(netif_carrier_ok(adapter->netdev))) 7379 return; 7380 7381 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7382 if (gpc) /* If incrementing then no need for the check below */ 7383 return; 7384 /* Check to see if a bad DMA write target from an errant or 7385 * malicious VF has caused a PCIe error. If so then we can 7386 * issue a VFLR to the offending VF(s) and then resume without 7387 * requesting a full slot reset. 7388 */ 7389 7390 if (!pdev) 7391 return; 7392 7393 /* check status reg for all VFs owned by this PF */ 7394 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7395 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7396 u16 status_reg; 7397 7398 if (!vfdev) 7399 continue; 7400 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7401 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7402 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7403 pcie_flr(vfdev); 7404 } 7405 } 7406 7407 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7408 { 7409 u32 ssvpc; 7410 7411 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7412 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7413 adapter->num_vfs == 0) 7414 return; 7415 7416 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7417 7418 /* 7419 * ssvpc register is cleared on read, if zero then no 7420 * spoofed packets in the last interval. 7421 */ 7422 if (!ssvpc) 7423 return; 7424 7425 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7426 } 7427 #else 7428 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7429 { 7430 } 7431 7432 static void 7433 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7434 { 7435 } 7436 #endif /* CONFIG_PCI_IOV */ 7437 7438 7439 /** 7440 * ixgbe_watchdog_subtask - check and bring link up 7441 * @adapter: pointer to the device adapter structure 7442 **/ 7443 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7444 { 7445 /* if interface is down, removing or resetting, do nothing */ 7446 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7447 test_bit(__IXGBE_REMOVING, &adapter->state) || 7448 test_bit(__IXGBE_RESETTING, &adapter->state)) 7449 return; 7450 7451 ixgbe_watchdog_update_link(adapter); 7452 7453 if (adapter->link_up) 7454 ixgbe_watchdog_link_is_up(adapter); 7455 else 7456 ixgbe_watchdog_link_is_down(adapter); 7457 7458 ixgbe_check_for_bad_vf(adapter); 7459 ixgbe_spoof_check(adapter); 7460 ixgbe_update_stats(adapter); 7461 7462 ixgbe_watchdog_flush_tx(adapter); 7463 } 7464 7465 /** 7466 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7467 * @adapter: the ixgbe adapter structure 7468 **/ 7469 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7470 { 7471 struct ixgbe_hw *hw = &adapter->hw; 7472 s32 err; 7473 7474 /* not searching for SFP so there is nothing to do here */ 7475 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7476 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7477 return; 7478 7479 if (adapter->sfp_poll_time && 7480 time_after(adapter->sfp_poll_time, jiffies)) 7481 return; /* If not yet time to poll for SFP */ 7482 7483 /* someone else is in init, wait until next service event */ 7484 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7485 return; 7486 7487 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7488 7489 err = hw->phy.ops.identify_sfp(hw); 7490 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7491 goto sfp_out; 7492 7493 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7494 /* If no cable is present, then we need to reset 7495 * the next time we find a good cable. */ 7496 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7497 } 7498 7499 /* exit on error */ 7500 if (err) 7501 goto sfp_out; 7502 7503 /* exit if reset not needed */ 7504 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7505 goto sfp_out; 7506 7507 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7508 7509 /* 7510 * A module may be identified correctly, but the EEPROM may not have 7511 * support for that module. setup_sfp() will fail in that case, so 7512 * we should not allow that module to load. 7513 */ 7514 if (hw->mac.type == ixgbe_mac_82598EB) 7515 err = hw->phy.ops.reset(hw); 7516 else 7517 err = hw->mac.ops.setup_sfp(hw); 7518 7519 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7520 goto sfp_out; 7521 7522 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7523 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7524 7525 sfp_out: 7526 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7527 7528 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7529 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7530 e_dev_err("failed to initialize because an unsupported " 7531 "SFP+ module type was detected.\n"); 7532 e_dev_err("Reload the driver after installing a " 7533 "supported module.\n"); 7534 unregister_netdev(adapter->netdev); 7535 } 7536 } 7537 7538 /** 7539 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7540 * @adapter: the ixgbe adapter structure 7541 **/ 7542 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7543 { 7544 struct ixgbe_hw *hw = &adapter->hw; 7545 u32 speed; 7546 bool autoneg = false; 7547 7548 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7549 return; 7550 7551 /* someone else is in init, wait until next service event */ 7552 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7553 return; 7554 7555 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7556 7557 speed = hw->phy.autoneg_advertised; 7558 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 7559 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 7560 7561 /* setup the highest link when no autoneg */ 7562 if (!autoneg) { 7563 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 7564 speed = IXGBE_LINK_SPEED_10GB_FULL; 7565 } 7566 } 7567 7568 if (hw->mac.ops.setup_link) 7569 hw->mac.ops.setup_link(hw, speed, true); 7570 7571 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7572 adapter->link_check_timeout = jiffies; 7573 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7574 } 7575 7576 /** 7577 * ixgbe_service_timer - Timer Call-back 7578 * @data: pointer to adapter cast into an unsigned long 7579 **/ 7580 static void ixgbe_service_timer(unsigned long data) 7581 { 7582 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 7583 unsigned long next_event_offset; 7584 7585 /* poll faster when waiting for link */ 7586 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7587 next_event_offset = HZ / 10; 7588 else 7589 next_event_offset = HZ * 2; 7590 7591 /* Reset the timer */ 7592 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7593 7594 ixgbe_service_event_schedule(adapter); 7595 } 7596 7597 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7598 { 7599 struct ixgbe_hw *hw = &adapter->hw; 7600 u32 status; 7601 7602 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7603 return; 7604 7605 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7606 7607 if (!hw->phy.ops.handle_lasi) 7608 return; 7609 7610 status = hw->phy.ops.handle_lasi(&adapter->hw); 7611 if (status != IXGBE_ERR_OVERTEMP) 7612 return; 7613 7614 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7615 } 7616 7617 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7618 { 7619 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7620 return; 7621 7622 /* If we're already down, removing or resetting, just bail */ 7623 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7624 test_bit(__IXGBE_REMOVING, &adapter->state) || 7625 test_bit(__IXGBE_RESETTING, &adapter->state)) 7626 return; 7627 7628 ixgbe_dump(adapter); 7629 netdev_err(adapter->netdev, "Reset adapter\n"); 7630 adapter->tx_timeout_count++; 7631 7632 rtnl_lock(); 7633 ixgbe_reinit_locked(adapter); 7634 rtnl_unlock(); 7635 } 7636 7637 /** 7638 * ixgbe_service_task - manages and runs subtasks 7639 * @work: pointer to work_struct containing our data 7640 **/ 7641 static void ixgbe_service_task(struct work_struct *work) 7642 { 7643 struct ixgbe_adapter *adapter = container_of(work, 7644 struct ixgbe_adapter, 7645 service_task); 7646 if (ixgbe_removed(adapter->hw.hw_addr)) { 7647 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7648 rtnl_lock(); 7649 ixgbe_down(adapter); 7650 rtnl_unlock(); 7651 } 7652 ixgbe_service_event_complete(adapter); 7653 return; 7654 } 7655 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7656 rtnl_lock(); 7657 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7658 udp_tunnel_get_rx_info(adapter->netdev); 7659 rtnl_unlock(); 7660 } 7661 ixgbe_reset_subtask(adapter); 7662 ixgbe_phy_interrupt_subtask(adapter); 7663 ixgbe_sfp_detection_subtask(adapter); 7664 ixgbe_sfp_link_config_subtask(adapter); 7665 ixgbe_check_overtemp_subtask(adapter); 7666 ixgbe_watchdog_subtask(adapter); 7667 ixgbe_fdir_reinit_subtask(adapter); 7668 ixgbe_check_hang_subtask(adapter); 7669 7670 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7671 ixgbe_ptp_overflow_check(adapter); 7672 ixgbe_ptp_rx_hang(adapter); 7673 ixgbe_ptp_tx_hang(adapter); 7674 } 7675 7676 ixgbe_service_event_complete(adapter); 7677 } 7678 7679 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7680 struct ixgbe_tx_buffer *first, 7681 u8 *hdr_len) 7682 { 7683 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7684 struct sk_buff *skb = first->skb; 7685 union { 7686 struct iphdr *v4; 7687 struct ipv6hdr *v6; 7688 unsigned char *hdr; 7689 } ip; 7690 union { 7691 struct tcphdr *tcp; 7692 unsigned char *hdr; 7693 } l4; 7694 u32 paylen, l4_offset; 7695 int err; 7696 7697 if (skb->ip_summed != CHECKSUM_PARTIAL) 7698 return 0; 7699 7700 if (!skb_is_gso(skb)) 7701 return 0; 7702 7703 err = skb_cow_head(skb, 0); 7704 if (err < 0) 7705 return err; 7706 7707 if (eth_p_mpls(first->protocol)) 7708 ip.hdr = skb_inner_network_header(skb); 7709 else 7710 ip.hdr = skb_network_header(skb); 7711 l4.hdr = skb_checksum_start(skb); 7712 7713 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7714 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7715 7716 /* initialize outer IP header fields */ 7717 if (ip.v4->version == 4) { 7718 unsigned char *csum_start = skb_checksum_start(skb); 7719 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7720 7721 /* IP header will have to cancel out any data that 7722 * is not a part of the outer IP header 7723 */ 7724 ip.v4->check = csum_fold(csum_partial(trans_start, 7725 csum_start - trans_start, 7726 0)); 7727 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7728 7729 ip.v4->tot_len = 0; 7730 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7731 IXGBE_TX_FLAGS_CSUM | 7732 IXGBE_TX_FLAGS_IPV4; 7733 } else { 7734 ip.v6->payload_len = 0; 7735 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7736 IXGBE_TX_FLAGS_CSUM; 7737 } 7738 7739 /* determine offset of inner transport header */ 7740 l4_offset = l4.hdr - skb->data; 7741 7742 /* compute length of segmentation header */ 7743 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7744 7745 /* remove payload length from inner checksum */ 7746 paylen = skb->len - l4_offset; 7747 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7748 7749 /* update gso size and bytecount with header size */ 7750 first->gso_segs = skb_shinfo(skb)->gso_segs; 7751 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7752 7753 /* mss_l4len_id: use 0 as index for TSO */ 7754 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7755 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7756 7757 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7758 vlan_macip_lens = l4.hdr - ip.hdr; 7759 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7760 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7761 7762 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 7763 mss_l4len_idx); 7764 7765 return 1; 7766 } 7767 7768 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7769 { 7770 unsigned int offset = 0; 7771 7772 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7773 7774 return offset == skb_checksum_start_offset(skb); 7775 } 7776 7777 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7778 struct ixgbe_tx_buffer *first) 7779 { 7780 struct sk_buff *skb = first->skb; 7781 u32 vlan_macip_lens = 0; 7782 u32 type_tucmd = 0; 7783 7784 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7785 csum_failed: 7786 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7787 IXGBE_TX_FLAGS_CC))) 7788 return; 7789 goto no_csum; 7790 } 7791 7792 switch (skb->csum_offset) { 7793 case offsetof(struct tcphdr, check): 7794 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7795 /* fall through */ 7796 case offsetof(struct udphdr, check): 7797 break; 7798 case offsetof(struct sctphdr, checksum): 7799 /* validate that this is actually an SCTP request */ 7800 if (((first->protocol == htons(ETH_P_IP)) && 7801 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7802 ((first->protocol == htons(ETH_P_IPV6)) && 7803 ixgbe_ipv6_csum_is_sctp(skb))) { 7804 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7805 break; 7806 } 7807 /* fall through */ 7808 default: 7809 skb_checksum_help(skb); 7810 goto csum_failed; 7811 } 7812 7813 /* update TX checksum flag */ 7814 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7815 vlan_macip_lens = skb_checksum_start_offset(skb) - 7816 skb_network_offset(skb); 7817 no_csum: 7818 /* vlan_macip_lens: MACLEN, VLAN tag */ 7819 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7820 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7821 7822 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0); 7823 } 7824 7825 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7826 ((_flag <= _result) ? \ 7827 ((u32)(_input & _flag) * (_result / _flag)) : \ 7828 ((u32)(_input & _flag) / (_flag / _result))) 7829 7830 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7831 { 7832 /* set type for advanced descriptor with frame checksum insertion */ 7833 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7834 IXGBE_ADVTXD_DCMD_DEXT | 7835 IXGBE_ADVTXD_DCMD_IFCS; 7836 7837 /* set HW vlan bit if vlan is present */ 7838 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7839 IXGBE_ADVTXD_DCMD_VLE); 7840 7841 /* set segmentation enable bits for TSO/FSO */ 7842 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7843 IXGBE_ADVTXD_DCMD_TSE); 7844 7845 /* set timestamp bit if present */ 7846 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7847 IXGBE_ADVTXD_MAC_TSTAMP); 7848 7849 /* insert frame checksum */ 7850 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7851 7852 return cmd_type; 7853 } 7854 7855 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7856 u32 tx_flags, unsigned int paylen) 7857 { 7858 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7859 7860 /* enable L4 checksum for TSO and TX checksum offload */ 7861 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7862 IXGBE_TX_FLAGS_CSUM, 7863 IXGBE_ADVTXD_POPTS_TXSM); 7864 7865 /* enble IPv4 checksum for TSO */ 7866 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7867 IXGBE_TX_FLAGS_IPV4, 7868 IXGBE_ADVTXD_POPTS_IXSM); 7869 7870 /* 7871 * Check Context must be set if Tx switch is enabled, which it 7872 * always is for case where virtual functions are running 7873 */ 7874 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7875 IXGBE_TX_FLAGS_CC, 7876 IXGBE_ADVTXD_CC); 7877 7878 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7879 } 7880 7881 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7882 { 7883 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7884 7885 /* Herbert's original patch had: 7886 * smp_mb__after_netif_stop_queue(); 7887 * but since that doesn't exist yet, just open code it. 7888 */ 7889 smp_mb(); 7890 7891 /* We need to check again in a case another CPU has just 7892 * made room available. 7893 */ 7894 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7895 return -EBUSY; 7896 7897 /* A reprieve! - use start_queue because it doesn't call schedule */ 7898 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7899 ++tx_ring->tx_stats.restart_queue; 7900 return 0; 7901 } 7902 7903 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7904 { 7905 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7906 return 0; 7907 7908 return __ixgbe_maybe_stop_tx(tx_ring, size); 7909 } 7910 7911 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7912 IXGBE_TXD_CMD_RS) 7913 7914 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7915 struct ixgbe_tx_buffer *first, 7916 const u8 hdr_len) 7917 { 7918 struct sk_buff *skb = first->skb; 7919 struct ixgbe_tx_buffer *tx_buffer; 7920 union ixgbe_adv_tx_desc *tx_desc; 7921 struct skb_frag_struct *frag; 7922 dma_addr_t dma; 7923 unsigned int data_len, size; 7924 u32 tx_flags = first->tx_flags; 7925 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7926 u16 i = tx_ring->next_to_use; 7927 7928 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7929 7930 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7931 7932 size = skb_headlen(skb); 7933 data_len = skb->data_len; 7934 7935 #ifdef IXGBE_FCOE 7936 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7937 if (data_len < sizeof(struct fcoe_crc_eof)) { 7938 size -= sizeof(struct fcoe_crc_eof) - data_len; 7939 data_len = 0; 7940 } else { 7941 data_len -= sizeof(struct fcoe_crc_eof); 7942 } 7943 } 7944 7945 #endif 7946 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7947 7948 tx_buffer = first; 7949 7950 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7951 if (dma_mapping_error(tx_ring->dev, dma)) 7952 goto dma_error; 7953 7954 /* record length, and DMA address */ 7955 dma_unmap_len_set(tx_buffer, len, size); 7956 dma_unmap_addr_set(tx_buffer, dma, dma); 7957 7958 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7959 7960 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7961 tx_desc->read.cmd_type_len = 7962 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7963 7964 i++; 7965 tx_desc++; 7966 if (i == tx_ring->count) { 7967 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7968 i = 0; 7969 } 7970 tx_desc->read.olinfo_status = 0; 7971 7972 dma += IXGBE_MAX_DATA_PER_TXD; 7973 size -= IXGBE_MAX_DATA_PER_TXD; 7974 7975 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7976 } 7977 7978 if (likely(!data_len)) 7979 break; 7980 7981 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7982 7983 i++; 7984 tx_desc++; 7985 if (i == tx_ring->count) { 7986 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7987 i = 0; 7988 } 7989 tx_desc->read.olinfo_status = 0; 7990 7991 #ifdef IXGBE_FCOE 7992 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7993 #else 7994 size = skb_frag_size(frag); 7995 #endif 7996 data_len -= size; 7997 7998 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7999 DMA_TO_DEVICE); 8000 8001 tx_buffer = &tx_ring->tx_buffer_info[i]; 8002 } 8003 8004 /* write last descriptor with RS and EOP bits */ 8005 cmd_type |= size | IXGBE_TXD_CMD; 8006 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8007 8008 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8009 8010 /* set the timestamp */ 8011 first->time_stamp = jiffies; 8012 8013 /* 8014 * Force memory writes to complete before letting h/w know there 8015 * are new descriptors to fetch. (Only applicable for weak-ordered 8016 * memory model archs, such as IA-64). 8017 * 8018 * We also need this memory barrier to make certain all of the 8019 * status bits have been updated before next_to_watch is written. 8020 */ 8021 wmb(); 8022 8023 /* set next_to_watch value indicating a packet is present */ 8024 first->next_to_watch = tx_desc; 8025 8026 i++; 8027 if (i == tx_ring->count) 8028 i = 0; 8029 8030 tx_ring->next_to_use = i; 8031 8032 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8033 8034 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8035 writel(i, tx_ring->tail); 8036 8037 /* we need this if more than one processor can write to our tail 8038 * at a time, it synchronizes IO on IA64/Altix systems 8039 */ 8040 mmiowb(); 8041 } 8042 8043 return 0; 8044 dma_error: 8045 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8046 tx_buffer = &tx_ring->tx_buffer_info[i]; 8047 8048 /* clear dma mappings for failed tx_buffer_info map */ 8049 while (tx_buffer != first) { 8050 if (dma_unmap_len(tx_buffer, len)) 8051 dma_unmap_page(tx_ring->dev, 8052 dma_unmap_addr(tx_buffer, dma), 8053 dma_unmap_len(tx_buffer, len), 8054 DMA_TO_DEVICE); 8055 dma_unmap_len_set(tx_buffer, len, 0); 8056 8057 if (i--) 8058 i += tx_ring->count; 8059 tx_buffer = &tx_ring->tx_buffer_info[i]; 8060 } 8061 8062 if (dma_unmap_len(tx_buffer, len)) 8063 dma_unmap_single(tx_ring->dev, 8064 dma_unmap_addr(tx_buffer, dma), 8065 dma_unmap_len(tx_buffer, len), 8066 DMA_TO_DEVICE); 8067 dma_unmap_len_set(tx_buffer, len, 0); 8068 8069 dev_kfree_skb_any(first->skb); 8070 first->skb = NULL; 8071 8072 tx_ring->next_to_use = i; 8073 8074 return -1; 8075 } 8076 8077 static void ixgbe_atr(struct ixgbe_ring *ring, 8078 struct ixgbe_tx_buffer *first) 8079 { 8080 struct ixgbe_q_vector *q_vector = ring->q_vector; 8081 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8082 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8083 union { 8084 unsigned char *network; 8085 struct iphdr *ipv4; 8086 struct ipv6hdr *ipv6; 8087 } hdr; 8088 struct tcphdr *th; 8089 unsigned int hlen; 8090 struct sk_buff *skb; 8091 __be16 vlan_id; 8092 int l4_proto; 8093 8094 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8095 if (!q_vector) 8096 return; 8097 8098 /* do nothing if sampling is disabled */ 8099 if (!ring->atr_sample_rate) 8100 return; 8101 8102 ring->atr_count++; 8103 8104 /* currently only IPv4/IPv6 with TCP is supported */ 8105 if ((first->protocol != htons(ETH_P_IP)) && 8106 (first->protocol != htons(ETH_P_IPV6))) 8107 return; 8108 8109 /* snag network header to get L4 type and address */ 8110 skb = first->skb; 8111 hdr.network = skb_network_header(skb); 8112 if (unlikely(hdr.network <= skb->data)) 8113 return; 8114 if (skb->encapsulation && 8115 first->protocol == htons(ETH_P_IP) && 8116 hdr.ipv4->protocol == IPPROTO_UDP) { 8117 struct ixgbe_adapter *adapter = q_vector->adapter; 8118 8119 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8120 VXLAN_HEADROOM)) 8121 return; 8122 8123 /* verify the port is recognized as VXLAN */ 8124 if (adapter->vxlan_port && 8125 udp_hdr(skb)->dest == adapter->vxlan_port) 8126 hdr.network = skb_inner_network_header(skb); 8127 8128 if (adapter->geneve_port && 8129 udp_hdr(skb)->dest == adapter->geneve_port) 8130 hdr.network = skb_inner_network_header(skb); 8131 } 8132 8133 /* Make sure we have at least [minimum IPv4 header + TCP] 8134 * or [IPv6 header] bytes 8135 */ 8136 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8137 return; 8138 8139 /* Currently only IPv4/IPv6 with TCP is supported */ 8140 switch (hdr.ipv4->version) { 8141 case IPVERSION: 8142 /* access ihl as u8 to avoid unaligned access on ia64 */ 8143 hlen = (hdr.network[0] & 0x0F) << 2; 8144 l4_proto = hdr.ipv4->protocol; 8145 break; 8146 case 6: 8147 hlen = hdr.network - skb->data; 8148 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8149 hlen -= hdr.network - skb->data; 8150 break; 8151 default: 8152 return; 8153 } 8154 8155 if (l4_proto != IPPROTO_TCP) 8156 return; 8157 8158 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8159 hlen + sizeof(struct tcphdr))) 8160 return; 8161 8162 th = (struct tcphdr *)(hdr.network + hlen); 8163 8164 /* skip this packet since the socket is closing */ 8165 if (th->fin) 8166 return; 8167 8168 /* sample on all syn packets or once every atr sample count */ 8169 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8170 return; 8171 8172 /* reset sample count */ 8173 ring->atr_count = 0; 8174 8175 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8176 8177 /* 8178 * src and dst are inverted, think how the receiver sees them 8179 * 8180 * The input is broken into two sections, a non-compressed section 8181 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8182 * is XORed together and stored in the compressed dword. 8183 */ 8184 input.formatted.vlan_id = vlan_id; 8185 8186 /* 8187 * since src port and flex bytes occupy the same word XOR them together 8188 * and write the value to source port portion of compressed dword 8189 */ 8190 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8191 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8192 else 8193 common.port.src ^= th->dest ^ first->protocol; 8194 common.port.dst ^= th->source; 8195 8196 switch (hdr.ipv4->version) { 8197 case IPVERSION: 8198 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8199 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8200 break; 8201 case 6: 8202 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8203 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8204 hdr.ipv6->saddr.s6_addr32[1] ^ 8205 hdr.ipv6->saddr.s6_addr32[2] ^ 8206 hdr.ipv6->saddr.s6_addr32[3] ^ 8207 hdr.ipv6->daddr.s6_addr32[0] ^ 8208 hdr.ipv6->daddr.s6_addr32[1] ^ 8209 hdr.ipv6->daddr.s6_addr32[2] ^ 8210 hdr.ipv6->daddr.s6_addr32[3]; 8211 break; 8212 default: 8213 break; 8214 } 8215 8216 if (hdr.network != skb_network_header(skb)) 8217 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8218 8219 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8220 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8221 input, common, ring->queue_index); 8222 } 8223 8224 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8225 void *accel_priv, select_queue_fallback_t fallback) 8226 { 8227 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8228 #ifdef IXGBE_FCOE 8229 struct ixgbe_adapter *adapter; 8230 struct ixgbe_ring_feature *f; 8231 int txq; 8232 #endif 8233 8234 if (fwd_adapter) 8235 return skb->queue_mapping + fwd_adapter->tx_base_queue; 8236 8237 #ifdef IXGBE_FCOE 8238 8239 /* 8240 * only execute the code below if protocol is FCoE 8241 * or FIP and we have FCoE enabled on the adapter 8242 */ 8243 switch (vlan_get_protocol(skb)) { 8244 case htons(ETH_P_FCOE): 8245 case htons(ETH_P_FIP): 8246 adapter = netdev_priv(dev); 8247 8248 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8249 break; 8250 /* fall through */ 8251 default: 8252 return fallback(dev, skb); 8253 } 8254 8255 f = &adapter->ring_feature[RING_F_FCOE]; 8256 8257 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8258 smp_processor_id(); 8259 8260 while (txq >= f->indices) 8261 txq -= f->indices; 8262 8263 return txq + f->offset; 8264 #else 8265 return fallback(dev, skb); 8266 #endif 8267 } 8268 8269 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8270 struct xdp_buff *xdp) 8271 { 8272 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8273 struct ixgbe_tx_buffer *tx_buffer; 8274 union ixgbe_adv_tx_desc *tx_desc; 8275 u32 len, cmd_type; 8276 dma_addr_t dma; 8277 u16 i; 8278 8279 len = xdp->data_end - xdp->data; 8280 8281 if (unlikely(!ixgbe_desc_unused(ring))) 8282 return IXGBE_XDP_CONSUMED; 8283 8284 dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE); 8285 if (dma_mapping_error(ring->dev, dma)) 8286 return IXGBE_XDP_CONSUMED; 8287 8288 /* record the location of the first descriptor for this packet */ 8289 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8290 tx_buffer->bytecount = len; 8291 tx_buffer->gso_segs = 1; 8292 tx_buffer->protocol = 0; 8293 8294 i = ring->next_to_use; 8295 tx_desc = IXGBE_TX_DESC(ring, i); 8296 8297 dma_unmap_len_set(tx_buffer, len, len); 8298 dma_unmap_addr_set(tx_buffer, dma, dma); 8299 tx_buffer->data = xdp->data; 8300 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8301 8302 /* put descriptor type bits */ 8303 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8304 IXGBE_ADVTXD_DCMD_DEXT | 8305 IXGBE_ADVTXD_DCMD_IFCS; 8306 cmd_type |= len | IXGBE_TXD_CMD; 8307 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8308 tx_desc->read.olinfo_status = 8309 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8310 8311 /* Avoid any potential race with xdp_xmit and cleanup */ 8312 smp_wmb(); 8313 8314 /* set next_to_watch value indicating a packet is present */ 8315 i++; 8316 if (i == ring->count) 8317 i = 0; 8318 8319 tx_buffer->next_to_watch = tx_desc; 8320 ring->next_to_use = i; 8321 8322 return IXGBE_XDP_TX; 8323 } 8324 8325 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8326 struct ixgbe_adapter *adapter, 8327 struct ixgbe_ring *tx_ring) 8328 { 8329 struct ixgbe_tx_buffer *first; 8330 int tso; 8331 u32 tx_flags = 0; 8332 unsigned short f; 8333 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8334 __be16 protocol = skb->protocol; 8335 u8 hdr_len = 0; 8336 8337 /* 8338 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8339 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8340 * + 2 desc gap to keep tail from touching head, 8341 * + 1 desc for context descriptor, 8342 * otherwise try next time 8343 */ 8344 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8345 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8346 8347 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8348 tx_ring->tx_stats.tx_busy++; 8349 return NETDEV_TX_BUSY; 8350 } 8351 8352 /* record the location of the first descriptor for this packet */ 8353 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8354 first->skb = skb; 8355 first->bytecount = skb->len; 8356 first->gso_segs = 1; 8357 8358 /* if we have a HW VLAN tag being added default to the HW one */ 8359 if (skb_vlan_tag_present(skb)) { 8360 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8361 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8362 /* else if it is a SW VLAN check the next protocol and store the tag */ 8363 } else if (protocol == htons(ETH_P_8021Q)) { 8364 struct vlan_hdr *vhdr, _vhdr; 8365 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8366 if (!vhdr) 8367 goto out_drop; 8368 8369 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8370 IXGBE_TX_FLAGS_VLAN_SHIFT; 8371 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8372 } 8373 protocol = vlan_get_protocol(skb); 8374 8375 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8376 adapter->ptp_clock) { 8377 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8378 &adapter->state)) { 8379 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8380 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8381 8382 /* schedule check for Tx timestamp */ 8383 adapter->ptp_tx_skb = skb_get(skb); 8384 adapter->ptp_tx_start = jiffies; 8385 schedule_work(&adapter->ptp_tx_work); 8386 } else { 8387 adapter->tx_hwtstamp_skipped++; 8388 } 8389 } 8390 8391 skb_tx_timestamp(skb); 8392 8393 #ifdef CONFIG_PCI_IOV 8394 /* 8395 * Use the l2switch_enable flag - would be false if the DMA 8396 * Tx switch had been disabled. 8397 */ 8398 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8399 tx_flags |= IXGBE_TX_FLAGS_CC; 8400 8401 #endif 8402 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8403 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8404 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8405 (skb->priority != TC_PRIO_CONTROL))) { 8406 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8407 tx_flags |= (skb->priority & 0x7) << 8408 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8409 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8410 struct vlan_ethhdr *vhdr; 8411 8412 if (skb_cow_head(skb, 0)) 8413 goto out_drop; 8414 vhdr = (struct vlan_ethhdr *)skb->data; 8415 vhdr->h_vlan_TCI = htons(tx_flags >> 8416 IXGBE_TX_FLAGS_VLAN_SHIFT); 8417 } else { 8418 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8419 } 8420 } 8421 8422 /* record initial flags and protocol */ 8423 first->tx_flags = tx_flags; 8424 first->protocol = protocol; 8425 8426 #ifdef IXGBE_FCOE 8427 /* setup tx offload for FCoE */ 8428 if ((protocol == htons(ETH_P_FCOE)) && 8429 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8430 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8431 if (tso < 0) 8432 goto out_drop; 8433 8434 goto xmit_fcoe; 8435 } 8436 8437 #endif /* IXGBE_FCOE */ 8438 tso = ixgbe_tso(tx_ring, first, &hdr_len); 8439 if (tso < 0) 8440 goto out_drop; 8441 else if (!tso) 8442 ixgbe_tx_csum(tx_ring, first); 8443 8444 /* add the ATR filter if ATR is on */ 8445 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8446 ixgbe_atr(tx_ring, first); 8447 8448 #ifdef IXGBE_FCOE 8449 xmit_fcoe: 8450 #endif /* IXGBE_FCOE */ 8451 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8452 goto cleanup_tx_timestamp; 8453 8454 return NETDEV_TX_OK; 8455 8456 out_drop: 8457 dev_kfree_skb_any(first->skb); 8458 first->skb = NULL; 8459 cleanup_tx_timestamp: 8460 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8461 dev_kfree_skb_any(adapter->ptp_tx_skb); 8462 adapter->ptp_tx_skb = NULL; 8463 cancel_work_sync(&adapter->ptp_tx_work); 8464 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8465 } 8466 8467 return NETDEV_TX_OK; 8468 } 8469 8470 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8471 struct net_device *netdev, 8472 struct ixgbe_ring *ring) 8473 { 8474 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8475 struct ixgbe_ring *tx_ring; 8476 8477 /* 8478 * The minimum packet size for olinfo paylen is 17 so pad the skb 8479 * in order to meet this minimum size requirement. 8480 */ 8481 if (skb_put_padto(skb, 17)) 8482 return NETDEV_TX_OK; 8483 8484 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8485 8486 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8487 } 8488 8489 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8490 struct net_device *netdev) 8491 { 8492 return __ixgbe_xmit_frame(skb, netdev, NULL); 8493 } 8494 8495 /** 8496 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8497 * @netdev: network interface device structure 8498 * @p: pointer to an address structure 8499 * 8500 * Returns 0 on success, negative on failure 8501 **/ 8502 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8503 { 8504 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8505 struct ixgbe_hw *hw = &adapter->hw; 8506 struct sockaddr *addr = p; 8507 8508 if (!is_valid_ether_addr(addr->sa_data)) 8509 return -EADDRNOTAVAIL; 8510 8511 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8512 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8513 8514 ixgbe_mac_set_default_filter(adapter); 8515 8516 return 0; 8517 } 8518 8519 static int 8520 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8521 { 8522 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8523 struct ixgbe_hw *hw = &adapter->hw; 8524 u16 value; 8525 int rc; 8526 8527 if (prtad != hw->phy.mdio.prtad) 8528 return -EINVAL; 8529 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8530 if (!rc) 8531 rc = value; 8532 return rc; 8533 } 8534 8535 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8536 u16 addr, u16 value) 8537 { 8538 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8539 struct ixgbe_hw *hw = &adapter->hw; 8540 8541 if (prtad != hw->phy.mdio.prtad) 8542 return -EINVAL; 8543 return hw->phy.ops.write_reg(hw, addr, devad, value); 8544 } 8545 8546 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8547 { 8548 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8549 8550 switch (cmd) { 8551 case SIOCSHWTSTAMP: 8552 return ixgbe_ptp_set_ts_config(adapter, req); 8553 case SIOCGHWTSTAMP: 8554 return ixgbe_ptp_get_ts_config(adapter, req); 8555 default: 8556 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8557 } 8558 } 8559 8560 /** 8561 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8562 * netdev->dev_addrs 8563 * @netdev: network interface device structure 8564 * 8565 * Returns non-zero on failure 8566 **/ 8567 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8568 { 8569 int err = 0; 8570 struct ixgbe_adapter *adapter = netdev_priv(dev); 8571 struct ixgbe_hw *hw = &adapter->hw; 8572 8573 if (is_valid_ether_addr(hw->mac.san_addr)) { 8574 rtnl_lock(); 8575 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8576 rtnl_unlock(); 8577 8578 /* update SAN MAC vmdq pool selection */ 8579 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8580 } 8581 return err; 8582 } 8583 8584 /** 8585 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8586 * netdev->dev_addrs 8587 * @netdev: network interface device structure 8588 * 8589 * Returns non-zero on failure 8590 **/ 8591 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8592 { 8593 int err = 0; 8594 struct ixgbe_adapter *adapter = netdev_priv(dev); 8595 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8596 8597 if (is_valid_ether_addr(mac->san_addr)) { 8598 rtnl_lock(); 8599 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8600 rtnl_unlock(); 8601 } 8602 return err; 8603 } 8604 8605 #ifdef CONFIG_NET_POLL_CONTROLLER 8606 /* 8607 * Polling 'interrupt' - used by things like netconsole to send skbs 8608 * without having to re-enable interrupts. It's not called while 8609 * the interrupt routine is executing. 8610 */ 8611 static void ixgbe_netpoll(struct net_device *netdev) 8612 { 8613 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8614 int i; 8615 8616 /* if interface is down do nothing */ 8617 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8618 return; 8619 8620 /* loop through and schedule all active queues */ 8621 for (i = 0; i < adapter->num_q_vectors; i++) 8622 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8623 } 8624 8625 #endif 8626 8627 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8628 struct ixgbe_ring *ring) 8629 { 8630 u64 bytes, packets; 8631 unsigned int start; 8632 8633 if (ring) { 8634 do { 8635 start = u64_stats_fetch_begin_irq(&ring->syncp); 8636 packets = ring->stats.packets; 8637 bytes = ring->stats.bytes; 8638 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8639 stats->tx_packets += packets; 8640 stats->tx_bytes += bytes; 8641 } 8642 } 8643 8644 static void ixgbe_get_stats64(struct net_device *netdev, 8645 struct rtnl_link_stats64 *stats) 8646 { 8647 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8648 int i; 8649 8650 rcu_read_lock(); 8651 for (i = 0; i < adapter->num_rx_queues; i++) { 8652 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 8653 u64 bytes, packets; 8654 unsigned int start; 8655 8656 if (ring) { 8657 do { 8658 start = u64_stats_fetch_begin_irq(&ring->syncp); 8659 packets = ring->stats.packets; 8660 bytes = ring->stats.bytes; 8661 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8662 stats->rx_packets += packets; 8663 stats->rx_bytes += bytes; 8664 } 8665 } 8666 8667 for (i = 0; i < adapter->num_tx_queues; i++) { 8668 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 8669 8670 ixgbe_get_ring_stats64(stats, ring); 8671 } 8672 for (i = 0; i < adapter->num_xdp_queues; i++) { 8673 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->xdp_ring[i]); 8674 8675 ixgbe_get_ring_stats64(stats, ring); 8676 } 8677 rcu_read_unlock(); 8678 8679 /* following stats updated by ixgbe_watchdog_task() */ 8680 stats->multicast = netdev->stats.multicast; 8681 stats->rx_errors = netdev->stats.rx_errors; 8682 stats->rx_length_errors = netdev->stats.rx_length_errors; 8683 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8684 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8685 } 8686 8687 #ifdef CONFIG_IXGBE_DCB 8688 /** 8689 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8690 * @adapter: pointer to ixgbe_adapter 8691 * @tc: number of traffic classes currently enabled 8692 * 8693 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8694 * 802.1Q priority maps to a packet buffer that exists. 8695 */ 8696 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8697 { 8698 struct ixgbe_hw *hw = &adapter->hw; 8699 u32 reg, rsave; 8700 int i; 8701 8702 /* 82598 have a static priority to TC mapping that can not 8703 * be changed so no validation is needed. 8704 */ 8705 if (hw->mac.type == ixgbe_mac_82598EB) 8706 return; 8707 8708 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8709 rsave = reg; 8710 8711 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8712 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8713 8714 /* If up2tc is out of bounds default to zero */ 8715 if (up2tc > tc) 8716 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8717 } 8718 8719 if (reg != rsave) 8720 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8721 8722 return; 8723 } 8724 8725 /** 8726 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8727 * @adapter: Pointer to adapter struct 8728 * 8729 * Populate the netdev user priority to tc map 8730 */ 8731 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8732 { 8733 struct net_device *dev = adapter->netdev; 8734 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8735 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8736 u8 prio; 8737 8738 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8739 u8 tc = 0; 8740 8741 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8742 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8743 else if (ets) 8744 tc = ets->prio_tc[prio]; 8745 8746 netdev_set_prio_tc_map(dev, prio, tc); 8747 } 8748 } 8749 8750 #endif /* CONFIG_IXGBE_DCB */ 8751 /** 8752 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8753 * 8754 * @netdev: net device to configure 8755 * @tc: number of traffic classes to enable 8756 */ 8757 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8758 { 8759 struct ixgbe_adapter *adapter = netdev_priv(dev); 8760 struct ixgbe_hw *hw = &adapter->hw; 8761 bool pools; 8762 8763 /* Hardware supports up to 8 traffic classes */ 8764 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8765 return -EINVAL; 8766 8767 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8768 return -EINVAL; 8769 8770 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 8771 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 8772 return -EBUSY; 8773 8774 /* Hardware has to reinitialize queues and interrupts to 8775 * match packet buffer alignment. Unfortunately, the 8776 * hardware is not flexible enough to do this dynamically. 8777 */ 8778 if (netif_running(dev)) 8779 ixgbe_close(dev); 8780 else 8781 ixgbe_reset(adapter); 8782 8783 ixgbe_clear_interrupt_scheme(adapter); 8784 8785 #ifdef CONFIG_IXGBE_DCB 8786 if (tc) { 8787 netdev_set_num_tc(dev, tc); 8788 ixgbe_set_prio_tc_map(adapter); 8789 8790 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8791 8792 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8793 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8794 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8795 } 8796 } else { 8797 netdev_reset_tc(dev); 8798 8799 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8800 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8801 8802 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8803 8804 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8805 adapter->dcb_cfg.pfc_mode_enable = false; 8806 } 8807 8808 ixgbe_validate_rtr(adapter, tc); 8809 8810 #endif /* CONFIG_IXGBE_DCB */ 8811 ixgbe_init_interrupt_scheme(adapter); 8812 8813 if (netif_running(dev)) 8814 return ixgbe_open(dev); 8815 8816 return 0; 8817 } 8818 8819 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8820 struct tc_cls_u32_offload *cls) 8821 { 8822 u32 hdl = cls->knode.handle; 8823 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8824 u32 loc = cls->knode.handle & 0xfffff; 8825 int err = 0, i, j; 8826 struct ixgbe_jump_table *jump = NULL; 8827 8828 if (loc > IXGBE_MAX_HW_ENTRIES) 8829 return -EINVAL; 8830 8831 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8832 return -EINVAL; 8833 8834 /* Clear this filter in the link data it is associated with */ 8835 if (uhtid != 0x800) { 8836 jump = adapter->jump_tables[uhtid]; 8837 if (!jump) 8838 return -EINVAL; 8839 if (!test_bit(loc - 1, jump->child_loc_map)) 8840 return -EINVAL; 8841 clear_bit(loc - 1, jump->child_loc_map); 8842 } 8843 8844 /* Check if the filter being deleted is a link */ 8845 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8846 jump = adapter->jump_tables[i]; 8847 if (jump && jump->link_hdl == hdl) { 8848 /* Delete filters in the hardware in the child hash 8849 * table associated with this link 8850 */ 8851 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8852 if (!test_bit(j, jump->child_loc_map)) 8853 continue; 8854 spin_lock(&adapter->fdir_perfect_lock); 8855 err = ixgbe_update_ethtool_fdir_entry(adapter, 8856 NULL, 8857 j + 1); 8858 spin_unlock(&adapter->fdir_perfect_lock); 8859 clear_bit(j, jump->child_loc_map); 8860 } 8861 /* Remove resources for this link */ 8862 kfree(jump->input); 8863 kfree(jump->mask); 8864 kfree(jump); 8865 adapter->jump_tables[i] = NULL; 8866 return err; 8867 } 8868 } 8869 8870 spin_lock(&adapter->fdir_perfect_lock); 8871 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8872 spin_unlock(&adapter->fdir_perfect_lock); 8873 return err; 8874 } 8875 8876 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8877 struct tc_cls_u32_offload *cls) 8878 { 8879 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8880 8881 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8882 return -EINVAL; 8883 8884 /* This ixgbe devices do not support hash tables at the moment 8885 * so abort when given hash tables. 8886 */ 8887 if (cls->hnode.divisor > 0) 8888 return -EINVAL; 8889 8890 set_bit(uhtid - 1, &adapter->tables); 8891 return 0; 8892 } 8893 8894 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8895 struct tc_cls_u32_offload *cls) 8896 { 8897 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8898 8899 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8900 return -EINVAL; 8901 8902 clear_bit(uhtid - 1, &adapter->tables); 8903 return 0; 8904 } 8905 8906 #ifdef CONFIG_NET_CLS_ACT 8907 struct upper_walk_data { 8908 struct ixgbe_adapter *adapter; 8909 u64 action; 8910 int ifindex; 8911 u8 queue; 8912 }; 8913 8914 static int get_macvlan_queue(struct net_device *upper, void *_data) 8915 { 8916 if (netif_is_macvlan(upper)) { 8917 struct macvlan_dev *dfwd = netdev_priv(upper); 8918 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 8919 struct upper_walk_data *data = _data; 8920 struct ixgbe_adapter *adapter = data->adapter; 8921 int ifindex = data->ifindex; 8922 8923 if (vadapter && vadapter->netdev->ifindex == ifindex) { 8924 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 8925 data->action = data->queue; 8926 return 1; 8927 } 8928 } 8929 8930 return 0; 8931 } 8932 8933 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 8934 u8 *queue, u64 *action) 8935 { 8936 unsigned int num_vfs = adapter->num_vfs, vf; 8937 struct upper_walk_data data; 8938 struct net_device *upper; 8939 8940 /* redirect to a SRIOV VF */ 8941 for (vf = 0; vf < num_vfs; ++vf) { 8942 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 8943 if (upper->ifindex == ifindex) { 8944 if (adapter->num_rx_pools > 1) 8945 *queue = vf * 2; 8946 else 8947 *queue = vf * adapter->num_rx_queues_per_pool; 8948 8949 *action = vf + 1; 8950 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 8951 return 0; 8952 } 8953 } 8954 8955 /* redirect to a offloaded macvlan netdev */ 8956 data.adapter = adapter; 8957 data.ifindex = ifindex; 8958 data.action = 0; 8959 data.queue = 0; 8960 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 8961 get_macvlan_queue, &data)) { 8962 *action = data.action; 8963 *queue = data.queue; 8964 8965 return 0; 8966 } 8967 8968 return -EINVAL; 8969 } 8970 8971 static int parse_tc_actions(struct ixgbe_adapter *adapter, 8972 struct tcf_exts *exts, u64 *action, u8 *queue) 8973 { 8974 const struct tc_action *a; 8975 LIST_HEAD(actions); 8976 int err; 8977 8978 if (!tcf_exts_has_actions(exts)) 8979 return -EINVAL; 8980 8981 tcf_exts_to_list(exts, &actions); 8982 list_for_each_entry(a, &actions, list) { 8983 8984 /* Drop action */ 8985 if (is_tcf_gact_shot(a)) { 8986 *action = IXGBE_FDIR_DROP_QUEUE; 8987 *queue = IXGBE_FDIR_DROP_QUEUE; 8988 return 0; 8989 } 8990 8991 /* Redirect to a VF or a offloaded macvlan */ 8992 if (is_tcf_mirred_egress_redirect(a)) { 8993 int ifindex = tcf_mirred_ifindex(a); 8994 8995 err = handle_redirect_action(adapter, ifindex, queue, 8996 action); 8997 if (err == 0) 8998 return err; 8999 } 9000 } 9001 9002 return -EINVAL; 9003 } 9004 #else 9005 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9006 struct tcf_exts *exts, u64 *action, u8 *queue) 9007 { 9008 return -EINVAL; 9009 } 9010 #endif /* CONFIG_NET_CLS_ACT */ 9011 9012 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9013 union ixgbe_atr_input *mask, 9014 struct tc_cls_u32_offload *cls, 9015 struct ixgbe_mat_field *field_ptr, 9016 struct ixgbe_nexthdr *nexthdr) 9017 { 9018 int i, j, off; 9019 __be32 val, m; 9020 bool found_entry = false, found_jump_field = false; 9021 9022 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9023 off = cls->knode.sel->keys[i].off; 9024 val = cls->knode.sel->keys[i].val; 9025 m = cls->knode.sel->keys[i].mask; 9026 9027 for (j = 0; field_ptr[j].val; j++) { 9028 if (field_ptr[j].off == off) { 9029 field_ptr[j].val(input, mask, val, m); 9030 input->filter.formatted.flow_type |= 9031 field_ptr[j].type; 9032 found_entry = true; 9033 break; 9034 } 9035 } 9036 if (nexthdr) { 9037 if (nexthdr->off == cls->knode.sel->keys[i].off && 9038 nexthdr->val == cls->knode.sel->keys[i].val && 9039 nexthdr->mask == cls->knode.sel->keys[i].mask) 9040 found_jump_field = true; 9041 else 9042 continue; 9043 } 9044 } 9045 9046 if (nexthdr && !found_jump_field) 9047 return -EINVAL; 9048 9049 if (!found_entry) 9050 return 0; 9051 9052 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9053 IXGBE_ATR_L4TYPE_MASK; 9054 9055 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9056 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9057 9058 return 0; 9059 } 9060 9061 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9062 struct tc_cls_u32_offload *cls) 9063 { 9064 __be16 protocol = cls->common.protocol; 9065 u32 loc = cls->knode.handle & 0xfffff; 9066 struct ixgbe_hw *hw = &adapter->hw; 9067 struct ixgbe_mat_field *field_ptr; 9068 struct ixgbe_fdir_filter *input = NULL; 9069 union ixgbe_atr_input *mask = NULL; 9070 struct ixgbe_jump_table *jump = NULL; 9071 int i, err = -EINVAL; 9072 u8 queue; 9073 u32 uhtid, link_uhtid; 9074 9075 uhtid = TC_U32_USERHTID(cls->knode.handle); 9076 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9077 9078 /* At the moment cls_u32 jumps to network layer and skips past 9079 * L2 headers. The canonical method to match L2 frames is to use 9080 * negative values. However this is error prone at best but really 9081 * just broken because there is no way to "know" what sort of hdr 9082 * is in front of the network layer. Fix cls_u32 to support L2 9083 * headers when needed. 9084 */ 9085 if (protocol != htons(ETH_P_IP)) 9086 return err; 9087 9088 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9089 e_err(drv, "Location out of range\n"); 9090 return err; 9091 } 9092 9093 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9094 * links and also the fields used to advance the parser across each 9095 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9096 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9097 * To add support for new nodes update ixgbe_model.h parse structures 9098 * this function _should_ be generic try not to hardcode values here. 9099 */ 9100 if (uhtid == 0x800) { 9101 field_ptr = (adapter->jump_tables[0])->mat; 9102 } else { 9103 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9104 return err; 9105 if (!adapter->jump_tables[uhtid]) 9106 return err; 9107 field_ptr = (adapter->jump_tables[uhtid])->mat; 9108 } 9109 9110 if (!field_ptr) 9111 return err; 9112 9113 /* At this point we know the field_ptr is valid and need to either 9114 * build cls_u32 link or attach filter. Because adding a link to 9115 * a handle that does not exist is invalid and the same for adding 9116 * rules to handles that don't exist. 9117 */ 9118 9119 if (link_uhtid) { 9120 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9121 9122 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9123 return err; 9124 9125 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9126 return err; 9127 9128 /* Multiple filters as links to the same hash table are not 9129 * supported. To add a new filter with the same next header 9130 * but different match/jump conditions, create a new hash table 9131 * and link to it. 9132 */ 9133 if (adapter->jump_tables[link_uhtid] && 9134 (adapter->jump_tables[link_uhtid])->link_hdl) { 9135 e_err(drv, "Link filter exists for link: %x\n", 9136 link_uhtid); 9137 return err; 9138 } 9139 9140 for (i = 0; nexthdr[i].jump; i++) { 9141 if (nexthdr[i].o != cls->knode.sel->offoff || 9142 nexthdr[i].s != cls->knode.sel->offshift || 9143 nexthdr[i].m != cls->knode.sel->offmask) 9144 return err; 9145 9146 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9147 if (!jump) 9148 return -ENOMEM; 9149 input = kzalloc(sizeof(*input), GFP_KERNEL); 9150 if (!input) { 9151 err = -ENOMEM; 9152 goto free_jump; 9153 } 9154 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9155 if (!mask) { 9156 err = -ENOMEM; 9157 goto free_input; 9158 } 9159 jump->input = input; 9160 jump->mask = mask; 9161 jump->link_hdl = cls->knode.handle; 9162 9163 err = ixgbe_clsu32_build_input(input, mask, cls, 9164 field_ptr, &nexthdr[i]); 9165 if (!err) { 9166 jump->mat = nexthdr[i].jump; 9167 adapter->jump_tables[link_uhtid] = jump; 9168 break; 9169 } 9170 } 9171 return 0; 9172 } 9173 9174 input = kzalloc(sizeof(*input), GFP_KERNEL); 9175 if (!input) 9176 return -ENOMEM; 9177 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9178 if (!mask) { 9179 err = -ENOMEM; 9180 goto free_input; 9181 } 9182 9183 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9184 if ((adapter->jump_tables[uhtid])->input) 9185 memcpy(input, (adapter->jump_tables[uhtid])->input, 9186 sizeof(*input)); 9187 if ((adapter->jump_tables[uhtid])->mask) 9188 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9189 sizeof(*mask)); 9190 9191 /* Lookup in all child hash tables if this location is already 9192 * filled with a filter 9193 */ 9194 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9195 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9196 9197 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9198 e_err(drv, "Filter exists in location: %x\n", 9199 loc); 9200 err = -EINVAL; 9201 goto err_out; 9202 } 9203 } 9204 } 9205 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9206 if (err) 9207 goto err_out; 9208 9209 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9210 &queue); 9211 if (err < 0) 9212 goto err_out; 9213 9214 input->sw_idx = loc; 9215 9216 spin_lock(&adapter->fdir_perfect_lock); 9217 9218 if (hlist_empty(&adapter->fdir_filter_list)) { 9219 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9220 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9221 if (err) 9222 goto err_out_w_lock; 9223 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9224 err = -EINVAL; 9225 goto err_out_w_lock; 9226 } 9227 9228 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9229 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9230 input->sw_idx, queue); 9231 if (!err) 9232 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9233 spin_unlock(&adapter->fdir_perfect_lock); 9234 9235 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9236 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9237 9238 kfree(mask); 9239 return err; 9240 err_out_w_lock: 9241 spin_unlock(&adapter->fdir_perfect_lock); 9242 err_out: 9243 kfree(mask); 9244 free_input: 9245 kfree(input); 9246 free_jump: 9247 kfree(jump); 9248 return err; 9249 } 9250 9251 static int ixgbe_setup_tc_cls_u32(struct net_device *dev, 9252 struct tc_cls_u32_offload *cls_u32) 9253 { 9254 struct ixgbe_adapter *adapter = netdev_priv(dev); 9255 9256 if (!is_classid_clsact_ingress(cls_u32->common.classid) || 9257 cls_u32->common.chain_index) 9258 return -EOPNOTSUPP; 9259 9260 switch (cls_u32->command) { 9261 case TC_CLSU32_NEW_KNODE: 9262 case TC_CLSU32_REPLACE_KNODE: 9263 return ixgbe_configure_clsu32(adapter, cls_u32); 9264 case TC_CLSU32_DELETE_KNODE: 9265 return ixgbe_delete_clsu32(adapter, cls_u32); 9266 case TC_CLSU32_NEW_HNODE: 9267 case TC_CLSU32_REPLACE_HNODE: 9268 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9269 case TC_CLSU32_DELETE_HNODE: 9270 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9271 default: 9272 return -EOPNOTSUPP; 9273 } 9274 } 9275 9276 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9277 struct tc_mqprio_qopt *mqprio) 9278 { 9279 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9280 return ixgbe_setup_tc(dev, mqprio->num_tc); 9281 } 9282 9283 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9284 void *type_data) 9285 { 9286 switch (type) { 9287 case TC_SETUP_CLSU32: 9288 return ixgbe_setup_tc_cls_u32(dev, type_data); 9289 case TC_SETUP_MQPRIO: 9290 return ixgbe_setup_tc_mqprio(dev, type_data); 9291 default: 9292 return -EOPNOTSUPP; 9293 } 9294 } 9295 9296 #ifdef CONFIG_PCI_IOV 9297 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9298 { 9299 struct net_device *netdev = adapter->netdev; 9300 9301 rtnl_lock(); 9302 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 9303 rtnl_unlock(); 9304 } 9305 9306 #endif 9307 void ixgbe_do_reset(struct net_device *netdev) 9308 { 9309 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9310 9311 if (netif_running(netdev)) 9312 ixgbe_reinit_locked(adapter); 9313 else 9314 ixgbe_reset(adapter); 9315 } 9316 9317 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9318 netdev_features_t features) 9319 { 9320 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9321 9322 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9323 if (!(features & NETIF_F_RXCSUM)) 9324 features &= ~NETIF_F_LRO; 9325 9326 /* Turn off LRO if not RSC capable */ 9327 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9328 features &= ~NETIF_F_LRO; 9329 9330 return features; 9331 } 9332 9333 static int ixgbe_set_features(struct net_device *netdev, 9334 netdev_features_t features) 9335 { 9336 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9337 netdev_features_t changed = netdev->features ^ features; 9338 bool need_reset = false; 9339 9340 /* Make sure RSC matches LRO, reset if change */ 9341 if (!(features & NETIF_F_LRO)) { 9342 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9343 need_reset = true; 9344 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9345 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9346 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9347 if (adapter->rx_itr_setting == 1 || 9348 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9349 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9350 need_reset = true; 9351 } else if ((changed ^ features) & NETIF_F_LRO) { 9352 e_info(probe, "rx-usecs set too low, " 9353 "disabling RSC\n"); 9354 } 9355 } 9356 9357 /* 9358 * Check if Flow Director n-tuple support or hw_tc support was 9359 * enabled or disabled. If the state changed, we need to reset. 9360 */ 9361 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9362 /* turn off ATR, enable perfect filters and reset */ 9363 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9364 need_reset = true; 9365 9366 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9367 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9368 } else { 9369 /* turn off perfect filters, enable ATR and reset */ 9370 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9371 need_reset = true; 9372 9373 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9374 9375 /* We cannot enable ATR if SR-IOV is enabled */ 9376 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9377 /* We cannot enable ATR if we have 2 or more tcs */ 9378 (netdev_get_num_tc(netdev) > 1) || 9379 /* We cannot enable ATR if RSS is disabled */ 9380 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9381 /* A sample rate of 0 indicates ATR disabled */ 9382 (!adapter->atr_sample_rate)) 9383 ; /* do nothing not supported */ 9384 else /* otherwise supported and set the flag */ 9385 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9386 } 9387 9388 if (changed & NETIF_F_RXALL) 9389 need_reset = true; 9390 9391 netdev->features = features; 9392 9393 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9394 if (features & NETIF_F_RXCSUM) { 9395 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9396 } else { 9397 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9398 9399 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9400 } 9401 } 9402 9403 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9404 if (features & NETIF_F_RXCSUM) { 9405 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9406 } else { 9407 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9408 9409 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9410 } 9411 } 9412 9413 if (need_reset) 9414 ixgbe_do_reset(netdev); 9415 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9416 NETIF_F_HW_VLAN_CTAG_FILTER)) 9417 ixgbe_set_rx_mode(netdev); 9418 9419 return 0; 9420 } 9421 9422 /** 9423 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9424 * @dev: The port's netdev 9425 * @ti: Tunnel endpoint information 9426 **/ 9427 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9428 struct udp_tunnel_info *ti) 9429 { 9430 struct ixgbe_adapter *adapter = netdev_priv(dev); 9431 struct ixgbe_hw *hw = &adapter->hw; 9432 __be16 port = ti->port; 9433 u32 port_shift = 0; 9434 u32 reg; 9435 9436 if (ti->sa_family != AF_INET) 9437 return; 9438 9439 switch (ti->type) { 9440 case UDP_TUNNEL_TYPE_VXLAN: 9441 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9442 return; 9443 9444 if (adapter->vxlan_port == port) 9445 return; 9446 9447 if (adapter->vxlan_port) { 9448 netdev_info(dev, 9449 "VXLAN port %d set, not adding port %d\n", 9450 ntohs(adapter->vxlan_port), 9451 ntohs(port)); 9452 return; 9453 } 9454 9455 adapter->vxlan_port = port; 9456 break; 9457 case UDP_TUNNEL_TYPE_GENEVE: 9458 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9459 return; 9460 9461 if (adapter->geneve_port == port) 9462 return; 9463 9464 if (adapter->geneve_port) { 9465 netdev_info(dev, 9466 "GENEVE port %d set, not adding port %d\n", 9467 ntohs(adapter->geneve_port), 9468 ntohs(port)); 9469 return; 9470 } 9471 9472 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9473 adapter->geneve_port = port; 9474 break; 9475 default: 9476 return; 9477 } 9478 9479 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9480 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9481 } 9482 9483 /** 9484 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9485 * @dev: The port's netdev 9486 * @ti: Tunnel endpoint information 9487 **/ 9488 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9489 struct udp_tunnel_info *ti) 9490 { 9491 struct ixgbe_adapter *adapter = netdev_priv(dev); 9492 u32 port_mask; 9493 9494 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9495 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9496 return; 9497 9498 if (ti->sa_family != AF_INET) 9499 return; 9500 9501 switch (ti->type) { 9502 case UDP_TUNNEL_TYPE_VXLAN: 9503 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9504 return; 9505 9506 if (adapter->vxlan_port != ti->port) { 9507 netdev_info(dev, "VXLAN port %d not found\n", 9508 ntohs(ti->port)); 9509 return; 9510 } 9511 9512 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9513 break; 9514 case UDP_TUNNEL_TYPE_GENEVE: 9515 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9516 return; 9517 9518 if (adapter->geneve_port != ti->port) { 9519 netdev_info(dev, "GENEVE port %d not found\n", 9520 ntohs(ti->port)); 9521 return; 9522 } 9523 9524 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9525 break; 9526 default: 9527 return; 9528 } 9529 9530 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9531 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9532 } 9533 9534 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9535 struct net_device *dev, 9536 const unsigned char *addr, u16 vid, 9537 u16 flags) 9538 { 9539 /* guarantee we can provide a unique filter for the unicast address */ 9540 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9541 struct ixgbe_adapter *adapter = netdev_priv(dev); 9542 u16 pool = VMDQ_P(0); 9543 9544 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9545 return -ENOMEM; 9546 } 9547 9548 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9549 } 9550 9551 /** 9552 * ixgbe_configure_bridge_mode - set various bridge modes 9553 * @adapter - the private structure 9554 * @mode - requested bridge mode 9555 * 9556 * Configure some settings require for various bridge modes. 9557 **/ 9558 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9559 __u16 mode) 9560 { 9561 struct ixgbe_hw *hw = &adapter->hw; 9562 unsigned int p, num_pools; 9563 u32 vmdctl; 9564 9565 switch (mode) { 9566 case BRIDGE_MODE_VEPA: 9567 /* disable Tx loopback, rely on switch hairpin mode */ 9568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9569 9570 /* must enable Rx switching replication to allow multicast 9571 * packet reception on all VFs, and to enable source address 9572 * pruning. 9573 */ 9574 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9575 vmdctl |= IXGBE_VT_CTL_REPLEN; 9576 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9577 9578 /* enable Rx source address pruning. Note, this requires 9579 * replication to be enabled or else it does nothing. 9580 */ 9581 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9582 for (p = 0; p < num_pools; p++) { 9583 if (hw->mac.ops.set_source_address_pruning) 9584 hw->mac.ops.set_source_address_pruning(hw, 9585 true, 9586 p); 9587 } 9588 break; 9589 case BRIDGE_MODE_VEB: 9590 /* enable Tx loopback for internal VF/PF communication */ 9591 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9592 IXGBE_PFDTXGSWC_VT_LBEN); 9593 9594 /* disable Rx switching replication unless we have SR-IOV 9595 * virtual functions 9596 */ 9597 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9598 if (!adapter->num_vfs) 9599 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9600 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9601 9602 /* disable Rx source address pruning, since we don't expect to 9603 * be receiving external loopback of our transmitted frames. 9604 */ 9605 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9606 for (p = 0; p < num_pools; p++) { 9607 if (hw->mac.ops.set_source_address_pruning) 9608 hw->mac.ops.set_source_address_pruning(hw, 9609 false, 9610 p); 9611 } 9612 break; 9613 default: 9614 return -EINVAL; 9615 } 9616 9617 adapter->bridge_mode = mode; 9618 9619 e_info(drv, "enabling bridge mode: %s\n", 9620 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9621 9622 return 0; 9623 } 9624 9625 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9626 struct nlmsghdr *nlh, u16 flags) 9627 { 9628 struct ixgbe_adapter *adapter = netdev_priv(dev); 9629 struct nlattr *attr, *br_spec; 9630 int rem; 9631 9632 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9633 return -EOPNOTSUPP; 9634 9635 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9636 if (!br_spec) 9637 return -EINVAL; 9638 9639 nla_for_each_nested(attr, br_spec, rem) { 9640 int status; 9641 __u16 mode; 9642 9643 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9644 continue; 9645 9646 if (nla_len(attr) < sizeof(mode)) 9647 return -EINVAL; 9648 9649 mode = nla_get_u16(attr); 9650 status = ixgbe_configure_bridge_mode(adapter, mode); 9651 if (status) 9652 return status; 9653 9654 break; 9655 } 9656 9657 return 0; 9658 } 9659 9660 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9661 struct net_device *dev, 9662 u32 filter_mask, int nlflags) 9663 { 9664 struct ixgbe_adapter *adapter = netdev_priv(dev); 9665 9666 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9667 return 0; 9668 9669 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9670 adapter->bridge_mode, 0, 0, nlflags, 9671 filter_mask, NULL); 9672 } 9673 9674 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9675 { 9676 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 9677 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9678 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 9679 unsigned int limit; 9680 int pool, err; 9681 9682 /* Hardware has a limited number of available pools. Each VF, and the 9683 * PF require a pool. Check to ensure we don't attempt to use more 9684 * then the available number of pools. 9685 */ 9686 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9687 return ERR_PTR(-EINVAL); 9688 9689 #ifdef CONFIG_RPS 9690 if (vdev->num_rx_queues != vdev->num_tx_queues) { 9691 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 9692 vdev->name); 9693 return ERR_PTR(-EINVAL); 9694 } 9695 #endif 9696 /* Check for hardware restriction on number of rx/tx queues */ 9697 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 9698 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 9699 netdev_info(pdev, 9700 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 9701 pdev->name); 9702 return ERR_PTR(-EINVAL); 9703 } 9704 9705 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9706 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 9707 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 9708 return ERR_PTR(-EBUSY); 9709 9710 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 9711 if (!fwd_adapter) 9712 return ERR_PTR(-ENOMEM); 9713 9714 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 9715 adapter->num_rx_pools++; 9716 set_bit(pool, &adapter->fwd_bitmask); 9717 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9718 9719 /* Enable VMDq flag so device will be set in VM mode */ 9720 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 9721 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9722 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 9723 9724 /* Force reinit of ring allocation with VMDQ enabled */ 9725 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9726 if (err) 9727 goto fwd_add_err; 9728 fwd_adapter->pool = pool; 9729 fwd_adapter->real_adapter = adapter; 9730 9731 if (netif_running(pdev)) { 9732 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 9733 if (err) 9734 goto fwd_add_err; 9735 netif_tx_start_all_queues(vdev); 9736 } 9737 9738 return fwd_adapter; 9739 fwd_add_err: 9740 /* unwind counter and free adapter struct */ 9741 netdev_info(pdev, 9742 "%s: dfwd hardware acceleration failed\n", vdev->name); 9743 clear_bit(pool, &adapter->fwd_bitmask); 9744 adapter->num_rx_pools--; 9745 kfree(fwd_adapter); 9746 return ERR_PTR(err); 9747 } 9748 9749 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9750 { 9751 struct ixgbe_fwd_adapter *fwd_adapter = priv; 9752 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 9753 unsigned int limit; 9754 9755 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 9756 adapter->num_rx_pools--; 9757 9758 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9759 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9760 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 9761 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9762 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 9763 fwd_adapter->pool, adapter->num_rx_pools, 9764 fwd_adapter->rx_base_queue, 9765 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 9766 adapter->fwd_bitmask); 9767 kfree(fwd_adapter); 9768 } 9769 9770 #define IXGBE_MAX_MAC_HDR_LEN 127 9771 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9772 9773 static netdev_features_t 9774 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9775 netdev_features_t features) 9776 { 9777 unsigned int network_hdr_len, mac_hdr_len; 9778 9779 /* Make certain the headers can be described by a context descriptor */ 9780 mac_hdr_len = skb_network_header(skb) - skb->data; 9781 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9782 return features & ~(NETIF_F_HW_CSUM | 9783 NETIF_F_SCTP_CRC | 9784 NETIF_F_HW_VLAN_CTAG_TX | 9785 NETIF_F_TSO | 9786 NETIF_F_TSO6); 9787 9788 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9789 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9790 return features & ~(NETIF_F_HW_CSUM | 9791 NETIF_F_SCTP_CRC | 9792 NETIF_F_TSO | 9793 NETIF_F_TSO6); 9794 9795 /* We can only support IPV4 TSO in tunnels if we can mangle the 9796 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9797 */ 9798 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 9799 features &= ~NETIF_F_TSO; 9800 9801 return features; 9802 } 9803 9804 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9805 { 9806 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9807 struct ixgbe_adapter *adapter = netdev_priv(dev); 9808 struct bpf_prog *old_prog; 9809 9810 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9811 return -EINVAL; 9812 9813 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9814 return -EINVAL; 9815 9816 /* verify ixgbe ring attributes are sufficient for XDP */ 9817 for (i = 0; i < adapter->num_rx_queues; i++) { 9818 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9819 9820 if (ring_is_rsc_enabled(ring)) 9821 return -EINVAL; 9822 9823 if (frame_size > ixgbe_rx_bufsz(ring)) 9824 return -EINVAL; 9825 } 9826 9827 if (nr_cpu_ids > MAX_XDP_QUEUES) 9828 return -ENOMEM; 9829 9830 old_prog = xchg(&adapter->xdp_prog, prog); 9831 9832 /* If transitioning XDP modes reconfigure rings */ 9833 if (!!prog != !!old_prog) { 9834 int err = ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 9835 9836 if (err) { 9837 rcu_assign_pointer(adapter->xdp_prog, old_prog); 9838 return -EINVAL; 9839 } 9840 } else { 9841 for (i = 0; i < adapter->num_rx_queues; i++) 9842 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); 9843 } 9844 9845 if (old_prog) 9846 bpf_prog_put(old_prog); 9847 9848 return 0; 9849 } 9850 9851 static int ixgbe_xdp(struct net_device *dev, struct netdev_xdp *xdp) 9852 { 9853 struct ixgbe_adapter *adapter = netdev_priv(dev); 9854 9855 switch (xdp->command) { 9856 case XDP_SETUP_PROG: 9857 return ixgbe_xdp_setup(dev, xdp->prog); 9858 case XDP_QUERY_PROG: 9859 xdp->prog_attached = !!(adapter->xdp_prog); 9860 xdp->prog_id = adapter->xdp_prog ? 9861 adapter->xdp_prog->aux->id : 0; 9862 return 0; 9863 default: 9864 return -EINVAL; 9865 } 9866 } 9867 9868 static int ixgbe_xdp_xmit(struct net_device *dev, struct xdp_buff *xdp) 9869 { 9870 struct ixgbe_adapter *adapter = netdev_priv(dev); 9871 struct ixgbe_ring *ring; 9872 int err; 9873 9874 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 9875 return -ENETDOWN; 9876 9877 /* During program transitions its possible adapter->xdp_prog is assigned 9878 * but ring has not been configured yet. In this case simply abort xmit. 9879 */ 9880 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 9881 if (unlikely(!ring)) 9882 return -ENXIO; 9883 9884 err = ixgbe_xmit_xdp_ring(adapter, xdp); 9885 if (err != IXGBE_XDP_TX) 9886 return -ENOSPC; 9887 9888 return 0; 9889 } 9890 9891 static void ixgbe_xdp_flush(struct net_device *dev) 9892 { 9893 struct ixgbe_adapter *adapter = netdev_priv(dev); 9894 struct ixgbe_ring *ring; 9895 9896 /* Its possible the device went down between xdp xmit and flush so 9897 * we need to ensure device is still up. 9898 */ 9899 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 9900 return; 9901 9902 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 9903 if (unlikely(!ring)) 9904 return; 9905 9906 /* Force memory writes to complete before letting h/w know there 9907 * are new descriptors to fetch. 9908 */ 9909 wmb(); 9910 writel(ring->next_to_use, ring->tail); 9911 9912 return; 9913 } 9914 9915 static const struct net_device_ops ixgbe_netdev_ops = { 9916 .ndo_open = ixgbe_open, 9917 .ndo_stop = ixgbe_close, 9918 .ndo_start_xmit = ixgbe_xmit_frame, 9919 .ndo_select_queue = ixgbe_select_queue, 9920 .ndo_set_rx_mode = ixgbe_set_rx_mode, 9921 .ndo_validate_addr = eth_validate_addr, 9922 .ndo_set_mac_address = ixgbe_set_mac, 9923 .ndo_change_mtu = ixgbe_change_mtu, 9924 .ndo_tx_timeout = ixgbe_tx_timeout, 9925 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 9926 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 9927 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 9928 .ndo_do_ioctl = ixgbe_ioctl, 9929 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 9930 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 9931 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 9932 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 9933 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 9934 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 9935 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 9936 .ndo_get_stats64 = ixgbe_get_stats64, 9937 .ndo_setup_tc = __ixgbe_setup_tc, 9938 #ifdef CONFIG_NET_POLL_CONTROLLER 9939 .ndo_poll_controller = ixgbe_netpoll, 9940 #endif 9941 #ifdef IXGBE_FCOE 9942 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 9943 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 9944 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 9945 .ndo_fcoe_enable = ixgbe_fcoe_enable, 9946 .ndo_fcoe_disable = ixgbe_fcoe_disable, 9947 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 9948 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 9949 #endif /* IXGBE_FCOE */ 9950 .ndo_set_features = ixgbe_set_features, 9951 .ndo_fix_features = ixgbe_fix_features, 9952 .ndo_fdb_add = ixgbe_ndo_fdb_add, 9953 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 9954 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 9955 .ndo_dfwd_add_station = ixgbe_fwd_add, 9956 .ndo_dfwd_del_station = ixgbe_fwd_del, 9957 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 9958 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 9959 .ndo_features_check = ixgbe_features_check, 9960 .ndo_xdp = ixgbe_xdp, 9961 .ndo_xdp_xmit = ixgbe_xdp_xmit, 9962 .ndo_xdp_flush = ixgbe_xdp_flush, 9963 }; 9964 9965 /** 9966 * ixgbe_enumerate_functions - Get the number of ports this device has 9967 * @adapter: adapter structure 9968 * 9969 * This function enumerates the phsyical functions co-located on a single slot, 9970 * in order to determine how many ports a device has. This is most useful in 9971 * determining the required GT/s of PCIe bandwidth necessary for optimal 9972 * performance. 9973 **/ 9974 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 9975 { 9976 struct pci_dev *entry, *pdev = adapter->pdev; 9977 int physfns = 0; 9978 9979 /* Some cards can not use the generic count PCIe functions method, 9980 * because they are behind a parent switch, so we hardcode these with 9981 * the correct number of functions. 9982 */ 9983 if (ixgbe_pcie_from_parent(&adapter->hw)) 9984 physfns = 4; 9985 9986 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 9987 /* don't count virtual functions */ 9988 if (entry->is_virtfn) 9989 continue; 9990 9991 /* When the devices on the bus don't all match our device ID, 9992 * we can't reliably determine the correct number of 9993 * functions. This can occur if a function has been direct 9994 * attached to a virtual machine using VT-d, for example. In 9995 * this case, simply return -1 to indicate this. 9996 */ 9997 if ((entry->vendor != pdev->vendor) || 9998 (entry->device != pdev->device)) 9999 return -1; 10000 10001 physfns++; 10002 } 10003 10004 return physfns; 10005 } 10006 10007 /** 10008 * ixgbe_wol_supported - Check whether device supports WoL 10009 * @adapter: the adapter private structure 10010 * @device_id: the device ID 10011 * @subdev_id: the subsystem device ID 10012 * 10013 * This function is used by probe and ethtool to determine 10014 * which devices have WoL support 10015 * 10016 **/ 10017 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10018 u16 subdevice_id) 10019 { 10020 struct ixgbe_hw *hw = &adapter->hw; 10021 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10022 10023 /* WOL not supported on 82598 */ 10024 if (hw->mac.type == ixgbe_mac_82598EB) 10025 return false; 10026 10027 /* check eeprom to see if WOL is enabled for X540 and newer */ 10028 if (hw->mac.type >= ixgbe_mac_X540) { 10029 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10030 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10031 (hw->bus.func == 0))) 10032 return true; 10033 } 10034 10035 /* WOL is determined based on device IDs for 82599 MACs */ 10036 switch (device_id) { 10037 case IXGBE_DEV_ID_82599_SFP: 10038 /* Only these subdevices could supports WOL */ 10039 switch (subdevice_id) { 10040 case IXGBE_SUBDEV_ID_82599_560FLR: 10041 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10042 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10043 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10044 /* only support first port */ 10045 if (hw->bus.func != 0) 10046 break; 10047 /* fall through */ 10048 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10049 case IXGBE_SUBDEV_ID_82599_SFP: 10050 case IXGBE_SUBDEV_ID_82599_RNDC: 10051 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10052 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10053 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10054 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10055 return true; 10056 } 10057 break; 10058 case IXGBE_DEV_ID_82599EN_SFP: 10059 /* Only these subdevices support WOL */ 10060 switch (subdevice_id) { 10061 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10062 return true; 10063 } 10064 break; 10065 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10066 /* All except this subdevice support WOL */ 10067 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10068 return true; 10069 break; 10070 case IXGBE_DEV_ID_82599_KX4: 10071 return true; 10072 default: 10073 break; 10074 } 10075 10076 return false; 10077 } 10078 10079 /** 10080 * ixgbe_probe - Device Initialization Routine 10081 * @pdev: PCI device information struct 10082 * @ent: entry in ixgbe_pci_tbl 10083 * 10084 * Returns 0 on success, negative on failure 10085 * 10086 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10087 * The OS initialization, configuring of the adapter private structure, 10088 * and a hardware reset occur. 10089 **/ 10090 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10091 { 10092 struct net_device *netdev; 10093 struct ixgbe_adapter *adapter = NULL; 10094 struct ixgbe_hw *hw; 10095 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10096 int i, err, pci_using_dac, expected_gts; 10097 unsigned int indices = MAX_TX_QUEUES; 10098 u8 part_str[IXGBE_PBANUM_LENGTH]; 10099 bool disable_dev = false; 10100 #ifdef IXGBE_FCOE 10101 u16 device_caps; 10102 #endif 10103 u32 eec; 10104 10105 /* Catch broken hardware that put the wrong VF device ID in 10106 * the PCIe SR-IOV capability. 10107 */ 10108 if (pdev->is_virtfn) { 10109 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10110 pci_name(pdev), pdev->vendor, pdev->device); 10111 return -EINVAL; 10112 } 10113 10114 err = pci_enable_device_mem(pdev); 10115 if (err) 10116 return err; 10117 10118 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10119 pci_using_dac = 1; 10120 } else { 10121 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10122 if (err) { 10123 dev_err(&pdev->dev, 10124 "No usable DMA configuration, aborting\n"); 10125 goto err_dma; 10126 } 10127 pci_using_dac = 0; 10128 } 10129 10130 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10131 if (err) { 10132 dev_err(&pdev->dev, 10133 "pci_request_selected_regions failed 0x%x\n", err); 10134 goto err_pci_reg; 10135 } 10136 10137 pci_enable_pcie_error_reporting(pdev); 10138 10139 pci_set_master(pdev); 10140 pci_save_state(pdev); 10141 10142 if (ii->mac == ixgbe_mac_82598EB) { 10143 #ifdef CONFIG_IXGBE_DCB 10144 /* 8 TC w/ 4 queues per TC */ 10145 indices = 4 * MAX_TRAFFIC_CLASS; 10146 #else 10147 indices = IXGBE_MAX_RSS_INDICES; 10148 #endif 10149 } 10150 10151 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10152 if (!netdev) { 10153 err = -ENOMEM; 10154 goto err_alloc_etherdev; 10155 } 10156 10157 SET_NETDEV_DEV(netdev, &pdev->dev); 10158 10159 adapter = netdev_priv(netdev); 10160 10161 adapter->netdev = netdev; 10162 adapter->pdev = pdev; 10163 hw = &adapter->hw; 10164 hw->back = adapter; 10165 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10166 10167 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10168 pci_resource_len(pdev, 0)); 10169 adapter->io_addr = hw->hw_addr; 10170 if (!hw->hw_addr) { 10171 err = -EIO; 10172 goto err_ioremap; 10173 } 10174 10175 netdev->netdev_ops = &ixgbe_netdev_ops; 10176 ixgbe_set_ethtool_ops(netdev); 10177 netdev->watchdog_timeo = 5 * HZ; 10178 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10179 10180 /* Setup hw api */ 10181 hw->mac.ops = *ii->mac_ops; 10182 hw->mac.type = ii->mac; 10183 hw->mvals = ii->mvals; 10184 if (ii->link_ops) 10185 hw->link.ops = *ii->link_ops; 10186 10187 /* EEPROM */ 10188 hw->eeprom.ops = *ii->eeprom_ops; 10189 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10190 if (ixgbe_removed(hw->hw_addr)) { 10191 err = -EIO; 10192 goto err_ioremap; 10193 } 10194 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10195 if (!(eec & BIT(8))) 10196 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10197 10198 /* PHY */ 10199 hw->phy.ops = *ii->phy_ops; 10200 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10201 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10202 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10203 hw->phy.mdio.mmds = 0; 10204 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10205 hw->phy.mdio.dev = netdev; 10206 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10207 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10208 10209 /* setup the private structure */ 10210 err = ixgbe_sw_init(adapter, ii); 10211 if (err) 10212 goto err_sw_init; 10213 10214 /* Make sure the SWFW semaphore is in a valid state */ 10215 if (hw->mac.ops.init_swfw_sync) 10216 hw->mac.ops.init_swfw_sync(hw); 10217 10218 /* Make it possible the adapter to be woken up via WOL */ 10219 switch (adapter->hw.mac.type) { 10220 case ixgbe_mac_82599EB: 10221 case ixgbe_mac_X540: 10222 case ixgbe_mac_X550: 10223 case ixgbe_mac_X550EM_x: 10224 case ixgbe_mac_x550em_a: 10225 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10226 break; 10227 default: 10228 break; 10229 } 10230 10231 /* 10232 * If there is a fan on this device and it has failed log the 10233 * failure. 10234 */ 10235 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10236 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10237 if (esdp & IXGBE_ESDP_SDP1) 10238 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10239 } 10240 10241 if (allow_unsupported_sfp) 10242 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10243 10244 /* reset_hw fills in the perm_addr as well */ 10245 hw->phy.reset_if_overtemp = true; 10246 err = hw->mac.ops.reset_hw(hw); 10247 hw->phy.reset_if_overtemp = false; 10248 ixgbe_set_eee_capable(adapter); 10249 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10250 err = 0; 10251 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10252 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10253 e_dev_err("Reload the driver after installing a supported module.\n"); 10254 goto err_sw_init; 10255 } else if (err) { 10256 e_dev_err("HW Init failed: %d\n", err); 10257 goto err_sw_init; 10258 } 10259 10260 #ifdef CONFIG_PCI_IOV 10261 /* SR-IOV not supported on the 82598 */ 10262 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10263 goto skip_sriov; 10264 /* Mailbox */ 10265 ixgbe_init_mbx_params_pf(hw); 10266 hw->mbx.ops = ii->mbx_ops; 10267 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10268 ixgbe_enable_sriov(adapter, max_vfs); 10269 skip_sriov: 10270 10271 #endif 10272 netdev->features = NETIF_F_SG | 10273 NETIF_F_TSO | 10274 NETIF_F_TSO6 | 10275 NETIF_F_RXHASH | 10276 NETIF_F_RXCSUM | 10277 NETIF_F_HW_CSUM; 10278 10279 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10280 NETIF_F_GSO_GRE_CSUM | \ 10281 NETIF_F_GSO_IPXIP4 | \ 10282 NETIF_F_GSO_IPXIP6 | \ 10283 NETIF_F_GSO_UDP_TUNNEL | \ 10284 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10285 10286 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10287 netdev->features |= NETIF_F_GSO_PARTIAL | 10288 IXGBE_GSO_PARTIAL_FEATURES; 10289 10290 if (hw->mac.type >= ixgbe_mac_82599EB) 10291 netdev->features |= NETIF_F_SCTP_CRC; 10292 10293 /* copy netdev features into list of user selectable features */ 10294 netdev->hw_features |= netdev->features | 10295 NETIF_F_HW_VLAN_CTAG_FILTER | 10296 NETIF_F_HW_VLAN_CTAG_RX | 10297 NETIF_F_HW_VLAN_CTAG_TX | 10298 NETIF_F_RXALL | 10299 NETIF_F_HW_L2FW_DOFFLOAD; 10300 10301 if (hw->mac.type >= ixgbe_mac_82599EB) 10302 netdev->hw_features |= NETIF_F_NTUPLE | 10303 NETIF_F_HW_TC; 10304 10305 if (pci_using_dac) 10306 netdev->features |= NETIF_F_HIGHDMA; 10307 10308 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10309 netdev->hw_enc_features |= netdev->vlan_features; 10310 netdev->mpls_features |= NETIF_F_SG | 10311 NETIF_F_TSO | 10312 NETIF_F_TSO6 | 10313 NETIF_F_HW_CSUM; 10314 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10315 10316 /* set this bit last since it cannot be part of vlan_features */ 10317 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10318 NETIF_F_HW_VLAN_CTAG_RX | 10319 NETIF_F_HW_VLAN_CTAG_TX; 10320 10321 netdev->priv_flags |= IFF_UNICAST_FLT; 10322 netdev->priv_flags |= IFF_SUPP_NOFCS; 10323 10324 /* MTU range: 68 - 9710 */ 10325 netdev->min_mtu = ETH_MIN_MTU; 10326 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10327 10328 #ifdef CONFIG_IXGBE_DCB 10329 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10330 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10331 #endif 10332 10333 #ifdef IXGBE_FCOE 10334 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10335 unsigned int fcoe_l; 10336 10337 if (hw->mac.ops.get_device_caps) { 10338 hw->mac.ops.get_device_caps(hw, &device_caps); 10339 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10340 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10341 } 10342 10343 10344 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10345 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10346 10347 netdev->features |= NETIF_F_FSO | 10348 NETIF_F_FCOE_CRC; 10349 10350 netdev->vlan_features |= NETIF_F_FSO | 10351 NETIF_F_FCOE_CRC | 10352 NETIF_F_FCOE_MTU; 10353 } 10354 #endif /* IXGBE_FCOE */ 10355 10356 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10357 netdev->hw_features |= NETIF_F_LRO; 10358 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10359 netdev->features |= NETIF_F_LRO; 10360 10361 /* make sure the EEPROM is good */ 10362 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10363 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10364 err = -EIO; 10365 goto err_sw_init; 10366 } 10367 10368 eth_platform_get_mac_address(&adapter->pdev->dev, 10369 adapter->hw.mac.perm_addr); 10370 10371 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10372 10373 if (!is_valid_ether_addr(netdev->dev_addr)) { 10374 e_dev_err("invalid MAC address\n"); 10375 err = -EIO; 10376 goto err_sw_init; 10377 } 10378 10379 /* Set hw->mac.addr to permanent MAC address */ 10380 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10381 ixgbe_mac_set_default_filter(adapter); 10382 10383 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 10384 (unsigned long) adapter); 10385 10386 if (ixgbe_removed(hw->hw_addr)) { 10387 err = -EIO; 10388 goto err_sw_init; 10389 } 10390 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10391 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10392 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10393 10394 err = ixgbe_init_interrupt_scheme(adapter); 10395 if (err) 10396 goto err_sw_init; 10397 10398 for (i = 0; i < adapter->num_rx_queues; i++) 10399 u64_stats_init(&adapter->rx_ring[i]->syncp); 10400 for (i = 0; i < adapter->num_tx_queues; i++) 10401 u64_stats_init(&adapter->tx_ring[i]->syncp); 10402 for (i = 0; i < adapter->num_xdp_queues; i++) 10403 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10404 10405 /* WOL not supported for all devices */ 10406 adapter->wol = 0; 10407 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10408 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10409 pdev->subsystem_device); 10410 if (hw->wol_enabled) 10411 adapter->wol = IXGBE_WUFC_MAG; 10412 10413 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10414 10415 /* save off EEPROM version number */ 10416 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 10417 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 10418 10419 /* pick up the PCI bus settings for reporting later */ 10420 if (ixgbe_pcie_from_parent(hw)) 10421 ixgbe_get_parent_bus_info(adapter); 10422 else 10423 hw->mac.ops.get_bus_info(hw); 10424 10425 /* calculate the expected PCIe bandwidth required for optimal 10426 * performance. Note that some older parts will never have enough 10427 * bandwidth due to being older generation PCIe parts. We clamp these 10428 * parts to ensure no warning is displayed if it can't be fixed. 10429 */ 10430 switch (hw->mac.type) { 10431 case ixgbe_mac_82598EB: 10432 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10433 break; 10434 default: 10435 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10436 break; 10437 } 10438 10439 /* don't check link if we failed to enumerate functions */ 10440 if (expected_gts > 0) 10441 ixgbe_check_minimum_link(adapter, expected_gts); 10442 10443 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10444 if (err) 10445 strlcpy(part_str, "Unknown", sizeof(part_str)); 10446 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10447 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10448 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10449 part_str); 10450 else 10451 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10452 hw->mac.type, hw->phy.type, part_str); 10453 10454 e_dev_info("%pM\n", netdev->dev_addr); 10455 10456 /* reset the hardware with the new settings */ 10457 err = hw->mac.ops.start_hw(hw); 10458 if (err == IXGBE_ERR_EEPROM_VERSION) { 10459 /* We are running on a pre-production device, log a warning */ 10460 e_dev_warn("This device is a pre-production adapter/LOM. " 10461 "Please be aware there may be issues associated " 10462 "with your hardware. If you are experiencing " 10463 "problems please contact your Intel or hardware " 10464 "representative who provided you with this " 10465 "hardware.\n"); 10466 } 10467 strcpy(netdev->name, "eth%d"); 10468 pci_set_drvdata(pdev, adapter); 10469 err = register_netdev(netdev); 10470 if (err) 10471 goto err_register; 10472 10473 10474 /* power down the optics for 82599 SFP+ fiber */ 10475 if (hw->mac.ops.disable_tx_laser) 10476 hw->mac.ops.disable_tx_laser(hw); 10477 10478 /* carrier off reporting is important to ethtool even BEFORE open */ 10479 netif_carrier_off(netdev); 10480 10481 #ifdef CONFIG_IXGBE_DCA 10482 if (dca_add_requester(&pdev->dev) == 0) { 10483 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10484 ixgbe_setup_dca(adapter); 10485 } 10486 #endif 10487 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10488 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10489 for (i = 0; i < adapter->num_vfs; i++) 10490 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10491 } 10492 10493 /* firmware requires driver version to be 0xFFFFFFFF 10494 * since os does not support feature 10495 */ 10496 if (hw->mac.ops.set_fw_drv_ver) 10497 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10498 sizeof(ixgbe_driver_version) - 1, 10499 ixgbe_driver_version); 10500 10501 /* add san mac addr to netdev */ 10502 ixgbe_add_sanmac_netdev(netdev); 10503 10504 e_dev_info("%s\n", ixgbe_default_device_descr); 10505 10506 #ifdef CONFIG_IXGBE_HWMON 10507 if (ixgbe_sysfs_init(adapter)) 10508 e_err(probe, "failed to allocate sysfs resources\n"); 10509 #endif /* CONFIG_IXGBE_HWMON */ 10510 10511 ixgbe_dbg_adapter_init(adapter); 10512 10513 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10514 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10515 hw->mac.ops.setup_link(hw, 10516 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10517 true); 10518 10519 return 0; 10520 10521 err_register: 10522 ixgbe_release_hw_control(adapter); 10523 ixgbe_clear_interrupt_scheme(adapter); 10524 err_sw_init: 10525 ixgbe_disable_sriov(adapter); 10526 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10527 iounmap(adapter->io_addr); 10528 kfree(adapter->jump_tables[0]); 10529 kfree(adapter->mac_table); 10530 kfree(adapter->rss_key); 10531 err_ioremap: 10532 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10533 free_netdev(netdev); 10534 err_alloc_etherdev: 10535 pci_release_mem_regions(pdev); 10536 err_pci_reg: 10537 err_dma: 10538 if (!adapter || disable_dev) 10539 pci_disable_device(pdev); 10540 return err; 10541 } 10542 10543 /** 10544 * ixgbe_remove - Device Removal Routine 10545 * @pdev: PCI device information struct 10546 * 10547 * ixgbe_remove is called by the PCI subsystem to alert the driver 10548 * that it should release a PCI device. The could be caused by a 10549 * Hot-Plug event, or because the driver is going to be removed from 10550 * memory. 10551 **/ 10552 static void ixgbe_remove(struct pci_dev *pdev) 10553 { 10554 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10555 struct net_device *netdev; 10556 bool disable_dev; 10557 int i; 10558 10559 /* if !adapter then we already cleaned up in probe */ 10560 if (!adapter) 10561 return; 10562 10563 netdev = adapter->netdev; 10564 ixgbe_dbg_adapter_exit(adapter); 10565 10566 set_bit(__IXGBE_REMOVING, &adapter->state); 10567 cancel_work_sync(&adapter->service_task); 10568 10569 10570 #ifdef CONFIG_IXGBE_DCA 10571 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10572 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10573 dca_remove_requester(&pdev->dev); 10574 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10575 IXGBE_DCA_CTRL_DCA_DISABLE); 10576 } 10577 10578 #endif 10579 #ifdef CONFIG_IXGBE_HWMON 10580 ixgbe_sysfs_exit(adapter); 10581 #endif /* CONFIG_IXGBE_HWMON */ 10582 10583 /* remove the added san mac */ 10584 ixgbe_del_sanmac_netdev(netdev); 10585 10586 #ifdef CONFIG_PCI_IOV 10587 ixgbe_disable_sriov(adapter); 10588 #endif 10589 if (netdev->reg_state == NETREG_REGISTERED) 10590 unregister_netdev(netdev); 10591 10592 ixgbe_clear_interrupt_scheme(adapter); 10593 10594 ixgbe_release_hw_control(adapter); 10595 10596 #ifdef CONFIG_DCB 10597 kfree(adapter->ixgbe_ieee_pfc); 10598 kfree(adapter->ixgbe_ieee_ets); 10599 10600 #endif 10601 iounmap(adapter->io_addr); 10602 pci_release_mem_regions(pdev); 10603 10604 e_dev_info("complete\n"); 10605 10606 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10607 if (adapter->jump_tables[i]) { 10608 kfree(adapter->jump_tables[i]->input); 10609 kfree(adapter->jump_tables[i]->mask); 10610 } 10611 kfree(adapter->jump_tables[i]); 10612 } 10613 10614 kfree(adapter->mac_table); 10615 kfree(adapter->rss_key); 10616 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10617 free_netdev(netdev); 10618 10619 pci_disable_pcie_error_reporting(pdev); 10620 10621 if (disable_dev) 10622 pci_disable_device(pdev); 10623 } 10624 10625 /** 10626 * ixgbe_io_error_detected - called when PCI error is detected 10627 * @pdev: Pointer to PCI device 10628 * @state: The current pci connection state 10629 * 10630 * This function is called after a PCI bus error affecting 10631 * this device has been detected. 10632 */ 10633 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10634 pci_channel_state_t state) 10635 { 10636 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10637 struct net_device *netdev = adapter->netdev; 10638 10639 #ifdef CONFIG_PCI_IOV 10640 struct ixgbe_hw *hw = &adapter->hw; 10641 struct pci_dev *bdev, *vfdev; 10642 u32 dw0, dw1, dw2, dw3; 10643 int vf, pos; 10644 u16 req_id, pf_func; 10645 10646 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10647 adapter->num_vfs == 0) 10648 goto skip_bad_vf_detection; 10649 10650 bdev = pdev->bus->self; 10651 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10652 bdev = bdev->bus->self; 10653 10654 if (!bdev) 10655 goto skip_bad_vf_detection; 10656 10657 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10658 if (!pos) 10659 goto skip_bad_vf_detection; 10660 10661 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10662 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10663 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10664 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10665 if (ixgbe_removed(hw->hw_addr)) 10666 goto skip_bad_vf_detection; 10667 10668 req_id = dw1 >> 16; 10669 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10670 if (!(req_id & 0x0080)) 10671 goto skip_bad_vf_detection; 10672 10673 pf_func = req_id & 0x01; 10674 if ((pf_func & 1) == (pdev->devfn & 1)) { 10675 unsigned int device_id; 10676 10677 vf = (req_id & 0x7F) >> 1; 10678 e_dev_err("VF %d has caused a PCIe error\n", vf); 10679 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10680 "%8.8x\tdw3: %8.8x\n", 10681 dw0, dw1, dw2, dw3); 10682 switch (adapter->hw.mac.type) { 10683 case ixgbe_mac_82599EB: 10684 device_id = IXGBE_82599_VF_DEVICE_ID; 10685 break; 10686 case ixgbe_mac_X540: 10687 device_id = IXGBE_X540_VF_DEVICE_ID; 10688 break; 10689 case ixgbe_mac_X550: 10690 device_id = IXGBE_DEV_ID_X550_VF; 10691 break; 10692 case ixgbe_mac_X550EM_x: 10693 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10694 break; 10695 case ixgbe_mac_x550em_a: 10696 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10697 break; 10698 default: 10699 device_id = 0; 10700 break; 10701 } 10702 10703 /* Find the pci device of the offending VF */ 10704 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10705 while (vfdev) { 10706 if (vfdev->devfn == (req_id & 0xFF)) 10707 break; 10708 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10709 device_id, vfdev); 10710 } 10711 /* 10712 * There's a slim chance the VF could have been hot plugged, 10713 * so if it is no longer present we don't need to issue the 10714 * VFLR. Just clean up the AER in that case. 10715 */ 10716 if (vfdev) { 10717 pcie_flr(vfdev); 10718 /* Free device reference count */ 10719 pci_dev_put(vfdev); 10720 } 10721 10722 pci_cleanup_aer_uncorrect_error_status(pdev); 10723 } 10724 10725 /* 10726 * Even though the error may have occurred on the other port 10727 * we still need to increment the vf error reference count for 10728 * both ports because the I/O resume function will be called 10729 * for both of them. 10730 */ 10731 adapter->vferr_refcount++; 10732 10733 return PCI_ERS_RESULT_RECOVERED; 10734 10735 skip_bad_vf_detection: 10736 #endif /* CONFIG_PCI_IOV */ 10737 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10738 return PCI_ERS_RESULT_DISCONNECT; 10739 10740 rtnl_lock(); 10741 netif_device_detach(netdev); 10742 10743 if (state == pci_channel_io_perm_failure) { 10744 rtnl_unlock(); 10745 return PCI_ERS_RESULT_DISCONNECT; 10746 } 10747 10748 if (netif_running(netdev)) 10749 ixgbe_close_suspend(adapter); 10750 10751 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10752 pci_disable_device(pdev); 10753 rtnl_unlock(); 10754 10755 /* Request a slot reset. */ 10756 return PCI_ERS_RESULT_NEED_RESET; 10757 } 10758 10759 /** 10760 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10761 * @pdev: Pointer to PCI device 10762 * 10763 * Restart the card from scratch, as if from a cold-boot. 10764 */ 10765 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10766 { 10767 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10768 pci_ers_result_t result; 10769 int err; 10770 10771 if (pci_enable_device_mem(pdev)) { 10772 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10773 result = PCI_ERS_RESULT_DISCONNECT; 10774 } else { 10775 smp_mb__before_atomic(); 10776 clear_bit(__IXGBE_DISABLED, &adapter->state); 10777 adapter->hw.hw_addr = adapter->io_addr; 10778 pci_set_master(pdev); 10779 pci_restore_state(pdev); 10780 pci_save_state(pdev); 10781 10782 pci_wake_from_d3(pdev, false); 10783 10784 ixgbe_reset(adapter); 10785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10786 result = PCI_ERS_RESULT_RECOVERED; 10787 } 10788 10789 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10790 if (err) { 10791 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10792 "failed 0x%0x\n", err); 10793 /* non-fatal, continue */ 10794 } 10795 10796 return result; 10797 } 10798 10799 /** 10800 * ixgbe_io_resume - called when traffic can start flowing again. 10801 * @pdev: Pointer to PCI device 10802 * 10803 * This callback is called when the error recovery driver tells us that 10804 * its OK to resume normal operation. 10805 */ 10806 static void ixgbe_io_resume(struct pci_dev *pdev) 10807 { 10808 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10809 struct net_device *netdev = adapter->netdev; 10810 10811 #ifdef CONFIG_PCI_IOV 10812 if (adapter->vferr_refcount) { 10813 e_info(drv, "Resuming after VF err\n"); 10814 adapter->vferr_refcount--; 10815 return; 10816 } 10817 10818 #endif 10819 rtnl_lock(); 10820 if (netif_running(netdev)) 10821 ixgbe_open(netdev); 10822 10823 netif_device_attach(netdev); 10824 rtnl_unlock(); 10825 } 10826 10827 static const struct pci_error_handlers ixgbe_err_handler = { 10828 .error_detected = ixgbe_io_error_detected, 10829 .slot_reset = ixgbe_io_slot_reset, 10830 .resume = ixgbe_io_resume, 10831 }; 10832 10833 static struct pci_driver ixgbe_driver = { 10834 .name = ixgbe_driver_name, 10835 .id_table = ixgbe_pci_tbl, 10836 .probe = ixgbe_probe, 10837 .remove = ixgbe_remove, 10838 #ifdef CONFIG_PM 10839 .suspend = ixgbe_suspend, 10840 .resume = ixgbe_resume, 10841 #endif 10842 .shutdown = ixgbe_shutdown, 10843 .sriov_configure = ixgbe_pci_sriov_configure, 10844 .err_handler = &ixgbe_err_handler 10845 }; 10846 10847 /** 10848 * ixgbe_init_module - Driver Registration Routine 10849 * 10850 * ixgbe_init_module is the first routine called when the driver is 10851 * loaded. All it does is register with the PCI subsystem. 10852 **/ 10853 static int __init ixgbe_init_module(void) 10854 { 10855 int ret; 10856 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 10857 pr_info("%s\n", ixgbe_copyright); 10858 10859 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 10860 if (!ixgbe_wq) { 10861 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 10862 return -ENOMEM; 10863 } 10864 10865 ixgbe_dbg_init(); 10866 10867 ret = pci_register_driver(&ixgbe_driver); 10868 if (ret) { 10869 destroy_workqueue(ixgbe_wq); 10870 ixgbe_dbg_exit(); 10871 return ret; 10872 } 10873 10874 #ifdef CONFIG_IXGBE_DCA 10875 dca_register_notify(&dca_notifier); 10876 #endif 10877 10878 return 0; 10879 } 10880 10881 module_init(ixgbe_init_module); 10882 10883 /** 10884 * ixgbe_exit_module - Driver Exit Cleanup Routine 10885 * 10886 * ixgbe_exit_module is called just before the driver is removed 10887 * from memory. 10888 **/ 10889 static void __exit ixgbe_exit_module(void) 10890 { 10891 #ifdef CONFIG_IXGBE_DCA 10892 dca_unregister_notify(&dca_notifier); 10893 #endif 10894 pci_unregister_driver(&ixgbe_driver); 10895 10896 ixgbe_dbg_exit(); 10897 if (ixgbe_wq) { 10898 destroy_workqueue(ixgbe_wq); 10899 ixgbe_wq = NULL; 10900 } 10901 } 10902 10903 #ifdef CONFIG_IXGBE_DCA 10904 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 10905 void *p) 10906 { 10907 int ret_val; 10908 10909 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 10910 __ixgbe_notify_dca); 10911 10912 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 10913 } 10914 10915 #endif /* CONFIG_IXGBE_DCA */ 10916 10917 module_exit(ixgbe_exit_module); 10918 10919 /* ixgbe_main.c */ 10920