1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2015 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <scsi/fc/fc_fcoe.h> 53 #include <net/vxlan.h> 54 55 #ifdef CONFIG_OF 56 #include <linux/of_net.h> 57 #endif 58 59 #ifdef CONFIG_SPARC 60 #include <asm/idprom.h> 61 #include <asm/prom.h> 62 #endif 63 64 #include "ixgbe.h" 65 #include "ixgbe_common.h" 66 #include "ixgbe_dcb_82599.h" 67 #include "ixgbe_sriov.h" 68 #ifdef CONFIG_IXGBE_VXLAN 69 #include <net/vxlan.h> 70 #endif 71 72 char ixgbe_driver_name[] = "ixgbe"; 73 static const char ixgbe_driver_string[] = 74 "Intel(R) 10 Gigabit PCI Express Network Driver"; 75 #ifdef IXGBE_FCOE 76 char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #else 79 static char ixgbe_default_device_descr[] = 80 "Intel(R) 10 Gigabit Network Connection"; 81 #endif 82 #define DRV_VERSION "4.0.1-k" 83 const char ixgbe_driver_version[] = DRV_VERSION; 84 static const char ixgbe_copyright[] = 85 "Copyright (c) 1999-2015 Intel Corporation."; 86 87 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 88 89 static const struct ixgbe_info *ixgbe_info_tbl[] = { 90 [board_82598] = &ixgbe_82598_info, 91 [board_82599] = &ixgbe_82599_info, 92 [board_X540] = &ixgbe_X540_info, 93 [board_X550] = &ixgbe_X550_info, 94 [board_X550EM_x] = &ixgbe_X550EM_x_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 140 /* required last entry */ 141 {0, } 142 }; 143 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 144 145 #ifdef CONFIG_IXGBE_DCA 146 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 147 void *p); 148 static struct notifier_block dca_notifier = { 149 .notifier_call = ixgbe_notify_dca, 150 .next = NULL, 151 .priority = 0 152 }; 153 #endif 154 155 #ifdef CONFIG_PCI_IOV 156 static unsigned int max_vfs; 157 module_param(max_vfs, uint, 0); 158 MODULE_PARM_DESC(max_vfs, 159 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 160 #endif /* CONFIG_PCI_IOV */ 161 162 static unsigned int allow_unsupported_sfp; 163 module_param(allow_unsupported_sfp, uint, 0); 164 MODULE_PARM_DESC(allow_unsupported_sfp, 165 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 166 167 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 168 static int debug = -1; 169 module_param(debug, int, 0); 170 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 171 172 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 173 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 174 MODULE_LICENSE("GPL"); 175 MODULE_VERSION(DRV_VERSION); 176 177 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 178 179 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 180 u32 reg, u16 *value) 181 { 182 struct pci_dev *parent_dev; 183 struct pci_bus *parent_bus; 184 185 parent_bus = adapter->pdev->bus->parent; 186 if (!parent_bus) 187 return -1; 188 189 parent_dev = parent_bus->self; 190 if (!parent_dev) 191 return -1; 192 193 if (!pci_is_pcie(parent_dev)) 194 return -1; 195 196 pcie_capability_read_word(parent_dev, reg, value); 197 if (*value == IXGBE_FAILED_READ_CFG_WORD && 198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 199 return -1; 200 return 0; 201 } 202 203 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 204 { 205 struct ixgbe_hw *hw = &adapter->hw; 206 u16 link_status = 0; 207 int err; 208 209 hw->bus.type = ixgbe_bus_type_pci_express; 210 211 /* Get the negotiated link width and speed from PCI config space of the 212 * parent, as this device is behind a switch 213 */ 214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 215 216 /* assume caller will handle error case */ 217 if (err) 218 return err; 219 220 hw->bus.width = ixgbe_convert_bus_width(link_status); 221 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 222 223 return 0; 224 } 225 226 /** 227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 228 * @hw: hw specific details 229 * 230 * This function is used by probe to determine whether a device's PCI-Express 231 * bandwidth details should be gathered from the parent bus instead of from the 232 * device. Used to ensure that various locations all have the correct device ID 233 * checks. 234 */ 235 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 236 { 237 switch (hw->device_id) { 238 case IXGBE_DEV_ID_82599_SFP_SF_QP: 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 240 return true; 241 default: 242 return false; 243 } 244 } 245 246 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 247 int expected_gts) 248 { 249 struct ixgbe_hw *hw = &adapter->hw; 250 int max_gts = 0; 251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 253 struct pci_dev *pdev; 254 255 /* Some devices are not connected over PCIe and thus do not negotiate 256 * speed. These devices do not have valid bus info, and thus any report 257 * we generate may not be correct. 258 */ 259 if (hw->bus.type == ixgbe_bus_type_internal) 260 return; 261 262 /* determine whether to use the parent device */ 263 if (ixgbe_pcie_from_parent(&adapter->hw)) 264 pdev = adapter->pdev->bus->parent->self; 265 else 266 pdev = adapter->pdev; 267 268 if (pcie_get_minimum_link(pdev, &speed, &width) || 269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 270 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 271 return; 272 } 273 274 switch (speed) { 275 case PCIE_SPEED_2_5GT: 276 /* 8b/10b encoding reduces max throughput by 20% */ 277 max_gts = 2 * width; 278 break; 279 case PCIE_SPEED_5_0GT: 280 /* 8b/10b encoding reduces max throughput by 20% */ 281 max_gts = 4 * width; 282 break; 283 case PCIE_SPEED_8_0GT: 284 /* 128b/130b encoding reduces throughput by less than 2% */ 285 max_gts = 8 * width; 286 break; 287 default: 288 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 289 return; 290 } 291 292 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 293 max_gts); 294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 298 "Unknown"), 299 width, 300 (speed == PCIE_SPEED_2_5GT ? "20%" : 301 speed == PCIE_SPEED_5_0GT ? "20%" : 302 speed == PCIE_SPEED_8_0GT ? "<2%" : 303 "Unknown")); 304 305 if (max_gts < expected_gts) { 306 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 308 expected_gts); 309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 310 } 311 } 312 313 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 314 { 315 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 316 !test_bit(__IXGBE_REMOVING, &adapter->state) && 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 318 schedule_work(&adapter->service_task); 319 } 320 321 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 322 { 323 struct ixgbe_adapter *adapter = hw->back; 324 325 if (!hw->hw_addr) 326 return; 327 hw->hw_addr = NULL; 328 e_dev_err("Adapter removed\n"); 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 330 ixgbe_service_event_schedule(adapter); 331 } 332 333 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 334 { 335 u32 value; 336 337 /* The following check not only optimizes a bit by not 338 * performing a read on the status register when the 339 * register just read was a status register read that 340 * returned IXGBE_FAILED_READ_REG. It also blocks any 341 * potential recursion. 342 */ 343 if (reg == IXGBE_STATUS) { 344 ixgbe_remove_adapter(hw); 345 return; 346 } 347 value = ixgbe_read_reg(hw, IXGBE_STATUS); 348 if (value == IXGBE_FAILED_READ_REG) 349 ixgbe_remove_adapter(hw); 350 } 351 352 /** 353 * ixgbe_read_reg - Read from device register 354 * @hw: hw specific details 355 * @reg: offset of register to read 356 * 357 * Returns : value read or IXGBE_FAILED_READ_REG if removed 358 * 359 * This function is used to read device registers. It checks for device 360 * removal by confirming any read that returns all ones by checking the 361 * status register value for all ones. This function avoids reading from 362 * the hardware if a removal was previously detected in which case it 363 * returns IXGBE_FAILED_READ_REG (all ones). 364 */ 365 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 366 { 367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 368 u32 value; 369 370 if (ixgbe_removed(reg_addr)) 371 return IXGBE_FAILED_READ_REG; 372 value = readl(reg_addr + reg); 373 if (unlikely(value == IXGBE_FAILED_READ_REG)) 374 ixgbe_check_remove(hw, reg); 375 return value; 376 } 377 378 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 379 { 380 u16 value; 381 382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 383 if (value == IXGBE_FAILED_READ_CFG_WORD) { 384 ixgbe_remove_adapter(hw); 385 return true; 386 } 387 return false; 388 } 389 390 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 391 { 392 struct ixgbe_adapter *adapter = hw->back; 393 u16 value; 394 395 if (ixgbe_removed(hw->hw_addr)) 396 return IXGBE_FAILED_READ_CFG_WORD; 397 pci_read_config_word(adapter->pdev, reg, &value); 398 if (value == IXGBE_FAILED_READ_CFG_WORD && 399 ixgbe_check_cfg_remove(hw, adapter->pdev)) 400 return IXGBE_FAILED_READ_CFG_WORD; 401 return value; 402 } 403 404 #ifdef CONFIG_PCI_IOV 405 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 406 { 407 struct ixgbe_adapter *adapter = hw->back; 408 u32 value; 409 410 if (ixgbe_removed(hw->hw_addr)) 411 return IXGBE_FAILED_READ_CFG_DWORD; 412 pci_read_config_dword(adapter->pdev, reg, &value); 413 if (value == IXGBE_FAILED_READ_CFG_DWORD && 414 ixgbe_check_cfg_remove(hw, adapter->pdev)) 415 return IXGBE_FAILED_READ_CFG_DWORD; 416 return value; 417 } 418 #endif /* CONFIG_PCI_IOV */ 419 420 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 421 { 422 struct ixgbe_adapter *adapter = hw->back; 423 424 if (ixgbe_removed(hw->hw_addr)) 425 return; 426 pci_write_config_word(adapter->pdev, reg, value); 427 } 428 429 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 430 { 431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 432 433 /* flush memory to make sure state is correct before next watchdog */ 434 smp_mb__before_atomic(); 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 436 } 437 438 struct ixgbe_reg_info { 439 u32 ofs; 440 char *name; 441 }; 442 443 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 444 445 /* General Registers */ 446 {IXGBE_CTRL, "CTRL"}, 447 {IXGBE_STATUS, "STATUS"}, 448 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 449 450 /* Interrupt Registers */ 451 {IXGBE_EICR, "EICR"}, 452 453 /* RX Registers */ 454 {IXGBE_SRRCTL(0), "SRRCTL"}, 455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 456 {IXGBE_RDLEN(0), "RDLEN"}, 457 {IXGBE_RDH(0), "RDH"}, 458 {IXGBE_RDT(0), "RDT"}, 459 {IXGBE_RXDCTL(0), "RXDCTL"}, 460 {IXGBE_RDBAL(0), "RDBAL"}, 461 {IXGBE_RDBAH(0), "RDBAH"}, 462 463 /* TX Registers */ 464 {IXGBE_TDBAL(0), "TDBAL"}, 465 {IXGBE_TDBAH(0), "TDBAH"}, 466 {IXGBE_TDLEN(0), "TDLEN"}, 467 {IXGBE_TDH(0), "TDH"}, 468 {IXGBE_TDT(0), "TDT"}, 469 {IXGBE_TXDCTL(0), "TXDCTL"}, 470 471 /* List Terminator */ 472 { .name = NULL } 473 }; 474 475 476 /* 477 * ixgbe_regdump - register printout routine 478 */ 479 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 480 { 481 int i = 0, j = 0; 482 char rname[16]; 483 u32 regs[64]; 484 485 switch (reginfo->ofs) { 486 case IXGBE_SRRCTL(0): 487 for (i = 0; i < 64; i++) 488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 489 break; 490 case IXGBE_DCA_RXCTRL(0): 491 for (i = 0; i < 64; i++) 492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 493 break; 494 case IXGBE_RDLEN(0): 495 for (i = 0; i < 64; i++) 496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 497 break; 498 case IXGBE_RDH(0): 499 for (i = 0; i < 64; i++) 500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 501 break; 502 case IXGBE_RDT(0): 503 for (i = 0; i < 64; i++) 504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 505 break; 506 case IXGBE_RXDCTL(0): 507 for (i = 0; i < 64; i++) 508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 509 break; 510 case IXGBE_RDBAL(0): 511 for (i = 0; i < 64; i++) 512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 513 break; 514 case IXGBE_RDBAH(0): 515 for (i = 0; i < 64; i++) 516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 517 break; 518 case IXGBE_TDBAL(0): 519 for (i = 0; i < 64; i++) 520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 521 break; 522 case IXGBE_TDBAH(0): 523 for (i = 0; i < 64; i++) 524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 525 break; 526 case IXGBE_TDLEN(0): 527 for (i = 0; i < 64; i++) 528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 529 break; 530 case IXGBE_TDH(0): 531 for (i = 0; i < 64; i++) 532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 533 break; 534 case IXGBE_TDT(0): 535 for (i = 0; i < 64; i++) 536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 537 break; 538 case IXGBE_TXDCTL(0): 539 for (i = 0; i < 64; i++) 540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 541 break; 542 default: 543 pr_info("%-15s %08x\n", reginfo->name, 544 IXGBE_READ_REG(hw, reginfo->ofs)); 545 return; 546 } 547 548 for (i = 0; i < 8; i++) { 549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); 550 pr_err("%-15s", rname); 551 for (j = 0; j < 8; j++) 552 pr_cont(" %08x", regs[i*8+j]); 553 pr_cont("\n"); 554 } 555 556 } 557 558 /* 559 * ixgbe_dump - Print registers, tx-rings and rx-rings 560 */ 561 static void ixgbe_dump(struct ixgbe_adapter *adapter) 562 { 563 struct net_device *netdev = adapter->netdev; 564 struct ixgbe_hw *hw = &adapter->hw; 565 struct ixgbe_reg_info *reginfo; 566 int n = 0; 567 struct ixgbe_ring *tx_ring; 568 struct ixgbe_tx_buffer *tx_buffer; 569 union ixgbe_adv_tx_desc *tx_desc; 570 struct my_u0 { u64 a; u64 b; } *u0; 571 struct ixgbe_ring *rx_ring; 572 union ixgbe_adv_rx_desc *rx_desc; 573 struct ixgbe_rx_buffer *rx_buffer_info; 574 u32 staterr; 575 int i = 0; 576 577 if (!netif_msg_hw(adapter)) 578 return; 579 580 /* Print netdevice Info */ 581 if (netdev) { 582 dev_info(&adapter->pdev->dev, "Net device Info\n"); 583 pr_info("Device Name state " 584 "trans_start last_rx\n"); 585 pr_info("%-15s %016lX %016lX %016lX\n", 586 netdev->name, 587 netdev->state, 588 netdev->trans_start, 589 netdev->last_rx); 590 } 591 592 /* Print Registers */ 593 dev_info(&adapter->pdev->dev, "Register Dump\n"); 594 pr_info(" Register Name Value\n"); 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 596 reginfo->name; reginfo++) { 597 ixgbe_regdump(hw, reginfo); 598 } 599 600 /* Print TX Ring Summary */ 601 if (!netdev || !netif_running(netdev)) 602 return; 603 604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 605 pr_info(" %s %s %s %s\n", 606 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 607 "leng", "ntw", "timestamp"); 608 for (n = 0; n < adapter->num_tx_queues; n++) { 609 tx_ring = adapter->tx_ring[n]; 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 612 n, tx_ring->next_to_use, tx_ring->next_to_clean, 613 (u64)dma_unmap_addr(tx_buffer, dma), 614 dma_unmap_len(tx_buffer, len), 615 tx_buffer->next_to_watch, 616 (u64)tx_buffer->time_stamp); 617 } 618 619 /* Print TX Rings */ 620 if (!netif_msg_tx_done(adapter)) 621 goto rx_ring_summary; 622 623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 624 625 /* Transmit Descriptor Formats 626 * 627 * 82598 Advanced Transmit Descriptor 628 * +--------------------------------------------------------------+ 629 * 0 | Buffer Address [63:0] | 630 * +--------------------------------------------------------------+ 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 632 * +--------------------------------------------------------------+ 633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 634 * 635 * 82598 Advanced Transmit Descriptor (Write-Back Format) 636 * +--------------------------------------------------------------+ 637 * 0 | RSV [63:0] | 638 * +--------------------------------------------------------------+ 639 * 8 | RSV | STA | NXTSEQ | 640 * +--------------------------------------------------------------+ 641 * 63 36 35 32 31 0 642 * 643 * 82599+ Advanced Transmit Descriptor 644 * +--------------------------------------------------------------+ 645 * 0 | Buffer Address [63:0] | 646 * +--------------------------------------------------------------+ 647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 648 * +--------------------------------------------------------------+ 649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 650 * 651 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 652 * +--------------------------------------------------------------+ 653 * 0 | RSV [63:0] | 654 * +--------------------------------------------------------------+ 655 * 8 | RSV | STA | RSV | 656 * +--------------------------------------------------------------+ 657 * 63 36 35 32 31 0 658 */ 659 660 for (n = 0; n < adapter->num_tx_queues; n++) { 661 tx_ring = adapter->tx_ring[n]; 662 pr_info("------------------------------------\n"); 663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 664 pr_info("------------------------------------\n"); 665 pr_info("%s%s %s %s %s %s\n", 666 "T [desc] [address 63:0 ] ", 667 "[PlPOIdStDDt Ln] [bi->dma ] ", 668 "leng", "ntw", "timestamp", "bi->skb"); 669 670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 671 tx_desc = IXGBE_TX_DESC(tx_ring, i); 672 tx_buffer = &tx_ring->tx_buffer_info[i]; 673 u0 = (struct my_u0 *)tx_desc; 674 if (dma_unmap_len(tx_buffer, len) > 0) { 675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", 676 i, 677 le64_to_cpu(u0->a), 678 le64_to_cpu(u0->b), 679 (u64)dma_unmap_addr(tx_buffer, dma), 680 dma_unmap_len(tx_buffer, len), 681 tx_buffer->next_to_watch, 682 (u64)tx_buffer->time_stamp, 683 tx_buffer->skb); 684 if (i == tx_ring->next_to_use && 685 i == tx_ring->next_to_clean) 686 pr_cont(" NTC/U\n"); 687 else if (i == tx_ring->next_to_use) 688 pr_cont(" NTU\n"); 689 else if (i == tx_ring->next_to_clean) 690 pr_cont(" NTC\n"); 691 else 692 pr_cont("\n"); 693 694 if (netif_msg_pktdata(adapter) && 695 tx_buffer->skb) 696 print_hex_dump(KERN_INFO, "", 697 DUMP_PREFIX_ADDRESS, 16, 1, 698 tx_buffer->skb->data, 699 dma_unmap_len(tx_buffer, len), 700 true); 701 } 702 } 703 } 704 705 /* Print RX Rings Summary */ 706 rx_ring_summary: 707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 708 pr_info("Queue [NTU] [NTC]\n"); 709 for (n = 0; n < adapter->num_rx_queues; n++) { 710 rx_ring = adapter->rx_ring[n]; 711 pr_info("%5d %5X %5X\n", 712 n, rx_ring->next_to_use, rx_ring->next_to_clean); 713 } 714 715 /* Print RX Rings */ 716 if (!netif_msg_rx_status(adapter)) 717 return; 718 719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 720 721 /* Receive Descriptor Formats 722 * 723 * 82598 Advanced Receive Descriptor (Read) Format 724 * 63 1 0 725 * +-----------------------------------------------------+ 726 * 0 | Packet Buffer Address [63:1] |A0/NSE| 727 * +----------------------------------------------+------+ 728 * 8 | Header Buffer Address [63:1] | DD | 729 * +-----------------------------------------------------+ 730 * 731 * 732 * 82598 Advanced Receive Descriptor (Write-Back) Format 733 * 734 * 63 48 47 32 31 30 21 20 16 15 4 3 0 735 * +------------------------------------------------------+ 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 737 * | Packet | IP | | | | Type | Type | 738 * | Checksum | Ident | | | | | | 739 * +------------------------------------------------------+ 740 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 741 * +------------------------------------------------------+ 742 * 63 48 47 32 31 20 19 0 743 * 744 * 82599+ Advanced Receive Descriptor (Read) Format 745 * 63 1 0 746 * +-----------------------------------------------------+ 747 * 0 | Packet Buffer Address [63:1] |A0/NSE| 748 * +----------------------------------------------+------+ 749 * 8 | Header Buffer Address [63:1] | DD | 750 * +-----------------------------------------------------+ 751 * 752 * 753 * 82599+ Advanced Receive Descriptor (Write-Back) Format 754 * 755 * 63 48 47 32 31 30 21 20 17 16 4 3 0 756 * +------------------------------------------------------+ 757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 759 * |/ Flow Dir Flt ID | | | | | | 760 * +------------------------------------------------------+ 761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 762 * +------------------------------------------------------+ 763 * 63 48 47 32 31 20 19 0 764 */ 765 766 for (n = 0; n < adapter->num_rx_queues; n++) { 767 rx_ring = adapter->rx_ring[n]; 768 pr_info("------------------------------------\n"); 769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 770 pr_info("------------------------------------\n"); 771 pr_info("%s%s%s", 772 "R [desc] [ PktBuf A0] ", 773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 774 "<-- Adv Rx Read format\n"); 775 pr_info("%s%s%s", 776 "RWB[desc] [PcsmIpSHl PtRs] ", 777 "[vl er S cks ln] ---------------- [bi->skb ] ", 778 "<-- Adv Rx Write-Back format\n"); 779 780 for (i = 0; i < rx_ring->count; i++) { 781 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 782 rx_desc = IXGBE_RX_DESC(rx_ring, i); 783 u0 = (struct my_u0 *)rx_desc; 784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 785 if (staterr & IXGBE_RXD_STAT_DD) { 786 /* Descriptor Done */ 787 pr_info("RWB[0x%03X] %016llX " 788 "%016llX ---------------- %p", i, 789 le64_to_cpu(u0->a), 790 le64_to_cpu(u0->b), 791 rx_buffer_info->skb); 792 } else { 793 pr_info("R [0x%03X] %016llX " 794 "%016llX %016llX %p", i, 795 le64_to_cpu(u0->a), 796 le64_to_cpu(u0->b), 797 (u64)rx_buffer_info->dma, 798 rx_buffer_info->skb); 799 800 if (netif_msg_pktdata(adapter) && 801 rx_buffer_info->dma) { 802 print_hex_dump(KERN_INFO, "", 803 DUMP_PREFIX_ADDRESS, 16, 1, 804 page_address(rx_buffer_info->page) + 805 rx_buffer_info->page_offset, 806 ixgbe_rx_bufsz(rx_ring), true); 807 } 808 } 809 810 if (i == rx_ring->next_to_use) 811 pr_cont(" NTU\n"); 812 else if (i == rx_ring->next_to_clean) 813 pr_cont(" NTC\n"); 814 else 815 pr_cont("\n"); 816 817 } 818 } 819 } 820 821 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 822 { 823 u32 ctrl_ext; 824 825 /* Let firmware take over control of h/w */ 826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 829 } 830 831 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 832 { 833 u32 ctrl_ext; 834 835 /* Let firmware know the driver has taken over */ 836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 839 } 840 841 /** 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 843 * @adapter: pointer to adapter struct 844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 845 * @queue: queue to map the corresponding interrupt to 846 * @msix_vector: the vector to map to the corresponding queue 847 * 848 */ 849 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 850 u8 queue, u8 msix_vector) 851 { 852 u32 ivar, index; 853 struct ixgbe_hw *hw = &adapter->hw; 854 switch (hw->mac.type) { 855 case ixgbe_mac_82598EB: 856 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 857 if (direction == -1) 858 direction = 0; 859 index = (((direction * 64) + queue) >> 2) & 0x1F; 860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 861 ivar &= ~(0xFF << (8 * (queue & 0x3))); 862 ivar |= (msix_vector << (8 * (queue & 0x3))); 863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 864 break; 865 case ixgbe_mac_82599EB: 866 case ixgbe_mac_X540: 867 case ixgbe_mac_X550: 868 case ixgbe_mac_X550EM_x: 869 if (direction == -1) { 870 /* other causes */ 871 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 872 index = ((queue & 1) * 8); 873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 874 ivar &= ~(0xFF << index); 875 ivar |= (msix_vector << index); 876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 877 break; 878 } else { 879 /* tx or rx causes */ 880 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 881 index = ((16 * (queue & 1)) + (8 * direction)); 882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 883 ivar &= ~(0xFF << index); 884 ivar |= (msix_vector << index); 885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 886 break; 887 } 888 default: 889 break; 890 } 891 } 892 893 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 894 u64 qmask) 895 { 896 u32 mask; 897 898 switch (adapter->hw.mac.type) { 899 case ixgbe_mac_82598EB: 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 902 break; 903 case ixgbe_mac_82599EB: 904 case ixgbe_mac_X540: 905 case ixgbe_mac_X550: 906 case ixgbe_mac_X550EM_x: 907 mask = (qmask & 0xFFFFFFFF); 908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 909 mask = (qmask >> 32); 910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 911 break; 912 default: 913 break; 914 } 915 } 916 917 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, 918 struct ixgbe_tx_buffer *tx_buffer) 919 { 920 if (tx_buffer->skb) { 921 dev_kfree_skb_any(tx_buffer->skb); 922 if (dma_unmap_len(tx_buffer, len)) 923 dma_unmap_single(ring->dev, 924 dma_unmap_addr(tx_buffer, dma), 925 dma_unmap_len(tx_buffer, len), 926 DMA_TO_DEVICE); 927 } else if (dma_unmap_len(tx_buffer, len)) { 928 dma_unmap_page(ring->dev, 929 dma_unmap_addr(tx_buffer, dma), 930 dma_unmap_len(tx_buffer, len), 931 DMA_TO_DEVICE); 932 } 933 tx_buffer->next_to_watch = NULL; 934 tx_buffer->skb = NULL; 935 dma_unmap_len_set(tx_buffer, len, 0); 936 /* tx_buffer must be completely set up in the transmit path */ 937 } 938 939 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 940 { 941 struct ixgbe_hw *hw = &adapter->hw; 942 struct ixgbe_hw_stats *hwstats = &adapter->stats; 943 int i; 944 u32 data; 945 946 if ((hw->fc.current_mode != ixgbe_fc_full) && 947 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 948 return; 949 950 switch (hw->mac.type) { 951 case ixgbe_mac_82598EB: 952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 953 break; 954 default: 955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 956 } 957 hwstats->lxoffrxc += data; 958 959 /* refill credits (no tx hang) if we received xoff */ 960 if (!data) 961 return; 962 963 for (i = 0; i < adapter->num_tx_queues; i++) 964 clear_bit(__IXGBE_HANG_CHECK_ARMED, 965 &adapter->tx_ring[i]->state); 966 } 967 968 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 969 { 970 struct ixgbe_hw *hw = &adapter->hw; 971 struct ixgbe_hw_stats *hwstats = &adapter->stats; 972 u32 xoff[8] = {0}; 973 u8 tc; 974 int i; 975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 976 977 if (adapter->ixgbe_ieee_pfc) 978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 979 980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 981 ixgbe_update_xoff_rx_lfc(adapter); 982 return; 983 } 984 985 /* update stats for each tc, only valid with PFC enabled */ 986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 987 u32 pxoffrxc; 988 989 switch (hw->mac.type) { 990 case ixgbe_mac_82598EB: 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 992 break; 993 default: 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 995 } 996 hwstats->pxoffrxc[i] += pxoffrxc; 997 /* Get the TC for given UP */ 998 tc = netdev_get_prio_tc_map(adapter->netdev, i); 999 xoff[tc] += pxoffrxc; 1000 } 1001 1002 /* disarm tx queues that have received xoff frames */ 1003 for (i = 0; i < adapter->num_tx_queues; i++) { 1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1005 1006 tc = tx_ring->dcb_tc; 1007 if (xoff[tc]) 1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1009 } 1010 } 1011 1012 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1013 { 1014 return ring->stats.packets; 1015 } 1016 1017 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1018 { 1019 struct ixgbe_adapter *adapter; 1020 struct ixgbe_hw *hw; 1021 u32 head, tail; 1022 1023 if (ring->l2_accel_priv) 1024 adapter = ring->l2_accel_priv->real_adapter; 1025 else 1026 adapter = netdev_priv(ring->netdev); 1027 1028 hw = &adapter->hw; 1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1031 1032 if (head != tail) 1033 return (head < tail) ? 1034 tail - head : (tail + ring->count - head); 1035 1036 return 0; 1037 } 1038 1039 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1040 { 1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1044 1045 clear_check_for_tx_hang(tx_ring); 1046 1047 /* 1048 * Check for a hung queue, but be thorough. This verifies 1049 * that a transmit has been completed since the previous 1050 * check AND there is at least one packet pending. The 1051 * ARMED bit is set to indicate a potential hang. The 1052 * bit is cleared if a pause frame is received to remove 1053 * false hang detection due to PFC or 802.3x frames. By 1054 * requiring this to fail twice we avoid races with 1055 * pfc clearing the ARMED bit and conditions where we 1056 * run the check_tx_hang logic with a transmit completion 1057 * pending but without time to complete it yet. 1058 */ 1059 if (tx_done_old == tx_done && tx_pending) 1060 /* make sure it is true for two checks in a row */ 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1062 &tx_ring->state); 1063 /* update completed stats and continue */ 1064 tx_ring->tx_stats.tx_done_old = tx_done; 1065 /* reset the countdown */ 1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1067 1068 return false; 1069 } 1070 1071 /** 1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1073 * @adapter: driver private struct 1074 **/ 1075 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1076 { 1077 1078 /* Do the reset outside of interrupt context */ 1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 1081 e_warn(drv, "initiating reset due to tx timeout\n"); 1082 ixgbe_service_event_schedule(adapter); 1083 } 1084 } 1085 1086 /** 1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1088 * @q_vector: structure containing interrupt and ring information 1089 * @tx_ring: tx ring to clean 1090 **/ 1091 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1092 struct ixgbe_ring *tx_ring) 1093 { 1094 struct ixgbe_adapter *adapter = q_vector->adapter; 1095 struct ixgbe_tx_buffer *tx_buffer; 1096 union ixgbe_adv_tx_desc *tx_desc; 1097 unsigned int total_bytes = 0, total_packets = 0; 1098 unsigned int budget = q_vector->tx.work_limit; 1099 unsigned int i = tx_ring->next_to_clean; 1100 1101 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1102 return true; 1103 1104 tx_buffer = &tx_ring->tx_buffer_info[i]; 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1106 i -= tx_ring->count; 1107 1108 do { 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1110 1111 /* if next_to_watch is not set then there is no work pending */ 1112 if (!eop_desc) 1113 break; 1114 1115 /* prevent any other reads prior to eop_desc */ 1116 read_barrier_depends(); 1117 1118 /* if DD is not set pending work has not been completed */ 1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1120 break; 1121 1122 /* clear next_to_watch to prevent false hangs */ 1123 tx_buffer->next_to_watch = NULL; 1124 1125 /* update the statistics for this packet */ 1126 total_bytes += tx_buffer->bytecount; 1127 total_packets += tx_buffer->gso_segs; 1128 1129 /* free the skb */ 1130 dev_consume_skb_any(tx_buffer->skb); 1131 1132 /* unmap skb header data */ 1133 dma_unmap_single(tx_ring->dev, 1134 dma_unmap_addr(tx_buffer, dma), 1135 dma_unmap_len(tx_buffer, len), 1136 DMA_TO_DEVICE); 1137 1138 /* clear tx_buffer data */ 1139 tx_buffer->skb = NULL; 1140 dma_unmap_len_set(tx_buffer, len, 0); 1141 1142 /* unmap remaining buffers */ 1143 while (tx_desc != eop_desc) { 1144 tx_buffer++; 1145 tx_desc++; 1146 i++; 1147 if (unlikely(!i)) { 1148 i -= tx_ring->count; 1149 tx_buffer = tx_ring->tx_buffer_info; 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1151 } 1152 1153 /* unmap any remaining paged data */ 1154 if (dma_unmap_len(tx_buffer, len)) { 1155 dma_unmap_page(tx_ring->dev, 1156 dma_unmap_addr(tx_buffer, dma), 1157 dma_unmap_len(tx_buffer, len), 1158 DMA_TO_DEVICE); 1159 dma_unmap_len_set(tx_buffer, len, 0); 1160 } 1161 } 1162 1163 /* move us one more past the eop_desc for start of next pkt */ 1164 tx_buffer++; 1165 tx_desc++; 1166 i++; 1167 if (unlikely(!i)) { 1168 i -= tx_ring->count; 1169 tx_buffer = tx_ring->tx_buffer_info; 1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1171 } 1172 1173 /* issue prefetch for next Tx descriptor */ 1174 prefetch(tx_desc); 1175 1176 /* update budget accounting */ 1177 budget--; 1178 } while (likely(budget)); 1179 1180 i += tx_ring->count; 1181 tx_ring->next_to_clean = i; 1182 u64_stats_update_begin(&tx_ring->syncp); 1183 tx_ring->stats.bytes += total_bytes; 1184 tx_ring->stats.packets += total_packets; 1185 u64_stats_update_end(&tx_ring->syncp); 1186 q_vector->tx.total_bytes += total_bytes; 1187 q_vector->tx.total_packets += total_packets; 1188 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1190 /* schedule immediate reset if we believe we hung */ 1191 struct ixgbe_hw *hw = &adapter->hw; 1192 e_err(drv, "Detected Tx Unit Hang\n" 1193 " Tx Queue <%d>\n" 1194 " TDH, TDT <%x>, <%x>\n" 1195 " next_to_use <%x>\n" 1196 " next_to_clean <%x>\n" 1197 "tx_buffer_info[next_to_clean]\n" 1198 " time_stamp <%lx>\n" 1199 " jiffies <%lx>\n", 1200 tx_ring->queue_index, 1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1203 tx_ring->next_to_use, i, 1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1205 1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 1207 1208 e_info(probe, 1209 "tx hang %d detected on queue %d, resetting adapter\n", 1210 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1211 1212 /* schedule immediate reset if we believe we hung */ 1213 ixgbe_tx_timeout_reset(adapter); 1214 1215 /* the adapter is about to reset, no point in enabling stuff */ 1216 return true; 1217 } 1218 1219 netdev_tx_completed_queue(txring_txq(tx_ring), 1220 total_packets, total_bytes); 1221 1222 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1225 /* Make sure that anybody stopping the queue after this 1226 * sees the new next_to_clean. 1227 */ 1228 smp_mb(); 1229 if (__netif_subqueue_stopped(tx_ring->netdev, 1230 tx_ring->queue_index) 1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1232 netif_wake_subqueue(tx_ring->netdev, 1233 tx_ring->queue_index); 1234 ++tx_ring->tx_stats.restart_queue; 1235 } 1236 } 1237 1238 return !!budget; 1239 } 1240 1241 #ifdef CONFIG_IXGBE_DCA 1242 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1243 struct ixgbe_ring *tx_ring, 1244 int cpu) 1245 { 1246 struct ixgbe_hw *hw = &adapter->hw; 1247 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1248 u16 reg_offset; 1249 1250 switch (hw->mac.type) { 1251 case ixgbe_mac_82598EB: 1252 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1253 break; 1254 case ixgbe_mac_82599EB: 1255 case ixgbe_mac_X540: 1256 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1257 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1258 break; 1259 default: 1260 /* for unknown hardware do not write register */ 1261 return; 1262 } 1263 1264 /* 1265 * We can enable relaxed ordering for reads, but not writes when 1266 * DCA is enabled. This is due to a known issue in some chipsets 1267 * which will cause the DCA tag to be cleared. 1268 */ 1269 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1270 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1271 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1272 1273 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1274 } 1275 1276 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1277 struct ixgbe_ring *rx_ring, 1278 int cpu) 1279 { 1280 struct ixgbe_hw *hw = &adapter->hw; 1281 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1282 u8 reg_idx = rx_ring->reg_idx; 1283 1284 1285 switch (hw->mac.type) { 1286 case ixgbe_mac_82599EB: 1287 case ixgbe_mac_X540: 1288 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1289 break; 1290 default: 1291 break; 1292 } 1293 1294 /* 1295 * We can enable relaxed ordering for reads, but not writes when 1296 * DCA is enabled. This is due to a known issue in some chipsets 1297 * which will cause the DCA tag to be cleared. 1298 */ 1299 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1300 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1301 1302 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1303 } 1304 1305 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1306 { 1307 struct ixgbe_adapter *adapter = q_vector->adapter; 1308 struct ixgbe_ring *ring; 1309 int cpu = get_cpu(); 1310 1311 if (q_vector->cpu == cpu) 1312 goto out_no_update; 1313 1314 ixgbe_for_each_ring(ring, q_vector->tx) 1315 ixgbe_update_tx_dca(adapter, ring, cpu); 1316 1317 ixgbe_for_each_ring(ring, q_vector->rx) 1318 ixgbe_update_rx_dca(adapter, ring, cpu); 1319 1320 q_vector->cpu = cpu; 1321 out_no_update: 1322 put_cpu(); 1323 } 1324 1325 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1326 { 1327 int i; 1328 1329 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) 1330 return; 1331 1332 /* always use CB2 mode, difference is masked in the CB driver */ 1333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); 1334 1335 for (i = 0; i < adapter->num_q_vectors; i++) { 1336 adapter->q_vector[i]->cpu = -1; 1337 ixgbe_update_dca(adapter->q_vector[i]); 1338 } 1339 } 1340 1341 static int __ixgbe_notify_dca(struct device *dev, void *data) 1342 { 1343 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1344 unsigned long event = *(unsigned long *)data; 1345 1346 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1347 return 0; 1348 1349 switch (event) { 1350 case DCA_PROVIDER_ADD: 1351 /* if we're already enabled, don't do it again */ 1352 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1353 break; 1354 if (dca_add_requester(dev) == 0) { 1355 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1356 ixgbe_setup_dca(adapter); 1357 break; 1358 } 1359 /* Fall Through since DCA is disabled. */ 1360 case DCA_PROVIDER_REMOVE: 1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1362 dca_remove_requester(dev); 1363 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 1365 } 1366 break; 1367 } 1368 1369 return 0; 1370 } 1371 1372 #endif /* CONFIG_IXGBE_DCA */ 1373 1374 #define IXGBE_RSS_L4_TYPES_MASK \ 1375 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1376 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1377 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1378 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1379 1380 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1381 union ixgbe_adv_rx_desc *rx_desc, 1382 struct sk_buff *skb) 1383 { 1384 u16 rss_type; 1385 1386 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1387 return; 1388 1389 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1390 IXGBE_RXDADV_RSSTYPE_MASK; 1391 1392 if (!rss_type) 1393 return; 1394 1395 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1396 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1397 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1398 } 1399 1400 #ifdef IXGBE_FCOE 1401 /** 1402 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1403 * @ring: structure containing ring specific data 1404 * @rx_desc: advanced rx descriptor 1405 * 1406 * Returns : true if it is FCoE pkt 1407 */ 1408 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1409 union ixgbe_adv_rx_desc *rx_desc) 1410 { 1411 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1412 1413 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1414 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1415 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1416 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1417 } 1418 1419 #endif /* IXGBE_FCOE */ 1420 /** 1421 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1422 * @ring: structure containing ring specific data 1423 * @rx_desc: current Rx descriptor being processed 1424 * @skb: skb currently being received and modified 1425 **/ 1426 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1427 union ixgbe_adv_rx_desc *rx_desc, 1428 struct sk_buff *skb) 1429 { 1430 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1431 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; 1432 bool encap_pkt = false; 1433 1434 skb_checksum_none_assert(skb); 1435 1436 /* Rx csum disabled */ 1437 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1438 return; 1439 1440 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) && 1441 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) { 1442 encap_pkt = true; 1443 skb->encapsulation = 1; 1444 } 1445 1446 /* if IP and error */ 1447 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1448 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1449 ring->rx_stats.csum_err++; 1450 return; 1451 } 1452 1453 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1454 return; 1455 1456 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1457 /* 1458 * 82599 errata, UDP frames with a 0 checksum can be marked as 1459 * checksum errors. 1460 */ 1461 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1462 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1463 return; 1464 1465 ring->rx_stats.csum_err++; 1466 return; 1467 } 1468 1469 /* It must be a TCP or UDP packet with a valid checksum */ 1470 skb->ip_summed = CHECKSUM_UNNECESSARY; 1471 if (encap_pkt) { 1472 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1473 return; 1474 1475 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1476 ring->rx_stats.csum_err++; 1477 return; 1478 } 1479 /* If we checked the outer header let the stack know */ 1480 skb->csum_level = 1; 1481 } 1482 } 1483 1484 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1485 struct ixgbe_rx_buffer *bi) 1486 { 1487 struct page *page = bi->page; 1488 dma_addr_t dma; 1489 1490 /* since we are recycling buffers we should seldom need to alloc */ 1491 if (likely(page)) 1492 return true; 1493 1494 /* alloc new page for storage */ 1495 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1496 if (unlikely(!page)) { 1497 rx_ring->rx_stats.alloc_rx_page_failed++; 1498 return false; 1499 } 1500 1501 /* map page for use */ 1502 dma = dma_map_page(rx_ring->dev, page, 0, 1503 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1504 1505 /* 1506 * if mapping failed free memory back to system since 1507 * there isn't much point in holding memory we can't use 1508 */ 1509 if (dma_mapping_error(rx_ring->dev, dma)) { 1510 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1511 1512 rx_ring->rx_stats.alloc_rx_page_failed++; 1513 return false; 1514 } 1515 1516 bi->dma = dma; 1517 bi->page = page; 1518 bi->page_offset = 0; 1519 1520 return true; 1521 } 1522 1523 /** 1524 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1525 * @rx_ring: ring to place buffers on 1526 * @cleaned_count: number of buffers to replace 1527 **/ 1528 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1529 { 1530 union ixgbe_adv_rx_desc *rx_desc; 1531 struct ixgbe_rx_buffer *bi; 1532 u16 i = rx_ring->next_to_use; 1533 1534 /* nothing to do */ 1535 if (!cleaned_count) 1536 return; 1537 1538 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1539 bi = &rx_ring->rx_buffer_info[i]; 1540 i -= rx_ring->count; 1541 1542 do { 1543 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1544 break; 1545 1546 /* 1547 * Refresh the desc even if buffer_addrs didn't change 1548 * because each write-back erases this info. 1549 */ 1550 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1551 1552 rx_desc++; 1553 bi++; 1554 i++; 1555 if (unlikely(!i)) { 1556 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1557 bi = rx_ring->rx_buffer_info; 1558 i -= rx_ring->count; 1559 } 1560 1561 /* clear the status bits for the next_to_use descriptor */ 1562 rx_desc->wb.upper.status_error = 0; 1563 1564 cleaned_count--; 1565 } while (cleaned_count); 1566 1567 i += rx_ring->count; 1568 1569 if (rx_ring->next_to_use != i) { 1570 rx_ring->next_to_use = i; 1571 1572 /* update next to alloc since we have filled the ring */ 1573 rx_ring->next_to_alloc = i; 1574 1575 /* Force memory writes to complete before letting h/w 1576 * know there are new descriptors to fetch. (Only 1577 * applicable for weak-ordered memory model archs, 1578 * such as IA-64). 1579 */ 1580 wmb(); 1581 writel(i, rx_ring->tail); 1582 } 1583 } 1584 1585 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1586 struct sk_buff *skb) 1587 { 1588 u16 hdr_len = skb_headlen(skb); 1589 1590 /* set gso_size to avoid messing up TCP MSS */ 1591 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1592 IXGBE_CB(skb)->append_cnt); 1593 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1594 } 1595 1596 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1597 struct sk_buff *skb) 1598 { 1599 /* if append_cnt is 0 then frame is not RSC */ 1600 if (!IXGBE_CB(skb)->append_cnt) 1601 return; 1602 1603 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1604 rx_ring->rx_stats.rsc_flush++; 1605 1606 ixgbe_set_rsc_gso_size(rx_ring, skb); 1607 1608 /* gso_size is computed using append_cnt so always clear it last */ 1609 IXGBE_CB(skb)->append_cnt = 0; 1610 } 1611 1612 /** 1613 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1614 * @rx_ring: rx descriptor ring packet is being transacted on 1615 * @rx_desc: pointer to the EOP Rx descriptor 1616 * @skb: pointer to current skb being populated 1617 * 1618 * This function checks the ring, descriptor, and packet information in 1619 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1620 * other fields within the skb. 1621 **/ 1622 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1623 union ixgbe_adv_rx_desc *rx_desc, 1624 struct sk_buff *skb) 1625 { 1626 struct net_device *dev = rx_ring->netdev; 1627 1628 ixgbe_update_rsc_stats(rx_ring, skb); 1629 1630 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1631 1632 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1633 1634 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1635 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb); 1636 1637 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1638 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1639 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1641 } 1642 1643 skb_record_rx_queue(skb, rx_ring->queue_index); 1644 1645 skb->protocol = eth_type_trans(skb, dev); 1646 } 1647 1648 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1649 struct sk_buff *skb) 1650 { 1651 if (ixgbe_qv_busy_polling(q_vector)) 1652 netif_receive_skb(skb); 1653 else 1654 napi_gro_receive(&q_vector->napi, skb); 1655 } 1656 1657 /** 1658 * ixgbe_is_non_eop - process handling of non-EOP buffers 1659 * @rx_ring: Rx ring being processed 1660 * @rx_desc: Rx descriptor for current buffer 1661 * @skb: Current socket buffer containing buffer in progress 1662 * 1663 * This function updates next to clean. If the buffer is an EOP buffer 1664 * this function exits returning false, otherwise it will place the 1665 * sk_buff in the next buffer to be chained and return true indicating 1666 * that this is in fact a non-EOP buffer. 1667 **/ 1668 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1669 union ixgbe_adv_rx_desc *rx_desc, 1670 struct sk_buff *skb) 1671 { 1672 u32 ntc = rx_ring->next_to_clean + 1; 1673 1674 /* fetch, update, and store next to clean */ 1675 ntc = (ntc < rx_ring->count) ? ntc : 0; 1676 rx_ring->next_to_clean = ntc; 1677 1678 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1679 1680 /* update RSC append count if present */ 1681 if (ring_is_rsc_enabled(rx_ring)) { 1682 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1683 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1684 1685 if (unlikely(rsc_enabled)) { 1686 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1687 1688 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1689 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1690 1691 /* update ntc based on RSC value */ 1692 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1693 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1694 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1695 } 1696 } 1697 1698 /* if we are the last buffer then there is nothing else to do */ 1699 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1700 return false; 1701 1702 /* place skb in next buffer to be received */ 1703 rx_ring->rx_buffer_info[ntc].skb = skb; 1704 rx_ring->rx_stats.non_eop_descs++; 1705 1706 return true; 1707 } 1708 1709 /** 1710 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1711 * @rx_ring: rx descriptor ring packet is being transacted on 1712 * @skb: pointer to current skb being adjusted 1713 * 1714 * This function is an ixgbe specific version of __pskb_pull_tail. The 1715 * main difference between this version and the original function is that 1716 * this function can make several assumptions about the state of things 1717 * that allow for significant optimizations versus the standard function. 1718 * As a result we can do things like drop a frag and maintain an accurate 1719 * truesize for the skb. 1720 */ 1721 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1722 struct sk_buff *skb) 1723 { 1724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1725 unsigned char *va; 1726 unsigned int pull_len; 1727 1728 /* 1729 * it is valid to use page_address instead of kmap since we are 1730 * working with pages allocated out of the lomem pool per 1731 * alloc_page(GFP_ATOMIC) 1732 */ 1733 va = skb_frag_address(frag); 1734 1735 /* 1736 * we need the header to contain the greater of either ETH_HLEN or 1737 * 60 bytes if the skb->len is less than 60 for skb_pad. 1738 */ 1739 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1740 1741 /* align pull length to size of long to optimize memcpy performance */ 1742 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1743 1744 /* update all of the pointers */ 1745 skb_frag_size_sub(frag, pull_len); 1746 frag->page_offset += pull_len; 1747 skb->data_len -= pull_len; 1748 skb->tail += pull_len; 1749 } 1750 1751 /** 1752 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1753 * @rx_ring: rx descriptor ring packet is being transacted on 1754 * @skb: pointer to current skb being updated 1755 * 1756 * This function provides a basic DMA sync up for the first fragment of an 1757 * skb. The reason for doing this is that the first fragment cannot be 1758 * unmapped until we have reached the end of packet descriptor for a buffer 1759 * chain. 1760 */ 1761 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1762 struct sk_buff *skb) 1763 { 1764 /* if the page was released unmap it, else just sync our portion */ 1765 if (unlikely(IXGBE_CB(skb)->page_released)) { 1766 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, 1767 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 1768 IXGBE_CB(skb)->page_released = false; 1769 } else { 1770 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1771 1772 dma_sync_single_range_for_cpu(rx_ring->dev, 1773 IXGBE_CB(skb)->dma, 1774 frag->page_offset, 1775 ixgbe_rx_bufsz(rx_ring), 1776 DMA_FROM_DEVICE); 1777 } 1778 IXGBE_CB(skb)->dma = 0; 1779 } 1780 1781 /** 1782 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1783 * @rx_ring: rx descriptor ring packet is being transacted on 1784 * @rx_desc: pointer to the EOP Rx descriptor 1785 * @skb: pointer to current skb being fixed 1786 * 1787 * Check for corrupted packet headers caused by senders on the local L2 1788 * embedded NIC switch not setting up their Tx Descriptors right. These 1789 * should be very rare. 1790 * 1791 * Also address the case where we are pulling data in on pages only 1792 * and as such no data is present in the skb header. 1793 * 1794 * In addition if skb is not at least 60 bytes we need to pad it so that 1795 * it is large enough to qualify as a valid Ethernet frame. 1796 * 1797 * Returns true if an error was encountered and skb was freed. 1798 **/ 1799 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1800 union ixgbe_adv_rx_desc *rx_desc, 1801 struct sk_buff *skb) 1802 { 1803 struct net_device *netdev = rx_ring->netdev; 1804 1805 /* verify that the packet does not have any known errors */ 1806 if (unlikely(ixgbe_test_staterr(rx_desc, 1807 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1808 !(netdev->features & NETIF_F_RXALL))) { 1809 dev_kfree_skb_any(skb); 1810 return true; 1811 } 1812 1813 /* place header in linear portion of buffer */ 1814 if (skb_is_nonlinear(skb)) 1815 ixgbe_pull_tail(rx_ring, skb); 1816 1817 #ifdef IXGBE_FCOE 1818 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1819 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1820 return false; 1821 1822 #endif 1823 /* if eth_skb_pad returns an error the skb was freed */ 1824 if (eth_skb_pad(skb)) 1825 return true; 1826 1827 return false; 1828 } 1829 1830 /** 1831 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1832 * @rx_ring: rx descriptor ring to store buffers on 1833 * @old_buff: donor buffer to have page reused 1834 * 1835 * Synchronizes page for reuse by the adapter 1836 **/ 1837 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1838 struct ixgbe_rx_buffer *old_buff) 1839 { 1840 struct ixgbe_rx_buffer *new_buff; 1841 u16 nta = rx_ring->next_to_alloc; 1842 1843 new_buff = &rx_ring->rx_buffer_info[nta]; 1844 1845 /* update, and store next to alloc */ 1846 nta++; 1847 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1848 1849 /* transfer page from old buffer to new buffer */ 1850 *new_buff = *old_buff; 1851 1852 /* sync the buffer for use by the device */ 1853 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, 1854 new_buff->page_offset, 1855 ixgbe_rx_bufsz(rx_ring), 1856 DMA_FROM_DEVICE); 1857 } 1858 1859 static inline bool ixgbe_page_is_reserved(struct page *page) 1860 { 1861 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1862 } 1863 1864 /** 1865 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 1866 * @rx_ring: rx descriptor ring to transact packets on 1867 * @rx_buffer: buffer containing page to add 1868 * @rx_desc: descriptor containing length of buffer written by hardware 1869 * @skb: sk_buff to place the data into 1870 * 1871 * This function will add the data contained in rx_buffer->page to the skb. 1872 * This is done either through a direct copy if the data in the buffer is 1873 * less than the skb header size, otherwise it will just attach the page as 1874 * a frag to the skb. 1875 * 1876 * The function will then update the page offset if necessary and return 1877 * true if the buffer can be reused by the adapter. 1878 **/ 1879 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 1880 struct ixgbe_rx_buffer *rx_buffer, 1881 union ixgbe_adv_rx_desc *rx_desc, 1882 struct sk_buff *skb) 1883 { 1884 struct page *page = rx_buffer->page; 1885 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 1886 #if (PAGE_SIZE < 8192) 1887 unsigned int truesize = ixgbe_rx_bufsz(rx_ring); 1888 #else 1889 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1890 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - 1891 ixgbe_rx_bufsz(rx_ring); 1892 #endif 1893 1894 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1895 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1896 1897 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1898 1899 /* page is not reserved, we can reuse buffer as-is */ 1900 if (likely(!ixgbe_page_is_reserved(page))) 1901 return true; 1902 1903 /* this page cannot be reused so discard it */ 1904 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1905 return false; 1906 } 1907 1908 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1909 rx_buffer->page_offset, size, truesize); 1910 1911 /* avoid re-using remote pages */ 1912 if (unlikely(ixgbe_page_is_reserved(page))) 1913 return false; 1914 1915 #if (PAGE_SIZE < 8192) 1916 /* if we are only owner of page we can reuse it */ 1917 if (unlikely(page_count(page) != 1)) 1918 return false; 1919 1920 /* flip page offset to other buffer */ 1921 rx_buffer->page_offset ^= truesize; 1922 #else 1923 /* move offset up to the next cache line */ 1924 rx_buffer->page_offset += truesize; 1925 1926 if (rx_buffer->page_offset > last_offset) 1927 return false; 1928 #endif 1929 1930 /* Even if we own the page, we are not allowed to use atomic_set() 1931 * This would break get_page_unless_zero() users. 1932 */ 1933 atomic_inc(&page->_count); 1934 1935 return true; 1936 } 1937 1938 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, 1939 union ixgbe_adv_rx_desc *rx_desc) 1940 { 1941 struct ixgbe_rx_buffer *rx_buffer; 1942 struct sk_buff *skb; 1943 struct page *page; 1944 1945 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 1946 page = rx_buffer->page; 1947 prefetchw(page); 1948 1949 skb = rx_buffer->skb; 1950 1951 if (likely(!skb)) { 1952 void *page_addr = page_address(page) + 1953 rx_buffer->page_offset; 1954 1955 /* prefetch first cache line of first page */ 1956 prefetch(page_addr); 1957 #if L1_CACHE_BYTES < 128 1958 prefetch(page_addr + L1_CACHE_BYTES); 1959 #endif 1960 1961 /* allocate a skb to store the frags */ 1962 skb = napi_alloc_skb(&rx_ring->q_vector->napi, 1963 IXGBE_RX_HDR_SIZE); 1964 if (unlikely(!skb)) { 1965 rx_ring->rx_stats.alloc_rx_buff_failed++; 1966 return NULL; 1967 } 1968 1969 /* 1970 * we will be copying header into skb->data in 1971 * pskb_may_pull so it is in our interest to prefetch 1972 * it now to avoid a possible cache miss 1973 */ 1974 prefetchw(skb->data); 1975 1976 /* 1977 * Delay unmapping of the first packet. It carries the 1978 * header information, HW may still access the header 1979 * after the writeback. Only unmap it when EOP is 1980 * reached 1981 */ 1982 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1983 goto dma_sync; 1984 1985 IXGBE_CB(skb)->dma = rx_buffer->dma; 1986 } else { 1987 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 1988 ixgbe_dma_sync_frag(rx_ring, skb); 1989 1990 dma_sync: 1991 /* we are reusing so sync this buffer for CPU use */ 1992 dma_sync_single_range_for_cpu(rx_ring->dev, 1993 rx_buffer->dma, 1994 rx_buffer->page_offset, 1995 ixgbe_rx_bufsz(rx_ring), 1996 DMA_FROM_DEVICE); 1997 1998 rx_buffer->skb = NULL; 1999 } 2000 2001 /* pull page into skb */ 2002 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 2003 /* hand second half of page back to the ring */ 2004 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2005 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { 2006 /* the page has been released from the ring */ 2007 IXGBE_CB(skb)->page_released = true; 2008 } else { 2009 /* we are not reusing the buffer so unmap it */ 2010 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 2011 ixgbe_rx_pg_size(rx_ring), 2012 DMA_FROM_DEVICE); 2013 } 2014 2015 /* clear contents of buffer_info */ 2016 rx_buffer->page = NULL; 2017 2018 return skb; 2019 } 2020 2021 /** 2022 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2023 * @q_vector: structure containing interrupt and ring information 2024 * @rx_ring: rx descriptor ring to transact packets on 2025 * @budget: Total limit on number of packets to process 2026 * 2027 * This function provides a "bounce buffer" approach to Rx interrupt 2028 * processing. The advantage to this is that on systems that have 2029 * expensive overhead for IOMMU access this provides a means of avoiding 2030 * it by maintaining the mapping of the page to the syste. 2031 * 2032 * Returns amount of work completed 2033 **/ 2034 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2035 struct ixgbe_ring *rx_ring, 2036 const int budget) 2037 { 2038 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2039 #ifdef IXGBE_FCOE 2040 struct ixgbe_adapter *adapter = q_vector->adapter; 2041 int ddp_bytes; 2042 unsigned int mss = 0; 2043 #endif /* IXGBE_FCOE */ 2044 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2045 2046 while (likely(total_rx_packets < budget)) { 2047 union ixgbe_adv_rx_desc *rx_desc; 2048 struct sk_buff *skb; 2049 2050 /* return some buffers to hardware, one at a time is too slow */ 2051 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2052 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2053 cleaned_count = 0; 2054 } 2055 2056 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2057 2058 if (!rx_desc->wb.upper.status_error) 2059 break; 2060 2061 /* This memory barrier is needed to keep us from reading 2062 * any other fields out of the rx_desc until we know the 2063 * descriptor has been written back 2064 */ 2065 dma_rmb(); 2066 2067 /* retrieve a buffer from the ring */ 2068 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); 2069 2070 /* exit if we failed to retrieve a buffer */ 2071 if (!skb) 2072 break; 2073 2074 cleaned_count++; 2075 2076 /* place incomplete frames back on ring for completion */ 2077 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2078 continue; 2079 2080 /* verify the packet layout is correct */ 2081 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2082 continue; 2083 2084 /* probably a little skewed due to removing CRC */ 2085 total_rx_bytes += skb->len; 2086 2087 /* populate checksum, timestamp, VLAN, and protocol */ 2088 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2089 2090 #ifdef IXGBE_FCOE 2091 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2092 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2093 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2094 /* include DDPed FCoE data */ 2095 if (ddp_bytes > 0) { 2096 if (!mss) { 2097 mss = rx_ring->netdev->mtu - 2098 sizeof(struct fcoe_hdr) - 2099 sizeof(struct fc_frame_header) - 2100 sizeof(struct fcoe_crc_eof); 2101 if (mss > 512) 2102 mss &= ~511; 2103 } 2104 total_rx_bytes += ddp_bytes; 2105 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2106 mss); 2107 } 2108 if (!ddp_bytes) { 2109 dev_kfree_skb_any(skb); 2110 continue; 2111 } 2112 } 2113 2114 #endif /* IXGBE_FCOE */ 2115 skb_mark_napi_id(skb, &q_vector->napi); 2116 ixgbe_rx_skb(q_vector, skb); 2117 2118 /* update budget accounting */ 2119 total_rx_packets++; 2120 } 2121 2122 u64_stats_update_begin(&rx_ring->syncp); 2123 rx_ring->stats.packets += total_rx_packets; 2124 rx_ring->stats.bytes += total_rx_bytes; 2125 u64_stats_update_end(&rx_ring->syncp); 2126 q_vector->rx.total_packets += total_rx_packets; 2127 q_vector->rx.total_bytes += total_rx_bytes; 2128 2129 return total_rx_packets; 2130 } 2131 2132 #ifdef CONFIG_NET_RX_BUSY_POLL 2133 /* must be called with local_bh_disable()d */ 2134 static int ixgbe_low_latency_recv(struct napi_struct *napi) 2135 { 2136 struct ixgbe_q_vector *q_vector = 2137 container_of(napi, struct ixgbe_q_vector, napi); 2138 struct ixgbe_adapter *adapter = q_vector->adapter; 2139 struct ixgbe_ring *ring; 2140 int found = 0; 2141 2142 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2143 return LL_FLUSH_FAILED; 2144 2145 if (!ixgbe_qv_lock_poll(q_vector)) 2146 return LL_FLUSH_BUSY; 2147 2148 ixgbe_for_each_ring(ring, q_vector->rx) { 2149 found = ixgbe_clean_rx_irq(q_vector, ring, 4); 2150 #ifdef BP_EXTENDED_STATS 2151 if (found) 2152 ring->stats.cleaned += found; 2153 else 2154 ring->stats.misses++; 2155 #endif 2156 if (found) 2157 break; 2158 } 2159 2160 ixgbe_qv_unlock_poll(q_vector); 2161 2162 return found; 2163 } 2164 #endif /* CONFIG_NET_RX_BUSY_POLL */ 2165 2166 /** 2167 * ixgbe_configure_msix - Configure MSI-X hardware 2168 * @adapter: board private structure 2169 * 2170 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2171 * interrupts. 2172 **/ 2173 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2174 { 2175 struct ixgbe_q_vector *q_vector; 2176 int v_idx; 2177 u32 mask; 2178 2179 /* Populate MSIX to EITR Select */ 2180 if (adapter->num_vfs > 32) { 2181 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; 2182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2183 } 2184 2185 /* 2186 * Populate the IVAR table and set the ITR values to the 2187 * corresponding register. 2188 */ 2189 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2190 struct ixgbe_ring *ring; 2191 q_vector = adapter->q_vector[v_idx]; 2192 2193 ixgbe_for_each_ring(ring, q_vector->rx) 2194 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2195 2196 ixgbe_for_each_ring(ring, q_vector->tx) 2197 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2198 2199 ixgbe_write_eitr(q_vector); 2200 } 2201 2202 switch (adapter->hw.mac.type) { 2203 case ixgbe_mac_82598EB: 2204 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2205 v_idx); 2206 break; 2207 case ixgbe_mac_82599EB: 2208 case ixgbe_mac_X540: 2209 case ixgbe_mac_X550: 2210 case ixgbe_mac_X550EM_x: 2211 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2212 break; 2213 default: 2214 break; 2215 } 2216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2217 2218 /* set up to autoclear timer, and the vectors */ 2219 mask = IXGBE_EIMS_ENABLE_MASK; 2220 mask &= ~(IXGBE_EIMS_OTHER | 2221 IXGBE_EIMS_MAILBOX | 2222 IXGBE_EIMS_LSC); 2223 2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2225 } 2226 2227 enum latency_range { 2228 lowest_latency = 0, 2229 low_latency = 1, 2230 bulk_latency = 2, 2231 latency_invalid = 255 2232 }; 2233 2234 /** 2235 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2236 * @q_vector: structure containing interrupt and ring information 2237 * @ring_container: structure containing ring performance data 2238 * 2239 * Stores a new ITR value based on packets and byte 2240 * counts during the last interrupt. The advantage of per interrupt 2241 * computation is faster updates and more accurate ITR for the current 2242 * traffic pattern. Constants in this function were computed 2243 * based on theoretical maximum wire speed and thresholds were set based 2244 * on testing data as well as attempting to minimize response time 2245 * while increasing bulk throughput. 2246 * this functionality is controlled by the InterruptThrottleRate module 2247 * parameter (see ixgbe_param.c) 2248 **/ 2249 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2250 struct ixgbe_ring_container *ring_container) 2251 { 2252 int bytes = ring_container->total_bytes; 2253 int packets = ring_container->total_packets; 2254 u32 timepassed_us; 2255 u64 bytes_perint; 2256 u8 itr_setting = ring_container->itr; 2257 2258 if (packets == 0) 2259 return; 2260 2261 /* simple throttlerate management 2262 * 0-10MB/s lowest (100000 ints/s) 2263 * 10-20MB/s low (20000 ints/s) 2264 * 20-1249MB/s bulk (12000 ints/s) 2265 */ 2266 /* what was last interrupt timeslice? */ 2267 timepassed_us = q_vector->itr >> 2; 2268 if (timepassed_us == 0) 2269 return; 2270 2271 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2272 2273 switch (itr_setting) { 2274 case lowest_latency: 2275 if (bytes_perint > 10) 2276 itr_setting = low_latency; 2277 break; 2278 case low_latency: 2279 if (bytes_perint > 20) 2280 itr_setting = bulk_latency; 2281 else if (bytes_perint <= 10) 2282 itr_setting = lowest_latency; 2283 break; 2284 case bulk_latency: 2285 if (bytes_perint <= 20) 2286 itr_setting = low_latency; 2287 break; 2288 } 2289 2290 /* clear work counters since we have the values we need */ 2291 ring_container->total_bytes = 0; 2292 ring_container->total_packets = 0; 2293 2294 /* write updated itr to ring container */ 2295 ring_container->itr = itr_setting; 2296 } 2297 2298 /** 2299 * ixgbe_write_eitr - write EITR register in hardware specific way 2300 * @q_vector: structure containing interrupt and ring information 2301 * 2302 * This function is made to be called by ethtool and by the driver 2303 * when it needs to update EITR registers at runtime. Hardware 2304 * specific quirks/differences are taken care of here. 2305 */ 2306 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2307 { 2308 struct ixgbe_adapter *adapter = q_vector->adapter; 2309 struct ixgbe_hw *hw = &adapter->hw; 2310 int v_idx = q_vector->v_idx; 2311 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2312 2313 switch (adapter->hw.mac.type) { 2314 case ixgbe_mac_82598EB: 2315 /* must write high and low 16 bits to reset counter */ 2316 itr_reg |= (itr_reg << 16); 2317 break; 2318 case ixgbe_mac_82599EB: 2319 case ixgbe_mac_X540: 2320 case ixgbe_mac_X550: 2321 case ixgbe_mac_X550EM_x: 2322 /* 2323 * set the WDIS bit to not clear the timer bits and cause an 2324 * immediate assertion of the interrupt 2325 */ 2326 itr_reg |= IXGBE_EITR_CNT_WDIS; 2327 break; 2328 default: 2329 break; 2330 } 2331 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2332 } 2333 2334 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2335 { 2336 u32 new_itr = q_vector->itr; 2337 u8 current_itr; 2338 2339 ixgbe_update_itr(q_vector, &q_vector->tx); 2340 ixgbe_update_itr(q_vector, &q_vector->rx); 2341 2342 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2343 2344 switch (current_itr) { 2345 /* counts and packets in update_itr are dependent on these numbers */ 2346 case lowest_latency: 2347 new_itr = IXGBE_100K_ITR; 2348 break; 2349 case low_latency: 2350 new_itr = IXGBE_20K_ITR; 2351 break; 2352 case bulk_latency: 2353 new_itr = IXGBE_12K_ITR; 2354 break; 2355 default: 2356 break; 2357 } 2358 2359 if (new_itr != q_vector->itr) { 2360 /* do an exponential smoothing */ 2361 new_itr = (10 * new_itr * q_vector->itr) / 2362 ((9 * new_itr) + q_vector->itr); 2363 2364 /* save the algorithm value here */ 2365 q_vector->itr = new_itr; 2366 2367 ixgbe_write_eitr(q_vector); 2368 } 2369 } 2370 2371 /** 2372 * ixgbe_check_overtemp_subtask - check for over temperature 2373 * @adapter: pointer to adapter 2374 **/ 2375 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2376 { 2377 struct ixgbe_hw *hw = &adapter->hw; 2378 u32 eicr = adapter->interrupt_event; 2379 2380 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2381 return; 2382 2383 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2384 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2385 return; 2386 2387 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2388 2389 switch (hw->device_id) { 2390 case IXGBE_DEV_ID_82599_T3_LOM: 2391 /* 2392 * Since the warning interrupt is for both ports 2393 * we don't have to check if: 2394 * - This interrupt wasn't for our port. 2395 * - We may have missed the interrupt so always have to 2396 * check if we got a LSC 2397 */ 2398 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2399 !(eicr & IXGBE_EICR_LSC)) 2400 return; 2401 2402 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2403 u32 speed; 2404 bool link_up = false; 2405 2406 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2407 2408 if (link_up) 2409 return; 2410 } 2411 2412 /* Check if this is not due to overtemp */ 2413 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2414 return; 2415 2416 break; 2417 default: 2418 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2419 return; 2420 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2421 return; 2422 break; 2423 } 2424 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2425 2426 adapter->interrupt_event = 0; 2427 } 2428 2429 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2430 { 2431 struct ixgbe_hw *hw = &adapter->hw; 2432 2433 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2434 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2435 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2436 /* write to clear the interrupt */ 2437 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2438 } 2439 } 2440 2441 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2442 { 2443 struct ixgbe_hw *hw = &adapter->hw; 2444 2445 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2446 return; 2447 2448 switch (adapter->hw.mac.type) { 2449 case ixgbe_mac_82599EB: 2450 /* 2451 * Need to check link state so complete overtemp check 2452 * on service task 2453 */ 2454 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2455 (eicr & IXGBE_EICR_LSC)) && 2456 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2457 adapter->interrupt_event = eicr; 2458 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2459 ixgbe_service_event_schedule(adapter); 2460 return; 2461 } 2462 return; 2463 case ixgbe_mac_X540: 2464 if (!(eicr & IXGBE_EICR_TS)) 2465 return; 2466 break; 2467 default: 2468 return; 2469 } 2470 2471 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2472 } 2473 2474 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2475 { 2476 switch (hw->mac.type) { 2477 case ixgbe_mac_82598EB: 2478 if (hw->phy.type == ixgbe_phy_nl) 2479 return true; 2480 return false; 2481 case ixgbe_mac_82599EB: 2482 case ixgbe_mac_X550EM_x: 2483 switch (hw->mac.ops.get_media_type(hw)) { 2484 case ixgbe_media_type_fiber: 2485 case ixgbe_media_type_fiber_qsfp: 2486 return true; 2487 default: 2488 return false; 2489 } 2490 default: 2491 return false; 2492 } 2493 } 2494 2495 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2496 { 2497 struct ixgbe_hw *hw = &adapter->hw; 2498 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2499 2500 if (!ixgbe_is_sfp(hw)) 2501 return; 2502 2503 /* Later MAC's use different SDP */ 2504 if (hw->mac.type >= ixgbe_mac_X540) 2505 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2506 2507 if (eicr & eicr_mask) { 2508 /* Clear the interrupt */ 2509 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2510 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2511 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2512 ixgbe_service_event_schedule(adapter); 2513 } 2514 } 2515 2516 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2517 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2518 /* Clear the interrupt */ 2519 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2520 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2521 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2522 ixgbe_service_event_schedule(adapter); 2523 } 2524 } 2525 } 2526 2527 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2528 { 2529 struct ixgbe_hw *hw = &adapter->hw; 2530 2531 adapter->lsc_int++; 2532 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2533 adapter->link_check_timeout = jiffies; 2534 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2535 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2536 IXGBE_WRITE_FLUSH(hw); 2537 ixgbe_service_event_schedule(adapter); 2538 } 2539 } 2540 2541 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2542 u64 qmask) 2543 { 2544 u32 mask; 2545 struct ixgbe_hw *hw = &adapter->hw; 2546 2547 switch (hw->mac.type) { 2548 case ixgbe_mac_82598EB: 2549 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2550 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2551 break; 2552 case ixgbe_mac_82599EB: 2553 case ixgbe_mac_X540: 2554 case ixgbe_mac_X550: 2555 case ixgbe_mac_X550EM_x: 2556 mask = (qmask & 0xFFFFFFFF); 2557 if (mask) 2558 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2559 mask = (qmask >> 32); 2560 if (mask) 2561 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2562 break; 2563 default: 2564 break; 2565 } 2566 /* skip the flush */ 2567 } 2568 2569 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2570 u64 qmask) 2571 { 2572 u32 mask; 2573 struct ixgbe_hw *hw = &adapter->hw; 2574 2575 switch (hw->mac.type) { 2576 case ixgbe_mac_82598EB: 2577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2578 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2579 break; 2580 case ixgbe_mac_82599EB: 2581 case ixgbe_mac_X540: 2582 case ixgbe_mac_X550: 2583 case ixgbe_mac_X550EM_x: 2584 mask = (qmask & 0xFFFFFFFF); 2585 if (mask) 2586 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2587 mask = (qmask >> 32); 2588 if (mask) 2589 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2590 break; 2591 default: 2592 break; 2593 } 2594 /* skip the flush */ 2595 } 2596 2597 /** 2598 * ixgbe_irq_enable - Enable default interrupt generation settings 2599 * @adapter: board private structure 2600 **/ 2601 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2602 bool flush) 2603 { 2604 struct ixgbe_hw *hw = &adapter->hw; 2605 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2606 2607 /* don't reenable LSC while waiting for link */ 2608 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2609 mask &= ~IXGBE_EIMS_LSC; 2610 2611 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2612 switch (adapter->hw.mac.type) { 2613 case ixgbe_mac_82599EB: 2614 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2615 break; 2616 case ixgbe_mac_X540: 2617 case ixgbe_mac_X550: 2618 case ixgbe_mac_X550EM_x: 2619 mask |= IXGBE_EIMS_TS; 2620 break; 2621 default: 2622 break; 2623 } 2624 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2625 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2626 switch (adapter->hw.mac.type) { 2627 case ixgbe_mac_82599EB: 2628 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2629 mask |= IXGBE_EIMS_GPI_SDP2(hw); 2630 /* fall through */ 2631 case ixgbe_mac_X540: 2632 case ixgbe_mac_X550: 2633 case ixgbe_mac_X550EM_x: 2634 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 2635 mask |= IXGBE_EICR_GPI_SDP0_X540; 2636 mask |= IXGBE_EIMS_ECC; 2637 mask |= IXGBE_EIMS_MAILBOX; 2638 break; 2639 default: 2640 break; 2641 } 2642 2643 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2644 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2645 mask |= IXGBE_EIMS_FLOW_DIR; 2646 2647 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2648 if (queues) 2649 ixgbe_irq_enable_queues(adapter, ~0); 2650 if (flush) 2651 IXGBE_WRITE_FLUSH(&adapter->hw); 2652 } 2653 2654 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2655 { 2656 struct ixgbe_adapter *adapter = data; 2657 struct ixgbe_hw *hw = &adapter->hw; 2658 u32 eicr; 2659 2660 /* 2661 * Workaround for Silicon errata. Use clear-by-write instead 2662 * of clear-by-read. Reading with EICS will return the 2663 * interrupt causes without clearing, which later be done 2664 * with the write to EICR. 2665 */ 2666 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2667 2668 /* The lower 16bits of the EICR register are for the queue interrupts 2669 * which should be masked here in order to not accidentally clear them if 2670 * the bits are high when ixgbe_msix_other is called. There is a race 2671 * condition otherwise which results in possible performance loss 2672 * especially if the ixgbe_msix_other interrupt is triggering 2673 * consistently (as it would when PPS is turned on for the X540 device) 2674 */ 2675 eicr &= 0xFFFF0000; 2676 2677 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2678 2679 if (eicr & IXGBE_EICR_LSC) 2680 ixgbe_check_lsc(adapter); 2681 2682 if (eicr & IXGBE_EICR_MAILBOX) 2683 ixgbe_msg_task(adapter); 2684 2685 switch (hw->mac.type) { 2686 case ixgbe_mac_82599EB: 2687 case ixgbe_mac_X540: 2688 case ixgbe_mac_X550: 2689 case ixgbe_mac_X550EM_x: 2690 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 2691 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2692 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 2693 ixgbe_service_event_schedule(adapter); 2694 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2695 IXGBE_EICR_GPI_SDP0_X540); 2696 } 2697 if (eicr & IXGBE_EICR_ECC) { 2698 e_info(link, "Received ECC Err, initiating reset\n"); 2699 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2700 ixgbe_service_event_schedule(adapter); 2701 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2702 } 2703 /* Handle Flow Director Full threshold interrupt */ 2704 if (eicr & IXGBE_EICR_FLOW_DIR) { 2705 int reinit_count = 0; 2706 int i; 2707 for (i = 0; i < adapter->num_tx_queues; i++) { 2708 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2709 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2710 &ring->state)) 2711 reinit_count++; 2712 } 2713 if (reinit_count) { 2714 /* no more flow director interrupts until after init */ 2715 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 2716 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 2717 ixgbe_service_event_schedule(adapter); 2718 } 2719 } 2720 ixgbe_check_sfp_event(adapter, eicr); 2721 ixgbe_check_overtemp_event(adapter, eicr); 2722 break; 2723 default: 2724 break; 2725 } 2726 2727 ixgbe_check_fan_failure(adapter, eicr); 2728 2729 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2730 ixgbe_ptp_check_pps_event(adapter, eicr); 2731 2732 /* re-enable the original interrupt state, no lsc, no queues */ 2733 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2734 ixgbe_irq_enable(adapter, false, false); 2735 2736 return IRQ_HANDLED; 2737 } 2738 2739 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 2740 { 2741 struct ixgbe_q_vector *q_vector = data; 2742 2743 /* EIAM disabled interrupts (on this vector) for us */ 2744 2745 if (q_vector->rx.ring || q_vector->tx.ring) 2746 napi_schedule(&q_vector->napi); 2747 2748 return IRQ_HANDLED; 2749 } 2750 2751 /** 2752 * ixgbe_poll - NAPI Rx polling callback 2753 * @napi: structure for representing this polling device 2754 * @budget: how many packets driver is allowed to clean 2755 * 2756 * This function is used for legacy and MSI, NAPI mode 2757 **/ 2758 int ixgbe_poll(struct napi_struct *napi, int budget) 2759 { 2760 struct ixgbe_q_vector *q_vector = 2761 container_of(napi, struct ixgbe_q_vector, napi); 2762 struct ixgbe_adapter *adapter = q_vector->adapter; 2763 struct ixgbe_ring *ring; 2764 int per_ring_budget; 2765 bool clean_complete = true; 2766 2767 #ifdef CONFIG_IXGBE_DCA 2768 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 2769 ixgbe_update_dca(q_vector); 2770 #endif 2771 2772 ixgbe_for_each_ring(ring, q_vector->tx) 2773 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); 2774 2775 if (!ixgbe_qv_lock_napi(q_vector)) 2776 return budget; 2777 2778 /* attempt to distribute budget to each queue fairly, but don't allow 2779 * the budget to go below 1 because we'll exit polling */ 2780 if (q_vector->rx.count > 1) 2781 per_ring_budget = max(budget/q_vector->rx.count, 1); 2782 else 2783 per_ring_budget = budget; 2784 2785 ixgbe_for_each_ring(ring, q_vector->rx) 2786 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring, 2787 per_ring_budget) < per_ring_budget); 2788 2789 ixgbe_qv_unlock_napi(q_vector); 2790 /* If all work not completed, return budget and keep polling */ 2791 if (!clean_complete) 2792 return budget; 2793 2794 /* all work done, exit the polling mode */ 2795 napi_complete(napi); 2796 if (adapter->rx_itr_setting & 1) 2797 ixgbe_set_itr(q_vector); 2798 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2799 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); 2800 2801 return 0; 2802 } 2803 2804 /** 2805 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 2806 * @adapter: board private structure 2807 * 2808 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 2809 * interrupts from the kernel. 2810 **/ 2811 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 2812 { 2813 struct net_device *netdev = adapter->netdev; 2814 int vector, err; 2815 int ri = 0, ti = 0; 2816 2817 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2818 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2819 struct msix_entry *entry = &adapter->msix_entries[vector]; 2820 2821 if (q_vector->tx.ring && q_vector->rx.ring) { 2822 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2823 "%s-%s-%d", netdev->name, "TxRx", ri++); 2824 ti++; 2825 } else if (q_vector->rx.ring) { 2826 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2827 "%s-%s-%d", netdev->name, "rx", ri++); 2828 } else if (q_vector->tx.ring) { 2829 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 2830 "%s-%s-%d", netdev->name, "tx", ti++); 2831 } else { 2832 /* skip this unused q_vector */ 2833 continue; 2834 } 2835 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 2836 q_vector->name, q_vector); 2837 if (err) { 2838 e_err(probe, "request_irq failed for MSIX interrupt " 2839 "Error: %d\n", err); 2840 goto free_queue_irqs; 2841 } 2842 /* If Flow Director is enabled, set interrupt affinity */ 2843 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 2844 /* assign the mask for this irq */ 2845 irq_set_affinity_hint(entry->vector, 2846 &q_vector->affinity_mask); 2847 } 2848 } 2849 2850 err = request_irq(adapter->msix_entries[vector].vector, 2851 ixgbe_msix_other, 0, netdev->name, adapter); 2852 if (err) { 2853 e_err(probe, "request_irq for msix_other failed: %d\n", err); 2854 goto free_queue_irqs; 2855 } 2856 2857 return 0; 2858 2859 free_queue_irqs: 2860 while (vector) { 2861 vector--; 2862 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 2863 NULL); 2864 free_irq(adapter->msix_entries[vector].vector, 2865 adapter->q_vector[vector]); 2866 } 2867 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 2868 pci_disable_msix(adapter->pdev); 2869 kfree(adapter->msix_entries); 2870 adapter->msix_entries = NULL; 2871 return err; 2872 } 2873 2874 /** 2875 * ixgbe_intr - legacy mode Interrupt Handler 2876 * @irq: interrupt number 2877 * @data: pointer to a network interface device structure 2878 **/ 2879 static irqreturn_t ixgbe_intr(int irq, void *data) 2880 { 2881 struct ixgbe_adapter *adapter = data; 2882 struct ixgbe_hw *hw = &adapter->hw; 2883 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 2884 u32 eicr; 2885 2886 /* 2887 * Workaround for silicon errata #26 on 82598. Mask the interrupt 2888 * before the read of EICR. 2889 */ 2890 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 2891 2892 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 2893 * therefore no explicit interrupt disable is necessary */ 2894 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 2895 if (!eicr) { 2896 /* 2897 * shared interrupt alert! 2898 * make sure interrupts are enabled because the read will 2899 * have disabled interrupts due to EIAM 2900 * finish the workaround of silicon errata on 82598. Unmask 2901 * the interrupt that we masked before the EICR read. 2902 */ 2903 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2904 ixgbe_irq_enable(adapter, true, true); 2905 return IRQ_NONE; /* Not our interrupt */ 2906 } 2907 2908 if (eicr & IXGBE_EICR_LSC) 2909 ixgbe_check_lsc(adapter); 2910 2911 switch (hw->mac.type) { 2912 case ixgbe_mac_82599EB: 2913 ixgbe_check_sfp_event(adapter, eicr); 2914 /* Fall through */ 2915 case ixgbe_mac_X540: 2916 case ixgbe_mac_X550: 2917 case ixgbe_mac_X550EM_x: 2918 if (eicr & IXGBE_EICR_ECC) { 2919 e_info(link, "Received ECC Err, initiating reset\n"); 2920 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 2921 ixgbe_service_event_schedule(adapter); 2922 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2923 } 2924 ixgbe_check_overtemp_event(adapter, eicr); 2925 break; 2926 default: 2927 break; 2928 } 2929 2930 ixgbe_check_fan_failure(adapter, eicr); 2931 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 2932 ixgbe_ptp_check_pps_event(adapter, eicr); 2933 2934 /* would disable interrupts here but EIAM disabled it */ 2935 napi_schedule(&q_vector->napi); 2936 2937 /* 2938 * re-enable link(maybe) and non-queue interrupts, no flush. 2939 * ixgbe_poll will re-enable the queue interrupts 2940 */ 2941 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 2942 ixgbe_irq_enable(adapter, false, false); 2943 2944 return IRQ_HANDLED; 2945 } 2946 2947 /** 2948 * ixgbe_request_irq - initialize interrupts 2949 * @adapter: board private structure 2950 * 2951 * Attempts to configure interrupts using the best available 2952 * capabilities of the hardware and kernel. 2953 **/ 2954 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 2955 { 2956 struct net_device *netdev = adapter->netdev; 2957 int err; 2958 2959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 2960 err = ixgbe_request_msix_irqs(adapter); 2961 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 2962 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 2963 netdev->name, adapter); 2964 else 2965 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 2966 netdev->name, adapter); 2967 2968 if (err) 2969 e_err(probe, "request_irq failed, Error %d\n", err); 2970 2971 return err; 2972 } 2973 2974 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 2975 { 2976 int vector; 2977 2978 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2979 free_irq(adapter->pdev->irq, adapter); 2980 return; 2981 } 2982 2983 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 2984 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 2985 struct msix_entry *entry = &adapter->msix_entries[vector]; 2986 2987 /* free only the irqs that were actually requested */ 2988 if (!q_vector->rx.ring && !q_vector->tx.ring) 2989 continue; 2990 2991 /* clear the affinity_mask in the IRQ descriptor */ 2992 irq_set_affinity_hint(entry->vector, NULL); 2993 2994 free_irq(entry->vector, q_vector); 2995 } 2996 2997 free_irq(adapter->msix_entries[vector++].vector, adapter); 2998 } 2999 3000 /** 3001 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3002 * @adapter: board private structure 3003 **/ 3004 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3005 { 3006 switch (adapter->hw.mac.type) { 3007 case ixgbe_mac_82598EB: 3008 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3009 break; 3010 case ixgbe_mac_82599EB: 3011 case ixgbe_mac_X540: 3012 case ixgbe_mac_X550: 3013 case ixgbe_mac_X550EM_x: 3014 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3015 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3016 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3017 break; 3018 default: 3019 break; 3020 } 3021 IXGBE_WRITE_FLUSH(&adapter->hw); 3022 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3023 int vector; 3024 3025 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3026 synchronize_irq(adapter->msix_entries[vector].vector); 3027 3028 synchronize_irq(adapter->msix_entries[vector++].vector); 3029 } else { 3030 synchronize_irq(adapter->pdev->irq); 3031 } 3032 } 3033 3034 /** 3035 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3036 * 3037 **/ 3038 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3039 { 3040 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3041 3042 ixgbe_write_eitr(q_vector); 3043 3044 ixgbe_set_ivar(adapter, 0, 0, 0); 3045 ixgbe_set_ivar(adapter, 1, 0, 0); 3046 3047 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3048 } 3049 3050 /** 3051 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3052 * @adapter: board private structure 3053 * @ring: structure containing ring specific data 3054 * 3055 * Configure the Tx descriptor ring after a reset. 3056 **/ 3057 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3058 struct ixgbe_ring *ring) 3059 { 3060 struct ixgbe_hw *hw = &adapter->hw; 3061 u64 tdba = ring->dma; 3062 int wait_loop = 10; 3063 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3064 u8 reg_idx = ring->reg_idx; 3065 3066 /* disable queue to avoid issues while updating state */ 3067 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3068 IXGBE_WRITE_FLUSH(hw); 3069 3070 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3071 (tdba & DMA_BIT_MASK(32))); 3072 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3073 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3074 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3075 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3076 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3077 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3078 3079 /* 3080 * set WTHRESH to encourage burst writeback, it should not be set 3081 * higher than 1 when: 3082 * - ITR is 0 as it could cause false TX hangs 3083 * - ITR is set to > 100k int/sec and BQL is enabled 3084 * 3085 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3086 * to or less than the number of on chip descriptors, which is 3087 * currently 40. 3088 */ 3089 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3090 txdctl |= (1 << 16); /* WTHRESH = 1 */ 3091 else 3092 txdctl |= (8 << 16); /* WTHRESH = 8 */ 3093 3094 /* 3095 * Setting PTHRESH to 32 both improves performance 3096 * and avoids a TX hang with DFP enabled 3097 */ 3098 txdctl |= (1 << 8) | /* HTHRESH = 1 */ 3099 32; /* PTHRESH = 32 */ 3100 3101 /* reinitialize flowdirector state */ 3102 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3103 ring->atr_sample_rate = adapter->atr_sample_rate; 3104 ring->atr_count = 0; 3105 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3106 } else { 3107 ring->atr_sample_rate = 0; 3108 } 3109 3110 /* initialize XPS */ 3111 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3112 struct ixgbe_q_vector *q_vector = ring->q_vector; 3113 3114 if (q_vector) 3115 netif_set_xps_queue(ring->netdev, 3116 &q_vector->affinity_mask, 3117 ring->queue_index); 3118 } 3119 3120 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3121 3122 /* enable queue */ 3123 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3124 3125 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3126 if (hw->mac.type == ixgbe_mac_82598EB && 3127 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3128 return; 3129 3130 /* poll to verify queue is enabled */ 3131 do { 3132 usleep_range(1000, 2000); 3133 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3134 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3135 if (!wait_loop) 3136 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); 3137 } 3138 3139 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3140 { 3141 struct ixgbe_hw *hw = &adapter->hw; 3142 u32 rttdcs, mtqc; 3143 u8 tcs = netdev_get_num_tc(adapter->netdev); 3144 3145 if (hw->mac.type == ixgbe_mac_82598EB) 3146 return; 3147 3148 /* disable the arbiter while setting MTQC */ 3149 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3150 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3151 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3152 3153 /* set transmit pool layout */ 3154 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3155 mtqc = IXGBE_MTQC_VT_ENA; 3156 if (tcs > 4) 3157 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3158 else if (tcs > 1) 3159 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3160 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3161 mtqc |= IXGBE_MTQC_32VF; 3162 else 3163 mtqc |= IXGBE_MTQC_64VF; 3164 } else { 3165 if (tcs > 4) 3166 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3167 else if (tcs > 1) 3168 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3169 else 3170 mtqc = IXGBE_MTQC_64Q_1PB; 3171 } 3172 3173 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3174 3175 /* Enable Security TX Buffer IFG for multiple pb */ 3176 if (tcs) { 3177 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3178 sectx |= IXGBE_SECTX_DCB; 3179 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3180 } 3181 3182 /* re-enable the arbiter */ 3183 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3184 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3185 } 3186 3187 /** 3188 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3189 * @adapter: board private structure 3190 * 3191 * Configure the Tx unit of the MAC after a reset. 3192 **/ 3193 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3194 { 3195 struct ixgbe_hw *hw = &adapter->hw; 3196 u32 dmatxctl; 3197 u32 i; 3198 3199 ixgbe_setup_mtqc(adapter); 3200 3201 if (hw->mac.type != ixgbe_mac_82598EB) { 3202 /* DMATXCTL.EN must be before Tx queues are enabled */ 3203 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3204 dmatxctl |= IXGBE_DMATXCTL_TE; 3205 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3206 } 3207 3208 /* Setup the HW Tx Head and Tail descriptor pointers */ 3209 for (i = 0; i < adapter->num_tx_queues; i++) 3210 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3211 } 3212 3213 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3214 struct ixgbe_ring *ring) 3215 { 3216 struct ixgbe_hw *hw = &adapter->hw; 3217 u8 reg_idx = ring->reg_idx; 3218 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3219 3220 srrctl |= IXGBE_SRRCTL_DROP_EN; 3221 3222 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3223 } 3224 3225 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3226 struct ixgbe_ring *ring) 3227 { 3228 struct ixgbe_hw *hw = &adapter->hw; 3229 u8 reg_idx = ring->reg_idx; 3230 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3231 3232 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3233 3234 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3235 } 3236 3237 #ifdef CONFIG_IXGBE_DCB 3238 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3239 #else 3240 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3241 #endif 3242 { 3243 int i; 3244 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3245 3246 if (adapter->ixgbe_ieee_pfc) 3247 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3248 3249 /* 3250 * We should set the drop enable bit if: 3251 * SR-IOV is enabled 3252 * or 3253 * Number of Rx queues > 1 and flow control is disabled 3254 * 3255 * This allows us to avoid head of line blocking for security 3256 * and performance reasons. 3257 */ 3258 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3259 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3260 for (i = 0; i < adapter->num_rx_queues; i++) 3261 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3262 } else { 3263 for (i = 0; i < adapter->num_rx_queues; i++) 3264 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3265 } 3266 } 3267 3268 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3269 3270 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3271 struct ixgbe_ring *rx_ring) 3272 { 3273 struct ixgbe_hw *hw = &adapter->hw; 3274 u32 srrctl; 3275 u8 reg_idx = rx_ring->reg_idx; 3276 3277 if (hw->mac.type == ixgbe_mac_82598EB) { 3278 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3279 3280 /* 3281 * if VMDq is not active we must program one srrctl register 3282 * per RSS queue since we have enabled RDRXCTL.MVMEN 3283 */ 3284 reg_idx &= mask; 3285 } 3286 3287 /* configure header buffer length, needed for RSC */ 3288 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3289 3290 /* configure the packet buffer length */ 3291 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3292 3293 /* configure descriptor type */ 3294 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3295 3296 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3297 } 3298 3299 /** 3300 * Return a number of entries in the RSS indirection table 3301 * 3302 * @adapter: device handle 3303 * 3304 * - 82598/82599/X540: 128 3305 * - X550(non-SRIOV mode): 512 3306 * - X550(SRIOV mode): 64 3307 */ 3308 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3309 { 3310 if (adapter->hw.mac.type < ixgbe_mac_X550) 3311 return 128; 3312 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3313 return 64; 3314 else 3315 return 512; 3316 } 3317 3318 /** 3319 * Write the RETA table to HW 3320 * 3321 * @adapter: device handle 3322 * 3323 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3324 */ 3325 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3326 { 3327 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3328 struct ixgbe_hw *hw = &adapter->hw; 3329 u32 reta = 0; 3330 u32 indices_multi; 3331 u8 *indir_tbl = adapter->rss_indir_tbl; 3332 3333 /* Fill out the redirection table as follows: 3334 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3335 * indices. 3336 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3337 * - X550: 8 bit wide entries containing 6 bit RSS index 3338 */ 3339 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3340 indices_multi = 0x11; 3341 else 3342 indices_multi = 0x1; 3343 3344 /* Write redirection table to HW */ 3345 for (i = 0; i < reta_entries; i++) { 3346 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3347 if ((i & 3) == 3) { 3348 if (i < 128) 3349 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3350 else 3351 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3352 reta); 3353 reta = 0; 3354 } 3355 } 3356 } 3357 3358 /** 3359 * Write the RETA table to HW (for x550 devices in SRIOV mode) 3360 * 3361 * @adapter: device handle 3362 * 3363 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3364 */ 3365 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3366 { 3367 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3368 struct ixgbe_hw *hw = &adapter->hw; 3369 u32 vfreta = 0; 3370 unsigned int pf_pool = adapter->num_vfs; 3371 3372 /* Write redirection table to HW */ 3373 for (i = 0; i < reta_entries; i++) { 3374 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3375 if ((i & 3) == 3) { 3376 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3377 vfreta); 3378 vfreta = 0; 3379 } 3380 } 3381 } 3382 3383 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3384 { 3385 struct ixgbe_hw *hw = &adapter->hw; 3386 u32 i, j; 3387 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3388 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3389 3390 /* Program table for at least 2 queues w/ SR-IOV so that VFs can 3391 * make full use of any rings they may have. We will use the 3392 * PSRTYPE register to control how many rings we use within the PF. 3393 */ 3394 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) 3395 rss_i = 2; 3396 3397 /* Fill out hash function seeds */ 3398 for (i = 0; i < 10; i++) 3399 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3400 3401 /* Fill out redirection table */ 3402 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3403 3404 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3405 if (j == rss_i) 3406 j = 0; 3407 3408 adapter->rss_indir_tbl[i] = j; 3409 } 3410 3411 ixgbe_store_reta(adapter); 3412 } 3413 3414 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3415 { 3416 struct ixgbe_hw *hw = &adapter->hw; 3417 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3418 unsigned int pf_pool = adapter->num_vfs; 3419 int i, j; 3420 3421 /* Fill out hash function seeds */ 3422 for (i = 0; i < 10; i++) 3423 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), 3424 adapter->rss_key[i]); 3425 3426 /* Fill out the redirection table */ 3427 for (i = 0, j = 0; i < 64; i++, j++) { 3428 if (j == rss_i) 3429 j = 0; 3430 3431 adapter->rss_indir_tbl[i] = j; 3432 } 3433 3434 ixgbe_store_vfreta(adapter); 3435 } 3436 3437 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3438 { 3439 struct ixgbe_hw *hw = &adapter->hw; 3440 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3441 u32 rxcsum; 3442 3443 /* Disable indicating checksum in descriptor, enables RSS hash */ 3444 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3445 rxcsum |= IXGBE_RXCSUM_PCSD; 3446 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3447 3448 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3449 if (adapter->ring_feature[RING_F_RSS].mask) 3450 mrqc = IXGBE_MRQC_RSSEN; 3451 } else { 3452 u8 tcs = netdev_get_num_tc(adapter->netdev); 3453 3454 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3455 if (tcs > 4) 3456 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3457 else if (tcs > 1) 3458 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3459 else if (adapter->ring_feature[RING_F_RSS].indices == 4) 3460 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3461 else 3462 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3463 } else { 3464 if (tcs > 4) 3465 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3466 else if (tcs > 1) 3467 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3468 else 3469 mrqc = IXGBE_MRQC_RSSEN; 3470 } 3471 } 3472 3473 /* Perform hash on these packet types */ 3474 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3475 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3476 IXGBE_MRQC_RSS_FIELD_IPV6 | 3477 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3478 3479 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3480 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3481 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3482 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3483 3484 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key)); 3485 if ((hw->mac.type >= ixgbe_mac_X550) && 3486 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3487 unsigned int pf_pool = adapter->num_vfs; 3488 3489 /* Enable VF RSS mode */ 3490 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3491 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3492 3493 /* Setup RSS through the VF registers */ 3494 ixgbe_setup_vfreta(adapter); 3495 vfmrqc = IXGBE_MRQC_RSSEN; 3496 vfmrqc |= rss_field; 3497 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3498 } else { 3499 ixgbe_setup_reta(adapter); 3500 mrqc |= rss_field; 3501 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3502 } 3503 } 3504 3505 /** 3506 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3507 * @adapter: address of board private structure 3508 * @index: index of ring to set 3509 **/ 3510 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3511 struct ixgbe_ring *ring) 3512 { 3513 struct ixgbe_hw *hw = &adapter->hw; 3514 u32 rscctrl; 3515 u8 reg_idx = ring->reg_idx; 3516 3517 if (!ring_is_rsc_enabled(ring)) 3518 return; 3519 3520 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3521 rscctrl |= IXGBE_RSCCTL_RSCEN; 3522 /* 3523 * we must limit the number of descriptors so that the 3524 * total size of max desc * buf_len is not greater 3525 * than 65536 3526 */ 3527 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3528 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3529 } 3530 3531 #define IXGBE_MAX_RX_DESC_POLL 10 3532 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3533 struct ixgbe_ring *ring) 3534 { 3535 struct ixgbe_hw *hw = &adapter->hw; 3536 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3537 u32 rxdctl; 3538 u8 reg_idx = ring->reg_idx; 3539 3540 if (ixgbe_removed(hw->hw_addr)) 3541 return; 3542 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3543 if (hw->mac.type == ixgbe_mac_82598EB && 3544 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3545 return; 3546 3547 do { 3548 usleep_range(1000, 2000); 3549 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3550 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3551 3552 if (!wait_loop) { 3553 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3554 "the polling period\n", reg_idx); 3555 } 3556 } 3557 3558 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3559 struct ixgbe_ring *ring) 3560 { 3561 struct ixgbe_hw *hw = &adapter->hw; 3562 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3563 u32 rxdctl; 3564 u8 reg_idx = ring->reg_idx; 3565 3566 if (ixgbe_removed(hw->hw_addr)) 3567 return; 3568 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3569 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3570 3571 /* write value back with RXDCTL.ENABLE bit cleared */ 3572 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3573 3574 if (hw->mac.type == ixgbe_mac_82598EB && 3575 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3576 return; 3577 3578 /* the hardware may take up to 100us to really disable the rx queue */ 3579 do { 3580 udelay(10); 3581 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3582 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3583 3584 if (!wait_loop) { 3585 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3586 "the polling period\n", reg_idx); 3587 } 3588 } 3589 3590 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3591 struct ixgbe_ring *ring) 3592 { 3593 struct ixgbe_hw *hw = &adapter->hw; 3594 u64 rdba = ring->dma; 3595 u32 rxdctl; 3596 u8 reg_idx = ring->reg_idx; 3597 3598 /* disable queue to avoid issues while updating state */ 3599 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3600 ixgbe_disable_rx_queue(adapter, ring); 3601 3602 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3603 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3604 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3605 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3606 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3607 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3608 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3609 3610 ixgbe_configure_srrctl(adapter, ring); 3611 ixgbe_configure_rscctl(adapter, ring); 3612 3613 if (hw->mac.type == ixgbe_mac_82598EB) { 3614 /* 3615 * enable cache line friendly hardware writes: 3616 * PTHRESH=32 descriptors (half the internal cache), 3617 * this also removes ugly rx_no_buffer_count increment 3618 * HTHRESH=4 descriptors (to minimize latency on fetch) 3619 * WTHRESH=8 burst writeback up to two cache lines 3620 */ 3621 rxdctl &= ~0x3FFFFF; 3622 rxdctl |= 0x080420; 3623 } 3624 3625 /* enable receive descriptor ring */ 3626 rxdctl |= IXGBE_RXDCTL_ENABLE; 3627 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3628 3629 ixgbe_rx_desc_queue_enable(adapter, ring); 3630 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3631 } 3632 3633 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3634 { 3635 struct ixgbe_hw *hw = &adapter->hw; 3636 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 3637 u16 pool; 3638 3639 /* PSRTYPE must be initialized in non 82598 adapters */ 3640 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 3641 IXGBE_PSRTYPE_UDPHDR | 3642 IXGBE_PSRTYPE_IPV4HDR | 3643 IXGBE_PSRTYPE_L2HDR | 3644 IXGBE_PSRTYPE_IPV6HDR; 3645 3646 if (hw->mac.type == ixgbe_mac_82598EB) 3647 return; 3648 3649 if (rss_i > 3) 3650 psrtype |= 2 << 29; 3651 else if (rss_i > 1) 3652 psrtype |= 1 << 29; 3653 3654 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 3655 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 3656 } 3657 3658 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 3659 { 3660 struct ixgbe_hw *hw = &adapter->hw; 3661 u32 reg_offset, vf_shift; 3662 u32 gcr_ext, vmdctl; 3663 int i; 3664 3665 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3666 return; 3667 3668 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3669 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 3670 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 3671 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 3672 vmdctl |= IXGBE_VT_CTL_REPLEN; 3673 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 3674 3675 vf_shift = VMDQ_P(0) % 32; 3676 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 3677 3678 /* Enable only the PF's pool for Tx/Rx */ 3679 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); 3680 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 3681 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); 3682 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 3683 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 3684 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 3685 3686 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 3687 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 3688 3689 /* 3690 * Set up VF register offsets for selected VT Mode, 3691 * i.e. 32 or 64 VFs for SR-IOV 3692 */ 3693 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 3694 case IXGBE_82599_VMDQ_8Q_MASK: 3695 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 3696 break; 3697 case IXGBE_82599_VMDQ_4Q_MASK: 3698 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 3699 break; 3700 default: 3701 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 3702 break; 3703 } 3704 3705 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 3706 3707 3708 /* Enable MAC Anti-Spoofing */ 3709 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), 3710 adapter->num_vfs); 3711 3712 /* Ensure LLDP is set for Ethertype Antispoofing if we will be 3713 * calling set_ethertype_anti_spoofing for each VF in loop below 3714 */ 3715 if (hw->mac.ops.set_ethertype_anti_spoofing) 3716 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP), 3717 (IXGBE_ETQF_FILTER_EN | /* enable filter */ 3718 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */ 3719 IXGBE_ETH_P_LLDP)); /* LLDP eth type */ 3720 3721 /* For VFs that have spoof checking turned off */ 3722 for (i = 0; i < adapter->num_vfs; i++) { 3723 if (!adapter->vfinfo[i].spoofchk_enabled) 3724 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); 3725 3726 /* enable ethertype anti spoofing if hw supports it */ 3727 if (hw->mac.ops.set_ethertype_anti_spoofing) 3728 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i); 3729 3730 /* Enable/Disable RSS query feature */ 3731 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 3732 adapter->vfinfo[i].rss_query_enabled); 3733 } 3734 } 3735 3736 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 3737 { 3738 struct ixgbe_hw *hw = &adapter->hw; 3739 struct net_device *netdev = adapter->netdev; 3740 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 3741 struct ixgbe_ring *rx_ring; 3742 int i; 3743 u32 mhadd, hlreg0; 3744 3745 #ifdef IXGBE_FCOE 3746 /* adjust max frame to be able to do baby jumbo for FCoE */ 3747 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 3748 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 3749 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 3750 3751 #endif /* IXGBE_FCOE */ 3752 3753 /* adjust max frame to be at least the size of a standard frame */ 3754 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 3755 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 3756 3757 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 3758 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 3759 mhadd &= ~IXGBE_MHADD_MFS_MASK; 3760 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 3761 3762 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 3763 } 3764 3765 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3766 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 3767 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 3768 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3769 3770 /* 3771 * Setup the HW Rx Head and Tail Descriptor Pointers and 3772 * the Base and Length of the Rx Descriptor Ring 3773 */ 3774 for (i = 0; i < adapter->num_rx_queues; i++) { 3775 rx_ring = adapter->rx_ring[i]; 3776 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 3777 set_ring_rsc_enabled(rx_ring); 3778 else 3779 clear_ring_rsc_enabled(rx_ring); 3780 } 3781 } 3782 3783 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 3784 { 3785 struct ixgbe_hw *hw = &adapter->hw; 3786 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 3787 3788 switch (hw->mac.type) { 3789 case ixgbe_mac_X550: 3790 case ixgbe_mac_X550EM_x: 3791 case ixgbe_mac_82598EB: 3792 /* 3793 * For VMDq support of different descriptor types or 3794 * buffer sizes through the use of multiple SRRCTL 3795 * registers, RDRXCTL.MVMEN must be set to 1 3796 * 3797 * also, the manual doesn't mention it clearly but DCA hints 3798 * will only use queue 0's tags unless this bit is set. Side 3799 * effects of setting this bit are only that SRRCTL must be 3800 * fully programmed [0..15] 3801 */ 3802 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 3803 break; 3804 case ixgbe_mac_82599EB: 3805 case ixgbe_mac_X540: 3806 /* Disable RSC for ACK packets */ 3807 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 3808 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 3809 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 3810 /* hardware requires some bits to be set by default */ 3811 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 3812 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 3813 break; 3814 default: 3815 /* We should do nothing since we don't know this hardware */ 3816 return; 3817 } 3818 3819 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 3820 } 3821 3822 /** 3823 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 3824 * @adapter: board private structure 3825 * 3826 * Configure the Rx unit of the MAC after a reset. 3827 **/ 3828 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 3829 { 3830 struct ixgbe_hw *hw = &adapter->hw; 3831 int i; 3832 u32 rxctrl, rfctl; 3833 3834 /* disable receives while setting up the descriptors */ 3835 hw->mac.ops.disable_rx(hw); 3836 3837 ixgbe_setup_psrtype(adapter); 3838 ixgbe_setup_rdrxctl(adapter); 3839 3840 /* RSC Setup */ 3841 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 3842 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 3843 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 3844 rfctl |= IXGBE_RFCTL_RSC_DIS; 3845 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 3846 3847 /* Program registers for the distribution of queues */ 3848 ixgbe_setup_mrqc(adapter); 3849 3850 /* set_rx_buffer_len must be called before ring initialization */ 3851 ixgbe_set_rx_buffer_len(adapter); 3852 3853 /* 3854 * Setup the HW Rx Head and Tail Descriptor Pointers and 3855 * the Base and Length of the Rx Descriptor Ring 3856 */ 3857 for (i = 0; i < adapter->num_rx_queues; i++) 3858 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 3859 3860 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 3861 /* disable drop enable for 82598 parts */ 3862 if (hw->mac.type == ixgbe_mac_82598EB) 3863 rxctrl |= IXGBE_RXCTRL_DMBYPS; 3864 3865 /* enable all receives */ 3866 rxctrl |= IXGBE_RXCTRL_RXEN; 3867 hw->mac.ops.enable_rx_dma(hw, rxctrl); 3868 } 3869 3870 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 3871 __be16 proto, u16 vid) 3872 { 3873 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3874 struct ixgbe_hw *hw = &adapter->hw; 3875 3876 /* add VID to filter table */ 3877 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true); 3878 set_bit(vid, adapter->active_vlans); 3879 3880 return 0; 3881 } 3882 3883 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 3884 __be16 proto, u16 vid) 3885 { 3886 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3887 struct ixgbe_hw *hw = &adapter->hw; 3888 3889 /* remove VID from filter table */ 3890 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false); 3891 clear_bit(vid, adapter->active_vlans); 3892 3893 return 0; 3894 } 3895 3896 /** 3897 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 3898 * @adapter: driver data 3899 */ 3900 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 3901 { 3902 struct ixgbe_hw *hw = &adapter->hw; 3903 u32 vlnctrl; 3904 int i, j; 3905 3906 switch (hw->mac.type) { 3907 case ixgbe_mac_82598EB: 3908 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3909 vlnctrl &= ~IXGBE_VLNCTRL_VME; 3910 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3911 break; 3912 case ixgbe_mac_82599EB: 3913 case ixgbe_mac_X540: 3914 case ixgbe_mac_X550: 3915 case ixgbe_mac_X550EM_x: 3916 for (i = 0; i < adapter->num_rx_queues; i++) { 3917 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3918 3919 if (ring->l2_accel_priv) 3920 continue; 3921 j = ring->reg_idx; 3922 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3923 vlnctrl &= ~IXGBE_RXDCTL_VME; 3924 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3925 } 3926 break; 3927 default: 3928 break; 3929 } 3930 } 3931 3932 /** 3933 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 3934 * @adapter: driver data 3935 */ 3936 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 3937 { 3938 struct ixgbe_hw *hw = &adapter->hw; 3939 u32 vlnctrl; 3940 int i, j; 3941 3942 switch (hw->mac.type) { 3943 case ixgbe_mac_82598EB: 3944 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 3945 vlnctrl |= IXGBE_VLNCTRL_VME; 3946 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 3947 break; 3948 case ixgbe_mac_82599EB: 3949 case ixgbe_mac_X540: 3950 case ixgbe_mac_X550: 3951 case ixgbe_mac_X550EM_x: 3952 for (i = 0; i < adapter->num_rx_queues; i++) { 3953 struct ixgbe_ring *ring = adapter->rx_ring[i]; 3954 3955 if (ring->l2_accel_priv) 3956 continue; 3957 j = ring->reg_idx; 3958 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 3959 vlnctrl |= IXGBE_RXDCTL_VME; 3960 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 3961 } 3962 break; 3963 default: 3964 break; 3965 } 3966 } 3967 3968 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 3969 { 3970 u16 vid; 3971 3972 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 3973 3974 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 3975 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 3976 } 3977 3978 /** 3979 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 3980 * @netdev: network interface device structure 3981 * 3982 * Writes multicast address list to the MTA hash table. 3983 * Returns: -ENOMEM on failure 3984 * 0 on no addresses written 3985 * X on writing X addresses to MTA 3986 **/ 3987 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 3988 { 3989 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3990 struct ixgbe_hw *hw = &adapter->hw; 3991 3992 if (!netif_running(netdev)) 3993 return 0; 3994 3995 if (hw->mac.ops.update_mc_addr_list) 3996 hw->mac.ops.update_mc_addr_list(hw, netdev); 3997 else 3998 return -ENOMEM; 3999 4000 #ifdef CONFIG_PCI_IOV 4001 ixgbe_restore_vf_multicasts(adapter); 4002 #endif 4003 4004 return netdev_mc_count(netdev); 4005 } 4006 4007 #ifdef CONFIG_PCI_IOV 4008 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4009 { 4010 struct ixgbe_hw *hw = &adapter->hw; 4011 int i; 4012 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4013 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 4014 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr, 4015 adapter->mac_table[i].queue, 4016 IXGBE_RAH_AV); 4017 else 4018 hw->mac.ops.clear_rar(hw, i); 4019 4020 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED); 4021 } 4022 } 4023 #endif 4024 4025 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4026 { 4027 struct ixgbe_hw *hw = &adapter->hw; 4028 int i; 4029 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4030 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) { 4031 if (adapter->mac_table[i].state & 4032 IXGBE_MAC_STATE_IN_USE) 4033 hw->mac.ops.set_rar(hw, i, 4034 adapter->mac_table[i].addr, 4035 adapter->mac_table[i].queue, 4036 IXGBE_RAH_AV); 4037 else 4038 hw->mac.ops.clear_rar(hw, i); 4039 4040 adapter->mac_table[i].state &= 4041 ~(IXGBE_MAC_STATE_MODIFIED); 4042 } 4043 } 4044 } 4045 4046 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4047 { 4048 int i; 4049 struct ixgbe_hw *hw = &adapter->hw; 4050 4051 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4052 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 4053 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 4054 eth_zero_addr(adapter->mac_table[i].addr); 4055 adapter->mac_table[i].queue = 0; 4056 } 4057 ixgbe_sync_mac_table(adapter); 4058 } 4059 4060 static int ixgbe_available_rars(struct ixgbe_adapter *adapter) 4061 { 4062 struct ixgbe_hw *hw = &adapter->hw; 4063 int i, count = 0; 4064 4065 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4066 if (adapter->mac_table[i].state == 0) 4067 count++; 4068 } 4069 return count; 4070 } 4071 4072 /* this function destroys the first RAR entry */ 4073 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter, 4074 u8 *addr) 4075 { 4076 struct ixgbe_hw *hw = &adapter->hw; 4077 4078 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN); 4079 adapter->mac_table[0].queue = VMDQ_P(0); 4080 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT | 4081 IXGBE_MAC_STATE_IN_USE); 4082 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr, 4083 adapter->mac_table[0].queue, 4084 IXGBE_RAH_AV); 4085 } 4086 4087 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 4088 { 4089 struct ixgbe_hw *hw = &adapter->hw; 4090 int i; 4091 4092 if (is_zero_ether_addr(addr)) 4093 return -EINVAL; 4094 4095 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4096 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) 4097 continue; 4098 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED | 4099 IXGBE_MAC_STATE_IN_USE); 4100 ether_addr_copy(adapter->mac_table[i].addr, addr); 4101 adapter->mac_table[i].queue = queue; 4102 ixgbe_sync_mac_table(adapter); 4103 return i; 4104 } 4105 return -ENOMEM; 4106 } 4107 4108 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue) 4109 { 4110 /* search table for addr, if found, set to 0 and sync */ 4111 int i; 4112 struct ixgbe_hw *hw = &adapter->hw; 4113 4114 if (is_zero_ether_addr(addr)) 4115 return -EINVAL; 4116 4117 for (i = 0; i < hw->mac.num_rar_entries; i++) { 4118 if (ether_addr_equal(addr, adapter->mac_table[i].addr) && 4119 adapter->mac_table[i].queue == queue) { 4120 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED; 4121 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE; 4122 eth_zero_addr(adapter->mac_table[i].addr); 4123 adapter->mac_table[i].queue = 0; 4124 ixgbe_sync_mac_table(adapter); 4125 return 0; 4126 } 4127 } 4128 return -ENOMEM; 4129 } 4130 /** 4131 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4132 * @netdev: network interface device structure 4133 * 4134 * Writes unicast address list to the RAR table. 4135 * Returns: -ENOMEM on failure/insufficient address space 4136 * 0 on no addresses written 4137 * X on writing X addresses to the RAR table 4138 **/ 4139 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4140 { 4141 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4142 int count = 0; 4143 4144 /* return ENOMEM indicating insufficient memory for addresses */ 4145 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter)) 4146 return -ENOMEM; 4147 4148 if (!netdev_uc_empty(netdev)) { 4149 struct netdev_hw_addr *ha; 4150 netdev_for_each_uc_addr(ha, netdev) { 4151 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4152 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4153 count++; 4154 } 4155 } 4156 return count; 4157 } 4158 4159 /** 4160 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4161 * @netdev: network interface device structure 4162 * 4163 * The set_rx_method entry point is called whenever the unicast/multicast 4164 * address list or the network interface flags are updated. This routine is 4165 * responsible for configuring the hardware for proper unicast, multicast and 4166 * promiscuous mode. 4167 **/ 4168 void ixgbe_set_rx_mode(struct net_device *netdev) 4169 { 4170 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4171 struct ixgbe_hw *hw = &adapter->hw; 4172 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4173 u32 vlnctrl; 4174 int count; 4175 4176 /* Check for Promiscuous and All Multicast modes */ 4177 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4178 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4179 4180 /* set all bits that we expect to always be set */ 4181 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4182 fctrl |= IXGBE_FCTRL_BAM; 4183 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4184 fctrl |= IXGBE_FCTRL_PMCF; 4185 4186 /* clear the bits we are changing the status of */ 4187 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4188 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4189 if (netdev->flags & IFF_PROMISC) { 4190 hw->addr_ctrl.user_set_promisc = true; 4191 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4192 vmolr |= IXGBE_VMOLR_MPE; 4193 /* Only disable hardware filter vlans in promiscuous mode 4194 * if SR-IOV and VMDQ are disabled - otherwise ensure 4195 * that hardware VLAN filters remain enabled. 4196 */ 4197 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED | 4198 IXGBE_FLAG_SRIOV_ENABLED)) 4199 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); 4200 } else { 4201 if (netdev->flags & IFF_ALLMULTI) { 4202 fctrl |= IXGBE_FCTRL_MPE; 4203 vmolr |= IXGBE_VMOLR_MPE; 4204 } 4205 vlnctrl |= IXGBE_VLNCTRL_VFE; 4206 hw->addr_ctrl.user_set_promisc = false; 4207 } 4208 4209 /* 4210 * Write addresses to available RAR registers, if there is not 4211 * sufficient space to store all the addresses then enable 4212 * unicast promiscuous mode 4213 */ 4214 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0)); 4215 if (count < 0) { 4216 fctrl |= IXGBE_FCTRL_UPE; 4217 vmolr |= IXGBE_VMOLR_ROPE; 4218 } 4219 4220 /* Write addresses to the MTA, if the attempt fails 4221 * then we should just turn on promiscuous mode so 4222 * that we can at least receive multicast traffic 4223 */ 4224 count = ixgbe_write_mc_addr_list(netdev); 4225 if (count < 0) { 4226 fctrl |= IXGBE_FCTRL_MPE; 4227 vmolr |= IXGBE_VMOLR_MPE; 4228 } else if (count) { 4229 vmolr |= IXGBE_VMOLR_ROMPE; 4230 } 4231 4232 if (hw->mac.type != ixgbe_mac_82598EB) { 4233 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4234 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4235 IXGBE_VMOLR_ROPE); 4236 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4237 } 4238 4239 /* This is useful for sniffing bad packets. */ 4240 if (adapter->netdev->features & NETIF_F_RXALL) { 4241 /* UPE and MPE will be handled by normal PROMISC logic 4242 * in e1000e_set_rx_mode */ 4243 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4244 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4245 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4246 4247 fctrl &= ~(IXGBE_FCTRL_DPF); 4248 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4249 } 4250 4251 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4252 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4253 4254 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 4255 ixgbe_vlan_strip_enable(adapter); 4256 else 4257 ixgbe_vlan_strip_disable(adapter); 4258 } 4259 4260 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4261 { 4262 int q_idx; 4263 4264 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4265 ixgbe_qv_init_lock(adapter->q_vector[q_idx]); 4266 napi_enable(&adapter->q_vector[q_idx]->napi); 4267 } 4268 } 4269 4270 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4271 { 4272 int q_idx; 4273 4274 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { 4275 napi_disable(&adapter->q_vector[q_idx]->napi); 4276 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { 4277 pr_info("QV %d locked\n", q_idx); 4278 usleep_range(1000, 20000); 4279 } 4280 } 4281 } 4282 4283 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter) 4284 { 4285 switch (adapter->hw.mac.type) { 4286 case ixgbe_mac_X550: 4287 case ixgbe_mac_X550EM_x: 4288 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0); 4289 #ifdef CONFIG_IXGBE_VXLAN 4290 adapter->vxlan_port = 0; 4291 #endif 4292 break; 4293 default: 4294 break; 4295 } 4296 } 4297 4298 #ifdef CONFIG_IXGBE_DCB 4299 /** 4300 * ixgbe_configure_dcb - Configure DCB hardware 4301 * @adapter: ixgbe adapter struct 4302 * 4303 * This is called by the driver on open to configure the DCB hardware. 4304 * This is also called by the gennetlink interface when reconfiguring 4305 * the DCB state. 4306 */ 4307 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4308 { 4309 struct ixgbe_hw *hw = &adapter->hw; 4310 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4311 4312 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4313 if (hw->mac.type == ixgbe_mac_82598EB) 4314 netif_set_gso_max_size(adapter->netdev, 65536); 4315 return; 4316 } 4317 4318 if (hw->mac.type == ixgbe_mac_82598EB) 4319 netif_set_gso_max_size(adapter->netdev, 32768); 4320 4321 #ifdef IXGBE_FCOE 4322 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4323 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4324 #endif 4325 4326 /* reconfigure the hardware */ 4327 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4328 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4329 DCB_TX_CONFIG); 4330 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4331 DCB_RX_CONFIG); 4332 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4333 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4334 ixgbe_dcb_hw_ets(&adapter->hw, 4335 adapter->ixgbe_ieee_ets, 4336 max_frame); 4337 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4338 adapter->ixgbe_ieee_pfc->pfc_en, 4339 adapter->ixgbe_ieee_ets->prio_tc); 4340 } 4341 4342 /* Enable RSS Hash per TC */ 4343 if (hw->mac.type != ixgbe_mac_82598EB) { 4344 u32 msb = 0; 4345 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4346 4347 while (rss_i) { 4348 msb++; 4349 rss_i >>= 1; 4350 } 4351 4352 /* write msb to all 8 TCs in one write */ 4353 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4354 } 4355 } 4356 #endif 4357 4358 /* Additional bittime to account for IXGBE framing */ 4359 #define IXGBE_ETH_FRAMING 20 4360 4361 /** 4362 * ixgbe_hpbthresh - calculate high water mark for flow control 4363 * 4364 * @adapter: board private structure to calculate for 4365 * @pb: packet buffer to calculate 4366 */ 4367 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4368 { 4369 struct ixgbe_hw *hw = &adapter->hw; 4370 struct net_device *dev = adapter->netdev; 4371 int link, tc, kb, marker; 4372 u32 dv_id, rx_pba; 4373 4374 /* Calculate max LAN frame size */ 4375 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4376 4377 #ifdef IXGBE_FCOE 4378 /* FCoE traffic class uses FCOE jumbo frames */ 4379 if ((dev->features & NETIF_F_FCOE_MTU) && 4380 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4381 (pb == ixgbe_fcoe_get_tc(adapter))) 4382 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4383 #endif 4384 4385 /* Calculate delay value for device */ 4386 switch (hw->mac.type) { 4387 case ixgbe_mac_X540: 4388 case ixgbe_mac_X550: 4389 case ixgbe_mac_X550EM_x: 4390 dv_id = IXGBE_DV_X540(link, tc); 4391 break; 4392 default: 4393 dv_id = IXGBE_DV(link, tc); 4394 break; 4395 } 4396 4397 /* Loopback switch introduces additional latency */ 4398 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4399 dv_id += IXGBE_B2BT(tc); 4400 4401 /* Delay value is calculated in bit times convert to KB */ 4402 kb = IXGBE_BT2KB(dv_id); 4403 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4404 4405 marker = rx_pba - kb; 4406 4407 /* It is possible that the packet buffer is not large enough 4408 * to provide required headroom. In this case throw an error 4409 * to user and a do the best we can. 4410 */ 4411 if (marker < 0) { 4412 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4413 "headroom to support flow control." 4414 "Decrease MTU or number of traffic classes\n", pb); 4415 marker = tc + 1; 4416 } 4417 4418 return marker; 4419 } 4420 4421 /** 4422 * ixgbe_lpbthresh - calculate low water mark for for flow control 4423 * 4424 * @adapter: board private structure to calculate for 4425 * @pb: packet buffer to calculate 4426 */ 4427 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 4428 { 4429 struct ixgbe_hw *hw = &adapter->hw; 4430 struct net_device *dev = adapter->netdev; 4431 int tc; 4432 u32 dv_id; 4433 4434 /* Calculate max LAN frame size */ 4435 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 4436 4437 #ifdef IXGBE_FCOE 4438 /* FCoE traffic class uses FCOE jumbo frames */ 4439 if ((dev->features & NETIF_F_FCOE_MTU) && 4440 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4441 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 4442 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4443 #endif 4444 4445 /* Calculate delay value for device */ 4446 switch (hw->mac.type) { 4447 case ixgbe_mac_X540: 4448 case ixgbe_mac_X550: 4449 case ixgbe_mac_X550EM_x: 4450 dv_id = IXGBE_LOW_DV_X540(tc); 4451 break; 4452 default: 4453 dv_id = IXGBE_LOW_DV(tc); 4454 break; 4455 } 4456 4457 /* Delay value is calculated in bit times convert to KB */ 4458 return IXGBE_BT2KB(dv_id); 4459 } 4460 4461 /* 4462 * ixgbe_pbthresh_setup - calculate and setup high low water marks 4463 */ 4464 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 4465 { 4466 struct ixgbe_hw *hw = &adapter->hw; 4467 int num_tc = netdev_get_num_tc(adapter->netdev); 4468 int i; 4469 4470 if (!num_tc) 4471 num_tc = 1; 4472 4473 for (i = 0; i < num_tc; i++) { 4474 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 4475 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 4476 4477 /* Low water marks must not be larger than high water marks */ 4478 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 4479 hw->fc.low_water[i] = 0; 4480 } 4481 4482 for (; i < MAX_TRAFFIC_CLASS; i++) 4483 hw->fc.high_water[i] = 0; 4484 } 4485 4486 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 4487 { 4488 struct ixgbe_hw *hw = &adapter->hw; 4489 int hdrm; 4490 u8 tc = netdev_get_num_tc(adapter->netdev); 4491 4492 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 4493 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 4494 hdrm = 32 << adapter->fdir_pballoc; 4495 else 4496 hdrm = 0; 4497 4498 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 4499 ixgbe_pbthresh_setup(adapter); 4500 } 4501 4502 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 4503 { 4504 struct ixgbe_hw *hw = &adapter->hw; 4505 struct hlist_node *node2; 4506 struct ixgbe_fdir_filter *filter; 4507 4508 spin_lock(&adapter->fdir_perfect_lock); 4509 4510 if (!hlist_empty(&adapter->fdir_filter_list)) 4511 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 4512 4513 hlist_for_each_entry_safe(filter, node2, 4514 &adapter->fdir_filter_list, fdir_node) { 4515 ixgbe_fdir_write_perfect_filter_82599(hw, 4516 &filter->filter, 4517 filter->sw_idx, 4518 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 4519 IXGBE_FDIR_DROP_QUEUE : 4520 adapter->rx_ring[filter->action]->reg_idx); 4521 } 4522 4523 spin_unlock(&adapter->fdir_perfect_lock); 4524 } 4525 4526 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 4527 struct ixgbe_adapter *adapter) 4528 { 4529 struct ixgbe_hw *hw = &adapter->hw; 4530 u32 vmolr; 4531 4532 /* No unicast promiscuous support for VMDQ devices. */ 4533 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 4534 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 4535 4536 /* clear the affected bit */ 4537 vmolr &= ~IXGBE_VMOLR_MPE; 4538 4539 if (dev->flags & IFF_ALLMULTI) { 4540 vmolr |= IXGBE_VMOLR_MPE; 4541 } else { 4542 vmolr |= IXGBE_VMOLR_ROMPE; 4543 hw->mac.ops.update_mc_addr_list(hw, dev); 4544 } 4545 ixgbe_write_uc_addr_list(adapter->netdev, pool); 4546 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 4547 } 4548 4549 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 4550 { 4551 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4552 int rss_i = adapter->num_rx_queues_per_pool; 4553 struct ixgbe_hw *hw = &adapter->hw; 4554 u16 pool = vadapter->pool; 4555 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4556 IXGBE_PSRTYPE_UDPHDR | 4557 IXGBE_PSRTYPE_IPV4HDR | 4558 IXGBE_PSRTYPE_L2HDR | 4559 IXGBE_PSRTYPE_IPV6HDR; 4560 4561 if (hw->mac.type == ixgbe_mac_82598EB) 4562 return; 4563 4564 if (rss_i > 3) 4565 psrtype |= 2 << 29; 4566 else if (rss_i > 1) 4567 psrtype |= 1 << 29; 4568 4569 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4570 } 4571 4572 /** 4573 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 4574 * @rx_ring: ring to free buffers from 4575 **/ 4576 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 4577 { 4578 struct device *dev = rx_ring->dev; 4579 unsigned long size; 4580 u16 i; 4581 4582 /* ring already cleared, nothing to do */ 4583 if (!rx_ring->rx_buffer_info) 4584 return; 4585 4586 /* Free all the Rx ring sk_buffs */ 4587 for (i = 0; i < rx_ring->count; i++) { 4588 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 4589 4590 if (rx_buffer->skb) { 4591 struct sk_buff *skb = rx_buffer->skb; 4592 if (IXGBE_CB(skb)->page_released) 4593 dma_unmap_page(dev, 4594 IXGBE_CB(skb)->dma, 4595 ixgbe_rx_bufsz(rx_ring), 4596 DMA_FROM_DEVICE); 4597 dev_kfree_skb(skb); 4598 rx_buffer->skb = NULL; 4599 } 4600 4601 if (!rx_buffer->page) 4602 continue; 4603 4604 dma_unmap_page(dev, rx_buffer->dma, 4605 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); 4606 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); 4607 4608 rx_buffer->page = NULL; 4609 } 4610 4611 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 4612 memset(rx_ring->rx_buffer_info, 0, size); 4613 4614 /* Zero out the descriptor ring */ 4615 memset(rx_ring->desc, 0, rx_ring->size); 4616 4617 rx_ring->next_to_alloc = 0; 4618 rx_ring->next_to_clean = 0; 4619 rx_ring->next_to_use = 0; 4620 } 4621 4622 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 4623 struct ixgbe_ring *rx_ring) 4624 { 4625 struct ixgbe_adapter *adapter = vadapter->real_adapter; 4626 int index = rx_ring->queue_index + vadapter->rx_base_queue; 4627 4628 /* shutdown specific queue receive and wait for dma to settle */ 4629 ixgbe_disable_rx_queue(adapter, rx_ring); 4630 usleep_range(10000, 20000); 4631 ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); 4632 ixgbe_clean_rx_ring(rx_ring); 4633 rx_ring->l2_accel_priv = NULL; 4634 } 4635 4636 static int ixgbe_fwd_ring_down(struct net_device *vdev, 4637 struct ixgbe_fwd_adapter *accel) 4638 { 4639 struct ixgbe_adapter *adapter = accel->real_adapter; 4640 unsigned int rxbase = accel->rx_base_queue; 4641 unsigned int txbase = accel->tx_base_queue; 4642 int i; 4643 4644 netif_tx_stop_all_queues(vdev); 4645 4646 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4647 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4648 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 4649 } 4650 4651 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4652 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 4653 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 4654 } 4655 4656 4657 return 0; 4658 } 4659 4660 static int ixgbe_fwd_ring_up(struct net_device *vdev, 4661 struct ixgbe_fwd_adapter *accel) 4662 { 4663 struct ixgbe_adapter *adapter = accel->real_adapter; 4664 unsigned int rxbase, txbase, queues; 4665 int i, baseq, err = 0; 4666 4667 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 4668 return 0; 4669 4670 baseq = accel->pool * adapter->num_rx_queues_per_pool; 4671 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 4672 accel->pool, adapter->num_rx_pools, 4673 baseq, baseq + adapter->num_rx_queues_per_pool, 4674 adapter->fwd_bitmask); 4675 4676 accel->netdev = vdev; 4677 accel->rx_base_queue = rxbase = baseq; 4678 accel->tx_base_queue = txbase = baseq; 4679 4680 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 4681 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 4682 4683 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4684 adapter->rx_ring[rxbase + i]->netdev = vdev; 4685 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 4686 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 4687 } 4688 4689 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 4690 adapter->tx_ring[txbase + i]->netdev = vdev; 4691 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 4692 } 4693 4694 queues = min_t(unsigned int, 4695 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 4696 err = netif_set_real_num_tx_queues(vdev, queues); 4697 if (err) 4698 goto fwd_queue_err; 4699 4700 err = netif_set_real_num_rx_queues(vdev, queues); 4701 if (err) 4702 goto fwd_queue_err; 4703 4704 if (is_valid_ether_addr(vdev->dev_addr)) 4705 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 4706 4707 ixgbe_fwd_psrtype(accel); 4708 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 4709 return err; 4710 fwd_queue_err: 4711 ixgbe_fwd_ring_down(vdev, accel); 4712 return err; 4713 } 4714 4715 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 4716 { 4717 struct net_device *upper; 4718 struct list_head *iter; 4719 int err; 4720 4721 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 4722 if (netif_is_macvlan(upper)) { 4723 struct macvlan_dev *dfwd = netdev_priv(upper); 4724 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 4725 4726 if (dfwd->fwd_priv) { 4727 err = ixgbe_fwd_ring_up(upper, vadapter); 4728 if (err) 4729 continue; 4730 } 4731 } 4732 } 4733 } 4734 4735 static void ixgbe_configure(struct ixgbe_adapter *adapter) 4736 { 4737 struct ixgbe_hw *hw = &adapter->hw; 4738 4739 ixgbe_configure_pb(adapter); 4740 #ifdef CONFIG_IXGBE_DCB 4741 ixgbe_configure_dcb(adapter); 4742 #endif 4743 /* 4744 * We must restore virtualization before VLANs or else 4745 * the VLVF registers will not be populated 4746 */ 4747 ixgbe_configure_virtualization(adapter); 4748 4749 ixgbe_set_rx_mode(adapter->netdev); 4750 ixgbe_restore_vlan(adapter); 4751 4752 switch (hw->mac.type) { 4753 case ixgbe_mac_82599EB: 4754 case ixgbe_mac_X540: 4755 hw->mac.ops.disable_rx_buff(hw); 4756 break; 4757 default: 4758 break; 4759 } 4760 4761 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 4762 ixgbe_init_fdir_signature_82599(&adapter->hw, 4763 adapter->fdir_pballoc); 4764 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 4765 ixgbe_init_fdir_perfect_82599(&adapter->hw, 4766 adapter->fdir_pballoc); 4767 ixgbe_fdir_filter_restore(adapter); 4768 } 4769 4770 switch (hw->mac.type) { 4771 case ixgbe_mac_82599EB: 4772 case ixgbe_mac_X540: 4773 hw->mac.ops.enable_rx_buff(hw); 4774 break; 4775 default: 4776 break; 4777 } 4778 4779 #ifdef IXGBE_FCOE 4780 /* configure FCoE L2 filters, redirection table, and Rx control */ 4781 ixgbe_configure_fcoe(adapter); 4782 4783 #endif /* IXGBE_FCOE */ 4784 ixgbe_configure_tx(adapter); 4785 ixgbe_configure_rx(adapter); 4786 ixgbe_configure_dfwd(adapter); 4787 } 4788 4789 /** 4790 * ixgbe_sfp_link_config - set up SFP+ link 4791 * @adapter: pointer to private adapter struct 4792 **/ 4793 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 4794 { 4795 /* 4796 * We are assuming the worst case scenario here, and that 4797 * is that an SFP was inserted/removed after the reset 4798 * but before SFP detection was enabled. As such the best 4799 * solution is to just start searching as soon as we start 4800 */ 4801 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4802 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 4803 4804 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 4805 } 4806 4807 /** 4808 * ixgbe_non_sfp_link_config - set up non-SFP+ link 4809 * @hw: pointer to private hardware struct 4810 * 4811 * Returns 0 on success, negative on failure 4812 **/ 4813 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 4814 { 4815 u32 speed; 4816 bool autoneg, link_up = false; 4817 int ret = IXGBE_ERR_LINK_SETUP; 4818 4819 if (hw->mac.ops.check_link) 4820 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 4821 4822 if (ret) 4823 return ret; 4824 4825 speed = hw->phy.autoneg_advertised; 4826 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 4827 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 4828 &autoneg); 4829 if (ret) 4830 return ret; 4831 4832 if (hw->mac.ops.setup_link) 4833 ret = hw->mac.ops.setup_link(hw, speed, link_up); 4834 4835 return ret; 4836 } 4837 4838 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 4839 { 4840 struct ixgbe_hw *hw = &adapter->hw; 4841 u32 gpie = 0; 4842 4843 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 4844 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 4845 IXGBE_GPIE_OCD; 4846 gpie |= IXGBE_GPIE_EIAME; 4847 /* 4848 * use EIAM to auto-mask when MSI-X interrupt is asserted 4849 * this saves a register write for every interrupt 4850 */ 4851 switch (hw->mac.type) { 4852 case ixgbe_mac_82598EB: 4853 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4854 break; 4855 case ixgbe_mac_82599EB: 4856 case ixgbe_mac_X540: 4857 case ixgbe_mac_X550: 4858 case ixgbe_mac_X550EM_x: 4859 default: 4860 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 4861 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 4862 break; 4863 } 4864 } else { 4865 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 4866 * specifically only auto mask tx and rx interrupts */ 4867 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 4868 } 4869 4870 /* XXX: to interrupt immediately for EICS writes, enable this */ 4871 /* gpie |= IXGBE_GPIE_EIMEN; */ 4872 4873 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4874 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 4875 4876 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4877 case IXGBE_82599_VMDQ_8Q_MASK: 4878 gpie |= IXGBE_GPIE_VTMODE_16; 4879 break; 4880 case IXGBE_82599_VMDQ_4Q_MASK: 4881 gpie |= IXGBE_GPIE_VTMODE_32; 4882 break; 4883 default: 4884 gpie |= IXGBE_GPIE_VTMODE_64; 4885 break; 4886 } 4887 } 4888 4889 /* Enable Thermal over heat sensor interrupt */ 4890 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 4891 switch (adapter->hw.mac.type) { 4892 case ixgbe_mac_82599EB: 4893 gpie |= IXGBE_SDP0_GPIEN_8259X; 4894 break; 4895 case ixgbe_mac_X540: 4896 gpie |= IXGBE_EIMS_TS; 4897 break; 4898 default: 4899 break; 4900 } 4901 } 4902 4903 /* Enable fan failure interrupt */ 4904 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 4905 gpie |= IXGBE_SDP1_GPIEN(hw); 4906 4907 if (hw->mac.type == ixgbe_mac_82599EB) { 4908 gpie |= IXGBE_SDP1_GPIEN_8259X; 4909 gpie |= IXGBE_SDP2_GPIEN_8259X; 4910 } 4911 4912 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 4913 } 4914 4915 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 4916 { 4917 struct ixgbe_hw *hw = &adapter->hw; 4918 int err; 4919 u32 ctrl_ext; 4920 4921 ixgbe_get_hw_control(adapter); 4922 ixgbe_setup_gpie(adapter); 4923 4924 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 4925 ixgbe_configure_msix(adapter); 4926 else 4927 ixgbe_configure_msi_and_legacy(adapter); 4928 4929 /* enable the optics for 82599 SFP+ fiber */ 4930 if (hw->mac.ops.enable_tx_laser) 4931 hw->mac.ops.enable_tx_laser(hw); 4932 4933 if (hw->phy.ops.set_phy_power) 4934 hw->phy.ops.set_phy_power(hw, true); 4935 4936 smp_mb__before_atomic(); 4937 clear_bit(__IXGBE_DOWN, &adapter->state); 4938 ixgbe_napi_enable_all(adapter); 4939 4940 if (ixgbe_is_sfp(hw)) { 4941 ixgbe_sfp_link_config(adapter); 4942 } else { 4943 err = ixgbe_non_sfp_link_config(hw); 4944 if (err) 4945 e_err(probe, "link_config FAILED %d\n", err); 4946 } 4947 4948 /* clear any pending interrupts, may auto mask */ 4949 IXGBE_READ_REG(hw, IXGBE_EICR); 4950 ixgbe_irq_enable(adapter, true, true); 4951 4952 /* 4953 * If this adapter has a fan, check to see if we had a failure 4954 * before we enabled the interrupt. 4955 */ 4956 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 4957 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4958 if (esdp & IXGBE_ESDP_SDP1) 4959 e_crit(drv, "Fan has stopped, replace the adapter\n"); 4960 } 4961 4962 /* bring the link up in the watchdog, this could race with our first 4963 * link up interrupt but shouldn't be a problem */ 4964 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4965 adapter->link_check_timeout = jiffies; 4966 mod_timer(&adapter->service_timer, jiffies); 4967 4968 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 4969 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 4970 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 4971 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 4972 } 4973 4974 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 4975 { 4976 WARN_ON(in_interrupt()); 4977 /* put off any impending NetWatchDogTimeout */ 4978 adapter->netdev->trans_start = jiffies; 4979 4980 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 4981 usleep_range(1000, 2000); 4982 ixgbe_down(adapter); 4983 /* 4984 * If SR-IOV enabled then wait a bit before bringing the adapter 4985 * back up to give the VFs time to respond to the reset. The 4986 * two second wait is based upon the watchdog timer cycle in 4987 * the VF driver. 4988 */ 4989 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4990 msleep(2000); 4991 ixgbe_up(adapter); 4992 clear_bit(__IXGBE_RESETTING, &adapter->state); 4993 } 4994 4995 void ixgbe_up(struct ixgbe_adapter *adapter) 4996 { 4997 /* hardware has been reset, we need to reload some things */ 4998 ixgbe_configure(adapter); 4999 5000 ixgbe_up_complete(adapter); 5001 } 5002 5003 void ixgbe_reset(struct ixgbe_adapter *adapter) 5004 { 5005 struct ixgbe_hw *hw = &adapter->hw; 5006 struct net_device *netdev = adapter->netdev; 5007 int err; 5008 u8 old_addr[ETH_ALEN]; 5009 5010 if (ixgbe_removed(hw->hw_addr)) 5011 return; 5012 /* lock SFP init bit to prevent race conditions with the watchdog */ 5013 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5014 usleep_range(1000, 2000); 5015 5016 /* clear all SFP and link config related flags while holding SFP_INIT */ 5017 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5018 IXGBE_FLAG2_SFP_NEEDS_RESET); 5019 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5020 5021 err = hw->mac.ops.init_hw(hw); 5022 switch (err) { 5023 case 0: 5024 case IXGBE_ERR_SFP_NOT_PRESENT: 5025 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5026 break; 5027 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5028 e_dev_err("master disable timed out\n"); 5029 break; 5030 case IXGBE_ERR_EEPROM_VERSION: 5031 /* We are running on a pre-production device, log a warning */ 5032 e_dev_warn("This device is a pre-production adapter/LOM. " 5033 "Please be aware there may be issues associated with " 5034 "your hardware. If you are experiencing problems " 5035 "please contact your Intel or hardware " 5036 "representative who provided you with this " 5037 "hardware.\n"); 5038 break; 5039 default: 5040 e_dev_err("Hardware Error: %d\n", err); 5041 } 5042 5043 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5044 /* do not flush user set addresses */ 5045 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len); 5046 ixgbe_flush_sw_mac_table(adapter); 5047 ixgbe_mac_set_default_filter(adapter, old_addr); 5048 5049 /* update SAN MAC vmdq pool selection */ 5050 if (hw->mac.san_mac_rar_index) 5051 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5052 5053 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5054 ixgbe_ptp_reset(adapter); 5055 5056 if (hw->phy.ops.set_phy_power) { 5057 if (!netif_running(adapter->netdev) && !adapter->wol) 5058 hw->phy.ops.set_phy_power(hw, false); 5059 else 5060 hw->phy.ops.set_phy_power(hw, true); 5061 } 5062 } 5063 5064 /** 5065 * ixgbe_clean_tx_ring - Free Tx Buffers 5066 * @tx_ring: ring to be cleaned 5067 **/ 5068 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5069 { 5070 struct ixgbe_tx_buffer *tx_buffer_info; 5071 unsigned long size; 5072 u16 i; 5073 5074 /* ring already cleared, nothing to do */ 5075 if (!tx_ring->tx_buffer_info) 5076 return; 5077 5078 /* Free all the Tx ring sk_buffs */ 5079 for (i = 0; i < tx_ring->count; i++) { 5080 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 5081 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 5082 } 5083 5084 netdev_tx_reset_queue(txring_txq(tx_ring)); 5085 5086 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5087 memset(tx_ring->tx_buffer_info, 0, size); 5088 5089 /* Zero out the descriptor ring */ 5090 memset(tx_ring->desc, 0, tx_ring->size); 5091 5092 tx_ring->next_to_use = 0; 5093 tx_ring->next_to_clean = 0; 5094 } 5095 5096 /** 5097 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5098 * @adapter: board private structure 5099 **/ 5100 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5101 { 5102 int i; 5103 5104 for (i = 0; i < adapter->num_rx_queues; i++) 5105 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5106 } 5107 5108 /** 5109 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5110 * @adapter: board private structure 5111 **/ 5112 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5113 { 5114 int i; 5115 5116 for (i = 0; i < adapter->num_tx_queues; i++) 5117 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5118 } 5119 5120 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5121 { 5122 struct hlist_node *node2; 5123 struct ixgbe_fdir_filter *filter; 5124 5125 spin_lock(&adapter->fdir_perfect_lock); 5126 5127 hlist_for_each_entry_safe(filter, node2, 5128 &adapter->fdir_filter_list, fdir_node) { 5129 hlist_del(&filter->fdir_node); 5130 kfree(filter); 5131 } 5132 adapter->fdir_filter_count = 0; 5133 5134 spin_unlock(&adapter->fdir_perfect_lock); 5135 } 5136 5137 void ixgbe_down(struct ixgbe_adapter *adapter) 5138 { 5139 struct net_device *netdev = adapter->netdev; 5140 struct ixgbe_hw *hw = &adapter->hw; 5141 struct net_device *upper; 5142 struct list_head *iter; 5143 int i; 5144 5145 /* signal that we are down to the interrupt handler */ 5146 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5147 return; /* do nothing if already down */ 5148 5149 /* disable receives */ 5150 hw->mac.ops.disable_rx(hw); 5151 5152 /* disable all enabled rx queues */ 5153 for (i = 0; i < adapter->num_rx_queues; i++) 5154 /* this call also flushes the previous write */ 5155 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5156 5157 usleep_range(10000, 20000); 5158 5159 netif_tx_stop_all_queues(netdev); 5160 5161 /* call carrier off first to avoid false dev_watchdog timeouts */ 5162 netif_carrier_off(netdev); 5163 netif_tx_disable(netdev); 5164 5165 /* disable any upper devices */ 5166 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 5167 if (netif_is_macvlan(upper)) { 5168 struct macvlan_dev *vlan = netdev_priv(upper); 5169 5170 if (vlan->fwd_priv) { 5171 netif_tx_stop_all_queues(upper); 5172 netif_carrier_off(upper); 5173 netif_tx_disable(upper); 5174 } 5175 } 5176 } 5177 5178 ixgbe_irq_disable(adapter); 5179 5180 ixgbe_napi_disable_all(adapter); 5181 5182 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | 5183 IXGBE_FLAG2_RESET_REQUESTED); 5184 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5185 5186 del_timer_sync(&adapter->service_timer); 5187 5188 if (adapter->num_vfs) { 5189 /* Clear EITR Select mapping */ 5190 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5191 5192 /* Mark all the VFs as inactive */ 5193 for (i = 0 ; i < adapter->num_vfs; i++) 5194 adapter->vfinfo[i].clear_to_send = false; 5195 5196 /* ping all the active vfs to let them know we are going down */ 5197 ixgbe_ping_all_vfs(adapter); 5198 5199 /* Disable all VFTE/VFRE TX/RX */ 5200 ixgbe_disable_tx_rx(adapter); 5201 } 5202 5203 /* disable transmits in the hardware now that interrupts are off */ 5204 for (i = 0; i < adapter->num_tx_queues; i++) { 5205 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5206 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5207 } 5208 5209 /* Disable the Tx DMA engine on 82599 and later MAC */ 5210 switch (hw->mac.type) { 5211 case ixgbe_mac_82599EB: 5212 case ixgbe_mac_X540: 5213 case ixgbe_mac_X550: 5214 case ixgbe_mac_X550EM_x: 5215 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5216 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5217 ~IXGBE_DMATXCTL_TE)); 5218 break; 5219 default: 5220 break; 5221 } 5222 5223 if (!pci_channel_offline(adapter->pdev)) 5224 ixgbe_reset(adapter); 5225 5226 /* power down the optics for 82599 SFP+ fiber */ 5227 if (hw->mac.ops.disable_tx_laser) 5228 hw->mac.ops.disable_tx_laser(hw); 5229 5230 ixgbe_clean_all_tx_rings(adapter); 5231 ixgbe_clean_all_rx_rings(adapter); 5232 5233 #ifdef CONFIG_IXGBE_DCA 5234 /* since we reset the hardware DCA settings were cleared */ 5235 ixgbe_setup_dca(adapter); 5236 #endif 5237 } 5238 5239 /** 5240 * ixgbe_tx_timeout - Respond to a Tx Hang 5241 * @netdev: network interface device structure 5242 **/ 5243 static void ixgbe_tx_timeout(struct net_device *netdev) 5244 { 5245 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5246 5247 /* Do the reset outside of interrupt context */ 5248 ixgbe_tx_timeout_reset(adapter); 5249 } 5250 5251 /** 5252 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5253 * @adapter: board private structure to initialize 5254 * 5255 * ixgbe_sw_init initializes the Adapter private data structure. 5256 * Fields are initialized based on PCI device information and 5257 * OS network device settings (MTU size). 5258 **/ 5259 static int ixgbe_sw_init(struct ixgbe_adapter *adapter) 5260 { 5261 struct ixgbe_hw *hw = &adapter->hw; 5262 struct pci_dev *pdev = adapter->pdev; 5263 unsigned int rss, fdir; 5264 u32 fwsm; 5265 #ifdef CONFIG_IXGBE_DCB 5266 int j; 5267 struct tc_configuration *tc; 5268 #endif 5269 5270 /* PCI config space info */ 5271 5272 hw->vendor_id = pdev->vendor; 5273 hw->device_id = pdev->device; 5274 hw->revision_id = pdev->revision; 5275 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5276 hw->subsystem_device_id = pdev->subsystem_device; 5277 5278 /* Set common capability flags and settings */ 5279 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 5280 adapter->ring_feature[RING_F_RSS].limit = rss; 5281 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 5282 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 5283 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 5284 adapter->atr_sample_rate = 20; 5285 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 5286 adapter->ring_feature[RING_F_FDIR].limit = fdir; 5287 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 5288 #ifdef CONFIG_IXGBE_DCA 5289 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 5290 #endif 5291 #ifdef IXGBE_FCOE 5292 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 5293 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5294 #ifdef CONFIG_IXGBE_DCB 5295 /* Default traffic class to use for FCoE */ 5296 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 5297 #endif /* CONFIG_IXGBE_DCB */ 5298 #endif /* IXGBE_FCOE */ 5299 5300 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 5301 hw->mac.num_rar_entries, 5302 GFP_ATOMIC); 5303 5304 /* Set MAC specific capability flags and exceptions */ 5305 switch (hw->mac.type) { 5306 case ixgbe_mac_82598EB: 5307 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 5308 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 5309 5310 if (hw->device_id == IXGBE_DEV_ID_82598AT) 5311 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 5312 5313 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 5314 adapter->ring_feature[RING_F_FDIR].limit = 0; 5315 adapter->atr_sample_rate = 0; 5316 adapter->fdir_pballoc = 0; 5317 #ifdef IXGBE_FCOE 5318 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 5319 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 5320 #ifdef CONFIG_IXGBE_DCB 5321 adapter->fcoe.up = 0; 5322 #endif /* IXGBE_DCB */ 5323 #endif /* IXGBE_FCOE */ 5324 break; 5325 case ixgbe_mac_82599EB: 5326 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 5327 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5328 break; 5329 case ixgbe_mac_X540: 5330 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 5331 if (fwsm & IXGBE_FWSM_TS_ENABLED) 5332 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 5333 break; 5334 case ixgbe_mac_X550EM_x: 5335 case ixgbe_mac_X550: 5336 #ifdef CONFIG_IXGBE_DCA 5337 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 5338 #endif 5339 #ifdef CONFIG_IXGBE_VXLAN 5340 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 5341 #endif 5342 break; 5343 default: 5344 break; 5345 } 5346 5347 #ifdef IXGBE_FCOE 5348 /* FCoE support exists, always init the FCoE lock */ 5349 spin_lock_init(&adapter->fcoe.lock); 5350 5351 #endif 5352 /* n-tuple support exists, always init our spinlock */ 5353 spin_lock_init(&adapter->fdir_perfect_lock); 5354 5355 #ifdef CONFIG_IXGBE_DCB 5356 switch (hw->mac.type) { 5357 case ixgbe_mac_X540: 5358 case ixgbe_mac_X550: 5359 case ixgbe_mac_X550EM_x: 5360 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5361 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5362 break; 5363 default: 5364 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5365 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5366 break; 5367 } 5368 5369 /* Configure DCB traffic classes */ 5370 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5371 tc = &adapter->dcb_cfg.tc_config[j]; 5372 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5373 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5374 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5375 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5376 tc->dcb_pfc = pfc_disabled; 5377 } 5378 5379 /* Initialize default user to priority mapping, UPx->TC0 */ 5380 tc = &adapter->dcb_cfg.tc_config[0]; 5381 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5382 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5383 5384 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5385 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5386 adapter->dcb_cfg.pfc_mode_enable = false; 5387 adapter->dcb_set_bitmap = 0x00; 5388 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5389 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5390 sizeof(adapter->temp_dcb_cfg)); 5391 5392 #endif 5393 5394 /* default flow control settings */ 5395 hw->fc.requested_mode = ixgbe_fc_full; 5396 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 5397 ixgbe_pbthresh_setup(adapter); 5398 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 5399 hw->fc.send_xon = true; 5400 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 5401 5402 #ifdef CONFIG_PCI_IOV 5403 if (max_vfs > 0) 5404 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 5405 5406 /* assign number of SR-IOV VFs */ 5407 if (hw->mac.type != ixgbe_mac_82598EB) { 5408 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 5409 adapter->num_vfs = 0; 5410 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 5411 } else { 5412 adapter->num_vfs = max_vfs; 5413 } 5414 } 5415 #endif /* CONFIG_PCI_IOV */ 5416 5417 /* enable itr by default in dynamic mode */ 5418 adapter->rx_itr_setting = 1; 5419 adapter->tx_itr_setting = 1; 5420 5421 /* set default ring sizes */ 5422 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 5423 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 5424 5425 /* set default work limits */ 5426 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 5427 5428 /* initialize eeprom parameters */ 5429 if (ixgbe_init_eeprom_params_generic(hw)) { 5430 e_dev_err("EEPROM initialization failed\n"); 5431 return -EIO; 5432 } 5433 5434 /* PF holds first pool slot */ 5435 set_bit(0, &adapter->fwd_bitmask); 5436 set_bit(__IXGBE_DOWN, &adapter->state); 5437 5438 return 0; 5439 } 5440 5441 /** 5442 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 5443 * @tx_ring: tx descriptor ring (for a specific queue) to setup 5444 * 5445 * Return 0 on success, negative on failure 5446 **/ 5447 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 5448 { 5449 struct device *dev = tx_ring->dev; 5450 int orig_node = dev_to_node(dev); 5451 int ring_node = -1; 5452 int size; 5453 5454 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 5455 5456 if (tx_ring->q_vector) 5457 ring_node = tx_ring->q_vector->numa_node; 5458 5459 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); 5460 if (!tx_ring->tx_buffer_info) 5461 tx_ring->tx_buffer_info = vzalloc(size); 5462 if (!tx_ring->tx_buffer_info) 5463 goto err; 5464 5465 u64_stats_init(&tx_ring->syncp); 5466 5467 /* round up to nearest 4K */ 5468 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 5469 tx_ring->size = ALIGN(tx_ring->size, 4096); 5470 5471 set_dev_node(dev, ring_node); 5472 tx_ring->desc = dma_alloc_coherent(dev, 5473 tx_ring->size, 5474 &tx_ring->dma, 5475 GFP_KERNEL); 5476 set_dev_node(dev, orig_node); 5477 if (!tx_ring->desc) 5478 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 5479 &tx_ring->dma, GFP_KERNEL); 5480 if (!tx_ring->desc) 5481 goto err; 5482 5483 tx_ring->next_to_use = 0; 5484 tx_ring->next_to_clean = 0; 5485 return 0; 5486 5487 err: 5488 vfree(tx_ring->tx_buffer_info); 5489 tx_ring->tx_buffer_info = NULL; 5490 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 5491 return -ENOMEM; 5492 } 5493 5494 /** 5495 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 5496 * @adapter: board private structure 5497 * 5498 * If this function returns with an error, then it's possible one or 5499 * more of the rings is populated (while the rest are not). It is the 5500 * callers duty to clean those orphaned rings. 5501 * 5502 * Return 0 on success, negative on failure 5503 **/ 5504 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 5505 { 5506 int i, err = 0; 5507 5508 for (i = 0; i < adapter->num_tx_queues; i++) { 5509 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 5510 if (!err) 5511 continue; 5512 5513 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 5514 goto err_setup_tx; 5515 } 5516 5517 return 0; 5518 err_setup_tx: 5519 /* rewind the index freeing the rings as we go */ 5520 while (i--) 5521 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5522 return err; 5523 } 5524 5525 /** 5526 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 5527 * @rx_ring: rx descriptor ring (for a specific queue) to setup 5528 * 5529 * Returns 0 on success, negative on failure 5530 **/ 5531 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) 5532 { 5533 struct device *dev = rx_ring->dev; 5534 int orig_node = dev_to_node(dev); 5535 int ring_node = -1; 5536 int size; 5537 5538 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 5539 5540 if (rx_ring->q_vector) 5541 ring_node = rx_ring->q_vector->numa_node; 5542 5543 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); 5544 if (!rx_ring->rx_buffer_info) 5545 rx_ring->rx_buffer_info = vzalloc(size); 5546 if (!rx_ring->rx_buffer_info) 5547 goto err; 5548 5549 u64_stats_init(&rx_ring->syncp); 5550 5551 /* Round up to nearest 4K */ 5552 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 5553 rx_ring->size = ALIGN(rx_ring->size, 4096); 5554 5555 set_dev_node(dev, ring_node); 5556 rx_ring->desc = dma_alloc_coherent(dev, 5557 rx_ring->size, 5558 &rx_ring->dma, 5559 GFP_KERNEL); 5560 set_dev_node(dev, orig_node); 5561 if (!rx_ring->desc) 5562 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 5563 &rx_ring->dma, GFP_KERNEL); 5564 if (!rx_ring->desc) 5565 goto err; 5566 5567 rx_ring->next_to_clean = 0; 5568 rx_ring->next_to_use = 0; 5569 5570 return 0; 5571 err: 5572 vfree(rx_ring->rx_buffer_info); 5573 rx_ring->rx_buffer_info = NULL; 5574 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 5575 return -ENOMEM; 5576 } 5577 5578 /** 5579 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 5580 * @adapter: board private structure 5581 * 5582 * If this function returns with an error, then it's possible one or 5583 * more of the rings is populated (while the rest are not). It is the 5584 * callers duty to clean those orphaned rings. 5585 * 5586 * Return 0 on success, negative on failure 5587 **/ 5588 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 5589 { 5590 int i, err = 0; 5591 5592 for (i = 0; i < adapter->num_rx_queues; i++) { 5593 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); 5594 if (!err) 5595 continue; 5596 5597 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 5598 goto err_setup_rx; 5599 } 5600 5601 #ifdef IXGBE_FCOE 5602 err = ixgbe_setup_fcoe_ddp_resources(adapter); 5603 if (!err) 5604 #endif 5605 return 0; 5606 err_setup_rx: 5607 /* rewind the index freeing the rings as we go */ 5608 while (i--) 5609 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5610 return err; 5611 } 5612 5613 /** 5614 * ixgbe_free_tx_resources - Free Tx Resources per Queue 5615 * @tx_ring: Tx descriptor ring for a specific queue 5616 * 5617 * Free all transmit software resources 5618 **/ 5619 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 5620 { 5621 ixgbe_clean_tx_ring(tx_ring); 5622 5623 vfree(tx_ring->tx_buffer_info); 5624 tx_ring->tx_buffer_info = NULL; 5625 5626 /* if not set, then don't free */ 5627 if (!tx_ring->desc) 5628 return; 5629 5630 dma_free_coherent(tx_ring->dev, tx_ring->size, 5631 tx_ring->desc, tx_ring->dma); 5632 5633 tx_ring->desc = NULL; 5634 } 5635 5636 /** 5637 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 5638 * @adapter: board private structure 5639 * 5640 * Free all transmit software resources 5641 **/ 5642 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 5643 { 5644 int i; 5645 5646 for (i = 0; i < adapter->num_tx_queues; i++) 5647 if (adapter->tx_ring[i]->desc) 5648 ixgbe_free_tx_resources(adapter->tx_ring[i]); 5649 } 5650 5651 /** 5652 * ixgbe_free_rx_resources - Free Rx Resources 5653 * @rx_ring: ring to clean the resources from 5654 * 5655 * Free all receive software resources 5656 **/ 5657 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 5658 { 5659 ixgbe_clean_rx_ring(rx_ring); 5660 5661 vfree(rx_ring->rx_buffer_info); 5662 rx_ring->rx_buffer_info = NULL; 5663 5664 /* if not set, then don't free */ 5665 if (!rx_ring->desc) 5666 return; 5667 5668 dma_free_coherent(rx_ring->dev, rx_ring->size, 5669 rx_ring->desc, rx_ring->dma); 5670 5671 rx_ring->desc = NULL; 5672 } 5673 5674 /** 5675 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 5676 * @adapter: board private structure 5677 * 5678 * Free all receive software resources 5679 **/ 5680 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 5681 { 5682 int i; 5683 5684 #ifdef IXGBE_FCOE 5685 ixgbe_free_fcoe_ddp_resources(adapter); 5686 5687 #endif 5688 for (i = 0; i < adapter->num_rx_queues; i++) 5689 if (adapter->rx_ring[i]->desc) 5690 ixgbe_free_rx_resources(adapter->rx_ring[i]); 5691 } 5692 5693 /** 5694 * ixgbe_change_mtu - Change the Maximum Transfer Unit 5695 * @netdev: network interface device structure 5696 * @new_mtu: new value for maximum frame size 5697 * 5698 * Returns 0 on success, negative on failure 5699 **/ 5700 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 5701 { 5702 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5703 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 5704 5705 /* MTU < 68 is an error and causes problems on some kernels */ 5706 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) 5707 return -EINVAL; 5708 5709 /* 5710 * For 82599EB we cannot allow legacy VFs to enable their receive 5711 * paths when MTU greater than 1500 is configured. So display a 5712 * warning that legacy VFs will be disabled. 5713 */ 5714 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 5715 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 5716 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 5717 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 5718 5719 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 5720 5721 /* must set new MTU before calling down or up */ 5722 netdev->mtu = new_mtu; 5723 5724 if (netif_running(netdev)) 5725 ixgbe_reinit_locked(adapter); 5726 5727 return 0; 5728 } 5729 5730 /** 5731 * ixgbe_open - Called when a network interface is made active 5732 * @netdev: network interface device structure 5733 * 5734 * Returns 0 on success, negative value on failure 5735 * 5736 * The open entry point is called when a network interface is made 5737 * active by the system (IFF_UP). At this point all resources needed 5738 * for transmit and receive operations are allocated, the interrupt 5739 * handler is registered with the OS, the watchdog timer is started, 5740 * and the stack is notified that the interface is ready. 5741 **/ 5742 static int ixgbe_open(struct net_device *netdev) 5743 { 5744 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5745 struct ixgbe_hw *hw = &adapter->hw; 5746 int err, queues; 5747 5748 /* disallow open during test */ 5749 if (test_bit(__IXGBE_TESTING, &adapter->state)) 5750 return -EBUSY; 5751 5752 netif_carrier_off(netdev); 5753 5754 /* allocate transmit descriptors */ 5755 err = ixgbe_setup_all_tx_resources(adapter); 5756 if (err) 5757 goto err_setup_tx; 5758 5759 /* allocate receive descriptors */ 5760 err = ixgbe_setup_all_rx_resources(adapter); 5761 if (err) 5762 goto err_setup_rx; 5763 5764 ixgbe_configure(adapter); 5765 5766 err = ixgbe_request_irq(adapter); 5767 if (err) 5768 goto err_req_irq; 5769 5770 /* Notify the stack of the actual queue counts. */ 5771 if (adapter->num_rx_pools > 1) 5772 queues = adapter->num_rx_queues_per_pool; 5773 else 5774 queues = adapter->num_tx_queues; 5775 5776 err = netif_set_real_num_tx_queues(netdev, queues); 5777 if (err) 5778 goto err_set_queues; 5779 5780 if (adapter->num_rx_pools > 1 && 5781 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 5782 queues = IXGBE_MAX_L2A_QUEUES; 5783 else 5784 queues = adapter->num_rx_queues; 5785 err = netif_set_real_num_rx_queues(netdev, queues); 5786 if (err) 5787 goto err_set_queues; 5788 5789 ixgbe_ptp_init(adapter); 5790 5791 ixgbe_up_complete(adapter); 5792 5793 ixgbe_clear_vxlan_port(adapter); 5794 #ifdef CONFIG_IXGBE_VXLAN 5795 vxlan_get_rx_port(netdev); 5796 #endif 5797 5798 return 0; 5799 5800 err_set_queues: 5801 ixgbe_free_irq(adapter); 5802 err_req_irq: 5803 ixgbe_free_all_rx_resources(adapter); 5804 if (hw->phy.ops.set_phy_power && !adapter->wol) 5805 hw->phy.ops.set_phy_power(&adapter->hw, false); 5806 err_setup_rx: 5807 ixgbe_free_all_tx_resources(adapter); 5808 err_setup_tx: 5809 ixgbe_reset(adapter); 5810 5811 return err; 5812 } 5813 5814 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 5815 { 5816 ixgbe_ptp_suspend(adapter); 5817 5818 if (adapter->hw.phy.ops.enter_lplu) { 5819 adapter->hw.phy.reset_disable = true; 5820 ixgbe_down(adapter); 5821 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 5822 adapter->hw.phy.reset_disable = false; 5823 } else { 5824 ixgbe_down(adapter); 5825 } 5826 5827 ixgbe_free_irq(adapter); 5828 5829 ixgbe_free_all_tx_resources(adapter); 5830 ixgbe_free_all_rx_resources(adapter); 5831 } 5832 5833 /** 5834 * ixgbe_close - Disables a network interface 5835 * @netdev: network interface device structure 5836 * 5837 * Returns 0, this is not allowed to fail 5838 * 5839 * The close entry point is called when an interface is de-activated 5840 * by the OS. The hardware is still under the drivers control, but 5841 * needs to be disabled. A global MAC reset is issued to stop the 5842 * hardware, and all transmit and receive resources are freed. 5843 **/ 5844 static int ixgbe_close(struct net_device *netdev) 5845 { 5846 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5847 5848 ixgbe_ptp_stop(adapter); 5849 5850 ixgbe_close_suspend(adapter); 5851 5852 ixgbe_fdir_filter_exit(adapter); 5853 5854 ixgbe_release_hw_control(adapter); 5855 5856 return 0; 5857 } 5858 5859 #ifdef CONFIG_PM 5860 static int ixgbe_resume(struct pci_dev *pdev) 5861 { 5862 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5863 struct net_device *netdev = adapter->netdev; 5864 u32 err; 5865 5866 adapter->hw.hw_addr = adapter->io_addr; 5867 pci_set_power_state(pdev, PCI_D0); 5868 pci_restore_state(pdev); 5869 /* 5870 * pci_restore_state clears dev->state_saved so call 5871 * pci_save_state to restore it. 5872 */ 5873 pci_save_state(pdev); 5874 5875 err = pci_enable_device_mem(pdev); 5876 if (err) { 5877 e_dev_err("Cannot enable PCI device from suspend\n"); 5878 return err; 5879 } 5880 smp_mb__before_atomic(); 5881 clear_bit(__IXGBE_DISABLED, &adapter->state); 5882 pci_set_master(pdev); 5883 5884 pci_wake_from_d3(pdev, false); 5885 5886 ixgbe_reset(adapter); 5887 5888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 5889 5890 rtnl_lock(); 5891 err = ixgbe_init_interrupt_scheme(adapter); 5892 if (!err && netif_running(netdev)) 5893 err = ixgbe_open(netdev); 5894 5895 rtnl_unlock(); 5896 5897 if (err) 5898 return err; 5899 5900 netif_device_attach(netdev); 5901 5902 return 0; 5903 } 5904 #endif /* CONFIG_PM */ 5905 5906 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 5907 { 5908 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 5909 struct net_device *netdev = adapter->netdev; 5910 struct ixgbe_hw *hw = &adapter->hw; 5911 u32 ctrl, fctrl; 5912 u32 wufc = adapter->wol; 5913 #ifdef CONFIG_PM 5914 int retval = 0; 5915 #endif 5916 5917 netif_device_detach(netdev); 5918 5919 rtnl_lock(); 5920 if (netif_running(netdev)) 5921 ixgbe_close_suspend(adapter); 5922 rtnl_unlock(); 5923 5924 ixgbe_clear_interrupt_scheme(adapter); 5925 5926 #ifdef CONFIG_PM 5927 retval = pci_save_state(pdev); 5928 if (retval) 5929 return retval; 5930 5931 #endif 5932 if (hw->mac.ops.stop_link_on_d3) 5933 hw->mac.ops.stop_link_on_d3(hw); 5934 5935 if (wufc) { 5936 ixgbe_set_rx_mode(netdev); 5937 5938 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 5939 if (hw->mac.ops.enable_tx_laser) 5940 hw->mac.ops.enable_tx_laser(hw); 5941 5942 /* turn on all-multi mode if wake on multicast is enabled */ 5943 if (wufc & IXGBE_WUFC_MC) { 5944 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5945 fctrl |= IXGBE_FCTRL_MPE; 5946 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5947 } 5948 5949 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 5950 ctrl |= IXGBE_CTRL_GIO_DIS; 5951 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 5952 5953 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 5954 } else { 5955 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 5956 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 5957 } 5958 5959 switch (hw->mac.type) { 5960 case ixgbe_mac_82598EB: 5961 pci_wake_from_d3(pdev, false); 5962 break; 5963 case ixgbe_mac_82599EB: 5964 case ixgbe_mac_X540: 5965 case ixgbe_mac_X550: 5966 case ixgbe_mac_X550EM_x: 5967 pci_wake_from_d3(pdev, !!wufc); 5968 break; 5969 default: 5970 break; 5971 } 5972 5973 *enable_wake = !!wufc; 5974 if (hw->phy.ops.set_phy_power && !*enable_wake) 5975 hw->phy.ops.set_phy_power(hw, false); 5976 5977 ixgbe_release_hw_control(adapter); 5978 5979 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 5980 pci_disable_device(pdev); 5981 5982 return 0; 5983 } 5984 5985 #ifdef CONFIG_PM 5986 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 5987 { 5988 int retval; 5989 bool wake; 5990 5991 retval = __ixgbe_shutdown(pdev, &wake); 5992 if (retval) 5993 return retval; 5994 5995 if (wake) { 5996 pci_prepare_to_sleep(pdev); 5997 } else { 5998 pci_wake_from_d3(pdev, false); 5999 pci_set_power_state(pdev, PCI_D3hot); 6000 } 6001 6002 return 0; 6003 } 6004 #endif /* CONFIG_PM */ 6005 6006 static void ixgbe_shutdown(struct pci_dev *pdev) 6007 { 6008 bool wake; 6009 6010 __ixgbe_shutdown(pdev, &wake); 6011 6012 if (system_state == SYSTEM_POWER_OFF) { 6013 pci_wake_from_d3(pdev, wake); 6014 pci_set_power_state(pdev, PCI_D3hot); 6015 } 6016 } 6017 6018 /** 6019 * ixgbe_update_stats - Update the board statistics counters. 6020 * @adapter: board private structure 6021 **/ 6022 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6023 { 6024 struct net_device *netdev = adapter->netdev; 6025 struct ixgbe_hw *hw = &adapter->hw; 6026 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6027 u64 total_mpc = 0; 6028 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6029 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6030 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6031 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6032 6033 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6034 test_bit(__IXGBE_RESETTING, &adapter->state)) 6035 return; 6036 6037 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6038 u64 rsc_count = 0; 6039 u64 rsc_flush = 0; 6040 for (i = 0; i < adapter->num_rx_queues; i++) { 6041 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6042 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6043 } 6044 adapter->rsc_total_count = rsc_count; 6045 adapter->rsc_total_flush = rsc_flush; 6046 } 6047 6048 for (i = 0; i < adapter->num_rx_queues; i++) { 6049 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6050 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6051 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6052 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6053 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6054 bytes += rx_ring->stats.bytes; 6055 packets += rx_ring->stats.packets; 6056 } 6057 adapter->non_eop_descs = non_eop_descs; 6058 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6059 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6060 adapter->hw_csum_rx_error = hw_csum_rx_error; 6061 netdev->stats.rx_bytes = bytes; 6062 netdev->stats.rx_packets = packets; 6063 6064 bytes = 0; 6065 packets = 0; 6066 /* gather some stats to the adapter struct that are per queue */ 6067 for (i = 0; i < adapter->num_tx_queues; i++) { 6068 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6069 restart_queue += tx_ring->tx_stats.restart_queue; 6070 tx_busy += tx_ring->tx_stats.tx_busy; 6071 bytes += tx_ring->stats.bytes; 6072 packets += tx_ring->stats.packets; 6073 } 6074 adapter->restart_queue = restart_queue; 6075 adapter->tx_busy = tx_busy; 6076 netdev->stats.tx_bytes = bytes; 6077 netdev->stats.tx_packets = packets; 6078 6079 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6080 6081 /* 8 register reads */ 6082 for (i = 0; i < 8; i++) { 6083 /* for packet buffers not used, the register should read 0 */ 6084 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6085 missed_rx += mpc; 6086 hwstats->mpc[i] += mpc; 6087 total_mpc += hwstats->mpc[i]; 6088 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6089 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6090 switch (hw->mac.type) { 6091 case ixgbe_mac_82598EB: 6092 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6093 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6094 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6095 hwstats->pxonrxc[i] += 6096 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6097 break; 6098 case ixgbe_mac_82599EB: 6099 case ixgbe_mac_X540: 6100 case ixgbe_mac_X550: 6101 case ixgbe_mac_X550EM_x: 6102 hwstats->pxonrxc[i] += 6103 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6104 break; 6105 default: 6106 break; 6107 } 6108 } 6109 6110 /*16 register reads */ 6111 for (i = 0; i < 16; i++) { 6112 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6113 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6114 if ((hw->mac.type == ixgbe_mac_82599EB) || 6115 (hw->mac.type == ixgbe_mac_X540) || 6116 (hw->mac.type == ixgbe_mac_X550) || 6117 (hw->mac.type == ixgbe_mac_X550EM_x)) { 6118 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6119 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6120 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6121 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6122 } 6123 } 6124 6125 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6126 /* work around hardware counting issue */ 6127 hwstats->gprc -= missed_rx; 6128 6129 ixgbe_update_xoff_received(adapter); 6130 6131 /* 82598 hardware only has a 32 bit counter in the high register */ 6132 switch (hw->mac.type) { 6133 case ixgbe_mac_82598EB: 6134 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6135 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6136 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6137 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6138 break; 6139 case ixgbe_mac_X540: 6140 case ixgbe_mac_X550: 6141 case ixgbe_mac_X550EM_x: 6142 /* OS2BMC stats are X540 and later */ 6143 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6144 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6145 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6146 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6147 case ixgbe_mac_82599EB: 6148 for (i = 0; i < 16; i++) 6149 adapter->hw_rx_no_dma_resources += 6150 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6151 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6152 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6153 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6154 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6155 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6156 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6157 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6158 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6159 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6160 #ifdef IXGBE_FCOE 6161 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6162 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6163 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6164 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6165 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6166 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6167 /* Add up per cpu counters for total ddp aloc fail */ 6168 if (adapter->fcoe.ddp_pool) { 6169 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6170 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6171 unsigned int cpu; 6172 u64 noddp = 0, noddp_ext_buff = 0; 6173 for_each_possible_cpu(cpu) { 6174 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6175 noddp += ddp_pool->noddp; 6176 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6177 } 6178 hwstats->fcoe_noddp = noddp; 6179 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6180 } 6181 #endif /* IXGBE_FCOE */ 6182 break; 6183 default: 6184 break; 6185 } 6186 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6187 hwstats->bprc += bprc; 6188 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6189 if (hw->mac.type == ixgbe_mac_82598EB) 6190 hwstats->mprc -= bprc; 6191 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6192 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6193 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6194 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6195 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6196 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6197 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6198 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6199 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6200 hwstats->lxontxc += lxon; 6201 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6202 hwstats->lxofftxc += lxoff; 6203 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6204 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6205 /* 6206 * 82598 errata - tx of flow control packets is included in tx counters 6207 */ 6208 xon_off_tot = lxon + lxoff; 6209 hwstats->gptc -= xon_off_tot; 6210 hwstats->mptc -= xon_off_tot; 6211 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6212 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6213 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6214 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6215 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6216 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6217 hwstats->ptc64 -= xon_off_tot; 6218 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6219 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6220 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6221 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6222 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6223 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6224 6225 /* Fill out the OS statistics structure */ 6226 netdev->stats.multicast = hwstats->mprc; 6227 6228 /* Rx Errors */ 6229 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6230 netdev->stats.rx_dropped = 0; 6231 netdev->stats.rx_length_errors = hwstats->rlec; 6232 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6233 netdev->stats.rx_missed_errors = total_mpc; 6234 } 6235 6236 /** 6237 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6238 * @adapter: pointer to the device adapter structure 6239 **/ 6240 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6241 { 6242 struct ixgbe_hw *hw = &adapter->hw; 6243 int i; 6244 6245 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6246 return; 6247 6248 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6249 6250 /* if interface is down do nothing */ 6251 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6252 return; 6253 6254 /* do nothing if we are not using signature filters */ 6255 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6256 return; 6257 6258 adapter->fdir_overflow++; 6259 6260 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 6261 for (i = 0; i < adapter->num_tx_queues; i++) 6262 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 6263 &(adapter->tx_ring[i]->state)); 6264 /* re-enable flow director interrupts */ 6265 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 6266 } else { 6267 e_err(probe, "failed to finish FDIR re-initialization, " 6268 "ignored adding FDIR ATR filters\n"); 6269 } 6270 } 6271 6272 /** 6273 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 6274 * @adapter: pointer to the device adapter structure 6275 * 6276 * This function serves two purposes. First it strobes the interrupt lines 6277 * in order to make certain interrupts are occurring. Secondly it sets the 6278 * bits needed to check for TX hangs. As a result we should immediately 6279 * determine if a hang has occurred. 6280 */ 6281 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 6282 { 6283 struct ixgbe_hw *hw = &adapter->hw; 6284 u64 eics = 0; 6285 int i; 6286 6287 /* If we're down, removing or resetting, just bail */ 6288 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6289 test_bit(__IXGBE_REMOVING, &adapter->state) || 6290 test_bit(__IXGBE_RESETTING, &adapter->state)) 6291 return; 6292 6293 /* Force detection of hung controller */ 6294 if (netif_carrier_ok(adapter->netdev)) { 6295 for (i = 0; i < adapter->num_tx_queues; i++) 6296 set_check_for_tx_hang(adapter->tx_ring[i]); 6297 } 6298 6299 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 6300 /* 6301 * for legacy and MSI interrupts don't set any bits 6302 * that are enabled for EIAM, because this operation 6303 * would set *both* EIMS and EICS for any bit in EIAM 6304 */ 6305 IXGBE_WRITE_REG(hw, IXGBE_EICS, 6306 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 6307 } else { 6308 /* get one bit for every active tx/rx interrupt vector */ 6309 for (i = 0; i < adapter->num_q_vectors; i++) { 6310 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 6311 if (qv->rx.ring || qv->tx.ring) 6312 eics |= ((u64)1 << i); 6313 } 6314 } 6315 6316 /* Cause software interrupt to ensure rings are cleaned */ 6317 ixgbe_irq_rearm_queues(adapter, eics); 6318 } 6319 6320 /** 6321 * ixgbe_watchdog_update_link - update the link status 6322 * @adapter: pointer to the device adapter structure 6323 * @link_speed: pointer to a u32 to store the link_speed 6324 **/ 6325 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 6326 { 6327 struct ixgbe_hw *hw = &adapter->hw; 6328 u32 link_speed = adapter->link_speed; 6329 bool link_up = adapter->link_up; 6330 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 6331 6332 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 6333 return; 6334 6335 if (hw->mac.ops.check_link) { 6336 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 6337 } else { 6338 /* always assume link is up, if no check link function */ 6339 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 6340 link_up = true; 6341 } 6342 6343 if (adapter->ixgbe_ieee_pfc) 6344 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 6345 6346 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 6347 hw->mac.ops.fc_enable(hw); 6348 ixgbe_set_rx_drop_en(adapter); 6349 } 6350 6351 if (link_up || 6352 time_after(jiffies, (adapter->link_check_timeout + 6353 IXGBE_TRY_LINK_TIMEOUT))) { 6354 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6355 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 6356 IXGBE_WRITE_FLUSH(hw); 6357 } 6358 6359 adapter->link_up = link_up; 6360 adapter->link_speed = link_speed; 6361 } 6362 6363 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 6364 { 6365 #ifdef CONFIG_IXGBE_DCB 6366 struct net_device *netdev = adapter->netdev; 6367 struct dcb_app app = { 6368 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 6369 .protocol = 0, 6370 }; 6371 u8 up = 0; 6372 6373 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 6374 up = dcb_ieee_getapp_mask(netdev, &app); 6375 6376 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 6377 #endif 6378 } 6379 6380 /** 6381 * ixgbe_watchdog_link_is_up - update netif_carrier status and 6382 * print link up message 6383 * @adapter: pointer to the device adapter structure 6384 **/ 6385 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 6386 { 6387 struct net_device *netdev = adapter->netdev; 6388 struct ixgbe_hw *hw = &adapter->hw; 6389 struct net_device *upper; 6390 struct list_head *iter; 6391 u32 link_speed = adapter->link_speed; 6392 const char *speed_str; 6393 bool flow_rx, flow_tx; 6394 6395 /* only continue if link was previously down */ 6396 if (netif_carrier_ok(netdev)) 6397 return; 6398 6399 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 6400 6401 switch (hw->mac.type) { 6402 case ixgbe_mac_82598EB: { 6403 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6404 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 6405 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 6406 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 6407 } 6408 break; 6409 case ixgbe_mac_X540: 6410 case ixgbe_mac_X550: 6411 case ixgbe_mac_X550EM_x: 6412 case ixgbe_mac_82599EB: { 6413 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 6414 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 6415 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 6416 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 6417 } 6418 break; 6419 default: 6420 flow_tx = false; 6421 flow_rx = false; 6422 break; 6423 } 6424 6425 adapter->last_rx_ptp_check = jiffies; 6426 6427 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6428 ixgbe_ptp_start_cyclecounter(adapter); 6429 6430 switch (link_speed) { 6431 case IXGBE_LINK_SPEED_10GB_FULL: 6432 speed_str = "10 Gbps"; 6433 break; 6434 case IXGBE_LINK_SPEED_2_5GB_FULL: 6435 speed_str = "2.5 Gbps"; 6436 break; 6437 case IXGBE_LINK_SPEED_1GB_FULL: 6438 speed_str = "1 Gbps"; 6439 break; 6440 case IXGBE_LINK_SPEED_100_FULL: 6441 speed_str = "100 Mbps"; 6442 break; 6443 default: 6444 speed_str = "unknown speed"; 6445 break; 6446 } 6447 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 6448 ((flow_rx && flow_tx) ? "RX/TX" : 6449 (flow_rx ? "RX" : 6450 (flow_tx ? "TX" : "None")))); 6451 6452 netif_carrier_on(netdev); 6453 ixgbe_check_vf_rate_limit(adapter); 6454 6455 /* enable transmits */ 6456 netif_tx_wake_all_queues(adapter->netdev); 6457 6458 /* enable any upper devices */ 6459 rtnl_lock(); 6460 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { 6461 if (netif_is_macvlan(upper)) { 6462 struct macvlan_dev *vlan = netdev_priv(upper); 6463 6464 if (vlan->fwd_priv) 6465 netif_tx_wake_all_queues(upper); 6466 } 6467 } 6468 rtnl_unlock(); 6469 6470 /* update the default user priority for VFs */ 6471 ixgbe_update_default_up(adapter); 6472 6473 /* ping all the active vfs to let them know link has changed */ 6474 ixgbe_ping_all_vfs(adapter); 6475 } 6476 6477 /** 6478 * ixgbe_watchdog_link_is_down - update netif_carrier status and 6479 * print link down message 6480 * @adapter: pointer to the adapter structure 6481 **/ 6482 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 6483 { 6484 struct net_device *netdev = adapter->netdev; 6485 struct ixgbe_hw *hw = &adapter->hw; 6486 6487 adapter->link_up = false; 6488 adapter->link_speed = 0; 6489 6490 /* only continue if link was up previously */ 6491 if (!netif_carrier_ok(netdev)) 6492 return; 6493 6494 /* poll for SFP+ cable when link is down */ 6495 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 6496 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 6497 6498 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6499 ixgbe_ptp_start_cyclecounter(adapter); 6500 6501 e_info(drv, "NIC Link is Down\n"); 6502 netif_carrier_off(netdev); 6503 6504 /* ping all the active vfs to let them know link has changed */ 6505 ixgbe_ping_all_vfs(adapter); 6506 } 6507 6508 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 6509 { 6510 int i; 6511 6512 for (i = 0; i < adapter->num_tx_queues; i++) { 6513 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6514 6515 if (tx_ring->next_to_use != tx_ring->next_to_clean) 6516 return true; 6517 } 6518 6519 return false; 6520 } 6521 6522 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 6523 { 6524 struct ixgbe_hw *hw = &adapter->hw; 6525 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 6526 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 6527 6528 int i, j; 6529 6530 if (!adapter->num_vfs) 6531 return false; 6532 6533 /* resetting the PF is only needed for MAC before X550 */ 6534 if (hw->mac.type >= ixgbe_mac_X550) 6535 return false; 6536 6537 for (i = 0; i < adapter->num_vfs; i++) { 6538 for (j = 0; j < q_per_pool; j++) { 6539 u32 h, t; 6540 6541 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 6542 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 6543 6544 if (h != t) 6545 return true; 6546 } 6547 } 6548 6549 return false; 6550 } 6551 6552 /** 6553 * ixgbe_watchdog_flush_tx - flush queues on link down 6554 * @adapter: pointer to the device adapter structure 6555 **/ 6556 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 6557 { 6558 if (!netif_carrier_ok(adapter->netdev)) { 6559 if (ixgbe_ring_tx_pending(adapter) || 6560 ixgbe_vf_tx_pending(adapter)) { 6561 /* We've lost link, so the controller stops DMA, 6562 * but we've got queued Tx work that's never going 6563 * to get done, so reset controller to flush Tx. 6564 * (Do the reset outside of interrupt context). 6565 */ 6566 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 6567 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; 6568 } 6569 } 6570 } 6571 6572 #ifdef CONFIG_PCI_IOV 6573 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 6574 struct pci_dev *vfdev) 6575 { 6576 if (!pci_wait_for_pending_transaction(vfdev)) 6577 e_dev_warn("Issuing VFLR with pending transactions\n"); 6578 6579 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 6580 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 6581 6582 msleep(100); 6583 } 6584 6585 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 6586 { 6587 struct ixgbe_hw *hw = &adapter->hw; 6588 struct pci_dev *pdev = adapter->pdev; 6589 struct pci_dev *vfdev; 6590 u32 gpc; 6591 int pos; 6592 unsigned short vf_id; 6593 6594 if (!(netif_carrier_ok(adapter->netdev))) 6595 return; 6596 6597 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 6598 if (gpc) /* If incrementing then no need for the check below */ 6599 return; 6600 /* Check to see if a bad DMA write target from an errant or 6601 * malicious VF has caused a PCIe error. If so then we can 6602 * issue a VFLR to the offending VF(s) and then resume without 6603 * requesting a full slot reset. 6604 */ 6605 6606 if (!pdev) 6607 return; 6608 6609 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 6610 if (!pos) 6611 return; 6612 6613 /* get the device ID for the VF */ 6614 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id); 6615 6616 /* check status reg for all VFs owned by this PF */ 6617 vfdev = pci_get_device(pdev->vendor, vf_id, NULL); 6618 while (vfdev) { 6619 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) { 6620 u16 status_reg; 6621 6622 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 6623 if (status_reg & PCI_STATUS_REC_MASTER_ABORT) 6624 /* issue VFLR */ 6625 ixgbe_issue_vf_flr(adapter, vfdev); 6626 } 6627 6628 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev); 6629 } 6630 } 6631 6632 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 6633 { 6634 u32 ssvpc; 6635 6636 /* Do not perform spoof check for 82598 or if not in IOV mode */ 6637 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 6638 adapter->num_vfs == 0) 6639 return; 6640 6641 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 6642 6643 /* 6644 * ssvpc register is cleared on read, if zero then no 6645 * spoofed packets in the last interval. 6646 */ 6647 if (!ssvpc) 6648 return; 6649 6650 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 6651 } 6652 #else 6653 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 6654 { 6655 } 6656 6657 static void 6658 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 6659 { 6660 } 6661 #endif /* CONFIG_PCI_IOV */ 6662 6663 6664 /** 6665 * ixgbe_watchdog_subtask - check and bring link up 6666 * @adapter: pointer to the device adapter structure 6667 **/ 6668 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 6669 { 6670 /* if interface is down, removing or resetting, do nothing */ 6671 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6672 test_bit(__IXGBE_REMOVING, &adapter->state) || 6673 test_bit(__IXGBE_RESETTING, &adapter->state)) 6674 return; 6675 6676 ixgbe_watchdog_update_link(adapter); 6677 6678 if (adapter->link_up) 6679 ixgbe_watchdog_link_is_up(adapter); 6680 else 6681 ixgbe_watchdog_link_is_down(adapter); 6682 6683 ixgbe_check_for_bad_vf(adapter); 6684 ixgbe_spoof_check(adapter); 6685 ixgbe_update_stats(adapter); 6686 6687 ixgbe_watchdog_flush_tx(adapter); 6688 } 6689 6690 /** 6691 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 6692 * @adapter: the ixgbe adapter structure 6693 **/ 6694 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 6695 { 6696 struct ixgbe_hw *hw = &adapter->hw; 6697 s32 err; 6698 6699 /* not searching for SFP so there is nothing to do here */ 6700 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 6701 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6702 return; 6703 6704 /* someone else is in init, wait until next service event */ 6705 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6706 return; 6707 6708 err = hw->phy.ops.identify_sfp(hw); 6709 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6710 goto sfp_out; 6711 6712 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 6713 /* If no cable is present, then we need to reset 6714 * the next time we find a good cable. */ 6715 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 6716 } 6717 6718 /* exit on error */ 6719 if (err) 6720 goto sfp_out; 6721 6722 /* exit if reset not needed */ 6723 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 6724 goto sfp_out; 6725 6726 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 6727 6728 /* 6729 * A module may be identified correctly, but the EEPROM may not have 6730 * support for that module. setup_sfp() will fail in that case, so 6731 * we should not allow that module to load. 6732 */ 6733 if (hw->mac.type == ixgbe_mac_82598EB) 6734 err = hw->phy.ops.reset(hw); 6735 else 6736 err = hw->mac.ops.setup_sfp(hw); 6737 6738 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 6739 goto sfp_out; 6740 6741 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 6742 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 6743 6744 sfp_out: 6745 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6746 6747 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 6748 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 6749 e_dev_err("failed to initialize because an unsupported " 6750 "SFP+ module type was detected.\n"); 6751 e_dev_err("Reload the driver after installing a " 6752 "supported module.\n"); 6753 unregister_netdev(adapter->netdev); 6754 } 6755 } 6756 6757 /** 6758 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 6759 * @adapter: the ixgbe adapter structure 6760 **/ 6761 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 6762 { 6763 struct ixgbe_hw *hw = &adapter->hw; 6764 u32 speed; 6765 bool autoneg = false; 6766 6767 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 6768 return; 6769 6770 /* someone else is in init, wait until next service event */ 6771 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6772 return; 6773 6774 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6775 6776 speed = hw->phy.autoneg_advertised; 6777 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 6778 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 6779 6780 /* setup the highest link when no autoneg */ 6781 if (!autoneg) { 6782 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 6783 speed = IXGBE_LINK_SPEED_10GB_FULL; 6784 } 6785 } 6786 6787 if (hw->mac.ops.setup_link) 6788 hw->mac.ops.setup_link(hw, speed, true); 6789 6790 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6791 adapter->link_check_timeout = jiffies; 6792 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6793 } 6794 6795 /** 6796 * ixgbe_service_timer - Timer Call-back 6797 * @data: pointer to adapter cast into an unsigned long 6798 **/ 6799 static void ixgbe_service_timer(unsigned long data) 6800 { 6801 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 6802 unsigned long next_event_offset; 6803 6804 /* poll faster when waiting for link */ 6805 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 6806 next_event_offset = HZ / 10; 6807 else 6808 next_event_offset = HZ * 2; 6809 6810 /* Reset the timer */ 6811 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 6812 6813 ixgbe_service_event_schedule(adapter); 6814 } 6815 6816 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 6817 { 6818 struct ixgbe_hw *hw = &adapter->hw; 6819 u32 status; 6820 6821 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 6822 return; 6823 6824 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 6825 6826 if (!hw->phy.ops.handle_lasi) 6827 return; 6828 6829 status = hw->phy.ops.handle_lasi(&adapter->hw); 6830 if (status != IXGBE_ERR_OVERTEMP) 6831 return; 6832 6833 e_crit(drv, "%s\n", ixgbe_overheat_msg); 6834 } 6835 6836 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 6837 { 6838 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) 6839 return; 6840 6841 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; 6842 6843 /* If we're already down, removing or resetting, just bail */ 6844 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6845 test_bit(__IXGBE_REMOVING, &adapter->state) || 6846 test_bit(__IXGBE_RESETTING, &adapter->state)) 6847 return; 6848 6849 ixgbe_dump(adapter); 6850 netdev_err(adapter->netdev, "Reset adapter\n"); 6851 adapter->tx_timeout_count++; 6852 6853 rtnl_lock(); 6854 ixgbe_reinit_locked(adapter); 6855 rtnl_unlock(); 6856 } 6857 6858 /** 6859 * ixgbe_service_task - manages and runs subtasks 6860 * @work: pointer to work_struct containing our data 6861 **/ 6862 static void ixgbe_service_task(struct work_struct *work) 6863 { 6864 struct ixgbe_adapter *adapter = container_of(work, 6865 struct ixgbe_adapter, 6866 service_task); 6867 if (ixgbe_removed(adapter->hw.hw_addr)) { 6868 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 6869 rtnl_lock(); 6870 ixgbe_down(adapter); 6871 rtnl_unlock(); 6872 } 6873 ixgbe_service_event_complete(adapter); 6874 return; 6875 } 6876 #ifdef CONFIG_IXGBE_VXLAN 6877 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) { 6878 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED; 6879 vxlan_get_rx_port(adapter->netdev); 6880 } 6881 #endif /* CONFIG_IXGBE_VXLAN */ 6882 ixgbe_reset_subtask(adapter); 6883 ixgbe_phy_interrupt_subtask(adapter); 6884 ixgbe_sfp_detection_subtask(adapter); 6885 ixgbe_sfp_link_config_subtask(adapter); 6886 ixgbe_check_overtemp_subtask(adapter); 6887 ixgbe_watchdog_subtask(adapter); 6888 ixgbe_fdir_reinit_subtask(adapter); 6889 ixgbe_check_hang_subtask(adapter); 6890 6891 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 6892 ixgbe_ptp_overflow_check(adapter); 6893 ixgbe_ptp_rx_hang(adapter); 6894 } 6895 6896 ixgbe_service_event_complete(adapter); 6897 } 6898 6899 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 6900 struct ixgbe_tx_buffer *first, 6901 u8 *hdr_len) 6902 { 6903 struct sk_buff *skb = first->skb; 6904 u32 vlan_macip_lens, type_tucmd; 6905 u32 mss_l4len_idx, l4len; 6906 int err; 6907 6908 if (skb->ip_summed != CHECKSUM_PARTIAL) 6909 return 0; 6910 6911 if (!skb_is_gso(skb)) 6912 return 0; 6913 6914 err = skb_cow_head(skb, 0); 6915 if (err < 0) 6916 return err; 6917 6918 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 6919 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 6920 6921 if (first->protocol == htons(ETH_P_IP)) { 6922 struct iphdr *iph = ip_hdr(skb); 6923 iph->tot_len = 0; 6924 iph->check = 0; 6925 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 6926 iph->daddr, 0, 6927 IPPROTO_TCP, 6928 0); 6929 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 6930 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6931 IXGBE_TX_FLAGS_CSUM | 6932 IXGBE_TX_FLAGS_IPV4; 6933 } else if (skb_is_gso_v6(skb)) { 6934 ipv6_hdr(skb)->payload_len = 0; 6935 tcp_hdr(skb)->check = 6936 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 6937 &ipv6_hdr(skb)->daddr, 6938 0, IPPROTO_TCP, 0); 6939 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 6940 IXGBE_TX_FLAGS_CSUM; 6941 } 6942 6943 /* compute header lengths */ 6944 l4len = tcp_hdrlen(skb); 6945 *hdr_len = skb_transport_offset(skb) + l4len; 6946 6947 /* update gso size and bytecount with header size */ 6948 first->gso_segs = skb_shinfo(skb)->gso_segs; 6949 first->bytecount += (first->gso_segs - 1) * *hdr_len; 6950 6951 /* mss_l4len_id: use 0 as index for TSO */ 6952 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; 6953 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 6954 6955 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 6956 vlan_macip_lens = skb_network_header_len(skb); 6957 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 6958 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 6959 6960 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 6961 mss_l4len_idx); 6962 6963 return 1; 6964 } 6965 6966 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 6967 struct ixgbe_tx_buffer *first) 6968 { 6969 struct sk_buff *skb = first->skb; 6970 u32 vlan_macip_lens = 0; 6971 u32 mss_l4len_idx = 0; 6972 u32 type_tucmd = 0; 6973 6974 if (skb->ip_summed != CHECKSUM_PARTIAL) { 6975 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && 6976 !(first->tx_flags & IXGBE_TX_FLAGS_CC)) 6977 return; 6978 vlan_macip_lens = skb_network_offset(skb) << 6979 IXGBE_ADVTXD_MACLEN_SHIFT; 6980 } else { 6981 u8 l4_hdr = 0; 6982 union { 6983 struct iphdr *ipv4; 6984 struct ipv6hdr *ipv6; 6985 u8 *raw; 6986 } network_hdr; 6987 union { 6988 struct tcphdr *tcphdr; 6989 u8 *raw; 6990 } transport_hdr; 6991 6992 if (skb->encapsulation) { 6993 network_hdr.raw = skb_inner_network_header(skb); 6994 transport_hdr.raw = skb_inner_transport_header(skb); 6995 vlan_macip_lens = skb_inner_network_offset(skb) << 6996 IXGBE_ADVTXD_MACLEN_SHIFT; 6997 } else { 6998 network_hdr.raw = skb_network_header(skb); 6999 transport_hdr.raw = skb_transport_header(skb); 7000 vlan_macip_lens = skb_network_offset(skb) << 7001 IXGBE_ADVTXD_MACLEN_SHIFT; 7002 } 7003 7004 /* use first 4 bits to determine IP version */ 7005 switch (network_hdr.ipv4->version) { 7006 case IPVERSION: 7007 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw; 7008 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7009 l4_hdr = network_hdr.ipv4->protocol; 7010 break; 7011 case 6: 7012 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw; 7013 l4_hdr = network_hdr.ipv6->nexthdr; 7014 break; 7015 default: 7016 if (unlikely(net_ratelimit())) { 7017 dev_warn(tx_ring->dev, 7018 "partial checksum but version=%d\n", 7019 network_hdr.ipv4->version); 7020 } 7021 } 7022 7023 switch (l4_hdr) { 7024 case IPPROTO_TCP: 7025 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; 7026 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 7027 IXGBE_ADVTXD_L4LEN_SHIFT; 7028 break; 7029 case IPPROTO_SCTP: 7030 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7031 mss_l4len_idx = sizeof(struct sctphdr) << 7032 IXGBE_ADVTXD_L4LEN_SHIFT; 7033 break; 7034 case IPPROTO_UDP: 7035 mss_l4len_idx = sizeof(struct udphdr) << 7036 IXGBE_ADVTXD_L4LEN_SHIFT; 7037 break; 7038 default: 7039 if (unlikely(net_ratelimit())) { 7040 dev_warn(tx_ring->dev, 7041 "partial checksum but l4 proto=%x!\n", 7042 l4_hdr); 7043 } 7044 break; 7045 } 7046 7047 /* update TX checksum flag */ 7048 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7049 } 7050 7051 /* vlan_macip_lens: MACLEN, VLAN tag */ 7052 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7053 7054 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, 7055 type_tucmd, mss_l4len_idx); 7056 } 7057 7058 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7059 ((_flag <= _result) ? \ 7060 ((u32)(_input & _flag) * (_result / _flag)) : \ 7061 ((u32)(_input & _flag) / (_flag / _result))) 7062 7063 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7064 { 7065 /* set type for advanced descriptor with frame checksum insertion */ 7066 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7067 IXGBE_ADVTXD_DCMD_DEXT | 7068 IXGBE_ADVTXD_DCMD_IFCS; 7069 7070 /* set HW vlan bit if vlan is present */ 7071 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7072 IXGBE_ADVTXD_DCMD_VLE); 7073 7074 /* set segmentation enable bits for TSO/FSO */ 7075 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7076 IXGBE_ADVTXD_DCMD_TSE); 7077 7078 /* set timestamp bit if present */ 7079 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7080 IXGBE_ADVTXD_MAC_TSTAMP); 7081 7082 /* insert frame checksum */ 7083 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7084 7085 return cmd_type; 7086 } 7087 7088 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7089 u32 tx_flags, unsigned int paylen) 7090 { 7091 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7092 7093 /* enable L4 checksum for TSO and TX checksum offload */ 7094 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7095 IXGBE_TX_FLAGS_CSUM, 7096 IXGBE_ADVTXD_POPTS_TXSM); 7097 7098 /* enble IPv4 checksum for TSO */ 7099 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7100 IXGBE_TX_FLAGS_IPV4, 7101 IXGBE_ADVTXD_POPTS_IXSM); 7102 7103 /* 7104 * Check Context must be set if Tx switch is enabled, which it 7105 * always is for case where virtual functions are running 7106 */ 7107 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7108 IXGBE_TX_FLAGS_CC, 7109 IXGBE_ADVTXD_CC); 7110 7111 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7112 } 7113 7114 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7115 { 7116 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7117 7118 /* Herbert's original patch had: 7119 * smp_mb__after_netif_stop_queue(); 7120 * but since that doesn't exist yet, just open code it. 7121 */ 7122 smp_mb(); 7123 7124 /* We need to check again in a case another CPU has just 7125 * made room available. 7126 */ 7127 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7128 return -EBUSY; 7129 7130 /* A reprieve! - use start_queue because it doesn't call schedule */ 7131 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7132 ++tx_ring->tx_stats.restart_queue; 7133 return 0; 7134 } 7135 7136 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7137 { 7138 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7139 return 0; 7140 7141 return __ixgbe_maybe_stop_tx(tx_ring, size); 7142 } 7143 7144 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7145 IXGBE_TXD_CMD_RS) 7146 7147 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7148 struct ixgbe_tx_buffer *first, 7149 const u8 hdr_len) 7150 { 7151 struct sk_buff *skb = first->skb; 7152 struct ixgbe_tx_buffer *tx_buffer; 7153 union ixgbe_adv_tx_desc *tx_desc; 7154 struct skb_frag_struct *frag; 7155 dma_addr_t dma; 7156 unsigned int data_len, size; 7157 u32 tx_flags = first->tx_flags; 7158 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7159 u16 i = tx_ring->next_to_use; 7160 7161 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7162 7163 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7164 7165 size = skb_headlen(skb); 7166 data_len = skb->data_len; 7167 7168 #ifdef IXGBE_FCOE 7169 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7170 if (data_len < sizeof(struct fcoe_crc_eof)) { 7171 size -= sizeof(struct fcoe_crc_eof) - data_len; 7172 data_len = 0; 7173 } else { 7174 data_len -= sizeof(struct fcoe_crc_eof); 7175 } 7176 } 7177 7178 #endif 7179 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7180 7181 tx_buffer = first; 7182 7183 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7184 if (dma_mapping_error(tx_ring->dev, dma)) 7185 goto dma_error; 7186 7187 /* record length, and DMA address */ 7188 dma_unmap_len_set(tx_buffer, len, size); 7189 dma_unmap_addr_set(tx_buffer, dma, dma); 7190 7191 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7192 7193 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7194 tx_desc->read.cmd_type_len = 7195 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7196 7197 i++; 7198 tx_desc++; 7199 if (i == tx_ring->count) { 7200 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7201 i = 0; 7202 } 7203 tx_desc->read.olinfo_status = 0; 7204 7205 dma += IXGBE_MAX_DATA_PER_TXD; 7206 size -= IXGBE_MAX_DATA_PER_TXD; 7207 7208 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7209 } 7210 7211 if (likely(!data_len)) 7212 break; 7213 7214 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7215 7216 i++; 7217 tx_desc++; 7218 if (i == tx_ring->count) { 7219 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7220 i = 0; 7221 } 7222 tx_desc->read.olinfo_status = 0; 7223 7224 #ifdef IXGBE_FCOE 7225 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7226 #else 7227 size = skb_frag_size(frag); 7228 #endif 7229 data_len -= size; 7230 7231 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7232 DMA_TO_DEVICE); 7233 7234 tx_buffer = &tx_ring->tx_buffer_info[i]; 7235 } 7236 7237 /* write last descriptor with RS and EOP bits */ 7238 cmd_type |= size | IXGBE_TXD_CMD; 7239 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7240 7241 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7242 7243 /* set the timestamp */ 7244 first->time_stamp = jiffies; 7245 7246 /* 7247 * Force memory writes to complete before letting h/w know there 7248 * are new descriptors to fetch. (Only applicable for weak-ordered 7249 * memory model archs, such as IA-64). 7250 * 7251 * We also need this memory barrier to make certain all of the 7252 * status bits have been updated before next_to_watch is written. 7253 */ 7254 wmb(); 7255 7256 /* set next_to_watch value indicating a packet is present */ 7257 first->next_to_watch = tx_desc; 7258 7259 i++; 7260 if (i == tx_ring->count) 7261 i = 0; 7262 7263 tx_ring->next_to_use = i; 7264 7265 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 7266 7267 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 7268 writel(i, tx_ring->tail); 7269 7270 /* we need this if more than one processor can write to our tail 7271 * at a time, it synchronizes IO on IA64/Altix systems 7272 */ 7273 mmiowb(); 7274 } 7275 7276 return; 7277 dma_error: 7278 dev_err(tx_ring->dev, "TX DMA map failed\n"); 7279 7280 /* clear dma mappings for failed tx_buffer_info map */ 7281 for (;;) { 7282 tx_buffer = &tx_ring->tx_buffer_info[i]; 7283 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 7284 if (tx_buffer == first) 7285 break; 7286 if (i == 0) 7287 i = tx_ring->count; 7288 i--; 7289 } 7290 7291 tx_ring->next_to_use = i; 7292 } 7293 7294 static void ixgbe_atr(struct ixgbe_ring *ring, 7295 struct ixgbe_tx_buffer *first) 7296 { 7297 struct ixgbe_q_vector *q_vector = ring->q_vector; 7298 union ixgbe_atr_hash_dword input = { .dword = 0 }; 7299 union ixgbe_atr_hash_dword common = { .dword = 0 }; 7300 union { 7301 unsigned char *network; 7302 struct iphdr *ipv4; 7303 struct ipv6hdr *ipv6; 7304 } hdr; 7305 struct tcphdr *th; 7306 struct sk_buff *skb; 7307 #ifdef CONFIG_IXGBE_VXLAN 7308 u8 encap = false; 7309 #endif /* CONFIG_IXGBE_VXLAN */ 7310 __be16 vlan_id; 7311 7312 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 7313 if (!q_vector) 7314 return; 7315 7316 /* do nothing if sampling is disabled */ 7317 if (!ring->atr_sample_rate) 7318 return; 7319 7320 ring->atr_count++; 7321 7322 /* snag network header to get L4 type and address */ 7323 skb = first->skb; 7324 hdr.network = skb_network_header(skb); 7325 if (skb->encapsulation) { 7326 #ifdef CONFIG_IXGBE_VXLAN 7327 struct ixgbe_adapter *adapter = q_vector->adapter; 7328 7329 if (!adapter->vxlan_port) 7330 return; 7331 if (first->protocol != htons(ETH_P_IP) || 7332 hdr.ipv4->version != IPVERSION || 7333 hdr.ipv4->protocol != IPPROTO_UDP) { 7334 return; 7335 } 7336 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port) 7337 return; 7338 encap = true; 7339 hdr.network = skb_inner_network_header(skb); 7340 th = inner_tcp_hdr(skb); 7341 #else 7342 return; 7343 #endif /* CONFIG_IXGBE_VXLAN */ 7344 } else { 7345 /* Currently only IPv4/IPv6 with TCP is supported */ 7346 if ((first->protocol != htons(ETH_P_IPV6) || 7347 hdr.ipv6->nexthdr != IPPROTO_TCP) && 7348 (first->protocol != htons(ETH_P_IP) || 7349 hdr.ipv4->protocol != IPPROTO_TCP)) 7350 return; 7351 th = tcp_hdr(skb); 7352 } 7353 7354 /* skip this packet since it is invalid or the socket is closing */ 7355 if (!th || th->fin) 7356 return; 7357 7358 /* sample on all syn packets or once every atr sample count */ 7359 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 7360 return; 7361 7362 /* reset sample count */ 7363 ring->atr_count = 0; 7364 7365 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 7366 7367 /* 7368 * src and dst are inverted, think how the receiver sees them 7369 * 7370 * The input is broken into two sections, a non-compressed section 7371 * containing vm_pool, vlan_id, and flow_type. The rest of the data 7372 * is XORed together and stored in the compressed dword. 7373 */ 7374 input.formatted.vlan_id = vlan_id; 7375 7376 /* 7377 * since src port and flex bytes occupy the same word XOR them together 7378 * and write the value to source port portion of compressed dword 7379 */ 7380 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 7381 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 7382 else 7383 common.port.src ^= th->dest ^ first->protocol; 7384 common.port.dst ^= th->source; 7385 7386 if (first->protocol == htons(ETH_P_IP)) { 7387 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 7388 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 7389 } else { 7390 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 7391 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 7392 hdr.ipv6->saddr.s6_addr32[1] ^ 7393 hdr.ipv6->saddr.s6_addr32[2] ^ 7394 hdr.ipv6->saddr.s6_addr32[3] ^ 7395 hdr.ipv6->daddr.s6_addr32[0] ^ 7396 hdr.ipv6->daddr.s6_addr32[1] ^ 7397 hdr.ipv6->daddr.s6_addr32[2] ^ 7398 hdr.ipv6->daddr.s6_addr32[3]; 7399 } 7400 7401 #ifdef CONFIG_IXGBE_VXLAN 7402 if (encap) 7403 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 7404 #endif /* CONFIG_IXGBE_VXLAN */ 7405 7406 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 7407 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 7408 input, common, ring->queue_index); 7409 } 7410 7411 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 7412 void *accel_priv, select_queue_fallback_t fallback) 7413 { 7414 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 7415 #ifdef IXGBE_FCOE 7416 struct ixgbe_adapter *adapter; 7417 struct ixgbe_ring_feature *f; 7418 int txq; 7419 #endif 7420 7421 if (fwd_adapter) 7422 return skb->queue_mapping + fwd_adapter->tx_base_queue; 7423 7424 #ifdef IXGBE_FCOE 7425 7426 /* 7427 * only execute the code below if protocol is FCoE 7428 * or FIP and we have FCoE enabled on the adapter 7429 */ 7430 switch (vlan_get_protocol(skb)) { 7431 case htons(ETH_P_FCOE): 7432 case htons(ETH_P_FIP): 7433 adapter = netdev_priv(dev); 7434 7435 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 7436 break; 7437 default: 7438 return fallback(dev, skb); 7439 } 7440 7441 f = &adapter->ring_feature[RING_F_FCOE]; 7442 7443 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 7444 smp_processor_id(); 7445 7446 while (txq >= f->indices) 7447 txq -= f->indices; 7448 7449 return txq + f->offset; 7450 #else 7451 return fallback(dev, skb); 7452 #endif 7453 } 7454 7455 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 7456 struct ixgbe_adapter *adapter, 7457 struct ixgbe_ring *tx_ring) 7458 { 7459 struct ixgbe_tx_buffer *first; 7460 int tso; 7461 u32 tx_flags = 0; 7462 unsigned short f; 7463 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 7464 __be16 protocol = skb->protocol; 7465 u8 hdr_len = 0; 7466 7467 /* 7468 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 7469 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 7470 * + 2 desc gap to keep tail from touching head, 7471 * + 1 desc for context descriptor, 7472 * otherwise try next time 7473 */ 7474 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 7475 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 7476 7477 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 7478 tx_ring->tx_stats.tx_busy++; 7479 return NETDEV_TX_BUSY; 7480 } 7481 7482 /* record the location of the first descriptor for this packet */ 7483 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 7484 first->skb = skb; 7485 first->bytecount = skb->len; 7486 first->gso_segs = 1; 7487 7488 /* if we have a HW VLAN tag being added default to the HW one */ 7489 if (skb_vlan_tag_present(skb)) { 7490 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 7491 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7492 /* else if it is a SW VLAN check the next protocol and store the tag */ 7493 } else if (protocol == htons(ETH_P_8021Q)) { 7494 struct vlan_hdr *vhdr, _vhdr; 7495 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 7496 if (!vhdr) 7497 goto out_drop; 7498 7499 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 7500 IXGBE_TX_FLAGS_VLAN_SHIFT; 7501 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 7502 } 7503 protocol = vlan_get_protocol(skb); 7504 7505 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 7506 adapter->ptp_clock && 7507 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 7508 &adapter->state)) { 7509 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 7510 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 7511 7512 /* schedule check for Tx timestamp */ 7513 adapter->ptp_tx_skb = skb_get(skb); 7514 adapter->ptp_tx_start = jiffies; 7515 schedule_work(&adapter->ptp_tx_work); 7516 } 7517 7518 skb_tx_timestamp(skb); 7519 7520 #ifdef CONFIG_PCI_IOV 7521 /* 7522 * Use the l2switch_enable flag - would be false if the DMA 7523 * Tx switch had been disabled. 7524 */ 7525 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 7526 tx_flags |= IXGBE_TX_FLAGS_CC; 7527 7528 #endif 7529 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 7530 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 7531 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 7532 (skb->priority != TC_PRIO_CONTROL))) { 7533 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 7534 tx_flags |= (skb->priority & 0x7) << 7535 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 7536 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 7537 struct vlan_ethhdr *vhdr; 7538 7539 if (skb_cow_head(skb, 0)) 7540 goto out_drop; 7541 vhdr = (struct vlan_ethhdr *)skb->data; 7542 vhdr->h_vlan_TCI = htons(tx_flags >> 7543 IXGBE_TX_FLAGS_VLAN_SHIFT); 7544 } else { 7545 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 7546 } 7547 } 7548 7549 /* record initial flags and protocol */ 7550 first->tx_flags = tx_flags; 7551 first->protocol = protocol; 7552 7553 #ifdef IXGBE_FCOE 7554 /* setup tx offload for FCoE */ 7555 if ((protocol == htons(ETH_P_FCOE)) && 7556 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 7557 tso = ixgbe_fso(tx_ring, first, &hdr_len); 7558 if (tso < 0) 7559 goto out_drop; 7560 7561 goto xmit_fcoe; 7562 } 7563 7564 #endif /* IXGBE_FCOE */ 7565 tso = ixgbe_tso(tx_ring, first, &hdr_len); 7566 if (tso < 0) 7567 goto out_drop; 7568 else if (!tso) 7569 ixgbe_tx_csum(tx_ring, first); 7570 7571 /* add the ATR filter if ATR is on */ 7572 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 7573 ixgbe_atr(tx_ring, first); 7574 7575 #ifdef IXGBE_FCOE 7576 xmit_fcoe: 7577 #endif /* IXGBE_FCOE */ 7578 ixgbe_tx_map(tx_ring, first, hdr_len); 7579 7580 return NETDEV_TX_OK; 7581 7582 out_drop: 7583 dev_kfree_skb_any(first->skb); 7584 first->skb = NULL; 7585 7586 return NETDEV_TX_OK; 7587 } 7588 7589 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 7590 struct net_device *netdev, 7591 struct ixgbe_ring *ring) 7592 { 7593 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7594 struct ixgbe_ring *tx_ring; 7595 7596 /* 7597 * The minimum packet size for olinfo paylen is 17 so pad the skb 7598 * in order to meet this minimum size requirement. 7599 */ 7600 if (skb_put_padto(skb, 17)) 7601 return NETDEV_TX_OK; 7602 7603 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 7604 7605 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 7606 } 7607 7608 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 7609 struct net_device *netdev) 7610 { 7611 return __ixgbe_xmit_frame(skb, netdev, NULL); 7612 } 7613 7614 /** 7615 * ixgbe_set_mac - Change the Ethernet Address of the NIC 7616 * @netdev: network interface device structure 7617 * @p: pointer to an address structure 7618 * 7619 * Returns 0 on success, negative on failure 7620 **/ 7621 static int ixgbe_set_mac(struct net_device *netdev, void *p) 7622 { 7623 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7624 struct ixgbe_hw *hw = &adapter->hw; 7625 struct sockaddr *addr = p; 7626 int ret; 7627 7628 if (!is_valid_ether_addr(addr->sa_data)) 7629 return -EADDRNOTAVAIL; 7630 7631 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7632 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 7633 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 7634 7635 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0)); 7636 return ret > 0 ? 0 : ret; 7637 } 7638 7639 static int 7640 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 7641 { 7642 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7643 struct ixgbe_hw *hw = &adapter->hw; 7644 u16 value; 7645 int rc; 7646 7647 if (prtad != hw->phy.mdio.prtad) 7648 return -EINVAL; 7649 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 7650 if (!rc) 7651 rc = value; 7652 return rc; 7653 } 7654 7655 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 7656 u16 addr, u16 value) 7657 { 7658 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7659 struct ixgbe_hw *hw = &adapter->hw; 7660 7661 if (prtad != hw->phy.mdio.prtad) 7662 return -EINVAL; 7663 return hw->phy.ops.write_reg(hw, addr, devad, value); 7664 } 7665 7666 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 7667 { 7668 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7669 7670 switch (cmd) { 7671 case SIOCSHWTSTAMP: 7672 return ixgbe_ptp_set_ts_config(adapter, req); 7673 case SIOCGHWTSTAMP: 7674 return ixgbe_ptp_get_ts_config(adapter, req); 7675 default: 7676 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 7677 } 7678 } 7679 7680 /** 7681 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 7682 * netdev->dev_addrs 7683 * @netdev: network interface device structure 7684 * 7685 * Returns non-zero on failure 7686 **/ 7687 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 7688 { 7689 int err = 0; 7690 struct ixgbe_adapter *adapter = netdev_priv(dev); 7691 struct ixgbe_hw *hw = &adapter->hw; 7692 7693 if (is_valid_ether_addr(hw->mac.san_addr)) { 7694 rtnl_lock(); 7695 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 7696 rtnl_unlock(); 7697 7698 /* update SAN MAC vmdq pool selection */ 7699 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 7700 } 7701 return err; 7702 } 7703 7704 /** 7705 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 7706 * netdev->dev_addrs 7707 * @netdev: network interface device structure 7708 * 7709 * Returns non-zero on failure 7710 **/ 7711 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 7712 { 7713 int err = 0; 7714 struct ixgbe_adapter *adapter = netdev_priv(dev); 7715 struct ixgbe_mac_info *mac = &adapter->hw.mac; 7716 7717 if (is_valid_ether_addr(mac->san_addr)) { 7718 rtnl_lock(); 7719 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 7720 rtnl_unlock(); 7721 } 7722 return err; 7723 } 7724 7725 #ifdef CONFIG_NET_POLL_CONTROLLER 7726 /* 7727 * Polling 'interrupt' - used by things like netconsole to send skbs 7728 * without having to re-enable interrupts. It's not called while 7729 * the interrupt routine is executing. 7730 */ 7731 static void ixgbe_netpoll(struct net_device *netdev) 7732 { 7733 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7734 int i; 7735 7736 /* if interface is down do nothing */ 7737 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7738 return; 7739 7740 /* loop through and schedule all active queues */ 7741 for (i = 0; i < adapter->num_q_vectors; i++) 7742 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 7743 } 7744 7745 #endif 7746 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, 7747 struct rtnl_link_stats64 *stats) 7748 { 7749 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7750 int i; 7751 7752 rcu_read_lock(); 7753 for (i = 0; i < adapter->num_rx_queues; i++) { 7754 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 7755 u64 bytes, packets; 7756 unsigned int start; 7757 7758 if (ring) { 7759 do { 7760 start = u64_stats_fetch_begin_irq(&ring->syncp); 7761 packets = ring->stats.packets; 7762 bytes = ring->stats.bytes; 7763 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7764 stats->rx_packets += packets; 7765 stats->rx_bytes += bytes; 7766 } 7767 } 7768 7769 for (i = 0; i < adapter->num_tx_queues; i++) { 7770 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 7771 u64 bytes, packets; 7772 unsigned int start; 7773 7774 if (ring) { 7775 do { 7776 start = u64_stats_fetch_begin_irq(&ring->syncp); 7777 packets = ring->stats.packets; 7778 bytes = ring->stats.bytes; 7779 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 7780 stats->tx_packets += packets; 7781 stats->tx_bytes += bytes; 7782 } 7783 } 7784 rcu_read_unlock(); 7785 /* following stats updated by ixgbe_watchdog_task() */ 7786 stats->multicast = netdev->stats.multicast; 7787 stats->rx_errors = netdev->stats.rx_errors; 7788 stats->rx_length_errors = netdev->stats.rx_length_errors; 7789 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 7790 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 7791 return stats; 7792 } 7793 7794 #ifdef CONFIG_IXGBE_DCB 7795 /** 7796 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 7797 * @adapter: pointer to ixgbe_adapter 7798 * @tc: number of traffic classes currently enabled 7799 * 7800 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 7801 * 802.1Q priority maps to a packet buffer that exists. 7802 */ 7803 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 7804 { 7805 struct ixgbe_hw *hw = &adapter->hw; 7806 u32 reg, rsave; 7807 int i; 7808 7809 /* 82598 have a static priority to TC mapping that can not 7810 * be changed so no validation is needed. 7811 */ 7812 if (hw->mac.type == ixgbe_mac_82598EB) 7813 return; 7814 7815 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 7816 rsave = reg; 7817 7818 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 7819 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 7820 7821 /* If up2tc is out of bounds default to zero */ 7822 if (up2tc > tc) 7823 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 7824 } 7825 7826 if (reg != rsave) 7827 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 7828 7829 return; 7830 } 7831 7832 /** 7833 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 7834 * @adapter: Pointer to adapter struct 7835 * 7836 * Populate the netdev user priority to tc map 7837 */ 7838 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 7839 { 7840 struct net_device *dev = adapter->netdev; 7841 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 7842 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 7843 u8 prio; 7844 7845 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 7846 u8 tc = 0; 7847 7848 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 7849 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 7850 else if (ets) 7851 tc = ets->prio_tc[prio]; 7852 7853 netdev_set_prio_tc_map(dev, prio, tc); 7854 } 7855 } 7856 7857 #endif /* CONFIG_IXGBE_DCB */ 7858 /** 7859 * ixgbe_setup_tc - configure net_device for multiple traffic classes 7860 * 7861 * @netdev: net device to configure 7862 * @tc: number of traffic classes to enable 7863 */ 7864 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 7865 { 7866 struct ixgbe_adapter *adapter = netdev_priv(dev); 7867 struct ixgbe_hw *hw = &adapter->hw; 7868 bool pools; 7869 7870 /* Hardware supports up to 8 traffic classes */ 7871 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 7872 return -EINVAL; 7873 7874 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 7875 return -EINVAL; 7876 7877 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 7878 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 7879 return -EBUSY; 7880 7881 /* Hardware has to reinitialize queues and interrupts to 7882 * match packet buffer alignment. Unfortunately, the 7883 * hardware is not flexible enough to do this dynamically. 7884 */ 7885 if (netif_running(dev)) 7886 ixgbe_close(dev); 7887 ixgbe_clear_interrupt_scheme(adapter); 7888 7889 #ifdef CONFIG_IXGBE_DCB 7890 if (tc) { 7891 netdev_set_num_tc(dev, tc); 7892 ixgbe_set_prio_tc_map(adapter); 7893 7894 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 7895 7896 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 7897 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 7898 adapter->hw.fc.requested_mode = ixgbe_fc_none; 7899 } 7900 } else { 7901 netdev_reset_tc(dev); 7902 7903 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 7904 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 7905 7906 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 7907 7908 adapter->temp_dcb_cfg.pfc_mode_enable = false; 7909 adapter->dcb_cfg.pfc_mode_enable = false; 7910 } 7911 7912 ixgbe_validate_rtr(adapter, tc); 7913 7914 #endif /* CONFIG_IXGBE_DCB */ 7915 ixgbe_init_interrupt_scheme(adapter); 7916 7917 if (netif_running(dev)) 7918 return ixgbe_open(dev); 7919 7920 return 0; 7921 } 7922 7923 #ifdef CONFIG_PCI_IOV 7924 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 7925 { 7926 struct net_device *netdev = adapter->netdev; 7927 7928 rtnl_lock(); 7929 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 7930 rtnl_unlock(); 7931 } 7932 7933 #endif 7934 void ixgbe_do_reset(struct net_device *netdev) 7935 { 7936 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7937 7938 if (netif_running(netdev)) 7939 ixgbe_reinit_locked(adapter); 7940 else 7941 ixgbe_reset(adapter); 7942 } 7943 7944 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 7945 netdev_features_t features) 7946 { 7947 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7948 7949 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 7950 if (!(features & NETIF_F_RXCSUM)) 7951 features &= ~NETIF_F_LRO; 7952 7953 /* Turn off LRO if not RSC capable */ 7954 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 7955 features &= ~NETIF_F_LRO; 7956 7957 return features; 7958 } 7959 7960 static int ixgbe_set_features(struct net_device *netdev, 7961 netdev_features_t features) 7962 { 7963 struct ixgbe_adapter *adapter = netdev_priv(netdev); 7964 netdev_features_t changed = netdev->features ^ features; 7965 bool need_reset = false; 7966 7967 /* Make sure RSC matches LRO, reset if change */ 7968 if (!(features & NETIF_F_LRO)) { 7969 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 7970 need_reset = true; 7971 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 7972 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 7973 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 7974 if (adapter->rx_itr_setting == 1 || 7975 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 7976 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 7977 need_reset = true; 7978 } else if ((changed ^ features) & NETIF_F_LRO) { 7979 e_info(probe, "rx-usecs set too low, " 7980 "disabling RSC\n"); 7981 } 7982 } 7983 7984 /* 7985 * Check if Flow Director n-tuple support was enabled or disabled. If 7986 * the state changed, we need to reset. 7987 */ 7988 switch (features & NETIF_F_NTUPLE) { 7989 case NETIF_F_NTUPLE: 7990 /* turn off ATR, enable perfect filters and reset */ 7991 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 7992 need_reset = true; 7993 7994 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 7995 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 7996 break; 7997 default: 7998 /* turn off perfect filters, enable ATR and reset */ 7999 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 8000 need_reset = true; 8001 8002 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 8003 8004 /* We cannot enable ATR if SR-IOV is enabled */ 8005 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8006 break; 8007 8008 /* We cannot enable ATR if we have 2 or more traffic classes */ 8009 if (netdev_get_num_tc(netdev) > 1) 8010 break; 8011 8012 /* We cannot enable ATR if RSS is disabled */ 8013 if (adapter->ring_feature[RING_F_RSS].limit <= 1) 8014 break; 8015 8016 /* A sample rate of 0 indicates ATR disabled */ 8017 if (!adapter->atr_sample_rate) 8018 break; 8019 8020 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 8021 break; 8022 } 8023 8024 if (features & NETIF_F_HW_VLAN_CTAG_RX) 8025 ixgbe_vlan_strip_enable(adapter); 8026 else 8027 ixgbe_vlan_strip_disable(adapter); 8028 8029 if (changed & NETIF_F_RXALL) 8030 need_reset = true; 8031 8032 netdev->features = features; 8033 8034 #ifdef CONFIG_IXGBE_VXLAN 8035 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 8036 if (features & NETIF_F_RXCSUM) 8037 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; 8038 else 8039 ixgbe_clear_vxlan_port(adapter); 8040 } 8041 #endif /* CONFIG_IXGBE_VXLAN */ 8042 8043 if (need_reset) 8044 ixgbe_do_reset(netdev); 8045 8046 return 0; 8047 } 8048 8049 #ifdef CONFIG_IXGBE_VXLAN 8050 /** 8051 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up 8052 * @dev: The port's netdev 8053 * @sa_family: Socket Family that VXLAN is notifiying us about 8054 * @port: New UDP port number that VXLAN started listening to 8055 **/ 8056 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, 8057 __be16 port) 8058 { 8059 struct ixgbe_adapter *adapter = netdev_priv(dev); 8060 struct ixgbe_hw *hw = &adapter->hw; 8061 u16 new_port = ntohs(port); 8062 8063 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 8064 return; 8065 8066 if (sa_family == AF_INET6) 8067 return; 8068 8069 if (adapter->vxlan_port == new_port) 8070 return; 8071 8072 if (adapter->vxlan_port) { 8073 netdev_info(dev, 8074 "Hit Max num of VXLAN ports, not adding port %d\n", 8075 new_port); 8076 return; 8077 } 8078 8079 adapter->vxlan_port = new_port; 8080 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port); 8081 } 8082 8083 /** 8084 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away 8085 * @dev: The port's netdev 8086 * @sa_family: Socket Family that VXLAN is notifying us about 8087 * @port: UDP port number that VXLAN stopped listening to 8088 **/ 8089 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, 8090 __be16 port) 8091 { 8092 struct ixgbe_adapter *adapter = netdev_priv(dev); 8093 u16 new_port = ntohs(port); 8094 8095 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 8096 return; 8097 8098 if (sa_family == AF_INET6) 8099 return; 8100 8101 if (adapter->vxlan_port != new_port) { 8102 netdev_info(dev, "Port %d was not found, not deleting\n", 8103 new_port); 8104 return; 8105 } 8106 8107 ixgbe_clear_vxlan_port(adapter); 8108 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; 8109 } 8110 #endif /* CONFIG_IXGBE_VXLAN */ 8111 8112 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 8113 struct net_device *dev, 8114 const unsigned char *addr, u16 vid, 8115 u16 flags) 8116 { 8117 /* guarantee we can provide a unique filter for the unicast address */ 8118 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 8119 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev)) 8120 return -ENOMEM; 8121 } 8122 8123 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 8124 } 8125 8126 /** 8127 * ixgbe_configure_bridge_mode - set various bridge modes 8128 * @adapter - the private structure 8129 * @mode - requested bridge mode 8130 * 8131 * Configure some settings require for various bridge modes. 8132 **/ 8133 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 8134 __u16 mode) 8135 { 8136 struct ixgbe_hw *hw = &adapter->hw; 8137 unsigned int p, num_pools; 8138 u32 vmdctl; 8139 8140 switch (mode) { 8141 case BRIDGE_MODE_VEPA: 8142 /* disable Tx loopback, rely on switch hairpin mode */ 8143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 8144 8145 /* must enable Rx switching replication to allow multicast 8146 * packet reception on all VFs, and to enable source address 8147 * pruning. 8148 */ 8149 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 8150 vmdctl |= IXGBE_VT_CTL_REPLEN; 8151 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 8152 8153 /* enable Rx source address pruning. Note, this requires 8154 * replication to be enabled or else it does nothing. 8155 */ 8156 num_pools = adapter->num_vfs + adapter->num_rx_pools; 8157 for (p = 0; p < num_pools; p++) { 8158 if (hw->mac.ops.set_source_address_pruning) 8159 hw->mac.ops.set_source_address_pruning(hw, 8160 true, 8161 p); 8162 } 8163 break; 8164 case BRIDGE_MODE_VEB: 8165 /* enable Tx loopback for internal VF/PF communication */ 8166 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 8167 IXGBE_PFDTXGSWC_VT_LBEN); 8168 8169 /* disable Rx switching replication unless we have SR-IOV 8170 * virtual functions 8171 */ 8172 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 8173 if (!adapter->num_vfs) 8174 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 8175 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 8176 8177 /* disable Rx source address pruning, since we don't expect to 8178 * be receiving external loopback of our transmitted frames. 8179 */ 8180 num_pools = adapter->num_vfs + adapter->num_rx_pools; 8181 for (p = 0; p < num_pools; p++) { 8182 if (hw->mac.ops.set_source_address_pruning) 8183 hw->mac.ops.set_source_address_pruning(hw, 8184 false, 8185 p); 8186 } 8187 break; 8188 default: 8189 return -EINVAL; 8190 } 8191 8192 adapter->bridge_mode = mode; 8193 8194 e_info(drv, "enabling bridge mode: %s\n", 8195 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 8196 8197 return 0; 8198 } 8199 8200 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 8201 struct nlmsghdr *nlh, u16 flags) 8202 { 8203 struct ixgbe_adapter *adapter = netdev_priv(dev); 8204 struct nlattr *attr, *br_spec; 8205 int rem; 8206 8207 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 8208 return -EOPNOTSUPP; 8209 8210 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 8211 if (!br_spec) 8212 return -EINVAL; 8213 8214 nla_for_each_nested(attr, br_spec, rem) { 8215 int status; 8216 __u16 mode; 8217 8218 if (nla_type(attr) != IFLA_BRIDGE_MODE) 8219 continue; 8220 8221 if (nla_len(attr) < sizeof(mode)) 8222 return -EINVAL; 8223 8224 mode = nla_get_u16(attr); 8225 status = ixgbe_configure_bridge_mode(adapter, mode); 8226 if (status) 8227 return status; 8228 8229 break; 8230 } 8231 8232 return 0; 8233 } 8234 8235 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 8236 struct net_device *dev, 8237 u32 filter_mask, int nlflags) 8238 { 8239 struct ixgbe_adapter *adapter = netdev_priv(dev); 8240 8241 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 8242 return 0; 8243 8244 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 8245 adapter->bridge_mode, 0, 0, nlflags, 8246 filter_mask, NULL); 8247 } 8248 8249 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 8250 { 8251 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 8252 struct ixgbe_adapter *adapter = netdev_priv(pdev); 8253 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 8254 unsigned int limit; 8255 int pool, err; 8256 8257 /* Hardware has a limited number of available pools. Each VF, and the 8258 * PF require a pool. Check to ensure we don't attempt to use more 8259 * then the available number of pools. 8260 */ 8261 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 8262 return ERR_PTR(-EINVAL); 8263 8264 #ifdef CONFIG_RPS 8265 if (vdev->num_rx_queues != vdev->num_tx_queues) { 8266 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 8267 vdev->name); 8268 return ERR_PTR(-EINVAL); 8269 } 8270 #endif 8271 /* Check for hardware restriction on number of rx/tx queues */ 8272 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 8273 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 8274 netdev_info(pdev, 8275 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 8276 pdev->name); 8277 return ERR_PTR(-EINVAL); 8278 } 8279 8280 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8281 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 8282 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 8283 return ERR_PTR(-EBUSY); 8284 8285 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 8286 if (!fwd_adapter) 8287 return ERR_PTR(-ENOMEM); 8288 8289 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 8290 adapter->num_rx_pools++; 8291 set_bit(pool, &adapter->fwd_bitmask); 8292 limit = find_last_bit(&adapter->fwd_bitmask, 32); 8293 8294 /* Enable VMDq flag so device will be set in VM mode */ 8295 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 8296 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 8297 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 8298 8299 /* Force reinit of ring allocation with VMDQ enabled */ 8300 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 8301 if (err) 8302 goto fwd_add_err; 8303 fwd_adapter->pool = pool; 8304 fwd_adapter->real_adapter = adapter; 8305 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 8306 if (err) 8307 goto fwd_add_err; 8308 netif_tx_start_all_queues(vdev); 8309 return fwd_adapter; 8310 fwd_add_err: 8311 /* unwind counter and free adapter struct */ 8312 netdev_info(pdev, 8313 "%s: dfwd hardware acceleration failed\n", vdev->name); 8314 clear_bit(pool, &adapter->fwd_bitmask); 8315 adapter->num_rx_pools--; 8316 kfree(fwd_adapter); 8317 return ERR_PTR(err); 8318 } 8319 8320 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 8321 { 8322 struct ixgbe_fwd_adapter *fwd_adapter = priv; 8323 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 8324 unsigned int limit; 8325 8326 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 8327 adapter->num_rx_pools--; 8328 8329 limit = find_last_bit(&adapter->fwd_bitmask, 32); 8330 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 8331 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 8332 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 8333 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 8334 fwd_adapter->pool, adapter->num_rx_pools, 8335 fwd_adapter->rx_base_queue, 8336 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 8337 adapter->fwd_bitmask); 8338 kfree(fwd_adapter); 8339 } 8340 8341 #define IXGBE_MAX_TUNNEL_HDR_LEN 80 8342 static netdev_features_t 8343 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 8344 netdev_features_t features) 8345 { 8346 if (!skb->encapsulation) 8347 return features; 8348 8349 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) > 8350 IXGBE_MAX_TUNNEL_HDR_LEN)) 8351 return features & ~NETIF_F_ALL_CSUM; 8352 8353 return features; 8354 } 8355 8356 static const struct net_device_ops ixgbe_netdev_ops = { 8357 .ndo_open = ixgbe_open, 8358 .ndo_stop = ixgbe_close, 8359 .ndo_start_xmit = ixgbe_xmit_frame, 8360 .ndo_select_queue = ixgbe_select_queue, 8361 .ndo_set_rx_mode = ixgbe_set_rx_mode, 8362 .ndo_validate_addr = eth_validate_addr, 8363 .ndo_set_mac_address = ixgbe_set_mac, 8364 .ndo_change_mtu = ixgbe_change_mtu, 8365 .ndo_tx_timeout = ixgbe_tx_timeout, 8366 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 8367 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 8368 .ndo_do_ioctl = ixgbe_ioctl, 8369 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 8370 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 8371 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 8372 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 8373 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 8374 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 8375 .ndo_get_stats64 = ixgbe_get_stats64, 8376 #ifdef CONFIG_IXGBE_DCB 8377 .ndo_setup_tc = ixgbe_setup_tc, 8378 #endif 8379 #ifdef CONFIG_NET_POLL_CONTROLLER 8380 .ndo_poll_controller = ixgbe_netpoll, 8381 #endif 8382 #ifdef CONFIG_NET_RX_BUSY_POLL 8383 .ndo_busy_poll = ixgbe_low_latency_recv, 8384 #endif 8385 #ifdef IXGBE_FCOE 8386 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 8387 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 8388 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 8389 .ndo_fcoe_enable = ixgbe_fcoe_enable, 8390 .ndo_fcoe_disable = ixgbe_fcoe_disable, 8391 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 8392 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 8393 #endif /* IXGBE_FCOE */ 8394 .ndo_set_features = ixgbe_set_features, 8395 .ndo_fix_features = ixgbe_fix_features, 8396 .ndo_fdb_add = ixgbe_ndo_fdb_add, 8397 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 8398 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 8399 .ndo_dfwd_add_station = ixgbe_fwd_add, 8400 .ndo_dfwd_del_station = ixgbe_fwd_del, 8401 #ifdef CONFIG_IXGBE_VXLAN 8402 .ndo_add_vxlan_port = ixgbe_add_vxlan_port, 8403 .ndo_del_vxlan_port = ixgbe_del_vxlan_port, 8404 #endif /* CONFIG_IXGBE_VXLAN */ 8405 .ndo_features_check = ixgbe_features_check, 8406 }; 8407 8408 /** 8409 * ixgbe_enumerate_functions - Get the number of ports this device has 8410 * @adapter: adapter structure 8411 * 8412 * This function enumerates the phsyical functions co-located on a single slot, 8413 * in order to determine how many ports a device has. This is most useful in 8414 * determining the required GT/s of PCIe bandwidth necessary for optimal 8415 * performance. 8416 **/ 8417 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 8418 { 8419 struct pci_dev *entry, *pdev = adapter->pdev; 8420 int physfns = 0; 8421 8422 /* Some cards can not use the generic count PCIe functions method, 8423 * because they are behind a parent switch, so we hardcode these with 8424 * the correct number of functions. 8425 */ 8426 if (ixgbe_pcie_from_parent(&adapter->hw)) 8427 physfns = 4; 8428 8429 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 8430 /* don't count virtual functions */ 8431 if (entry->is_virtfn) 8432 continue; 8433 8434 /* When the devices on the bus don't all match our device ID, 8435 * we can't reliably determine the correct number of 8436 * functions. This can occur if a function has been direct 8437 * attached to a virtual machine using VT-d, for example. In 8438 * this case, simply return -1 to indicate this. 8439 */ 8440 if ((entry->vendor != pdev->vendor) || 8441 (entry->device != pdev->device)) 8442 return -1; 8443 8444 physfns++; 8445 } 8446 8447 return physfns; 8448 } 8449 8450 /** 8451 * ixgbe_wol_supported - Check whether device supports WoL 8452 * @hw: hw specific details 8453 * @device_id: the device ID 8454 * @subdev_id: the subsystem device ID 8455 * 8456 * This function is used by probe and ethtool to determine 8457 * which devices have WoL support 8458 * 8459 **/ 8460 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 8461 u16 subdevice_id) 8462 { 8463 struct ixgbe_hw *hw = &adapter->hw; 8464 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 8465 int is_wol_supported = 0; 8466 8467 switch (device_id) { 8468 case IXGBE_DEV_ID_82599_SFP: 8469 /* Only these subdevices could supports WOL */ 8470 switch (subdevice_id) { 8471 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 8472 case IXGBE_SUBDEV_ID_82599_560FLR: 8473 /* only support first port */ 8474 if (hw->bus.func != 0) 8475 break; 8476 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 8477 case IXGBE_SUBDEV_ID_82599_SFP: 8478 case IXGBE_SUBDEV_ID_82599_RNDC: 8479 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 8480 case IXGBE_SUBDEV_ID_82599_LOM_SFP: 8481 is_wol_supported = 1; 8482 break; 8483 } 8484 break; 8485 case IXGBE_DEV_ID_82599EN_SFP: 8486 /* Only this subdevice supports WOL */ 8487 switch (subdevice_id) { 8488 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 8489 is_wol_supported = 1; 8490 break; 8491 } 8492 break; 8493 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 8494 /* All except this subdevice support WOL */ 8495 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 8496 is_wol_supported = 1; 8497 break; 8498 case IXGBE_DEV_ID_82599_KX4: 8499 is_wol_supported = 1; 8500 break; 8501 case IXGBE_DEV_ID_X540T: 8502 case IXGBE_DEV_ID_X540T1: 8503 case IXGBE_DEV_ID_X550T: 8504 case IXGBE_DEV_ID_X550EM_X_KX4: 8505 case IXGBE_DEV_ID_X550EM_X_KR: 8506 case IXGBE_DEV_ID_X550EM_X_10G_T: 8507 /* check eeprom to see if enabled wol */ 8508 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 8509 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 8510 (hw->bus.func == 0))) { 8511 is_wol_supported = 1; 8512 } 8513 break; 8514 } 8515 8516 return is_wol_supported; 8517 } 8518 8519 /** 8520 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM 8521 * @adapter: Pointer to adapter struct 8522 */ 8523 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter) 8524 { 8525 #ifdef CONFIG_OF 8526 struct device_node *dp = pci_device_to_OF_node(adapter->pdev); 8527 struct ixgbe_hw *hw = &adapter->hw; 8528 const unsigned char *addr; 8529 8530 addr = of_get_mac_address(dp); 8531 if (addr) { 8532 ether_addr_copy(hw->mac.perm_addr, addr); 8533 return; 8534 } 8535 #endif /* CONFIG_OF */ 8536 8537 #ifdef CONFIG_SPARC 8538 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr); 8539 #endif /* CONFIG_SPARC */ 8540 } 8541 8542 /** 8543 * ixgbe_probe - Device Initialization Routine 8544 * @pdev: PCI device information struct 8545 * @ent: entry in ixgbe_pci_tbl 8546 * 8547 * Returns 0 on success, negative on failure 8548 * 8549 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 8550 * The OS initialization, configuring of the adapter private structure, 8551 * and a hardware reset occur. 8552 **/ 8553 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 8554 { 8555 struct net_device *netdev; 8556 struct ixgbe_adapter *adapter = NULL; 8557 struct ixgbe_hw *hw; 8558 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 8559 int i, err, pci_using_dac, expected_gts; 8560 unsigned int indices = MAX_TX_QUEUES; 8561 u8 part_str[IXGBE_PBANUM_LENGTH]; 8562 bool disable_dev = false; 8563 #ifdef IXGBE_FCOE 8564 u16 device_caps; 8565 #endif 8566 u32 eec; 8567 8568 /* Catch broken hardware that put the wrong VF device ID in 8569 * the PCIe SR-IOV capability. 8570 */ 8571 if (pdev->is_virtfn) { 8572 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 8573 pci_name(pdev), pdev->vendor, pdev->device); 8574 return -EINVAL; 8575 } 8576 8577 err = pci_enable_device_mem(pdev); 8578 if (err) 8579 return err; 8580 8581 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 8582 pci_using_dac = 1; 8583 } else { 8584 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 8585 if (err) { 8586 dev_err(&pdev->dev, 8587 "No usable DMA configuration, aborting\n"); 8588 goto err_dma; 8589 } 8590 pci_using_dac = 0; 8591 } 8592 8593 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 8594 IORESOURCE_MEM), ixgbe_driver_name); 8595 if (err) { 8596 dev_err(&pdev->dev, 8597 "pci_request_selected_regions failed 0x%x\n", err); 8598 goto err_pci_reg; 8599 } 8600 8601 pci_enable_pcie_error_reporting(pdev); 8602 8603 pci_set_master(pdev); 8604 pci_save_state(pdev); 8605 8606 if (ii->mac == ixgbe_mac_82598EB) { 8607 #ifdef CONFIG_IXGBE_DCB 8608 /* 8 TC w/ 4 queues per TC */ 8609 indices = 4 * MAX_TRAFFIC_CLASS; 8610 #else 8611 indices = IXGBE_MAX_RSS_INDICES; 8612 #endif 8613 } 8614 8615 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 8616 if (!netdev) { 8617 err = -ENOMEM; 8618 goto err_alloc_etherdev; 8619 } 8620 8621 SET_NETDEV_DEV(netdev, &pdev->dev); 8622 8623 adapter = netdev_priv(netdev); 8624 8625 adapter->netdev = netdev; 8626 adapter->pdev = pdev; 8627 hw = &adapter->hw; 8628 hw->back = adapter; 8629 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 8630 8631 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 8632 pci_resource_len(pdev, 0)); 8633 adapter->io_addr = hw->hw_addr; 8634 if (!hw->hw_addr) { 8635 err = -EIO; 8636 goto err_ioremap; 8637 } 8638 8639 netdev->netdev_ops = &ixgbe_netdev_ops; 8640 ixgbe_set_ethtool_ops(netdev); 8641 netdev->watchdog_timeo = 5 * HZ; 8642 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 8643 8644 /* Setup hw api */ 8645 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); 8646 hw->mac.type = ii->mac; 8647 hw->mvals = ii->mvals; 8648 8649 /* EEPROM */ 8650 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); 8651 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 8652 if (ixgbe_removed(hw->hw_addr)) { 8653 err = -EIO; 8654 goto err_ioremap; 8655 } 8656 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 8657 if (!(eec & (1 << 8))) 8658 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 8659 8660 /* PHY */ 8661 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 8662 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 8663 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 8664 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 8665 hw->phy.mdio.mmds = 0; 8666 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 8667 hw->phy.mdio.dev = netdev; 8668 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 8669 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 8670 8671 ii->get_invariants(hw); 8672 8673 /* setup the private structure */ 8674 err = ixgbe_sw_init(adapter); 8675 if (err) 8676 goto err_sw_init; 8677 8678 /* Make it possible the adapter to be woken up via WOL */ 8679 switch (adapter->hw.mac.type) { 8680 case ixgbe_mac_82599EB: 8681 case ixgbe_mac_X540: 8682 case ixgbe_mac_X550: 8683 case ixgbe_mac_X550EM_x: 8684 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 8685 break; 8686 default: 8687 break; 8688 } 8689 8690 /* 8691 * If there is a fan on this device and it has failed log the 8692 * failure. 8693 */ 8694 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 8695 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 8696 if (esdp & IXGBE_ESDP_SDP1) 8697 e_crit(probe, "Fan has stopped, replace the adapter\n"); 8698 } 8699 8700 if (allow_unsupported_sfp) 8701 hw->allow_unsupported_sfp = allow_unsupported_sfp; 8702 8703 /* reset_hw fills in the perm_addr as well */ 8704 hw->phy.reset_if_overtemp = true; 8705 err = hw->mac.ops.reset_hw(hw); 8706 hw->phy.reset_if_overtemp = false; 8707 if (err == IXGBE_ERR_SFP_NOT_PRESENT && 8708 hw->mac.type == ixgbe_mac_82598EB) { 8709 err = 0; 8710 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 8711 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 8712 e_dev_err("Reload the driver after installing a supported module.\n"); 8713 goto err_sw_init; 8714 } else if (err) { 8715 e_dev_err("HW Init failed: %d\n", err); 8716 goto err_sw_init; 8717 } 8718 8719 #ifdef CONFIG_PCI_IOV 8720 /* SR-IOV not supported on the 82598 */ 8721 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8722 goto skip_sriov; 8723 /* Mailbox */ 8724 ixgbe_init_mbx_params_pf(hw); 8725 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops)); 8726 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 8727 ixgbe_enable_sriov(adapter); 8728 skip_sriov: 8729 8730 #endif 8731 netdev->features = NETIF_F_SG | 8732 NETIF_F_IP_CSUM | 8733 NETIF_F_IPV6_CSUM | 8734 NETIF_F_HW_VLAN_CTAG_TX | 8735 NETIF_F_HW_VLAN_CTAG_RX | 8736 NETIF_F_TSO | 8737 NETIF_F_TSO6 | 8738 NETIF_F_RXHASH | 8739 NETIF_F_RXCSUM; 8740 8741 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD; 8742 8743 switch (adapter->hw.mac.type) { 8744 case ixgbe_mac_82599EB: 8745 case ixgbe_mac_X540: 8746 case ixgbe_mac_X550: 8747 case ixgbe_mac_X550EM_x: 8748 netdev->features |= NETIF_F_SCTP_CSUM; 8749 netdev->hw_features |= NETIF_F_SCTP_CSUM | 8750 NETIF_F_NTUPLE; 8751 break; 8752 default: 8753 break; 8754 } 8755 8756 netdev->hw_features |= NETIF_F_RXALL; 8757 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 8758 8759 netdev->vlan_features |= NETIF_F_TSO; 8760 netdev->vlan_features |= NETIF_F_TSO6; 8761 netdev->vlan_features |= NETIF_F_IP_CSUM; 8762 netdev->vlan_features |= NETIF_F_IPV6_CSUM; 8763 netdev->vlan_features |= NETIF_F_SG; 8764 8765 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 8766 NETIF_F_IPV6_CSUM; 8767 8768 netdev->priv_flags |= IFF_UNICAST_FLT; 8769 netdev->priv_flags |= IFF_SUPP_NOFCS; 8770 8771 #ifdef CONFIG_IXGBE_VXLAN 8772 switch (adapter->hw.mac.type) { 8773 case ixgbe_mac_X550: 8774 case ixgbe_mac_X550EM_x: 8775 netdev->hw_enc_features |= NETIF_F_RXCSUM | 8776 NETIF_F_IP_CSUM | 8777 NETIF_F_IPV6_CSUM; 8778 break; 8779 default: 8780 break; 8781 } 8782 #endif /* CONFIG_IXGBE_VXLAN */ 8783 8784 #ifdef CONFIG_IXGBE_DCB 8785 netdev->dcbnl_ops = &dcbnl_ops; 8786 #endif 8787 8788 #ifdef IXGBE_FCOE 8789 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 8790 unsigned int fcoe_l; 8791 8792 if (hw->mac.ops.get_device_caps) { 8793 hw->mac.ops.get_device_caps(hw, &device_caps); 8794 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 8795 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 8796 } 8797 8798 8799 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 8800 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 8801 8802 netdev->features |= NETIF_F_FSO | 8803 NETIF_F_FCOE_CRC; 8804 8805 netdev->vlan_features |= NETIF_F_FSO | 8806 NETIF_F_FCOE_CRC | 8807 NETIF_F_FCOE_MTU; 8808 } 8809 #endif /* IXGBE_FCOE */ 8810 if (pci_using_dac) { 8811 netdev->features |= NETIF_F_HIGHDMA; 8812 netdev->vlan_features |= NETIF_F_HIGHDMA; 8813 } 8814 8815 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 8816 netdev->hw_features |= NETIF_F_LRO; 8817 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 8818 netdev->features |= NETIF_F_LRO; 8819 8820 /* make sure the EEPROM is good */ 8821 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 8822 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 8823 err = -EIO; 8824 goto err_sw_init; 8825 } 8826 8827 ixgbe_get_platform_mac_addr(adapter); 8828 8829 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 8830 8831 if (!is_valid_ether_addr(netdev->dev_addr)) { 8832 e_dev_err("invalid MAC address\n"); 8833 err = -EIO; 8834 goto err_sw_init; 8835 } 8836 8837 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr); 8838 8839 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 8840 (unsigned long) adapter); 8841 8842 if (ixgbe_removed(hw->hw_addr)) { 8843 err = -EIO; 8844 goto err_sw_init; 8845 } 8846 INIT_WORK(&adapter->service_task, ixgbe_service_task); 8847 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 8848 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 8849 8850 err = ixgbe_init_interrupt_scheme(adapter); 8851 if (err) 8852 goto err_sw_init; 8853 8854 /* WOL not supported for all devices */ 8855 adapter->wol = 0; 8856 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 8857 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 8858 pdev->subsystem_device); 8859 if (hw->wol_enabled) 8860 adapter->wol = IXGBE_WUFC_MAG; 8861 8862 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 8863 8864 /* save off EEPROM version number */ 8865 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 8866 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 8867 8868 /* pick up the PCI bus settings for reporting later */ 8869 if (ixgbe_pcie_from_parent(hw)) 8870 ixgbe_get_parent_bus_info(adapter); 8871 else 8872 hw->mac.ops.get_bus_info(hw); 8873 8874 /* calculate the expected PCIe bandwidth required for optimal 8875 * performance. Note that some older parts will never have enough 8876 * bandwidth due to being older generation PCIe parts. We clamp these 8877 * parts to ensure no warning is displayed if it can't be fixed. 8878 */ 8879 switch (hw->mac.type) { 8880 case ixgbe_mac_82598EB: 8881 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 8882 break; 8883 default: 8884 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 8885 break; 8886 } 8887 8888 /* don't check link if we failed to enumerate functions */ 8889 if (expected_gts > 0) 8890 ixgbe_check_minimum_link(adapter, expected_gts); 8891 8892 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 8893 if (err) 8894 strlcpy(part_str, "Unknown", sizeof(part_str)); 8895 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 8896 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 8897 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 8898 part_str); 8899 else 8900 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 8901 hw->mac.type, hw->phy.type, part_str); 8902 8903 e_dev_info("%pM\n", netdev->dev_addr); 8904 8905 /* reset the hardware with the new settings */ 8906 err = hw->mac.ops.start_hw(hw); 8907 if (err == IXGBE_ERR_EEPROM_VERSION) { 8908 /* We are running on a pre-production device, log a warning */ 8909 e_dev_warn("This device is a pre-production adapter/LOM. " 8910 "Please be aware there may be issues associated " 8911 "with your hardware. If you are experiencing " 8912 "problems please contact your Intel or hardware " 8913 "representative who provided you with this " 8914 "hardware.\n"); 8915 } 8916 strcpy(netdev->name, "eth%d"); 8917 err = register_netdev(netdev); 8918 if (err) 8919 goto err_register; 8920 8921 pci_set_drvdata(pdev, adapter); 8922 8923 /* power down the optics for 82599 SFP+ fiber */ 8924 if (hw->mac.ops.disable_tx_laser) 8925 hw->mac.ops.disable_tx_laser(hw); 8926 8927 /* carrier off reporting is important to ethtool even BEFORE open */ 8928 netif_carrier_off(netdev); 8929 8930 #ifdef CONFIG_IXGBE_DCA 8931 if (dca_add_requester(&pdev->dev) == 0) { 8932 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 8933 ixgbe_setup_dca(adapter); 8934 } 8935 #endif 8936 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 8937 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 8938 for (i = 0; i < adapter->num_vfs; i++) 8939 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 8940 } 8941 8942 /* firmware requires driver version to be 0xFFFFFFFF 8943 * since os does not support feature 8944 */ 8945 if (hw->mac.ops.set_fw_drv_ver) 8946 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 8947 0xFF); 8948 8949 /* add san mac addr to netdev */ 8950 ixgbe_add_sanmac_netdev(netdev); 8951 8952 e_dev_info("%s\n", ixgbe_default_device_descr); 8953 8954 #ifdef CONFIG_IXGBE_HWMON 8955 if (ixgbe_sysfs_init(adapter)) 8956 e_err(probe, "failed to allocate sysfs resources\n"); 8957 #endif /* CONFIG_IXGBE_HWMON */ 8958 8959 ixgbe_dbg_adapter_init(adapter); 8960 8961 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 8962 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 8963 hw->mac.ops.setup_link(hw, 8964 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 8965 true); 8966 8967 return 0; 8968 8969 err_register: 8970 ixgbe_release_hw_control(adapter); 8971 ixgbe_clear_interrupt_scheme(adapter); 8972 err_sw_init: 8973 ixgbe_disable_sriov(adapter); 8974 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 8975 iounmap(adapter->io_addr); 8976 kfree(adapter->mac_table); 8977 err_ioremap: 8978 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 8979 free_netdev(netdev); 8980 err_alloc_etherdev: 8981 pci_release_selected_regions(pdev, 8982 pci_select_bars(pdev, IORESOURCE_MEM)); 8983 err_pci_reg: 8984 err_dma: 8985 if (!adapter || disable_dev) 8986 pci_disable_device(pdev); 8987 return err; 8988 } 8989 8990 /** 8991 * ixgbe_remove - Device Removal Routine 8992 * @pdev: PCI device information struct 8993 * 8994 * ixgbe_remove is called by the PCI subsystem to alert the driver 8995 * that it should release a PCI device. The could be caused by a 8996 * Hot-Plug event, or because the driver is going to be removed from 8997 * memory. 8998 **/ 8999 static void ixgbe_remove(struct pci_dev *pdev) 9000 { 9001 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9002 struct net_device *netdev; 9003 bool disable_dev; 9004 9005 /* if !adapter then we already cleaned up in probe */ 9006 if (!adapter) 9007 return; 9008 9009 netdev = adapter->netdev; 9010 ixgbe_dbg_adapter_exit(adapter); 9011 9012 set_bit(__IXGBE_REMOVING, &adapter->state); 9013 cancel_work_sync(&adapter->service_task); 9014 9015 9016 #ifdef CONFIG_IXGBE_DCA 9017 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 9018 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 9019 dca_remove_requester(&pdev->dev); 9020 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); 9021 } 9022 9023 #endif 9024 #ifdef CONFIG_IXGBE_HWMON 9025 ixgbe_sysfs_exit(adapter); 9026 #endif /* CONFIG_IXGBE_HWMON */ 9027 9028 /* remove the added san mac */ 9029 ixgbe_del_sanmac_netdev(netdev); 9030 9031 #ifdef CONFIG_PCI_IOV 9032 ixgbe_disable_sriov(adapter); 9033 #endif 9034 if (netdev->reg_state == NETREG_REGISTERED) 9035 unregister_netdev(netdev); 9036 9037 ixgbe_clear_interrupt_scheme(adapter); 9038 9039 ixgbe_release_hw_control(adapter); 9040 9041 #ifdef CONFIG_DCB 9042 kfree(adapter->ixgbe_ieee_pfc); 9043 kfree(adapter->ixgbe_ieee_ets); 9044 9045 #endif 9046 iounmap(adapter->io_addr); 9047 pci_release_selected_regions(pdev, pci_select_bars(pdev, 9048 IORESOURCE_MEM)); 9049 9050 e_dev_info("complete\n"); 9051 9052 kfree(adapter->mac_table); 9053 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 9054 free_netdev(netdev); 9055 9056 pci_disable_pcie_error_reporting(pdev); 9057 9058 if (disable_dev) 9059 pci_disable_device(pdev); 9060 } 9061 9062 /** 9063 * ixgbe_io_error_detected - called when PCI error is detected 9064 * @pdev: Pointer to PCI device 9065 * @state: The current pci connection state 9066 * 9067 * This function is called after a PCI bus error affecting 9068 * this device has been detected. 9069 */ 9070 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 9071 pci_channel_state_t state) 9072 { 9073 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9074 struct net_device *netdev = adapter->netdev; 9075 9076 #ifdef CONFIG_PCI_IOV 9077 struct ixgbe_hw *hw = &adapter->hw; 9078 struct pci_dev *bdev, *vfdev; 9079 u32 dw0, dw1, dw2, dw3; 9080 int vf, pos; 9081 u16 req_id, pf_func; 9082 9083 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 9084 adapter->num_vfs == 0) 9085 goto skip_bad_vf_detection; 9086 9087 bdev = pdev->bus->self; 9088 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 9089 bdev = bdev->bus->self; 9090 9091 if (!bdev) 9092 goto skip_bad_vf_detection; 9093 9094 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 9095 if (!pos) 9096 goto skip_bad_vf_detection; 9097 9098 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 9099 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 9100 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 9101 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 9102 if (ixgbe_removed(hw->hw_addr)) 9103 goto skip_bad_vf_detection; 9104 9105 req_id = dw1 >> 16; 9106 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 9107 if (!(req_id & 0x0080)) 9108 goto skip_bad_vf_detection; 9109 9110 pf_func = req_id & 0x01; 9111 if ((pf_func & 1) == (pdev->devfn & 1)) { 9112 unsigned int device_id; 9113 9114 vf = (req_id & 0x7F) >> 1; 9115 e_dev_err("VF %d has caused a PCIe error\n", vf); 9116 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 9117 "%8.8x\tdw3: %8.8x\n", 9118 dw0, dw1, dw2, dw3); 9119 switch (adapter->hw.mac.type) { 9120 case ixgbe_mac_82599EB: 9121 device_id = IXGBE_82599_VF_DEVICE_ID; 9122 break; 9123 case ixgbe_mac_X540: 9124 device_id = IXGBE_X540_VF_DEVICE_ID; 9125 break; 9126 case ixgbe_mac_X550: 9127 device_id = IXGBE_DEV_ID_X550_VF; 9128 break; 9129 case ixgbe_mac_X550EM_x: 9130 device_id = IXGBE_DEV_ID_X550EM_X_VF; 9131 break; 9132 default: 9133 device_id = 0; 9134 break; 9135 } 9136 9137 /* Find the pci device of the offending VF */ 9138 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 9139 while (vfdev) { 9140 if (vfdev->devfn == (req_id & 0xFF)) 9141 break; 9142 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 9143 device_id, vfdev); 9144 } 9145 /* 9146 * There's a slim chance the VF could have been hot plugged, 9147 * so if it is no longer present we don't need to issue the 9148 * VFLR. Just clean up the AER in that case. 9149 */ 9150 if (vfdev) { 9151 ixgbe_issue_vf_flr(adapter, vfdev); 9152 /* Free device reference count */ 9153 pci_dev_put(vfdev); 9154 } 9155 9156 pci_cleanup_aer_uncorrect_error_status(pdev); 9157 } 9158 9159 /* 9160 * Even though the error may have occurred on the other port 9161 * we still need to increment the vf error reference count for 9162 * both ports because the I/O resume function will be called 9163 * for both of them. 9164 */ 9165 adapter->vferr_refcount++; 9166 9167 return PCI_ERS_RESULT_RECOVERED; 9168 9169 skip_bad_vf_detection: 9170 #endif /* CONFIG_PCI_IOV */ 9171 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 9172 return PCI_ERS_RESULT_DISCONNECT; 9173 9174 rtnl_lock(); 9175 netif_device_detach(netdev); 9176 9177 if (state == pci_channel_io_perm_failure) { 9178 rtnl_unlock(); 9179 return PCI_ERS_RESULT_DISCONNECT; 9180 } 9181 9182 if (netif_running(netdev)) 9183 ixgbe_down(adapter); 9184 9185 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 9186 pci_disable_device(pdev); 9187 rtnl_unlock(); 9188 9189 /* Request a slot reset. */ 9190 return PCI_ERS_RESULT_NEED_RESET; 9191 } 9192 9193 /** 9194 * ixgbe_io_slot_reset - called after the pci bus has been reset. 9195 * @pdev: Pointer to PCI device 9196 * 9197 * Restart the card from scratch, as if from a cold-boot. 9198 */ 9199 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 9200 { 9201 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9202 pci_ers_result_t result; 9203 int err; 9204 9205 if (pci_enable_device_mem(pdev)) { 9206 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 9207 result = PCI_ERS_RESULT_DISCONNECT; 9208 } else { 9209 smp_mb__before_atomic(); 9210 clear_bit(__IXGBE_DISABLED, &adapter->state); 9211 adapter->hw.hw_addr = adapter->io_addr; 9212 pci_set_master(pdev); 9213 pci_restore_state(pdev); 9214 pci_save_state(pdev); 9215 9216 pci_wake_from_d3(pdev, false); 9217 9218 ixgbe_reset(adapter); 9219 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 9220 result = PCI_ERS_RESULT_RECOVERED; 9221 } 9222 9223 err = pci_cleanup_aer_uncorrect_error_status(pdev); 9224 if (err) { 9225 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 9226 "failed 0x%0x\n", err); 9227 /* non-fatal, continue */ 9228 } 9229 9230 return result; 9231 } 9232 9233 /** 9234 * ixgbe_io_resume - called when traffic can start flowing again. 9235 * @pdev: Pointer to PCI device 9236 * 9237 * This callback is called when the error recovery driver tells us that 9238 * its OK to resume normal operation. 9239 */ 9240 static void ixgbe_io_resume(struct pci_dev *pdev) 9241 { 9242 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 9243 struct net_device *netdev = adapter->netdev; 9244 9245 #ifdef CONFIG_PCI_IOV 9246 if (adapter->vferr_refcount) { 9247 e_info(drv, "Resuming after VF err\n"); 9248 adapter->vferr_refcount--; 9249 return; 9250 } 9251 9252 #endif 9253 if (netif_running(netdev)) 9254 ixgbe_up(adapter); 9255 9256 netif_device_attach(netdev); 9257 } 9258 9259 static const struct pci_error_handlers ixgbe_err_handler = { 9260 .error_detected = ixgbe_io_error_detected, 9261 .slot_reset = ixgbe_io_slot_reset, 9262 .resume = ixgbe_io_resume, 9263 }; 9264 9265 static struct pci_driver ixgbe_driver = { 9266 .name = ixgbe_driver_name, 9267 .id_table = ixgbe_pci_tbl, 9268 .probe = ixgbe_probe, 9269 .remove = ixgbe_remove, 9270 #ifdef CONFIG_PM 9271 .suspend = ixgbe_suspend, 9272 .resume = ixgbe_resume, 9273 #endif 9274 .shutdown = ixgbe_shutdown, 9275 .sriov_configure = ixgbe_pci_sriov_configure, 9276 .err_handler = &ixgbe_err_handler 9277 }; 9278 9279 /** 9280 * ixgbe_init_module - Driver Registration Routine 9281 * 9282 * ixgbe_init_module is the first routine called when the driver is 9283 * loaded. All it does is register with the PCI subsystem. 9284 **/ 9285 static int __init ixgbe_init_module(void) 9286 { 9287 int ret; 9288 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 9289 pr_info("%s\n", ixgbe_copyright); 9290 9291 ixgbe_dbg_init(); 9292 9293 ret = pci_register_driver(&ixgbe_driver); 9294 if (ret) { 9295 ixgbe_dbg_exit(); 9296 return ret; 9297 } 9298 9299 #ifdef CONFIG_IXGBE_DCA 9300 dca_register_notify(&dca_notifier); 9301 #endif 9302 9303 return 0; 9304 } 9305 9306 module_init(ixgbe_init_module); 9307 9308 /** 9309 * ixgbe_exit_module - Driver Exit Cleanup Routine 9310 * 9311 * ixgbe_exit_module is called just before the driver is removed 9312 * from memory. 9313 **/ 9314 static void __exit ixgbe_exit_module(void) 9315 { 9316 #ifdef CONFIG_IXGBE_DCA 9317 dca_unregister_notify(&dca_notifier); 9318 #endif 9319 pci_unregister_driver(&ixgbe_driver); 9320 9321 ixgbe_dbg_exit(); 9322 } 9323 9324 #ifdef CONFIG_IXGBE_DCA 9325 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 9326 void *p) 9327 { 9328 int ret_val; 9329 9330 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 9331 __ixgbe_notify_dca); 9332 9333 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 9334 } 9335 9336 #endif /* CONFIG_IXGBE_DCA */ 9337 9338 module_exit(ixgbe_exit_module); 9339 9340 /* ixgbe_main.c */ 9341