1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <linux/bpf.h> 53 #include <linux/bpf_trace.h> 54 #include <linux/atomic.h> 55 #include <scsi/fc/fc_fcoe.h> 56 #include <net/udp_tunnel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/vxlan.h> 61 62 #include "ixgbe.h" 63 #include "ixgbe_common.h" 64 #include "ixgbe_dcb_82599.h" 65 #include "ixgbe_sriov.h" 66 #include "ixgbe_model.h" 67 68 char ixgbe_driver_name[] = "ixgbe"; 69 static const char ixgbe_driver_string[] = 70 "Intel(R) 10 Gigabit PCI Express Network Driver"; 71 #ifdef IXGBE_FCOE 72 char ixgbe_default_device_descr[] = 73 "Intel(R) 10 Gigabit Network Connection"; 74 #else 75 static char ixgbe_default_device_descr[] = 76 "Intel(R) 10 Gigabit Network Connection"; 77 #endif 78 #define DRV_VERSION "5.0.0-k" 79 const char ixgbe_driver_version[] = DRV_VERSION; 80 static const char ixgbe_copyright[] = 81 "Copyright (c) 1999-2016 Intel Corporation."; 82 83 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 84 85 static const struct ixgbe_info *ixgbe_info_tbl[] = { 86 [board_82598] = &ixgbe_82598_info, 87 [board_82599] = &ixgbe_82599_info, 88 [board_X540] = &ixgbe_X540_info, 89 [board_X550] = &ixgbe_X550_info, 90 [board_X550EM_x] = &ixgbe_X550EM_x_info, 91 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 92 [board_x550em_a] = &ixgbe_x550em_a_info, 93 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 94 }; 95 96 /* ixgbe_pci_tbl - PCI Device ID Table 97 * 98 * Wildcard entries (PCI_ANY_ID) should come last 99 * Last entry must be all 0s 100 * 101 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 102 * Class, Class Mask, private data (not used) } 103 */ 104 static const struct pci_device_id ixgbe_pci_tbl[] = { 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 152 /* required last entry */ 153 {0, } 154 }; 155 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 156 157 #ifdef CONFIG_IXGBE_DCA 158 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 159 void *p); 160 static struct notifier_block dca_notifier = { 161 .notifier_call = ixgbe_notify_dca, 162 .next = NULL, 163 .priority = 0 164 }; 165 #endif 166 167 #ifdef CONFIG_PCI_IOV 168 static unsigned int max_vfs; 169 module_param(max_vfs, uint, 0); 170 MODULE_PARM_DESC(max_vfs, 171 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 172 #endif /* CONFIG_PCI_IOV */ 173 174 static unsigned int allow_unsupported_sfp; 175 module_param(allow_unsupported_sfp, uint, 0); 176 MODULE_PARM_DESC(allow_unsupported_sfp, 177 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 178 179 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 180 static int debug = -1; 181 module_param(debug, int, 0); 182 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 183 184 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 185 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 186 MODULE_LICENSE("GPL"); 187 MODULE_VERSION(DRV_VERSION); 188 189 static struct workqueue_struct *ixgbe_wq; 190 191 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 192 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 193 194 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 195 u32 reg, u16 *value) 196 { 197 struct pci_dev *parent_dev; 198 struct pci_bus *parent_bus; 199 200 parent_bus = adapter->pdev->bus->parent; 201 if (!parent_bus) 202 return -1; 203 204 parent_dev = parent_bus->self; 205 if (!parent_dev) 206 return -1; 207 208 if (!pci_is_pcie(parent_dev)) 209 return -1; 210 211 pcie_capability_read_word(parent_dev, reg, value); 212 if (*value == IXGBE_FAILED_READ_CFG_WORD && 213 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 214 return -1; 215 return 0; 216 } 217 218 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 219 { 220 struct ixgbe_hw *hw = &adapter->hw; 221 u16 link_status = 0; 222 int err; 223 224 hw->bus.type = ixgbe_bus_type_pci_express; 225 226 /* Get the negotiated link width and speed from PCI config space of the 227 * parent, as this device is behind a switch 228 */ 229 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 230 231 /* assume caller will handle error case */ 232 if (err) 233 return err; 234 235 hw->bus.width = ixgbe_convert_bus_width(link_status); 236 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 237 238 return 0; 239 } 240 241 /** 242 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 243 * @hw: hw specific details 244 * 245 * This function is used by probe to determine whether a device's PCI-Express 246 * bandwidth details should be gathered from the parent bus instead of from the 247 * device. Used to ensure that various locations all have the correct device ID 248 * checks. 249 */ 250 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 251 { 252 switch (hw->device_id) { 253 case IXGBE_DEV_ID_82599_SFP_SF_QP: 254 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 255 return true; 256 default: 257 return false; 258 } 259 } 260 261 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 262 int expected_gts) 263 { 264 struct ixgbe_hw *hw = &adapter->hw; 265 int max_gts = 0; 266 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 267 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 268 struct pci_dev *pdev; 269 270 /* Some devices are not connected over PCIe and thus do not negotiate 271 * speed. These devices do not have valid bus info, and thus any report 272 * we generate may not be correct. 273 */ 274 if (hw->bus.type == ixgbe_bus_type_internal) 275 return; 276 277 /* determine whether to use the parent device */ 278 if (ixgbe_pcie_from_parent(&adapter->hw)) 279 pdev = adapter->pdev->bus->parent->self; 280 else 281 pdev = adapter->pdev; 282 283 if (pcie_get_minimum_link(pdev, &speed, &width) || 284 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 285 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 286 return; 287 } 288 289 switch (speed) { 290 case PCIE_SPEED_2_5GT: 291 /* 8b/10b encoding reduces max throughput by 20% */ 292 max_gts = 2 * width; 293 break; 294 case PCIE_SPEED_5_0GT: 295 /* 8b/10b encoding reduces max throughput by 20% */ 296 max_gts = 4 * width; 297 break; 298 case PCIE_SPEED_8_0GT: 299 /* 128b/130b encoding reduces throughput by less than 2% */ 300 max_gts = 8 * width; 301 break; 302 default: 303 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 304 return; 305 } 306 307 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 308 max_gts); 309 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 310 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 311 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 312 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 313 "Unknown"), 314 width, 315 (speed == PCIE_SPEED_2_5GT ? "20%" : 316 speed == PCIE_SPEED_5_0GT ? "20%" : 317 speed == PCIE_SPEED_8_0GT ? "<2%" : 318 "Unknown")); 319 320 if (max_gts < expected_gts) { 321 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 322 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 323 expected_gts); 324 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 325 } 326 } 327 328 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 329 { 330 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 331 !test_bit(__IXGBE_REMOVING, &adapter->state) && 332 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 333 queue_work(ixgbe_wq, &adapter->service_task); 334 } 335 336 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 337 { 338 struct ixgbe_adapter *adapter = hw->back; 339 340 if (!hw->hw_addr) 341 return; 342 hw->hw_addr = NULL; 343 e_dev_err("Adapter removed\n"); 344 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 345 ixgbe_service_event_schedule(adapter); 346 } 347 348 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 349 { 350 u32 value; 351 352 /* The following check not only optimizes a bit by not 353 * performing a read on the status register when the 354 * register just read was a status register read that 355 * returned IXGBE_FAILED_READ_REG. It also blocks any 356 * potential recursion. 357 */ 358 if (reg == IXGBE_STATUS) { 359 ixgbe_remove_adapter(hw); 360 return; 361 } 362 value = ixgbe_read_reg(hw, IXGBE_STATUS); 363 if (value == IXGBE_FAILED_READ_REG) 364 ixgbe_remove_adapter(hw); 365 } 366 367 /** 368 * ixgbe_read_reg - Read from device register 369 * @hw: hw specific details 370 * @reg: offset of register to read 371 * 372 * Returns : value read or IXGBE_FAILED_READ_REG if removed 373 * 374 * This function is used to read device registers. It checks for device 375 * removal by confirming any read that returns all ones by checking the 376 * status register value for all ones. This function avoids reading from 377 * the hardware if a removal was previously detected in which case it 378 * returns IXGBE_FAILED_READ_REG (all ones). 379 */ 380 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 381 { 382 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); 383 u32 value; 384 385 if (ixgbe_removed(reg_addr)) 386 return IXGBE_FAILED_READ_REG; 387 if (unlikely(hw->phy.nw_mng_if_sel & 388 IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) { 389 struct ixgbe_adapter *adapter; 390 int i; 391 392 for (i = 0; i < 200; ++i) { 393 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 394 if (likely(!value)) 395 goto writes_completed; 396 if (value == IXGBE_FAILED_READ_REG) { 397 ixgbe_remove_adapter(hw); 398 return IXGBE_FAILED_READ_REG; 399 } 400 udelay(5); 401 } 402 403 adapter = hw->back; 404 e_warn(hw, "register writes incomplete %08x\n", value); 405 } 406 407 writes_completed: 408 value = readl(reg_addr + reg); 409 if (unlikely(value == IXGBE_FAILED_READ_REG)) 410 ixgbe_check_remove(hw, reg); 411 return value; 412 } 413 414 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 415 { 416 u16 value; 417 418 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 419 if (value == IXGBE_FAILED_READ_CFG_WORD) { 420 ixgbe_remove_adapter(hw); 421 return true; 422 } 423 return false; 424 } 425 426 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 427 { 428 struct ixgbe_adapter *adapter = hw->back; 429 u16 value; 430 431 if (ixgbe_removed(hw->hw_addr)) 432 return IXGBE_FAILED_READ_CFG_WORD; 433 pci_read_config_word(adapter->pdev, reg, &value); 434 if (value == IXGBE_FAILED_READ_CFG_WORD && 435 ixgbe_check_cfg_remove(hw, adapter->pdev)) 436 return IXGBE_FAILED_READ_CFG_WORD; 437 return value; 438 } 439 440 #ifdef CONFIG_PCI_IOV 441 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 442 { 443 struct ixgbe_adapter *adapter = hw->back; 444 u32 value; 445 446 if (ixgbe_removed(hw->hw_addr)) 447 return IXGBE_FAILED_READ_CFG_DWORD; 448 pci_read_config_dword(adapter->pdev, reg, &value); 449 if (value == IXGBE_FAILED_READ_CFG_DWORD && 450 ixgbe_check_cfg_remove(hw, adapter->pdev)) 451 return IXGBE_FAILED_READ_CFG_DWORD; 452 return value; 453 } 454 #endif /* CONFIG_PCI_IOV */ 455 456 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 457 { 458 struct ixgbe_adapter *adapter = hw->back; 459 460 if (ixgbe_removed(hw->hw_addr)) 461 return; 462 pci_write_config_word(adapter->pdev, reg, value); 463 } 464 465 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 466 { 467 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 468 469 /* flush memory to make sure state is correct before next watchdog */ 470 smp_mb__before_atomic(); 471 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 472 } 473 474 struct ixgbe_reg_info { 475 u32 ofs; 476 char *name; 477 }; 478 479 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 480 481 /* General Registers */ 482 {IXGBE_CTRL, "CTRL"}, 483 {IXGBE_STATUS, "STATUS"}, 484 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 485 486 /* Interrupt Registers */ 487 {IXGBE_EICR, "EICR"}, 488 489 /* RX Registers */ 490 {IXGBE_SRRCTL(0), "SRRCTL"}, 491 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 492 {IXGBE_RDLEN(0), "RDLEN"}, 493 {IXGBE_RDH(0), "RDH"}, 494 {IXGBE_RDT(0), "RDT"}, 495 {IXGBE_RXDCTL(0), "RXDCTL"}, 496 {IXGBE_RDBAL(0), "RDBAL"}, 497 {IXGBE_RDBAH(0), "RDBAH"}, 498 499 /* TX Registers */ 500 {IXGBE_TDBAL(0), "TDBAL"}, 501 {IXGBE_TDBAH(0), "TDBAH"}, 502 {IXGBE_TDLEN(0), "TDLEN"}, 503 {IXGBE_TDH(0), "TDH"}, 504 {IXGBE_TDT(0), "TDT"}, 505 {IXGBE_TXDCTL(0), "TXDCTL"}, 506 507 /* List Terminator */ 508 { .name = NULL } 509 }; 510 511 512 /* 513 * ixgbe_regdump - register printout routine 514 */ 515 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 516 { 517 int i; 518 char rname[16]; 519 u32 regs[64]; 520 521 switch (reginfo->ofs) { 522 case IXGBE_SRRCTL(0): 523 for (i = 0; i < 64; i++) 524 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 525 break; 526 case IXGBE_DCA_RXCTRL(0): 527 for (i = 0; i < 64; i++) 528 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 529 break; 530 case IXGBE_RDLEN(0): 531 for (i = 0; i < 64; i++) 532 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 533 break; 534 case IXGBE_RDH(0): 535 for (i = 0; i < 64; i++) 536 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 537 break; 538 case IXGBE_RDT(0): 539 for (i = 0; i < 64; i++) 540 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 541 break; 542 case IXGBE_RXDCTL(0): 543 for (i = 0; i < 64; i++) 544 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 545 break; 546 case IXGBE_RDBAL(0): 547 for (i = 0; i < 64; i++) 548 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 549 break; 550 case IXGBE_RDBAH(0): 551 for (i = 0; i < 64; i++) 552 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 553 break; 554 case IXGBE_TDBAL(0): 555 for (i = 0; i < 64; i++) 556 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 557 break; 558 case IXGBE_TDBAH(0): 559 for (i = 0; i < 64; i++) 560 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 561 break; 562 case IXGBE_TDLEN(0): 563 for (i = 0; i < 64; i++) 564 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 565 break; 566 case IXGBE_TDH(0): 567 for (i = 0; i < 64; i++) 568 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 569 break; 570 case IXGBE_TDT(0): 571 for (i = 0; i < 64; i++) 572 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 573 break; 574 case IXGBE_TXDCTL(0): 575 for (i = 0; i < 64; i++) 576 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 577 break; 578 default: 579 pr_info("%-15s %08x\n", 580 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 581 return; 582 } 583 584 i = 0; 585 while (i < 64) { 586 int j; 587 char buf[9 * 8 + 1]; 588 char *p = buf; 589 590 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 591 for (j = 0; j < 8; j++) 592 p += sprintf(p, " %08x", regs[i++]); 593 pr_err("%-15s%s\n", rname, buf); 594 } 595 596 } 597 598 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 599 { 600 struct ixgbe_tx_buffer *tx_buffer; 601 602 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 603 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 604 n, ring->next_to_use, ring->next_to_clean, 605 (u64)dma_unmap_addr(tx_buffer, dma), 606 dma_unmap_len(tx_buffer, len), 607 tx_buffer->next_to_watch, 608 (u64)tx_buffer->time_stamp); 609 } 610 611 /* 612 * ixgbe_dump - Print registers, tx-rings and rx-rings 613 */ 614 static void ixgbe_dump(struct ixgbe_adapter *adapter) 615 { 616 struct net_device *netdev = adapter->netdev; 617 struct ixgbe_hw *hw = &adapter->hw; 618 struct ixgbe_reg_info *reginfo; 619 int n = 0; 620 struct ixgbe_ring *ring; 621 struct ixgbe_tx_buffer *tx_buffer; 622 union ixgbe_adv_tx_desc *tx_desc; 623 struct my_u0 { u64 a; u64 b; } *u0; 624 struct ixgbe_ring *rx_ring; 625 union ixgbe_adv_rx_desc *rx_desc; 626 struct ixgbe_rx_buffer *rx_buffer_info; 627 int i = 0; 628 629 if (!netif_msg_hw(adapter)) 630 return; 631 632 /* Print netdevice Info */ 633 if (netdev) { 634 dev_info(&adapter->pdev->dev, "Net device Info\n"); 635 pr_info("Device Name state " 636 "trans_start\n"); 637 pr_info("%-15s %016lX %016lX\n", 638 netdev->name, 639 netdev->state, 640 dev_trans_start(netdev)); 641 } 642 643 /* Print Registers */ 644 dev_info(&adapter->pdev->dev, "Register Dump\n"); 645 pr_info(" Register Name Value\n"); 646 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 647 reginfo->name; reginfo++) { 648 ixgbe_regdump(hw, reginfo); 649 } 650 651 /* Print TX Ring Summary */ 652 if (!netdev || !netif_running(netdev)) 653 return; 654 655 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 656 pr_info(" %s %s %s %s\n", 657 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 658 "leng", "ntw", "timestamp"); 659 for (n = 0; n < adapter->num_tx_queues; n++) { 660 ring = adapter->tx_ring[n]; 661 ixgbe_print_buffer(ring, n); 662 } 663 664 for (n = 0; n < adapter->num_xdp_queues; n++) { 665 ring = adapter->xdp_ring[n]; 666 ixgbe_print_buffer(ring, n); 667 } 668 669 /* Print TX Rings */ 670 if (!netif_msg_tx_done(adapter)) 671 goto rx_ring_summary; 672 673 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 674 675 /* Transmit Descriptor Formats 676 * 677 * 82598 Advanced Transmit Descriptor 678 * +--------------------------------------------------------------+ 679 * 0 | Buffer Address [63:0] | 680 * +--------------------------------------------------------------+ 681 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 682 * +--------------------------------------------------------------+ 683 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 684 * 685 * 82598 Advanced Transmit Descriptor (Write-Back Format) 686 * +--------------------------------------------------------------+ 687 * 0 | RSV [63:0] | 688 * +--------------------------------------------------------------+ 689 * 8 | RSV | STA | NXTSEQ | 690 * +--------------------------------------------------------------+ 691 * 63 36 35 32 31 0 692 * 693 * 82599+ Advanced Transmit Descriptor 694 * +--------------------------------------------------------------+ 695 * 0 | Buffer Address [63:0] | 696 * +--------------------------------------------------------------+ 697 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 698 * +--------------------------------------------------------------+ 699 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 700 * 701 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 702 * +--------------------------------------------------------------+ 703 * 0 | RSV [63:0] | 704 * +--------------------------------------------------------------+ 705 * 8 | RSV | STA | RSV | 706 * +--------------------------------------------------------------+ 707 * 63 36 35 32 31 0 708 */ 709 710 for (n = 0; n < adapter->num_tx_queues; n++) { 711 ring = adapter->tx_ring[n]; 712 pr_info("------------------------------------\n"); 713 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 714 pr_info("------------------------------------\n"); 715 pr_info("%s%s %s %s %s %s\n", 716 "T [desc] [address 63:0 ] ", 717 "[PlPOIdStDDt Ln] [bi->dma ] ", 718 "leng", "ntw", "timestamp", "bi->skb"); 719 720 for (i = 0; ring->desc && (i < ring->count); i++) { 721 tx_desc = IXGBE_TX_DESC(ring, i); 722 tx_buffer = &ring->tx_buffer_info[i]; 723 u0 = (struct my_u0 *)tx_desc; 724 if (dma_unmap_len(tx_buffer, len) > 0) { 725 const char *ring_desc; 726 727 if (i == ring->next_to_use && 728 i == ring->next_to_clean) 729 ring_desc = " NTC/U"; 730 else if (i == ring->next_to_use) 731 ring_desc = " NTU"; 732 else if (i == ring->next_to_clean) 733 ring_desc = " NTC"; 734 else 735 ring_desc = ""; 736 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 737 i, 738 le64_to_cpu(u0->a), 739 le64_to_cpu(u0->b), 740 (u64)dma_unmap_addr(tx_buffer, dma), 741 dma_unmap_len(tx_buffer, len), 742 tx_buffer->next_to_watch, 743 (u64)tx_buffer->time_stamp, 744 tx_buffer->skb, 745 ring_desc); 746 747 if (netif_msg_pktdata(adapter) && 748 tx_buffer->skb) 749 print_hex_dump(KERN_INFO, "", 750 DUMP_PREFIX_ADDRESS, 16, 1, 751 tx_buffer->skb->data, 752 dma_unmap_len(tx_buffer, len), 753 true); 754 } 755 } 756 } 757 758 /* Print RX Rings Summary */ 759 rx_ring_summary: 760 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 761 pr_info("Queue [NTU] [NTC]\n"); 762 for (n = 0; n < adapter->num_rx_queues; n++) { 763 rx_ring = adapter->rx_ring[n]; 764 pr_info("%5d %5X %5X\n", 765 n, rx_ring->next_to_use, rx_ring->next_to_clean); 766 } 767 768 /* Print RX Rings */ 769 if (!netif_msg_rx_status(adapter)) 770 return; 771 772 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 773 774 /* Receive Descriptor Formats 775 * 776 * 82598 Advanced Receive Descriptor (Read) Format 777 * 63 1 0 778 * +-----------------------------------------------------+ 779 * 0 | Packet Buffer Address [63:1] |A0/NSE| 780 * +----------------------------------------------+------+ 781 * 8 | Header Buffer Address [63:1] | DD | 782 * +-----------------------------------------------------+ 783 * 784 * 785 * 82598 Advanced Receive Descriptor (Write-Back) Format 786 * 787 * 63 48 47 32 31 30 21 20 16 15 4 3 0 788 * +------------------------------------------------------+ 789 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 790 * | Packet | IP | | | | Type | Type | 791 * | Checksum | Ident | | | | | | 792 * +------------------------------------------------------+ 793 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 794 * +------------------------------------------------------+ 795 * 63 48 47 32 31 20 19 0 796 * 797 * 82599+ Advanced Receive Descriptor (Read) Format 798 * 63 1 0 799 * +-----------------------------------------------------+ 800 * 0 | Packet Buffer Address [63:1] |A0/NSE| 801 * +----------------------------------------------+------+ 802 * 8 | Header Buffer Address [63:1] | DD | 803 * +-----------------------------------------------------+ 804 * 805 * 806 * 82599+ Advanced Receive Descriptor (Write-Back) Format 807 * 808 * 63 48 47 32 31 30 21 20 17 16 4 3 0 809 * +------------------------------------------------------+ 810 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 811 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 812 * |/ Flow Dir Flt ID | | | | | | 813 * +------------------------------------------------------+ 814 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 815 * +------------------------------------------------------+ 816 * 63 48 47 32 31 20 19 0 817 */ 818 819 for (n = 0; n < adapter->num_rx_queues; n++) { 820 rx_ring = adapter->rx_ring[n]; 821 pr_info("------------------------------------\n"); 822 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 823 pr_info("------------------------------------\n"); 824 pr_info("%s%s%s\n", 825 "R [desc] [ PktBuf A0] ", 826 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 827 "<-- Adv Rx Read format"); 828 pr_info("%s%s%s\n", 829 "RWB[desc] [PcsmIpSHl PtRs] ", 830 "[vl er S cks ln] ---------------- [bi->skb ] ", 831 "<-- Adv Rx Write-Back format"); 832 833 for (i = 0; i < rx_ring->count; i++) { 834 const char *ring_desc; 835 836 if (i == rx_ring->next_to_use) 837 ring_desc = " NTU"; 838 else if (i == rx_ring->next_to_clean) 839 ring_desc = " NTC"; 840 else 841 ring_desc = ""; 842 843 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 844 rx_desc = IXGBE_RX_DESC(rx_ring, i); 845 u0 = (struct my_u0 *)rx_desc; 846 if (rx_desc->wb.upper.length) { 847 /* Descriptor Done */ 848 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 849 i, 850 le64_to_cpu(u0->a), 851 le64_to_cpu(u0->b), 852 rx_buffer_info->skb, 853 ring_desc); 854 } else { 855 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 856 i, 857 le64_to_cpu(u0->a), 858 le64_to_cpu(u0->b), 859 (u64)rx_buffer_info->dma, 860 rx_buffer_info->skb, 861 ring_desc); 862 863 if (netif_msg_pktdata(adapter) && 864 rx_buffer_info->dma) { 865 print_hex_dump(KERN_INFO, "", 866 DUMP_PREFIX_ADDRESS, 16, 1, 867 page_address(rx_buffer_info->page) + 868 rx_buffer_info->page_offset, 869 ixgbe_rx_bufsz(rx_ring), true); 870 } 871 } 872 } 873 } 874 } 875 876 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 877 { 878 u32 ctrl_ext; 879 880 /* Let firmware take over control of h/w */ 881 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 883 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 884 } 885 886 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 887 { 888 u32 ctrl_ext; 889 890 /* Let firmware know the driver has taken over */ 891 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 892 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 893 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 894 } 895 896 /** 897 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 898 * @adapter: pointer to adapter struct 899 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 900 * @queue: queue to map the corresponding interrupt to 901 * @msix_vector: the vector to map to the corresponding queue 902 * 903 */ 904 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 905 u8 queue, u8 msix_vector) 906 { 907 u32 ivar, index; 908 struct ixgbe_hw *hw = &adapter->hw; 909 switch (hw->mac.type) { 910 case ixgbe_mac_82598EB: 911 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 912 if (direction == -1) 913 direction = 0; 914 index = (((direction * 64) + queue) >> 2) & 0x1F; 915 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 916 ivar &= ~(0xFF << (8 * (queue & 0x3))); 917 ivar |= (msix_vector << (8 * (queue & 0x3))); 918 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 919 break; 920 case ixgbe_mac_82599EB: 921 case ixgbe_mac_X540: 922 case ixgbe_mac_X550: 923 case ixgbe_mac_X550EM_x: 924 case ixgbe_mac_x550em_a: 925 if (direction == -1) { 926 /* other causes */ 927 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 928 index = ((queue & 1) * 8); 929 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 930 ivar &= ~(0xFF << index); 931 ivar |= (msix_vector << index); 932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 933 break; 934 } else { 935 /* tx or rx causes */ 936 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 937 index = ((16 * (queue & 1)) + (8 * direction)); 938 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 939 ivar &= ~(0xFF << index); 940 ivar |= (msix_vector << index); 941 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 942 break; 943 } 944 default: 945 break; 946 } 947 } 948 949 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 950 u64 qmask) 951 { 952 u32 mask; 953 954 switch (adapter->hw.mac.type) { 955 case ixgbe_mac_82598EB: 956 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 957 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 958 break; 959 case ixgbe_mac_82599EB: 960 case ixgbe_mac_X540: 961 case ixgbe_mac_X550: 962 case ixgbe_mac_X550EM_x: 963 case ixgbe_mac_x550em_a: 964 mask = (qmask & 0xFFFFFFFF); 965 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 966 mask = (qmask >> 32); 967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 968 break; 969 default: 970 break; 971 } 972 } 973 974 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 975 { 976 struct ixgbe_hw *hw = &adapter->hw; 977 struct ixgbe_hw_stats *hwstats = &adapter->stats; 978 int i; 979 u32 data; 980 981 if ((hw->fc.current_mode != ixgbe_fc_full) && 982 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 983 return; 984 985 switch (hw->mac.type) { 986 case ixgbe_mac_82598EB: 987 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 988 break; 989 default: 990 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 991 } 992 hwstats->lxoffrxc += data; 993 994 /* refill credits (no tx hang) if we received xoff */ 995 if (!data) 996 return; 997 998 for (i = 0; i < adapter->num_tx_queues; i++) 999 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1000 &adapter->tx_ring[i]->state); 1001 1002 for (i = 0; i < adapter->num_xdp_queues; i++) 1003 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1004 &adapter->xdp_ring[i]->state); 1005 } 1006 1007 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1008 { 1009 struct ixgbe_hw *hw = &adapter->hw; 1010 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1011 u32 xoff[8] = {0}; 1012 u8 tc; 1013 int i; 1014 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1015 1016 if (adapter->ixgbe_ieee_pfc) 1017 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1018 1019 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1020 ixgbe_update_xoff_rx_lfc(adapter); 1021 return; 1022 } 1023 1024 /* update stats for each tc, only valid with PFC enabled */ 1025 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1026 u32 pxoffrxc; 1027 1028 switch (hw->mac.type) { 1029 case ixgbe_mac_82598EB: 1030 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1031 break; 1032 default: 1033 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1034 } 1035 hwstats->pxoffrxc[i] += pxoffrxc; 1036 /* Get the TC for given UP */ 1037 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1038 xoff[tc] += pxoffrxc; 1039 } 1040 1041 /* disarm tx queues that have received xoff frames */ 1042 for (i = 0; i < adapter->num_tx_queues; i++) { 1043 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1044 1045 tc = tx_ring->dcb_tc; 1046 if (xoff[tc]) 1047 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1048 } 1049 1050 for (i = 0; i < adapter->num_xdp_queues; i++) { 1051 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1052 1053 tc = xdp_ring->dcb_tc; 1054 if (xoff[tc]) 1055 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1056 } 1057 } 1058 1059 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1060 { 1061 return ring->stats.packets; 1062 } 1063 1064 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1065 { 1066 struct ixgbe_adapter *adapter; 1067 struct ixgbe_hw *hw; 1068 u32 head, tail; 1069 1070 if (ring->l2_accel_priv) 1071 adapter = ring->l2_accel_priv->real_adapter; 1072 else 1073 adapter = netdev_priv(ring->netdev); 1074 1075 hw = &adapter->hw; 1076 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); 1077 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); 1078 1079 if (head != tail) 1080 return (head < tail) ? 1081 tail - head : (tail + ring->count - head); 1082 1083 return 0; 1084 } 1085 1086 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1087 { 1088 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1089 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1090 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1091 1092 clear_check_for_tx_hang(tx_ring); 1093 1094 /* 1095 * Check for a hung queue, but be thorough. This verifies 1096 * that a transmit has been completed since the previous 1097 * check AND there is at least one packet pending. The 1098 * ARMED bit is set to indicate a potential hang. The 1099 * bit is cleared if a pause frame is received to remove 1100 * false hang detection due to PFC or 802.3x frames. By 1101 * requiring this to fail twice we avoid races with 1102 * pfc clearing the ARMED bit and conditions where we 1103 * run the check_tx_hang logic with a transmit completion 1104 * pending but without time to complete it yet. 1105 */ 1106 if (tx_done_old == tx_done && tx_pending) 1107 /* make sure it is true for two checks in a row */ 1108 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1109 &tx_ring->state); 1110 /* update completed stats and continue */ 1111 tx_ring->tx_stats.tx_done_old = tx_done; 1112 /* reset the countdown */ 1113 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1114 1115 return false; 1116 } 1117 1118 /** 1119 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1120 * @adapter: driver private struct 1121 **/ 1122 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1123 { 1124 1125 /* Do the reset outside of interrupt context */ 1126 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1127 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1128 e_warn(drv, "initiating reset due to tx timeout\n"); 1129 ixgbe_service_event_schedule(adapter); 1130 } 1131 } 1132 1133 /** 1134 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1135 **/ 1136 static int ixgbe_tx_maxrate(struct net_device *netdev, 1137 int queue_index, u32 maxrate) 1138 { 1139 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1140 struct ixgbe_hw *hw = &adapter->hw; 1141 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1142 1143 if (!maxrate) 1144 return 0; 1145 1146 /* Calculate the rate factor values to set */ 1147 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1148 bcnrc_val /= maxrate; 1149 1150 /* clear everything but the rate factor */ 1151 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1152 IXGBE_RTTBCNRC_RF_DEC_MASK; 1153 1154 /* enable the rate scheduler */ 1155 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1156 1157 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1158 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1159 1160 return 0; 1161 } 1162 1163 /** 1164 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1165 * @q_vector: structure containing interrupt and ring information 1166 * @tx_ring: tx ring to clean 1167 * @napi_budget: Used to determine if we are in netpoll 1168 **/ 1169 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1170 struct ixgbe_ring *tx_ring, int napi_budget) 1171 { 1172 struct ixgbe_adapter *adapter = q_vector->adapter; 1173 struct ixgbe_tx_buffer *tx_buffer; 1174 union ixgbe_adv_tx_desc *tx_desc; 1175 unsigned int total_bytes = 0, total_packets = 0; 1176 unsigned int budget = q_vector->tx.work_limit; 1177 unsigned int i = tx_ring->next_to_clean; 1178 1179 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1180 return true; 1181 1182 tx_buffer = &tx_ring->tx_buffer_info[i]; 1183 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1184 i -= tx_ring->count; 1185 1186 do { 1187 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1188 1189 /* if next_to_watch is not set then there is no work pending */ 1190 if (!eop_desc) 1191 break; 1192 1193 /* prevent any other reads prior to eop_desc */ 1194 read_barrier_depends(); 1195 1196 /* if DD is not set pending work has not been completed */ 1197 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1198 break; 1199 1200 /* clear next_to_watch to prevent false hangs */ 1201 tx_buffer->next_to_watch = NULL; 1202 1203 /* update the statistics for this packet */ 1204 total_bytes += tx_buffer->bytecount; 1205 total_packets += tx_buffer->gso_segs; 1206 1207 /* free the skb */ 1208 if (ring_is_xdp(tx_ring)) 1209 page_frag_free(tx_buffer->data); 1210 else 1211 napi_consume_skb(tx_buffer->skb, napi_budget); 1212 1213 /* unmap skb header data */ 1214 dma_unmap_single(tx_ring->dev, 1215 dma_unmap_addr(tx_buffer, dma), 1216 dma_unmap_len(tx_buffer, len), 1217 DMA_TO_DEVICE); 1218 1219 /* clear tx_buffer data */ 1220 dma_unmap_len_set(tx_buffer, len, 0); 1221 1222 /* unmap remaining buffers */ 1223 while (tx_desc != eop_desc) { 1224 tx_buffer++; 1225 tx_desc++; 1226 i++; 1227 if (unlikely(!i)) { 1228 i -= tx_ring->count; 1229 tx_buffer = tx_ring->tx_buffer_info; 1230 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1231 } 1232 1233 /* unmap any remaining paged data */ 1234 if (dma_unmap_len(tx_buffer, len)) { 1235 dma_unmap_page(tx_ring->dev, 1236 dma_unmap_addr(tx_buffer, dma), 1237 dma_unmap_len(tx_buffer, len), 1238 DMA_TO_DEVICE); 1239 dma_unmap_len_set(tx_buffer, len, 0); 1240 } 1241 } 1242 1243 /* move us one more past the eop_desc for start of next pkt */ 1244 tx_buffer++; 1245 tx_desc++; 1246 i++; 1247 if (unlikely(!i)) { 1248 i -= tx_ring->count; 1249 tx_buffer = tx_ring->tx_buffer_info; 1250 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1251 } 1252 1253 /* issue prefetch for next Tx descriptor */ 1254 prefetch(tx_desc); 1255 1256 /* update budget accounting */ 1257 budget--; 1258 } while (likely(budget)); 1259 1260 i += tx_ring->count; 1261 tx_ring->next_to_clean = i; 1262 u64_stats_update_begin(&tx_ring->syncp); 1263 tx_ring->stats.bytes += total_bytes; 1264 tx_ring->stats.packets += total_packets; 1265 u64_stats_update_end(&tx_ring->syncp); 1266 q_vector->tx.total_bytes += total_bytes; 1267 q_vector->tx.total_packets += total_packets; 1268 1269 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1270 /* schedule immediate reset if we believe we hung */ 1271 struct ixgbe_hw *hw = &adapter->hw; 1272 e_err(drv, "Detected Tx Unit Hang %s\n" 1273 " Tx Queue <%d>\n" 1274 " TDH, TDT <%x>, <%x>\n" 1275 " next_to_use <%x>\n" 1276 " next_to_clean <%x>\n" 1277 "tx_buffer_info[next_to_clean]\n" 1278 " time_stamp <%lx>\n" 1279 " jiffies <%lx>\n", 1280 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1281 tx_ring->queue_index, 1282 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1283 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1284 tx_ring->next_to_use, i, 1285 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1286 1287 if (!ring_is_xdp(tx_ring)) 1288 netif_stop_subqueue(tx_ring->netdev, 1289 tx_ring->queue_index); 1290 1291 e_info(probe, 1292 "tx hang %d detected on queue %d, resetting adapter\n", 1293 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1294 1295 /* schedule immediate reset if we believe we hung */ 1296 ixgbe_tx_timeout_reset(adapter); 1297 1298 /* the adapter is about to reset, no point in enabling stuff */ 1299 return true; 1300 } 1301 1302 if (ring_is_xdp(tx_ring)) 1303 return !!budget; 1304 1305 netdev_tx_completed_queue(txring_txq(tx_ring), 1306 total_packets, total_bytes); 1307 1308 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1309 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1310 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1311 /* Make sure that anybody stopping the queue after this 1312 * sees the new next_to_clean. 1313 */ 1314 smp_mb(); 1315 if (__netif_subqueue_stopped(tx_ring->netdev, 1316 tx_ring->queue_index) 1317 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1318 netif_wake_subqueue(tx_ring->netdev, 1319 tx_ring->queue_index); 1320 ++tx_ring->tx_stats.restart_queue; 1321 } 1322 } 1323 1324 return !!budget; 1325 } 1326 1327 #ifdef CONFIG_IXGBE_DCA 1328 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1329 struct ixgbe_ring *tx_ring, 1330 int cpu) 1331 { 1332 struct ixgbe_hw *hw = &adapter->hw; 1333 u32 txctrl = 0; 1334 u16 reg_offset; 1335 1336 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1337 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1338 1339 switch (hw->mac.type) { 1340 case ixgbe_mac_82598EB: 1341 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1342 break; 1343 case ixgbe_mac_82599EB: 1344 case ixgbe_mac_X540: 1345 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1346 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1347 break; 1348 default: 1349 /* for unknown hardware do not write register */ 1350 return; 1351 } 1352 1353 /* 1354 * We can enable relaxed ordering for reads, but not writes when 1355 * DCA is enabled. This is due to a known issue in some chipsets 1356 * which will cause the DCA tag to be cleared. 1357 */ 1358 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1359 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1360 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1361 1362 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1363 } 1364 1365 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1366 struct ixgbe_ring *rx_ring, 1367 int cpu) 1368 { 1369 struct ixgbe_hw *hw = &adapter->hw; 1370 u32 rxctrl = 0; 1371 u8 reg_idx = rx_ring->reg_idx; 1372 1373 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1374 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1375 1376 switch (hw->mac.type) { 1377 case ixgbe_mac_82599EB: 1378 case ixgbe_mac_X540: 1379 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1380 break; 1381 default: 1382 break; 1383 } 1384 1385 /* 1386 * We can enable relaxed ordering for reads, but not writes when 1387 * DCA is enabled. This is due to a known issue in some chipsets 1388 * which will cause the DCA tag to be cleared. 1389 */ 1390 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1391 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1392 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1393 1394 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1395 } 1396 1397 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1398 { 1399 struct ixgbe_adapter *adapter = q_vector->adapter; 1400 struct ixgbe_ring *ring; 1401 int cpu = get_cpu(); 1402 1403 if (q_vector->cpu == cpu) 1404 goto out_no_update; 1405 1406 ixgbe_for_each_ring(ring, q_vector->tx) 1407 ixgbe_update_tx_dca(adapter, ring, cpu); 1408 1409 ixgbe_for_each_ring(ring, q_vector->rx) 1410 ixgbe_update_rx_dca(adapter, ring, cpu); 1411 1412 q_vector->cpu = cpu; 1413 out_no_update: 1414 put_cpu(); 1415 } 1416 1417 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1418 { 1419 int i; 1420 1421 /* always use CB2 mode, difference is masked in the CB driver */ 1422 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1424 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1425 else 1426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1427 IXGBE_DCA_CTRL_DCA_DISABLE); 1428 1429 for (i = 0; i < adapter->num_q_vectors; i++) { 1430 adapter->q_vector[i]->cpu = -1; 1431 ixgbe_update_dca(adapter->q_vector[i]); 1432 } 1433 } 1434 1435 static int __ixgbe_notify_dca(struct device *dev, void *data) 1436 { 1437 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1438 unsigned long event = *(unsigned long *)data; 1439 1440 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1441 return 0; 1442 1443 switch (event) { 1444 case DCA_PROVIDER_ADD: 1445 /* if we're already enabled, don't do it again */ 1446 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1447 break; 1448 if (dca_add_requester(dev) == 0) { 1449 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1450 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1451 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1452 break; 1453 } 1454 /* Fall Through since DCA is disabled. */ 1455 case DCA_PROVIDER_REMOVE: 1456 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1457 dca_remove_requester(dev); 1458 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1459 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1460 IXGBE_DCA_CTRL_DCA_DISABLE); 1461 } 1462 break; 1463 } 1464 1465 return 0; 1466 } 1467 1468 #endif /* CONFIG_IXGBE_DCA */ 1469 1470 #define IXGBE_RSS_L4_TYPES_MASK \ 1471 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1472 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1473 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1474 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1475 1476 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1477 union ixgbe_adv_rx_desc *rx_desc, 1478 struct sk_buff *skb) 1479 { 1480 u16 rss_type; 1481 1482 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1483 return; 1484 1485 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1486 IXGBE_RXDADV_RSSTYPE_MASK; 1487 1488 if (!rss_type) 1489 return; 1490 1491 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1492 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1493 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1494 } 1495 1496 #ifdef IXGBE_FCOE 1497 /** 1498 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1499 * @ring: structure containing ring specific data 1500 * @rx_desc: advanced rx descriptor 1501 * 1502 * Returns : true if it is FCoE pkt 1503 */ 1504 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1505 union ixgbe_adv_rx_desc *rx_desc) 1506 { 1507 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1508 1509 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1510 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1511 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1512 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1513 } 1514 1515 #endif /* IXGBE_FCOE */ 1516 /** 1517 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1518 * @ring: structure containing ring specific data 1519 * @rx_desc: current Rx descriptor being processed 1520 * @skb: skb currently being received and modified 1521 **/ 1522 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1523 union ixgbe_adv_rx_desc *rx_desc, 1524 struct sk_buff *skb) 1525 { 1526 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1527 bool encap_pkt = false; 1528 1529 skb_checksum_none_assert(skb); 1530 1531 /* Rx csum disabled */ 1532 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1533 return; 1534 1535 /* check for VXLAN and Geneve packets */ 1536 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1537 encap_pkt = true; 1538 skb->encapsulation = 1; 1539 } 1540 1541 /* if IP and error */ 1542 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1543 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1544 ring->rx_stats.csum_err++; 1545 return; 1546 } 1547 1548 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1549 return; 1550 1551 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1552 /* 1553 * 82599 errata, UDP frames with a 0 checksum can be marked as 1554 * checksum errors. 1555 */ 1556 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1557 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1558 return; 1559 1560 ring->rx_stats.csum_err++; 1561 return; 1562 } 1563 1564 /* It must be a TCP or UDP packet with a valid checksum */ 1565 skb->ip_summed = CHECKSUM_UNNECESSARY; 1566 if (encap_pkt) { 1567 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1568 return; 1569 1570 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1571 skb->ip_summed = CHECKSUM_NONE; 1572 return; 1573 } 1574 /* If we checked the outer header let the stack know */ 1575 skb->csum_level = 1; 1576 } 1577 } 1578 1579 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1580 { 1581 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1582 } 1583 1584 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1585 struct ixgbe_rx_buffer *bi) 1586 { 1587 struct page *page = bi->page; 1588 dma_addr_t dma; 1589 1590 /* since we are recycling buffers we should seldom need to alloc */ 1591 if (likely(page)) 1592 return true; 1593 1594 /* alloc new page for storage */ 1595 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1596 if (unlikely(!page)) { 1597 rx_ring->rx_stats.alloc_rx_page_failed++; 1598 return false; 1599 } 1600 1601 /* map page for use */ 1602 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1603 ixgbe_rx_pg_size(rx_ring), 1604 DMA_FROM_DEVICE, 1605 IXGBE_RX_DMA_ATTR); 1606 1607 /* 1608 * if mapping failed free memory back to system since 1609 * there isn't much point in holding memory we can't use 1610 */ 1611 if (dma_mapping_error(rx_ring->dev, dma)) { 1612 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1613 1614 rx_ring->rx_stats.alloc_rx_page_failed++; 1615 return false; 1616 } 1617 1618 bi->dma = dma; 1619 bi->page = page; 1620 bi->page_offset = ixgbe_rx_offset(rx_ring); 1621 bi->pagecnt_bias = 1; 1622 1623 return true; 1624 } 1625 1626 /** 1627 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1628 * @rx_ring: ring to place buffers on 1629 * @cleaned_count: number of buffers to replace 1630 **/ 1631 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1632 { 1633 union ixgbe_adv_rx_desc *rx_desc; 1634 struct ixgbe_rx_buffer *bi; 1635 u16 i = rx_ring->next_to_use; 1636 u16 bufsz; 1637 1638 /* nothing to do */ 1639 if (!cleaned_count) 1640 return; 1641 1642 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1643 bi = &rx_ring->rx_buffer_info[i]; 1644 i -= rx_ring->count; 1645 1646 bufsz = ixgbe_rx_bufsz(rx_ring); 1647 1648 do { 1649 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1650 break; 1651 1652 /* sync the buffer for use by the device */ 1653 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1654 bi->page_offset, bufsz, 1655 DMA_FROM_DEVICE); 1656 1657 /* 1658 * Refresh the desc even if buffer_addrs didn't change 1659 * because each write-back erases this info. 1660 */ 1661 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1662 1663 rx_desc++; 1664 bi++; 1665 i++; 1666 if (unlikely(!i)) { 1667 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1668 bi = rx_ring->rx_buffer_info; 1669 i -= rx_ring->count; 1670 } 1671 1672 /* clear the length for the next_to_use descriptor */ 1673 rx_desc->wb.upper.length = 0; 1674 1675 cleaned_count--; 1676 } while (cleaned_count); 1677 1678 i += rx_ring->count; 1679 1680 if (rx_ring->next_to_use != i) { 1681 rx_ring->next_to_use = i; 1682 1683 /* update next to alloc since we have filled the ring */ 1684 rx_ring->next_to_alloc = i; 1685 1686 /* Force memory writes to complete before letting h/w 1687 * know there are new descriptors to fetch. (Only 1688 * applicable for weak-ordered memory model archs, 1689 * such as IA-64). 1690 */ 1691 wmb(); 1692 writel(i, rx_ring->tail); 1693 } 1694 } 1695 1696 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1697 struct sk_buff *skb) 1698 { 1699 u16 hdr_len = skb_headlen(skb); 1700 1701 /* set gso_size to avoid messing up TCP MSS */ 1702 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1703 IXGBE_CB(skb)->append_cnt); 1704 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1705 } 1706 1707 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1708 struct sk_buff *skb) 1709 { 1710 /* if append_cnt is 0 then frame is not RSC */ 1711 if (!IXGBE_CB(skb)->append_cnt) 1712 return; 1713 1714 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1715 rx_ring->rx_stats.rsc_flush++; 1716 1717 ixgbe_set_rsc_gso_size(rx_ring, skb); 1718 1719 /* gso_size is computed using append_cnt so always clear it last */ 1720 IXGBE_CB(skb)->append_cnt = 0; 1721 } 1722 1723 /** 1724 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1725 * @rx_ring: rx descriptor ring packet is being transacted on 1726 * @rx_desc: pointer to the EOP Rx descriptor 1727 * @skb: pointer to current skb being populated 1728 * 1729 * This function checks the ring, descriptor, and packet information in 1730 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1731 * other fields within the skb. 1732 **/ 1733 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1734 union ixgbe_adv_rx_desc *rx_desc, 1735 struct sk_buff *skb) 1736 { 1737 struct net_device *dev = rx_ring->netdev; 1738 u32 flags = rx_ring->q_vector->adapter->flags; 1739 1740 ixgbe_update_rsc_stats(rx_ring, skb); 1741 1742 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1743 1744 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1745 1746 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1747 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1748 1749 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1750 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1751 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1752 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1753 } 1754 1755 skb_record_rx_queue(skb, rx_ring->queue_index); 1756 1757 skb->protocol = eth_type_trans(skb, dev); 1758 } 1759 1760 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1761 struct sk_buff *skb) 1762 { 1763 napi_gro_receive(&q_vector->napi, skb); 1764 } 1765 1766 /** 1767 * ixgbe_is_non_eop - process handling of non-EOP buffers 1768 * @rx_ring: Rx ring being processed 1769 * @rx_desc: Rx descriptor for current buffer 1770 * @skb: Current socket buffer containing buffer in progress 1771 * 1772 * This function updates next to clean. If the buffer is an EOP buffer 1773 * this function exits returning false, otherwise it will place the 1774 * sk_buff in the next buffer to be chained and return true indicating 1775 * that this is in fact a non-EOP buffer. 1776 **/ 1777 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1778 union ixgbe_adv_rx_desc *rx_desc, 1779 struct sk_buff *skb) 1780 { 1781 u32 ntc = rx_ring->next_to_clean + 1; 1782 1783 /* fetch, update, and store next to clean */ 1784 ntc = (ntc < rx_ring->count) ? ntc : 0; 1785 rx_ring->next_to_clean = ntc; 1786 1787 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1788 1789 /* update RSC append count if present */ 1790 if (ring_is_rsc_enabled(rx_ring)) { 1791 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1792 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1793 1794 if (unlikely(rsc_enabled)) { 1795 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1796 1797 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1798 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1799 1800 /* update ntc based on RSC value */ 1801 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1802 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1803 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1804 } 1805 } 1806 1807 /* if we are the last buffer then there is nothing else to do */ 1808 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1809 return false; 1810 1811 /* place skb in next buffer to be received */ 1812 rx_ring->rx_buffer_info[ntc].skb = skb; 1813 rx_ring->rx_stats.non_eop_descs++; 1814 1815 return true; 1816 } 1817 1818 /** 1819 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1820 * @rx_ring: rx descriptor ring packet is being transacted on 1821 * @skb: pointer to current skb being adjusted 1822 * 1823 * This function is an ixgbe specific version of __pskb_pull_tail. The 1824 * main difference between this version and the original function is that 1825 * this function can make several assumptions about the state of things 1826 * that allow for significant optimizations versus the standard function. 1827 * As a result we can do things like drop a frag and maintain an accurate 1828 * truesize for the skb. 1829 */ 1830 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1831 struct sk_buff *skb) 1832 { 1833 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1834 unsigned char *va; 1835 unsigned int pull_len; 1836 1837 /* 1838 * it is valid to use page_address instead of kmap since we are 1839 * working with pages allocated out of the lomem pool per 1840 * alloc_page(GFP_ATOMIC) 1841 */ 1842 va = skb_frag_address(frag); 1843 1844 /* 1845 * we need the header to contain the greater of either ETH_HLEN or 1846 * 60 bytes if the skb->len is less than 60 for skb_pad. 1847 */ 1848 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1849 1850 /* align pull length to size of long to optimize memcpy performance */ 1851 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1852 1853 /* update all of the pointers */ 1854 skb_frag_size_sub(frag, pull_len); 1855 frag->page_offset += pull_len; 1856 skb->data_len -= pull_len; 1857 skb->tail += pull_len; 1858 } 1859 1860 /** 1861 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1862 * @rx_ring: rx descriptor ring packet is being transacted on 1863 * @skb: pointer to current skb being updated 1864 * 1865 * This function provides a basic DMA sync up for the first fragment of an 1866 * skb. The reason for doing this is that the first fragment cannot be 1867 * unmapped until we have reached the end of packet descriptor for a buffer 1868 * chain. 1869 */ 1870 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1871 struct sk_buff *skb) 1872 { 1873 /* if the page was released unmap it, else just sync our portion */ 1874 if (unlikely(IXGBE_CB(skb)->page_released)) { 1875 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1876 ixgbe_rx_pg_size(rx_ring), 1877 DMA_FROM_DEVICE, 1878 IXGBE_RX_DMA_ATTR); 1879 } else { 1880 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1881 1882 dma_sync_single_range_for_cpu(rx_ring->dev, 1883 IXGBE_CB(skb)->dma, 1884 frag->page_offset, 1885 skb_frag_size(frag), 1886 DMA_FROM_DEVICE); 1887 } 1888 } 1889 1890 /** 1891 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1892 * @rx_ring: rx descriptor ring packet is being transacted on 1893 * @rx_desc: pointer to the EOP Rx descriptor 1894 * @skb: pointer to current skb being fixed 1895 * 1896 * Check if the skb is valid in the XDP case it will be an error pointer. 1897 * Return true in this case to abort processing and advance to next 1898 * descriptor. 1899 * 1900 * Check for corrupted packet headers caused by senders on the local L2 1901 * embedded NIC switch not setting up their Tx Descriptors right. These 1902 * should be very rare. 1903 * 1904 * Also address the case where we are pulling data in on pages only 1905 * and as such no data is present in the skb header. 1906 * 1907 * In addition if skb is not at least 60 bytes we need to pad it so that 1908 * it is large enough to qualify as a valid Ethernet frame. 1909 * 1910 * Returns true if an error was encountered and skb was freed. 1911 **/ 1912 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1913 union ixgbe_adv_rx_desc *rx_desc, 1914 struct sk_buff *skb) 1915 { 1916 struct net_device *netdev = rx_ring->netdev; 1917 1918 /* XDP packets use error pointer so abort at this point */ 1919 if (IS_ERR(skb)) 1920 return true; 1921 1922 /* verify that the packet does not have any known errors */ 1923 if (unlikely(ixgbe_test_staterr(rx_desc, 1924 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1925 !(netdev->features & NETIF_F_RXALL))) { 1926 dev_kfree_skb_any(skb); 1927 return true; 1928 } 1929 1930 /* place header in linear portion of buffer */ 1931 if (!skb_headlen(skb)) 1932 ixgbe_pull_tail(rx_ring, skb); 1933 1934 #ifdef IXGBE_FCOE 1935 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1936 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1937 return false; 1938 1939 #endif 1940 /* if eth_skb_pad returns an error the skb was freed */ 1941 if (eth_skb_pad(skb)) 1942 return true; 1943 1944 return false; 1945 } 1946 1947 /** 1948 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1949 * @rx_ring: rx descriptor ring to store buffers on 1950 * @old_buff: donor buffer to have page reused 1951 * 1952 * Synchronizes page for reuse by the adapter 1953 **/ 1954 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1955 struct ixgbe_rx_buffer *old_buff) 1956 { 1957 struct ixgbe_rx_buffer *new_buff; 1958 u16 nta = rx_ring->next_to_alloc; 1959 1960 new_buff = &rx_ring->rx_buffer_info[nta]; 1961 1962 /* update, and store next to alloc */ 1963 nta++; 1964 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1965 1966 /* Transfer page from old buffer to new buffer. 1967 * Move each member individually to avoid possible store 1968 * forwarding stalls and unnecessary copy of skb. 1969 */ 1970 new_buff->dma = old_buff->dma; 1971 new_buff->page = old_buff->page; 1972 new_buff->page_offset = old_buff->page_offset; 1973 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1974 } 1975 1976 static inline bool ixgbe_page_is_reserved(struct page *page) 1977 { 1978 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1979 } 1980 1981 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1982 { 1983 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1984 struct page *page = rx_buffer->page; 1985 1986 /* avoid re-using remote pages */ 1987 if (unlikely(ixgbe_page_is_reserved(page))) 1988 return false; 1989 1990 #if (PAGE_SIZE < 8192) 1991 /* if we are only owner of page we can reuse it */ 1992 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 1993 return false; 1994 #else 1995 /* The last offset is a bit aggressive in that we assume the 1996 * worst case of FCoE being enabled and using a 3K buffer. 1997 * However this should have minimal impact as the 1K extra is 1998 * still less than one buffer in size. 1999 */ 2000 #define IXGBE_LAST_OFFSET \ 2001 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2002 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2003 return false; 2004 #endif 2005 2006 /* If we have drained the page fragment pool we need to update 2007 * the pagecnt_bias and page count so that we fully restock the 2008 * number of references the driver holds. 2009 */ 2010 if (unlikely(!pagecnt_bias)) { 2011 page_ref_add(page, USHRT_MAX); 2012 rx_buffer->pagecnt_bias = USHRT_MAX; 2013 } 2014 2015 return true; 2016 } 2017 2018 /** 2019 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2020 * @rx_ring: rx descriptor ring to transact packets on 2021 * @rx_buffer: buffer containing page to add 2022 * @rx_desc: descriptor containing length of buffer written by hardware 2023 * @skb: sk_buff to place the data into 2024 * 2025 * This function will add the data contained in rx_buffer->page to the skb. 2026 * This is done either through a direct copy if the data in the buffer is 2027 * less than the skb header size, otherwise it will just attach the page as 2028 * a frag to the skb. 2029 * 2030 * The function will then update the page offset if necessary and return 2031 * true if the buffer can be reused by the adapter. 2032 **/ 2033 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2034 struct ixgbe_rx_buffer *rx_buffer, 2035 struct sk_buff *skb, 2036 unsigned int size) 2037 { 2038 #if (PAGE_SIZE < 8192) 2039 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2040 #else 2041 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2042 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2043 SKB_DATA_ALIGN(size); 2044 #endif 2045 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2046 rx_buffer->page_offset, size, truesize); 2047 #if (PAGE_SIZE < 8192) 2048 rx_buffer->page_offset ^= truesize; 2049 #else 2050 rx_buffer->page_offset += truesize; 2051 #endif 2052 } 2053 2054 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2055 union ixgbe_adv_rx_desc *rx_desc, 2056 struct sk_buff **skb, 2057 const unsigned int size) 2058 { 2059 struct ixgbe_rx_buffer *rx_buffer; 2060 2061 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2062 prefetchw(rx_buffer->page); 2063 *skb = rx_buffer->skb; 2064 2065 /* Delay unmapping of the first packet. It carries the header 2066 * information, HW may still access the header after the writeback. 2067 * Only unmap it when EOP is reached 2068 */ 2069 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2070 if (!*skb) 2071 goto skip_sync; 2072 } else { 2073 if (*skb) 2074 ixgbe_dma_sync_frag(rx_ring, *skb); 2075 } 2076 2077 /* we are reusing so sync this buffer for CPU use */ 2078 dma_sync_single_range_for_cpu(rx_ring->dev, 2079 rx_buffer->dma, 2080 rx_buffer->page_offset, 2081 size, 2082 DMA_FROM_DEVICE); 2083 skip_sync: 2084 rx_buffer->pagecnt_bias--; 2085 2086 return rx_buffer; 2087 } 2088 2089 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2090 struct ixgbe_rx_buffer *rx_buffer, 2091 struct sk_buff *skb) 2092 { 2093 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2094 /* hand second half of page back to the ring */ 2095 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2096 } else { 2097 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2098 /* the page has been released from the ring */ 2099 IXGBE_CB(skb)->page_released = true; 2100 } else { 2101 /* we are not reusing the buffer so unmap it */ 2102 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2103 ixgbe_rx_pg_size(rx_ring), 2104 DMA_FROM_DEVICE, 2105 IXGBE_RX_DMA_ATTR); 2106 } 2107 __page_frag_cache_drain(rx_buffer->page, 2108 rx_buffer->pagecnt_bias); 2109 } 2110 2111 /* clear contents of rx_buffer */ 2112 rx_buffer->page = NULL; 2113 rx_buffer->skb = NULL; 2114 } 2115 2116 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2117 struct ixgbe_rx_buffer *rx_buffer, 2118 struct xdp_buff *xdp, 2119 union ixgbe_adv_rx_desc *rx_desc) 2120 { 2121 unsigned int size = xdp->data_end - xdp->data; 2122 #if (PAGE_SIZE < 8192) 2123 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2124 #else 2125 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2126 xdp->data_hard_start); 2127 #endif 2128 struct sk_buff *skb; 2129 2130 /* prefetch first cache line of first page */ 2131 prefetch(xdp->data); 2132 #if L1_CACHE_BYTES < 128 2133 prefetch(xdp->data + L1_CACHE_BYTES); 2134 #endif 2135 2136 /* allocate a skb to store the frags */ 2137 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2138 if (unlikely(!skb)) 2139 return NULL; 2140 2141 if (size > IXGBE_RX_HDR_SIZE) { 2142 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2143 IXGBE_CB(skb)->dma = rx_buffer->dma; 2144 2145 skb_add_rx_frag(skb, 0, rx_buffer->page, 2146 xdp->data - page_address(rx_buffer->page), 2147 size, truesize); 2148 #if (PAGE_SIZE < 8192) 2149 rx_buffer->page_offset ^= truesize; 2150 #else 2151 rx_buffer->page_offset += truesize; 2152 #endif 2153 } else { 2154 memcpy(__skb_put(skb, size), 2155 xdp->data, ALIGN(size, sizeof(long))); 2156 rx_buffer->pagecnt_bias++; 2157 } 2158 2159 return skb; 2160 } 2161 2162 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2163 struct ixgbe_rx_buffer *rx_buffer, 2164 struct xdp_buff *xdp, 2165 union ixgbe_adv_rx_desc *rx_desc) 2166 { 2167 #if (PAGE_SIZE < 8192) 2168 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2169 #else 2170 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2171 SKB_DATA_ALIGN(xdp->data_end - 2172 xdp->data_hard_start); 2173 #endif 2174 struct sk_buff *skb; 2175 2176 /* prefetch first cache line of first page */ 2177 prefetch(xdp->data); 2178 #if L1_CACHE_BYTES < 128 2179 prefetch(xdp->data + L1_CACHE_BYTES); 2180 #endif 2181 2182 /* build an skb to around the page buffer */ 2183 skb = build_skb(xdp->data_hard_start, truesize); 2184 if (unlikely(!skb)) 2185 return NULL; 2186 2187 /* update pointers within the skb to store the data */ 2188 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2189 __skb_put(skb, xdp->data_end - xdp->data); 2190 2191 /* record DMA address if this is the start of a chain of buffers */ 2192 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2193 IXGBE_CB(skb)->dma = rx_buffer->dma; 2194 2195 /* update buffer offset */ 2196 #if (PAGE_SIZE < 8192) 2197 rx_buffer->page_offset ^= truesize; 2198 #else 2199 rx_buffer->page_offset += truesize; 2200 #endif 2201 2202 return skb; 2203 } 2204 2205 #define IXGBE_XDP_PASS 0 2206 #define IXGBE_XDP_CONSUMED 1 2207 #define IXGBE_XDP_TX 2 2208 2209 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2210 struct xdp_buff *xdp); 2211 2212 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2213 struct ixgbe_ring *rx_ring, 2214 struct xdp_buff *xdp) 2215 { 2216 int result = IXGBE_XDP_PASS; 2217 struct bpf_prog *xdp_prog; 2218 u32 act; 2219 2220 rcu_read_lock(); 2221 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2222 2223 if (!xdp_prog) 2224 goto xdp_out; 2225 2226 act = bpf_prog_run_xdp(xdp_prog, xdp); 2227 switch (act) { 2228 case XDP_PASS: 2229 break; 2230 case XDP_TX: 2231 result = ixgbe_xmit_xdp_ring(adapter, xdp); 2232 break; 2233 default: 2234 bpf_warn_invalid_xdp_action(act); 2235 case XDP_ABORTED: 2236 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2237 /* fallthrough -- handle aborts by dropping packet */ 2238 case XDP_DROP: 2239 result = IXGBE_XDP_CONSUMED; 2240 break; 2241 } 2242 xdp_out: 2243 rcu_read_unlock(); 2244 return ERR_PTR(-result); 2245 } 2246 2247 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2248 struct ixgbe_rx_buffer *rx_buffer, 2249 unsigned int size) 2250 { 2251 #if (PAGE_SIZE < 8192) 2252 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2253 2254 rx_buffer->page_offset ^= truesize; 2255 #else 2256 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2257 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2258 SKB_DATA_ALIGN(size); 2259 2260 rx_buffer->page_offset += truesize; 2261 #endif 2262 } 2263 2264 /** 2265 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2266 * @q_vector: structure containing interrupt and ring information 2267 * @rx_ring: rx descriptor ring to transact packets on 2268 * @budget: Total limit on number of packets to process 2269 * 2270 * This function provides a "bounce buffer" approach to Rx interrupt 2271 * processing. The advantage to this is that on systems that have 2272 * expensive overhead for IOMMU access this provides a means of avoiding 2273 * it by maintaining the mapping of the page to the syste. 2274 * 2275 * Returns amount of work completed 2276 **/ 2277 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2278 struct ixgbe_ring *rx_ring, 2279 const int budget) 2280 { 2281 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2282 struct ixgbe_adapter *adapter = q_vector->adapter; 2283 #ifdef IXGBE_FCOE 2284 int ddp_bytes; 2285 unsigned int mss = 0; 2286 #endif /* IXGBE_FCOE */ 2287 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2288 bool xdp_xmit = false; 2289 2290 while (likely(total_rx_packets < budget)) { 2291 union ixgbe_adv_rx_desc *rx_desc; 2292 struct ixgbe_rx_buffer *rx_buffer; 2293 struct sk_buff *skb; 2294 struct xdp_buff xdp; 2295 unsigned int size; 2296 2297 /* return some buffers to hardware, one at a time is too slow */ 2298 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2299 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2300 cleaned_count = 0; 2301 } 2302 2303 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2304 size = le16_to_cpu(rx_desc->wb.upper.length); 2305 if (!size) 2306 break; 2307 2308 /* This memory barrier is needed to keep us from reading 2309 * any other fields out of the rx_desc until we know the 2310 * descriptor has been written back 2311 */ 2312 dma_rmb(); 2313 2314 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2315 2316 /* retrieve a buffer from the ring */ 2317 if (!skb) { 2318 xdp.data = page_address(rx_buffer->page) + 2319 rx_buffer->page_offset; 2320 xdp.data_hard_start = xdp.data - 2321 ixgbe_rx_offset(rx_ring); 2322 xdp.data_end = xdp.data + size; 2323 2324 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2325 } 2326 2327 if (IS_ERR(skb)) { 2328 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2329 xdp_xmit = true; 2330 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2331 } else { 2332 rx_buffer->pagecnt_bias++; 2333 } 2334 total_rx_packets++; 2335 total_rx_bytes += size; 2336 } else if (skb) { 2337 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2338 } else if (ring_uses_build_skb(rx_ring)) { 2339 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2340 &xdp, rx_desc); 2341 } else { 2342 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2343 &xdp, rx_desc); 2344 } 2345 2346 /* exit if we failed to retrieve a buffer */ 2347 if (!skb) { 2348 rx_ring->rx_stats.alloc_rx_buff_failed++; 2349 rx_buffer->pagecnt_bias++; 2350 break; 2351 } 2352 2353 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2354 cleaned_count++; 2355 2356 /* place incomplete frames back on ring for completion */ 2357 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2358 continue; 2359 2360 /* verify the packet layout is correct */ 2361 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2362 continue; 2363 2364 /* probably a little skewed due to removing CRC */ 2365 total_rx_bytes += skb->len; 2366 2367 /* populate checksum, timestamp, VLAN, and protocol */ 2368 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2369 2370 #ifdef IXGBE_FCOE 2371 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2372 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2373 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2374 /* include DDPed FCoE data */ 2375 if (ddp_bytes > 0) { 2376 if (!mss) { 2377 mss = rx_ring->netdev->mtu - 2378 sizeof(struct fcoe_hdr) - 2379 sizeof(struct fc_frame_header) - 2380 sizeof(struct fcoe_crc_eof); 2381 if (mss > 512) 2382 mss &= ~511; 2383 } 2384 total_rx_bytes += ddp_bytes; 2385 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2386 mss); 2387 } 2388 if (!ddp_bytes) { 2389 dev_kfree_skb_any(skb); 2390 continue; 2391 } 2392 } 2393 2394 #endif /* IXGBE_FCOE */ 2395 ixgbe_rx_skb(q_vector, skb); 2396 2397 /* update budget accounting */ 2398 total_rx_packets++; 2399 } 2400 2401 if (xdp_xmit) { 2402 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2403 2404 /* Force memory writes to complete before letting h/w 2405 * know there are new descriptors to fetch. 2406 */ 2407 wmb(); 2408 writel(ring->next_to_use, ring->tail); 2409 } 2410 2411 u64_stats_update_begin(&rx_ring->syncp); 2412 rx_ring->stats.packets += total_rx_packets; 2413 rx_ring->stats.bytes += total_rx_bytes; 2414 u64_stats_update_end(&rx_ring->syncp); 2415 q_vector->rx.total_packets += total_rx_packets; 2416 q_vector->rx.total_bytes += total_rx_bytes; 2417 2418 return total_rx_packets; 2419 } 2420 2421 /** 2422 * ixgbe_configure_msix - Configure MSI-X hardware 2423 * @adapter: board private structure 2424 * 2425 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2426 * interrupts. 2427 **/ 2428 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2429 { 2430 struct ixgbe_q_vector *q_vector; 2431 int v_idx; 2432 u32 mask; 2433 2434 /* Populate MSIX to EITR Select */ 2435 if (adapter->num_vfs > 32) { 2436 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2438 } 2439 2440 /* 2441 * Populate the IVAR table and set the ITR values to the 2442 * corresponding register. 2443 */ 2444 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2445 struct ixgbe_ring *ring; 2446 q_vector = adapter->q_vector[v_idx]; 2447 2448 ixgbe_for_each_ring(ring, q_vector->rx) 2449 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2450 2451 ixgbe_for_each_ring(ring, q_vector->tx) 2452 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2453 2454 ixgbe_write_eitr(q_vector); 2455 } 2456 2457 switch (adapter->hw.mac.type) { 2458 case ixgbe_mac_82598EB: 2459 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2460 v_idx); 2461 break; 2462 case ixgbe_mac_82599EB: 2463 case ixgbe_mac_X540: 2464 case ixgbe_mac_X550: 2465 case ixgbe_mac_X550EM_x: 2466 case ixgbe_mac_x550em_a: 2467 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2468 break; 2469 default: 2470 break; 2471 } 2472 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2473 2474 /* set up to autoclear timer, and the vectors */ 2475 mask = IXGBE_EIMS_ENABLE_MASK; 2476 mask &= ~(IXGBE_EIMS_OTHER | 2477 IXGBE_EIMS_MAILBOX | 2478 IXGBE_EIMS_LSC); 2479 2480 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2481 } 2482 2483 enum latency_range { 2484 lowest_latency = 0, 2485 low_latency = 1, 2486 bulk_latency = 2, 2487 latency_invalid = 255 2488 }; 2489 2490 /** 2491 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2492 * @q_vector: structure containing interrupt and ring information 2493 * @ring_container: structure containing ring performance data 2494 * 2495 * Stores a new ITR value based on packets and byte 2496 * counts during the last interrupt. The advantage of per interrupt 2497 * computation is faster updates and more accurate ITR for the current 2498 * traffic pattern. Constants in this function were computed 2499 * based on theoretical maximum wire speed and thresholds were set based 2500 * on testing data as well as attempting to minimize response time 2501 * while increasing bulk throughput. 2502 * this functionality is controlled by the InterruptThrottleRate module 2503 * parameter (see ixgbe_param.c) 2504 **/ 2505 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2506 struct ixgbe_ring_container *ring_container) 2507 { 2508 int bytes = ring_container->total_bytes; 2509 int packets = ring_container->total_packets; 2510 u32 timepassed_us; 2511 u64 bytes_perint; 2512 u8 itr_setting = ring_container->itr; 2513 2514 if (packets == 0) 2515 return; 2516 2517 /* simple throttlerate management 2518 * 0-10MB/s lowest (100000 ints/s) 2519 * 10-20MB/s low (20000 ints/s) 2520 * 20-1249MB/s bulk (12000 ints/s) 2521 */ 2522 /* what was last interrupt timeslice? */ 2523 timepassed_us = q_vector->itr >> 2; 2524 if (timepassed_us == 0) 2525 return; 2526 2527 bytes_perint = bytes / timepassed_us; /* bytes/usec */ 2528 2529 switch (itr_setting) { 2530 case lowest_latency: 2531 if (bytes_perint > 10) 2532 itr_setting = low_latency; 2533 break; 2534 case low_latency: 2535 if (bytes_perint > 20) 2536 itr_setting = bulk_latency; 2537 else if (bytes_perint <= 10) 2538 itr_setting = lowest_latency; 2539 break; 2540 case bulk_latency: 2541 if (bytes_perint <= 20) 2542 itr_setting = low_latency; 2543 break; 2544 } 2545 2546 /* clear work counters since we have the values we need */ 2547 ring_container->total_bytes = 0; 2548 ring_container->total_packets = 0; 2549 2550 /* write updated itr to ring container */ 2551 ring_container->itr = itr_setting; 2552 } 2553 2554 /** 2555 * ixgbe_write_eitr - write EITR register in hardware specific way 2556 * @q_vector: structure containing interrupt and ring information 2557 * 2558 * This function is made to be called by ethtool and by the driver 2559 * when it needs to update EITR registers at runtime. Hardware 2560 * specific quirks/differences are taken care of here. 2561 */ 2562 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2563 { 2564 struct ixgbe_adapter *adapter = q_vector->adapter; 2565 struct ixgbe_hw *hw = &adapter->hw; 2566 int v_idx = q_vector->v_idx; 2567 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2568 2569 switch (adapter->hw.mac.type) { 2570 case ixgbe_mac_82598EB: 2571 /* must write high and low 16 bits to reset counter */ 2572 itr_reg |= (itr_reg << 16); 2573 break; 2574 case ixgbe_mac_82599EB: 2575 case ixgbe_mac_X540: 2576 case ixgbe_mac_X550: 2577 case ixgbe_mac_X550EM_x: 2578 case ixgbe_mac_x550em_a: 2579 /* 2580 * set the WDIS bit to not clear the timer bits and cause an 2581 * immediate assertion of the interrupt 2582 */ 2583 itr_reg |= IXGBE_EITR_CNT_WDIS; 2584 break; 2585 default: 2586 break; 2587 } 2588 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2589 } 2590 2591 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2592 { 2593 u32 new_itr = q_vector->itr; 2594 u8 current_itr; 2595 2596 ixgbe_update_itr(q_vector, &q_vector->tx); 2597 ixgbe_update_itr(q_vector, &q_vector->rx); 2598 2599 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 2600 2601 switch (current_itr) { 2602 /* counts and packets in update_itr are dependent on these numbers */ 2603 case lowest_latency: 2604 new_itr = IXGBE_100K_ITR; 2605 break; 2606 case low_latency: 2607 new_itr = IXGBE_20K_ITR; 2608 break; 2609 case bulk_latency: 2610 new_itr = IXGBE_12K_ITR; 2611 break; 2612 default: 2613 break; 2614 } 2615 2616 if (new_itr != q_vector->itr) { 2617 /* do an exponential smoothing */ 2618 new_itr = (10 * new_itr * q_vector->itr) / 2619 ((9 * new_itr) + q_vector->itr); 2620 2621 /* save the algorithm value here */ 2622 q_vector->itr = new_itr; 2623 2624 ixgbe_write_eitr(q_vector); 2625 } 2626 } 2627 2628 /** 2629 * ixgbe_check_overtemp_subtask - check for over temperature 2630 * @adapter: pointer to adapter 2631 **/ 2632 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2633 { 2634 struct ixgbe_hw *hw = &adapter->hw; 2635 u32 eicr = adapter->interrupt_event; 2636 s32 rc; 2637 2638 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2639 return; 2640 2641 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && 2642 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2643 return; 2644 2645 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2646 2647 switch (hw->device_id) { 2648 case IXGBE_DEV_ID_82599_T3_LOM: 2649 /* 2650 * Since the warning interrupt is for both ports 2651 * we don't have to check if: 2652 * - This interrupt wasn't for our port. 2653 * - We may have missed the interrupt so always have to 2654 * check if we got a LSC 2655 */ 2656 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2657 !(eicr & IXGBE_EICR_LSC)) 2658 return; 2659 2660 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2661 u32 speed; 2662 bool link_up = false; 2663 2664 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2665 2666 if (link_up) 2667 return; 2668 } 2669 2670 /* Check if this is not due to overtemp */ 2671 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2672 return; 2673 2674 break; 2675 case IXGBE_DEV_ID_X550EM_A_1G_T: 2676 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2677 rc = hw->phy.ops.check_overtemp(hw); 2678 if (rc != IXGBE_ERR_OVERTEMP) 2679 return; 2680 break; 2681 default: 2682 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2683 return; 2684 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2685 return; 2686 break; 2687 } 2688 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2689 2690 adapter->interrupt_event = 0; 2691 } 2692 2693 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2694 { 2695 struct ixgbe_hw *hw = &adapter->hw; 2696 2697 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2698 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2699 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2700 /* write to clear the interrupt */ 2701 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2702 } 2703 } 2704 2705 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2706 { 2707 struct ixgbe_hw *hw = &adapter->hw; 2708 2709 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2710 return; 2711 2712 switch (adapter->hw.mac.type) { 2713 case ixgbe_mac_82599EB: 2714 /* 2715 * Need to check link state so complete overtemp check 2716 * on service task 2717 */ 2718 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2719 (eicr & IXGBE_EICR_LSC)) && 2720 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2721 adapter->interrupt_event = eicr; 2722 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2723 ixgbe_service_event_schedule(adapter); 2724 return; 2725 } 2726 return; 2727 case ixgbe_mac_x550em_a: 2728 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2729 adapter->interrupt_event = eicr; 2730 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2731 ixgbe_service_event_schedule(adapter); 2732 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2733 IXGBE_EICR_GPI_SDP0_X550EM_a); 2734 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2735 IXGBE_EICR_GPI_SDP0_X550EM_a); 2736 } 2737 return; 2738 case ixgbe_mac_X550: 2739 case ixgbe_mac_X540: 2740 if (!(eicr & IXGBE_EICR_TS)) 2741 return; 2742 break; 2743 default: 2744 return; 2745 } 2746 2747 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2748 } 2749 2750 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2751 { 2752 switch (hw->mac.type) { 2753 case ixgbe_mac_82598EB: 2754 if (hw->phy.type == ixgbe_phy_nl) 2755 return true; 2756 return false; 2757 case ixgbe_mac_82599EB: 2758 case ixgbe_mac_X550EM_x: 2759 case ixgbe_mac_x550em_a: 2760 switch (hw->mac.ops.get_media_type(hw)) { 2761 case ixgbe_media_type_fiber: 2762 case ixgbe_media_type_fiber_qsfp: 2763 return true; 2764 default: 2765 return false; 2766 } 2767 default: 2768 return false; 2769 } 2770 } 2771 2772 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2773 { 2774 struct ixgbe_hw *hw = &adapter->hw; 2775 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2776 2777 if (!ixgbe_is_sfp(hw)) 2778 return; 2779 2780 /* Later MAC's use different SDP */ 2781 if (hw->mac.type >= ixgbe_mac_X540) 2782 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2783 2784 if (eicr & eicr_mask) { 2785 /* Clear the interrupt */ 2786 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2787 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2788 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2789 adapter->sfp_poll_time = 0; 2790 ixgbe_service_event_schedule(adapter); 2791 } 2792 } 2793 2794 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2795 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2796 /* Clear the interrupt */ 2797 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2798 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2799 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2800 ixgbe_service_event_schedule(adapter); 2801 } 2802 } 2803 } 2804 2805 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2806 { 2807 struct ixgbe_hw *hw = &adapter->hw; 2808 2809 adapter->lsc_int++; 2810 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2811 adapter->link_check_timeout = jiffies; 2812 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2813 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2814 IXGBE_WRITE_FLUSH(hw); 2815 ixgbe_service_event_schedule(adapter); 2816 } 2817 } 2818 2819 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2820 u64 qmask) 2821 { 2822 u32 mask; 2823 struct ixgbe_hw *hw = &adapter->hw; 2824 2825 switch (hw->mac.type) { 2826 case ixgbe_mac_82598EB: 2827 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2828 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2829 break; 2830 case ixgbe_mac_82599EB: 2831 case ixgbe_mac_X540: 2832 case ixgbe_mac_X550: 2833 case ixgbe_mac_X550EM_x: 2834 case ixgbe_mac_x550em_a: 2835 mask = (qmask & 0xFFFFFFFF); 2836 if (mask) 2837 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2838 mask = (qmask >> 32); 2839 if (mask) 2840 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2841 break; 2842 default: 2843 break; 2844 } 2845 /* skip the flush */ 2846 } 2847 2848 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2849 u64 qmask) 2850 { 2851 u32 mask; 2852 struct ixgbe_hw *hw = &adapter->hw; 2853 2854 switch (hw->mac.type) { 2855 case ixgbe_mac_82598EB: 2856 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2857 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 2858 break; 2859 case ixgbe_mac_82599EB: 2860 case ixgbe_mac_X540: 2861 case ixgbe_mac_X550: 2862 case ixgbe_mac_X550EM_x: 2863 case ixgbe_mac_x550em_a: 2864 mask = (qmask & 0xFFFFFFFF); 2865 if (mask) 2866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 2867 mask = (qmask >> 32); 2868 if (mask) 2869 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 2870 break; 2871 default: 2872 break; 2873 } 2874 /* skip the flush */ 2875 } 2876 2877 /** 2878 * ixgbe_irq_enable - Enable default interrupt generation settings 2879 * @adapter: board private structure 2880 **/ 2881 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 2882 bool flush) 2883 { 2884 struct ixgbe_hw *hw = &adapter->hw; 2885 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 2886 2887 /* don't reenable LSC while waiting for link */ 2888 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 2889 mask &= ~IXGBE_EIMS_LSC; 2890 2891 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 2892 switch (adapter->hw.mac.type) { 2893 case ixgbe_mac_82599EB: 2894 mask |= IXGBE_EIMS_GPI_SDP0(hw); 2895 break; 2896 case ixgbe_mac_X540: 2897 case ixgbe_mac_X550: 2898 case ixgbe_mac_X550EM_x: 2899 case ixgbe_mac_x550em_a: 2900 mask |= IXGBE_EIMS_TS; 2901 break; 2902 default: 2903 break; 2904 } 2905 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 2906 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2907 switch (adapter->hw.mac.type) { 2908 case ixgbe_mac_82599EB: 2909 mask |= IXGBE_EIMS_GPI_SDP1(hw); 2910 mask |= IXGBE_EIMS_GPI_SDP2(hw); 2911 /* fall through */ 2912 case ixgbe_mac_X540: 2913 case ixgbe_mac_X550: 2914 case ixgbe_mac_X550EM_x: 2915 case ixgbe_mac_x550em_a: 2916 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 2917 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 2918 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 2919 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 2920 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 2921 mask |= IXGBE_EICR_GPI_SDP0_X540; 2922 mask |= IXGBE_EIMS_ECC; 2923 mask |= IXGBE_EIMS_MAILBOX; 2924 break; 2925 default: 2926 break; 2927 } 2928 2929 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 2930 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 2931 mask |= IXGBE_EIMS_FLOW_DIR; 2932 2933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 2934 if (queues) 2935 ixgbe_irq_enable_queues(adapter, ~0); 2936 if (flush) 2937 IXGBE_WRITE_FLUSH(&adapter->hw); 2938 } 2939 2940 static irqreturn_t ixgbe_msix_other(int irq, void *data) 2941 { 2942 struct ixgbe_adapter *adapter = data; 2943 struct ixgbe_hw *hw = &adapter->hw; 2944 u32 eicr; 2945 2946 /* 2947 * Workaround for Silicon errata. Use clear-by-write instead 2948 * of clear-by-read. Reading with EICS will return the 2949 * interrupt causes without clearing, which later be done 2950 * with the write to EICR. 2951 */ 2952 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 2953 2954 /* The lower 16bits of the EICR register are for the queue interrupts 2955 * which should be masked here in order to not accidentally clear them if 2956 * the bits are high when ixgbe_msix_other is called. There is a race 2957 * condition otherwise which results in possible performance loss 2958 * especially if the ixgbe_msix_other interrupt is triggering 2959 * consistently (as it would when PPS is turned on for the X540 device) 2960 */ 2961 eicr &= 0xFFFF0000; 2962 2963 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 2964 2965 if (eicr & IXGBE_EICR_LSC) 2966 ixgbe_check_lsc(adapter); 2967 2968 if (eicr & IXGBE_EICR_MAILBOX) 2969 ixgbe_msg_task(adapter); 2970 2971 switch (hw->mac.type) { 2972 case ixgbe_mac_82599EB: 2973 case ixgbe_mac_X540: 2974 case ixgbe_mac_X550: 2975 case ixgbe_mac_X550EM_x: 2976 case ixgbe_mac_x550em_a: 2977 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 2978 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 2979 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 2980 ixgbe_service_event_schedule(adapter); 2981 IXGBE_WRITE_REG(hw, IXGBE_EICR, 2982 IXGBE_EICR_GPI_SDP0_X540); 2983 } 2984 if (eicr & IXGBE_EICR_ECC) { 2985 e_info(link, "Received ECC Err, initiating reset\n"); 2986 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 2987 ixgbe_service_event_schedule(adapter); 2988 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 2989 } 2990 /* Handle Flow Director Full threshold interrupt */ 2991 if (eicr & IXGBE_EICR_FLOW_DIR) { 2992 int reinit_count = 0; 2993 int i; 2994 for (i = 0; i < adapter->num_tx_queues; i++) { 2995 struct ixgbe_ring *ring = adapter->tx_ring[i]; 2996 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 2997 &ring->state)) 2998 reinit_count++; 2999 } 3000 if (reinit_count) { 3001 /* no more flow director interrupts until after init */ 3002 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3003 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3004 ixgbe_service_event_schedule(adapter); 3005 } 3006 } 3007 ixgbe_check_sfp_event(adapter, eicr); 3008 ixgbe_check_overtemp_event(adapter, eicr); 3009 break; 3010 default: 3011 break; 3012 } 3013 3014 ixgbe_check_fan_failure(adapter, eicr); 3015 3016 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3017 ixgbe_ptp_check_pps_event(adapter); 3018 3019 /* re-enable the original interrupt state, no lsc, no queues */ 3020 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3021 ixgbe_irq_enable(adapter, false, false); 3022 3023 return IRQ_HANDLED; 3024 } 3025 3026 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3027 { 3028 struct ixgbe_q_vector *q_vector = data; 3029 3030 /* EIAM disabled interrupts (on this vector) for us */ 3031 3032 if (q_vector->rx.ring || q_vector->tx.ring) 3033 napi_schedule_irqoff(&q_vector->napi); 3034 3035 return IRQ_HANDLED; 3036 } 3037 3038 /** 3039 * ixgbe_poll - NAPI Rx polling callback 3040 * @napi: structure for representing this polling device 3041 * @budget: how many packets driver is allowed to clean 3042 * 3043 * This function is used for legacy and MSI, NAPI mode 3044 **/ 3045 int ixgbe_poll(struct napi_struct *napi, int budget) 3046 { 3047 struct ixgbe_q_vector *q_vector = 3048 container_of(napi, struct ixgbe_q_vector, napi); 3049 struct ixgbe_adapter *adapter = q_vector->adapter; 3050 struct ixgbe_ring *ring; 3051 int per_ring_budget, work_done = 0; 3052 bool clean_complete = true; 3053 3054 #ifdef CONFIG_IXGBE_DCA 3055 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3056 ixgbe_update_dca(q_vector); 3057 #endif 3058 3059 ixgbe_for_each_ring(ring, q_vector->tx) { 3060 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3061 clean_complete = false; 3062 } 3063 3064 /* Exit if we are called by netpoll */ 3065 if (budget <= 0) 3066 return budget; 3067 3068 /* attempt to distribute budget to each queue fairly, but don't allow 3069 * the budget to go below 1 because we'll exit polling */ 3070 if (q_vector->rx.count > 1) 3071 per_ring_budget = max(budget/q_vector->rx.count, 1); 3072 else 3073 per_ring_budget = budget; 3074 3075 ixgbe_for_each_ring(ring, q_vector->rx) { 3076 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3077 per_ring_budget); 3078 3079 work_done += cleaned; 3080 if (cleaned >= per_ring_budget) 3081 clean_complete = false; 3082 } 3083 3084 /* If all work not completed, return budget and keep polling */ 3085 if (!clean_complete) 3086 return budget; 3087 3088 /* all work done, exit the polling mode */ 3089 napi_complete_done(napi, work_done); 3090 if (adapter->rx_itr_setting & 1) 3091 ixgbe_set_itr(q_vector); 3092 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3093 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3094 3095 return min(work_done, budget - 1); 3096 } 3097 3098 /** 3099 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3100 * @adapter: board private structure 3101 * 3102 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3103 * interrupts from the kernel. 3104 **/ 3105 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3106 { 3107 struct net_device *netdev = adapter->netdev; 3108 int vector, err; 3109 int ri = 0, ti = 0; 3110 3111 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3112 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3113 struct msix_entry *entry = &adapter->msix_entries[vector]; 3114 3115 if (q_vector->tx.ring && q_vector->rx.ring) { 3116 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 3117 "%s-%s-%d", netdev->name, "TxRx", ri++); 3118 ti++; 3119 } else if (q_vector->rx.ring) { 3120 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 3121 "%s-%s-%d", netdev->name, "rx", ri++); 3122 } else if (q_vector->tx.ring) { 3123 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 3124 "%s-%s-%d", netdev->name, "tx", ti++); 3125 } else { 3126 /* skip this unused q_vector */ 3127 continue; 3128 } 3129 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3130 q_vector->name, q_vector); 3131 if (err) { 3132 e_err(probe, "request_irq failed for MSIX interrupt " 3133 "Error: %d\n", err); 3134 goto free_queue_irqs; 3135 } 3136 /* If Flow Director is enabled, set interrupt affinity */ 3137 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3138 /* assign the mask for this irq */ 3139 irq_set_affinity_hint(entry->vector, 3140 &q_vector->affinity_mask); 3141 } 3142 } 3143 3144 err = request_irq(adapter->msix_entries[vector].vector, 3145 ixgbe_msix_other, 0, netdev->name, adapter); 3146 if (err) { 3147 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3148 goto free_queue_irqs; 3149 } 3150 3151 return 0; 3152 3153 free_queue_irqs: 3154 while (vector) { 3155 vector--; 3156 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3157 NULL); 3158 free_irq(adapter->msix_entries[vector].vector, 3159 adapter->q_vector[vector]); 3160 } 3161 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3162 pci_disable_msix(adapter->pdev); 3163 kfree(adapter->msix_entries); 3164 adapter->msix_entries = NULL; 3165 return err; 3166 } 3167 3168 /** 3169 * ixgbe_intr - legacy mode Interrupt Handler 3170 * @irq: interrupt number 3171 * @data: pointer to a network interface device structure 3172 **/ 3173 static irqreturn_t ixgbe_intr(int irq, void *data) 3174 { 3175 struct ixgbe_adapter *adapter = data; 3176 struct ixgbe_hw *hw = &adapter->hw; 3177 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3178 u32 eicr; 3179 3180 /* 3181 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3182 * before the read of EICR. 3183 */ 3184 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3185 3186 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3187 * therefore no explicit interrupt disable is necessary */ 3188 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3189 if (!eicr) { 3190 /* 3191 * shared interrupt alert! 3192 * make sure interrupts are enabled because the read will 3193 * have disabled interrupts due to EIAM 3194 * finish the workaround of silicon errata on 82598. Unmask 3195 * the interrupt that we masked before the EICR read. 3196 */ 3197 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3198 ixgbe_irq_enable(adapter, true, true); 3199 return IRQ_NONE; /* Not our interrupt */ 3200 } 3201 3202 if (eicr & IXGBE_EICR_LSC) 3203 ixgbe_check_lsc(adapter); 3204 3205 switch (hw->mac.type) { 3206 case ixgbe_mac_82599EB: 3207 ixgbe_check_sfp_event(adapter, eicr); 3208 /* Fall through */ 3209 case ixgbe_mac_X540: 3210 case ixgbe_mac_X550: 3211 case ixgbe_mac_X550EM_x: 3212 case ixgbe_mac_x550em_a: 3213 if (eicr & IXGBE_EICR_ECC) { 3214 e_info(link, "Received ECC Err, initiating reset\n"); 3215 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3216 ixgbe_service_event_schedule(adapter); 3217 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3218 } 3219 ixgbe_check_overtemp_event(adapter, eicr); 3220 break; 3221 default: 3222 break; 3223 } 3224 3225 ixgbe_check_fan_failure(adapter, eicr); 3226 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3227 ixgbe_ptp_check_pps_event(adapter); 3228 3229 /* would disable interrupts here but EIAM disabled it */ 3230 napi_schedule_irqoff(&q_vector->napi); 3231 3232 /* 3233 * re-enable link(maybe) and non-queue interrupts, no flush. 3234 * ixgbe_poll will re-enable the queue interrupts 3235 */ 3236 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3237 ixgbe_irq_enable(adapter, false, false); 3238 3239 return IRQ_HANDLED; 3240 } 3241 3242 /** 3243 * ixgbe_request_irq - initialize interrupts 3244 * @adapter: board private structure 3245 * 3246 * Attempts to configure interrupts using the best available 3247 * capabilities of the hardware and kernel. 3248 **/ 3249 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3250 { 3251 struct net_device *netdev = adapter->netdev; 3252 int err; 3253 3254 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3255 err = ixgbe_request_msix_irqs(adapter); 3256 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3257 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3258 netdev->name, adapter); 3259 else 3260 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3261 netdev->name, adapter); 3262 3263 if (err) 3264 e_err(probe, "request_irq failed, Error %d\n", err); 3265 3266 return err; 3267 } 3268 3269 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3270 { 3271 int vector; 3272 3273 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3274 free_irq(adapter->pdev->irq, adapter); 3275 return; 3276 } 3277 3278 if (!adapter->msix_entries) 3279 return; 3280 3281 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3282 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3283 struct msix_entry *entry = &adapter->msix_entries[vector]; 3284 3285 /* free only the irqs that were actually requested */ 3286 if (!q_vector->rx.ring && !q_vector->tx.ring) 3287 continue; 3288 3289 /* clear the affinity_mask in the IRQ descriptor */ 3290 irq_set_affinity_hint(entry->vector, NULL); 3291 3292 free_irq(entry->vector, q_vector); 3293 } 3294 3295 free_irq(adapter->msix_entries[vector].vector, adapter); 3296 } 3297 3298 /** 3299 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3300 * @adapter: board private structure 3301 **/ 3302 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3303 { 3304 switch (adapter->hw.mac.type) { 3305 case ixgbe_mac_82598EB: 3306 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3307 break; 3308 case ixgbe_mac_82599EB: 3309 case ixgbe_mac_X540: 3310 case ixgbe_mac_X550: 3311 case ixgbe_mac_X550EM_x: 3312 case ixgbe_mac_x550em_a: 3313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3314 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3316 break; 3317 default: 3318 break; 3319 } 3320 IXGBE_WRITE_FLUSH(&adapter->hw); 3321 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3322 int vector; 3323 3324 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3325 synchronize_irq(adapter->msix_entries[vector].vector); 3326 3327 synchronize_irq(adapter->msix_entries[vector++].vector); 3328 } else { 3329 synchronize_irq(adapter->pdev->irq); 3330 } 3331 } 3332 3333 /** 3334 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3335 * 3336 **/ 3337 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3338 { 3339 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3340 3341 ixgbe_write_eitr(q_vector); 3342 3343 ixgbe_set_ivar(adapter, 0, 0, 0); 3344 ixgbe_set_ivar(adapter, 1, 0, 0); 3345 3346 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3347 } 3348 3349 /** 3350 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3351 * @adapter: board private structure 3352 * @ring: structure containing ring specific data 3353 * 3354 * Configure the Tx descriptor ring after a reset. 3355 **/ 3356 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3357 struct ixgbe_ring *ring) 3358 { 3359 struct ixgbe_hw *hw = &adapter->hw; 3360 u64 tdba = ring->dma; 3361 int wait_loop = 10; 3362 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3363 u8 reg_idx = ring->reg_idx; 3364 3365 /* disable queue to avoid issues while updating state */ 3366 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3367 IXGBE_WRITE_FLUSH(hw); 3368 3369 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3370 (tdba & DMA_BIT_MASK(32))); 3371 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3372 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3373 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3374 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3375 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3376 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3377 3378 /* 3379 * set WTHRESH to encourage burst writeback, it should not be set 3380 * higher than 1 when: 3381 * - ITR is 0 as it could cause false TX hangs 3382 * - ITR is set to > 100k int/sec and BQL is enabled 3383 * 3384 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3385 * to or less than the number of on chip descriptors, which is 3386 * currently 40. 3387 */ 3388 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3389 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3390 else 3391 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3392 3393 /* 3394 * Setting PTHRESH to 32 both improves performance 3395 * and avoids a TX hang with DFP enabled 3396 */ 3397 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3398 32; /* PTHRESH = 32 */ 3399 3400 /* reinitialize flowdirector state */ 3401 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3402 ring->atr_sample_rate = adapter->atr_sample_rate; 3403 ring->atr_count = 0; 3404 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3405 } else { 3406 ring->atr_sample_rate = 0; 3407 } 3408 3409 /* initialize XPS */ 3410 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3411 struct ixgbe_q_vector *q_vector = ring->q_vector; 3412 3413 if (q_vector) 3414 netif_set_xps_queue(ring->netdev, 3415 &q_vector->affinity_mask, 3416 ring->queue_index); 3417 } 3418 3419 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3420 3421 /* reinitialize tx_buffer_info */ 3422 memset(ring->tx_buffer_info, 0, 3423 sizeof(struct ixgbe_tx_buffer) * ring->count); 3424 3425 /* enable queue */ 3426 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3427 3428 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3429 if (hw->mac.type == ixgbe_mac_82598EB && 3430 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3431 return; 3432 3433 /* poll to verify queue is enabled */ 3434 do { 3435 usleep_range(1000, 2000); 3436 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3437 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3438 if (!wait_loop) 3439 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3440 } 3441 3442 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3443 { 3444 struct ixgbe_hw *hw = &adapter->hw; 3445 u32 rttdcs, mtqc; 3446 u8 tcs = netdev_get_num_tc(adapter->netdev); 3447 3448 if (hw->mac.type == ixgbe_mac_82598EB) 3449 return; 3450 3451 /* disable the arbiter while setting MTQC */ 3452 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3453 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3454 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3455 3456 /* set transmit pool layout */ 3457 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3458 mtqc = IXGBE_MTQC_VT_ENA; 3459 if (tcs > 4) 3460 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3461 else if (tcs > 1) 3462 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3463 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3464 IXGBE_82599_VMDQ_4Q_MASK) 3465 mtqc |= IXGBE_MTQC_32VF; 3466 else 3467 mtqc |= IXGBE_MTQC_64VF; 3468 } else { 3469 if (tcs > 4) 3470 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3471 else if (tcs > 1) 3472 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3473 else 3474 mtqc = IXGBE_MTQC_64Q_1PB; 3475 } 3476 3477 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3478 3479 /* Enable Security TX Buffer IFG for multiple pb */ 3480 if (tcs) { 3481 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3482 sectx |= IXGBE_SECTX_DCB; 3483 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3484 } 3485 3486 /* re-enable the arbiter */ 3487 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3488 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3489 } 3490 3491 /** 3492 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3493 * @adapter: board private structure 3494 * 3495 * Configure the Tx unit of the MAC after a reset. 3496 **/ 3497 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3498 { 3499 struct ixgbe_hw *hw = &adapter->hw; 3500 u32 dmatxctl; 3501 u32 i; 3502 3503 ixgbe_setup_mtqc(adapter); 3504 3505 if (hw->mac.type != ixgbe_mac_82598EB) { 3506 /* DMATXCTL.EN must be before Tx queues are enabled */ 3507 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3508 dmatxctl |= IXGBE_DMATXCTL_TE; 3509 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3510 } 3511 3512 /* Setup the HW Tx Head and Tail descriptor pointers */ 3513 for (i = 0; i < adapter->num_tx_queues; i++) 3514 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3515 for (i = 0; i < adapter->num_xdp_queues; i++) 3516 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3517 } 3518 3519 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3520 struct ixgbe_ring *ring) 3521 { 3522 struct ixgbe_hw *hw = &adapter->hw; 3523 u8 reg_idx = ring->reg_idx; 3524 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3525 3526 srrctl |= IXGBE_SRRCTL_DROP_EN; 3527 3528 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3529 } 3530 3531 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3532 struct ixgbe_ring *ring) 3533 { 3534 struct ixgbe_hw *hw = &adapter->hw; 3535 u8 reg_idx = ring->reg_idx; 3536 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3537 3538 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3539 3540 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3541 } 3542 3543 #ifdef CONFIG_IXGBE_DCB 3544 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3545 #else 3546 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3547 #endif 3548 { 3549 int i; 3550 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3551 3552 if (adapter->ixgbe_ieee_pfc) 3553 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3554 3555 /* 3556 * We should set the drop enable bit if: 3557 * SR-IOV is enabled 3558 * or 3559 * Number of Rx queues > 1 and flow control is disabled 3560 * 3561 * This allows us to avoid head of line blocking for security 3562 * and performance reasons. 3563 */ 3564 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3565 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3566 for (i = 0; i < adapter->num_rx_queues; i++) 3567 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3568 } else { 3569 for (i = 0; i < adapter->num_rx_queues; i++) 3570 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3571 } 3572 } 3573 3574 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3575 3576 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3577 struct ixgbe_ring *rx_ring) 3578 { 3579 struct ixgbe_hw *hw = &adapter->hw; 3580 u32 srrctl; 3581 u8 reg_idx = rx_ring->reg_idx; 3582 3583 if (hw->mac.type == ixgbe_mac_82598EB) { 3584 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3585 3586 /* 3587 * if VMDq is not active we must program one srrctl register 3588 * per RSS queue since we have enabled RDRXCTL.MVMEN 3589 */ 3590 reg_idx &= mask; 3591 } 3592 3593 /* configure header buffer length, needed for RSC */ 3594 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3595 3596 /* configure the packet buffer length */ 3597 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3598 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3599 else 3600 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3601 3602 /* configure descriptor type */ 3603 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3604 3605 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3606 } 3607 3608 /** 3609 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3610 * @adapter: device handle 3611 * 3612 * - 82598/82599/X540: 128 3613 * - X550(non-SRIOV mode): 512 3614 * - X550(SRIOV mode): 64 3615 */ 3616 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3617 { 3618 if (adapter->hw.mac.type < ixgbe_mac_X550) 3619 return 128; 3620 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3621 return 64; 3622 else 3623 return 512; 3624 } 3625 3626 /** 3627 * ixgbe_store_key - Write the RSS key to HW 3628 * @adapter: device handle 3629 * 3630 * Write the RSS key stored in adapter.rss_key to HW. 3631 */ 3632 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3633 { 3634 struct ixgbe_hw *hw = &adapter->hw; 3635 int i; 3636 3637 for (i = 0; i < 10; i++) 3638 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3639 } 3640 3641 /** 3642 * ixgbe_init_rss_key - Initialize adapter RSS key 3643 * @adapter: device handle 3644 * 3645 * Allocates and initializes the RSS key if it is not allocated. 3646 **/ 3647 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3648 { 3649 u32 *rss_key; 3650 3651 if (!adapter->rss_key) { 3652 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3653 if (unlikely(!rss_key)) 3654 return -ENOMEM; 3655 3656 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3657 adapter->rss_key = rss_key; 3658 } 3659 3660 return 0; 3661 } 3662 3663 /** 3664 * ixgbe_store_reta - Write the RETA table to HW 3665 * @adapter: device handle 3666 * 3667 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3668 */ 3669 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3670 { 3671 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3672 struct ixgbe_hw *hw = &adapter->hw; 3673 u32 reta = 0; 3674 u32 indices_multi; 3675 u8 *indir_tbl = adapter->rss_indir_tbl; 3676 3677 /* Fill out the redirection table as follows: 3678 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3679 * indices. 3680 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3681 * - X550: 8 bit wide entries containing 6 bit RSS index 3682 */ 3683 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3684 indices_multi = 0x11; 3685 else 3686 indices_multi = 0x1; 3687 3688 /* Write redirection table to HW */ 3689 for (i = 0; i < reta_entries; i++) { 3690 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3691 if ((i & 3) == 3) { 3692 if (i < 128) 3693 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3694 else 3695 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3696 reta); 3697 reta = 0; 3698 } 3699 } 3700 } 3701 3702 /** 3703 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3704 * @adapter: device handle 3705 * 3706 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3707 */ 3708 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3709 { 3710 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3711 struct ixgbe_hw *hw = &adapter->hw; 3712 u32 vfreta = 0; 3713 unsigned int pf_pool = adapter->num_vfs; 3714 3715 /* Write redirection table to HW */ 3716 for (i = 0; i < reta_entries; i++) { 3717 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3718 if ((i & 3) == 3) { 3719 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), 3720 vfreta); 3721 vfreta = 0; 3722 } 3723 } 3724 } 3725 3726 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3727 { 3728 u32 i, j; 3729 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3730 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3731 3732 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3733 * make full use of any rings they may have. We will use the 3734 * PSRTYPE register to control how many rings we use within the PF. 3735 */ 3736 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3737 rss_i = 4; 3738 3739 /* Fill out hash function seeds */ 3740 ixgbe_store_key(adapter); 3741 3742 /* Fill out redirection table */ 3743 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3744 3745 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3746 if (j == rss_i) 3747 j = 0; 3748 3749 adapter->rss_indir_tbl[i] = j; 3750 } 3751 3752 ixgbe_store_reta(adapter); 3753 } 3754 3755 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3756 { 3757 struct ixgbe_hw *hw = &adapter->hw; 3758 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3759 unsigned int pf_pool = adapter->num_vfs; 3760 int i, j; 3761 3762 /* Fill out hash function seeds */ 3763 for (i = 0; i < 10; i++) 3764 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), 3765 *(adapter->rss_key + i)); 3766 3767 /* Fill out the redirection table */ 3768 for (i = 0, j = 0; i < 64; i++, j++) { 3769 if (j == rss_i) 3770 j = 0; 3771 3772 adapter->rss_indir_tbl[i] = j; 3773 } 3774 3775 ixgbe_store_vfreta(adapter); 3776 } 3777 3778 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3779 { 3780 struct ixgbe_hw *hw = &adapter->hw; 3781 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3782 u32 rxcsum; 3783 3784 /* Disable indicating checksum in descriptor, enables RSS hash */ 3785 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3786 rxcsum |= IXGBE_RXCSUM_PCSD; 3787 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3788 3789 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3790 if (adapter->ring_feature[RING_F_RSS].mask) 3791 mrqc = IXGBE_MRQC_RSSEN; 3792 } else { 3793 u8 tcs = netdev_get_num_tc(adapter->netdev); 3794 3795 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3796 if (tcs > 4) 3797 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3798 else if (tcs > 1) 3799 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3800 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3801 IXGBE_82599_VMDQ_4Q_MASK) 3802 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3803 else 3804 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3805 } else { 3806 if (tcs > 4) 3807 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3808 else if (tcs > 1) 3809 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3810 else 3811 mrqc = IXGBE_MRQC_RSSEN; 3812 } 3813 } 3814 3815 /* Perform hash on these packet types */ 3816 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3817 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3818 IXGBE_MRQC_RSS_FIELD_IPV6 | 3819 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3820 3821 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3822 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3823 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3824 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3825 3826 if ((hw->mac.type >= ixgbe_mac_X550) && 3827 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3828 unsigned int pf_pool = adapter->num_vfs; 3829 3830 /* Enable VF RSS mode */ 3831 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3832 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3833 3834 /* Setup RSS through the VF registers */ 3835 ixgbe_setup_vfreta(adapter); 3836 vfmrqc = IXGBE_MRQC_RSSEN; 3837 vfmrqc |= rss_field; 3838 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); 3839 } else { 3840 ixgbe_setup_reta(adapter); 3841 mrqc |= rss_field; 3842 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3843 } 3844 } 3845 3846 /** 3847 * ixgbe_configure_rscctl - enable RSC for the indicated ring 3848 * @adapter: address of board private structure 3849 * @index: index of ring to set 3850 **/ 3851 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 3852 struct ixgbe_ring *ring) 3853 { 3854 struct ixgbe_hw *hw = &adapter->hw; 3855 u32 rscctrl; 3856 u8 reg_idx = ring->reg_idx; 3857 3858 if (!ring_is_rsc_enabled(ring)) 3859 return; 3860 3861 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 3862 rscctrl |= IXGBE_RSCCTL_RSCEN; 3863 /* 3864 * we must limit the number of descriptors so that the 3865 * total size of max desc * buf_len is not greater 3866 * than 65536 3867 */ 3868 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 3869 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 3870 } 3871 3872 #define IXGBE_MAX_RX_DESC_POLL 10 3873 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 3874 struct ixgbe_ring *ring) 3875 { 3876 struct ixgbe_hw *hw = &adapter->hw; 3877 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3878 u32 rxdctl; 3879 u8 reg_idx = ring->reg_idx; 3880 3881 if (ixgbe_removed(hw->hw_addr)) 3882 return; 3883 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3884 if (hw->mac.type == ixgbe_mac_82598EB && 3885 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3886 return; 3887 3888 do { 3889 usleep_range(1000, 2000); 3890 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3891 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 3892 3893 if (!wait_loop) { 3894 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 3895 "the polling period\n", reg_idx); 3896 } 3897 } 3898 3899 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 3900 struct ixgbe_ring *ring) 3901 { 3902 struct ixgbe_hw *hw = &adapter->hw; 3903 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 3904 u32 rxdctl; 3905 u8 reg_idx = ring->reg_idx; 3906 3907 if (ixgbe_removed(hw->hw_addr)) 3908 return; 3909 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3910 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 3911 3912 /* write value back with RXDCTL.ENABLE bit cleared */ 3913 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3914 3915 if (hw->mac.type == ixgbe_mac_82598EB && 3916 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3917 return; 3918 3919 /* the hardware may take up to 100us to really disable the rx queue */ 3920 do { 3921 udelay(10); 3922 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3923 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 3924 3925 if (!wait_loop) { 3926 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 3927 "the polling period\n", reg_idx); 3928 } 3929 } 3930 3931 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 3932 struct ixgbe_ring *ring) 3933 { 3934 struct ixgbe_hw *hw = &adapter->hw; 3935 union ixgbe_adv_rx_desc *rx_desc; 3936 u64 rdba = ring->dma; 3937 u32 rxdctl; 3938 u8 reg_idx = ring->reg_idx; 3939 3940 /* disable queue to avoid issues while updating state */ 3941 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 3942 ixgbe_disable_rx_queue(adapter, ring); 3943 3944 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 3945 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 3946 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 3947 ring->count * sizeof(union ixgbe_adv_rx_desc)); 3948 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 3949 IXGBE_WRITE_FLUSH(hw); 3950 3951 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 3952 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 3953 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 3954 3955 ixgbe_configure_srrctl(adapter, ring); 3956 ixgbe_configure_rscctl(adapter, ring); 3957 3958 if (hw->mac.type == ixgbe_mac_82598EB) { 3959 /* 3960 * enable cache line friendly hardware writes: 3961 * PTHRESH=32 descriptors (half the internal cache), 3962 * this also removes ugly rx_no_buffer_count increment 3963 * HTHRESH=4 descriptors (to minimize latency on fetch) 3964 * WTHRESH=8 burst writeback up to two cache lines 3965 */ 3966 rxdctl &= ~0x3FFFFF; 3967 rxdctl |= 0x080420; 3968 #if (PAGE_SIZE < 8192) 3969 } else { 3970 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 3971 IXGBE_RXDCTL_RLPML_EN); 3972 3973 /* Limit the maximum frame size so we don't overrun the skb */ 3974 if (ring_uses_build_skb(ring) && 3975 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 3976 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 3977 IXGBE_RXDCTL_RLPML_EN; 3978 #endif 3979 } 3980 3981 /* initialize rx_buffer_info */ 3982 memset(ring->rx_buffer_info, 0, 3983 sizeof(struct ixgbe_rx_buffer) * ring->count); 3984 3985 /* initialize Rx descriptor 0 */ 3986 rx_desc = IXGBE_RX_DESC(ring, 0); 3987 rx_desc->wb.upper.length = 0; 3988 3989 /* enable receive descriptor ring */ 3990 rxdctl |= IXGBE_RXDCTL_ENABLE; 3991 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 3992 3993 ixgbe_rx_desc_queue_enable(adapter, ring); 3994 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 3995 } 3996 3997 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 3998 { 3999 struct ixgbe_hw *hw = &adapter->hw; 4000 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4001 u16 pool; 4002 4003 /* PSRTYPE must be initialized in non 82598 adapters */ 4004 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4005 IXGBE_PSRTYPE_UDPHDR | 4006 IXGBE_PSRTYPE_IPV4HDR | 4007 IXGBE_PSRTYPE_L2HDR | 4008 IXGBE_PSRTYPE_IPV6HDR; 4009 4010 if (hw->mac.type == ixgbe_mac_82598EB) 4011 return; 4012 4013 if (rss_i > 3) 4014 psrtype |= 2u << 29; 4015 else if (rss_i > 1) 4016 psrtype |= 1u << 29; 4017 4018 for_each_set_bit(pool, &adapter->fwd_bitmask, 32) 4019 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4020 } 4021 4022 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4023 { 4024 struct ixgbe_hw *hw = &adapter->hw; 4025 u32 reg_offset, vf_shift; 4026 u32 gcr_ext, vmdctl; 4027 int i; 4028 4029 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4030 return; 4031 4032 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4033 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4034 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4035 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4036 vmdctl |= IXGBE_VT_CTL_REPLEN; 4037 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4038 4039 vf_shift = VMDQ_P(0) % 32; 4040 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4041 4042 /* Enable only the PF's pool for Tx/Rx */ 4043 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4044 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4045 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4046 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4047 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4048 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4049 4050 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4051 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4052 4053 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4054 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4055 4056 /* 4057 * Set up VF register offsets for selected VT Mode, 4058 * i.e. 32 or 64 VFs for SR-IOV 4059 */ 4060 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4061 case IXGBE_82599_VMDQ_8Q_MASK: 4062 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4063 break; 4064 case IXGBE_82599_VMDQ_4Q_MASK: 4065 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4066 break; 4067 default: 4068 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4069 break; 4070 } 4071 4072 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4073 4074 for (i = 0; i < adapter->num_vfs; i++) { 4075 /* configure spoof checking */ 4076 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4077 adapter->vfinfo[i].spoofchk_enabled); 4078 4079 /* Enable/Disable RSS query feature */ 4080 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4081 adapter->vfinfo[i].rss_query_enabled); 4082 } 4083 } 4084 4085 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4086 { 4087 struct ixgbe_hw *hw = &adapter->hw; 4088 struct net_device *netdev = adapter->netdev; 4089 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4090 struct ixgbe_ring *rx_ring; 4091 int i; 4092 u32 mhadd, hlreg0; 4093 4094 #ifdef IXGBE_FCOE 4095 /* adjust max frame to be able to do baby jumbo for FCoE */ 4096 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4097 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4098 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4099 4100 #endif /* IXGBE_FCOE */ 4101 4102 /* adjust max frame to be at least the size of a standard frame */ 4103 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4104 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4105 4106 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4107 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4108 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4109 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4110 4111 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4112 } 4113 4114 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4115 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4116 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4117 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4118 4119 /* 4120 * Setup the HW Rx Head and Tail Descriptor Pointers and 4121 * the Base and Length of the Rx Descriptor Ring 4122 */ 4123 for (i = 0; i < adapter->num_rx_queues; i++) { 4124 rx_ring = adapter->rx_ring[i]; 4125 4126 clear_ring_rsc_enabled(rx_ring); 4127 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4128 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4129 4130 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4131 set_ring_rsc_enabled(rx_ring); 4132 4133 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4134 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4135 4136 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4137 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4138 continue; 4139 4140 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4141 4142 #if (PAGE_SIZE < 8192) 4143 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4144 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4145 4146 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4147 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4148 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4149 #endif 4150 } 4151 } 4152 4153 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4154 { 4155 struct ixgbe_hw *hw = &adapter->hw; 4156 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4157 4158 switch (hw->mac.type) { 4159 case ixgbe_mac_82598EB: 4160 /* 4161 * For VMDq support of different descriptor types or 4162 * buffer sizes through the use of multiple SRRCTL 4163 * registers, RDRXCTL.MVMEN must be set to 1 4164 * 4165 * also, the manual doesn't mention it clearly but DCA hints 4166 * will only use queue 0's tags unless this bit is set. Side 4167 * effects of setting this bit are only that SRRCTL must be 4168 * fully programmed [0..15] 4169 */ 4170 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4171 break; 4172 case ixgbe_mac_X550: 4173 case ixgbe_mac_X550EM_x: 4174 case ixgbe_mac_x550em_a: 4175 if (adapter->num_vfs) 4176 rdrxctl |= IXGBE_RDRXCTL_PSP; 4177 /* fall through for older HW */ 4178 case ixgbe_mac_82599EB: 4179 case ixgbe_mac_X540: 4180 /* Disable RSC for ACK packets */ 4181 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4182 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4183 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4184 /* hardware requires some bits to be set by default */ 4185 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4186 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4187 break; 4188 default: 4189 /* We should do nothing since we don't know this hardware */ 4190 return; 4191 } 4192 4193 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4194 } 4195 4196 /** 4197 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4198 * @adapter: board private structure 4199 * 4200 * Configure the Rx unit of the MAC after a reset. 4201 **/ 4202 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4203 { 4204 struct ixgbe_hw *hw = &adapter->hw; 4205 int i; 4206 u32 rxctrl, rfctl; 4207 4208 /* disable receives while setting up the descriptors */ 4209 hw->mac.ops.disable_rx(hw); 4210 4211 ixgbe_setup_psrtype(adapter); 4212 ixgbe_setup_rdrxctl(adapter); 4213 4214 /* RSC Setup */ 4215 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4216 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4217 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4218 rfctl |= IXGBE_RFCTL_RSC_DIS; 4219 4220 /* disable NFS filtering */ 4221 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4222 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4223 4224 /* Program registers for the distribution of queues */ 4225 ixgbe_setup_mrqc(adapter); 4226 4227 /* set_rx_buffer_len must be called before ring initialization */ 4228 ixgbe_set_rx_buffer_len(adapter); 4229 4230 /* 4231 * Setup the HW Rx Head and Tail Descriptor Pointers and 4232 * the Base and Length of the Rx Descriptor Ring 4233 */ 4234 for (i = 0; i < adapter->num_rx_queues; i++) 4235 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4236 4237 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4238 /* disable drop enable for 82598 parts */ 4239 if (hw->mac.type == ixgbe_mac_82598EB) 4240 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4241 4242 /* enable all receives */ 4243 rxctrl |= IXGBE_RXCTRL_RXEN; 4244 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4245 } 4246 4247 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4248 __be16 proto, u16 vid) 4249 { 4250 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4251 struct ixgbe_hw *hw = &adapter->hw; 4252 4253 /* add VID to filter table */ 4254 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4255 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4256 4257 set_bit(vid, adapter->active_vlans); 4258 4259 return 0; 4260 } 4261 4262 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4263 { 4264 u32 vlvf; 4265 int idx; 4266 4267 /* short cut the special case */ 4268 if (vlan == 0) 4269 return 0; 4270 4271 /* Search for the vlan id in the VLVF entries */ 4272 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4273 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4274 if ((vlvf & VLAN_VID_MASK) == vlan) 4275 break; 4276 } 4277 4278 return idx; 4279 } 4280 4281 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4282 { 4283 struct ixgbe_hw *hw = &adapter->hw; 4284 u32 bits, word; 4285 int idx; 4286 4287 idx = ixgbe_find_vlvf_entry(hw, vid); 4288 if (!idx) 4289 return; 4290 4291 /* See if any other pools are set for this VLAN filter 4292 * entry other than the PF. 4293 */ 4294 word = idx * 2 + (VMDQ_P(0) / 32); 4295 bits = ~BIT(VMDQ_P(0) % 32); 4296 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4297 4298 /* Disable the filter so this falls into the default pool. */ 4299 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4300 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4301 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4302 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4303 } 4304 } 4305 4306 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4307 __be16 proto, u16 vid) 4308 { 4309 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4310 struct ixgbe_hw *hw = &adapter->hw; 4311 4312 /* remove VID from filter table */ 4313 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4314 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4315 4316 clear_bit(vid, adapter->active_vlans); 4317 4318 return 0; 4319 } 4320 4321 /** 4322 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4323 * @adapter: driver data 4324 */ 4325 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4326 { 4327 struct ixgbe_hw *hw = &adapter->hw; 4328 u32 vlnctrl; 4329 int i, j; 4330 4331 switch (hw->mac.type) { 4332 case ixgbe_mac_82598EB: 4333 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4334 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4335 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4336 break; 4337 case ixgbe_mac_82599EB: 4338 case ixgbe_mac_X540: 4339 case ixgbe_mac_X550: 4340 case ixgbe_mac_X550EM_x: 4341 case ixgbe_mac_x550em_a: 4342 for (i = 0; i < adapter->num_rx_queues; i++) { 4343 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4344 4345 if (ring->l2_accel_priv) 4346 continue; 4347 j = ring->reg_idx; 4348 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4349 vlnctrl &= ~IXGBE_RXDCTL_VME; 4350 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4351 } 4352 break; 4353 default: 4354 break; 4355 } 4356 } 4357 4358 /** 4359 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4360 * @adapter: driver data 4361 */ 4362 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4363 { 4364 struct ixgbe_hw *hw = &adapter->hw; 4365 u32 vlnctrl; 4366 int i, j; 4367 4368 switch (hw->mac.type) { 4369 case ixgbe_mac_82598EB: 4370 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4371 vlnctrl |= IXGBE_VLNCTRL_VME; 4372 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4373 break; 4374 case ixgbe_mac_82599EB: 4375 case ixgbe_mac_X540: 4376 case ixgbe_mac_X550: 4377 case ixgbe_mac_X550EM_x: 4378 case ixgbe_mac_x550em_a: 4379 for (i = 0; i < adapter->num_rx_queues; i++) { 4380 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4381 4382 if (ring->l2_accel_priv) 4383 continue; 4384 j = ring->reg_idx; 4385 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4386 vlnctrl |= IXGBE_RXDCTL_VME; 4387 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4388 } 4389 break; 4390 default: 4391 break; 4392 } 4393 } 4394 4395 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4396 { 4397 struct ixgbe_hw *hw = &adapter->hw; 4398 u32 vlnctrl, i; 4399 4400 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4401 4402 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4403 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4404 vlnctrl |= IXGBE_VLNCTRL_VFE; 4405 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4406 } else { 4407 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4408 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4409 return; 4410 } 4411 4412 /* Nothing to do for 82598 */ 4413 if (hw->mac.type == ixgbe_mac_82598EB) 4414 return; 4415 4416 /* We are already in VLAN promisc, nothing to do */ 4417 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4418 return; 4419 4420 /* Set flag so we don't redo unnecessary work */ 4421 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4422 4423 /* Add PF to all active pools */ 4424 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4425 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4426 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4427 4428 vlvfb |= BIT(VMDQ_P(0) % 32); 4429 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4430 } 4431 4432 /* Set all bits in the VLAN filter table array */ 4433 for (i = hw->mac.vft_size; i--;) 4434 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4435 } 4436 4437 #define VFTA_BLOCK_SIZE 8 4438 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4439 { 4440 struct ixgbe_hw *hw = &adapter->hw; 4441 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4442 u32 vid_start = vfta_offset * 32; 4443 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4444 u32 i, vid, word, bits; 4445 4446 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4447 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4448 4449 /* pull VLAN ID from VLVF */ 4450 vid = vlvf & VLAN_VID_MASK; 4451 4452 /* only concern outselves with a certain range */ 4453 if (vid < vid_start || vid >= vid_end) 4454 continue; 4455 4456 if (vlvf) { 4457 /* record VLAN ID in VFTA */ 4458 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4459 4460 /* if PF is part of this then continue */ 4461 if (test_bit(vid, adapter->active_vlans)) 4462 continue; 4463 } 4464 4465 /* remove PF from the pool */ 4466 word = i * 2 + VMDQ_P(0) / 32; 4467 bits = ~BIT(VMDQ_P(0) % 32); 4468 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4469 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4470 } 4471 4472 /* extract values from active_vlans and write back to VFTA */ 4473 for (i = VFTA_BLOCK_SIZE; i--;) { 4474 vid = (vfta_offset + i) * 32; 4475 word = vid / BITS_PER_LONG; 4476 bits = vid % BITS_PER_LONG; 4477 4478 vfta[i] |= adapter->active_vlans[word] >> bits; 4479 4480 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4481 } 4482 } 4483 4484 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4485 { 4486 struct ixgbe_hw *hw = &adapter->hw; 4487 u32 vlnctrl, i; 4488 4489 /* Set VLAN filtering to enabled */ 4490 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4491 vlnctrl |= IXGBE_VLNCTRL_VFE; 4492 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4493 4494 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4495 hw->mac.type == ixgbe_mac_82598EB) 4496 return; 4497 4498 /* We are not in VLAN promisc, nothing to do */ 4499 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4500 return; 4501 4502 /* Set flag so we don't redo unnecessary work */ 4503 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4504 4505 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4506 ixgbe_scrub_vfta(adapter, i); 4507 } 4508 4509 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4510 { 4511 u16 vid = 1; 4512 4513 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4514 4515 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4516 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4517 } 4518 4519 /** 4520 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4521 * @netdev: network interface device structure 4522 * 4523 * Writes multicast address list to the MTA hash table. 4524 * Returns: -ENOMEM on failure 4525 * 0 on no addresses written 4526 * X on writing X addresses to MTA 4527 **/ 4528 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4529 { 4530 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4531 struct ixgbe_hw *hw = &adapter->hw; 4532 4533 if (!netif_running(netdev)) 4534 return 0; 4535 4536 if (hw->mac.ops.update_mc_addr_list) 4537 hw->mac.ops.update_mc_addr_list(hw, netdev); 4538 else 4539 return -ENOMEM; 4540 4541 #ifdef CONFIG_PCI_IOV 4542 ixgbe_restore_vf_multicasts(adapter); 4543 #endif 4544 4545 return netdev_mc_count(netdev); 4546 } 4547 4548 #ifdef CONFIG_PCI_IOV 4549 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4550 { 4551 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4552 struct ixgbe_hw *hw = &adapter->hw; 4553 int i; 4554 4555 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4556 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4557 4558 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4559 hw->mac.ops.set_rar(hw, i, 4560 mac_table->addr, 4561 mac_table->pool, 4562 IXGBE_RAH_AV); 4563 else 4564 hw->mac.ops.clear_rar(hw, i); 4565 } 4566 } 4567 4568 #endif 4569 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4570 { 4571 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4572 struct ixgbe_hw *hw = &adapter->hw; 4573 int i; 4574 4575 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4576 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4577 continue; 4578 4579 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4580 4581 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4582 hw->mac.ops.set_rar(hw, i, 4583 mac_table->addr, 4584 mac_table->pool, 4585 IXGBE_RAH_AV); 4586 else 4587 hw->mac.ops.clear_rar(hw, i); 4588 } 4589 } 4590 4591 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4592 { 4593 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4594 struct ixgbe_hw *hw = &adapter->hw; 4595 int i; 4596 4597 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4598 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4599 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4600 } 4601 4602 ixgbe_sync_mac_table(adapter); 4603 } 4604 4605 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4606 { 4607 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4608 struct ixgbe_hw *hw = &adapter->hw; 4609 int i, count = 0; 4610 4611 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4612 /* do not count default RAR as available */ 4613 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4614 continue; 4615 4616 /* only count unused and addresses that belong to us */ 4617 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4618 if (mac_table->pool != pool) 4619 continue; 4620 } 4621 4622 count++; 4623 } 4624 4625 return count; 4626 } 4627 4628 /* this function destroys the first RAR entry */ 4629 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4630 { 4631 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4632 struct ixgbe_hw *hw = &adapter->hw; 4633 4634 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4635 mac_table->pool = VMDQ_P(0); 4636 4637 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4638 4639 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4640 IXGBE_RAH_AV); 4641 } 4642 4643 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4644 const u8 *addr, u16 pool) 4645 { 4646 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4647 struct ixgbe_hw *hw = &adapter->hw; 4648 int i; 4649 4650 if (is_zero_ether_addr(addr)) 4651 return -EINVAL; 4652 4653 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4654 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4655 continue; 4656 4657 ether_addr_copy(mac_table->addr, addr); 4658 mac_table->pool = pool; 4659 4660 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4661 IXGBE_MAC_STATE_IN_USE; 4662 4663 ixgbe_sync_mac_table(adapter); 4664 4665 return i; 4666 } 4667 4668 return -ENOMEM; 4669 } 4670 4671 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4672 const u8 *addr, u16 pool) 4673 { 4674 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4675 struct ixgbe_hw *hw = &adapter->hw; 4676 int i; 4677 4678 if (is_zero_ether_addr(addr)) 4679 return -EINVAL; 4680 4681 /* search table for addr, if found clear IN_USE flag and sync */ 4682 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4683 /* we can only delete an entry if it is in use */ 4684 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4685 continue; 4686 /* we only care about entries that belong to the given pool */ 4687 if (mac_table->pool != pool) 4688 continue; 4689 /* we only care about a specific MAC address */ 4690 if (!ether_addr_equal(addr, mac_table->addr)) 4691 continue; 4692 4693 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4694 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4695 4696 ixgbe_sync_mac_table(adapter); 4697 4698 return 0; 4699 } 4700 4701 return -ENOMEM; 4702 } 4703 /** 4704 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4705 * @netdev: network interface device structure 4706 * 4707 * Writes unicast address list to the RAR table. 4708 * Returns: -ENOMEM on failure/insufficient address space 4709 * 0 on no addresses written 4710 * X on writing X addresses to the RAR table 4711 **/ 4712 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4713 { 4714 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4715 int count = 0; 4716 4717 /* return ENOMEM indicating insufficient memory for addresses */ 4718 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) 4719 return -ENOMEM; 4720 4721 if (!netdev_uc_empty(netdev)) { 4722 struct netdev_hw_addr *ha; 4723 netdev_for_each_uc_addr(ha, netdev) { 4724 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4725 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4726 count++; 4727 } 4728 } 4729 return count; 4730 } 4731 4732 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4733 { 4734 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4735 int ret; 4736 4737 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4738 4739 return min_t(int, ret, 0); 4740 } 4741 4742 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4743 { 4744 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4745 4746 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4747 4748 return 0; 4749 } 4750 4751 /** 4752 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4753 * @netdev: network interface device structure 4754 * 4755 * The set_rx_method entry point is called whenever the unicast/multicast 4756 * address list or the network interface flags are updated. This routine is 4757 * responsible for configuring the hardware for proper unicast, multicast and 4758 * promiscuous mode. 4759 **/ 4760 void ixgbe_set_rx_mode(struct net_device *netdev) 4761 { 4762 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4763 struct ixgbe_hw *hw = &adapter->hw; 4764 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4765 netdev_features_t features = netdev->features; 4766 int count; 4767 4768 /* Check for Promiscuous and All Multicast modes */ 4769 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4770 4771 /* set all bits that we expect to always be set */ 4772 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4773 fctrl |= IXGBE_FCTRL_BAM; 4774 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4775 fctrl |= IXGBE_FCTRL_PMCF; 4776 4777 /* clear the bits we are changing the status of */ 4778 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4779 if (netdev->flags & IFF_PROMISC) { 4780 hw->addr_ctrl.user_set_promisc = true; 4781 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4782 vmolr |= IXGBE_VMOLR_MPE; 4783 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4784 } else { 4785 if (netdev->flags & IFF_ALLMULTI) { 4786 fctrl |= IXGBE_FCTRL_MPE; 4787 vmolr |= IXGBE_VMOLR_MPE; 4788 } 4789 hw->addr_ctrl.user_set_promisc = false; 4790 } 4791 4792 /* 4793 * Write addresses to available RAR registers, if there is not 4794 * sufficient space to store all the addresses then enable 4795 * unicast promiscuous mode 4796 */ 4797 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4798 fctrl |= IXGBE_FCTRL_UPE; 4799 vmolr |= IXGBE_VMOLR_ROPE; 4800 } 4801 4802 /* Write addresses to the MTA, if the attempt fails 4803 * then we should just turn on promiscuous mode so 4804 * that we can at least receive multicast traffic 4805 */ 4806 count = ixgbe_write_mc_addr_list(netdev); 4807 if (count < 0) { 4808 fctrl |= IXGBE_FCTRL_MPE; 4809 vmolr |= IXGBE_VMOLR_MPE; 4810 } else if (count) { 4811 vmolr |= IXGBE_VMOLR_ROMPE; 4812 } 4813 4814 if (hw->mac.type != ixgbe_mac_82598EB) { 4815 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4816 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4817 IXGBE_VMOLR_ROPE); 4818 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4819 } 4820 4821 /* This is useful for sniffing bad packets. */ 4822 if (features & NETIF_F_RXALL) { 4823 /* UPE and MPE will be handled by normal PROMISC logic 4824 * in e1000e_set_rx_mode */ 4825 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4826 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4827 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4828 4829 fctrl &= ~(IXGBE_FCTRL_DPF); 4830 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4831 } 4832 4833 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4834 4835 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4836 ixgbe_vlan_strip_enable(adapter); 4837 else 4838 ixgbe_vlan_strip_disable(adapter); 4839 4840 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 4841 ixgbe_vlan_promisc_disable(adapter); 4842 else 4843 ixgbe_vlan_promisc_enable(adapter); 4844 } 4845 4846 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 4847 { 4848 int q_idx; 4849 4850 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4851 napi_enable(&adapter->q_vector[q_idx]->napi); 4852 } 4853 4854 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 4855 { 4856 int q_idx; 4857 4858 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 4859 napi_disable(&adapter->q_vector[q_idx]->napi); 4860 } 4861 4862 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 4863 { 4864 struct ixgbe_hw *hw = &adapter->hw; 4865 u32 vxlanctrl; 4866 4867 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 4868 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 4869 return; 4870 4871 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) && ~mask; 4872 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 4873 4874 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 4875 adapter->vxlan_port = 0; 4876 4877 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 4878 adapter->geneve_port = 0; 4879 } 4880 4881 #ifdef CONFIG_IXGBE_DCB 4882 /** 4883 * ixgbe_configure_dcb - Configure DCB hardware 4884 * @adapter: ixgbe adapter struct 4885 * 4886 * This is called by the driver on open to configure the DCB hardware. 4887 * This is also called by the gennetlink interface when reconfiguring 4888 * the DCB state. 4889 */ 4890 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 4891 { 4892 struct ixgbe_hw *hw = &adapter->hw; 4893 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4894 4895 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 4896 if (hw->mac.type == ixgbe_mac_82598EB) 4897 netif_set_gso_max_size(adapter->netdev, 65536); 4898 return; 4899 } 4900 4901 if (hw->mac.type == ixgbe_mac_82598EB) 4902 netif_set_gso_max_size(adapter->netdev, 32768); 4903 4904 #ifdef IXGBE_FCOE 4905 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 4906 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 4907 #endif 4908 4909 /* reconfigure the hardware */ 4910 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 4911 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4912 DCB_TX_CONFIG); 4913 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 4914 DCB_RX_CONFIG); 4915 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 4916 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 4917 ixgbe_dcb_hw_ets(&adapter->hw, 4918 adapter->ixgbe_ieee_ets, 4919 max_frame); 4920 ixgbe_dcb_hw_pfc_config(&adapter->hw, 4921 adapter->ixgbe_ieee_pfc->pfc_en, 4922 adapter->ixgbe_ieee_ets->prio_tc); 4923 } 4924 4925 /* Enable RSS Hash per TC */ 4926 if (hw->mac.type != ixgbe_mac_82598EB) { 4927 u32 msb = 0; 4928 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 4929 4930 while (rss_i) { 4931 msb++; 4932 rss_i >>= 1; 4933 } 4934 4935 /* write msb to all 8 TCs in one write */ 4936 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 4937 } 4938 } 4939 #endif 4940 4941 /* Additional bittime to account for IXGBE framing */ 4942 #define IXGBE_ETH_FRAMING 20 4943 4944 /** 4945 * ixgbe_hpbthresh - calculate high water mark for flow control 4946 * 4947 * @adapter: board private structure to calculate for 4948 * @pb: packet buffer to calculate 4949 */ 4950 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 4951 { 4952 struct ixgbe_hw *hw = &adapter->hw; 4953 struct net_device *dev = adapter->netdev; 4954 int link, tc, kb, marker; 4955 u32 dv_id, rx_pba; 4956 4957 /* Calculate max LAN frame size */ 4958 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 4959 4960 #ifdef IXGBE_FCOE 4961 /* FCoE traffic class uses FCOE jumbo frames */ 4962 if ((dev->features & NETIF_F_FCOE_MTU) && 4963 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 4964 (pb == ixgbe_fcoe_get_tc(adapter))) 4965 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4966 #endif 4967 4968 /* Calculate delay value for device */ 4969 switch (hw->mac.type) { 4970 case ixgbe_mac_X540: 4971 case ixgbe_mac_X550: 4972 case ixgbe_mac_X550EM_x: 4973 case ixgbe_mac_x550em_a: 4974 dv_id = IXGBE_DV_X540(link, tc); 4975 break; 4976 default: 4977 dv_id = IXGBE_DV(link, tc); 4978 break; 4979 } 4980 4981 /* Loopback switch introduces additional latency */ 4982 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4983 dv_id += IXGBE_B2BT(tc); 4984 4985 /* Delay value is calculated in bit times convert to KB */ 4986 kb = IXGBE_BT2KB(dv_id); 4987 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 4988 4989 marker = rx_pba - kb; 4990 4991 /* It is possible that the packet buffer is not large enough 4992 * to provide required headroom. In this case throw an error 4993 * to user and a do the best we can. 4994 */ 4995 if (marker < 0) { 4996 e_warn(drv, "Packet Buffer(%i) can not provide enough" 4997 "headroom to support flow control." 4998 "Decrease MTU or number of traffic classes\n", pb); 4999 marker = tc + 1; 5000 } 5001 5002 return marker; 5003 } 5004 5005 /** 5006 * ixgbe_lpbthresh - calculate low water mark for for flow control 5007 * 5008 * @adapter: board private structure to calculate for 5009 * @pb: packet buffer to calculate 5010 */ 5011 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5012 { 5013 struct ixgbe_hw *hw = &adapter->hw; 5014 struct net_device *dev = adapter->netdev; 5015 int tc; 5016 u32 dv_id; 5017 5018 /* Calculate max LAN frame size */ 5019 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5020 5021 #ifdef IXGBE_FCOE 5022 /* FCoE traffic class uses FCOE jumbo frames */ 5023 if ((dev->features & NETIF_F_FCOE_MTU) && 5024 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5025 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5026 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5027 #endif 5028 5029 /* Calculate delay value for device */ 5030 switch (hw->mac.type) { 5031 case ixgbe_mac_X540: 5032 case ixgbe_mac_X550: 5033 case ixgbe_mac_X550EM_x: 5034 case ixgbe_mac_x550em_a: 5035 dv_id = IXGBE_LOW_DV_X540(tc); 5036 break; 5037 default: 5038 dv_id = IXGBE_LOW_DV(tc); 5039 break; 5040 } 5041 5042 /* Delay value is calculated in bit times convert to KB */ 5043 return IXGBE_BT2KB(dv_id); 5044 } 5045 5046 /* 5047 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5048 */ 5049 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5050 { 5051 struct ixgbe_hw *hw = &adapter->hw; 5052 int num_tc = netdev_get_num_tc(adapter->netdev); 5053 int i; 5054 5055 if (!num_tc) 5056 num_tc = 1; 5057 5058 for (i = 0; i < num_tc; i++) { 5059 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5060 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5061 5062 /* Low water marks must not be larger than high water marks */ 5063 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5064 hw->fc.low_water[i] = 0; 5065 } 5066 5067 for (; i < MAX_TRAFFIC_CLASS; i++) 5068 hw->fc.high_water[i] = 0; 5069 } 5070 5071 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5072 { 5073 struct ixgbe_hw *hw = &adapter->hw; 5074 int hdrm; 5075 u8 tc = netdev_get_num_tc(adapter->netdev); 5076 5077 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5078 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5079 hdrm = 32 << adapter->fdir_pballoc; 5080 else 5081 hdrm = 0; 5082 5083 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5084 ixgbe_pbthresh_setup(adapter); 5085 } 5086 5087 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5088 { 5089 struct ixgbe_hw *hw = &adapter->hw; 5090 struct hlist_node *node2; 5091 struct ixgbe_fdir_filter *filter; 5092 5093 spin_lock(&adapter->fdir_perfect_lock); 5094 5095 if (!hlist_empty(&adapter->fdir_filter_list)) 5096 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5097 5098 hlist_for_each_entry_safe(filter, node2, 5099 &adapter->fdir_filter_list, fdir_node) { 5100 ixgbe_fdir_write_perfect_filter_82599(hw, 5101 &filter->filter, 5102 filter->sw_idx, 5103 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5104 IXGBE_FDIR_DROP_QUEUE : 5105 adapter->rx_ring[filter->action]->reg_idx); 5106 } 5107 5108 spin_unlock(&adapter->fdir_perfect_lock); 5109 } 5110 5111 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 5112 struct ixgbe_adapter *adapter) 5113 { 5114 struct ixgbe_hw *hw = &adapter->hw; 5115 u32 vmolr; 5116 5117 /* No unicast promiscuous support for VMDQ devices. */ 5118 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 5119 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 5120 5121 /* clear the affected bit */ 5122 vmolr &= ~IXGBE_VMOLR_MPE; 5123 5124 if (dev->flags & IFF_ALLMULTI) { 5125 vmolr |= IXGBE_VMOLR_MPE; 5126 } else { 5127 vmolr |= IXGBE_VMOLR_ROMPE; 5128 hw->mac.ops.update_mc_addr_list(hw, dev); 5129 } 5130 ixgbe_write_uc_addr_list(adapter->netdev, pool); 5131 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 5132 } 5133 5134 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) 5135 { 5136 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5137 int rss_i = adapter->num_rx_queues_per_pool; 5138 struct ixgbe_hw *hw = &adapter->hw; 5139 u16 pool = vadapter->pool; 5140 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 5141 IXGBE_PSRTYPE_UDPHDR | 5142 IXGBE_PSRTYPE_IPV4HDR | 5143 IXGBE_PSRTYPE_L2HDR | 5144 IXGBE_PSRTYPE_IPV6HDR; 5145 5146 if (hw->mac.type == ixgbe_mac_82598EB) 5147 return; 5148 5149 if (rss_i > 3) 5150 psrtype |= 2u << 29; 5151 else if (rss_i > 1) 5152 psrtype |= 1u << 29; 5153 5154 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 5155 } 5156 5157 /** 5158 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5159 * @rx_ring: ring to free buffers from 5160 **/ 5161 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5162 { 5163 u16 i = rx_ring->next_to_clean; 5164 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5165 5166 /* Free all the Rx ring sk_buffs */ 5167 while (i != rx_ring->next_to_alloc) { 5168 if (rx_buffer->skb) { 5169 struct sk_buff *skb = rx_buffer->skb; 5170 if (IXGBE_CB(skb)->page_released) 5171 dma_unmap_page_attrs(rx_ring->dev, 5172 IXGBE_CB(skb)->dma, 5173 ixgbe_rx_pg_size(rx_ring), 5174 DMA_FROM_DEVICE, 5175 IXGBE_RX_DMA_ATTR); 5176 dev_kfree_skb(skb); 5177 } 5178 5179 /* Invalidate cache lines that may have been written to by 5180 * device so that we avoid corrupting memory. 5181 */ 5182 dma_sync_single_range_for_cpu(rx_ring->dev, 5183 rx_buffer->dma, 5184 rx_buffer->page_offset, 5185 ixgbe_rx_bufsz(rx_ring), 5186 DMA_FROM_DEVICE); 5187 5188 /* free resources associated with mapping */ 5189 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5190 ixgbe_rx_pg_size(rx_ring), 5191 DMA_FROM_DEVICE, 5192 IXGBE_RX_DMA_ATTR); 5193 __page_frag_cache_drain(rx_buffer->page, 5194 rx_buffer->pagecnt_bias); 5195 5196 i++; 5197 rx_buffer++; 5198 if (i == rx_ring->count) { 5199 i = 0; 5200 rx_buffer = rx_ring->rx_buffer_info; 5201 } 5202 } 5203 5204 rx_ring->next_to_alloc = 0; 5205 rx_ring->next_to_clean = 0; 5206 rx_ring->next_to_use = 0; 5207 } 5208 5209 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, 5210 struct ixgbe_ring *rx_ring) 5211 { 5212 struct ixgbe_adapter *adapter = vadapter->real_adapter; 5213 int index = rx_ring->queue_index + vadapter->rx_base_queue; 5214 5215 /* shutdown specific queue receive and wait for dma to settle */ 5216 ixgbe_disable_rx_queue(adapter, rx_ring); 5217 usleep_range(10000, 20000); 5218 ixgbe_irq_disable_queues(adapter, BIT_ULL(index)); 5219 ixgbe_clean_rx_ring(rx_ring); 5220 rx_ring->l2_accel_priv = NULL; 5221 } 5222 5223 static int ixgbe_fwd_ring_down(struct net_device *vdev, 5224 struct ixgbe_fwd_adapter *accel) 5225 { 5226 struct ixgbe_adapter *adapter = accel->real_adapter; 5227 unsigned int rxbase = accel->rx_base_queue; 5228 unsigned int txbase = accel->tx_base_queue; 5229 int i; 5230 5231 netif_tx_stop_all_queues(vdev); 5232 5233 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5234 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5235 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; 5236 } 5237 5238 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5239 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; 5240 adapter->tx_ring[txbase + i]->netdev = adapter->netdev; 5241 } 5242 5243 5244 return 0; 5245 } 5246 5247 static int ixgbe_fwd_ring_up(struct net_device *vdev, 5248 struct ixgbe_fwd_adapter *accel) 5249 { 5250 struct ixgbe_adapter *adapter = accel->real_adapter; 5251 unsigned int rxbase, txbase, queues; 5252 int i, baseq, err = 0; 5253 5254 if (!test_bit(accel->pool, &adapter->fwd_bitmask)) 5255 return 0; 5256 5257 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5258 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 5259 accel->pool, adapter->num_rx_pools, 5260 baseq, baseq + adapter->num_rx_queues_per_pool, 5261 adapter->fwd_bitmask); 5262 5263 accel->netdev = vdev; 5264 accel->rx_base_queue = rxbase = baseq; 5265 accel->tx_base_queue = txbase = baseq; 5266 5267 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5268 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); 5269 5270 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5271 adapter->rx_ring[rxbase + i]->netdev = vdev; 5272 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; 5273 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); 5274 } 5275 5276 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 5277 adapter->tx_ring[txbase + i]->netdev = vdev; 5278 adapter->tx_ring[txbase + i]->l2_accel_priv = accel; 5279 } 5280 5281 queues = min_t(unsigned int, 5282 adapter->num_rx_queues_per_pool, vdev->num_tx_queues); 5283 err = netif_set_real_num_tx_queues(vdev, queues); 5284 if (err) 5285 goto fwd_queue_err; 5286 5287 err = netif_set_real_num_rx_queues(vdev, queues); 5288 if (err) 5289 goto fwd_queue_err; 5290 5291 if (is_valid_ether_addr(vdev->dev_addr)) 5292 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); 5293 5294 ixgbe_fwd_psrtype(accel); 5295 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 5296 return err; 5297 fwd_queue_err: 5298 ixgbe_fwd_ring_down(vdev, accel); 5299 return err; 5300 } 5301 5302 static int ixgbe_upper_dev_walk(struct net_device *upper, void *data) 5303 { 5304 if (netif_is_macvlan(upper)) { 5305 struct macvlan_dev *dfwd = netdev_priv(upper); 5306 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 5307 5308 if (dfwd->fwd_priv) 5309 ixgbe_fwd_ring_up(upper, vadapter); 5310 } 5311 5312 return 0; 5313 } 5314 5315 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5316 { 5317 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5318 ixgbe_upper_dev_walk, NULL); 5319 } 5320 5321 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5322 { 5323 struct ixgbe_hw *hw = &adapter->hw; 5324 5325 ixgbe_configure_pb(adapter); 5326 #ifdef CONFIG_IXGBE_DCB 5327 ixgbe_configure_dcb(adapter); 5328 #endif 5329 /* 5330 * We must restore virtualization before VLANs or else 5331 * the VLVF registers will not be populated 5332 */ 5333 ixgbe_configure_virtualization(adapter); 5334 5335 ixgbe_set_rx_mode(adapter->netdev); 5336 ixgbe_restore_vlan(adapter); 5337 5338 switch (hw->mac.type) { 5339 case ixgbe_mac_82599EB: 5340 case ixgbe_mac_X540: 5341 hw->mac.ops.disable_rx_buff(hw); 5342 break; 5343 default: 5344 break; 5345 } 5346 5347 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5348 ixgbe_init_fdir_signature_82599(&adapter->hw, 5349 adapter->fdir_pballoc); 5350 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5351 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5352 adapter->fdir_pballoc); 5353 ixgbe_fdir_filter_restore(adapter); 5354 } 5355 5356 switch (hw->mac.type) { 5357 case ixgbe_mac_82599EB: 5358 case ixgbe_mac_X540: 5359 hw->mac.ops.enable_rx_buff(hw); 5360 break; 5361 default: 5362 break; 5363 } 5364 5365 #ifdef CONFIG_IXGBE_DCA 5366 /* configure DCA */ 5367 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5368 ixgbe_setup_dca(adapter); 5369 #endif /* CONFIG_IXGBE_DCA */ 5370 5371 #ifdef IXGBE_FCOE 5372 /* configure FCoE L2 filters, redirection table, and Rx control */ 5373 ixgbe_configure_fcoe(adapter); 5374 5375 #endif /* IXGBE_FCOE */ 5376 ixgbe_configure_tx(adapter); 5377 ixgbe_configure_rx(adapter); 5378 ixgbe_configure_dfwd(adapter); 5379 } 5380 5381 /** 5382 * ixgbe_sfp_link_config - set up SFP+ link 5383 * @adapter: pointer to private adapter struct 5384 **/ 5385 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5386 { 5387 /* 5388 * We are assuming the worst case scenario here, and that 5389 * is that an SFP was inserted/removed after the reset 5390 * but before SFP detection was enabled. As such the best 5391 * solution is to just start searching as soon as we start 5392 */ 5393 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5394 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5395 5396 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5397 adapter->sfp_poll_time = 0; 5398 } 5399 5400 /** 5401 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5402 * @hw: pointer to private hardware struct 5403 * 5404 * Returns 0 on success, negative on failure 5405 **/ 5406 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5407 { 5408 u32 speed; 5409 bool autoneg, link_up = false; 5410 int ret = IXGBE_ERR_LINK_SETUP; 5411 5412 if (hw->mac.ops.check_link) 5413 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5414 5415 if (ret) 5416 return ret; 5417 5418 speed = hw->phy.autoneg_advertised; 5419 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5420 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5421 &autoneg); 5422 if (ret) 5423 return ret; 5424 5425 if (hw->mac.ops.setup_link) 5426 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5427 5428 return ret; 5429 } 5430 5431 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5432 { 5433 struct ixgbe_hw *hw = &adapter->hw; 5434 u32 gpie = 0; 5435 5436 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5437 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5438 IXGBE_GPIE_OCD; 5439 gpie |= IXGBE_GPIE_EIAME; 5440 /* 5441 * use EIAM to auto-mask when MSI-X interrupt is asserted 5442 * this saves a register write for every interrupt 5443 */ 5444 switch (hw->mac.type) { 5445 case ixgbe_mac_82598EB: 5446 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5447 break; 5448 case ixgbe_mac_82599EB: 5449 case ixgbe_mac_X540: 5450 case ixgbe_mac_X550: 5451 case ixgbe_mac_X550EM_x: 5452 case ixgbe_mac_x550em_a: 5453 default: 5454 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5455 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5456 break; 5457 } 5458 } else { 5459 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5460 * specifically only auto mask tx and rx interrupts */ 5461 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5462 } 5463 5464 /* XXX: to interrupt immediately for EICS writes, enable this */ 5465 /* gpie |= IXGBE_GPIE_EIMEN; */ 5466 5467 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5468 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5469 5470 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5471 case IXGBE_82599_VMDQ_8Q_MASK: 5472 gpie |= IXGBE_GPIE_VTMODE_16; 5473 break; 5474 case IXGBE_82599_VMDQ_4Q_MASK: 5475 gpie |= IXGBE_GPIE_VTMODE_32; 5476 break; 5477 default: 5478 gpie |= IXGBE_GPIE_VTMODE_64; 5479 break; 5480 } 5481 } 5482 5483 /* Enable Thermal over heat sensor interrupt */ 5484 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5485 switch (adapter->hw.mac.type) { 5486 case ixgbe_mac_82599EB: 5487 gpie |= IXGBE_SDP0_GPIEN_8259X; 5488 break; 5489 default: 5490 break; 5491 } 5492 } 5493 5494 /* Enable fan failure interrupt */ 5495 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5496 gpie |= IXGBE_SDP1_GPIEN(hw); 5497 5498 switch (hw->mac.type) { 5499 case ixgbe_mac_82599EB: 5500 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5501 break; 5502 case ixgbe_mac_X550EM_x: 5503 case ixgbe_mac_x550em_a: 5504 gpie |= IXGBE_SDP0_GPIEN_X540; 5505 break; 5506 default: 5507 break; 5508 } 5509 5510 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5511 } 5512 5513 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5514 { 5515 struct ixgbe_hw *hw = &adapter->hw; 5516 int err; 5517 u32 ctrl_ext; 5518 5519 ixgbe_get_hw_control(adapter); 5520 ixgbe_setup_gpie(adapter); 5521 5522 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5523 ixgbe_configure_msix(adapter); 5524 else 5525 ixgbe_configure_msi_and_legacy(adapter); 5526 5527 /* enable the optics for 82599 SFP+ fiber */ 5528 if (hw->mac.ops.enable_tx_laser) 5529 hw->mac.ops.enable_tx_laser(hw); 5530 5531 if (hw->phy.ops.set_phy_power) 5532 hw->phy.ops.set_phy_power(hw, true); 5533 5534 smp_mb__before_atomic(); 5535 clear_bit(__IXGBE_DOWN, &adapter->state); 5536 ixgbe_napi_enable_all(adapter); 5537 5538 if (ixgbe_is_sfp(hw)) { 5539 ixgbe_sfp_link_config(adapter); 5540 } else { 5541 err = ixgbe_non_sfp_link_config(hw); 5542 if (err) 5543 e_err(probe, "link_config FAILED %d\n", err); 5544 } 5545 5546 /* clear any pending interrupts, may auto mask */ 5547 IXGBE_READ_REG(hw, IXGBE_EICR); 5548 ixgbe_irq_enable(adapter, true, true); 5549 5550 /* 5551 * If this adapter has a fan, check to see if we had a failure 5552 * before we enabled the interrupt. 5553 */ 5554 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5555 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5556 if (esdp & IXGBE_ESDP_SDP1) 5557 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5558 } 5559 5560 /* bring the link up in the watchdog, this could race with our first 5561 * link up interrupt but shouldn't be a problem */ 5562 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5563 adapter->link_check_timeout = jiffies; 5564 mod_timer(&adapter->service_timer, jiffies); 5565 5566 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5567 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5568 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5569 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5570 } 5571 5572 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5573 { 5574 WARN_ON(in_interrupt()); 5575 /* put off any impending NetWatchDogTimeout */ 5576 netif_trans_update(adapter->netdev); 5577 5578 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5579 usleep_range(1000, 2000); 5580 if (adapter->hw.phy.type == ixgbe_phy_fw) 5581 ixgbe_watchdog_link_is_down(adapter); 5582 ixgbe_down(adapter); 5583 /* 5584 * If SR-IOV enabled then wait a bit before bringing the adapter 5585 * back up to give the VFs time to respond to the reset. The 5586 * two second wait is based upon the watchdog timer cycle in 5587 * the VF driver. 5588 */ 5589 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5590 msleep(2000); 5591 ixgbe_up(adapter); 5592 clear_bit(__IXGBE_RESETTING, &adapter->state); 5593 } 5594 5595 void ixgbe_up(struct ixgbe_adapter *adapter) 5596 { 5597 /* hardware has been reset, we need to reload some things */ 5598 ixgbe_configure(adapter); 5599 5600 ixgbe_up_complete(adapter); 5601 } 5602 5603 void ixgbe_reset(struct ixgbe_adapter *adapter) 5604 { 5605 struct ixgbe_hw *hw = &adapter->hw; 5606 struct net_device *netdev = adapter->netdev; 5607 int err; 5608 5609 if (ixgbe_removed(hw->hw_addr)) 5610 return; 5611 /* lock SFP init bit to prevent race conditions with the watchdog */ 5612 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5613 usleep_range(1000, 2000); 5614 5615 /* clear all SFP and link config related flags while holding SFP_INIT */ 5616 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5617 IXGBE_FLAG2_SFP_NEEDS_RESET); 5618 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5619 5620 err = hw->mac.ops.init_hw(hw); 5621 switch (err) { 5622 case 0: 5623 case IXGBE_ERR_SFP_NOT_PRESENT: 5624 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5625 break; 5626 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5627 e_dev_err("master disable timed out\n"); 5628 break; 5629 case IXGBE_ERR_EEPROM_VERSION: 5630 /* We are running on a pre-production device, log a warning */ 5631 e_dev_warn("This device is a pre-production adapter/LOM. " 5632 "Please be aware there may be issues associated with " 5633 "your hardware. If you are experiencing problems " 5634 "please contact your Intel or hardware " 5635 "representative who provided you with this " 5636 "hardware.\n"); 5637 break; 5638 default: 5639 e_dev_err("Hardware Error: %d\n", err); 5640 } 5641 5642 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5643 5644 /* flush entries out of MAC table */ 5645 ixgbe_flush_sw_mac_table(adapter); 5646 __dev_uc_unsync(netdev, NULL); 5647 5648 /* do not flush user set addresses */ 5649 ixgbe_mac_set_default_filter(adapter); 5650 5651 /* update SAN MAC vmdq pool selection */ 5652 if (hw->mac.san_mac_rar_index) 5653 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5654 5655 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5656 ixgbe_ptp_reset(adapter); 5657 5658 if (hw->phy.ops.set_phy_power) { 5659 if (!netif_running(adapter->netdev) && !adapter->wol) 5660 hw->phy.ops.set_phy_power(hw, false); 5661 else 5662 hw->phy.ops.set_phy_power(hw, true); 5663 } 5664 } 5665 5666 /** 5667 * ixgbe_clean_tx_ring - Free Tx Buffers 5668 * @tx_ring: ring to be cleaned 5669 **/ 5670 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5671 { 5672 u16 i = tx_ring->next_to_clean; 5673 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5674 5675 while (i != tx_ring->next_to_use) { 5676 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5677 5678 /* Free all the Tx ring sk_buffs */ 5679 if (ring_is_xdp(tx_ring)) 5680 page_frag_free(tx_buffer->data); 5681 else 5682 dev_kfree_skb_any(tx_buffer->skb); 5683 5684 /* unmap skb header data */ 5685 dma_unmap_single(tx_ring->dev, 5686 dma_unmap_addr(tx_buffer, dma), 5687 dma_unmap_len(tx_buffer, len), 5688 DMA_TO_DEVICE); 5689 5690 /* check for eop_desc to determine the end of the packet */ 5691 eop_desc = tx_buffer->next_to_watch; 5692 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5693 5694 /* unmap remaining buffers */ 5695 while (tx_desc != eop_desc) { 5696 tx_buffer++; 5697 tx_desc++; 5698 i++; 5699 if (unlikely(i == tx_ring->count)) { 5700 i = 0; 5701 tx_buffer = tx_ring->tx_buffer_info; 5702 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5703 } 5704 5705 /* unmap any remaining paged data */ 5706 if (dma_unmap_len(tx_buffer, len)) 5707 dma_unmap_page(tx_ring->dev, 5708 dma_unmap_addr(tx_buffer, dma), 5709 dma_unmap_len(tx_buffer, len), 5710 DMA_TO_DEVICE); 5711 } 5712 5713 /* move us one more past the eop_desc for start of next pkt */ 5714 tx_buffer++; 5715 i++; 5716 if (unlikely(i == tx_ring->count)) { 5717 i = 0; 5718 tx_buffer = tx_ring->tx_buffer_info; 5719 } 5720 } 5721 5722 /* reset BQL for queue */ 5723 if (!ring_is_xdp(tx_ring)) 5724 netdev_tx_reset_queue(txring_txq(tx_ring)); 5725 5726 /* reset next_to_use and next_to_clean */ 5727 tx_ring->next_to_use = 0; 5728 tx_ring->next_to_clean = 0; 5729 } 5730 5731 /** 5732 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5733 * @adapter: board private structure 5734 **/ 5735 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5736 { 5737 int i; 5738 5739 for (i = 0; i < adapter->num_rx_queues; i++) 5740 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5741 } 5742 5743 /** 5744 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5745 * @adapter: board private structure 5746 **/ 5747 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5748 { 5749 int i; 5750 5751 for (i = 0; i < adapter->num_tx_queues; i++) 5752 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5753 for (i = 0; i < adapter->num_xdp_queues; i++) 5754 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5755 } 5756 5757 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5758 { 5759 struct hlist_node *node2; 5760 struct ixgbe_fdir_filter *filter; 5761 5762 spin_lock(&adapter->fdir_perfect_lock); 5763 5764 hlist_for_each_entry_safe(filter, node2, 5765 &adapter->fdir_filter_list, fdir_node) { 5766 hlist_del(&filter->fdir_node); 5767 kfree(filter); 5768 } 5769 adapter->fdir_filter_count = 0; 5770 5771 spin_unlock(&adapter->fdir_perfect_lock); 5772 } 5773 5774 static int ixgbe_disable_macvlan(struct net_device *upper, void *data) 5775 { 5776 if (netif_is_macvlan(upper)) { 5777 struct macvlan_dev *vlan = netdev_priv(upper); 5778 5779 if (vlan->fwd_priv) { 5780 netif_tx_stop_all_queues(upper); 5781 netif_carrier_off(upper); 5782 netif_tx_disable(upper); 5783 } 5784 } 5785 5786 return 0; 5787 } 5788 5789 void ixgbe_down(struct ixgbe_adapter *adapter) 5790 { 5791 struct net_device *netdev = adapter->netdev; 5792 struct ixgbe_hw *hw = &adapter->hw; 5793 int i; 5794 5795 /* signal that we are down to the interrupt handler */ 5796 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5797 return; /* do nothing if already down */ 5798 5799 /* disable receives */ 5800 hw->mac.ops.disable_rx(hw); 5801 5802 /* disable all enabled rx queues */ 5803 for (i = 0; i < adapter->num_rx_queues; i++) 5804 /* this call also flushes the previous write */ 5805 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5806 5807 usleep_range(10000, 20000); 5808 5809 netif_tx_stop_all_queues(netdev); 5810 5811 /* call carrier off first to avoid false dev_watchdog timeouts */ 5812 netif_carrier_off(netdev); 5813 netif_tx_disable(netdev); 5814 5815 /* disable any upper devices */ 5816 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5817 ixgbe_disable_macvlan, NULL); 5818 5819 ixgbe_irq_disable(adapter); 5820 5821 ixgbe_napi_disable_all(adapter); 5822 5823 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5824 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5825 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5826 5827 del_timer_sync(&adapter->service_timer); 5828 5829 if (adapter->num_vfs) { 5830 /* Clear EITR Select mapping */ 5831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5832 5833 /* Mark all the VFs as inactive */ 5834 for (i = 0 ; i < adapter->num_vfs; i++) 5835 adapter->vfinfo[i].clear_to_send = false; 5836 5837 /* ping all the active vfs to let them know we are going down */ 5838 ixgbe_ping_all_vfs(adapter); 5839 5840 /* Disable all VFTE/VFRE TX/RX */ 5841 ixgbe_disable_tx_rx(adapter); 5842 } 5843 5844 /* disable transmits in the hardware now that interrupts are off */ 5845 for (i = 0; i < adapter->num_tx_queues; i++) { 5846 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5847 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5848 } 5849 for (i = 0; i < adapter->num_xdp_queues; i++) { 5850 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5851 5852 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5853 } 5854 5855 /* Disable the Tx DMA engine on 82599 and later MAC */ 5856 switch (hw->mac.type) { 5857 case ixgbe_mac_82599EB: 5858 case ixgbe_mac_X540: 5859 case ixgbe_mac_X550: 5860 case ixgbe_mac_X550EM_x: 5861 case ixgbe_mac_x550em_a: 5862 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5863 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5864 ~IXGBE_DMATXCTL_TE)); 5865 break; 5866 default: 5867 break; 5868 } 5869 5870 if (!pci_channel_offline(adapter->pdev)) 5871 ixgbe_reset(adapter); 5872 5873 /* power down the optics for 82599 SFP+ fiber */ 5874 if (hw->mac.ops.disable_tx_laser) 5875 hw->mac.ops.disable_tx_laser(hw); 5876 5877 ixgbe_clean_all_tx_rings(adapter); 5878 ixgbe_clean_all_rx_rings(adapter); 5879 } 5880 5881 /** 5882 * ixgbe_eee_capable - helper function to determine EEE support on X550 5883 * @adapter: board private structure 5884 */ 5885 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5886 { 5887 struct ixgbe_hw *hw = &adapter->hw; 5888 5889 switch (hw->device_id) { 5890 case IXGBE_DEV_ID_X550EM_A_1G_T: 5891 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 5892 if (!hw->phy.eee_speeds_supported) 5893 break; 5894 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 5895 if (!hw->phy.eee_speeds_advertised) 5896 break; 5897 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 5898 break; 5899 default: 5900 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 5901 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 5902 break; 5903 } 5904 } 5905 5906 /** 5907 * ixgbe_tx_timeout - Respond to a Tx Hang 5908 * @netdev: network interface device structure 5909 **/ 5910 static void ixgbe_tx_timeout(struct net_device *netdev) 5911 { 5912 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5913 5914 /* Do the reset outside of interrupt context */ 5915 ixgbe_tx_timeout_reset(adapter); 5916 } 5917 5918 #ifdef CONFIG_IXGBE_DCB 5919 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 5920 { 5921 struct ixgbe_hw *hw = &adapter->hw; 5922 struct tc_configuration *tc; 5923 int j; 5924 5925 switch (hw->mac.type) { 5926 case ixgbe_mac_82598EB: 5927 case ixgbe_mac_82599EB: 5928 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 5929 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 5930 break; 5931 case ixgbe_mac_X540: 5932 case ixgbe_mac_X550: 5933 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 5934 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 5935 break; 5936 case ixgbe_mac_X550EM_x: 5937 case ixgbe_mac_x550em_a: 5938 default: 5939 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 5940 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 5941 break; 5942 } 5943 5944 /* Configure DCB traffic classes */ 5945 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 5946 tc = &adapter->dcb_cfg.tc_config[j]; 5947 tc->path[DCB_TX_CONFIG].bwg_id = 0; 5948 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 5949 tc->path[DCB_RX_CONFIG].bwg_id = 0; 5950 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 5951 tc->dcb_pfc = pfc_disabled; 5952 } 5953 5954 /* Initialize default user to priority mapping, UPx->TC0 */ 5955 tc = &adapter->dcb_cfg.tc_config[0]; 5956 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 5957 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 5958 5959 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 5960 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 5961 adapter->dcb_cfg.pfc_mode_enable = false; 5962 adapter->dcb_set_bitmap = 0x00; 5963 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 5964 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 5965 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 5966 sizeof(adapter->temp_dcb_cfg)); 5967 } 5968 #endif 5969 5970 /** 5971 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 5972 * @adapter: board private structure to initialize 5973 * 5974 * ixgbe_sw_init initializes the Adapter private data structure. 5975 * Fields are initialized based on PCI device information and 5976 * OS network device settings (MTU size). 5977 **/ 5978 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 5979 const struct ixgbe_info *ii) 5980 { 5981 struct ixgbe_hw *hw = &adapter->hw; 5982 struct pci_dev *pdev = adapter->pdev; 5983 unsigned int rss, fdir; 5984 u32 fwsm; 5985 int i; 5986 5987 /* PCI config space info */ 5988 5989 hw->vendor_id = pdev->vendor; 5990 hw->device_id = pdev->device; 5991 hw->revision_id = pdev->revision; 5992 hw->subsystem_vendor_id = pdev->subsystem_vendor; 5993 hw->subsystem_device_id = pdev->subsystem_device; 5994 5995 /* get_invariants needs the device IDs */ 5996 ii->get_invariants(hw); 5997 5998 /* Set common capability flags and settings */ 5999 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6000 adapter->ring_feature[RING_F_RSS].limit = rss; 6001 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6002 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6003 adapter->atr_sample_rate = 20; 6004 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6005 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6006 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6007 #ifdef CONFIG_IXGBE_DCA 6008 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6009 #endif 6010 #ifdef CONFIG_IXGBE_DCB 6011 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6012 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6013 #endif 6014 #ifdef IXGBE_FCOE 6015 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6016 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6017 #ifdef CONFIG_IXGBE_DCB 6018 /* Default traffic class to use for FCoE */ 6019 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6020 #endif /* CONFIG_IXGBE_DCB */ 6021 #endif /* IXGBE_FCOE */ 6022 6023 /* initialize static ixgbe jump table entries */ 6024 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6025 GFP_KERNEL); 6026 if (!adapter->jump_tables[0]) 6027 return -ENOMEM; 6028 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6029 6030 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6031 adapter->jump_tables[i] = NULL; 6032 6033 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6034 hw->mac.num_rar_entries, 6035 GFP_ATOMIC); 6036 if (!adapter->mac_table) 6037 return -ENOMEM; 6038 6039 if (ixgbe_init_rss_key(adapter)) 6040 return -ENOMEM; 6041 6042 /* Set MAC specific capability flags and exceptions */ 6043 switch (hw->mac.type) { 6044 case ixgbe_mac_82598EB: 6045 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6046 6047 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6048 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6049 6050 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6051 adapter->ring_feature[RING_F_FDIR].limit = 0; 6052 adapter->atr_sample_rate = 0; 6053 adapter->fdir_pballoc = 0; 6054 #ifdef IXGBE_FCOE 6055 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6056 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6057 #ifdef CONFIG_IXGBE_DCB 6058 adapter->fcoe.up = 0; 6059 #endif /* IXGBE_DCB */ 6060 #endif /* IXGBE_FCOE */ 6061 break; 6062 case ixgbe_mac_82599EB: 6063 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6064 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6065 break; 6066 case ixgbe_mac_X540: 6067 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6068 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6069 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6070 break; 6071 case ixgbe_mac_x550em_a: 6072 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6073 switch (hw->device_id) { 6074 case IXGBE_DEV_ID_X550EM_A_1G_T: 6075 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6076 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6077 break; 6078 default: 6079 break; 6080 } 6081 /* fall through */ 6082 case ixgbe_mac_X550EM_x: 6083 #ifdef CONFIG_IXGBE_DCB 6084 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6085 #endif 6086 #ifdef IXGBE_FCOE 6087 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6088 #ifdef CONFIG_IXGBE_DCB 6089 adapter->fcoe.up = 0; 6090 #endif /* IXGBE_DCB */ 6091 #endif /* IXGBE_FCOE */ 6092 /* Fall Through */ 6093 case ixgbe_mac_X550: 6094 if (hw->mac.type == ixgbe_mac_X550) 6095 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6096 #ifdef CONFIG_IXGBE_DCA 6097 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6098 #endif 6099 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6100 break; 6101 default: 6102 break; 6103 } 6104 6105 #ifdef IXGBE_FCOE 6106 /* FCoE support exists, always init the FCoE lock */ 6107 spin_lock_init(&adapter->fcoe.lock); 6108 6109 #endif 6110 /* n-tuple support exists, always init our spinlock */ 6111 spin_lock_init(&adapter->fdir_perfect_lock); 6112 6113 #ifdef CONFIG_IXGBE_DCB 6114 ixgbe_init_dcb(adapter); 6115 #endif 6116 6117 /* default flow control settings */ 6118 hw->fc.requested_mode = ixgbe_fc_full; 6119 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6120 ixgbe_pbthresh_setup(adapter); 6121 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6122 hw->fc.send_xon = true; 6123 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6124 6125 #ifdef CONFIG_PCI_IOV 6126 if (max_vfs > 0) 6127 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6128 6129 /* assign number of SR-IOV VFs */ 6130 if (hw->mac.type != ixgbe_mac_82598EB) { 6131 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6132 max_vfs = 0; 6133 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6134 } 6135 } 6136 #endif /* CONFIG_PCI_IOV */ 6137 6138 /* enable itr by default in dynamic mode */ 6139 adapter->rx_itr_setting = 1; 6140 adapter->tx_itr_setting = 1; 6141 6142 /* set default ring sizes */ 6143 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6144 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6145 6146 /* set default work limits */ 6147 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6148 6149 /* initialize eeprom parameters */ 6150 if (ixgbe_init_eeprom_params_generic(hw)) { 6151 e_dev_err("EEPROM initialization failed\n"); 6152 return -EIO; 6153 } 6154 6155 /* PF holds first pool slot */ 6156 set_bit(0, &adapter->fwd_bitmask); 6157 set_bit(__IXGBE_DOWN, &adapter->state); 6158 6159 return 0; 6160 } 6161 6162 /** 6163 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6164 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6165 * 6166 * Return 0 on success, negative on failure 6167 **/ 6168 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6169 { 6170 struct device *dev = tx_ring->dev; 6171 int orig_node = dev_to_node(dev); 6172 int ring_node = -1; 6173 int size; 6174 6175 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6176 6177 if (tx_ring->q_vector) 6178 ring_node = tx_ring->q_vector->numa_node; 6179 6180 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6181 if (!tx_ring->tx_buffer_info) 6182 tx_ring->tx_buffer_info = vmalloc(size); 6183 if (!tx_ring->tx_buffer_info) 6184 goto err; 6185 6186 u64_stats_init(&tx_ring->syncp); 6187 6188 /* round up to nearest 4K */ 6189 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6190 tx_ring->size = ALIGN(tx_ring->size, 4096); 6191 6192 set_dev_node(dev, ring_node); 6193 tx_ring->desc = dma_alloc_coherent(dev, 6194 tx_ring->size, 6195 &tx_ring->dma, 6196 GFP_KERNEL); 6197 set_dev_node(dev, orig_node); 6198 if (!tx_ring->desc) 6199 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6200 &tx_ring->dma, GFP_KERNEL); 6201 if (!tx_ring->desc) 6202 goto err; 6203 6204 tx_ring->next_to_use = 0; 6205 tx_ring->next_to_clean = 0; 6206 return 0; 6207 6208 err: 6209 vfree(tx_ring->tx_buffer_info); 6210 tx_ring->tx_buffer_info = NULL; 6211 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6212 return -ENOMEM; 6213 } 6214 6215 /** 6216 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6217 * @adapter: board private structure 6218 * 6219 * If this function returns with an error, then it's possible one or 6220 * more of the rings is populated (while the rest are not). It is the 6221 * callers duty to clean those orphaned rings. 6222 * 6223 * Return 0 on success, negative on failure 6224 **/ 6225 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6226 { 6227 int i, j = 0, err = 0; 6228 6229 for (i = 0; i < adapter->num_tx_queues; i++) { 6230 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6231 if (!err) 6232 continue; 6233 6234 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6235 goto err_setup_tx; 6236 } 6237 for (j = 0; j < adapter->num_xdp_queues; j++) { 6238 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6239 if (!err) 6240 continue; 6241 6242 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6243 goto err_setup_tx; 6244 } 6245 6246 return 0; 6247 err_setup_tx: 6248 /* rewind the index freeing the rings as we go */ 6249 while (j--) 6250 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6251 while (i--) 6252 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6253 return err; 6254 } 6255 6256 /** 6257 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6258 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6259 * 6260 * Returns 0 on success, negative on failure 6261 **/ 6262 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6263 struct ixgbe_ring *rx_ring) 6264 { 6265 struct device *dev = rx_ring->dev; 6266 int orig_node = dev_to_node(dev); 6267 int ring_node = -1; 6268 int size; 6269 6270 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6271 6272 if (rx_ring->q_vector) 6273 ring_node = rx_ring->q_vector->numa_node; 6274 6275 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6276 if (!rx_ring->rx_buffer_info) 6277 rx_ring->rx_buffer_info = vmalloc(size); 6278 if (!rx_ring->rx_buffer_info) 6279 goto err; 6280 6281 u64_stats_init(&rx_ring->syncp); 6282 6283 /* Round up to nearest 4K */ 6284 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6285 rx_ring->size = ALIGN(rx_ring->size, 4096); 6286 6287 set_dev_node(dev, ring_node); 6288 rx_ring->desc = dma_alloc_coherent(dev, 6289 rx_ring->size, 6290 &rx_ring->dma, 6291 GFP_KERNEL); 6292 set_dev_node(dev, orig_node); 6293 if (!rx_ring->desc) 6294 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6295 &rx_ring->dma, GFP_KERNEL); 6296 if (!rx_ring->desc) 6297 goto err; 6298 6299 rx_ring->next_to_clean = 0; 6300 rx_ring->next_to_use = 0; 6301 6302 rx_ring->xdp_prog = adapter->xdp_prog; 6303 6304 return 0; 6305 err: 6306 vfree(rx_ring->rx_buffer_info); 6307 rx_ring->rx_buffer_info = NULL; 6308 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6309 return -ENOMEM; 6310 } 6311 6312 /** 6313 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6314 * @adapter: board private structure 6315 * 6316 * If this function returns with an error, then it's possible one or 6317 * more of the rings is populated (while the rest are not). It is the 6318 * callers duty to clean those orphaned rings. 6319 * 6320 * Return 0 on success, negative on failure 6321 **/ 6322 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6323 { 6324 int i, err = 0; 6325 6326 for (i = 0; i < adapter->num_rx_queues; i++) { 6327 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6328 if (!err) 6329 continue; 6330 6331 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6332 goto err_setup_rx; 6333 } 6334 6335 #ifdef IXGBE_FCOE 6336 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6337 if (!err) 6338 #endif 6339 return 0; 6340 err_setup_rx: 6341 /* rewind the index freeing the rings as we go */ 6342 while (i--) 6343 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6344 return err; 6345 } 6346 6347 /** 6348 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6349 * @tx_ring: Tx descriptor ring for a specific queue 6350 * 6351 * Free all transmit software resources 6352 **/ 6353 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6354 { 6355 ixgbe_clean_tx_ring(tx_ring); 6356 6357 vfree(tx_ring->tx_buffer_info); 6358 tx_ring->tx_buffer_info = NULL; 6359 6360 /* if not set, then don't free */ 6361 if (!tx_ring->desc) 6362 return; 6363 6364 dma_free_coherent(tx_ring->dev, tx_ring->size, 6365 tx_ring->desc, tx_ring->dma); 6366 6367 tx_ring->desc = NULL; 6368 } 6369 6370 /** 6371 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6372 * @adapter: board private structure 6373 * 6374 * Free all transmit software resources 6375 **/ 6376 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6377 { 6378 int i; 6379 6380 for (i = 0; i < adapter->num_tx_queues; i++) 6381 if (adapter->tx_ring[i]->desc) 6382 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6383 for (i = 0; i < adapter->num_xdp_queues; i++) 6384 if (adapter->xdp_ring[i]->desc) 6385 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6386 } 6387 6388 /** 6389 * ixgbe_free_rx_resources - Free Rx Resources 6390 * @rx_ring: ring to clean the resources from 6391 * 6392 * Free all receive software resources 6393 **/ 6394 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6395 { 6396 ixgbe_clean_rx_ring(rx_ring); 6397 6398 rx_ring->xdp_prog = NULL; 6399 vfree(rx_ring->rx_buffer_info); 6400 rx_ring->rx_buffer_info = NULL; 6401 6402 /* if not set, then don't free */ 6403 if (!rx_ring->desc) 6404 return; 6405 6406 dma_free_coherent(rx_ring->dev, rx_ring->size, 6407 rx_ring->desc, rx_ring->dma); 6408 6409 rx_ring->desc = NULL; 6410 } 6411 6412 /** 6413 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6414 * @adapter: board private structure 6415 * 6416 * Free all receive software resources 6417 **/ 6418 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6419 { 6420 int i; 6421 6422 #ifdef IXGBE_FCOE 6423 ixgbe_free_fcoe_ddp_resources(adapter); 6424 6425 #endif 6426 for (i = 0; i < adapter->num_rx_queues; i++) 6427 if (adapter->rx_ring[i]->desc) 6428 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6429 } 6430 6431 /** 6432 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6433 * @netdev: network interface device structure 6434 * @new_mtu: new value for maximum frame size 6435 * 6436 * Returns 0 on success, negative on failure 6437 **/ 6438 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6439 { 6440 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6441 6442 /* 6443 * For 82599EB we cannot allow legacy VFs to enable their receive 6444 * paths when MTU greater than 1500 is configured. So display a 6445 * warning that legacy VFs will be disabled. 6446 */ 6447 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6448 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6449 (new_mtu > ETH_DATA_LEN)) 6450 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6451 6452 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6453 6454 /* must set new MTU before calling down or up */ 6455 netdev->mtu = new_mtu; 6456 6457 if (netif_running(netdev)) 6458 ixgbe_reinit_locked(adapter); 6459 6460 return 0; 6461 } 6462 6463 /** 6464 * ixgbe_open - Called when a network interface is made active 6465 * @netdev: network interface device structure 6466 * 6467 * Returns 0 on success, negative value on failure 6468 * 6469 * The open entry point is called when a network interface is made 6470 * active by the system (IFF_UP). At this point all resources needed 6471 * for transmit and receive operations are allocated, the interrupt 6472 * handler is registered with the OS, the watchdog timer is started, 6473 * and the stack is notified that the interface is ready. 6474 **/ 6475 int ixgbe_open(struct net_device *netdev) 6476 { 6477 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6478 struct ixgbe_hw *hw = &adapter->hw; 6479 int err, queues; 6480 6481 /* disallow open during test */ 6482 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6483 return -EBUSY; 6484 6485 netif_carrier_off(netdev); 6486 6487 /* allocate transmit descriptors */ 6488 err = ixgbe_setup_all_tx_resources(adapter); 6489 if (err) 6490 goto err_setup_tx; 6491 6492 /* allocate receive descriptors */ 6493 err = ixgbe_setup_all_rx_resources(adapter); 6494 if (err) 6495 goto err_setup_rx; 6496 6497 ixgbe_configure(adapter); 6498 6499 err = ixgbe_request_irq(adapter); 6500 if (err) 6501 goto err_req_irq; 6502 6503 /* Notify the stack of the actual queue counts. */ 6504 if (adapter->num_rx_pools > 1) 6505 queues = adapter->num_rx_queues_per_pool; 6506 else 6507 queues = adapter->num_tx_queues; 6508 6509 err = netif_set_real_num_tx_queues(netdev, queues); 6510 if (err) 6511 goto err_set_queues; 6512 6513 if (adapter->num_rx_pools > 1 && 6514 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) 6515 queues = IXGBE_MAX_L2A_QUEUES; 6516 else 6517 queues = adapter->num_rx_queues; 6518 err = netif_set_real_num_rx_queues(netdev, queues); 6519 if (err) 6520 goto err_set_queues; 6521 6522 ixgbe_ptp_init(adapter); 6523 6524 ixgbe_up_complete(adapter); 6525 6526 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6527 udp_tunnel_get_rx_info(netdev); 6528 6529 return 0; 6530 6531 err_set_queues: 6532 ixgbe_free_irq(adapter); 6533 err_req_irq: 6534 ixgbe_free_all_rx_resources(adapter); 6535 if (hw->phy.ops.set_phy_power && !adapter->wol) 6536 hw->phy.ops.set_phy_power(&adapter->hw, false); 6537 err_setup_rx: 6538 ixgbe_free_all_tx_resources(adapter); 6539 err_setup_tx: 6540 ixgbe_reset(adapter); 6541 6542 return err; 6543 } 6544 6545 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6546 { 6547 ixgbe_ptp_suspend(adapter); 6548 6549 if (adapter->hw.phy.ops.enter_lplu) { 6550 adapter->hw.phy.reset_disable = true; 6551 ixgbe_down(adapter); 6552 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6553 adapter->hw.phy.reset_disable = false; 6554 } else { 6555 ixgbe_down(adapter); 6556 } 6557 6558 ixgbe_free_irq(adapter); 6559 6560 ixgbe_free_all_tx_resources(adapter); 6561 ixgbe_free_all_rx_resources(adapter); 6562 } 6563 6564 /** 6565 * ixgbe_close - Disables a network interface 6566 * @netdev: network interface device structure 6567 * 6568 * Returns 0, this is not allowed to fail 6569 * 6570 * The close entry point is called when an interface is de-activated 6571 * by the OS. The hardware is still under the drivers control, but 6572 * needs to be disabled. A global MAC reset is issued to stop the 6573 * hardware, and all transmit and receive resources are freed. 6574 **/ 6575 int ixgbe_close(struct net_device *netdev) 6576 { 6577 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6578 6579 ixgbe_ptp_stop(adapter); 6580 6581 if (netif_device_present(netdev)) 6582 ixgbe_close_suspend(adapter); 6583 6584 ixgbe_fdir_filter_exit(adapter); 6585 6586 ixgbe_release_hw_control(adapter); 6587 6588 return 0; 6589 } 6590 6591 #ifdef CONFIG_PM 6592 static int ixgbe_resume(struct pci_dev *pdev) 6593 { 6594 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6595 struct net_device *netdev = adapter->netdev; 6596 u32 err; 6597 6598 adapter->hw.hw_addr = adapter->io_addr; 6599 pci_set_power_state(pdev, PCI_D0); 6600 pci_restore_state(pdev); 6601 /* 6602 * pci_restore_state clears dev->state_saved so call 6603 * pci_save_state to restore it. 6604 */ 6605 pci_save_state(pdev); 6606 6607 err = pci_enable_device_mem(pdev); 6608 if (err) { 6609 e_dev_err("Cannot enable PCI device from suspend\n"); 6610 return err; 6611 } 6612 smp_mb__before_atomic(); 6613 clear_bit(__IXGBE_DISABLED, &adapter->state); 6614 pci_set_master(pdev); 6615 6616 pci_wake_from_d3(pdev, false); 6617 6618 ixgbe_reset(adapter); 6619 6620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6621 6622 rtnl_lock(); 6623 err = ixgbe_init_interrupt_scheme(adapter); 6624 if (!err && netif_running(netdev)) 6625 err = ixgbe_open(netdev); 6626 6627 6628 if (!err) 6629 netif_device_attach(netdev); 6630 rtnl_unlock(); 6631 6632 return err; 6633 } 6634 #endif /* CONFIG_PM */ 6635 6636 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6637 { 6638 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6639 struct net_device *netdev = adapter->netdev; 6640 struct ixgbe_hw *hw = &adapter->hw; 6641 u32 ctrl, fctrl; 6642 u32 wufc = adapter->wol; 6643 #ifdef CONFIG_PM 6644 int retval = 0; 6645 #endif 6646 6647 rtnl_lock(); 6648 netif_device_detach(netdev); 6649 6650 if (netif_running(netdev)) 6651 ixgbe_close_suspend(adapter); 6652 6653 ixgbe_clear_interrupt_scheme(adapter); 6654 rtnl_unlock(); 6655 6656 #ifdef CONFIG_PM 6657 retval = pci_save_state(pdev); 6658 if (retval) 6659 return retval; 6660 6661 #endif 6662 if (hw->mac.ops.stop_link_on_d3) 6663 hw->mac.ops.stop_link_on_d3(hw); 6664 6665 if (wufc) { 6666 ixgbe_set_rx_mode(netdev); 6667 6668 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6669 if (hw->mac.ops.enable_tx_laser) 6670 hw->mac.ops.enable_tx_laser(hw); 6671 6672 /* turn on all-multi mode if wake on multicast is enabled */ 6673 if (wufc & IXGBE_WUFC_MC) { 6674 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6675 fctrl |= IXGBE_FCTRL_MPE; 6676 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6677 } 6678 6679 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6680 ctrl |= IXGBE_CTRL_GIO_DIS; 6681 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6682 6683 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6684 } else { 6685 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6686 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6687 } 6688 6689 switch (hw->mac.type) { 6690 case ixgbe_mac_82598EB: 6691 pci_wake_from_d3(pdev, false); 6692 break; 6693 case ixgbe_mac_82599EB: 6694 case ixgbe_mac_X540: 6695 case ixgbe_mac_X550: 6696 case ixgbe_mac_X550EM_x: 6697 case ixgbe_mac_x550em_a: 6698 pci_wake_from_d3(pdev, !!wufc); 6699 break; 6700 default: 6701 break; 6702 } 6703 6704 *enable_wake = !!wufc; 6705 if (hw->phy.ops.set_phy_power && !*enable_wake) 6706 hw->phy.ops.set_phy_power(hw, false); 6707 6708 ixgbe_release_hw_control(adapter); 6709 6710 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6711 pci_disable_device(pdev); 6712 6713 return 0; 6714 } 6715 6716 #ifdef CONFIG_PM 6717 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6718 { 6719 int retval; 6720 bool wake; 6721 6722 retval = __ixgbe_shutdown(pdev, &wake); 6723 if (retval) 6724 return retval; 6725 6726 if (wake) { 6727 pci_prepare_to_sleep(pdev); 6728 } else { 6729 pci_wake_from_d3(pdev, false); 6730 pci_set_power_state(pdev, PCI_D3hot); 6731 } 6732 6733 return 0; 6734 } 6735 #endif /* CONFIG_PM */ 6736 6737 static void ixgbe_shutdown(struct pci_dev *pdev) 6738 { 6739 bool wake; 6740 6741 __ixgbe_shutdown(pdev, &wake); 6742 6743 if (system_state == SYSTEM_POWER_OFF) { 6744 pci_wake_from_d3(pdev, wake); 6745 pci_set_power_state(pdev, PCI_D3hot); 6746 } 6747 } 6748 6749 /** 6750 * ixgbe_update_stats - Update the board statistics counters. 6751 * @adapter: board private structure 6752 **/ 6753 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6754 { 6755 struct net_device *netdev = adapter->netdev; 6756 struct ixgbe_hw *hw = &adapter->hw; 6757 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6758 u64 total_mpc = 0; 6759 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6760 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6761 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6762 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6763 6764 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6765 test_bit(__IXGBE_RESETTING, &adapter->state)) 6766 return; 6767 6768 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6769 u64 rsc_count = 0; 6770 u64 rsc_flush = 0; 6771 for (i = 0; i < adapter->num_rx_queues; i++) { 6772 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6773 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6774 } 6775 adapter->rsc_total_count = rsc_count; 6776 adapter->rsc_total_flush = rsc_flush; 6777 } 6778 6779 for (i = 0; i < adapter->num_rx_queues; i++) { 6780 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6781 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6782 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6783 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6784 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6785 bytes += rx_ring->stats.bytes; 6786 packets += rx_ring->stats.packets; 6787 } 6788 adapter->non_eop_descs = non_eop_descs; 6789 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6790 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6791 adapter->hw_csum_rx_error = hw_csum_rx_error; 6792 netdev->stats.rx_bytes = bytes; 6793 netdev->stats.rx_packets = packets; 6794 6795 bytes = 0; 6796 packets = 0; 6797 /* gather some stats to the adapter struct that are per queue */ 6798 for (i = 0; i < adapter->num_tx_queues; i++) { 6799 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6800 restart_queue += tx_ring->tx_stats.restart_queue; 6801 tx_busy += tx_ring->tx_stats.tx_busy; 6802 bytes += tx_ring->stats.bytes; 6803 packets += tx_ring->stats.packets; 6804 } 6805 for (i = 0; i < adapter->num_xdp_queues; i++) { 6806 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6807 6808 restart_queue += xdp_ring->tx_stats.restart_queue; 6809 tx_busy += xdp_ring->tx_stats.tx_busy; 6810 bytes += xdp_ring->stats.bytes; 6811 packets += xdp_ring->stats.packets; 6812 } 6813 adapter->restart_queue = restart_queue; 6814 adapter->tx_busy = tx_busy; 6815 netdev->stats.tx_bytes = bytes; 6816 netdev->stats.tx_packets = packets; 6817 6818 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6819 6820 /* 8 register reads */ 6821 for (i = 0; i < 8; i++) { 6822 /* for packet buffers not used, the register should read 0 */ 6823 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6824 missed_rx += mpc; 6825 hwstats->mpc[i] += mpc; 6826 total_mpc += hwstats->mpc[i]; 6827 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6828 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6829 switch (hw->mac.type) { 6830 case ixgbe_mac_82598EB: 6831 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6832 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6833 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6834 hwstats->pxonrxc[i] += 6835 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6836 break; 6837 case ixgbe_mac_82599EB: 6838 case ixgbe_mac_X540: 6839 case ixgbe_mac_X550: 6840 case ixgbe_mac_X550EM_x: 6841 case ixgbe_mac_x550em_a: 6842 hwstats->pxonrxc[i] += 6843 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6844 break; 6845 default: 6846 break; 6847 } 6848 } 6849 6850 /*16 register reads */ 6851 for (i = 0; i < 16; i++) { 6852 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6853 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6854 if ((hw->mac.type == ixgbe_mac_82599EB) || 6855 (hw->mac.type == ixgbe_mac_X540) || 6856 (hw->mac.type == ixgbe_mac_X550) || 6857 (hw->mac.type == ixgbe_mac_X550EM_x) || 6858 (hw->mac.type == ixgbe_mac_x550em_a)) { 6859 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6860 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6861 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6862 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6863 } 6864 } 6865 6866 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6867 /* work around hardware counting issue */ 6868 hwstats->gprc -= missed_rx; 6869 6870 ixgbe_update_xoff_received(adapter); 6871 6872 /* 82598 hardware only has a 32 bit counter in the high register */ 6873 switch (hw->mac.type) { 6874 case ixgbe_mac_82598EB: 6875 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6876 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6877 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6878 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6879 break; 6880 case ixgbe_mac_X540: 6881 case ixgbe_mac_X550: 6882 case ixgbe_mac_X550EM_x: 6883 case ixgbe_mac_x550em_a: 6884 /* OS2BMC stats are X540 and later */ 6885 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6886 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6887 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6888 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6889 case ixgbe_mac_82599EB: 6890 for (i = 0; i < 16; i++) 6891 adapter->hw_rx_no_dma_resources += 6892 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6893 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6894 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6895 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6896 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6897 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6898 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6899 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6900 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6901 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6902 #ifdef IXGBE_FCOE 6903 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6904 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6905 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6906 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6907 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6908 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6909 /* Add up per cpu counters for total ddp aloc fail */ 6910 if (adapter->fcoe.ddp_pool) { 6911 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6912 struct ixgbe_fcoe_ddp_pool *ddp_pool; 6913 unsigned int cpu; 6914 u64 noddp = 0, noddp_ext_buff = 0; 6915 for_each_possible_cpu(cpu) { 6916 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 6917 noddp += ddp_pool->noddp; 6918 noddp_ext_buff += ddp_pool->noddp_ext_buff; 6919 } 6920 hwstats->fcoe_noddp = noddp; 6921 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 6922 } 6923 #endif /* IXGBE_FCOE */ 6924 break; 6925 default: 6926 break; 6927 } 6928 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 6929 hwstats->bprc += bprc; 6930 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 6931 if (hw->mac.type == ixgbe_mac_82598EB) 6932 hwstats->mprc -= bprc; 6933 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 6934 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 6935 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 6936 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 6937 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 6938 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 6939 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 6940 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 6941 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 6942 hwstats->lxontxc += lxon; 6943 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 6944 hwstats->lxofftxc += lxoff; 6945 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 6946 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 6947 /* 6948 * 82598 errata - tx of flow control packets is included in tx counters 6949 */ 6950 xon_off_tot = lxon + lxoff; 6951 hwstats->gptc -= xon_off_tot; 6952 hwstats->mptc -= xon_off_tot; 6953 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 6954 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 6955 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 6956 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 6957 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 6958 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 6959 hwstats->ptc64 -= xon_off_tot; 6960 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 6961 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 6962 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 6963 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 6964 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 6965 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 6966 6967 /* Fill out the OS statistics structure */ 6968 netdev->stats.multicast = hwstats->mprc; 6969 6970 /* Rx Errors */ 6971 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 6972 netdev->stats.rx_dropped = 0; 6973 netdev->stats.rx_length_errors = hwstats->rlec; 6974 netdev->stats.rx_crc_errors = hwstats->crcerrs; 6975 netdev->stats.rx_missed_errors = total_mpc; 6976 } 6977 6978 /** 6979 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 6980 * @adapter: pointer to the device adapter structure 6981 **/ 6982 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 6983 { 6984 struct ixgbe_hw *hw = &adapter->hw; 6985 int i; 6986 6987 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 6988 return; 6989 6990 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6991 6992 /* if interface is down do nothing */ 6993 if (test_bit(__IXGBE_DOWN, &adapter->state)) 6994 return; 6995 6996 /* do nothing if we are not using signature filters */ 6997 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 6998 return; 6999 7000 adapter->fdir_overflow++; 7001 7002 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7003 for (i = 0; i < adapter->num_tx_queues; i++) 7004 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7005 &(adapter->tx_ring[i]->state)); 7006 for (i = 0; i < adapter->num_xdp_queues; i++) 7007 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7008 &adapter->xdp_ring[i]->state); 7009 /* re-enable flow director interrupts */ 7010 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7011 } else { 7012 e_err(probe, "failed to finish FDIR re-initialization, " 7013 "ignored adding FDIR ATR filters\n"); 7014 } 7015 } 7016 7017 /** 7018 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7019 * @adapter: pointer to the device adapter structure 7020 * 7021 * This function serves two purposes. First it strobes the interrupt lines 7022 * in order to make certain interrupts are occurring. Secondly it sets the 7023 * bits needed to check for TX hangs. As a result we should immediately 7024 * determine if a hang has occurred. 7025 */ 7026 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7027 { 7028 struct ixgbe_hw *hw = &adapter->hw; 7029 u64 eics = 0; 7030 int i; 7031 7032 /* If we're down, removing or resetting, just bail */ 7033 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7034 test_bit(__IXGBE_REMOVING, &adapter->state) || 7035 test_bit(__IXGBE_RESETTING, &adapter->state)) 7036 return; 7037 7038 /* Force detection of hung controller */ 7039 if (netif_carrier_ok(adapter->netdev)) { 7040 for (i = 0; i < adapter->num_tx_queues; i++) 7041 set_check_for_tx_hang(adapter->tx_ring[i]); 7042 for (i = 0; i < adapter->num_xdp_queues; i++) 7043 set_check_for_tx_hang(adapter->xdp_ring[i]); 7044 } 7045 7046 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7047 /* 7048 * for legacy and MSI interrupts don't set any bits 7049 * that are enabled for EIAM, because this operation 7050 * would set *both* EIMS and EICS for any bit in EIAM 7051 */ 7052 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7053 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7054 } else { 7055 /* get one bit for every active tx/rx interrupt vector */ 7056 for (i = 0; i < adapter->num_q_vectors; i++) { 7057 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7058 if (qv->rx.ring || qv->tx.ring) 7059 eics |= BIT_ULL(i); 7060 } 7061 } 7062 7063 /* Cause software interrupt to ensure rings are cleaned */ 7064 ixgbe_irq_rearm_queues(adapter, eics); 7065 } 7066 7067 /** 7068 * ixgbe_watchdog_update_link - update the link status 7069 * @adapter: pointer to the device adapter structure 7070 * @link_speed: pointer to a u32 to store the link_speed 7071 **/ 7072 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7073 { 7074 struct ixgbe_hw *hw = &adapter->hw; 7075 u32 link_speed = adapter->link_speed; 7076 bool link_up = adapter->link_up; 7077 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7078 7079 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7080 return; 7081 7082 if (hw->mac.ops.check_link) { 7083 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7084 } else { 7085 /* always assume link is up, if no check link function */ 7086 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7087 link_up = true; 7088 } 7089 7090 if (adapter->ixgbe_ieee_pfc) 7091 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7092 7093 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7094 hw->mac.ops.fc_enable(hw); 7095 ixgbe_set_rx_drop_en(adapter); 7096 } 7097 7098 if (link_up || 7099 time_after(jiffies, (adapter->link_check_timeout + 7100 IXGBE_TRY_LINK_TIMEOUT))) { 7101 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7102 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7103 IXGBE_WRITE_FLUSH(hw); 7104 } 7105 7106 adapter->link_up = link_up; 7107 adapter->link_speed = link_speed; 7108 } 7109 7110 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7111 { 7112 #ifdef CONFIG_IXGBE_DCB 7113 struct net_device *netdev = adapter->netdev; 7114 struct dcb_app app = { 7115 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7116 .protocol = 0, 7117 }; 7118 u8 up = 0; 7119 7120 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7121 up = dcb_ieee_getapp_mask(netdev, &app); 7122 7123 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7124 #endif 7125 } 7126 7127 static int ixgbe_enable_macvlan(struct net_device *upper, void *data) 7128 { 7129 if (netif_is_macvlan(upper)) { 7130 struct macvlan_dev *vlan = netdev_priv(upper); 7131 7132 if (vlan->fwd_priv) 7133 netif_tx_wake_all_queues(upper); 7134 } 7135 7136 return 0; 7137 } 7138 7139 /** 7140 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7141 * print link up message 7142 * @adapter: pointer to the device adapter structure 7143 **/ 7144 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7145 { 7146 struct net_device *netdev = adapter->netdev; 7147 struct ixgbe_hw *hw = &adapter->hw; 7148 u32 link_speed = adapter->link_speed; 7149 const char *speed_str; 7150 bool flow_rx, flow_tx; 7151 7152 /* only continue if link was previously down */ 7153 if (netif_carrier_ok(netdev)) 7154 return; 7155 7156 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7157 7158 switch (hw->mac.type) { 7159 case ixgbe_mac_82598EB: { 7160 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7161 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7162 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7163 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7164 } 7165 break; 7166 case ixgbe_mac_X540: 7167 case ixgbe_mac_X550: 7168 case ixgbe_mac_X550EM_x: 7169 case ixgbe_mac_x550em_a: 7170 case ixgbe_mac_82599EB: { 7171 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7172 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7173 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7174 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7175 } 7176 break; 7177 default: 7178 flow_tx = false; 7179 flow_rx = false; 7180 break; 7181 } 7182 7183 adapter->last_rx_ptp_check = jiffies; 7184 7185 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7186 ixgbe_ptp_start_cyclecounter(adapter); 7187 7188 switch (link_speed) { 7189 case IXGBE_LINK_SPEED_10GB_FULL: 7190 speed_str = "10 Gbps"; 7191 break; 7192 case IXGBE_LINK_SPEED_2_5GB_FULL: 7193 speed_str = "2.5 Gbps"; 7194 break; 7195 case IXGBE_LINK_SPEED_1GB_FULL: 7196 speed_str = "1 Gbps"; 7197 break; 7198 case IXGBE_LINK_SPEED_100_FULL: 7199 speed_str = "100 Mbps"; 7200 break; 7201 case IXGBE_LINK_SPEED_10_FULL: 7202 speed_str = "10 Mbps"; 7203 break; 7204 default: 7205 speed_str = "unknown speed"; 7206 break; 7207 } 7208 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7209 ((flow_rx && flow_tx) ? "RX/TX" : 7210 (flow_rx ? "RX" : 7211 (flow_tx ? "TX" : "None")))); 7212 7213 netif_carrier_on(netdev); 7214 ixgbe_check_vf_rate_limit(adapter); 7215 7216 /* enable transmits */ 7217 netif_tx_wake_all_queues(adapter->netdev); 7218 7219 /* enable any upper devices */ 7220 rtnl_lock(); 7221 netdev_walk_all_upper_dev_rcu(adapter->netdev, 7222 ixgbe_enable_macvlan, NULL); 7223 rtnl_unlock(); 7224 7225 /* update the default user priority for VFs */ 7226 ixgbe_update_default_up(adapter); 7227 7228 /* ping all the active vfs to let them know link has changed */ 7229 ixgbe_ping_all_vfs(adapter); 7230 } 7231 7232 /** 7233 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7234 * print link down message 7235 * @adapter: pointer to the adapter structure 7236 **/ 7237 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7238 { 7239 struct net_device *netdev = adapter->netdev; 7240 struct ixgbe_hw *hw = &adapter->hw; 7241 7242 adapter->link_up = false; 7243 adapter->link_speed = 0; 7244 7245 /* only continue if link was up previously */ 7246 if (!netif_carrier_ok(netdev)) 7247 return; 7248 7249 /* poll for SFP+ cable when link is down */ 7250 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7251 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7252 7253 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7254 ixgbe_ptp_start_cyclecounter(adapter); 7255 7256 e_info(drv, "NIC Link is Down\n"); 7257 netif_carrier_off(netdev); 7258 7259 /* ping all the active vfs to let them know link has changed */ 7260 ixgbe_ping_all_vfs(adapter); 7261 } 7262 7263 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7264 { 7265 int i; 7266 7267 for (i = 0; i < adapter->num_tx_queues; i++) { 7268 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7269 7270 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7271 return true; 7272 } 7273 7274 for (i = 0; i < adapter->num_xdp_queues; i++) { 7275 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7276 7277 if (ring->next_to_use != ring->next_to_clean) 7278 return true; 7279 } 7280 7281 return false; 7282 } 7283 7284 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7285 { 7286 struct ixgbe_hw *hw = &adapter->hw; 7287 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7288 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7289 7290 int i, j; 7291 7292 if (!adapter->num_vfs) 7293 return false; 7294 7295 /* resetting the PF is only needed for MAC before X550 */ 7296 if (hw->mac.type >= ixgbe_mac_X550) 7297 return false; 7298 7299 for (i = 0; i < adapter->num_vfs; i++) { 7300 for (j = 0; j < q_per_pool; j++) { 7301 u32 h, t; 7302 7303 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7304 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7305 7306 if (h != t) 7307 return true; 7308 } 7309 } 7310 7311 return false; 7312 } 7313 7314 /** 7315 * ixgbe_watchdog_flush_tx - flush queues on link down 7316 * @adapter: pointer to the device adapter structure 7317 **/ 7318 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7319 { 7320 if (!netif_carrier_ok(adapter->netdev)) { 7321 if (ixgbe_ring_tx_pending(adapter) || 7322 ixgbe_vf_tx_pending(adapter)) { 7323 /* We've lost link, so the controller stops DMA, 7324 * but we've got queued Tx work that's never going 7325 * to get done, so reset controller to flush Tx. 7326 * (Do the reset outside of interrupt context). 7327 */ 7328 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7329 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7330 } 7331 } 7332 } 7333 7334 #ifdef CONFIG_PCI_IOV 7335 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, 7336 struct pci_dev *vfdev) 7337 { 7338 if (!pci_wait_for_pending_transaction(vfdev)) 7339 e_dev_warn("Issuing VFLR with pending transactions\n"); 7340 7341 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); 7342 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 7343 7344 msleep(100); 7345 } 7346 7347 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7348 { 7349 struct ixgbe_hw *hw = &adapter->hw; 7350 struct pci_dev *pdev = adapter->pdev; 7351 unsigned int vf; 7352 u32 gpc; 7353 7354 if (!(netif_carrier_ok(adapter->netdev))) 7355 return; 7356 7357 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7358 if (gpc) /* If incrementing then no need for the check below */ 7359 return; 7360 /* Check to see if a bad DMA write target from an errant or 7361 * malicious VF has caused a PCIe error. If so then we can 7362 * issue a VFLR to the offending VF(s) and then resume without 7363 * requesting a full slot reset. 7364 */ 7365 7366 if (!pdev) 7367 return; 7368 7369 /* check status reg for all VFs owned by this PF */ 7370 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7371 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7372 u16 status_reg; 7373 7374 if (!vfdev) 7375 continue; 7376 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7377 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7378 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7379 ixgbe_issue_vf_flr(adapter, vfdev); 7380 } 7381 } 7382 7383 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7384 { 7385 u32 ssvpc; 7386 7387 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7388 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7389 adapter->num_vfs == 0) 7390 return; 7391 7392 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7393 7394 /* 7395 * ssvpc register is cleared on read, if zero then no 7396 * spoofed packets in the last interval. 7397 */ 7398 if (!ssvpc) 7399 return; 7400 7401 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7402 } 7403 #else 7404 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7405 { 7406 } 7407 7408 static void 7409 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7410 { 7411 } 7412 #endif /* CONFIG_PCI_IOV */ 7413 7414 7415 /** 7416 * ixgbe_watchdog_subtask - check and bring link up 7417 * @adapter: pointer to the device adapter structure 7418 **/ 7419 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7420 { 7421 /* if interface is down, removing or resetting, do nothing */ 7422 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7423 test_bit(__IXGBE_REMOVING, &adapter->state) || 7424 test_bit(__IXGBE_RESETTING, &adapter->state)) 7425 return; 7426 7427 ixgbe_watchdog_update_link(adapter); 7428 7429 if (adapter->link_up) 7430 ixgbe_watchdog_link_is_up(adapter); 7431 else 7432 ixgbe_watchdog_link_is_down(adapter); 7433 7434 ixgbe_check_for_bad_vf(adapter); 7435 ixgbe_spoof_check(adapter); 7436 ixgbe_update_stats(adapter); 7437 7438 ixgbe_watchdog_flush_tx(adapter); 7439 } 7440 7441 /** 7442 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7443 * @adapter: the ixgbe adapter structure 7444 **/ 7445 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7446 { 7447 struct ixgbe_hw *hw = &adapter->hw; 7448 s32 err; 7449 7450 /* not searching for SFP so there is nothing to do here */ 7451 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7452 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7453 return; 7454 7455 if (adapter->sfp_poll_time && 7456 time_after(adapter->sfp_poll_time, jiffies)) 7457 return; /* If not yet time to poll for SFP */ 7458 7459 /* someone else is in init, wait until next service event */ 7460 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7461 return; 7462 7463 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7464 7465 err = hw->phy.ops.identify_sfp(hw); 7466 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7467 goto sfp_out; 7468 7469 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7470 /* If no cable is present, then we need to reset 7471 * the next time we find a good cable. */ 7472 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7473 } 7474 7475 /* exit on error */ 7476 if (err) 7477 goto sfp_out; 7478 7479 /* exit if reset not needed */ 7480 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7481 goto sfp_out; 7482 7483 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7484 7485 /* 7486 * A module may be identified correctly, but the EEPROM may not have 7487 * support for that module. setup_sfp() will fail in that case, so 7488 * we should not allow that module to load. 7489 */ 7490 if (hw->mac.type == ixgbe_mac_82598EB) 7491 err = hw->phy.ops.reset(hw); 7492 else 7493 err = hw->mac.ops.setup_sfp(hw); 7494 7495 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7496 goto sfp_out; 7497 7498 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7499 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7500 7501 sfp_out: 7502 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7503 7504 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7505 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7506 e_dev_err("failed to initialize because an unsupported " 7507 "SFP+ module type was detected.\n"); 7508 e_dev_err("Reload the driver after installing a " 7509 "supported module.\n"); 7510 unregister_netdev(adapter->netdev); 7511 } 7512 } 7513 7514 /** 7515 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7516 * @adapter: the ixgbe adapter structure 7517 **/ 7518 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7519 { 7520 struct ixgbe_hw *hw = &adapter->hw; 7521 u32 speed; 7522 bool autoneg = false; 7523 7524 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7525 return; 7526 7527 /* someone else is in init, wait until next service event */ 7528 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7529 return; 7530 7531 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7532 7533 speed = hw->phy.autoneg_advertised; 7534 if ((!speed) && (hw->mac.ops.get_link_capabilities)) { 7535 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); 7536 7537 /* setup the highest link when no autoneg */ 7538 if (!autoneg) { 7539 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 7540 speed = IXGBE_LINK_SPEED_10GB_FULL; 7541 } 7542 } 7543 7544 if (hw->mac.ops.setup_link) 7545 hw->mac.ops.setup_link(hw, speed, true); 7546 7547 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7548 adapter->link_check_timeout = jiffies; 7549 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7550 } 7551 7552 /** 7553 * ixgbe_service_timer - Timer Call-back 7554 * @data: pointer to adapter cast into an unsigned long 7555 **/ 7556 static void ixgbe_service_timer(unsigned long data) 7557 { 7558 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; 7559 unsigned long next_event_offset; 7560 7561 /* poll faster when waiting for link */ 7562 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7563 next_event_offset = HZ / 10; 7564 else 7565 next_event_offset = HZ * 2; 7566 7567 /* Reset the timer */ 7568 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7569 7570 ixgbe_service_event_schedule(adapter); 7571 } 7572 7573 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7574 { 7575 struct ixgbe_hw *hw = &adapter->hw; 7576 u32 status; 7577 7578 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7579 return; 7580 7581 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7582 7583 if (!hw->phy.ops.handle_lasi) 7584 return; 7585 7586 status = hw->phy.ops.handle_lasi(&adapter->hw); 7587 if (status != IXGBE_ERR_OVERTEMP) 7588 return; 7589 7590 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7591 } 7592 7593 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7594 { 7595 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7596 return; 7597 7598 /* If we're already down, removing or resetting, just bail */ 7599 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7600 test_bit(__IXGBE_REMOVING, &adapter->state) || 7601 test_bit(__IXGBE_RESETTING, &adapter->state)) 7602 return; 7603 7604 ixgbe_dump(adapter); 7605 netdev_err(adapter->netdev, "Reset adapter\n"); 7606 adapter->tx_timeout_count++; 7607 7608 rtnl_lock(); 7609 ixgbe_reinit_locked(adapter); 7610 rtnl_unlock(); 7611 } 7612 7613 /** 7614 * ixgbe_service_task - manages and runs subtasks 7615 * @work: pointer to work_struct containing our data 7616 **/ 7617 static void ixgbe_service_task(struct work_struct *work) 7618 { 7619 struct ixgbe_adapter *adapter = container_of(work, 7620 struct ixgbe_adapter, 7621 service_task); 7622 if (ixgbe_removed(adapter->hw.hw_addr)) { 7623 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7624 rtnl_lock(); 7625 ixgbe_down(adapter); 7626 rtnl_unlock(); 7627 } 7628 ixgbe_service_event_complete(adapter); 7629 return; 7630 } 7631 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7632 rtnl_lock(); 7633 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7634 udp_tunnel_get_rx_info(adapter->netdev); 7635 rtnl_unlock(); 7636 } 7637 ixgbe_reset_subtask(adapter); 7638 ixgbe_phy_interrupt_subtask(adapter); 7639 ixgbe_sfp_detection_subtask(adapter); 7640 ixgbe_sfp_link_config_subtask(adapter); 7641 ixgbe_check_overtemp_subtask(adapter); 7642 ixgbe_watchdog_subtask(adapter); 7643 ixgbe_fdir_reinit_subtask(adapter); 7644 ixgbe_check_hang_subtask(adapter); 7645 7646 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7647 ixgbe_ptp_overflow_check(adapter); 7648 ixgbe_ptp_rx_hang(adapter); 7649 } 7650 7651 ixgbe_service_event_complete(adapter); 7652 } 7653 7654 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7655 struct ixgbe_tx_buffer *first, 7656 u8 *hdr_len) 7657 { 7658 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7659 struct sk_buff *skb = first->skb; 7660 union { 7661 struct iphdr *v4; 7662 struct ipv6hdr *v6; 7663 unsigned char *hdr; 7664 } ip; 7665 union { 7666 struct tcphdr *tcp; 7667 unsigned char *hdr; 7668 } l4; 7669 u32 paylen, l4_offset; 7670 int err; 7671 7672 if (skb->ip_summed != CHECKSUM_PARTIAL) 7673 return 0; 7674 7675 if (!skb_is_gso(skb)) 7676 return 0; 7677 7678 err = skb_cow_head(skb, 0); 7679 if (err < 0) 7680 return err; 7681 7682 ip.hdr = skb_network_header(skb); 7683 l4.hdr = skb_checksum_start(skb); 7684 7685 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7686 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7687 7688 /* initialize outer IP header fields */ 7689 if (ip.v4->version == 4) { 7690 unsigned char *csum_start = skb_checksum_start(skb); 7691 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7692 7693 /* IP header will have to cancel out any data that 7694 * is not a part of the outer IP header 7695 */ 7696 ip.v4->check = csum_fold(csum_partial(trans_start, 7697 csum_start - trans_start, 7698 0)); 7699 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7700 7701 ip.v4->tot_len = 0; 7702 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7703 IXGBE_TX_FLAGS_CSUM | 7704 IXGBE_TX_FLAGS_IPV4; 7705 } else { 7706 ip.v6->payload_len = 0; 7707 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7708 IXGBE_TX_FLAGS_CSUM; 7709 } 7710 7711 /* determine offset of inner transport header */ 7712 l4_offset = l4.hdr - skb->data; 7713 7714 /* compute length of segmentation header */ 7715 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7716 7717 /* remove payload length from inner checksum */ 7718 paylen = skb->len - l4_offset; 7719 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7720 7721 /* update gso size and bytecount with header size */ 7722 first->gso_segs = skb_shinfo(skb)->gso_segs; 7723 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7724 7725 /* mss_l4len_id: use 0 as index for TSO */ 7726 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7727 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7728 7729 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7730 vlan_macip_lens = l4.hdr - ip.hdr; 7731 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7732 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7733 7734 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 7735 mss_l4len_idx); 7736 7737 return 1; 7738 } 7739 7740 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7741 { 7742 unsigned int offset = 0; 7743 7744 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7745 7746 return offset == skb_checksum_start_offset(skb); 7747 } 7748 7749 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7750 struct ixgbe_tx_buffer *first) 7751 { 7752 struct sk_buff *skb = first->skb; 7753 u32 vlan_macip_lens = 0; 7754 u32 type_tucmd = 0; 7755 7756 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7757 csum_failed: 7758 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7759 IXGBE_TX_FLAGS_CC))) 7760 return; 7761 goto no_csum; 7762 } 7763 7764 switch (skb->csum_offset) { 7765 case offsetof(struct tcphdr, check): 7766 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7767 /* fall through */ 7768 case offsetof(struct udphdr, check): 7769 break; 7770 case offsetof(struct sctphdr, checksum): 7771 /* validate that this is actually an SCTP request */ 7772 if (((first->protocol == htons(ETH_P_IP)) && 7773 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7774 ((first->protocol == htons(ETH_P_IPV6)) && 7775 ixgbe_ipv6_csum_is_sctp(skb))) { 7776 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7777 break; 7778 } 7779 /* fall through */ 7780 default: 7781 skb_checksum_help(skb); 7782 goto csum_failed; 7783 } 7784 7785 /* update TX checksum flag */ 7786 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7787 vlan_macip_lens = skb_checksum_start_offset(skb) - 7788 skb_network_offset(skb); 7789 no_csum: 7790 /* vlan_macip_lens: MACLEN, VLAN tag */ 7791 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7792 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7793 7794 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0); 7795 } 7796 7797 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7798 ((_flag <= _result) ? \ 7799 ((u32)(_input & _flag) * (_result / _flag)) : \ 7800 ((u32)(_input & _flag) / (_flag / _result))) 7801 7802 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7803 { 7804 /* set type for advanced descriptor with frame checksum insertion */ 7805 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7806 IXGBE_ADVTXD_DCMD_DEXT | 7807 IXGBE_ADVTXD_DCMD_IFCS; 7808 7809 /* set HW vlan bit if vlan is present */ 7810 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7811 IXGBE_ADVTXD_DCMD_VLE); 7812 7813 /* set segmentation enable bits for TSO/FSO */ 7814 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7815 IXGBE_ADVTXD_DCMD_TSE); 7816 7817 /* set timestamp bit if present */ 7818 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7819 IXGBE_ADVTXD_MAC_TSTAMP); 7820 7821 /* insert frame checksum */ 7822 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7823 7824 return cmd_type; 7825 } 7826 7827 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7828 u32 tx_flags, unsigned int paylen) 7829 { 7830 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7831 7832 /* enable L4 checksum for TSO and TX checksum offload */ 7833 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7834 IXGBE_TX_FLAGS_CSUM, 7835 IXGBE_ADVTXD_POPTS_TXSM); 7836 7837 /* enble IPv4 checksum for TSO */ 7838 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7839 IXGBE_TX_FLAGS_IPV4, 7840 IXGBE_ADVTXD_POPTS_IXSM); 7841 7842 /* 7843 * Check Context must be set if Tx switch is enabled, which it 7844 * always is for case where virtual functions are running 7845 */ 7846 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7847 IXGBE_TX_FLAGS_CC, 7848 IXGBE_ADVTXD_CC); 7849 7850 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7851 } 7852 7853 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7854 { 7855 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7856 7857 /* Herbert's original patch had: 7858 * smp_mb__after_netif_stop_queue(); 7859 * but since that doesn't exist yet, just open code it. 7860 */ 7861 smp_mb(); 7862 7863 /* We need to check again in a case another CPU has just 7864 * made room available. 7865 */ 7866 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7867 return -EBUSY; 7868 7869 /* A reprieve! - use start_queue because it doesn't call schedule */ 7870 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7871 ++tx_ring->tx_stats.restart_queue; 7872 return 0; 7873 } 7874 7875 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7876 { 7877 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7878 return 0; 7879 7880 return __ixgbe_maybe_stop_tx(tx_ring, size); 7881 } 7882 7883 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7884 IXGBE_TXD_CMD_RS) 7885 7886 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7887 struct ixgbe_tx_buffer *first, 7888 const u8 hdr_len) 7889 { 7890 struct sk_buff *skb = first->skb; 7891 struct ixgbe_tx_buffer *tx_buffer; 7892 union ixgbe_adv_tx_desc *tx_desc; 7893 struct skb_frag_struct *frag; 7894 dma_addr_t dma; 7895 unsigned int data_len, size; 7896 u32 tx_flags = first->tx_flags; 7897 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7898 u16 i = tx_ring->next_to_use; 7899 7900 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7901 7902 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7903 7904 size = skb_headlen(skb); 7905 data_len = skb->data_len; 7906 7907 #ifdef IXGBE_FCOE 7908 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7909 if (data_len < sizeof(struct fcoe_crc_eof)) { 7910 size -= sizeof(struct fcoe_crc_eof) - data_len; 7911 data_len = 0; 7912 } else { 7913 data_len -= sizeof(struct fcoe_crc_eof); 7914 } 7915 } 7916 7917 #endif 7918 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7919 7920 tx_buffer = first; 7921 7922 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7923 if (dma_mapping_error(tx_ring->dev, dma)) 7924 goto dma_error; 7925 7926 /* record length, and DMA address */ 7927 dma_unmap_len_set(tx_buffer, len, size); 7928 dma_unmap_addr_set(tx_buffer, dma, dma); 7929 7930 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7931 7932 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 7933 tx_desc->read.cmd_type_len = 7934 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 7935 7936 i++; 7937 tx_desc++; 7938 if (i == tx_ring->count) { 7939 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7940 i = 0; 7941 } 7942 tx_desc->read.olinfo_status = 0; 7943 7944 dma += IXGBE_MAX_DATA_PER_TXD; 7945 size -= IXGBE_MAX_DATA_PER_TXD; 7946 7947 tx_desc->read.buffer_addr = cpu_to_le64(dma); 7948 } 7949 7950 if (likely(!data_len)) 7951 break; 7952 7953 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 7954 7955 i++; 7956 tx_desc++; 7957 if (i == tx_ring->count) { 7958 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 7959 i = 0; 7960 } 7961 tx_desc->read.olinfo_status = 0; 7962 7963 #ifdef IXGBE_FCOE 7964 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 7965 #else 7966 size = skb_frag_size(frag); 7967 #endif 7968 data_len -= size; 7969 7970 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 7971 DMA_TO_DEVICE); 7972 7973 tx_buffer = &tx_ring->tx_buffer_info[i]; 7974 } 7975 7976 /* write last descriptor with RS and EOP bits */ 7977 cmd_type |= size | IXGBE_TXD_CMD; 7978 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 7979 7980 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 7981 7982 /* set the timestamp */ 7983 first->time_stamp = jiffies; 7984 7985 /* 7986 * Force memory writes to complete before letting h/w know there 7987 * are new descriptors to fetch. (Only applicable for weak-ordered 7988 * memory model archs, such as IA-64). 7989 * 7990 * We also need this memory barrier to make certain all of the 7991 * status bits have been updated before next_to_watch is written. 7992 */ 7993 wmb(); 7994 7995 /* set next_to_watch value indicating a packet is present */ 7996 first->next_to_watch = tx_desc; 7997 7998 i++; 7999 if (i == tx_ring->count) 8000 i = 0; 8001 8002 tx_ring->next_to_use = i; 8003 8004 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8005 8006 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8007 writel(i, tx_ring->tail); 8008 8009 /* we need this if more than one processor can write to our tail 8010 * at a time, it synchronizes IO on IA64/Altix systems 8011 */ 8012 mmiowb(); 8013 } 8014 8015 return; 8016 dma_error: 8017 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8018 tx_buffer = &tx_ring->tx_buffer_info[i]; 8019 8020 /* clear dma mappings for failed tx_buffer_info map */ 8021 while (tx_buffer != first) { 8022 if (dma_unmap_len(tx_buffer, len)) 8023 dma_unmap_page(tx_ring->dev, 8024 dma_unmap_addr(tx_buffer, dma), 8025 dma_unmap_len(tx_buffer, len), 8026 DMA_TO_DEVICE); 8027 dma_unmap_len_set(tx_buffer, len, 0); 8028 8029 if (i--) 8030 i += tx_ring->count; 8031 tx_buffer = &tx_ring->tx_buffer_info[i]; 8032 } 8033 8034 if (dma_unmap_len(tx_buffer, len)) 8035 dma_unmap_single(tx_ring->dev, 8036 dma_unmap_addr(tx_buffer, dma), 8037 dma_unmap_len(tx_buffer, len), 8038 DMA_TO_DEVICE); 8039 dma_unmap_len_set(tx_buffer, len, 0); 8040 8041 dev_kfree_skb_any(first->skb); 8042 first->skb = NULL; 8043 8044 tx_ring->next_to_use = i; 8045 } 8046 8047 static void ixgbe_atr(struct ixgbe_ring *ring, 8048 struct ixgbe_tx_buffer *first) 8049 { 8050 struct ixgbe_q_vector *q_vector = ring->q_vector; 8051 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8052 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8053 union { 8054 unsigned char *network; 8055 struct iphdr *ipv4; 8056 struct ipv6hdr *ipv6; 8057 } hdr; 8058 struct tcphdr *th; 8059 unsigned int hlen; 8060 struct sk_buff *skb; 8061 __be16 vlan_id; 8062 int l4_proto; 8063 8064 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8065 if (!q_vector) 8066 return; 8067 8068 /* do nothing if sampling is disabled */ 8069 if (!ring->atr_sample_rate) 8070 return; 8071 8072 ring->atr_count++; 8073 8074 /* currently only IPv4/IPv6 with TCP is supported */ 8075 if ((first->protocol != htons(ETH_P_IP)) && 8076 (first->protocol != htons(ETH_P_IPV6))) 8077 return; 8078 8079 /* snag network header to get L4 type and address */ 8080 skb = first->skb; 8081 hdr.network = skb_network_header(skb); 8082 if (unlikely(hdr.network <= skb->data)) 8083 return; 8084 if (skb->encapsulation && 8085 first->protocol == htons(ETH_P_IP) && 8086 hdr.ipv4->protocol == IPPROTO_UDP) { 8087 struct ixgbe_adapter *adapter = q_vector->adapter; 8088 8089 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8090 VXLAN_HEADROOM)) 8091 return; 8092 8093 /* verify the port is recognized as VXLAN */ 8094 if (adapter->vxlan_port && 8095 udp_hdr(skb)->dest == adapter->vxlan_port) 8096 hdr.network = skb_inner_network_header(skb); 8097 8098 if (adapter->geneve_port && 8099 udp_hdr(skb)->dest == adapter->geneve_port) 8100 hdr.network = skb_inner_network_header(skb); 8101 } 8102 8103 /* Make sure we have at least [minimum IPv4 header + TCP] 8104 * or [IPv6 header] bytes 8105 */ 8106 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8107 return; 8108 8109 /* Currently only IPv4/IPv6 with TCP is supported */ 8110 switch (hdr.ipv4->version) { 8111 case IPVERSION: 8112 /* access ihl as u8 to avoid unaligned access on ia64 */ 8113 hlen = (hdr.network[0] & 0x0F) << 2; 8114 l4_proto = hdr.ipv4->protocol; 8115 break; 8116 case 6: 8117 hlen = hdr.network - skb->data; 8118 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8119 hlen -= hdr.network - skb->data; 8120 break; 8121 default: 8122 return; 8123 } 8124 8125 if (l4_proto != IPPROTO_TCP) 8126 return; 8127 8128 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8129 hlen + sizeof(struct tcphdr))) 8130 return; 8131 8132 th = (struct tcphdr *)(hdr.network + hlen); 8133 8134 /* skip this packet since the socket is closing */ 8135 if (th->fin) 8136 return; 8137 8138 /* sample on all syn packets or once every atr sample count */ 8139 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8140 return; 8141 8142 /* reset sample count */ 8143 ring->atr_count = 0; 8144 8145 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8146 8147 /* 8148 * src and dst are inverted, think how the receiver sees them 8149 * 8150 * The input is broken into two sections, a non-compressed section 8151 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8152 * is XORed together and stored in the compressed dword. 8153 */ 8154 input.formatted.vlan_id = vlan_id; 8155 8156 /* 8157 * since src port and flex bytes occupy the same word XOR them together 8158 * and write the value to source port portion of compressed dword 8159 */ 8160 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8161 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8162 else 8163 common.port.src ^= th->dest ^ first->protocol; 8164 common.port.dst ^= th->source; 8165 8166 switch (hdr.ipv4->version) { 8167 case IPVERSION: 8168 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8169 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8170 break; 8171 case 6: 8172 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8173 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8174 hdr.ipv6->saddr.s6_addr32[1] ^ 8175 hdr.ipv6->saddr.s6_addr32[2] ^ 8176 hdr.ipv6->saddr.s6_addr32[3] ^ 8177 hdr.ipv6->daddr.s6_addr32[0] ^ 8178 hdr.ipv6->daddr.s6_addr32[1] ^ 8179 hdr.ipv6->daddr.s6_addr32[2] ^ 8180 hdr.ipv6->daddr.s6_addr32[3]; 8181 break; 8182 default: 8183 break; 8184 } 8185 8186 if (hdr.network != skb_network_header(skb)) 8187 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8188 8189 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8190 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8191 input, common, ring->queue_index); 8192 } 8193 8194 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8195 void *accel_priv, select_queue_fallback_t fallback) 8196 { 8197 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8198 #ifdef IXGBE_FCOE 8199 struct ixgbe_adapter *adapter; 8200 struct ixgbe_ring_feature *f; 8201 int txq; 8202 #endif 8203 8204 if (fwd_adapter) 8205 return skb->queue_mapping + fwd_adapter->tx_base_queue; 8206 8207 #ifdef IXGBE_FCOE 8208 8209 /* 8210 * only execute the code below if protocol is FCoE 8211 * or FIP and we have FCoE enabled on the adapter 8212 */ 8213 switch (vlan_get_protocol(skb)) { 8214 case htons(ETH_P_FCOE): 8215 case htons(ETH_P_FIP): 8216 adapter = netdev_priv(dev); 8217 8218 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8219 break; 8220 default: 8221 return fallback(dev, skb); 8222 } 8223 8224 f = &adapter->ring_feature[RING_F_FCOE]; 8225 8226 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8227 smp_processor_id(); 8228 8229 while (txq >= f->indices) 8230 txq -= f->indices; 8231 8232 return txq + f->offset; 8233 #else 8234 return fallback(dev, skb); 8235 #endif 8236 } 8237 8238 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8239 struct xdp_buff *xdp) 8240 { 8241 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8242 struct ixgbe_tx_buffer *tx_buffer; 8243 union ixgbe_adv_tx_desc *tx_desc; 8244 u32 len, cmd_type; 8245 dma_addr_t dma; 8246 u16 i; 8247 8248 len = xdp->data_end - xdp->data; 8249 8250 if (unlikely(!ixgbe_desc_unused(ring))) 8251 return IXGBE_XDP_CONSUMED; 8252 8253 dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE); 8254 if (dma_mapping_error(ring->dev, dma)) 8255 return IXGBE_XDP_CONSUMED; 8256 8257 /* record the location of the first descriptor for this packet */ 8258 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8259 tx_buffer->bytecount = len; 8260 tx_buffer->gso_segs = 1; 8261 tx_buffer->protocol = 0; 8262 8263 i = ring->next_to_use; 8264 tx_desc = IXGBE_TX_DESC(ring, i); 8265 8266 dma_unmap_len_set(tx_buffer, len, len); 8267 dma_unmap_addr_set(tx_buffer, dma, dma); 8268 tx_buffer->data = xdp->data; 8269 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8270 8271 /* put descriptor type bits */ 8272 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8273 IXGBE_ADVTXD_DCMD_DEXT | 8274 IXGBE_ADVTXD_DCMD_IFCS; 8275 cmd_type |= len | IXGBE_TXD_CMD; 8276 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8277 tx_desc->read.olinfo_status = 8278 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8279 8280 /* Avoid any potential race with xdp_xmit and cleanup */ 8281 smp_wmb(); 8282 8283 /* set next_to_watch value indicating a packet is present */ 8284 i++; 8285 if (i == ring->count) 8286 i = 0; 8287 8288 tx_buffer->next_to_watch = tx_desc; 8289 ring->next_to_use = i; 8290 8291 return IXGBE_XDP_TX; 8292 } 8293 8294 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8295 struct ixgbe_adapter *adapter, 8296 struct ixgbe_ring *tx_ring) 8297 { 8298 struct ixgbe_tx_buffer *first; 8299 int tso; 8300 u32 tx_flags = 0; 8301 unsigned short f; 8302 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8303 __be16 protocol = skb->protocol; 8304 u8 hdr_len = 0; 8305 8306 /* 8307 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8308 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8309 * + 2 desc gap to keep tail from touching head, 8310 * + 1 desc for context descriptor, 8311 * otherwise try next time 8312 */ 8313 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8314 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8315 8316 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8317 tx_ring->tx_stats.tx_busy++; 8318 return NETDEV_TX_BUSY; 8319 } 8320 8321 /* record the location of the first descriptor for this packet */ 8322 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8323 first->skb = skb; 8324 first->bytecount = skb->len; 8325 first->gso_segs = 1; 8326 8327 /* if we have a HW VLAN tag being added default to the HW one */ 8328 if (skb_vlan_tag_present(skb)) { 8329 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8330 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8331 /* else if it is a SW VLAN check the next protocol and store the tag */ 8332 } else if (protocol == htons(ETH_P_8021Q)) { 8333 struct vlan_hdr *vhdr, _vhdr; 8334 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8335 if (!vhdr) 8336 goto out_drop; 8337 8338 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8339 IXGBE_TX_FLAGS_VLAN_SHIFT; 8340 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8341 } 8342 protocol = vlan_get_protocol(skb); 8343 8344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8345 adapter->ptp_clock && 8346 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8347 &adapter->state)) { 8348 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8349 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8350 8351 /* schedule check for Tx timestamp */ 8352 adapter->ptp_tx_skb = skb_get(skb); 8353 adapter->ptp_tx_start = jiffies; 8354 schedule_work(&adapter->ptp_tx_work); 8355 } 8356 8357 skb_tx_timestamp(skb); 8358 8359 #ifdef CONFIG_PCI_IOV 8360 /* 8361 * Use the l2switch_enable flag - would be false if the DMA 8362 * Tx switch had been disabled. 8363 */ 8364 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8365 tx_flags |= IXGBE_TX_FLAGS_CC; 8366 8367 #endif 8368 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8369 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8370 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8371 (skb->priority != TC_PRIO_CONTROL))) { 8372 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8373 tx_flags |= (skb->priority & 0x7) << 8374 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8375 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8376 struct vlan_ethhdr *vhdr; 8377 8378 if (skb_cow_head(skb, 0)) 8379 goto out_drop; 8380 vhdr = (struct vlan_ethhdr *)skb->data; 8381 vhdr->h_vlan_TCI = htons(tx_flags >> 8382 IXGBE_TX_FLAGS_VLAN_SHIFT); 8383 } else { 8384 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8385 } 8386 } 8387 8388 /* record initial flags and protocol */ 8389 first->tx_flags = tx_flags; 8390 first->protocol = protocol; 8391 8392 #ifdef IXGBE_FCOE 8393 /* setup tx offload for FCoE */ 8394 if ((protocol == htons(ETH_P_FCOE)) && 8395 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8396 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8397 if (tso < 0) 8398 goto out_drop; 8399 8400 goto xmit_fcoe; 8401 } 8402 8403 #endif /* IXGBE_FCOE */ 8404 tso = ixgbe_tso(tx_ring, first, &hdr_len); 8405 if (tso < 0) 8406 goto out_drop; 8407 else if (!tso) 8408 ixgbe_tx_csum(tx_ring, first); 8409 8410 /* add the ATR filter if ATR is on */ 8411 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8412 ixgbe_atr(tx_ring, first); 8413 8414 #ifdef IXGBE_FCOE 8415 xmit_fcoe: 8416 #endif /* IXGBE_FCOE */ 8417 ixgbe_tx_map(tx_ring, first, hdr_len); 8418 8419 return NETDEV_TX_OK; 8420 8421 out_drop: 8422 dev_kfree_skb_any(first->skb); 8423 first->skb = NULL; 8424 8425 return NETDEV_TX_OK; 8426 } 8427 8428 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8429 struct net_device *netdev, 8430 struct ixgbe_ring *ring) 8431 { 8432 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8433 struct ixgbe_ring *tx_ring; 8434 8435 /* 8436 * The minimum packet size for olinfo paylen is 17 so pad the skb 8437 * in order to meet this minimum size requirement. 8438 */ 8439 if (skb_put_padto(skb, 17)) 8440 return NETDEV_TX_OK; 8441 8442 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8443 8444 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8445 } 8446 8447 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8448 struct net_device *netdev) 8449 { 8450 return __ixgbe_xmit_frame(skb, netdev, NULL); 8451 } 8452 8453 /** 8454 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8455 * @netdev: network interface device structure 8456 * @p: pointer to an address structure 8457 * 8458 * Returns 0 on success, negative on failure 8459 **/ 8460 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8461 { 8462 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8463 struct ixgbe_hw *hw = &adapter->hw; 8464 struct sockaddr *addr = p; 8465 8466 if (!is_valid_ether_addr(addr->sa_data)) 8467 return -EADDRNOTAVAIL; 8468 8469 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8470 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8471 8472 ixgbe_mac_set_default_filter(adapter); 8473 8474 return 0; 8475 } 8476 8477 static int 8478 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8479 { 8480 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8481 struct ixgbe_hw *hw = &adapter->hw; 8482 u16 value; 8483 int rc; 8484 8485 if (prtad != hw->phy.mdio.prtad) 8486 return -EINVAL; 8487 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8488 if (!rc) 8489 rc = value; 8490 return rc; 8491 } 8492 8493 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8494 u16 addr, u16 value) 8495 { 8496 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8497 struct ixgbe_hw *hw = &adapter->hw; 8498 8499 if (prtad != hw->phy.mdio.prtad) 8500 return -EINVAL; 8501 return hw->phy.ops.write_reg(hw, addr, devad, value); 8502 } 8503 8504 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8505 { 8506 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8507 8508 switch (cmd) { 8509 case SIOCSHWTSTAMP: 8510 return ixgbe_ptp_set_ts_config(adapter, req); 8511 case SIOCGHWTSTAMP: 8512 return ixgbe_ptp_get_ts_config(adapter, req); 8513 default: 8514 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8515 } 8516 } 8517 8518 /** 8519 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8520 * netdev->dev_addrs 8521 * @netdev: network interface device structure 8522 * 8523 * Returns non-zero on failure 8524 **/ 8525 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8526 { 8527 int err = 0; 8528 struct ixgbe_adapter *adapter = netdev_priv(dev); 8529 struct ixgbe_hw *hw = &adapter->hw; 8530 8531 if (is_valid_ether_addr(hw->mac.san_addr)) { 8532 rtnl_lock(); 8533 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8534 rtnl_unlock(); 8535 8536 /* update SAN MAC vmdq pool selection */ 8537 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8538 } 8539 return err; 8540 } 8541 8542 /** 8543 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8544 * netdev->dev_addrs 8545 * @netdev: network interface device structure 8546 * 8547 * Returns non-zero on failure 8548 **/ 8549 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8550 { 8551 int err = 0; 8552 struct ixgbe_adapter *adapter = netdev_priv(dev); 8553 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8554 8555 if (is_valid_ether_addr(mac->san_addr)) { 8556 rtnl_lock(); 8557 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8558 rtnl_unlock(); 8559 } 8560 return err; 8561 } 8562 8563 #ifdef CONFIG_NET_POLL_CONTROLLER 8564 /* 8565 * Polling 'interrupt' - used by things like netconsole to send skbs 8566 * without having to re-enable interrupts. It's not called while 8567 * the interrupt routine is executing. 8568 */ 8569 static void ixgbe_netpoll(struct net_device *netdev) 8570 { 8571 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8572 int i; 8573 8574 /* if interface is down do nothing */ 8575 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8576 return; 8577 8578 /* loop through and schedule all active queues */ 8579 for (i = 0; i < adapter->num_q_vectors; i++) 8580 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8581 } 8582 8583 #endif 8584 8585 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8586 struct ixgbe_ring *ring) 8587 { 8588 u64 bytes, packets; 8589 unsigned int start; 8590 8591 if (ring) { 8592 do { 8593 start = u64_stats_fetch_begin_irq(&ring->syncp); 8594 packets = ring->stats.packets; 8595 bytes = ring->stats.bytes; 8596 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8597 stats->tx_packets += packets; 8598 stats->tx_bytes += bytes; 8599 } 8600 } 8601 8602 static void ixgbe_get_stats64(struct net_device *netdev, 8603 struct rtnl_link_stats64 *stats) 8604 { 8605 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8606 int i; 8607 8608 rcu_read_lock(); 8609 for (i = 0; i < adapter->num_rx_queues; i++) { 8610 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); 8611 u64 bytes, packets; 8612 unsigned int start; 8613 8614 if (ring) { 8615 do { 8616 start = u64_stats_fetch_begin_irq(&ring->syncp); 8617 packets = ring->stats.packets; 8618 bytes = ring->stats.bytes; 8619 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8620 stats->rx_packets += packets; 8621 stats->rx_bytes += bytes; 8622 } 8623 } 8624 8625 for (i = 0; i < adapter->num_tx_queues; i++) { 8626 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); 8627 8628 ixgbe_get_ring_stats64(stats, ring); 8629 } 8630 for (i = 0; i < adapter->num_xdp_queues; i++) { 8631 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->xdp_ring[i]); 8632 8633 ixgbe_get_ring_stats64(stats, ring); 8634 } 8635 rcu_read_unlock(); 8636 8637 /* following stats updated by ixgbe_watchdog_task() */ 8638 stats->multicast = netdev->stats.multicast; 8639 stats->rx_errors = netdev->stats.rx_errors; 8640 stats->rx_length_errors = netdev->stats.rx_length_errors; 8641 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8642 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8643 } 8644 8645 #ifdef CONFIG_IXGBE_DCB 8646 /** 8647 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8648 * @adapter: pointer to ixgbe_adapter 8649 * @tc: number of traffic classes currently enabled 8650 * 8651 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8652 * 802.1Q priority maps to a packet buffer that exists. 8653 */ 8654 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8655 { 8656 struct ixgbe_hw *hw = &adapter->hw; 8657 u32 reg, rsave; 8658 int i; 8659 8660 /* 82598 have a static priority to TC mapping that can not 8661 * be changed so no validation is needed. 8662 */ 8663 if (hw->mac.type == ixgbe_mac_82598EB) 8664 return; 8665 8666 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8667 rsave = reg; 8668 8669 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8670 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8671 8672 /* If up2tc is out of bounds default to zero */ 8673 if (up2tc > tc) 8674 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8675 } 8676 8677 if (reg != rsave) 8678 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8679 8680 return; 8681 } 8682 8683 /** 8684 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8685 * @adapter: Pointer to adapter struct 8686 * 8687 * Populate the netdev user priority to tc map 8688 */ 8689 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8690 { 8691 struct net_device *dev = adapter->netdev; 8692 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8693 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8694 u8 prio; 8695 8696 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8697 u8 tc = 0; 8698 8699 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8700 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8701 else if (ets) 8702 tc = ets->prio_tc[prio]; 8703 8704 netdev_set_prio_tc_map(dev, prio, tc); 8705 } 8706 } 8707 8708 #endif /* CONFIG_IXGBE_DCB */ 8709 /** 8710 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8711 * 8712 * @netdev: net device to configure 8713 * @tc: number of traffic classes to enable 8714 */ 8715 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8716 { 8717 struct ixgbe_adapter *adapter = netdev_priv(dev); 8718 struct ixgbe_hw *hw = &adapter->hw; 8719 bool pools; 8720 8721 /* Hardware supports up to 8 traffic classes */ 8722 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8723 return -EINVAL; 8724 8725 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8726 return -EINVAL; 8727 8728 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 8729 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) 8730 return -EBUSY; 8731 8732 /* Hardware has to reinitialize queues and interrupts to 8733 * match packet buffer alignment. Unfortunately, the 8734 * hardware is not flexible enough to do this dynamically. 8735 */ 8736 if (netif_running(dev)) 8737 ixgbe_close(dev); 8738 else 8739 ixgbe_reset(adapter); 8740 8741 ixgbe_clear_interrupt_scheme(adapter); 8742 8743 #ifdef CONFIG_IXGBE_DCB 8744 if (tc) { 8745 netdev_set_num_tc(dev, tc); 8746 ixgbe_set_prio_tc_map(adapter); 8747 8748 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8749 8750 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8751 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8752 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8753 } 8754 } else { 8755 netdev_reset_tc(dev); 8756 8757 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8758 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8759 8760 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8761 8762 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8763 adapter->dcb_cfg.pfc_mode_enable = false; 8764 } 8765 8766 ixgbe_validate_rtr(adapter, tc); 8767 8768 #endif /* CONFIG_IXGBE_DCB */ 8769 ixgbe_init_interrupt_scheme(adapter); 8770 8771 if (netif_running(dev)) 8772 return ixgbe_open(dev); 8773 8774 return 0; 8775 } 8776 8777 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8778 struct tc_cls_u32_offload *cls) 8779 { 8780 u32 hdl = cls->knode.handle; 8781 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8782 u32 loc = cls->knode.handle & 0xfffff; 8783 int err = 0, i, j; 8784 struct ixgbe_jump_table *jump = NULL; 8785 8786 if (loc > IXGBE_MAX_HW_ENTRIES) 8787 return -EINVAL; 8788 8789 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8790 return -EINVAL; 8791 8792 /* Clear this filter in the link data it is associated with */ 8793 if (uhtid != 0x800) { 8794 jump = adapter->jump_tables[uhtid]; 8795 if (!jump) 8796 return -EINVAL; 8797 if (!test_bit(loc - 1, jump->child_loc_map)) 8798 return -EINVAL; 8799 clear_bit(loc - 1, jump->child_loc_map); 8800 } 8801 8802 /* Check if the filter being deleted is a link */ 8803 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8804 jump = adapter->jump_tables[i]; 8805 if (jump && jump->link_hdl == hdl) { 8806 /* Delete filters in the hardware in the child hash 8807 * table associated with this link 8808 */ 8809 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8810 if (!test_bit(j, jump->child_loc_map)) 8811 continue; 8812 spin_lock(&adapter->fdir_perfect_lock); 8813 err = ixgbe_update_ethtool_fdir_entry(adapter, 8814 NULL, 8815 j + 1); 8816 spin_unlock(&adapter->fdir_perfect_lock); 8817 clear_bit(j, jump->child_loc_map); 8818 } 8819 /* Remove resources for this link */ 8820 kfree(jump->input); 8821 kfree(jump->mask); 8822 kfree(jump); 8823 adapter->jump_tables[i] = NULL; 8824 return err; 8825 } 8826 } 8827 8828 spin_lock(&adapter->fdir_perfect_lock); 8829 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8830 spin_unlock(&adapter->fdir_perfect_lock); 8831 return err; 8832 } 8833 8834 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8835 __be16 protocol, 8836 struct tc_cls_u32_offload *cls) 8837 { 8838 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8839 8840 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8841 return -EINVAL; 8842 8843 /* This ixgbe devices do not support hash tables at the moment 8844 * so abort when given hash tables. 8845 */ 8846 if (cls->hnode.divisor > 0) 8847 return -EINVAL; 8848 8849 set_bit(uhtid - 1, &adapter->tables); 8850 return 0; 8851 } 8852 8853 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8854 struct tc_cls_u32_offload *cls) 8855 { 8856 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8857 8858 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8859 return -EINVAL; 8860 8861 clear_bit(uhtid - 1, &adapter->tables); 8862 return 0; 8863 } 8864 8865 #ifdef CONFIG_NET_CLS_ACT 8866 struct upper_walk_data { 8867 struct ixgbe_adapter *adapter; 8868 u64 action; 8869 int ifindex; 8870 u8 queue; 8871 }; 8872 8873 static int get_macvlan_queue(struct net_device *upper, void *_data) 8874 { 8875 if (netif_is_macvlan(upper)) { 8876 struct macvlan_dev *dfwd = netdev_priv(upper); 8877 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 8878 struct upper_walk_data *data = _data; 8879 struct ixgbe_adapter *adapter = data->adapter; 8880 int ifindex = data->ifindex; 8881 8882 if (vadapter && vadapter->netdev->ifindex == ifindex) { 8883 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 8884 data->action = data->queue; 8885 return 1; 8886 } 8887 } 8888 8889 return 0; 8890 } 8891 8892 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 8893 u8 *queue, u64 *action) 8894 { 8895 unsigned int num_vfs = adapter->num_vfs, vf; 8896 struct upper_walk_data data; 8897 struct net_device *upper; 8898 8899 /* redirect to a SRIOV VF */ 8900 for (vf = 0; vf < num_vfs; ++vf) { 8901 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 8902 if (upper->ifindex == ifindex) { 8903 if (adapter->num_rx_pools > 1) 8904 *queue = vf * 2; 8905 else 8906 *queue = vf * adapter->num_rx_queues_per_pool; 8907 8908 *action = vf + 1; 8909 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 8910 return 0; 8911 } 8912 } 8913 8914 /* redirect to a offloaded macvlan netdev */ 8915 data.adapter = adapter; 8916 data.ifindex = ifindex; 8917 data.action = 0; 8918 data.queue = 0; 8919 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 8920 get_macvlan_queue, &data)) { 8921 *action = data.action; 8922 *queue = data.queue; 8923 8924 return 0; 8925 } 8926 8927 return -EINVAL; 8928 } 8929 8930 static int parse_tc_actions(struct ixgbe_adapter *adapter, 8931 struct tcf_exts *exts, u64 *action, u8 *queue) 8932 { 8933 const struct tc_action *a; 8934 LIST_HEAD(actions); 8935 int err; 8936 8937 if (tc_no_actions(exts)) 8938 return -EINVAL; 8939 8940 tcf_exts_to_list(exts, &actions); 8941 list_for_each_entry(a, &actions, list) { 8942 8943 /* Drop action */ 8944 if (is_tcf_gact_shot(a)) { 8945 *action = IXGBE_FDIR_DROP_QUEUE; 8946 *queue = IXGBE_FDIR_DROP_QUEUE; 8947 return 0; 8948 } 8949 8950 /* Redirect to a VF or a offloaded macvlan */ 8951 if (is_tcf_mirred_egress_redirect(a)) { 8952 int ifindex = tcf_mirred_ifindex(a); 8953 8954 err = handle_redirect_action(adapter, ifindex, queue, 8955 action); 8956 if (err == 0) 8957 return err; 8958 } 8959 } 8960 8961 return -EINVAL; 8962 } 8963 #else 8964 static int parse_tc_actions(struct ixgbe_adapter *adapter, 8965 struct tcf_exts *exts, u64 *action, u8 *queue) 8966 { 8967 return -EINVAL; 8968 } 8969 #endif /* CONFIG_NET_CLS_ACT */ 8970 8971 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 8972 union ixgbe_atr_input *mask, 8973 struct tc_cls_u32_offload *cls, 8974 struct ixgbe_mat_field *field_ptr, 8975 struct ixgbe_nexthdr *nexthdr) 8976 { 8977 int i, j, off; 8978 __be32 val, m; 8979 bool found_entry = false, found_jump_field = false; 8980 8981 for (i = 0; i < cls->knode.sel->nkeys; i++) { 8982 off = cls->knode.sel->keys[i].off; 8983 val = cls->knode.sel->keys[i].val; 8984 m = cls->knode.sel->keys[i].mask; 8985 8986 for (j = 0; field_ptr[j].val; j++) { 8987 if (field_ptr[j].off == off) { 8988 field_ptr[j].val(input, mask, val, m); 8989 input->filter.formatted.flow_type |= 8990 field_ptr[j].type; 8991 found_entry = true; 8992 break; 8993 } 8994 } 8995 if (nexthdr) { 8996 if (nexthdr->off == cls->knode.sel->keys[i].off && 8997 nexthdr->val == cls->knode.sel->keys[i].val && 8998 nexthdr->mask == cls->knode.sel->keys[i].mask) 8999 found_jump_field = true; 9000 else 9001 continue; 9002 } 9003 } 9004 9005 if (nexthdr && !found_jump_field) 9006 return -EINVAL; 9007 9008 if (!found_entry) 9009 return 0; 9010 9011 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9012 IXGBE_ATR_L4TYPE_MASK; 9013 9014 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9015 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9016 9017 return 0; 9018 } 9019 9020 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9021 __be16 protocol, 9022 struct tc_cls_u32_offload *cls) 9023 { 9024 u32 loc = cls->knode.handle & 0xfffff; 9025 struct ixgbe_hw *hw = &adapter->hw; 9026 struct ixgbe_mat_field *field_ptr; 9027 struct ixgbe_fdir_filter *input = NULL; 9028 union ixgbe_atr_input *mask = NULL; 9029 struct ixgbe_jump_table *jump = NULL; 9030 int i, err = -EINVAL; 9031 u8 queue; 9032 u32 uhtid, link_uhtid; 9033 9034 uhtid = TC_U32_USERHTID(cls->knode.handle); 9035 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9036 9037 /* At the moment cls_u32 jumps to network layer and skips past 9038 * L2 headers. The canonical method to match L2 frames is to use 9039 * negative values. However this is error prone at best but really 9040 * just broken because there is no way to "know" what sort of hdr 9041 * is in front of the network layer. Fix cls_u32 to support L2 9042 * headers when needed. 9043 */ 9044 if (protocol != htons(ETH_P_IP)) 9045 return err; 9046 9047 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9048 e_err(drv, "Location out of range\n"); 9049 return err; 9050 } 9051 9052 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9053 * links and also the fields used to advance the parser across each 9054 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9055 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9056 * To add support for new nodes update ixgbe_model.h parse structures 9057 * this function _should_ be generic try not to hardcode values here. 9058 */ 9059 if (uhtid == 0x800) { 9060 field_ptr = (adapter->jump_tables[0])->mat; 9061 } else { 9062 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9063 return err; 9064 if (!adapter->jump_tables[uhtid]) 9065 return err; 9066 field_ptr = (adapter->jump_tables[uhtid])->mat; 9067 } 9068 9069 if (!field_ptr) 9070 return err; 9071 9072 /* At this point we know the field_ptr is valid and need to either 9073 * build cls_u32 link or attach filter. Because adding a link to 9074 * a handle that does not exist is invalid and the same for adding 9075 * rules to handles that don't exist. 9076 */ 9077 9078 if (link_uhtid) { 9079 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9080 9081 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9082 return err; 9083 9084 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9085 return err; 9086 9087 /* Multiple filters as links to the same hash table are not 9088 * supported. To add a new filter with the same next header 9089 * but different match/jump conditions, create a new hash table 9090 * and link to it. 9091 */ 9092 if (adapter->jump_tables[link_uhtid] && 9093 (adapter->jump_tables[link_uhtid])->link_hdl) { 9094 e_err(drv, "Link filter exists for link: %x\n", 9095 link_uhtid); 9096 return err; 9097 } 9098 9099 for (i = 0; nexthdr[i].jump; i++) { 9100 if (nexthdr[i].o != cls->knode.sel->offoff || 9101 nexthdr[i].s != cls->knode.sel->offshift || 9102 nexthdr[i].m != cls->knode.sel->offmask) 9103 return err; 9104 9105 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9106 if (!jump) 9107 return -ENOMEM; 9108 input = kzalloc(sizeof(*input), GFP_KERNEL); 9109 if (!input) { 9110 err = -ENOMEM; 9111 goto free_jump; 9112 } 9113 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9114 if (!mask) { 9115 err = -ENOMEM; 9116 goto free_input; 9117 } 9118 jump->input = input; 9119 jump->mask = mask; 9120 jump->link_hdl = cls->knode.handle; 9121 9122 err = ixgbe_clsu32_build_input(input, mask, cls, 9123 field_ptr, &nexthdr[i]); 9124 if (!err) { 9125 jump->mat = nexthdr[i].jump; 9126 adapter->jump_tables[link_uhtid] = jump; 9127 break; 9128 } 9129 } 9130 return 0; 9131 } 9132 9133 input = kzalloc(sizeof(*input), GFP_KERNEL); 9134 if (!input) 9135 return -ENOMEM; 9136 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9137 if (!mask) { 9138 err = -ENOMEM; 9139 goto free_input; 9140 } 9141 9142 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9143 if ((adapter->jump_tables[uhtid])->input) 9144 memcpy(input, (adapter->jump_tables[uhtid])->input, 9145 sizeof(*input)); 9146 if ((adapter->jump_tables[uhtid])->mask) 9147 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9148 sizeof(*mask)); 9149 9150 /* Lookup in all child hash tables if this location is already 9151 * filled with a filter 9152 */ 9153 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9154 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9155 9156 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9157 e_err(drv, "Filter exists in location: %x\n", 9158 loc); 9159 err = -EINVAL; 9160 goto err_out; 9161 } 9162 } 9163 } 9164 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9165 if (err) 9166 goto err_out; 9167 9168 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9169 &queue); 9170 if (err < 0) 9171 goto err_out; 9172 9173 input->sw_idx = loc; 9174 9175 spin_lock(&adapter->fdir_perfect_lock); 9176 9177 if (hlist_empty(&adapter->fdir_filter_list)) { 9178 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9179 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9180 if (err) 9181 goto err_out_w_lock; 9182 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9183 err = -EINVAL; 9184 goto err_out_w_lock; 9185 } 9186 9187 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9188 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9189 input->sw_idx, queue); 9190 if (!err) 9191 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9192 spin_unlock(&adapter->fdir_perfect_lock); 9193 9194 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9195 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9196 9197 kfree(mask); 9198 return err; 9199 err_out_w_lock: 9200 spin_unlock(&adapter->fdir_perfect_lock); 9201 err_out: 9202 kfree(mask); 9203 free_input: 9204 kfree(input); 9205 free_jump: 9206 kfree(jump); 9207 return err; 9208 } 9209 9210 static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto, 9211 struct tc_to_netdev *tc) 9212 { 9213 struct ixgbe_adapter *adapter = netdev_priv(dev); 9214 9215 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) && 9216 tc->type == TC_SETUP_CLSU32) { 9217 switch (tc->cls_u32->command) { 9218 case TC_CLSU32_NEW_KNODE: 9219 case TC_CLSU32_REPLACE_KNODE: 9220 return ixgbe_configure_clsu32(adapter, 9221 proto, tc->cls_u32); 9222 case TC_CLSU32_DELETE_KNODE: 9223 return ixgbe_delete_clsu32(adapter, tc->cls_u32); 9224 case TC_CLSU32_NEW_HNODE: 9225 case TC_CLSU32_REPLACE_HNODE: 9226 return ixgbe_configure_clsu32_add_hnode(adapter, proto, 9227 tc->cls_u32); 9228 case TC_CLSU32_DELETE_HNODE: 9229 return ixgbe_configure_clsu32_del_hnode(adapter, 9230 tc->cls_u32); 9231 default: 9232 return -EINVAL; 9233 } 9234 } 9235 9236 if (tc->type != TC_SETUP_MQPRIO) 9237 return -EINVAL; 9238 9239 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9240 9241 return ixgbe_setup_tc(dev, tc->mqprio->num_tc); 9242 } 9243 9244 #ifdef CONFIG_PCI_IOV 9245 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9246 { 9247 struct net_device *netdev = adapter->netdev; 9248 9249 rtnl_lock(); 9250 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); 9251 rtnl_unlock(); 9252 } 9253 9254 #endif 9255 void ixgbe_do_reset(struct net_device *netdev) 9256 { 9257 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9258 9259 if (netif_running(netdev)) 9260 ixgbe_reinit_locked(adapter); 9261 else 9262 ixgbe_reset(adapter); 9263 } 9264 9265 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9266 netdev_features_t features) 9267 { 9268 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9269 9270 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9271 if (!(features & NETIF_F_RXCSUM)) 9272 features &= ~NETIF_F_LRO; 9273 9274 /* Turn off LRO if not RSC capable */ 9275 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9276 features &= ~NETIF_F_LRO; 9277 9278 return features; 9279 } 9280 9281 static int ixgbe_set_features(struct net_device *netdev, 9282 netdev_features_t features) 9283 { 9284 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9285 netdev_features_t changed = netdev->features ^ features; 9286 bool need_reset = false; 9287 9288 /* Make sure RSC matches LRO, reset if change */ 9289 if (!(features & NETIF_F_LRO)) { 9290 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9291 need_reset = true; 9292 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9293 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9294 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9295 if (adapter->rx_itr_setting == 1 || 9296 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9297 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9298 need_reset = true; 9299 } else if ((changed ^ features) & NETIF_F_LRO) { 9300 e_info(probe, "rx-usecs set too low, " 9301 "disabling RSC\n"); 9302 } 9303 } 9304 9305 /* 9306 * Check if Flow Director n-tuple support or hw_tc support was 9307 * enabled or disabled. If the state changed, we need to reset. 9308 */ 9309 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9310 /* turn off ATR, enable perfect filters and reset */ 9311 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9312 need_reset = true; 9313 9314 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9315 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9316 } else { 9317 /* turn off perfect filters, enable ATR and reset */ 9318 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9319 need_reset = true; 9320 9321 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9322 9323 /* We cannot enable ATR if SR-IOV is enabled */ 9324 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9325 /* We cannot enable ATR if we have 2 or more tcs */ 9326 (netdev_get_num_tc(netdev) > 1) || 9327 /* We cannot enable ATR if RSS is disabled */ 9328 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9329 /* A sample rate of 0 indicates ATR disabled */ 9330 (!adapter->atr_sample_rate)) 9331 ; /* do nothing not supported */ 9332 else /* otherwise supported and set the flag */ 9333 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9334 } 9335 9336 if (changed & NETIF_F_RXALL) 9337 need_reset = true; 9338 9339 netdev->features = features; 9340 9341 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9342 if (features & NETIF_F_RXCSUM) { 9343 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9344 } else { 9345 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9346 9347 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9348 } 9349 } 9350 9351 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9352 if (features & NETIF_F_RXCSUM) { 9353 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9354 } else { 9355 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9356 9357 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9358 } 9359 } 9360 9361 if (need_reset) 9362 ixgbe_do_reset(netdev); 9363 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9364 NETIF_F_HW_VLAN_CTAG_FILTER)) 9365 ixgbe_set_rx_mode(netdev); 9366 9367 return 0; 9368 } 9369 9370 /** 9371 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9372 * @dev: The port's netdev 9373 * @ti: Tunnel endpoint information 9374 **/ 9375 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9376 struct udp_tunnel_info *ti) 9377 { 9378 struct ixgbe_adapter *adapter = netdev_priv(dev); 9379 struct ixgbe_hw *hw = &adapter->hw; 9380 __be16 port = ti->port; 9381 u32 port_shift = 0; 9382 u32 reg; 9383 9384 if (ti->sa_family != AF_INET) 9385 return; 9386 9387 switch (ti->type) { 9388 case UDP_TUNNEL_TYPE_VXLAN: 9389 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9390 return; 9391 9392 if (adapter->vxlan_port == port) 9393 return; 9394 9395 if (adapter->vxlan_port) { 9396 netdev_info(dev, 9397 "VXLAN port %d set, not adding port %d\n", 9398 ntohs(adapter->vxlan_port), 9399 ntohs(port)); 9400 return; 9401 } 9402 9403 adapter->vxlan_port = port; 9404 break; 9405 case UDP_TUNNEL_TYPE_GENEVE: 9406 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9407 return; 9408 9409 if (adapter->geneve_port == port) 9410 return; 9411 9412 if (adapter->geneve_port) { 9413 netdev_info(dev, 9414 "GENEVE port %d set, not adding port %d\n", 9415 ntohs(adapter->geneve_port), 9416 ntohs(port)); 9417 return; 9418 } 9419 9420 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9421 adapter->geneve_port = port; 9422 break; 9423 default: 9424 return; 9425 } 9426 9427 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9428 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9429 } 9430 9431 /** 9432 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9433 * @dev: The port's netdev 9434 * @ti: Tunnel endpoint information 9435 **/ 9436 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9437 struct udp_tunnel_info *ti) 9438 { 9439 struct ixgbe_adapter *adapter = netdev_priv(dev); 9440 u32 port_mask; 9441 9442 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9443 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9444 return; 9445 9446 if (ti->sa_family != AF_INET) 9447 return; 9448 9449 switch (ti->type) { 9450 case UDP_TUNNEL_TYPE_VXLAN: 9451 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9452 return; 9453 9454 if (adapter->vxlan_port != ti->port) { 9455 netdev_info(dev, "VXLAN port %d not found\n", 9456 ntohs(ti->port)); 9457 return; 9458 } 9459 9460 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9461 break; 9462 case UDP_TUNNEL_TYPE_GENEVE: 9463 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9464 return; 9465 9466 if (adapter->geneve_port != ti->port) { 9467 netdev_info(dev, "GENEVE port %d not found\n", 9468 ntohs(ti->port)); 9469 return; 9470 } 9471 9472 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9473 break; 9474 default: 9475 return; 9476 } 9477 9478 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9479 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9480 } 9481 9482 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9483 struct net_device *dev, 9484 const unsigned char *addr, u16 vid, 9485 u16 flags) 9486 { 9487 /* guarantee we can provide a unique filter for the unicast address */ 9488 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9489 struct ixgbe_adapter *adapter = netdev_priv(dev); 9490 u16 pool = VMDQ_P(0); 9491 9492 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9493 return -ENOMEM; 9494 } 9495 9496 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9497 } 9498 9499 /** 9500 * ixgbe_configure_bridge_mode - set various bridge modes 9501 * @adapter - the private structure 9502 * @mode - requested bridge mode 9503 * 9504 * Configure some settings require for various bridge modes. 9505 **/ 9506 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9507 __u16 mode) 9508 { 9509 struct ixgbe_hw *hw = &adapter->hw; 9510 unsigned int p, num_pools; 9511 u32 vmdctl; 9512 9513 switch (mode) { 9514 case BRIDGE_MODE_VEPA: 9515 /* disable Tx loopback, rely on switch hairpin mode */ 9516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9517 9518 /* must enable Rx switching replication to allow multicast 9519 * packet reception on all VFs, and to enable source address 9520 * pruning. 9521 */ 9522 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9523 vmdctl |= IXGBE_VT_CTL_REPLEN; 9524 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9525 9526 /* enable Rx source address pruning. Note, this requires 9527 * replication to be enabled or else it does nothing. 9528 */ 9529 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9530 for (p = 0; p < num_pools; p++) { 9531 if (hw->mac.ops.set_source_address_pruning) 9532 hw->mac.ops.set_source_address_pruning(hw, 9533 true, 9534 p); 9535 } 9536 break; 9537 case BRIDGE_MODE_VEB: 9538 /* enable Tx loopback for internal VF/PF communication */ 9539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9540 IXGBE_PFDTXGSWC_VT_LBEN); 9541 9542 /* disable Rx switching replication unless we have SR-IOV 9543 * virtual functions 9544 */ 9545 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9546 if (!adapter->num_vfs) 9547 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9548 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9549 9550 /* disable Rx source address pruning, since we don't expect to 9551 * be receiving external loopback of our transmitted frames. 9552 */ 9553 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9554 for (p = 0; p < num_pools; p++) { 9555 if (hw->mac.ops.set_source_address_pruning) 9556 hw->mac.ops.set_source_address_pruning(hw, 9557 false, 9558 p); 9559 } 9560 break; 9561 default: 9562 return -EINVAL; 9563 } 9564 9565 adapter->bridge_mode = mode; 9566 9567 e_info(drv, "enabling bridge mode: %s\n", 9568 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9569 9570 return 0; 9571 } 9572 9573 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9574 struct nlmsghdr *nlh, u16 flags) 9575 { 9576 struct ixgbe_adapter *adapter = netdev_priv(dev); 9577 struct nlattr *attr, *br_spec; 9578 int rem; 9579 9580 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9581 return -EOPNOTSUPP; 9582 9583 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9584 if (!br_spec) 9585 return -EINVAL; 9586 9587 nla_for_each_nested(attr, br_spec, rem) { 9588 int status; 9589 __u16 mode; 9590 9591 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9592 continue; 9593 9594 if (nla_len(attr) < sizeof(mode)) 9595 return -EINVAL; 9596 9597 mode = nla_get_u16(attr); 9598 status = ixgbe_configure_bridge_mode(adapter, mode); 9599 if (status) 9600 return status; 9601 9602 break; 9603 } 9604 9605 return 0; 9606 } 9607 9608 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9609 struct net_device *dev, 9610 u32 filter_mask, int nlflags) 9611 { 9612 struct ixgbe_adapter *adapter = netdev_priv(dev); 9613 9614 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9615 return 0; 9616 9617 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9618 adapter->bridge_mode, 0, 0, nlflags, 9619 filter_mask, NULL); 9620 } 9621 9622 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9623 { 9624 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 9625 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9626 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 9627 unsigned int limit; 9628 int pool, err; 9629 9630 /* Hardware has a limited number of available pools. Each VF, and the 9631 * PF require a pool. Check to ensure we don't attempt to use more 9632 * then the available number of pools. 9633 */ 9634 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9635 return ERR_PTR(-EINVAL); 9636 9637 #ifdef CONFIG_RPS 9638 if (vdev->num_rx_queues != vdev->num_tx_queues) { 9639 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", 9640 vdev->name); 9641 return ERR_PTR(-EINVAL); 9642 } 9643 #endif 9644 /* Check for hardware restriction on number of rx/tx queues */ 9645 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || 9646 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { 9647 netdev_info(pdev, 9648 "%s: Supports RX/TX Queue counts 1,2, and 4\n", 9649 pdev->name); 9650 return ERR_PTR(-EINVAL); 9651 } 9652 9653 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9654 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || 9655 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 9656 return ERR_PTR(-EBUSY); 9657 9658 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 9659 if (!fwd_adapter) 9660 return ERR_PTR(-ENOMEM); 9661 9662 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); 9663 adapter->num_rx_pools++; 9664 set_bit(pool, &adapter->fwd_bitmask); 9665 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9666 9667 /* Enable VMDq flag so device will be set in VM mode */ 9668 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 9669 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9670 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; 9671 9672 /* Force reinit of ring allocation with VMDQ enabled */ 9673 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9674 if (err) 9675 goto fwd_add_err; 9676 fwd_adapter->pool = pool; 9677 fwd_adapter->real_adapter = adapter; 9678 9679 if (netif_running(pdev)) { 9680 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 9681 if (err) 9682 goto fwd_add_err; 9683 netif_tx_start_all_queues(vdev); 9684 } 9685 9686 return fwd_adapter; 9687 fwd_add_err: 9688 /* unwind counter and free adapter struct */ 9689 netdev_info(pdev, 9690 "%s: dfwd hardware acceleration failed\n", vdev->name); 9691 clear_bit(pool, &adapter->fwd_bitmask); 9692 adapter->num_rx_pools--; 9693 kfree(fwd_adapter); 9694 return ERR_PTR(err); 9695 } 9696 9697 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9698 { 9699 struct ixgbe_fwd_adapter *fwd_adapter = priv; 9700 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; 9701 unsigned int limit; 9702 9703 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); 9704 adapter->num_rx_pools--; 9705 9706 limit = find_last_bit(&adapter->fwd_bitmask, 32); 9707 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9708 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); 9709 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); 9710 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", 9711 fwd_adapter->pool, adapter->num_rx_pools, 9712 fwd_adapter->rx_base_queue, 9713 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, 9714 adapter->fwd_bitmask); 9715 kfree(fwd_adapter); 9716 } 9717 9718 #define IXGBE_MAX_MAC_HDR_LEN 127 9719 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9720 9721 static netdev_features_t 9722 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9723 netdev_features_t features) 9724 { 9725 unsigned int network_hdr_len, mac_hdr_len; 9726 9727 /* Make certain the headers can be described by a context descriptor */ 9728 mac_hdr_len = skb_network_header(skb) - skb->data; 9729 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9730 return features & ~(NETIF_F_HW_CSUM | 9731 NETIF_F_SCTP_CRC | 9732 NETIF_F_HW_VLAN_CTAG_TX | 9733 NETIF_F_TSO | 9734 NETIF_F_TSO6); 9735 9736 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9737 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9738 return features & ~(NETIF_F_HW_CSUM | 9739 NETIF_F_SCTP_CRC | 9740 NETIF_F_TSO | 9741 NETIF_F_TSO6); 9742 9743 /* We can only support IPV4 TSO in tunnels if we can mangle the 9744 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9745 */ 9746 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 9747 features &= ~NETIF_F_TSO; 9748 9749 return features; 9750 } 9751 9752 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9753 { 9754 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9755 struct ixgbe_adapter *adapter = netdev_priv(dev); 9756 struct bpf_prog *old_prog; 9757 9758 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9759 return -EINVAL; 9760 9761 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9762 return -EINVAL; 9763 9764 /* verify ixgbe ring attributes are sufficient for XDP */ 9765 for (i = 0; i < adapter->num_rx_queues; i++) { 9766 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9767 9768 if (ring_is_rsc_enabled(ring)) 9769 return -EINVAL; 9770 9771 if (frame_size > ixgbe_rx_bufsz(ring)) 9772 return -EINVAL; 9773 } 9774 9775 if (nr_cpu_ids > MAX_XDP_QUEUES) 9776 return -ENOMEM; 9777 9778 old_prog = xchg(&adapter->xdp_prog, prog); 9779 9780 /* If transitioning XDP modes reconfigure rings */ 9781 if (!!prog != !!old_prog) { 9782 int err = ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 9783 9784 if (err) { 9785 rcu_assign_pointer(adapter->xdp_prog, old_prog); 9786 return -EINVAL; 9787 } 9788 } else { 9789 for (i = 0; i < adapter->num_rx_queues; i++) 9790 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); 9791 } 9792 9793 if (old_prog) 9794 bpf_prog_put(old_prog); 9795 9796 return 0; 9797 } 9798 9799 static int ixgbe_xdp(struct net_device *dev, struct netdev_xdp *xdp) 9800 { 9801 struct ixgbe_adapter *adapter = netdev_priv(dev); 9802 9803 switch (xdp->command) { 9804 case XDP_SETUP_PROG: 9805 return ixgbe_xdp_setup(dev, xdp->prog); 9806 case XDP_QUERY_PROG: 9807 xdp->prog_attached = !!(adapter->xdp_prog); 9808 return 0; 9809 default: 9810 return -EINVAL; 9811 } 9812 } 9813 9814 static const struct net_device_ops ixgbe_netdev_ops = { 9815 .ndo_open = ixgbe_open, 9816 .ndo_stop = ixgbe_close, 9817 .ndo_start_xmit = ixgbe_xmit_frame, 9818 .ndo_select_queue = ixgbe_select_queue, 9819 .ndo_set_rx_mode = ixgbe_set_rx_mode, 9820 .ndo_validate_addr = eth_validate_addr, 9821 .ndo_set_mac_address = ixgbe_set_mac, 9822 .ndo_change_mtu = ixgbe_change_mtu, 9823 .ndo_tx_timeout = ixgbe_tx_timeout, 9824 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 9825 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 9826 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 9827 .ndo_do_ioctl = ixgbe_ioctl, 9828 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 9829 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 9830 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 9831 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 9832 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 9833 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 9834 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 9835 .ndo_get_stats64 = ixgbe_get_stats64, 9836 .ndo_setup_tc = __ixgbe_setup_tc, 9837 #ifdef CONFIG_NET_POLL_CONTROLLER 9838 .ndo_poll_controller = ixgbe_netpoll, 9839 #endif 9840 #ifdef IXGBE_FCOE 9841 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 9842 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 9843 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 9844 .ndo_fcoe_enable = ixgbe_fcoe_enable, 9845 .ndo_fcoe_disable = ixgbe_fcoe_disable, 9846 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 9847 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 9848 #endif /* IXGBE_FCOE */ 9849 .ndo_set_features = ixgbe_set_features, 9850 .ndo_fix_features = ixgbe_fix_features, 9851 .ndo_fdb_add = ixgbe_ndo_fdb_add, 9852 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 9853 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 9854 .ndo_dfwd_add_station = ixgbe_fwd_add, 9855 .ndo_dfwd_del_station = ixgbe_fwd_del, 9856 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 9857 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 9858 .ndo_features_check = ixgbe_features_check, 9859 .ndo_xdp = ixgbe_xdp, 9860 }; 9861 9862 /** 9863 * ixgbe_enumerate_functions - Get the number of ports this device has 9864 * @adapter: adapter structure 9865 * 9866 * This function enumerates the phsyical functions co-located on a single slot, 9867 * in order to determine how many ports a device has. This is most useful in 9868 * determining the required GT/s of PCIe bandwidth necessary for optimal 9869 * performance. 9870 **/ 9871 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 9872 { 9873 struct pci_dev *entry, *pdev = adapter->pdev; 9874 int physfns = 0; 9875 9876 /* Some cards can not use the generic count PCIe functions method, 9877 * because they are behind a parent switch, so we hardcode these with 9878 * the correct number of functions. 9879 */ 9880 if (ixgbe_pcie_from_parent(&adapter->hw)) 9881 physfns = 4; 9882 9883 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 9884 /* don't count virtual functions */ 9885 if (entry->is_virtfn) 9886 continue; 9887 9888 /* When the devices on the bus don't all match our device ID, 9889 * we can't reliably determine the correct number of 9890 * functions. This can occur if a function has been direct 9891 * attached to a virtual machine using VT-d, for example. In 9892 * this case, simply return -1 to indicate this. 9893 */ 9894 if ((entry->vendor != pdev->vendor) || 9895 (entry->device != pdev->device)) 9896 return -1; 9897 9898 physfns++; 9899 } 9900 9901 return physfns; 9902 } 9903 9904 /** 9905 * ixgbe_wol_supported - Check whether device supports WoL 9906 * @adapter: the adapter private structure 9907 * @device_id: the device ID 9908 * @subdev_id: the subsystem device ID 9909 * 9910 * This function is used by probe and ethtool to determine 9911 * which devices have WoL support 9912 * 9913 **/ 9914 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 9915 u16 subdevice_id) 9916 { 9917 struct ixgbe_hw *hw = &adapter->hw; 9918 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 9919 9920 /* WOL not supported on 82598 */ 9921 if (hw->mac.type == ixgbe_mac_82598EB) 9922 return false; 9923 9924 /* check eeprom to see if WOL is enabled for X540 and newer */ 9925 if (hw->mac.type >= ixgbe_mac_X540) { 9926 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 9927 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 9928 (hw->bus.func == 0))) 9929 return true; 9930 } 9931 9932 /* WOL is determined based on device IDs for 82599 MACs */ 9933 switch (device_id) { 9934 case IXGBE_DEV_ID_82599_SFP: 9935 /* Only these subdevices could supports WOL */ 9936 switch (subdevice_id) { 9937 case IXGBE_SUBDEV_ID_82599_560FLR: 9938 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 9939 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 9940 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 9941 /* only support first port */ 9942 if (hw->bus.func != 0) 9943 break; 9944 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 9945 case IXGBE_SUBDEV_ID_82599_SFP: 9946 case IXGBE_SUBDEV_ID_82599_RNDC: 9947 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 9948 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 9949 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 9950 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 9951 return true; 9952 } 9953 break; 9954 case IXGBE_DEV_ID_82599EN_SFP: 9955 /* Only these subdevices support WOL */ 9956 switch (subdevice_id) { 9957 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 9958 return true; 9959 } 9960 break; 9961 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 9962 /* All except this subdevice support WOL */ 9963 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 9964 return true; 9965 break; 9966 case IXGBE_DEV_ID_82599_KX4: 9967 return true; 9968 default: 9969 break; 9970 } 9971 9972 return false; 9973 } 9974 9975 /** 9976 * ixgbe_probe - Device Initialization Routine 9977 * @pdev: PCI device information struct 9978 * @ent: entry in ixgbe_pci_tbl 9979 * 9980 * Returns 0 on success, negative on failure 9981 * 9982 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 9983 * The OS initialization, configuring of the adapter private structure, 9984 * and a hardware reset occur. 9985 **/ 9986 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 9987 { 9988 struct net_device *netdev; 9989 struct ixgbe_adapter *adapter = NULL; 9990 struct ixgbe_hw *hw; 9991 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 9992 int i, err, pci_using_dac, expected_gts; 9993 unsigned int indices = MAX_TX_QUEUES; 9994 u8 part_str[IXGBE_PBANUM_LENGTH]; 9995 bool disable_dev = false; 9996 #ifdef IXGBE_FCOE 9997 u16 device_caps; 9998 #endif 9999 u32 eec; 10000 10001 /* Catch broken hardware that put the wrong VF device ID in 10002 * the PCIe SR-IOV capability. 10003 */ 10004 if (pdev->is_virtfn) { 10005 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10006 pci_name(pdev), pdev->vendor, pdev->device); 10007 return -EINVAL; 10008 } 10009 10010 err = pci_enable_device_mem(pdev); 10011 if (err) 10012 return err; 10013 10014 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10015 pci_using_dac = 1; 10016 } else { 10017 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10018 if (err) { 10019 dev_err(&pdev->dev, 10020 "No usable DMA configuration, aborting\n"); 10021 goto err_dma; 10022 } 10023 pci_using_dac = 0; 10024 } 10025 10026 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10027 if (err) { 10028 dev_err(&pdev->dev, 10029 "pci_request_selected_regions failed 0x%x\n", err); 10030 goto err_pci_reg; 10031 } 10032 10033 pci_enable_pcie_error_reporting(pdev); 10034 10035 pci_set_master(pdev); 10036 pci_save_state(pdev); 10037 10038 if (ii->mac == ixgbe_mac_82598EB) { 10039 #ifdef CONFIG_IXGBE_DCB 10040 /* 8 TC w/ 4 queues per TC */ 10041 indices = 4 * MAX_TRAFFIC_CLASS; 10042 #else 10043 indices = IXGBE_MAX_RSS_INDICES; 10044 #endif 10045 } 10046 10047 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10048 if (!netdev) { 10049 err = -ENOMEM; 10050 goto err_alloc_etherdev; 10051 } 10052 10053 SET_NETDEV_DEV(netdev, &pdev->dev); 10054 10055 adapter = netdev_priv(netdev); 10056 10057 adapter->netdev = netdev; 10058 adapter->pdev = pdev; 10059 hw = &adapter->hw; 10060 hw->back = adapter; 10061 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10062 10063 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10064 pci_resource_len(pdev, 0)); 10065 adapter->io_addr = hw->hw_addr; 10066 if (!hw->hw_addr) { 10067 err = -EIO; 10068 goto err_ioremap; 10069 } 10070 10071 netdev->netdev_ops = &ixgbe_netdev_ops; 10072 ixgbe_set_ethtool_ops(netdev); 10073 netdev->watchdog_timeo = 5 * HZ; 10074 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10075 10076 /* Setup hw api */ 10077 hw->mac.ops = *ii->mac_ops; 10078 hw->mac.type = ii->mac; 10079 hw->mvals = ii->mvals; 10080 if (ii->link_ops) 10081 hw->link.ops = *ii->link_ops; 10082 10083 /* EEPROM */ 10084 hw->eeprom.ops = *ii->eeprom_ops; 10085 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10086 if (ixgbe_removed(hw->hw_addr)) { 10087 err = -EIO; 10088 goto err_ioremap; 10089 } 10090 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10091 if (!(eec & BIT(8))) 10092 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10093 10094 /* PHY */ 10095 hw->phy.ops = *ii->phy_ops; 10096 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10097 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10098 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10099 hw->phy.mdio.mmds = 0; 10100 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10101 hw->phy.mdio.dev = netdev; 10102 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10103 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10104 10105 /* setup the private structure */ 10106 err = ixgbe_sw_init(adapter, ii); 10107 if (err) 10108 goto err_sw_init; 10109 10110 /* Make sure the SWFW semaphore is in a valid state */ 10111 if (hw->mac.ops.init_swfw_sync) 10112 hw->mac.ops.init_swfw_sync(hw); 10113 10114 /* Make it possible the adapter to be woken up via WOL */ 10115 switch (adapter->hw.mac.type) { 10116 case ixgbe_mac_82599EB: 10117 case ixgbe_mac_X540: 10118 case ixgbe_mac_X550: 10119 case ixgbe_mac_X550EM_x: 10120 case ixgbe_mac_x550em_a: 10121 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10122 break; 10123 default: 10124 break; 10125 } 10126 10127 /* 10128 * If there is a fan on this device and it has failed log the 10129 * failure. 10130 */ 10131 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10132 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10133 if (esdp & IXGBE_ESDP_SDP1) 10134 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10135 } 10136 10137 if (allow_unsupported_sfp) 10138 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10139 10140 /* reset_hw fills in the perm_addr as well */ 10141 hw->phy.reset_if_overtemp = true; 10142 err = hw->mac.ops.reset_hw(hw); 10143 hw->phy.reset_if_overtemp = false; 10144 ixgbe_set_eee_capable(adapter); 10145 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10146 err = 0; 10147 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10148 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10149 e_dev_err("Reload the driver after installing a supported module.\n"); 10150 goto err_sw_init; 10151 } else if (err) { 10152 e_dev_err("HW Init failed: %d\n", err); 10153 goto err_sw_init; 10154 } 10155 10156 #ifdef CONFIG_PCI_IOV 10157 /* SR-IOV not supported on the 82598 */ 10158 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10159 goto skip_sriov; 10160 /* Mailbox */ 10161 ixgbe_init_mbx_params_pf(hw); 10162 hw->mbx.ops = ii->mbx_ops; 10163 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10164 ixgbe_enable_sriov(adapter, max_vfs); 10165 skip_sriov: 10166 10167 #endif 10168 netdev->features = NETIF_F_SG | 10169 NETIF_F_TSO | 10170 NETIF_F_TSO6 | 10171 NETIF_F_RXHASH | 10172 NETIF_F_RXCSUM | 10173 NETIF_F_HW_CSUM; 10174 10175 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10176 NETIF_F_GSO_GRE_CSUM | \ 10177 NETIF_F_GSO_IPXIP4 | \ 10178 NETIF_F_GSO_IPXIP6 | \ 10179 NETIF_F_GSO_UDP_TUNNEL | \ 10180 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10181 10182 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10183 netdev->features |= NETIF_F_GSO_PARTIAL | 10184 IXGBE_GSO_PARTIAL_FEATURES; 10185 10186 if (hw->mac.type >= ixgbe_mac_82599EB) 10187 netdev->features |= NETIF_F_SCTP_CRC; 10188 10189 /* copy netdev features into list of user selectable features */ 10190 netdev->hw_features |= netdev->features | 10191 NETIF_F_HW_VLAN_CTAG_FILTER | 10192 NETIF_F_HW_VLAN_CTAG_RX | 10193 NETIF_F_HW_VLAN_CTAG_TX | 10194 NETIF_F_RXALL | 10195 NETIF_F_HW_L2FW_DOFFLOAD; 10196 10197 if (hw->mac.type >= ixgbe_mac_82599EB) 10198 netdev->hw_features |= NETIF_F_NTUPLE | 10199 NETIF_F_HW_TC; 10200 10201 if (pci_using_dac) 10202 netdev->features |= NETIF_F_HIGHDMA; 10203 10204 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10205 netdev->hw_enc_features |= netdev->vlan_features; 10206 netdev->mpls_features |= NETIF_F_HW_CSUM; 10207 10208 /* set this bit last since it cannot be part of vlan_features */ 10209 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10210 NETIF_F_HW_VLAN_CTAG_RX | 10211 NETIF_F_HW_VLAN_CTAG_TX; 10212 10213 netdev->priv_flags |= IFF_UNICAST_FLT; 10214 netdev->priv_flags |= IFF_SUPP_NOFCS; 10215 10216 /* MTU range: 68 - 9710 */ 10217 netdev->min_mtu = ETH_MIN_MTU; 10218 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10219 10220 #ifdef CONFIG_IXGBE_DCB 10221 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10222 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10223 #endif 10224 10225 #ifdef IXGBE_FCOE 10226 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10227 unsigned int fcoe_l; 10228 10229 if (hw->mac.ops.get_device_caps) { 10230 hw->mac.ops.get_device_caps(hw, &device_caps); 10231 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10232 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10233 } 10234 10235 10236 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10237 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10238 10239 netdev->features |= NETIF_F_FSO | 10240 NETIF_F_FCOE_CRC; 10241 10242 netdev->vlan_features |= NETIF_F_FSO | 10243 NETIF_F_FCOE_CRC | 10244 NETIF_F_FCOE_MTU; 10245 } 10246 #endif /* IXGBE_FCOE */ 10247 10248 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10249 netdev->hw_features |= NETIF_F_LRO; 10250 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10251 netdev->features |= NETIF_F_LRO; 10252 10253 /* make sure the EEPROM is good */ 10254 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10255 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10256 err = -EIO; 10257 goto err_sw_init; 10258 } 10259 10260 eth_platform_get_mac_address(&adapter->pdev->dev, 10261 adapter->hw.mac.perm_addr); 10262 10263 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10264 10265 if (!is_valid_ether_addr(netdev->dev_addr)) { 10266 e_dev_err("invalid MAC address\n"); 10267 err = -EIO; 10268 goto err_sw_init; 10269 } 10270 10271 /* Set hw->mac.addr to permanent MAC address */ 10272 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10273 ixgbe_mac_set_default_filter(adapter); 10274 10275 setup_timer(&adapter->service_timer, &ixgbe_service_timer, 10276 (unsigned long) adapter); 10277 10278 if (ixgbe_removed(hw->hw_addr)) { 10279 err = -EIO; 10280 goto err_sw_init; 10281 } 10282 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10283 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10284 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10285 10286 err = ixgbe_init_interrupt_scheme(adapter); 10287 if (err) 10288 goto err_sw_init; 10289 10290 for (i = 0; i < adapter->num_xdp_queues; i++) 10291 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10292 10293 /* WOL not supported for all devices */ 10294 adapter->wol = 0; 10295 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10296 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10297 pdev->subsystem_device); 10298 if (hw->wol_enabled) 10299 adapter->wol = IXGBE_WUFC_MAG; 10300 10301 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10302 10303 /* save off EEPROM version number */ 10304 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); 10305 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); 10306 10307 /* pick up the PCI bus settings for reporting later */ 10308 if (ixgbe_pcie_from_parent(hw)) 10309 ixgbe_get_parent_bus_info(adapter); 10310 else 10311 hw->mac.ops.get_bus_info(hw); 10312 10313 /* calculate the expected PCIe bandwidth required for optimal 10314 * performance. Note that some older parts will never have enough 10315 * bandwidth due to being older generation PCIe parts. We clamp these 10316 * parts to ensure no warning is displayed if it can't be fixed. 10317 */ 10318 switch (hw->mac.type) { 10319 case ixgbe_mac_82598EB: 10320 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10321 break; 10322 default: 10323 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10324 break; 10325 } 10326 10327 /* don't check link if we failed to enumerate functions */ 10328 if (expected_gts > 0) 10329 ixgbe_check_minimum_link(adapter, expected_gts); 10330 10331 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10332 if (err) 10333 strlcpy(part_str, "Unknown", sizeof(part_str)); 10334 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10335 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10336 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10337 part_str); 10338 else 10339 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10340 hw->mac.type, hw->phy.type, part_str); 10341 10342 e_dev_info("%pM\n", netdev->dev_addr); 10343 10344 /* reset the hardware with the new settings */ 10345 err = hw->mac.ops.start_hw(hw); 10346 if (err == IXGBE_ERR_EEPROM_VERSION) { 10347 /* We are running on a pre-production device, log a warning */ 10348 e_dev_warn("This device is a pre-production adapter/LOM. " 10349 "Please be aware there may be issues associated " 10350 "with your hardware. If you are experiencing " 10351 "problems please contact your Intel or hardware " 10352 "representative who provided you with this " 10353 "hardware.\n"); 10354 } 10355 strcpy(netdev->name, "eth%d"); 10356 err = register_netdev(netdev); 10357 if (err) 10358 goto err_register; 10359 10360 pci_set_drvdata(pdev, adapter); 10361 10362 /* power down the optics for 82599 SFP+ fiber */ 10363 if (hw->mac.ops.disable_tx_laser) 10364 hw->mac.ops.disable_tx_laser(hw); 10365 10366 /* carrier off reporting is important to ethtool even BEFORE open */ 10367 netif_carrier_off(netdev); 10368 10369 #ifdef CONFIG_IXGBE_DCA 10370 if (dca_add_requester(&pdev->dev) == 0) { 10371 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10372 ixgbe_setup_dca(adapter); 10373 } 10374 #endif 10375 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10376 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10377 for (i = 0; i < adapter->num_vfs; i++) 10378 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10379 } 10380 10381 /* firmware requires driver version to be 0xFFFFFFFF 10382 * since os does not support feature 10383 */ 10384 if (hw->mac.ops.set_fw_drv_ver) 10385 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10386 sizeof(ixgbe_driver_version) - 1, 10387 ixgbe_driver_version); 10388 10389 /* add san mac addr to netdev */ 10390 ixgbe_add_sanmac_netdev(netdev); 10391 10392 e_dev_info("%s\n", ixgbe_default_device_descr); 10393 10394 #ifdef CONFIG_IXGBE_HWMON 10395 if (ixgbe_sysfs_init(adapter)) 10396 e_err(probe, "failed to allocate sysfs resources\n"); 10397 #endif /* CONFIG_IXGBE_HWMON */ 10398 10399 ixgbe_dbg_adapter_init(adapter); 10400 10401 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10402 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10403 hw->mac.ops.setup_link(hw, 10404 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10405 true); 10406 10407 return 0; 10408 10409 err_register: 10410 ixgbe_release_hw_control(adapter); 10411 ixgbe_clear_interrupt_scheme(adapter); 10412 err_sw_init: 10413 ixgbe_disable_sriov(adapter); 10414 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10415 iounmap(adapter->io_addr); 10416 kfree(adapter->jump_tables[0]); 10417 kfree(adapter->mac_table); 10418 kfree(adapter->rss_key); 10419 err_ioremap: 10420 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10421 free_netdev(netdev); 10422 err_alloc_etherdev: 10423 pci_release_mem_regions(pdev); 10424 err_pci_reg: 10425 err_dma: 10426 if (!adapter || disable_dev) 10427 pci_disable_device(pdev); 10428 return err; 10429 } 10430 10431 /** 10432 * ixgbe_remove - Device Removal Routine 10433 * @pdev: PCI device information struct 10434 * 10435 * ixgbe_remove is called by the PCI subsystem to alert the driver 10436 * that it should release a PCI device. The could be caused by a 10437 * Hot-Plug event, or because the driver is going to be removed from 10438 * memory. 10439 **/ 10440 static void ixgbe_remove(struct pci_dev *pdev) 10441 { 10442 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10443 struct net_device *netdev; 10444 bool disable_dev; 10445 int i; 10446 10447 /* if !adapter then we already cleaned up in probe */ 10448 if (!adapter) 10449 return; 10450 10451 netdev = adapter->netdev; 10452 ixgbe_dbg_adapter_exit(adapter); 10453 10454 set_bit(__IXGBE_REMOVING, &adapter->state); 10455 cancel_work_sync(&adapter->service_task); 10456 10457 10458 #ifdef CONFIG_IXGBE_DCA 10459 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10460 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10461 dca_remove_requester(&pdev->dev); 10462 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10463 IXGBE_DCA_CTRL_DCA_DISABLE); 10464 } 10465 10466 #endif 10467 #ifdef CONFIG_IXGBE_HWMON 10468 ixgbe_sysfs_exit(adapter); 10469 #endif /* CONFIG_IXGBE_HWMON */ 10470 10471 /* remove the added san mac */ 10472 ixgbe_del_sanmac_netdev(netdev); 10473 10474 #ifdef CONFIG_PCI_IOV 10475 ixgbe_disable_sriov(adapter); 10476 #endif 10477 if (netdev->reg_state == NETREG_REGISTERED) 10478 unregister_netdev(netdev); 10479 10480 ixgbe_clear_interrupt_scheme(adapter); 10481 10482 ixgbe_release_hw_control(adapter); 10483 10484 #ifdef CONFIG_DCB 10485 kfree(adapter->ixgbe_ieee_pfc); 10486 kfree(adapter->ixgbe_ieee_ets); 10487 10488 #endif 10489 iounmap(adapter->io_addr); 10490 pci_release_mem_regions(pdev); 10491 10492 e_dev_info("complete\n"); 10493 10494 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10495 if (adapter->jump_tables[i]) { 10496 kfree(adapter->jump_tables[i]->input); 10497 kfree(adapter->jump_tables[i]->mask); 10498 } 10499 kfree(adapter->jump_tables[i]); 10500 } 10501 10502 kfree(adapter->mac_table); 10503 kfree(adapter->rss_key); 10504 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10505 free_netdev(netdev); 10506 10507 pci_disable_pcie_error_reporting(pdev); 10508 10509 if (disable_dev) 10510 pci_disable_device(pdev); 10511 } 10512 10513 /** 10514 * ixgbe_io_error_detected - called when PCI error is detected 10515 * @pdev: Pointer to PCI device 10516 * @state: The current pci connection state 10517 * 10518 * This function is called after a PCI bus error affecting 10519 * this device has been detected. 10520 */ 10521 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10522 pci_channel_state_t state) 10523 { 10524 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10525 struct net_device *netdev = adapter->netdev; 10526 10527 #ifdef CONFIG_PCI_IOV 10528 struct ixgbe_hw *hw = &adapter->hw; 10529 struct pci_dev *bdev, *vfdev; 10530 u32 dw0, dw1, dw2, dw3; 10531 int vf, pos; 10532 u16 req_id, pf_func; 10533 10534 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10535 adapter->num_vfs == 0) 10536 goto skip_bad_vf_detection; 10537 10538 bdev = pdev->bus->self; 10539 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10540 bdev = bdev->bus->self; 10541 10542 if (!bdev) 10543 goto skip_bad_vf_detection; 10544 10545 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10546 if (!pos) 10547 goto skip_bad_vf_detection; 10548 10549 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10550 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10551 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10552 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10553 if (ixgbe_removed(hw->hw_addr)) 10554 goto skip_bad_vf_detection; 10555 10556 req_id = dw1 >> 16; 10557 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10558 if (!(req_id & 0x0080)) 10559 goto skip_bad_vf_detection; 10560 10561 pf_func = req_id & 0x01; 10562 if ((pf_func & 1) == (pdev->devfn & 1)) { 10563 unsigned int device_id; 10564 10565 vf = (req_id & 0x7F) >> 1; 10566 e_dev_err("VF %d has caused a PCIe error\n", vf); 10567 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10568 "%8.8x\tdw3: %8.8x\n", 10569 dw0, dw1, dw2, dw3); 10570 switch (adapter->hw.mac.type) { 10571 case ixgbe_mac_82599EB: 10572 device_id = IXGBE_82599_VF_DEVICE_ID; 10573 break; 10574 case ixgbe_mac_X540: 10575 device_id = IXGBE_X540_VF_DEVICE_ID; 10576 break; 10577 case ixgbe_mac_X550: 10578 device_id = IXGBE_DEV_ID_X550_VF; 10579 break; 10580 case ixgbe_mac_X550EM_x: 10581 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10582 break; 10583 case ixgbe_mac_x550em_a: 10584 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10585 break; 10586 default: 10587 device_id = 0; 10588 break; 10589 } 10590 10591 /* Find the pci device of the offending VF */ 10592 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10593 while (vfdev) { 10594 if (vfdev->devfn == (req_id & 0xFF)) 10595 break; 10596 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10597 device_id, vfdev); 10598 } 10599 /* 10600 * There's a slim chance the VF could have been hot plugged, 10601 * so if it is no longer present we don't need to issue the 10602 * VFLR. Just clean up the AER in that case. 10603 */ 10604 if (vfdev) { 10605 ixgbe_issue_vf_flr(adapter, vfdev); 10606 /* Free device reference count */ 10607 pci_dev_put(vfdev); 10608 } 10609 10610 pci_cleanup_aer_uncorrect_error_status(pdev); 10611 } 10612 10613 /* 10614 * Even though the error may have occurred on the other port 10615 * we still need to increment the vf error reference count for 10616 * both ports because the I/O resume function will be called 10617 * for both of them. 10618 */ 10619 adapter->vferr_refcount++; 10620 10621 return PCI_ERS_RESULT_RECOVERED; 10622 10623 skip_bad_vf_detection: 10624 #endif /* CONFIG_PCI_IOV */ 10625 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10626 return PCI_ERS_RESULT_DISCONNECT; 10627 10628 rtnl_lock(); 10629 netif_device_detach(netdev); 10630 10631 if (state == pci_channel_io_perm_failure) { 10632 rtnl_unlock(); 10633 return PCI_ERS_RESULT_DISCONNECT; 10634 } 10635 10636 if (netif_running(netdev)) 10637 ixgbe_close_suspend(adapter); 10638 10639 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10640 pci_disable_device(pdev); 10641 rtnl_unlock(); 10642 10643 /* Request a slot reset. */ 10644 return PCI_ERS_RESULT_NEED_RESET; 10645 } 10646 10647 /** 10648 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10649 * @pdev: Pointer to PCI device 10650 * 10651 * Restart the card from scratch, as if from a cold-boot. 10652 */ 10653 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10654 { 10655 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10656 pci_ers_result_t result; 10657 int err; 10658 10659 if (pci_enable_device_mem(pdev)) { 10660 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10661 result = PCI_ERS_RESULT_DISCONNECT; 10662 } else { 10663 smp_mb__before_atomic(); 10664 clear_bit(__IXGBE_DISABLED, &adapter->state); 10665 adapter->hw.hw_addr = adapter->io_addr; 10666 pci_set_master(pdev); 10667 pci_restore_state(pdev); 10668 pci_save_state(pdev); 10669 10670 pci_wake_from_d3(pdev, false); 10671 10672 ixgbe_reset(adapter); 10673 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10674 result = PCI_ERS_RESULT_RECOVERED; 10675 } 10676 10677 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10678 if (err) { 10679 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10680 "failed 0x%0x\n", err); 10681 /* non-fatal, continue */ 10682 } 10683 10684 return result; 10685 } 10686 10687 /** 10688 * ixgbe_io_resume - called when traffic can start flowing again. 10689 * @pdev: Pointer to PCI device 10690 * 10691 * This callback is called when the error recovery driver tells us that 10692 * its OK to resume normal operation. 10693 */ 10694 static void ixgbe_io_resume(struct pci_dev *pdev) 10695 { 10696 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10697 struct net_device *netdev = adapter->netdev; 10698 10699 #ifdef CONFIG_PCI_IOV 10700 if (adapter->vferr_refcount) { 10701 e_info(drv, "Resuming after VF err\n"); 10702 adapter->vferr_refcount--; 10703 return; 10704 } 10705 10706 #endif 10707 rtnl_lock(); 10708 if (netif_running(netdev)) 10709 ixgbe_open(netdev); 10710 10711 netif_device_attach(netdev); 10712 rtnl_unlock(); 10713 } 10714 10715 static const struct pci_error_handlers ixgbe_err_handler = { 10716 .error_detected = ixgbe_io_error_detected, 10717 .slot_reset = ixgbe_io_slot_reset, 10718 .resume = ixgbe_io_resume, 10719 }; 10720 10721 static struct pci_driver ixgbe_driver = { 10722 .name = ixgbe_driver_name, 10723 .id_table = ixgbe_pci_tbl, 10724 .probe = ixgbe_probe, 10725 .remove = ixgbe_remove, 10726 #ifdef CONFIG_PM 10727 .suspend = ixgbe_suspend, 10728 .resume = ixgbe_resume, 10729 #endif 10730 .shutdown = ixgbe_shutdown, 10731 .sriov_configure = ixgbe_pci_sriov_configure, 10732 .err_handler = &ixgbe_err_handler 10733 }; 10734 10735 /** 10736 * ixgbe_init_module - Driver Registration Routine 10737 * 10738 * ixgbe_init_module is the first routine called when the driver is 10739 * loaded. All it does is register with the PCI subsystem. 10740 **/ 10741 static int __init ixgbe_init_module(void) 10742 { 10743 int ret; 10744 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 10745 pr_info("%s\n", ixgbe_copyright); 10746 10747 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 10748 if (!ixgbe_wq) { 10749 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 10750 return -ENOMEM; 10751 } 10752 10753 ixgbe_dbg_init(); 10754 10755 ret = pci_register_driver(&ixgbe_driver); 10756 if (ret) { 10757 destroy_workqueue(ixgbe_wq); 10758 ixgbe_dbg_exit(); 10759 return ret; 10760 } 10761 10762 #ifdef CONFIG_IXGBE_DCA 10763 dca_register_notify(&dca_notifier); 10764 #endif 10765 10766 return 0; 10767 } 10768 10769 module_init(ixgbe_init_module); 10770 10771 /** 10772 * ixgbe_exit_module - Driver Exit Cleanup Routine 10773 * 10774 * ixgbe_exit_module is called just before the driver is removed 10775 * from memory. 10776 **/ 10777 static void __exit ixgbe_exit_module(void) 10778 { 10779 #ifdef CONFIG_IXGBE_DCA 10780 dca_unregister_notify(&dca_notifier); 10781 #endif 10782 pci_unregister_driver(&ixgbe_driver); 10783 10784 ixgbe_dbg_exit(); 10785 if (ixgbe_wq) { 10786 destroy_workqueue(ixgbe_wq); 10787 ixgbe_wq = NULL; 10788 } 10789 } 10790 10791 #ifdef CONFIG_IXGBE_DCA 10792 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 10793 void *p) 10794 { 10795 int ret_val; 10796 10797 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 10798 __ixgbe_notify_dca); 10799 10800 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 10801 } 10802 10803 #endif /* CONFIG_IXGBE_DCA */ 10804 10805 module_exit(ixgbe_exit_module); 10806 10807 /* ixgbe_main.c */ 10808