1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/netdevice.h> 33 #include <linux/vmalloc.h> 34 #include <linux/string.h> 35 #include <linux/in.h> 36 #include <linux/interrupt.h> 37 #include <linux/ip.h> 38 #include <linux/tcp.h> 39 #include <linux/sctp.h> 40 #include <linux/pkt_sched.h> 41 #include <linux/ipv6.h> 42 #include <linux/slab.h> 43 #include <net/checksum.h> 44 #include <net/ip6_checksum.h> 45 #include <linux/etherdevice.h> 46 #include <linux/ethtool.h> 47 #include <linux/if.h> 48 #include <linux/if_vlan.h> 49 #include <linux/if_macvlan.h> 50 #include <linux/if_bridge.h> 51 #include <linux/prefetch.h> 52 #include <linux/bpf.h> 53 #include <linux/bpf_trace.h> 54 #include <linux/atomic.h> 55 #include <scsi/fc/fc_fcoe.h> 56 #include <net/udp_tunnel.h> 57 #include <net/pkt_cls.h> 58 #include <net/tc_act/tc_gact.h> 59 #include <net/tc_act/tc_mirred.h> 60 #include <net/vxlan.h> 61 #include <net/mpls.h> 62 63 #include "ixgbe.h" 64 #include "ixgbe_common.h" 65 #include "ixgbe_dcb_82599.h" 66 #include "ixgbe_sriov.h" 67 #include "ixgbe_model.h" 68 69 char ixgbe_driver_name[] = "ixgbe"; 70 static const char ixgbe_driver_string[] = 71 "Intel(R) 10 Gigabit PCI Express Network Driver"; 72 #ifdef IXGBE_FCOE 73 char ixgbe_default_device_descr[] = 74 "Intel(R) 10 Gigabit Network Connection"; 75 #else 76 static char ixgbe_default_device_descr[] = 77 "Intel(R) 10 Gigabit Network Connection"; 78 #endif 79 #define DRV_VERSION "5.1.0-k" 80 const char ixgbe_driver_version[] = DRV_VERSION; 81 static const char ixgbe_copyright[] = 82 "Copyright (c) 1999-2016 Intel Corporation."; 83 84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 85 86 static const struct ixgbe_info *ixgbe_info_tbl[] = { 87 [board_82598] = &ixgbe_82598_info, 88 [board_82599] = &ixgbe_82599_info, 89 [board_X540] = &ixgbe_X540_info, 90 [board_X550] = &ixgbe_X550_info, 91 [board_X550EM_x] = &ixgbe_X550EM_x_info, 92 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 93 [board_x550em_a] = &ixgbe_x550em_a_info, 94 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 95 }; 96 97 /* ixgbe_pci_tbl - PCI Device ID Table 98 * 99 * Wildcard entries (PCI_ANY_ID) should come last 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 103 * Class, Class Mask, private data (not used) } 104 */ 105 static const struct pci_device_id ixgbe_pci_tbl[] = { 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 141 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 142 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 143 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 144 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 145 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 146 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 147 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 148 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 149 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 150 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 151 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 152 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 153 /* required last entry */ 154 {0, } 155 }; 156 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 157 158 #ifdef CONFIG_IXGBE_DCA 159 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 160 void *p); 161 static struct notifier_block dca_notifier = { 162 .notifier_call = ixgbe_notify_dca, 163 .next = NULL, 164 .priority = 0 165 }; 166 #endif 167 168 #ifdef CONFIG_PCI_IOV 169 static unsigned int max_vfs; 170 module_param(max_vfs, uint, 0); 171 MODULE_PARM_DESC(max_vfs, 172 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 173 #endif /* CONFIG_PCI_IOV */ 174 175 static unsigned int allow_unsupported_sfp; 176 module_param(allow_unsupported_sfp, uint, 0); 177 MODULE_PARM_DESC(allow_unsupported_sfp, 178 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 179 180 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 181 static int debug = -1; 182 module_param(debug, int, 0); 183 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 184 185 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 186 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 187 MODULE_LICENSE("GPL"); 188 MODULE_VERSION(DRV_VERSION); 189 190 static struct workqueue_struct *ixgbe_wq; 191 192 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 193 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 194 195 static const struct net_device_ops ixgbe_netdev_ops; 196 197 static bool netif_is_ixgbe(struct net_device *dev) 198 { 199 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 200 } 201 202 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 203 u32 reg, u16 *value) 204 { 205 struct pci_dev *parent_dev; 206 struct pci_bus *parent_bus; 207 208 parent_bus = adapter->pdev->bus->parent; 209 if (!parent_bus) 210 return -1; 211 212 parent_dev = parent_bus->self; 213 if (!parent_dev) 214 return -1; 215 216 if (!pci_is_pcie(parent_dev)) 217 return -1; 218 219 pcie_capability_read_word(parent_dev, reg, value); 220 if (*value == IXGBE_FAILED_READ_CFG_WORD && 221 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 222 return -1; 223 return 0; 224 } 225 226 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 227 { 228 struct ixgbe_hw *hw = &adapter->hw; 229 u16 link_status = 0; 230 int err; 231 232 hw->bus.type = ixgbe_bus_type_pci_express; 233 234 /* Get the negotiated link width and speed from PCI config space of the 235 * parent, as this device is behind a switch 236 */ 237 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 238 239 /* assume caller will handle error case */ 240 if (err) 241 return err; 242 243 hw->bus.width = ixgbe_convert_bus_width(link_status); 244 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 245 246 return 0; 247 } 248 249 /** 250 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent 251 * @hw: hw specific details 252 * 253 * This function is used by probe to determine whether a device's PCI-Express 254 * bandwidth details should be gathered from the parent bus instead of from the 255 * device. Used to ensure that various locations all have the correct device ID 256 * checks. 257 */ 258 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 259 { 260 switch (hw->device_id) { 261 case IXGBE_DEV_ID_82599_SFP_SF_QP: 262 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 263 return true; 264 default: 265 return false; 266 } 267 } 268 269 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 270 int expected_gts) 271 { 272 struct ixgbe_hw *hw = &adapter->hw; 273 int max_gts = 0; 274 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; 275 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; 276 struct pci_dev *pdev; 277 278 /* Some devices are not connected over PCIe and thus do not negotiate 279 * speed. These devices do not have valid bus info, and thus any report 280 * we generate may not be correct. 281 */ 282 if (hw->bus.type == ixgbe_bus_type_internal) 283 return; 284 285 /* determine whether to use the parent device */ 286 if (ixgbe_pcie_from_parent(&adapter->hw)) 287 pdev = adapter->pdev->bus->parent->self; 288 else 289 pdev = adapter->pdev; 290 291 if (pcie_get_minimum_link(pdev, &speed, &width) || 292 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 293 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 294 return; 295 } 296 297 switch (speed) { 298 case PCIE_SPEED_2_5GT: 299 /* 8b/10b encoding reduces max throughput by 20% */ 300 max_gts = 2 * width; 301 break; 302 case PCIE_SPEED_5_0GT: 303 /* 8b/10b encoding reduces max throughput by 20% */ 304 max_gts = 4 * width; 305 break; 306 case PCIE_SPEED_8_0GT: 307 /* 128b/130b encoding reduces throughput by less than 2% */ 308 max_gts = 8 * width; 309 break; 310 default: 311 e_dev_warn("Unable to determine PCI Express bandwidth.\n"); 312 return; 313 } 314 315 e_dev_info("PCI Express bandwidth of %dGT/s available\n", 316 max_gts); 317 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", 318 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : 319 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : 320 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : 321 "Unknown"), 322 width, 323 (speed == PCIE_SPEED_2_5GT ? "20%" : 324 speed == PCIE_SPEED_5_0GT ? "20%" : 325 speed == PCIE_SPEED_8_0GT ? "<2%" : 326 "Unknown")); 327 328 if (max_gts < expected_gts) { 329 e_dev_warn("This is not sufficient for optimal performance of this card.\n"); 330 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", 331 expected_gts); 332 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); 333 } 334 } 335 336 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 337 { 338 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 339 !test_bit(__IXGBE_REMOVING, &adapter->state) && 340 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 341 queue_work(ixgbe_wq, &adapter->service_task); 342 } 343 344 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 345 { 346 struct ixgbe_adapter *adapter = hw->back; 347 348 if (!hw->hw_addr) 349 return; 350 hw->hw_addr = NULL; 351 e_dev_err("Adapter removed\n"); 352 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 353 ixgbe_service_event_schedule(adapter); 354 } 355 356 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 357 { 358 u32 value; 359 360 /* The following check not only optimizes a bit by not 361 * performing a read on the status register when the 362 * register just read was a status register read that 363 * returned IXGBE_FAILED_READ_REG. It also blocks any 364 * potential recursion. 365 */ 366 if (reg == IXGBE_STATUS) { 367 ixgbe_remove_adapter(hw); 368 return; 369 } 370 value = ixgbe_read_reg(hw, IXGBE_STATUS); 371 if (value == IXGBE_FAILED_READ_REG) 372 ixgbe_remove_adapter(hw); 373 } 374 375 /** 376 * ixgbe_read_reg - Read from device register 377 * @hw: hw specific details 378 * @reg: offset of register to read 379 * 380 * Returns : value read or IXGBE_FAILED_READ_REG if removed 381 * 382 * This function is used to read device registers. It checks for device 383 * removal by confirming any read that returns all ones by checking the 384 * status register value for all ones. This function avoids reading from 385 * the hardware if a removal was previously detected in which case it 386 * returns IXGBE_FAILED_READ_REG (all ones). 387 */ 388 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 389 { 390 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 391 u32 value; 392 393 if (ixgbe_removed(reg_addr)) 394 return IXGBE_FAILED_READ_REG; 395 if (unlikely(hw->phy.nw_mng_if_sel & 396 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 397 struct ixgbe_adapter *adapter; 398 int i; 399 400 for (i = 0; i < 200; ++i) { 401 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 402 if (likely(!value)) 403 goto writes_completed; 404 if (value == IXGBE_FAILED_READ_REG) { 405 ixgbe_remove_adapter(hw); 406 return IXGBE_FAILED_READ_REG; 407 } 408 udelay(5); 409 } 410 411 adapter = hw->back; 412 e_warn(hw, "register writes incomplete %08x\n", value); 413 } 414 415 writes_completed: 416 value = readl(reg_addr + reg); 417 if (unlikely(value == IXGBE_FAILED_READ_REG)) 418 ixgbe_check_remove(hw, reg); 419 return value; 420 } 421 422 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 423 { 424 u16 value; 425 426 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 427 if (value == IXGBE_FAILED_READ_CFG_WORD) { 428 ixgbe_remove_adapter(hw); 429 return true; 430 } 431 return false; 432 } 433 434 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 435 { 436 struct ixgbe_adapter *adapter = hw->back; 437 u16 value; 438 439 if (ixgbe_removed(hw->hw_addr)) 440 return IXGBE_FAILED_READ_CFG_WORD; 441 pci_read_config_word(adapter->pdev, reg, &value); 442 if (value == IXGBE_FAILED_READ_CFG_WORD && 443 ixgbe_check_cfg_remove(hw, adapter->pdev)) 444 return IXGBE_FAILED_READ_CFG_WORD; 445 return value; 446 } 447 448 #ifdef CONFIG_PCI_IOV 449 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 450 { 451 struct ixgbe_adapter *adapter = hw->back; 452 u32 value; 453 454 if (ixgbe_removed(hw->hw_addr)) 455 return IXGBE_FAILED_READ_CFG_DWORD; 456 pci_read_config_dword(adapter->pdev, reg, &value); 457 if (value == IXGBE_FAILED_READ_CFG_DWORD && 458 ixgbe_check_cfg_remove(hw, adapter->pdev)) 459 return IXGBE_FAILED_READ_CFG_DWORD; 460 return value; 461 } 462 #endif /* CONFIG_PCI_IOV */ 463 464 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 465 { 466 struct ixgbe_adapter *adapter = hw->back; 467 468 if (ixgbe_removed(hw->hw_addr)) 469 return; 470 pci_write_config_word(adapter->pdev, reg, value); 471 } 472 473 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 474 { 475 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 476 477 /* flush memory to make sure state is correct before next watchdog */ 478 smp_mb__before_atomic(); 479 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 480 } 481 482 struct ixgbe_reg_info { 483 u32 ofs; 484 char *name; 485 }; 486 487 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 488 489 /* General Registers */ 490 {IXGBE_CTRL, "CTRL"}, 491 {IXGBE_STATUS, "STATUS"}, 492 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 493 494 /* Interrupt Registers */ 495 {IXGBE_EICR, "EICR"}, 496 497 /* RX Registers */ 498 {IXGBE_SRRCTL(0), "SRRCTL"}, 499 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 500 {IXGBE_RDLEN(0), "RDLEN"}, 501 {IXGBE_RDH(0), "RDH"}, 502 {IXGBE_RDT(0), "RDT"}, 503 {IXGBE_RXDCTL(0), "RXDCTL"}, 504 {IXGBE_RDBAL(0), "RDBAL"}, 505 {IXGBE_RDBAH(0), "RDBAH"}, 506 507 /* TX Registers */ 508 {IXGBE_TDBAL(0), "TDBAL"}, 509 {IXGBE_TDBAH(0), "TDBAH"}, 510 {IXGBE_TDLEN(0), "TDLEN"}, 511 {IXGBE_TDH(0), "TDH"}, 512 {IXGBE_TDT(0), "TDT"}, 513 {IXGBE_TXDCTL(0), "TXDCTL"}, 514 515 /* List Terminator */ 516 { .name = NULL } 517 }; 518 519 520 /* 521 * ixgbe_regdump - register printout routine 522 */ 523 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 524 { 525 int i; 526 char rname[16]; 527 u32 regs[64]; 528 529 switch (reginfo->ofs) { 530 case IXGBE_SRRCTL(0): 531 for (i = 0; i < 64; i++) 532 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 533 break; 534 case IXGBE_DCA_RXCTRL(0): 535 for (i = 0; i < 64; i++) 536 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 537 break; 538 case IXGBE_RDLEN(0): 539 for (i = 0; i < 64; i++) 540 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 541 break; 542 case IXGBE_RDH(0): 543 for (i = 0; i < 64; i++) 544 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 545 break; 546 case IXGBE_RDT(0): 547 for (i = 0; i < 64; i++) 548 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 549 break; 550 case IXGBE_RXDCTL(0): 551 for (i = 0; i < 64; i++) 552 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 553 break; 554 case IXGBE_RDBAL(0): 555 for (i = 0; i < 64; i++) 556 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 557 break; 558 case IXGBE_RDBAH(0): 559 for (i = 0; i < 64; i++) 560 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 561 break; 562 case IXGBE_TDBAL(0): 563 for (i = 0; i < 64; i++) 564 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 565 break; 566 case IXGBE_TDBAH(0): 567 for (i = 0; i < 64; i++) 568 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 569 break; 570 case IXGBE_TDLEN(0): 571 for (i = 0; i < 64; i++) 572 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 573 break; 574 case IXGBE_TDH(0): 575 for (i = 0; i < 64; i++) 576 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 577 break; 578 case IXGBE_TDT(0): 579 for (i = 0; i < 64; i++) 580 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 581 break; 582 case IXGBE_TXDCTL(0): 583 for (i = 0; i < 64; i++) 584 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 585 break; 586 default: 587 pr_info("%-15s %08x\n", 588 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 589 return; 590 } 591 592 i = 0; 593 while (i < 64) { 594 int j; 595 char buf[9 * 8 + 1]; 596 char *p = buf; 597 598 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 599 for (j = 0; j < 8; j++) 600 p += sprintf(p, " %08x", regs[i++]); 601 pr_err("%-15s%s\n", rname, buf); 602 } 603 604 } 605 606 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 607 { 608 struct ixgbe_tx_buffer *tx_buffer; 609 610 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 612 n, ring->next_to_use, ring->next_to_clean, 613 (u64)dma_unmap_addr(tx_buffer, dma), 614 dma_unmap_len(tx_buffer, len), 615 tx_buffer->next_to_watch, 616 (u64)tx_buffer->time_stamp); 617 } 618 619 /* 620 * ixgbe_dump - Print registers, tx-rings and rx-rings 621 */ 622 static void ixgbe_dump(struct ixgbe_adapter *adapter) 623 { 624 struct net_device *netdev = adapter->netdev; 625 struct ixgbe_hw *hw = &adapter->hw; 626 struct ixgbe_reg_info *reginfo; 627 int n = 0; 628 struct ixgbe_ring *ring; 629 struct ixgbe_tx_buffer *tx_buffer; 630 union ixgbe_adv_tx_desc *tx_desc; 631 struct my_u0 { u64 a; u64 b; } *u0; 632 struct ixgbe_ring *rx_ring; 633 union ixgbe_adv_rx_desc *rx_desc; 634 struct ixgbe_rx_buffer *rx_buffer_info; 635 int i = 0; 636 637 if (!netif_msg_hw(adapter)) 638 return; 639 640 /* Print netdevice Info */ 641 if (netdev) { 642 dev_info(&adapter->pdev->dev, "Net device Info\n"); 643 pr_info("Device Name state " 644 "trans_start\n"); 645 pr_info("%-15s %016lX %016lX\n", 646 netdev->name, 647 netdev->state, 648 dev_trans_start(netdev)); 649 } 650 651 /* Print Registers */ 652 dev_info(&adapter->pdev->dev, "Register Dump\n"); 653 pr_info(" Register Name Value\n"); 654 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 655 reginfo->name; reginfo++) { 656 ixgbe_regdump(hw, reginfo); 657 } 658 659 /* Print TX Ring Summary */ 660 if (!netdev || !netif_running(netdev)) 661 return; 662 663 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 664 pr_info(" %s %s %s %s\n", 665 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 666 "leng", "ntw", "timestamp"); 667 for (n = 0; n < adapter->num_tx_queues; n++) { 668 ring = adapter->tx_ring[n]; 669 ixgbe_print_buffer(ring, n); 670 } 671 672 for (n = 0; n < adapter->num_xdp_queues; n++) { 673 ring = adapter->xdp_ring[n]; 674 ixgbe_print_buffer(ring, n); 675 } 676 677 /* Print TX Rings */ 678 if (!netif_msg_tx_done(adapter)) 679 goto rx_ring_summary; 680 681 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 682 683 /* Transmit Descriptor Formats 684 * 685 * 82598 Advanced Transmit Descriptor 686 * +--------------------------------------------------------------+ 687 * 0 | Buffer Address [63:0] | 688 * +--------------------------------------------------------------+ 689 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 690 * +--------------------------------------------------------------+ 691 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 692 * 693 * 82598 Advanced Transmit Descriptor (Write-Back Format) 694 * +--------------------------------------------------------------+ 695 * 0 | RSV [63:0] | 696 * +--------------------------------------------------------------+ 697 * 8 | RSV | STA | NXTSEQ | 698 * +--------------------------------------------------------------+ 699 * 63 36 35 32 31 0 700 * 701 * 82599+ Advanced Transmit Descriptor 702 * +--------------------------------------------------------------+ 703 * 0 | Buffer Address [63:0] | 704 * +--------------------------------------------------------------+ 705 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 706 * +--------------------------------------------------------------+ 707 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 708 * 709 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 710 * +--------------------------------------------------------------+ 711 * 0 | RSV [63:0] | 712 * +--------------------------------------------------------------+ 713 * 8 | RSV | STA | RSV | 714 * +--------------------------------------------------------------+ 715 * 63 36 35 32 31 0 716 */ 717 718 for (n = 0; n < adapter->num_tx_queues; n++) { 719 ring = adapter->tx_ring[n]; 720 pr_info("------------------------------------\n"); 721 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 722 pr_info("------------------------------------\n"); 723 pr_info("%s%s %s %s %s %s\n", 724 "T [desc] [address 63:0 ] ", 725 "[PlPOIdStDDt Ln] [bi->dma ] ", 726 "leng", "ntw", "timestamp", "bi->skb"); 727 728 for (i = 0; ring->desc && (i < ring->count); i++) { 729 tx_desc = IXGBE_TX_DESC(ring, i); 730 tx_buffer = &ring->tx_buffer_info[i]; 731 u0 = (struct my_u0 *)tx_desc; 732 if (dma_unmap_len(tx_buffer, len) > 0) { 733 const char *ring_desc; 734 735 if (i == ring->next_to_use && 736 i == ring->next_to_clean) 737 ring_desc = " NTC/U"; 738 else if (i == ring->next_to_use) 739 ring_desc = " NTU"; 740 else if (i == ring->next_to_clean) 741 ring_desc = " NTC"; 742 else 743 ring_desc = ""; 744 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 745 i, 746 le64_to_cpu(u0->a), 747 le64_to_cpu(u0->b), 748 (u64)dma_unmap_addr(tx_buffer, dma), 749 dma_unmap_len(tx_buffer, len), 750 tx_buffer->next_to_watch, 751 (u64)tx_buffer->time_stamp, 752 tx_buffer->skb, 753 ring_desc); 754 755 if (netif_msg_pktdata(adapter) && 756 tx_buffer->skb) 757 print_hex_dump(KERN_INFO, "", 758 DUMP_PREFIX_ADDRESS, 16, 1, 759 tx_buffer->skb->data, 760 dma_unmap_len(tx_buffer, len), 761 true); 762 } 763 } 764 } 765 766 /* Print RX Rings Summary */ 767 rx_ring_summary: 768 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 769 pr_info("Queue [NTU] [NTC]\n"); 770 for (n = 0; n < adapter->num_rx_queues; n++) { 771 rx_ring = adapter->rx_ring[n]; 772 pr_info("%5d %5X %5X\n", 773 n, rx_ring->next_to_use, rx_ring->next_to_clean); 774 } 775 776 /* Print RX Rings */ 777 if (!netif_msg_rx_status(adapter)) 778 return; 779 780 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 781 782 /* Receive Descriptor Formats 783 * 784 * 82598 Advanced Receive Descriptor (Read) Format 785 * 63 1 0 786 * +-----------------------------------------------------+ 787 * 0 | Packet Buffer Address [63:1] |A0/NSE| 788 * +----------------------------------------------+------+ 789 * 8 | Header Buffer Address [63:1] | DD | 790 * +-----------------------------------------------------+ 791 * 792 * 793 * 82598 Advanced Receive Descriptor (Write-Back) Format 794 * 795 * 63 48 47 32 31 30 21 20 16 15 4 3 0 796 * +------------------------------------------------------+ 797 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 798 * | Packet | IP | | | | Type | Type | 799 * | Checksum | Ident | | | | | | 800 * +------------------------------------------------------+ 801 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 802 * +------------------------------------------------------+ 803 * 63 48 47 32 31 20 19 0 804 * 805 * 82599+ Advanced Receive Descriptor (Read) Format 806 * 63 1 0 807 * +-----------------------------------------------------+ 808 * 0 | Packet Buffer Address [63:1] |A0/NSE| 809 * +----------------------------------------------+------+ 810 * 8 | Header Buffer Address [63:1] | DD | 811 * +-----------------------------------------------------+ 812 * 813 * 814 * 82599+ Advanced Receive Descriptor (Write-Back) Format 815 * 816 * 63 48 47 32 31 30 21 20 17 16 4 3 0 817 * +------------------------------------------------------+ 818 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 819 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 820 * |/ Flow Dir Flt ID | | | | | | 821 * +------------------------------------------------------+ 822 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 823 * +------------------------------------------------------+ 824 * 63 48 47 32 31 20 19 0 825 */ 826 827 for (n = 0; n < adapter->num_rx_queues; n++) { 828 rx_ring = adapter->rx_ring[n]; 829 pr_info("------------------------------------\n"); 830 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 831 pr_info("------------------------------------\n"); 832 pr_info("%s%s%s\n", 833 "R [desc] [ PktBuf A0] ", 834 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 835 "<-- Adv Rx Read format"); 836 pr_info("%s%s%s\n", 837 "RWB[desc] [PcsmIpSHl PtRs] ", 838 "[vl er S cks ln] ---------------- [bi->skb ] ", 839 "<-- Adv Rx Write-Back format"); 840 841 for (i = 0; i < rx_ring->count; i++) { 842 const char *ring_desc; 843 844 if (i == rx_ring->next_to_use) 845 ring_desc = " NTU"; 846 else if (i == rx_ring->next_to_clean) 847 ring_desc = " NTC"; 848 else 849 ring_desc = ""; 850 851 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 852 rx_desc = IXGBE_RX_DESC(rx_ring, i); 853 u0 = (struct my_u0 *)rx_desc; 854 if (rx_desc->wb.upper.length) { 855 /* Descriptor Done */ 856 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 857 i, 858 le64_to_cpu(u0->a), 859 le64_to_cpu(u0->b), 860 rx_buffer_info->skb, 861 ring_desc); 862 } else { 863 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 864 i, 865 le64_to_cpu(u0->a), 866 le64_to_cpu(u0->b), 867 (u64)rx_buffer_info->dma, 868 rx_buffer_info->skb, 869 ring_desc); 870 871 if (netif_msg_pktdata(adapter) && 872 rx_buffer_info->dma) { 873 print_hex_dump(KERN_INFO, "", 874 DUMP_PREFIX_ADDRESS, 16, 1, 875 page_address(rx_buffer_info->page) + 876 rx_buffer_info->page_offset, 877 ixgbe_rx_bufsz(rx_ring), true); 878 } 879 } 880 } 881 } 882 } 883 884 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 885 { 886 u32 ctrl_ext; 887 888 /* Let firmware take over control of h/w */ 889 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 890 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 891 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 892 } 893 894 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 895 { 896 u32 ctrl_ext; 897 898 /* Let firmware know the driver has taken over */ 899 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 901 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 902 } 903 904 /** 905 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 906 * @adapter: pointer to adapter struct 907 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 908 * @queue: queue to map the corresponding interrupt to 909 * @msix_vector: the vector to map to the corresponding queue 910 * 911 */ 912 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 913 u8 queue, u8 msix_vector) 914 { 915 u32 ivar, index; 916 struct ixgbe_hw *hw = &adapter->hw; 917 switch (hw->mac.type) { 918 case ixgbe_mac_82598EB: 919 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 920 if (direction == -1) 921 direction = 0; 922 index = (((direction * 64) + queue) >> 2) & 0x1F; 923 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 924 ivar &= ~(0xFF << (8 * (queue & 0x3))); 925 ivar |= (msix_vector << (8 * (queue & 0x3))); 926 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 927 break; 928 case ixgbe_mac_82599EB: 929 case ixgbe_mac_X540: 930 case ixgbe_mac_X550: 931 case ixgbe_mac_X550EM_x: 932 case ixgbe_mac_x550em_a: 933 if (direction == -1) { 934 /* other causes */ 935 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 936 index = ((queue & 1) * 8); 937 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 938 ivar &= ~(0xFF << index); 939 ivar |= (msix_vector << index); 940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 941 break; 942 } else { 943 /* tx or rx causes */ 944 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 945 index = ((16 * (queue & 1)) + (8 * direction)); 946 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 947 ivar &= ~(0xFF << index); 948 ivar |= (msix_vector << index); 949 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 950 break; 951 } 952 default: 953 break; 954 } 955 } 956 957 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 958 u64 qmask) 959 { 960 u32 mask; 961 962 switch (adapter->hw.mac.type) { 963 case ixgbe_mac_82598EB: 964 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 965 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 966 break; 967 case ixgbe_mac_82599EB: 968 case ixgbe_mac_X540: 969 case ixgbe_mac_X550: 970 case ixgbe_mac_X550EM_x: 971 case ixgbe_mac_x550em_a: 972 mask = (qmask & 0xFFFFFFFF); 973 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 974 mask = (qmask >> 32); 975 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 976 break; 977 default: 978 break; 979 } 980 } 981 982 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 983 { 984 struct ixgbe_hw *hw = &adapter->hw; 985 struct ixgbe_hw_stats *hwstats = &adapter->stats; 986 int i; 987 u32 data; 988 989 if ((hw->fc.current_mode != ixgbe_fc_full) && 990 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 991 return; 992 993 switch (hw->mac.type) { 994 case ixgbe_mac_82598EB: 995 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 996 break; 997 default: 998 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 999 } 1000 hwstats->lxoffrxc += data; 1001 1002 /* refill credits (no tx hang) if we received xoff */ 1003 if (!data) 1004 return; 1005 1006 for (i = 0; i < adapter->num_tx_queues; i++) 1007 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1008 &adapter->tx_ring[i]->state); 1009 1010 for (i = 0; i < adapter->num_xdp_queues; i++) 1011 clear_bit(__IXGBE_HANG_CHECK_ARMED, 1012 &adapter->xdp_ring[i]->state); 1013 } 1014 1015 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 1016 { 1017 struct ixgbe_hw *hw = &adapter->hw; 1018 struct ixgbe_hw_stats *hwstats = &adapter->stats; 1019 u32 xoff[8] = {0}; 1020 u8 tc; 1021 int i; 1022 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 1023 1024 if (adapter->ixgbe_ieee_pfc) 1025 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 1026 1027 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 1028 ixgbe_update_xoff_rx_lfc(adapter); 1029 return; 1030 } 1031 1032 /* update stats for each tc, only valid with PFC enabled */ 1033 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 1034 u32 pxoffrxc; 1035 1036 switch (hw->mac.type) { 1037 case ixgbe_mac_82598EB: 1038 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 1039 break; 1040 default: 1041 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1042 } 1043 hwstats->pxoffrxc[i] += pxoffrxc; 1044 /* Get the TC for given UP */ 1045 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1046 xoff[tc] += pxoffrxc; 1047 } 1048 1049 /* disarm tx queues that have received xoff frames */ 1050 for (i = 0; i < adapter->num_tx_queues; i++) { 1051 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1052 1053 tc = tx_ring->dcb_tc; 1054 if (xoff[tc]) 1055 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1056 } 1057 1058 for (i = 0; i < adapter->num_xdp_queues; i++) { 1059 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1060 1061 tc = xdp_ring->dcb_tc; 1062 if (xoff[tc]) 1063 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1064 } 1065 } 1066 1067 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1068 { 1069 return ring->stats.packets; 1070 } 1071 1072 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1073 { 1074 unsigned int head, tail; 1075 1076 head = ring->next_to_clean; 1077 tail = ring->next_to_use; 1078 1079 return ((head <= tail) ? tail : tail + ring->count) - head; 1080 } 1081 1082 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1083 { 1084 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1085 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1086 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1087 1088 clear_check_for_tx_hang(tx_ring); 1089 1090 /* 1091 * Check for a hung queue, but be thorough. This verifies 1092 * that a transmit has been completed since the previous 1093 * check AND there is at least one packet pending. The 1094 * ARMED bit is set to indicate a potential hang. The 1095 * bit is cleared if a pause frame is received to remove 1096 * false hang detection due to PFC or 802.3x frames. By 1097 * requiring this to fail twice we avoid races with 1098 * pfc clearing the ARMED bit and conditions where we 1099 * run the check_tx_hang logic with a transmit completion 1100 * pending but without time to complete it yet. 1101 */ 1102 if (tx_done_old == tx_done && tx_pending) 1103 /* make sure it is true for two checks in a row */ 1104 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1105 &tx_ring->state); 1106 /* update completed stats and continue */ 1107 tx_ring->tx_stats.tx_done_old = tx_done; 1108 /* reset the countdown */ 1109 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1110 1111 return false; 1112 } 1113 1114 /** 1115 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1116 * @adapter: driver private struct 1117 **/ 1118 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1119 { 1120 1121 /* Do the reset outside of interrupt context */ 1122 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1123 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1124 e_warn(drv, "initiating reset due to tx timeout\n"); 1125 ixgbe_service_event_schedule(adapter); 1126 } 1127 } 1128 1129 /** 1130 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1131 * @netdev: network interface device structure 1132 * @queue_index: Tx queue to set 1133 * @maxrate: desired maximum transmit bitrate 1134 **/ 1135 static int ixgbe_tx_maxrate(struct net_device *netdev, 1136 int queue_index, u32 maxrate) 1137 { 1138 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1139 struct ixgbe_hw *hw = &adapter->hw; 1140 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1141 1142 if (!maxrate) 1143 return 0; 1144 1145 /* Calculate the rate factor values to set */ 1146 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1147 bcnrc_val /= maxrate; 1148 1149 /* clear everything but the rate factor */ 1150 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1151 IXGBE_RTTBCNRC_RF_DEC_MASK; 1152 1153 /* enable the rate scheduler */ 1154 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1155 1156 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1157 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1158 1159 return 0; 1160 } 1161 1162 /** 1163 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1164 * @q_vector: structure containing interrupt and ring information 1165 * @tx_ring: tx ring to clean 1166 * @napi_budget: Used to determine if we are in netpoll 1167 **/ 1168 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1169 struct ixgbe_ring *tx_ring, int napi_budget) 1170 { 1171 struct ixgbe_adapter *adapter = q_vector->adapter; 1172 struct ixgbe_tx_buffer *tx_buffer; 1173 union ixgbe_adv_tx_desc *tx_desc; 1174 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1175 unsigned int budget = q_vector->tx.work_limit; 1176 unsigned int i = tx_ring->next_to_clean; 1177 1178 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1179 return true; 1180 1181 tx_buffer = &tx_ring->tx_buffer_info[i]; 1182 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1183 i -= tx_ring->count; 1184 1185 do { 1186 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1187 1188 /* if next_to_watch is not set then there is no work pending */ 1189 if (!eop_desc) 1190 break; 1191 1192 /* prevent any other reads prior to eop_desc */ 1193 smp_rmb(); 1194 1195 /* if DD is not set pending work has not been completed */ 1196 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1197 break; 1198 1199 /* clear next_to_watch to prevent false hangs */ 1200 tx_buffer->next_to_watch = NULL; 1201 1202 /* update the statistics for this packet */ 1203 total_bytes += tx_buffer->bytecount; 1204 total_packets += tx_buffer->gso_segs; 1205 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1206 total_ipsec++; 1207 1208 /* free the skb */ 1209 if (ring_is_xdp(tx_ring)) 1210 page_frag_free(tx_buffer->data); 1211 else 1212 napi_consume_skb(tx_buffer->skb, napi_budget); 1213 1214 /* unmap skb header data */ 1215 dma_unmap_single(tx_ring->dev, 1216 dma_unmap_addr(tx_buffer, dma), 1217 dma_unmap_len(tx_buffer, len), 1218 DMA_TO_DEVICE); 1219 1220 /* clear tx_buffer data */ 1221 dma_unmap_len_set(tx_buffer, len, 0); 1222 1223 /* unmap remaining buffers */ 1224 while (tx_desc != eop_desc) { 1225 tx_buffer++; 1226 tx_desc++; 1227 i++; 1228 if (unlikely(!i)) { 1229 i -= tx_ring->count; 1230 tx_buffer = tx_ring->tx_buffer_info; 1231 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1232 } 1233 1234 /* unmap any remaining paged data */ 1235 if (dma_unmap_len(tx_buffer, len)) { 1236 dma_unmap_page(tx_ring->dev, 1237 dma_unmap_addr(tx_buffer, dma), 1238 dma_unmap_len(tx_buffer, len), 1239 DMA_TO_DEVICE); 1240 dma_unmap_len_set(tx_buffer, len, 0); 1241 } 1242 } 1243 1244 /* move us one more past the eop_desc for start of next pkt */ 1245 tx_buffer++; 1246 tx_desc++; 1247 i++; 1248 if (unlikely(!i)) { 1249 i -= tx_ring->count; 1250 tx_buffer = tx_ring->tx_buffer_info; 1251 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1252 } 1253 1254 /* issue prefetch for next Tx descriptor */ 1255 prefetch(tx_desc); 1256 1257 /* update budget accounting */ 1258 budget--; 1259 } while (likely(budget)); 1260 1261 i += tx_ring->count; 1262 tx_ring->next_to_clean = i; 1263 u64_stats_update_begin(&tx_ring->syncp); 1264 tx_ring->stats.bytes += total_bytes; 1265 tx_ring->stats.packets += total_packets; 1266 u64_stats_update_end(&tx_ring->syncp); 1267 q_vector->tx.total_bytes += total_bytes; 1268 q_vector->tx.total_packets += total_packets; 1269 adapter->tx_ipsec += total_ipsec; 1270 1271 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1272 /* schedule immediate reset if we believe we hung */ 1273 struct ixgbe_hw *hw = &adapter->hw; 1274 e_err(drv, "Detected Tx Unit Hang %s\n" 1275 " Tx Queue <%d>\n" 1276 " TDH, TDT <%x>, <%x>\n" 1277 " next_to_use <%x>\n" 1278 " next_to_clean <%x>\n" 1279 "tx_buffer_info[next_to_clean]\n" 1280 " time_stamp <%lx>\n" 1281 " jiffies <%lx>\n", 1282 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1283 tx_ring->queue_index, 1284 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1285 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1286 tx_ring->next_to_use, i, 1287 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1288 1289 if (!ring_is_xdp(tx_ring)) 1290 netif_stop_subqueue(tx_ring->netdev, 1291 tx_ring->queue_index); 1292 1293 e_info(probe, 1294 "tx hang %d detected on queue %d, resetting adapter\n", 1295 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1296 1297 /* schedule immediate reset if we believe we hung */ 1298 ixgbe_tx_timeout_reset(adapter); 1299 1300 /* the adapter is about to reset, no point in enabling stuff */ 1301 return true; 1302 } 1303 1304 if (ring_is_xdp(tx_ring)) 1305 return !!budget; 1306 1307 netdev_tx_completed_queue(txring_txq(tx_ring), 1308 total_packets, total_bytes); 1309 1310 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1311 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 1312 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 1313 /* Make sure that anybody stopping the queue after this 1314 * sees the new next_to_clean. 1315 */ 1316 smp_mb(); 1317 if (__netif_subqueue_stopped(tx_ring->netdev, 1318 tx_ring->queue_index) 1319 && !test_bit(__IXGBE_DOWN, &adapter->state)) { 1320 netif_wake_subqueue(tx_ring->netdev, 1321 tx_ring->queue_index); 1322 ++tx_ring->tx_stats.restart_queue; 1323 } 1324 } 1325 1326 return !!budget; 1327 } 1328 1329 #ifdef CONFIG_IXGBE_DCA 1330 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1331 struct ixgbe_ring *tx_ring, 1332 int cpu) 1333 { 1334 struct ixgbe_hw *hw = &adapter->hw; 1335 u32 txctrl = 0; 1336 u16 reg_offset; 1337 1338 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1339 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1340 1341 switch (hw->mac.type) { 1342 case ixgbe_mac_82598EB: 1343 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1344 break; 1345 case ixgbe_mac_82599EB: 1346 case ixgbe_mac_X540: 1347 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1348 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1349 break; 1350 default: 1351 /* for unknown hardware do not write register */ 1352 return; 1353 } 1354 1355 /* 1356 * We can enable relaxed ordering for reads, but not writes when 1357 * DCA is enabled. This is due to a known issue in some chipsets 1358 * which will cause the DCA tag to be cleared. 1359 */ 1360 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1361 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1362 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1363 1364 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1365 } 1366 1367 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1368 struct ixgbe_ring *rx_ring, 1369 int cpu) 1370 { 1371 struct ixgbe_hw *hw = &adapter->hw; 1372 u32 rxctrl = 0; 1373 u8 reg_idx = rx_ring->reg_idx; 1374 1375 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1376 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1377 1378 switch (hw->mac.type) { 1379 case ixgbe_mac_82599EB: 1380 case ixgbe_mac_X540: 1381 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1382 break; 1383 default: 1384 break; 1385 } 1386 1387 /* 1388 * We can enable relaxed ordering for reads, but not writes when 1389 * DCA is enabled. This is due to a known issue in some chipsets 1390 * which will cause the DCA tag to be cleared. 1391 */ 1392 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1393 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1394 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1395 1396 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1397 } 1398 1399 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1400 { 1401 struct ixgbe_adapter *adapter = q_vector->adapter; 1402 struct ixgbe_ring *ring; 1403 int cpu = get_cpu(); 1404 1405 if (q_vector->cpu == cpu) 1406 goto out_no_update; 1407 1408 ixgbe_for_each_ring(ring, q_vector->tx) 1409 ixgbe_update_tx_dca(adapter, ring, cpu); 1410 1411 ixgbe_for_each_ring(ring, q_vector->rx) 1412 ixgbe_update_rx_dca(adapter, ring, cpu); 1413 1414 q_vector->cpu = cpu; 1415 out_no_update: 1416 put_cpu(); 1417 } 1418 1419 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1420 { 1421 int i; 1422 1423 /* always use CB2 mode, difference is masked in the CB driver */ 1424 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1426 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1427 else 1428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1429 IXGBE_DCA_CTRL_DCA_DISABLE); 1430 1431 for (i = 0; i < adapter->num_q_vectors; i++) { 1432 adapter->q_vector[i]->cpu = -1; 1433 ixgbe_update_dca(adapter->q_vector[i]); 1434 } 1435 } 1436 1437 static int __ixgbe_notify_dca(struct device *dev, void *data) 1438 { 1439 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1440 unsigned long event = *(unsigned long *)data; 1441 1442 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1443 return 0; 1444 1445 switch (event) { 1446 case DCA_PROVIDER_ADD: 1447 /* if we're already enabled, don't do it again */ 1448 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1449 break; 1450 if (dca_add_requester(dev) == 0) { 1451 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1452 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1453 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1454 break; 1455 } 1456 /* fall through - DCA is disabled. */ 1457 case DCA_PROVIDER_REMOVE: 1458 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1459 dca_remove_requester(dev); 1460 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1462 IXGBE_DCA_CTRL_DCA_DISABLE); 1463 } 1464 break; 1465 } 1466 1467 return 0; 1468 } 1469 1470 #endif /* CONFIG_IXGBE_DCA */ 1471 1472 #define IXGBE_RSS_L4_TYPES_MASK \ 1473 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1474 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1475 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1476 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1477 1478 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1479 union ixgbe_adv_rx_desc *rx_desc, 1480 struct sk_buff *skb) 1481 { 1482 u16 rss_type; 1483 1484 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1485 return; 1486 1487 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1488 IXGBE_RXDADV_RSSTYPE_MASK; 1489 1490 if (!rss_type) 1491 return; 1492 1493 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1494 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1495 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1496 } 1497 1498 #ifdef IXGBE_FCOE 1499 /** 1500 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1501 * @ring: structure containing ring specific data 1502 * @rx_desc: advanced rx descriptor 1503 * 1504 * Returns : true if it is FCoE pkt 1505 */ 1506 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1507 union ixgbe_adv_rx_desc *rx_desc) 1508 { 1509 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1510 1511 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1512 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1513 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1514 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1515 } 1516 1517 #endif /* IXGBE_FCOE */ 1518 /** 1519 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1520 * @ring: structure containing ring specific data 1521 * @rx_desc: current Rx descriptor being processed 1522 * @skb: skb currently being received and modified 1523 **/ 1524 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1525 union ixgbe_adv_rx_desc *rx_desc, 1526 struct sk_buff *skb) 1527 { 1528 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1529 bool encap_pkt = false; 1530 1531 skb_checksum_none_assert(skb); 1532 1533 /* Rx csum disabled */ 1534 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1535 return; 1536 1537 /* check for VXLAN and Geneve packets */ 1538 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1539 encap_pkt = true; 1540 skb->encapsulation = 1; 1541 } 1542 1543 /* if IP and error */ 1544 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1545 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1546 ring->rx_stats.csum_err++; 1547 return; 1548 } 1549 1550 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1551 return; 1552 1553 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1554 /* 1555 * 82599 errata, UDP frames with a 0 checksum can be marked as 1556 * checksum errors. 1557 */ 1558 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1559 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1560 return; 1561 1562 ring->rx_stats.csum_err++; 1563 return; 1564 } 1565 1566 /* It must be a TCP or UDP packet with a valid checksum */ 1567 skb->ip_summed = CHECKSUM_UNNECESSARY; 1568 if (encap_pkt) { 1569 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1570 return; 1571 1572 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1573 skb->ip_summed = CHECKSUM_NONE; 1574 return; 1575 } 1576 /* If we checked the outer header let the stack know */ 1577 skb->csum_level = 1; 1578 } 1579 } 1580 1581 static inline unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1582 { 1583 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1584 } 1585 1586 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1587 struct ixgbe_rx_buffer *bi) 1588 { 1589 struct page *page = bi->page; 1590 dma_addr_t dma; 1591 1592 /* since we are recycling buffers we should seldom need to alloc */ 1593 if (likely(page)) 1594 return true; 1595 1596 /* alloc new page for storage */ 1597 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1598 if (unlikely(!page)) { 1599 rx_ring->rx_stats.alloc_rx_page_failed++; 1600 return false; 1601 } 1602 1603 /* map page for use */ 1604 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1605 ixgbe_rx_pg_size(rx_ring), 1606 DMA_FROM_DEVICE, 1607 IXGBE_RX_DMA_ATTR); 1608 1609 /* 1610 * if mapping failed free memory back to system since 1611 * there isn't much point in holding memory we can't use 1612 */ 1613 if (dma_mapping_error(rx_ring->dev, dma)) { 1614 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1615 1616 rx_ring->rx_stats.alloc_rx_page_failed++; 1617 return false; 1618 } 1619 1620 bi->dma = dma; 1621 bi->page = page; 1622 bi->page_offset = ixgbe_rx_offset(rx_ring); 1623 bi->pagecnt_bias = 1; 1624 rx_ring->rx_stats.alloc_rx_page++; 1625 1626 return true; 1627 } 1628 1629 /** 1630 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1631 * @rx_ring: ring to place buffers on 1632 * @cleaned_count: number of buffers to replace 1633 **/ 1634 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1635 { 1636 union ixgbe_adv_rx_desc *rx_desc; 1637 struct ixgbe_rx_buffer *bi; 1638 u16 i = rx_ring->next_to_use; 1639 u16 bufsz; 1640 1641 /* nothing to do */ 1642 if (!cleaned_count) 1643 return; 1644 1645 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1646 bi = &rx_ring->rx_buffer_info[i]; 1647 i -= rx_ring->count; 1648 1649 bufsz = ixgbe_rx_bufsz(rx_ring); 1650 1651 do { 1652 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1653 break; 1654 1655 /* sync the buffer for use by the device */ 1656 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1657 bi->page_offset, bufsz, 1658 DMA_FROM_DEVICE); 1659 1660 /* 1661 * Refresh the desc even if buffer_addrs didn't change 1662 * because each write-back erases this info. 1663 */ 1664 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1665 1666 rx_desc++; 1667 bi++; 1668 i++; 1669 if (unlikely(!i)) { 1670 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1671 bi = rx_ring->rx_buffer_info; 1672 i -= rx_ring->count; 1673 } 1674 1675 /* clear the length for the next_to_use descriptor */ 1676 rx_desc->wb.upper.length = 0; 1677 1678 cleaned_count--; 1679 } while (cleaned_count); 1680 1681 i += rx_ring->count; 1682 1683 if (rx_ring->next_to_use != i) { 1684 rx_ring->next_to_use = i; 1685 1686 /* update next to alloc since we have filled the ring */ 1687 rx_ring->next_to_alloc = i; 1688 1689 /* Force memory writes to complete before letting h/w 1690 * know there are new descriptors to fetch. (Only 1691 * applicable for weak-ordered memory model archs, 1692 * such as IA-64). 1693 */ 1694 wmb(); 1695 writel(i, rx_ring->tail); 1696 } 1697 } 1698 1699 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1700 struct sk_buff *skb) 1701 { 1702 u16 hdr_len = skb_headlen(skb); 1703 1704 /* set gso_size to avoid messing up TCP MSS */ 1705 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1706 IXGBE_CB(skb)->append_cnt); 1707 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1708 } 1709 1710 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1711 struct sk_buff *skb) 1712 { 1713 /* if append_cnt is 0 then frame is not RSC */ 1714 if (!IXGBE_CB(skb)->append_cnt) 1715 return; 1716 1717 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1718 rx_ring->rx_stats.rsc_flush++; 1719 1720 ixgbe_set_rsc_gso_size(rx_ring, skb); 1721 1722 /* gso_size is computed using append_cnt so always clear it last */ 1723 IXGBE_CB(skb)->append_cnt = 0; 1724 } 1725 1726 /** 1727 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1728 * @rx_ring: rx descriptor ring packet is being transacted on 1729 * @rx_desc: pointer to the EOP Rx descriptor 1730 * @skb: pointer to current skb being populated 1731 * 1732 * This function checks the ring, descriptor, and packet information in 1733 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1734 * other fields within the skb. 1735 **/ 1736 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1737 union ixgbe_adv_rx_desc *rx_desc, 1738 struct sk_buff *skb) 1739 { 1740 struct net_device *dev = rx_ring->netdev; 1741 u32 flags = rx_ring->q_vector->adapter->flags; 1742 1743 ixgbe_update_rsc_stats(rx_ring, skb); 1744 1745 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1746 1747 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1748 1749 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1750 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1751 1752 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1753 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1754 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1755 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1756 } 1757 1758 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1759 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1760 1761 skb->protocol = eth_type_trans(skb, dev); 1762 1763 /* record Rx queue, or update MACVLAN statistics */ 1764 if (netif_is_ixgbe(dev)) 1765 skb_record_rx_queue(skb, rx_ring->queue_index); 1766 else 1767 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1768 (skb->pkt_type == PACKET_BROADCAST) || 1769 (skb->pkt_type == PACKET_MULTICAST)); 1770 } 1771 1772 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1773 struct sk_buff *skb) 1774 { 1775 napi_gro_receive(&q_vector->napi, skb); 1776 } 1777 1778 /** 1779 * ixgbe_is_non_eop - process handling of non-EOP buffers 1780 * @rx_ring: Rx ring being processed 1781 * @rx_desc: Rx descriptor for current buffer 1782 * @skb: Current socket buffer containing buffer in progress 1783 * 1784 * This function updates next to clean. If the buffer is an EOP buffer 1785 * this function exits returning false, otherwise it will place the 1786 * sk_buff in the next buffer to be chained and return true indicating 1787 * that this is in fact a non-EOP buffer. 1788 **/ 1789 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1790 union ixgbe_adv_rx_desc *rx_desc, 1791 struct sk_buff *skb) 1792 { 1793 u32 ntc = rx_ring->next_to_clean + 1; 1794 1795 /* fetch, update, and store next to clean */ 1796 ntc = (ntc < rx_ring->count) ? ntc : 0; 1797 rx_ring->next_to_clean = ntc; 1798 1799 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1800 1801 /* update RSC append count if present */ 1802 if (ring_is_rsc_enabled(rx_ring)) { 1803 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1804 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1805 1806 if (unlikely(rsc_enabled)) { 1807 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1808 1809 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1810 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1811 1812 /* update ntc based on RSC value */ 1813 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1814 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1815 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1816 } 1817 } 1818 1819 /* if we are the last buffer then there is nothing else to do */ 1820 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1821 return false; 1822 1823 /* place skb in next buffer to be received */ 1824 rx_ring->rx_buffer_info[ntc].skb = skb; 1825 rx_ring->rx_stats.non_eop_descs++; 1826 1827 return true; 1828 } 1829 1830 /** 1831 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1832 * @rx_ring: rx descriptor ring packet is being transacted on 1833 * @skb: pointer to current skb being adjusted 1834 * 1835 * This function is an ixgbe specific version of __pskb_pull_tail. The 1836 * main difference between this version and the original function is that 1837 * this function can make several assumptions about the state of things 1838 * that allow for significant optimizations versus the standard function. 1839 * As a result we can do things like drop a frag and maintain an accurate 1840 * truesize for the skb. 1841 */ 1842 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1843 struct sk_buff *skb) 1844 { 1845 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1846 unsigned char *va; 1847 unsigned int pull_len; 1848 1849 /* 1850 * it is valid to use page_address instead of kmap since we are 1851 * working with pages allocated out of the lomem pool per 1852 * alloc_page(GFP_ATOMIC) 1853 */ 1854 va = skb_frag_address(frag); 1855 1856 /* 1857 * we need the header to contain the greater of either ETH_HLEN or 1858 * 60 bytes if the skb->len is less than 60 for skb_pad. 1859 */ 1860 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); 1861 1862 /* align pull length to size of long to optimize memcpy performance */ 1863 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1864 1865 /* update all of the pointers */ 1866 skb_frag_size_sub(frag, pull_len); 1867 frag->page_offset += pull_len; 1868 skb->data_len -= pull_len; 1869 skb->tail += pull_len; 1870 } 1871 1872 /** 1873 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1874 * @rx_ring: rx descriptor ring packet is being transacted on 1875 * @skb: pointer to current skb being updated 1876 * 1877 * This function provides a basic DMA sync up for the first fragment of an 1878 * skb. The reason for doing this is that the first fragment cannot be 1879 * unmapped until we have reached the end of packet descriptor for a buffer 1880 * chain. 1881 */ 1882 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1883 struct sk_buff *skb) 1884 { 1885 /* if the page was released unmap it, else just sync our portion */ 1886 if (unlikely(IXGBE_CB(skb)->page_released)) { 1887 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1888 ixgbe_rx_pg_size(rx_ring), 1889 DMA_FROM_DEVICE, 1890 IXGBE_RX_DMA_ATTR); 1891 } else { 1892 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1893 1894 dma_sync_single_range_for_cpu(rx_ring->dev, 1895 IXGBE_CB(skb)->dma, 1896 frag->page_offset, 1897 skb_frag_size(frag), 1898 DMA_FROM_DEVICE); 1899 } 1900 } 1901 1902 /** 1903 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1904 * @rx_ring: rx descriptor ring packet is being transacted on 1905 * @rx_desc: pointer to the EOP Rx descriptor 1906 * @skb: pointer to current skb being fixed 1907 * 1908 * Check if the skb is valid in the XDP case it will be an error pointer. 1909 * Return true in this case to abort processing and advance to next 1910 * descriptor. 1911 * 1912 * Check for corrupted packet headers caused by senders on the local L2 1913 * embedded NIC switch not setting up their Tx Descriptors right. These 1914 * should be very rare. 1915 * 1916 * Also address the case where we are pulling data in on pages only 1917 * and as such no data is present in the skb header. 1918 * 1919 * In addition if skb is not at least 60 bytes we need to pad it so that 1920 * it is large enough to qualify as a valid Ethernet frame. 1921 * 1922 * Returns true if an error was encountered and skb was freed. 1923 **/ 1924 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1925 union ixgbe_adv_rx_desc *rx_desc, 1926 struct sk_buff *skb) 1927 { 1928 struct net_device *netdev = rx_ring->netdev; 1929 1930 /* XDP packets use error pointer so abort at this point */ 1931 if (IS_ERR(skb)) 1932 return true; 1933 1934 /* Verify netdev is present, and that packet does not have any 1935 * errors that would be unacceptable to the netdev. 1936 */ 1937 if (!netdev || 1938 (unlikely(ixgbe_test_staterr(rx_desc, 1939 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1940 !(netdev->features & NETIF_F_RXALL)))) { 1941 dev_kfree_skb_any(skb); 1942 return true; 1943 } 1944 1945 /* place header in linear portion of buffer */ 1946 if (!skb_headlen(skb)) 1947 ixgbe_pull_tail(rx_ring, skb); 1948 1949 #ifdef IXGBE_FCOE 1950 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1951 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1952 return false; 1953 1954 #endif 1955 /* if eth_skb_pad returns an error the skb was freed */ 1956 if (eth_skb_pad(skb)) 1957 return true; 1958 1959 return false; 1960 } 1961 1962 /** 1963 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1964 * @rx_ring: rx descriptor ring to store buffers on 1965 * @old_buff: donor buffer to have page reused 1966 * 1967 * Synchronizes page for reuse by the adapter 1968 **/ 1969 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1970 struct ixgbe_rx_buffer *old_buff) 1971 { 1972 struct ixgbe_rx_buffer *new_buff; 1973 u16 nta = rx_ring->next_to_alloc; 1974 1975 new_buff = &rx_ring->rx_buffer_info[nta]; 1976 1977 /* update, and store next to alloc */ 1978 nta++; 1979 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1980 1981 /* Transfer page from old buffer to new buffer. 1982 * Move each member individually to avoid possible store 1983 * forwarding stalls and unnecessary copy of skb. 1984 */ 1985 new_buff->dma = old_buff->dma; 1986 new_buff->page = old_buff->page; 1987 new_buff->page_offset = old_buff->page_offset; 1988 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1989 } 1990 1991 static inline bool ixgbe_page_is_reserved(struct page *page) 1992 { 1993 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1994 } 1995 1996 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer) 1997 { 1998 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1999 struct page *page = rx_buffer->page; 2000 2001 /* avoid re-using remote pages */ 2002 if (unlikely(ixgbe_page_is_reserved(page))) 2003 return false; 2004 2005 #if (PAGE_SIZE < 8192) 2006 /* if we are only owner of page we can reuse it */ 2007 if (unlikely((page_ref_count(page) - pagecnt_bias) > 1)) 2008 return false; 2009 #else 2010 /* The last offset is a bit aggressive in that we assume the 2011 * worst case of FCoE being enabled and using a 3K buffer. 2012 * However this should have minimal impact as the 1K extra is 2013 * still less than one buffer in size. 2014 */ 2015 #define IXGBE_LAST_OFFSET \ 2016 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2017 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2018 return false; 2019 #endif 2020 2021 /* If we have drained the page fragment pool we need to update 2022 * the pagecnt_bias and page count so that we fully restock the 2023 * number of references the driver holds. 2024 */ 2025 if (unlikely(!pagecnt_bias)) { 2026 page_ref_add(page, USHRT_MAX); 2027 rx_buffer->pagecnt_bias = USHRT_MAX; 2028 } 2029 2030 return true; 2031 } 2032 2033 /** 2034 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2035 * @rx_ring: rx descriptor ring to transact packets on 2036 * @rx_buffer: buffer containing page to add 2037 * @skb: sk_buff to place the data into 2038 * @size: size of data in rx_buffer 2039 * 2040 * This function will add the data contained in rx_buffer->page to the skb. 2041 * This is done either through a direct copy if the data in the buffer is 2042 * less than the skb header size, otherwise it will just attach the page as 2043 * a frag to the skb. 2044 * 2045 * The function will then update the page offset if necessary and return 2046 * true if the buffer can be reused by the adapter. 2047 **/ 2048 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2049 struct ixgbe_rx_buffer *rx_buffer, 2050 struct sk_buff *skb, 2051 unsigned int size) 2052 { 2053 #if (PAGE_SIZE < 8192) 2054 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2055 #else 2056 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2057 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2058 SKB_DATA_ALIGN(size); 2059 #endif 2060 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2061 rx_buffer->page_offset, size, truesize); 2062 #if (PAGE_SIZE < 8192) 2063 rx_buffer->page_offset ^= truesize; 2064 #else 2065 rx_buffer->page_offset += truesize; 2066 #endif 2067 } 2068 2069 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2070 union ixgbe_adv_rx_desc *rx_desc, 2071 struct sk_buff **skb, 2072 const unsigned int size) 2073 { 2074 struct ixgbe_rx_buffer *rx_buffer; 2075 2076 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2077 prefetchw(rx_buffer->page); 2078 *skb = rx_buffer->skb; 2079 2080 /* Delay unmapping of the first packet. It carries the header 2081 * information, HW may still access the header after the writeback. 2082 * Only unmap it when EOP is reached 2083 */ 2084 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2085 if (!*skb) 2086 goto skip_sync; 2087 } else { 2088 if (*skb) 2089 ixgbe_dma_sync_frag(rx_ring, *skb); 2090 } 2091 2092 /* we are reusing so sync this buffer for CPU use */ 2093 dma_sync_single_range_for_cpu(rx_ring->dev, 2094 rx_buffer->dma, 2095 rx_buffer->page_offset, 2096 size, 2097 DMA_FROM_DEVICE); 2098 skip_sync: 2099 rx_buffer->pagecnt_bias--; 2100 2101 return rx_buffer; 2102 } 2103 2104 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2105 struct ixgbe_rx_buffer *rx_buffer, 2106 struct sk_buff *skb) 2107 { 2108 if (ixgbe_can_reuse_rx_page(rx_buffer)) { 2109 /* hand second half of page back to the ring */ 2110 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2111 } else { 2112 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2113 /* the page has been released from the ring */ 2114 IXGBE_CB(skb)->page_released = true; 2115 } else { 2116 /* we are not reusing the buffer so unmap it */ 2117 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2118 ixgbe_rx_pg_size(rx_ring), 2119 DMA_FROM_DEVICE, 2120 IXGBE_RX_DMA_ATTR); 2121 } 2122 __page_frag_cache_drain(rx_buffer->page, 2123 rx_buffer->pagecnt_bias); 2124 } 2125 2126 /* clear contents of rx_buffer */ 2127 rx_buffer->page = NULL; 2128 rx_buffer->skb = NULL; 2129 } 2130 2131 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2132 struct ixgbe_rx_buffer *rx_buffer, 2133 struct xdp_buff *xdp, 2134 union ixgbe_adv_rx_desc *rx_desc) 2135 { 2136 unsigned int size = xdp->data_end - xdp->data; 2137 #if (PAGE_SIZE < 8192) 2138 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2139 #else 2140 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2141 xdp->data_hard_start); 2142 #endif 2143 struct sk_buff *skb; 2144 2145 /* prefetch first cache line of first page */ 2146 prefetch(xdp->data); 2147 #if L1_CACHE_BYTES < 128 2148 prefetch(xdp->data + L1_CACHE_BYTES); 2149 #endif 2150 /* Note, we get here by enabling legacy-rx via: 2151 * 2152 * ethtool --set-priv-flags <dev> legacy-rx on 2153 * 2154 * In this mode, we currently get 0 extra XDP headroom as 2155 * opposed to having legacy-rx off, where we process XDP 2156 * packets going to stack via ixgbe_build_skb(). The latter 2157 * provides us currently with 192 bytes of headroom. 2158 * 2159 * For ixgbe_construct_skb() mode it means that the 2160 * xdp->data_meta will always point to xdp->data, since 2161 * the helper cannot expand the head. Should this ever 2162 * change in future for legacy-rx mode on, then lets also 2163 * add xdp->data_meta handling here. 2164 */ 2165 2166 /* allocate a skb to store the frags */ 2167 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2168 if (unlikely(!skb)) 2169 return NULL; 2170 2171 if (size > IXGBE_RX_HDR_SIZE) { 2172 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2173 IXGBE_CB(skb)->dma = rx_buffer->dma; 2174 2175 skb_add_rx_frag(skb, 0, rx_buffer->page, 2176 xdp->data - page_address(rx_buffer->page), 2177 size, truesize); 2178 #if (PAGE_SIZE < 8192) 2179 rx_buffer->page_offset ^= truesize; 2180 #else 2181 rx_buffer->page_offset += truesize; 2182 #endif 2183 } else { 2184 memcpy(__skb_put(skb, size), 2185 xdp->data, ALIGN(size, sizeof(long))); 2186 rx_buffer->pagecnt_bias++; 2187 } 2188 2189 return skb; 2190 } 2191 2192 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2193 struct ixgbe_rx_buffer *rx_buffer, 2194 struct xdp_buff *xdp, 2195 union ixgbe_adv_rx_desc *rx_desc) 2196 { 2197 unsigned int metasize = xdp->data - xdp->data_meta; 2198 #if (PAGE_SIZE < 8192) 2199 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2200 #else 2201 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2202 SKB_DATA_ALIGN(xdp->data_end - 2203 xdp->data_hard_start); 2204 #endif 2205 struct sk_buff *skb; 2206 2207 /* Prefetch first cache line of first page. If xdp->data_meta 2208 * is unused, this points extactly as xdp->data, otherwise we 2209 * likely have a consumer accessing first few bytes of meta 2210 * data, and then actual data. 2211 */ 2212 prefetch(xdp->data_meta); 2213 #if L1_CACHE_BYTES < 128 2214 prefetch(xdp->data_meta + L1_CACHE_BYTES); 2215 #endif 2216 2217 /* build an skb to around the page buffer */ 2218 skb = build_skb(xdp->data_hard_start, truesize); 2219 if (unlikely(!skb)) 2220 return NULL; 2221 2222 /* update pointers within the skb to store the data */ 2223 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2224 __skb_put(skb, xdp->data_end - xdp->data); 2225 if (metasize) 2226 skb_metadata_set(skb, metasize); 2227 2228 /* record DMA address if this is the start of a chain of buffers */ 2229 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2230 IXGBE_CB(skb)->dma = rx_buffer->dma; 2231 2232 /* update buffer offset */ 2233 #if (PAGE_SIZE < 8192) 2234 rx_buffer->page_offset ^= truesize; 2235 #else 2236 rx_buffer->page_offset += truesize; 2237 #endif 2238 2239 return skb; 2240 } 2241 2242 #define IXGBE_XDP_PASS 0 2243 #define IXGBE_XDP_CONSUMED 1 2244 #define IXGBE_XDP_TX 2 2245 2246 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 2247 struct xdp_buff *xdp); 2248 2249 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2250 struct ixgbe_ring *rx_ring, 2251 struct xdp_buff *xdp) 2252 { 2253 int err, result = IXGBE_XDP_PASS; 2254 struct bpf_prog *xdp_prog; 2255 u32 act; 2256 2257 rcu_read_lock(); 2258 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2259 2260 if (!xdp_prog) 2261 goto xdp_out; 2262 2263 act = bpf_prog_run_xdp(xdp_prog, xdp); 2264 switch (act) { 2265 case XDP_PASS: 2266 break; 2267 case XDP_TX: 2268 result = ixgbe_xmit_xdp_ring(adapter, xdp); 2269 break; 2270 case XDP_REDIRECT: 2271 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2272 if (!err) 2273 result = IXGBE_XDP_TX; 2274 else 2275 result = IXGBE_XDP_CONSUMED; 2276 break; 2277 default: 2278 bpf_warn_invalid_xdp_action(act); 2279 /* fallthrough */ 2280 case XDP_ABORTED: 2281 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2282 /* fallthrough -- handle aborts by dropping packet */ 2283 case XDP_DROP: 2284 result = IXGBE_XDP_CONSUMED; 2285 break; 2286 } 2287 xdp_out: 2288 rcu_read_unlock(); 2289 return ERR_PTR(-result); 2290 } 2291 2292 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2293 struct ixgbe_rx_buffer *rx_buffer, 2294 unsigned int size) 2295 { 2296 #if (PAGE_SIZE < 8192) 2297 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2298 2299 rx_buffer->page_offset ^= truesize; 2300 #else 2301 unsigned int truesize = ring_uses_build_skb(rx_ring) ? 2302 SKB_DATA_ALIGN(IXGBE_SKB_PAD + size) : 2303 SKB_DATA_ALIGN(size); 2304 2305 rx_buffer->page_offset += truesize; 2306 #endif 2307 } 2308 2309 /** 2310 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2311 * @q_vector: structure containing interrupt and ring information 2312 * @rx_ring: rx descriptor ring to transact packets on 2313 * @budget: Total limit on number of packets to process 2314 * 2315 * This function provides a "bounce buffer" approach to Rx interrupt 2316 * processing. The advantage to this is that on systems that have 2317 * expensive overhead for IOMMU access this provides a means of avoiding 2318 * it by maintaining the mapping of the page to the syste. 2319 * 2320 * Returns amount of work completed 2321 **/ 2322 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2323 struct ixgbe_ring *rx_ring, 2324 const int budget) 2325 { 2326 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 2327 struct ixgbe_adapter *adapter = q_vector->adapter; 2328 #ifdef IXGBE_FCOE 2329 int ddp_bytes; 2330 unsigned int mss = 0; 2331 #endif /* IXGBE_FCOE */ 2332 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2333 bool xdp_xmit = false; 2334 struct xdp_buff xdp; 2335 2336 xdp.rxq = &rx_ring->xdp_rxq; 2337 2338 while (likely(total_rx_packets < budget)) { 2339 union ixgbe_adv_rx_desc *rx_desc; 2340 struct ixgbe_rx_buffer *rx_buffer; 2341 struct sk_buff *skb; 2342 unsigned int size; 2343 2344 /* return some buffers to hardware, one at a time is too slow */ 2345 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2346 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2347 cleaned_count = 0; 2348 } 2349 2350 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2351 size = le16_to_cpu(rx_desc->wb.upper.length); 2352 if (!size) 2353 break; 2354 2355 /* This memory barrier is needed to keep us from reading 2356 * any other fields out of the rx_desc until we know the 2357 * descriptor has been written back 2358 */ 2359 dma_rmb(); 2360 2361 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size); 2362 2363 /* retrieve a buffer from the ring */ 2364 if (!skb) { 2365 xdp.data = page_address(rx_buffer->page) + 2366 rx_buffer->page_offset; 2367 xdp.data_meta = xdp.data; 2368 xdp.data_hard_start = xdp.data - 2369 ixgbe_rx_offset(rx_ring); 2370 xdp.data_end = xdp.data + size; 2371 2372 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2373 } 2374 2375 if (IS_ERR(skb)) { 2376 if (PTR_ERR(skb) == -IXGBE_XDP_TX) { 2377 xdp_xmit = true; 2378 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2379 } else { 2380 rx_buffer->pagecnt_bias++; 2381 } 2382 total_rx_packets++; 2383 total_rx_bytes += size; 2384 } else if (skb) { 2385 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2386 } else if (ring_uses_build_skb(rx_ring)) { 2387 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2388 &xdp, rx_desc); 2389 } else { 2390 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2391 &xdp, rx_desc); 2392 } 2393 2394 /* exit if we failed to retrieve a buffer */ 2395 if (!skb) { 2396 rx_ring->rx_stats.alloc_rx_buff_failed++; 2397 rx_buffer->pagecnt_bias++; 2398 break; 2399 } 2400 2401 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb); 2402 cleaned_count++; 2403 2404 /* place incomplete frames back on ring for completion */ 2405 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2406 continue; 2407 2408 /* verify the packet layout is correct */ 2409 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2410 continue; 2411 2412 /* probably a little skewed due to removing CRC */ 2413 total_rx_bytes += skb->len; 2414 2415 /* populate checksum, timestamp, VLAN, and protocol */ 2416 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2417 2418 #ifdef IXGBE_FCOE 2419 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2420 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2421 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2422 /* include DDPed FCoE data */ 2423 if (ddp_bytes > 0) { 2424 if (!mss) { 2425 mss = rx_ring->netdev->mtu - 2426 sizeof(struct fcoe_hdr) - 2427 sizeof(struct fc_frame_header) - 2428 sizeof(struct fcoe_crc_eof); 2429 if (mss > 512) 2430 mss &= ~511; 2431 } 2432 total_rx_bytes += ddp_bytes; 2433 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2434 mss); 2435 } 2436 if (!ddp_bytes) { 2437 dev_kfree_skb_any(skb); 2438 continue; 2439 } 2440 } 2441 2442 #endif /* IXGBE_FCOE */ 2443 ixgbe_rx_skb(q_vector, skb); 2444 2445 /* update budget accounting */ 2446 total_rx_packets++; 2447 } 2448 2449 if (xdp_xmit) { 2450 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 2451 2452 /* Force memory writes to complete before letting h/w 2453 * know there are new descriptors to fetch. 2454 */ 2455 wmb(); 2456 writel(ring->next_to_use, ring->tail); 2457 2458 xdp_do_flush_map(); 2459 } 2460 2461 u64_stats_update_begin(&rx_ring->syncp); 2462 rx_ring->stats.packets += total_rx_packets; 2463 rx_ring->stats.bytes += total_rx_bytes; 2464 u64_stats_update_end(&rx_ring->syncp); 2465 q_vector->rx.total_packets += total_rx_packets; 2466 q_vector->rx.total_bytes += total_rx_bytes; 2467 2468 return total_rx_packets; 2469 } 2470 2471 /** 2472 * ixgbe_configure_msix - Configure MSI-X hardware 2473 * @adapter: board private structure 2474 * 2475 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2476 * interrupts. 2477 **/ 2478 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2479 { 2480 struct ixgbe_q_vector *q_vector; 2481 int v_idx; 2482 u32 mask; 2483 2484 /* Populate MSIX to EITR Select */ 2485 if (adapter->num_vfs > 32) { 2486 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2488 } 2489 2490 /* 2491 * Populate the IVAR table and set the ITR values to the 2492 * corresponding register. 2493 */ 2494 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2495 struct ixgbe_ring *ring; 2496 q_vector = adapter->q_vector[v_idx]; 2497 2498 ixgbe_for_each_ring(ring, q_vector->rx) 2499 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2500 2501 ixgbe_for_each_ring(ring, q_vector->tx) 2502 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2503 2504 ixgbe_write_eitr(q_vector); 2505 } 2506 2507 switch (adapter->hw.mac.type) { 2508 case ixgbe_mac_82598EB: 2509 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2510 v_idx); 2511 break; 2512 case ixgbe_mac_82599EB: 2513 case ixgbe_mac_X540: 2514 case ixgbe_mac_X550: 2515 case ixgbe_mac_X550EM_x: 2516 case ixgbe_mac_x550em_a: 2517 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2518 break; 2519 default: 2520 break; 2521 } 2522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2523 2524 /* set up to autoclear timer, and the vectors */ 2525 mask = IXGBE_EIMS_ENABLE_MASK; 2526 mask &= ~(IXGBE_EIMS_OTHER | 2527 IXGBE_EIMS_MAILBOX | 2528 IXGBE_EIMS_LSC); 2529 2530 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2531 } 2532 2533 /** 2534 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2535 * @q_vector: structure containing interrupt and ring information 2536 * @ring_container: structure containing ring performance data 2537 * 2538 * Stores a new ITR value based on packets and byte 2539 * counts during the last interrupt. The advantage of per interrupt 2540 * computation is faster updates and more accurate ITR for the current 2541 * traffic pattern. Constants in this function were computed 2542 * based on theoretical maximum wire speed and thresholds were set based 2543 * on testing data as well as attempting to minimize response time 2544 * while increasing bulk throughput. 2545 **/ 2546 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2547 struct ixgbe_ring_container *ring_container) 2548 { 2549 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2550 IXGBE_ITR_ADAPTIVE_LATENCY; 2551 unsigned int avg_wire_size, packets, bytes; 2552 unsigned long next_update = jiffies; 2553 2554 /* If we don't have any rings just leave ourselves set for maximum 2555 * possible latency so we take ourselves out of the equation. 2556 */ 2557 if (!ring_container->ring) 2558 return; 2559 2560 /* If we didn't update within up to 1 - 2 jiffies we can assume 2561 * that either packets are coming in so slow there hasn't been 2562 * any work, or that there is so much work that NAPI is dealing 2563 * with interrupt moderation and we don't need to do anything. 2564 */ 2565 if (time_after(next_update, ring_container->next_update)) 2566 goto clear_counts; 2567 2568 packets = ring_container->total_packets; 2569 2570 /* We have no packets to actually measure against. This means 2571 * either one of the other queues on this vector is active or 2572 * we are a Tx queue doing TSO with too high of an interrupt rate. 2573 * 2574 * When this occurs just tick up our delay by the minimum value 2575 * and hope that this extra delay will prevent us from being called 2576 * without any work on our queue. 2577 */ 2578 if (!packets) { 2579 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2580 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2581 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2582 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2583 goto clear_counts; 2584 } 2585 2586 bytes = ring_container->total_bytes; 2587 2588 /* If packets are less than 4 or bytes are less than 9000 assume 2589 * insufficient data to use bulk rate limiting approach. We are 2590 * likely latency driven. 2591 */ 2592 if (packets < 4 && bytes < 9000) { 2593 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2594 goto adjust_by_size; 2595 } 2596 2597 /* Between 4 and 48 we can assume that our current interrupt delay 2598 * is only slightly too low. As such we should increase it by a small 2599 * fixed amount. 2600 */ 2601 if (packets < 48) { 2602 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2603 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2604 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2605 goto clear_counts; 2606 } 2607 2608 /* Between 48 and 96 is our "goldilocks" zone where we are working 2609 * out "just right". Just report that our current ITR is good for us. 2610 */ 2611 if (packets < 96) { 2612 itr = q_vector->itr >> 2; 2613 goto clear_counts; 2614 } 2615 2616 /* If packet count is 96 or greater we are likely looking at a slight 2617 * overrun of the delay we want. Try halving our delay to see if that 2618 * will cut the number of packets in half per interrupt. 2619 */ 2620 if (packets < 256) { 2621 itr = q_vector->itr >> 3; 2622 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2623 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2624 goto clear_counts; 2625 } 2626 2627 /* The paths below assume we are dealing with a bulk ITR since number 2628 * of packets is 256 or greater. We are just going to have to compute 2629 * a value and try to bring the count under control, though for smaller 2630 * packet sizes there isn't much we can do as NAPI polling will likely 2631 * be kicking in sooner rather than later. 2632 */ 2633 itr = IXGBE_ITR_ADAPTIVE_BULK; 2634 2635 adjust_by_size: 2636 /* If packet counts are 256 or greater we can assume we have a gross 2637 * overestimation of what the rate should be. Instead of trying to fine 2638 * tune it just use the formula below to try and dial in an exact value 2639 * give the current packet size of the frame. 2640 */ 2641 avg_wire_size = bytes / packets; 2642 2643 /* The following is a crude approximation of: 2644 * wmem_default / (size + overhead) = desired_pkts_per_int 2645 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2646 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2647 * 2648 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2649 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2650 * formula down to 2651 * 2652 * (170 * (size + 24)) / (size + 640) = ITR 2653 * 2654 * We first do some math on the packet size and then finally bitshift 2655 * by 8 after rounding up. We also have to account for PCIe link speed 2656 * difference as ITR scales based on this. 2657 */ 2658 if (avg_wire_size <= 60) { 2659 /* Start at 50k ints/sec */ 2660 avg_wire_size = 5120; 2661 } else if (avg_wire_size <= 316) { 2662 /* 50K ints/sec to 16K ints/sec */ 2663 avg_wire_size *= 40; 2664 avg_wire_size += 2720; 2665 } else if (avg_wire_size <= 1084) { 2666 /* 16K ints/sec to 9.2K ints/sec */ 2667 avg_wire_size *= 15; 2668 avg_wire_size += 11452; 2669 } else if (avg_wire_size <= 1980) { 2670 /* 9.2K ints/sec to 8K ints/sec */ 2671 avg_wire_size *= 5; 2672 avg_wire_size += 22420; 2673 } else { 2674 /* plateau at a limit of 8K ints/sec */ 2675 avg_wire_size = 32256; 2676 } 2677 2678 /* If we are in low latency mode half our delay which doubles the rate 2679 * to somewhere between 100K to 16K ints/sec 2680 */ 2681 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2682 avg_wire_size >>= 1; 2683 2684 /* Resultant value is 256 times larger than it needs to be. This 2685 * gives us room to adjust the value as needed to either increase 2686 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2687 * 2688 * Use addition as we have already recorded the new latency flag 2689 * for the ITR value. 2690 */ 2691 switch (q_vector->adapter->link_speed) { 2692 case IXGBE_LINK_SPEED_10GB_FULL: 2693 case IXGBE_LINK_SPEED_100_FULL: 2694 default: 2695 itr += DIV_ROUND_UP(avg_wire_size, 2696 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2697 IXGBE_ITR_ADAPTIVE_MIN_INC; 2698 break; 2699 case IXGBE_LINK_SPEED_2_5GB_FULL: 2700 case IXGBE_LINK_SPEED_1GB_FULL: 2701 case IXGBE_LINK_SPEED_10_FULL: 2702 itr += DIV_ROUND_UP(avg_wire_size, 2703 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2704 IXGBE_ITR_ADAPTIVE_MIN_INC; 2705 break; 2706 } 2707 2708 clear_counts: 2709 /* write back value */ 2710 ring_container->itr = itr; 2711 2712 /* next update should occur within next jiffy */ 2713 ring_container->next_update = next_update + 1; 2714 2715 ring_container->total_bytes = 0; 2716 ring_container->total_packets = 0; 2717 } 2718 2719 /** 2720 * ixgbe_write_eitr - write EITR register in hardware specific way 2721 * @q_vector: structure containing interrupt and ring information 2722 * 2723 * This function is made to be called by ethtool and by the driver 2724 * when it needs to update EITR registers at runtime. Hardware 2725 * specific quirks/differences are taken care of here. 2726 */ 2727 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2728 { 2729 struct ixgbe_adapter *adapter = q_vector->adapter; 2730 struct ixgbe_hw *hw = &adapter->hw; 2731 int v_idx = q_vector->v_idx; 2732 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2733 2734 switch (adapter->hw.mac.type) { 2735 case ixgbe_mac_82598EB: 2736 /* must write high and low 16 bits to reset counter */ 2737 itr_reg |= (itr_reg << 16); 2738 break; 2739 case ixgbe_mac_82599EB: 2740 case ixgbe_mac_X540: 2741 case ixgbe_mac_X550: 2742 case ixgbe_mac_X550EM_x: 2743 case ixgbe_mac_x550em_a: 2744 /* 2745 * set the WDIS bit to not clear the timer bits and cause an 2746 * immediate assertion of the interrupt 2747 */ 2748 itr_reg |= IXGBE_EITR_CNT_WDIS; 2749 break; 2750 default: 2751 break; 2752 } 2753 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2754 } 2755 2756 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2757 { 2758 u32 new_itr; 2759 2760 ixgbe_update_itr(q_vector, &q_vector->tx); 2761 ixgbe_update_itr(q_vector, &q_vector->rx); 2762 2763 /* use the smallest value of new ITR delay calculations */ 2764 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2765 2766 /* Clear latency flag if set, shift into correct position */ 2767 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2768 new_itr <<= 2; 2769 2770 if (new_itr != q_vector->itr) { 2771 /* save the algorithm value here */ 2772 q_vector->itr = new_itr; 2773 2774 ixgbe_write_eitr(q_vector); 2775 } 2776 } 2777 2778 /** 2779 * ixgbe_check_overtemp_subtask - check for over temperature 2780 * @adapter: pointer to adapter 2781 **/ 2782 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2783 { 2784 struct ixgbe_hw *hw = &adapter->hw; 2785 u32 eicr = adapter->interrupt_event; 2786 s32 rc; 2787 2788 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2789 return; 2790 2791 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2792 return; 2793 2794 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2795 2796 switch (hw->device_id) { 2797 case IXGBE_DEV_ID_82599_T3_LOM: 2798 /* 2799 * Since the warning interrupt is for both ports 2800 * we don't have to check if: 2801 * - This interrupt wasn't for our port. 2802 * - We may have missed the interrupt so always have to 2803 * check if we got a LSC 2804 */ 2805 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2806 !(eicr & IXGBE_EICR_LSC)) 2807 return; 2808 2809 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2810 u32 speed; 2811 bool link_up = false; 2812 2813 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2814 2815 if (link_up) 2816 return; 2817 } 2818 2819 /* Check if this is not due to overtemp */ 2820 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) 2821 return; 2822 2823 break; 2824 case IXGBE_DEV_ID_X550EM_A_1G_T: 2825 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2826 rc = hw->phy.ops.check_overtemp(hw); 2827 if (rc != IXGBE_ERR_OVERTEMP) 2828 return; 2829 break; 2830 default: 2831 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2832 return; 2833 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2834 return; 2835 break; 2836 } 2837 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2838 2839 adapter->interrupt_event = 0; 2840 } 2841 2842 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2843 { 2844 struct ixgbe_hw *hw = &adapter->hw; 2845 2846 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2847 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2848 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2849 /* write to clear the interrupt */ 2850 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2851 } 2852 } 2853 2854 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2855 { 2856 struct ixgbe_hw *hw = &adapter->hw; 2857 2858 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2859 return; 2860 2861 switch (adapter->hw.mac.type) { 2862 case ixgbe_mac_82599EB: 2863 /* 2864 * Need to check link state so complete overtemp check 2865 * on service task 2866 */ 2867 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2868 (eicr & IXGBE_EICR_LSC)) && 2869 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2870 adapter->interrupt_event = eicr; 2871 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2872 ixgbe_service_event_schedule(adapter); 2873 return; 2874 } 2875 return; 2876 case ixgbe_mac_x550em_a: 2877 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2878 adapter->interrupt_event = eicr; 2879 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2880 ixgbe_service_event_schedule(adapter); 2881 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2882 IXGBE_EICR_GPI_SDP0_X550EM_a); 2883 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2884 IXGBE_EICR_GPI_SDP0_X550EM_a); 2885 } 2886 return; 2887 case ixgbe_mac_X550: 2888 case ixgbe_mac_X540: 2889 if (!(eicr & IXGBE_EICR_TS)) 2890 return; 2891 break; 2892 default: 2893 return; 2894 } 2895 2896 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2897 } 2898 2899 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2900 { 2901 switch (hw->mac.type) { 2902 case ixgbe_mac_82598EB: 2903 if (hw->phy.type == ixgbe_phy_nl) 2904 return true; 2905 return false; 2906 case ixgbe_mac_82599EB: 2907 case ixgbe_mac_X550EM_x: 2908 case ixgbe_mac_x550em_a: 2909 switch (hw->mac.ops.get_media_type(hw)) { 2910 case ixgbe_media_type_fiber: 2911 case ixgbe_media_type_fiber_qsfp: 2912 return true; 2913 default: 2914 return false; 2915 } 2916 default: 2917 return false; 2918 } 2919 } 2920 2921 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2922 { 2923 struct ixgbe_hw *hw = &adapter->hw; 2924 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2925 2926 if (!ixgbe_is_sfp(hw)) 2927 return; 2928 2929 /* Later MAC's use different SDP */ 2930 if (hw->mac.type >= ixgbe_mac_X540) 2931 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2932 2933 if (eicr & eicr_mask) { 2934 /* Clear the interrupt */ 2935 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2936 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2937 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2938 adapter->sfp_poll_time = 0; 2939 ixgbe_service_event_schedule(adapter); 2940 } 2941 } 2942 2943 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2944 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2945 /* Clear the interrupt */ 2946 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2947 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2948 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2949 ixgbe_service_event_schedule(adapter); 2950 } 2951 } 2952 } 2953 2954 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2955 { 2956 struct ixgbe_hw *hw = &adapter->hw; 2957 2958 adapter->lsc_int++; 2959 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2960 adapter->link_check_timeout = jiffies; 2961 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2962 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2963 IXGBE_WRITE_FLUSH(hw); 2964 ixgbe_service_event_schedule(adapter); 2965 } 2966 } 2967 2968 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2969 u64 qmask) 2970 { 2971 u32 mask; 2972 struct ixgbe_hw *hw = &adapter->hw; 2973 2974 switch (hw->mac.type) { 2975 case ixgbe_mac_82598EB: 2976 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2977 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2978 break; 2979 case ixgbe_mac_82599EB: 2980 case ixgbe_mac_X540: 2981 case ixgbe_mac_X550: 2982 case ixgbe_mac_X550EM_x: 2983 case ixgbe_mac_x550em_a: 2984 mask = (qmask & 0xFFFFFFFF); 2985 if (mask) 2986 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2987 mask = (qmask >> 32); 2988 if (mask) 2989 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2990 break; 2991 default: 2992 break; 2993 } 2994 /* skip the flush */ 2995 } 2996 2997 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, 2998 u64 qmask) 2999 { 3000 u32 mask; 3001 struct ixgbe_hw *hw = &adapter->hw; 3002 3003 switch (hw->mac.type) { 3004 case ixgbe_mac_82598EB: 3005 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3006 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); 3007 break; 3008 case ixgbe_mac_82599EB: 3009 case ixgbe_mac_X540: 3010 case ixgbe_mac_X550: 3011 case ixgbe_mac_X550EM_x: 3012 case ixgbe_mac_x550em_a: 3013 mask = (qmask & 0xFFFFFFFF); 3014 if (mask) 3015 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); 3016 mask = (qmask >> 32); 3017 if (mask) 3018 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); 3019 break; 3020 default: 3021 break; 3022 } 3023 /* skip the flush */ 3024 } 3025 3026 /** 3027 * ixgbe_irq_enable - Enable default interrupt generation settings 3028 * @adapter: board private structure 3029 * @queues: enable irqs for queues 3030 * @flush: flush register write 3031 **/ 3032 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3033 bool flush) 3034 { 3035 struct ixgbe_hw *hw = &adapter->hw; 3036 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3037 3038 /* don't reenable LSC while waiting for link */ 3039 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3040 mask &= ~IXGBE_EIMS_LSC; 3041 3042 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3043 switch (adapter->hw.mac.type) { 3044 case ixgbe_mac_82599EB: 3045 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3046 break; 3047 case ixgbe_mac_X540: 3048 case ixgbe_mac_X550: 3049 case ixgbe_mac_X550EM_x: 3050 case ixgbe_mac_x550em_a: 3051 mask |= IXGBE_EIMS_TS; 3052 break; 3053 default: 3054 break; 3055 } 3056 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3057 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3058 switch (adapter->hw.mac.type) { 3059 case ixgbe_mac_82599EB: 3060 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3061 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3062 /* fall through */ 3063 case ixgbe_mac_X540: 3064 case ixgbe_mac_X550: 3065 case ixgbe_mac_X550EM_x: 3066 case ixgbe_mac_x550em_a: 3067 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3068 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3069 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3070 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3071 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3072 mask |= IXGBE_EICR_GPI_SDP0_X540; 3073 mask |= IXGBE_EIMS_ECC; 3074 mask |= IXGBE_EIMS_MAILBOX; 3075 break; 3076 default: 3077 break; 3078 } 3079 3080 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3081 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3082 mask |= IXGBE_EIMS_FLOW_DIR; 3083 3084 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3085 if (queues) 3086 ixgbe_irq_enable_queues(adapter, ~0); 3087 if (flush) 3088 IXGBE_WRITE_FLUSH(&adapter->hw); 3089 } 3090 3091 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3092 { 3093 struct ixgbe_adapter *adapter = data; 3094 struct ixgbe_hw *hw = &adapter->hw; 3095 u32 eicr; 3096 3097 /* 3098 * Workaround for Silicon errata. Use clear-by-write instead 3099 * of clear-by-read. Reading with EICS will return the 3100 * interrupt causes without clearing, which later be done 3101 * with the write to EICR. 3102 */ 3103 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3104 3105 /* The lower 16bits of the EICR register are for the queue interrupts 3106 * which should be masked here in order to not accidentally clear them if 3107 * the bits are high when ixgbe_msix_other is called. There is a race 3108 * condition otherwise which results in possible performance loss 3109 * especially if the ixgbe_msix_other interrupt is triggering 3110 * consistently (as it would when PPS is turned on for the X540 device) 3111 */ 3112 eicr &= 0xFFFF0000; 3113 3114 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3115 3116 if (eicr & IXGBE_EICR_LSC) 3117 ixgbe_check_lsc(adapter); 3118 3119 if (eicr & IXGBE_EICR_MAILBOX) 3120 ixgbe_msg_task(adapter); 3121 3122 switch (hw->mac.type) { 3123 case ixgbe_mac_82599EB: 3124 case ixgbe_mac_X540: 3125 case ixgbe_mac_X550: 3126 case ixgbe_mac_X550EM_x: 3127 case ixgbe_mac_x550em_a: 3128 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3129 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3130 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3131 ixgbe_service_event_schedule(adapter); 3132 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3133 IXGBE_EICR_GPI_SDP0_X540); 3134 } 3135 if (eicr & IXGBE_EICR_ECC) { 3136 e_info(link, "Received ECC Err, initiating reset\n"); 3137 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3138 ixgbe_service_event_schedule(adapter); 3139 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3140 } 3141 /* Handle Flow Director Full threshold interrupt */ 3142 if (eicr & IXGBE_EICR_FLOW_DIR) { 3143 int reinit_count = 0; 3144 int i; 3145 for (i = 0; i < adapter->num_tx_queues; i++) { 3146 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3147 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3148 &ring->state)) 3149 reinit_count++; 3150 } 3151 if (reinit_count) { 3152 /* no more flow director interrupts until after init */ 3153 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3154 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3155 ixgbe_service_event_schedule(adapter); 3156 } 3157 } 3158 ixgbe_check_sfp_event(adapter, eicr); 3159 ixgbe_check_overtemp_event(adapter, eicr); 3160 break; 3161 default: 3162 break; 3163 } 3164 3165 ixgbe_check_fan_failure(adapter, eicr); 3166 3167 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3168 ixgbe_ptp_check_pps_event(adapter); 3169 3170 /* re-enable the original interrupt state, no lsc, no queues */ 3171 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3172 ixgbe_irq_enable(adapter, false, false); 3173 3174 return IRQ_HANDLED; 3175 } 3176 3177 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3178 { 3179 struct ixgbe_q_vector *q_vector = data; 3180 3181 /* EIAM disabled interrupts (on this vector) for us */ 3182 3183 if (q_vector->rx.ring || q_vector->tx.ring) 3184 napi_schedule_irqoff(&q_vector->napi); 3185 3186 return IRQ_HANDLED; 3187 } 3188 3189 /** 3190 * ixgbe_poll - NAPI Rx polling callback 3191 * @napi: structure for representing this polling device 3192 * @budget: how many packets driver is allowed to clean 3193 * 3194 * This function is used for legacy and MSI, NAPI mode 3195 **/ 3196 int ixgbe_poll(struct napi_struct *napi, int budget) 3197 { 3198 struct ixgbe_q_vector *q_vector = 3199 container_of(napi, struct ixgbe_q_vector, napi); 3200 struct ixgbe_adapter *adapter = q_vector->adapter; 3201 struct ixgbe_ring *ring; 3202 int per_ring_budget, work_done = 0; 3203 bool clean_complete = true; 3204 3205 #ifdef CONFIG_IXGBE_DCA 3206 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3207 ixgbe_update_dca(q_vector); 3208 #endif 3209 3210 ixgbe_for_each_ring(ring, q_vector->tx) { 3211 if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) 3212 clean_complete = false; 3213 } 3214 3215 /* Exit if we are called by netpoll */ 3216 if (budget <= 0) 3217 return budget; 3218 3219 /* attempt to distribute budget to each queue fairly, but don't allow 3220 * the budget to go below 1 because we'll exit polling */ 3221 if (q_vector->rx.count > 1) 3222 per_ring_budget = max(budget/q_vector->rx.count, 1); 3223 else 3224 per_ring_budget = budget; 3225 3226 ixgbe_for_each_ring(ring, q_vector->rx) { 3227 int cleaned = ixgbe_clean_rx_irq(q_vector, ring, 3228 per_ring_budget); 3229 3230 work_done += cleaned; 3231 if (cleaned >= per_ring_budget) 3232 clean_complete = false; 3233 } 3234 3235 /* If all work not completed, return budget and keep polling */ 3236 if (!clean_complete) 3237 return budget; 3238 3239 /* all work done, exit the polling mode */ 3240 napi_complete_done(napi, work_done); 3241 if (adapter->rx_itr_setting & 1) 3242 ixgbe_set_itr(q_vector); 3243 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3244 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); 3245 3246 return min(work_done, budget - 1); 3247 } 3248 3249 /** 3250 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3251 * @adapter: board private structure 3252 * 3253 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3254 * interrupts from the kernel. 3255 **/ 3256 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3257 { 3258 struct net_device *netdev = adapter->netdev; 3259 unsigned int ri = 0, ti = 0; 3260 int vector, err; 3261 3262 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3263 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3264 struct msix_entry *entry = &adapter->msix_entries[vector]; 3265 3266 if (q_vector->tx.ring && q_vector->rx.ring) { 3267 snprintf(q_vector->name, sizeof(q_vector->name), 3268 "%s-TxRx-%u", netdev->name, ri++); 3269 ti++; 3270 } else if (q_vector->rx.ring) { 3271 snprintf(q_vector->name, sizeof(q_vector->name), 3272 "%s-rx-%u", netdev->name, ri++); 3273 } else if (q_vector->tx.ring) { 3274 snprintf(q_vector->name, sizeof(q_vector->name), 3275 "%s-tx-%u", netdev->name, ti++); 3276 } else { 3277 /* skip this unused q_vector */ 3278 continue; 3279 } 3280 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3281 q_vector->name, q_vector); 3282 if (err) { 3283 e_err(probe, "request_irq failed for MSIX interrupt " 3284 "Error: %d\n", err); 3285 goto free_queue_irqs; 3286 } 3287 /* If Flow Director is enabled, set interrupt affinity */ 3288 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3289 /* assign the mask for this irq */ 3290 irq_set_affinity_hint(entry->vector, 3291 &q_vector->affinity_mask); 3292 } 3293 } 3294 3295 err = request_irq(adapter->msix_entries[vector].vector, 3296 ixgbe_msix_other, 0, netdev->name, adapter); 3297 if (err) { 3298 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3299 goto free_queue_irqs; 3300 } 3301 3302 return 0; 3303 3304 free_queue_irqs: 3305 while (vector) { 3306 vector--; 3307 irq_set_affinity_hint(adapter->msix_entries[vector].vector, 3308 NULL); 3309 free_irq(adapter->msix_entries[vector].vector, 3310 adapter->q_vector[vector]); 3311 } 3312 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3313 pci_disable_msix(adapter->pdev); 3314 kfree(adapter->msix_entries); 3315 adapter->msix_entries = NULL; 3316 return err; 3317 } 3318 3319 /** 3320 * ixgbe_intr - legacy mode Interrupt Handler 3321 * @irq: interrupt number 3322 * @data: pointer to a network interface device structure 3323 **/ 3324 static irqreturn_t ixgbe_intr(int irq, void *data) 3325 { 3326 struct ixgbe_adapter *adapter = data; 3327 struct ixgbe_hw *hw = &adapter->hw; 3328 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3329 u32 eicr; 3330 3331 /* 3332 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3333 * before the read of EICR. 3334 */ 3335 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3336 3337 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3338 * therefore no explicit interrupt disable is necessary */ 3339 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3340 if (!eicr) { 3341 /* 3342 * shared interrupt alert! 3343 * make sure interrupts are enabled because the read will 3344 * have disabled interrupts due to EIAM 3345 * finish the workaround of silicon errata on 82598. Unmask 3346 * the interrupt that we masked before the EICR read. 3347 */ 3348 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3349 ixgbe_irq_enable(adapter, true, true); 3350 return IRQ_NONE; /* Not our interrupt */ 3351 } 3352 3353 if (eicr & IXGBE_EICR_LSC) 3354 ixgbe_check_lsc(adapter); 3355 3356 switch (hw->mac.type) { 3357 case ixgbe_mac_82599EB: 3358 ixgbe_check_sfp_event(adapter, eicr); 3359 /* Fall through */ 3360 case ixgbe_mac_X540: 3361 case ixgbe_mac_X550: 3362 case ixgbe_mac_X550EM_x: 3363 case ixgbe_mac_x550em_a: 3364 if (eicr & IXGBE_EICR_ECC) { 3365 e_info(link, "Received ECC Err, initiating reset\n"); 3366 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3367 ixgbe_service_event_schedule(adapter); 3368 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3369 } 3370 ixgbe_check_overtemp_event(adapter, eicr); 3371 break; 3372 default: 3373 break; 3374 } 3375 3376 ixgbe_check_fan_failure(adapter, eicr); 3377 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3378 ixgbe_ptp_check_pps_event(adapter); 3379 3380 /* would disable interrupts here but EIAM disabled it */ 3381 napi_schedule_irqoff(&q_vector->napi); 3382 3383 /* 3384 * re-enable link(maybe) and non-queue interrupts, no flush. 3385 * ixgbe_poll will re-enable the queue interrupts 3386 */ 3387 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3388 ixgbe_irq_enable(adapter, false, false); 3389 3390 return IRQ_HANDLED; 3391 } 3392 3393 /** 3394 * ixgbe_request_irq - initialize interrupts 3395 * @adapter: board private structure 3396 * 3397 * Attempts to configure interrupts using the best available 3398 * capabilities of the hardware and kernel. 3399 **/ 3400 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3401 { 3402 struct net_device *netdev = adapter->netdev; 3403 int err; 3404 3405 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3406 err = ixgbe_request_msix_irqs(adapter); 3407 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3408 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3409 netdev->name, adapter); 3410 else 3411 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3412 netdev->name, adapter); 3413 3414 if (err) 3415 e_err(probe, "request_irq failed, Error %d\n", err); 3416 3417 return err; 3418 } 3419 3420 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3421 { 3422 int vector; 3423 3424 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3425 free_irq(adapter->pdev->irq, adapter); 3426 return; 3427 } 3428 3429 if (!adapter->msix_entries) 3430 return; 3431 3432 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3433 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3434 struct msix_entry *entry = &adapter->msix_entries[vector]; 3435 3436 /* free only the irqs that were actually requested */ 3437 if (!q_vector->rx.ring && !q_vector->tx.ring) 3438 continue; 3439 3440 /* clear the affinity_mask in the IRQ descriptor */ 3441 irq_set_affinity_hint(entry->vector, NULL); 3442 3443 free_irq(entry->vector, q_vector); 3444 } 3445 3446 free_irq(adapter->msix_entries[vector].vector, adapter); 3447 } 3448 3449 /** 3450 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3451 * @adapter: board private structure 3452 **/ 3453 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3454 { 3455 switch (adapter->hw.mac.type) { 3456 case ixgbe_mac_82598EB: 3457 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3458 break; 3459 case ixgbe_mac_82599EB: 3460 case ixgbe_mac_X540: 3461 case ixgbe_mac_X550: 3462 case ixgbe_mac_X550EM_x: 3463 case ixgbe_mac_x550em_a: 3464 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3467 break; 3468 default: 3469 break; 3470 } 3471 IXGBE_WRITE_FLUSH(&adapter->hw); 3472 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3473 int vector; 3474 3475 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3476 synchronize_irq(adapter->msix_entries[vector].vector); 3477 3478 synchronize_irq(adapter->msix_entries[vector++].vector); 3479 } else { 3480 synchronize_irq(adapter->pdev->irq); 3481 } 3482 } 3483 3484 /** 3485 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3486 * @adapter: board private structure 3487 * 3488 **/ 3489 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3490 { 3491 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3492 3493 ixgbe_write_eitr(q_vector); 3494 3495 ixgbe_set_ivar(adapter, 0, 0, 0); 3496 ixgbe_set_ivar(adapter, 1, 0, 0); 3497 3498 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3499 } 3500 3501 /** 3502 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3503 * @adapter: board private structure 3504 * @ring: structure containing ring specific data 3505 * 3506 * Configure the Tx descriptor ring after a reset. 3507 **/ 3508 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3509 struct ixgbe_ring *ring) 3510 { 3511 struct ixgbe_hw *hw = &adapter->hw; 3512 u64 tdba = ring->dma; 3513 int wait_loop = 10; 3514 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3515 u8 reg_idx = ring->reg_idx; 3516 3517 /* disable queue to avoid issues while updating state */ 3518 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3519 IXGBE_WRITE_FLUSH(hw); 3520 3521 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3522 (tdba & DMA_BIT_MASK(32))); 3523 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3524 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3525 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3526 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3527 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3528 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3529 3530 /* 3531 * set WTHRESH to encourage burst writeback, it should not be set 3532 * higher than 1 when: 3533 * - ITR is 0 as it could cause false TX hangs 3534 * - ITR is set to > 100k int/sec and BQL is enabled 3535 * 3536 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3537 * to or less than the number of on chip descriptors, which is 3538 * currently 40. 3539 */ 3540 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3541 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3542 else 3543 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3544 3545 /* 3546 * Setting PTHRESH to 32 both improves performance 3547 * and avoids a TX hang with DFP enabled 3548 */ 3549 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3550 32; /* PTHRESH = 32 */ 3551 3552 /* reinitialize flowdirector state */ 3553 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3554 ring->atr_sample_rate = adapter->atr_sample_rate; 3555 ring->atr_count = 0; 3556 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3557 } else { 3558 ring->atr_sample_rate = 0; 3559 } 3560 3561 /* initialize XPS */ 3562 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3563 struct ixgbe_q_vector *q_vector = ring->q_vector; 3564 3565 if (q_vector) 3566 netif_set_xps_queue(ring->netdev, 3567 &q_vector->affinity_mask, 3568 ring->queue_index); 3569 } 3570 3571 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3572 3573 /* reinitialize tx_buffer_info */ 3574 memset(ring->tx_buffer_info, 0, 3575 sizeof(struct ixgbe_tx_buffer) * ring->count); 3576 3577 /* enable queue */ 3578 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3579 3580 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3581 if (hw->mac.type == ixgbe_mac_82598EB && 3582 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3583 return; 3584 3585 /* poll to verify queue is enabled */ 3586 do { 3587 usleep_range(1000, 2000); 3588 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3589 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3590 if (!wait_loop) 3591 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3592 } 3593 3594 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3595 { 3596 struct ixgbe_hw *hw = &adapter->hw; 3597 u32 rttdcs, mtqc; 3598 u8 tcs = adapter->hw_tcs; 3599 3600 if (hw->mac.type == ixgbe_mac_82598EB) 3601 return; 3602 3603 /* disable the arbiter while setting MTQC */ 3604 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3605 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3606 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3607 3608 /* set transmit pool layout */ 3609 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3610 mtqc = IXGBE_MTQC_VT_ENA; 3611 if (tcs > 4) 3612 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3613 else if (tcs > 1) 3614 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3615 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3616 IXGBE_82599_VMDQ_4Q_MASK) 3617 mtqc |= IXGBE_MTQC_32VF; 3618 else 3619 mtqc |= IXGBE_MTQC_64VF; 3620 } else { 3621 if (tcs > 4) 3622 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3623 else if (tcs > 1) 3624 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3625 else 3626 mtqc = IXGBE_MTQC_64Q_1PB; 3627 } 3628 3629 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3630 3631 /* Enable Security TX Buffer IFG for multiple pb */ 3632 if (tcs) { 3633 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3634 sectx |= IXGBE_SECTX_DCB; 3635 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3636 } 3637 3638 /* re-enable the arbiter */ 3639 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3640 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3641 } 3642 3643 /** 3644 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3645 * @adapter: board private structure 3646 * 3647 * Configure the Tx unit of the MAC after a reset. 3648 **/ 3649 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3650 { 3651 struct ixgbe_hw *hw = &adapter->hw; 3652 u32 dmatxctl; 3653 u32 i; 3654 3655 ixgbe_setup_mtqc(adapter); 3656 3657 if (hw->mac.type != ixgbe_mac_82598EB) { 3658 /* DMATXCTL.EN must be before Tx queues are enabled */ 3659 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3660 dmatxctl |= IXGBE_DMATXCTL_TE; 3661 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3662 } 3663 3664 /* Setup the HW Tx Head and Tail descriptor pointers */ 3665 for (i = 0; i < adapter->num_tx_queues; i++) 3666 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3667 for (i = 0; i < adapter->num_xdp_queues; i++) 3668 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3669 } 3670 3671 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3672 struct ixgbe_ring *ring) 3673 { 3674 struct ixgbe_hw *hw = &adapter->hw; 3675 u8 reg_idx = ring->reg_idx; 3676 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3677 3678 srrctl |= IXGBE_SRRCTL_DROP_EN; 3679 3680 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3681 } 3682 3683 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3684 struct ixgbe_ring *ring) 3685 { 3686 struct ixgbe_hw *hw = &adapter->hw; 3687 u8 reg_idx = ring->reg_idx; 3688 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3689 3690 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3691 3692 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3693 } 3694 3695 #ifdef CONFIG_IXGBE_DCB 3696 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3697 #else 3698 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3699 #endif 3700 { 3701 int i; 3702 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3703 3704 if (adapter->ixgbe_ieee_pfc) 3705 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3706 3707 /* 3708 * We should set the drop enable bit if: 3709 * SR-IOV is enabled 3710 * or 3711 * Number of Rx queues > 1 and flow control is disabled 3712 * 3713 * This allows us to avoid head of line blocking for security 3714 * and performance reasons. 3715 */ 3716 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3717 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3718 for (i = 0; i < adapter->num_rx_queues; i++) 3719 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3720 } else { 3721 for (i = 0; i < adapter->num_rx_queues; i++) 3722 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3723 } 3724 } 3725 3726 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3727 3728 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3729 struct ixgbe_ring *rx_ring) 3730 { 3731 struct ixgbe_hw *hw = &adapter->hw; 3732 u32 srrctl; 3733 u8 reg_idx = rx_ring->reg_idx; 3734 3735 if (hw->mac.type == ixgbe_mac_82598EB) { 3736 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3737 3738 /* 3739 * if VMDq is not active we must program one srrctl register 3740 * per RSS queue since we have enabled RDRXCTL.MVMEN 3741 */ 3742 reg_idx &= mask; 3743 } 3744 3745 /* configure header buffer length, needed for RSC */ 3746 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3747 3748 /* configure the packet buffer length */ 3749 if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) 3750 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3751 else 3752 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3753 3754 /* configure descriptor type */ 3755 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3756 3757 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3758 } 3759 3760 /** 3761 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3762 * @adapter: device handle 3763 * 3764 * - 82598/82599/X540: 128 3765 * - X550(non-SRIOV mode): 512 3766 * - X550(SRIOV mode): 64 3767 */ 3768 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3769 { 3770 if (adapter->hw.mac.type < ixgbe_mac_X550) 3771 return 128; 3772 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3773 return 64; 3774 else 3775 return 512; 3776 } 3777 3778 /** 3779 * ixgbe_store_key - Write the RSS key to HW 3780 * @adapter: device handle 3781 * 3782 * Write the RSS key stored in adapter.rss_key to HW. 3783 */ 3784 void ixgbe_store_key(struct ixgbe_adapter *adapter) 3785 { 3786 struct ixgbe_hw *hw = &adapter->hw; 3787 int i; 3788 3789 for (i = 0; i < 10; i++) 3790 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3791 } 3792 3793 /** 3794 * ixgbe_init_rss_key - Initialize adapter RSS key 3795 * @adapter: device handle 3796 * 3797 * Allocates and initializes the RSS key if it is not allocated. 3798 **/ 3799 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3800 { 3801 u32 *rss_key; 3802 3803 if (!adapter->rss_key) { 3804 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3805 if (unlikely(!rss_key)) 3806 return -ENOMEM; 3807 3808 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3809 adapter->rss_key = rss_key; 3810 } 3811 3812 return 0; 3813 } 3814 3815 /** 3816 * ixgbe_store_reta - Write the RETA table to HW 3817 * @adapter: device handle 3818 * 3819 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3820 */ 3821 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3822 { 3823 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3824 struct ixgbe_hw *hw = &adapter->hw; 3825 u32 reta = 0; 3826 u32 indices_multi; 3827 u8 *indir_tbl = adapter->rss_indir_tbl; 3828 3829 /* Fill out the redirection table as follows: 3830 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3831 * indices. 3832 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3833 * - X550: 8 bit wide entries containing 6 bit RSS index 3834 */ 3835 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3836 indices_multi = 0x11; 3837 else 3838 indices_multi = 0x1; 3839 3840 /* Write redirection table to HW */ 3841 for (i = 0; i < reta_entries; i++) { 3842 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3843 if ((i & 3) == 3) { 3844 if (i < 128) 3845 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3846 else 3847 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3848 reta); 3849 reta = 0; 3850 } 3851 } 3852 } 3853 3854 /** 3855 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3856 * @adapter: device handle 3857 * 3858 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3859 */ 3860 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3861 { 3862 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3863 struct ixgbe_hw *hw = &adapter->hw; 3864 u32 vfreta = 0; 3865 3866 /* Write redirection table to HW */ 3867 for (i = 0; i < reta_entries; i++) { 3868 u16 pool = adapter->num_rx_pools; 3869 3870 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3871 if ((i & 3) != 3) 3872 continue; 3873 3874 while (pool--) 3875 IXGBE_WRITE_REG(hw, 3876 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3877 vfreta); 3878 vfreta = 0; 3879 } 3880 } 3881 3882 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3883 { 3884 u32 i, j; 3885 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3886 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3887 3888 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3889 * make full use of any rings they may have. We will use the 3890 * PSRTYPE register to control how many rings we use within the PF. 3891 */ 3892 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3893 rss_i = 4; 3894 3895 /* Fill out hash function seeds */ 3896 ixgbe_store_key(adapter); 3897 3898 /* Fill out redirection table */ 3899 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3900 3901 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3902 if (j == rss_i) 3903 j = 0; 3904 3905 adapter->rss_indir_tbl[i] = j; 3906 } 3907 3908 ixgbe_store_reta(adapter); 3909 } 3910 3911 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3912 { 3913 struct ixgbe_hw *hw = &adapter->hw; 3914 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3915 int i, j; 3916 3917 /* Fill out hash function seeds */ 3918 for (i = 0; i < 10; i++) { 3919 u16 pool = adapter->num_rx_pools; 3920 3921 while (pool--) 3922 IXGBE_WRITE_REG(hw, 3923 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3924 *(adapter->rss_key + i)); 3925 } 3926 3927 /* Fill out the redirection table */ 3928 for (i = 0, j = 0; i < 64; i++, j++) { 3929 if (j == rss_i) 3930 j = 0; 3931 3932 adapter->rss_indir_tbl[i] = j; 3933 } 3934 3935 ixgbe_store_vfreta(adapter); 3936 } 3937 3938 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3939 { 3940 struct ixgbe_hw *hw = &adapter->hw; 3941 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3942 u32 rxcsum; 3943 3944 /* Disable indicating checksum in descriptor, enables RSS hash */ 3945 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3946 rxcsum |= IXGBE_RXCSUM_PCSD; 3947 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3948 3949 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3950 if (adapter->ring_feature[RING_F_RSS].mask) 3951 mrqc = IXGBE_MRQC_RSSEN; 3952 } else { 3953 u8 tcs = adapter->hw_tcs; 3954 3955 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3956 if (tcs > 4) 3957 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3958 else if (tcs > 1) 3959 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3960 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3961 IXGBE_82599_VMDQ_4Q_MASK) 3962 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3963 else 3964 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3965 3966 /* Enable L3/L4 for Tx Switched packets */ 3967 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3968 } else { 3969 if (tcs > 4) 3970 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3971 else if (tcs > 1) 3972 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3973 else 3974 mrqc = IXGBE_MRQC_RSSEN; 3975 } 3976 } 3977 3978 /* Perform hash on these packet types */ 3979 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3980 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3981 IXGBE_MRQC_RSS_FIELD_IPV6 | 3982 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3983 3984 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3985 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3986 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3987 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3988 3989 if ((hw->mac.type >= ixgbe_mac_X550) && 3990 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 3991 u16 pool = adapter->num_rx_pools; 3992 3993 /* Enable VF RSS mode */ 3994 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 3995 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3996 3997 /* Setup RSS through the VF registers */ 3998 ixgbe_setup_vfreta(adapter); 3999 vfmrqc = IXGBE_MRQC_RSSEN; 4000 vfmrqc |= rss_field; 4001 4002 while (pool--) 4003 IXGBE_WRITE_REG(hw, 4004 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4005 vfmrqc); 4006 } else { 4007 ixgbe_setup_reta(adapter); 4008 mrqc |= rss_field; 4009 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4010 } 4011 } 4012 4013 /** 4014 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4015 * @adapter: address of board private structure 4016 * @ring: structure containing ring specific data 4017 **/ 4018 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4019 struct ixgbe_ring *ring) 4020 { 4021 struct ixgbe_hw *hw = &adapter->hw; 4022 u32 rscctrl; 4023 u8 reg_idx = ring->reg_idx; 4024 4025 if (!ring_is_rsc_enabled(ring)) 4026 return; 4027 4028 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4029 rscctrl |= IXGBE_RSCCTL_RSCEN; 4030 /* 4031 * we must limit the number of descriptors so that the 4032 * total size of max desc * buf_len is not greater 4033 * than 65536 4034 */ 4035 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4036 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4037 } 4038 4039 #define IXGBE_MAX_RX_DESC_POLL 10 4040 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4041 struct ixgbe_ring *ring) 4042 { 4043 struct ixgbe_hw *hw = &adapter->hw; 4044 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4045 u32 rxdctl; 4046 u8 reg_idx = ring->reg_idx; 4047 4048 if (ixgbe_removed(hw->hw_addr)) 4049 return; 4050 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4051 if (hw->mac.type == ixgbe_mac_82598EB && 4052 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4053 return; 4054 4055 do { 4056 usleep_range(1000, 2000); 4057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4058 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4059 4060 if (!wait_loop) { 4061 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4062 "the polling period\n", reg_idx); 4063 } 4064 } 4065 4066 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, 4067 struct ixgbe_ring *ring) 4068 { 4069 struct ixgbe_hw *hw = &adapter->hw; 4070 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4071 u32 rxdctl; 4072 u8 reg_idx = ring->reg_idx; 4073 4074 if (ixgbe_removed(hw->hw_addr)) 4075 return; 4076 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4077 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4078 4079 /* write value back with RXDCTL.ENABLE bit cleared */ 4080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4081 4082 if (hw->mac.type == ixgbe_mac_82598EB && 4083 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4084 return; 4085 4086 /* the hardware may take up to 100us to really disable the rx queue */ 4087 do { 4088 udelay(10); 4089 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4090 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); 4091 4092 if (!wait_loop) { 4093 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " 4094 "the polling period\n", reg_idx); 4095 } 4096 } 4097 4098 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4099 struct ixgbe_ring *ring) 4100 { 4101 struct ixgbe_hw *hw = &adapter->hw; 4102 union ixgbe_adv_rx_desc *rx_desc; 4103 u64 rdba = ring->dma; 4104 u32 rxdctl; 4105 u8 reg_idx = ring->reg_idx; 4106 4107 /* disable queue to avoid issues while updating state */ 4108 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4109 ixgbe_disable_rx_queue(adapter, ring); 4110 4111 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4112 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4113 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4114 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4115 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4116 IXGBE_WRITE_FLUSH(hw); 4117 4118 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4119 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4120 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4121 4122 ixgbe_configure_srrctl(adapter, ring); 4123 ixgbe_configure_rscctl(adapter, ring); 4124 4125 if (hw->mac.type == ixgbe_mac_82598EB) { 4126 /* 4127 * enable cache line friendly hardware writes: 4128 * PTHRESH=32 descriptors (half the internal cache), 4129 * this also removes ugly rx_no_buffer_count increment 4130 * HTHRESH=4 descriptors (to minimize latency on fetch) 4131 * WTHRESH=8 burst writeback up to two cache lines 4132 */ 4133 rxdctl &= ~0x3FFFFF; 4134 rxdctl |= 0x080420; 4135 #if (PAGE_SIZE < 8192) 4136 /* RXDCTL.RLPML does not work on 82599 */ 4137 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4138 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4139 IXGBE_RXDCTL_RLPML_EN); 4140 4141 /* Limit the maximum frame size so we don't overrun the skb. 4142 * This can happen in SRIOV mode when the MTU of the VF is 4143 * higher than the MTU of the PF. 4144 */ 4145 if (ring_uses_build_skb(ring) && 4146 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4147 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4148 IXGBE_RXDCTL_RLPML_EN; 4149 #endif 4150 } 4151 4152 /* initialize rx_buffer_info */ 4153 memset(ring->rx_buffer_info, 0, 4154 sizeof(struct ixgbe_rx_buffer) * ring->count); 4155 4156 /* initialize Rx descriptor 0 */ 4157 rx_desc = IXGBE_RX_DESC(ring, 0); 4158 rx_desc->wb.upper.length = 0; 4159 4160 /* enable receive descriptor ring */ 4161 rxdctl |= IXGBE_RXDCTL_ENABLE; 4162 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4163 4164 ixgbe_rx_desc_queue_enable(adapter, ring); 4165 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4166 } 4167 4168 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4169 { 4170 struct ixgbe_hw *hw = &adapter->hw; 4171 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4172 u16 pool = adapter->num_rx_pools; 4173 4174 /* PSRTYPE must be initialized in non 82598 adapters */ 4175 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4176 IXGBE_PSRTYPE_UDPHDR | 4177 IXGBE_PSRTYPE_IPV4HDR | 4178 IXGBE_PSRTYPE_L2HDR | 4179 IXGBE_PSRTYPE_IPV6HDR; 4180 4181 if (hw->mac.type == ixgbe_mac_82598EB) 4182 return; 4183 4184 if (rss_i > 3) 4185 psrtype |= 2u << 29; 4186 else if (rss_i > 1) 4187 psrtype |= 1u << 29; 4188 4189 while (pool--) 4190 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4191 } 4192 4193 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4194 { 4195 struct ixgbe_hw *hw = &adapter->hw; 4196 u32 reg_offset, vf_shift; 4197 u32 gcr_ext, vmdctl; 4198 int i; 4199 4200 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4201 return; 4202 4203 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4204 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4205 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4206 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4207 vmdctl |= IXGBE_VT_CTL_REPLEN; 4208 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4209 4210 vf_shift = VMDQ_P(0) % 32; 4211 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4212 4213 /* Enable only the PF's pool for Tx/Rx */ 4214 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4215 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4216 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4217 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4218 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4219 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4220 4221 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4222 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4223 4224 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4225 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4226 4227 /* 4228 * Set up VF register offsets for selected VT Mode, 4229 * i.e. 32 or 64 VFs for SR-IOV 4230 */ 4231 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4232 case IXGBE_82599_VMDQ_8Q_MASK: 4233 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4234 break; 4235 case IXGBE_82599_VMDQ_4Q_MASK: 4236 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4237 break; 4238 default: 4239 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4240 break; 4241 } 4242 4243 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4244 4245 for (i = 0; i < adapter->num_vfs; i++) { 4246 /* configure spoof checking */ 4247 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4248 adapter->vfinfo[i].spoofchk_enabled); 4249 4250 /* Enable/Disable RSS query feature */ 4251 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4252 adapter->vfinfo[i].rss_query_enabled); 4253 } 4254 } 4255 4256 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4257 { 4258 struct ixgbe_hw *hw = &adapter->hw; 4259 struct net_device *netdev = adapter->netdev; 4260 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4261 struct ixgbe_ring *rx_ring; 4262 int i; 4263 u32 mhadd, hlreg0; 4264 4265 #ifdef IXGBE_FCOE 4266 /* adjust max frame to be able to do baby jumbo for FCoE */ 4267 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4268 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4269 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4270 4271 #endif /* IXGBE_FCOE */ 4272 4273 /* adjust max frame to be at least the size of a standard frame */ 4274 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4275 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4276 4277 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4278 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4279 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4280 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4281 4282 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4283 } 4284 4285 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4286 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4287 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4288 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4289 4290 /* 4291 * Setup the HW Rx Head and Tail Descriptor Pointers and 4292 * the Base and Length of the Rx Descriptor Ring 4293 */ 4294 for (i = 0; i < adapter->num_rx_queues; i++) { 4295 rx_ring = adapter->rx_ring[i]; 4296 4297 clear_ring_rsc_enabled(rx_ring); 4298 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4299 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4300 4301 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4302 set_ring_rsc_enabled(rx_ring); 4303 4304 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4305 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4306 4307 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4308 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4309 continue; 4310 4311 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4312 4313 #if (PAGE_SIZE < 8192) 4314 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4315 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4316 4317 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4318 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4319 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4320 #endif 4321 } 4322 } 4323 4324 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4325 { 4326 struct ixgbe_hw *hw = &adapter->hw; 4327 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4328 4329 switch (hw->mac.type) { 4330 case ixgbe_mac_82598EB: 4331 /* 4332 * For VMDq support of different descriptor types or 4333 * buffer sizes through the use of multiple SRRCTL 4334 * registers, RDRXCTL.MVMEN must be set to 1 4335 * 4336 * also, the manual doesn't mention it clearly but DCA hints 4337 * will only use queue 0's tags unless this bit is set. Side 4338 * effects of setting this bit are only that SRRCTL must be 4339 * fully programmed [0..15] 4340 */ 4341 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4342 break; 4343 case ixgbe_mac_X550: 4344 case ixgbe_mac_X550EM_x: 4345 case ixgbe_mac_x550em_a: 4346 if (adapter->num_vfs) 4347 rdrxctl |= IXGBE_RDRXCTL_PSP; 4348 /* fall through */ 4349 case ixgbe_mac_82599EB: 4350 case ixgbe_mac_X540: 4351 /* Disable RSC for ACK packets */ 4352 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4353 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4354 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4355 /* hardware requires some bits to be set by default */ 4356 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4357 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4358 break; 4359 default: 4360 /* We should do nothing since we don't know this hardware */ 4361 return; 4362 } 4363 4364 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4365 } 4366 4367 /** 4368 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4369 * @adapter: board private structure 4370 * 4371 * Configure the Rx unit of the MAC after a reset. 4372 **/ 4373 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4374 { 4375 struct ixgbe_hw *hw = &adapter->hw; 4376 int i; 4377 u32 rxctrl, rfctl; 4378 4379 /* disable receives while setting up the descriptors */ 4380 hw->mac.ops.disable_rx(hw); 4381 4382 ixgbe_setup_psrtype(adapter); 4383 ixgbe_setup_rdrxctl(adapter); 4384 4385 /* RSC Setup */ 4386 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4387 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4388 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4389 rfctl |= IXGBE_RFCTL_RSC_DIS; 4390 4391 /* disable NFS filtering */ 4392 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4393 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4394 4395 /* Program registers for the distribution of queues */ 4396 ixgbe_setup_mrqc(adapter); 4397 4398 /* set_rx_buffer_len must be called before ring initialization */ 4399 ixgbe_set_rx_buffer_len(adapter); 4400 4401 /* 4402 * Setup the HW Rx Head and Tail Descriptor Pointers and 4403 * the Base and Length of the Rx Descriptor Ring 4404 */ 4405 for (i = 0; i < adapter->num_rx_queues; i++) 4406 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4407 4408 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4409 /* disable drop enable for 82598 parts */ 4410 if (hw->mac.type == ixgbe_mac_82598EB) 4411 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4412 4413 /* enable all receives */ 4414 rxctrl |= IXGBE_RXCTRL_RXEN; 4415 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4416 } 4417 4418 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4419 __be16 proto, u16 vid) 4420 { 4421 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4422 struct ixgbe_hw *hw = &adapter->hw; 4423 4424 /* add VID to filter table */ 4425 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4426 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4427 4428 set_bit(vid, adapter->active_vlans); 4429 4430 return 0; 4431 } 4432 4433 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4434 { 4435 u32 vlvf; 4436 int idx; 4437 4438 /* short cut the special case */ 4439 if (vlan == 0) 4440 return 0; 4441 4442 /* Search for the vlan id in the VLVF entries */ 4443 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4444 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4445 if ((vlvf & VLAN_VID_MASK) == vlan) 4446 break; 4447 } 4448 4449 return idx; 4450 } 4451 4452 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4453 { 4454 struct ixgbe_hw *hw = &adapter->hw; 4455 u32 bits, word; 4456 int idx; 4457 4458 idx = ixgbe_find_vlvf_entry(hw, vid); 4459 if (!idx) 4460 return; 4461 4462 /* See if any other pools are set for this VLAN filter 4463 * entry other than the PF. 4464 */ 4465 word = idx * 2 + (VMDQ_P(0) / 32); 4466 bits = ~BIT(VMDQ_P(0) % 32); 4467 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4468 4469 /* Disable the filter so this falls into the default pool. */ 4470 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4471 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4472 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4473 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4474 } 4475 } 4476 4477 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4478 __be16 proto, u16 vid) 4479 { 4480 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4481 struct ixgbe_hw *hw = &adapter->hw; 4482 4483 /* remove VID from filter table */ 4484 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4485 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4486 4487 clear_bit(vid, adapter->active_vlans); 4488 4489 return 0; 4490 } 4491 4492 /** 4493 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4494 * @adapter: driver data 4495 */ 4496 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4497 { 4498 struct ixgbe_hw *hw = &adapter->hw; 4499 u32 vlnctrl; 4500 int i, j; 4501 4502 switch (hw->mac.type) { 4503 case ixgbe_mac_82598EB: 4504 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4505 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4506 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4507 break; 4508 case ixgbe_mac_82599EB: 4509 case ixgbe_mac_X540: 4510 case ixgbe_mac_X550: 4511 case ixgbe_mac_X550EM_x: 4512 case ixgbe_mac_x550em_a: 4513 for (i = 0; i < adapter->num_rx_queues; i++) { 4514 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4515 4516 if (!netif_is_ixgbe(ring->netdev)) 4517 continue; 4518 4519 j = ring->reg_idx; 4520 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4521 vlnctrl &= ~IXGBE_RXDCTL_VME; 4522 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4523 } 4524 break; 4525 default: 4526 break; 4527 } 4528 } 4529 4530 /** 4531 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4532 * @adapter: driver data 4533 */ 4534 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4535 { 4536 struct ixgbe_hw *hw = &adapter->hw; 4537 u32 vlnctrl; 4538 int i, j; 4539 4540 switch (hw->mac.type) { 4541 case ixgbe_mac_82598EB: 4542 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4543 vlnctrl |= IXGBE_VLNCTRL_VME; 4544 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4545 break; 4546 case ixgbe_mac_82599EB: 4547 case ixgbe_mac_X540: 4548 case ixgbe_mac_X550: 4549 case ixgbe_mac_X550EM_x: 4550 case ixgbe_mac_x550em_a: 4551 for (i = 0; i < adapter->num_rx_queues; i++) { 4552 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4553 4554 if (!netif_is_ixgbe(ring->netdev)) 4555 continue; 4556 4557 j = ring->reg_idx; 4558 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4559 vlnctrl |= IXGBE_RXDCTL_VME; 4560 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4561 } 4562 break; 4563 default: 4564 break; 4565 } 4566 } 4567 4568 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4569 { 4570 struct ixgbe_hw *hw = &adapter->hw; 4571 u32 vlnctrl, i; 4572 4573 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4574 4575 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4576 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4577 vlnctrl |= IXGBE_VLNCTRL_VFE; 4578 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4579 } else { 4580 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4581 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4582 return; 4583 } 4584 4585 /* Nothing to do for 82598 */ 4586 if (hw->mac.type == ixgbe_mac_82598EB) 4587 return; 4588 4589 /* We are already in VLAN promisc, nothing to do */ 4590 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4591 return; 4592 4593 /* Set flag so we don't redo unnecessary work */ 4594 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4595 4596 /* Add PF to all active pools */ 4597 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4598 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4599 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4600 4601 vlvfb |= BIT(VMDQ_P(0) % 32); 4602 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4603 } 4604 4605 /* Set all bits in the VLAN filter table array */ 4606 for (i = hw->mac.vft_size; i--;) 4607 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4608 } 4609 4610 #define VFTA_BLOCK_SIZE 8 4611 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4612 { 4613 struct ixgbe_hw *hw = &adapter->hw; 4614 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4615 u32 vid_start = vfta_offset * 32; 4616 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4617 u32 i, vid, word, bits; 4618 4619 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4620 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4621 4622 /* pull VLAN ID from VLVF */ 4623 vid = vlvf & VLAN_VID_MASK; 4624 4625 /* only concern outselves with a certain range */ 4626 if (vid < vid_start || vid >= vid_end) 4627 continue; 4628 4629 if (vlvf) { 4630 /* record VLAN ID in VFTA */ 4631 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4632 4633 /* if PF is part of this then continue */ 4634 if (test_bit(vid, adapter->active_vlans)) 4635 continue; 4636 } 4637 4638 /* remove PF from the pool */ 4639 word = i * 2 + VMDQ_P(0) / 32; 4640 bits = ~BIT(VMDQ_P(0) % 32); 4641 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4642 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4643 } 4644 4645 /* extract values from active_vlans and write back to VFTA */ 4646 for (i = VFTA_BLOCK_SIZE; i--;) { 4647 vid = (vfta_offset + i) * 32; 4648 word = vid / BITS_PER_LONG; 4649 bits = vid % BITS_PER_LONG; 4650 4651 vfta[i] |= adapter->active_vlans[word] >> bits; 4652 4653 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4654 } 4655 } 4656 4657 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4658 { 4659 struct ixgbe_hw *hw = &adapter->hw; 4660 u32 vlnctrl, i; 4661 4662 /* Set VLAN filtering to enabled */ 4663 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4664 vlnctrl |= IXGBE_VLNCTRL_VFE; 4665 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4666 4667 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4668 hw->mac.type == ixgbe_mac_82598EB) 4669 return; 4670 4671 /* We are not in VLAN promisc, nothing to do */ 4672 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4673 return; 4674 4675 /* Set flag so we don't redo unnecessary work */ 4676 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4677 4678 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4679 ixgbe_scrub_vfta(adapter, i); 4680 } 4681 4682 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4683 { 4684 u16 vid = 1; 4685 4686 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4687 4688 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4689 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4690 } 4691 4692 /** 4693 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4694 * @netdev: network interface device structure 4695 * 4696 * Writes multicast address list to the MTA hash table. 4697 * Returns: -ENOMEM on failure 4698 * 0 on no addresses written 4699 * X on writing X addresses to MTA 4700 **/ 4701 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4702 { 4703 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4704 struct ixgbe_hw *hw = &adapter->hw; 4705 4706 if (!netif_running(netdev)) 4707 return 0; 4708 4709 if (hw->mac.ops.update_mc_addr_list) 4710 hw->mac.ops.update_mc_addr_list(hw, netdev); 4711 else 4712 return -ENOMEM; 4713 4714 #ifdef CONFIG_PCI_IOV 4715 ixgbe_restore_vf_multicasts(adapter); 4716 #endif 4717 4718 return netdev_mc_count(netdev); 4719 } 4720 4721 #ifdef CONFIG_PCI_IOV 4722 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4723 { 4724 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4725 struct ixgbe_hw *hw = &adapter->hw; 4726 int i; 4727 4728 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4729 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4730 4731 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4732 hw->mac.ops.set_rar(hw, i, 4733 mac_table->addr, 4734 mac_table->pool, 4735 IXGBE_RAH_AV); 4736 else 4737 hw->mac.ops.clear_rar(hw, i); 4738 } 4739 } 4740 4741 #endif 4742 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4743 { 4744 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4745 struct ixgbe_hw *hw = &adapter->hw; 4746 int i; 4747 4748 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4749 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4750 continue; 4751 4752 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4753 4754 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4755 hw->mac.ops.set_rar(hw, i, 4756 mac_table->addr, 4757 mac_table->pool, 4758 IXGBE_RAH_AV); 4759 else 4760 hw->mac.ops.clear_rar(hw, i); 4761 } 4762 } 4763 4764 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4765 { 4766 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4767 struct ixgbe_hw *hw = &adapter->hw; 4768 int i; 4769 4770 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4771 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4772 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4773 } 4774 4775 ixgbe_sync_mac_table(adapter); 4776 } 4777 4778 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4779 { 4780 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4781 struct ixgbe_hw *hw = &adapter->hw; 4782 int i, count = 0; 4783 4784 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4785 /* do not count default RAR as available */ 4786 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4787 continue; 4788 4789 /* only count unused and addresses that belong to us */ 4790 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4791 if (mac_table->pool != pool) 4792 continue; 4793 } 4794 4795 count++; 4796 } 4797 4798 return count; 4799 } 4800 4801 /* this function destroys the first RAR entry */ 4802 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4803 { 4804 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4805 struct ixgbe_hw *hw = &adapter->hw; 4806 4807 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4808 mac_table->pool = VMDQ_P(0); 4809 4810 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4811 4812 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4813 IXGBE_RAH_AV); 4814 } 4815 4816 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4817 const u8 *addr, u16 pool) 4818 { 4819 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4820 struct ixgbe_hw *hw = &adapter->hw; 4821 int i; 4822 4823 if (is_zero_ether_addr(addr)) 4824 return -EINVAL; 4825 4826 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4827 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4828 continue; 4829 4830 ether_addr_copy(mac_table->addr, addr); 4831 mac_table->pool = pool; 4832 4833 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4834 IXGBE_MAC_STATE_IN_USE; 4835 4836 ixgbe_sync_mac_table(adapter); 4837 4838 return i; 4839 } 4840 4841 return -ENOMEM; 4842 } 4843 4844 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4845 const u8 *addr, u16 pool) 4846 { 4847 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4848 struct ixgbe_hw *hw = &adapter->hw; 4849 int i; 4850 4851 if (is_zero_ether_addr(addr)) 4852 return -EINVAL; 4853 4854 /* search table for addr, if found clear IN_USE flag and sync */ 4855 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4856 /* we can only delete an entry if it is in use */ 4857 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4858 continue; 4859 /* we only care about entries that belong to the given pool */ 4860 if (mac_table->pool != pool) 4861 continue; 4862 /* we only care about a specific MAC address */ 4863 if (!ether_addr_equal(addr, mac_table->addr)) 4864 continue; 4865 4866 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4867 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4868 4869 ixgbe_sync_mac_table(adapter); 4870 4871 return 0; 4872 } 4873 4874 return -ENOMEM; 4875 } 4876 4877 /** 4878 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table 4879 * @netdev: network interface device structure 4880 * @vfn: pool to associate with unicast addresses 4881 * 4882 * Writes unicast address list to the RAR table. 4883 * Returns: -ENOMEM on failure/insufficient address space 4884 * 0 on no addresses written 4885 * X on writing X addresses to the RAR table 4886 **/ 4887 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) 4888 { 4889 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4890 int count = 0; 4891 4892 /* return ENOMEM indicating insufficient memory for addresses */ 4893 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) 4894 return -ENOMEM; 4895 4896 if (!netdev_uc_empty(netdev)) { 4897 struct netdev_hw_addr *ha; 4898 netdev_for_each_uc_addr(ha, netdev) { 4899 ixgbe_del_mac_filter(adapter, ha->addr, vfn); 4900 ixgbe_add_mac_filter(adapter, ha->addr, vfn); 4901 count++; 4902 } 4903 } 4904 return count; 4905 } 4906 4907 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4908 { 4909 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4910 int ret; 4911 4912 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4913 4914 return min_t(int, ret, 0); 4915 } 4916 4917 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4918 { 4919 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4920 4921 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4922 4923 return 0; 4924 } 4925 4926 /** 4927 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4928 * @netdev: network interface device structure 4929 * 4930 * The set_rx_method entry point is called whenever the unicast/multicast 4931 * address list or the network interface flags are updated. This routine is 4932 * responsible for configuring the hardware for proper unicast, multicast and 4933 * promiscuous mode. 4934 **/ 4935 void ixgbe_set_rx_mode(struct net_device *netdev) 4936 { 4937 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4938 struct ixgbe_hw *hw = &adapter->hw; 4939 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4940 netdev_features_t features = netdev->features; 4941 int count; 4942 4943 /* Check for Promiscuous and All Multicast modes */ 4944 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4945 4946 /* set all bits that we expect to always be set */ 4947 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4948 fctrl |= IXGBE_FCTRL_BAM; 4949 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4950 fctrl |= IXGBE_FCTRL_PMCF; 4951 4952 /* clear the bits we are changing the status of */ 4953 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4954 if (netdev->flags & IFF_PROMISC) { 4955 hw->addr_ctrl.user_set_promisc = true; 4956 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4957 vmolr |= IXGBE_VMOLR_MPE; 4958 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4959 } else { 4960 if (netdev->flags & IFF_ALLMULTI) { 4961 fctrl |= IXGBE_FCTRL_MPE; 4962 vmolr |= IXGBE_VMOLR_MPE; 4963 } 4964 hw->addr_ctrl.user_set_promisc = false; 4965 } 4966 4967 /* 4968 * Write addresses to available RAR registers, if there is not 4969 * sufficient space to store all the addresses then enable 4970 * unicast promiscuous mode 4971 */ 4972 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4973 fctrl |= IXGBE_FCTRL_UPE; 4974 vmolr |= IXGBE_VMOLR_ROPE; 4975 } 4976 4977 /* Write addresses to the MTA, if the attempt fails 4978 * then we should just turn on promiscuous mode so 4979 * that we can at least receive multicast traffic 4980 */ 4981 count = ixgbe_write_mc_addr_list(netdev); 4982 if (count < 0) { 4983 fctrl |= IXGBE_FCTRL_MPE; 4984 vmolr |= IXGBE_VMOLR_MPE; 4985 } else if (count) { 4986 vmolr |= IXGBE_VMOLR_ROMPE; 4987 } 4988 4989 if (hw->mac.type != ixgbe_mac_82598EB) { 4990 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4991 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4992 IXGBE_VMOLR_ROPE); 4993 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4994 } 4995 4996 /* This is useful for sniffing bad packets. */ 4997 if (features & NETIF_F_RXALL) { 4998 /* UPE and MPE will be handled by normal PROMISC logic 4999 * in e1000e_set_rx_mode */ 5000 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 5001 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 5002 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 5003 5004 fctrl &= ~(IXGBE_FCTRL_DPF); 5005 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 5006 } 5007 5008 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5009 5010 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5011 ixgbe_vlan_strip_enable(adapter); 5012 else 5013 ixgbe_vlan_strip_disable(adapter); 5014 5015 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 5016 ixgbe_vlan_promisc_disable(adapter); 5017 else 5018 ixgbe_vlan_promisc_enable(adapter); 5019 } 5020 5021 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5022 { 5023 int q_idx; 5024 5025 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5026 napi_enable(&adapter->q_vector[q_idx]->napi); 5027 } 5028 5029 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5030 { 5031 int q_idx; 5032 5033 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5034 napi_disable(&adapter->q_vector[q_idx]->napi); 5035 } 5036 5037 static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) 5038 { 5039 struct ixgbe_hw *hw = &adapter->hw; 5040 u32 vxlanctrl; 5041 5042 if (!(adapter->flags & (IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE | 5043 IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE))) 5044 return; 5045 5046 vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; 5047 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, vxlanctrl); 5048 5049 if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) 5050 adapter->vxlan_port = 0; 5051 5052 if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) 5053 adapter->geneve_port = 0; 5054 } 5055 5056 #ifdef CONFIG_IXGBE_DCB 5057 /** 5058 * ixgbe_configure_dcb - Configure DCB hardware 5059 * @adapter: ixgbe adapter struct 5060 * 5061 * This is called by the driver on open to configure the DCB hardware. 5062 * This is also called by the gennetlink interface when reconfiguring 5063 * the DCB state. 5064 */ 5065 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5066 { 5067 struct ixgbe_hw *hw = &adapter->hw; 5068 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5069 5070 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5071 if (hw->mac.type == ixgbe_mac_82598EB) 5072 netif_set_gso_max_size(adapter->netdev, 65536); 5073 return; 5074 } 5075 5076 if (hw->mac.type == ixgbe_mac_82598EB) 5077 netif_set_gso_max_size(adapter->netdev, 32768); 5078 5079 #ifdef IXGBE_FCOE 5080 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5081 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5082 #endif 5083 5084 /* reconfigure the hardware */ 5085 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5086 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5087 DCB_TX_CONFIG); 5088 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5089 DCB_RX_CONFIG); 5090 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5091 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5092 ixgbe_dcb_hw_ets(&adapter->hw, 5093 adapter->ixgbe_ieee_ets, 5094 max_frame); 5095 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5096 adapter->ixgbe_ieee_pfc->pfc_en, 5097 adapter->ixgbe_ieee_ets->prio_tc); 5098 } 5099 5100 /* Enable RSS Hash per TC */ 5101 if (hw->mac.type != ixgbe_mac_82598EB) { 5102 u32 msb = 0; 5103 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5104 5105 while (rss_i) { 5106 msb++; 5107 rss_i >>= 1; 5108 } 5109 5110 /* write msb to all 8 TCs in one write */ 5111 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5112 } 5113 } 5114 #endif 5115 5116 /* Additional bittime to account for IXGBE framing */ 5117 #define IXGBE_ETH_FRAMING 20 5118 5119 /** 5120 * ixgbe_hpbthresh - calculate high water mark for flow control 5121 * 5122 * @adapter: board private structure to calculate for 5123 * @pb: packet buffer to calculate 5124 */ 5125 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5126 { 5127 struct ixgbe_hw *hw = &adapter->hw; 5128 struct net_device *dev = adapter->netdev; 5129 int link, tc, kb, marker; 5130 u32 dv_id, rx_pba; 5131 5132 /* Calculate max LAN frame size */ 5133 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5134 5135 #ifdef IXGBE_FCOE 5136 /* FCoE traffic class uses FCOE jumbo frames */ 5137 if ((dev->features & NETIF_F_FCOE_MTU) && 5138 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5139 (pb == ixgbe_fcoe_get_tc(adapter))) 5140 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5141 #endif 5142 5143 /* Calculate delay value for device */ 5144 switch (hw->mac.type) { 5145 case ixgbe_mac_X540: 5146 case ixgbe_mac_X550: 5147 case ixgbe_mac_X550EM_x: 5148 case ixgbe_mac_x550em_a: 5149 dv_id = IXGBE_DV_X540(link, tc); 5150 break; 5151 default: 5152 dv_id = IXGBE_DV(link, tc); 5153 break; 5154 } 5155 5156 /* Loopback switch introduces additional latency */ 5157 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5158 dv_id += IXGBE_B2BT(tc); 5159 5160 /* Delay value is calculated in bit times convert to KB */ 5161 kb = IXGBE_BT2KB(dv_id); 5162 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5163 5164 marker = rx_pba - kb; 5165 5166 /* It is possible that the packet buffer is not large enough 5167 * to provide required headroom. In this case throw an error 5168 * to user and a do the best we can. 5169 */ 5170 if (marker < 0) { 5171 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5172 "headroom to support flow control." 5173 "Decrease MTU or number of traffic classes\n", pb); 5174 marker = tc + 1; 5175 } 5176 5177 return marker; 5178 } 5179 5180 /** 5181 * ixgbe_lpbthresh - calculate low water mark for for flow control 5182 * 5183 * @adapter: board private structure to calculate for 5184 * @pb: packet buffer to calculate 5185 */ 5186 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5187 { 5188 struct ixgbe_hw *hw = &adapter->hw; 5189 struct net_device *dev = adapter->netdev; 5190 int tc; 5191 u32 dv_id; 5192 5193 /* Calculate max LAN frame size */ 5194 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5195 5196 #ifdef IXGBE_FCOE 5197 /* FCoE traffic class uses FCOE jumbo frames */ 5198 if ((dev->features & NETIF_F_FCOE_MTU) && 5199 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5200 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5201 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5202 #endif 5203 5204 /* Calculate delay value for device */ 5205 switch (hw->mac.type) { 5206 case ixgbe_mac_X540: 5207 case ixgbe_mac_X550: 5208 case ixgbe_mac_X550EM_x: 5209 case ixgbe_mac_x550em_a: 5210 dv_id = IXGBE_LOW_DV_X540(tc); 5211 break; 5212 default: 5213 dv_id = IXGBE_LOW_DV(tc); 5214 break; 5215 } 5216 5217 /* Delay value is calculated in bit times convert to KB */ 5218 return IXGBE_BT2KB(dv_id); 5219 } 5220 5221 /* 5222 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5223 */ 5224 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5225 { 5226 struct ixgbe_hw *hw = &adapter->hw; 5227 int num_tc = adapter->hw_tcs; 5228 int i; 5229 5230 if (!num_tc) 5231 num_tc = 1; 5232 5233 for (i = 0; i < num_tc; i++) { 5234 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5235 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5236 5237 /* Low water marks must not be larger than high water marks */ 5238 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5239 hw->fc.low_water[i] = 0; 5240 } 5241 5242 for (; i < MAX_TRAFFIC_CLASS; i++) 5243 hw->fc.high_water[i] = 0; 5244 } 5245 5246 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5247 { 5248 struct ixgbe_hw *hw = &adapter->hw; 5249 int hdrm; 5250 u8 tc = adapter->hw_tcs; 5251 5252 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5253 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5254 hdrm = 32 << adapter->fdir_pballoc; 5255 else 5256 hdrm = 0; 5257 5258 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5259 ixgbe_pbthresh_setup(adapter); 5260 } 5261 5262 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5263 { 5264 struct ixgbe_hw *hw = &adapter->hw; 5265 struct hlist_node *node2; 5266 struct ixgbe_fdir_filter *filter; 5267 5268 spin_lock(&adapter->fdir_perfect_lock); 5269 5270 if (!hlist_empty(&adapter->fdir_filter_list)) 5271 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5272 5273 hlist_for_each_entry_safe(filter, node2, 5274 &adapter->fdir_filter_list, fdir_node) { 5275 ixgbe_fdir_write_perfect_filter_82599(hw, 5276 &filter->filter, 5277 filter->sw_idx, 5278 (filter->action == IXGBE_FDIR_DROP_QUEUE) ? 5279 IXGBE_FDIR_DROP_QUEUE : 5280 adapter->rx_ring[filter->action]->reg_idx); 5281 } 5282 5283 spin_unlock(&adapter->fdir_perfect_lock); 5284 } 5285 5286 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, 5287 struct ixgbe_adapter *adapter) 5288 { 5289 struct ixgbe_hw *hw = &adapter->hw; 5290 u32 vmolr; 5291 5292 /* No unicast promiscuous support for VMDQ devices. */ 5293 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); 5294 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 5295 5296 /* clear the affected bit */ 5297 vmolr &= ~IXGBE_VMOLR_MPE; 5298 5299 if (dev->flags & IFF_ALLMULTI) { 5300 vmolr |= IXGBE_VMOLR_MPE; 5301 } else { 5302 vmolr |= IXGBE_VMOLR_ROMPE; 5303 hw->mac.ops.update_mc_addr_list(hw, dev); 5304 } 5305 ixgbe_write_uc_addr_list(adapter->netdev, pool); 5306 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); 5307 } 5308 5309 /** 5310 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5311 * @rx_ring: ring to free buffers from 5312 **/ 5313 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5314 { 5315 u16 i = rx_ring->next_to_clean; 5316 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5317 5318 /* Free all the Rx ring sk_buffs */ 5319 while (i != rx_ring->next_to_alloc) { 5320 if (rx_buffer->skb) { 5321 struct sk_buff *skb = rx_buffer->skb; 5322 if (IXGBE_CB(skb)->page_released) 5323 dma_unmap_page_attrs(rx_ring->dev, 5324 IXGBE_CB(skb)->dma, 5325 ixgbe_rx_pg_size(rx_ring), 5326 DMA_FROM_DEVICE, 5327 IXGBE_RX_DMA_ATTR); 5328 dev_kfree_skb(skb); 5329 } 5330 5331 /* Invalidate cache lines that may have been written to by 5332 * device so that we avoid corrupting memory. 5333 */ 5334 dma_sync_single_range_for_cpu(rx_ring->dev, 5335 rx_buffer->dma, 5336 rx_buffer->page_offset, 5337 ixgbe_rx_bufsz(rx_ring), 5338 DMA_FROM_DEVICE); 5339 5340 /* free resources associated with mapping */ 5341 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5342 ixgbe_rx_pg_size(rx_ring), 5343 DMA_FROM_DEVICE, 5344 IXGBE_RX_DMA_ATTR); 5345 __page_frag_cache_drain(rx_buffer->page, 5346 rx_buffer->pagecnt_bias); 5347 5348 i++; 5349 rx_buffer++; 5350 if (i == rx_ring->count) { 5351 i = 0; 5352 rx_buffer = rx_ring->rx_buffer_info; 5353 } 5354 } 5355 5356 rx_ring->next_to_alloc = 0; 5357 rx_ring->next_to_clean = 0; 5358 rx_ring->next_to_use = 0; 5359 } 5360 5361 static int ixgbe_fwd_ring_up(struct net_device *vdev, 5362 struct ixgbe_fwd_adapter *accel) 5363 { 5364 struct ixgbe_adapter *adapter = accel->real_adapter; 5365 int i, baseq, err; 5366 5367 if (!test_bit(accel->pool, adapter->fwd_bitmask)) 5368 return 0; 5369 5370 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5371 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5372 accel->pool, adapter->num_rx_pools, 5373 baseq, baseq + adapter->num_rx_queues_per_pool); 5374 5375 accel->netdev = vdev; 5376 accel->rx_base_queue = baseq; 5377 accel->tx_base_queue = baseq; 5378 5379 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5380 adapter->rx_ring[baseq + i]->netdev = vdev; 5381 5382 /* Guarantee all rings are updated before we update the 5383 * MAC address filter. 5384 */ 5385 wmb(); 5386 5387 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5388 * need to only treat it as an error value if it is negative. 5389 */ 5390 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5391 VMDQ_P(accel->pool)); 5392 if (err >= 0) { 5393 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); 5394 return 0; 5395 } 5396 5397 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5398 adapter->rx_ring[baseq + i]->netdev = NULL; 5399 5400 return err; 5401 } 5402 5403 static int ixgbe_upper_dev_walk(struct net_device *upper, void *data) 5404 { 5405 if (netif_is_macvlan(upper)) { 5406 struct macvlan_dev *dfwd = netdev_priv(upper); 5407 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 5408 5409 if (dfwd->fwd_priv) 5410 ixgbe_fwd_ring_up(upper, vadapter); 5411 } 5412 5413 return 0; 5414 } 5415 5416 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5417 { 5418 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5419 ixgbe_upper_dev_walk, NULL); 5420 } 5421 5422 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5423 { 5424 struct ixgbe_hw *hw = &adapter->hw; 5425 5426 ixgbe_configure_pb(adapter); 5427 #ifdef CONFIG_IXGBE_DCB 5428 ixgbe_configure_dcb(adapter); 5429 #endif 5430 /* 5431 * We must restore virtualization before VLANs or else 5432 * the VLVF registers will not be populated 5433 */ 5434 ixgbe_configure_virtualization(adapter); 5435 5436 ixgbe_set_rx_mode(adapter->netdev); 5437 ixgbe_restore_vlan(adapter); 5438 ixgbe_ipsec_restore(adapter); 5439 5440 switch (hw->mac.type) { 5441 case ixgbe_mac_82599EB: 5442 case ixgbe_mac_X540: 5443 hw->mac.ops.disable_rx_buff(hw); 5444 break; 5445 default: 5446 break; 5447 } 5448 5449 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5450 ixgbe_init_fdir_signature_82599(&adapter->hw, 5451 adapter->fdir_pballoc); 5452 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5453 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5454 adapter->fdir_pballoc); 5455 ixgbe_fdir_filter_restore(adapter); 5456 } 5457 5458 switch (hw->mac.type) { 5459 case ixgbe_mac_82599EB: 5460 case ixgbe_mac_X540: 5461 hw->mac.ops.enable_rx_buff(hw); 5462 break; 5463 default: 5464 break; 5465 } 5466 5467 #ifdef CONFIG_IXGBE_DCA 5468 /* configure DCA */ 5469 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5470 ixgbe_setup_dca(adapter); 5471 #endif /* CONFIG_IXGBE_DCA */ 5472 5473 #ifdef IXGBE_FCOE 5474 /* configure FCoE L2 filters, redirection table, and Rx control */ 5475 ixgbe_configure_fcoe(adapter); 5476 5477 #endif /* IXGBE_FCOE */ 5478 ixgbe_configure_tx(adapter); 5479 ixgbe_configure_rx(adapter); 5480 ixgbe_configure_dfwd(adapter); 5481 } 5482 5483 /** 5484 * ixgbe_sfp_link_config - set up SFP+ link 5485 * @adapter: pointer to private adapter struct 5486 **/ 5487 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5488 { 5489 /* 5490 * We are assuming the worst case scenario here, and that 5491 * is that an SFP was inserted/removed after the reset 5492 * but before SFP detection was enabled. As such the best 5493 * solution is to just start searching as soon as we start 5494 */ 5495 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5496 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5497 5498 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5499 adapter->sfp_poll_time = 0; 5500 } 5501 5502 /** 5503 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5504 * @hw: pointer to private hardware struct 5505 * 5506 * Returns 0 on success, negative on failure 5507 **/ 5508 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5509 { 5510 u32 speed; 5511 bool autoneg, link_up = false; 5512 int ret = IXGBE_ERR_LINK_SETUP; 5513 5514 if (hw->mac.ops.check_link) 5515 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5516 5517 if (ret) 5518 return ret; 5519 5520 speed = hw->phy.autoneg_advertised; 5521 if ((!speed) && (hw->mac.ops.get_link_capabilities)) 5522 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5523 &autoneg); 5524 if (ret) 5525 return ret; 5526 5527 if (hw->mac.ops.setup_link) 5528 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5529 5530 return ret; 5531 } 5532 5533 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5534 { 5535 struct ixgbe_hw *hw = &adapter->hw; 5536 u32 gpie = 0; 5537 5538 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5539 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5540 IXGBE_GPIE_OCD; 5541 gpie |= IXGBE_GPIE_EIAME; 5542 /* 5543 * use EIAM to auto-mask when MSI-X interrupt is asserted 5544 * this saves a register write for every interrupt 5545 */ 5546 switch (hw->mac.type) { 5547 case ixgbe_mac_82598EB: 5548 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5549 break; 5550 case ixgbe_mac_82599EB: 5551 case ixgbe_mac_X540: 5552 case ixgbe_mac_X550: 5553 case ixgbe_mac_X550EM_x: 5554 case ixgbe_mac_x550em_a: 5555 default: 5556 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5557 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5558 break; 5559 } 5560 } else { 5561 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5562 * specifically only auto mask tx and rx interrupts */ 5563 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5564 } 5565 5566 /* XXX: to interrupt immediately for EICS writes, enable this */ 5567 /* gpie |= IXGBE_GPIE_EIMEN; */ 5568 5569 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5570 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5571 5572 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5573 case IXGBE_82599_VMDQ_8Q_MASK: 5574 gpie |= IXGBE_GPIE_VTMODE_16; 5575 break; 5576 case IXGBE_82599_VMDQ_4Q_MASK: 5577 gpie |= IXGBE_GPIE_VTMODE_32; 5578 break; 5579 default: 5580 gpie |= IXGBE_GPIE_VTMODE_64; 5581 break; 5582 } 5583 } 5584 5585 /* Enable Thermal over heat sensor interrupt */ 5586 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5587 switch (adapter->hw.mac.type) { 5588 case ixgbe_mac_82599EB: 5589 gpie |= IXGBE_SDP0_GPIEN_8259X; 5590 break; 5591 default: 5592 break; 5593 } 5594 } 5595 5596 /* Enable fan failure interrupt */ 5597 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5598 gpie |= IXGBE_SDP1_GPIEN(hw); 5599 5600 switch (hw->mac.type) { 5601 case ixgbe_mac_82599EB: 5602 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5603 break; 5604 case ixgbe_mac_X550EM_x: 5605 case ixgbe_mac_x550em_a: 5606 gpie |= IXGBE_SDP0_GPIEN_X540; 5607 break; 5608 default: 5609 break; 5610 } 5611 5612 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5613 } 5614 5615 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5616 { 5617 struct ixgbe_hw *hw = &adapter->hw; 5618 int err; 5619 u32 ctrl_ext; 5620 5621 ixgbe_get_hw_control(adapter); 5622 ixgbe_setup_gpie(adapter); 5623 5624 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5625 ixgbe_configure_msix(adapter); 5626 else 5627 ixgbe_configure_msi_and_legacy(adapter); 5628 5629 /* enable the optics for 82599 SFP+ fiber */ 5630 if (hw->mac.ops.enable_tx_laser) 5631 hw->mac.ops.enable_tx_laser(hw); 5632 5633 if (hw->phy.ops.set_phy_power) 5634 hw->phy.ops.set_phy_power(hw, true); 5635 5636 smp_mb__before_atomic(); 5637 clear_bit(__IXGBE_DOWN, &adapter->state); 5638 ixgbe_napi_enable_all(adapter); 5639 5640 if (ixgbe_is_sfp(hw)) { 5641 ixgbe_sfp_link_config(adapter); 5642 } else { 5643 err = ixgbe_non_sfp_link_config(hw); 5644 if (err) 5645 e_err(probe, "link_config FAILED %d\n", err); 5646 } 5647 5648 /* clear any pending interrupts, may auto mask */ 5649 IXGBE_READ_REG(hw, IXGBE_EICR); 5650 ixgbe_irq_enable(adapter, true, true); 5651 5652 /* 5653 * If this adapter has a fan, check to see if we had a failure 5654 * before we enabled the interrupt. 5655 */ 5656 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5657 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5658 if (esdp & IXGBE_ESDP_SDP1) 5659 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5660 } 5661 5662 /* bring the link up in the watchdog, this could race with our first 5663 * link up interrupt but shouldn't be a problem */ 5664 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5665 adapter->link_check_timeout = jiffies; 5666 mod_timer(&adapter->service_timer, jiffies); 5667 5668 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5669 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5670 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5671 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5672 } 5673 5674 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5675 { 5676 WARN_ON(in_interrupt()); 5677 /* put off any impending NetWatchDogTimeout */ 5678 netif_trans_update(adapter->netdev); 5679 5680 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5681 usleep_range(1000, 2000); 5682 if (adapter->hw.phy.type == ixgbe_phy_fw) 5683 ixgbe_watchdog_link_is_down(adapter); 5684 ixgbe_down(adapter); 5685 /* 5686 * If SR-IOV enabled then wait a bit before bringing the adapter 5687 * back up to give the VFs time to respond to the reset. The 5688 * two second wait is based upon the watchdog timer cycle in 5689 * the VF driver. 5690 */ 5691 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5692 msleep(2000); 5693 ixgbe_up(adapter); 5694 clear_bit(__IXGBE_RESETTING, &adapter->state); 5695 } 5696 5697 void ixgbe_up(struct ixgbe_adapter *adapter) 5698 { 5699 /* hardware has been reset, we need to reload some things */ 5700 ixgbe_configure(adapter); 5701 5702 ixgbe_up_complete(adapter); 5703 } 5704 5705 void ixgbe_reset(struct ixgbe_adapter *adapter) 5706 { 5707 struct ixgbe_hw *hw = &adapter->hw; 5708 struct net_device *netdev = adapter->netdev; 5709 int err; 5710 5711 if (ixgbe_removed(hw->hw_addr)) 5712 return; 5713 /* lock SFP init bit to prevent race conditions with the watchdog */ 5714 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 5715 usleep_range(1000, 2000); 5716 5717 /* clear all SFP and link config related flags while holding SFP_INIT */ 5718 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 5719 IXGBE_FLAG2_SFP_NEEDS_RESET); 5720 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 5721 5722 err = hw->mac.ops.init_hw(hw); 5723 switch (err) { 5724 case 0: 5725 case IXGBE_ERR_SFP_NOT_PRESENT: 5726 case IXGBE_ERR_SFP_NOT_SUPPORTED: 5727 break; 5728 case IXGBE_ERR_MASTER_REQUESTS_PENDING: 5729 e_dev_err("master disable timed out\n"); 5730 break; 5731 case IXGBE_ERR_EEPROM_VERSION: 5732 /* We are running on a pre-production device, log a warning */ 5733 e_dev_warn("This device is a pre-production adapter/LOM. " 5734 "Please be aware there may be issues associated with " 5735 "your hardware. If you are experiencing problems " 5736 "please contact your Intel or hardware " 5737 "representative who provided you with this " 5738 "hardware.\n"); 5739 break; 5740 default: 5741 e_dev_err("Hardware Error: %d\n", err); 5742 } 5743 5744 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 5745 5746 /* flush entries out of MAC table */ 5747 ixgbe_flush_sw_mac_table(adapter); 5748 __dev_uc_unsync(netdev, NULL); 5749 5750 /* do not flush user set addresses */ 5751 ixgbe_mac_set_default_filter(adapter); 5752 5753 /* update SAN MAC vmdq pool selection */ 5754 if (hw->mac.san_mac_rar_index) 5755 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 5756 5757 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 5758 ixgbe_ptp_reset(adapter); 5759 5760 if (hw->phy.ops.set_phy_power) { 5761 if (!netif_running(adapter->netdev) && !adapter->wol) 5762 hw->phy.ops.set_phy_power(hw, false); 5763 else 5764 hw->phy.ops.set_phy_power(hw, true); 5765 } 5766 } 5767 5768 /** 5769 * ixgbe_clean_tx_ring - Free Tx Buffers 5770 * @tx_ring: ring to be cleaned 5771 **/ 5772 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 5773 { 5774 u16 i = tx_ring->next_to_clean; 5775 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 5776 5777 while (i != tx_ring->next_to_use) { 5778 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 5779 5780 /* Free all the Tx ring sk_buffs */ 5781 if (ring_is_xdp(tx_ring)) 5782 page_frag_free(tx_buffer->data); 5783 else 5784 dev_kfree_skb_any(tx_buffer->skb); 5785 5786 /* unmap skb header data */ 5787 dma_unmap_single(tx_ring->dev, 5788 dma_unmap_addr(tx_buffer, dma), 5789 dma_unmap_len(tx_buffer, len), 5790 DMA_TO_DEVICE); 5791 5792 /* check for eop_desc to determine the end of the packet */ 5793 eop_desc = tx_buffer->next_to_watch; 5794 tx_desc = IXGBE_TX_DESC(tx_ring, i); 5795 5796 /* unmap remaining buffers */ 5797 while (tx_desc != eop_desc) { 5798 tx_buffer++; 5799 tx_desc++; 5800 i++; 5801 if (unlikely(i == tx_ring->count)) { 5802 i = 0; 5803 tx_buffer = tx_ring->tx_buffer_info; 5804 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 5805 } 5806 5807 /* unmap any remaining paged data */ 5808 if (dma_unmap_len(tx_buffer, len)) 5809 dma_unmap_page(tx_ring->dev, 5810 dma_unmap_addr(tx_buffer, dma), 5811 dma_unmap_len(tx_buffer, len), 5812 DMA_TO_DEVICE); 5813 } 5814 5815 /* move us one more past the eop_desc for start of next pkt */ 5816 tx_buffer++; 5817 i++; 5818 if (unlikely(i == tx_ring->count)) { 5819 i = 0; 5820 tx_buffer = tx_ring->tx_buffer_info; 5821 } 5822 } 5823 5824 /* reset BQL for queue */ 5825 if (!ring_is_xdp(tx_ring)) 5826 netdev_tx_reset_queue(txring_txq(tx_ring)); 5827 5828 /* reset next_to_use and next_to_clean */ 5829 tx_ring->next_to_use = 0; 5830 tx_ring->next_to_clean = 0; 5831 } 5832 5833 /** 5834 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 5835 * @adapter: board private structure 5836 **/ 5837 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 5838 { 5839 int i; 5840 5841 for (i = 0; i < adapter->num_rx_queues; i++) 5842 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 5843 } 5844 5845 /** 5846 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 5847 * @adapter: board private structure 5848 **/ 5849 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 5850 { 5851 int i; 5852 5853 for (i = 0; i < adapter->num_tx_queues; i++) 5854 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 5855 for (i = 0; i < adapter->num_xdp_queues; i++) 5856 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 5857 } 5858 5859 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 5860 { 5861 struct hlist_node *node2; 5862 struct ixgbe_fdir_filter *filter; 5863 5864 spin_lock(&adapter->fdir_perfect_lock); 5865 5866 hlist_for_each_entry_safe(filter, node2, 5867 &adapter->fdir_filter_list, fdir_node) { 5868 hlist_del(&filter->fdir_node); 5869 kfree(filter); 5870 } 5871 adapter->fdir_filter_count = 0; 5872 5873 spin_unlock(&adapter->fdir_perfect_lock); 5874 } 5875 5876 void ixgbe_down(struct ixgbe_adapter *adapter) 5877 { 5878 struct net_device *netdev = adapter->netdev; 5879 struct ixgbe_hw *hw = &adapter->hw; 5880 int i; 5881 5882 /* signal that we are down to the interrupt handler */ 5883 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 5884 return; /* do nothing if already down */ 5885 5886 /* disable receives */ 5887 hw->mac.ops.disable_rx(hw); 5888 5889 /* disable all enabled rx queues */ 5890 for (i = 0; i < adapter->num_rx_queues; i++) 5891 /* this call also flushes the previous write */ 5892 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); 5893 5894 usleep_range(10000, 20000); 5895 5896 /* synchronize_sched() needed for pending XDP buffers to drain */ 5897 if (adapter->xdp_ring[0]) 5898 synchronize_sched(); 5899 netif_tx_stop_all_queues(netdev); 5900 5901 /* call carrier off first to avoid false dev_watchdog timeouts */ 5902 netif_carrier_off(netdev); 5903 netif_tx_disable(netdev); 5904 5905 ixgbe_irq_disable(adapter); 5906 5907 ixgbe_napi_disable_all(adapter); 5908 5909 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 5910 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 5911 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 5912 5913 del_timer_sync(&adapter->service_timer); 5914 5915 if (adapter->num_vfs) { 5916 /* Clear EITR Select mapping */ 5917 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 5918 5919 /* Mark all the VFs as inactive */ 5920 for (i = 0 ; i < adapter->num_vfs; i++) 5921 adapter->vfinfo[i].clear_to_send = false; 5922 5923 /* ping all the active vfs to let them know we are going down */ 5924 ixgbe_ping_all_vfs(adapter); 5925 5926 /* Disable all VFTE/VFRE TX/RX */ 5927 ixgbe_disable_tx_rx(adapter); 5928 } 5929 5930 /* disable transmits in the hardware now that interrupts are off */ 5931 for (i = 0; i < adapter->num_tx_queues; i++) { 5932 u8 reg_idx = adapter->tx_ring[i]->reg_idx; 5933 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5934 } 5935 for (i = 0; i < adapter->num_xdp_queues; i++) { 5936 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; 5937 5938 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5939 } 5940 5941 /* Disable the Tx DMA engine on 82599 and later MAC */ 5942 switch (hw->mac.type) { 5943 case ixgbe_mac_82599EB: 5944 case ixgbe_mac_X540: 5945 case ixgbe_mac_X550: 5946 case ixgbe_mac_X550EM_x: 5947 case ixgbe_mac_x550em_a: 5948 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5949 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5950 ~IXGBE_DMATXCTL_TE)); 5951 break; 5952 default: 5953 break; 5954 } 5955 5956 if (!pci_channel_offline(adapter->pdev)) 5957 ixgbe_reset(adapter); 5958 5959 /* power down the optics for 82599 SFP+ fiber */ 5960 if (hw->mac.ops.disable_tx_laser) 5961 hw->mac.ops.disable_tx_laser(hw); 5962 5963 ixgbe_clean_all_tx_rings(adapter); 5964 ixgbe_clean_all_rx_rings(adapter); 5965 } 5966 5967 /** 5968 * ixgbe_eee_capable - helper function to determine EEE support on X550 5969 * @adapter: board private structure 5970 */ 5971 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 5972 { 5973 struct ixgbe_hw *hw = &adapter->hw; 5974 5975 switch (hw->device_id) { 5976 case IXGBE_DEV_ID_X550EM_A_1G_T: 5977 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 5978 if (!hw->phy.eee_speeds_supported) 5979 break; 5980 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 5981 if (!hw->phy.eee_speeds_advertised) 5982 break; 5983 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 5984 break; 5985 default: 5986 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 5987 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 5988 break; 5989 } 5990 } 5991 5992 /** 5993 * ixgbe_tx_timeout - Respond to a Tx Hang 5994 * @netdev: network interface device structure 5995 **/ 5996 static void ixgbe_tx_timeout(struct net_device *netdev) 5997 { 5998 struct ixgbe_adapter *adapter = netdev_priv(netdev); 5999 6000 /* Do the reset outside of interrupt context */ 6001 ixgbe_tx_timeout_reset(adapter); 6002 } 6003 6004 #ifdef CONFIG_IXGBE_DCB 6005 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6006 { 6007 struct ixgbe_hw *hw = &adapter->hw; 6008 struct tc_configuration *tc; 6009 int j; 6010 6011 switch (hw->mac.type) { 6012 case ixgbe_mac_82598EB: 6013 case ixgbe_mac_82599EB: 6014 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6015 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6016 break; 6017 case ixgbe_mac_X540: 6018 case ixgbe_mac_X550: 6019 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6020 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6021 break; 6022 case ixgbe_mac_X550EM_x: 6023 case ixgbe_mac_x550em_a: 6024 default: 6025 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6026 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6027 break; 6028 } 6029 6030 /* Configure DCB traffic classes */ 6031 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6032 tc = &adapter->dcb_cfg.tc_config[j]; 6033 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6034 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6035 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6036 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6037 tc->dcb_pfc = pfc_disabled; 6038 } 6039 6040 /* Initialize default user to priority mapping, UPx->TC0 */ 6041 tc = &adapter->dcb_cfg.tc_config[0]; 6042 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6043 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6044 6045 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6046 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6047 adapter->dcb_cfg.pfc_mode_enable = false; 6048 adapter->dcb_set_bitmap = 0x00; 6049 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6050 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6051 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6052 sizeof(adapter->temp_dcb_cfg)); 6053 } 6054 #endif 6055 6056 /** 6057 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6058 * @adapter: board private structure to initialize 6059 * @ii: pointer to ixgbe_info for device 6060 * 6061 * ixgbe_sw_init initializes the Adapter private data structure. 6062 * Fields are initialized based on PCI device information and 6063 * OS network device settings (MTU size). 6064 **/ 6065 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6066 const struct ixgbe_info *ii) 6067 { 6068 struct ixgbe_hw *hw = &adapter->hw; 6069 struct pci_dev *pdev = adapter->pdev; 6070 unsigned int rss, fdir; 6071 u32 fwsm; 6072 int i; 6073 6074 /* PCI config space info */ 6075 6076 hw->vendor_id = pdev->vendor; 6077 hw->device_id = pdev->device; 6078 hw->revision_id = pdev->revision; 6079 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6080 hw->subsystem_device_id = pdev->subsystem_device; 6081 6082 /* get_invariants needs the device IDs */ 6083 ii->get_invariants(hw); 6084 6085 /* Set common capability flags and settings */ 6086 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6087 adapter->ring_feature[RING_F_RSS].limit = rss; 6088 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6089 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6090 adapter->atr_sample_rate = 20; 6091 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6092 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6093 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6094 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6095 #ifdef CONFIG_IXGBE_DCA 6096 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6097 #endif 6098 #ifdef CONFIG_IXGBE_DCB 6099 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6100 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6101 #endif 6102 #ifdef IXGBE_FCOE 6103 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6104 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6105 #ifdef CONFIG_IXGBE_DCB 6106 /* Default traffic class to use for FCoE */ 6107 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6108 #endif /* CONFIG_IXGBE_DCB */ 6109 #endif /* IXGBE_FCOE */ 6110 6111 /* initialize static ixgbe jump table entries */ 6112 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6113 GFP_KERNEL); 6114 if (!adapter->jump_tables[0]) 6115 return -ENOMEM; 6116 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6117 6118 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6119 adapter->jump_tables[i] = NULL; 6120 6121 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * 6122 hw->mac.num_rar_entries, 6123 GFP_ATOMIC); 6124 if (!adapter->mac_table) 6125 return -ENOMEM; 6126 6127 if (ixgbe_init_rss_key(adapter)) 6128 return -ENOMEM; 6129 6130 /* Set MAC specific capability flags and exceptions */ 6131 switch (hw->mac.type) { 6132 case ixgbe_mac_82598EB: 6133 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6134 6135 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6136 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6137 6138 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6139 adapter->ring_feature[RING_F_FDIR].limit = 0; 6140 adapter->atr_sample_rate = 0; 6141 adapter->fdir_pballoc = 0; 6142 #ifdef IXGBE_FCOE 6143 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6144 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6145 #ifdef CONFIG_IXGBE_DCB 6146 adapter->fcoe.up = 0; 6147 #endif /* IXGBE_DCB */ 6148 #endif /* IXGBE_FCOE */ 6149 break; 6150 case ixgbe_mac_82599EB: 6151 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6152 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6153 break; 6154 case ixgbe_mac_X540: 6155 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6156 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6157 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6158 break; 6159 case ixgbe_mac_x550em_a: 6160 adapter->flags |= IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE; 6161 switch (hw->device_id) { 6162 case IXGBE_DEV_ID_X550EM_A_1G_T: 6163 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6164 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6165 break; 6166 default: 6167 break; 6168 } 6169 /* fall through */ 6170 case ixgbe_mac_X550EM_x: 6171 #ifdef CONFIG_IXGBE_DCB 6172 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6173 #endif 6174 #ifdef IXGBE_FCOE 6175 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6176 #ifdef CONFIG_IXGBE_DCB 6177 adapter->fcoe.up = 0; 6178 #endif /* IXGBE_DCB */ 6179 #endif /* IXGBE_FCOE */ 6180 /* Fall Through */ 6181 case ixgbe_mac_X550: 6182 if (hw->mac.type == ixgbe_mac_X550) 6183 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6184 #ifdef CONFIG_IXGBE_DCA 6185 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6186 #endif 6187 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; 6188 break; 6189 default: 6190 break; 6191 } 6192 6193 #ifdef IXGBE_FCOE 6194 /* FCoE support exists, always init the FCoE lock */ 6195 spin_lock_init(&adapter->fcoe.lock); 6196 6197 #endif 6198 /* n-tuple support exists, always init our spinlock */ 6199 spin_lock_init(&adapter->fdir_perfect_lock); 6200 6201 #ifdef CONFIG_IXGBE_DCB 6202 ixgbe_init_dcb(adapter); 6203 #endif 6204 6205 /* default flow control settings */ 6206 hw->fc.requested_mode = ixgbe_fc_full; 6207 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6208 ixgbe_pbthresh_setup(adapter); 6209 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6210 hw->fc.send_xon = true; 6211 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6212 6213 #ifdef CONFIG_PCI_IOV 6214 if (max_vfs > 0) 6215 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6216 6217 /* assign number of SR-IOV VFs */ 6218 if (hw->mac.type != ixgbe_mac_82598EB) { 6219 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6220 max_vfs = 0; 6221 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6222 } 6223 } 6224 #endif /* CONFIG_PCI_IOV */ 6225 6226 /* enable itr by default in dynamic mode */ 6227 adapter->rx_itr_setting = 1; 6228 adapter->tx_itr_setting = 1; 6229 6230 /* set default ring sizes */ 6231 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6232 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6233 6234 /* set default work limits */ 6235 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6236 6237 /* initialize eeprom parameters */ 6238 if (ixgbe_init_eeprom_params_generic(hw)) { 6239 e_dev_err("EEPROM initialization failed\n"); 6240 return -EIO; 6241 } 6242 6243 /* PF holds first pool slot */ 6244 set_bit(0, adapter->fwd_bitmask); 6245 set_bit(__IXGBE_DOWN, &adapter->state); 6246 6247 return 0; 6248 } 6249 6250 /** 6251 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6252 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6253 * 6254 * Return 0 on success, negative on failure 6255 **/ 6256 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6257 { 6258 struct device *dev = tx_ring->dev; 6259 int orig_node = dev_to_node(dev); 6260 int ring_node = -1; 6261 int size; 6262 6263 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6264 6265 if (tx_ring->q_vector) 6266 ring_node = tx_ring->q_vector->numa_node; 6267 6268 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6269 if (!tx_ring->tx_buffer_info) 6270 tx_ring->tx_buffer_info = vmalloc(size); 6271 if (!tx_ring->tx_buffer_info) 6272 goto err; 6273 6274 /* round up to nearest 4K */ 6275 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6276 tx_ring->size = ALIGN(tx_ring->size, 4096); 6277 6278 set_dev_node(dev, ring_node); 6279 tx_ring->desc = dma_alloc_coherent(dev, 6280 tx_ring->size, 6281 &tx_ring->dma, 6282 GFP_KERNEL); 6283 set_dev_node(dev, orig_node); 6284 if (!tx_ring->desc) 6285 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6286 &tx_ring->dma, GFP_KERNEL); 6287 if (!tx_ring->desc) 6288 goto err; 6289 6290 tx_ring->next_to_use = 0; 6291 tx_ring->next_to_clean = 0; 6292 return 0; 6293 6294 err: 6295 vfree(tx_ring->tx_buffer_info); 6296 tx_ring->tx_buffer_info = NULL; 6297 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6298 return -ENOMEM; 6299 } 6300 6301 /** 6302 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6303 * @adapter: board private structure 6304 * 6305 * If this function returns with an error, then it's possible one or 6306 * more of the rings is populated (while the rest are not). It is the 6307 * callers duty to clean those orphaned rings. 6308 * 6309 * Return 0 on success, negative on failure 6310 **/ 6311 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6312 { 6313 int i, j = 0, err = 0; 6314 6315 for (i = 0; i < adapter->num_tx_queues; i++) { 6316 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6317 if (!err) 6318 continue; 6319 6320 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6321 goto err_setup_tx; 6322 } 6323 for (j = 0; j < adapter->num_xdp_queues; j++) { 6324 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6325 if (!err) 6326 continue; 6327 6328 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6329 goto err_setup_tx; 6330 } 6331 6332 return 0; 6333 err_setup_tx: 6334 /* rewind the index freeing the rings as we go */ 6335 while (j--) 6336 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6337 while (i--) 6338 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6339 return err; 6340 } 6341 6342 /** 6343 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6344 * @adapter: pointer to ixgbe_adapter 6345 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6346 * 6347 * Returns 0 on success, negative on failure 6348 **/ 6349 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6350 struct ixgbe_ring *rx_ring) 6351 { 6352 struct device *dev = rx_ring->dev; 6353 int orig_node = dev_to_node(dev); 6354 int ring_node = -1; 6355 int size; 6356 6357 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6358 6359 if (rx_ring->q_vector) 6360 ring_node = rx_ring->q_vector->numa_node; 6361 6362 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6363 if (!rx_ring->rx_buffer_info) 6364 rx_ring->rx_buffer_info = vmalloc(size); 6365 if (!rx_ring->rx_buffer_info) 6366 goto err; 6367 6368 /* Round up to nearest 4K */ 6369 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6370 rx_ring->size = ALIGN(rx_ring->size, 4096); 6371 6372 set_dev_node(dev, ring_node); 6373 rx_ring->desc = dma_alloc_coherent(dev, 6374 rx_ring->size, 6375 &rx_ring->dma, 6376 GFP_KERNEL); 6377 set_dev_node(dev, orig_node); 6378 if (!rx_ring->desc) 6379 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6380 &rx_ring->dma, GFP_KERNEL); 6381 if (!rx_ring->desc) 6382 goto err; 6383 6384 rx_ring->next_to_clean = 0; 6385 rx_ring->next_to_use = 0; 6386 6387 /* XDP RX-queue info */ 6388 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6389 rx_ring->queue_index) < 0) 6390 goto err; 6391 6392 rx_ring->xdp_prog = adapter->xdp_prog; 6393 6394 return 0; 6395 err: 6396 vfree(rx_ring->rx_buffer_info); 6397 rx_ring->rx_buffer_info = NULL; 6398 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6399 return -ENOMEM; 6400 } 6401 6402 /** 6403 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6404 * @adapter: board private structure 6405 * 6406 * If this function returns with an error, then it's possible one or 6407 * more of the rings is populated (while the rest are not). It is the 6408 * callers duty to clean those orphaned rings. 6409 * 6410 * Return 0 on success, negative on failure 6411 **/ 6412 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6413 { 6414 int i, err = 0; 6415 6416 for (i = 0; i < adapter->num_rx_queues; i++) { 6417 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6418 if (!err) 6419 continue; 6420 6421 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6422 goto err_setup_rx; 6423 } 6424 6425 #ifdef IXGBE_FCOE 6426 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6427 if (!err) 6428 #endif 6429 return 0; 6430 err_setup_rx: 6431 /* rewind the index freeing the rings as we go */ 6432 while (i--) 6433 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6434 return err; 6435 } 6436 6437 /** 6438 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6439 * @tx_ring: Tx descriptor ring for a specific queue 6440 * 6441 * Free all transmit software resources 6442 **/ 6443 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6444 { 6445 ixgbe_clean_tx_ring(tx_ring); 6446 6447 vfree(tx_ring->tx_buffer_info); 6448 tx_ring->tx_buffer_info = NULL; 6449 6450 /* if not set, then don't free */ 6451 if (!tx_ring->desc) 6452 return; 6453 6454 dma_free_coherent(tx_ring->dev, tx_ring->size, 6455 tx_ring->desc, tx_ring->dma); 6456 6457 tx_ring->desc = NULL; 6458 } 6459 6460 /** 6461 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6462 * @adapter: board private structure 6463 * 6464 * Free all transmit software resources 6465 **/ 6466 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6467 { 6468 int i; 6469 6470 for (i = 0; i < adapter->num_tx_queues; i++) 6471 if (adapter->tx_ring[i]->desc) 6472 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6473 for (i = 0; i < adapter->num_xdp_queues; i++) 6474 if (adapter->xdp_ring[i]->desc) 6475 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6476 } 6477 6478 /** 6479 * ixgbe_free_rx_resources - Free Rx Resources 6480 * @rx_ring: ring to clean the resources from 6481 * 6482 * Free all receive software resources 6483 **/ 6484 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6485 { 6486 ixgbe_clean_rx_ring(rx_ring); 6487 6488 rx_ring->xdp_prog = NULL; 6489 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6490 vfree(rx_ring->rx_buffer_info); 6491 rx_ring->rx_buffer_info = NULL; 6492 6493 /* if not set, then don't free */ 6494 if (!rx_ring->desc) 6495 return; 6496 6497 dma_free_coherent(rx_ring->dev, rx_ring->size, 6498 rx_ring->desc, rx_ring->dma); 6499 6500 rx_ring->desc = NULL; 6501 } 6502 6503 /** 6504 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6505 * @adapter: board private structure 6506 * 6507 * Free all receive software resources 6508 **/ 6509 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6510 { 6511 int i; 6512 6513 #ifdef IXGBE_FCOE 6514 ixgbe_free_fcoe_ddp_resources(adapter); 6515 6516 #endif 6517 for (i = 0; i < adapter->num_rx_queues; i++) 6518 if (adapter->rx_ring[i]->desc) 6519 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6520 } 6521 6522 /** 6523 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6524 * @netdev: network interface device structure 6525 * @new_mtu: new value for maximum frame size 6526 * 6527 * Returns 0 on success, negative on failure 6528 **/ 6529 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6530 { 6531 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6532 6533 /* 6534 * For 82599EB we cannot allow legacy VFs to enable their receive 6535 * paths when MTU greater than 1500 is configured. So display a 6536 * warning that legacy VFs will be disabled. 6537 */ 6538 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6539 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6540 (new_mtu > ETH_DATA_LEN)) 6541 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6542 6543 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); 6544 6545 /* must set new MTU before calling down or up */ 6546 netdev->mtu = new_mtu; 6547 6548 if (netif_running(netdev)) 6549 ixgbe_reinit_locked(adapter); 6550 6551 return 0; 6552 } 6553 6554 /** 6555 * ixgbe_open - Called when a network interface is made active 6556 * @netdev: network interface device structure 6557 * 6558 * Returns 0 on success, negative value on failure 6559 * 6560 * The open entry point is called when a network interface is made 6561 * active by the system (IFF_UP). At this point all resources needed 6562 * for transmit and receive operations are allocated, the interrupt 6563 * handler is registered with the OS, the watchdog timer is started, 6564 * and the stack is notified that the interface is ready. 6565 **/ 6566 int ixgbe_open(struct net_device *netdev) 6567 { 6568 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6569 struct ixgbe_hw *hw = &adapter->hw; 6570 int err, queues; 6571 6572 /* disallow open during test */ 6573 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6574 return -EBUSY; 6575 6576 netif_carrier_off(netdev); 6577 6578 /* allocate transmit descriptors */ 6579 err = ixgbe_setup_all_tx_resources(adapter); 6580 if (err) 6581 goto err_setup_tx; 6582 6583 /* allocate receive descriptors */ 6584 err = ixgbe_setup_all_rx_resources(adapter); 6585 if (err) 6586 goto err_setup_rx; 6587 6588 ixgbe_configure(adapter); 6589 6590 err = ixgbe_request_irq(adapter); 6591 if (err) 6592 goto err_req_irq; 6593 6594 /* Notify the stack of the actual queue counts. */ 6595 queues = adapter->num_tx_queues; 6596 err = netif_set_real_num_tx_queues(netdev, queues); 6597 if (err) 6598 goto err_set_queues; 6599 6600 queues = adapter->num_rx_queues; 6601 err = netif_set_real_num_rx_queues(netdev, queues); 6602 if (err) 6603 goto err_set_queues; 6604 6605 ixgbe_ptp_init(adapter); 6606 6607 ixgbe_up_complete(adapter); 6608 6609 ixgbe_clear_udp_tunnel_port(adapter, IXGBE_VXLANCTRL_ALL_UDPPORT_MASK); 6610 udp_tunnel_get_rx_info(netdev); 6611 6612 return 0; 6613 6614 err_set_queues: 6615 ixgbe_free_irq(adapter); 6616 err_req_irq: 6617 ixgbe_free_all_rx_resources(adapter); 6618 if (hw->phy.ops.set_phy_power && !adapter->wol) 6619 hw->phy.ops.set_phy_power(&adapter->hw, false); 6620 err_setup_rx: 6621 ixgbe_free_all_tx_resources(adapter); 6622 err_setup_tx: 6623 ixgbe_reset(adapter); 6624 6625 return err; 6626 } 6627 6628 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6629 { 6630 ixgbe_ptp_suspend(adapter); 6631 6632 if (adapter->hw.phy.ops.enter_lplu) { 6633 adapter->hw.phy.reset_disable = true; 6634 ixgbe_down(adapter); 6635 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6636 adapter->hw.phy.reset_disable = false; 6637 } else { 6638 ixgbe_down(adapter); 6639 } 6640 6641 ixgbe_free_irq(adapter); 6642 6643 ixgbe_free_all_tx_resources(adapter); 6644 ixgbe_free_all_rx_resources(adapter); 6645 } 6646 6647 /** 6648 * ixgbe_close - Disables a network interface 6649 * @netdev: network interface device structure 6650 * 6651 * Returns 0, this is not allowed to fail 6652 * 6653 * The close entry point is called when an interface is de-activated 6654 * by the OS. The hardware is still under the drivers control, but 6655 * needs to be disabled. A global MAC reset is issued to stop the 6656 * hardware, and all transmit and receive resources are freed. 6657 **/ 6658 int ixgbe_close(struct net_device *netdev) 6659 { 6660 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6661 6662 ixgbe_ptp_stop(adapter); 6663 6664 if (netif_device_present(netdev)) 6665 ixgbe_close_suspend(adapter); 6666 6667 ixgbe_fdir_filter_exit(adapter); 6668 6669 ixgbe_release_hw_control(adapter); 6670 6671 return 0; 6672 } 6673 6674 #ifdef CONFIG_PM 6675 static int ixgbe_resume(struct pci_dev *pdev) 6676 { 6677 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6678 struct net_device *netdev = adapter->netdev; 6679 u32 err; 6680 6681 adapter->hw.hw_addr = adapter->io_addr; 6682 pci_set_power_state(pdev, PCI_D0); 6683 pci_restore_state(pdev); 6684 /* 6685 * pci_restore_state clears dev->state_saved so call 6686 * pci_save_state to restore it. 6687 */ 6688 pci_save_state(pdev); 6689 6690 err = pci_enable_device_mem(pdev); 6691 if (err) { 6692 e_dev_err("Cannot enable PCI device from suspend\n"); 6693 return err; 6694 } 6695 smp_mb__before_atomic(); 6696 clear_bit(__IXGBE_DISABLED, &adapter->state); 6697 pci_set_master(pdev); 6698 6699 pci_wake_from_d3(pdev, false); 6700 6701 ixgbe_reset(adapter); 6702 6703 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 6704 6705 rtnl_lock(); 6706 err = ixgbe_init_interrupt_scheme(adapter); 6707 if (!err && netif_running(netdev)) 6708 err = ixgbe_open(netdev); 6709 6710 6711 if (!err) 6712 netif_device_attach(netdev); 6713 rtnl_unlock(); 6714 6715 return err; 6716 } 6717 #endif /* CONFIG_PM */ 6718 6719 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 6720 { 6721 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6722 struct net_device *netdev = adapter->netdev; 6723 struct ixgbe_hw *hw = &adapter->hw; 6724 u32 ctrl; 6725 u32 wufc = adapter->wol; 6726 #ifdef CONFIG_PM 6727 int retval = 0; 6728 #endif 6729 6730 rtnl_lock(); 6731 netif_device_detach(netdev); 6732 6733 if (netif_running(netdev)) 6734 ixgbe_close_suspend(adapter); 6735 6736 ixgbe_clear_interrupt_scheme(adapter); 6737 rtnl_unlock(); 6738 6739 #ifdef CONFIG_PM 6740 retval = pci_save_state(pdev); 6741 if (retval) 6742 return retval; 6743 6744 #endif 6745 if (hw->mac.ops.stop_link_on_d3) 6746 hw->mac.ops.stop_link_on_d3(hw); 6747 6748 if (wufc) { 6749 u32 fctrl; 6750 6751 ixgbe_set_rx_mode(netdev); 6752 6753 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 6754 if (hw->mac.ops.enable_tx_laser) 6755 hw->mac.ops.enable_tx_laser(hw); 6756 6757 /* enable the reception of multicast packets */ 6758 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 6759 fctrl |= IXGBE_FCTRL_MPE; 6760 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 6761 6762 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 6763 ctrl |= IXGBE_CTRL_GIO_DIS; 6764 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 6765 6766 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 6767 } else { 6768 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 6769 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 6770 } 6771 6772 switch (hw->mac.type) { 6773 case ixgbe_mac_82598EB: 6774 pci_wake_from_d3(pdev, false); 6775 break; 6776 case ixgbe_mac_82599EB: 6777 case ixgbe_mac_X540: 6778 case ixgbe_mac_X550: 6779 case ixgbe_mac_X550EM_x: 6780 case ixgbe_mac_x550em_a: 6781 pci_wake_from_d3(pdev, !!wufc); 6782 break; 6783 default: 6784 break; 6785 } 6786 6787 *enable_wake = !!wufc; 6788 if (hw->phy.ops.set_phy_power && !*enable_wake) 6789 hw->phy.ops.set_phy_power(hw, false); 6790 6791 ixgbe_release_hw_control(adapter); 6792 6793 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 6794 pci_disable_device(pdev); 6795 6796 return 0; 6797 } 6798 6799 #ifdef CONFIG_PM 6800 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) 6801 { 6802 int retval; 6803 bool wake; 6804 6805 retval = __ixgbe_shutdown(pdev, &wake); 6806 if (retval) 6807 return retval; 6808 6809 if (wake) { 6810 pci_prepare_to_sleep(pdev); 6811 } else { 6812 pci_wake_from_d3(pdev, false); 6813 pci_set_power_state(pdev, PCI_D3hot); 6814 } 6815 6816 return 0; 6817 } 6818 #endif /* CONFIG_PM */ 6819 6820 static void ixgbe_shutdown(struct pci_dev *pdev) 6821 { 6822 bool wake; 6823 6824 __ixgbe_shutdown(pdev, &wake); 6825 6826 if (system_state == SYSTEM_POWER_OFF) { 6827 pci_wake_from_d3(pdev, wake); 6828 pci_set_power_state(pdev, PCI_D3hot); 6829 } 6830 } 6831 6832 /** 6833 * ixgbe_update_stats - Update the board statistics counters. 6834 * @adapter: board private structure 6835 **/ 6836 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 6837 { 6838 struct net_device *netdev = adapter->netdev; 6839 struct ixgbe_hw *hw = &adapter->hw; 6840 struct ixgbe_hw_stats *hwstats = &adapter->stats; 6841 u64 total_mpc = 0; 6842 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 6843 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 6844 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 6845 u64 alloc_rx_page = 0; 6846 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 6847 6848 if (test_bit(__IXGBE_DOWN, &adapter->state) || 6849 test_bit(__IXGBE_RESETTING, &adapter->state)) 6850 return; 6851 6852 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 6853 u64 rsc_count = 0; 6854 u64 rsc_flush = 0; 6855 for (i = 0; i < adapter->num_rx_queues; i++) { 6856 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 6857 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 6858 } 6859 adapter->rsc_total_count = rsc_count; 6860 adapter->rsc_total_flush = rsc_flush; 6861 } 6862 6863 for (i = 0; i < adapter->num_rx_queues; i++) { 6864 struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; 6865 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 6866 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 6867 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 6868 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 6869 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 6870 bytes += rx_ring->stats.bytes; 6871 packets += rx_ring->stats.packets; 6872 } 6873 adapter->non_eop_descs = non_eop_descs; 6874 adapter->alloc_rx_page = alloc_rx_page; 6875 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 6876 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 6877 adapter->hw_csum_rx_error = hw_csum_rx_error; 6878 netdev->stats.rx_bytes = bytes; 6879 netdev->stats.rx_packets = packets; 6880 6881 bytes = 0; 6882 packets = 0; 6883 /* gather some stats to the adapter struct that are per queue */ 6884 for (i = 0; i < adapter->num_tx_queues; i++) { 6885 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 6886 restart_queue += tx_ring->tx_stats.restart_queue; 6887 tx_busy += tx_ring->tx_stats.tx_busy; 6888 bytes += tx_ring->stats.bytes; 6889 packets += tx_ring->stats.packets; 6890 } 6891 for (i = 0; i < adapter->num_xdp_queues; i++) { 6892 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 6893 6894 restart_queue += xdp_ring->tx_stats.restart_queue; 6895 tx_busy += xdp_ring->tx_stats.tx_busy; 6896 bytes += xdp_ring->stats.bytes; 6897 packets += xdp_ring->stats.packets; 6898 } 6899 adapter->restart_queue = restart_queue; 6900 adapter->tx_busy = tx_busy; 6901 netdev->stats.tx_bytes = bytes; 6902 netdev->stats.tx_packets = packets; 6903 6904 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 6905 6906 /* 8 register reads */ 6907 for (i = 0; i < 8; i++) { 6908 /* for packet buffers not used, the register should read 0 */ 6909 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 6910 missed_rx += mpc; 6911 hwstats->mpc[i] += mpc; 6912 total_mpc += hwstats->mpc[i]; 6913 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 6914 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 6915 switch (hw->mac.type) { 6916 case ixgbe_mac_82598EB: 6917 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 6918 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 6919 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 6920 hwstats->pxonrxc[i] += 6921 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 6922 break; 6923 case ixgbe_mac_82599EB: 6924 case ixgbe_mac_X540: 6925 case ixgbe_mac_X550: 6926 case ixgbe_mac_X550EM_x: 6927 case ixgbe_mac_x550em_a: 6928 hwstats->pxonrxc[i] += 6929 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 6930 break; 6931 default: 6932 break; 6933 } 6934 } 6935 6936 /*16 register reads */ 6937 for (i = 0; i < 16; i++) { 6938 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 6939 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 6940 if ((hw->mac.type == ixgbe_mac_82599EB) || 6941 (hw->mac.type == ixgbe_mac_X540) || 6942 (hw->mac.type == ixgbe_mac_X550) || 6943 (hw->mac.type == ixgbe_mac_X550EM_x) || 6944 (hw->mac.type == ixgbe_mac_x550em_a)) { 6945 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 6946 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 6947 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 6948 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 6949 } 6950 } 6951 6952 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 6953 /* work around hardware counting issue */ 6954 hwstats->gprc -= missed_rx; 6955 6956 ixgbe_update_xoff_received(adapter); 6957 6958 /* 82598 hardware only has a 32 bit counter in the high register */ 6959 switch (hw->mac.type) { 6960 case ixgbe_mac_82598EB: 6961 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 6962 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 6963 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 6964 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 6965 break; 6966 case ixgbe_mac_X540: 6967 case ixgbe_mac_X550: 6968 case ixgbe_mac_X550EM_x: 6969 case ixgbe_mac_x550em_a: 6970 /* OS2BMC stats are X540 and later */ 6971 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 6972 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 6973 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 6974 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 6975 /* fall through */ 6976 case ixgbe_mac_82599EB: 6977 for (i = 0; i < 16; i++) 6978 adapter->hw_rx_no_dma_resources += 6979 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 6980 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 6981 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 6982 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 6983 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 6984 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 6985 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 6986 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 6987 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 6988 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 6989 #ifdef IXGBE_FCOE 6990 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 6991 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 6992 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 6993 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 6994 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 6995 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 6996 /* Add up per cpu counters for total ddp aloc fail */ 6997 if (adapter->fcoe.ddp_pool) { 6998 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 6999 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7000 unsigned int cpu; 7001 u64 noddp = 0, noddp_ext_buff = 0; 7002 for_each_possible_cpu(cpu) { 7003 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7004 noddp += ddp_pool->noddp; 7005 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7006 } 7007 hwstats->fcoe_noddp = noddp; 7008 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7009 } 7010 #endif /* IXGBE_FCOE */ 7011 break; 7012 default: 7013 break; 7014 } 7015 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7016 hwstats->bprc += bprc; 7017 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7018 if (hw->mac.type == ixgbe_mac_82598EB) 7019 hwstats->mprc -= bprc; 7020 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7021 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7022 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7023 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7024 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7025 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7026 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7027 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7028 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7029 hwstats->lxontxc += lxon; 7030 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7031 hwstats->lxofftxc += lxoff; 7032 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7033 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7034 /* 7035 * 82598 errata - tx of flow control packets is included in tx counters 7036 */ 7037 xon_off_tot = lxon + lxoff; 7038 hwstats->gptc -= xon_off_tot; 7039 hwstats->mptc -= xon_off_tot; 7040 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7041 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7042 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7043 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7044 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7045 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7046 hwstats->ptc64 -= xon_off_tot; 7047 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7048 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7049 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7050 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7051 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7052 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7053 7054 /* Fill out the OS statistics structure */ 7055 netdev->stats.multicast = hwstats->mprc; 7056 7057 /* Rx Errors */ 7058 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7059 netdev->stats.rx_dropped = 0; 7060 netdev->stats.rx_length_errors = hwstats->rlec; 7061 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7062 netdev->stats.rx_missed_errors = total_mpc; 7063 } 7064 7065 /** 7066 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7067 * @adapter: pointer to the device adapter structure 7068 **/ 7069 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7070 { 7071 struct ixgbe_hw *hw = &adapter->hw; 7072 int i; 7073 7074 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7075 return; 7076 7077 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7078 7079 /* if interface is down do nothing */ 7080 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7081 return; 7082 7083 /* do nothing if we are not using signature filters */ 7084 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7085 return; 7086 7087 adapter->fdir_overflow++; 7088 7089 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7090 for (i = 0; i < adapter->num_tx_queues; i++) 7091 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7092 &(adapter->tx_ring[i]->state)); 7093 for (i = 0; i < adapter->num_xdp_queues; i++) 7094 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7095 &adapter->xdp_ring[i]->state); 7096 /* re-enable flow director interrupts */ 7097 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7098 } else { 7099 e_err(probe, "failed to finish FDIR re-initialization, " 7100 "ignored adding FDIR ATR filters\n"); 7101 } 7102 } 7103 7104 /** 7105 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7106 * @adapter: pointer to the device adapter structure 7107 * 7108 * This function serves two purposes. First it strobes the interrupt lines 7109 * in order to make certain interrupts are occurring. Secondly it sets the 7110 * bits needed to check for TX hangs. As a result we should immediately 7111 * determine if a hang has occurred. 7112 */ 7113 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7114 { 7115 struct ixgbe_hw *hw = &adapter->hw; 7116 u64 eics = 0; 7117 int i; 7118 7119 /* If we're down, removing or resetting, just bail */ 7120 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7121 test_bit(__IXGBE_REMOVING, &adapter->state) || 7122 test_bit(__IXGBE_RESETTING, &adapter->state)) 7123 return; 7124 7125 /* Force detection of hung controller */ 7126 if (netif_carrier_ok(adapter->netdev)) { 7127 for (i = 0; i < adapter->num_tx_queues; i++) 7128 set_check_for_tx_hang(adapter->tx_ring[i]); 7129 for (i = 0; i < adapter->num_xdp_queues; i++) 7130 set_check_for_tx_hang(adapter->xdp_ring[i]); 7131 } 7132 7133 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7134 /* 7135 * for legacy and MSI interrupts don't set any bits 7136 * that are enabled for EIAM, because this operation 7137 * would set *both* EIMS and EICS for any bit in EIAM 7138 */ 7139 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7140 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7141 } else { 7142 /* get one bit for every active tx/rx interrupt vector */ 7143 for (i = 0; i < adapter->num_q_vectors; i++) { 7144 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7145 if (qv->rx.ring || qv->tx.ring) 7146 eics |= BIT_ULL(i); 7147 } 7148 } 7149 7150 /* Cause software interrupt to ensure rings are cleaned */ 7151 ixgbe_irq_rearm_queues(adapter, eics); 7152 } 7153 7154 /** 7155 * ixgbe_watchdog_update_link - update the link status 7156 * @adapter: pointer to the device adapter structure 7157 **/ 7158 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7159 { 7160 struct ixgbe_hw *hw = &adapter->hw; 7161 u32 link_speed = adapter->link_speed; 7162 bool link_up = adapter->link_up; 7163 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7164 7165 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7166 return; 7167 7168 if (hw->mac.ops.check_link) { 7169 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7170 } else { 7171 /* always assume link is up, if no check link function */ 7172 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7173 link_up = true; 7174 } 7175 7176 if (adapter->ixgbe_ieee_pfc) 7177 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7178 7179 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7180 hw->mac.ops.fc_enable(hw); 7181 ixgbe_set_rx_drop_en(adapter); 7182 } 7183 7184 if (link_up || 7185 time_after(jiffies, (adapter->link_check_timeout + 7186 IXGBE_TRY_LINK_TIMEOUT))) { 7187 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7188 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7189 IXGBE_WRITE_FLUSH(hw); 7190 } 7191 7192 adapter->link_up = link_up; 7193 adapter->link_speed = link_speed; 7194 } 7195 7196 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7197 { 7198 #ifdef CONFIG_IXGBE_DCB 7199 struct net_device *netdev = adapter->netdev; 7200 struct dcb_app app = { 7201 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7202 .protocol = 0, 7203 }; 7204 u8 up = 0; 7205 7206 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7207 up = dcb_ieee_getapp_mask(netdev, &app); 7208 7209 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7210 #endif 7211 } 7212 7213 /** 7214 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7215 * print link up message 7216 * @adapter: pointer to the device adapter structure 7217 **/ 7218 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7219 { 7220 struct net_device *netdev = adapter->netdev; 7221 struct ixgbe_hw *hw = &adapter->hw; 7222 u32 link_speed = adapter->link_speed; 7223 const char *speed_str; 7224 bool flow_rx, flow_tx; 7225 7226 /* only continue if link was previously down */ 7227 if (netif_carrier_ok(netdev)) 7228 return; 7229 7230 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7231 7232 switch (hw->mac.type) { 7233 case ixgbe_mac_82598EB: { 7234 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7235 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7236 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7237 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7238 } 7239 break; 7240 case ixgbe_mac_X540: 7241 case ixgbe_mac_X550: 7242 case ixgbe_mac_X550EM_x: 7243 case ixgbe_mac_x550em_a: 7244 case ixgbe_mac_82599EB: { 7245 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7246 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7247 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7248 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7249 } 7250 break; 7251 default: 7252 flow_tx = false; 7253 flow_rx = false; 7254 break; 7255 } 7256 7257 adapter->last_rx_ptp_check = jiffies; 7258 7259 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7260 ixgbe_ptp_start_cyclecounter(adapter); 7261 7262 switch (link_speed) { 7263 case IXGBE_LINK_SPEED_10GB_FULL: 7264 speed_str = "10 Gbps"; 7265 break; 7266 case IXGBE_LINK_SPEED_5GB_FULL: 7267 speed_str = "5 Gbps"; 7268 break; 7269 case IXGBE_LINK_SPEED_2_5GB_FULL: 7270 speed_str = "2.5 Gbps"; 7271 break; 7272 case IXGBE_LINK_SPEED_1GB_FULL: 7273 speed_str = "1 Gbps"; 7274 break; 7275 case IXGBE_LINK_SPEED_100_FULL: 7276 speed_str = "100 Mbps"; 7277 break; 7278 case IXGBE_LINK_SPEED_10_FULL: 7279 speed_str = "10 Mbps"; 7280 break; 7281 default: 7282 speed_str = "unknown speed"; 7283 break; 7284 } 7285 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7286 ((flow_rx && flow_tx) ? "RX/TX" : 7287 (flow_rx ? "RX" : 7288 (flow_tx ? "TX" : "None")))); 7289 7290 netif_carrier_on(netdev); 7291 ixgbe_check_vf_rate_limit(adapter); 7292 7293 /* enable transmits */ 7294 netif_tx_wake_all_queues(adapter->netdev); 7295 7296 /* update the default user priority for VFs */ 7297 ixgbe_update_default_up(adapter); 7298 7299 /* ping all the active vfs to let them know link has changed */ 7300 ixgbe_ping_all_vfs(adapter); 7301 } 7302 7303 /** 7304 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7305 * print link down message 7306 * @adapter: pointer to the adapter structure 7307 **/ 7308 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7309 { 7310 struct net_device *netdev = adapter->netdev; 7311 struct ixgbe_hw *hw = &adapter->hw; 7312 7313 adapter->link_up = false; 7314 adapter->link_speed = 0; 7315 7316 /* only continue if link was up previously */ 7317 if (!netif_carrier_ok(netdev)) 7318 return; 7319 7320 /* poll for SFP+ cable when link is down */ 7321 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7322 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7323 7324 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7325 ixgbe_ptp_start_cyclecounter(adapter); 7326 7327 e_info(drv, "NIC Link is Down\n"); 7328 netif_carrier_off(netdev); 7329 7330 /* ping all the active vfs to let them know link has changed */ 7331 ixgbe_ping_all_vfs(adapter); 7332 } 7333 7334 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7335 { 7336 int i; 7337 7338 for (i = 0; i < adapter->num_tx_queues; i++) { 7339 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7340 7341 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7342 return true; 7343 } 7344 7345 for (i = 0; i < adapter->num_xdp_queues; i++) { 7346 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7347 7348 if (ring->next_to_use != ring->next_to_clean) 7349 return true; 7350 } 7351 7352 return false; 7353 } 7354 7355 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7356 { 7357 struct ixgbe_hw *hw = &adapter->hw; 7358 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7359 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7360 7361 int i, j; 7362 7363 if (!adapter->num_vfs) 7364 return false; 7365 7366 /* resetting the PF is only needed for MAC before X550 */ 7367 if (hw->mac.type >= ixgbe_mac_X550) 7368 return false; 7369 7370 for (i = 0; i < adapter->num_vfs; i++) { 7371 for (j = 0; j < q_per_pool; j++) { 7372 u32 h, t; 7373 7374 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7375 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7376 7377 if (h != t) 7378 return true; 7379 } 7380 } 7381 7382 return false; 7383 } 7384 7385 /** 7386 * ixgbe_watchdog_flush_tx - flush queues on link down 7387 * @adapter: pointer to the device adapter structure 7388 **/ 7389 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7390 { 7391 if (!netif_carrier_ok(adapter->netdev)) { 7392 if (ixgbe_ring_tx_pending(adapter) || 7393 ixgbe_vf_tx_pending(adapter)) { 7394 /* We've lost link, so the controller stops DMA, 7395 * but we've got queued Tx work that's never going 7396 * to get done, so reset controller to flush Tx. 7397 * (Do the reset outside of interrupt context). 7398 */ 7399 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7400 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7401 } 7402 } 7403 } 7404 7405 #ifdef CONFIG_PCI_IOV 7406 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7407 { 7408 struct ixgbe_hw *hw = &adapter->hw; 7409 struct pci_dev *pdev = adapter->pdev; 7410 unsigned int vf; 7411 u32 gpc; 7412 7413 if (!(netif_carrier_ok(adapter->netdev))) 7414 return; 7415 7416 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7417 if (gpc) /* If incrementing then no need for the check below */ 7418 return; 7419 /* Check to see if a bad DMA write target from an errant or 7420 * malicious VF has caused a PCIe error. If so then we can 7421 * issue a VFLR to the offending VF(s) and then resume without 7422 * requesting a full slot reset. 7423 */ 7424 7425 if (!pdev) 7426 return; 7427 7428 /* check status reg for all VFs owned by this PF */ 7429 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7430 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7431 u16 status_reg; 7432 7433 if (!vfdev) 7434 continue; 7435 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7436 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7437 status_reg & PCI_STATUS_REC_MASTER_ABORT) 7438 pcie_flr(vfdev); 7439 } 7440 } 7441 7442 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7443 { 7444 u32 ssvpc; 7445 7446 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7447 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7448 adapter->num_vfs == 0) 7449 return; 7450 7451 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7452 7453 /* 7454 * ssvpc register is cleared on read, if zero then no 7455 * spoofed packets in the last interval. 7456 */ 7457 if (!ssvpc) 7458 return; 7459 7460 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7461 } 7462 #else 7463 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7464 { 7465 } 7466 7467 static void 7468 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7469 { 7470 } 7471 #endif /* CONFIG_PCI_IOV */ 7472 7473 7474 /** 7475 * ixgbe_watchdog_subtask - check and bring link up 7476 * @adapter: pointer to the device adapter structure 7477 **/ 7478 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7479 { 7480 /* if interface is down, removing or resetting, do nothing */ 7481 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7482 test_bit(__IXGBE_REMOVING, &adapter->state) || 7483 test_bit(__IXGBE_RESETTING, &adapter->state)) 7484 return; 7485 7486 ixgbe_watchdog_update_link(adapter); 7487 7488 if (adapter->link_up) 7489 ixgbe_watchdog_link_is_up(adapter); 7490 else 7491 ixgbe_watchdog_link_is_down(adapter); 7492 7493 ixgbe_check_for_bad_vf(adapter); 7494 ixgbe_spoof_check(adapter); 7495 ixgbe_update_stats(adapter); 7496 7497 ixgbe_watchdog_flush_tx(adapter); 7498 } 7499 7500 /** 7501 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7502 * @adapter: the ixgbe adapter structure 7503 **/ 7504 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7505 { 7506 struct ixgbe_hw *hw = &adapter->hw; 7507 s32 err; 7508 7509 /* not searching for SFP so there is nothing to do here */ 7510 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7511 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7512 return; 7513 7514 if (adapter->sfp_poll_time && 7515 time_after(adapter->sfp_poll_time, jiffies)) 7516 return; /* If not yet time to poll for SFP */ 7517 7518 /* someone else is in init, wait until next service event */ 7519 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7520 return; 7521 7522 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7523 7524 err = hw->phy.ops.identify_sfp(hw); 7525 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7526 goto sfp_out; 7527 7528 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 7529 /* If no cable is present, then we need to reset 7530 * the next time we find a good cable. */ 7531 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7532 } 7533 7534 /* exit on error */ 7535 if (err) 7536 goto sfp_out; 7537 7538 /* exit if reset not needed */ 7539 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7540 goto sfp_out; 7541 7542 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7543 7544 /* 7545 * A module may be identified correctly, but the EEPROM may not have 7546 * support for that module. setup_sfp() will fail in that case, so 7547 * we should not allow that module to load. 7548 */ 7549 if (hw->mac.type == ixgbe_mac_82598EB) 7550 err = hw->phy.ops.reset(hw); 7551 else 7552 err = hw->mac.ops.setup_sfp(hw); 7553 7554 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) 7555 goto sfp_out; 7556 7557 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7558 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7559 7560 sfp_out: 7561 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7562 7563 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && 7564 (adapter->netdev->reg_state == NETREG_REGISTERED)) { 7565 e_dev_err("failed to initialize because an unsupported " 7566 "SFP+ module type was detected.\n"); 7567 e_dev_err("Reload the driver after installing a " 7568 "supported module.\n"); 7569 unregister_netdev(adapter->netdev); 7570 } 7571 } 7572 7573 /** 7574 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7575 * @adapter: the ixgbe adapter structure 7576 **/ 7577 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7578 { 7579 struct ixgbe_hw *hw = &adapter->hw; 7580 u32 cap_speed; 7581 u32 speed; 7582 bool autoneg = false; 7583 7584 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7585 return; 7586 7587 /* someone else is in init, wait until next service event */ 7588 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7589 return; 7590 7591 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7592 7593 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7594 7595 /* advertise highest capable link speed */ 7596 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7597 speed = IXGBE_LINK_SPEED_10GB_FULL; 7598 else 7599 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7600 IXGBE_LINK_SPEED_1GB_FULL); 7601 7602 if (hw->mac.ops.setup_link) 7603 hw->mac.ops.setup_link(hw, speed, true); 7604 7605 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7606 adapter->link_check_timeout = jiffies; 7607 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7608 } 7609 7610 /** 7611 * ixgbe_service_timer - Timer Call-back 7612 * @t: pointer to timer_list structure 7613 **/ 7614 static void ixgbe_service_timer(struct timer_list *t) 7615 { 7616 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7617 unsigned long next_event_offset; 7618 7619 /* poll faster when waiting for link */ 7620 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7621 next_event_offset = HZ / 10; 7622 else 7623 next_event_offset = HZ * 2; 7624 7625 /* Reset the timer */ 7626 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7627 7628 ixgbe_service_event_schedule(adapter); 7629 } 7630 7631 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7632 { 7633 struct ixgbe_hw *hw = &adapter->hw; 7634 u32 status; 7635 7636 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7637 return; 7638 7639 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7640 7641 if (!hw->phy.ops.handle_lasi) 7642 return; 7643 7644 status = hw->phy.ops.handle_lasi(&adapter->hw); 7645 if (status != IXGBE_ERR_OVERTEMP) 7646 return; 7647 7648 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7649 } 7650 7651 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7652 { 7653 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7654 return; 7655 7656 /* If we're already down, removing or resetting, just bail */ 7657 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7658 test_bit(__IXGBE_REMOVING, &adapter->state) || 7659 test_bit(__IXGBE_RESETTING, &adapter->state)) 7660 return; 7661 7662 ixgbe_dump(adapter); 7663 netdev_err(adapter->netdev, "Reset adapter\n"); 7664 adapter->tx_timeout_count++; 7665 7666 rtnl_lock(); 7667 ixgbe_reinit_locked(adapter); 7668 rtnl_unlock(); 7669 } 7670 7671 /** 7672 * ixgbe_service_task - manages and runs subtasks 7673 * @work: pointer to work_struct containing our data 7674 **/ 7675 static void ixgbe_service_task(struct work_struct *work) 7676 { 7677 struct ixgbe_adapter *adapter = container_of(work, 7678 struct ixgbe_adapter, 7679 service_task); 7680 if (ixgbe_removed(adapter->hw.hw_addr)) { 7681 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 7682 rtnl_lock(); 7683 ixgbe_down(adapter); 7684 rtnl_unlock(); 7685 } 7686 ixgbe_service_event_complete(adapter); 7687 return; 7688 } 7689 if (adapter->flags2 & IXGBE_FLAG2_UDP_TUN_REREG_NEEDED) { 7690 rtnl_lock(); 7691 adapter->flags2 &= ~IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 7692 udp_tunnel_get_rx_info(adapter->netdev); 7693 rtnl_unlock(); 7694 } 7695 ixgbe_reset_subtask(adapter); 7696 ixgbe_phy_interrupt_subtask(adapter); 7697 ixgbe_sfp_detection_subtask(adapter); 7698 ixgbe_sfp_link_config_subtask(adapter); 7699 ixgbe_check_overtemp_subtask(adapter); 7700 ixgbe_watchdog_subtask(adapter); 7701 ixgbe_fdir_reinit_subtask(adapter); 7702 ixgbe_check_hang_subtask(adapter); 7703 7704 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 7705 ixgbe_ptp_overflow_check(adapter); 7706 ixgbe_ptp_rx_hang(adapter); 7707 ixgbe_ptp_tx_hang(adapter); 7708 } 7709 7710 ixgbe_service_event_complete(adapter); 7711 } 7712 7713 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 7714 struct ixgbe_tx_buffer *first, 7715 u8 *hdr_len) 7716 { 7717 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 7718 struct sk_buff *skb = first->skb; 7719 union { 7720 struct iphdr *v4; 7721 struct ipv6hdr *v6; 7722 unsigned char *hdr; 7723 } ip; 7724 union { 7725 struct tcphdr *tcp; 7726 unsigned char *hdr; 7727 } l4; 7728 u32 paylen, l4_offset; 7729 int err; 7730 7731 if (skb->ip_summed != CHECKSUM_PARTIAL) 7732 return 0; 7733 7734 if (!skb_is_gso(skb)) 7735 return 0; 7736 7737 err = skb_cow_head(skb, 0); 7738 if (err < 0) 7739 return err; 7740 7741 if (eth_p_mpls(first->protocol)) 7742 ip.hdr = skb_inner_network_header(skb); 7743 else 7744 ip.hdr = skb_network_header(skb); 7745 l4.hdr = skb_checksum_start(skb); 7746 7747 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 7748 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7749 7750 /* initialize outer IP header fields */ 7751 if (ip.v4->version == 4) { 7752 unsigned char *csum_start = skb_checksum_start(skb); 7753 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 7754 7755 /* IP header will have to cancel out any data that 7756 * is not a part of the outer IP header 7757 */ 7758 ip.v4->check = csum_fold(csum_partial(trans_start, 7759 csum_start - trans_start, 7760 0)); 7761 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 7762 7763 ip.v4->tot_len = 0; 7764 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7765 IXGBE_TX_FLAGS_CSUM | 7766 IXGBE_TX_FLAGS_IPV4; 7767 } else { 7768 ip.v6->payload_len = 0; 7769 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 7770 IXGBE_TX_FLAGS_CSUM; 7771 } 7772 7773 /* determine offset of inner transport header */ 7774 l4_offset = l4.hdr - skb->data; 7775 7776 /* compute length of segmentation header */ 7777 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 7778 7779 /* remove payload length from inner checksum */ 7780 paylen = skb->len - l4_offset; 7781 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 7782 7783 /* update gso size and bytecount with header size */ 7784 first->gso_segs = skb_shinfo(skb)->gso_segs; 7785 first->bytecount += (first->gso_segs - 1) * *hdr_len; 7786 7787 /* mss_l4len_id: use 0 as index for TSO */ 7788 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 7789 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 7790 7791 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 7792 vlan_macip_lens = l4.hdr - ip.hdr; 7793 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 7794 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7795 7796 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 7797 mss_l4len_idx); 7798 7799 return 1; 7800 } 7801 7802 static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) 7803 { 7804 unsigned int offset = 0; 7805 7806 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); 7807 7808 return offset == skb_checksum_start_offset(skb); 7809 } 7810 7811 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 7812 struct ixgbe_tx_buffer *first, 7813 struct ixgbe_ipsec_tx_data *itd) 7814 { 7815 struct sk_buff *skb = first->skb; 7816 u32 vlan_macip_lens = 0; 7817 u32 fceof_saidx = 0; 7818 u32 type_tucmd = 0; 7819 7820 if (skb->ip_summed != CHECKSUM_PARTIAL) { 7821 csum_failed: 7822 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 7823 IXGBE_TX_FLAGS_CC))) 7824 return; 7825 goto no_csum; 7826 } 7827 7828 switch (skb->csum_offset) { 7829 case offsetof(struct tcphdr, check): 7830 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 7831 /* fall through */ 7832 case offsetof(struct udphdr, check): 7833 break; 7834 case offsetof(struct sctphdr, checksum): 7835 /* validate that this is actually an SCTP request */ 7836 if (((first->protocol == htons(ETH_P_IP)) && 7837 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || 7838 ((first->protocol == htons(ETH_P_IPV6)) && 7839 ixgbe_ipv6_csum_is_sctp(skb))) { 7840 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 7841 break; 7842 } 7843 /* fall through */ 7844 default: 7845 skb_checksum_help(skb); 7846 goto csum_failed; 7847 } 7848 7849 /* update TX checksum flag */ 7850 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 7851 vlan_macip_lens = skb_checksum_start_offset(skb) - 7852 skb_network_offset(skb); 7853 no_csum: 7854 /* vlan_macip_lens: MACLEN, VLAN tag */ 7855 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 7856 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 7857 7858 if (first->tx_flags & IXGBE_TX_FLAGS_IPSEC) { 7859 fceof_saidx |= itd->sa_idx; 7860 type_tucmd |= itd->flags | itd->trailer_len; 7861 } 7862 7863 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 7864 } 7865 7866 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 7867 ((_flag <= _result) ? \ 7868 ((u32)(_input & _flag) * (_result / _flag)) : \ 7869 ((u32)(_input & _flag) / (_flag / _result))) 7870 7871 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 7872 { 7873 /* set type for advanced descriptor with frame checksum insertion */ 7874 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 7875 IXGBE_ADVTXD_DCMD_DEXT | 7876 IXGBE_ADVTXD_DCMD_IFCS; 7877 7878 /* set HW vlan bit if vlan is present */ 7879 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 7880 IXGBE_ADVTXD_DCMD_VLE); 7881 7882 /* set segmentation enable bits for TSO/FSO */ 7883 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 7884 IXGBE_ADVTXD_DCMD_TSE); 7885 7886 /* set timestamp bit if present */ 7887 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 7888 IXGBE_ADVTXD_MAC_TSTAMP); 7889 7890 /* insert frame checksum */ 7891 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 7892 7893 return cmd_type; 7894 } 7895 7896 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 7897 u32 tx_flags, unsigned int paylen) 7898 { 7899 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 7900 7901 /* enable L4 checksum for TSO and TX checksum offload */ 7902 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7903 IXGBE_TX_FLAGS_CSUM, 7904 IXGBE_ADVTXD_POPTS_TXSM); 7905 7906 /* enable IPv4 checksum for TSO */ 7907 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7908 IXGBE_TX_FLAGS_IPV4, 7909 IXGBE_ADVTXD_POPTS_IXSM); 7910 7911 /* enable IPsec */ 7912 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7913 IXGBE_TX_FLAGS_IPSEC, 7914 IXGBE_ADVTXD_POPTS_IPSEC); 7915 7916 /* 7917 * Check Context must be set if Tx switch is enabled, which it 7918 * always is for case where virtual functions are running 7919 */ 7920 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 7921 IXGBE_TX_FLAGS_CC, 7922 IXGBE_ADVTXD_CC); 7923 7924 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 7925 } 7926 7927 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7928 { 7929 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 7930 7931 /* Herbert's original patch had: 7932 * smp_mb__after_netif_stop_queue(); 7933 * but since that doesn't exist yet, just open code it. 7934 */ 7935 smp_mb(); 7936 7937 /* We need to check again in a case another CPU has just 7938 * made room available. 7939 */ 7940 if (likely(ixgbe_desc_unused(tx_ring) < size)) 7941 return -EBUSY; 7942 7943 /* A reprieve! - use start_queue because it doesn't call schedule */ 7944 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 7945 ++tx_ring->tx_stats.restart_queue; 7946 return 0; 7947 } 7948 7949 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 7950 { 7951 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 7952 return 0; 7953 7954 return __ixgbe_maybe_stop_tx(tx_ring, size); 7955 } 7956 7957 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ 7958 IXGBE_TXD_CMD_RS) 7959 7960 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 7961 struct ixgbe_tx_buffer *first, 7962 const u8 hdr_len) 7963 { 7964 struct sk_buff *skb = first->skb; 7965 struct ixgbe_tx_buffer *tx_buffer; 7966 union ixgbe_adv_tx_desc *tx_desc; 7967 struct skb_frag_struct *frag; 7968 dma_addr_t dma; 7969 unsigned int data_len, size; 7970 u32 tx_flags = first->tx_flags; 7971 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 7972 u16 i = tx_ring->next_to_use; 7973 7974 tx_desc = IXGBE_TX_DESC(tx_ring, i); 7975 7976 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 7977 7978 size = skb_headlen(skb); 7979 data_len = skb->data_len; 7980 7981 #ifdef IXGBE_FCOE 7982 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 7983 if (data_len < sizeof(struct fcoe_crc_eof)) { 7984 size -= sizeof(struct fcoe_crc_eof) - data_len; 7985 data_len = 0; 7986 } else { 7987 data_len -= sizeof(struct fcoe_crc_eof); 7988 } 7989 } 7990 7991 #endif 7992 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 7993 7994 tx_buffer = first; 7995 7996 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 7997 if (dma_mapping_error(tx_ring->dev, dma)) 7998 goto dma_error; 7999 8000 /* record length, and DMA address */ 8001 dma_unmap_len_set(tx_buffer, len, size); 8002 dma_unmap_addr_set(tx_buffer, dma, dma); 8003 8004 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8005 8006 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8007 tx_desc->read.cmd_type_len = 8008 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8009 8010 i++; 8011 tx_desc++; 8012 if (i == tx_ring->count) { 8013 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8014 i = 0; 8015 } 8016 tx_desc->read.olinfo_status = 0; 8017 8018 dma += IXGBE_MAX_DATA_PER_TXD; 8019 size -= IXGBE_MAX_DATA_PER_TXD; 8020 8021 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8022 } 8023 8024 if (likely(!data_len)) 8025 break; 8026 8027 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8028 8029 i++; 8030 tx_desc++; 8031 if (i == tx_ring->count) { 8032 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8033 i = 0; 8034 } 8035 tx_desc->read.olinfo_status = 0; 8036 8037 #ifdef IXGBE_FCOE 8038 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8039 #else 8040 size = skb_frag_size(frag); 8041 #endif 8042 data_len -= size; 8043 8044 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8045 DMA_TO_DEVICE); 8046 8047 tx_buffer = &tx_ring->tx_buffer_info[i]; 8048 } 8049 8050 /* write last descriptor with RS and EOP bits */ 8051 cmd_type |= size | IXGBE_TXD_CMD; 8052 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8053 8054 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8055 8056 /* set the timestamp */ 8057 first->time_stamp = jiffies; 8058 8059 /* 8060 * Force memory writes to complete before letting h/w know there 8061 * are new descriptors to fetch. (Only applicable for weak-ordered 8062 * memory model archs, such as IA-64). 8063 * 8064 * We also need this memory barrier to make certain all of the 8065 * status bits have been updated before next_to_watch is written. 8066 */ 8067 wmb(); 8068 8069 /* set next_to_watch value indicating a packet is present */ 8070 first->next_to_watch = tx_desc; 8071 8072 i++; 8073 if (i == tx_ring->count) 8074 i = 0; 8075 8076 tx_ring->next_to_use = i; 8077 8078 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8079 8080 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { 8081 writel(i, tx_ring->tail); 8082 8083 /* we need this if more than one processor can write to our tail 8084 * at a time, it synchronizes IO on IA64/Altix systems 8085 */ 8086 mmiowb(); 8087 } 8088 8089 return 0; 8090 dma_error: 8091 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8092 8093 /* clear dma mappings for failed tx_buffer_info map */ 8094 for (;;) { 8095 tx_buffer = &tx_ring->tx_buffer_info[i]; 8096 if (dma_unmap_len(tx_buffer, len)) 8097 dma_unmap_page(tx_ring->dev, 8098 dma_unmap_addr(tx_buffer, dma), 8099 dma_unmap_len(tx_buffer, len), 8100 DMA_TO_DEVICE); 8101 dma_unmap_len_set(tx_buffer, len, 0); 8102 if (tx_buffer == first) 8103 break; 8104 if (i == 0) 8105 i += tx_ring->count; 8106 i--; 8107 } 8108 8109 dev_kfree_skb_any(first->skb); 8110 first->skb = NULL; 8111 8112 tx_ring->next_to_use = i; 8113 8114 return -1; 8115 } 8116 8117 static void ixgbe_atr(struct ixgbe_ring *ring, 8118 struct ixgbe_tx_buffer *first) 8119 { 8120 struct ixgbe_q_vector *q_vector = ring->q_vector; 8121 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8122 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8123 union { 8124 unsigned char *network; 8125 struct iphdr *ipv4; 8126 struct ipv6hdr *ipv6; 8127 } hdr; 8128 struct tcphdr *th; 8129 unsigned int hlen; 8130 struct sk_buff *skb; 8131 __be16 vlan_id; 8132 int l4_proto; 8133 8134 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8135 if (!q_vector) 8136 return; 8137 8138 /* do nothing if sampling is disabled */ 8139 if (!ring->atr_sample_rate) 8140 return; 8141 8142 ring->atr_count++; 8143 8144 /* currently only IPv4/IPv6 with TCP is supported */ 8145 if ((first->protocol != htons(ETH_P_IP)) && 8146 (first->protocol != htons(ETH_P_IPV6))) 8147 return; 8148 8149 /* snag network header to get L4 type and address */ 8150 skb = first->skb; 8151 hdr.network = skb_network_header(skb); 8152 if (unlikely(hdr.network <= skb->data)) 8153 return; 8154 if (skb->encapsulation && 8155 first->protocol == htons(ETH_P_IP) && 8156 hdr.ipv4->protocol == IPPROTO_UDP) { 8157 struct ixgbe_adapter *adapter = q_vector->adapter; 8158 8159 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8160 VXLAN_HEADROOM)) 8161 return; 8162 8163 /* verify the port is recognized as VXLAN */ 8164 if (adapter->vxlan_port && 8165 udp_hdr(skb)->dest == adapter->vxlan_port) 8166 hdr.network = skb_inner_network_header(skb); 8167 8168 if (adapter->geneve_port && 8169 udp_hdr(skb)->dest == adapter->geneve_port) 8170 hdr.network = skb_inner_network_header(skb); 8171 } 8172 8173 /* Make sure we have at least [minimum IPv4 header + TCP] 8174 * or [IPv6 header] bytes 8175 */ 8176 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8177 return; 8178 8179 /* Currently only IPv4/IPv6 with TCP is supported */ 8180 switch (hdr.ipv4->version) { 8181 case IPVERSION: 8182 /* access ihl as u8 to avoid unaligned access on ia64 */ 8183 hlen = (hdr.network[0] & 0x0F) << 2; 8184 l4_proto = hdr.ipv4->protocol; 8185 break; 8186 case 6: 8187 hlen = hdr.network - skb->data; 8188 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8189 hlen -= hdr.network - skb->data; 8190 break; 8191 default: 8192 return; 8193 } 8194 8195 if (l4_proto != IPPROTO_TCP) 8196 return; 8197 8198 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8199 hlen + sizeof(struct tcphdr))) 8200 return; 8201 8202 th = (struct tcphdr *)(hdr.network + hlen); 8203 8204 /* skip this packet since the socket is closing */ 8205 if (th->fin) 8206 return; 8207 8208 /* sample on all syn packets or once every atr sample count */ 8209 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8210 return; 8211 8212 /* reset sample count */ 8213 ring->atr_count = 0; 8214 8215 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8216 8217 /* 8218 * src and dst are inverted, think how the receiver sees them 8219 * 8220 * The input is broken into two sections, a non-compressed section 8221 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8222 * is XORed together and stored in the compressed dword. 8223 */ 8224 input.formatted.vlan_id = vlan_id; 8225 8226 /* 8227 * since src port and flex bytes occupy the same word XOR them together 8228 * and write the value to source port portion of compressed dword 8229 */ 8230 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8231 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8232 else 8233 common.port.src ^= th->dest ^ first->protocol; 8234 common.port.dst ^= th->source; 8235 8236 switch (hdr.ipv4->version) { 8237 case IPVERSION: 8238 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8239 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8240 break; 8241 case 6: 8242 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8243 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8244 hdr.ipv6->saddr.s6_addr32[1] ^ 8245 hdr.ipv6->saddr.s6_addr32[2] ^ 8246 hdr.ipv6->saddr.s6_addr32[3] ^ 8247 hdr.ipv6->daddr.s6_addr32[0] ^ 8248 hdr.ipv6->daddr.s6_addr32[1] ^ 8249 hdr.ipv6->daddr.s6_addr32[2] ^ 8250 hdr.ipv6->daddr.s6_addr32[3]; 8251 break; 8252 default: 8253 break; 8254 } 8255 8256 if (hdr.network != skb_network_header(skb)) 8257 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8258 8259 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8260 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8261 input, common, ring->queue_index); 8262 } 8263 8264 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8265 void *accel_priv, select_queue_fallback_t fallback) 8266 { 8267 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; 8268 struct ixgbe_adapter *adapter; 8269 int txq; 8270 #ifdef IXGBE_FCOE 8271 struct ixgbe_ring_feature *f; 8272 #endif 8273 8274 if (fwd_adapter) { 8275 adapter = netdev_priv(dev); 8276 txq = reciprocal_scale(skb_get_hash(skb), 8277 adapter->num_rx_queues_per_pool); 8278 8279 return txq + fwd_adapter->tx_base_queue; 8280 } 8281 8282 #ifdef IXGBE_FCOE 8283 8284 /* 8285 * only execute the code below if protocol is FCoE 8286 * or FIP and we have FCoE enabled on the adapter 8287 */ 8288 switch (vlan_get_protocol(skb)) { 8289 case htons(ETH_P_FCOE): 8290 case htons(ETH_P_FIP): 8291 adapter = netdev_priv(dev); 8292 8293 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) 8294 break; 8295 /* fall through */ 8296 default: 8297 return fallback(dev, skb); 8298 } 8299 8300 f = &adapter->ring_feature[RING_F_FCOE]; 8301 8302 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8303 smp_processor_id(); 8304 8305 while (txq >= f->indices) 8306 txq -= f->indices; 8307 8308 return txq + f->offset; 8309 #else 8310 return fallback(dev, skb); 8311 #endif 8312 } 8313 8314 static int ixgbe_xmit_xdp_ring(struct ixgbe_adapter *adapter, 8315 struct xdp_buff *xdp) 8316 { 8317 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 8318 struct ixgbe_tx_buffer *tx_buffer; 8319 union ixgbe_adv_tx_desc *tx_desc; 8320 u32 len, cmd_type; 8321 dma_addr_t dma; 8322 u16 i; 8323 8324 len = xdp->data_end - xdp->data; 8325 8326 if (unlikely(!ixgbe_desc_unused(ring))) 8327 return IXGBE_XDP_CONSUMED; 8328 8329 dma = dma_map_single(ring->dev, xdp->data, len, DMA_TO_DEVICE); 8330 if (dma_mapping_error(ring->dev, dma)) 8331 return IXGBE_XDP_CONSUMED; 8332 8333 /* record the location of the first descriptor for this packet */ 8334 tx_buffer = &ring->tx_buffer_info[ring->next_to_use]; 8335 tx_buffer->bytecount = len; 8336 tx_buffer->gso_segs = 1; 8337 tx_buffer->protocol = 0; 8338 8339 i = ring->next_to_use; 8340 tx_desc = IXGBE_TX_DESC(ring, i); 8341 8342 dma_unmap_len_set(tx_buffer, len, len); 8343 dma_unmap_addr_set(tx_buffer, dma, dma); 8344 tx_buffer->data = xdp->data; 8345 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8346 8347 /* put descriptor type bits */ 8348 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8349 IXGBE_ADVTXD_DCMD_DEXT | 8350 IXGBE_ADVTXD_DCMD_IFCS; 8351 cmd_type |= len | IXGBE_TXD_CMD; 8352 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8353 tx_desc->read.olinfo_status = 8354 cpu_to_le32(len << IXGBE_ADVTXD_PAYLEN_SHIFT); 8355 8356 /* Avoid any potential race with xdp_xmit and cleanup */ 8357 smp_wmb(); 8358 8359 /* set next_to_watch value indicating a packet is present */ 8360 i++; 8361 if (i == ring->count) 8362 i = 0; 8363 8364 tx_buffer->next_to_watch = tx_desc; 8365 ring->next_to_use = i; 8366 8367 return IXGBE_XDP_TX; 8368 } 8369 8370 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8371 struct ixgbe_adapter *adapter, 8372 struct ixgbe_ring *tx_ring) 8373 { 8374 struct ixgbe_tx_buffer *first; 8375 int tso; 8376 u32 tx_flags = 0; 8377 unsigned short f; 8378 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8379 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8380 __be16 protocol = skb->protocol; 8381 u8 hdr_len = 0; 8382 8383 /* 8384 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8385 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8386 * + 2 desc gap to keep tail from touching head, 8387 * + 1 desc for context descriptor, 8388 * otherwise try next time 8389 */ 8390 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8391 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 8392 8393 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8394 tx_ring->tx_stats.tx_busy++; 8395 return NETDEV_TX_BUSY; 8396 } 8397 8398 /* record the location of the first descriptor for this packet */ 8399 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8400 first->skb = skb; 8401 first->bytecount = skb->len; 8402 first->gso_segs = 1; 8403 8404 /* if we have a HW VLAN tag being added default to the HW one */ 8405 if (skb_vlan_tag_present(skb)) { 8406 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8407 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8408 /* else if it is a SW VLAN check the next protocol and store the tag */ 8409 } else if (protocol == htons(ETH_P_8021Q)) { 8410 struct vlan_hdr *vhdr, _vhdr; 8411 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8412 if (!vhdr) 8413 goto out_drop; 8414 8415 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8416 IXGBE_TX_FLAGS_VLAN_SHIFT; 8417 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8418 } 8419 protocol = vlan_get_protocol(skb); 8420 8421 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8422 adapter->ptp_clock) { 8423 if (!test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8424 &adapter->state)) { 8425 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8426 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8427 8428 /* schedule check for Tx timestamp */ 8429 adapter->ptp_tx_skb = skb_get(skb); 8430 adapter->ptp_tx_start = jiffies; 8431 schedule_work(&adapter->ptp_tx_work); 8432 } else { 8433 adapter->tx_hwtstamp_skipped++; 8434 } 8435 } 8436 8437 skb_tx_timestamp(skb); 8438 8439 #ifdef CONFIG_PCI_IOV 8440 /* 8441 * Use the l2switch_enable flag - would be false if the DMA 8442 * Tx switch had been disabled. 8443 */ 8444 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8445 tx_flags |= IXGBE_TX_FLAGS_CC; 8446 8447 #endif 8448 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8449 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8450 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8451 (skb->priority != TC_PRIO_CONTROL))) { 8452 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8453 tx_flags |= (skb->priority & 0x7) << 8454 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8455 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8456 struct vlan_ethhdr *vhdr; 8457 8458 if (skb_cow_head(skb, 0)) 8459 goto out_drop; 8460 vhdr = (struct vlan_ethhdr *)skb->data; 8461 vhdr->h_vlan_TCI = htons(tx_flags >> 8462 IXGBE_TX_FLAGS_VLAN_SHIFT); 8463 } else { 8464 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8465 } 8466 } 8467 8468 /* record initial flags and protocol */ 8469 first->tx_flags = tx_flags; 8470 first->protocol = protocol; 8471 8472 #ifdef IXGBE_FCOE 8473 /* setup tx offload for FCoE */ 8474 if ((protocol == htons(ETH_P_FCOE)) && 8475 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8476 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8477 if (tso < 0) 8478 goto out_drop; 8479 8480 goto xmit_fcoe; 8481 } 8482 8483 #endif /* IXGBE_FCOE */ 8484 8485 #ifdef CONFIG_XFRM_OFFLOAD 8486 if (skb->sp && !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8487 goto out_drop; 8488 #endif 8489 tso = ixgbe_tso(tx_ring, first, &hdr_len); 8490 if (tso < 0) 8491 goto out_drop; 8492 else if (!tso) 8493 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8494 8495 /* add the ATR filter if ATR is on */ 8496 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8497 ixgbe_atr(tx_ring, first); 8498 8499 #ifdef IXGBE_FCOE 8500 xmit_fcoe: 8501 #endif /* IXGBE_FCOE */ 8502 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8503 goto cleanup_tx_timestamp; 8504 8505 return NETDEV_TX_OK; 8506 8507 out_drop: 8508 dev_kfree_skb_any(first->skb); 8509 first->skb = NULL; 8510 cleanup_tx_timestamp: 8511 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8512 dev_kfree_skb_any(adapter->ptp_tx_skb); 8513 adapter->ptp_tx_skb = NULL; 8514 cancel_work_sync(&adapter->ptp_tx_work); 8515 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8516 } 8517 8518 return NETDEV_TX_OK; 8519 } 8520 8521 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8522 struct net_device *netdev, 8523 struct ixgbe_ring *ring) 8524 { 8525 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8526 struct ixgbe_ring *tx_ring; 8527 8528 /* 8529 * The minimum packet size for olinfo paylen is 17 so pad the skb 8530 * in order to meet this minimum size requirement. 8531 */ 8532 if (skb_put_padto(skb, 17)) 8533 return NETDEV_TX_OK; 8534 8535 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; 8536 8537 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8538 } 8539 8540 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8541 struct net_device *netdev) 8542 { 8543 return __ixgbe_xmit_frame(skb, netdev, NULL); 8544 } 8545 8546 /** 8547 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8548 * @netdev: network interface device structure 8549 * @p: pointer to an address structure 8550 * 8551 * Returns 0 on success, negative on failure 8552 **/ 8553 static int ixgbe_set_mac(struct net_device *netdev, void *p) 8554 { 8555 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8556 struct ixgbe_hw *hw = &adapter->hw; 8557 struct sockaddr *addr = p; 8558 8559 if (!is_valid_ether_addr(addr->sa_data)) 8560 return -EADDRNOTAVAIL; 8561 8562 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 8563 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8564 8565 ixgbe_mac_set_default_filter(adapter); 8566 8567 return 0; 8568 } 8569 8570 static int 8571 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8572 { 8573 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8574 struct ixgbe_hw *hw = &adapter->hw; 8575 u16 value; 8576 int rc; 8577 8578 if (prtad != hw->phy.mdio.prtad) 8579 return -EINVAL; 8580 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8581 if (!rc) 8582 rc = value; 8583 return rc; 8584 } 8585 8586 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8587 u16 addr, u16 value) 8588 { 8589 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8590 struct ixgbe_hw *hw = &adapter->hw; 8591 8592 if (prtad != hw->phy.mdio.prtad) 8593 return -EINVAL; 8594 return hw->phy.ops.write_reg(hw, addr, devad, value); 8595 } 8596 8597 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8598 { 8599 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8600 8601 switch (cmd) { 8602 case SIOCSHWTSTAMP: 8603 return ixgbe_ptp_set_ts_config(adapter, req); 8604 case SIOCGHWTSTAMP: 8605 return ixgbe_ptp_get_ts_config(adapter, req); 8606 case SIOCGMIIPHY: 8607 if (!adapter->hw.phy.ops.read_reg) 8608 return -EOPNOTSUPP; 8609 /* fall through */ 8610 default: 8611 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 8612 } 8613 } 8614 8615 /** 8616 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 8617 * netdev->dev_addrs 8618 * @dev: network interface device structure 8619 * 8620 * Returns non-zero on failure 8621 **/ 8622 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 8623 { 8624 int err = 0; 8625 struct ixgbe_adapter *adapter = netdev_priv(dev); 8626 struct ixgbe_hw *hw = &adapter->hw; 8627 8628 if (is_valid_ether_addr(hw->mac.san_addr)) { 8629 rtnl_lock(); 8630 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 8631 rtnl_unlock(); 8632 8633 /* update SAN MAC vmdq pool selection */ 8634 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 8635 } 8636 return err; 8637 } 8638 8639 /** 8640 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 8641 * netdev->dev_addrs 8642 * @dev: network interface device structure 8643 * 8644 * Returns non-zero on failure 8645 **/ 8646 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 8647 { 8648 int err = 0; 8649 struct ixgbe_adapter *adapter = netdev_priv(dev); 8650 struct ixgbe_mac_info *mac = &adapter->hw.mac; 8651 8652 if (is_valid_ether_addr(mac->san_addr)) { 8653 rtnl_lock(); 8654 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 8655 rtnl_unlock(); 8656 } 8657 return err; 8658 } 8659 8660 #ifdef CONFIG_NET_POLL_CONTROLLER 8661 /* 8662 * Polling 'interrupt' - used by things like netconsole to send skbs 8663 * without having to re-enable interrupts. It's not called while 8664 * the interrupt routine is executing. 8665 */ 8666 static void ixgbe_netpoll(struct net_device *netdev) 8667 { 8668 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8669 int i; 8670 8671 /* if interface is down do nothing */ 8672 if (test_bit(__IXGBE_DOWN, &adapter->state)) 8673 return; 8674 8675 /* loop through and schedule all active queues */ 8676 for (i = 0; i < adapter->num_q_vectors; i++) 8677 ixgbe_msix_clean_rings(0, adapter->q_vector[i]); 8678 } 8679 8680 #endif 8681 8682 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 8683 struct ixgbe_ring *ring) 8684 { 8685 u64 bytes, packets; 8686 unsigned int start; 8687 8688 if (ring) { 8689 do { 8690 start = u64_stats_fetch_begin_irq(&ring->syncp); 8691 packets = ring->stats.packets; 8692 bytes = ring->stats.bytes; 8693 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8694 stats->tx_packets += packets; 8695 stats->tx_bytes += bytes; 8696 } 8697 } 8698 8699 static void ixgbe_get_stats64(struct net_device *netdev, 8700 struct rtnl_link_stats64 *stats) 8701 { 8702 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8703 int i; 8704 8705 rcu_read_lock(); 8706 for (i = 0; i < adapter->num_rx_queues; i++) { 8707 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 8708 u64 bytes, packets; 8709 unsigned int start; 8710 8711 if (ring) { 8712 do { 8713 start = u64_stats_fetch_begin_irq(&ring->syncp); 8714 packets = ring->stats.packets; 8715 bytes = ring->stats.bytes; 8716 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 8717 stats->rx_packets += packets; 8718 stats->rx_bytes += bytes; 8719 } 8720 } 8721 8722 for (i = 0; i < adapter->num_tx_queues; i++) { 8723 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 8724 8725 ixgbe_get_ring_stats64(stats, ring); 8726 } 8727 for (i = 0; i < adapter->num_xdp_queues; i++) { 8728 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 8729 8730 ixgbe_get_ring_stats64(stats, ring); 8731 } 8732 rcu_read_unlock(); 8733 8734 /* following stats updated by ixgbe_watchdog_task() */ 8735 stats->multicast = netdev->stats.multicast; 8736 stats->rx_errors = netdev->stats.rx_errors; 8737 stats->rx_length_errors = netdev->stats.rx_length_errors; 8738 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 8739 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 8740 } 8741 8742 #ifdef CONFIG_IXGBE_DCB 8743 /** 8744 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 8745 * @adapter: pointer to ixgbe_adapter 8746 * @tc: number of traffic classes currently enabled 8747 * 8748 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 8749 * 802.1Q priority maps to a packet buffer that exists. 8750 */ 8751 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 8752 { 8753 struct ixgbe_hw *hw = &adapter->hw; 8754 u32 reg, rsave; 8755 int i; 8756 8757 /* 82598 have a static priority to TC mapping that can not 8758 * be changed so no validation is needed. 8759 */ 8760 if (hw->mac.type == ixgbe_mac_82598EB) 8761 return; 8762 8763 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 8764 rsave = reg; 8765 8766 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 8767 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 8768 8769 /* If up2tc is out of bounds default to zero */ 8770 if (up2tc > tc) 8771 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 8772 } 8773 8774 if (reg != rsave) 8775 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 8776 8777 return; 8778 } 8779 8780 /** 8781 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 8782 * @adapter: Pointer to adapter struct 8783 * 8784 * Populate the netdev user priority to tc map 8785 */ 8786 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 8787 { 8788 struct net_device *dev = adapter->netdev; 8789 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 8790 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 8791 u8 prio; 8792 8793 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 8794 u8 tc = 0; 8795 8796 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 8797 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 8798 else if (ets) 8799 tc = ets->prio_tc[prio]; 8800 8801 netdev_set_prio_tc_map(dev, prio, tc); 8802 } 8803 } 8804 8805 #endif /* CONFIG_IXGBE_DCB */ 8806 /** 8807 * ixgbe_setup_tc - configure net_device for multiple traffic classes 8808 * 8809 * @dev: net device to configure 8810 * @tc: number of traffic classes to enable 8811 */ 8812 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 8813 { 8814 struct ixgbe_adapter *adapter = netdev_priv(dev); 8815 struct ixgbe_hw *hw = &adapter->hw; 8816 8817 /* Hardware supports up to 8 traffic classes */ 8818 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 8819 return -EINVAL; 8820 8821 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 8822 return -EINVAL; 8823 8824 /* Hardware has to reinitialize queues and interrupts to 8825 * match packet buffer alignment. Unfortunately, the 8826 * hardware is not flexible enough to do this dynamically. 8827 */ 8828 if (netif_running(dev)) 8829 ixgbe_close(dev); 8830 else 8831 ixgbe_reset(adapter); 8832 8833 ixgbe_clear_interrupt_scheme(adapter); 8834 8835 #ifdef CONFIG_IXGBE_DCB 8836 if (tc) { 8837 netdev_set_num_tc(dev, tc); 8838 ixgbe_set_prio_tc_map(adapter); 8839 8840 adapter->hw_tcs = tc; 8841 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 8842 8843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 8844 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 8845 adapter->hw.fc.requested_mode = ixgbe_fc_none; 8846 } 8847 } else { 8848 netdev_reset_tc(dev); 8849 8850 /* To support macvlan offload we have to use num_tc to 8851 * restrict the queues that can be used by the device. 8852 * By doing this we can avoid reporting a false number of 8853 * queues. 8854 */ 8855 if (!tc && adapter->num_rx_pools > 1) 8856 netdev_set_num_tc(dev, 1); 8857 8858 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 8859 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 8860 8861 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 8862 adapter->hw_tcs = tc; 8863 8864 adapter->temp_dcb_cfg.pfc_mode_enable = false; 8865 adapter->dcb_cfg.pfc_mode_enable = false; 8866 } 8867 8868 ixgbe_validate_rtr(adapter, tc); 8869 8870 #endif /* CONFIG_IXGBE_DCB */ 8871 ixgbe_init_interrupt_scheme(adapter); 8872 8873 if (netif_running(dev)) 8874 return ixgbe_open(dev); 8875 8876 return 0; 8877 } 8878 8879 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 8880 struct tc_cls_u32_offload *cls) 8881 { 8882 u32 hdl = cls->knode.handle; 8883 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 8884 u32 loc = cls->knode.handle & 0xfffff; 8885 int err = 0, i, j; 8886 struct ixgbe_jump_table *jump = NULL; 8887 8888 if (loc > IXGBE_MAX_HW_ENTRIES) 8889 return -EINVAL; 8890 8891 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 8892 return -EINVAL; 8893 8894 /* Clear this filter in the link data it is associated with */ 8895 if (uhtid != 0x800) { 8896 jump = adapter->jump_tables[uhtid]; 8897 if (!jump) 8898 return -EINVAL; 8899 if (!test_bit(loc - 1, jump->child_loc_map)) 8900 return -EINVAL; 8901 clear_bit(loc - 1, jump->child_loc_map); 8902 } 8903 8904 /* Check if the filter being deleted is a link */ 8905 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 8906 jump = adapter->jump_tables[i]; 8907 if (jump && jump->link_hdl == hdl) { 8908 /* Delete filters in the hardware in the child hash 8909 * table associated with this link 8910 */ 8911 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 8912 if (!test_bit(j, jump->child_loc_map)) 8913 continue; 8914 spin_lock(&adapter->fdir_perfect_lock); 8915 err = ixgbe_update_ethtool_fdir_entry(adapter, 8916 NULL, 8917 j + 1); 8918 spin_unlock(&adapter->fdir_perfect_lock); 8919 clear_bit(j, jump->child_loc_map); 8920 } 8921 /* Remove resources for this link */ 8922 kfree(jump->input); 8923 kfree(jump->mask); 8924 kfree(jump); 8925 adapter->jump_tables[i] = NULL; 8926 return err; 8927 } 8928 } 8929 8930 spin_lock(&adapter->fdir_perfect_lock); 8931 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 8932 spin_unlock(&adapter->fdir_perfect_lock); 8933 return err; 8934 } 8935 8936 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 8937 struct tc_cls_u32_offload *cls) 8938 { 8939 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8940 8941 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8942 return -EINVAL; 8943 8944 /* This ixgbe devices do not support hash tables at the moment 8945 * so abort when given hash tables. 8946 */ 8947 if (cls->hnode.divisor > 0) 8948 return -EINVAL; 8949 8950 set_bit(uhtid - 1, &adapter->tables); 8951 return 0; 8952 } 8953 8954 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 8955 struct tc_cls_u32_offload *cls) 8956 { 8957 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 8958 8959 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 8960 return -EINVAL; 8961 8962 clear_bit(uhtid - 1, &adapter->tables); 8963 return 0; 8964 } 8965 8966 #ifdef CONFIG_NET_CLS_ACT 8967 struct upper_walk_data { 8968 struct ixgbe_adapter *adapter; 8969 u64 action; 8970 int ifindex; 8971 u8 queue; 8972 }; 8973 8974 static int get_macvlan_queue(struct net_device *upper, void *_data) 8975 { 8976 if (netif_is_macvlan(upper)) { 8977 struct macvlan_dev *dfwd = netdev_priv(upper); 8978 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; 8979 struct upper_walk_data *data = _data; 8980 struct ixgbe_adapter *adapter = data->adapter; 8981 int ifindex = data->ifindex; 8982 8983 if (vadapter && vadapter->netdev->ifindex == ifindex) { 8984 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 8985 data->action = data->queue; 8986 return 1; 8987 } 8988 } 8989 8990 return 0; 8991 } 8992 8993 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 8994 u8 *queue, u64 *action) 8995 { 8996 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 8997 unsigned int num_vfs = adapter->num_vfs, vf; 8998 struct upper_walk_data data; 8999 struct net_device *upper; 9000 9001 /* redirect to a SRIOV VF */ 9002 for (vf = 0; vf < num_vfs; ++vf) { 9003 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9004 if (upper->ifindex == ifindex) { 9005 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9006 *action = vf + 1; 9007 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9008 return 0; 9009 } 9010 } 9011 9012 /* redirect to a offloaded macvlan netdev */ 9013 data.adapter = adapter; 9014 data.ifindex = ifindex; 9015 data.action = 0; 9016 data.queue = 0; 9017 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9018 get_macvlan_queue, &data)) { 9019 *action = data.action; 9020 *queue = data.queue; 9021 9022 return 0; 9023 } 9024 9025 return -EINVAL; 9026 } 9027 9028 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9029 struct tcf_exts *exts, u64 *action, u8 *queue) 9030 { 9031 const struct tc_action *a; 9032 LIST_HEAD(actions); 9033 int err; 9034 9035 if (!tcf_exts_has_actions(exts)) 9036 return -EINVAL; 9037 9038 tcf_exts_to_list(exts, &actions); 9039 list_for_each_entry(a, &actions, list) { 9040 9041 /* Drop action */ 9042 if (is_tcf_gact_shot(a)) { 9043 *action = IXGBE_FDIR_DROP_QUEUE; 9044 *queue = IXGBE_FDIR_DROP_QUEUE; 9045 return 0; 9046 } 9047 9048 /* Redirect to a VF or a offloaded macvlan */ 9049 if (is_tcf_mirred_egress_redirect(a)) { 9050 struct net_device *dev = tcf_mirred_dev(a); 9051 9052 if (!dev) 9053 return -EINVAL; 9054 err = handle_redirect_action(adapter, dev->ifindex, queue, 9055 action); 9056 if (err == 0) 9057 return err; 9058 } 9059 } 9060 9061 return -EINVAL; 9062 } 9063 #else 9064 static int parse_tc_actions(struct ixgbe_adapter *adapter, 9065 struct tcf_exts *exts, u64 *action, u8 *queue) 9066 { 9067 return -EINVAL; 9068 } 9069 #endif /* CONFIG_NET_CLS_ACT */ 9070 9071 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9072 union ixgbe_atr_input *mask, 9073 struct tc_cls_u32_offload *cls, 9074 struct ixgbe_mat_field *field_ptr, 9075 struct ixgbe_nexthdr *nexthdr) 9076 { 9077 int i, j, off; 9078 __be32 val, m; 9079 bool found_entry = false, found_jump_field = false; 9080 9081 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9082 off = cls->knode.sel->keys[i].off; 9083 val = cls->knode.sel->keys[i].val; 9084 m = cls->knode.sel->keys[i].mask; 9085 9086 for (j = 0; field_ptr[j].val; j++) { 9087 if (field_ptr[j].off == off) { 9088 field_ptr[j].val(input, mask, val, m); 9089 input->filter.formatted.flow_type |= 9090 field_ptr[j].type; 9091 found_entry = true; 9092 break; 9093 } 9094 } 9095 if (nexthdr) { 9096 if (nexthdr->off == cls->knode.sel->keys[i].off && 9097 nexthdr->val == cls->knode.sel->keys[i].val && 9098 nexthdr->mask == cls->knode.sel->keys[i].mask) 9099 found_jump_field = true; 9100 else 9101 continue; 9102 } 9103 } 9104 9105 if (nexthdr && !found_jump_field) 9106 return -EINVAL; 9107 9108 if (!found_entry) 9109 return 0; 9110 9111 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9112 IXGBE_ATR_L4TYPE_MASK; 9113 9114 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9115 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9116 9117 return 0; 9118 } 9119 9120 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9121 struct tc_cls_u32_offload *cls) 9122 { 9123 __be16 protocol = cls->common.protocol; 9124 u32 loc = cls->knode.handle & 0xfffff; 9125 struct ixgbe_hw *hw = &adapter->hw; 9126 struct ixgbe_mat_field *field_ptr; 9127 struct ixgbe_fdir_filter *input = NULL; 9128 union ixgbe_atr_input *mask = NULL; 9129 struct ixgbe_jump_table *jump = NULL; 9130 int i, err = -EINVAL; 9131 u8 queue; 9132 u32 uhtid, link_uhtid; 9133 9134 uhtid = TC_U32_USERHTID(cls->knode.handle); 9135 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9136 9137 /* At the moment cls_u32 jumps to network layer and skips past 9138 * L2 headers. The canonical method to match L2 frames is to use 9139 * negative values. However this is error prone at best but really 9140 * just broken because there is no way to "know" what sort of hdr 9141 * is in front of the network layer. Fix cls_u32 to support L2 9142 * headers when needed. 9143 */ 9144 if (protocol != htons(ETH_P_IP)) 9145 return err; 9146 9147 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9148 e_err(drv, "Location out of range\n"); 9149 return err; 9150 } 9151 9152 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9153 * links and also the fields used to advance the parser across each 9154 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9155 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9156 * To add support for new nodes update ixgbe_model.h parse structures 9157 * this function _should_ be generic try not to hardcode values here. 9158 */ 9159 if (uhtid == 0x800) { 9160 field_ptr = (adapter->jump_tables[0])->mat; 9161 } else { 9162 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9163 return err; 9164 if (!adapter->jump_tables[uhtid]) 9165 return err; 9166 field_ptr = (adapter->jump_tables[uhtid])->mat; 9167 } 9168 9169 if (!field_ptr) 9170 return err; 9171 9172 /* At this point we know the field_ptr is valid and need to either 9173 * build cls_u32 link or attach filter. Because adding a link to 9174 * a handle that does not exist is invalid and the same for adding 9175 * rules to handles that don't exist. 9176 */ 9177 9178 if (link_uhtid) { 9179 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9180 9181 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9182 return err; 9183 9184 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9185 return err; 9186 9187 /* Multiple filters as links to the same hash table are not 9188 * supported. To add a new filter with the same next header 9189 * but different match/jump conditions, create a new hash table 9190 * and link to it. 9191 */ 9192 if (adapter->jump_tables[link_uhtid] && 9193 (adapter->jump_tables[link_uhtid])->link_hdl) { 9194 e_err(drv, "Link filter exists for link: %x\n", 9195 link_uhtid); 9196 return err; 9197 } 9198 9199 for (i = 0; nexthdr[i].jump; i++) { 9200 if (nexthdr[i].o != cls->knode.sel->offoff || 9201 nexthdr[i].s != cls->knode.sel->offshift || 9202 nexthdr[i].m != cls->knode.sel->offmask) 9203 return err; 9204 9205 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9206 if (!jump) 9207 return -ENOMEM; 9208 input = kzalloc(sizeof(*input), GFP_KERNEL); 9209 if (!input) { 9210 err = -ENOMEM; 9211 goto free_jump; 9212 } 9213 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9214 if (!mask) { 9215 err = -ENOMEM; 9216 goto free_input; 9217 } 9218 jump->input = input; 9219 jump->mask = mask; 9220 jump->link_hdl = cls->knode.handle; 9221 9222 err = ixgbe_clsu32_build_input(input, mask, cls, 9223 field_ptr, &nexthdr[i]); 9224 if (!err) { 9225 jump->mat = nexthdr[i].jump; 9226 adapter->jump_tables[link_uhtid] = jump; 9227 break; 9228 } 9229 } 9230 return 0; 9231 } 9232 9233 input = kzalloc(sizeof(*input), GFP_KERNEL); 9234 if (!input) 9235 return -ENOMEM; 9236 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9237 if (!mask) { 9238 err = -ENOMEM; 9239 goto free_input; 9240 } 9241 9242 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9243 if ((adapter->jump_tables[uhtid])->input) 9244 memcpy(input, (adapter->jump_tables[uhtid])->input, 9245 sizeof(*input)); 9246 if ((adapter->jump_tables[uhtid])->mask) 9247 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9248 sizeof(*mask)); 9249 9250 /* Lookup in all child hash tables if this location is already 9251 * filled with a filter 9252 */ 9253 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9254 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9255 9256 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9257 e_err(drv, "Filter exists in location: %x\n", 9258 loc); 9259 err = -EINVAL; 9260 goto err_out; 9261 } 9262 } 9263 } 9264 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9265 if (err) 9266 goto err_out; 9267 9268 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9269 &queue); 9270 if (err < 0) 9271 goto err_out; 9272 9273 input->sw_idx = loc; 9274 9275 spin_lock(&adapter->fdir_perfect_lock); 9276 9277 if (hlist_empty(&adapter->fdir_filter_list)) { 9278 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9279 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9280 if (err) 9281 goto err_out_w_lock; 9282 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9283 err = -EINVAL; 9284 goto err_out_w_lock; 9285 } 9286 9287 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9288 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9289 input->sw_idx, queue); 9290 if (!err) 9291 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9292 spin_unlock(&adapter->fdir_perfect_lock); 9293 9294 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9295 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9296 9297 kfree(mask); 9298 return err; 9299 err_out_w_lock: 9300 spin_unlock(&adapter->fdir_perfect_lock); 9301 err_out: 9302 kfree(mask); 9303 free_input: 9304 kfree(input); 9305 free_jump: 9306 kfree(jump); 9307 return err; 9308 } 9309 9310 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9311 struct tc_cls_u32_offload *cls_u32) 9312 { 9313 switch (cls_u32->command) { 9314 case TC_CLSU32_NEW_KNODE: 9315 case TC_CLSU32_REPLACE_KNODE: 9316 return ixgbe_configure_clsu32(adapter, cls_u32); 9317 case TC_CLSU32_DELETE_KNODE: 9318 return ixgbe_delete_clsu32(adapter, cls_u32); 9319 case TC_CLSU32_NEW_HNODE: 9320 case TC_CLSU32_REPLACE_HNODE: 9321 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9322 case TC_CLSU32_DELETE_HNODE: 9323 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9324 default: 9325 return -EOPNOTSUPP; 9326 } 9327 } 9328 9329 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9330 void *cb_priv) 9331 { 9332 struct ixgbe_adapter *adapter = cb_priv; 9333 9334 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9335 return -EOPNOTSUPP; 9336 9337 switch (type) { 9338 case TC_SETUP_CLSU32: 9339 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9340 default: 9341 return -EOPNOTSUPP; 9342 } 9343 } 9344 9345 static int ixgbe_setup_tc_block(struct net_device *dev, 9346 struct tc_block_offload *f) 9347 { 9348 struct ixgbe_adapter *adapter = netdev_priv(dev); 9349 9350 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 9351 return -EOPNOTSUPP; 9352 9353 switch (f->command) { 9354 case TC_BLOCK_BIND: 9355 return tcf_block_cb_register(f->block, ixgbe_setup_tc_block_cb, 9356 adapter, adapter); 9357 case TC_BLOCK_UNBIND: 9358 tcf_block_cb_unregister(f->block, ixgbe_setup_tc_block_cb, 9359 adapter); 9360 return 0; 9361 default: 9362 return -EOPNOTSUPP; 9363 } 9364 } 9365 9366 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9367 struct tc_mqprio_qopt *mqprio) 9368 { 9369 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9370 return ixgbe_setup_tc(dev, mqprio->num_tc); 9371 } 9372 9373 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9374 void *type_data) 9375 { 9376 switch (type) { 9377 case TC_SETUP_BLOCK: 9378 return ixgbe_setup_tc_block(dev, type_data); 9379 case TC_SETUP_QDISC_MQPRIO: 9380 return ixgbe_setup_tc_mqprio(dev, type_data); 9381 default: 9382 return -EOPNOTSUPP; 9383 } 9384 } 9385 9386 #ifdef CONFIG_PCI_IOV 9387 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9388 { 9389 struct net_device *netdev = adapter->netdev; 9390 9391 rtnl_lock(); 9392 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9393 rtnl_unlock(); 9394 } 9395 9396 #endif 9397 void ixgbe_do_reset(struct net_device *netdev) 9398 { 9399 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9400 9401 if (netif_running(netdev)) 9402 ixgbe_reinit_locked(adapter); 9403 else 9404 ixgbe_reset(adapter); 9405 } 9406 9407 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9408 netdev_features_t features) 9409 { 9410 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9411 9412 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9413 if (!(features & NETIF_F_RXCSUM)) 9414 features &= ~NETIF_F_LRO; 9415 9416 /* Turn off LRO if not RSC capable */ 9417 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9418 features &= ~NETIF_F_LRO; 9419 9420 return features; 9421 } 9422 9423 static int ixgbe_set_features(struct net_device *netdev, 9424 netdev_features_t features) 9425 { 9426 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9427 netdev_features_t changed = netdev->features ^ features; 9428 bool need_reset = false; 9429 9430 /* Make sure RSC matches LRO, reset if change */ 9431 if (!(features & NETIF_F_LRO)) { 9432 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9433 need_reset = true; 9434 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9435 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9436 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9437 if (adapter->rx_itr_setting == 1 || 9438 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9439 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9440 need_reset = true; 9441 } else if ((changed ^ features) & NETIF_F_LRO) { 9442 e_info(probe, "rx-usecs set too low, " 9443 "disabling RSC\n"); 9444 } 9445 } 9446 9447 /* 9448 * Check if Flow Director n-tuple support or hw_tc support was 9449 * enabled or disabled. If the state changed, we need to reset. 9450 */ 9451 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9452 /* turn off ATR, enable perfect filters and reset */ 9453 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9454 need_reset = true; 9455 9456 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9457 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9458 } else { 9459 /* turn off perfect filters, enable ATR and reset */ 9460 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9461 need_reset = true; 9462 9463 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9464 9465 /* We cannot enable ATR if SR-IOV is enabled */ 9466 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9467 /* We cannot enable ATR if we have 2 or more tcs */ 9468 (adapter->hw_tcs > 1) || 9469 /* We cannot enable ATR if RSS is disabled */ 9470 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9471 /* A sample rate of 0 indicates ATR disabled */ 9472 (!adapter->atr_sample_rate)) 9473 ; /* do nothing not supported */ 9474 else /* otherwise supported and set the flag */ 9475 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9476 } 9477 9478 if (changed & NETIF_F_RXALL) 9479 need_reset = true; 9480 9481 netdev->features = features; 9482 9483 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { 9484 if (features & NETIF_F_RXCSUM) { 9485 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9486 } else { 9487 u32 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9488 9489 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9490 } 9491 } 9492 9493 if ((adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) { 9494 if (features & NETIF_F_RXCSUM) { 9495 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9496 } else { 9497 u32 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9498 9499 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9500 } 9501 } 9502 9503 if (need_reset) 9504 ixgbe_do_reset(netdev); 9505 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9506 NETIF_F_HW_VLAN_CTAG_FILTER)) 9507 ixgbe_set_rx_mode(netdev); 9508 9509 return 0; 9510 } 9511 9512 /** 9513 * ixgbe_add_udp_tunnel_port - Get notifications about adding UDP tunnel ports 9514 * @dev: The port's netdev 9515 * @ti: Tunnel endpoint information 9516 **/ 9517 static void ixgbe_add_udp_tunnel_port(struct net_device *dev, 9518 struct udp_tunnel_info *ti) 9519 { 9520 struct ixgbe_adapter *adapter = netdev_priv(dev); 9521 struct ixgbe_hw *hw = &adapter->hw; 9522 __be16 port = ti->port; 9523 u32 port_shift = 0; 9524 u32 reg; 9525 9526 if (ti->sa_family != AF_INET) 9527 return; 9528 9529 switch (ti->type) { 9530 case UDP_TUNNEL_TYPE_VXLAN: 9531 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9532 return; 9533 9534 if (adapter->vxlan_port == port) 9535 return; 9536 9537 if (adapter->vxlan_port) { 9538 netdev_info(dev, 9539 "VXLAN port %d set, not adding port %d\n", 9540 ntohs(adapter->vxlan_port), 9541 ntohs(port)); 9542 return; 9543 } 9544 9545 adapter->vxlan_port = port; 9546 break; 9547 case UDP_TUNNEL_TYPE_GENEVE: 9548 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9549 return; 9550 9551 if (adapter->geneve_port == port) 9552 return; 9553 9554 if (adapter->geneve_port) { 9555 netdev_info(dev, 9556 "GENEVE port %d set, not adding port %d\n", 9557 ntohs(adapter->geneve_port), 9558 ntohs(port)); 9559 return; 9560 } 9561 9562 port_shift = IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT; 9563 adapter->geneve_port = port; 9564 break; 9565 default: 9566 return; 9567 } 9568 9569 reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; 9570 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); 9571 } 9572 9573 /** 9574 * ixgbe_del_udp_tunnel_port - Get notifications about removing UDP tunnel ports 9575 * @dev: The port's netdev 9576 * @ti: Tunnel endpoint information 9577 **/ 9578 static void ixgbe_del_udp_tunnel_port(struct net_device *dev, 9579 struct udp_tunnel_info *ti) 9580 { 9581 struct ixgbe_adapter *adapter = netdev_priv(dev); 9582 u32 port_mask; 9583 9584 if (ti->type != UDP_TUNNEL_TYPE_VXLAN && 9585 ti->type != UDP_TUNNEL_TYPE_GENEVE) 9586 return; 9587 9588 if (ti->sa_family != AF_INET) 9589 return; 9590 9591 switch (ti->type) { 9592 case UDP_TUNNEL_TYPE_VXLAN: 9593 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) 9594 return; 9595 9596 if (adapter->vxlan_port != ti->port) { 9597 netdev_info(dev, "VXLAN port %d not found\n", 9598 ntohs(ti->port)); 9599 return; 9600 } 9601 9602 port_mask = IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK; 9603 break; 9604 case UDP_TUNNEL_TYPE_GENEVE: 9605 if (!(adapter->flags & IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE)) 9606 return; 9607 9608 if (adapter->geneve_port != ti->port) { 9609 netdev_info(dev, "GENEVE port %d not found\n", 9610 ntohs(ti->port)); 9611 return; 9612 } 9613 9614 port_mask = IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK; 9615 break; 9616 default: 9617 return; 9618 } 9619 9620 ixgbe_clear_udp_tunnel_port(adapter, port_mask); 9621 adapter->flags2 |= IXGBE_FLAG2_UDP_TUN_REREG_NEEDED; 9622 } 9623 9624 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9625 struct net_device *dev, 9626 const unsigned char *addr, u16 vid, 9627 u16 flags) 9628 { 9629 /* guarantee we can provide a unique filter for the unicast address */ 9630 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9631 struct ixgbe_adapter *adapter = netdev_priv(dev); 9632 u16 pool = VMDQ_P(0); 9633 9634 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9635 return -ENOMEM; 9636 } 9637 9638 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9639 } 9640 9641 /** 9642 * ixgbe_configure_bridge_mode - set various bridge modes 9643 * @adapter: the private structure 9644 * @mode: requested bridge mode 9645 * 9646 * Configure some settings require for various bridge modes. 9647 **/ 9648 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9649 __u16 mode) 9650 { 9651 struct ixgbe_hw *hw = &adapter->hw; 9652 unsigned int p, num_pools; 9653 u32 vmdctl; 9654 9655 switch (mode) { 9656 case BRIDGE_MODE_VEPA: 9657 /* disable Tx loopback, rely on switch hairpin mode */ 9658 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9659 9660 /* must enable Rx switching replication to allow multicast 9661 * packet reception on all VFs, and to enable source address 9662 * pruning. 9663 */ 9664 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9665 vmdctl |= IXGBE_VT_CTL_REPLEN; 9666 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9667 9668 /* enable Rx source address pruning. Note, this requires 9669 * replication to be enabled or else it does nothing. 9670 */ 9671 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9672 for (p = 0; p < num_pools; p++) { 9673 if (hw->mac.ops.set_source_address_pruning) 9674 hw->mac.ops.set_source_address_pruning(hw, 9675 true, 9676 p); 9677 } 9678 break; 9679 case BRIDGE_MODE_VEB: 9680 /* enable Tx loopback for internal VF/PF communication */ 9681 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 9682 IXGBE_PFDTXGSWC_VT_LBEN); 9683 9684 /* disable Rx switching replication unless we have SR-IOV 9685 * virtual functions 9686 */ 9687 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9688 if (!adapter->num_vfs) 9689 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 9690 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 9691 9692 /* disable Rx source address pruning, since we don't expect to 9693 * be receiving external loopback of our transmitted frames. 9694 */ 9695 num_pools = adapter->num_vfs + adapter->num_rx_pools; 9696 for (p = 0; p < num_pools; p++) { 9697 if (hw->mac.ops.set_source_address_pruning) 9698 hw->mac.ops.set_source_address_pruning(hw, 9699 false, 9700 p); 9701 } 9702 break; 9703 default: 9704 return -EINVAL; 9705 } 9706 9707 adapter->bridge_mode = mode; 9708 9709 e_info(drv, "enabling bridge mode: %s\n", 9710 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 9711 9712 return 0; 9713 } 9714 9715 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 9716 struct nlmsghdr *nlh, u16 flags) 9717 { 9718 struct ixgbe_adapter *adapter = netdev_priv(dev); 9719 struct nlattr *attr, *br_spec; 9720 int rem; 9721 9722 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9723 return -EOPNOTSUPP; 9724 9725 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 9726 if (!br_spec) 9727 return -EINVAL; 9728 9729 nla_for_each_nested(attr, br_spec, rem) { 9730 int status; 9731 __u16 mode; 9732 9733 if (nla_type(attr) != IFLA_BRIDGE_MODE) 9734 continue; 9735 9736 if (nla_len(attr) < sizeof(mode)) 9737 return -EINVAL; 9738 9739 mode = nla_get_u16(attr); 9740 status = ixgbe_configure_bridge_mode(adapter, mode); 9741 if (status) 9742 return status; 9743 9744 break; 9745 } 9746 9747 return 0; 9748 } 9749 9750 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 9751 struct net_device *dev, 9752 u32 filter_mask, int nlflags) 9753 { 9754 struct ixgbe_adapter *adapter = netdev_priv(dev); 9755 9756 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 9757 return 0; 9758 9759 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 9760 adapter->bridge_mode, 0, 0, nlflags, 9761 filter_mask, NULL); 9762 } 9763 9764 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 9765 { 9766 struct ixgbe_fwd_adapter *fwd_adapter = NULL; 9767 struct ixgbe_adapter *adapter = netdev_priv(pdev); 9768 int used_pools = adapter->num_vfs + adapter->num_rx_pools; 9769 int tcs = adapter->hw_tcs ? : 1; 9770 unsigned int limit; 9771 int pool, err; 9772 9773 /* Hardware has a limited number of available pools. Each VF, and the 9774 * PF require a pool. Check to ensure we don't attempt to use more 9775 * then the available number of pools. 9776 */ 9777 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 9778 return ERR_PTR(-EINVAL); 9779 9780 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9781 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 9782 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) 9783 return ERR_PTR(-EBUSY); 9784 9785 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); 9786 if (!fwd_adapter) 9787 return ERR_PTR(-ENOMEM); 9788 9789 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9790 set_bit(pool, adapter->fwd_bitmask); 9791 limit = find_last_bit(adapter->fwd_bitmask, adapter->num_rx_pools + 1); 9792 9793 /* Enable VMDq flag so device will be set in VM mode */ 9794 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; 9795 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9796 9797 fwd_adapter->pool = pool; 9798 fwd_adapter->real_adapter = adapter; 9799 9800 /* Force reinit of ring allocation with VMDQ enabled */ 9801 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 9802 9803 if (!err && netif_running(pdev)) 9804 err = ixgbe_fwd_ring_up(vdev, fwd_adapter); 9805 9806 if (!err) 9807 return fwd_adapter; 9808 9809 /* unwind counter and free adapter struct */ 9810 netdev_info(pdev, 9811 "%s: dfwd hardware acceleration failed\n", vdev->name); 9812 clear_bit(pool, adapter->fwd_bitmask); 9813 kfree(fwd_adapter); 9814 return ERR_PTR(err); 9815 } 9816 9817 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 9818 { 9819 struct ixgbe_fwd_adapter *accel = priv; 9820 struct ixgbe_adapter *adapter = accel->real_adapter; 9821 unsigned int rxbase = accel->rx_base_queue; 9822 unsigned int limit, i; 9823 9824 /* delete unicast filter associated with offloaded interface */ 9825 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 9826 VMDQ_P(accel->pool)); 9827 9828 /* disable ability to receive packets for this pool */ 9829 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VMOLR(accel->pool), 0); 9830 9831 /* Allow remaining Rx packets to get flushed out of the 9832 * Rx FIFO before we drop the netdev for the ring. 9833 */ 9834 usleep_range(10000, 20000); 9835 9836 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 9837 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 9838 struct ixgbe_q_vector *qv = ring->q_vector; 9839 9840 /* Make sure we aren't processing any packets and clear 9841 * netdev to shut down the ring. 9842 */ 9843 if (netif_running(adapter->netdev)) 9844 napi_synchronize(&qv->napi); 9845 ring->netdev = NULL; 9846 } 9847 9848 clear_bit(accel->pool, adapter->fwd_bitmask); 9849 limit = find_last_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9850 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; 9851 9852 /* go back to full RSS if we're done with our VMQs */ 9853 if (adapter->ring_feature[RING_F_VMDQ].limit == 1) { 9854 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9855 num_online_cpus()); 9856 9857 adapter->flags &= ~IXGBE_FLAG_VMDQ_ENABLED; 9858 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; 9859 adapter->ring_feature[RING_F_RSS].limit = rss; 9860 } 9861 9862 ixgbe_setup_tc(pdev, adapter->hw_tcs); 9863 netdev_dbg(pdev, "pool %i:%i queues %i:%i\n", 9864 accel->pool, adapter->num_rx_pools, 9865 accel->rx_base_queue, 9866 accel->rx_base_queue + 9867 adapter->num_rx_queues_per_pool); 9868 kfree(accel); 9869 } 9870 9871 #define IXGBE_MAX_MAC_HDR_LEN 127 9872 #define IXGBE_MAX_NETWORK_HDR_LEN 511 9873 9874 static netdev_features_t 9875 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 9876 netdev_features_t features) 9877 { 9878 unsigned int network_hdr_len, mac_hdr_len; 9879 9880 /* Make certain the headers can be described by a context descriptor */ 9881 mac_hdr_len = skb_network_header(skb) - skb->data; 9882 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 9883 return features & ~(NETIF_F_HW_CSUM | 9884 NETIF_F_SCTP_CRC | 9885 NETIF_F_HW_VLAN_CTAG_TX | 9886 NETIF_F_TSO | 9887 NETIF_F_TSO6); 9888 9889 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 9890 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 9891 return features & ~(NETIF_F_HW_CSUM | 9892 NETIF_F_SCTP_CRC | 9893 NETIF_F_TSO | 9894 NETIF_F_TSO6); 9895 9896 /* We can only support IPV4 TSO in tunnels if we can mangle the 9897 * inner IP ID field, so strip TSO if MANGLEID is not supported. 9898 */ 9899 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) 9900 features &= ~NETIF_F_TSO; 9901 9902 #ifdef CONFIG_XFRM_OFFLOAD 9903 /* IPsec offload doesn't get along well with others *yet* */ 9904 if (skb->sp) 9905 features &= ~(NETIF_F_TSO | NETIF_F_HW_CSUM); 9906 #endif 9907 9908 return features; 9909 } 9910 9911 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 9912 { 9913 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 9914 struct ixgbe_adapter *adapter = netdev_priv(dev); 9915 struct bpf_prog *old_prog; 9916 9917 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9918 return -EINVAL; 9919 9920 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 9921 return -EINVAL; 9922 9923 /* verify ixgbe ring attributes are sufficient for XDP */ 9924 for (i = 0; i < adapter->num_rx_queues; i++) { 9925 struct ixgbe_ring *ring = adapter->rx_ring[i]; 9926 9927 if (ring_is_rsc_enabled(ring)) 9928 return -EINVAL; 9929 9930 if (frame_size > ixgbe_rx_bufsz(ring)) 9931 return -EINVAL; 9932 } 9933 9934 if (nr_cpu_ids > MAX_XDP_QUEUES) 9935 return -ENOMEM; 9936 9937 old_prog = xchg(&adapter->xdp_prog, prog); 9938 9939 /* If transitioning XDP modes reconfigure rings */ 9940 if (!!prog != !!old_prog) { 9941 int err = ixgbe_setup_tc(dev, adapter->hw_tcs); 9942 9943 if (err) { 9944 rcu_assign_pointer(adapter->xdp_prog, old_prog); 9945 return -EINVAL; 9946 } 9947 } else { 9948 for (i = 0; i < adapter->num_rx_queues; i++) 9949 xchg(&adapter->rx_ring[i]->xdp_prog, adapter->xdp_prog); 9950 } 9951 9952 if (old_prog) 9953 bpf_prog_put(old_prog); 9954 9955 return 0; 9956 } 9957 9958 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 9959 { 9960 struct ixgbe_adapter *adapter = netdev_priv(dev); 9961 9962 switch (xdp->command) { 9963 case XDP_SETUP_PROG: 9964 return ixgbe_xdp_setup(dev, xdp->prog); 9965 case XDP_QUERY_PROG: 9966 xdp->prog_attached = !!(adapter->xdp_prog); 9967 xdp->prog_id = adapter->xdp_prog ? 9968 adapter->xdp_prog->aux->id : 0; 9969 return 0; 9970 default: 9971 return -EINVAL; 9972 } 9973 } 9974 9975 static int ixgbe_xdp_xmit(struct net_device *dev, struct xdp_buff *xdp) 9976 { 9977 struct ixgbe_adapter *adapter = netdev_priv(dev); 9978 struct ixgbe_ring *ring; 9979 int err; 9980 9981 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 9982 return -ENETDOWN; 9983 9984 /* During program transitions its possible adapter->xdp_prog is assigned 9985 * but ring has not been configured yet. In this case simply abort xmit. 9986 */ 9987 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 9988 if (unlikely(!ring)) 9989 return -ENXIO; 9990 9991 err = ixgbe_xmit_xdp_ring(adapter, xdp); 9992 if (err != IXGBE_XDP_TX) 9993 return -ENOSPC; 9994 9995 return 0; 9996 } 9997 9998 static void ixgbe_xdp_flush(struct net_device *dev) 9999 { 10000 struct ixgbe_adapter *adapter = netdev_priv(dev); 10001 struct ixgbe_ring *ring; 10002 10003 /* Its possible the device went down between xdp xmit and flush so 10004 * we need to ensure device is still up. 10005 */ 10006 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10007 return; 10008 10009 ring = adapter->xdp_prog ? adapter->xdp_ring[smp_processor_id()] : NULL; 10010 if (unlikely(!ring)) 10011 return; 10012 10013 /* Force memory writes to complete before letting h/w know there 10014 * are new descriptors to fetch. 10015 */ 10016 wmb(); 10017 writel(ring->next_to_use, ring->tail); 10018 10019 return; 10020 } 10021 10022 static const struct net_device_ops ixgbe_netdev_ops = { 10023 .ndo_open = ixgbe_open, 10024 .ndo_stop = ixgbe_close, 10025 .ndo_start_xmit = ixgbe_xmit_frame, 10026 .ndo_select_queue = ixgbe_select_queue, 10027 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10028 .ndo_validate_addr = eth_validate_addr, 10029 .ndo_set_mac_address = ixgbe_set_mac, 10030 .ndo_change_mtu = ixgbe_change_mtu, 10031 .ndo_tx_timeout = ixgbe_tx_timeout, 10032 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10033 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10034 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10035 .ndo_do_ioctl = ixgbe_ioctl, 10036 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10037 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10038 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10039 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10040 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10041 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10042 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10043 .ndo_get_stats64 = ixgbe_get_stats64, 10044 .ndo_setup_tc = __ixgbe_setup_tc, 10045 #ifdef CONFIG_NET_POLL_CONTROLLER 10046 .ndo_poll_controller = ixgbe_netpoll, 10047 #endif 10048 #ifdef IXGBE_FCOE 10049 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10050 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10051 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10052 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10053 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10054 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10055 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10056 #endif /* IXGBE_FCOE */ 10057 .ndo_set_features = ixgbe_set_features, 10058 .ndo_fix_features = ixgbe_fix_features, 10059 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10060 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10061 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10062 .ndo_dfwd_add_station = ixgbe_fwd_add, 10063 .ndo_dfwd_del_station = ixgbe_fwd_del, 10064 .ndo_udp_tunnel_add = ixgbe_add_udp_tunnel_port, 10065 .ndo_udp_tunnel_del = ixgbe_del_udp_tunnel_port, 10066 .ndo_features_check = ixgbe_features_check, 10067 .ndo_bpf = ixgbe_xdp, 10068 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10069 .ndo_xdp_flush = ixgbe_xdp_flush, 10070 }; 10071 10072 /** 10073 * ixgbe_enumerate_functions - Get the number of ports this device has 10074 * @adapter: adapter structure 10075 * 10076 * This function enumerates the phsyical functions co-located on a single slot, 10077 * in order to determine how many ports a device has. This is most useful in 10078 * determining the required GT/s of PCIe bandwidth necessary for optimal 10079 * performance. 10080 **/ 10081 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10082 { 10083 struct pci_dev *entry, *pdev = adapter->pdev; 10084 int physfns = 0; 10085 10086 /* Some cards can not use the generic count PCIe functions method, 10087 * because they are behind a parent switch, so we hardcode these with 10088 * the correct number of functions. 10089 */ 10090 if (ixgbe_pcie_from_parent(&adapter->hw)) 10091 physfns = 4; 10092 10093 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10094 /* don't count virtual functions */ 10095 if (entry->is_virtfn) 10096 continue; 10097 10098 /* When the devices on the bus don't all match our device ID, 10099 * we can't reliably determine the correct number of 10100 * functions. This can occur if a function has been direct 10101 * attached to a virtual machine using VT-d, for example. In 10102 * this case, simply return -1 to indicate this. 10103 */ 10104 if ((entry->vendor != pdev->vendor) || 10105 (entry->device != pdev->device)) 10106 return -1; 10107 10108 physfns++; 10109 } 10110 10111 return physfns; 10112 } 10113 10114 /** 10115 * ixgbe_wol_supported - Check whether device supports WoL 10116 * @adapter: the adapter private structure 10117 * @device_id: the device ID 10118 * @subdevice_id: the subsystem device ID 10119 * 10120 * This function is used by probe and ethtool to determine 10121 * which devices have WoL support 10122 * 10123 **/ 10124 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10125 u16 subdevice_id) 10126 { 10127 struct ixgbe_hw *hw = &adapter->hw; 10128 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10129 10130 /* WOL not supported on 82598 */ 10131 if (hw->mac.type == ixgbe_mac_82598EB) 10132 return false; 10133 10134 /* check eeprom to see if WOL is enabled for X540 and newer */ 10135 if (hw->mac.type >= ixgbe_mac_X540) { 10136 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10137 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10138 (hw->bus.func == 0))) 10139 return true; 10140 } 10141 10142 /* WOL is determined based on device IDs for 82599 MACs */ 10143 switch (device_id) { 10144 case IXGBE_DEV_ID_82599_SFP: 10145 /* Only these subdevices could supports WOL */ 10146 switch (subdevice_id) { 10147 case IXGBE_SUBDEV_ID_82599_560FLR: 10148 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10149 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10150 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10151 /* only support first port */ 10152 if (hw->bus.func != 0) 10153 break; 10154 /* fall through */ 10155 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10156 case IXGBE_SUBDEV_ID_82599_SFP: 10157 case IXGBE_SUBDEV_ID_82599_RNDC: 10158 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10159 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10160 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10161 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10162 return true; 10163 } 10164 break; 10165 case IXGBE_DEV_ID_82599EN_SFP: 10166 /* Only these subdevices support WOL */ 10167 switch (subdevice_id) { 10168 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10169 return true; 10170 } 10171 break; 10172 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10173 /* All except this subdevice support WOL */ 10174 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10175 return true; 10176 break; 10177 case IXGBE_DEV_ID_82599_KX4: 10178 return true; 10179 default: 10180 break; 10181 } 10182 10183 return false; 10184 } 10185 10186 /** 10187 * ixgbe_set_fw_version - Set FW version 10188 * @adapter: the adapter private structure 10189 * 10190 * This function is used by probe and ethtool to determine the FW version to 10191 * format to display. The FW version is taken from the EEPROM/NVM. 10192 */ 10193 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10194 { 10195 struct ixgbe_hw *hw = &adapter->hw; 10196 struct ixgbe_nvm_version nvm_ver; 10197 10198 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10199 if (nvm_ver.oem_valid) { 10200 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10201 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10202 nvm_ver.oem_release); 10203 return; 10204 } 10205 10206 ixgbe_get_etk_id(hw, &nvm_ver); 10207 ixgbe_get_orom_version(hw, &nvm_ver); 10208 10209 if (nvm_ver.or_valid) { 10210 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10211 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10212 nvm_ver.or_build, nvm_ver.or_patch); 10213 return; 10214 } 10215 10216 /* Set ETrack ID format */ 10217 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10218 "0x%08x", nvm_ver.etk_id); 10219 } 10220 10221 /** 10222 * ixgbe_probe - Device Initialization Routine 10223 * @pdev: PCI device information struct 10224 * @ent: entry in ixgbe_pci_tbl 10225 * 10226 * Returns 0 on success, negative on failure 10227 * 10228 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10229 * The OS initialization, configuring of the adapter private structure, 10230 * and a hardware reset occur. 10231 **/ 10232 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10233 { 10234 struct net_device *netdev; 10235 struct ixgbe_adapter *adapter = NULL; 10236 struct ixgbe_hw *hw; 10237 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10238 int i, err, pci_using_dac, expected_gts; 10239 unsigned int indices = MAX_TX_QUEUES; 10240 u8 part_str[IXGBE_PBANUM_LENGTH]; 10241 bool disable_dev = false; 10242 #ifdef IXGBE_FCOE 10243 u16 device_caps; 10244 #endif 10245 u32 eec; 10246 10247 /* Catch broken hardware that put the wrong VF device ID in 10248 * the PCIe SR-IOV capability. 10249 */ 10250 if (pdev->is_virtfn) { 10251 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10252 pci_name(pdev), pdev->vendor, pdev->device); 10253 return -EINVAL; 10254 } 10255 10256 err = pci_enable_device_mem(pdev); 10257 if (err) 10258 return err; 10259 10260 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 10261 pci_using_dac = 1; 10262 } else { 10263 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10264 if (err) { 10265 dev_err(&pdev->dev, 10266 "No usable DMA configuration, aborting\n"); 10267 goto err_dma; 10268 } 10269 pci_using_dac = 0; 10270 } 10271 10272 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10273 if (err) { 10274 dev_err(&pdev->dev, 10275 "pci_request_selected_regions failed 0x%x\n", err); 10276 goto err_pci_reg; 10277 } 10278 10279 pci_enable_pcie_error_reporting(pdev); 10280 10281 pci_set_master(pdev); 10282 pci_save_state(pdev); 10283 10284 if (ii->mac == ixgbe_mac_82598EB) { 10285 #ifdef CONFIG_IXGBE_DCB 10286 /* 8 TC w/ 4 queues per TC */ 10287 indices = 4 * MAX_TRAFFIC_CLASS; 10288 #else 10289 indices = IXGBE_MAX_RSS_INDICES; 10290 #endif 10291 } 10292 10293 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10294 if (!netdev) { 10295 err = -ENOMEM; 10296 goto err_alloc_etherdev; 10297 } 10298 10299 SET_NETDEV_DEV(netdev, &pdev->dev); 10300 10301 adapter = netdev_priv(netdev); 10302 10303 adapter->netdev = netdev; 10304 adapter->pdev = pdev; 10305 hw = &adapter->hw; 10306 hw->back = adapter; 10307 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10308 10309 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10310 pci_resource_len(pdev, 0)); 10311 adapter->io_addr = hw->hw_addr; 10312 if (!hw->hw_addr) { 10313 err = -EIO; 10314 goto err_ioremap; 10315 } 10316 10317 netdev->netdev_ops = &ixgbe_netdev_ops; 10318 ixgbe_set_ethtool_ops(netdev); 10319 netdev->watchdog_timeo = 5 * HZ; 10320 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10321 10322 /* Setup hw api */ 10323 hw->mac.ops = *ii->mac_ops; 10324 hw->mac.type = ii->mac; 10325 hw->mvals = ii->mvals; 10326 if (ii->link_ops) 10327 hw->link.ops = *ii->link_ops; 10328 10329 /* EEPROM */ 10330 hw->eeprom.ops = *ii->eeprom_ops; 10331 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10332 if (ixgbe_removed(hw->hw_addr)) { 10333 err = -EIO; 10334 goto err_ioremap; 10335 } 10336 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10337 if (!(eec & BIT(8))) 10338 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10339 10340 /* PHY */ 10341 hw->phy.ops = *ii->phy_ops; 10342 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10343 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10344 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10345 hw->phy.mdio.mmds = 0; 10346 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10347 hw->phy.mdio.dev = netdev; 10348 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10349 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10350 10351 /* setup the private structure */ 10352 err = ixgbe_sw_init(adapter, ii); 10353 if (err) 10354 goto err_sw_init; 10355 10356 /* Make sure the SWFW semaphore is in a valid state */ 10357 if (hw->mac.ops.init_swfw_sync) 10358 hw->mac.ops.init_swfw_sync(hw); 10359 10360 /* Make it possible the adapter to be woken up via WOL */ 10361 switch (adapter->hw.mac.type) { 10362 case ixgbe_mac_82599EB: 10363 case ixgbe_mac_X540: 10364 case ixgbe_mac_X550: 10365 case ixgbe_mac_X550EM_x: 10366 case ixgbe_mac_x550em_a: 10367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10368 break; 10369 default: 10370 break; 10371 } 10372 10373 /* 10374 * If there is a fan on this device and it has failed log the 10375 * failure. 10376 */ 10377 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10378 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10379 if (esdp & IXGBE_ESDP_SDP1) 10380 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10381 } 10382 10383 if (allow_unsupported_sfp) 10384 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10385 10386 /* reset_hw fills in the perm_addr as well */ 10387 hw->phy.reset_if_overtemp = true; 10388 err = hw->mac.ops.reset_hw(hw); 10389 hw->phy.reset_if_overtemp = false; 10390 ixgbe_set_eee_capable(adapter); 10391 if (err == IXGBE_ERR_SFP_NOT_PRESENT) { 10392 err = 0; 10393 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { 10394 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10395 e_dev_err("Reload the driver after installing a supported module.\n"); 10396 goto err_sw_init; 10397 } else if (err) { 10398 e_dev_err("HW Init failed: %d\n", err); 10399 goto err_sw_init; 10400 } 10401 10402 #ifdef CONFIG_PCI_IOV 10403 /* SR-IOV not supported on the 82598 */ 10404 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 10405 goto skip_sriov; 10406 /* Mailbox */ 10407 ixgbe_init_mbx_params_pf(hw); 10408 hw->mbx.ops = ii->mbx_ops; 10409 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 10410 ixgbe_enable_sriov(adapter, max_vfs); 10411 skip_sriov: 10412 10413 #endif 10414 netdev->features = NETIF_F_SG | 10415 NETIF_F_TSO | 10416 NETIF_F_TSO6 | 10417 NETIF_F_RXHASH | 10418 NETIF_F_RXCSUM | 10419 NETIF_F_HW_CSUM; 10420 10421 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 10422 NETIF_F_GSO_GRE_CSUM | \ 10423 NETIF_F_GSO_IPXIP4 | \ 10424 NETIF_F_GSO_IPXIP6 | \ 10425 NETIF_F_GSO_UDP_TUNNEL | \ 10426 NETIF_F_GSO_UDP_TUNNEL_CSUM) 10427 10428 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 10429 netdev->features |= NETIF_F_GSO_PARTIAL | 10430 IXGBE_GSO_PARTIAL_FEATURES; 10431 10432 if (hw->mac.type >= ixgbe_mac_82599EB) 10433 netdev->features |= NETIF_F_SCTP_CRC; 10434 10435 /* copy netdev features into list of user selectable features */ 10436 netdev->hw_features |= netdev->features | 10437 NETIF_F_HW_VLAN_CTAG_FILTER | 10438 NETIF_F_HW_VLAN_CTAG_RX | 10439 NETIF_F_HW_VLAN_CTAG_TX | 10440 NETIF_F_RXALL | 10441 NETIF_F_HW_L2FW_DOFFLOAD; 10442 10443 if (hw->mac.type >= ixgbe_mac_82599EB) 10444 netdev->hw_features |= NETIF_F_NTUPLE | 10445 NETIF_F_HW_TC; 10446 10447 if (pci_using_dac) 10448 netdev->features |= NETIF_F_HIGHDMA; 10449 10450 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 10451 netdev->hw_enc_features |= netdev->vlan_features; 10452 netdev->mpls_features |= NETIF_F_SG | 10453 NETIF_F_TSO | 10454 NETIF_F_TSO6 | 10455 NETIF_F_HW_CSUM; 10456 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 10457 10458 /* set this bit last since it cannot be part of vlan_features */ 10459 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 10460 NETIF_F_HW_VLAN_CTAG_RX | 10461 NETIF_F_HW_VLAN_CTAG_TX; 10462 10463 netdev->priv_flags |= IFF_UNICAST_FLT; 10464 netdev->priv_flags |= IFF_SUPP_NOFCS; 10465 10466 /* MTU range: 68 - 9710 */ 10467 netdev->min_mtu = ETH_MIN_MTU; 10468 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 10469 10470 #ifdef CONFIG_IXGBE_DCB 10471 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 10472 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 10473 #endif 10474 10475 #ifdef IXGBE_FCOE 10476 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 10477 unsigned int fcoe_l; 10478 10479 if (hw->mac.ops.get_device_caps) { 10480 hw->mac.ops.get_device_caps(hw, &device_caps); 10481 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 10482 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 10483 } 10484 10485 10486 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 10487 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 10488 10489 netdev->features |= NETIF_F_FSO | 10490 NETIF_F_FCOE_CRC; 10491 10492 netdev->vlan_features |= NETIF_F_FSO | 10493 NETIF_F_FCOE_CRC | 10494 NETIF_F_FCOE_MTU; 10495 } 10496 #endif /* IXGBE_FCOE */ 10497 ixgbe_init_ipsec_offload(adapter); 10498 10499 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 10500 netdev->hw_features |= NETIF_F_LRO; 10501 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10502 netdev->features |= NETIF_F_LRO; 10503 10504 /* make sure the EEPROM is good */ 10505 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 10506 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 10507 err = -EIO; 10508 goto err_sw_init; 10509 } 10510 10511 eth_platform_get_mac_address(&adapter->pdev->dev, 10512 adapter->hw.mac.perm_addr); 10513 10514 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); 10515 10516 if (!is_valid_ether_addr(netdev->dev_addr)) { 10517 e_dev_err("invalid MAC address\n"); 10518 err = -EIO; 10519 goto err_sw_init; 10520 } 10521 10522 /* Set hw->mac.addr to permanent MAC address */ 10523 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 10524 ixgbe_mac_set_default_filter(adapter); 10525 10526 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 10527 10528 if (ixgbe_removed(hw->hw_addr)) { 10529 err = -EIO; 10530 goto err_sw_init; 10531 } 10532 INIT_WORK(&adapter->service_task, ixgbe_service_task); 10533 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 10534 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 10535 10536 err = ixgbe_init_interrupt_scheme(adapter); 10537 if (err) 10538 goto err_sw_init; 10539 10540 for (i = 0; i < adapter->num_rx_queues; i++) 10541 u64_stats_init(&adapter->rx_ring[i]->syncp); 10542 for (i = 0; i < adapter->num_tx_queues; i++) 10543 u64_stats_init(&adapter->tx_ring[i]->syncp); 10544 for (i = 0; i < adapter->num_xdp_queues; i++) 10545 u64_stats_init(&adapter->xdp_ring[i]->syncp); 10546 10547 /* WOL not supported for all devices */ 10548 adapter->wol = 0; 10549 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 10550 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 10551 pdev->subsystem_device); 10552 if (hw->wol_enabled) 10553 adapter->wol = IXGBE_WUFC_MAG; 10554 10555 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 10556 10557 /* save off EEPROM version number */ 10558 ixgbe_set_fw_version(adapter); 10559 10560 /* pick up the PCI bus settings for reporting later */ 10561 if (ixgbe_pcie_from_parent(hw)) 10562 ixgbe_get_parent_bus_info(adapter); 10563 else 10564 hw->mac.ops.get_bus_info(hw); 10565 10566 /* calculate the expected PCIe bandwidth required for optimal 10567 * performance. Note that some older parts will never have enough 10568 * bandwidth due to being older generation PCIe parts. We clamp these 10569 * parts to ensure no warning is displayed if it can't be fixed. 10570 */ 10571 switch (hw->mac.type) { 10572 case ixgbe_mac_82598EB: 10573 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 10574 break; 10575 default: 10576 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 10577 break; 10578 } 10579 10580 /* don't check link if we failed to enumerate functions */ 10581 if (expected_gts > 0) 10582 ixgbe_check_minimum_link(adapter, expected_gts); 10583 10584 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 10585 if (err) 10586 strlcpy(part_str, "Unknown", sizeof(part_str)); 10587 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 10588 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 10589 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 10590 part_str); 10591 else 10592 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 10593 hw->mac.type, hw->phy.type, part_str); 10594 10595 e_dev_info("%pM\n", netdev->dev_addr); 10596 10597 /* reset the hardware with the new settings */ 10598 err = hw->mac.ops.start_hw(hw); 10599 if (err == IXGBE_ERR_EEPROM_VERSION) { 10600 /* We are running on a pre-production device, log a warning */ 10601 e_dev_warn("This device is a pre-production adapter/LOM. " 10602 "Please be aware there may be issues associated " 10603 "with your hardware. If you are experiencing " 10604 "problems please contact your Intel or hardware " 10605 "representative who provided you with this " 10606 "hardware.\n"); 10607 } 10608 strcpy(netdev->name, "eth%d"); 10609 pci_set_drvdata(pdev, adapter); 10610 err = register_netdev(netdev); 10611 if (err) 10612 goto err_register; 10613 10614 10615 /* power down the optics for 82599 SFP+ fiber */ 10616 if (hw->mac.ops.disable_tx_laser) 10617 hw->mac.ops.disable_tx_laser(hw); 10618 10619 /* carrier off reporting is important to ethtool even BEFORE open */ 10620 netif_carrier_off(netdev); 10621 10622 #ifdef CONFIG_IXGBE_DCA 10623 if (dca_add_requester(&pdev->dev) == 0) { 10624 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 10625 ixgbe_setup_dca(adapter); 10626 } 10627 #endif 10628 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 10629 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 10630 for (i = 0; i < adapter->num_vfs; i++) 10631 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 10632 } 10633 10634 /* firmware requires driver version to be 0xFFFFFFFF 10635 * since os does not support feature 10636 */ 10637 if (hw->mac.ops.set_fw_drv_ver) 10638 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 10639 sizeof(ixgbe_driver_version) - 1, 10640 ixgbe_driver_version); 10641 10642 /* add san mac addr to netdev */ 10643 ixgbe_add_sanmac_netdev(netdev); 10644 10645 e_dev_info("%s\n", ixgbe_default_device_descr); 10646 10647 #ifdef CONFIG_IXGBE_HWMON 10648 if (ixgbe_sysfs_init(adapter)) 10649 e_err(probe, "failed to allocate sysfs resources\n"); 10650 #endif /* CONFIG_IXGBE_HWMON */ 10651 10652 ixgbe_dbg_adapter_init(adapter); 10653 10654 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 10655 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 10656 hw->mac.ops.setup_link(hw, 10657 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 10658 true); 10659 10660 return 0; 10661 10662 err_register: 10663 ixgbe_release_hw_control(adapter); 10664 ixgbe_clear_interrupt_scheme(adapter); 10665 err_sw_init: 10666 ixgbe_disable_sriov(adapter); 10667 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 10668 iounmap(adapter->io_addr); 10669 kfree(adapter->jump_tables[0]); 10670 kfree(adapter->mac_table); 10671 kfree(adapter->rss_key); 10672 err_ioremap: 10673 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10674 free_netdev(netdev); 10675 err_alloc_etherdev: 10676 pci_release_mem_regions(pdev); 10677 err_pci_reg: 10678 err_dma: 10679 if (!adapter || disable_dev) 10680 pci_disable_device(pdev); 10681 return err; 10682 } 10683 10684 /** 10685 * ixgbe_remove - Device Removal Routine 10686 * @pdev: PCI device information struct 10687 * 10688 * ixgbe_remove is called by the PCI subsystem to alert the driver 10689 * that it should release a PCI device. The could be caused by a 10690 * Hot-Plug event, or because the driver is going to be removed from 10691 * memory. 10692 **/ 10693 static void ixgbe_remove(struct pci_dev *pdev) 10694 { 10695 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10696 struct net_device *netdev; 10697 bool disable_dev; 10698 int i; 10699 10700 /* if !adapter then we already cleaned up in probe */ 10701 if (!adapter) 10702 return; 10703 10704 netdev = adapter->netdev; 10705 ixgbe_dbg_adapter_exit(adapter); 10706 10707 set_bit(__IXGBE_REMOVING, &adapter->state); 10708 cancel_work_sync(&adapter->service_task); 10709 10710 10711 #ifdef CONFIG_IXGBE_DCA 10712 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 10713 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 10714 dca_remove_requester(&pdev->dev); 10715 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 10716 IXGBE_DCA_CTRL_DCA_DISABLE); 10717 } 10718 10719 #endif 10720 #ifdef CONFIG_IXGBE_HWMON 10721 ixgbe_sysfs_exit(adapter); 10722 #endif /* CONFIG_IXGBE_HWMON */ 10723 10724 /* remove the added san mac */ 10725 ixgbe_del_sanmac_netdev(netdev); 10726 10727 #ifdef CONFIG_PCI_IOV 10728 ixgbe_disable_sriov(adapter); 10729 #endif 10730 if (netdev->reg_state == NETREG_REGISTERED) 10731 unregister_netdev(netdev); 10732 10733 ixgbe_stop_ipsec_offload(adapter); 10734 ixgbe_clear_interrupt_scheme(adapter); 10735 10736 ixgbe_release_hw_control(adapter); 10737 10738 #ifdef CONFIG_DCB 10739 kfree(adapter->ixgbe_ieee_pfc); 10740 kfree(adapter->ixgbe_ieee_ets); 10741 10742 #endif 10743 iounmap(adapter->io_addr); 10744 pci_release_mem_regions(pdev); 10745 10746 e_dev_info("complete\n"); 10747 10748 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 10749 if (adapter->jump_tables[i]) { 10750 kfree(adapter->jump_tables[i]->input); 10751 kfree(adapter->jump_tables[i]->mask); 10752 } 10753 kfree(adapter->jump_tables[i]); 10754 } 10755 10756 kfree(adapter->mac_table); 10757 kfree(adapter->rss_key); 10758 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 10759 free_netdev(netdev); 10760 10761 pci_disable_pcie_error_reporting(pdev); 10762 10763 if (disable_dev) 10764 pci_disable_device(pdev); 10765 } 10766 10767 /** 10768 * ixgbe_io_error_detected - called when PCI error is detected 10769 * @pdev: Pointer to PCI device 10770 * @state: The current pci connection state 10771 * 10772 * This function is called after a PCI bus error affecting 10773 * this device has been detected. 10774 */ 10775 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 10776 pci_channel_state_t state) 10777 { 10778 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10779 struct net_device *netdev = adapter->netdev; 10780 10781 #ifdef CONFIG_PCI_IOV 10782 struct ixgbe_hw *hw = &adapter->hw; 10783 struct pci_dev *bdev, *vfdev; 10784 u32 dw0, dw1, dw2, dw3; 10785 int vf, pos; 10786 u16 req_id, pf_func; 10787 10788 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 10789 adapter->num_vfs == 0) 10790 goto skip_bad_vf_detection; 10791 10792 bdev = pdev->bus->self; 10793 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 10794 bdev = bdev->bus->self; 10795 10796 if (!bdev) 10797 goto skip_bad_vf_detection; 10798 10799 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 10800 if (!pos) 10801 goto skip_bad_vf_detection; 10802 10803 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 10804 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 10805 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 10806 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 10807 if (ixgbe_removed(hw->hw_addr)) 10808 goto skip_bad_vf_detection; 10809 10810 req_id = dw1 >> 16; 10811 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 10812 if (!(req_id & 0x0080)) 10813 goto skip_bad_vf_detection; 10814 10815 pf_func = req_id & 0x01; 10816 if ((pf_func & 1) == (pdev->devfn & 1)) { 10817 unsigned int device_id; 10818 10819 vf = (req_id & 0x7F) >> 1; 10820 e_dev_err("VF %d has caused a PCIe error\n", vf); 10821 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 10822 "%8.8x\tdw3: %8.8x\n", 10823 dw0, dw1, dw2, dw3); 10824 switch (adapter->hw.mac.type) { 10825 case ixgbe_mac_82599EB: 10826 device_id = IXGBE_82599_VF_DEVICE_ID; 10827 break; 10828 case ixgbe_mac_X540: 10829 device_id = IXGBE_X540_VF_DEVICE_ID; 10830 break; 10831 case ixgbe_mac_X550: 10832 device_id = IXGBE_DEV_ID_X550_VF; 10833 break; 10834 case ixgbe_mac_X550EM_x: 10835 device_id = IXGBE_DEV_ID_X550EM_X_VF; 10836 break; 10837 case ixgbe_mac_x550em_a: 10838 device_id = IXGBE_DEV_ID_X550EM_A_VF; 10839 break; 10840 default: 10841 device_id = 0; 10842 break; 10843 } 10844 10845 /* Find the pci device of the offending VF */ 10846 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 10847 while (vfdev) { 10848 if (vfdev->devfn == (req_id & 0xFF)) 10849 break; 10850 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 10851 device_id, vfdev); 10852 } 10853 /* 10854 * There's a slim chance the VF could have been hot plugged, 10855 * so if it is no longer present we don't need to issue the 10856 * VFLR. Just clean up the AER in that case. 10857 */ 10858 if (vfdev) { 10859 pcie_flr(vfdev); 10860 /* Free device reference count */ 10861 pci_dev_put(vfdev); 10862 } 10863 10864 pci_cleanup_aer_uncorrect_error_status(pdev); 10865 } 10866 10867 /* 10868 * Even though the error may have occurred on the other port 10869 * we still need to increment the vf error reference count for 10870 * both ports because the I/O resume function will be called 10871 * for both of them. 10872 */ 10873 adapter->vferr_refcount++; 10874 10875 return PCI_ERS_RESULT_RECOVERED; 10876 10877 skip_bad_vf_detection: 10878 #endif /* CONFIG_PCI_IOV */ 10879 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 10880 return PCI_ERS_RESULT_DISCONNECT; 10881 10882 if (!netif_device_present(netdev)) 10883 return PCI_ERS_RESULT_DISCONNECT; 10884 10885 rtnl_lock(); 10886 netif_device_detach(netdev); 10887 10888 if (state == pci_channel_io_perm_failure) { 10889 rtnl_unlock(); 10890 return PCI_ERS_RESULT_DISCONNECT; 10891 } 10892 10893 if (netif_running(netdev)) 10894 ixgbe_close_suspend(adapter); 10895 10896 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 10897 pci_disable_device(pdev); 10898 rtnl_unlock(); 10899 10900 /* Request a slot reset. */ 10901 return PCI_ERS_RESULT_NEED_RESET; 10902 } 10903 10904 /** 10905 * ixgbe_io_slot_reset - called after the pci bus has been reset. 10906 * @pdev: Pointer to PCI device 10907 * 10908 * Restart the card from scratch, as if from a cold-boot. 10909 */ 10910 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 10911 { 10912 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10913 pci_ers_result_t result; 10914 int err; 10915 10916 if (pci_enable_device_mem(pdev)) { 10917 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 10918 result = PCI_ERS_RESULT_DISCONNECT; 10919 } else { 10920 smp_mb__before_atomic(); 10921 clear_bit(__IXGBE_DISABLED, &adapter->state); 10922 adapter->hw.hw_addr = adapter->io_addr; 10923 pci_set_master(pdev); 10924 pci_restore_state(pdev); 10925 pci_save_state(pdev); 10926 10927 pci_wake_from_d3(pdev, false); 10928 10929 ixgbe_reset(adapter); 10930 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10931 result = PCI_ERS_RESULT_RECOVERED; 10932 } 10933 10934 err = pci_cleanup_aer_uncorrect_error_status(pdev); 10935 if (err) { 10936 e_dev_err("pci_cleanup_aer_uncorrect_error_status " 10937 "failed 0x%0x\n", err); 10938 /* non-fatal, continue */ 10939 } 10940 10941 return result; 10942 } 10943 10944 /** 10945 * ixgbe_io_resume - called when traffic can start flowing again. 10946 * @pdev: Pointer to PCI device 10947 * 10948 * This callback is called when the error recovery driver tells us that 10949 * its OK to resume normal operation. 10950 */ 10951 static void ixgbe_io_resume(struct pci_dev *pdev) 10952 { 10953 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 10954 struct net_device *netdev = adapter->netdev; 10955 10956 #ifdef CONFIG_PCI_IOV 10957 if (adapter->vferr_refcount) { 10958 e_info(drv, "Resuming after VF err\n"); 10959 adapter->vferr_refcount--; 10960 return; 10961 } 10962 10963 #endif 10964 rtnl_lock(); 10965 if (netif_running(netdev)) 10966 ixgbe_open(netdev); 10967 10968 netif_device_attach(netdev); 10969 rtnl_unlock(); 10970 } 10971 10972 static const struct pci_error_handlers ixgbe_err_handler = { 10973 .error_detected = ixgbe_io_error_detected, 10974 .slot_reset = ixgbe_io_slot_reset, 10975 .resume = ixgbe_io_resume, 10976 }; 10977 10978 static struct pci_driver ixgbe_driver = { 10979 .name = ixgbe_driver_name, 10980 .id_table = ixgbe_pci_tbl, 10981 .probe = ixgbe_probe, 10982 .remove = ixgbe_remove, 10983 #ifdef CONFIG_PM 10984 .suspend = ixgbe_suspend, 10985 .resume = ixgbe_resume, 10986 #endif 10987 .shutdown = ixgbe_shutdown, 10988 .sriov_configure = ixgbe_pci_sriov_configure, 10989 .err_handler = &ixgbe_err_handler 10990 }; 10991 10992 /** 10993 * ixgbe_init_module - Driver Registration Routine 10994 * 10995 * ixgbe_init_module is the first routine called when the driver is 10996 * loaded. All it does is register with the PCI subsystem. 10997 **/ 10998 static int __init ixgbe_init_module(void) 10999 { 11000 int ret; 11001 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); 11002 pr_info("%s\n", ixgbe_copyright); 11003 11004 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11005 if (!ixgbe_wq) { 11006 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11007 return -ENOMEM; 11008 } 11009 11010 ixgbe_dbg_init(); 11011 11012 ret = pci_register_driver(&ixgbe_driver); 11013 if (ret) { 11014 destroy_workqueue(ixgbe_wq); 11015 ixgbe_dbg_exit(); 11016 return ret; 11017 } 11018 11019 #ifdef CONFIG_IXGBE_DCA 11020 dca_register_notify(&dca_notifier); 11021 #endif 11022 11023 return 0; 11024 } 11025 11026 module_init(ixgbe_init_module); 11027 11028 /** 11029 * ixgbe_exit_module - Driver Exit Cleanup Routine 11030 * 11031 * ixgbe_exit_module is called just before the driver is removed 11032 * from memory. 11033 **/ 11034 static void __exit ixgbe_exit_module(void) 11035 { 11036 #ifdef CONFIG_IXGBE_DCA 11037 dca_unregister_notify(&dca_notifier); 11038 #endif 11039 pci_unregister_driver(&ixgbe_driver); 11040 11041 ixgbe_dbg_exit(); 11042 if (ixgbe_wq) { 11043 destroy_workqueue(ixgbe_wq); 11044 ixgbe_wq = NULL; 11045 } 11046 } 11047 11048 #ifdef CONFIG_IXGBE_DCA 11049 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11050 void *p) 11051 { 11052 int ret_val; 11053 11054 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11055 __ixgbe_notify_dca); 11056 11057 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11058 } 11059 11060 #endif /* CONFIG_IXGBE_DCA */ 11061 11062 module_exit(ixgbe_exit_module); 11063 11064 /* ixgbe_main.c */ 11065