1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include "ixgbe.h" 29 #include "ixgbe_sriov.h" 30 31 #ifdef CONFIG_IXGBE_DCB 32 /** 33 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV 34 * @adapter: board private structure to initialize 35 * 36 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It 37 * will also try to cache the proper offsets if RSS/FCoE are enabled along 38 * with VMDq. 39 * 40 **/ 41 static bool ixgbe_cache_ring_dcb_sriov(struct ixgbe_adapter *adapter) 42 { 43 #ifdef IXGBE_FCOE 44 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; 45 #endif /* IXGBE_FCOE */ 46 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 47 int i; 48 u16 reg_idx; 49 u8 tcs = netdev_get_num_tc(adapter->netdev); 50 51 /* verify we have DCB queueing enabled before proceeding */ 52 if (tcs <= 1) 53 return false; 54 55 /* verify we have VMDq enabled before proceeding */ 56 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 57 return false; 58 59 /* start at VMDq register offset for SR-IOV enabled setups */ 60 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 61 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { 62 /* If we are greater than indices move to next pool */ 63 if ((reg_idx & ~vmdq->mask) >= tcs) 64 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 65 adapter->rx_ring[i]->reg_idx = reg_idx; 66 } 67 68 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 69 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { 70 /* If we are greater than indices move to next pool */ 71 if ((reg_idx & ~vmdq->mask) >= tcs) 72 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 73 adapter->tx_ring[i]->reg_idx = reg_idx; 74 } 75 76 #ifdef IXGBE_FCOE 77 /* nothing to do if FCoE is disabled */ 78 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 79 return true; 80 81 /* The work is already done if the FCoE ring is shared */ 82 if (fcoe->offset < tcs) 83 return true; 84 85 /* The FCoE rings exist separately, we need to move their reg_idx */ 86 if (fcoe->indices) { 87 u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 88 u8 fcoe_tc = ixgbe_fcoe_get_tc(adapter); 89 90 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; 91 for (i = fcoe->offset; i < adapter->num_rx_queues; i++) { 92 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; 93 adapter->rx_ring[i]->reg_idx = reg_idx; 94 reg_idx++; 95 } 96 97 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; 98 for (i = fcoe->offset; i < adapter->num_tx_queues; i++) { 99 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; 100 adapter->tx_ring[i]->reg_idx = reg_idx; 101 reg_idx++; 102 } 103 } 104 105 #endif /* IXGBE_FCOE */ 106 return true; 107 } 108 109 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ 110 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, 111 unsigned int *tx, unsigned int *rx) 112 { 113 struct net_device *dev = adapter->netdev; 114 struct ixgbe_hw *hw = &adapter->hw; 115 u8 num_tcs = netdev_get_num_tc(dev); 116 117 *tx = 0; 118 *rx = 0; 119 120 switch (hw->mac.type) { 121 case ixgbe_mac_82598EB: 122 /* TxQs/TC: 4 RxQs/TC: 8 */ 123 *tx = tc << 2; /* 0, 4, 8, 12, 16, 20, 24, 28 */ 124 *rx = tc << 3; /* 0, 8, 16, 24, 32, 40, 48, 56 */ 125 break; 126 case ixgbe_mac_82599EB: 127 case ixgbe_mac_X540: 128 if (num_tcs > 4) { 129 /* 130 * TCs : TC0/1 TC2/3 TC4-7 131 * TxQs/TC: 32 16 8 132 * RxQs/TC: 16 16 16 133 */ 134 *rx = tc << 4; 135 if (tc < 3) 136 *tx = tc << 5; /* 0, 32, 64 */ 137 else if (tc < 5) 138 *tx = (tc + 2) << 4; /* 80, 96 */ 139 else 140 *tx = (tc + 8) << 3; /* 104, 112, 120 */ 141 } else { 142 /* 143 * TCs : TC0 TC1 TC2/3 144 * TxQs/TC: 64 32 16 145 * RxQs/TC: 32 32 32 146 */ 147 *rx = tc << 5; 148 if (tc < 2) 149 *tx = tc << 6; /* 0, 64 */ 150 else 151 *tx = (tc + 4) << 4; /* 96, 112 */ 152 } 153 default: 154 break; 155 } 156 } 157 158 /** 159 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB 160 * @adapter: board private structure to initialize 161 * 162 * Cache the descriptor ring offsets for DCB to the assigned rings. 163 * 164 **/ 165 static bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) 166 { 167 struct net_device *dev = adapter->netdev; 168 unsigned int tx_idx, rx_idx; 169 int tc, offset, rss_i, i; 170 u8 num_tcs = netdev_get_num_tc(dev); 171 172 /* verify we have DCB queueing enabled before proceeding */ 173 if (num_tcs <= 1) 174 return false; 175 176 rss_i = adapter->ring_feature[RING_F_RSS].indices; 177 178 for (tc = 0, offset = 0; tc < num_tcs; tc++, offset += rss_i) { 179 ixgbe_get_first_reg_idx(adapter, tc, &tx_idx, &rx_idx); 180 for (i = 0; i < rss_i; i++, tx_idx++, rx_idx++) { 181 adapter->tx_ring[offset + i]->reg_idx = tx_idx; 182 adapter->rx_ring[offset + i]->reg_idx = rx_idx; 183 adapter->tx_ring[offset + i]->dcb_tc = tc; 184 adapter->rx_ring[offset + i]->dcb_tc = tc; 185 } 186 } 187 188 return true; 189 } 190 191 #endif 192 /** 193 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov 194 * @adapter: board private structure to initialize 195 * 196 * SR-IOV doesn't use any descriptor rings but changes the default if 197 * no other mapping is used. 198 * 199 */ 200 static bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) 201 { 202 #ifdef IXGBE_FCOE 203 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; 204 #endif /* IXGBE_FCOE */ 205 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 206 struct ixgbe_ring_feature *rss = &adapter->ring_feature[RING_F_RSS]; 207 int i; 208 u16 reg_idx; 209 210 /* only proceed if VMDq is enabled */ 211 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)) 212 return false; 213 214 /* start at VMDq register offset for SR-IOV enabled setups */ 215 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 216 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { 217 #ifdef IXGBE_FCOE 218 /* Allow first FCoE queue to be mapped as RSS */ 219 if (fcoe->offset && (i > fcoe->offset)) 220 break; 221 #endif 222 /* If we are greater than indices move to next pool */ 223 if ((reg_idx & ~vmdq->mask) >= rss->indices) 224 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 225 adapter->rx_ring[i]->reg_idx = reg_idx; 226 } 227 228 #ifdef IXGBE_FCOE 229 /* FCoE uses a linear block of queues so just assigning 1:1 */ 230 for (; i < adapter->num_rx_queues; i++, reg_idx++) 231 adapter->rx_ring[i]->reg_idx = reg_idx; 232 233 #endif 234 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 235 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { 236 #ifdef IXGBE_FCOE 237 /* Allow first FCoE queue to be mapped as RSS */ 238 if (fcoe->offset && (i > fcoe->offset)) 239 break; 240 #endif 241 /* If we are greater than indices move to next pool */ 242 if ((reg_idx & rss->mask) >= rss->indices) 243 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 244 adapter->tx_ring[i]->reg_idx = reg_idx; 245 } 246 247 #ifdef IXGBE_FCOE 248 /* FCoE uses a linear block of queues so just assigning 1:1 */ 249 for (; i < adapter->num_tx_queues; i++, reg_idx++) 250 adapter->tx_ring[i]->reg_idx = reg_idx; 251 252 #endif 253 254 return true; 255 } 256 257 /** 258 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS 259 * @adapter: board private structure to initialize 260 * 261 * Cache the descriptor ring offsets for RSS to the assigned rings. 262 * 263 **/ 264 static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) 265 { 266 int i; 267 268 for (i = 0; i < adapter->num_rx_queues; i++) 269 adapter->rx_ring[i]->reg_idx = i; 270 for (i = 0; i < adapter->num_tx_queues; i++) 271 adapter->tx_ring[i]->reg_idx = i; 272 273 return true; 274 } 275 276 /** 277 * ixgbe_cache_ring_register - Descriptor ring to register mapping 278 * @adapter: board private structure to initialize 279 * 280 * Once we know the feature-set enabled for the device, we'll cache 281 * the register offset the descriptor ring is assigned to. 282 * 283 * Note, the order the various feature calls is important. It must start with 284 * the "most" features enabled at the same time, then trickle down to the 285 * least amount of features turned on at once. 286 **/ 287 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) 288 { 289 /* start with default case */ 290 adapter->rx_ring[0]->reg_idx = 0; 291 adapter->tx_ring[0]->reg_idx = 0; 292 293 #ifdef CONFIG_IXGBE_DCB 294 if (ixgbe_cache_ring_dcb_sriov(adapter)) 295 return; 296 297 if (ixgbe_cache_ring_dcb(adapter)) 298 return; 299 300 #endif 301 if (ixgbe_cache_ring_sriov(adapter)) 302 return; 303 304 ixgbe_cache_ring_rss(adapter); 305 } 306 307 #define IXGBE_RSS_16Q_MASK 0xF 308 #define IXGBE_RSS_8Q_MASK 0x7 309 #define IXGBE_RSS_4Q_MASK 0x3 310 #define IXGBE_RSS_2Q_MASK 0x1 311 #define IXGBE_RSS_DISABLED_MASK 0x0 312 313 #ifdef CONFIG_IXGBE_DCB 314 /** 315 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB 316 * @adapter: board private structure to initialize 317 * 318 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues 319 * and VM pools where appropriate. Also assign queues based on DCB 320 * priorities and map accordingly.. 321 * 322 **/ 323 static bool ixgbe_set_dcb_sriov_queues(struct ixgbe_adapter *adapter) 324 { 325 int i; 326 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; 327 u16 vmdq_m = 0; 328 #ifdef IXGBE_FCOE 329 u16 fcoe_i = 0; 330 #endif 331 u8 tcs = netdev_get_num_tc(adapter->netdev); 332 333 /* verify we have DCB queueing enabled before proceeding */ 334 if (tcs <= 1) 335 return false; 336 337 /* verify we have VMDq enabled before proceeding */ 338 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 339 return false; 340 341 /* Add starting offset to total pool count */ 342 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; 343 344 /* 16 pools w/ 8 TC per pool */ 345 if (tcs > 4) { 346 vmdq_i = min_t(u16, vmdq_i, 16); 347 vmdq_m = IXGBE_82599_VMDQ_8Q_MASK; 348 /* 32 pools w/ 4 TC per pool */ 349 } else { 350 vmdq_i = min_t(u16, vmdq_i, 32); 351 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK; 352 } 353 354 #ifdef IXGBE_FCOE 355 /* queues in the remaining pools are available for FCoE */ 356 fcoe_i = (128 / __ALIGN_MASK(1, ~vmdq_m)) - vmdq_i; 357 358 #endif 359 /* remove the starting offset from the pool count */ 360 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; 361 362 /* save features for later use */ 363 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; 364 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; 365 366 /* 367 * We do not support DCB, VMDq, and RSS all simultaneously 368 * so we will disable RSS since it is the lowest priority 369 */ 370 adapter->ring_feature[RING_F_RSS].indices = 1; 371 adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK; 372 373 /* disable ATR as it is not supported when VMDq is enabled */ 374 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 375 376 adapter->num_rx_pools = vmdq_i; 377 adapter->num_rx_queues_per_pool = tcs; 378 379 adapter->num_tx_queues = vmdq_i * tcs; 380 adapter->num_rx_queues = vmdq_i * tcs; 381 382 #ifdef IXGBE_FCOE 383 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 384 struct ixgbe_ring_feature *fcoe; 385 386 fcoe = &adapter->ring_feature[RING_F_FCOE]; 387 388 /* limit ourselves based on feature limits */ 389 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); 390 391 if (fcoe_i) { 392 /* alloc queues for FCoE separately */ 393 fcoe->indices = fcoe_i; 394 fcoe->offset = vmdq_i * tcs; 395 396 /* add queues to adapter */ 397 adapter->num_tx_queues += fcoe_i; 398 adapter->num_rx_queues += fcoe_i; 399 } else if (tcs > 1) { 400 /* use queue belonging to FcoE TC */ 401 fcoe->indices = 1; 402 fcoe->offset = ixgbe_fcoe_get_tc(adapter); 403 } else { 404 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 405 406 fcoe->indices = 0; 407 fcoe->offset = 0; 408 } 409 } 410 411 #endif /* IXGBE_FCOE */ 412 /* configure TC to queue mapping */ 413 for (i = 0; i < tcs; i++) 414 netdev_set_tc_queue(adapter->netdev, i, 1, i); 415 416 return true; 417 } 418 419 static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) 420 { 421 struct net_device *dev = adapter->netdev; 422 struct ixgbe_ring_feature *f; 423 int rss_i, rss_m, i; 424 int tcs; 425 426 /* Map queue offset and counts onto allocated tx queues */ 427 tcs = netdev_get_num_tc(dev); 428 429 /* verify we have DCB queueing enabled before proceeding */ 430 if (tcs <= 1) 431 return false; 432 433 /* determine the upper limit for our current DCB mode */ 434 rss_i = dev->num_tx_queues / tcs; 435 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 436 /* 8 TC w/ 4 queues per TC */ 437 rss_i = min_t(u16, rss_i, 4); 438 rss_m = IXGBE_RSS_4Q_MASK; 439 } else if (tcs > 4) { 440 /* 8 TC w/ 8 queues per TC */ 441 rss_i = min_t(u16, rss_i, 8); 442 rss_m = IXGBE_RSS_8Q_MASK; 443 } else { 444 /* 4 TC w/ 16 queues per TC */ 445 rss_i = min_t(u16, rss_i, 16); 446 rss_m = IXGBE_RSS_16Q_MASK; 447 } 448 449 /* set RSS mask and indices */ 450 f = &adapter->ring_feature[RING_F_RSS]; 451 rss_i = min_t(int, rss_i, f->limit); 452 f->indices = rss_i; 453 f->mask = rss_m; 454 455 /* disable ATR as it is not supported when multiple TCs are enabled */ 456 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 457 458 #ifdef IXGBE_FCOE 459 /* FCoE enabled queues require special configuration indexed 460 * by feature specific indices and offset. Here we map FCoE 461 * indices onto the DCB queue pairs allowing FCoE to own 462 * configuration later. 463 */ 464 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 465 u8 tc = ixgbe_fcoe_get_tc(adapter); 466 467 f = &adapter->ring_feature[RING_F_FCOE]; 468 f->indices = min_t(u16, rss_i, f->limit); 469 f->offset = rss_i * tc; 470 } 471 472 #endif /* IXGBE_FCOE */ 473 for (i = 0; i < tcs; i++) 474 netdev_set_tc_queue(dev, i, rss_i, rss_i * i); 475 476 adapter->num_tx_queues = rss_i * tcs; 477 adapter->num_rx_queues = rss_i * tcs; 478 479 return true; 480 } 481 482 #endif 483 /** 484 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices 485 * @adapter: board private structure to initialize 486 * 487 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues 488 * and VM pools where appropriate. If RSS is available, then also try and 489 * enable RSS and map accordingly. 490 * 491 **/ 492 static bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) 493 { 494 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; 495 u16 vmdq_m = 0; 496 u16 rss_i = adapter->ring_feature[RING_F_RSS].limit; 497 u16 rss_m = IXGBE_RSS_DISABLED_MASK; 498 #ifdef IXGBE_FCOE 499 u16 fcoe_i = 0; 500 #endif 501 502 /* only proceed if SR-IOV is enabled */ 503 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 504 return false; 505 506 /* Add starting offset to total pool count */ 507 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; 508 509 /* double check we are limited to maximum pools */ 510 vmdq_i = min_t(u16, IXGBE_MAX_VMDQ_INDICES, vmdq_i); 511 512 /* 64 pool mode with 2 queues per pool */ 513 if ((vmdq_i > 32) || (rss_i < 4)) { 514 vmdq_m = IXGBE_82599_VMDQ_2Q_MASK; 515 rss_m = IXGBE_RSS_2Q_MASK; 516 rss_i = min_t(u16, rss_i, 2); 517 /* 32 pool mode with 4 queues per pool */ 518 } else { 519 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK; 520 rss_m = IXGBE_RSS_4Q_MASK; 521 rss_i = 4; 522 } 523 524 #ifdef IXGBE_FCOE 525 /* queues in the remaining pools are available for FCoE */ 526 fcoe_i = 128 - (vmdq_i * __ALIGN_MASK(1, ~vmdq_m)); 527 528 #endif 529 /* remove the starting offset from the pool count */ 530 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; 531 532 /* save features for later use */ 533 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; 534 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; 535 536 /* limit RSS based on user input and save for later use */ 537 adapter->ring_feature[RING_F_RSS].indices = rss_i; 538 adapter->ring_feature[RING_F_RSS].mask = rss_m; 539 540 adapter->num_rx_pools = vmdq_i; 541 adapter->num_rx_queues_per_pool = rss_i; 542 543 adapter->num_rx_queues = vmdq_i * rss_i; 544 adapter->num_tx_queues = vmdq_i * rss_i; 545 546 /* disable ATR as it is not supported when VMDq is enabled */ 547 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 548 549 #ifdef IXGBE_FCOE 550 /* 551 * FCoE can use rings from adjacent buffers to allow RSS 552 * like behavior. To account for this we need to add the 553 * FCoE indices to the total ring count. 554 */ 555 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 556 struct ixgbe_ring_feature *fcoe; 557 558 fcoe = &adapter->ring_feature[RING_F_FCOE]; 559 560 /* limit ourselves based on feature limits */ 561 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); 562 563 if (vmdq_i > 1 && fcoe_i) { 564 /* alloc queues for FCoE separately */ 565 fcoe->indices = fcoe_i; 566 fcoe->offset = vmdq_i * rss_i; 567 } else { 568 /* merge FCoE queues with RSS queues */ 569 fcoe_i = min_t(u16, fcoe_i + rss_i, num_online_cpus()); 570 571 /* limit indices to rss_i if MSI-X is disabled */ 572 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 573 fcoe_i = rss_i; 574 575 /* attempt to reserve some queues for just FCoE */ 576 fcoe->indices = min_t(u16, fcoe_i, fcoe->limit); 577 fcoe->offset = fcoe_i - fcoe->indices; 578 579 fcoe_i -= rss_i; 580 } 581 582 /* add queues to adapter */ 583 adapter->num_tx_queues += fcoe_i; 584 adapter->num_rx_queues += fcoe_i; 585 } 586 587 #endif 588 return true; 589 } 590 591 /** 592 * ixgbe_set_rss_queues - Allocate queues for RSS 593 * @adapter: board private structure to initialize 594 * 595 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 596 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 597 * 598 **/ 599 static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) 600 { 601 struct ixgbe_ring_feature *f; 602 u16 rss_i; 603 604 /* set mask for 16 queue limit of RSS */ 605 f = &adapter->ring_feature[RING_F_RSS]; 606 rss_i = f->limit; 607 608 f->indices = rss_i; 609 f->mask = IXGBE_RSS_16Q_MASK; 610 611 /* disable ATR by default, it will be configured below */ 612 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 613 614 /* 615 * Use Flow Director in addition to RSS to ensure the best 616 * distribution of flows across cores, even when an FDIR flow 617 * isn't matched. 618 */ 619 if (rss_i > 1 && adapter->atr_sample_rate) { 620 f = &adapter->ring_feature[RING_F_FDIR]; 621 622 rss_i = f->indices = f->limit; 623 624 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 625 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 626 } 627 628 #ifdef IXGBE_FCOE 629 /* 630 * FCoE can exist on the same rings as standard network traffic 631 * however it is preferred to avoid that if possible. In order 632 * to get the best performance we allocate as many FCoE queues 633 * as we can and we place them at the end of the ring array to 634 * avoid sharing queues with standard RSS on systems with 24 or 635 * more CPUs. 636 */ 637 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 638 struct net_device *dev = adapter->netdev; 639 u16 fcoe_i; 640 641 f = &adapter->ring_feature[RING_F_FCOE]; 642 643 /* merge FCoE queues with RSS queues */ 644 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); 645 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); 646 647 /* limit indices to rss_i if MSI-X is disabled */ 648 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 649 fcoe_i = rss_i; 650 651 /* attempt to reserve some queues for just FCoE */ 652 f->indices = min_t(u16, fcoe_i, f->limit); 653 f->offset = fcoe_i - f->indices; 654 rss_i = max_t(u16, fcoe_i, rss_i); 655 } 656 657 #endif /* IXGBE_FCOE */ 658 adapter->num_rx_queues = rss_i; 659 adapter->num_tx_queues = rss_i; 660 661 return true; 662 } 663 664 /** 665 * ixgbe_set_num_queues - Allocate queues for device, feature dependent 666 * @adapter: board private structure to initialize 667 * 668 * This is the top level queue allocation routine. The order here is very 669 * important, starting with the "most" number of features turned on at once, 670 * and ending with the smallest set of features. This way large combinations 671 * can be allocated if they're turned on, and smaller combinations are the 672 * fallthrough conditions. 673 * 674 **/ 675 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) 676 { 677 /* Start with base case */ 678 adapter->num_rx_queues = 1; 679 adapter->num_tx_queues = 1; 680 adapter->num_rx_pools = adapter->num_rx_queues; 681 adapter->num_rx_queues_per_pool = 1; 682 683 #ifdef CONFIG_IXGBE_DCB 684 if (ixgbe_set_dcb_sriov_queues(adapter)) 685 return; 686 687 if (ixgbe_set_dcb_queues(adapter)) 688 return; 689 690 #endif 691 if (ixgbe_set_sriov_queues(adapter)) 692 return; 693 694 ixgbe_set_rss_queues(adapter); 695 } 696 697 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, 698 int vectors) 699 { 700 int err, vector_threshold; 701 702 /* We'll want at least 2 (vector_threshold): 703 * 1) TxQ[0] + RxQ[0] handler 704 * 2) Other (Link Status Change, etc.) 705 */ 706 vector_threshold = MIN_MSIX_COUNT; 707 708 /* 709 * The more we get, the more we will assign to Tx/Rx Cleanup 710 * for the separate queues...where Rx Cleanup >= Tx Cleanup. 711 * Right now, we simply care about how many we'll get; we'll 712 * set them up later while requesting irq's. 713 */ 714 while (vectors >= vector_threshold) { 715 err = pci_enable_msix(adapter->pdev, adapter->msix_entries, 716 vectors); 717 if (!err) /* Success in acquiring all requested vectors. */ 718 break; 719 else if (err < 0) 720 vectors = 0; /* Nasty failure, quit now */ 721 else /* err == number of vectors we should try again with */ 722 vectors = err; 723 } 724 725 if (vectors < vector_threshold) { 726 /* Can't allocate enough MSI-X interrupts? Oh well. 727 * This just means we'll go with either a single MSI 728 * vector or fall back to legacy interrupts. 729 */ 730 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 731 "Unable to allocate MSI-X interrupts\n"); 732 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 733 kfree(adapter->msix_entries); 734 adapter->msix_entries = NULL; 735 } else { 736 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ 737 /* 738 * Adjust for only the vectors we'll use, which is minimum 739 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of 740 * vectors we were allocated. 741 */ 742 vectors -= NON_Q_VECTORS; 743 adapter->num_q_vectors = min(vectors, adapter->max_q_vectors); 744 } 745 } 746 747 static void ixgbe_add_ring(struct ixgbe_ring *ring, 748 struct ixgbe_ring_container *head) 749 { 750 ring->next = head->ring; 751 head->ring = ring; 752 head->count++; 753 } 754 755 /** 756 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector 757 * @adapter: board private structure to initialize 758 * @v_count: q_vectors allocated on adapter, used for ring interleaving 759 * @v_idx: index of vector in adapter struct 760 * @txr_count: total number of Tx rings to allocate 761 * @txr_idx: index of first Tx ring to allocate 762 * @rxr_count: total number of Rx rings to allocate 763 * @rxr_idx: index of first Rx ring to allocate 764 * 765 * We allocate one q_vector. If allocation fails we return -ENOMEM. 766 **/ 767 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, 768 int v_count, int v_idx, 769 int txr_count, int txr_idx, 770 int rxr_count, int rxr_idx) 771 { 772 struct ixgbe_q_vector *q_vector; 773 struct ixgbe_ring *ring; 774 int node = NUMA_NO_NODE; 775 int cpu = -1; 776 int ring_count, size; 777 u8 tcs = netdev_get_num_tc(adapter->netdev); 778 779 ring_count = txr_count + rxr_count; 780 size = sizeof(struct ixgbe_q_vector) + 781 (sizeof(struct ixgbe_ring) * ring_count); 782 783 /* customize cpu for Flow Director mapping */ 784 if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 785 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 786 if (rss_i > 1 && adapter->atr_sample_rate) { 787 if (cpu_online(v_idx)) { 788 cpu = v_idx; 789 node = cpu_to_node(cpu); 790 } 791 } 792 } 793 794 /* allocate q_vector and rings */ 795 q_vector = kzalloc_node(size, GFP_KERNEL, node); 796 if (!q_vector) 797 q_vector = kzalloc(size, GFP_KERNEL); 798 if (!q_vector) 799 return -ENOMEM; 800 801 /* setup affinity mask and node */ 802 if (cpu != -1) 803 cpumask_set_cpu(cpu, &q_vector->affinity_mask); 804 q_vector->numa_node = node; 805 806 #ifdef CONFIG_IXGBE_DCA 807 /* initialize CPU for DCA */ 808 q_vector->cpu = -1; 809 810 #endif 811 /* initialize NAPI */ 812 netif_napi_add(adapter->netdev, &q_vector->napi, 813 ixgbe_poll, 64); 814 napi_hash_add(&q_vector->napi); 815 816 /* tie q_vector and adapter together */ 817 adapter->q_vector[v_idx] = q_vector; 818 q_vector->adapter = adapter; 819 q_vector->v_idx = v_idx; 820 821 /* initialize work limits */ 822 q_vector->tx.work_limit = adapter->tx_work_limit; 823 824 /* initialize pointer to rings */ 825 ring = q_vector->ring; 826 827 /* intialize ITR */ 828 if (txr_count && !rxr_count) { 829 /* tx only vector */ 830 if (adapter->tx_itr_setting == 1) 831 q_vector->itr = IXGBE_10K_ITR; 832 else 833 q_vector->itr = adapter->tx_itr_setting; 834 } else { 835 /* rx or rx/tx vector */ 836 if (adapter->rx_itr_setting == 1) 837 q_vector->itr = IXGBE_20K_ITR; 838 else 839 q_vector->itr = adapter->rx_itr_setting; 840 } 841 842 while (txr_count) { 843 /* assign generic ring traits */ 844 ring->dev = &adapter->pdev->dev; 845 ring->netdev = adapter->netdev; 846 847 /* configure backlink on ring */ 848 ring->q_vector = q_vector; 849 850 /* update q_vector Tx values */ 851 ixgbe_add_ring(ring, &q_vector->tx); 852 853 /* apply Tx specific ring traits */ 854 ring->count = adapter->tx_ring_count; 855 ring->queue_index = txr_idx; 856 857 /* assign ring to adapter */ 858 adapter->tx_ring[txr_idx] = ring; 859 860 /* update count and index */ 861 txr_count--; 862 txr_idx += v_count; 863 864 /* push pointer to next ring */ 865 ring++; 866 } 867 868 while (rxr_count) { 869 /* assign generic ring traits */ 870 ring->dev = &adapter->pdev->dev; 871 ring->netdev = adapter->netdev; 872 873 /* configure backlink on ring */ 874 ring->q_vector = q_vector; 875 876 /* update q_vector Rx values */ 877 ixgbe_add_ring(ring, &q_vector->rx); 878 879 /* 880 * 82599 errata, UDP frames with a 0 checksum 881 * can be marked as checksum errors. 882 */ 883 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 884 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); 885 886 #ifdef IXGBE_FCOE 887 if (adapter->netdev->features & NETIF_F_FCOE_MTU) { 888 struct ixgbe_ring_feature *f; 889 f = &adapter->ring_feature[RING_F_FCOE]; 890 if ((rxr_idx >= f->offset) && 891 (rxr_idx < f->offset + f->indices)) 892 set_bit(__IXGBE_RX_FCOE, &ring->state); 893 } 894 895 #endif /* IXGBE_FCOE */ 896 /* apply Rx specific ring traits */ 897 ring->count = adapter->rx_ring_count; 898 ring->queue_index = rxr_idx; 899 900 /* assign ring to adapter */ 901 adapter->rx_ring[rxr_idx] = ring; 902 903 /* update count and index */ 904 rxr_count--; 905 rxr_idx += v_count; 906 907 /* push pointer to next ring */ 908 ring++; 909 } 910 911 return 0; 912 } 913 914 /** 915 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector 916 * @adapter: board private structure to initialize 917 * @v_idx: Index of vector to be freed 918 * 919 * This function frees the memory allocated to the q_vector. In addition if 920 * NAPI is enabled it will delete any references to the NAPI struct prior 921 * to freeing the q_vector. 922 **/ 923 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx) 924 { 925 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; 926 struct ixgbe_ring *ring; 927 928 ixgbe_for_each_ring(ring, q_vector->tx) 929 adapter->tx_ring[ring->queue_index] = NULL; 930 931 ixgbe_for_each_ring(ring, q_vector->rx) 932 adapter->rx_ring[ring->queue_index] = NULL; 933 934 adapter->q_vector[v_idx] = NULL; 935 napi_hash_del(&q_vector->napi); 936 netif_napi_del(&q_vector->napi); 937 938 /* 939 * ixgbe_get_stats64() might access the rings on this vector, 940 * we must wait a grace period before freeing it. 941 */ 942 kfree_rcu(q_vector, rcu); 943 } 944 945 /** 946 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors 947 * @adapter: board private structure to initialize 948 * 949 * We allocate one q_vector per queue interrupt. If allocation fails we 950 * return -ENOMEM. 951 **/ 952 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) 953 { 954 int q_vectors = adapter->num_q_vectors; 955 int rxr_remaining = adapter->num_rx_queues; 956 int txr_remaining = adapter->num_tx_queues; 957 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 958 int err; 959 960 /* only one q_vector if MSI-X is disabled. */ 961 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 962 q_vectors = 1; 963 964 if (q_vectors >= (rxr_remaining + txr_remaining)) { 965 for (; rxr_remaining; v_idx++) { 966 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 967 0, 0, 1, rxr_idx); 968 969 if (err) 970 goto err_out; 971 972 /* update counts and index */ 973 rxr_remaining--; 974 rxr_idx++; 975 } 976 } 977 978 for (; v_idx < q_vectors; v_idx++) { 979 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 980 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 981 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 982 tqpv, txr_idx, 983 rqpv, rxr_idx); 984 985 if (err) 986 goto err_out; 987 988 /* update counts and index */ 989 rxr_remaining -= rqpv; 990 txr_remaining -= tqpv; 991 rxr_idx++; 992 txr_idx++; 993 } 994 995 return 0; 996 997 err_out: 998 adapter->num_tx_queues = 0; 999 adapter->num_rx_queues = 0; 1000 adapter->num_q_vectors = 0; 1001 1002 while (v_idx--) 1003 ixgbe_free_q_vector(adapter, v_idx); 1004 1005 return -ENOMEM; 1006 } 1007 1008 /** 1009 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors 1010 * @adapter: board private structure to initialize 1011 * 1012 * This function frees the memory allocated to the q_vectors. In addition if 1013 * NAPI is enabled it will delete any references to the NAPI struct prior 1014 * to freeing the q_vector. 1015 **/ 1016 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) 1017 { 1018 int v_idx = adapter->num_q_vectors; 1019 1020 adapter->num_tx_queues = 0; 1021 adapter->num_rx_queues = 0; 1022 adapter->num_q_vectors = 0; 1023 1024 while (v_idx--) 1025 ixgbe_free_q_vector(adapter, v_idx); 1026 } 1027 1028 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) 1029 { 1030 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 1031 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 1032 pci_disable_msix(adapter->pdev); 1033 kfree(adapter->msix_entries); 1034 adapter->msix_entries = NULL; 1035 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1036 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; 1037 pci_disable_msi(adapter->pdev); 1038 } 1039 } 1040 1041 /** 1042 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported 1043 * @adapter: board private structure to initialize 1044 * 1045 * Attempt to configure the interrupts using the best available 1046 * capabilities of the hardware and the kernel. 1047 **/ 1048 static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) 1049 { 1050 struct ixgbe_hw *hw = &adapter->hw; 1051 int vector, v_budget, err; 1052 1053 /* 1054 * It's easy to be greedy for MSI-X vectors, but it really 1055 * doesn't do us much good if we have a lot more vectors 1056 * than CPU's. So let's be conservative and only ask for 1057 * (roughly) the same number of vectors as there are CPU's. 1058 * The default is to use pairs of vectors. 1059 */ 1060 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); 1061 v_budget = min_t(int, v_budget, num_online_cpus()); 1062 v_budget += NON_Q_VECTORS; 1063 1064 /* 1065 * At the same time, hardware can only support a maximum of 1066 * hw.mac->max_msix_vectors vectors. With features 1067 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx 1068 * descriptor queues supported by our device. Thus, we cap it off in 1069 * those rare cases where the cpu count also exceeds our vector limit. 1070 */ 1071 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); 1072 1073 /* A failure in MSI-X entry allocation isn't fatal, but it does 1074 * mean we disable MSI-X capabilities of the adapter. */ 1075 adapter->msix_entries = kcalloc(v_budget, 1076 sizeof(struct msix_entry), GFP_KERNEL); 1077 if (adapter->msix_entries) { 1078 for (vector = 0; vector < v_budget; vector++) 1079 adapter->msix_entries[vector].entry = vector; 1080 1081 ixgbe_acquire_msix_vectors(adapter, v_budget); 1082 1083 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 1084 return; 1085 } 1086 1087 /* disable DCB if number of TCs exceeds 1 */ 1088 if (netdev_get_num_tc(adapter->netdev) > 1) { 1089 e_err(probe, "num TCs exceeds number of queues - disabling DCB\n"); 1090 netdev_reset_tc(adapter->netdev); 1091 1092 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 1093 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 1094 1095 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1096 adapter->temp_dcb_cfg.pfc_mode_enable = false; 1097 adapter->dcb_cfg.pfc_mode_enable = false; 1098 } 1099 adapter->dcb_cfg.num_tcs.pg_tcs = 1; 1100 adapter->dcb_cfg.num_tcs.pfc_tcs = 1; 1101 1102 /* disable SR-IOV */ 1103 ixgbe_disable_sriov(adapter); 1104 1105 /* disable RSS */ 1106 adapter->ring_feature[RING_F_RSS].limit = 1; 1107 1108 ixgbe_set_num_queues(adapter); 1109 adapter->num_q_vectors = 1; 1110 1111 err = pci_enable_msi(adapter->pdev); 1112 if (err) { 1113 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 1114 "Unable to allocate MSI interrupt, " 1115 "falling back to legacy. Error: %d\n", err); 1116 return; 1117 } 1118 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; 1119 } 1120 1121 /** 1122 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme 1123 * @adapter: board private structure to initialize 1124 * 1125 * We determine which interrupt scheme to use based on... 1126 * - Kernel support (MSI, MSI-X) 1127 * - which can be user-defined (via MODULE_PARAM) 1128 * - Hardware queue count (num_*_queues) 1129 * - defined by miscellaneous hardware support/features (RSS, etc.) 1130 **/ 1131 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) 1132 { 1133 int err; 1134 1135 /* Number of supported queues */ 1136 ixgbe_set_num_queues(adapter); 1137 1138 /* Set interrupt mode */ 1139 ixgbe_set_interrupt_capability(adapter); 1140 1141 err = ixgbe_alloc_q_vectors(adapter); 1142 if (err) { 1143 e_dev_err("Unable to allocate memory for queue vectors\n"); 1144 goto err_alloc_q_vectors; 1145 } 1146 1147 ixgbe_cache_ring_register(adapter); 1148 1149 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", 1150 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", 1151 adapter->num_rx_queues, adapter->num_tx_queues); 1152 1153 set_bit(__IXGBE_DOWN, &adapter->state); 1154 1155 return 0; 1156 1157 err_alloc_q_vectors: 1158 ixgbe_reset_interrupt_capability(adapter); 1159 return err; 1160 } 1161 1162 /** 1163 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings 1164 * @adapter: board private structure to clear interrupt scheme on 1165 * 1166 * We go through and clear interrupt specific resources and reset the structure 1167 * to pre-load conditions 1168 **/ 1169 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) 1170 { 1171 adapter->num_tx_queues = 0; 1172 adapter->num_rx_queues = 0; 1173 1174 ixgbe_free_q_vectors(adapter); 1175 ixgbe_reset_interrupt_capability(adapter); 1176 } 1177 1178 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, 1179 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1180 { 1181 struct ixgbe_adv_tx_context_desc *context_desc; 1182 u16 i = tx_ring->next_to_use; 1183 1184 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i); 1185 1186 i++; 1187 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1188 1189 /* set bits to identify this as an advanced context descriptor */ 1190 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; 1191 1192 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1193 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1194 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1195 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1196 } 1197 1198