1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include "ixgbe.h" 29 #include "ixgbe_sriov.h" 30 31 #ifdef CONFIG_IXGBE_DCB 32 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ 33 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, 34 unsigned int *tx, unsigned int *rx) 35 { 36 struct net_device *dev = adapter->netdev; 37 struct ixgbe_hw *hw = &adapter->hw; 38 u8 num_tcs = netdev_get_num_tc(dev); 39 40 *tx = 0; 41 *rx = 0; 42 43 switch (hw->mac.type) { 44 case ixgbe_mac_82598EB: 45 *tx = tc << 2; 46 *rx = tc << 3; 47 break; 48 case ixgbe_mac_82599EB: 49 case ixgbe_mac_X540: 50 if (num_tcs > 4) { 51 if (tc < 3) { 52 *tx = tc << 5; 53 *rx = tc << 4; 54 } else if (tc < 5) { 55 *tx = ((tc + 2) << 4); 56 *rx = tc << 4; 57 } else if (tc < num_tcs) { 58 *tx = ((tc + 8) << 3); 59 *rx = tc << 4; 60 } 61 } else { 62 *rx = tc << 5; 63 switch (tc) { 64 case 0: 65 *tx = 0; 66 break; 67 case 1: 68 *tx = 64; 69 break; 70 case 2: 71 *tx = 96; 72 break; 73 case 3: 74 *tx = 112; 75 break; 76 default: 77 break; 78 } 79 } 80 break; 81 default: 82 break; 83 } 84 } 85 86 /** 87 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB 88 * @adapter: board private structure to initialize 89 * 90 * Cache the descriptor ring offsets for DCB to the assigned rings. 91 * 92 **/ 93 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) 94 { 95 struct net_device *dev = adapter->netdev; 96 int i, j, k; 97 u8 num_tcs = netdev_get_num_tc(dev); 98 99 if (!num_tcs) 100 return false; 101 102 for (i = 0, k = 0; i < num_tcs; i++) { 103 unsigned int tx_s, rx_s; 104 u16 count = dev->tc_to_txq[i].count; 105 106 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); 107 for (j = 0; j < count; j++, k++) { 108 adapter->tx_ring[k]->reg_idx = tx_s + j; 109 adapter->rx_ring[k]->reg_idx = rx_s + j; 110 adapter->tx_ring[k]->dcb_tc = i; 111 adapter->rx_ring[k]->dcb_tc = i; 112 } 113 } 114 115 return true; 116 } 117 118 #endif 119 /** 120 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov 121 * @adapter: board private structure to initialize 122 * 123 * SR-IOV doesn't use any descriptor rings but changes the default if 124 * no other mapping is used. 125 * 126 */ 127 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) 128 { 129 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; 130 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; 131 if (adapter->num_vfs) 132 return true; 133 else 134 return false; 135 } 136 137 /** 138 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS 139 * @adapter: board private structure to initialize 140 * 141 * Cache the descriptor ring offsets for RSS to the assigned rings. 142 * 143 **/ 144 static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) 145 { 146 int i; 147 148 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) 149 return false; 150 151 for (i = 0; i < adapter->num_rx_queues; i++) 152 adapter->rx_ring[i]->reg_idx = i; 153 for (i = 0; i < adapter->num_tx_queues; i++) 154 adapter->tx_ring[i]->reg_idx = i; 155 156 return true; 157 } 158 159 /** 160 * ixgbe_cache_ring_register - Descriptor ring to register mapping 161 * @adapter: board private structure to initialize 162 * 163 * Once we know the feature-set enabled for the device, we'll cache 164 * the register offset the descriptor ring is assigned to. 165 * 166 * Note, the order the various feature calls is important. It must start with 167 * the "most" features enabled at the same time, then trickle down to the 168 * least amount of features turned on at once. 169 **/ 170 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) 171 { 172 /* start with default case */ 173 adapter->rx_ring[0]->reg_idx = 0; 174 adapter->tx_ring[0]->reg_idx = 0; 175 176 if (ixgbe_cache_ring_sriov(adapter)) 177 return; 178 179 #ifdef CONFIG_IXGBE_DCB 180 if (ixgbe_cache_ring_dcb(adapter)) 181 return; 182 #endif 183 184 ixgbe_cache_ring_rss(adapter); 185 } 186 187 /** 188 * ixgbe_set_sriov_queues - Allocate queues for IOV use 189 * @adapter: board private structure to initialize 190 * 191 * IOV doesn't actually use anything, so just NAK the 192 * request for now and let the other queue routines 193 * figure out what to do. 194 */ 195 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) 196 { 197 return false; 198 } 199 200 #define IXGBE_RSS_16Q_MASK 0xF 201 #define IXGBE_RSS_8Q_MASK 0x7 202 #define IXGBE_RSS_4Q_MASK 0x3 203 #define IXGBE_RSS_2Q_MASK 0x1 204 #define IXGBE_RSS_DISABLED_MASK 0x0 205 206 #ifdef CONFIG_IXGBE_DCB 207 static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) 208 { 209 struct net_device *dev = adapter->netdev; 210 struct ixgbe_ring_feature *f; 211 int rss_i, rss_m, i; 212 int tcs; 213 214 /* Map queue offset and counts onto allocated tx queues */ 215 tcs = netdev_get_num_tc(dev); 216 217 /* verify we have DCB queueing enabled before proceeding */ 218 if (tcs <= 1) 219 return false; 220 221 /* determine the upper limit for our current DCB mode */ 222 rss_i = dev->num_tx_queues / tcs; 223 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 224 /* 8 TC w/ 4 queues per TC */ 225 rss_i = min_t(u16, rss_i, 4); 226 rss_m = IXGBE_RSS_4Q_MASK; 227 } else if (tcs > 4) { 228 /* 8 TC w/ 8 queues per TC */ 229 rss_i = min_t(u16, rss_i, 8); 230 rss_m = IXGBE_RSS_8Q_MASK; 231 } else { 232 /* 4 TC w/ 16 queues per TC */ 233 rss_i = min_t(u16, rss_i, 16); 234 rss_m = IXGBE_RSS_16Q_MASK; 235 } 236 237 /* set RSS mask and indices */ 238 f = &adapter->ring_feature[RING_F_RSS]; 239 rss_i = min_t(int, rss_i, f->limit); 240 f->indices = rss_i; 241 f->mask = rss_m; 242 243 #ifdef IXGBE_FCOE 244 /* FCoE enabled queues require special configuration indexed 245 * by feature specific indices and offset. Here we map FCoE 246 * indices onto the DCB queue pairs allowing FCoE to own 247 * configuration later. 248 */ 249 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 250 u8 tc = ixgbe_fcoe_get_tc(adapter); 251 252 f = &adapter->ring_feature[RING_F_FCOE]; 253 f->indices = min_t(u16, rss_i, f->limit); 254 f->offset = rss_i * tc; 255 } 256 257 #endif /* IXGBE_FCOE */ 258 for (i = 0; i < tcs; i++) 259 netdev_set_tc_queue(dev, i, rss_i, rss_i * i); 260 261 adapter->num_tx_queues = rss_i * tcs; 262 adapter->num_rx_queues = rss_i * tcs; 263 264 return true; 265 } 266 267 #endif 268 /** 269 * ixgbe_set_rss_queues - Allocate queues for RSS 270 * @adapter: board private structure to initialize 271 * 272 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 273 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 274 * 275 **/ 276 static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) 277 { 278 struct ixgbe_ring_feature *f; 279 u16 rss_i; 280 281 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { 282 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 283 return false; 284 } 285 286 /* set mask for 16 queue limit of RSS */ 287 f = &adapter->ring_feature[RING_F_RSS]; 288 rss_i = f->limit; 289 290 f->indices = rss_i; 291 f->mask = IXGBE_RSS_16Q_MASK; 292 293 /* 294 * Use Flow Director in addition to RSS to ensure the best 295 * distribution of flows across cores, even when an FDIR flow 296 * isn't matched. 297 */ 298 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 299 f = &adapter->ring_feature[RING_F_FDIR]; 300 301 f->indices = min_t(u16, num_online_cpus(), f->limit); 302 rss_i = max_t(u16, rss_i, f->indices); 303 } 304 305 #ifdef IXGBE_FCOE 306 /* 307 * FCoE can exist on the same rings as standard network traffic 308 * however it is preferred to avoid that if possible. In order 309 * to get the best performance we allocate as many FCoE queues 310 * as we can and we place them at the end of the ring array to 311 * avoid sharing queues with standard RSS on systems with 24 or 312 * more CPUs. 313 */ 314 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 315 struct net_device *dev = adapter->netdev; 316 u16 fcoe_i; 317 318 f = &adapter->ring_feature[RING_F_FCOE]; 319 320 /* merge FCoE queues with RSS queues */ 321 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); 322 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); 323 324 /* limit indices to rss_i if MSI-X is disabled */ 325 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 326 fcoe_i = rss_i; 327 328 /* attempt to reserve some queues for just FCoE */ 329 f->indices = min_t(u16, fcoe_i, f->limit); 330 f->offset = fcoe_i - f->indices; 331 rss_i = max_t(u16, fcoe_i, rss_i); 332 } 333 334 #endif /* IXGBE_FCOE */ 335 adapter->num_rx_queues = rss_i; 336 adapter->num_tx_queues = rss_i; 337 338 return true; 339 } 340 341 /** 342 * ixgbe_set_num_queues - Allocate queues for device, feature dependent 343 * @adapter: board private structure to initialize 344 * 345 * This is the top level queue allocation routine. The order here is very 346 * important, starting with the "most" number of features turned on at once, 347 * and ending with the smallest set of features. This way large combinations 348 * can be allocated if they're turned on, and smaller combinations are the 349 * fallthrough conditions. 350 * 351 **/ 352 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) 353 { 354 /* Start with base case */ 355 adapter->num_rx_queues = 1; 356 adapter->num_tx_queues = 1; 357 adapter->num_rx_pools = adapter->num_rx_queues; 358 adapter->num_rx_queues_per_pool = 1; 359 360 if (ixgbe_set_sriov_queues(adapter)) 361 goto done; 362 363 #ifdef CONFIG_IXGBE_DCB 364 if (ixgbe_set_dcb_queues(adapter)) 365 goto done; 366 367 #endif 368 if (ixgbe_set_rss_queues(adapter)) 369 goto done; 370 371 /* fallback to base case */ 372 adapter->num_rx_queues = 1; 373 adapter->num_tx_queues = 1; 374 375 done: 376 if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) || 377 (adapter->netdev->reg_state == NETREG_UNREGISTERING)) 378 return 0; 379 380 /* Notify the stack of the (possibly) reduced queue counts. */ 381 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 382 return netif_set_real_num_rx_queues(adapter->netdev, 383 adapter->num_rx_queues); 384 } 385 386 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, 387 int vectors) 388 { 389 int err, vector_threshold; 390 391 /* We'll want at least 2 (vector_threshold): 392 * 1) TxQ[0] + RxQ[0] handler 393 * 2) Other (Link Status Change, etc.) 394 */ 395 vector_threshold = MIN_MSIX_COUNT; 396 397 /* 398 * The more we get, the more we will assign to Tx/Rx Cleanup 399 * for the separate queues...where Rx Cleanup >= Tx Cleanup. 400 * Right now, we simply care about how many we'll get; we'll 401 * set them up later while requesting irq's. 402 */ 403 while (vectors >= vector_threshold) { 404 err = pci_enable_msix(adapter->pdev, adapter->msix_entries, 405 vectors); 406 if (!err) /* Success in acquiring all requested vectors. */ 407 break; 408 else if (err < 0) 409 vectors = 0; /* Nasty failure, quit now */ 410 else /* err == number of vectors we should try again with */ 411 vectors = err; 412 } 413 414 if (vectors < vector_threshold) { 415 /* Can't allocate enough MSI-X interrupts? Oh well. 416 * This just means we'll go with either a single MSI 417 * vector or fall back to legacy interrupts. 418 */ 419 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 420 "Unable to allocate MSI-X interrupts\n"); 421 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 422 kfree(adapter->msix_entries); 423 adapter->msix_entries = NULL; 424 } else { 425 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ 426 /* 427 * Adjust for only the vectors we'll use, which is minimum 428 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of 429 * vectors we were allocated. 430 */ 431 vectors -= NON_Q_VECTORS; 432 adapter->num_q_vectors = min(vectors, adapter->max_q_vectors); 433 } 434 } 435 436 static void ixgbe_add_ring(struct ixgbe_ring *ring, 437 struct ixgbe_ring_container *head) 438 { 439 ring->next = head->ring; 440 head->ring = ring; 441 head->count++; 442 } 443 444 /** 445 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector 446 * @adapter: board private structure to initialize 447 * @v_count: q_vectors allocated on adapter, used for ring interleaving 448 * @v_idx: index of vector in adapter struct 449 * @txr_count: total number of Tx rings to allocate 450 * @txr_idx: index of first Tx ring to allocate 451 * @rxr_count: total number of Rx rings to allocate 452 * @rxr_idx: index of first Rx ring to allocate 453 * 454 * We allocate one q_vector. If allocation fails we return -ENOMEM. 455 **/ 456 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, 457 int v_count, int v_idx, 458 int txr_count, int txr_idx, 459 int rxr_count, int rxr_idx) 460 { 461 struct ixgbe_q_vector *q_vector; 462 struct ixgbe_ring *ring; 463 int node = -1; 464 int cpu = -1; 465 int ring_count, size; 466 467 ring_count = txr_count + rxr_count; 468 size = sizeof(struct ixgbe_q_vector) + 469 (sizeof(struct ixgbe_ring) * ring_count); 470 471 /* customize cpu for Flow Director mapping */ 472 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 473 if (cpu_online(v_idx)) { 474 cpu = v_idx; 475 node = cpu_to_node(cpu); 476 } 477 } 478 479 /* allocate q_vector and rings */ 480 q_vector = kzalloc_node(size, GFP_KERNEL, node); 481 if (!q_vector) 482 q_vector = kzalloc(size, GFP_KERNEL); 483 if (!q_vector) 484 return -ENOMEM; 485 486 /* setup affinity mask and node */ 487 if (cpu != -1) 488 cpumask_set_cpu(cpu, &q_vector->affinity_mask); 489 else 490 cpumask_copy(&q_vector->affinity_mask, cpu_online_mask); 491 q_vector->numa_node = node; 492 493 /* initialize NAPI */ 494 netif_napi_add(adapter->netdev, &q_vector->napi, 495 ixgbe_poll, 64); 496 497 /* tie q_vector and adapter together */ 498 adapter->q_vector[v_idx] = q_vector; 499 q_vector->adapter = adapter; 500 q_vector->v_idx = v_idx; 501 502 /* initialize work limits */ 503 q_vector->tx.work_limit = adapter->tx_work_limit; 504 505 /* initialize pointer to rings */ 506 ring = q_vector->ring; 507 508 while (txr_count) { 509 /* assign generic ring traits */ 510 ring->dev = &adapter->pdev->dev; 511 ring->netdev = adapter->netdev; 512 513 /* configure backlink on ring */ 514 ring->q_vector = q_vector; 515 516 /* update q_vector Tx values */ 517 ixgbe_add_ring(ring, &q_vector->tx); 518 519 /* apply Tx specific ring traits */ 520 ring->count = adapter->tx_ring_count; 521 ring->queue_index = txr_idx; 522 523 /* assign ring to adapter */ 524 adapter->tx_ring[txr_idx] = ring; 525 526 /* update count and index */ 527 txr_count--; 528 txr_idx += v_count; 529 530 /* push pointer to next ring */ 531 ring++; 532 } 533 534 while (rxr_count) { 535 /* assign generic ring traits */ 536 ring->dev = &adapter->pdev->dev; 537 ring->netdev = adapter->netdev; 538 539 /* configure backlink on ring */ 540 ring->q_vector = q_vector; 541 542 /* update q_vector Rx values */ 543 ixgbe_add_ring(ring, &q_vector->rx); 544 545 /* 546 * 82599 errata, UDP frames with a 0 checksum 547 * can be marked as checksum errors. 548 */ 549 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 550 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); 551 552 #ifdef IXGBE_FCOE 553 if (adapter->netdev->features & NETIF_F_FCOE_MTU) { 554 struct ixgbe_ring_feature *f; 555 f = &adapter->ring_feature[RING_F_FCOE]; 556 if ((rxr_idx >= f->offset) && 557 (rxr_idx < f->offset + f->indices)) 558 set_bit(__IXGBE_RX_FCOE, &ring->state); 559 } 560 561 #endif /* IXGBE_FCOE */ 562 /* apply Rx specific ring traits */ 563 ring->count = adapter->rx_ring_count; 564 ring->queue_index = rxr_idx; 565 566 /* assign ring to adapter */ 567 adapter->rx_ring[rxr_idx] = ring; 568 569 /* update count and index */ 570 rxr_count--; 571 rxr_idx += v_count; 572 573 /* push pointer to next ring */ 574 ring++; 575 } 576 577 return 0; 578 } 579 580 /** 581 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector 582 * @adapter: board private structure to initialize 583 * @v_idx: Index of vector to be freed 584 * 585 * This function frees the memory allocated to the q_vector. In addition if 586 * NAPI is enabled it will delete any references to the NAPI struct prior 587 * to freeing the q_vector. 588 **/ 589 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx) 590 { 591 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; 592 struct ixgbe_ring *ring; 593 594 ixgbe_for_each_ring(ring, q_vector->tx) 595 adapter->tx_ring[ring->queue_index] = NULL; 596 597 ixgbe_for_each_ring(ring, q_vector->rx) 598 adapter->rx_ring[ring->queue_index] = NULL; 599 600 adapter->q_vector[v_idx] = NULL; 601 netif_napi_del(&q_vector->napi); 602 603 /* 604 * ixgbe_get_stats64() might access the rings on this vector, 605 * we must wait a grace period before freeing it. 606 */ 607 kfree_rcu(q_vector, rcu); 608 } 609 610 /** 611 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors 612 * @adapter: board private structure to initialize 613 * 614 * We allocate one q_vector per queue interrupt. If allocation fails we 615 * return -ENOMEM. 616 **/ 617 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) 618 { 619 int q_vectors = adapter->num_q_vectors; 620 int rxr_remaining = adapter->num_rx_queues; 621 int txr_remaining = adapter->num_tx_queues; 622 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 623 int err; 624 625 /* only one q_vector if MSI-X is disabled. */ 626 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 627 q_vectors = 1; 628 629 if (q_vectors >= (rxr_remaining + txr_remaining)) { 630 for (; rxr_remaining; v_idx++) { 631 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 632 0, 0, 1, rxr_idx); 633 634 if (err) 635 goto err_out; 636 637 /* update counts and index */ 638 rxr_remaining--; 639 rxr_idx++; 640 } 641 } 642 643 for (; v_idx < q_vectors; v_idx++) { 644 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 645 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 646 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 647 tqpv, txr_idx, 648 rqpv, rxr_idx); 649 650 if (err) 651 goto err_out; 652 653 /* update counts and index */ 654 rxr_remaining -= rqpv; 655 txr_remaining -= tqpv; 656 rxr_idx++; 657 txr_idx++; 658 } 659 660 return 0; 661 662 err_out: 663 adapter->num_tx_queues = 0; 664 adapter->num_rx_queues = 0; 665 adapter->num_q_vectors = 0; 666 667 while (v_idx--) 668 ixgbe_free_q_vector(adapter, v_idx); 669 670 return -ENOMEM; 671 } 672 673 /** 674 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors 675 * @adapter: board private structure to initialize 676 * 677 * This function frees the memory allocated to the q_vectors. In addition if 678 * NAPI is enabled it will delete any references to the NAPI struct prior 679 * to freeing the q_vector. 680 **/ 681 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) 682 { 683 int v_idx = adapter->num_q_vectors; 684 685 adapter->num_tx_queues = 0; 686 adapter->num_rx_queues = 0; 687 adapter->num_q_vectors = 0; 688 689 while (v_idx--) 690 ixgbe_free_q_vector(adapter, v_idx); 691 } 692 693 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) 694 { 695 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 696 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 697 pci_disable_msix(adapter->pdev); 698 kfree(adapter->msix_entries); 699 adapter->msix_entries = NULL; 700 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 701 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; 702 pci_disable_msi(adapter->pdev); 703 } 704 } 705 706 /** 707 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported 708 * @adapter: board private structure to initialize 709 * 710 * Attempt to configure the interrupts using the best available 711 * capabilities of the hardware and the kernel. 712 **/ 713 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) 714 { 715 struct ixgbe_hw *hw = &adapter->hw; 716 int err = 0; 717 int vector, v_budget; 718 719 /* 720 * It's easy to be greedy for MSI-X vectors, but it really 721 * doesn't do us much good if we have a lot more vectors 722 * than CPU's. So let's be conservative and only ask for 723 * (roughly) the same number of vectors as there are CPU's. 724 * The default is to use pairs of vectors. 725 */ 726 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); 727 v_budget = min_t(int, v_budget, num_online_cpus()); 728 v_budget += NON_Q_VECTORS; 729 730 /* 731 * At the same time, hardware can only support a maximum of 732 * hw.mac->max_msix_vectors vectors. With features 733 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx 734 * descriptor queues supported by our device. Thus, we cap it off in 735 * those rare cases where the cpu count also exceeds our vector limit. 736 */ 737 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); 738 739 /* A failure in MSI-X entry allocation isn't fatal, but it does 740 * mean we disable MSI-X capabilities of the adapter. */ 741 adapter->msix_entries = kcalloc(v_budget, 742 sizeof(struct msix_entry), GFP_KERNEL); 743 if (adapter->msix_entries) { 744 for (vector = 0; vector < v_budget; vector++) 745 adapter->msix_entries[vector].entry = vector; 746 747 ixgbe_acquire_msix_vectors(adapter, v_budget); 748 749 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 750 goto out; 751 } 752 753 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 754 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; 755 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 756 e_err(probe, 757 "ATR is not supported while multiple " 758 "queues are disabled. Disabling Flow Director\n"); 759 } 760 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 761 adapter->atr_sample_rate = 0; 762 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 763 ixgbe_disable_sriov(adapter); 764 765 err = ixgbe_set_num_queues(adapter); 766 if (err) 767 return err; 768 769 adapter->num_q_vectors = 1; 770 771 err = pci_enable_msi(adapter->pdev); 772 if (!err) { 773 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; 774 } else { 775 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 776 "Unable to allocate MSI interrupt, " 777 "falling back to legacy. Error: %d\n", err); 778 /* reset err */ 779 err = 0; 780 } 781 782 out: 783 return err; 784 } 785 786 /** 787 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme 788 * @adapter: board private structure to initialize 789 * 790 * We determine which interrupt scheme to use based on... 791 * - Kernel support (MSI, MSI-X) 792 * - which can be user-defined (via MODULE_PARAM) 793 * - Hardware queue count (num_*_queues) 794 * - defined by miscellaneous hardware support/features (RSS, etc.) 795 **/ 796 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) 797 { 798 int err; 799 800 /* Number of supported queues */ 801 err = ixgbe_set_num_queues(adapter); 802 if (err) 803 return err; 804 805 err = ixgbe_set_interrupt_capability(adapter); 806 if (err) { 807 e_dev_err("Unable to setup interrupt capabilities\n"); 808 goto err_set_interrupt; 809 } 810 811 err = ixgbe_alloc_q_vectors(adapter); 812 if (err) { 813 e_dev_err("Unable to allocate memory for queue vectors\n"); 814 goto err_alloc_q_vectors; 815 } 816 817 ixgbe_cache_ring_register(adapter); 818 819 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", 820 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", 821 adapter->num_rx_queues, adapter->num_tx_queues); 822 823 set_bit(__IXGBE_DOWN, &adapter->state); 824 825 return 0; 826 827 err_alloc_q_vectors: 828 ixgbe_reset_interrupt_capability(adapter); 829 err_set_interrupt: 830 return err; 831 } 832 833 /** 834 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings 835 * @adapter: board private structure to clear interrupt scheme on 836 * 837 * We go through and clear interrupt specific resources and reset the structure 838 * to pre-load conditions 839 **/ 840 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) 841 { 842 adapter->num_tx_queues = 0; 843 adapter->num_rx_queues = 0; 844 845 ixgbe_free_q_vectors(adapter); 846 ixgbe_reset_interrupt_capability(adapter); 847 } 848 849 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, 850 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 851 { 852 struct ixgbe_adv_tx_context_desc *context_desc; 853 u16 i = tx_ring->next_to_use; 854 855 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i); 856 857 i++; 858 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 859 860 /* set bits to identify this as an advanced context descriptor */ 861 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; 862 863 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 864 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 865 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 866 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 867 } 868 869