1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include "ixgbe.h" 29 #include "ixgbe_sriov.h" 30 31 #ifdef CONFIG_IXGBE_DCB 32 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ 33 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, 34 unsigned int *tx, unsigned int *rx) 35 { 36 struct net_device *dev = adapter->netdev; 37 struct ixgbe_hw *hw = &adapter->hw; 38 u8 num_tcs = netdev_get_num_tc(dev); 39 40 *tx = 0; 41 *rx = 0; 42 43 switch (hw->mac.type) { 44 case ixgbe_mac_82598EB: 45 *tx = tc << 2; 46 *rx = tc << 3; 47 break; 48 case ixgbe_mac_82599EB: 49 case ixgbe_mac_X540: 50 if (num_tcs > 4) { 51 if (tc < 3) { 52 *tx = tc << 5; 53 *rx = tc << 4; 54 } else if (tc < 5) { 55 *tx = ((tc + 2) << 4); 56 *rx = tc << 4; 57 } else if (tc < num_tcs) { 58 *tx = ((tc + 8) << 3); 59 *rx = tc << 4; 60 } 61 } else { 62 *rx = tc << 5; 63 switch (tc) { 64 case 0: 65 *tx = 0; 66 break; 67 case 1: 68 *tx = 64; 69 break; 70 case 2: 71 *tx = 96; 72 break; 73 case 3: 74 *tx = 112; 75 break; 76 default: 77 break; 78 } 79 } 80 break; 81 default: 82 break; 83 } 84 } 85 86 /** 87 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB 88 * @adapter: board private structure to initialize 89 * 90 * Cache the descriptor ring offsets for DCB to the assigned rings. 91 * 92 **/ 93 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) 94 { 95 struct net_device *dev = adapter->netdev; 96 int i, j, k; 97 u8 num_tcs = netdev_get_num_tc(dev); 98 99 if (!num_tcs) 100 return false; 101 102 for (i = 0, k = 0; i < num_tcs; i++) { 103 unsigned int tx_s, rx_s; 104 u16 count = dev->tc_to_txq[i].count; 105 106 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); 107 for (j = 0; j < count; j++, k++) { 108 adapter->tx_ring[k]->reg_idx = tx_s + j; 109 adapter->rx_ring[k]->reg_idx = rx_s + j; 110 adapter->tx_ring[k]->dcb_tc = i; 111 adapter->rx_ring[k]->dcb_tc = i; 112 } 113 } 114 115 return true; 116 } 117 118 #endif 119 /** 120 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov 121 * @adapter: board private structure to initialize 122 * 123 * SR-IOV doesn't use any descriptor rings but changes the default if 124 * no other mapping is used. 125 * 126 */ 127 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) 128 { 129 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; 130 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; 131 if (adapter->num_vfs) 132 return true; 133 else 134 return false; 135 } 136 137 /** 138 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS 139 * @adapter: board private structure to initialize 140 * 141 * Cache the descriptor ring offsets for RSS to the assigned rings. 142 * 143 **/ 144 static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) 145 { 146 int i; 147 148 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) 149 return false; 150 151 for (i = 0; i < adapter->num_rx_queues; i++) 152 adapter->rx_ring[i]->reg_idx = i; 153 for (i = 0; i < adapter->num_tx_queues; i++) 154 adapter->tx_ring[i]->reg_idx = i; 155 156 return true; 157 } 158 159 /** 160 * ixgbe_cache_ring_register - Descriptor ring to register mapping 161 * @adapter: board private structure to initialize 162 * 163 * Once we know the feature-set enabled for the device, we'll cache 164 * the register offset the descriptor ring is assigned to. 165 * 166 * Note, the order the various feature calls is important. It must start with 167 * the "most" features enabled at the same time, then trickle down to the 168 * least amount of features turned on at once. 169 **/ 170 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) 171 { 172 /* start with default case */ 173 adapter->rx_ring[0]->reg_idx = 0; 174 adapter->tx_ring[0]->reg_idx = 0; 175 176 if (ixgbe_cache_ring_sriov(adapter)) 177 return; 178 179 #ifdef CONFIG_IXGBE_DCB 180 if (ixgbe_cache_ring_dcb(adapter)) 181 return; 182 #endif 183 184 ixgbe_cache_ring_rss(adapter); 185 } 186 187 /** 188 * ixgbe_set_sriov_queues - Allocate queues for IOV use 189 * @adapter: board private structure to initialize 190 * 191 * IOV doesn't actually use anything, so just NAK the 192 * request for now and let the other queue routines 193 * figure out what to do. 194 */ 195 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) 196 { 197 return false; 198 } 199 200 #define IXGBE_RSS_16Q_MASK 0xF 201 #define IXGBE_RSS_8Q_MASK 0x7 202 #define IXGBE_RSS_4Q_MASK 0x3 203 #define IXGBE_RSS_2Q_MASK 0x1 204 #define IXGBE_RSS_DISABLED_MASK 0x0 205 206 #ifdef CONFIG_IXGBE_DCB 207 static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) 208 { 209 struct net_device *dev = adapter->netdev; 210 struct ixgbe_ring_feature *f; 211 int rss_i, rss_m, i; 212 int tcs; 213 214 /* Map queue offset and counts onto allocated tx queues */ 215 tcs = netdev_get_num_tc(dev); 216 217 /* verify we have DCB queueing enabled before proceeding */ 218 if (tcs <= 1) 219 return false; 220 221 /* determine the upper limit for our current DCB mode */ 222 rss_i = dev->num_tx_queues / tcs; 223 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 224 /* 8 TC w/ 4 queues per TC */ 225 rss_i = min_t(u16, rss_i, 4); 226 rss_m = IXGBE_RSS_4Q_MASK; 227 } else if (tcs > 4) { 228 /* 8 TC w/ 8 queues per TC */ 229 rss_i = min_t(u16, rss_i, 8); 230 rss_m = IXGBE_RSS_8Q_MASK; 231 } else { 232 /* 4 TC w/ 16 queues per TC */ 233 rss_i = min_t(u16, rss_i, 16); 234 rss_m = IXGBE_RSS_16Q_MASK; 235 } 236 237 /* set RSS mask and indices */ 238 f = &adapter->ring_feature[RING_F_RSS]; 239 rss_i = min_t(int, rss_i, f->limit); 240 f->indices = rss_i; 241 f->mask = rss_m; 242 243 #ifdef IXGBE_FCOE 244 /* FCoE enabled queues require special configuration indexed 245 * by feature specific indices and offset. Here we map FCoE 246 * indices onto the DCB queue pairs allowing FCoE to own 247 * configuration later. 248 */ 249 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 250 u8 tc = ixgbe_fcoe_get_tc(adapter); 251 252 f = &adapter->ring_feature[RING_F_FCOE]; 253 f->indices = min_t(u16, rss_i, f->limit); 254 f->offset = rss_i * tc; 255 } 256 257 #endif /* IXGBE_FCOE */ 258 for (i = 0; i < tcs; i++) 259 netdev_set_tc_queue(dev, i, rss_i, rss_i * i); 260 261 adapter->num_tx_queues = rss_i * tcs; 262 adapter->num_rx_queues = rss_i * tcs; 263 264 return true; 265 } 266 267 #endif 268 /** 269 * ixgbe_set_rss_queues - Allocate queues for RSS 270 * @adapter: board private structure to initialize 271 * 272 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 273 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 274 * 275 **/ 276 static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) 277 { 278 struct ixgbe_ring_feature *f; 279 u16 rss_i; 280 281 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { 282 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 283 return false; 284 } 285 286 /* set mask for 16 queue limit of RSS */ 287 f = &adapter->ring_feature[RING_F_RSS]; 288 rss_i = f->limit; 289 290 f->indices = rss_i; 291 f->mask = IXGBE_RSS_16Q_MASK; 292 293 /* 294 * Use Flow Director in addition to RSS to ensure the best 295 * distribution of flows across cores, even when an FDIR flow 296 * isn't matched. 297 */ 298 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 299 f = &adapter->ring_feature[RING_F_FDIR]; 300 301 f->indices = min_t(u16, num_online_cpus(), f->limit); 302 rss_i = max_t(u16, rss_i, f->indices); 303 } 304 305 #ifdef IXGBE_FCOE 306 /* 307 * FCoE can exist on the same rings as standard network traffic 308 * however it is preferred to avoid that if possible. In order 309 * to get the best performance we allocate as many FCoE queues 310 * as we can and we place them at the end of the ring array to 311 * avoid sharing queues with standard RSS on systems with 24 or 312 * more CPUs. 313 */ 314 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 315 struct net_device *dev = adapter->netdev; 316 u16 fcoe_i; 317 318 f = &adapter->ring_feature[RING_F_FCOE]; 319 320 /* merge FCoE queues with RSS queues */ 321 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); 322 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); 323 324 /* limit indices to rss_i if MSI-X is disabled */ 325 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 326 fcoe_i = rss_i; 327 328 /* attempt to reserve some queues for just FCoE */ 329 f->indices = min_t(u16, fcoe_i, f->limit); 330 f->offset = fcoe_i - f->indices; 331 rss_i = max_t(u16, fcoe_i, rss_i); 332 } 333 334 #endif /* IXGBE_FCOE */ 335 adapter->num_rx_queues = rss_i; 336 adapter->num_tx_queues = rss_i; 337 338 return true; 339 } 340 341 /** 342 * ixgbe_set_num_queues - Allocate queues for device, feature dependent 343 * @adapter: board private structure to initialize 344 * 345 * This is the top level queue allocation routine. The order here is very 346 * important, starting with the "most" number of features turned on at once, 347 * and ending with the smallest set of features. This way large combinations 348 * can be allocated if they're turned on, and smaller combinations are the 349 * fallthrough conditions. 350 * 351 **/ 352 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) 353 { 354 /* Start with base case */ 355 adapter->num_rx_queues = 1; 356 adapter->num_tx_queues = 1; 357 adapter->num_rx_pools = adapter->num_rx_queues; 358 adapter->num_rx_queues_per_pool = 1; 359 360 if (ixgbe_set_sriov_queues(adapter)) 361 return; 362 363 #ifdef CONFIG_IXGBE_DCB 364 if (ixgbe_set_dcb_queues(adapter)) 365 return; 366 367 #endif 368 ixgbe_set_rss_queues(adapter); 369 } 370 371 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, 372 int vectors) 373 { 374 int err, vector_threshold; 375 376 /* We'll want at least 2 (vector_threshold): 377 * 1) TxQ[0] + RxQ[0] handler 378 * 2) Other (Link Status Change, etc.) 379 */ 380 vector_threshold = MIN_MSIX_COUNT; 381 382 /* 383 * The more we get, the more we will assign to Tx/Rx Cleanup 384 * for the separate queues...where Rx Cleanup >= Tx Cleanup. 385 * Right now, we simply care about how many we'll get; we'll 386 * set them up later while requesting irq's. 387 */ 388 while (vectors >= vector_threshold) { 389 err = pci_enable_msix(adapter->pdev, adapter->msix_entries, 390 vectors); 391 if (!err) /* Success in acquiring all requested vectors. */ 392 break; 393 else if (err < 0) 394 vectors = 0; /* Nasty failure, quit now */ 395 else /* err == number of vectors we should try again with */ 396 vectors = err; 397 } 398 399 if (vectors < vector_threshold) { 400 /* Can't allocate enough MSI-X interrupts? Oh well. 401 * This just means we'll go with either a single MSI 402 * vector or fall back to legacy interrupts. 403 */ 404 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 405 "Unable to allocate MSI-X interrupts\n"); 406 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 407 kfree(adapter->msix_entries); 408 adapter->msix_entries = NULL; 409 } else { 410 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ 411 /* 412 * Adjust for only the vectors we'll use, which is minimum 413 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of 414 * vectors we were allocated. 415 */ 416 vectors -= NON_Q_VECTORS; 417 adapter->num_q_vectors = min(vectors, adapter->max_q_vectors); 418 } 419 } 420 421 static void ixgbe_add_ring(struct ixgbe_ring *ring, 422 struct ixgbe_ring_container *head) 423 { 424 ring->next = head->ring; 425 head->ring = ring; 426 head->count++; 427 } 428 429 /** 430 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector 431 * @adapter: board private structure to initialize 432 * @v_count: q_vectors allocated on adapter, used for ring interleaving 433 * @v_idx: index of vector in adapter struct 434 * @txr_count: total number of Tx rings to allocate 435 * @txr_idx: index of first Tx ring to allocate 436 * @rxr_count: total number of Rx rings to allocate 437 * @rxr_idx: index of first Rx ring to allocate 438 * 439 * We allocate one q_vector. If allocation fails we return -ENOMEM. 440 **/ 441 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, 442 int v_count, int v_idx, 443 int txr_count, int txr_idx, 444 int rxr_count, int rxr_idx) 445 { 446 struct ixgbe_q_vector *q_vector; 447 struct ixgbe_ring *ring; 448 int node = -1; 449 int cpu = -1; 450 int ring_count, size; 451 452 ring_count = txr_count + rxr_count; 453 size = sizeof(struct ixgbe_q_vector) + 454 (sizeof(struct ixgbe_ring) * ring_count); 455 456 /* customize cpu for Flow Director mapping */ 457 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 458 if (cpu_online(v_idx)) { 459 cpu = v_idx; 460 node = cpu_to_node(cpu); 461 } 462 } 463 464 /* allocate q_vector and rings */ 465 q_vector = kzalloc_node(size, GFP_KERNEL, node); 466 if (!q_vector) 467 q_vector = kzalloc(size, GFP_KERNEL); 468 if (!q_vector) 469 return -ENOMEM; 470 471 /* setup affinity mask and node */ 472 if (cpu != -1) 473 cpumask_set_cpu(cpu, &q_vector->affinity_mask); 474 else 475 cpumask_copy(&q_vector->affinity_mask, cpu_online_mask); 476 q_vector->numa_node = node; 477 478 /* initialize NAPI */ 479 netif_napi_add(adapter->netdev, &q_vector->napi, 480 ixgbe_poll, 64); 481 482 /* tie q_vector and adapter together */ 483 adapter->q_vector[v_idx] = q_vector; 484 q_vector->adapter = adapter; 485 q_vector->v_idx = v_idx; 486 487 /* initialize work limits */ 488 q_vector->tx.work_limit = adapter->tx_work_limit; 489 490 /* initialize pointer to rings */ 491 ring = q_vector->ring; 492 493 while (txr_count) { 494 /* assign generic ring traits */ 495 ring->dev = &adapter->pdev->dev; 496 ring->netdev = adapter->netdev; 497 498 /* configure backlink on ring */ 499 ring->q_vector = q_vector; 500 501 /* update q_vector Tx values */ 502 ixgbe_add_ring(ring, &q_vector->tx); 503 504 /* apply Tx specific ring traits */ 505 ring->count = adapter->tx_ring_count; 506 ring->queue_index = txr_idx; 507 508 /* assign ring to adapter */ 509 adapter->tx_ring[txr_idx] = ring; 510 511 /* update count and index */ 512 txr_count--; 513 txr_idx += v_count; 514 515 /* push pointer to next ring */ 516 ring++; 517 } 518 519 while (rxr_count) { 520 /* assign generic ring traits */ 521 ring->dev = &adapter->pdev->dev; 522 ring->netdev = adapter->netdev; 523 524 /* configure backlink on ring */ 525 ring->q_vector = q_vector; 526 527 /* update q_vector Rx values */ 528 ixgbe_add_ring(ring, &q_vector->rx); 529 530 /* 531 * 82599 errata, UDP frames with a 0 checksum 532 * can be marked as checksum errors. 533 */ 534 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 535 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); 536 537 #ifdef IXGBE_FCOE 538 if (adapter->netdev->features & NETIF_F_FCOE_MTU) { 539 struct ixgbe_ring_feature *f; 540 f = &adapter->ring_feature[RING_F_FCOE]; 541 if ((rxr_idx >= f->offset) && 542 (rxr_idx < f->offset + f->indices)) 543 set_bit(__IXGBE_RX_FCOE, &ring->state); 544 } 545 546 #endif /* IXGBE_FCOE */ 547 /* apply Rx specific ring traits */ 548 ring->count = adapter->rx_ring_count; 549 ring->queue_index = rxr_idx; 550 551 /* assign ring to adapter */ 552 adapter->rx_ring[rxr_idx] = ring; 553 554 /* update count and index */ 555 rxr_count--; 556 rxr_idx += v_count; 557 558 /* push pointer to next ring */ 559 ring++; 560 } 561 562 return 0; 563 } 564 565 /** 566 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector 567 * @adapter: board private structure to initialize 568 * @v_idx: Index of vector to be freed 569 * 570 * This function frees the memory allocated to the q_vector. In addition if 571 * NAPI is enabled it will delete any references to the NAPI struct prior 572 * to freeing the q_vector. 573 **/ 574 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx) 575 { 576 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; 577 struct ixgbe_ring *ring; 578 579 ixgbe_for_each_ring(ring, q_vector->tx) 580 adapter->tx_ring[ring->queue_index] = NULL; 581 582 ixgbe_for_each_ring(ring, q_vector->rx) 583 adapter->rx_ring[ring->queue_index] = NULL; 584 585 adapter->q_vector[v_idx] = NULL; 586 netif_napi_del(&q_vector->napi); 587 588 /* 589 * ixgbe_get_stats64() might access the rings on this vector, 590 * we must wait a grace period before freeing it. 591 */ 592 kfree_rcu(q_vector, rcu); 593 } 594 595 /** 596 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors 597 * @adapter: board private structure to initialize 598 * 599 * We allocate one q_vector per queue interrupt. If allocation fails we 600 * return -ENOMEM. 601 **/ 602 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) 603 { 604 int q_vectors = adapter->num_q_vectors; 605 int rxr_remaining = adapter->num_rx_queues; 606 int txr_remaining = adapter->num_tx_queues; 607 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 608 int err; 609 610 /* only one q_vector if MSI-X is disabled. */ 611 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 612 q_vectors = 1; 613 614 if (q_vectors >= (rxr_remaining + txr_remaining)) { 615 for (; rxr_remaining; v_idx++) { 616 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 617 0, 0, 1, rxr_idx); 618 619 if (err) 620 goto err_out; 621 622 /* update counts and index */ 623 rxr_remaining--; 624 rxr_idx++; 625 } 626 } 627 628 for (; v_idx < q_vectors; v_idx++) { 629 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 630 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 631 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 632 tqpv, txr_idx, 633 rqpv, rxr_idx); 634 635 if (err) 636 goto err_out; 637 638 /* update counts and index */ 639 rxr_remaining -= rqpv; 640 txr_remaining -= tqpv; 641 rxr_idx++; 642 txr_idx++; 643 } 644 645 return 0; 646 647 err_out: 648 adapter->num_tx_queues = 0; 649 adapter->num_rx_queues = 0; 650 adapter->num_q_vectors = 0; 651 652 while (v_idx--) 653 ixgbe_free_q_vector(adapter, v_idx); 654 655 return -ENOMEM; 656 } 657 658 /** 659 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors 660 * @adapter: board private structure to initialize 661 * 662 * This function frees the memory allocated to the q_vectors. In addition if 663 * NAPI is enabled it will delete any references to the NAPI struct prior 664 * to freeing the q_vector. 665 **/ 666 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) 667 { 668 int v_idx = adapter->num_q_vectors; 669 670 adapter->num_tx_queues = 0; 671 adapter->num_rx_queues = 0; 672 adapter->num_q_vectors = 0; 673 674 while (v_idx--) 675 ixgbe_free_q_vector(adapter, v_idx); 676 } 677 678 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) 679 { 680 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 681 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 682 pci_disable_msix(adapter->pdev); 683 kfree(adapter->msix_entries); 684 adapter->msix_entries = NULL; 685 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 686 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; 687 pci_disable_msi(adapter->pdev); 688 } 689 } 690 691 /** 692 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported 693 * @adapter: board private structure to initialize 694 * 695 * Attempt to configure the interrupts using the best available 696 * capabilities of the hardware and the kernel. 697 **/ 698 static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) 699 { 700 struct ixgbe_hw *hw = &adapter->hw; 701 int vector, v_budget, err; 702 703 /* 704 * It's easy to be greedy for MSI-X vectors, but it really 705 * doesn't do us much good if we have a lot more vectors 706 * than CPU's. So let's be conservative and only ask for 707 * (roughly) the same number of vectors as there are CPU's. 708 * The default is to use pairs of vectors. 709 */ 710 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); 711 v_budget = min_t(int, v_budget, num_online_cpus()); 712 v_budget += NON_Q_VECTORS; 713 714 /* 715 * At the same time, hardware can only support a maximum of 716 * hw.mac->max_msix_vectors vectors. With features 717 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx 718 * descriptor queues supported by our device. Thus, we cap it off in 719 * those rare cases where the cpu count also exceeds our vector limit. 720 */ 721 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); 722 723 /* A failure in MSI-X entry allocation isn't fatal, but it does 724 * mean we disable MSI-X capabilities of the adapter. */ 725 adapter->msix_entries = kcalloc(v_budget, 726 sizeof(struct msix_entry), GFP_KERNEL); 727 if (adapter->msix_entries) { 728 for (vector = 0; vector < v_budget; vector++) 729 adapter->msix_entries[vector].entry = vector; 730 731 ixgbe_acquire_msix_vectors(adapter, v_budget); 732 733 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 734 return; 735 } 736 737 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 738 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; 739 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 740 e_err(probe, 741 "ATR is not supported while multiple " 742 "queues are disabled. Disabling Flow Director\n"); 743 } 744 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 745 adapter->atr_sample_rate = 0; 746 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 747 ixgbe_disable_sriov(adapter); 748 749 ixgbe_set_num_queues(adapter); 750 adapter->num_q_vectors = 1; 751 752 err = pci_enable_msi(adapter->pdev); 753 if (err) { 754 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 755 "Unable to allocate MSI interrupt, " 756 "falling back to legacy. Error: %d\n", err); 757 return; 758 } 759 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; 760 } 761 762 /** 763 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme 764 * @adapter: board private structure to initialize 765 * 766 * We determine which interrupt scheme to use based on... 767 * - Kernel support (MSI, MSI-X) 768 * - which can be user-defined (via MODULE_PARAM) 769 * - Hardware queue count (num_*_queues) 770 * - defined by miscellaneous hardware support/features (RSS, etc.) 771 **/ 772 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) 773 { 774 int err; 775 776 /* Number of supported queues */ 777 ixgbe_set_num_queues(adapter); 778 779 /* Set interrupt mode */ 780 ixgbe_set_interrupt_capability(adapter); 781 782 err = ixgbe_alloc_q_vectors(adapter); 783 if (err) { 784 e_dev_err("Unable to allocate memory for queue vectors\n"); 785 goto err_alloc_q_vectors; 786 } 787 788 ixgbe_cache_ring_register(adapter); 789 790 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", 791 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", 792 adapter->num_rx_queues, adapter->num_tx_queues); 793 794 set_bit(__IXGBE_DOWN, &adapter->state); 795 796 return 0; 797 798 err_alloc_q_vectors: 799 ixgbe_reset_interrupt_capability(adapter); 800 return err; 801 } 802 803 /** 804 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings 805 * @adapter: board private structure to clear interrupt scheme on 806 * 807 * We go through and clear interrupt specific resources and reset the structure 808 * to pre-load conditions 809 **/ 810 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) 811 { 812 adapter->num_tx_queues = 0; 813 adapter->num_rx_queues = 0; 814 815 ixgbe_free_q_vectors(adapter); 816 ixgbe_reset_interrupt_capability(adapter); 817 } 818 819 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, 820 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 821 { 822 struct ixgbe_adv_tx_context_desc *context_desc; 823 u16 i = tx_ring->next_to_use; 824 825 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i); 826 827 i++; 828 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 829 830 /* set bits to identify this as an advanced context descriptor */ 831 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; 832 833 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 834 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 835 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 836 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 837 } 838 839