1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include "ixgbe.h" 29 #include "ixgbe_sriov.h" 30 31 #ifdef CONFIG_IXGBE_DCB 32 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ 33 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, 34 unsigned int *tx, unsigned int *rx) 35 { 36 struct net_device *dev = adapter->netdev; 37 struct ixgbe_hw *hw = &adapter->hw; 38 u8 num_tcs = netdev_get_num_tc(dev); 39 40 *tx = 0; 41 *rx = 0; 42 43 switch (hw->mac.type) { 44 case ixgbe_mac_82598EB: 45 /* TxQs/TC: 4 RxQs/TC: 8 */ 46 *tx = tc << 2; /* 0, 4, 8, 12, 16, 20, 24, 28 */ 47 *rx = tc << 3; /* 0, 8, 16, 24, 32, 40, 48, 56 */ 48 break; 49 case ixgbe_mac_82599EB: 50 case ixgbe_mac_X540: 51 if (num_tcs > 4) { 52 /* 53 * TCs : TC0/1 TC2/3 TC4-7 54 * TxQs/TC: 32 16 8 55 * RxQs/TC: 16 16 16 56 */ 57 *rx = tc << 4; 58 if (tc < 3) 59 *tx = tc << 5; /* 0, 32, 64 */ 60 else if (tc < 5) 61 *tx = (tc + 2) << 4; /* 80, 96 */ 62 else 63 *tx = (tc + 8) << 3; /* 104, 112, 120 */ 64 } else { 65 /* 66 * TCs : TC0 TC1 TC2/3 67 * TxQs/TC: 64 32 16 68 * RxQs/TC: 32 32 32 69 */ 70 *rx = tc << 5; 71 if (tc < 2) 72 *tx = tc << 6; /* 0, 64 */ 73 else 74 *tx = (tc + 4) << 4; /* 96, 112 */ 75 } 76 default: 77 break; 78 } 79 } 80 81 /** 82 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB 83 * @adapter: board private structure to initialize 84 * 85 * Cache the descriptor ring offsets for DCB to the assigned rings. 86 * 87 **/ 88 static bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) 89 { 90 struct net_device *dev = adapter->netdev; 91 unsigned int tx_idx, rx_idx; 92 int tc, offset, rss_i, i; 93 u8 num_tcs = netdev_get_num_tc(dev); 94 95 /* verify we have DCB queueing enabled before proceeding */ 96 if (num_tcs <= 1) 97 return false; 98 99 rss_i = adapter->ring_feature[RING_F_RSS].indices; 100 101 for (tc = 0, offset = 0; tc < num_tcs; tc++, offset += rss_i) { 102 ixgbe_get_first_reg_idx(adapter, tc, &tx_idx, &rx_idx); 103 for (i = 0; i < rss_i; i++, tx_idx++, rx_idx++) { 104 adapter->tx_ring[offset + i]->reg_idx = tx_idx; 105 adapter->rx_ring[offset + i]->reg_idx = rx_idx; 106 adapter->tx_ring[offset + i]->dcb_tc = tc; 107 adapter->rx_ring[offset + i]->dcb_tc = tc; 108 } 109 } 110 111 return true; 112 } 113 114 #endif 115 /** 116 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov 117 * @adapter: board private structure to initialize 118 * 119 * SR-IOV doesn't use any descriptor rings but changes the default if 120 * no other mapping is used. 121 * 122 */ 123 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) 124 { 125 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; 126 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; 127 if (adapter->num_vfs) 128 return true; 129 else 130 return false; 131 } 132 133 /** 134 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS 135 * @adapter: board private structure to initialize 136 * 137 * Cache the descriptor ring offsets for RSS to the assigned rings. 138 * 139 **/ 140 static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) 141 { 142 int i; 143 144 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) 145 return false; 146 147 for (i = 0; i < adapter->num_rx_queues; i++) 148 adapter->rx_ring[i]->reg_idx = i; 149 for (i = 0; i < adapter->num_tx_queues; i++) 150 adapter->tx_ring[i]->reg_idx = i; 151 152 return true; 153 } 154 155 /** 156 * ixgbe_cache_ring_register - Descriptor ring to register mapping 157 * @adapter: board private structure to initialize 158 * 159 * Once we know the feature-set enabled for the device, we'll cache 160 * the register offset the descriptor ring is assigned to. 161 * 162 * Note, the order the various feature calls is important. It must start with 163 * the "most" features enabled at the same time, then trickle down to the 164 * least amount of features turned on at once. 165 **/ 166 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) 167 { 168 /* start with default case */ 169 adapter->rx_ring[0]->reg_idx = 0; 170 adapter->tx_ring[0]->reg_idx = 0; 171 172 if (ixgbe_cache_ring_sriov(adapter)) 173 return; 174 175 #ifdef CONFIG_IXGBE_DCB 176 if (ixgbe_cache_ring_dcb(adapter)) 177 return; 178 #endif 179 180 ixgbe_cache_ring_rss(adapter); 181 } 182 183 /** 184 * ixgbe_set_sriov_queues - Allocate queues for IOV use 185 * @adapter: board private structure to initialize 186 * 187 * IOV doesn't actually use anything, so just NAK the 188 * request for now and let the other queue routines 189 * figure out what to do. 190 */ 191 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) 192 { 193 return false; 194 } 195 196 #define IXGBE_RSS_16Q_MASK 0xF 197 #define IXGBE_RSS_8Q_MASK 0x7 198 #define IXGBE_RSS_4Q_MASK 0x3 199 #define IXGBE_RSS_2Q_MASK 0x1 200 #define IXGBE_RSS_DISABLED_MASK 0x0 201 202 #ifdef CONFIG_IXGBE_DCB 203 static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) 204 { 205 struct net_device *dev = adapter->netdev; 206 struct ixgbe_ring_feature *f; 207 int rss_i, rss_m, i; 208 int tcs; 209 210 /* Map queue offset and counts onto allocated tx queues */ 211 tcs = netdev_get_num_tc(dev); 212 213 /* verify we have DCB queueing enabled before proceeding */ 214 if (tcs <= 1) 215 return false; 216 217 /* determine the upper limit for our current DCB mode */ 218 rss_i = dev->num_tx_queues / tcs; 219 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 220 /* 8 TC w/ 4 queues per TC */ 221 rss_i = min_t(u16, rss_i, 4); 222 rss_m = IXGBE_RSS_4Q_MASK; 223 } else if (tcs > 4) { 224 /* 8 TC w/ 8 queues per TC */ 225 rss_i = min_t(u16, rss_i, 8); 226 rss_m = IXGBE_RSS_8Q_MASK; 227 } else { 228 /* 4 TC w/ 16 queues per TC */ 229 rss_i = min_t(u16, rss_i, 16); 230 rss_m = IXGBE_RSS_16Q_MASK; 231 } 232 233 /* set RSS mask and indices */ 234 f = &adapter->ring_feature[RING_F_RSS]; 235 rss_i = min_t(int, rss_i, f->limit); 236 f->indices = rss_i; 237 f->mask = rss_m; 238 239 #ifdef IXGBE_FCOE 240 /* FCoE enabled queues require special configuration indexed 241 * by feature specific indices and offset. Here we map FCoE 242 * indices onto the DCB queue pairs allowing FCoE to own 243 * configuration later. 244 */ 245 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 246 u8 tc = ixgbe_fcoe_get_tc(adapter); 247 248 f = &adapter->ring_feature[RING_F_FCOE]; 249 f->indices = min_t(u16, rss_i, f->limit); 250 f->offset = rss_i * tc; 251 } 252 253 #endif /* IXGBE_FCOE */ 254 for (i = 0; i < tcs; i++) 255 netdev_set_tc_queue(dev, i, rss_i, rss_i * i); 256 257 adapter->num_tx_queues = rss_i * tcs; 258 adapter->num_rx_queues = rss_i * tcs; 259 260 return true; 261 } 262 263 #endif 264 /** 265 * ixgbe_set_rss_queues - Allocate queues for RSS 266 * @adapter: board private structure to initialize 267 * 268 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 269 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 270 * 271 **/ 272 static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) 273 { 274 struct ixgbe_ring_feature *f; 275 u16 rss_i; 276 277 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { 278 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 279 return false; 280 } 281 282 /* set mask for 16 queue limit of RSS */ 283 f = &adapter->ring_feature[RING_F_RSS]; 284 rss_i = f->limit; 285 286 f->indices = rss_i; 287 f->mask = IXGBE_RSS_16Q_MASK; 288 289 /* 290 * Use Flow Director in addition to RSS to ensure the best 291 * distribution of flows across cores, even when an FDIR flow 292 * isn't matched. 293 */ 294 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 295 f = &adapter->ring_feature[RING_F_FDIR]; 296 297 f->indices = min_t(u16, num_online_cpus(), f->limit); 298 rss_i = max_t(u16, rss_i, f->indices); 299 } 300 301 #ifdef IXGBE_FCOE 302 /* 303 * FCoE can exist on the same rings as standard network traffic 304 * however it is preferred to avoid that if possible. In order 305 * to get the best performance we allocate as many FCoE queues 306 * as we can and we place them at the end of the ring array to 307 * avoid sharing queues with standard RSS on systems with 24 or 308 * more CPUs. 309 */ 310 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 311 struct net_device *dev = adapter->netdev; 312 u16 fcoe_i; 313 314 f = &adapter->ring_feature[RING_F_FCOE]; 315 316 /* merge FCoE queues with RSS queues */ 317 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); 318 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); 319 320 /* limit indices to rss_i if MSI-X is disabled */ 321 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 322 fcoe_i = rss_i; 323 324 /* attempt to reserve some queues for just FCoE */ 325 f->indices = min_t(u16, fcoe_i, f->limit); 326 f->offset = fcoe_i - f->indices; 327 rss_i = max_t(u16, fcoe_i, rss_i); 328 } 329 330 #endif /* IXGBE_FCOE */ 331 adapter->num_rx_queues = rss_i; 332 adapter->num_tx_queues = rss_i; 333 334 return true; 335 } 336 337 /** 338 * ixgbe_set_num_queues - Allocate queues for device, feature dependent 339 * @adapter: board private structure to initialize 340 * 341 * This is the top level queue allocation routine. The order here is very 342 * important, starting with the "most" number of features turned on at once, 343 * and ending with the smallest set of features. This way large combinations 344 * can be allocated if they're turned on, and smaller combinations are the 345 * fallthrough conditions. 346 * 347 **/ 348 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) 349 { 350 /* Start with base case */ 351 adapter->num_rx_queues = 1; 352 adapter->num_tx_queues = 1; 353 adapter->num_rx_pools = adapter->num_rx_queues; 354 adapter->num_rx_queues_per_pool = 1; 355 356 if (ixgbe_set_sriov_queues(adapter)) 357 return; 358 359 #ifdef CONFIG_IXGBE_DCB 360 if (ixgbe_set_dcb_queues(adapter)) 361 return; 362 363 #endif 364 ixgbe_set_rss_queues(adapter); 365 } 366 367 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, 368 int vectors) 369 { 370 int err, vector_threshold; 371 372 /* We'll want at least 2 (vector_threshold): 373 * 1) TxQ[0] + RxQ[0] handler 374 * 2) Other (Link Status Change, etc.) 375 */ 376 vector_threshold = MIN_MSIX_COUNT; 377 378 /* 379 * The more we get, the more we will assign to Tx/Rx Cleanup 380 * for the separate queues...where Rx Cleanup >= Tx Cleanup. 381 * Right now, we simply care about how many we'll get; we'll 382 * set them up later while requesting irq's. 383 */ 384 while (vectors >= vector_threshold) { 385 err = pci_enable_msix(adapter->pdev, adapter->msix_entries, 386 vectors); 387 if (!err) /* Success in acquiring all requested vectors. */ 388 break; 389 else if (err < 0) 390 vectors = 0; /* Nasty failure, quit now */ 391 else /* err == number of vectors we should try again with */ 392 vectors = err; 393 } 394 395 if (vectors < vector_threshold) { 396 /* Can't allocate enough MSI-X interrupts? Oh well. 397 * This just means we'll go with either a single MSI 398 * vector or fall back to legacy interrupts. 399 */ 400 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 401 "Unable to allocate MSI-X interrupts\n"); 402 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 403 kfree(adapter->msix_entries); 404 adapter->msix_entries = NULL; 405 } else { 406 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ 407 /* 408 * Adjust for only the vectors we'll use, which is minimum 409 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of 410 * vectors we were allocated. 411 */ 412 vectors -= NON_Q_VECTORS; 413 adapter->num_q_vectors = min(vectors, adapter->max_q_vectors); 414 } 415 } 416 417 static void ixgbe_add_ring(struct ixgbe_ring *ring, 418 struct ixgbe_ring_container *head) 419 { 420 ring->next = head->ring; 421 head->ring = ring; 422 head->count++; 423 } 424 425 /** 426 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector 427 * @adapter: board private structure to initialize 428 * @v_count: q_vectors allocated on adapter, used for ring interleaving 429 * @v_idx: index of vector in adapter struct 430 * @txr_count: total number of Tx rings to allocate 431 * @txr_idx: index of first Tx ring to allocate 432 * @rxr_count: total number of Rx rings to allocate 433 * @rxr_idx: index of first Rx ring to allocate 434 * 435 * We allocate one q_vector. If allocation fails we return -ENOMEM. 436 **/ 437 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, 438 int v_count, int v_idx, 439 int txr_count, int txr_idx, 440 int rxr_count, int rxr_idx) 441 { 442 struct ixgbe_q_vector *q_vector; 443 struct ixgbe_ring *ring; 444 int node = -1; 445 int cpu = -1; 446 int ring_count, size; 447 448 ring_count = txr_count + rxr_count; 449 size = sizeof(struct ixgbe_q_vector) + 450 (sizeof(struct ixgbe_ring) * ring_count); 451 452 /* customize cpu for Flow Director mapping */ 453 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 454 if (cpu_online(v_idx)) { 455 cpu = v_idx; 456 node = cpu_to_node(cpu); 457 } 458 } 459 460 /* allocate q_vector and rings */ 461 q_vector = kzalloc_node(size, GFP_KERNEL, node); 462 if (!q_vector) 463 q_vector = kzalloc(size, GFP_KERNEL); 464 if (!q_vector) 465 return -ENOMEM; 466 467 /* setup affinity mask and node */ 468 if (cpu != -1) 469 cpumask_set_cpu(cpu, &q_vector->affinity_mask); 470 else 471 cpumask_copy(&q_vector->affinity_mask, cpu_online_mask); 472 q_vector->numa_node = node; 473 474 /* initialize NAPI */ 475 netif_napi_add(adapter->netdev, &q_vector->napi, 476 ixgbe_poll, 64); 477 478 /* tie q_vector and adapter together */ 479 adapter->q_vector[v_idx] = q_vector; 480 q_vector->adapter = adapter; 481 q_vector->v_idx = v_idx; 482 483 /* initialize work limits */ 484 q_vector->tx.work_limit = adapter->tx_work_limit; 485 486 /* initialize pointer to rings */ 487 ring = q_vector->ring; 488 489 while (txr_count) { 490 /* assign generic ring traits */ 491 ring->dev = &adapter->pdev->dev; 492 ring->netdev = adapter->netdev; 493 494 /* configure backlink on ring */ 495 ring->q_vector = q_vector; 496 497 /* update q_vector Tx values */ 498 ixgbe_add_ring(ring, &q_vector->tx); 499 500 /* apply Tx specific ring traits */ 501 ring->count = adapter->tx_ring_count; 502 ring->queue_index = txr_idx; 503 504 /* assign ring to adapter */ 505 adapter->tx_ring[txr_idx] = ring; 506 507 /* update count and index */ 508 txr_count--; 509 txr_idx += v_count; 510 511 /* push pointer to next ring */ 512 ring++; 513 } 514 515 while (rxr_count) { 516 /* assign generic ring traits */ 517 ring->dev = &adapter->pdev->dev; 518 ring->netdev = adapter->netdev; 519 520 /* configure backlink on ring */ 521 ring->q_vector = q_vector; 522 523 /* update q_vector Rx values */ 524 ixgbe_add_ring(ring, &q_vector->rx); 525 526 /* 527 * 82599 errata, UDP frames with a 0 checksum 528 * can be marked as checksum errors. 529 */ 530 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 531 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); 532 533 #ifdef IXGBE_FCOE 534 if (adapter->netdev->features & NETIF_F_FCOE_MTU) { 535 struct ixgbe_ring_feature *f; 536 f = &adapter->ring_feature[RING_F_FCOE]; 537 if ((rxr_idx >= f->offset) && 538 (rxr_idx < f->offset + f->indices)) 539 set_bit(__IXGBE_RX_FCOE, &ring->state); 540 } 541 542 #endif /* IXGBE_FCOE */ 543 /* apply Rx specific ring traits */ 544 ring->count = adapter->rx_ring_count; 545 ring->queue_index = rxr_idx; 546 547 /* assign ring to adapter */ 548 adapter->rx_ring[rxr_idx] = ring; 549 550 /* update count and index */ 551 rxr_count--; 552 rxr_idx += v_count; 553 554 /* push pointer to next ring */ 555 ring++; 556 } 557 558 return 0; 559 } 560 561 /** 562 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector 563 * @adapter: board private structure to initialize 564 * @v_idx: Index of vector to be freed 565 * 566 * This function frees the memory allocated to the q_vector. In addition if 567 * NAPI is enabled it will delete any references to the NAPI struct prior 568 * to freeing the q_vector. 569 **/ 570 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx) 571 { 572 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; 573 struct ixgbe_ring *ring; 574 575 ixgbe_for_each_ring(ring, q_vector->tx) 576 adapter->tx_ring[ring->queue_index] = NULL; 577 578 ixgbe_for_each_ring(ring, q_vector->rx) 579 adapter->rx_ring[ring->queue_index] = NULL; 580 581 adapter->q_vector[v_idx] = NULL; 582 netif_napi_del(&q_vector->napi); 583 584 /* 585 * ixgbe_get_stats64() might access the rings on this vector, 586 * we must wait a grace period before freeing it. 587 */ 588 kfree_rcu(q_vector, rcu); 589 } 590 591 /** 592 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors 593 * @adapter: board private structure to initialize 594 * 595 * We allocate one q_vector per queue interrupt. If allocation fails we 596 * return -ENOMEM. 597 **/ 598 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) 599 { 600 int q_vectors = adapter->num_q_vectors; 601 int rxr_remaining = adapter->num_rx_queues; 602 int txr_remaining = adapter->num_tx_queues; 603 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 604 int err; 605 606 /* only one q_vector if MSI-X is disabled. */ 607 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 608 q_vectors = 1; 609 610 if (q_vectors >= (rxr_remaining + txr_remaining)) { 611 for (; rxr_remaining; v_idx++) { 612 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 613 0, 0, 1, rxr_idx); 614 615 if (err) 616 goto err_out; 617 618 /* update counts and index */ 619 rxr_remaining--; 620 rxr_idx++; 621 } 622 } 623 624 for (; v_idx < q_vectors; v_idx++) { 625 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 626 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 627 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 628 tqpv, txr_idx, 629 rqpv, rxr_idx); 630 631 if (err) 632 goto err_out; 633 634 /* update counts and index */ 635 rxr_remaining -= rqpv; 636 txr_remaining -= tqpv; 637 rxr_idx++; 638 txr_idx++; 639 } 640 641 return 0; 642 643 err_out: 644 adapter->num_tx_queues = 0; 645 adapter->num_rx_queues = 0; 646 adapter->num_q_vectors = 0; 647 648 while (v_idx--) 649 ixgbe_free_q_vector(adapter, v_idx); 650 651 return -ENOMEM; 652 } 653 654 /** 655 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors 656 * @adapter: board private structure to initialize 657 * 658 * This function frees the memory allocated to the q_vectors. In addition if 659 * NAPI is enabled it will delete any references to the NAPI struct prior 660 * to freeing the q_vector. 661 **/ 662 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) 663 { 664 int v_idx = adapter->num_q_vectors; 665 666 adapter->num_tx_queues = 0; 667 adapter->num_rx_queues = 0; 668 adapter->num_q_vectors = 0; 669 670 while (v_idx--) 671 ixgbe_free_q_vector(adapter, v_idx); 672 } 673 674 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) 675 { 676 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 677 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 678 pci_disable_msix(adapter->pdev); 679 kfree(adapter->msix_entries); 680 adapter->msix_entries = NULL; 681 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 682 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; 683 pci_disable_msi(adapter->pdev); 684 } 685 } 686 687 /** 688 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported 689 * @adapter: board private structure to initialize 690 * 691 * Attempt to configure the interrupts using the best available 692 * capabilities of the hardware and the kernel. 693 **/ 694 static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) 695 { 696 struct ixgbe_hw *hw = &adapter->hw; 697 int vector, v_budget, err; 698 699 /* 700 * It's easy to be greedy for MSI-X vectors, but it really 701 * doesn't do us much good if we have a lot more vectors 702 * than CPU's. So let's be conservative and only ask for 703 * (roughly) the same number of vectors as there are CPU's. 704 * The default is to use pairs of vectors. 705 */ 706 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); 707 v_budget = min_t(int, v_budget, num_online_cpus()); 708 v_budget += NON_Q_VECTORS; 709 710 /* 711 * At the same time, hardware can only support a maximum of 712 * hw.mac->max_msix_vectors vectors. With features 713 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx 714 * descriptor queues supported by our device. Thus, we cap it off in 715 * those rare cases where the cpu count also exceeds our vector limit. 716 */ 717 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); 718 719 /* A failure in MSI-X entry allocation isn't fatal, but it does 720 * mean we disable MSI-X capabilities of the adapter. */ 721 adapter->msix_entries = kcalloc(v_budget, 722 sizeof(struct msix_entry), GFP_KERNEL); 723 if (adapter->msix_entries) { 724 for (vector = 0; vector < v_budget; vector++) 725 adapter->msix_entries[vector].entry = vector; 726 727 ixgbe_acquire_msix_vectors(adapter, v_budget); 728 729 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 730 return; 731 } 732 733 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 734 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; 735 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 736 e_err(probe, 737 "ATR is not supported while multiple " 738 "queues are disabled. Disabling Flow Director\n"); 739 } 740 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 741 adapter->atr_sample_rate = 0; 742 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 743 ixgbe_disable_sriov(adapter); 744 745 ixgbe_set_num_queues(adapter); 746 adapter->num_q_vectors = 1; 747 748 err = pci_enable_msi(adapter->pdev); 749 if (err) { 750 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, 751 "Unable to allocate MSI interrupt, " 752 "falling back to legacy. Error: %d\n", err); 753 return; 754 } 755 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; 756 } 757 758 /** 759 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme 760 * @adapter: board private structure to initialize 761 * 762 * We determine which interrupt scheme to use based on... 763 * - Kernel support (MSI, MSI-X) 764 * - which can be user-defined (via MODULE_PARAM) 765 * - Hardware queue count (num_*_queues) 766 * - defined by miscellaneous hardware support/features (RSS, etc.) 767 **/ 768 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) 769 { 770 int err; 771 772 /* Number of supported queues */ 773 ixgbe_set_num_queues(adapter); 774 775 /* Set interrupt mode */ 776 ixgbe_set_interrupt_capability(adapter); 777 778 err = ixgbe_alloc_q_vectors(adapter); 779 if (err) { 780 e_dev_err("Unable to allocate memory for queue vectors\n"); 781 goto err_alloc_q_vectors; 782 } 783 784 ixgbe_cache_ring_register(adapter); 785 786 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", 787 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", 788 adapter->num_rx_queues, adapter->num_tx_queues); 789 790 set_bit(__IXGBE_DOWN, &adapter->state); 791 792 return 0; 793 794 err_alloc_q_vectors: 795 ixgbe_reset_interrupt_capability(adapter); 796 return err; 797 } 798 799 /** 800 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings 801 * @adapter: board private structure to clear interrupt scheme on 802 * 803 * We go through and clear interrupt specific resources and reset the structure 804 * to pre-load conditions 805 **/ 806 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) 807 { 808 adapter->num_tx_queues = 0; 809 adapter->num_rx_queues = 0; 810 811 ixgbe_free_q_vectors(adapter); 812 ixgbe_reset_interrupt_capability(adapter); 813 } 814 815 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, 816 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 817 { 818 struct ixgbe_adv_tx_context_desc *context_desc; 819 u16 i = tx_ring->next_to_use; 820 821 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i); 822 823 i++; 824 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 825 826 /* set bits to identify this as an advanced context descriptor */ 827 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; 828 829 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 830 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 831 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 832 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 833 } 834 835