1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "ixgbe.h" 30 #include "ixgbe_sriov.h" 31 32 #ifdef CONFIG_IXGBE_DCB 33 /** 34 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV 35 * @adapter: board private structure to initialize 36 * 37 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It 38 * will also try to cache the proper offsets if RSS/FCoE are enabled along 39 * with VMDq. 40 * 41 **/ 42 static bool ixgbe_cache_ring_dcb_sriov(struct ixgbe_adapter *adapter) 43 { 44 #ifdef IXGBE_FCOE 45 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; 46 #endif /* IXGBE_FCOE */ 47 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 48 int i; 49 u16 reg_idx; 50 u8 tcs = netdev_get_num_tc(adapter->netdev); 51 52 /* verify we have DCB queueing enabled before proceeding */ 53 if (tcs <= 1) 54 return false; 55 56 /* verify we have VMDq enabled before proceeding */ 57 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 58 return false; 59 60 /* start at VMDq register offset for SR-IOV enabled setups */ 61 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 62 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { 63 /* If we are greater than indices move to next pool */ 64 if ((reg_idx & ~vmdq->mask) >= tcs) 65 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 66 adapter->rx_ring[i]->reg_idx = reg_idx; 67 } 68 69 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 70 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { 71 /* If we are greater than indices move to next pool */ 72 if ((reg_idx & ~vmdq->mask) >= tcs) 73 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 74 adapter->tx_ring[i]->reg_idx = reg_idx; 75 } 76 77 #ifdef IXGBE_FCOE 78 /* nothing to do if FCoE is disabled */ 79 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 80 return true; 81 82 /* The work is already done if the FCoE ring is shared */ 83 if (fcoe->offset < tcs) 84 return true; 85 86 /* The FCoE rings exist separately, we need to move their reg_idx */ 87 if (fcoe->indices) { 88 u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 89 u8 fcoe_tc = ixgbe_fcoe_get_tc(adapter); 90 91 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; 92 for (i = fcoe->offset; i < adapter->num_rx_queues; i++) { 93 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; 94 adapter->rx_ring[i]->reg_idx = reg_idx; 95 reg_idx++; 96 } 97 98 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; 99 for (i = fcoe->offset; i < adapter->num_tx_queues; i++) { 100 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; 101 adapter->tx_ring[i]->reg_idx = reg_idx; 102 reg_idx++; 103 } 104 } 105 106 #endif /* IXGBE_FCOE */ 107 return true; 108 } 109 110 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ 111 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, 112 unsigned int *tx, unsigned int *rx) 113 { 114 struct net_device *dev = adapter->netdev; 115 struct ixgbe_hw *hw = &adapter->hw; 116 u8 num_tcs = netdev_get_num_tc(dev); 117 118 *tx = 0; 119 *rx = 0; 120 121 switch (hw->mac.type) { 122 case ixgbe_mac_82598EB: 123 /* TxQs/TC: 4 RxQs/TC: 8 */ 124 *tx = tc << 2; /* 0, 4, 8, 12, 16, 20, 24, 28 */ 125 *rx = tc << 3; /* 0, 8, 16, 24, 32, 40, 48, 56 */ 126 break; 127 case ixgbe_mac_82599EB: 128 case ixgbe_mac_X540: 129 case ixgbe_mac_X550: 130 case ixgbe_mac_X550EM_x: 131 case ixgbe_mac_x550em_a: 132 if (num_tcs > 4) { 133 /* 134 * TCs : TC0/1 TC2/3 TC4-7 135 * TxQs/TC: 32 16 8 136 * RxQs/TC: 16 16 16 137 */ 138 *rx = tc << 4; 139 if (tc < 3) 140 *tx = tc << 5; /* 0, 32, 64 */ 141 else if (tc < 5) 142 *tx = (tc + 2) << 4; /* 80, 96 */ 143 else 144 *tx = (tc + 8) << 3; /* 104, 112, 120 */ 145 } else { 146 /* 147 * TCs : TC0 TC1 TC2/3 148 * TxQs/TC: 64 32 16 149 * RxQs/TC: 32 32 32 150 */ 151 *rx = tc << 5; 152 if (tc < 2) 153 *tx = tc << 6; /* 0, 64 */ 154 else 155 *tx = (tc + 4) << 4; /* 96, 112 */ 156 } 157 default: 158 break; 159 } 160 } 161 162 /** 163 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB 164 * @adapter: board private structure to initialize 165 * 166 * Cache the descriptor ring offsets for DCB to the assigned rings. 167 * 168 **/ 169 static bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) 170 { 171 struct net_device *dev = adapter->netdev; 172 unsigned int tx_idx, rx_idx; 173 int tc, offset, rss_i, i; 174 u8 num_tcs = netdev_get_num_tc(dev); 175 176 /* verify we have DCB queueing enabled before proceeding */ 177 if (num_tcs <= 1) 178 return false; 179 180 rss_i = adapter->ring_feature[RING_F_RSS].indices; 181 182 for (tc = 0, offset = 0; tc < num_tcs; tc++, offset += rss_i) { 183 ixgbe_get_first_reg_idx(adapter, tc, &tx_idx, &rx_idx); 184 for (i = 0; i < rss_i; i++, tx_idx++, rx_idx++) { 185 adapter->tx_ring[offset + i]->reg_idx = tx_idx; 186 adapter->rx_ring[offset + i]->reg_idx = rx_idx; 187 adapter->tx_ring[offset + i]->dcb_tc = tc; 188 adapter->rx_ring[offset + i]->dcb_tc = tc; 189 } 190 } 191 192 return true; 193 } 194 195 #endif 196 /** 197 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov 198 * @adapter: board private structure to initialize 199 * 200 * SR-IOV doesn't use any descriptor rings but changes the default if 201 * no other mapping is used. 202 * 203 */ 204 static bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) 205 { 206 #ifdef IXGBE_FCOE 207 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; 208 #endif /* IXGBE_FCOE */ 209 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 210 struct ixgbe_ring_feature *rss = &adapter->ring_feature[RING_F_RSS]; 211 int i; 212 u16 reg_idx; 213 214 /* only proceed if VMDq is enabled */ 215 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)) 216 return false; 217 218 /* start at VMDq register offset for SR-IOV enabled setups */ 219 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 220 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { 221 #ifdef IXGBE_FCOE 222 /* Allow first FCoE queue to be mapped as RSS */ 223 if (fcoe->offset && (i > fcoe->offset)) 224 break; 225 #endif 226 /* If we are greater than indices move to next pool */ 227 if ((reg_idx & ~vmdq->mask) >= rss->indices) 228 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 229 adapter->rx_ring[i]->reg_idx = reg_idx; 230 } 231 232 #ifdef IXGBE_FCOE 233 /* FCoE uses a linear block of queues so just assigning 1:1 */ 234 for (; i < adapter->num_rx_queues; i++, reg_idx++) 235 adapter->rx_ring[i]->reg_idx = reg_idx; 236 237 #endif 238 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 239 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { 240 #ifdef IXGBE_FCOE 241 /* Allow first FCoE queue to be mapped as RSS */ 242 if (fcoe->offset && (i > fcoe->offset)) 243 break; 244 #endif 245 /* If we are greater than indices move to next pool */ 246 if ((reg_idx & rss->mask) >= rss->indices) 247 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 248 adapter->tx_ring[i]->reg_idx = reg_idx; 249 } 250 251 #ifdef IXGBE_FCOE 252 /* FCoE uses a linear block of queues so just assigning 1:1 */ 253 for (; i < adapter->num_tx_queues; i++, reg_idx++) 254 adapter->tx_ring[i]->reg_idx = reg_idx; 255 256 #endif 257 258 return true; 259 } 260 261 /** 262 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS 263 * @adapter: board private structure to initialize 264 * 265 * Cache the descriptor ring offsets for RSS to the assigned rings. 266 * 267 **/ 268 static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) 269 { 270 int i; 271 272 for (i = 0; i < adapter->num_rx_queues; i++) 273 adapter->rx_ring[i]->reg_idx = i; 274 for (i = 0; i < adapter->num_tx_queues; i++) 275 adapter->tx_ring[i]->reg_idx = i; 276 277 return true; 278 } 279 280 /** 281 * ixgbe_cache_ring_register - Descriptor ring to register mapping 282 * @adapter: board private structure to initialize 283 * 284 * Once we know the feature-set enabled for the device, we'll cache 285 * the register offset the descriptor ring is assigned to. 286 * 287 * Note, the order the various feature calls is important. It must start with 288 * the "most" features enabled at the same time, then trickle down to the 289 * least amount of features turned on at once. 290 **/ 291 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) 292 { 293 /* start with default case */ 294 adapter->rx_ring[0]->reg_idx = 0; 295 adapter->tx_ring[0]->reg_idx = 0; 296 297 #ifdef CONFIG_IXGBE_DCB 298 if (ixgbe_cache_ring_dcb_sriov(adapter)) 299 return; 300 301 if (ixgbe_cache_ring_dcb(adapter)) 302 return; 303 304 #endif 305 if (ixgbe_cache_ring_sriov(adapter)) 306 return; 307 308 ixgbe_cache_ring_rss(adapter); 309 } 310 311 #define IXGBE_RSS_64Q_MASK 0x3F 312 #define IXGBE_RSS_16Q_MASK 0xF 313 #define IXGBE_RSS_8Q_MASK 0x7 314 #define IXGBE_RSS_4Q_MASK 0x3 315 #define IXGBE_RSS_2Q_MASK 0x1 316 #define IXGBE_RSS_DISABLED_MASK 0x0 317 318 #ifdef CONFIG_IXGBE_DCB 319 /** 320 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB 321 * @adapter: board private structure to initialize 322 * 323 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues 324 * and VM pools where appropriate. Also assign queues based on DCB 325 * priorities and map accordingly.. 326 * 327 **/ 328 static bool ixgbe_set_dcb_sriov_queues(struct ixgbe_adapter *adapter) 329 { 330 int i; 331 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; 332 u16 vmdq_m = 0; 333 #ifdef IXGBE_FCOE 334 u16 fcoe_i = 0; 335 #endif 336 u8 tcs = netdev_get_num_tc(adapter->netdev); 337 338 /* verify we have DCB queueing enabled before proceeding */ 339 if (tcs <= 1) 340 return false; 341 342 /* verify we have VMDq enabled before proceeding */ 343 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 344 return false; 345 346 /* Add starting offset to total pool count */ 347 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; 348 349 /* 16 pools w/ 8 TC per pool */ 350 if (tcs > 4) { 351 vmdq_i = min_t(u16, vmdq_i, 16); 352 vmdq_m = IXGBE_82599_VMDQ_8Q_MASK; 353 /* 32 pools w/ 4 TC per pool */ 354 } else { 355 vmdq_i = min_t(u16, vmdq_i, 32); 356 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK; 357 } 358 359 #ifdef IXGBE_FCOE 360 /* queues in the remaining pools are available for FCoE */ 361 fcoe_i = (128 / __ALIGN_MASK(1, ~vmdq_m)) - vmdq_i; 362 363 #endif 364 /* remove the starting offset from the pool count */ 365 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; 366 367 /* save features for later use */ 368 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; 369 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; 370 371 /* 372 * We do not support DCB, VMDq, and RSS all simultaneously 373 * so we will disable RSS since it is the lowest priority 374 */ 375 adapter->ring_feature[RING_F_RSS].indices = 1; 376 adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK; 377 378 /* disable ATR as it is not supported when VMDq is enabled */ 379 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 380 381 adapter->num_rx_pools = vmdq_i; 382 adapter->num_rx_queues_per_pool = tcs; 383 384 adapter->num_tx_queues = vmdq_i * tcs; 385 adapter->num_rx_queues = vmdq_i * tcs; 386 387 #ifdef IXGBE_FCOE 388 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 389 struct ixgbe_ring_feature *fcoe; 390 391 fcoe = &adapter->ring_feature[RING_F_FCOE]; 392 393 /* limit ourselves based on feature limits */ 394 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); 395 396 if (fcoe_i) { 397 /* alloc queues for FCoE separately */ 398 fcoe->indices = fcoe_i; 399 fcoe->offset = vmdq_i * tcs; 400 401 /* add queues to adapter */ 402 adapter->num_tx_queues += fcoe_i; 403 adapter->num_rx_queues += fcoe_i; 404 } else if (tcs > 1) { 405 /* use queue belonging to FcoE TC */ 406 fcoe->indices = 1; 407 fcoe->offset = ixgbe_fcoe_get_tc(adapter); 408 } else { 409 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 410 411 fcoe->indices = 0; 412 fcoe->offset = 0; 413 } 414 } 415 416 #endif /* IXGBE_FCOE */ 417 /* configure TC to queue mapping */ 418 for (i = 0; i < tcs; i++) 419 netdev_set_tc_queue(adapter->netdev, i, 1, i); 420 421 return true; 422 } 423 424 static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) 425 { 426 struct net_device *dev = adapter->netdev; 427 struct ixgbe_ring_feature *f; 428 int rss_i, rss_m, i; 429 int tcs; 430 431 /* Map queue offset and counts onto allocated tx queues */ 432 tcs = netdev_get_num_tc(dev); 433 434 /* verify we have DCB queueing enabled before proceeding */ 435 if (tcs <= 1) 436 return false; 437 438 /* determine the upper limit for our current DCB mode */ 439 rss_i = dev->num_tx_queues / tcs; 440 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 441 /* 8 TC w/ 4 queues per TC */ 442 rss_i = min_t(u16, rss_i, 4); 443 rss_m = IXGBE_RSS_4Q_MASK; 444 } else if (tcs > 4) { 445 /* 8 TC w/ 8 queues per TC */ 446 rss_i = min_t(u16, rss_i, 8); 447 rss_m = IXGBE_RSS_8Q_MASK; 448 } else { 449 /* 4 TC w/ 16 queues per TC */ 450 rss_i = min_t(u16, rss_i, 16); 451 rss_m = IXGBE_RSS_16Q_MASK; 452 } 453 454 /* set RSS mask and indices */ 455 f = &adapter->ring_feature[RING_F_RSS]; 456 rss_i = min_t(int, rss_i, f->limit); 457 f->indices = rss_i; 458 f->mask = rss_m; 459 460 /* disable ATR as it is not supported when multiple TCs are enabled */ 461 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 462 463 #ifdef IXGBE_FCOE 464 /* FCoE enabled queues require special configuration indexed 465 * by feature specific indices and offset. Here we map FCoE 466 * indices onto the DCB queue pairs allowing FCoE to own 467 * configuration later. 468 */ 469 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 470 u8 tc = ixgbe_fcoe_get_tc(adapter); 471 472 f = &adapter->ring_feature[RING_F_FCOE]; 473 f->indices = min_t(u16, rss_i, f->limit); 474 f->offset = rss_i * tc; 475 } 476 477 #endif /* IXGBE_FCOE */ 478 for (i = 0; i < tcs; i++) 479 netdev_set_tc_queue(dev, i, rss_i, rss_i * i); 480 481 adapter->num_tx_queues = rss_i * tcs; 482 adapter->num_rx_queues = rss_i * tcs; 483 484 return true; 485 } 486 487 #endif 488 /** 489 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices 490 * @adapter: board private structure to initialize 491 * 492 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues 493 * and VM pools where appropriate. If RSS is available, then also try and 494 * enable RSS and map accordingly. 495 * 496 **/ 497 static bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) 498 { 499 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; 500 u16 vmdq_m = 0; 501 u16 rss_i = adapter->ring_feature[RING_F_RSS].limit; 502 u16 rss_m = IXGBE_RSS_DISABLED_MASK; 503 #ifdef IXGBE_FCOE 504 u16 fcoe_i = 0; 505 #endif 506 bool pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); 507 508 /* only proceed if SR-IOV is enabled */ 509 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 510 return false; 511 512 /* Add starting offset to total pool count */ 513 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; 514 515 /* double check we are limited to maximum pools */ 516 vmdq_i = min_t(u16, IXGBE_MAX_VMDQ_INDICES, vmdq_i); 517 518 /* 64 pool mode with 2 queues per pool */ 519 if ((vmdq_i > 32) || (vmdq_i > 16 && pools)) { 520 vmdq_m = IXGBE_82599_VMDQ_2Q_MASK; 521 rss_m = IXGBE_RSS_2Q_MASK; 522 rss_i = min_t(u16, rss_i, 2); 523 /* 32 pool mode with up to 4 queues per pool */ 524 } else { 525 vmdq_m = IXGBE_82599_VMDQ_4Q_MASK; 526 rss_m = IXGBE_RSS_4Q_MASK; 527 /* We can support 4, 2, or 1 queues */ 528 rss_i = (rss_i > 3) ? 4 : (rss_i > 1) ? 2 : 1; 529 } 530 531 #ifdef IXGBE_FCOE 532 /* queues in the remaining pools are available for FCoE */ 533 fcoe_i = 128 - (vmdq_i * __ALIGN_MASK(1, ~vmdq_m)); 534 535 #endif 536 /* remove the starting offset from the pool count */ 537 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; 538 539 /* save features for later use */ 540 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; 541 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; 542 543 /* limit RSS based on user input and save for later use */ 544 adapter->ring_feature[RING_F_RSS].indices = rss_i; 545 adapter->ring_feature[RING_F_RSS].mask = rss_m; 546 547 adapter->num_rx_pools = vmdq_i; 548 adapter->num_rx_queues_per_pool = rss_i; 549 550 adapter->num_rx_queues = vmdq_i * rss_i; 551 adapter->num_tx_queues = vmdq_i * rss_i; 552 553 /* disable ATR as it is not supported when VMDq is enabled */ 554 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 555 556 #ifdef IXGBE_FCOE 557 /* 558 * FCoE can use rings from adjacent buffers to allow RSS 559 * like behavior. To account for this we need to add the 560 * FCoE indices to the total ring count. 561 */ 562 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 563 struct ixgbe_ring_feature *fcoe; 564 565 fcoe = &adapter->ring_feature[RING_F_FCOE]; 566 567 /* limit ourselves based on feature limits */ 568 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); 569 570 if (vmdq_i > 1 && fcoe_i) { 571 /* alloc queues for FCoE separately */ 572 fcoe->indices = fcoe_i; 573 fcoe->offset = vmdq_i * rss_i; 574 } else { 575 /* merge FCoE queues with RSS queues */ 576 fcoe_i = min_t(u16, fcoe_i + rss_i, num_online_cpus()); 577 578 /* limit indices to rss_i if MSI-X is disabled */ 579 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 580 fcoe_i = rss_i; 581 582 /* attempt to reserve some queues for just FCoE */ 583 fcoe->indices = min_t(u16, fcoe_i, fcoe->limit); 584 fcoe->offset = fcoe_i - fcoe->indices; 585 586 fcoe_i -= rss_i; 587 } 588 589 /* add queues to adapter */ 590 adapter->num_tx_queues += fcoe_i; 591 adapter->num_rx_queues += fcoe_i; 592 } 593 594 #endif 595 return true; 596 } 597 598 /** 599 * ixgbe_set_rss_queues - Allocate queues for RSS 600 * @adapter: board private structure to initialize 601 * 602 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 603 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 604 * 605 **/ 606 static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) 607 { 608 struct ixgbe_hw *hw = &adapter->hw; 609 struct ixgbe_ring_feature *f; 610 u16 rss_i; 611 612 /* set mask for 16 queue limit of RSS */ 613 f = &adapter->ring_feature[RING_F_RSS]; 614 rss_i = f->limit; 615 616 f->indices = rss_i; 617 618 if (hw->mac.type < ixgbe_mac_X550) 619 f->mask = IXGBE_RSS_16Q_MASK; 620 else 621 f->mask = IXGBE_RSS_64Q_MASK; 622 623 /* disable ATR by default, it will be configured below */ 624 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 625 626 /* 627 * Use Flow Director in addition to RSS to ensure the best 628 * distribution of flows across cores, even when an FDIR flow 629 * isn't matched. 630 */ 631 if (rss_i > 1 && adapter->atr_sample_rate) { 632 f = &adapter->ring_feature[RING_F_FDIR]; 633 634 rss_i = f->indices = f->limit; 635 636 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 637 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 638 } 639 640 #ifdef IXGBE_FCOE 641 /* 642 * FCoE can exist on the same rings as standard network traffic 643 * however it is preferred to avoid that if possible. In order 644 * to get the best performance we allocate as many FCoE queues 645 * as we can and we place them at the end of the ring array to 646 * avoid sharing queues with standard RSS on systems with 24 or 647 * more CPUs. 648 */ 649 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { 650 struct net_device *dev = adapter->netdev; 651 u16 fcoe_i; 652 653 f = &adapter->ring_feature[RING_F_FCOE]; 654 655 /* merge FCoE queues with RSS queues */ 656 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); 657 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); 658 659 /* limit indices to rss_i if MSI-X is disabled */ 660 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 661 fcoe_i = rss_i; 662 663 /* attempt to reserve some queues for just FCoE */ 664 f->indices = min_t(u16, fcoe_i, f->limit); 665 f->offset = fcoe_i - f->indices; 666 rss_i = max_t(u16, fcoe_i, rss_i); 667 } 668 669 #endif /* IXGBE_FCOE */ 670 adapter->num_rx_queues = rss_i; 671 adapter->num_tx_queues = rss_i; 672 673 return true; 674 } 675 676 /** 677 * ixgbe_set_num_queues - Allocate queues for device, feature dependent 678 * @adapter: board private structure to initialize 679 * 680 * This is the top level queue allocation routine. The order here is very 681 * important, starting with the "most" number of features turned on at once, 682 * and ending with the smallest set of features. This way large combinations 683 * can be allocated if they're turned on, and smaller combinations are the 684 * fallthrough conditions. 685 * 686 **/ 687 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) 688 { 689 /* Start with base case */ 690 adapter->num_rx_queues = 1; 691 adapter->num_tx_queues = 1; 692 adapter->num_rx_pools = adapter->num_rx_queues; 693 adapter->num_rx_queues_per_pool = 1; 694 695 #ifdef CONFIG_IXGBE_DCB 696 if (ixgbe_set_dcb_sriov_queues(adapter)) 697 return; 698 699 if (ixgbe_set_dcb_queues(adapter)) 700 return; 701 702 #endif 703 if (ixgbe_set_sriov_queues(adapter)) 704 return; 705 706 ixgbe_set_rss_queues(adapter); 707 } 708 709 /** 710 * ixgbe_acquire_msix_vectors - acquire MSI-X vectors 711 * @adapter: board private structure 712 * 713 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 714 * return a negative error code if unable to acquire MSI-X vectors for any 715 * reason. 716 */ 717 static int ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter) 718 { 719 struct ixgbe_hw *hw = &adapter->hw; 720 int i, vectors, vector_threshold; 721 722 /* We start by asking for one vector per queue pair */ 723 vectors = max(adapter->num_rx_queues, adapter->num_tx_queues); 724 725 /* It is easy to be greedy for MSI-X vectors. However, it really 726 * doesn't do much good if we have a lot more vectors than CPUs. We'll 727 * be somewhat conservative and only ask for (roughly) the same number 728 * of vectors as there are CPUs. 729 */ 730 vectors = min_t(int, vectors, num_online_cpus()); 731 732 /* Some vectors are necessary for non-queue interrupts */ 733 vectors += NON_Q_VECTORS; 734 735 /* Hardware can only support a maximum of hw.mac->max_msix_vectors. 736 * With features such as RSS and VMDq, we can easily surpass the 737 * number of Rx and Tx descriptor queues supported by our device. 738 * Thus, we cap the maximum in the rare cases where the CPU count also 739 * exceeds our vector limit 740 */ 741 vectors = min_t(int, vectors, hw->mac.max_msix_vectors); 742 743 /* We want a minimum of two MSI-X vectors for (1) a TxQ[0] + RxQ[0] 744 * handler, and (2) an Other (Link Status Change, etc.) handler. 745 */ 746 vector_threshold = MIN_MSIX_COUNT; 747 748 adapter->msix_entries = kcalloc(vectors, 749 sizeof(struct msix_entry), 750 GFP_KERNEL); 751 if (!adapter->msix_entries) 752 return -ENOMEM; 753 754 for (i = 0; i < vectors; i++) 755 adapter->msix_entries[i].entry = i; 756 757 vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries, 758 vector_threshold, vectors); 759 760 if (vectors < 0) { 761 /* A negative count of allocated vectors indicates an error in 762 * acquiring within the specified range of MSI-X vectors 763 */ 764 e_dev_warn("Failed to allocate MSI-X interrupts. Err: %d\n", 765 vectors); 766 767 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 768 kfree(adapter->msix_entries); 769 adapter->msix_entries = NULL; 770 771 return vectors; 772 } 773 774 /* we successfully allocated some number of vectors within our 775 * requested range. 776 */ 777 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; 778 779 /* Adjust for only the vectors we'll use, which is minimum 780 * of max_q_vectors, or the number of vectors we were allocated. 781 */ 782 vectors -= NON_Q_VECTORS; 783 adapter->num_q_vectors = min_t(int, vectors, adapter->max_q_vectors); 784 785 return 0; 786 } 787 788 static void ixgbe_add_ring(struct ixgbe_ring *ring, 789 struct ixgbe_ring_container *head) 790 { 791 ring->next = head->ring; 792 head->ring = ring; 793 head->count++; 794 } 795 796 /** 797 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector 798 * @adapter: board private structure to initialize 799 * @v_count: q_vectors allocated on adapter, used for ring interleaving 800 * @v_idx: index of vector in adapter struct 801 * @txr_count: total number of Tx rings to allocate 802 * @txr_idx: index of first Tx ring to allocate 803 * @rxr_count: total number of Rx rings to allocate 804 * @rxr_idx: index of first Rx ring to allocate 805 * 806 * We allocate one q_vector. If allocation fails we return -ENOMEM. 807 **/ 808 static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, 809 int v_count, int v_idx, 810 int txr_count, int txr_idx, 811 int rxr_count, int rxr_idx) 812 { 813 struct ixgbe_q_vector *q_vector; 814 struct ixgbe_ring *ring; 815 int node = NUMA_NO_NODE; 816 int cpu = -1; 817 int ring_count, size; 818 u8 tcs = netdev_get_num_tc(adapter->netdev); 819 820 ring_count = txr_count + rxr_count; 821 size = sizeof(struct ixgbe_q_vector) + 822 (sizeof(struct ixgbe_ring) * ring_count); 823 824 /* customize cpu for Flow Director mapping */ 825 if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 826 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 827 if (rss_i > 1 && adapter->atr_sample_rate) { 828 if (cpu_online(v_idx)) { 829 cpu = v_idx; 830 node = cpu_to_node(cpu); 831 } 832 } 833 } 834 835 /* allocate q_vector and rings */ 836 q_vector = kzalloc_node(size, GFP_KERNEL, node); 837 if (!q_vector) 838 q_vector = kzalloc(size, GFP_KERNEL); 839 if (!q_vector) 840 return -ENOMEM; 841 842 /* setup affinity mask and node */ 843 if (cpu != -1) 844 cpumask_set_cpu(cpu, &q_vector->affinity_mask); 845 q_vector->numa_node = node; 846 847 #ifdef CONFIG_IXGBE_DCA 848 /* initialize CPU for DCA */ 849 q_vector->cpu = -1; 850 851 #endif 852 /* initialize NAPI */ 853 netif_napi_add(adapter->netdev, &q_vector->napi, 854 ixgbe_poll, 64); 855 856 /* tie q_vector and adapter together */ 857 adapter->q_vector[v_idx] = q_vector; 858 q_vector->adapter = adapter; 859 q_vector->v_idx = v_idx; 860 861 /* initialize work limits */ 862 q_vector->tx.work_limit = adapter->tx_work_limit; 863 864 /* initialize pointer to rings */ 865 ring = q_vector->ring; 866 867 /* intialize ITR */ 868 if (txr_count && !rxr_count) { 869 /* tx only vector */ 870 if (adapter->tx_itr_setting == 1) 871 q_vector->itr = IXGBE_12K_ITR; 872 else 873 q_vector->itr = adapter->tx_itr_setting; 874 } else { 875 /* rx or rx/tx vector */ 876 if (adapter->rx_itr_setting == 1) 877 q_vector->itr = IXGBE_20K_ITR; 878 else 879 q_vector->itr = adapter->rx_itr_setting; 880 } 881 882 while (txr_count) { 883 /* assign generic ring traits */ 884 ring->dev = &adapter->pdev->dev; 885 ring->netdev = adapter->netdev; 886 887 /* configure backlink on ring */ 888 ring->q_vector = q_vector; 889 890 /* update q_vector Tx values */ 891 ixgbe_add_ring(ring, &q_vector->tx); 892 893 /* apply Tx specific ring traits */ 894 ring->count = adapter->tx_ring_count; 895 if (adapter->num_rx_pools > 1) 896 ring->queue_index = 897 txr_idx % adapter->num_rx_queues_per_pool; 898 else 899 ring->queue_index = txr_idx; 900 901 /* assign ring to adapter */ 902 adapter->tx_ring[txr_idx] = ring; 903 904 /* update count and index */ 905 txr_count--; 906 txr_idx += v_count; 907 908 /* push pointer to next ring */ 909 ring++; 910 } 911 912 while (rxr_count) { 913 /* assign generic ring traits */ 914 ring->dev = &adapter->pdev->dev; 915 ring->netdev = adapter->netdev; 916 917 /* configure backlink on ring */ 918 ring->q_vector = q_vector; 919 920 /* update q_vector Rx values */ 921 ixgbe_add_ring(ring, &q_vector->rx); 922 923 /* 924 * 82599 errata, UDP frames with a 0 checksum 925 * can be marked as checksum errors. 926 */ 927 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 928 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); 929 930 #ifdef IXGBE_FCOE 931 if (adapter->netdev->features & NETIF_F_FCOE_MTU) { 932 struct ixgbe_ring_feature *f; 933 f = &adapter->ring_feature[RING_F_FCOE]; 934 if ((rxr_idx >= f->offset) && 935 (rxr_idx < f->offset + f->indices)) 936 set_bit(__IXGBE_RX_FCOE, &ring->state); 937 } 938 939 #endif /* IXGBE_FCOE */ 940 /* apply Rx specific ring traits */ 941 ring->count = adapter->rx_ring_count; 942 if (adapter->num_rx_pools > 1) 943 ring->queue_index = 944 rxr_idx % adapter->num_rx_queues_per_pool; 945 else 946 ring->queue_index = rxr_idx; 947 948 /* assign ring to adapter */ 949 adapter->rx_ring[rxr_idx] = ring; 950 951 /* update count and index */ 952 rxr_count--; 953 rxr_idx += v_count; 954 955 /* push pointer to next ring */ 956 ring++; 957 } 958 959 return 0; 960 } 961 962 /** 963 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector 964 * @adapter: board private structure to initialize 965 * @v_idx: Index of vector to be freed 966 * 967 * This function frees the memory allocated to the q_vector. In addition if 968 * NAPI is enabled it will delete any references to the NAPI struct prior 969 * to freeing the q_vector. 970 **/ 971 static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx) 972 { 973 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; 974 struct ixgbe_ring *ring; 975 976 ixgbe_for_each_ring(ring, q_vector->tx) 977 adapter->tx_ring[ring->queue_index] = NULL; 978 979 ixgbe_for_each_ring(ring, q_vector->rx) 980 adapter->rx_ring[ring->queue_index] = NULL; 981 982 adapter->q_vector[v_idx] = NULL; 983 napi_hash_del(&q_vector->napi); 984 netif_napi_del(&q_vector->napi); 985 986 /* 987 * ixgbe_get_stats64() might access the rings on this vector, 988 * we must wait a grace period before freeing it. 989 */ 990 kfree_rcu(q_vector, rcu); 991 } 992 993 /** 994 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors 995 * @adapter: board private structure to initialize 996 * 997 * We allocate one q_vector per queue interrupt. If allocation fails we 998 * return -ENOMEM. 999 **/ 1000 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) 1001 { 1002 int q_vectors = adapter->num_q_vectors; 1003 int rxr_remaining = adapter->num_rx_queues; 1004 int txr_remaining = adapter->num_tx_queues; 1005 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1006 int err; 1007 1008 /* only one q_vector if MSI-X is disabled. */ 1009 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) 1010 q_vectors = 1; 1011 1012 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1013 for (; rxr_remaining; v_idx++) { 1014 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 1015 0, 0, 1, rxr_idx); 1016 1017 if (err) 1018 goto err_out; 1019 1020 /* update counts and index */ 1021 rxr_remaining--; 1022 rxr_idx++; 1023 } 1024 } 1025 1026 for (; v_idx < q_vectors; v_idx++) { 1027 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1028 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1029 err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx, 1030 tqpv, txr_idx, 1031 rqpv, rxr_idx); 1032 1033 if (err) 1034 goto err_out; 1035 1036 /* update counts and index */ 1037 rxr_remaining -= rqpv; 1038 txr_remaining -= tqpv; 1039 rxr_idx++; 1040 txr_idx++; 1041 } 1042 1043 return 0; 1044 1045 err_out: 1046 adapter->num_tx_queues = 0; 1047 adapter->num_rx_queues = 0; 1048 adapter->num_q_vectors = 0; 1049 1050 while (v_idx--) 1051 ixgbe_free_q_vector(adapter, v_idx); 1052 1053 return -ENOMEM; 1054 } 1055 1056 /** 1057 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors 1058 * @adapter: board private structure to initialize 1059 * 1060 * This function frees the memory allocated to the q_vectors. In addition if 1061 * NAPI is enabled it will delete any references to the NAPI struct prior 1062 * to freeing the q_vector. 1063 **/ 1064 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) 1065 { 1066 int v_idx = adapter->num_q_vectors; 1067 1068 adapter->num_tx_queues = 0; 1069 adapter->num_rx_queues = 0; 1070 adapter->num_q_vectors = 0; 1071 1072 while (v_idx--) 1073 ixgbe_free_q_vector(adapter, v_idx); 1074 } 1075 1076 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) 1077 { 1078 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 1079 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 1080 pci_disable_msix(adapter->pdev); 1081 kfree(adapter->msix_entries); 1082 adapter->msix_entries = NULL; 1083 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1084 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; 1085 pci_disable_msi(adapter->pdev); 1086 } 1087 } 1088 1089 /** 1090 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported 1091 * @adapter: board private structure to initialize 1092 * 1093 * Attempt to configure the interrupts using the best available 1094 * capabilities of the hardware and the kernel. 1095 **/ 1096 static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) 1097 { 1098 int err; 1099 1100 /* We will try to get MSI-X interrupts first */ 1101 if (!ixgbe_acquire_msix_vectors(adapter)) 1102 return; 1103 1104 /* At this point, we do not have MSI-X capabilities. We need to 1105 * reconfigure or disable various features which require MSI-X 1106 * capability. 1107 */ 1108 1109 /* Disable DCB unless we only have a single traffic class */ 1110 if (netdev_get_num_tc(adapter->netdev) > 1) { 1111 e_dev_warn("Number of DCB TCs exceeds number of available queues. Disabling DCB support.\n"); 1112 netdev_reset_tc(adapter->netdev); 1113 1114 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 1115 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 1116 1117 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1118 adapter->temp_dcb_cfg.pfc_mode_enable = false; 1119 adapter->dcb_cfg.pfc_mode_enable = false; 1120 } 1121 1122 adapter->dcb_cfg.num_tcs.pg_tcs = 1; 1123 adapter->dcb_cfg.num_tcs.pfc_tcs = 1; 1124 1125 /* Disable SR-IOV support */ 1126 e_dev_warn("Disabling SR-IOV support\n"); 1127 ixgbe_disable_sriov(adapter); 1128 1129 /* Disable RSS */ 1130 e_dev_warn("Disabling RSS support\n"); 1131 adapter->ring_feature[RING_F_RSS].limit = 1; 1132 1133 /* recalculate number of queues now that many features have been 1134 * changed or disabled. 1135 */ 1136 ixgbe_set_num_queues(adapter); 1137 adapter->num_q_vectors = 1; 1138 1139 err = pci_enable_msi(adapter->pdev); 1140 if (err) 1141 e_dev_warn("Failed to allocate MSI interrupt, falling back to legacy. Error: %d\n", 1142 err); 1143 else 1144 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; 1145 } 1146 1147 /** 1148 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme 1149 * @adapter: board private structure to initialize 1150 * 1151 * We determine which interrupt scheme to use based on... 1152 * - Kernel support (MSI, MSI-X) 1153 * - which can be user-defined (via MODULE_PARAM) 1154 * - Hardware queue count (num_*_queues) 1155 * - defined by miscellaneous hardware support/features (RSS, etc.) 1156 **/ 1157 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) 1158 { 1159 int err; 1160 1161 /* Number of supported queues */ 1162 ixgbe_set_num_queues(adapter); 1163 1164 /* Set interrupt mode */ 1165 ixgbe_set_interrupt_capability(adapter); 1166 1167 err = ixgbe_alloc_q_vectors(adapter); 1168 if (err) { 1169 e_dev_err("Unable to allocate memory for queue vectors\n"); 1170 goto err_alloc_q_vectors; 1171 } 1172 1173 ixgbe_cache_ring_register(adapter); 1174 1175 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", 1176 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", 1177 adapter->num_rx_queues, adapter->num_tx_queues); 1178 1179 set_bit(__IXGBE_DOWN, &adapter->state); 1180 1181 return 0; 1182 1183 err_alloc_q_vectors: 1184 ixgbe_reset_interrupt_capability(adapter); 1185 return err; 1186 } 1187 1188 /** 1189 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings 1190 * @adapter: board private structure to clear interrupt scheme on 1191 * 1192 * We go through and clear interrupt specific resources and reset the structure 1193 * to pre-load conditions 1194 **/ 1195 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) 1196 { 1197 adapter->num_tx_queues = 0; 1198 adapter->num_rx_queues = 0; 1199 1200 ixgbe_free_q_vectors(adapter); 1201 ixgbe_reset_interrupt_capability(adapter); 1202 } 1203 1204 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, 1205 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1206 { 1207 struct ixgbe_adv_tx_context_desc *context_desc; 1208 u16 i = tx_ring->next_to_use; 1209 1210 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i); 1211 1212 i++; 1213 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1214 1215 /* set bits to identify this as an advanced context descriptor */ 1216 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; 1217 1218 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1219 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1220 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1221 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1222 } 1223 1224