1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* ethtool support for ixgbe */ 5 6 #include <linux/interrupt.h> 7 #include <linux/types.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/pci.h> 11 #include <linux/netdevice.h> 12 #include <linux/ethtool.h> 13 #include <linux/vmalloc.h> 14 #include <linux/highmem.h> 15 #include <linux/uaccess.h> 16 17 #include "ixgbe.h" 18 #include "ixgbe_phy.h" 19 20 21 #define IXGBE_ALL_RAR_ENTRIES 16 22 23 enum {NETDEV_STATS, IXGBE_STATS}; 24 25 struct ixgbe_stats { 26 char stat_string[ETH_GSTRING_LEN]; 27 int type; 28 int sizeof_stat; 29 int stat_offset; 30 }; 31 32 #define IXGBE_STAT(m) IXGBE_STATS, \ 33 sizeof(((struct ixgbe_adapter *)0)->m), \ 34 offsetof(struct ixgbe_adapter, m) 35 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 36 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 37 offsetof(struct rtnl_link_stats64, m) 38 39 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 40 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 41 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 42 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 43 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 44 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 45 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 46 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 47 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 48 {"lsc_int", IXGBE_STAT(lsc_int)}, 49 {"tx_busy", IXGBE_STAT(tx_busy)}, 50 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 51 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 52 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 53 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 54 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 55 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 56 {"broadcast", IXGBE_STAT(stats.bprc)}, 57 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 58 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 59 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 60 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 61 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 62 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 63 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 64 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 65 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 66 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 67 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 68 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 69 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 70 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 71 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 72 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 73 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 74 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 75 {"rx_length_errors", IXGBE_STAT(stats.rlec)}, 76 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 77 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 78 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 79 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 80 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 81 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 82 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 83 {"alloc_rx_page", IXGBE_STAT(alloc_rx_page)}, 84 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 85 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 86 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 87 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 88 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 89 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 90 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 91 {"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)}, 92 {"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)}, 93 {"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)}, 94 {"tx_ipsec", IXGBE_STAT(tx_ipsec)}, 95 {"rx_ipsec", IXGBE_STAT(rx_ipsec)}, 96 #ifdef IXGBE_FCOE 97 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 98 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 99 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 100 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 101 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 102 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 103 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 104 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 105 #endif /* IXGBE_FCOE */ 106 }; 107 108 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 109 * we set the num_rx_queues to evaluate to num_tx_queues. This is 110 * used because we do not have a good way to get the max number of 111 * rx queues with CONFIG_RPS disabled. 112 */ 113 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 114 115 #define IXGBE_QUEUE_STATS_LEN ( \ 116 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 117 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 118 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 119 #define IXGBE_PB_STATS_LEN ( \ 120 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 121 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 122 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 123 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 124 / sizeof(u64)) 125 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 126 IXGBE_PB_STATS_LEN + \ 127 IXGBE_QUEUE_STATS_LEN) 128 129 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 130 "Register test (offline)", "Eeprom test (offline)", 131 "Interrupt test (offline)", "Loopback test (offline)", 132 "Link test (on/offline)" 133 }; 134 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 135 136 static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = { 137 #define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) 138 "legacy-rx", 139 #define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1) 140 "vf-ipsec", 141 }; 142 143 #define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings) 144 145 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane) 146 147 static void ixgbe_set_supported_10gtypes(struct ixgbe_hw *hw, 148 struct ethtool_link_ksettings *cmd) 149 { 150 if (!ixgbe_isbackplane(hw->phy.media_type)) { 151 ethtool_link_ksettings_add_link_mode(cmd, supported, 152 10000baseT_Full); 153 return; 154 } 155 156 switch (hw->device_id) { 157 case IXGBE_DEV_ID_82598: 158 case IXGBE_DEV_ID_82599_KX4: 159 case IXGBE_DEV_ID_82599_KX4_MEZZ: 160 case IXGBE_DEV_ID_X550EM_X_KX4: 161 ethtool_link_ksettings_add_link_mode 162 (cmd, supported, 10000baseKX4_Full); 163 break; 164 case IXGBE_DEV_ID_82598_BX: 165 case IXGBE_DEV_ID_82599_KR: 166 case IXGBE_DEV_ID_X550EM_X_KR: 167 case IXGBE_DEV_ID_X550EM_X_XFI: 168 ethtool_link_ksettings_add_link_mode 169 (cmd, supported, 10000baseKR_Full); 170 break; 171 default: 172 ethtool_link_ksettings_add_link_mode 173 (cmd, supported, 10000baseKX4_Full); 174 ethtool_link_ksettings_add_link_mode 175 (cmd, supported, 10000baseKR_Full); 176 break; 177 } 178 } 179 180 static void ixgbe_set_advertising_10gtypes(struct ixgbe_hw *hw, 181 struct ethtool_link_ksettings *cmd) 182 { 183 if (!ixgbe_isbackplane(hw->phy.media_type)) { 184 ethtool_link_ksettings_add_link_mode(cmd, advertising, 185 10000baseT_Full); 186 return; 187 } 188 189 switch (hw->device_id) { 190 case IXGBE_DEV_ID_82598: 191 case IXGBE_DEV_ID_82599_KX4: 192 case IXGBE_DEV_ID_82599_KX4_MEZZ: 193 case IXGBE_DEV_ID_X550EM_X_KX4: 194 ethtool_link_ksettings_add_link_mode 195 (cmd, advertising, 10000baseKX4_Full); 196 break; 197 case IXGBE_DEV_ID_82598_BX: 198 case IXGBE_DEV_ID_82599_KR: 199 case IXGBE_DEV_ID_X550EM_X_KR: 200 case IXGBE_DEV_ID_X550EM_X_XFI: 201 ethtool_link_ksettings_add_link_mode 202 (cmd, advertising, 10000baseKR_Full); 203 break; 204 default: 205 ethtool_link_ksettings_add_link_mode 206 (cmd, advertising, 10000baseKX4_Full); 207 ethtool_link_ksettings_add_link_mode 208 (cmd, advertising, 10000baseKR_Full); 209 break; 210 } 211 } 212 213 static int ixgbe_get_link_ksettings(struct net_device *netdev, 214 struct ethtool_link_ksettings *cmd) 215 { 216 struct ixgbe_adapter *adapter = netdev_priv(netdev); 217 struct ixgbe_hw *hw = &adapter->hw; 218 ixgbe_link_speed supported_link; 219 bool autoneg = false; 220 221 ethtool_link_ksettings_zero_link_mode(cmd, supported); 222 ethtool_link_ksettings_zero_link_mode(cmd, advertising); 223 224 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 225 226 /* set the supported link speeds */ 227 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) { 228 ixgbe_set_supported_10gtypes(hw, cmd); 229 ixgbe_set_advertising_10gtypes(hw, cmd); 230 } 231 if (supported_link & IXGBE_LINK_SPEED_5GB_FULL) 232 ethtool_link_ksettings_add_link_mode(cmd, supported, 233 5000baseT_Full); 234 235 if (supported_link & IXGBE_LINK_SPEED_2_5GB_FULL) 236 ethtool_link_ksettings_add_link_mode(cmd, supported, 237 2500baseT_Full); 238 239 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) { 240 if (ixgbe_isbackplane(hw->phy.media_type)) { 241 ethtool_link_ksettings_add_link_mode(cmd, supported, 242 1000baseKX_Full); 243 ethtool_link_ksettings_add_link_mode(cmd, advertising, 244 1000baseKX_Full); 245 } else { 246 ethtool_link_ksettings_add_link_mode(cmd, supported, 247 1000baseT_Full); 248 ethtool_link_ksettings_add_link_mode(cmd, advertising, 249 1000baseT_Full); 250 } 251 } 252 if (supported_link & IXGBE_LINK_SPEED_100_FULL) { 253 ethtool_link_ksettings_add_link_mode(cmd, supported, 254 100baseT_Full); 255 ethtool_link_ksettings_add_link_mode(cmd, advertising, 256 100baseT_Full); 257 } 258 if (supported_link & IXGBE_LINK_SPEED_10_FULL) { 259 ethtool_link_ksettings_add_link_mode(cmd, supported, 260 10baseT_Full); 261 ethtool_link_ksettings_add_link_mode(cmd, advertising, 262 10baseT_Full); 263 } 264 265 /* set the advertised speeds */ 266 if (hw->phy.autoneg_advertised) { 267 ethtool_link_ksettings_zero_link_mode(cmd, advertising); 268 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) 269 ethtool_link_ksettings_add_link_mode(cmd, advertising, 270 10baseT_Full); 271 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 272 ethtool_link_ksettings_add_link_mode(cmd, advertising, 273 100baseT_Full); 274 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 275 ixgbe_set_advertising_10gtypes(hw, cmd); 276 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 277 if (ethtool_link_ksettings_test_link_mode 278 (cmd, supported, 1000baseKX_Full)) 279 ethtool_link_ksettings_add_link_mode 280 (cmd, advertising, 1000baseKX_Full); 281 else 282 ethtool_link_ksettings_add_link_mode 283 (cmd, advertising, 1000baseT_Full); 284 } 285 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) 286 ethtool_link_ksettings_add_link_mode(cmd, advertising, 287 5000baseT_Full); 288 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 289 ethtool_link_ksettings_add_link_mode(cmd, advertising, 290 2500baseT_Full); 291 } else { 292 if (hw->phy.multispeed_fiber && !autoneg) { 293 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 294 ethtool_link_ksettings_add_link_mode 295 (cmd, advertising, 10000baseT_Full); 296 } 297 } 298 299 if (autoneg) { 300 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 301 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 302 cmd->base.autoneg = AUTONEG_ENABLE; 303 } else 304 cmd->base.autoneg = AUTONEG_DISABLE; 305 306 /* Determine the remaining settings based on the PHY type. */ 307 switch (adapter->hw.phy.type) { 308 case ixgbe_phy_tn: 309 case ixgbe_phy_aq: 310 case ixgbe_phy_x550em_ext_t: 311 case ixgbe_phy_fw: 312 case ixgbe_phy_cu_unknown: 313 ethtool_link_ksettings_add_link_mode(cmd, supported, TP); 314 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP); 315 cmd->base.port = PORT_TP; 316 break; 317 case ixgbe_phy_qt: 318 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 319 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE); 320 cmd->base.port = PORT_FIBRE; 321 break; 322 case ixgbe_phy_nl: 323 case ixgbe_phy_sfp_passive_tyco: 324 case ixgbe_phy_sfp_passive_unknown: 325 case ixgbe_phy_sfp_ftl: 326 case ixgbe_phy_sfp_avago: 327 case ixgbe_phy_sfp_intel: 328 case ixgbe_phy_sfp_unknown: 329 case ixgbe_phy_qsfp_passive_unknown: 330 case ixgbe_phy_qsfp_active_unknown: 331 case ixgbe_phy_qsfp_intel: 332 case ixgbe_phy_qsfp_unknown: 333 /* SFP+ devices, further checking needed */ 334 switch (adapter->hw.phy.sfp_type) { 335 case ixgbe_sfp_type_da_cu: 336 case ixgbe_sfp_type_da_cu_core0: 337 case ixgbe_sfp_type_da_cu_core1: 338 ethtool_link_ksettings_add_link_mode(cmd, supported, 339 FIBRE); 340 ethtool_link_ksettings_add_link_mode(cmd, advertising, 341 FIBRE); 342 cmd->base.port = PORT_DA; 343 break; 344 case ixgbe_sfp_type_sr: 345 case ixgbe_sfp_type_lr: 346 case ixgbe_sfp_type_srlr_core0: 347 case ixgbe_sfp_type_srlr_core1: 348 case ixgbe_sfp_type_1g_sx_core0: 349 case ixgbe_sfp_type_1g_sx_core1: 350 case ixgbe_sfp_type_1g_lx_core0: 351 case ixgbe_sfp_type_1g_lx_core1: 352 ethtool_link_ksettings_add_link_mode(cmd, supported, 353 FIBRE); 354 ethtool_link_ksettings_add_link_mode(cmd, advertising, 355 FIBRE); 356 cmd->base.port = PORT_FIBRE; 357 break; 358 case ixgbe_sfp_type_not_present: 359 ethtool_link_ksettings_add_link_mode(cmd, supported, 360 FIBRE); 361 ethtool_link_ksettings_add_link_mode(cmd, advertising, 362 FIBRE); 363 cmd->base.port = PORT_NONE; 364 break; 365 case ixgbe_sfp_type_1g_cu_core0: 366 case ixgbe_sfp_type_1g_cu_core1: 367 ethtool_link_ksettings_add_link_mode(cmd, supported, 368 TP); 369 ethtool_link_ksettings_add_link_mode(cmd, advertising, 370 TP); 371 cmd->base.port = PORT_TP; 372 break; 373 case ixgbe_sfp_type_unknown: 374 default: 375 ethtool_link_ksettings_add_link_mode(cmd, supported, 376 FIBRE); 377 ethtool_link_ksettings_add_link_mode(cmd, advertising, 378 FIBRE); 379 cmd->base.port = PORT_OTHER; 380 break; 381 } 382 break; 383 case ixgbe_phy_xaui: 384 ethtool_link_ksettings_add_link_mode(cmd, supported, 385 FIBRE); 386 ethtool_link_ksettings_add_link_mode(cmd, advertising, 387 FIBRE); 388 cmd->base.port = PORT_NONE; 389 break; 390 case ixgbe_phy_unknown: 391 case ixgbe_phy_generic: 392 case ixgbe_phy_sfp_unsupported: 393 default: 394 ethtool_link_ksettings_add_link_mode(cmd, supported, 395 FIBRE); 396 ethtool_link_ksettings_add_link_mode(cmd, advertising, 397 FIBRE); 398 cmd->base.port = PORT_OTHER; 399 break; 400 } 401 402 /* Indicate pause support */ 403 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 404 405 switch (hw->fc.requested_mode) { 406 case ixgbe_fc_full: 407 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); 408 break; 409 case ixgbe_fc_rx_pause: 410 ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause); 411 ethtool_link_ksettings_add_link_mode(cmd, advertising, 412 Asym_Pause); 413 break; 414 case ixgbe_fc_tx_pause: 415 ethtool_link_ksettings_add_link_mode(cmd, advertising, 416 Asym_Pause); 417 break; 418 default: 419 ethtool_link_ksettings_del_link_mode(cmd, advertising, Pause); 420 ethtool_link_ksettings_del_link_mode(cmd, advertising, 421 Asym_Pause); 422 } 423 424 if (netif_carrier_ok(netdev)) { 425 switch (adapter->link_speed) { 426 case IXGBE_LINK_SPEED_10GB_FULL: 427 cmd->base.speed = SPEED_10000; 428 break; 429 case IXGBE_LINK_SPEED_5GB_FULL: 430 cmd->base.speed = SPEED_5000; 431 break; 432 case IXGBE_LINK_SPEED_2_5GB_FULL: 433 cmd->base.speed = SPEED_2500; 434 break; 435 case IXGBE_LINK_SPEED_1GB_FULL: 436 cmd->base.speed = SPEED_1000; 437 break; 438 case IXGBE_LINK_SPEED_100_FULL: 439 cmd->base.speed = SPEED_100; 440 break; 441 case IXGBE_LINK_SPEED_10_FULL: 442 cmd->base.speed = SPEED_10; 443 break; 444 default: 445 break; 446 } 447 cmd->base.duplex = DUPLEX_FULL; 448 } else { 449 cmd->base.speed = SPEED_UNKNOWN; 450 cmd->base.duplex = DUPLEX_UNKNOWN; 451 } 452 453 return 0; 454 } 455 456 static int ixgbe_set_link_ksettings(struct net_device *netdev, 457 const struct ethtool_link_ksettings *cmd) 458 { 459 struct ixgbe_adapter *adapter = netdev_priv(netdev); 460 struct ixgbe_hw *hw = &adapter->hw; 461 u32 advertised, old; 462 s32 err = 0; 463 464 if ((hw->phy.media_type == ixgbe_media_type_copper) || 465 (hw->phy.multispeed_fiber)) { 466 /* 467 * this function does not support duplex forcing, but can 468 * limit the advertising of the adapter to the specified speed 469 */ 470 if (!linkmode_subset(cmd->link_modes.advertising, 471 cmd->link_modes.supported)) 472 return -EINVAL; 473 474 /* only allow one speed at a time if no autoneg */ 475 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { 476 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 477 10000baseT_Full) && 478 ethtool_link_ksettings_test_link_mode(cmd, advertising, 479 1000baseT_Full)) 480 return -EINVAL; 481 } 482 483 old = hw->phy.autoneg_advertised; 484 advertised = 0; 485 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 486 10000baseT_Full)) 487 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 488 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 489 5000baseT_Full)) 490 advertised |= IXGBE_LINK_SPEED_5GB_FULL; 491 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 492 2500baseT_Full)) 493 advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 494 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 495 1000baseT_Full)) 496 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 497 498 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 499 100baseT_Full)) 500 advertised |= IXGBE_LINK_SPEED_100_FULL; 501 502 if (ethtool_link_ksettings_test_link_mode(cmd, advertising, 503 10baseT_Full)) 504 advertised |= IXGBE_LINK_SPEED_10_FULL; 505 506 if (old == advertised) 507 return err; 508 /* this sets the link speed and restarts auto-neg */ 509 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 510 usleep_range(1000, 2000); 511 512 hw->mac.autotry_restart = true; 513 err = hw->mac.ops.setup_link(hw, advertised, true); 514 if (err) { 515 e_info(probe, "setup link failed with code %d\n", err); 516 hw->mac.ops.setup_link(hw, old, true); 517 } 518 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 519 } else { 520 /* in this case we currently only support 10Gb/FULL */ 521 u32 speed = cmd->base.speed; 522 523 if ((cmd->base.autoneg == AUTONEG_ENABLE) || 524 (!ethtool_link_ksettings_test_link_mode(cmd, advertising, 525 10000baseT_Full)) || 526 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) 527 return -EINVAL; 528 } 529 530 return err; 531 } 532 533 static void ixgbe_get_pause_stats(struct net_device *netdev, 534 struct ethtool_pause_stats *stats) 535 { 536 struct ixgbe_adapter *adapter = netdev_priv(netdev); 537 struct ixgbe_hw_stats *hwstats = &adapter->stats; 538 539 stats->tx_pause_frames = hwstats->lxontxc + hwstats->lxofftxc; 540 stats->rx_pause_frames = hwstats->lxonrxc + hwstats->lxoffrxc; 541 } 542 543 static void ixgbe_get_pauseparam(struct net_device *netdev, 544 struct ethtool_pauseparam *pause) 545 { 546 struct ixgbe_adapter *adapter = netdev_priv(netdev); 547 struct ixgbe_hw *hw = &adapter->hw; 548 549 if (ixgbe_device_supports_autoneg_fc(hw) && 550 !hw->fc.disable_fc_autoneg) 551 pause->autoneg = 1; 552 else 553 pause->autoneg = 0; 554 555 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 556 pause->rx_pause = 1; 557 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 558 pause->tx_pause = 1; 559 } else if (hw->fc.current_mode == ixgbe_fc_full) { 560 pause->rx_pause = 1; 561 pause->tx_pause = 1; 562 } 563 } 564 565 static int ixgbe_set_pauseparam(struct net_device *netdev, 566 struct ethtool_pauseparam *pause) 567 { 568 struct ixgbe_adapter *adapter = netdev_priv(netdev); 569 struct ixgbe_hw *hw = &adapter->hw; 570 struct ixgbe_fc_info fc = hw->fc; 571 572 /* 82598 does no support link flow control with DCB enabled */ 573 if ((hw->mac.type == ixgbe_mac_82598EB) && 574 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 575 return -EINVAL; 576 577 /* some devices do not support autoneg of link flow control */ 578 if ((pause->autoneg == AUTONEG_ENABLE) && 579 !ixgbe_device_supports_autoneg_fc(hw)) 580 return -EINVAL; 581 582 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 583 584 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 585 fc.requested_mode = ixgbe_fc_full; 586 else if (pause->rx_pause && !pause->tx_pause) 587 fc.requested_mode = ixgbe_fc_rx_pause; 588 else if (!pause->rx_pause && pause->tx_pause) 589 fc.requested_mode = ixgbe_fc_tx_pause; 590 else 591 fc.requested_mode = ixgbe_fc_none; 592 593 /* if the thing changed then we'll update and use new autoneg */ 594 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 595 hw->fc = fc; 596 if (netif_running(netdev)) 597 ixgbe_reinit_locked(adapter); 598 else 599 ixgbe_reset(adapter); 600 } 601 602 return 0; 603 } 604 605 static u32 ixgbe_get_msglevel(struct net_device *netdev) 606 { 607 struct ixgbe_adapter *adapter = netdev_priv(netdev); 608 return adapter->msg_enable; 609 } 610 611 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 612 { 613 struct ixgbe_adapter *adapter = netdev_priv(netdev); 614 adapter->msg_enable = data; 615 } 616 617 static int ixgbe_get_regs_len(struct net_device *netdev) 618 { 619 #define IXGBE_REGS_LEN 1145 620 return IXGBE_REGS_LEN * sizeof(u32); 621 } 622 623 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 624 625 static void ixgbe_get_regs(struct net_device *netdev, 626 struct ethtool_regs *regs, void *p) 627 { 628 struct ixgbe_adapter *adapter = netdev_priv(netdev); 629 struct ixgbe_hw *hw = &adapter->hw; 630 u32 *regs_buff = p; 631 u8 i; 632 633 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 634 635 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 636 hw->device_id; 637 638 /* General Registers */ 639 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 640 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 641 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 642 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 643 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 644 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 645 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 646 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 647 648 /* NVM Register */ 649 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 650 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 651 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 652 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 653 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 654 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 655 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 656 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 657 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 658 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 659 660 /* Interrupt */ 661 /* don't read EICR because it can clear interrupt causes, instead 662 * read EICS which is a shadow but doesn't clear EICR */ 663 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 664 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 665 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 666 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 667 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 668 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 669 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 670 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 671 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 672 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 673 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 674 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 675 676 /* Flow Control */ 677 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 678 for (i = 0; i < 4; i++) 679 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i)); 680 for (i = 0; i < 8; i++) { 681 switch (hw->mac.type) { 682 case ixgbe_mac_82598EB: 683 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 684 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 685 break; 686 case ixgbe_mac_82599EB: 687 case ixgbe_mac_X540: 688 case ixgbe_mac_X550: 689 case ixgbe_mac_X550EM_x: 690 case ixgbe_mac_x550em_a: 691 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 692 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 693 break; 694 default: 695 break; 696 } 697 } 698 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 699 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 700 701 /* Receive DMA */ 702 for (i = 0; i < 64; i++) 703 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 704 for (i = 0; i < 64; i++) 705 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 706 for (i = 0; i < 64; i++) 707 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 708 for (i = 0; i < 64; i++) 709 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 710 for (i = 0; i < 64; i++) 711 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 712 for (i = 0; i < 64; i++) 713 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 714 for (i = 0; i < 16; i++) 715 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 716 for (i = 0; i < 16; i++) 717 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 718 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 719 for (i = 0; i < 8; i++) 720 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 721 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 722 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 723 724 /* Receive */ 725 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 726 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 727 for (i = 0; i < 16; i++) 728 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 729 for (i = 0; i < 16; i++) 730 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 731 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 732 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 733 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 734 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 735 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 736 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 737 for (i = 0; i < 8; i++) 738 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 739 for (i = 0; i < 8; i++) 740 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 741 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 742 743 /* Transmit */ 744 for (i = 0; i < 32; i++) 745 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 746 for (i = 0; i < 32; i++) 747 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 748 for (i = 0; i < 32; i++) 749 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 750 for (i = 0; i < 32; i++) 751 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 752 for (i = 0; i < 32; i++) 753 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 754 for (i = 0; i < 32; i++) 755 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 756 for (i = 0; i < 32; i++) 757 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 758 for (i = 0; i < 32; i++) 759 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 760 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 761 for (i = 0; i < 16; i++) 762 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 763 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 764 for (i = 0; i < 8; i++) 765 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 766 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 767 768 /* Wake Up */ 769 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 770 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 771 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 772 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 773 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 774 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 775 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 776 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 777 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 778 779 /* DCB */ 780 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 781 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 782 783 switch (hw->mac.type) { 784 case ixgbe_mac_82598EB: 785 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 786 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 787 for (i = 0; i < 8; i++) 788 regs_buff[833 + i] = 789 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 790 for (i = 0; i < 8; i++) 791 regs_buff[841 + i] = 792 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 793 for (i = 0; i < 8; i++) 794 regs_buff[849 + i] = 795 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 796 for (i = 0; i < 8; i++) 797 regs_buff[857 + i] = 798 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 799 break; 800 case ixgbe_mac_82599EB: 801 case ixgbe_mac_X540: 802 case ixgbe_mac_X550: 803 case ixgbe_mac_X550EM_x: 804 case ixgbe_mac_x550em_a: 805 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 806 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 807 for (i = 0; i < 8; i++) 808 regs_buff[833 + i] = 809 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 810 for (i = 0; i < 8; i++) 811 regs_buff[841 + i] = 812 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 813 for (i = 0; i < 8; i++) 814 regs_buff[849 + i] = 815 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 816 for (i = 0; i < 8; i++) 817 regs_buff[857 + i] = 818 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 819 break; 820 default: 821 break; 822 } 823 824 for (i = 0; i < 8; i++) 825 regs_buff[865 + i] = 826 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 827 for (i = 0; i < 8; i++) 828 regs_buff[873 + i] = 829 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 830 831 /* Statistics */ 832 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 833 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 834 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 835 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 836 for (i = 0; i < 8; i++) 837 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 838 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 839 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 840 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 841 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 842 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 843 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 844 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 845 for (i = 0; i < 8; i++) 846 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 847 for (i = 0; i < 8; i++) 848 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 849 for (i = 0; i < 8; i++) 850 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 851 for (i = 0; i < 8; i++) 852 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 853 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 854 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 855 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 856 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 857 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 858 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 859 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 860 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 861 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 862 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 863 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc); 864 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32); 865 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc); 866 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32); 867 for (i = 0; i < 8; i++) 868 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 869 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 870 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 871 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 872 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 873 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 874 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 875 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 876 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor); 877 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32); 878 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 879 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 880 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 881 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 882 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 883 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 884 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 885 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 886 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 887 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 888 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 889 for (i = 0; i < 16; i++) 890 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 891 for (i = 0; i < 16; i++) 892 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 893 for (i = 0; i < 16; i++) 894 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 895 for (i = 0; i < 16; i++) 896 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 897 898 /* MAC */ 899 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 900 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 901 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 902 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 903 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 904 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 905 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 906 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 907 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 908 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 909 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 910 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 911 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 912 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 913 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 914 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 915 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 916 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 917 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 918 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 919 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 920 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 921 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 922 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 923 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 924 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 925 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 926 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 927 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 928 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 929 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 930 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 931 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 932 933 /* Diagnostic */ 934 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 935 for (i = 0; i < 8; i++) 936 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 937 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 938 for (i = 0; i < 4; i++) 939 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 940 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 941 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 942 for (i = 0; i < 8; i++) 943 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 944 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 945 for (i = 0; i < 4; i++) 946 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 947 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 948 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 949 for (i = 0; i < 4; i++) 950 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i)); 951 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 952 for (i = 0; i < 4; i++) 953 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i)); 954 for (i = 0; i < 8; i++) 955 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 956 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 957 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 958 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 959 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 960 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 961 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 962 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 963 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 964 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 965 966 /* 82599 X540 specific registers */ 967 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 968 969 /* 82599 X540 specific DCB registers */ 970 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 971 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 972 for (i = 0; i < 4; i++) 973 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 974 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 975 /* same as RTTQCNRM */ 976 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 977 /* same as RTTQCNRR */ 978 979 /* X540 specific DCB registers */ 980 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 981 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 982 983 /* Security config registers */ 984 regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 985 regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 986 regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF); 987 regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 988 regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 989 regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 990 } 991 992 static int ixgbe_get_eeprom_len(struct net_device *netdev) 993 { 994 struct ixgbe_adapter *adapter = netdev_priv(netdev); 995 return adapter->hw.eeprom.word_size * 2; 996 } 997 998 static int ixgbe_get_eeprom(struct net_device *netdev, 999 struct ethtool_eeprom *eeprom, u8 *bytes) 1000 { 1001 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1002 struct ixgbe_hw *hw = &adapter->hw; 1003 u16 *eeprom_buff; 1004 int first_word, last_word, eeprom_len; 1005 int ret_val = 0; 1006 u16 i; 1007 1008 if (eeprom->len == 0) 1009 return -EINVAL; 1010 1011 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 1012 1013 first_word = eeprom->offset >> 1; 1014 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 1015 eeprom_len = last_word - first_word + 1; 1016 1017 eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL); 1018 if (!eeprom_buff) 1019 return -ENOMEM; 1020 1021 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 1022 eeprom_buff); 1023 1024 /* Device's eeprom is always little-endian, word addressable */ 1025 for (i = 0; i < eeprom_len; i++) 1026 le16_to_cpus(&eeprom_buff[i]); 1027 1028 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 1029 kfree(eeprom_buff); 1030 1031 return ret_val; 1032 } 1033 1034 static int ixgbe_set_eeprom(struct net_device *netdev, 1035 struct ethtool_eeprom *eeprom, u8 *bytes) 1036 { 1037 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1038 struct ixgbe_hw *hw = &adapter->hw; 1039 u16 *eeprom_buff; 1040 void *ptr; 1041 int max_len, first_word, last_word, ret_val = 0; 1042 u16 i; 1043 1044 if (eeprom->len == 0) 1045 return -EINVAL; 1046 1047 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 1048 return -EINVAL; 1049 1050 max_len = hw->eeprom.word_size * 2; 1051 1052 first_word = eeprom->offset >> 1; 1053 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 1054 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 1055 if (!eeprom_buff) 1056 return -ENOMEM; 1057 1058 ptr = eeprom_buff; 1059 1060 if (eeprom->offset & 1) { 1061 /* 1062 * need read/modify/write of first changed EEPROM word 1063 * only the second byte of the word is being modified 1064 */ 1065 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 1066 if (ret_val) 1067 goto err; 1068 1069 ptr++; 1070 } 1071 if ((eeprom->offset + eeprom->len) & 1) { 1072 /* 1073 * need read/modify/write of last changed EEPROM word 1074 * only the first byte of the word is being modified 1075 */ 1076 ret_val = hw->eeprom.ops.read(hw, last_word, 1077 &eeprom_buff[last_word - first_word]); 1078 if (ret_val) 1079 goto err; 1080 } 1081 1082 /* Device's eeprom is always little-endian, word addressable */ 1083 for (i = 0; i < last_word - first_word + 1; i++) 1084 le16_to_cpus(&eeprom_buff[i]); 1085 1086 memcpy(ptr, bytes, eeprom->len); 1087 1088 for (i = 0; i < last_word - first_word + 1; i++) 1089 cpu_to_le16s(&eeprom_buff[i]); 1090 1091 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 1092 last_word - first_word + 1, 1093 eeprom_buff); 1094 1095 /* Update the checksum */ 1096 if (ret_val == 0) 1097 hw->eeprom.ops.update_checksum(hw); 1098 1099 err: 1100 kfree(eeprom_buff); 1101 return ret_val; 1102 } 1103 1104 static void ixgbe_get_drvinfo(struct net_device *netdev, 1105 struct ethtool_drvinfo *drvinfo) 1106 { 1107 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1108 1109 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 1110 1111 strlcpy(drvinfo->fw_version, adapter->eeprom_id, 1112 sizeof(drvinfo->fw_version)); 1113 1114 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 1115 sizeof(drvinfo->bus_info)); 1116 1117 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN; 1118 } 1119 1120 static void ixgbe_get_ringparam(struct net_device *netdev, 1121 struct ethtool_ringparam *ring) 1122 { 1123 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1124 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 1125 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 1126 1127 ring->rx_max_pending = IXGBE_MAX_RXD; 1128 ring->tx_max_pending = IXGBE_MAX_TXD; 1129 ring->rx_pending = rx_ring->count; 1130 ring->tx_pending = tx_ring->count; 1131 } 1132 1133 static int ixgbe_set_ringparam(struct net_device *netdev, 1134 struct ethtool_ringparam *ring) 1135 { 1136 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1137 struct ixgbe_ring *temp_ring; 1138 int i, j, err = 0; 1139 u32 new_rx_count, new_tx_count; 1140 1141 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 1142 return -EINVAL; 1143 1144 new_tx_count = clamp_t(u32, ring->tx_pending, 1145 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 1146 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 1147 1148 new_rx_count = clamp_t(u32, ring->rx_pending, 1149 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 1150 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 1151 1152 if ((new_tx_count == adapter->tx_ring_count) && 1153 (new_rx_count == adapter->rx_ring_count)) { 1154 /* nothing to do */ 1155 return 0; 1156 } 1157 1158 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 1159 usleep_range(1000, 2000); 1160 1161 if (!netif_running(adapter->netdev)) { 1162 for (i = 0; i < adapter->num_tx_queues; i++) 1163 adapter->tx_ring[i]->count = new_tx_count; 1164 for (i = 0; i < adapter->num_xdp_queues; i++) 1165 adapter->xdp_ring[i]->count = new_tx_count; 1166 for (i = 0; i < adapter->num_rx_queues; i++) 1167 adapter->rx_ring[i]->count = new_rx_count; 1168 adapter->tx_ring_count = new_tx_count; 1169 adapter->xdp_ring_count = new_tx_count; 1170 adapter->rx_ring_count = new_rx_count; 1171 goto clear_reset; 1172 } 1173 1174 /* allocate temporary buffer to store rings in */ 1175 i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues, 1176 adapter->num_rx_queues); 1177 temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring))); 1178 1179 if (!temp_ring) { 1180 err = -ENOMEM; 1181 goto clear_reset; 1182 } 1183 1184 ixgbe_down(adapter); 1185 1186 /* 1187 * Setup new Tx resources and free the old Tx resources in that order. 1188 * We can then assign the new resources to the rings via a memcpy. 1189 * The advantage to this approach is that we are guaranteed to still 1190 * have resources even in the case of an allocation failure. 1191 */ 1192 if (new_tx_count != adapter->tx_ring_count) { 1193 for (i = 0; i < adapter->num_tx_queues; i++) { 1194 memcpy(&temp_ring[i], adapter->tx_ring[i], 1195 sizeof(struct ixgbe_ring)); 1196 1197 temp_ring[i].count = new_tx_count; 1198 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1199 if (err) { 1200 while (i) { 1201 i--; 1202 ixgbe_free_tx_resources(&temp_ring[i]); 1203 } 1204 goto err_setup; 1205 } 1206 } 1207 1208 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1209 memcpy(&temp_ring[i], adapter->xdp_ring[j], 1210 sizeof(struct ixgbe_ring)); 1211 1212 temp_ring[i].count = new_tx_count; 1213 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1214 if (err) { 1215 while (i) { 1216 i--; 1217 ixgbe_free_tx_resources(&temp_ring[i]); 1218 } 1219 goto err_setup; 1220 } 1221 } 1222 1223 for (i = 0; i < adapter->num_tx_queues; i++) { 1224 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1225 1226 memcpy(adapter->tx_ring[i], &temp_ring[i], 1227 sizeof(struct ixgbe_ring)); 1228 } 1229 for (j = 0; j < adapter->num_xdp_queues; j++, i++) { 1230 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 1231 1232 memcpy(adapter->xdp_ring[j], &temp_ring[i], 1233 sizeof(struct ixgbe_ring)); 1234 } 1235 1236 adapter->tx_ring_count = new_tx_count; 1237 } 1238 1239 /* Repeat the process for the Rx rings if needed */ 1240 if (new_rx_count != adapter->rx_ring_count) { 1241 for (i = 0; i < adapter->num_rx_queues; i++) { 1242 memcpy(&temp_ring[i], adapter->rx_ring[i], 1243 sizeof(struct ixgbe_ring)); 1244 1245 /* Clear copied XDP RX-queue info */ 1246 memset(&temp_ring[i].xdp_rxq, 0, 1247 sizeof(temp_ring[i].xdp_rxq)); 1248 1249 temp_ring[i].count = new_rx_count; 1250 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]); 1251 if (err) { 1252 while (i) { 1253 i--; 1254 ixgbe_free_rx_resources(&temp_ring[i]); 1255 } 1256 goto err_setup; 1257 } 1258 1259 } 1260 1261 for (i = 0; i < adapter->num_rx_queues; i++) { 1262 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1263 1264 memcpy(adapter->rx_ring[i], &temp_ring[i], 1265 sizeof(struct ixgbe_ring)); 1266 } 1267 1268 adapter->rx_ring_count = new_rx_count; 1269 } 1270 1271 err_setup: 1272 ixgbe_up(adapter); 1273 vfree(temp_ring); 1274 clear_reset: 1275 clear_bit(__IXGBE_RESETTING, &adapter->state); 1276 return err; 1277 } 1278 1279 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1280 { 1281 switch (sset) { 1282 case ETH_SS_TEST: 1283 return IXGBE_TEST_LEN; 1284 case ETH_SS_STATS: 1285 return IXGBE_STATS_LEN; 1286 case ETH_SS_PRIV_FLAGS: 1287 return IXGBE_PRIV_FLAGS_STR_LEN; 1288 default: 1289 return -EOPNOTSUPP; 1290 } 1291 } 1292 1293 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1294 struct ethtool_stats *stats, u64 *data) 1295 { 1296 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1297 struct rtnl_link_stats64 temp; 1298 const struct rtnl_link_stats64 *net_stats; 1299 unsigned int start; 1300 struct ixgbe_ring *ring; 1301 int i, j; 1302 char *p = NULL; 1303 1304 ixgbe_update_stats(adapter); 1305 net_stats = dev_get_stats(netdev, &temp); 1306 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1307 switch (ixgbe_gstrings_stats[i].type) { 1308 case NETDEV_STATS: 1309 p = (char *) net_stats + 1310 ixgbe_gstrings_stats[i].stat_offset; 1311 break; 1312 case IXGBE_STATS: 1313 p = (char *) adapter + 1314 ixgbe_gstrings_stats[i].stat_offset; 1315 break; 1316 default: 1317 data[i] = 0; 1318 continue; 1319 } 1320 1321 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1322 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1323 } 1324 for (j = 0; j < netdev->num_tx_queues; j++) { 1325 ring = adapter->tx_ring[j]; 1326 if (!ring) { 1327 data[i] = 0; 1328 data[i+1] = 0; 1329 i += 2; 1330 continue; 1331 } 1332 1333 do { 1334 start = u64_stats_fetch_begin_irq(&ring->syncp); 1335 data[i] = ring->stats.packets; 1336 data[i+1] = ring->stats.bytes; 1337 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1338 i += 2; 1339 } 1340 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1341 ring = adapter->rx_ring[j]; 1342 if (!ring) { 1343 data[i] = 0; 1344 data[i+1] = 0; 1345 i += 2; 1346 continue; 1347 } 1348 1349 do { 1350 start = u64_stats_fetch_begin_irq(&ring->syncp); 1351 data[i] = ring->stats.packets; 1352 data[i+1] = ring->stats.bytes; 1353 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1354 i += 2; 1355 } 1356 1357 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1358 data[i++] = adapter->stats.pxontxc[j]; 1359 data[i++] = adapter->stats.pxofftxc[j]; 1360 } 1361 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1362 data[i++] = adapter->stats.pxonrxc[j]; 1363 data[i++] = adapter->stats.pxoffrxc[j]; 1364 } 1365 } 1366 1367 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1368 u8 *data) 1369 { 1370 unsigned int i; 1371 u8 *p = data; 1372 1373 switch (stringset) { 1374 case ETH_SS_TEST: 1375 for (i = 0; i < IXGBE_TEST_LEN; i++) 1376 ethtool_sprintf(&p, ixgbe_gstrings_test[i]); 1377 break; 1378 case ETH_SS_STATS: 1379 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) 1380 ethtool_sprintf(&p, 1381 ixgbe_gstrings_stats[i].stat_string); 1382 for (i = 0; i < netdev->num_tx_queues; i++) { 1383 ethtool_sprintf(&p, "tx_queue_%u_packets", i); 1384 ethtool_sprintf(&p, "tx_queue_%u_bytes", i); 1385 } 1386 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1387 ethtool_sprintf(&p, "rx_queue_%u_packets", i); 1388 ethtool_sprintf(&p, "rx_queue_%u_bytes", i); 1389 } 1390 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1391 ethtool_sprintf(&p, "tx_pb_%u_pxon", i); 1392 ethtool_sprintf(&p, "tx_pb_%u_pxoff", i); 1393 } 1394 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1395 ethtool_sprintf(&p, "rx_pb_%u_pxon", i); 1396 ethtool_sprintf(&p, "rx_pb_%u_pxoff", i); 1397 } 1398 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1399 break; 1400 case ETH_SS_PRIV_FLAGS: 1401 memcpy(data, ixgbe_priv_flags_strings, 1402 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 1403 } 1404 } 1405 1406 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1407 { 1408 struct ixgbe_hw *hw = &adapter->hw; 1409 bool link_up; 1410 u32 link_speed = 0; 1411 1412 if (ixgbe_removed(hw->hw_addr)) { 1413 *data = 1; 1414 return 1; 1415 } 1416 *data = 0; 1417 1418 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1419 if (link_up) 1420 return *data; 1421 else 1422 *data = 1; 1423 return *data; 1424 } 1425 1426 /* ethtool register test data */ 1427 struct ixgbe_reg_test { 1428 u16 reg; 1429 u8 array_len; 1430 u8 test_type; 1431 u32 mask; 1432 u32 write; 1433 }; 1434 1435 /* In the hardware, registers are laid out either singly, in arrays 1436 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1437 * most tests take place on arrays or single registers (handled 1438 * as a single-element array) and special-case the tables. 1439 * Table tests are always pattern tests. 1440 * 1441 * We also make provision for some required setup steps by specifying 1442 * registers to be written without any read-back testing. 1443 */ 1444 1445 #define PATTERN_TEST 1 1446 #define SET_READ_TEST 2 1447 #define WRITE_NO_TEST 3 1448 #define TABLE32_TEST 4 1449 #define TABLE64_TEST_LO 5 1450 #define TABLE64_TEST_HI 6 1451 1452 /* default 82599 register test */ 1453 static const struct ixgbe_reg_test reg_test_82599[] = { 1454 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1455 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1456 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1457 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1458 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1459 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1460 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1461 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1462 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1463 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1464 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1465 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1466 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1467 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1468 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1469 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1470 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1471 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1472 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1473 { .reg = 0 } 1474 }; 1475 1476 /* default 82598 register test */ 1477 static const struct ixgbe_reg_test reg_test_82598[] = { 1478 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1479 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1480 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1481 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1482 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1483 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1484 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1485 /* Enable all four RX queues before testing. */ 1486 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1487 /* RDH is read-only for 82598, only test RDT. */ 1488 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1489 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1490 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1491 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1492 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1493 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1494 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1495 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1496 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1497 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1498 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1499 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1500 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1501 { .reg = 0 } 1502 }; 1503 1504 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1505 u32 mask, u32 write) 1506 { 1507 u32 pat, val, before; 1508 static const u32 test_pattern[] = { 1509 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1510 1511 if (ixgbe_removed(adapter->hw.hw_addr)) { 1512 *data = 1; 1513 return true; 1514 } 1515 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1516 before = ixgbe_read_reg(&adapter->hw, reg); 1517 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1518 val = ixgbe_read_reg(&adapter->hw, reg); 1519 if (val != (test_pattern[pat] & write & mask)) { 1520 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1521 reg, val, (test_pattern[pat] & write & mask)); 1522 *data = reg; 1523 ixgbe_write_reg(&adapter->hw, reg, before); 1524 return true; 1525 } 1526 ixgbe_write_reg(&adapter->hw, reg, before); 1527 } 1528 return false; 1529 } 1530 1531 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1532 u32 mask, u32 write) 1533 { 1534 u32 val, before; 1535 1536 if (ixgbe_removed(adapter->hw.hw_addr)) { 1537 *data = 1; 1538 return true; 1539 } 1540 before = ixgbe_read_reg(&adapter->hw, reg); 1541 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1542 val = ixgbe_read_reg(&adapter->hw, reg); 1543 if ((write & mask) != (val & mask)) { 1544 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1545 reg, (val & mask), (write & mask)); 1546 *data = reg; 1547 ixgbe_write_reg(&adapter->hw, reg, before); 1548 return true; 1549 } 1550 ixgbe_write_reg(&adapter->hw, reg, before); 1551 return false; 1552 } 1553 1554 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1555 { 1556 const struct ixgbe_reg_test *test; 1557 u32 value, before, after; 1558 u32 i, toggle; 1559 1560 if (ixgbe_removed(adapter->hw.hw_addr)) { 1561 e_err(drv, "Adapter removed - register test blocked\n"); 1562 *data = 1; 1563 return 1; 1564 } 1565 switch (adapter->hw.mac.type) { 1566 case ixgbe_mac_82598EB: 1567 toggle = 0x7FFFF3FF; 1568 test = reg_test_82598; 1569 break; 1570 case ixgbe_mac_82599EB: 1571 case ixgbe_mac_X540: 1572 case ixgbe_mac_X550: 1573 case ixgbe_mac_X550EM_x: 1574 case ixgbe_mac_x550em_a: 1575 toggle = 0x7FFFF30F; 1576 test = reg_test_82599; 1577 break; 1578 default: 1579 *data = 1; 1580 return 1; 1581 } 1582 1583 /* 1584 * Because the status register is such a special case, 1585 * we handle it separately from the rest of the register 1586 * tests. Some bits are read-only, some toggle, and some 1587 * are writeable on newer MACs. 1588 */ 1589 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1590 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1591 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1592 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1593 if (value != after) { 1594 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1595 after, value); 1596 *data = 1; 1597 return 1; 1598 } 1599 /* restore previous status */ 1600 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1601 1602 /* 1603 * Perform the remainder of the register test, looping through 1604 * the test table until we either fail or reach the null entry. 1605 */ 1606 while (test->reg) { 1607 for (i = 0; i < test->array_len; i++) { 1608 bool b = false; 1609 1610 switch (test->test_type) { 1611 case PATTERN_TEST: 1612 b = reg_pattern_test(adapter, data, 1613 test->reg + (i * 0x40), 1614 test->mask, 1615 test->write); 1616 break; 1617 case SET_READ_TEST: 1618 b = reg_set_and_check(adapter, data, 1619 test->reg + (i * 0x40), 1620 test->mask, 1621 test->write); 1622 break; 1623 case WRITE_NO_TEST: 1624 ixgbe_write_reg(&adapter->hw, 1625 test->reg + (i * 0x40), 1626 test->write); 1627 break; 1628 case TABLE32_TEST: 1629 b = reg_pattern_test(adapter, data, 1630 test->reg + (i * 4), 1631 test->mask, 1632 test->write); 1633 break; 1634 case TABLE64_TEST_LO: 1635 b = reg_pattern_test(adapter, data, 1636 test->reg + (i * 8), 1637 test->mask, 1638 test->write); 1639 break; 1640 case TABLE64_TEST_HI: 1641 b = reg_pattern_test(adapter, data, 1642 (test->reg + 4) + (i * 8), 1643 test->mask, 1644 test->write); 1645 break; 1646 } 1647 if (b) 1648 return 1; 1649 } 1650 test++; 1651 } 1652 1653 *data = 0; 1654 return 0; 1655 } 1656 1657 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1658 { 1659 struct ixgbe_hw *hw = &adapter->hw; 1660 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1661 *data = 1; 1662 else 1663 *data = 0; 1664 return *data; 1665 } 1666 1667 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1668 { 1669 struct net_device *netdev = (struct net_device *) data; 1670 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1671 1672 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1673 1674 return IRQ_HANDLED; 1675 } 1676 1677 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1678 { 1679 struct net_device *netdev = adapter->netdev; 1680 u32 mask, i = 0, shared_int = true; 1681 u32 irq = adapter->pdev->irq; 1682 1683 *data = 0; 1684 1685 /* Hook up test interrupt handler just for this test */ 1686 if (adapter->msix_entries) { 1687 /* NOTE: we don't test MSI-X interrupts here, yet */ 1688 return 0; 1689 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1690 shared_int = false; 1691 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1692 netdev)) { 1693 *data = 1; 1694 return -1; 1695 } 1696 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1697 netdev->name, netdev)) { 1698 shared_int = false; 1699 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1700 netdev->name, netdev)) { 1701 *data = 1; 1702 return -1; 1703 } 1704 e_info(hw, "testing %s interrupt\n", shared_int ? 1705 "shared" : "unshared"); 1706 1707 /* Disable all the interrupts */ 1708 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1709 IXGBE_WRITE_FLUSH(&adapter->hw); 1710 usleep_range(10000, 20000); 1711 1712 /* Test each interrupt */ 1713 for (; i < 10; i++) { 1714 /* Interrupt to test */ 1715 mask = BIT(i); 1716 1717 if (!shared_int) { 1718 /* 1719 * Disable the interrupts to be reported in 1720 * the cause register and then force the same 1721 * interrupt and see if one gets posted. If 1722 * an interrupt was posted to the bus, the 1723 * test failed. 1724 */ 1725 adapter->test_icr = 0; 1726 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1727 ~mask & 0x00007FFF); 1728 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1729 ~mask & 0x00007FFF); 1730 IXGBE_WRITE_FLUSH(&adapter->hw); 1731 usleep_range(10000, 20000); 1732 1733 if (adapter->test_icr & mask) { 1734 *data = 3; 1735 break; 1736 } 1737 } 1738 1739 /* 1740 * Enable the interrupt to be reported in the cause 1741 * register and then force the same interrupt and see 1742 * if one gets posted. If an interrupt was not posted 1743 * to the bus, the test failed. 1744 */ 1745 adapter->test_icr = 0; 1746 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1747 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1748 IXGBE_WRITE_FLUSH(&adapter->hw); 1749 usleep_range(10000, 20000); 1750 1751 if (!(adapter->test_icr & mask)) { 1752 *data = 4; 1753 break; 1754 } 1755 1756 if (!shared_int) { 1757 /* 1758 * Disable the other interrupts to be reported in 1759 * the cause register and then force the other 1760 * interrupts and see if any get posted. If 1761 * an interrupt was posted to the bus, the 1762 * test failed. 1763 */ 1764 adapter->test_icr = 0; 1765 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1766 ~mask & 0x00007FFF); 1767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1768 ~mask & 0x00007FFF); 1769 IXGBE_WRITE_FLUSH(&adapter->hw); 1770 usleep_range(10000, 20000); 1771 1772 if (adapter->test_icr) { 1773 *data = 5; 1774 break; 1775 } 1776 } 1777 } 1778 1779 /* Disable all the interrupts */ 1780 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1781 IXGBE_WRITE_FLUSH(&adapter->hw); 1782 usleep_range(10000, 20000); 1783 1784 /* Unhook test interrupt handler */ 1785 free_irq(irq, netdev); 1786 1787 return *data; 1788 } 1789 1790 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1791 { 1792 /* Shut down the DMA engines now so they can be reinitialized later, 1793 * since the test rings and normally used rings should overlap on 1794 * queue 0 we can just use the standard disable Rx/Tx calls and they 1795 * will take care of disabling the test rings for us. 1796 */ 1797 1798 /* first Rx */ 1799 ixgbe_disable_rx(adapter); 1800 1801 /* now Tx */ 1802 ixgbe_disable_tx(adapter); 1803 1804 ixgbe_reset(adapter); 1805 1806 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1807 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1808 } 1809 1810 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1811 { 1812 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1813 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1814 struct ixgbe_hw *hw = &adapter->hw; 1815 u32 rctl, reg_data; 1816 int ret_val; 1817 int err; 1818 1819 /* Setup Tx descriptor ring and Tx buffers */ 1820 tx_ring->count = IXGBE_DEFAULT_TXD; 1821 tx_ring->queue_index = 0; 1822 tx_ring->dev = &adapter->pdev->dev; 1823 tx_ring->netdev = adapter->netdev; 1824 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1825 1826 err = ixgbe_setup_tx_resources(tx_ring); 1827 if (err) 1828 return 1; 1829 1830 switch (adapter->hw.mac.type) { 1831 case ixgbe_mac_82599EB: 1832 case ixgbe_mac_X540: 1833 case ixgbe_mac_X550: 1834 case ixgbe_mac_X550EM_x: 1835 case ixgbe_mac_x550em_a: 1836 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1837 reg_data |= IXGBE_DMATXCTL_TE; 1838 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1839 break; 1840 default: 1841 break; 1842 } 1843 1844 ixgbe_configure_tx_ring(adapter, tx_ring); 1845 1846 /* Setup Rx Descriptor ring and Rx buffers */ 1847 rx_ring->count = IXGBE_DEFAULT_RXD; 1848 rx_ring->queue_index = 0; 1849 rx_ring->dev = &adapter->pdev->dev; 1850 rx_ring->netdev = adapter->netdev; 1851 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1852 1853 err = ixgbe_setup_rx_resources(adapter, rx_ring); 1854 if (err) { 1855 ret_val = 4; 1856 goto err_nomem; 1857 } 1858 1859 hw->mac.ops.disable_rx(hw); 1860 1861 ixgbe_configure_rx_ring(adapter, rx_ring); 1862 1863 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1864 rctl |= IXGBE_RXCTRL_DMBYPS; 1865 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1866 1867 hw->mac.ops.enable_rx(hw); 1868 1869 return 0; 1870 1871 err_nomem: 1872 ixgbe_free_desc_rings(adapter); 1873 return ret_val; 1874 } 1875 1876 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1877 { 1878 struct ixgbe_hw *hw = &adapter->hw; 1879 u32 reg_data; 1880 1881 1882 /* Setup MAC loopback */ 1883 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1884 reg_data |= IXGBE_HLREG0_LPBK; 1885 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1886 1887 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1888 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1889 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1890 1891 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1892 switch (adapter->hw.mac.type) { 1893 case ixgbe_mac_X540: 1894 case ixgbe_mac_X550: 1895 case ixgbe_mac_X550EM_x: 1896 case ixgbe_mac_x550em_a: 1897 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1898 reg_data |= IXGBE_MACC_FLU; 1899 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1900 break; 1901 default: 1902 if (hw->mac.orig_autoc) { 1903 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1904 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1905 } else { 1906 return 10; 1907 } 1908 } 1909 IXGBE_WRITE_FLUSH(hw); 1910 usleep_range(10000, 20000); 1911 1912 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1913 if (hw->mac.type == ixgbe_mac_82598EB) { 1914 u8 atlas; 1915 1916 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1917 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1918 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1919 1920 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1921 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1922 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1923 1924 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1925 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1926 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1927 1928 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1929 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1930 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1931 } 1932 1933 return 0; 1934 } 1935 1936 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1937 { 1938 u32 reg_data; 1939 1940 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1941 reg_data &= ~IXGBE_HLREG0_LPBK; 1942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1943 } 1944 1945 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1946 unsigned int frame_size) 1947 { 1948 memset(skb->data, 0xFF, frame_size); 1949 frame_size >>= 1; 1950 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1951 skb->data[frame_size + 10] = 0xBE; 1952 skb->data[frame_size + 12] = 0xAF; 1953 } 1954 1955 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1956 unsigned int frame_size) 1957 { 1958 unsigned char *data; 1959 bool match = true; 1960 1961 frame_size >>= 1; 1962 1963 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1964 1965 if (data[3] != 0xFF || 1966 data[frame_size + 10] != 0xBE || 1967 data[frame_size + 12] != 0xAF) 1968 match = false; 1969 1970 kunmap(rx_buffer->page); 1971 1972 return match; 1973 } 1974 1975 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1976 struct ixgbe_ring *tx_ring, 1977 unsigned int size) 1978 { 1979 union ixgbe_adv_rx_desc *rx_desc; 1980 u16 rx_ntc, tx_ntc, count = 0; 1981 1982 /* initialize next to clean and descriptor values */ 1983 rx_ntc = rx_ring->next_to_clean; 1984 tx_ntc = tx_ring->next_to_clean; 1985 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1986 1987 while (tx_ntc != tx_ring->next_to_use) { 1988 union ixgbe_adv_tx_desc *tx_desc; 1989 struct ixgbe_tx_buffer *tx_buffer; 1990 1991 tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc); 1992 1993 /* if DD is not set transmit has not completed */ 1994 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1995 return count; 1996 1997 /* unmap buffer on Tx side */ 1998 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1999 2000 /* Free all the Tx ring sk_buffs */ 2001 dev_kfree_skb_any(tx_buffer->skb); 2002 2003 /* unmap skb header data */ 2004 dma_unmap_single(tx_ring->dev, 2005 dma_unmap_addr(tx_buffer, dma), 2006 dma_unmap_len(tx_buffer, len), 2007 DMA_TO_DEVICE); 2008 dma_unmap_len_set(tx_buffer, len, 0); 2009 2010 /* increment Tx next to clean counter */ 2011 tx_ntc++; 2012 if (tx_ntc == tx_ring->count) 2013 tx_ntc = 0; 2014 } 2015 2016 while (rx_desc->wb.upper.length) { 2017 struct ixgbe_rx_buffer *rx_buffer; 2018 2019 /* check Rx buffer */ 2020 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 2021 2022 /* sync Rx buffer for CPU read */ 2023 dma_sync_single_for_cpu(rx_ring->dev, 2024 rx_buffer->dma, 2025 ixgbe_rx_bufsz(rx_ring), 2026 DMA_FROM_DEVICE); 2027 2028 /* verify contents of skb */ 2029 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 2030 count++; 2031 else 2032 break; 2033 2034 /* sync Rx buffer for device write */ 2035 dma_sync_single_for_device(rx_ring->dev, 2036 rx_buffer->dma, 2037 ixgbe_rx_bufsz(rx_ring), 2038 DMA_FROM_DEVICE); 2039 2040 /* increment Rx next to clean counter */ 2041 rx_ntc++; 2042 if (rx_ntc == rx_ring->count) 2043 rx_ntc = 0; 2044 2045 /* fetch next descriptor */ 2046 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 2047 } 2048 2049 netdev_tx_reset_queue(txring_txq(tx_ring)); 2050 2051 /* re-map buffers to ring, store next to clean values */ 2052 ixgbe_alloc_rx_buffers(rx_ring, count); 2053 rx_ring->next_to_clean = rx_ntc; 2054 tx_ring->next_to_clean = tx_ntc; 2055 2056 return count; 2057 } 2058 2059 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 2060 { 2061 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 2062 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 2063 int i, j, lc, good_cnt, ret_val = 0; 2064 unsigned int size = 1024; 2065 netdev_tx_t tx_ret_val; 2066 struct sk_buff *skb; 2067 u32 flags_orig = adapter->flags; 2068 2069 /* DCB can modify the frames on Tx */ 2070 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 2071 2072 /* allocate test skb */ 2073 skb = alloc_skb(size, GFP_KERNEL); 2074 if (!skb) 2075 return 11; 2076 2077 /* place data into test skb */ 2078 ixgbe_create_lbtest_frame(skb, size); 2079 skb_put(skb, size); 2080 2081 /* 2082 * Calculate the loop count based on the largest descriptor ring 2083 * The idea is to wrap the largest ring a number of times using 64 2084 * send/receive pairs during each loop 2085 */ 2086 2087 if (rx_ring->count <= tx_ring->count) 2088 lc = ((tx_ring->count / 64) * 2) + 1; 2089 else 2090 lc = ((rx_ring->count / 64) * 2) + 1; 2091 2092 for (j = 0; j <= lc; j++) { 2093 /* reset count of good packets */ 2094 good_cnt = 0; 2095 2096 /* place 64 packets on the transmit queue*/ 2097 for (i = 0; i < 64; i++) { 2098 skb_get(skb); 2099 tx_ret_val = ixgbe_xmit_frame_ring(skb, 2100 adapter, 2101 tx_ring); 2102 if (tx_ret_val == NETDEV_TX_OK) 2103 good_cnt++; 2104 } 2105 2106 if (good_cnt != 64) { 2107 ret_val = 12; 2108 break; 2109 } 2110 2111 /* allow 200 milliseconds for packets to go from Tx to Rx */ 2112 msleep(200); 2113 2114 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 2115 if (good_cnt != 64) { 2116 ret_val = 13; 2117 break; 2118 } 2119 } 2120 2121 /* free the original skb */ 2122 kfree_skb(skb); 2123 adapter->flags = flags_orig; 2124 2125 return ret_val; 2126 } 2127 2128 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 2129 { 2130 *data = ixgbe_setup_desc_rings(adapter); 2131 if (*data) 2132 goto out; 2133 *data = ixgbe_setup_loopback_test(adapter); 2134 if (*data) 2135 goto err_loopback; 2136 *data = ixgbe_run_loopback_test(adapter); 2137 ixgbe_loopback_cleanup(adapter); 2138 2139 err_loopback: 2140 ixgbe_free_desc_rings(adapter); 2141 out: 2142 return *data; 2143 } 2144 2145 static void ixgbe_diag_test(struct net_device *netdev, 2146 struct ethtool_test *eth_test, u64 *data) 2147 { 2148 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2149 bool if_running = netif_running(netdev); 2150 2151 if (ixgbe_removed(adapter->hw.hw_addr)) { 2152 e_err(hw, "Adapter removed - test blocked\n"); 2153 data[0] = 1; 2154 data[1] = 1; 2155 data[2] = 1; 2156 data[3] = 1; 2157 data[4] = 1; 2158 eth_test->flags |= ETH_TEST_FL_FAILED; 2159 return; 2160 } 2161 set_bit(__IXGBE_TESTING, &adapter->state); 2162 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2163 struct ixgbe_hw *hw = &adapter->hw; 2164 2165 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2166 int i; 2167 for (i = 0; i < adapter->num_vfs; i++) { 2168 if (adapter->vfinfo[i].clear_to_send) { 2169 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2170 data[0] = 1; 2171 data[1] = 1; 2172 data[2] = 1; 2173 data[3] = 1; 2174 data[4] = 1; 2175 eth_test->flags |= ETH_TEST_FL_FAILED; 2176 clear_bit(__IXGBE_TESTING, 2177 &adapter->state); 2178 return; 2179 } 2180 } 2181 } 2182 2183 /* Offline tests */ 2184 e_info(hw, "offline testing starting\n"); 2185 2186 /* Link test performed before hardware reset so autoneg doesn't 2187 * interfere with test result 2188 */ 2189 if (ixgbe_link_test(adapter, &data[4])) 2190 eth_test->flags |= ETH_TEST_FL_FAILED; 2191 2192 if (if_running) 2193 /* indicate we're in test mode */ 2194 ixgbe_close(netdev); 2195 else 2196 ixgbe_reset(adapter); 2197 2198 e_info(hw, "register testing starting\n"); 2199 if (ixgbe_reg_test(adapter, &data[0])) 2200 eth_test->flags |= ETH_TEST_FL_FAILED; 2201 2202 ixgbe_reset(adapter); 2203 e_info(hw, "eeprom testing starting\n"); 2204 if (ixgbe_eeprom_test(adapter, &data[1])) 2205 eth_test->flags |= ETH_TEST_FL_FAILED; 2206 2207 ixgbe_reset(adapter); 2208 e_info(hw, "interrupt testing starting\n"); 2209 if (ixgbe_intr_test(adapter, &data[2])) 2210 eth_test->flags |= ETH_TEST_FL_FAILED; 2211 2212 /* If SRIOV or VMDq is enabled then skip MAC 2213 * loopback diagnostic. */ 2214 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2215 IXGBE_FLAG_VMDQ_ENABLED)) { 2216 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2217 data[3] = 0; 2218 goto skip_loopback; 2219 } 2220 2221 ixgbe_reset(adapter); 2222 e_info(hw, "loopback testing starting\n"); 2223 if (ixgbe_loopback_test(adapter, &data[3])) 2224 eth_test->flags |= ETH_TEST_FL_FAILED; 2225 2226 skip_loopback: 2227 ixgbe_reset(adapter); 2228 2229 /* clear testing bit and return adapter to previous state */ 2230 clear_bit(__IXGBE_TESTING, &adapter->state); 2231 if (if_running) 2232 ixgbe_open(netdev); 2233 else if (hw->mac.ops.disable_tx_laser) 2234 hw->mac.ops.disable_tx_laser(hw); 2235 } else { 2236 e_info(hw, "online testing starting\n"); 2237 2238 /* Online tests */ 2239 if (ixgbe_link_test(adapter, &data[4])) 2240 eth_test->flags |= ETH_TEST_FL_FAILED; 2241 2242 /* Offline tests aren't run; pass by default */ 2243 data[0] = 0; 2244 data[1] = 0; 2245 data[2] = 0; 2246 data[3] = 0; 2247 2248 clear_bit(__IXGBE_TESTING, &adapter->state); 2249 } 2250 } 2251 2252 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2253 struct ethtool_wolinfo *wol) 2254 { 2255 struct ixgbe_hw *hw = &adapter->hw; 2256 int retval = 0; 2257 2258 /* WOL not supported for all devices */ 2259 if (!ixgbe_wol_supported(adapter, hw->device_id, 2260 hw->subsystem_device_id)) { 2261 retval = 1; 2262 wol->supported = 0; 2263 } 2264 2265 return retval; 2266 } 2267 2268 static void ixgbe_get_wol(struct net_device *netdev, 2269 struct ethtool_wolinfo *wol) 2270 { 2271 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2272 2273 wol->supported = WAKE_UCAST | WAKE_MCAST | 2274 WAKE_BCAST | WAKE_MAGIC; 2275 wol->wolopts = 0; 2276 2277 if (ixgbe_wol_exclusion(adapter, wol) || 2278 !device_can_wakeup(&adapter->pdev->dev)) 2279 return; 2280 2281 if (adapter->wol & IXGBE_WUFC_EX) 2282 wol->wolopts |= WAKE_UCAST; 2283 if (adapter->wol & IXGBE_WUFC_MC) 2284 wol->wolopts |= WAKE_MCAST; 2285 if (adapter->wol & IXGBE_WUFC_BC) 2286 wol->wolopts |= WAKE_BCAST; 2287 if (adapter->wol & IXGBE_WUFC_MAG) 2288 wol->wolopts |= WAKE_MAGIC; 2289 } 2290 2291 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2292 { 2293 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2294 2295 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE | 2296 WAKE_FILTER)) 2297 return -EOPNOTSUPP; 2298 2299 if (ixgbe_wol_exclusion(adapter, wol)) 2300 return wol->wolopts ? -EOPNOTSUPP : 0; 2301 2302 adapter->wol = 0; 2303 2304 if (wol->wolopts & WAKE_UCAST) 2305 adapter->wol |= IXGBE_WUFC_EX; 2306 if (wol->wolopts & WAKE_MCAST) 2307 adapter->wol |= IXGBE_WUFC_MC; 2308 if (wol->wolopts & WAKE_BCAST) 2309 adapter->wol |= IXGBE_WUFC_BC; 2310 if (wol->wolopts & WAKE_MAGIC) 2311 adapter->wol |= IXGBE_WUFC_MAG; 2312 2313 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2314 2315 return 0; 2316 } 2317 2318 static int ixgbe_nway_reset(struct net_device *netdev) 2319 { 2320 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2321 2322 if (netif_running(netdev)) 2323 ixgbe_reinit_locked(adapter); 2324 2325 return 0; 2326 } 2327 2328 static int ixgbe_set_phys_id(struct net_device *netdev, 2329 enum ethtool_phys_id_state state) 2330 { 2331 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2332 struct ixgbe_hw *hw = &adapter->hw; 2333 2334 if (!hw->mac.ops.led_on || !hw->mac.ops.led_off) 2335 return -EOPNOTSUPP; 2336 2337 switch (state) { 2338 case ETHTOOL_ID_ACTIVE: 2339 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2340 return 2; 2341 2342 case ETHTOOL_ID_ON: 2343 hw->mac.ops.led_on(hw, hw->mac.led_link_act); 2344 break; 2345 2346 case ETHTOOL_ID_OFF: 2347 hw->mac.ops.led_off(hw, hw->mac.led_link_act); 2348 break; 2349 2350 case ETHTOOL_ID_INACTIVE: 2351 /* Restore LED settings */ 2352 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2353 break; 2354 } 2355 2356 return 0; 2357 } 2358 2359 static int ixgbe_get_coalesce(struct net_device *netdev, 2360 struct ethtool_coalesce *ec, 2361 struct kernel_ethtool_coalesce *kernel_coal, 2362 struct netlink_ext_ack *extack) 2363 { 2364 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2365 2366 /* only valid if in constant ITR mode */ 2367 if (adapter->rx_itr_setting <= 1) 2368 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2369 else 2370 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2371 2372 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2373 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2374 return 0; 2375 2376 /* only valid if in constant ITR mode */ 2377 if (adapter->tx_itr_setting <= 1) 2378 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2379 else 2380 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2381 2382 return 0; 2383 } 2384 2385 /* 2386 * this function must be called before setting the new value of 2387 * rx_itr_setting 2388 */ 2389 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2390 { 2391 struct net_device *netdev = adapter->netdev; 2392 2393 /* nothing to do if LRO or RSC are not enabled */ 2394 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2395 !(netdev->features & NETIF_F_LRO)) 2396 return false; 2397 2398 /* check the feature flag value and enable RSC if necessary */ 2399 if (adapter->rx_itr_setting == 1 || 2400 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2401 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2402 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2403 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2404 return true; 2405 } 2406 /* if interrupt rate is too high then disable RSC */ 2407 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2408 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2409 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2410 return true; 2411 } 2412 return false; 2413 } 2414 2415 static int ixgbe_set_coalesce(struct net_device *netdev, 2416 struct ethtool_coalesce *ec, 2417 struct kernel_ethtool_coalesce *kernel_coal, 2418 struct netlink_ext_ack *extack) 2419 { 2420 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2421 struct ixgbe_q_vector *q_vector; 2422 int i; 2423 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2424 bool need_reset = false; 2425 2426 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2427 /* reject Tx specific changes in case of mixed RxTx vectors */ 2428 if (ec->tx_coalesce_usecs) 2429 return -EINVAL; 2430 tx_itr_prev = adapter->rx_itr_setting; 2431 } else { 2432 tx_itr_prev = adapter->tx_itr_setting; 2433 } 2434 2435 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2436 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2437 return -EINVAL; 2438 2439 if (ec->rx_coalesce_usecs > 1) 2440 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2441 else 2442 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2443 2444 if (adapter->rx_itr_setting == 1) 2445 rx_itr_param = IXGBE_20K_ITR; 2446 else 2447 rx_itr_param = adapter->rx_itr_setting; 2448 2449 if (ec->tx_coalesce_usecs > 1) 2450 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2451 else 2452 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2453 2454 if (adapter->tx_itr_setting == 1) 2455 tx_itr_param = IXGBE_12K_ITR; 2456 else 2457 tx_itr_param = adapter->tx_itr_setting; 2458 2459 /* mixed Rx/Tx */ 2460 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2461 adapter->tx_itr_setting = adapter->rx_itr_setting; 2462 2463 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2464 if ((adapter->tx_itr_setting != 1) && 2465 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2466 if ((tx_itr_prev == 1) || 2467 (tx_itr_prev >= IXGBE_100K_ITR)) 2468 need_reset = true; 2469 } else { 2470 if ((tx_itr_prev != 1) && 2471 (tx_itr_prev < IXGBE_100K_ITR)) 2472 need_reset = true; 2473 } 2474 2475 /* check the old value and enable RSC if necessary */ 2476 need_reset |= ixgbe_update_rsc(adapter); 2477 2478 for (i = 0; i < adapter->num_q_vectors; i++) { 2479 q_vector = adapter->q_vector[i]; 2480 if (q_vector->tx.count && !q_vector->rx.count) 2481 /* tx only */ 2482 q_vector->itr = tx_itr_param; 2483 else 2484 /* rx only or mixed */ 2485 q_vector->itr = rx_itr_param; 2486 ixgbe_write_eitr(q_vector); 2487 } 2488 2489 /* 2490 * do reset here at the end to make sure EITR==0 case is handled 2491 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2492 * also locks in RSC enable/disable which requires reset 2493 */ 2494 if (need_reset) 2495 ixgbe_do_reset(netdev); 2496 2497 return 0; 2498 } 2499 2500 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2501 struct ethtool_rxnfc *cmd) 2502 { 2503 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2504 struct ethtool_rx_flow_spec *fsp = 2505 (struct ethtool_rx_flow_spec *)&cmd->fs; 2506 struct hlist_node *node2; 2507 struct ixgbe_fdir_filter *rule = NULL; 2508 2509 /* report total rule count */ 2510 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2511 2512 hlist_for_each_entry_safe(rule, node2, 2513 &adapter->fdir_filter_list, fdir_node) { 2514 if (fsp->location <= rule->sw_idx) 2515 break; 2516 } 2517 2518 if (!rule || fsp->location != rule->sw_idx) 2519 return -EINVAL; 2520 2521 /* fill out the flow spec entry */ 2522 2523 /* set flow type field */ 2524 switch (rule->filter.formatted.flow_type) { 2525 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2526 fsp->flow_type = TCP_V4_FLOW; 2527 break; 2528 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2529 fsp->flow_type = UDP_V4_FLOW; 2530 break; 2531 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2532 fsp->flow_type = SCTP_V4_FLOW; 2533 break; 2534 case IXGBE_ATR_FLOW_TYPE_IPV4: 2535 fsp->flow_type = IP_USER_FLOW; 2536 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2537 fsp->h_u.usr_ip4_spec.proto = 0; 2538 fsp->m_u.usr_ip4_spec.proto = 0; 2539 break; 2540 default: 2541 return -EINVAL; 2542 } 2543 2544 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2545 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2546 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2547 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2548 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2549 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2550 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2551 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2552 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2553 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2554 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2555 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2556 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2557 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2558 fsp->flow_type |= FLOW_EXT; 2559 2560 /* record action */ 2561 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2562 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2563 else 2564 fsp->ring_cookie = rule->action; 2565 2566 return 0; 2567 } 2568 2569 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2570 struct ethtool_rxnfc *cmd, 2571 u32 *rule_locs) 2572 { 2573 struct hlist_node *node2; 2574 struct ixgbe_fdir_filter *rule; 2575 int cnt = 0; 2576 2577 /* report total rule count */ 2578 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2579 2580 hlist_for_each_entry_safe(rule, node2, 2581 &adapter->fdir_filter_list, fdir_node) { 2582 if (cnt == cmd->rule_cnt) 2583 return -EMSGSIZE; 2584 rule_locs[cnt] = rule->sw_idx; 2585 cnt++; 2586 } 2587 2588 cmd->rule_cnt = cnt; 2589 2590 return 0; 2591 } 2592 2593 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2594 struct ethtool_rxnfc *cmd) 2595 { 2596 cmd->data = 0; 2597 2598 /* Report default options for RSS on ixgbe */ 2599 switch (cmd->flow_type) { 2600 case TCP_V4_FLOW: 2601 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2602 fallthrough; 2603 case UDP_V4_FLOW: 2604 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2605 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2606 fallthrough; 2607 case SCTP_V4_FLOW: 2608 case AH_ESP_V4_FLOW: 2609 case AH_V4_FLOW: 2610 case ESP_V4_FLOW: 2611 case IPV4_FLOW: 2612 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2613 break; 2614 case TCP_V6_FLOW: 2615 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2616 fallthrough; 2617 case UDP_V6_FLOW: 2618 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2619 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2620 fallthrough; 2621 case SCTP_V6_FLOW: 2622 case AH_ESP_V6_FLOW: 2623 case AH_V6_FLOW: 2624 case ESP_V6_FLOW: 2625 case IPV6_FLOW: 2626 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2627 break; 2628 default: 2629 return -EINVAL; 2630 } 2631 2632 return 0; 2633 } 2634 2635 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2636 u32 *rule_locs) 2637 { 2638 struct ixgbe_adapter *adapter = netdev_priv(dev); 2639 int ret = -EOPNOTSUPP; 2640 2641 switch (cmd->cmd) { 2642 case ETHTOOL_GRXRINGS: 2643 cmd->data = adapter->num_rx_queues; 2644 ret = 0; 2645 break; 2646 case ETHTOOL_GRXCLSRLCNT: 2647 cmd->rule_cnt = adapter->fdir_filter_count; 2648 ret = 0; 2649 break; 2650 case ETHTOOL_GRXCLSRULE: 2651 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2652 break; 2653 case ETHTOOL_GRXCLSRLALL: 2654 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2655 break; 2656 case ETHTOOL_GRXFH: 2657 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2658 break; 2659 default: 2660 break; 2661 } 2662 2663 return ret; 2664 } 2665 2666 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2667 struct ixgbe_fdir_filter *input, 2668 u16 sw_idx) 2669 { 2670 struct ixgbe_hw *hw = &adapter->hw; 2671 struct hlist_node *node2; 2672 struct ixgbe_fdir_filter *rule, *parent; 2673 int err = -EINVAL; 2674 2675 parent = NULL; 2676 rule = NULL; 2677 2678 hlist_for_each_entry_safe(rule, node2, 2679 &adapter->fdir_filter_list, fdir_node) { 2680 /* hash found, or no matching entry */ 2681 if (rule->sw_idx >= sw_idx) 2682 break; 2683 parent = rule; 2684 } 2685 2686 /* if there is an old rule occupying our place remove it */ 2687 if (rule && (rule->sw_idx == sw_idx)) { 2688 if (!input || (rule->filter.formatted.bkt_hash != 2689 input->filter.formatted.bkt_hash)) { 2690 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2691 &rule->filter, 2692 sw_idx); 2693 } 2694 2695 hlist_del(&rule->fdir_node); 2696 kfree(rule); 2697 adapter->fdir_filter_count--; 2698 } 2699 2700 /* 2701 * If no input this was a delete, err should be 0 if a rule was 2702 * successfully found and removed from the list else -EINVAL 2703 */ 2704 if (!input) 2705 return err; 2706 2707 /* initialize node and set software index */ 2708 INIT_HLIST_NODE(&input->fdir_node); 2709 2710 /* add filter to the list */ 2711 if (parent) 2712 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2713 else 2714 hlist_add_head(&input->fdir_node, 2715 &adapter->fdir_filter_list); 2716 2717 /* update counts */ 2718 adapter->fdir_filter_count++; 2719 2720 return 0; 2721 } 2722 2723 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2724 u8 *flow_type) 2725 { 2726 switch (fsp->flow_type & ~FLOW_EXT) { 2727 case TCP_V4_FLOW: 2728 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2729 break; 2730 case UDP_V4_FLOW: 2731 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2732 break; 2733 case SCTP_V4_FLOW: 2734 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2735 break; 2736 case IP_USER_FLOW: 2737 switch (fsp->h_u.usr_ip4_spec.proto) { 2738 case IPPROTO_TCP: 2739 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2740 break; 2741 case IPPROTO_UDP: 2742 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2743 break; 2744 case IPPROTO_SCTP: 2745 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2746 break; 2747 case 0: 2748 if (!fsp->m_u.usr_ip4_spec.proto) { 2749 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2750 break; 2751 } 2752 fallthrough; 2753 default: 2754 return 0; 2755 } 2756 break; 2757 default: 2758 return 0; 2759 } 2760 2761 return 1; 2762 } 2763 2764 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2765 struct ethtool_rxnfc *cmd) 2766 { 2767 struct ethtool_rx_flow_spec *fsp = 2768 (struct ethtool_rx_flow_spec *)&cmd->fs; 2769 struct ixgbe_hw *hw = &adapter->hw; 2770 struct ixgbe_fdir_filter *input; 2771 union ixgbe_atr_input mask; 2772 u8 queue; 2773 int err; 2774 2775 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2776 return -EOPNOTSUPP; 2777 2778 /* ring_cookie is a masked into a set of queues and ixgbe pools or 2779 * we use the drop index. 2780 */ 2781 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 2782 queue = IXGBE_FDIR_DROP_QUEUE; 2783 } else { 2784 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); 2785 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie); 2786 2787 if (!vf && (ring >= adapter->num_rx_queues)) 2788 return -EINVAL; 2789 else if (vf && 2790 ((vf > adapter->num_vfs) || 2791 ring >= adapter->num_rx_queues_per_pool)) 2792 return -EINVAL; 2793 2794 /* Map the ring onto the absolute queue index */ 2795 if (!vf) 2796 queue = adapter->rx_ring[ring]->reg_idx; 2797 else 2798 queue = ((vf - 1) * 2799 adapter->num_rx_queues_per_pool) + ring; 2800 } 2801 2802 /* Don't allow indexes to exist outside of available space */ 2803 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2804 e_err(drv, "Location out of range\n"); 2805 return -EINVAL; 2806 } 2807 2808 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2809 if (!input) 2810 return -ENOMEM; 2811 2812 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2813 2814 /* set SW index */ 2815 input->sw_idx = fsp->location; 2816 2817 /* record flow type */ 2818 if (!ixgbe_flowspec_to_flow_type(fsp, 2819 &input->filter.formatted.flow_type)) { 2820 e_err(drv, "Unrecognized flow type\n"); 2821 goto err_out; 2822 } 2823 2824 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2825 IXGBE_ATR_L4TYPE_MASK; 2826 2827 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2828 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2829 2830 /* Copy input into formatted structures */ 2831 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2832 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2833 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2834 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2835 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2836 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2837 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2838 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2839 2840 if (fsp->flow_type & FLOW_EXT) { 2841 input->filter.formatted.vm_pool = 2842 (unsigned char)ntohl(fsp->h_ext.data[1]); 2843 mask.formatted.vm_pool = 2844 (unsigned char)ntohl(fsp->m_ext.data[1]); 2845 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2846 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2847 input->filter.formatted.flex_bytes = 2848 fsp->h_ext.vlan_etype; 2849 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2850 } 2851 2852 /* determine if we need to drop or route the packet */ 2853 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2854 input->action = IXGBE_FDIR_DROP_QUEUE; 2855 else 2856 input->action = fsp->ring_cookie; 2857 2858 spin_lock(&adapter->fdir_perfect_lock); 2859 2860 if (hlist_empty(&adapter->fdir_filter_list)) { 2861 /* save mask and program input mask into HW */ 2862 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2863 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2864 if (err) { 2865 e_err(drv, "Error writing mask\n"); 2866 goto err_out_w_lock; 2867 } 2868 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2869 e_err(drv, "Only one mask supported per port\n"); 2870 goto err_out_w_lock; 2871 } 2872 2873 /* apply mask and compute/store hash */ 2874 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2875 2876 /* program filters to filter memory */ 2877 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2878 &input->filter, input->sw_idx, queue); 2879 if (err) 2880 goto err_out_w_lock; 2881 2882 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2883 2884 spin_unlock(&adapter->fdir_perfect_lock); 2885 2886 return err; 2887 err_out_w_lock: 2888 spin_unlock(&adapter->fdir_perfect_lock); 2889 err_out: 2890 kfree(input); 2891 return -EINVAL; 2892 } 2893 2894 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2895 struct ethtool_rxnfc *cmd) 2896 { 2897 struct ethtool_rx_flow_spec *fsp = 2898 (struct ethtool_rx_flow_spec *)&cmd->fs; 2899 int err; 2900 2901 spin_lock(&adapter->fdir_perfect_lock); 2902 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2903 spin_unlock(&adapter->fdir_perfect_lock); 2904 2905 return err; 2906 } 2907 2908 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2909 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2910 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2911 struct ethtool_rxnfc *nfc) 2912 { 2913 u32 flags2 = adapter->flags2; 2914 2915 /* 2916 * RSS does not support anything other than hashing 2917 * to queues on src and dst IPs and ports 2918 */ 2919 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2920 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2921 return -EINVAL; 2922 2923 switch (nfc->flow_type) { 2924 case TCP_V4_FLOW: 2925 case TCP_V6_FLOW: 2926 if (!(nfc->data & RXH_IP_SRC) || 2927 !(nfc->data & RXH_IP_DST) || 2928 !(nfc->data & RXH_L4_B_0_1) || 2929 !(nfc->data & RXH_L4_B_2_3)) 2930 return -EINVAL; 2931 break; 2932 case UDP_V4_FLOW: 2933 if (!(nfc->data & RXH_IP_SRC) || 2934 !(nfc->data & RXH_IP_DST)) 2935 return -EINVAL; 2936 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2937 case 0: 2938 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2939 break; 2940 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2941 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2942 break; 2943 default: 2944 return -EINVAL; 2945 } 2946 break; 2947 case UDP_V6_FLOW: 2948 if (!(nfc->data & RXH_IP_SRC) || 2949 !(nfc->data & RXH_IP_DST)) 2950 return -EINVAL; 2951 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2952 case 0: 2953 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2954 break; 2955 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2956 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2957 break; 2958 default: 2959 return -EINVAL; 2960 } 2961 break; 2962 case AH_ESP_V4_FLOW: 2963 case AH_V4_FLOW: 2964 case ESP_V4_FLOW: 2965 case SCTP_V4_FLOW: 2966 case AH_ESP_V6_FLOW: 2967 case AH_V6_FLOW: 2968 case ESP_V6_FLOW: 2969 case SCTP_V6_FLOW: 2970 if (!(nfc->data & RXH_IP_SRC) || 2971 !(nfc->data & RXH_IP_DST) || 2972 (nfc->data & RXH_L4_B_0_1) || 2973 (nfc->data & RXH_L4_B_2_3)) 2974 return -EINVAL; 2975 break; 2976 default: 2977 return -EINVAL; 2978 } 2979 2980 /* if we changed something we need to update flags */ 2981 if (flags2 != adapter->flags2) { 2982 struct ixgbe_hw *hw = &adapter->hw; 2983 u32 mrqc; 2984 unsigned int pf_pool = adapter->num_vfs; 2985 2986 if ((hw->mac.type >= ixgbe_mac_X550) && 2987 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2988 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 2989 else 2990 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2991 2992 if ((flags2 & UDP_RSS_FLAGS) && 2993 !(adapter->flags2 & UDP_RSS_FLAGS)) 2994 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2995 2996 adapter->flags2 = flags2; 2997 2998 /* Perform hash on these packet types */ 2999 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 3000 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 3001 | IXGBE_MRQC_RSS_FIELD_IPV6 3002 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3003 3004 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 3005 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 3006 3007 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3008 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3009 3010 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3011 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3012 3013 if ((hw->mac.type >= ixgbe_mac_X550) && 3014 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 3015 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 3016 else 3017 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 3018 } 3019 3020 return 0; 3021 } 3022 3023 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3024 { 3025 struct ixgbe_adapter *adapter = netdev_priv(dev); 3026 int ret = -EOPNOTSUPP; 3027 3028 switch (cmd->cmd) { 3029 case ETHTOOL_SRXCLSRLINS: 3030 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 3031 break; 3032 case ETHTOOL_SRXCLSRLDEL: 3033 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 3034 break; 3035 case ETHTOOL_SRXFH: 3036 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 3037 break; 3038 default: 3039 break; 3040 } 3041 3042 return ret; 3043 } 3044 3045 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) 3046 { 3047 if (adapter->hw.mac.type < ixgbe_mac_X550) 3048 return 16; 3049 else 3050 return 64; 3051 } 3052 3053 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) 3054 { 3055 return IXGBE_RSS_KEY_SIZE; 3056 } 3057 3058 static u32 ixgbe_rss_indir_size(struct net_device *netdev) 3059 { 3060 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3061 3062 return ixgbe_rss_indir_tbl_entries(adapter); 3063 } 3064 3065 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir) 3066 { 3067 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter); 3068 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask; 3069 3070 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3071 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1; 3072 3073 for (i = 0; i < reta_size; i++) 3074 indir[i] = adapter->rss_indir_tbl[i] & rss_m; 3075 } 3076 3077 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 3078 u8 *hfunc) 3079 { 3080 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3081 3082 if (hfunc) 3083 *hfunc = ETH_RSS_HASH_TOP; 3084 3085 if (indir) 3086 ixgbe_get_reta(adapter, indir); 3087 3088 if (key) 3089 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev)); 3090 3091 return 0; 3092 } 3093 3094 static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir, 3095 const u8 *key, const u8 hfunc) 3096 { 3097 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3098 int i; 3099 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3100 3101 if (hfunc) 3102 return -EINVAL; 3103 3104 /* Fill out the redirection table */ 3105 if (indir) { 3106 int max_queues = min_t(int, adapter->num_rx_queues, 3107 ixgbe_rss_indir_tbl_max(adapter)); 3108 3109 /*Allow at least 2 queues w/ SR-IOV.*/ 3110 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 3111 (max_queues < 2)) 3112 max_queues = 2; 3113 3114 /* Verify user input. */ 3115 for (i = 0; i < reta_entries; i++) 3116 if (indir[i] >= max_queues) 3117 return -EINVAL; 3118 3119 for (i = 0; i < reta_entries; i++) 3120 adapter->rss_indir_tbl[i] = indir[i]; 3121 3122 ixgbe_store_reta(adapter); 3123 } 3124 3125 /* Fill out the rss hash key */ 3126 if (key) { 3127 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev)); 3128 ixgbe_store_key(adapter); 3129 } 3130 3131 return 0; 3132 } 3133 3134 static int ixgbe_get_ts_info(struct net_device *dev, 3135 struct ethtool_ts_info *info) 3136 { 3137 struct ixgbe_adapter *adapter = netdev_priv(dev); 3138 3139 /* we always support timestamping disabled */ 3140 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 3141 3142 switch (adapter->hw.mac.type) { 3143 case ixgbe_mac_X550: 3144 case ixgbe_mac_X550EM_x: 3145 case ixgbe_mac_x550em_a: 3146 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 3147 break; 3148 case ixgbe_mac_X540: 3149 case ixgbe_mac_82599EB: 3150 info->rx_filters |= 3151 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3152 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3153 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 3154 break; 3155 default: 3156 return ethtool_op_get_ts_info(dev, info); 3157 } 3158 3159 info->so_timestamping = 3160 SOF_TIMESTAMPING_TX_SOFTWARE | 3161 SOF_TIMESTAMPING_RX_SOFTWARE | 3162 SOF_TIMESTAMPING_SOFTWARE | 3163 SOF_TIMESTAMPING_TX_HARDWARE | 3164 SOF_TIMESTAMPING_RX_HARDWARE | 3165 SOF_TIMESTAMPING_RAW_HARDWARE; 3166 3167 if (adapter->ptp_clock) 3168 info->phc_index = ptp_clock_index(adapter->ptp_clock); 3169 else 3170 info->phc_index = -1; 3171 3172 info->tx_types = 3173 BIT(HWTSTAMP_TX_OFF) | 3174 BIT(HWTSTAMP_TX_ON); 3175 3176 return 0; 3177 } 3178 3179 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 3180 { 3181 unsigned int max_combined; 3182 u8 tcs = adapter->hw_tcs; 3183 3184 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3185 /* We only support one q_vector without MSI-X */ 3186 max_combined = 1; 3187 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3188 /* Limit value based on the queue mask */ 3189 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1; 3190 } else if (tcs > 1) { 3191 /* For DCB report channels per traffic class */ 3192 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3193 /* 8 TC w/ 4 queues per TC */ 3194 max_combined = 4; 3195 } else if (tcs > 4) { 3196 /* 8 TC w/ 8 queues per TC */ 3197 max_combined = 8; 3198 } else { 3199 /* 4 TC w/ 16 queues per TC */ 3200 max_combined = 16; 3201 } 3202 } else if (adapter->atr_sample_rate) { 3203 /* support up to 64 queues with ATR */ 3204 max_combined = IXGBE_MAX_FDIR_INDICES; 3205 } else { 3206 /* support up to 16 queues with RSS */ 3207 max_combined = ixgbe_max_rss_indices(adapter); 3208 } 3209 3210 return min_t(int, max_combined, num_online_cpus()); 3211 } 3212 3213 static void ixgbe_get_channels(struct net_device *dev, 3214 struct ethtool_channels *ch) 3215 { 3216 struct ixgbe_adapter *adapter = netdev_priv(dev); 3217 3218 /* report maximum channels */ 3219 ch->max_combined = ixgbe_max_channels(adapter); 3220 3221 /* report info for other vector */ 3222 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3223 ch->max_other = NON_Q_VECTORS; 3224 ch->other_count = NON_Q_VECTORS; 3225 } 3226 3227 /* record RSS queues */ 3228 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 3229 3230 /* nothing else to report if RSS is disabled */ 3231 if (ch->combined_count == 1) 3232 return; 3233 3234 /* we do not support ATR queueing if SR-IOV is enabled */ 3235 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3236 return; 3237 3238 /* same thing goes for being DCB enabled */ 3239 if (adapter->hw_tcs > 1) 3240 return; 3241 3242 /* if ATR is disabled we can exit */ 3243 if (!adapter->atr_sample_rate) 3244 return; 3245 3246 /* report flow director queues as maximum channels */ 3247 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 3248 } 3249 3250 static int ixgbe_set_channels(struct net_device *dev, 3251 struct ethtool_channels *ch) 3252 { 3253 struct ixgbe_adapter *adapter = netdev_priv(dev); 3254 unsigned int count = ch->combined_count; 3255 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 3256 3257 /* verify they are not requesting separate vectors */ 3258 if (!count || ch->rx_count || ch->tx_count) 3259 return -EINVAL; 3260 3261 /* verify other_count has not changed */ 3262 if (ch->other_count != NON_Q_VECTORS) 3263 return -EINVAL; 3264 3265 /* verify the number of channels does not exceed hardware limits */ 3266 if (count > ixgbe_max_channels(adapter)) 3267 return -EINVAL; 3268 3269 /* update feature limits from largest to smallest supported values */ 3270 adapter->ring_feature[RING_F_FDIR].limit = count; 3271 3272 /* cap RSS limit */ 3273 if (count > max_rss_indices) 3274 count = max_rss_indices; 3275 adapter->ring_feature[RING_F_RSS].limit = count; 3276 3277 #ifdef IXGBE_FCOE 3278 /* cap FCoE limit at 8 */ 3279 if (count > IXGBE_FCRETA_SIZE) 3280 count = IXGBE_FCRETA_SIZE; 3281 adapter->ring_feature[RING_F_FCOE].limit = count; 3282 3283 #endif 3284 /* use setup TC to update any traffic class queue mapping */ 3285 return ixgbe_setup_tc(dev, adapter->hw_tcs); 3286 } 3287 3288 static int ixgbe_get_module_info(struct net_device *dev, 3289 struct ethtool_modinfo *modinfo) 3290 { 3291 struct ixgbe_adapter *adapter = netdev_priv(dev); 3292 struct ixgbe_hw *hw = &adapter->hw; 3293 s32 status; 3294 u8 sff8472_rev, addr_mode; 3295 bool page_swap = false; 3296 3297 if (hw->phy.type == ixgbe_phy_fw) 3298 return -ENXIO; 3299 3300 /* Check whether we support SFF-8472 or not */ 3301 status = hw->phy.ops.read_i2c_eeprom(hw, 3302 IXGBE_SFF_SFF_8472_COMP, 3303 &sff8472_rev); 3304 if (status) 3305 return -EIO; 3306 3307 /* addressing mode is not supported */ 3308 status = hw->phy.ops.read_i2c_eeprom(hw, 3309 IXGBE_SFF_SFF_8472_SWAP, 3310 &addr_mode); 3311 if (status) 3312 return -EIO; 3313 3314 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3315 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3316 page_swap = true; 3317 } 3318 3319 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap || 3320 !(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) { 3321 /* We have a SFP, but it does not support SFF-8472 */ 3322 modinfo->type = ETH_MODULE_SFF_8079; 3323 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3324 } else { 3325 /* We have a SFP which supports a revision of SFF-8472. */ 3326 modinfo->type = ETH_MODULE_SFF_8472; 3327 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3328 } 3329 3330 return 0; 3331 } 3332 3333 static int ixgbe_get_module_eeprom(struct net_device *dev, 3334 struct ethtool_eeprom *ee, 3335 u8 *data) 3336 { 3337 struct ixgbe_adapter *adapter = netdev_priv(dev); 3338 struct ixgbe_hw *hw = &adapter->hw; 3339 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3340 u8 databyte = 0xFF; 3341 int i = 0; 3342 3343 if (ee->len == 0) 3344 return -EINVAL; 3345 3346 if (hw->phy.type == ixgbe_phy_fw) 3347 return -ENXIO; 3348 3349 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3350 /* I2C reads can take long time */ 3351 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3352 return -EBUSY; 3353 3354 if (i < ETH_MODULE_SFF_8079_LEN) 3355 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3356 else 3357 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3358 3359 if (status) 3360 return -EIO; 3361 3362 data[i - ee->offset] = databyte; 3363 } 3364 3365 return 0; 3366 } 3367 3368 static const struct { 3369 ixgbe_link_speed mac_speed; 3370 u32 supported; 3371 } ixgbe_ls_map[] = { 3372 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full }, 3373 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full }, 3374 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full }, 3375 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full }, 3376 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full }, 3377 }; 3378 3379 static const struct { 3380 u32 lp_advertised; 3381 u32 mac_speed; 3382 } ixgbe_lp_map[] = { 3383 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full }, 3384 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full }, 3385 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full }, 3386 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full }, 3387 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full }, 3388 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full}, 3389 }; 3390 3391 static int 3392 ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata) 3393 { 3394 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3395 struct ixgbe_hw *hw = &adapter->hw; 3396 s32 rc; 3397 u16 i; 3398 3399 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info); 3400 if (rc) 3401 return rc; 3402 3403 edata->lp_advertised = 0; 3404 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) { 3405 if (info[0] & ixgbe_lp_map[i].lp_advertised) 3406 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed; 3407 } 3408 3409 edata->supported = 0; 3410 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3411 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed) 3412 edata->supported |= ixgbe_ls_map[i].supported; 3413 } 3414 3415 edata->advertised = 0; 3416 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3417 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed) 3418 edata->advertised |= ixgbe_ls_map[i].supported; 3419 } 3420 3421 edata->eee_enabled = !!edata->advertised; 3422 edata->tx_lpi_enabled = edata->eee_enabled; 3423 if (edata->advertised & edata->lp_advertised) 3424 edata->eee_active = true; 3425 3426 return 0; 3427 } 3428 3429 static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3430 { 3431 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3432 struct ixgbe_hw *hw = &adapter->hw; 3433 3434 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3435 return -EOPNOTSUPP; 3436 3437 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw) 3438 return ixgbe_get_eee_fw(adapter, edata); 3439 3440 return -EOPNOTSUPP; 3441 } 3442 3443 static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata) 3444 { 3445 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3446 struct ixgbe_hw *hw = &adapter->hw; 3447 struct ethtool_eee eee_data; 3448 s32 ret_val; 3449 3450 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3451 return -EOPNOTSUPP; 3452 3453 memset(&eee_data, 0, sizeof(struct ethtool_eee)); 3454 3455 ret_val = ixgbe_get_eee(netdev, &eee_data); 3456 if (ret_val) 3457 return ret_val; 3458 3459 if (eee_data.eee_enabled && !edata->eee_enabled) { 3460 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) { 3461 e_err(drv, "Setting EEE tx-lpi is not supported\n"); 3462 return -EINVAL; 3463 } 3464 3465 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) { 3466 e_err(drv, 3467 "Setting EEE Tx LPI timer is not supported\n"); 3468 return -EINVAL; 3469 } 3470 3471 if (eee_data.advertised != edata->advertised) { 3472 e_err(drv, 3473 "Setting EEE advertised speeds is not supported\n"); 3474 return -EINVAL; 3475 } 3476 } 3477 3478 if (eee_data.eee_enabled != edata->eee_enabled) { 3479 if (edata->eee_enabled) { 3480 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 3481 hw->phy.eee_speeds_advertised = 3482 hw->phy.eee_speeds_supported; 3483 } else { 3484 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 3485 hw->phy.eee_speeds_advertised = 0; 3486 } 3487 3488 /* reset link */ 3489 if (netif_running(netdev)) 3490 ixgbe_reinit_locked(adapter); 3491 else 3492 ixgbe_reset(adapter); 3493 } 3494 3495 return 0; 3496 } 3497 3498 static u32 ixgbe_get_priv_flags(struct net_device *netdev) 3499 { 3500 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3501 u32 priv_flags = 0; 3502 3503 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 3504 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX; 3505 3506 if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED) 3507 priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN; 3508 3509 return priv_flags; 3510 } 3511 3512 static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3513 { 3514 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3515 unsigned int flags2 = adapter->flags2; 3516 3517 flags2 &= ~IXGBE_FLAG2_RX_LEGACY; 3518 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX) 3519 flags2 |= IXGBE_FLAG2_RX_LEGACY; 3520 3521 flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED; 3522 if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN) 3523 flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED; 3524 3525 if (flags2 != adapter->flags2) { 3526 adapter->flags2 = flags2; 3527 3528 /* reset interface to repopulate queues */ 3529 if (netif_running(netdev)) 3530 ixgbe_reinit_locked(adapter); 3531 } 3532 3533 return 0; 3534 } 3535 3536 static const struct ethtool_ops ixgbe_ethtool_ops = { 3537 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 3538 .get_drvinfo = ixgbe_get_drvinfo, 3539 .get_regs_len = ixgbe_get_regs_len, 3540 .get_regs = ixgbe_get_regs, 3541 .get_wol = ixgbe_get_wol, 3542 .set_wol = ixgbe_set_wol, 3543 .nway_reset = ixgbe_nway_reset, 3544 .get_link = ethtool_op_get_link, 3545 .get_eeprom_len = ixgbe_get_eeprom_len, 3546 .get_eeprom = ixgbe_get_eeprom, 3547 .set_eeprom = ixgbe_set_eeprom, 3548 .get_ringparam = ixgbe_get_ringparam, 3549 .set_ringparam = ixgbe_set_ringparam, 3550 .get_pause_stats = ixgbe_get_pause_stats, 3551 .get_pauseparam = ixgbe_get_pauseparam, 3552 .set_pauseparam = ixgbe_set_pauseparam, 3553 .get_msglevel = ixgbe_get_msglevel, 3554 .set_msglevel = ixgbe_set_msglevel, 3555 .self_test = ixgbe_diag_test, 3556 .get_strings = ixgbe_get_strings, 3557 .set_phys_id = ixgbe_set_phys_id, 3558 .get_sset_count = ixgbe_get_sset_count, 3559 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3560 .get_coalesce = ixgbe_get_coalesce, 3561 .set_coalesce = ixgbe_set_coalesce, 3562 .get_rxnfc = ixgbe_get_rxnfc, 3563 .set_rxnfc = ixgbe_set_rxnfc, 3564 .get_rxfh_indir_size = ixgbe_rss_indir_size, 3565 .get_rxfh_key_size = ixgbe_get_rxfh_key_size, 3566 .get_rxfh = ixgbe_get_rxfh, 3567 .set_rxfh = ixgbe_set_rxfh, 3568 .get_eee = ixgbe_get_eee, 3569 .set_eee = ixgbe_set_eee, 3570 .get_channels = ixgbe_get_channels, 3571 .set_channels = ixgbe_set_channels, 3572 .get_priv_flags = ixgbe_get_priv_flags, 3573 .set_priv_flags = ixgbe_set_priv_flags, 3574 .get_ts_info = ixgbe_get_ts_info, 3575 .get_module_info = ixgbe_get_module_info, 3576 .get_module_eeprom = ixgbe_get_module_eeprom, 3577 .get_link_ksettings = ixgbe_get_link_ksettings, 3578 .set_link_ksettings = ixgbe_set_link_ksettings, 3579 }; 3580 3581 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3582 { 3583 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3584 } 3585