1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* ethtool support for ixgbe */ 30 31 #include <linux/interrupt.h> 32 #include <linux/types.h> 33 #include <linux/module.h> 34 #include <linux/slab.h> 35 #include <linux/pci.h> 36 #include <linux/netdevice.h> 37 #include <linux/ethtool.h> 38 #include <linux/vmalloc.h> 39 #include <linux/highmem.h> 40 #include <linux/uaccess.h> 41 42 #include "ixgbe.h" 43 #include "ixgbe_phy.h" 44 45 46 #define IXGBE_ALL_RAR_ENTRIES 16 47 48 enum {NETDEV_STATS, IXGBE_STATS}; 49 50 struct ixgbe_stats { 51 char stat_string[ETH_GSTRING_LEN]; 52 int type; 53 int sizeof_stat; 54 int stat_offset; 55 }; 56 57 #define IXGBE_STAT(m) IXGBE_STATS, \ 58 sizeof(((struct ixgbe_adapter *)0)->m), \ 59 offsetof(struct ixgbe_adapter, m) 60 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 61 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 62 offsetof(struct rtnl_link_stats64, m) 63 64 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 73 {"lsc_int", IXGBE_STAT(lsc_int)}, 74 {"tx_busy", IXGBE_STAT(tx_busy)}, 75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 80 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 81 {"broadcast", IXGBE_STAT(stats.bprc)}, 82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 83 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 99 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 114 #ifdef IXGBE_FCOE 115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 123 #endif /* IXGBE_FCOE */ 124 }; 125 126 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 127 * we set the num_rx_queues to evaluate to num_tx_queues. This is 128 * used because we do not have a good way to get the max number of 129 * rx queues with CONFIG_RPS disabled. 130 */ 131 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 132 133 #define IXGBE_QUEUE_STATS_LEN ( \ 134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 136 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 137 #define IXGBE_PB_STATS_LEN ( \ 138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 142 / sizeof(u64)) 143 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 144 IXGBE_PB_STATS_LEN + \ 145 IXGBE_QUEUE_STATS_LEN) 146 147 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 148 "Register test (offline)", "Eeprom test (offline)", 149 "Interrupt test (offline)", "Loopback test (offline)", 150 "Link test (on/offline)" 151 }; 152 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 153 154 static int ixgbe_get_settings(struct net_device *netdev, 155 struct ethtool_cmd *ecmd) 156 { 157 struct ixgbe_adapter *adapter = netdev_priv(netdev); 158 struct ixgbe_hw *hw = &adapter->hw; 159 ixgbe_link_speed supported_link; 160 u32 link_speed = 0; 161 bool autoneg = false; 162 bool link_up; 163 164 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 165 166 /* set the supported link speeds */ 167 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 168 ecmd->supported |= SUPPORTED_10000baseT_Full; 169 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 170 ecmd->supported |= SUPPORTED_1000baseT_Full; 171 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 172 ecmd->supported |= SUPPORTED_100baseT_Full; 173 174 /* set the advertised speeds */ 175 if (hw->phy.autoneg_advertised) { 176 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 177 ecmd->advertising |= ADVERTISED_100baseT_Full; 178 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 179 ecmd->advertising |= ADVERTISED_10000baseT_Full; 180 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 181 ecmd->advertising |= ADVERTISED_1000baseT_Full; 182 } else { 183 /* default modes in case phy.autoneg_advertised isn't set */ 184 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 185 ecmd->advertising |= ADVERTISED_10000baseT_Full; 186 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 187 ecmd->advertising |= ADVERTISED_1000baseT_Full; 188 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 189 ecmd->advertising |= ADVERTISED_100baseT_Full; 190 191 if (hw->phy.multispeed_fiber && !autoneg) { 192 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 193 ecmd->advertising = ADVERTISED_10000baseT_Full; 194 } 195 } 196 197 if (autoneg) { 198 ecmd->supported |= SUPPORTED_Autoneg; 199 ecmd->advertising |= ADVERTISED_Autoneg; 200 ecmd->autoneg = AUTONEG_ENABLE; 201 } else 202 ecmd->autoneg = AUTONEG_DISABLE; 203 204 ecmd->transceiver = XCVR_EXTERNAL; 205 206 /* Determine the remaining settings based on the PHY type. */ 207 switch (adapter->hw.phy.type) { 208 case ixgbe_phy_tn: 209 case ixgbe_phy_aq: 210 case ixgbe_phy_x550em_ext_t: 211 case ixgbe_phy_cu_unknown: 212 ecmd->supported |= SUPPORTED_TP; 213 ecmd->advertising |= ADVERTISED_TP; 214 ecmd->port = PORT_TP; 215 break; 216 case ixgbe_phy_qt: 217 ecmd->supported |= SUPPORTED_FIBRE; 218 ecmd->advertising |= ADVERTISED_FIBRE; 219 ecmd->port = PORT_FIBRE; 220 break; 221 case ixgbe_phy_nl: 222 case ixgbe_phy_sfp_passive_tyco: 223 case ixgbe_phy_sfp_passive_unknown: 224 case ixgbe_phy_sfp_ftl: 225 case ixgbe_phy_sfp_avago: 226 case ixgbe_phy_sfp_intel: 227 case ixgbe_phy_sfp_unknown: 228 /* SFP+ devices, further checking needed */ 229 switch (adapter->hw.phy.sfp_type) { 230 case ixgbe_sfp_type_da_cu: 231 case ixgbe_sfp_type_da_cu_core0: 232 case ixgbe_sfp_type_da_cu_core1: 233 ecmd->supported |= SUPPORTED_FIBRE; 234 ecmd->advertising |= ADVERTISED_FIBRE; 235 ecmd->port = PORT_DA; 236 break; 237 case ixgbe_sfp_type_sr: 238 case ixgbe_sfp_type_lr: 239 case ixgbe_sfp_type_srlr_core0: 240 case ixgbe_sfp_type_srlr_core1: 241 case ixgbe_sfp_type_1g_sx_core0: 242 case ixgbe_sfp_type_1g_sx_core1: 243 case ixgbe_sfp_type_1g_lx_core0: 244 case ixgbe_sfp_type_1g_lx_core1: 245 ecmd->supported |= SUPPORTED_FIBRE; 246 ecmd->advertising |= ADVERTISED_FIBRE; 247 ecmd->port = PORT_FIBRE; 248 break; 249 case ixgbe_sfp_type_not_present: 250 ecmd->supported |= SUPPORTED_FIBRE; 251 ecmd->advertising |= ADVERTISED_FIBRE; 252 ecmd->port = PORT_NONE; 253 break; 254 case ixgbe_sfp_type_1g_cu_core0: 255 case ixgbe_sfp_type_1g_cu_core1: 256 ecmd->supported |= SUPPORTED_TP; 257 ecmd->advertising |= ADVERTISED_TP; 258 ecmd->port = PORT_TP; 259 break; 260 case ixgbe_sfp_type_unknown: 261 default: 262 ecmd->supported |= SUPPORTED_FIBRE; 263 ecmd->advertising |= ADVERTISED_FIBRE; 264 ecmd->port = PORT_OTHER; 265 break; 266 } 267 break; 268 case ixgbe_phy_xaui: 269 ecmd->supported |= SUPPORTED_FIBRE; 270 ecmd->advertising |= ADVERTISED_FIBRE; 271 ecmd->port = PORT_NONE; 272 break; 273 case ixgbe_phy_unknown: 274 case ixgbe_phy_generic: 275 case ixgbe_phy_sfp_unsupported: 276 default: 277 ecmd->supported |= SUPPORTED_FIBRE; 278 ecmd->advertising |= ADVERTISED_FIBRE; 279 ecmd->port = PORT_OTHER; 280 break; 281 } 282 283 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 284 if (link_up) { 285 switch (link_speed) { 286 case IXGBE_LINK_SPEED_10GB_FULL: 287 ethtool_cmd_speed_set(ecmd, SPEED_10000); 288 break; 289 case IXGBE_LINK_SPEED_1GB_FULL: 290 ethtool_cmd_speed_set(ecmd, SPEED_1000); 291 break; 292 case IXGBE_LINK_SPEED_100_FULL: 293 ethtool_cmd_speed_set(ecmd, SPEED_100); 294 break; 295 default: 296 break; 297 } 298 ecmd->duplex = DUPLEX_FULL; 299 } else { 300 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); 301 ecmd->duplex = DUPLEX_UNKNOWN; 302 } 303 304 return 0; 305 } 306 307 static int ixgbe_set_settings(struct net_device *netdev, 308 struct ethtool_cmd *ecmd) 309 { 310 struct ixgbe_adapter *adapter = netdev_priv(netdev); 311 struct ixgbe_hw *hw = &adapter->hw; 312 u32 advertised, old; 313 s32 err = 0; 314 315 if ((hw->phy.media_type == ixgbe_media_type_copper) || 316 (hw->phy.multispeed_fiber)) { 317 /* 318 * this function does not support duplex forcing, but can 319 * limit the advertising of the adapter to the specified speed 320 */ 321 if (ecmd->advertising & ~ecmd->supported) 322 return -EINVAL; 323 324 /* only allow one speed at a time if no autoneg */ 325 if (!ecmd->autoneg && hw->phy.multispeed_fiber) { 326 if (ecmd->advertising == 327 (ADVERTISED_10000baseT_Full | 328 ADVERTISED_1000baseT_Full)) 329 return -EINVAL; 330 } 331 332 old = hw->phy.autoneg_advertised; 333 advertised = 0; 334 if (ecmd->advertising & ADVERTISED_10000baseT_Full) 335 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 336 337 if (ecmd->advertising & ADVERTISED_1000baseT_Full) 338 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 339 340 if (ecmd->advertising & ADVERTISED_100baseT_Full) 341 advertised |= IXGBE_LINK_SPEED_100_FULL; 342 343 if (old == advertised) 344 return err; 345 /* this sets the link speed and restarts auto-neg */ 346 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 347 usleep_range(1000, 2000); 348 349 hw->mac.autotry_restart = true; 350 err = hw->mac.ops.setup_link(hw, advertised, true); 351 if (err) { 352 e_info(probe, "setup link failed with code %d\n", err); 353 hw->mac.ops.setup_link(hw, old, true); 354 } 355 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 356 } else { 357 /* in this case we currently only support 10Gb/FULL */ 358 u32 speed = ethtool_cmd_speed(ecmd); 359 if ((ecmd->autoneg == AUTONEG_ENABLE) || 360 (ecmd->advertising != ADVERTISED_10000baseT_Full) || 361 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) 362 return -EINVAL; 363 } 364 365 return err; 366 } 367 368 static void ixgbe_get_pauseparam(struct net_device *netdev, 369 struct ethtool_pauseparam *pause) 370 { 371 struct ixgbe_adapter *adapter = netdev_priv(netdev); 372 struct ixgbe_hw *hw = &adapter->hw; 373 374 if (ixgbe_device_supports_autoneg_fc(hw) && 375 !hw->fc.disable_fc_autoneg) 376 pause->autoneg = 1; 377 else 378 pause->autoneg = 0; 379 380 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 381 pause->rx_pause = 1; 382 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 383 pause->tx_pause = 1; 384 } else if (hw->fc.current_mode == ixgbe_fc_full) { 385 pause->rx_pause = 1; 386 pause->tx_pause = 1; 387 } 388 } 389 390 static int ixgbe_set_pauseparam(struct net_device *netdev, 391 struct ethtool_pauseparam *pause) 392 { 393 struct ixgbe_adapter *adapter = netdev_priv(netdev); 394 struct ixgbe_hw *hw = &adapter->hw; 395 struct ixgbe_fc_info fc = hw->fc; 396 397 /* 82598 does no support link flow control with DCB enabled */ 398 if ((hw->mac.type == ixgbe_mac_82598EB) && 399 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 400 return -EINVAL; 401 402 /* some devices do not support autoneg of link flow control */ 403 if ((pause->autoneg == AUTONEG_ENABLE) && 404 !ixgbe_device_supports_autoneg_fc(hw)) 405 return -EINVAL; 406 407 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 408 409 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 410 fc.requested_mode = ixgbe_fc_full; 411 else if (pause->rx_pause && !pause->tx_pause) 412 fc.requested_mode = ixgbe_fc_rx_pause; 413 else if (!pause->rx_pause && pause->tx_pause) 414 fc.requested_mode = ixgbe_fc_tx_pause; 415 else 416 fc.requested_mode = ixgbe_fc_none; 417 418 /* if the thing changed then we'll update and use new autoneg */ 419 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 420 hw->fc = fc; 421 if (netif_running(netdev)) 422 ixgbe_reinit_locked(adapter); 423 else 424 ixgbe_reset(adapter); 425 } 426 427 return 0; 428 } 429 430 static u32 ixgbe_get_msglevel(struct net_device *netdev) 431 { 432 struct ixgbe_adapter *adapter = netdev_priv(netdev); 433 return adapter->msg_enable; 434 } 435 436 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 437 { 438 struct ixgbe_adapter *adapter = netdev_priv(netdev); 439 adapter->msg_enable = data; 440 } 441 442 static int ixgbe_get_regs_len(struct net_device *netdev) 443 { 444 #define IXGBE_REGS_LEN 1139 445 return IXGBE_REGS_LEN * sizeof(u32); 446 } 447 448 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 449 450 static void ixgbe_get_regs(struct net_device *netdev, 451 struct ethtool_regs *regs, void *p) 452 { 453 struct ixgbe_adapter *adapter = netdev_priv(netdev); 454 struct ixgbe_hw *hw = &adapter->hw; 455 u32 *regs_buff = p; 456 u8 i; 457 458 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 459 460 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 461 hw->device_id; 462 463 /* General Registers */ 464 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 465 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 466 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 467 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 468 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 469 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 470 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 471 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 472 473 /* NVM Register */ 474 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 475 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 476 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 477 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 478 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 479 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 480 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 481 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 482 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 483 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 484 485 /* Interrupt */ 486 /* don't read EICR because it can clear interrupt causes, instead 487 * read EICS which is a shadow but doesn't clear EICR */ 488 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 489 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 490 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 491 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 492 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 493 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 494 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 495 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 496 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 497 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 498 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 499 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 500 501 /* Flow Control */ 502 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 503 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); 504 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); 505 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); 506 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); 507 for (i = 0; i < 8; i++) { 508 switch (hw->mac.type) { 509 case ixgbe_mac_82598EB: 510 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 511 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 512 break; 513 case ixgbe_mac_82599EB: 514 case ixgbe_mac_X540: 515 case ixgbe_mac_X550: 516 case ixgbe_mac_X550EM_x: 517 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 518 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 519 break; 520 default: 521 break; 522 } 523 } 524 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 525 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 526 527 /* Receive DMA */ 528 for (i = 0; i < 64; i++) 529 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 530 for (i = 0; i < 64; i++) 531 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 532 for (i = 0; i < 64; i++) 533 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 534 for (i = 0; i < 64; i++) 535 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 536 for (i = 0; i < 64; i++) 537 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 538 for (i = 0; i < 64; i++) 539 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 540 for (i = 0; i < 16; i++) 541 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 542 for (i = 0; i < 16; i++) 543 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 544 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 545 for (i = 0; i < 8; i++) 546 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 547 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 548 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 549 550 /* Receive */ 551 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 552 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 553 for (i = 0; i < 16; i++) 554 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 555 for (i = 0; i < 16; i++) 556 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 557 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 558 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 559 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 560 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 561 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 562 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 563 for (i = 0; i < 8; i++) 564 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 565 for (i = 0; i < 8; i++) 566 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 567 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 568 569 /* Transmit */ 570 for (i = 0; i < 32; i++) 571 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 572 for (i = 0; i < 32; i++) 573 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 574 for (i = 0; i < 32; i++) 575 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 576 for (i = 0; i < 32; i++) 577 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 578 for (i = 0; i < 32; i++) 579 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 580 for (i = 0; i < 32; i++) 581 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 582 for (i = 0; i < 32; i++) 583 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 584 for (i = 0; i < 32; i++) 585 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 586 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 587 for (i = 0; i < 16; i++) 588 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 589 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 590 for (i = 0; i < 8; i++) 591 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 592 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 593 594 /* Wake Up */ 595 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 596 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 597 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 598 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 599 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 600 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 601 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 602 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 603 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 604 605 /* DCB */ 606 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 607 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 608 609 switch (hw->mac.type) { 610 case ixgbe_mac_82598EB: 611 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 612 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 613 for (i = 0; i < 8; i++) 614 regs_buff[833 + i] = 615 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 616 for (i = 0; i < 8; i++) 617 regs_buff[841 + i] = 618 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 619 for (i = 0; i < 8; i++) 620 regs_buff[849 + i] = 621 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 622 for (i = 0; i < 8; i++) 623 regs_buff[857 + i] = 624 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 625 break; 626 case ixgbe_mac_82599EB: 627 case ixgbe_mac_X540: 628 case ixgbe_mac_X550: 629 case ixgbe_mac_X550EM_x: 630 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 631 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 632 for (i = 0; i < 8; i++) 633 regs_buff[833 + i] = 634 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 635 for (i = 0; i < 8; i++) 636 regs_buff[841 + i] = 637 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 638 for (i = 0; i < 8; i++) 639 regs_buff[849 + i] = 640 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 641 for (i = 0; i < 8; i++) 642 regs_buff[857 + i] = 643 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 644 break; 645 default: 646 break; 647 } 648 649 for (i = 0; i < 8; i++) 650 regs_buff[865 + i] = 651 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 652 for (i = 0; i < 8; i++) 653 regs_buff[873 + i] = 654 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 655 656 /* Statistics */ 657 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 658 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 659 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 660 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 661 for (i = 0; i < 8; i++) 662 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 663 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 664 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 665 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 666 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 667 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 668 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 669 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 670 for (i = 0; i < 8; i++) 671 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 672 for (i = 0; i < 8; i++) 673 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 674 for (i = 0; i < 8; i++) 675 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 676 for (i = 0; i < 8; i++) 677 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 678 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 679 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 680 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 681 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 682 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 683 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 684 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 685 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 686 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 687 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 688 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc); 689 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc); 690 for (i = 0; i < 8; i++) 691 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 692 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 693 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 694 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 695 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 696 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 697 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 698 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 699 regs_buff[961] = IXGBE_GET_STAT(adapter, tor); 700 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 701 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 702 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 703 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 704 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 705 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 706 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 707 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 708 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 709 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 710 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 711 for (i = 0; i < 16; i++) 712 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 713 for (i = 0; i < 16; i++) 714 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 715 for (i = 0; i < 16; i++) 716 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 717 for (i = 0; i < 16; i++) 718 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 719 720 /* MAC */ 721 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 722 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 723 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 724 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 725 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 726 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 727 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 728 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 729 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 730 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 731 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 732 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 733 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 734 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 735 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 736 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 737 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 738 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 739 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 740 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 741 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 742 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 743 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 744 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 745 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 746 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 747 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 748 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 749 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 750 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 751 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 752 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 753 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 754 755 /* Diagnostic */ 756 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 757 for (i = 0; i < 8; i++) 758 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 759 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 760 for (i = 0; i < 4; i++) 761 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 762 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 763 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 764 for (i = 0; i < 8; i++) 765 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 766 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 767 for (i = 0; i < 4; i++) 768 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 769 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 770 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 771 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); 772 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); 773 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); 774 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); 775 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 776 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); 777 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); 778 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); 779 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); 780 for (i = 0; i < 8; i++) 781 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 782 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 783 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 784 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 785 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 786 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 787 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 788 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 789 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 790 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 791 792 /* 82599 X540 specific registers */ 793 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 794 795 /* 82599 X540 specific DCB registers */ 796 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 797 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 798 for (i = 0; i < 4; i++) 799 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 800 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 801 /* same as RTTQCNRM */ 802 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 803 /* same as RTTQCNRR */ 804 805 /* X540 specific DCB registers */ 806 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 807 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 808 } 809 810 static int ixgbe_get_eeprom_len(struct net_device *netdev) 811 { 812 struct ixgbe_adapter *adapter = netdev_priv(netdev); 813 return adapter->hw.eeprom.word_size * 2; 814 } 815 816 static int ixgbe_get_eeprom(struct net_device *netdev, 817 struct ethtool_eeprom *eeprom, u8 *bytes) 818 { 819 struct ixgbe_adapter *adapter = netdev_priv(netdev); 820 struct ixgbe_hw *hw = &adapter->hw; 821 u16 *eeprom_buff; 822 int first_word, last_word, eeprom_len; 823 int ret_val = 0; 824 u16 i; 825 826 if (eeprom->len == 0) 827 return -EINVAL; 828 829 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 830 831 first_word = eeprom->offset >> 1; 832 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 833 eeprom_len = last_word - first_word + 1; 834 835 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); 836 if (!eeprom_buff) 837 return -ENOMEM; 838 839 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 840 eeprom_buff); 841 842 /* Device's eeprom is always little-endian, word addressable */ 843 for (i = 0; i < eeprom_len; i++) 844 le16_to_cpus(&eeprom_buff[i]); 845 846 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 847 kfree(eeprom_buff); 848 849 return ret_val; 850 } 851 852 static int ixgbe_set_eeprom(struct net_device *netdev, 853 struct ethtool_eeprom *eeprom, u8 *bytes) 854 { 855 struct ixgbe_adapter *adapter = netdev_priv(netdev); 856 struct ixgbe_hw *hw = &adapter->hw; 857 u16 *eeprom_buff; 858 void *ptr; 859 int max_len, first_word, last_word, ret_val = 0; 860 u16 i; 861 862 if (eeprom->len == 0) 863 return -EINVAL; 864 865 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 866 return -EINVAL; 867 868 max_len = hw->eeprom.word_size * 2; 869 870 first_word = eeprom->offset >> 1; 871 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 872 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 873 if (!eeprom_buff) 874 return -ENOMEM; 875 876 ptr = eeprom_buff; 877 878 if (eeprom->offset & 1) { 879 /* 880 * need read/modify/write of first changed EEPROM word 881 * only the second byte of the word is being modified 882 */ 883 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 884 if (ret_val) 885 goto err; 886 887 ptr++; 888 } 889 if ((eeprom->offset + eeprom->len) & 1) { 890 /* 891 * need read/modify/write of last changed EEPROM word 892 * only the first byte of the word is being modified 893 */ 894 ret_val = hw->eeprom.ops.read(hw, last_word, 895 &eeprom_buff[last_word - first_word]); 896 if (ret_val) 897 goto err; 898 } 899 900 /* Device's eeprom is always little-endian, word addressable */ 901 for (i = 0; i < last_word - first_word + 1; i++) 902 le16_to_cpus(&eeprom_buff[i]); 903 904 memcpy(ptr, bytes, eeprom->len); 905 906 for (i = 0; i < last_word - first_word + 1; i++) 907 cpu_to_le16s(&eeprom_buff[i]); 908 909 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 910 last_word - first_word + 1, 911 eeprom_buff); 912 913 /* Update the checksum */ 914 if (ret_val == 0) 915 hw->eeprom.ops.update_checksum(hw); 916 917 err: 918 kfree(eeprom_buff); 919 return ret_val; 920 } 921 922 static void ixgbe_get_drvinfo(struct net_device *netdev, 923 struct ethtool_drvinfo *drvinfo) 924 { 925 struct ixgbe_adapter *adapter = netdev_priv(netdev); 926 u32 nvm_track_id; 927 928 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 929 strlcpy(drvinfo->version, ixgbe_driver_version, 930 sizeof(drvinfo->version)); 931 932 nvm_track_id = (adapter->eeprom_verh << 16) | 933 adapter->eeprom_verl; 934 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x", 935 nvm_track_id); 936 937 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 938 sizeof(drvinfo->bus_info)); 939 drvinfo->n_stats = IXGBE_STATS_LEN; 940 drvinfo->testinfo_len = IXGBE_TEST_LEN; 941 drvinfo->regdump_len = ixgbe_get_regs_len(netdev); 942 } 943 944 static void ixgbe_get_ringparam(struct net_device *netdev, 945 struct ethtool_ringparam *ring) 946 { 947 struct ixgbe_adapter *adapter = netdev_priv(netdev); 948 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 949 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 950 951 ring->rx_max_pending = IXGBE_MAX_RXD; 952 ring->tx_max_pending = IXGBE_MAX_TXD; 953 ring->rx_pending = rx_ring->count; 954 ring->tx_pending = tx_ring->count; 955 } 956 957 static int ixgbe_set_ringparam(struct net_device *netdev, 958 struct ethtool_ringparam *ring) 959 { 960 struct ixgbe_adapter *adapter = netdev_priv(netdev); 961 struct ixgbe_ring *temp_ring; 962 int i, err = 0; 963 u32 new_rx_count, new_tx_count; 964 965 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 966 return -EINVAL; 967 968 new_tx_count = clamp_t(u32, ring->tx_pending, 969 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 970 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 971 972 new_rx_count = clamp_t(u32, ring->rx_pending, 973 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 974 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 975 976 if ((new_tx_count == adapter->tx_ring_count) && 977 (new_rx_count == adapter->rx_ring_count)) { 978 /* nothing to do */ 979 return 0; 980 } 981 982 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 983 usleep_range(1000, 2000); 984 985 if (!netif_running(adapter->netdev)) { 986 for (i = 0; i < adapter->num_tx_queues; i++) 987 adapter->tx_ring[i]->count = new_tx_count; 988 for (i = 0; i < adapter->num_rx_queues; i++) 989 adapter->rx_ring[i]->count = new_rx_count; 990 adapter->tx_ring_count = new_tx_count; 991 adapter->rx_ring_count = new_rx_count; 992 goto clear_reset; 993 } 994 995 /* allocate temporary buffer to store rings in */ 996 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues); 997 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring)); 998 999 if (!temp_ring) { 1000 err = -ENOMEM; 1001 goto clear_reset; 1002 } 1003 1004 ixgbe_down(adapter); 1005 1006 /* 1007 * Setup new Tx resources and free the old Tx resources in that order. 1008 * We can then assign the new resources to the rings via a memcpy. 1009 * The advantage to this approach is that we are guaranteed to still 1010 * have resources even in the case of an allocation failure. 1011 */ 1012 if (new_tx_count != adapter->tx_ring_count) { 1013 for (i = 0; i < adapter->num_tx_queues; i++) { 1014 memcpy(&temp_ring[i], adapter->tx_ring[i], 1015 sizeof(struct ixgbe_ring)); 1016 1017 temp_ring[i].count = new_tx_count; 1018 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1019 if (err) { 1020 while (i) { 1021 i--; 1022 ixgbe_free_tx_resources(&temp_ring[i]); 1023 } 1024 goto err_setup; 1025 } 1026 } 1027 1028 for (i = 0; i < adapter->num_tx_queues; i++) { 1029 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1030 1031 memcpy(adapter->tx_ring[i], &temp_ring[i], 1032 sizeof(struct ixgbe_ring)); 1033 } 1034 1035 adapter->tx_ring_count = new_tx_count; 1036 } 1037 1038 /* Repeat the process for the Rx rings if needed */ 1039 if (new_rx_count != adapter->rx_ring_count) { 1040 for (i = 0; i < adapter->num_rx_queues; i++) { 1041 memcpy(&temp_ring[i], adapter->rx_ring[i], 1042 sizeof(struct ixgbe_ring)); 1043 1044 temp_ring[i].count = new_rx_count; 1045 err = ixgbe_setup_rx_resources(&temp_ring[i]); 1046 if (err) { 1047 while (i) { 1048 i--; 1049 ixgbe_free_rx_resources(&temp_ring[i]); 1050 } 1051 goto err_setup; 1052 } 1053 1054 } 1055 1056 for (i = 0; i < adapter->num_rx_queues; i++) { 1057 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1058 1059 memcpy(adapter->rx_ring[i], &temp_ring[i], 1060 sizeof(struct ixgbe_ring)); 1061 } 1062 1063 adapter->rx_ring_count = new_rx_count; 1064 } 1065 1066 err_setup: 1067 ixgbe_up(adapter); 1068 vfree(temp_ring); 1069 clear_reset: 1070 clear_bit(__IXGBE_RESETTING, &adapter->state); 1071 return err; 1072 } 1073 1074 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1075 { 1076 switch (sset) { 1077 case ETH_SS_TEST: 1078 return IXGBE_TEST_LEN; 1079 case ETH_SS_STATS: 1080 return IXGBE_STATS_LEN; 1081 default: 1082 return -EOPNOTSUPP; 1083 } 1084 } 1085 1086 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1087 struct ethtool_stats *stats, u64 *data) 1088 { 1089 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1090 struct rtnl_link_stats64 temp; 1091 const struct rtnl_link_stats64 *net_stats; 1092 unsigned int start; 1093 struct ixgbe_ring *ring; 1094 int i, j; 1095 char *p = NULL; 1096 1097 ixgbe_update_stats(adapter); 1098 net_stats = dev_get_stats(netdev, &temp); 1099 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1100 switch (ixgbe_gstrings_stats[i].type) { 1101 case NETDEV_STATS: 1102 p = (char *) net_stats + 1103 ixgbe_gstrings_stats[i].stat_offset; 1104 break; 1105 case IXGBE_STATS: 1106 p = (char *) adapter + 1107 ixgbe_gstrings_stats[i].stat_offset; 1108 break; 1109 default: 1110 data[i] = 0; 1111 continue; 1112 } 1113 1114 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1115 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1116 } 1117 for (j = 0; j < netdev->num_tx_queues; j++) { 1118 ring = adapter->tx_ring[j]; 1119 if (!ring) { 1120 data[i] = 0; 1121 data[i+1] = 0; 1122 i += 2; 1123 #ifdef BP_EXTENDED_STATS 1124 data[i] = 0; 1125 data[i+1] = 0; 1126 data[i+2] = 0; 1127 i += 3; 1128 #endif 1129 continue; 1130 } 1131 1132 do { 1133 start = u64_stats_fetch_begin_irq(&ring->syncp); 1134 data[i] = ring->stats.packets; 1135 data[i+1] = ring->stats.bytes; 1136 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1137 i += 2; 1138 #ifdef BP_EXTENDED_STATS 1139 data[i] = ring->stats.yields; 1140 data[i+1] = ring->stats.misses; 1141 data[i+2] = ring->stats.cleaned; 1142 i += 3; 1143 #endif 1144 } 1145 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1146 ring = adapter->rx_ring[j]; 1147 if (!ring) { 1148 data[i] = 0; 1149 data[i+1] = 0; 1150 i += 2; 1151 #ifdef BP_EXTENDED_STATS 1152 data[i] = 0; 1153 data[i+1] = 0; 1154 data[i+2] = 0; 1155 i += 3; 1156 #endif 1157 continue; 1158 } 1159 1160 do { 1161 start = u64_stats_fetch_begin_irq(&ring->syncp); 1162 data[i] = ring->stats.packets; 1163 data[i+1] = ring->stats.bytes; 1164 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1165 i += 2; 1166 #ifdef BP_EXTENDED_STATS 1167 data[i] = ring->stats.yields; 1168 data[i+1] = ring->stats.misses; 1169 data[i+2] = ring->stats.cleaned; 1170 i += 3; 1171 #endif 1172 } 1173 1174 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1175 data[i++] = adapter->stats.pxontxc[j]; 1176 data[i++] = adapter->stats.pxofftxc[j]; 1177 } 1178 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1179 data[i++] = adapter->stats.pxonrxc[j]; 1180 data[i++] = adapter->stats.pxoffrxc[j]; 1181 } 1182 } 1183 1184 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1185 u8 *data) 1186 { 1187 char *p = (char *)data; 1188 int i; 1189 1190 switch (stringset) { 1191 case ETH_SS_TEST: 1192 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1193 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1194 data += ETH_GSTRING_LEN; 1195 } 1196 break; 1197 case ETH_SS_STATS: 1198 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1199 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1200 ETH_GSTRING_LEN); 1201 p += ETH_GSTRING_LEN; 1202 } 1203 for (i = 0; i < netdev->num_tx_queues; i++) { 1204 sprintf(p, "tx_queue_%u_packets", i); 1205 p += ETH_GSTRING_LEN; 1206 sprintf(p, "tx_queue_%u_bytes", i); 1207 p += ETH_GSTRING_LEN; 1208 #ifdef BP_EXTENDED_STATS 1209 sprintf(p, "tx_queue_%u_bp_napi_yield", i); 1210 p += ETH_GSTRING_LEN; 1211 sprintf(p, "tx_queue_%u_bp_misses", i); 1212 p += ETH_GSTRING_LEN; 1213 sprintf(p, "tx_queue_%u_bp_cleaned", i); 1214 p += ETH_GSTRING_LEN; 1215 #endif /* BP_EXTENDED_STATS */ 1216 } 1217 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1218 sprintf(p, "rx_queue_%u_packets", i); 1219 p += ETH_GSTRING_LEN; 1220 sprintf(p, "rx_queue_%u_bytes", i); 1221 p += ETH_GSTRING_LEN; 1222 #ifdef BP_EXTENDED_STATS 1223 sprintf(p, "rx_queue_%u_bp_poll_yield", i); 1224 p += ETH_GSTRING_LEN; 1225 sprintf(p, "rx_queue_%u_bp_misses", i); 1226 p += ETH_GSTRING_LEN; 1227 sprintf(p, "rx_queue_%u_bp_cleaned", i); 1228 p += ETH_GSTRING_LEN; 1229 #endif /* BP_EXTENDED_STATS */ 1230 } 1231 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1232 sprintf(p, "tx_pb_%u_pxon", i); 1233 p += ETH_GSTRING_LEN; 1234 sprintf(p, "tx_pb_%u_pxoff", i); 1235 p += ETH_GSTRING_LEN; 1236 } 1237 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1238 sprintf(p, "rx_pb_%u_pxon", i); 1239 p += ETH_GSTRING_LEN; 1240 sprintf(p, "rx_pb_%u_pxoff", i); 1241 p += ETH_GSTRING_LEN; 1242 } 1243 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1244 break; 1245 } 1246 } 1247 1248 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1249 { 1250 struct ixgbe_hw *hw = &adapter->hw; 1251 bool link_up; 1252 u32 link_speed = 0; 1253 1254 if (ixgbe_removed(hw->hw_addr)) { 1255 *data = 1; 1256 return 1; 1257 } 1258 *data = 0; 1259 1260 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1261 if (link_up) 1262 return *data; 1263 else 1264 *data = 1; 1265 return *data; 1266 } 1267 1268 /* ethtool register test data */ 1269 struct ixgbe_reg_test { 1270 u16 reg; 1271 u8 array_len; 1272 u8 test_type; 1273 u32 mask; 1274 u32 write; 1275 }; 1276 1277 /* In the hardware, registers are laid out either singly, in arrays 1278 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1279 * most tests take place on arrays or single registers (handled 1280 * as a single-element array) and special-case the tables. 1281 * Table tests are always pattern tests. 1282 * 1283 * We also make provision for some required setup steps by specifying 1284 * registers to be written without any read-back testing. 1285 */ 1286 1287 #define PATTERN_TEST 1 1288 #define SET_READ_TEST 2 1289 #define WRITE_NO_TEST 3 1290 #define TABLE32_TEST 4 1291 #define TABLE64_TEST_LO 5 1292 #define TABLE64_TEST_HI 6 1293 1294 /* default 82599 register test */ 1295 static const struct ixgbe_reg_test reg_test_82599[] = { 1296 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1297 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1298 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1299 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1300 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1301 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1302 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1303 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1304 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1305 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1306 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1307 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1308 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1309 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1310 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1311 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1312 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1313 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1314 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1315 { .reg = 0 } 1316 }; 1317 1318 /* default 82598 register test */ 1319 static const struct ixgbe_reg_test reg_test_82598[] = { 1320 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1321 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1322 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1323 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1324 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1325 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1326 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1327 /* Enable all four RX queues before testing. */ 1328 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1329 /* RDH is read-only for 82598, only test RDT. */ 1330 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1331 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1332 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1333 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1334 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1335 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1336 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1337 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1338 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1339 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1340 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1341 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1342 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1343 { .reg = 0 } 1344 }; 1345 1346 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1347 u32 mask, u32 write) 1348 { 1349 u32 pat, val, before; 1350 static const u32 test_pattern[] = { 1351 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1352 1353 if (ixgbe_removed(adapter->hw.hw_addr)) { 1354 *data = 1; 1355 return true; 1356 } 1357 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1358 before = ixgbe_read_reg(&adapter->hw, reg); 1359 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1360 val = ixgbe_read_reg(&adapter->hw, reg); 1361 if (val != (test_pattern[pat] & write & mask)) { 1362 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1363 reg, val, (test_pattern[pat] & write & mask)); 1364 *data = reg; 1365 ixgbe_write_reg(&adapter->hw, reg, before); 1366 return true; 1367 } 1368 ixgbe_write_reg(&adapter->hw, reg, before); 1369 } 1370 return false; 1371 } 1372 1373 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1374 u32 mask, u32 write) 1375 { 1376 u32 val, before; 1377 1378 if (ixgbe_removed(adapter->hw.hw_addr)) { 1379 *data = 1; 1380 return true; 1381 } 1382 before = ixgbe_read_reg(&adapter->hw, reg); 1383 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1384 val = ixgbe_read_reg(&adapter->hw, reg); 1385 if ((write & mask) != (val & mask)) { 1386 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1387 reg, (val & mask), (write & mask)); 1388 *data = reg; 1389 ixgbe_write_reg(&adapter->hw, reg, before); 1390 return true; 1391 } 1392 ixgbe_write_reg(&adapter->hw, reg, before); 1393 return false; 1394 } 1395 1396 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1397 { 1398 const struct ixgbe_reg_test *test; 1399 u32 value, before, after; 1400 u32 i, toggle; 1401 1402 if (ixgbe_removed(adapter->hw.hw_addr)) { 1403 e_err(drv, "Adapter removed - register test blocked\n"); 1404 *data = 1; 1405 return 1; 1406 } 1407 switch (adapter->hw.mac.type) { 1408 case ixgbe_mac_82598EB: 1409 toggle = 0x7FFFF3FF; 1410 test = reg_test_82598; 1411 break; 1412 case ixgbe_mac_82599EB: 1413 case ixgbe_mac_X540: 1414 case ixgbe_mac_X550: 1415 case ixgbe_mac_X550EM_x: 1416 toggle = 0x7FFFF30F; 1417 test = reg_test_82599; 1418 break; 1419 default: 1420 *data = 1; 1421 return 1; 1422 } 1423 1424 /* 1425 * Because the status register is such a special case, 1426 * we handle it separately from the rest of the register 1427 * tests. Some bits are read-only, some toggle, and some 1428 * are writeable on newer MACs. 1429 */ 1430 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1431 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1432 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1433 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1434 if (value != after) { 1435 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1436 after, value); 1437 *data = 1; 1438 return 1; 1439 } 1440 /* restore previous status */ 1441 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1442 1443 /* 1444 * Perform the remainder of the register test, looping through 1445 * the test table until we either fail or reach the null entry. 1446 */ 1447 while (test->reg) { 1448 for (i = 0; i < test->array_len; i++) { 1449 bool b = false; 1450 1451 switch (test->test_type) { 1452 case PATTERN_TEST: 1453 b = reg_pattern_test(adapter, data, 1454 test->reg + (i * 0x40), 1455 test->mask, 1456 test->write); 1457 break; 1458 case SET_READ_TEST: 1459 b = reg_set_and_check(adapter, data, 1460 test->reg + (i * 0x40), 1461 test->mask, 1462 test->write); 1463 break; 1464 case WRITE_NO_TEST: 1465 ixgbe_write_reg(&adapter->hw, 1466 test->reg + (i * 0x40), 1467 test->write); 1468 break; 1469 case TABLE32_TEST: 1470 b = reg_pattern_test(adapter, data, 1471 test->reg + (i * 4), 1472 test->mask, 1473 test->write); 1474 break; 1475 case TABLE64_TEST_LO: 1476 b = reg_pattern_test(adapter, data, 1477 test->reg + (i * 8), 1478 test->mask, 1479 test->write); 1480 break; 1481 case TABLE64_TEST_HI: 1482 b = reg_pattern_test(adapter, data, 1483 (test->reg + 4) + (i * 8), 1484 test->mask, 1485 test->write); 1486 break; 1487 } 1488 if (b) 1489 return 1; 1490 } 1491 test++; 1492 } 1493 1494 *data = 0; 1495 return 0; 1496 } 1497 1498 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1499 { 1500 struct ixgbe_hw *hw = &adapter->hw; 1501 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1502 *data = 1; 1503 else 1504 *data = 0; 1505 return *data; 1506 } 1507 1508 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1509 { 1510 struct net_device *netdev = (struct net_device *) data; 1511 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1512 1513 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1514 1515 return IRQ_HANDLED; 1516 } 1517 1518 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1519 { 1520 struct net_device *netdev = adapter->netdev; 1521 u32 mask, i = 0, shared_int = true; 1522 u32 irq = adapter->pdev->irq; 1523 1524 *data = 0; 1525 1526 /* Hook up test interrupt handler just for this test */ 1527 if (adapter->msix_entries) { 1528 /* NOTE: we don't test MSI-X interrupts here, yet */ 1529 return 0; 1530 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1531 shared_int = false; 1532 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1533 netdev)) { 1534 *data = 1; 1535 return -1; 1536 } 1537 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1538 netdev->name, netdev)) { 1539 shared_int = false; 1540 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1541 netdev->name, netdev)) { 1542 *data = 1; 1543 return -1; 1544 } 1545 e_info(hw, "testing %s interrupt\n", shared_int ? 1546 "shared" : "unshared"); 1547 1548 /* Disable all the interrupts */ 1549 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1550 IXGBE_WRITE_FLUSH(&adapter->hw); 1551 usleep_range(10000, 20000); 1552 1553 /* Test each interrupt */ 1554 for (; i < 10; i++) { 1555 /* Interrupt to test */ 1556 mask = 1 << i; 1557 1558 if (!shared_int) { 1559 /* 1560 * Disable the interrupts to be reported in 1561 * the cause register and then force the same 1562 * interrupt and see if one gets posted. If 1563 * an interrupt was posted to the bus, the 1564 * test failed. 1565 */ 1566 adapter->test_icr = 0; 1567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1568 ~mask & 0x00007FFF); 1569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1570 ~mask & 0x00007FFF); 1571 IXGBE_WRITE_FLUSH(&adapter->hw); 1572 usleep_range(10000, 20000); 1573 1574 if (adapter->test_icr & mask) { 1575 *data = 3; 1576 break; 1577 } 1578 } 1579 1580 /* 1581 * Enable the interrupt to be reported in the cause 1582 * register and then force the same interrupt and see 1583 * if one gets posted. If an interrupt was not posted 1584 * to the bus, the test failed. 1585 */ 1586 adapter->test_icr = 0; 1587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1589 IXGBE_WRITE_FLUSH(&adapter->hw); 1590 usleep_range(10000, 20000); 1591 1592 if (!(adapter->test_icr & mask)) { 1593 *data = 4; 1594 break; 1595 } 1596 1597 if (!shared_int) { 1598 /* 1599 * Disable the other interrupts to be reported in 1600 * the cause register and then force the other 1601 * interrupts and see if any get posted. If 1602 * an interrupt was posted to the bus, the 1603 * test failed. 1604 */ 1605 adapter->test_icr = 0; 1606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1607 ~mask & 0x00007FFF); 1608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1609 ~mask & 0x00007FFF); 1610 IXGBE_WRITE_FLUSH(&adapter->hw); 1611 usleep_range(10000, 20000); 1612 1613 if (adapter->test_icr) { 1614 *data = 5; 1615 break; 1616 } 1617 } 1618 } 1619 1620 /* Disable all the interrupts */ 1621 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1622 IXGBE_WRITE_FLUSH(&adapter->hw); 1623 usleep_range(10000, 20000); 1624 1625 /* Unhook test interrupt handler */ 1626 free_irq(irq, netdev); 1627 1628 return *data; 1629 } 1630 1631 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1632 { 1633 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1634 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1635 struct ixgbe_hw *hw = &adapter->hw; 1636 u32 reg_ctl; 1637 1638 /* shut down the DMA engines now so they can be reinitialized later */ 1639 1640 /* first Rx */ 1641 hw->mac.ops.disable_rx(hw); 1642 ixgbe_disable_rx_queue(adapter, rx_ring); 1643 1644 /* now Tx */ 1645 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); 1646 reg_ctl &= ~IXGBE_TXDCTL_ENABLE; 1647 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); 1648 1649 switch (hw->mac.type) { 1650 case ixgbe_mac_82599EB: 1651 case ixgbe_mac_X540: 1652 case ixgbe_mac_X550: 1653 case ixgbe_mac_X550EM_x: 1654 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1655 reg_ctl &= ~IXGBE_DMATXCTL_TE; 1656 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); 1657 break; 1658 default: 1659 break; 1660 } 1661 1662 ixgbe_reset(adapter); 1663 1664 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1665 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1666 } 1667 1668 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1669 { 1670 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1671 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1672 struct ixgbe_hw *hw = &adapter->hw; 1673 u32 rctl, reg_data; 1674 int ret_val; 1675 int err; 1676 1677 /* Setup Tx descriptor ring and Tx buffers */ 1678 tx_ring->count = IXGBE_DEFAULT_TXD; 1679 tx_ring->queue_index = 0; 1680 tx_ring->dev = &adapter->pdev->dev; 1681 tx_ring->netdev = adapter->netdev; 1682 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1683 1684 err = ixgbe_setup_tx_resources(tx_ring); 1685 if (err) 1686 return 1; 1687 1688 switch (adapter->hw.mac.type) { 1689 case ixgbe_mac_82599EB: 1690 case ixgbe_mac_X540: 1691 case ixgbe_mac_X550: 1692 case ixgbe_mac_X550EM_x: 1693 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1694 reg_data |= IXGBE_DMATXCTL_TE; 1695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1696 break; 1697 default: 1698 break; 1699 } 1700 1701 ixgbe_configure_tx_ring(adapter, tx_ring); 1702 1703 /* Setup Rx Descriptor ring and Rx buffers */ 1704 rx_ring->count = IXGBE_DEFAULT_RXD; 1705 rx_ring->queue_index = 0; 1706 rx_ring->dev = &adapter->pdev->dev; 1707 rx_ring->netdev = adapter->netdev; 1708 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1709 1710 err = ixgbe_setup_rx_resources(rx_ring); 1711 if (err) { 1712 ret_val = 4; 1713 goto err_nomem; 1714 } 1715 1716 hw->mac.ops.disable_rx(hw); 1717 1718 ixgbe_configure_rx_ring(adapter, rx_ring); 1719 1720 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1721 rctl |= IXGBE_RXCTRL_DMBYPS; 1722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1723 1724 hw->mac.ops.enable_rx(hw); 1725 1726 return 0; 1727 1728 err_nomem: 1729 ixgbe_free_desc_rings(adapter); 1730 return ret_val; 1731 } 1732 1733 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1734 { 1735 struct ixgbe_hw *hw = &adapter->hw; 1736 u32 reg_data; 1737 1738 1739 /* Setup MAC loopback */ 1740 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1741 reg_data |= IXGBE_HLREG0_LPBK; 1742 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1743 1744 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1745 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1746 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1747 1748 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1749 switch (adapter->hw.mac.type) { 1750 case ixgbe_mac_X540: 1751 case ixgbe_mac_X550: 1752 case ixgbe_mac_X550EM_x: 1753 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1754 reg_data |= IXGBE_MACC_FLU; 1755 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1756 break; 1757 default: 1758 if (hw->mac.orig_autoc) { 1759 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1760 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1761 } else { 1762 return 10; 1763 } 1764 } 1765 IXGBE_WRITE_FLUSH(hw); 1766 usleep_range(10000, 20000); 1767 1768 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1769 if (hw->mac.type == ixgbe_mac_82598EB) { 1770 u8 atlas; 1771 1772 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1773 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1774 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1775 1776 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1777 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1778 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1779 1780 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1781 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1782 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1783 1784 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1785 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1786 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1787 } 1788 1789 return 0; 1790 } 1791 1792 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1793 { 1794 u32 reg_data; 1795 1796 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1797 reg_data &= ~IXGBE_HLREG0_LPBK; 1798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1799 } 1800 1801 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1802 unsigned int frame_size) 1803 { 1804 memset(skb->data, 0xFF, frame_size); 1805 frame_size >>= 1; 1806 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1807 memset(&skb->data[frame_size + 10], 0xBE, 1); 1808 memset(&skb->data[frame_size + 12], 0xAF, 1); 1809 } 1810 1811 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1812 unsigned int frame_size) 1813 { 1814 unsigned char *data; 1815 bool match = true; 1816 1817 frame_size >>= 1; 1818 1819 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1820 1821 if (data[3] != 0xFF || 1822 data[frame_size + 10] != 0xBE || 1823 data[frame_size + 12] != 0xAF) 1824 match = false; 1825 1826 kunmap(rx_buffer->page); 1827 1828 return match; 1829 } 1830 1831 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1832 struct ixgbe_ring *tx_ring, 1833 unsigned int size) 1834 { 1835 union ixgbe_adv_rx_desc *rx_desc; 1836 struct ixgbe_rx_buffer *rx_buffer; 1837 struct ixgbe_tx_buffer *tx_buffer; 1838 u16 rx_ntc, tx_ntc, count = 0; 1839 1840 /* initialize next to clean and descriptor values */ 1841 rx_ntc = rx_ring->next_to_clean; 1842 tx_ntc = tx_ring->next_to_clean; 1843 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1844 1845 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) { 1846 /* check Rx buffer */ 1847 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 1848 1849 /* sync Rx buffer for CPU read */ 1850 dma_sync_single_for_cpu(rx_ring->dev, 1851 rx_buffer->dma, 1852 ixgbe_rx_bufsz(rx_ring), 1853 DMA_FROM_DEVICE); 1854 1855 /* verify contents of skb */ 1856 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 1857 count++; 1858 1859 /* sync Rx buffer for device write */ 1860 dma_sync_single_for_device(rx_ring->dev, 1861 rx_buffer->dma, 1862 ixgbe_rx_bufsz(rx_ring), 1863 DMA_FROM_DEVICE); 1864 1865 /* unmap buffer on Tx side */ 1866 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1867 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 1868 1869 /* increment Rx/Tx next to clean counters */ 1870 rx_ntc++; 1871 if (rx_ntc == rx_ring->count) 1872 rx_ntc = 0; 1873 tx_ntc++; 1874 if (tx_ntc == tx_ring->count) 1875 tx_ntc = 0; 1876 1877 /* fetch next descriptor */ 1878 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1879 } 1880 1881 netdev_tx_reset_queue(txring_txq(tx_ring)); 1882 1883 /* re-map buffers to ring, store next to clean values */ 1884 ixgbe_alloc_rx_buffers(rx_ring, count); 1885 rx_ring->next_to_clean = rx_ntc; 1886 tx_ring->next_to_clean = tx_ntc; 1887 1888 return count; 1889 } 1890 1891 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1892 { 1893 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1894 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1895 int i, j, lc, good_cnt, ret_val = 0; 1896 unsigned int size = 1024; 1897 netdev_tx_t tx_ret_val; 1898 struct sk_buff *skb; 1899 u32 flags_orig = adapter->flags; 1900 1901 /* DCB can modify the frames on Tx */ 1902 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1903 1904 /* allocate test skb */ 1905 skb = alloc_skb(size, GFP_KERNEL); 1906 if (!skb) 1907 return 11; 1908 1909 /* place data into test skb */ 1910 ixgbe_create_lbtest_frame(skb, size); 1911 skb_put(skb, size); 1912 1913 /* 1914 * Calculate the loop count based on the largest descriptor ring 1915 * The idea is to wrap the largest ring a number of times using 64 1916 * send/receive pairs during each loop 1917 */ 1918 1919 if (rx_ring->count <= tx_ring->count) 1920 lc = ((tx_ring->count / 64) * 2) + 1; 1921 else 1922 lc = ((rx_ring->count / 64) * 2) + 1; 1923 1924 for (j = 0; j <= lc; j++) { 1925 /* reset count of good packets */ 1926 good_cnt = 0; 1927 1928 /* place 64 packets on the transmit queue*/ 1929 for (i = 0; i < 64; i++) { 1930 skb_get(skb); 1931 tx_ret_val = ixgbe_xmit_frame_ring(skb, 1932 adapter, 1933 tx_ring); 1934 if (tx_ret_val == NETDEV_TX_OK) 1935 good_cnt++; 1936 } 1937 1938 if (good_cnt != 64) { 1939 ret_val = 12; 1940 break; 1941 } 1942 1943 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1944 msleep(200); 1945 1946 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 1947 if (good_cnt != 64) { 1948 ret_val = 13; 1949 break; 1950 } 1951 } 1952 1953 /* free the original skb */ 1954 kfree_skb(skb); 1955 adapter->flags = flags_orig; 1956 1957 return ret_val; 1958 } 1959 1960 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 1961 { 1962 *data = ixgbe_setup_desc_rings(adapter); 1963 if (*data) 1964 goto out; 1965 *data = ixgbe_setup_loopback_test(adapter); 1966 if (*data) 1967 goto err_loopback; 1968 *data = ixgbe_run_loopback_test(adapter); 1969 ixgbe_loopback_cleanup(adapter); 1970 1971 err_loopback: 1972 ixgbe_free_desc_rings(adapter); 1973 out: 1974 return *data; 1975 } 1976 1977 static void ixgbe_diag_test(struct net_device *netdev, 1978 struct ethtool_test *eth_test, u64 *data) 1979 { 1980 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1981 bool if_running = netif_running(netdev); 1982 1983 if (ixgbe_removed(adapter->hw.hw_addr)) { 1984 e_err(hw, "Adapter removed - test blocked\n"); 1985 data[0] = 1; 1986 data[1] = 1; 1987 data[2] = 1; 1988 data[3] = 1; 1989 data[4] = 1; 1990 eth_test->flags |= ETH_TEST_FL_FAILED; 1991 return; 1992 } 1993 set_bit(__IXGBE_TESTING, &adapter->state); 1994 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1995 struct ixgbe_hw *hw = &adapter->hw; 1996 1997 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 1998 int i; 1999 for (i = 0; i < adapter->num_vfs; i++) { 2000 if (adapter->vfinfo[i].clear_to_send) { 2001 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2002 data[0] = 1; 2003 data[1] = 1; 2004 data[2] = 1; 2005 data[3] = 1; 2006 data[4] = 1; 2007 eth_test->flags |= ETH_TEST_FL_FAILED; 2008 clear_bit(__IXGBE_TESTING, 2009 &adapter->state); 2010 goto skip_ol_tests; 2011 } 2012 } 2013 } 2014 2015 /* Offline tests */ 2016 e_info(hw, "offline testing starting\n"); 2017 2018 /* Link test performed before hardware reset so autoneg doesn't 2019 * interfere with test result 2020 */ 2021 if (ixgbe_link_test(adapter, &data[4])) 2022 eth_test->flags |= ETH_TEST_FL_FAILED; 2023 2024 if (if_running) 2025 /* indicate we're in test mode */ 2026 dev_close(netdev); 2027 else 2028 ixgbe_reset(adapter); 2029 2030 e_info(hw, "register testing starting\n"); 2031 if (ixgbe_reg_test(adapter, &data[0])) 2032 eth_test->flags |= ETH_TEST_FL_FAILED; 2033 2034 ixgbe_reset(adapter); 2035 e_info(hw, "eeprom testing starting\n"); 2036 if (ixgbe_eeprom_test(adapter, &data[1])) 2037 eth_test->flags |= ETH_TEST_FL_FAILED; 2038 2039 ixgbe_reset(adapter); 2040 e_info(hw, "interrupt testing starting\n"); 2041 if (ixgbe_intr_test(adapter, &data[2])) 2042 eth_test->flags |= ETH_TEST_FL_FAILED; 2043 2044 /* If SRIOV or VMDq is enabled then skip MAC 2045 * loopback diagnostic. */ 2046 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2047 IXGBE_FLAG_VMDQ_ENABLED)) { 2048 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2049 data[3] = 0; 2050 goto skip_loopback; 2051 } 2052 2053 ixgbe_reset(adapter); 2054 e_info(hw, "loopback testing starting\n"); 2055 if (ixgbe_loopback_test(adapter, &data[3])) 2056 eth_test->flags |= ETH_TEST_FL_FAILED; 2057 2058 skip_loopback: 2059 ixgbe_reset(adapter); 2060 2061 /* clear testing bit and return adapter to previous state */ 2062 clear_bit(__IXGBE_TESTING, &adapter->state); 2063 if (if_running) 2064 dev_open(netdev); 2065 else if (hw->mac.ops.disable_tx_laser) 2066 hw->mac.ops.disable_tx_laser(hw); 2067 } else { 2068 e_info(hw, "online testing starting\n"); 2069 2070 /* Online tests */ 2071 if (ixgbe_link_test(adapter, &data[4])) 2072 eth_test->flags |= ETH_TEST_FL_FAILED; 2073 2074 /* Offline tests aren't run; pass by default */ 2075 data[0] = 0; 2076 data[1] = 0; 2077 data[2] = 0; 2078 data[3] = 0; 2079 2080 clear_bit(__IXGBE_TESTING, &adapter->state); 2081 } 2082 2083 skip_ol_tests: 2084 msleep_interruptible(4 * 1000); 2085 } 2086 2087 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2088 struct ethtool_wolinfo *wol) 2089 { 2090 struct ixgbe_hw *hw = &adapter->hw; 2091 int retval = 0; 2092 2093 /* WOL not supported for all devices */ 2094 if (!ixgbe_wol_supported(adapter, hw->device_id, 2095 hw->subsystem_device_id)) { 2096 retval = 1; 2097 wol->supported = 0; 2098 } 2099 2100 return retval; 2101 } 2102 2103 static void ixgbe_get_wol(struct net_device *netdev, 2104 struct ethtool_wolinfo *wol) 2105 { 2106 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2107 2108 wol->supported = WAKE_UCAST | WAKE_MCAST | 2109 WAKE_BCAST | WAKE_MAGIC; 2110 wol->wolopts = 0; 2111 2112 if (ixgbe_wol_exclusion(adapter, wol) || 2113 !device_can_wakeup(&adapter->pdev->dev)) 2114 return; 2115 2116 if (adapter->wol & IXGBE_WUFC_EX) 2117 wol->wolopts |= WAKE_UCAST; 2118 if (adapter->wol & IXGBE_WUFC_MC) 2119 wol->wolopts |= WAKE_MCAST; 2120 if (adapter->wol & IXGBE_WUFC_BC) 2121 wol->wolopts |= WAKE_BCAST; 2122 if (adapter->wol & IXGBE_WUFC_MAG) 2123 wol->wolopts |= WAKE_MAGIC; 2124 } 2125 2126 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2127 { 2128 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2129 2130 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 2131 return -EOPNOTSUPP; 2132 2133 if (ixgbe_wol_exclusion(adapter, wol)) 2134 return wol->wolopts ? -EOPNOTSUPP : 0; 2135 2136 adapter->wol = 0; 2137 2138 if (wol->wolopts & WAKE_UCAST) 2139 adapter->wol |= IXGBE_WUFC_EX; 2140 if (wol->wolopts & WAKE_MCAST) 2141 adapter->wol |= IXGBE_WUFC_MC; 2142 if (wol->wolopts & WAKE_BCAST) 2143 adapter->wol |= IXGBE_WUFC_BC; 2144 if (wol->wolopts & WAKE_MAGIC) 2145 adapter->wol |= IXGBE_WUFC_MAG; 2146 2147 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2148 2149 return 0; 2150 } 2151 2152 static int ixgbe_nway_reset(struct net_device *netdev) 2153 { 2154 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2155 2156 if (netif_running(netdev)) 2157 ixgbe_reinit_locked(adapter); 2158 2159 return 0; 2160 } 2161 2162 static int ixgbe_set_phys_id(struct net_device *netdev, 2163 enum ethtool_phys_id_state state) 2164 { 2165 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2166 struct ixgbe_hw *hw = &adapter->hw; 2167 2168 switch (state) { 2169 case ETHTOOL_ID_ACTIVE: 2170 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2171 return 2; 2172 2173 case ETHTOOL_ID_ON: 2174 hw->mac.ops.led_on(hw, IXGBE_LED_ON); 2175 break; 2176 2177 case ETHTOOL_ID_OFF: 2178 hw->mac.ops.led_off(hw, IXGBE_LED_ON); 2179 break; 2180 2181 case ETHTOOL_ID_INACTIVE: 2182 /* Restore LED settings */ 2183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2184 break; 2185 } 2186 2187 return 0; 2188 } 2189 2190 static int ixgbe_get_coalesce(struct net_device *netdev, 2191 struct ethtool_coalesce *ec) 2192 { 2193 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2194 2195 /* only valid if in constant ITR mode */ 2196 if (adapter->rx_itr_setting <= 1) 2197 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2198 else 2199 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2200 2201 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2202 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2203 return 0; 2204 2205 /* only valid if in constant ITR mode */ 2206 if (adapter->tx_itr_setting <= 1) 2207 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2208 else 2209 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2210 2211 return 0; 2212 } 2213 2214 /* 2215 * this function must be called before setting the new value of 2216 * rx_itr_setting 2217 */ 2218 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2219 { 2220 struct net_device *netdev = adapter->netdev; 2221 2222 /* nothing to do if LRO or RSC are not enabled */ 2223 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2224 !(netdev->features & NETIF_F_LRO)) 2225 return false; 2226 2227 /* check the feature flag value and enable RSC if necessary */ 2228 if (adapter->rx_itr_setting == 1 || 2229 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2230 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2231 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2232 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2233 return true; 2234 } 2235 /* if interrupt rate is too high then disable RSC */ 2236 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2237 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2238 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2239 return true; 2240 } 2241 return false; 2242 } 2243 2244 static int ixgbe_set_coalesce(struct net_device *netdev, 2245 struct ethtool_coalesce *ec) 2246 { 2247 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2248 struct ixgbe_q_vector *q_vector; 2249 int i; 2250 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2251 bool need_reset = false; 2252 2253 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2254 /* reject Tx specific changes in case of mixed RxTx vectors */ 2255 if (ec->tx_coalesce_usecs) 2256 return -EINVAL; 2257 tx_itr_prev = adapter->rx_itr_setting; 2258 } else { 2259 tx_itr_prev = adapter->tx_itr_setting; 2260 } 2261 2262 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2263 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2264 return -EINVAL; 2265 2266 if (ec->rx_coalesce_usecs > 1) 2267 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2268 else 2269 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2270 2271 if (adapter->rx_itr_setting == 1) 2272 rx_itr_param = IXGBE_20K_ITR; 2273 else 2274 rx_itr_param = adapter->rx_itr_setting; 2275 2276 if (ec->tx_coalesce_usecs > 1) 2277 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2278 else 2279 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2280 2281 if (adapter->tx_itr_setting == 1) 2282 tx_itr_param = IXGBE_10K_ITR; 2283 else 2284 tx_itr_param = adapter->tx_itr_setting; 2285 2286 /* mixed Rx/Tx */ 2287 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2288 adapter->tx_itr_setting = adapter->rx_itr_setting; 2289 2290 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2291 if ((adapter->tx_itr_setting != 1) && 2292 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2293 if ((tx_itr_prev == 1) || 2294 (tx_itr_prev >= IXGBE_100K_ITR)) 2295 need_reset = true; 2296 } else { 2297 if ((tx_itr_prev != 1) && 2298 (tx_itr_prev < IXGBE_100K_ITR)) 2299 need_reset = true; 2300 } 2301 2302 /* check the old value and enable RSC if necessary */ 2303 need_reset |= ixgbe_update_rsc(adapter); 2304 2305 for (i = 0; i < adapter->num_q_vectors; i++) { 2306 q_vector = adapter->q_vector[i]; 2307 if (q_vector->tx.count && !q_vector->rx.count) 2308 /* tx only */ 2309 q_vector->itr = tx_itr_param; 2310 else 2311 /* rx only or mixed */ 2312 q_vector->itr = rx_itr_param; 2313 ixgbe_write_eitr(q_vector); 2314 } 2315 2316 /* 2317 * do reset here at the end to make sure EITR==0 case is handled 2318 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2319 * also locks in RSC enable/disable which requires reset 2320 */ 2321 if (need_reset) 2322 ixgbe_do_reset(netdev); 2323 2324 return 0; 2325 } 2326 2327 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2328 struct ethtool_rxnfc *cmd) 2329 { 2330 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2331 struct ethtool_rx_flow_spec *fsp = 2332 (struct ethtool_rx_flow_spec *)&cmd->fs; 2333 struct hlist_node *node2; 2334 struct ixgbe_fdir_filter *rule = NULL; 2335 2336 /* report total rule count */ 2337 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2338 2339 hlist_for_each_entry_safe(rule, node2, 2340 &adapter->fdir_filter_list, fdir_node) { 2341 if (fsp->location <= rule->sw_idx) 2342 break; 2343 } 2344 2345 if (!rule || fsp->location != rule->sw_idx) 2346 return -EINVAL; 2347 2348 /* fill out the flow spec entry */ 2349 2350 /* set flow type field */ 2351 switch (rule->filter.formatted.flow_type) { 2352 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2353 fsp->flow_type = TCP_V4_FLOW; 2354 break; 2355 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2356 fsp->flow_type = UDP_V4_FLOW; 2357 break; 2358 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2359 fsp->flow_type = SCTP_V4_FLOW; 2360 break; 2361 case IXGBE_ATR_FLOW_TYPE_IPV4: 2362 fsp->flow_type = IP_USER_FLOW; 2363 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2364 fsp->h_u.usr_ip4_spec.proto = 0; 2365 fsp->m_u.usr_ip4_spec.proto = 0; 2366 break; 2367 default: 2368 return -EINVAL; 2369 } 2370 2371 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2372 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2373 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2374 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2375 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2376 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2377 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2378 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2379 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2380 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2381 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2382 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2383 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2384 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2385 fsp->flow_type |= FLOW_EXT; 2386 2387 /* record action */ 2388 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2389 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2390 else 2391 fsp->ring_cookie = rule->action; 2392 2393 return 0; 2394 } 2395 2396 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2397 struct ethtool_rxnfc *cmd, 2398 u32 *rule_locs) 2399 { 2400 struct hlist_node *node2; 2401 struct ixgbe_fdir_filter *rule; 2402 int cnt = 0; 2403 2404 /* report total rule count */ 2405 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2406 2407 hlist_for_each_entry_safe(rule, node2, 2408 &adapter->fdir_filter_list, fdir_node) { 2409 if (cnt == cmd->rule_cnt) 2410 return -EMSGSIZE; 2411 rule_locs[cnt] = rule->sw_idx; 2412 cnt++; 2413 } 2414 2415 cmd->rule_cnt = cnt; 2416 2417 return 0; 2418 } 2419 2420 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2421 struct ethtool_rxnfc *cmd) 2422 { 2423 cmd->data = 0; 2424 2425 /* Report default options for RSS on ixgbe */ 2426 switch (cmd->flow_type) { 2427 case TCP_V4_FLOW: 2428 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2429 /* fallthrough */ 2430 case UDP_V4_FLOW: 2431 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2432 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2433 /* fallthrough */ 2434 case SCTP_V4_FLOW: 2435 case AH_ESP_V4_FLOW: 2436 case AH_V4_FLOW: 2437 case ESP_V4_FLOW: 2438 case IPV4_FLOW: 2439 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2440 break; 2441 case TCP_V6_FLOW: 2442 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2443 /* fallthrough */ 2444 case UDP_V6_FLOW: 2445 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2446 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2447 /* fallthrough */ 2448 case SCTP_V6_FLOW: 2449 case AH_ESP_V6_FLOW: 2450 case AH_V6_FLOW: 2451 case ESP_V6_FLOW: 2452 case IPV6_FLOW: 2453 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2454 break; 2455 default: 2456 return -EINVAL; 2457 } 2458 2459 return 0; 2460 } 2461 2462 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2463 u32 *rule_locs) 2464 { 2465 struct ixgbe_adapter *adapter = netdev_priv(dev); 2466 int ret = -EOPNOTSUPP; 2467 2468 switch (cmd->cmd) { 2469 case ETHTOOL_GRXRINGS: 2470 cmd->data = adapter->num_rx_queues; 2471 ret = 0; 2472 break; 2473 case ETHTOOL_GRXCLSRLCNT: 2474 cmd->rule_cnt = adapter->fdir_filter_count; 2475 ret = 0; 2476 break; 2477 case ETHTOOL_GRXCLSRULE: 2478 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2479 break; 2480 case ETHTOOL_GRXCLSRLALL: 2481 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2482 break; 2483 case ETHTOOL_GRXFH: 2484 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2485 break; 2486 default: 2487 break; 2488 } 2489 2490 return ret; 2491 } 2492 2493 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2494 struct ixgbe_fdir_filter *input, 2495 u16 sw_idx) 2496 { 2497 struct ixgbe_hw *hw = &adapter->hw; 2498 struct hlist_node *node2; 2499 struct ixgbe_fdir_filter *rule, *parent; 2500 int err = -EINVAL; 2501 2502 parent = NULL; 2503 rule = NULL; 2504 2505 hlist_for_each_entry_safe(rule, node2, 2506 &adapter->fdir_filter_list, fdir_node) { 2507 /* hash found, or no matching entry */ 2508 if (rule->sw_idx >= sw_idx) 2509 break; 2510 parent = rule; 2511 } 2512 2513 /* if there is an old rule occupying our place remove it */ 2514 if (rule && (rule->sw_idx == sw_idx)) { 2515 if (!input || (rule->filter.formatted.bkt_hash != 2516 input->filter.formatted.bkt_hash)) { 2517 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2518 &rule->filter, 2519 sw_idx); 2520 } 2521 2522 hlist_del(&rule->fdir_node); 2523 kfree(rule); 2524 adapter->fdir_filter_count--; 2525 } 2526 2527 /* 2528 * If no input this was a delete, err should be 0 if a rule was 2529 * successfully found and removed from the list else -EINVAL 2530 */ 2531 if (!input) 2532 return err; 2533 2534 /* initialize node and set software index */ 2535 INIT_HLIST_NODE(&input->fdir_node); 2536 2537 /* add filter to the list */ 2538 if (parent) 2539 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2540 else 2541 hlist_add_head(&input->fdir_node, 2542 &adapter->fdir_filter_list); 2543 2544 /* update counts */ 2545 adapter->fdir_filter_count++; 2546 2547 return 0; 2548 } 2549 2550 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2551 u8 *flow_type) 2552 { 2553 switch (fsp->flow_type & ~FLOW_EXT) { 2554 case TCP_V4_FLOW: 2555 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2556 break; 2557 case UDP_V4_FLOW: 2558 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2559 break; 2560 case SCTP_V4_FLOW: 2561 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2562 break; 2563 case IP_USER_FLOW: 2564 switch (fsp->h_u.usr_ip4_spec.proto) { 2565 case IPPROTO_TCP: 2566 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2567 break; 2568 case IPPROTO_UDP: 2569 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2570 break; 2571 case IPPROTO_SCTP: 2572 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2573 break; 2574 case 0: 2575 if (!fsp->m_u.usr_ip4_spec.proto) { 2576 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2577 break; 2578 } 2579 default: 2580 return 0; 2581 } 2582 break; 2583 default: 2584 return 0; 2585 } 2586 2587 return 1; 2588 } 2589 2590 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2591 struct ethtool_rxnfc *cmd) 2592 { 2593 struct ethtool_rx_flow_spec *fsp = 2594 (struct ethtool_rx_flow_spec *)&cmd->fs; 2595 struct ixgbe_hw *hw = &adapter->hw; 2596 struct ixgbe_fdir_filter *input; 2597 union ixgbe_atr_input mask; 2598 u8 queue; 2599 int err; 2600 2601 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2602 return -EOPNOTSUPP; 2603 2604 /* ring_cookie is a masked into a set of queues and ixgbe pools or 2605 * we use the drop index. 2606 */ 2607 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 2608 queue = IXGBE_FDIR_DROP_QUEUE; 2609 } else { 2610 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); 2611 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie); 2612 2613 if (!vf && (ring >= adapter->num_rx_queues)) 2614 return -EINVAL; 2615 else if (vf && 2616 ((vf > adapter->num_vfs) || 2617 ring >= adapter->num_rx_queues_per_pool)) 2618 return -EINVAL; 2619 2620 /* Map the ring onto the absolute queue index */ 2621 if (!vf) 2622 queue = adapter->rx_ring[ring]->reg_idx; 2623 else 2624 queue = ((vf - 1) * 2625 adapter->num_rx_queues_per_pool) + ring; 2626 } 2627 2628 /* Don't allow indexes to exist outside of available space */ 2629 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2630 e_err(drv, "Location out of range\n"); 2631 return -EINVAL; 2632 } 2633 2634 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2635 if (!input) 2636 return -ENOMEM; 2637 2638 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2639 2640 /* set SW index */ 2641 input->sw_idx = fsp->location; 2642 2643 /* record flow type */ 2644 if (!ixgbe_flowspec_to_flow_type(fsp, 2645 &input->filter.formatted.flow_type)) { 2646 e_err(drv, "Unrecognized flow type\n"); 2647 goto err_out; 2648 } 2649 2650 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2651 IXGBE_ATR_L4TYPE_MASK; 2652 2653 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2654 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2655 2656 /* Copy input into formatted structures */ 2657 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2658 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2659 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2660 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2661 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2662 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2663 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2664 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2665 2666 if (fsp->flow_type & FLOW_EXT) { 2667 input->filter.formatted.vm_pool = 2668 (unsigned char)ntohl(fsp->h_ext.data[1]); 2669 mask.formatted.vm_pool = 2670 (unsigned char)ntohl(fsp->m_ext.data[1]); 2671 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2672 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2673 input->filter.formatted.flex_bytes = 2674 fsp->h_ext.vlan_etype; 2675 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2676 } 2677 2678 /* determine if we need to drop or route the packet */ 2679 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2680 input->action = IXGBE_FDIR_DROP_QUEUE; 2681 else 2682 input->action = fsp->ring_cookie; 2683 2684 spin_lock(&adapter->fdir_perfect_lock); 2685 2686 if (hlist_empty(&adapter->fdir_filter_list)) { 2687 /* save mask and program input mask into HW */ 2688 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2689 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2690 if (err) { 2691 e_err(drv, "Error writing mask\n"); 2692 goto err_out_w_lock; 2693 } 2694 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2695 e_err(drv, "Only one mask supported per port\n"); 2696 goto err_out_w_lock; 2697 } 2698 2699 /* apply mask and compute/store hash */ 2700 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2701 2702 /* program filters to filter memory */ 2703 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2704 &input->filter, input->sw_idx, queue); 2705 if (err) 2706 goto err_out_w_lock; 2707 2708 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2709 2710 spin_unlock(&adapter->fdir_perfect_lock); 2711 2712 return err; 2713 err_out_w_lock: 2714 spin_unlock(&adapter->fdir_perfect_lock); 2715 err_out: 2716 kfree(input); 2717 return -EINVAL; 2718 } 2719 2720 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2721 struct ethtool_rxnfc *cmd) 2722 { 2723 struct ethtool_rx_flow_spec *fsp = 2724 (struct ethtool_rx_flow_spec *)&cmd->fs; 2725 int err; 2726 2727 spin_lock(&adapter->fdir_perfect_lock); 2728 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2729 spin_unlock(&adapter->fdir_perfect_lock); 2730 2731 return err; 2732 } 2733 2734 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2735 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2736 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2737 struct ethtool_rxnfc *nfc) 2738 { 2739 u32 flags2 = adapter->flags2; 2740 2741 /* 2742 * RSS does not support anything other than hashing 2743 * to queues on src and dst IPs and ports 2744 */ 2745 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2746 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2747 return -EINVAL; 2748 2749 switch (nfc->flow_type) { 2750 case TCP_V4_FLOW: 2751 case TCP_V6_FLOW: 2752 if (!(nfc->data & RXH_IP_SRC) || 2753 !(nfc->data & RXH_IP_DST) || 2754 !(nfc->data & RXH_L4_B_0_1) || 2755 !(nfc->data & RXH_L4_B_2_3)) 2756 return -EINVAL; 2757 break; 2758 case UDP_V4_FLOW: 2759 if (!(nfc->data & RXH_IP_SRC) || 2760 !(nfc->data & RXH_IP_DST)) 2761 return -EINVAL; 2762 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2763 case 0: 2764 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2765 break; 2766 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2767 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2768 break; 2769 default: 2770 return -EINVAL; 2771 } 2772 break; 2773 case UDP_V6_FLOW: 2774 if (!(nfc->data & RXH_IP_SRC) || 2775 !(nfc->data & RXH_IP_DST)) 2776 return -EINVAL; 2777 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2778 case 0: 2779 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2780 break; 2781 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2782 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2783 break; 2784 default: 2785 return -EINVAL; 2786 } 2787 break; 2788 case AH_ESP_V4_FLOW: 2789 case AH_V4_FLOW: 2790 case ESP_V4_FLOW: 2791 case SCTP_V4_FLOW: 2792 case AH_ESP_V6_FLOW: 2793 case AH_V6_FLOW: 2794 case ESP_V6_FLOW: 2795 case SCTP_V6_FLOW: 2796 if (!(nfc->data & RXH_IP_SRC) || 2797 !(nfc->data & RXH_IP_DST) || 2798 (nfc->data & RXH_L4_B_0_1) || 2799 (nfc->data & RXH_L4_B_2_3)) 2800 return -EINVAL; 2801 break; 2802 default: 2803 return -EINVAL; 2804 } 2805 2806 /* if we changed something we need to update flags */ 2807 if (flags2 != adapter->flags2) { 2808 struct ixgbe_hw *hw = &adapter->hw; 2809 u32 mrqc; 2810 unsigned int pf_pool = adapter->num_vfs; 2811 2812 if ((hw->mac.type >= ixgbe_mac_X550) && 2813 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2814 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 2815 else 2816 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2817 2818 if ((flags2 & UDP_RSS_FLAGS) && 2819 !(adapter->flags2 & UDP_RSS_FLAGS)) 2820 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2821 2822 adapter->flags2 = flags2; 2823 2824 /* Perform hash on these packet types */ 2825 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 2826 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 2827 | IXGBE_MRQC_RSS_FIELD_IPV6 2828 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 2829 2830 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2831 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 2832 2833 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2834 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 2835 2836 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2837 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 2838 2839 if ((hw->mac.type >= ixgbe_mac_X550) && 2840 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2841 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 2842 else 2843 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2844 } 2845 2846 return 0; 2847 } 2848 2849 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2850 { 2851 struct ixgbe_adapter *adapter = netdev_priv(dev); 2852 int ret = -EOPNOTSUPP; 2853 2854 switch (cmd->cmd) { 2855 case ETHTOOL_SRXCLSRLINS: 2856 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2857 break; 2858 case ETHTOOL_SRXCLSRLDEL: 2859 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2860 break; 2861 case ETHTOOL_SRXFH: 2862 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 2863 break; 2864 default: 2865 break; 2866 } 2867 2868 return ret; 2869 } 2870 2871 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) 2872 { 2873 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2874 2875 return sizeof(adapter->rss_key); 2876 } 2877 2878 static u32 ixgbe_rss_indir_size(struct net_device *netdev) 2879 { 2880 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2881 2882 return ixgbe_rss_indir_tbl_entries(adapter); 2883 } 2884 2885 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir) 2886 { 2887 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter); 2888 2889 for (i = 0; i < reta_size; i++) 2890 indir[i] = adapter->rss_indir_tbl[i]; 2891 } 2892 2893 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 2894 u8 *hfunc) 2895 { 2896 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2897 2898 if (hfunc) 2899 *hfunc = ETH_RSS_HASH_TOP; 2900 2901 if (indir) 2902 ixgbe_get_reta(adapter, indir); 2903 2904 if (key) 2905 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev)); 2906 2907 return 0; 2908 } 2909 2910 static int ixgbe_get_ts_info(struct net_device *dev, 2911 struct ethtool_ts_info *info) 2912 { 2913 struct ixgbe_adapter *adapter = netdev_priv(dev); 2914 2915 switch (adapter->hw.mac.type) { 2916 case ixgbe_mac_X550: 2917 case ixgbe_mac_X550EM_x: 2918 case ixgbe_mac_X540: 2919 case ixgbe_mac_82599EB: 2920 info->so_timestamping = 2921 SOF_TIMESTAMPING_TX_SOFTWARE | 2922 SOF_TIMESTAMPING_RX_SOFTWARE | 2923 SOF_TIMESTAMPING_SOFTWARE | 2924 SOF_TIMESTAMPING_TX_HARDWARE | 2925 SOF_TIMESTAMPING_RX_HARDWARE | 2926 SOF_TIMESTAMPING_RAW_HARDWARE; 2927 2928 if (adapter->ptp_clock) 2929 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2930 else 2931 info->phc_index = -1; 2932 2933 info->tx_types = 2934 (1 << HWTSTAMP_TX_OFF) | 2935 (1 << HWTSTAMP_TX_ON); 2936 2937 info->rx_filters = 2938 (1 << HWTSTAMP_FILTER_NONE) | 2939 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2940 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2941 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 2942 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 2943 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 2944 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 2945 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 2946 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 2947 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 2948 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 2949 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2950 break; 2951 default: 2952 return ethtool_op_get_ts_info(dev, info); 2953 } 2954 return 0; 2955 } 2956 2957 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 2958 { 2959 unsigned int max_combined; 2960 u8 tcs = netdev_get_num_tc(adapter->netdev); 2961 2962 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2963 /* We only support one q_vector without MSI-X */ 2964 max_combined = 1; 2965 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2966 /* SR-IOV currently only allows one queue on the PF */ 2967 max_combined = 1; 2968 } else if (tcs > 1) { 2969 /* For DCB report channels per traffic class */ 2970 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 2971 /* 8 TC w/ 4 queues per TC */ 2972 max_combined = 4; 2973 } else if (tcs > 4) { 2974 /* 8 TC w/ 8 queues per TC */ 2975 max_combined = 8; 2976 } else { 2977 /* 4 TC w/ 16 queues per TC */ 2978 max_combined = 16; 2979 } 2980 } else if (adapter->atr_sample_rate) { 2981 /* support up to 64 queues with ATR */ 2982 max_combined = IXGBE_MAX_FDIR_INDICES; 2983 } else { 2984 /* support up to 16 queues with RSS */ 2985 max_combined = ixgbe_max_rss_indices(adapter); 2986 } 2987 2988 return max_combined; 2989 } 2990 2991 static void ixgbe_get_channels(struct net_device *dev, 2992 struct ethtool_channels *ch) 2993 { 2994 struct ixgbe_adapter *adapter = netdev_priv(dev); 2995 2996 /* report maximum channels */ 2997 ch->max_combined = ixgbe_max_channels(adapter); 2998 2999 /* report info for other vector */ 3000 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3001 ch->max_other = NON_Q_VECTORS; 3002 ch->other_count = NON_Q_VECTORS; 3003 } 3004 3005 /* record RSS queues */ 3006 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 3007 3008 /* nothing else to report if RSS is disabled */ 3009 if (ch->combined_count == 1) 3010 return; 3011 3012 /* we do not support ATR queueing if SR-IOV is enabled */ 3013 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3014 return; 3015 3016 /* same thing goes for being DCB enabled */ 3017 if (netdev_get_num_tc(dev) > 1) 3018 return; 3019 3020 /* if ATR is disabled we can exit */ 3021 if (!adapter->atr_sample_rate) 3022 return; 3023 3024 /* report flow director queues as maximum channels */ 3025 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 3026 } 3027 3028 static int ixgbe_set_channels(struct net_device *dev, 3029 struct ethtool_channels *ch) 3030 { 3031 struct ixgbe_adapter *adapter = netdev_priv(dev); 3032 unsigned int count = ch->combined_count; 3033 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 3034 3035 /* verify they are not requesting separate vectors */ 3036 if (!count || ch->rx_count || ch->tx_count) 3037 return -EINVAL; 3038 3039 /* verify other_count has not changed */ 3040 if (ch->other_count != NON_Q_VECTORS) 3041 return -EINVAL; 3042 3043 /* verify the number of channels does not exceed hardware limits */ 3044 if (count > ixgbe_max_channels(adapter)) 3045 return -EINVAL; 3046 3047 /* update feature limits from largest to smallest supported values */ 3048 adapter->ring_feature[RING_F_FDIR].limit = count; 3049 3050 /* cap RSS limit */ 3051 if (count > max_rss_indices) 3052 count = max_rss_indices; 3053 adapter->ring_feature[RING_F_RSS].limit = count; 3054 3055 #ifdef IXGBE_FCOE 3056 /* cap FCoE limit at 8 */ 3057 if (count > IXGBE_FCRETA_SIZE) 3058 count = IXGBE_FCRETA_SIZE; 3059 adapter->ring_feature[RING_F_FCOE].limit = count; 3060 3061 #endif 3062 /* use setup TC to update any traffic class queue mapping */ 3063 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 3064 } 3065 3066 static int ixgbe_get_module_info(struct net_device *dev, 3067 struct ethtool_modinfo *modinfo) 3068 { 3069 struct ixgbe_adapter *adapter = netdev_priv(dev); 3070 struct ixgbe_hw *hw = &adapter->hw; 3071 s32 status; 3072 u8 sff8472_rev, addr_mode; 3073 bool page_swap = false; 3074 3075 /* Check whether we support SFF-8472 or not */ 3076 status = hw->phy.ops.read_i2c_eeprom(hw, 3077 IXGBE_SFF_SFF_8472_COMP, 3078 &sff8472_rev); 3079 if (status) 3080 return -EIO; 3081 3082 /* addressing mode is not supported */ 3083 status = hw->phy.ops.read_i2c_eeprom(hw, 3084 IXGBE_SFF_SFF_8472_SWAP, 3085 &addr_mode); 3086 if (status) 3087 return -EIO; 3088 3089 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3090 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3091 page_swap = true; 3092 } 3093 3094 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 3095 /* We have a SFP, but it does not support SFF-8472 */ 3096 modinfo->type = ETH_MODULE_SFF_8079; 3097 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3098 } else { 3099 /* We have a SFP which supports a revision of SFF-8472. */ 3100 modinfo->type = ETH_MODULE_SFF_8472; 3101 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3102 } 3103 3104 return 0; 3105 } 3106 3107 static int ixgbe_get_module_eeprom(struct net_device *dev, 3108 struct ethtool_eeprom *ee, 3109 u8 *data) 3110 { 3111 struct ixgbe_adapter *adapter = netdev_priv(dev); 3112 struct ixgbe_hw *hw = &adapter->hw; 3113 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3114 u8 databyte = 0xFF; 3115 int i = 0; 3116 3117 if (ee->len == 0) 3118 return -EINVAL; 3119 3120 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3121 /* I2C reads can take long time */ 3122 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3123 return -EBUSY; 3124 3125 if (i < ETH_MODULE_SFF_8079_LEN) 3126 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3127 else 3128 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3129 3130 if (status) 3131 return -EIO; 3132 3133 data[i - ee->offset] = databyte; 3134 } 3135 3136 return 0; 3137 } 3138 3139 static const struct ethtool_ops ixgbe_ethtool_ops = { 3140 .get_settings = ixgbe_get_settings, 3141 .set_settings = ixgbe_set_settings, 3142 .get_drvinfo = ixgbe_get_drvinfo, 3143 .get_regs_len = ixgbe_get_regs_len, 3144 .get_regs = ixgbe_get_regs, 3145 .get_wol = ixgbe_get_wol, 3146 .set_wol = ixgbe_set_wol, 3147 .nway_reset = ixgbe_nway_reset, 3148 .get_link = ethtool_op_get_link, 3149 .get_eeprom_len = ixgbe_get_eeprom_len, 3150 .get_eeprom = ixgbe_get_eeprom, 3151 .set_eeprom = ixgbe_set_eeprom, 3152 .get_ringparam = ixgbe_get_ringparam, 3153 .set_ringparam = ixgbe_set_ringparam, 3154 .get_pauseparam = ixgbe_get_pauseparam, 3155 .set_pauseparam = ixgbe_set_pauseparam, 3156 .get_msglevel = ixgbe_get_msglevel, 3157 .set_msglevel = ixgbe_set_msglevel, 3158 .self_test = ixgbe_diag_test, 3159 .get_strings = ixgbe_get_strings, 3160 .set_phys_id = ixgbe_set_phys_id, 3161 .get_sset_count = ixgbe_get_sset_count, 3162 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3163 .get_coalesce = ixgbe_get_coalesce, 3164 .set_coalesce = ixgbe_set_coalesce, 3165 .get_rxnfc = ixgbe_get_rxnfc, 3166 .set_rxnfc = ixgbe_set_rxnfc, 3167 .get_rxfh_indir_size = ixgbe_rss_indir_size, 3168 .get_rxfh_key_size = ixgbe_get_rxfh_key_size, 3169 .get_rxfh = ixgbe_get_rxfh, 3170 .get_channels = ixgbe_get_channels, 3171 .set_channels = ixgbe_set_channels, 3172 .get_ts_info = ixgbe_get_ts_info, 3173 .get_module_info = ixgbe_get_module_info, 3174 .get_module_eeprom = ixgbe_get_module_eeprom, 3175 }; 3176 3177 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3178 { 3179 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3180 } 3181