1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3 
4 /* ethtool support for ixgbe */
5 
6 #include <linux/interrupt.h>
7 #include <linux/types.h>
8 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/vmalloc.h>
14 #include <linux/highmem.h>
15 #include <linux/uaccess.h>
16 
17 #include "ixgbe.h"
18 #include "ixgbe_phy.h"
19 
20 
21 #define IXGBE_ALL_RAR_ENTRIES 16
22 
23 enum {NETDEV_STATS, IXGBE_STATS};
24 
25 struct ixgbe_stats {
26 	char stat_string[ETH_GSTRING_LEN];
27 	int type;
28 	int sizeof_stat;
29 	int stat_offset;
30 };
31 
32 #define IXGBE_STAT(m)		IXGBE_STATS, \
33 				sizeof(((struct ixgbe_adapter *)0)->m), \
34 				offsetof(struct ixgbe_adapter, m)
35 #define IXGBE_NETDEV_STAT(m)	NETDEV_STATS, \
36 				sizeof(((struct rtnl_link_stats64 *)0)->m), \
37 				offsetof(struct rtnl_link_stats64, m)
38 
39 static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
40 	{"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
41 	{"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
42 	{"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
43 	{"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
44 	{"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
45 	{"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
46 	{"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
47 	{"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
48 	{"lsc_int", IXGBE_STAT(lsc_int)},
49 	{"tx_busy", IXGBE_STAT(tx_busy)},
50 	{"non_eop_descs", IXGBE_STAT(non_eop_descs)},
51 	{"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
52 	{"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
53 	{"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
54 	{"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
55 	{"multicast", IXGBE_NETDEV_STAT(multicast)},
56 	{"broadcast", IXGBE_STAT(stats.bprc)},
57 	{"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
58 	{"collisions", IXGBE_NETDEV_STAT(collisions)},
59 	{"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
60 	{"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
61 	{"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
62 	{"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
63 	{"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
64 	{"fdir_match", IXGBE_STAT(stats.fdirmatch)},
65 	{"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
66 	{"fdir_overflow", IXGBE_STAT(fdir_overflow)},
67 	{"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
68 	{"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
69 	{"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
70 	{"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
71 	{"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
72 	{"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
73 	{"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
74 	{"tx_restart_queue", IXGBE_STAT(restart_queue)},
75 	{"rx_length_errors", IXGBE_STAT(stats.rlec)},
76 	{"rx_long_length_errors", IXGBE_STAT(stats.roc)},
77 	{"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
78 	{"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
79 	{"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
80 	{"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
81 	{"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
82 	{"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
83 	{"alloc_rx_page", IXGBE_STAT(alloc_rx_page)},
84 	{"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
85 	{"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
86 	{"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
87 	{"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
88 	{"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
89 	{"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
90 	{"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
91 	{"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)},
92 	{"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)},
93 	{"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)},
94 	{"tx_ipsec", IXGBE_STAT(tx_ipsec)},
95 	{"rx_ipsec", IXGBE_STAT(rx_ipsec)},
96 #ifdef IXGBE_FCOE
97 	{"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
98 	{"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
99 	{"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
100 	{"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
101 	{"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
102 	{"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
103 	{"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
104 	{"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
105 #endif /* IXGBE_FCOE */
106 };
107 
108 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
109  * we set the num_rx_queues to evaluate to num_tx_queues. This is
110  * used because we do not have a good way to get the max number of
111  * rx queues with CONFIG_RPS disabled.
112  */
113 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
114 
115 #define IXGBE_QUEUE_STATS_LEN ( \
116 	(netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
117 	(sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
118 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
119 #define IXGBE_PB_STATS_LEN ( \
120 			(sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
121 			 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
122 			 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
123 			 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
124 			/ sizeof(u64))
125 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
126 			 IXGBE_PB_STATS_LEN + \
127 			 IXGBE_QUEUE_STATS_LEN)
128 
129 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
130 	"Register test  (offline)", "Eeprom test    (offline)",
131 	"Interrupt test (offline)", "Loopback test  (offline)",
132 	"Link test   (on/offline)"
133 };
134 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
135 
136 static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = {
137 #define IXGBE_PRIV_FLAGS_LEGACY_RX	BIT(0)
138 	"legacy-rx",
139 #define IXGBE_PRIV_FLAGS_VF_IPSEC_EN	BIT(1)
140 	"vf-ipsec",
141 };
142 
143 #define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings)
144 
145 /* currently supported speeds for 10G */
146 #define ADVRTSD_MSK_10G (SUPPORTED_10000baseT_Full | \
147 			 SUPPORTED_10000baseKX4_Full | \
148 			 SUPPORTED_10000baseKR_Full)
149 
150 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane)
151 
152 static u32 ixgbe_get_supported_10gtypes(struct ixgbe_hw *hw)
153 {
154 	if (!ixgbe_isbackplane(hw->phy.media_type))
155 		return SUPPORTED_10000baseT_Full;
156 
157 	switch (hw->device_id) {
158 	case IXGBE_DEV_ID_82598:
159 	case IXGBE_DEV_ID_82599_KX4:
160 	case IXGBE_DEV_ID_82599_KX4_MEZZ:
161 	case IXGBE_DEV_ID_X550EM_X_KX4:
162 		return SUPPORTED_10000baseKX4_Full;
163 	case IXGBE_DEV_ID_82598_BX:
164 	case IXGBE_DEV_ID_82599_KR:
165 	case IXGBE_DEV_ID_X550EM_X_KR:
166 	case IXGBE_DEV_ID_X550EM_X_XFI:
167 		return SUPPORTED_10000baseKR_Full;
168 	default:
169 		return SUPPORTED_10000baseKX4_Full |
170 		       SUPPORTED_10000baseKR_Full;
171 	}
172 }
173 
174 static int ixgbe_get_link_ksettings(struct net_device *netdev,
175 				    struct ethtool_link_ksettings *cmd)
176 {
177 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
178 	struct ixgbe_hw *hw = &adapter->hw;
179 	ixgbe_link_speed supported_link;
180 	bool autoneg = false;
181 	u32 supported, advertising;
182 
183 	ethtool_convert_link_mode_to_legacy_u32(&supported,
184 						cmd->link_modes.supported);
185 
186 	hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
187 
188 	/* set the supported link speeds */
189 	if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
190 		supported |= ixgbe_get_supported_10gtypes(hw);
191 	if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
192 		supported |= (ixgbe_isbackplane(hw->phy.media_type)) ?
193 				   SUPPORTED_1000baseKX_Full :
194 				   SUPPORTED_1000baseT_Full;
195 	if (supported_link & IXGBE_LINK_SPEED_100_FULL)
196 		supported |= SUPPORTED_100baseT_Full;
197 	if (supported_link & IXGBE_LINK_SPEED_10_FULL)
198 		supported |= SUPPORTED_10baseT_Full;
199 
200 	/* default advertised speed if phy.autoneg_advertised isn't set */
201 	advertising = supported;
202 	/* set the advertised speeds */
203 	if (hw->phy.autoneg_advertised) {
204 		advertising = 0;
205 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
206 			advertising |= ADVERTISED_10baseT_Full;
207 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
208 			advertising |= ADVERTISED_100baseT_Full;
209 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
210 			advertising |= supported & ADVRTSD_MSK_10G;
211 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {
212 			if (supported & SUPPORTED_1000baseKX_Full)
213 				advertising |= ADVERTISED_1000baseKX_Full;
214 			else
215 				advertising |= ADVERTISED_1000baseT_Full;
216 		}
217 	} else {
218 		if (hw->phy.multispeed_fiber && !autoneg) {
219 			if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
220 				advertising = ADVERTISED_10000baseT_Full;
221 		}
222 	}
223 
224 	if (autoneg) {
225 		supported |= SUPPORTED_Autoneg;
226 		advertising |= ADVERTISED_Autoneg;
227 		cmd->base.autoneg = AUTONEG_ENABLE;
228 	} else
229 		cmd->base.autoneg = AUTONEG_DISABLE;
230 
231 	/* Determine the remaining settings based on the PHY type. */
232 	switch (adapter->hw.phy.type) {
233 	case ixgbe_phy_tn:
234 	case ixgbe_phy_aq:
235 	case ixgbe_phy_x550em_ext_t:
236 	case ixgbe_phy_fw:
237 	case ixgbe_phy_cu_unknown:
238 		supported |= SUPPORTED_TP;
239 		advertising |= ADVERTISED_TP;
240 		cmd->base.port = PORT_TP;
241 		break;
242 	case ixgbe_phy_qt:
243 		supported |= SUPPORTED_FIBRE;
244 		advertising |= ADVERTISED_FIBRE;
245 		cmd->base.port = PORT_FIBRE;
246 		break;
247 	case ixgbe_phy_nl:
248 	case ixgbe_phy_sfp_passive_tyco:
249 	case ixgbe_phy_sfp_passive_unknown:
250 	case ixgbe_phy_sfp_ftl:
251 	case ixgbe_phy_sfp_avago:
252 	case ixgbe_phy_sfp_intel:
253 	case ixgbe_phy_sfp_unknown:
254 	case ixgbe_phy_qsfp_passive_unknown:
255 	case ixgbe_phy_qsfp_active_unknown:
256 	case ixgbe_phy_qsfp_intel:
257 	case ixgbe_phy_qsfp_unknown:
258 		/* SFP+ devices, further checking needed */
259 		switch (adapter->hw.phy.sfp_type) {
260 		case ixgbe_sfp_type_da_cu:
261 		case ixgbe_sfp_type_da_cu_core0:
262 		case ixgbe_sfp_type_da_cu_core1:
263 			supported |= SUPPORTED_FIBRE;
264 			advertising |= ADVERTISED_FIBRE;
265 			cmd->base.port = PORT_DA;
266 			break;
267 		case ixgbe_sfp_type_sr:
268 		case ixgbe_sfp_type_lr:
269 		case ixgbe_sfp_type_srlr_core0:
270 		case ixgbe_sfp_type_srlr_core1:
271 		case ixgbe_sfp_type_1g_sx_core0:
272 		case ixgbe_sfp_type_1g_sx_core1:
273 		case ixgbe_sfp_type_1g_lx_core0:
274 		case ixgbe_sfp_type_1g_lx_core1:
275 			supported |= SUPPORTED_FIBRE;
276 			advertising |= ADVERTISED_FIBRE;
277 			cmd->base.port = PORT_FIBRE;
278 			break;
279 		case ixgbe_sfp_type_not_present:
280 			supported |= SUPPORTED_FIBRE;
281 			advertising |= ADVERTISED_FIBRE;
282 			cmd->base.port = PORT_NONE;
283 			break;
284 		case ixgbe_sfp_type_1g_cu_core0:
285 		case ixgbe_sfp_type_1g_cu_core1:
286 			supported |= SUPPORTED_TP;
287 			advertising |= ADVERTISED_TP;
288 			cmd->base.port = PORT_TP;
289 			break;
290 		case ixgbe_sfp_type_unknown:
291 		default:
292 			supported |= SUPPORTED_FIBRE;
293 			advertising |= ADVERTISED_FIBRE;
294 			cmd->base.port = PORT_OTHER;
295 			break;
296 		}
297 		break;
298 	case ixgbe_phy_xaui:
299 		supported |= SUPPORTED_FIBRE;
300 		advertising |= ADVERTISED_FIBRE;
301 		cmd->base.port = PORT_NONE;
302 		break;
303 	case ixgbe_phy_unknown:
304 	case ixgbe_phy_generic:
305 	case ixgbe_phy_sfp_unsupported:
306 	default:
307 		supported |= SUPPORTED_FIBRE;
308 		advertising |= ADVERTISED_FIBRE;
309 		cmd->base.port = PORT_OTHER;
310 		break;
311 	}
312 
313 	/* Indicate pause support */
314 	supported |= SUPPORTED_Pause;
315 
316 	switch (hw->fc.requested_mode) {
317 	case ixgbe_fc_full:
318 		advertising |= ADVERTISED_Pause;
319 		break;
320 	case ixgbe_fc_rx_pause:
321 		advertising |= ADVERTISED_Pause |
322 				     ADVERTISED_Asym_Pause;
323 		break;
324 	case ixgbe_fc_tx_pause:
325 		advertising |= ADVERTISED_Asym_Pause;
326 		break;
327 	default:
328 		advertising &= ~(ADVERTISED_Pause |
329 				       ADVERTISED_Asym_Pause);
330 	}
331 
332 	if (netif_carrier_ok(netdev)) {
333 		switch (adapter->link_speed) {
334 		case IXGBE_LINK_SPEED_10GB_FULL:
335 			cmd->base.speed = SPEED_10000;
336 			break;
337 		case IXGBE_LINK_SPEED_5GB_FULL:
338 			cmd->base.speed = SPEED_5000;
339 			break;
340 		case IXGBE_LINK_SPEED_2_5GB_FULL:
341 			cmd->base.speed = SPEED_2500;
342 			break;
343 		case IXGBE_LINK_SPEED_1GB_FULL:
344 			cmd->base.speed = SPEED_1000;
345 			break;
346 		case IXGBE_LINK_SPEED_100_FULL:
347 			cmd->base.speed = SPEED_100;
348 			break;
349 		case IXGBE_LINK_SPEED_10_FULL:
350 			cmd->base.speed = SPEED_10;
351 			break;
352 		default:
353 			break;
354 		}
355 		cmd->base.duplex = DUPLEX_FULL;
356 	} else {
357 		cmd->base.speed = SPEED_UNKNOWN;
358 		cmd->base.duplex = DUPLEX_UNKNOWN;
359 	}
360 
361 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
362 						supported);
363 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
364 						advertising);
365 
366 	return 0;
367 }
368 
369 static int ixgbe_set_link_ksettings(struct net_device *netdev,
370 				    const struct ethtool_link_ksettings *cmd)
371 {
372 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
373 	struct ixgbe_hw *hw = &adapter->hw;
374 	u32 advertised, old;
375 	s32 err = 0;
376 	u32 supported, advertising;
377 
378 	ethtool_convert_link_mode_to_legacy_u32(&supported,
379 						cmd->link_modes.supported);
380 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
381 						cmd->link_modes.advertising);
382 
383 	if ((hw->phy.media_type == ixgbe_media_type_copper) ||
384 	    (hw->phy.multispeed_fiber)) {
385 		/*
386 		 * this function does not support duplex forcing, but can
387 		 * limit the advertising of the adapter to the specified speed
388 		 */
389 		if (advertising & ~supported)
390 			return -EINVAL;
391 
392 		/* only allow one speed at a time if no autoneg */
393 		if (!cmd->base.autoneg && hw->phy.multispeed_fiber) {
394 			if (advertising ==
395 			    (ADVERTISED_10000baseT_Full |
396 			     ADVERTISED_1000baseT_Full))
397 				return -EINVAL;
398 		}
399 
400 		old = hw->phy.autoneg_advertised;
401 		advertised = 0;
402 		if (advertising & ADVERTISED_10000baseT_Full)
403 			advertised |= IXGBE_LINK_SPEED_10GB_FULL;
404 
405 		if (advertising & ADVERTISED_1000baseT_Full)
406 			advertised |= IXGBE_LINK_SPEED_1GB_FULL;
407 
408 		if (advertising & ADVERTISED_100baseT_Full)
409 			advertised |= IXGBE_LINK_SPEED_100_FULL;
410 
411 		if (advertising & ADVERTISED_10baseT_Full)
412 			advertised |= IXGBE_LINK_SPEED_10_FULL;
413 
414 		if (old == advertised)
415 			return err;
416 		/* this sets the link speed and restarts auto-neg */
417 		while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
418 			usleep_range(1000, 2000);
419 
420 		hw->mac.autotry_restart = true;
421 		err = hw->mac.ops.setup_link(hw, advertised, true);
422 		if (err) {
423 			e_info(probe, "setup link failed with code %d\n", err);
424 			hw->mac.ops.setup_link(hw, old, true);
425 		}
426 		clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
427 	} else {
428 		/* in this case we currently only support 10Gb/FULL */
429 		u32 speed = cmd->base.speed;
430 
431 		if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
432 		    (advertising != ADVERTISED_10000baseT_Full) ||
433 		    (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL))
434 			return -EINVAL;
435 	}
436 
437 	return err;
438 }
439 
440 static void ixgbe_get_pauseparam(struct net_device *netdev,
441 				 struct ethtool_pauseparam *pause)
442 {
443 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
444 	struct ixgbe_hw *hw = &adapter->hw;
445 
446 	if (ixgbe_device_supports_autoneg_fc(hw) &&
447 	    !hw->fc.disable_fc_autoneg)
448 		pause->autoneg = 1;
449 	else
450 		pause->autoneg = 0;
451 
452 	if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
453 		pause->rx_pause = 1;
454 	} else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
455 		pause->tx_pause = 1;
456 	} else if (hw->fc.current_mode == ixgbe_fc_full) {
457 		pause->rx_pause = 1;
458 		pause->tx_pause = 1;
459 	}
460 }
461 
462 static int ixgbe_set_pauseparam(struct net_device *netdev,
463 				struct ethtool_pauseparam *pause)
464 {
465 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
466 	struct ixgbe_hw *hw = &adapter->hw;
467 	struct ixgbe_fc_info fc = hw->fc;
468 
469 	/* 82598 does no support link flow control with DCB enabled */
470 	if ((hw->mac.type == ixgbe_mac_82598EB) &&
471 	    (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
472 		return -EINVAL;
473 
474 	/* some devices do not support autoneg of link flow control */
475 	if ((pause->autoneg == AUTONEG_ENABLE) &&
476 	    !ixgbe_device_supports_autoneg_fc(hw))
477 		return -EINVAL;
478 
479 	fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
480 
481 	if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
482 		fc.requested_mode = ixgbe_fc_full;
483 	else if (pause->rx_pause && !pause->tx_pause)
484 		fc.requested_mode = ixgbe_fc_rx_pause;
485 	else if (!pause->rx_pause && pause->tx_pause)
486 		fc.requested_mode = ixgbe_fc_tx_pause;
487 	else
488 		fc.requested_mode = ixgbe_fc_none;
489 
490 	/* if the thing changed then we'll update and use new autoneg */
491 	if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
492 		hw->fc = fc;
493 		if (netif_running(netdev))
494 			ixgbe_reinit_locked(adapter);
495 		else
496 			ixgbe_reset(adapter);
497 	}
498 
499 	return 0;
500 }
501 
502 static u32 ixgbe_get_msglevel(struct net_device *netdev)
503 {
504 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
505 	return adapter->msg_enable;
506 }
507 
508 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
509 {
510 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
511 	adapter->msg_enable = data;
512 }
513 
514 static int ixgbe_get_regs_len(struct net_device *netdev)
515 {
516 #define IXGBE_REGS_LEN  1145
517 	return IXGBE_REGS_LEN * sizeof(u32);
518 }
519 
520 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
521 
522 static void ixgbe_get_regs(struct net_device *netdev,
523 			   struct ethtool_regs *regs, void *p)
524 {
525 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
526 	struct ixgbe_hw *hw = &adapter->hw;
527 	u32 *regs_buff = p;
528 	u8 i;
529 
530 	memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
531 
532 	regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
533 			hw->device_id;
534 
535 	/* General Registers */
536 	regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
537 	regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
538 	regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
539 	regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
540 	regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
541 	regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
542 	regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
543 	regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
544 
545 	/* NVM Register */
546 	regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
547 	regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
548 	regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
549 	regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
550 	regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
551 	regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
552 	regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
553 	regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
554 	regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
555 	regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
556 
557 	/* Interrupt */
558 	/* don't read EICR because it can clear interrupt causes, instead
559 	 * read EICS which is a shadow but doesn't clear EICR */
560 	regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
561 	regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
562 	regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
563 	regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
564 	regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
565 	regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
566 	regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
567 	regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
568 	regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
569 	regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
570 	regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
571 	regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
572 
573 	/* Flow Control */
574 	regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
575 	for (i = 0; i < 4; i++)
576 		regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i));
577 	for (i = 0; i < 8; i++) {
578 		switch (hw->mac.type) {
579 		case ixgbe_mac_82598EB:
580 			regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
581 			regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
582 			break;
583 		case ixgbe_mac_82599EB:
584 		case ixgbe_mac_X540:
585 		case ixgbe_mac_X550:
586 		case ixgbe_mac_X550EM_x:
587 		case ixgbe_mac_x550em_a:
588 			regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
589 			regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
590 			break;
591 		default:
592 			break;
593 		}
594 	}
595 	regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
596 	regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
597 
598 	/* Receive DMA */
599 	for (i = 0; i < 64; i++)
600 		regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
601 	for (i = 0; i < 64; i++)
602 		regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
603 	for (i = 0; i < 64; i++)
604 		regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
605 	for (i = 0; i < 64; i++)
606 		regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
607 	for (i = 0; i < 64; i++)
608 		regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
609 	for (i = 0; i < 64; i++)
610 		regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
611 	for (i = 0; i < 16; i++)
612 		regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
613 	for (i = 0; i < 16; i++)
614 		regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
615 	regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
616 	for (i = 0; i < 8; i++)
617 		regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
618 	regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
619 	regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
620 
621 	/* Receive */
622 	regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
623 	regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
624 	for (i = 0; i < 16; i++)
625 		regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
626 	for (i = 0; i < 16; i++)
627 		regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
628 	regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
629 	regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
630 	regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
631 	regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
632 	regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
633 	regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
634 	for (i = 0; i < 8; i++)
635 		regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
636 	for (i = 0; i < 8; i++)
637 		regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
638 	regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
639 
640 	/* Transmit */
641 	for (i = 0; i < 32; i++)
642 		regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
643 	for (i = 0; i < 32; i++)
644 		regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
645 	for (i = 0; i < 32; i++)
646 		regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
647 	for (i = 0; i < 32; i++)
648 		regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
649 	for (i = 0; i < 32; i++)
650 		regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
651 	for (i = 0; i < 32; i++)
652 		regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
653 	for (i = 0; i < 32; i++)
654 		regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
655 	for (i = 0; i < 32; i++)
656 		regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
657 	regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
658 	for (i = 0; i < 16; i++)
659 		regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
660 	regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
661 	for (i = 0; i < 8; i++)
662 		regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
663 	regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
664 
665 	/* Wake Up */
666 	regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
667 	regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
668 	regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
669 	regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
670 	regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
671 	regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
672 	regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
673 	regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
674 	regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
675 
676 	/* DCB */
677 	regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);   /* same as FCCFG  */
678 	regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
679 
680 	switch (hw->mac.type) {
681 	case ixgbe_mac_82598EB:
682 		regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
683 		regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
684 		for (i = 0; i < 8; i++)
685 			regs_buff[833 + i] =
686 				IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
687 		for (i = 0; i < 8; i++)
688 			regs_buff[841 + i] =
689 				IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
690 		for (i = 0; i < 8; i++)
691 			regs_buff[849 + i] =
692 				IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
693 		for (i = 0; i < 8; i++)
694 			regs_buff[857 + i] =
695 				IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
696 		break;
697 	case ixgbe_mac_82599EB:
698 	case ixgbe_mac_X540:
699 	case ixgbe_mac_X550:
700 	case ixgbe_mac_X550EM_x:
701 	case ixgbe_mac_x550em_a:
702 		regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
703 		regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
704 		for (i = 0; i < 8; i++)
705 			regs_buff[833 + i] =
706 				IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
707 		for (i = 0; i < 8; i++)
708 			regs_buff[841 + i] =
709 				IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
710 		for (i = 0; i < 8; i++)
711 			regs_buff[849 + i] =
712 				IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
713 		for (i = 0; i < 8; i++)
714 			regs_buff[857 + i] =
715 				IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
716 		break;
717 	default:
718 		break;
719 	}
720 
721 	for (i = 0; i < 8; i++)
722 		regs_buff[865 + i] =
723 		IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
724 	for (i = 0; i < 8; i++)
725 		regs_buff[873 + i] =
726 		IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
727 
728 	/* Statistics */
729 	regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
730 	regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
731 	regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
732 	regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
733 	for (i = 0; i < 8; i++)
734 		regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
735 	regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
736 	regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
737 	regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
738 	regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
739 	regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
740 	regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
741 	regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
742 	for (i = 0; i < 8; i++)
743 		regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
744 	for (i = 0; i < 8; i++)
745 		regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
746 	for (i = 0; i < 8; i++)
747 		regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
748 	for (i = 0; i < 8; i++)
749 		regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
750 	regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
751 	regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
752 	regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
753 	regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
754 	regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
755 	regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
756 	regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
757 	regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
758 	regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
759 	regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
760 	regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc);
761 	regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32);
762 	regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc);
763 	regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32);
764 	for (i = 0; i < 8; i++)
765 		regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
766 	regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
767 	regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
768 	regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
769 	regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
770 	regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
771 	regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
772 	regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
773 	regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor);
774 	regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32);
775 	regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
776 	regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
777 	regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
778 	regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
779 	regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
780 	regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
781 	regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
782 	regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
783 	regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
784 	regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
785 	regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
786 	for (i = 0; i < 16; i++)
787 		regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
788 	for (i = 0; i < 16; i++)
789 		regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
790 	for (i = 0; i < 16; i++)
791 		regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
792 	for (i = 0; i < 16; i++)
793 		regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
794 
795 	/* MAC */
796 	regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
797 	regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
798 	regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
799 	regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
800 	regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
801 	regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
802 	regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
803 	regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
804 	regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
805 	regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
806 	regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
807 	regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
808 	regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
809 	regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
810 	regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
811 	regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
812 	regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
813 	regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
814 	regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
815 	regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
816 	regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
817 	regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
818 	regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
819 	regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
820 	regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
821 	regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
822 	regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
823 	regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
824 	regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
825 	regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
826 	regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
827 	regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
828 	regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
829 
830 	/* Diagnostic */
831 	regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
832 	for (i = 0; i < 8; i++)
833 		regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
834 	regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
835 	for (i = 0; i < 4; i++)
836 		regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
837 	regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
838 	regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
839 	for (i = 0; i < 8; i++)
840 		regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
841 	regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
842 	for (i = 0; i < 4; i++)
843 		regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
844 	regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
845 	regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
846 	for (i = 0; i < 4; i++)
847 		regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i));
848 	regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
849 	for (i = 0; i < 4; i++)
850 		regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i));
851 	for (i = 0; i < 8; i++)
852 		regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
853 	regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
854 	regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
855 	regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
856 	regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
857 	regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
858 	regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
859 	regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
860 	regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
861 	regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
862 
863 	/* 82599 X540 specific registers  */
864 	regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
865 
866 	/* 82599 X540 specific DCB registers  */
867 	regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
868 	regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
869 	for (i = 0; i < 4; i++)
870 		regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
871 	regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
872 					/* same as RTTQCNRM */
873 	regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
874 					/* same as RTTQCNRR */
875 
876 	/* X540 specific DCB registers  */
877 	regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
878 	regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
879 
880 	/* Security config registers */
881 	regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
882 	regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
883 	regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF);
884 	regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
885 	regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
886 	regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
887 }
888 
889 static int ixgbe_get_eeprom_len(struct net_device *netdev)
890 {
891 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
892 	return adapter->hw.eeprom.word_size * 2;
893 }
894 
895 static int ixgbe_get_eeprom(struct net_device *netdev,
896 			    struct ethtool_eeprom *eeprom, u8 *bytes)
897 {
898 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
899 	struct ixgbe_hw *hw = &adapter->hw;
900 	u16 *eeprom_buff;
901 	int first_word, last_word, eeprom_len;
902 	int ret_val = 0;
903 	u16 i;
904 
905 	if (eeprom->len == 0)
906 		return -EINVAL;
907 
908 	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
909 
910 	first_word = eeprom->offset >> 1;
911 	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
912 	eeprom_len = last_word - first_word + 1;
913 
914 	eeprom_buff = kmalloc_array(eeprom_len, sizeof(u16), GFP_KERNEL);
915 	if (!eeprom_buff)
916 		return -ENOMEM;
917 
918 	ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
919 					     eeprom_buff);
920 
921 	/* Device's eeprom is always little-endian, word addressable */
922 	for (i = 0; i < eeprom_len; i++)
923 		le16_to_cpus(&eeprom_buff[i]);
924 
925 	memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
926 	kfree(eeprom_buff);
927 
928 	return ret_val;
929 }
930 
931 static int ixgbe_set_eeprom(struct net_device *netdev,
932 			    struct ethtool_eeprom *eeprom, u8 *bytes)
933 {
934 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
935 	struct ixgbe_hw *hw = &adapter->hw;
936 	u16 *eeprom_buff;
937 	void *ptr;
938 	int max_len, first_word, last_word, ret_val = 0;
939 	u16 i;
940 
941 	if (eeprom->len == 0)
942 		return -EINVAL;
943 
944 	if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
945 		return -EINVAL;
946 
947 	max_len = hw->eeprom.word_size * 2;
948 
949 	first_word = eeprom->offset >> 1;
950 	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
951 	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
952 	if (!eeprom_buff)
953 		return -ENOMEM;
954 
955 	ptr = eeprom_buff;
956 
957 	if (eeprom->offset & 1) {
958 		/*
959 		 * need read/modify/write of first changed EEPROM word
960 		 * only the second byte of the word is being modified
961 		 */
962 		ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
963 		if (ret_val)
964 			goto err;
965 
966 		ptr++;
967 	}
968 	if ((eeprom->offset + eeprom->len) & 1) {
969 		/*
970 		 * need read/modify/write of last changed EEPROM word
971 		 * only the first byte of the word is being modified
972 		 */
973 		ret_val = hw->eeprom.ops.read(hw, last_word,
974 					  &eeprom_buff[last_word - first_word]);
975 		if (ret_val)
976 			goto err;
977 	}
978 
979 	/* Device's eeprom is always little-endian, word addressable */
980 	for (i = 0; i < last_word - first_word + 1; i++)
981 		le16_to_cpus(&eeprom_buff[i]);
982 
983 	memcpy(ptr, bytes, eeprom->len);
984 
985 	for (i = 0; i < last_word - first_word + 1; i++)
986 		cpu_to_le16s(&eeprom_buff[i]);
987 
988 	ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
989 					      last_word - first_word + 1,
990 					      eeprom_buff);
991 
992 	/* Update the checksum */
993 	if (ret_val == 0)
994 		hw->eeprom.ops.update_checksum(hw);
995 
996 err:
997 	kfree(eeprom_buff);
998 	return ret_val;
999 }
1000 
1001 static void ixgbe_get_drvinfo(struct net_device *netdev,
1002 			      struct ethtool_drvinfo *drvinfo)
1003 {
1004 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1005 
1006 	strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
1007 	strlcpy(drvinfo->version, ixgbe_driver_version,
1008 		sizeof(drvinfo->version));
1009 
1010 	strlcpy(drvinfo->fw_version, adapter->eeprom_id,
1011 		sizeof(drvinfo->fw_version));
1012 
1013 	strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
1014 		sizeof(drvinfo->bus_info));
1015 
1016 	drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN;
1017 }
1018 
1019 static void ixgbe_get_ringparam(struct net_device *netdev,
1020 				struct ethtool_ringparam *ring)
1021 {
1022 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1023 	struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1024 	struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1025 
1026 	ring->rx_max_pending = IXGBE_MAX_RXD;
1027 	ring->tx_max_pending = IXGBE_MAX_TXD;
1028 	ring->rx_pending = rx_ring->count;
1029 	ring->tx_pending = tx_ring->count;
1030 }
1031 
1032 static int ixgbe_set_ringparam(struct net_device *netdev,
1033 			       struct ethtool_ringparam *ring)
1034 {
1035 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1036 	struct ixgbe_ring *temp_ring;
1037 	int i, j, err = 0;
1038 	u32 new_rx_count, new_tx_count;
1039 
1040 	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1041 		return -EINVAL;
1042 
1043 	new_tx_count = clamp_t(u32, ring->tx_pending,
1044 			       IXGBE_MIN_TXD, IXGBE_MAX_TXD);
1045 	new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
1046 
1047 	new_rx_count = clamp_t(u32, ring->rx_pending,
1048 			       IXGBE_MIN_RXD, IXGBE_MAX_RXD);
1049 	new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
1050 
1051 	if ((new_tx_count == adapter->tx_ring_count) &&
1052 	    (new_rx_count == adapter->rx_ring_count)) {
1053 		/* nothing to do */
1054 		return 0;
1055 	}
1056 
1057 	while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1058 		usleep_range(1000, 2000);
1059 
1060 	if (!netif_running(adapter->netdev)) {
1061 		for (i = 0; i < adapter->num_tx_queues; i++)
1062 			adapter->tx_ring[i]->count = new_tx_count;
1063 		for (i = 0; i < adapter->num_xdp_queues; i++)
1064 			adapter->xdp_ring[i]->count = new_tx_count;
1065 		for (i = 0; i < adapter->num_rx_queues; i++)
1066 			adapter->rx_ring[i]->count = new_rx_count;
1067 		adapter->tx_ring_count = new_tx_count;
1068 		adapter->xdp_ring_count = new_tx_count;
1069 		adapter->rx_ring_count = new_rx_count;
1070 		goto clear_reset;
1071 	}
1072 
1073 	/* allocate temporary buffer to store rings in */
1074 	i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues,
1075 		  adapter->num_rx_queues);
1076 	temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring)));
1077 
1078 	if (!temp_ring) {
1079 		err = -ENOMEM;
1080 		goto clear_reset;
1081 	}
1082 
1083 	ixgbe_down(adapter);
1084 
1085 	/*
1086 	 * Setup new Tx resources and free the old Tx resources in that order.
1087 	 * We can then assign the new resources to the rings via a memcpy.
1088 	 * The advantage to this approach is that we are guaranteed to still
1089 	 * have resources even in the case of an allocation failure.
1090 	 */
1091 	if (new_tx_count != adapter->tx_ring_count) {
1092 		for (i = 0; i < adapter->num_tx_queues; i++) {
1093 			memcpy(&temp_ring[i], adapter->tx_ring[i],
1094 			       sizeof(struct ixgbe_ring));
1095 
1096 			temp_ring[i].count = new_tx_count;
1097 			err = ixgbe_setup_tx_resources(&temp_ring[i]);
1098 			if (err) {
1099 				while (i) {
1100 					i--;
1101 					ixgbe_free_tx_resources(&temp_ring[i]);
1102 				}
1103 				goto err_setup;
1104 			}
1105 		}
1106 
1107 		for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1108 			memcpy(&temp_ring[i], adapter->xdp_ring[j],
1109 			       sizeof(struct ixgbe_ring));
1110 
1111 			temp_ring[i].count = new_tx_count;
1112 			err = ixgbe_setup_tx_resources(&temp_ring[i]);
1113 			if (err) {
1114 				while (i) {
1115 					i--;
1116 					ixgbe_free_tx_resources(&temp_ring[i]);
1117 				}
1118 				goto err_setup;
1119 			}
1120 		}
1121 
1122 		for (i = 0; i < adapter->num_tx_queues; i++) {
1123 			ixgbe_free_tx_resources(adapter->tx_ring[i]);
1124 
1125 			memcpy(adapter->tx_ring[i], &temp_ring[i],
1126 			       sizeof(struct ixgbe_ring));
1127 		}
1128 		for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1129 			ixgbe_free_tx_resources(adapter->xdp_ring[j]);
1130 
1131 			memcpy(adapter->xdp_ring[j], &temp_ring[i],
1132 			       sizeof(struct ixgbe_ring));
1133 		}
1134 
1135 		adapter->tx_ring_count = new_tx_count;
1136 	}
1137 
1138 	/* Repeat the process for the Rx rings if needed */
1139 	if (new_rx_count != adapter->rx_ring_count) {
1140 		for (i = 0; i < adapter->num_rx_queues; i++) {
1141 			memcpy(&temp_ring[i], adapter->rx_ring[i],
1142 			       sizeof(struct ixgbe_ring));
1143 
1144 			/* Clear copied XDP RX-queue info */
1145 			memset(&temp_ring[i].xdp_rxq, 0,
1146 			       sizeof(temp_ring[i].xdp_rxq));
1147 
1148 			temp_ring[i].count = new_rx_count;
1149 			err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]);
1150 			if (err) {
1151 				while (i) {
1152 					i--;
1153 					ixgbe_free_rx_resources(&temp_ring[i]);
1154 				}
1155 				goto err_setup;
1156 			}
1157 
1158 		}
1159 
1160 		for (i = 0; i < adapter->num_rx_queues; i++) {
1161 			ixgbe_free_rx_resources(adapter->rx_ring[i]);
1162 
1163 			memcpy(adapter->rx_ring[i], &temp_ring[i],
1164 			       sizeof(struct ixgbe_ring));
1165 		}
1166 
1167 		adapter->rx_ring_count = new_rx_count;
1168 	}
1169 
1170 err_setup:
1171 	ixgbe_up(adapter);
1172 	vfree(temp_ring);
1173 clear_reset:
1174 	clear_bit(__IXGBE_RESETTING, &adapter->state);
1175 	return err;
1176 }
1177 
1178 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1179 {
1180 	switch (sset) {
1181 	case ETH_SS_TEST:
1182 		return IXGBE_TEST_LEN;
1183 	case ETH_SS_STATS:
1184 		return IXGBE_STATS_LEN;
1185 	case ETH_SS_PRIV_FLAGS:
1186 		return IXGBE_PRIV_FLAGS_STR_LEN;
1187 	default:
1188 		return -EOPNOTSUPP;
1189 	}
1190 }
1191 
1192 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1193 				    struct ethtool_stats *stats, u64 *data)
1194 {
1195 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1196 	struct rtnl_link_stats64 temp;
1197 	const struct rtnl_link_stats64 *net_stats;
1198 	unsigned int start;
1199 	struct ixgbe_ring *ring;
1200 	int i, j;
1201 	char *p = NULL;
1202 
1203 	ixgbe_update_stats(adapter);
1204 	net_stats = dev_get_stats(netdev, &temp);
1205 	for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1206 		switch (ixgbe_gstrings_stats[i].type) {
1207 		case NETDEV_STATS:
1208 			p = (char *) net_stats +
1209 					ixgbe_gstrings_stats[i].stat_offset;
1210 			break;
1211 		case IXGBE_STATS:
1212 			p = (char *) adapter +
1213 					ixgbe_gstrings_stats[i].stat_offset;
1214 			break;
1215 		default:
1216 			data[i] = 0;
1217 			continue;
1218 		}
1219 
1220 		data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1221 			   sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1222 	}
1223 	for (j = 0; j < netdev->num_tx_queues; j++) {
1224 		ring = adapter->tx_ring[j];
1225 		if (!ring) {
1226 			data[i] = 0;
1227 			data[i+1] = 0;
1228 			i += 2;
1229 			continue;
1230 		}
1231 
1232 		do {
1233 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1234 			data[i]   = ring->stats.packets;
1235 			data[i+1] = ring->stats.bytes;
1236 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1237 		i += 2;
1238 	}
1239 	for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1240 		ring = adapter->rx_ring[j];
1241 		if (!ring) {
1242 			data[i] = 0;
1243 			data[i+1] = 0;
1244 			i += 2;
1245 			continue;
1246 		}
1247 
1248 		do {
1249 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1250 			data[i]   = ring->stats.packets;
1251 			data[i+1] = ring->stats.bytes;
1252 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1253 		i += 2;
1254 	}
1255 
1256 	for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1257 		data[i++] = adapter->stats.pxontxc[j];
1258 		data[i++] = adapter->stats.pxofftxc[j];
1259 	}
1260 	for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1261 		data[i++] = adapter->stats.pxonrxc[j];
1262 		data[i++] = adapter->stats.pxoffrxc[j];
1263 	}
1264 }
1265 
1266 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1267 			      u8 *data)
1268 {
1269 	char *p = (char *)data;
1270 	unsigned int i;
1271 
1272 	switch (stringset) {
1273 	case ETH_SS_TEST:
1274 		for (i = 0; i < IXGBE_TEST_LEN; i++) {
1275 			memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1276 			data += ETH_GSTRING_LEN;
1277 		}
1278 		break;
1279 	case ETH_SS_STATS:
1280 		for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1281 			memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1282 			       ETH_GSTRING_LEN);
1283 			p += ETH_GSTRING_LEN;
1284 		}
1285 		for (i = 0; i < netdev->num_tx_queues; i++) {
1286 			sprintf(p, "tx_queue_%u_packets", i);
1287 			p += ETH_GSTRING_LEN;
1288 			sprintf(p, "tx_queue_%u_bytes", i);
1289 			p += ETH_GSTRING_LEN;
1290 		}
1291 		for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1292 			sprintf(p, "rx_queue_%u_packets", i);
1293 			p += ETH_GSTRING_LEN;
1294 			sprintf(p, "rx_queue_%u_bytes", i);
1295 			p += ETH_GSTRING_LEN;
1296 		}
1297 		for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1298 			sprintf(p, "tx_pb_%u_pxon", i);
1299 			p += ETH_GSTRING_LEN;
1300 			sprintf(p, "tx_pb_%u_pxoff", i);
1301 			p += ETH_GSTRING_LEN;
1302 		}
1303 		for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1304 			sprintf(p, "rx_pb_%u_pxon", i);
1305 			p += ETH_GSTRING_LEN;
1306 			sprintf(p, "rx_pb_%u_pxoff", i);
1307 			p += ETH_GSTRING_LEN;
1308 		}
1309 		/* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1310 		break;
1311 	case ETH_SS_PRIV_FLAGS:
1312 		memcpy(data, ixgbe_priv_flags_strings,
1313 		       IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
1314 	}
1315 }
1316 
1317 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1318 {
1319 	struct ixgbe_hw *hw = &adapter->hw;
1320 	bool link_up;
1321 	u32 link_speed = 0;
1322 
1323 	if (ixgbe_removed(hw->hw_addr)) {
1324 		*data = 1;
1325 		return 1;
1326 	}
1327 	*data = 0;
1328 
1329 	hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1330 	if (link_up)
1331 		return *data;
1332 	else
1333 		*data = 1;
1334 	return *data;
1335 }
1336 
1337 /* ethtool register test data */
1338 struct ixgbe_reg_test {
1339 	u16 reg;
1340 	u8  array_len;
1341 	u8  test_type;
1342 	u32 mask;
1343 	u32 write;
1344 };
1345 
1346 /* In the hardware, registers are laid out either singly, in arrays
1347  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1348  * most tests take place on arrays or single registers (handled
1349  * as a single-element array) and special-case the tables.
1350  * Table tests are always pattern tests.
1351  *
1352  * We also make provision for some required setup steps by specifying
1353  * registers to be written without any read-back testing.
1354  */
1355 
1356 #define PATTERN_TEST	1
1357 #define SET_READ_TEST	2
1358 #define WRITE_NO_TEST	3
1359 #define TABLE32_TEST	4
1360 #define TABLE64_TEST_LO	5
1361 #define TABLE64_TEST_HI	6
1362 
1363 /* default 82599 register test */
1364 static const struct ixgbe_reg_test reg_test_82599[] = {
1365 	{ IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1366 	{ IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1367 	{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1368 	{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1369 	{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1370 	{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1371 	{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1372 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1373 	{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1374 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1375 	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1376 	{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1377 	{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1378 	{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1379 	{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1380 	{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1381 	{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1382 	{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1383 	{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1384 	{ .reg = 0 }
1385 };
1386 
1387 /* default 82598 register test */
1388 static const struct ixgbe_reg_test reg_test_82598[] = {
1389 	{ IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1390 	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1391 	{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1392 	{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1393 	{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1394 	{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1395 	{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1396 	/* Enable all four RX queues before testing. */
1397 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1398 	/* RDH is read-only for 82598, only test RDT. */
1399 	{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1400 	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1401 	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1402 	{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1403 	{ IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1404 	{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1405 	{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1406 	{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1407 	{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1408 	{ IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1409 	{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1410 	{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1411 	{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1412 	{ .reg = 0 }
1413 };
1414 
1415 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1416 			     u32 mask, u32 write)
1417 {
1418 	u32 pat, val, before;
1419 	static const u32 test_pattern[] = {
1420 		0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1421 
1422 	if (ixgbe_removed(adapter->hw.hw_addr)) {
1423 		*data = 1;
1424 		return true;
1425 	}
1426 	for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1427 		before = ixgbe_read_reg(&adapter->hw, reg);
1428 		ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1429 		val = ixgbe_read_reg(&adapter->hw, reg);
1430 		if (val != (test_pattern[pat] & write & mask)) {
1431 			e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1432 			      reg, val, (test_pattern[pat] & write & mask));
1433 			*data = reg;
1434 			ixgbe_write_reg(&adapter->hw, reg, before);
1435 			return true;
1436 		}
1437 		ixgbe_write_reg(&adapter->hw, reg, before);
1438 	}
1439 	return false;
1440 }
1441 
1442 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1443 			      u32 mask, u32 write)
1444 {
1445 	u32 val, before;
1446 
1447 	if (ixgbe_removed(adapter->hw.hw_addr)) {
1448 		*data = 1;
1449 		return true;
1450 	}
1451 	before = ixgbe_read_reg(&adapter->hw, reg);
1452 	ixgbe_write_reg(&adapter->hw, reg, write & mask);
1453 	val = ixgbe_read_reg(&adapter->hw, reg);
1454 	if ((write & mask) != (val & mask)) {
1455 		e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1456 		      reg, (val & mask), (write & mask));
1457 		*data = reg;
1458 		ixgbe_write_reg(&adapter->hw, reg, before);
1459 		return true;
1460 	}
1461 	ixgbe_write_reg(&adapter->hw, reg, before);
1462 	return false;
1463 }
1464 
1465 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1466 {
1467 	const struct ixgbe_reg_test *test;
1468 	u32 value, before, after;
1469 	u32 i, toggle;
1470 
1471 	if (ixgbe_removed(adapter->hw.hw_addr)) {
1472 		e_err(drv, "Adapter removed - register test blocked\n");
1473 		*data = 1;
1474 		return 1;
1475 	}
1476 	switch (adapter->hw.mac.type) {
1477 	case ixgbe_mac_82598EB:
1478 		toggle = 0x7FFFF3FF;
1479 		test = reg_test_82598;
1480 		break;
1481 	case ixgbe_mac_82599EB:
1482 	case ixgbe_mac_X540:
1483 	case ixgbe_mac_X550:
1484 	case ixgbe_mac_X550EM_x:
1485 	case ixgbe_mac_x550em_a:
1486 		toggle = 0x7FFFF30F;
1487 		test = reg_test_82599;
1488 		break;
1489 	default:
1490 		*data = 1;
1491 		return 1;
1492 	}
1493 
1494 	/*
1495 	 * Because the status register is such a special case,
1496 	 * we handle it separately from the rest of the register
1497 	 * tests.  Some bits are read-only, some toggle, and some
1498 	 * are writeable on newer MACs.
1499 	 */
1500 	before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1501 	value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1502 	ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1503 	after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
1504 	if (value != after) {
1505 		e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1506 		      after, value);
1507 		*data = 1;
1508 		return 1;
1509 	}
1510 	/* restore previous status */
1511 	ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
1512 
1513 	/*
1514 	 * Perform the remainder of the register test, looping through
1515 	 * the test table until we either fail or reach the null entry.
1516 	 */
1517 	while (test->reg) {
1518 		for (i = 0; i < test->array_len; i++) {
1519 			bool b = false;
1520 
1521 			switch (test->test_type) {
1522 			case PATTERN_TEST:
1523 				b = reg_pattern_test(adapter, data,
1524 						     test->reg + (i * 0x40),
1525 						     test->mask,
1526 						     test->write);
1527 				break;
1528 			case SET_READ_TEST:
1529 				b = reg_set_and_check(adapter, data,
1530 						      test->reg + (i * 0x40),
1531 						      test->mask,
1532 						      test->write);
1533 				break;
1534 			case WRITE_NO_TEST:
1535 				ixgbe_write_reg(&adapter->hw,
1536 						test->reg + (i * 0x40),
1537 						test->write);
1538 				break;
1539 			case TABLE32_TEST:
1540 				b = reg_pattern_test(adapter, data,
1541 						     test->reg + (i * 4),
1542 						     test->mask,
1543 						     test->write);
1544 				break;
1545 			case TABLE64_TEST_LO:
1546 				b = reg_pattern_test(adapter, data,
1547 						     test->reg + (i * 8),
1548 						     test->mask,
1549 						     test->write);
1550 				break;
1551 			case TABLE64_TEST_HI:
1552 				b = reg_pattern_test(adapter, data,
1553 						     (test->reg + 4) + (i * 8),
1554 						     test->mask,
1555 						     test->write);
1556 				break;
1557 			}
1558 			if (b)
1559 				return 1;
1560 		}
1561 		test++;
1562 	}
1563 
1564 	*data = 0;
1565 	return 0;
1566 }
1567 
1568 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1569 {
1570 	struct ixgbe_hw *hw = &adapter->hw;
1571 	if (hw->eeprom.ops.validate_checksum(hw, NULL))
1572 		*data = 1;
1573 	else
1574 		*data = 0;
1575 	return *data;
1576 }
1577 
1578 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1579 {
1580 	struct net_device *netdev = (struct net_device *) data;
1581 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1582 
1583 	adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1584 
1585 	return IRQ_HANDLED;
1586 }
1587 
1588 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1589 {
1590 	struct net_device *netdev = adapter->netdev;
1591 	u32 mask, i = 0, shared_int = true;
1592 	u32 irq = adapter->pdev->irq;
1593 
1594 	*data = 0;
1595 
1596 	/* Hook up test interrupt handler just for this test */
1597 	if (adapter->msix_entries) {
1598 		/* NOTE: we don't test MSI-X interrupts here, yet */
1599 		return 0;
1600 	} else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1601 		shared_int = false;
1602 		if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1603 				netdev)) {
1604 			*data = 1;
1605 			return -1;
1606 		}
1607 	} else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1608 				netdev->name, netdev)) {
1609 		shared_int = false;
1610 	} else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1611 			       netdev->name, netdev)) {
1612 		*data = 1;
1613 		return -1;
1614 	}
1615 	e_info(hw, "testing %s interrupt\n", shared_int ?
1616 	       "shared" : "unshared");
1617 
1618 	/* Disable all the interrupts */
1619 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1620 	IXGBE_WRITE_FLUSH(&adapter->hw);
1621 	usleep_range(10000, 20000);
1622 
1623 	/* Test each interrupt */
1624 	for (; i < 10; i++) {
1625 		/* Interrupt to test */
1626 		mask = BIT(i);
1627 
1628 		if (!shared_int) {
1629 			/*
1630 			 * Disable the interrupts to be reported in
1631 			 * the cause register and then force the same
1632 			 * interrupt and see if one gets posted.  If
1633 			 * an interrupt was posted to the bus, the
1634 			 * test failed.
1635 			 */
1636 			adapter->test_icr = 0;
1637 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1638 					~mask & 0x00007FFF);
1639 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1640 					~mask & 0x00007FFF);
1641 			IXGBE_WRITE_FLUSH(&adapter->hw);
1642 			usleep_range(10000, 20000);
1643 
1644 			if (adapter->test_icr & mask) {
1645 				*data = 3;
1646 				break;
1647 			}
1648 		}
1649 
1650 		/*
1651 		 * Enable the interrupt to be reported in the cause
1652 		 * register and then force the same interrupt and see
1653 		 * if one gets posted.  If an interrupt was not posted
1654 		 * to the bus, the test failed.
1655 		 */
1656 		adapter->test_icr = 0;
1657 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1658 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1659 		IXGBE_WRITE_FLUSH(&adapter->hw);
1660 		usleep_range(10000, 20000);
1661 
1662 		if (!(adapter->test_icr & mask)) {
1663 			*data = 4;
1664 			break;
1665 		}
1666 
1667 		if (!shared_int) {
1668 			/*
1669 			 * Disable the other interrupts to be reported in
1670 			 * the cause register and then force the other
1671 			 * interrupts and see if any get posted.  If
1672 			 * an interrupt was posted to the bus, the
1673 			 * test failed.
1674 			 */
1675 			adapter->test_icr = 0;
1676 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1677 					~mask & 0x00007FFF);
1678 			IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1679 					~mask & 0x00007FFF);
1680 			IXGBE_WRITE_FLUSH(&adapter->hw);
1681 			usleep_range(10000, 20000);
1682 
1683 			if (adapter->test_icr) {
1684 				*data = 5;
1685 				break;
1686 			}
1687 		}
1688 	}
1689 
1690 	/* Disable all the interrupts */
1691 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1692 	IXGBE_WRITE_FLUSH(&adapter->hw);
1693 	usleep_range(10000, 20000);
1694 
1695 	/* Unhook test interrupt handler */
1696 	free_irq(irq, netdev);
1697 
1698 	return *data;
1699 }
1700 
1701 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1702 {
1703 	/* Shut down the DMA engines now so they can be reinitialized later,
1704 	 * since the test rings and normally used rings should overlap on
1705 	 * queue 0 we can just use the standard disable Rx/Tx calls and they
1706 	 * will take care of disabling the test rings for us.
1707 	 */
1708 
1709 	/* first Rx */
1710 	ixgbe_disable_rx(adapter);
1711 
1712 	/* now Tx */
1713 	ixgbe_disable_tx(adapter);
1714 
1715 	ixgbe_reset(adapter);
1716 
1717 	ixgbe_free_tx_resources(&adapter->test_tx_ring);
1718 	ixgbe_free_rx_resources(&adapter->test_rx_ring);
1719 }
1720 
1721 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1722 {
1723 	struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1724 	struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1725 	struct ixgbe_hw *hw = &adapter->hw;
1726 	u32 rctl, reg_data;
1727 	int ret_val;
1728 	int err;
1729 
1730 	/* Setup Tx descriptor ring and Tx buffers */
1731 	tx_ring->count = IXGBE_DEFAULT_TXD;
1732 	tx_ring->queue_index = 0;
1733 	tx_ring->dev = &adapter->pdev->dev;
1734 	tx_ring->netdev = adapter->netdev;
1735 	tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1736 
1737 	err = ixgbe_setup_tx_resources(tx_ring);
1738 	if (err)
1739 		return 1;
1740 
1741 	switch (adapter->hw.mac.type) {
1742 	case ixgbe_mac_82599EB:
1743 	case ixgbe_mac_X540:
1744 	case ixgbe_mac_X550:
1745 	case ixgbe_mac_X550EM_x:
1746 	case ixgbe_mac_x550em_a:
1747 		reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1748 		reg_data |= IXGBE_DMATXCTL_TE;
1749 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1750 		break;
1751 	default:
1752 		break;
1753 	}
1754 
1755 	ixgbe_configure_tx_ring(adapter, tx_ring);
1756 
1757 	/* Setup Rx Descriptor ring and Rx buffers */
1758 	rx_ring->count = IXGBE_DEFAULT_RXD;
1759 	rx_ring->queue_index = 0;
1760 	rx_ring->dev = &adapter->pdev->dev;
1761 	rx_ring->netdev = adapter->netdev;
1762 	rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1763 
1764 	err = ixgbe_setup_rx_resources(adapter, rx_ring);
1765 	if (err) {
1766 		ret_val = 4;
1767 		goto err_nomem;
1768 	}
1769 
1770 	hw->mac.ops.disable_rx(hw);
1771 
1772 	ixgbe_configure_rx_ring(adapter, rx_ring);
1773 
1774 	rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1775 	rctl |= IXGBE_RXCTRL_DMBYPS;
1776 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1777 
1778 	hw->mac.ops.enable_rx(hw);
1779 
1780 	return 0;
1781 
1782 err_nomem:
1783 	ixgbe_free_desc_rings(adapter);
1784 	return ret_val;
1785 }
1786 
1787 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1788 {
1789 	struct ixgbe_hw *hw = &adapter->hw;
1790 	u32 reg_data;
1791 
1792 
1793 	/* Setup MAC loopback */
1794 	reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1795 	reg_data |= IXGBE_HLREG0_LPBK;
1796 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1797 
1798 	reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1799 	reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1800 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1801 
1802 	/* X540 and X550 needs to set the MACC.FLU bit to force link up */
1803 	switch (adapter->hw.mac.type) {
1804 	case ixgbe_mac_X540:
1805 	case ixgbe_mac_X550:
1806 	case ixgbe_mac_X550EM_x:
1807 	case ixgbe_mac_x550em_a:
1808 		reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1809 		reg_data |= IXGBE_MACC_FLU;
1810 		IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1811 		break;
1812 	default:
1813 		if (hw->mac.orig_autoc) {
1814 			reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1815 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1816 		} else {
1817 			return 10;
1818 		}
1819 	}
1820 	IXGBE_WRITE_FLUSH(hw);
1821 	usleep_range(10000, 20000);
1822 
1823 	/* Disable Atlas Tx lanes; re-enabled in reset path */
1824 	if (hw->mac.type == ixgbe_mac_82598EB) {
1825 		u8 atlas;
1826 
1827 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1828 		atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1829 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1830 
1831 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1832 		atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1833 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1834 
1835 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1836 		atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1837 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1838 
1839 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1840 		atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1841 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1842 	}
1843 
1844 	return 0;
1845 }
1846 
1847 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1848 {
1849 	u32 reg_data;
1850 
1851 	reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1852 	reg_data &= ~IXGBE_HLREG0_LPBK;
1853 	IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1854 }
1855 
1856 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1857 				      unsigned int frame_size)
1858 {
1859 	memset(skb->data, 0xFF, frame_size);
1860 	frame_size >>= 1;
1861 	memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1862 	memset(&skb->data[frame_size + 10], 0xBE, 1);
1863 	memset(&skb->data[frame_size + 12], 0xAF, 1);
1864 }
1865 
1866 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1867 				     unsigned int frame_size)
1868 {
1869 	unsigned char *data;
1870 	bool match = true;
1871 
1872 	frame_size >>= 1;
1873 
1874 	data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1875 
1876 	if (data[3] != 0xFF ||
1877 	    data[frame_size + 10] != 0xBE ||
1878 	    data[frame_size + 12] != 0xAF)
1879 		match = false;
1880 
1881 	kunmap(rx_buffer->page);
1882 
1883 	return match;
1884 }
1885 
1886 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1887 				  struct ixgbe_ring *tx_ring,
1888 				  unsigned int size)
1889 {
1890 	union ixgbe_adv_rx_desc *rx_desc;
1891 	u16 rx_ntc, tx_ntc, count = 0;
1892 
1893 	/* initialize next to clean and descriptor values */
1894 	rx_ntc = rx_ring->next_to_clean;
1895 	tx_ntc = tx_ring->next_to_clean;
1896 	rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1897 
1898 	while (tx_ntc != tx_ring->next_to_use) {
1899 		union ixgbe_adv_tx_desc *tx_desc;
1900 		struct ixgbe_tx_buffer *tx_buffer;
1901 
1902 		tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc);
1903 
1904 		/* if DD is not set transmit has not completed */
1905 		if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1906 			return count;
1907 
1908 		/* unmap buffer on Tx side */
1909 		tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1910 
1911 		/* Free all the Tx ring sk_buffs */
1912 		dev_kfree_skb_any(tx_buffer->skb);
1913 
1914 		/* unmap skb header data */
1915 		dma_unmap_single(tx_ring->dev,
1916 				 dma_unmap_addr(tx_buffer, dma),
1917 				 dma_unmap_len(tx_buffer, len),
1918 				 DMA_TO_DEVICE);
1919 		dma_unmap_len_set(tx_buffer, len, 0);
1920 
1921 		/* increment Tx next to clean counter */
1922 		tx_ntc++;
1923 		if (tx_ntc == tx_ring->count)
1924 			tx_ntc = 0;
1925 	}
1926 
1927 	while (rx_desc->wb.upper.length) {
1928 		struct ixgbe_rx_buffer *rx_buffer;
1929 
1930 		/* check Rx buffer */
1931 		rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
1932 
1933 		/* sync Rx buffer for CPU read */
1934 		dma_sync_single_for_cpu(rx_ring->dev,
1935 					rx_buffer->dma,
1936 					ixgbe_rx_bufsz(rx_ring),
1937 					DMA_FROM_DEVICE);
1938 
1939 		/* verify contents of skb */
1940 		if (ixgbe_check_lbtest_frame(rx_buffer, size))
1941 			count++;
1942 		else
1943 			break;
1944 
1945 		/* sync Rx buffer for device write */
1946 		dma_sync_single_for_device(rx_ring->dev,
1947 					   rx_buffer->dma,
1948 					   ixgbe_rx_bufsz(rx_ring),
1949 					   DMA_FROM_DEVICE);
1950 
1951 		/* increment Rx next to clean counter */
1952 		rx_ntc++;
1953 		if (rx_ntc == rx_ring->count)
1954 			rx_ntc = 0;
1955 
1956 		/* fetch next descriptor */
1957 		rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1958 	}
1959 
1960 	netdev_tx_reset_queue(txring_txq(tx_ring));
1961 
1962 	/* re-map buffers to ring, store next to clean values */
1963 	ixgbe_alloc_rx_buffers(rx_ring, count);
1964 	rx_ring->next_to_clean = rx_ntc;
1965 	tx_ring->next_to_clean = tx_ntc;
1966 
1967 	return count;
1968 }
1969 
1970 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1971 {
1972 	struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1973 	struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1974 	int i, j, lc, good_cnt, ret_val = 0;
1975 	unsigned int size = 1024;
1976 	netdev_tx_t tx_ret_val;
1977 	struct sk_buff *skb;
1978 	u32 flags_orig = adapter->flags;
1979 
1980 	/* DCB can modify the frames on Tx */
1981 	adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1982 
1983 	/* allocate test skb */
1984 	skb = alloc_skb(size, GFP_KERNEL);
1985 	if (!skb)
1986 		return 11;
1987 
1988 	/* place data into test skb */
1989 	ixgbe_create_lbtest_frame(skb, size);
1990 	skb_put(skb, size);
1991 
1992 	/*
1993 	 * Calculate the loop count based on the largest descriptor ring
1994 	 * The idea is to wrap the largest ring a number of times using 64
1995 	 * send/receive pairs during each loop
1996 	 */
1997 
1998 	if (rx_ring->count <= tx_ring->count)
1999 		lc = ((tx_ring->count / 64) * 2) + 1;
2000 	else
2001 		lc = ((rx_ring->count / 64) * 2) + 1;
2002 
2003 	for (j = 0; j <= lc; j++) {
2004 		/* reset count of good packets */
2005 		good_cnt = 0;
2006 
2007 		/* place 64 packets on the transmit queue*/
2008 		for (i = 0; i < 64; i++) {
2009 			skb_get(skb);
2010 			tx_ret_val = ixgbe_xmit_frame_ring(skb,
2011 							   adapter,
2012 							   tx_ring);
2013 			if (tx_ret_val == NETDEV_TX_OK)
2014 				good_cnt++;
2015 		}
2016 
2017 		if (good_cnt != 64) {
2018 			ret_val = 12;
2019 			break;
2020 		}
2021 
2022 		/* allow 200 milliseconds for packets to go from Tx to Rx */
2023 		msleep(200);
2024 
2025 		good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
2026 		if (good_cnt != 64) {
2027 			ret_val = 13;
2028 			break;
2029 		}
2030 	}
2031 
2032 	/* free the original skb */
2033 	kfree_skb(skb);
2034 	adapter->flags = flags_orig;
2035 
2036 	return ret_val;
2037 }
2038 
2039 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
2040 {
2041 	*data = ixgbe_setup_desc_rings(adapter);
2042 	if (*data)
2043 		goto out;
2044 	*data = ixgbe_setup_loopback_test(adapter);
2045 	if (*data)
2046 		goto err_loopback;
2047 	*data = ixgbe_run_loopback_test(adapter);
2048 	ixgbe_loopback_cleanup(adapter);
2049 
2050 err_loopback:
2051 	ixgbe_free_desc_rings(adapter);
2052 out:
2053 	return *data;
2054 }
2055 
2056 static void ixgbe_diag_test(struct net_device *netdev,
2057 			    struct ethtool_test *eth_test, u64 *data)
2058 {
2059 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2060 	bool if_running = netif_running(netdev);
2061 
2062 	if (ixgbe_removed(adapter->hw.hw_addr)) {
2063 		e_err(hw, "Adapter removed - test blocked\n");
2064 		data[0] = 1;
2065 		data[1] = 1;
2066 		data[2] = 1;
2067 		data[3] = 1;
2068 		data[4] = 1;
2069 		eth_test->flags |= ETH_TEST_FL_FAILED;
2070 		return;
2071 	}
2072 	set_bit(__IXGBE_TESTING, &adapter->state);
2073 	if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2074 		struct ixgbe_hw *hw = &adapter->hw;
2075 
2076 		if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2077 			int i;
2078 			for (i = 0; i < adapter->num_vfs; i++) {
2079 				if (adapter->vfinfo[i].clear_to_send) {
2080 					netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
2081 					data[0] = 1;
2082 					data[1] = 1;
2083 					data[2] = 1;
2084 					data[3] = 1;
2085 					data[4] = 1;
2086 					eth_test->flags |= ETH_TEST_FL_FAILED;
2087 					clear_bit(__IXGBE_TESTING,
2088 						  &adapter->state);
2089 					goto skip_ol_tests;
2090 				}
2091 			}
2092 		}
2093 
2094 		/* Offline tests */
2095 		e_info(hw, "offline testing starting\n");
2096 
2097 		/* Link test performed before hardware reset so autoneg doesn't
2098 		 * interfere with test result
2099 		 */
2100 		if (ixgbe_link_test(adapter, &data[4]))
2101 			eth_test->flags |= ETH_TEST_FL_FAILED;
2102 
2103 		if (if_running)
2104 			/* indicate we're in test mode */
2105 			ixgbe_close(netdev);
2106 		else
2107 			ixgbe_reset(adapter);
2108 
2109 		e_info(hw, "register testing starting\n");
2110 		if (ixgbe_reg_test(adapter, &data[0]))
2111 			eth_test->flags |= ETH_TEST_FL_FAILED;
2112 
2113 		ixgbe_reset(adapter);
2114 		e_info(hw, "eeprom testing starting\n");
2115 		if (ixgbe_eeprom_test(adapter, &data[1]))
2116 			eth_test->flags |= ETH_TEST_FL_FAILED;
2117 
2118 		ixgbe_reset(adapter);
2119 		e_info(hw, "interrupt testing starting\n");
2120 		if (ixgbe_intr_test(adapter, &data[2]))
2121 			eth_test->flags |= ETH_TEST_FL_FAILED;
2122 
2123 		/* If SRIOV or VMDq is enabled then skip MAC
2124 		 * loopback diagnostic. */
2125 		if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2126 				      IXGBE_FLAG_VMDQ_ENABLED)) {
2127 			e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2128 			data[3] = 0;
2129 			goto skip_loopback;
2130 		}
2131 
2132 		ixgbe_reset(adapter);
2133 		e_info(hw, "loopback testing starting\n");
2134 		if (ixgbe_loopback_test(adapter, &data[3]))
2135 			eth_test->flags |= ETH_TEST_FL_FAILED;
2136 
2137 skip_loopback:
2138 		ixgbe_reset(adapter);
2139 
2140 		/* clear testing bit and return adapter to previous state */
2141 		clear_bit(__IXGBE_TESTING, &adapter->state);
2142 		if (if_running)
2143 			ixgbe_open(netdev);
2144 		else if (hw->mac.ops.disable_tx_laser)
2145 			hw->mac.ops.disable_tx_laser(hw);
2146 	} else {
2147 		e_info(hw, "online testing starting\n");
2148 
2149 		/* Online tests */
2150 		if (ixgbe_link_test(adapter, &data[4]))
2151 			eth_test->flags |= ETH_TEST_FL_FAILED;
2152 
2153 		/* Offline tests aren't run; pass by default */
2154 		data[0] = 0;
2155 		data[1] = 0;
2156 		data[2] = 0;
2157 		data[3] = 0;
2158 
2159 		clear_bit(__IXGBE_TESTING, &adapter->state);
2160 	}
2161 
2162 skip_ol_tests:
2163 	msleep_interruptible(4 * 1000);
2164 }
2165 
2166 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2167 			       struct ethtool_wolinfo *wol)
2168 {
2169 	struct ixgbe_hw *hw = &adapter->hw;
2170 	int retval = 0;
2171 
2172 	/* WOL not supported for all devices */
2173 	if (!ixgbe_wol_supported(adapter, hw->device_id,
2174 				 hw->subsystem_device_id)) {
2175 		retval = 1;
2176 		wol->supported = 0;
2177 	}
2178 
2179 	return retval;
2180 }
2181 
2182 static void ixgbe_get_wol(struct net_device *netdev,
2183 			  struct ethtool_wolinfo *wol)
2184 {
2185 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2186 
2187 	wol->supported = WAKE_UCAST | WAKE_MCAST |
2188 			 WAKE_BCAST | WAKE_MAGIC;
2189 	wol->wolopts = 0;
2190 
2191 	if (ixgbe_wol_exclusion(adapter, wol) ||
2192 	    !device_can_wakeup(&adapter->pdev->dev))
2193 		return;
2194 
2195 	if (adapter->wol & IXGBE_WUFC_EX)
2196 		wol->wolopts |= WAKE_UCAST;
2197 	if (adapter->wol & IXGBE_WUFC_MC)
2198 		wol->wolopts |= WAKE_MCAST;
2199 	if (adapter->wol & IXGBE_WUFC_BC)
2200 		wol->wolopts |= WAKE_BCAST;
2201 	if (adapter->wol & IXGBE_WUFC_MAG)
2202 		wol->wolopts |= WAKE_MAGIC;
2203 }
2204 
2205 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2206 {
2207 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2208 
2209 	if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE |
2210 			    WAKE_FILTER))
2211 		return -EOPNOTSUPP;
2212 
2213 	if (ixgbe_wol_exclusion(adapter, wol))
2214 		return wol->wolopts ? -EOPNOTSUPP : 0;
2215 
2216 	adapter->wol = 0;
2217 
2218 	if (wol->wolopts & WAKE_UCAST)
2219 		adapter->wol |= IXGBE_WUFC_EX;
2220 	if (wol->wolopts & WAKE_MCAST)
2221 		adapter->wol |= IXGBE_WUFC_MC;
2222 	if (wol->wolopts & WAKE_BCAST)
2223 		adapter->wol |= IXGBE_WUFC_BC;
2224 	if (wol->wolopts & WAKE_MAGIC)
2225 		adapter->wol |= IXGBE_WUFC_MAG;
2226 
2227 	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2228 
2229 	return 0;
2230 }
2231 
2232 static int ixgbe_nway_reset(struct net_device *netdev)
2233 {
2234 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2235 
2236 	if (netif_running(netdev))
2237 		ixgbe_reinit_locked(adapter);
2238 
2239 	return 0;
2240 }
2241 
2242 static int ixgbe_set_phys_id(struct net_device *netdev,
2243 			     enum ethtool_phys_id_state state)
2244 {
2245 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2246 	struct ixgbe_hw *hw = &adapter->hw;
2247 
2248 	if (!hw->mac.ops.led_on || !hw->mac.ops.led_off)
2249 		return -EOPNOTSUPP;
2250 
2251 	switch (state) {
2252 	case ETHTOOL_ID_ACTIVE:
2253 		adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2254 		return 2;
2255 
2256 	case ETHTOOL_ID_ON:
2257 		hw->mac.ops.led_on(hw, hw->mac.led_link_act);
2258 		break;
2259 
2260 	case ETHTOOL_ID_OFF:
2261 		hw->mac.ops.led_off(hw, hw->mac.led_link_act);
2262 		break;
2263 
2264 	case ETHTOOL_ID_INACTIVE:
2265 		/* Restore LED settings */
2266 		IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2267 		break;
2268 	}
2269 
2270 	return 0;
2271 }
2272 
2273 static int ixgbe_get_coalesce(struct net_device *netdev,
2274 			      struct ethtool_coalesce *ec)
2275 {
2276 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2277 
2278 	/* only valid if in constant ITR mode */
2279 	if (adapter->rx_itr_setting <= 1)
2280 		ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2281 	else
2282 		ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2283 
2284 	/* if in mixed tx/rx queues per vector mode, report only rx settings */
2285 	if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2286 		return 0;
2287 
2288 	/* only valid if in constant ITR mode */
2289 	if (adapter->tx_itr_setting <= 1)
2290 		ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2291 	else
2292 		ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2293 
2294 	return 0;
2295 }
2296 
2297 /*
2298  * this function must be called before setting the new value of
2299  * rx_itr_setting
2300  */
2301 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2302 {
2303 	struct net_device *netdev = adapter->netdev;
2304 
2305 	/* nothing to do if LRO or RSC are not enabled */
2306 	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2307 	    !(netdev->features & NETIF_F_LRO))
2308 		return false;
2309 
2310 	/* check the feature flag value and enable RSC if necessary */
2311 	if (adapter->rx_itr_setting == 1 ||
2312 	    adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2313 		if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2314 			adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2315 			e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2316 			return true;
2317 		}
2318 	/* if interrupt rate is too high then disable RSC */
2319 	} else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2320 		adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2321 		e_info(probe, "rx-usecs set too low, disabling RSC\n");
2322 		return true;
2323 	}
2324 	return false;
2325 }
2326 
2327 static int ixgbe_set_coalesce(struct net_device *netdev,
2328 			      struct ethtool_coalesce *ec)
2329 {
2330 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2331 	struct ixgbe_q_vector *q_vector;
2332 	int i;
2333 	u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2334 	bool need_reset = false;
2335 
2336 	if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2337 		/* reject Tx specific changes in case of mixed RxTx vectors */
2338 		if (ec->tx_coalesce_usecs)
2339 			return -EINVAL;
2340 		tx_itr_prev = adapter->rx_itr_setting;
2341 	} else {
2342 		tx_itr_prev = adapter->tx_itr_setting;
2343 	}
2344 
2345 	if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2346 	    (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2347 		return -EINVAL;
2348 
2349 	if (ec->rx_coalesce_usecs > 1)
2350 		adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2351 	else
2352 		adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2353 
2354 	if (adapter->rx_itr_setting == 1)
2355 		rx_itr_param = IXGBE_20K_ITR;
2356 	else
2357 		rx_itr_param = adapter->rx_itr_setting;
2358 
2359 	if (ec->tx_coalesce_usecs > 1)
2360 		adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2361 	else
2362 		adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2363 
2364 	if (adapter->tx_itr_setting == 1)
2365 		tx_itr_param = IXGBE_12K_ITR;
2366 	else
2367 		tx_itr_param = adapter->tx_itr_setting;
2368 
2369 	/* mixed Rx/Tx */
2370 	if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2371 		adapter->tx_itr_setting = adapter->rx_itr_setting;
2372 
2373 	/* detect ITR changes that require update of TXDCTL.WTHRESH */
2374 	if ((adapter->tx_itr_setting != 1) &&
2375 	    (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2376 		if ((tx_itr_prev == 1) ||
2377 		    (tx_itr_prev >= IXGBE_100K_ITR))
2378 			need_reset = true;
2379 	} else {
2380 		if ((tx_itr_prev != 1) &&
2381 		    (tx_itr_prev < IXGBE_100K_ITR))
2382 			need_reset = true;
2383 	}
2384 
2385 	/* check the old value and enable RSC if necessary */
2386 	need_reset |= ixgbe_update_rsc(adapter);
2387 
2388 	for (i = 0; i < adapter->num_q_vectors; i++) {
2389 		q_vector = adapter->q_vector[i];
2390 		if (q_vector->tx.count && !q_vector->rx.count)
2391 			/* tx only */
2392 			q_vector->itr = tx_itr_param;
2393 		else
2394 			/* rx only or mixed */
2395 			q_vector->itr = rx_itr_param;
2396 		ixgbe_write_eitr(q_vector);
2397 	}
2398 
2399 	/*
2400 	 * do reset here at the end to make sure EITR==0 case is handled
2401 	 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2402 	 * also locks in RSC enable/disable which requires reset
2403 	 */
2404 	if (need_reset)
2405 		ixgbe_do_reset(netdev);
2406 
2407 	return 0;
2408 }
2409 
2410 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2411 					struct ethtool_rxnfc *cmd)
2412 {
2413 	union ixgbe_atr_input *mask = &adapter->fdir_mask;
2414 	struct ethtool_rx_flow_spec *fsp =
2415 		(struct ethtool_rx_flow_spec *)&cmd->fs;
2416 	struct hlist_node *node2;
2417 	struct ixgbe_fdir_filter *rule = NULL;
2418 
2419 	/* report total rule count */
2420 	cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2421 
2422 	hlist_for_each_entry_safe(rule, node2,
2423 				  &adapter->fdir_filter_list, fdir_node) {
2424 		if (fsp->location <= rule->sw_idx)
2425 			break;
2426 	}
2427 
2428 	if (!rule || fsp->location != rule->sw_idx)
2429 		return -EINVAL;
2430 
2431 	/* fill out the flow spec entry */
2432 
2433 	/* set flow type field */
2434 	switch (rule->filter.formatted.flow_type) {
2435 	case IXGBE_ATR_FLOW_TYPE_TCPV4:
2436 		fsp->flow_type = TCP_V4_FLOW;
2437 		break;
2438 	case IXGBE_ATR_FLOW_TYPE_UDPV4:
2439 		fsp->flow_type = UDP_V4_FLOW;
2440 		break;
2441 	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2442 		fsp->flow_type = SCTP_V4_FLOW;
2443 		break;
2444 	case IXGBE_ATR_FLOW_TYPE_IPV4:
2445 		fsp->flow_type = IP_USER_FLOW;
2446 		fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2447 		fsp->h_u.usr_ip4_spec.proto = 0;
2448 		fsp->m_u.usr_ip4_spec.proto = 0;
2449 		break;
2450 	default:
2451 		return -EINVAL;
2452 	}
2453 
2454 	fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2455 	fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2456 	fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2457 	fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2458 	fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2459 	fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2460 	fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2461 	fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2462 	fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2463 	fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2464 	fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2465 	fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2466 	fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2467 	fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2468 	fsp->flow_type |= FLOW_EXT;
2469 
2470 	/* record action */
2471 	if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2472 		fsp->ring_cookie = RX_CLS_FLOW_DISC;
2473 	else
2474 		fsp->ring_cookie = rule->action;
2475 
2476 	return 0;
2477 }
2478 
2479 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2480 				      struct ethtool_rxnfc *cmd,
2481 				      u32 *rule_locs)
2482 {
2483 	struct hlist_node *node2;
2484 	struct ixgbe_fdir_filter *rule;
2485 	int cnt = 0;
2486 
2487 	/* report total rule count */
2488 	cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2489 
2490 	hlist_for_each_entry_safe(rule, node2,
2491 				  &adapter->fdir_filter_list, fdir_node) {
2492 		if (cnt == cmd->rule_cnt)
2493 			return -EMSGSIZE;
2494 		rule_locs[cnt] = rule->sw_idx;
2495 		cnt++;
2496 	}
2497 
2498 	cmd->rule_cnt = cnt;
2499 
2500 	return 0;
2501 }
2502 
2503 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2504 				   struct ethtool_rxnfc *cmd)
2505 {
2506 	cmd->data = 0;
2507 
2508 	/* Report default options for RSS on ixgbe */
2509 	switch (cmd->flow_type) {
2510 	case TCP_V4_FLOW:
2511 		cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2512 		/* fallthrough */
2513 	case UDP_V4_FLOW:
2514 		if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2515 			cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2516 		/* fallthrough */
2517 	case SCTP_V4_FLOW:
2518 	case AH_ESP_V4_FLOW:
2519 	case AH_V4_FLOW:
2520 	case ESP_V4_FLOW:
2521 	case IPV4_FLOW:
2522 		cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2523 		break;
2524 	case TCP_V6_FLOW:
2525 		cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2526 		/* fallthrough */
2527 	case UDP_V6_FLOW:
2528 		if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2529 			cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2530 		/* fallthrough */
2531 	case SCTP_V6_FLOW:
2532 	case AH_ESP_V6_FLOW:
2533 	case AH_V6_FLOW:
2534 	case ESP_V6_FLOW:
2535 	case IPV6_FLOW:
2536 		cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2537 		break;
2538 	default:
2539 		return -EINVAL;
2540 	}
2541 
2542 	return 0;
2543 }
2544 
2545 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2546 			   u32 *rule_locs)
2547 {
2548 	struct ixgbe_adapter *adapter = netdev_priv(dev);
2549 	int ret = -EOPNOTSUPP;
2550 
2551 	switch (cmd->cmd) {
2552 	case ETHTOOL_GRXRINGS:
2553 		cmd->data = adapter->num_rx_queues;
2554 		ret = 0;
2555 		break;
2556 	case ETHTOOL_GRXCLSRLCNT:
2557 		cmd->rule_cnt = adapter->fdir_filter_count;
2558 		ret = 0;
2559 		break;
2560 	case ETHTOOL_GRXCLSRULE:
2561 		ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2562 		break;
2563 	case ETHTOOL_GRXCLSRLALL:
2564 		ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2565 		break;
2566 	case ETHTOOL_GRXFH:
2567 		ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2568 		break;
2569 	default:
2570 		break;
2571 	}
2572 
2573 	return ret;
2574 }
2575 
2576 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2577 				    struct ixgbe_fdir_filter *input,
2578 				    u16 sw_idx)
2579 {
2580 	struct ixgbe_hw *hw = &adapter->hw;
2581 	struct hlist_node *node2;
2582 	struct ixgbe_fdir_filter *rule, *parent;
2583 	int err = -EINVAL;
2584 
2585 	parent = NULL;
2586 	rule = NULL;
2587 
2588 	hlist_for_each_entry_safe(rule, node2,
2589 				  &adapter->fdir_filter_list, fdir_node) {
2590 		/* hash found, or no matching entry */
2591 		if (rule->sw_idx >= sw_idx)
2592 			break;
2593 		parent = rule;
2594 	}
2595 
2596 	/* if there is an old rule occupying our place remove it */
2597 	if (rule && (rule->sw_idx == sw_idx)) {
2598 		if (!input || (rule->filter.formatted.bkt_hash !=
2599 			       input->filter.formatted.bkt_hash)) {
2600 			err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2601 								&rule->filter,
2602 								sw_idx);
2603 		}
2604 
2605 		hlist_del(&rule->fdir_node);
2606 		kfree(rule);
2607 		adapter->fdir_filter_count--;
2608 	}
2609 
2610 	/*
2611 	 * If no input this was a delete, err should be 0 if a rule was
2612 	 * successfully found and removed from the list else -EINVAL
2613 	 */
2614 	if (!input)
2615 		return err;
2616 
2617 	/* initialize node and set software index */
2618 	INIT_HLIST_NODE(&input->fdir_node);
2619 
2620 	/* add filter to the list */
2621 	if (parent)
2622 		hlist_add_behind(&input->fdir_node, &parent->fdir_node);
2623 	else
2624 		hlist_add_head(&input->fdir_node,
2625 			       &adapter->fdir_filter_list);
2626 
2627 	/* update counts */
2628 	adapter->fdir_filter_count++;
2629 
2630 	return 0;
2631 }
2632 
2633 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2634 				       u8 *flow_type)
2635 {
2636 	switch (fsp->flow_type & ~FLOW_EXT) {
2637 	case TCP_V4_FLOW:
2638 		*flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2639 		break;
2640 	case UDP_V4_FLOW:
2641 		*flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2642 		break;
2643 	case SCTP_V4_FLOW:
2644 		*flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2645 		break;
2646 	case IP_USER_FLOW:
2647 		switch (fsp->h_u.usr_ip4_spec.proto) {
2648 		case IPPROTO_TCP:
2649 			*flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2650 			break;
2651 		case IPPROTO_UDP:
2652 			*flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2653 			break;
2654 		case IPPROTO_SCTP:
2655 			*flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2656 			break;
2657 		case 0:
2658 			if (!fsp->m_u.usr_ip4_spec.proto) {
2659 				*flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2660 				break;
2661 			}
2662 			/* fall through */
2663 		default:
2664 			return 0;
2665 		}
2666 		break;
2667 	default:
2668 		return 0;
2669 	}
2670 
2671 	return 1;
2672 }
2673 
2674 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2675 					struct ethtool_rxnfc *cmd)
2676 {
2677 	struct ethtool_rx_flow_spec *fsp =
2678 		(struct ethtool_rx_flow_spec *)&cmd->fs;
2679 	struct ixgbe_hw *hw = &adapter->hw;
2680 	struct ixgbe_fdir_filter *input;
2681 	union ixgbe_atr_input mask;
2682 	u8 queue;
2683 	int err;
2684 
2685 	if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2686 		return -EOPNOTSUPP;
2687 
2688 	/* ring_cookie is a masked into a set of queues and ixgbe pools or
2689 	 * we use the drop index.
2690 	 */
2691 	if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2692 		queue = IXGBE_FDIR_DROP_QUEUE;
2693 	} else {
2694 		u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
2695 		u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
2696 
2697 		if (!vf && (ring >= adapter->num_rx_queues))
2698 			return -EINVAL;
2699 		else if (vf &&
2700 			 ((vf > adapter->num_vfs) ||
2701 			   ring >= adapter->num_rx_queues_per_pool))
2702 			return -EINVAL;
2703 
2704 		/* Map the ring onto the absolute queue index */
2705 		if (!vf)
2706 			queue = adapter->rx_ring[ring]->reg_idx;
2707 		else
2708 			queue = ((vf - 1) *
2709 				adapter->num_rx_queues_per_pool) + ring;
2710 	}
2711 
2712 	/* Don't allow indexes to exist outside of available space */
2713 	if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2714 		e_err(drv, "Location out of range\n");
2715 		return -EINVAL;
2716 	}
2717 
2718 	input = kzalloc(sizeof(*input), GFP_ATOMIC);
2719 	if (!input)
2720 		return -ENOMEM;
2721 
2722 	memset(&mask, 0, sizeof(union ixgbe_atr_input));
2723 
2724 	/* set SW index */
2725 	input->sw_idx = fsp->location;
2726 
2727 	/* record flow type */
2728 	if (!ixgbe_flowspec_to_flow_type(fsp,
2729 					 &input->filter.formatted.flow_type)) {
2730 		e_err(drv, "Unrecognized flow type\n");
2731 		goto err_out;
2732 	}
2733 
2734 	mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2735 				   IXGBE_ATR_L4TYPE_MASK;
2736 
2737 	if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2738 		mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2739 
2740 	/* Copy input into formatted structures */
2741 	input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2742 	mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2743 	input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2744 	mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2745 	input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2746 	mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2747 	input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2748 	mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2749 
2750 	if (fsp->flow_type & FLOW_EXT) {
2751 		input->filter.formatted.vm_pool =
2752 				(unsigned char)ntohl(fsp->h_ext.data[1]);
2753 		mask.formatted.vm_pool =
2754 				(unsigned char)ntohl(fsp->m_ext.data[1]);
2755 		input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2756 		mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2757 		input->filter.formatted.flex_bytes =
2758 						fsp->h_ext.vlan_etype;
2759 		mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2760 	}
2761 
2762 	/* determine if we need to drop or route the packet */
2763 	if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2764 		input->action = IXGBE_FDIR_DROP_QUEUE;
2765 	else
2766 		input->action = fsp->ring_cookie;
2767 
2768 	spin_lock(&adapter->fdir_perfect_lock);
2769 
2770 	if (hlist_empty(&adapter->fdir_filter_list)) {
2771 		/* save mask and program input mask into HW */
2772 		memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2773 		err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2774 		if (err) {
2775 			e_err(drv, "Error writing mask\n");
2776 			goto err_out_w_lock;
2777 		}
2778 	} else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2779 		e_err(drv, "Only one mask supported per port\n");
2780 		goto err_out_w_lock;
2781 	}
2782 
2783 	/* apply mask and compute/store hash */
2784 	ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2785 
2786 	/* program filters to filter memory */
2787 	err = ixgbe_fdir_write_perfect_filter_82599(hw,
2788 				&input->filter, input->sw_idx, queue);
2789 	if (err)
2790 		goto err_out_w_lock;
2791 
2792 	ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2793 
2794 	spin_unlock(&adapter->fdir_perfect_lock);
2795 
2796 	return err;
2797 err_out_w_lock:
2798 	spin_unlock(&adapter->fdir_perfect_lock);
2799 err_out:
2800 	kfree(input);
2801 	return -EINVAL;
2802 }
2803 
2804 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2805 					struct ethtool_rxnfc *cmd)
2806 {
2807 	struct ethtool_rx_flow_spec *fsp =
2808 		(struct ethtool_rx_flow_spec *)&cmd->fs;
2809 	int err;
2810 
2811 	spin_lock(&adapter->fdir_perfect_lock);
2812 	err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2813 	spin_unlock(&adapter->fdir_perfect_lock);
2814 
2815 	return err;
2816 }
2817 
2818 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2819 		       IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2820 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2821 				  struct ethtool_rxnfc *nfc)
2822 {
2823 	u32 flags2 = adapter->flags2;
2824 
2825 	/*
2826 	 * RSS does not support anything other than hashing
2827 	 * to queues on src and dst IPs and ports
2828 	 */
2829 	if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2830 			  RXH_L4_B_0_1 | RXH_L4_B_2_3))
2831 		return -EINVAL;
2832 
2833 	switch (nfc->flow_type) {
2834 	case TCP_V4_FLOW:
2835 	case TCP_V6_FLOW:
2836 		if (!(nfc->data & RXH_IP_SRC) ||
2837 		    !(nfc->data & RXH_IP_DST) ||
2838 		    !(nfc->data & RXH_L4_B_0_1) ||
2839 		    !(nfc->data & RXH_L4_B_2_3))
2840 			return -EINVAL;
2841 		break;
2842 	case UDP_V4_FLOW:
2843 		if (!(nfc->data & RXH_IP_SRC) ||
2844 		    !(nfc->data & RXH_IP_DST))
2845 			return -EINVAL;
2846 		switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2847 		case 0:
2848 			flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2849 			break;
2850 		case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2851 			flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2852 			break;
2853 		default:
2854 			return -EINVAL;
2855 		}
2856 		break;
2857 	case UDP_V6_FLOW:
2858 		if (!(nfc->data & RXH_IP_SRC) ||
2859 		    !(nfc->data & RXH_IP_DST))
2860 			return -EINVAL;
2861 		switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2862 		case 0:
2863 			flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2864 			break;
2865 		case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2866 			flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2867 			break;
2868 		default:
2869 			return -EINVAL;
2870 		}
2871 		break;
2872 	case AH_ESP_V4_FLOW:
2873 	case AH_V4_FLOW:
2874 	case ESP_V4_FLOW:
2875 	case SCTP_V4_FLOW:
2876 	case AH_ESP_V6_FLOW:
2877 	case AH_V6_FLOW:
2878 	case ESP_V6_FLOW:
2879 	case SCTP_V6_FLOW:
2880 		if (!(nfc->data & RXH_IP_SRC) ||
2881 		    !(nfc->data & RXH_IP_DST) ||
2882 		    (nfc->data & RXH_L4_B_0_1) ||
2883 		    (nfc->data & RXH_L4_B_2_3))
2884 			return -EINVAL;
2885 		break;
2886 	default:
2887 		return -EINVAL;
2888 	}
2889 
2890 	/* if we changed something we need to update flags */
2891 	if (flags2 != adapter->flags2) {
2892 		struct ixgbe_hw *hw = &adapter->hw;
2893 		u32 mrqc;
2894 		unsigned int pf_pool = adapter->num_vfs;
2895 
2896 		if ((hw->mac.type >= ixgbe_mac_X550) &&
2897 		    (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2898 			mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
2899 		else
2900 			mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2901 
2902 		if ((flags2 & UDP_RSS_FLAGS) &&
2903 		    !(adapter->flags2 & UDP_RSS_FLAGS))
2904 			e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2905 
2906 		adapter->flags2 = flags2;
2907 
2908 		/* Perform hash on these packet types */
2909 		mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2910 		      | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2911 		      | IXGBE_MRQC_RSS_FIELD_IPV6
2912 		      | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2913 
2914 		mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2915 			  IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2916 
2917 		if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2918 			mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2919 
2920 		if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2921 			mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2922 
2923 		if ((hw->mac.type >= ixgbe_mac_X550) &&
2924 		    (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2925 			IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
2926 		else
2927 			IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2928 	}
2929 
2930 	return 0;
2931 }
2932 
2933 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2934 {
2935 	struct ixgbe_adapter *adapter = netdev_priv(dev);
2936 	int ret = -EOPNOTSUPP;
2937 
2938 	switch (cmd->cmd) {
2939 	case ETHTOOL_SRXCLSRLINS:
2940 		ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2941 		break;
2942 	case ETHTOOL_SRXCLSRLDEL:
2943 		ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2944 		break;
2945 	case ETHTOOL_SRXFH:
2946 		ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2947 		break;
2948 	default:
2949 		break;
2950 	}
2951 
2952 	return ret;
2953 }
2954 
2955 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
2956 {
2957 	if (adapter->hw.mac.type < ixgbe_mac_X550)
2958 		return 16;
2959 	else
2960 		return 64;
2961 }
2962 
2963 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
2964 {
2965 	return IXGBE_RSS_KEY_SIZE;
2966 }
2967 
2968 static u32 ixgbe_rss_indir_size(struct net_device *netdev)
2969 {
2970 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2971 
2972 	return ixgbe_rss_indir_tbl_entries(adapter);
2973 }
2974 
2975 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
2976 {
2977 	int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
2978 	u16 rss_m = adapter->ring_feature[RING_F_RSS].mask;
2979 
2980 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2981 		rss_m = adapter->ring_feature[RING_F_RSS].indices - 1;
2982 
2983 	for (i = 0; i < reta_size; i++)
2984 		indir[i] = adapter->rss_indir_tbl[i] & rss_m;
2985 }
2986 
2987 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
2988 			  u8 *hfunc)
2989 {
2990 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
2991 
2992 	if (hfunc)
2993 		*hfunc = ETH_RSS_HASH_TOP;
2994 
2995 	if (indir)
2996 		ixgbe_get_reta(adapter, indir);
2997 
2998 	if (key)
2999 		memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
3000 
3001 	return 0;
3002 }
3003 
3004 static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
3005 			  const u8 *key, const u8 hfunc)
3006 {
3007 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3008 	int i;
3009 	u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3010 
3011 	if (hfunc)
3012 		return -EINVAL;
3013 
3014 	/* Fill out the redirection table */
3015 	if (indir) {
3016 		int max_queues = min_t(int, adapter->num_rx_queues,
3017 				       ixgbe_rss_indir_tbl_max(adapter));
3018 
3019 		/*Allow at least 2 queues w/ SR-IOV.*/
3020 		if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3021 		    (max_queues < 2))
3022 			max_queues = 2;
3023 
3024 		/* Verify user input. */
3025 		for (i = 0; i < reta_entries; i++)
3026 			if (indir[i] >= max_queues)
3027 				return -EINVAL;
3028 
3029 		for (i = 0; i < reta_entries; i++)
3030 			adapter->rss_indir_tbl[i] = indir[i];
3031 
3032 		ixgbe_store_reta(adapter);
3033 	}
3034 
3035 	/* Fill out the rss hash key */
3036 	if (key) {
3037 		memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev));
3038 		ixgbe_store_key(adapter);
3039 	}
3040 
3041 	return 0;
3042 }
3043 
3044 static int ixgbe_get_ts_info(struct net_device *dev,
3045 			     struct ethtool_ts_info *info)
3046 {
3047 	struct ixgbe_adapter *adapter = netdev_priv(dev);
3048 
3049 	/* we always support timestamping disabled */
3050 	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
3051 
3052 	switch (adapter->hw.mac.type) {
3053 	case ixgbe_mac_X550:
3054 	case ixgbe_mac_X550EM_x:
3055 	case ixgbe_mac_x550em_a:
3056 		info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
3057 		break;
3058 	case ixgbe_mac_X540:
3059 	case ixgbe_mac_82599EB:
3060 		info->rx_filters |=
3061 			BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3062 			BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3063 			BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
3064 		break;
3065 	default:
3066 		return ethtool_op_get_ts_info(dev, info);
3067 	}
3068 
3069 	info->so_timestamping =
3070 		SOF_TIMESTAMPING_TX_SOFTWARE |
3071 		SOF_TIMESTAMPING_RX_SOFTWARE |
3072 		SOF_TIMESTAMPING_SOFTWARE |
3073 		SOF_TIMESTAMPING_TX_HARDWARE |
3074 		SOF_TIMESTAMPING_RX_HARDWARE |
3075 		SOF_TIMESTAMPING_RAW_HARDWARE;
3076 
3077 	if (adapter->ptp_clock)
3078 		info->phc_index = ptp_clock_index(adapter->ptp_clock);
3079 	else
3080 		info->phc_index = -1;
3081 
3082 	info->tx_types =
3083 		BIT(HWTSTAMP_TX_OFF) |
3084 		BIT(HWTSTAMP_TX_ON);
3085 
3086 	return 0;
3087 }
3088 
3089 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
3090 {
3091 	unsigned int max_combined;
3092 	u8 tcs = adapter->hw_tcs;
3093 
3094 	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3095 		/* We only support one q_vector without MSI-X */
3096 		max_combined = 1;
3097 	} else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3098 		/* Limit value based on the queue mask */
3099 		max_combined = adapter->ring_feature[RING_F_RSS].mask + 1;
3100 	} else if (tcs > 1) {
3101 		/* For DCB report channels per traffic class */
3102 		if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3103 			/* 8 TC w/ 4 queues per TC */
3104 			max_combined = 4;
3105 		} else if (tcs > 4) {
3106 			/* 8 TC w/ 8 queues per TC */
3107 			max_combined = 8;
3108 		} else {
3109 			/* 4 TC w/ 16 queues per TC */
3110 			max_combined = 16;
3111 		}
3112 	} else if (adapter->atr_sample_rate) {
3113 		/* support up to 64 queues with ATR */
3114 		max_combined = IXGBE_MAX_FDIR_INDICES;
3115 	} else {
3116 		/* support up to 16 queues with RSS */
3117 		max_combined = ixgbe_max_rss_indices(adapter);
3118 	}
3119 
3120 	return max_combined;
3121 }
3122 
3123 static void ixgbe_get_channels(struct net_device *dev,
3124 			       struct ethtool_channels *ch)
3125 {
3126 	struct ixgbe_adapter *adapter = netdev_priv(dev);
3127 
3128 	/* report maximum channels */
3129 	ch->max_combined = ixgbe_max_channels(adapter);
3130 
3131 	/* report info for other vector */
3132 	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3133 		ch->max_other = NON_Q_VECTORS;
3134 		ch->other_count = NON_Q_VECTORS;
3135 	}
3136 
3137 	/* record RSS queues */
3138 	ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3139 
3140 	/* nothing else to report if RSS is disabled */
3141 	if (ch->combined_count == 1)
3142 		return;
3143 
3144 	/* we do not support ATR queueing if SR-IOV is enabled */
3145 	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3146 		return;
3147 
3148 	/* same thing goes for being DCB enabled */
3149 	if (adapter->hw_tcs > 1)
3150 		return;
3151 
3152 	/* if ATR is disabled we can exit */
3153 	if (!adapter->atr_sample_rate)
3154 		return;
3155 
3156 	/* report flow director queues as maximum channels */
3157 	ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3158 }
3159 
3160 static int ixgbe_set_channels(struct net_device *dev,
3161 			      struct ethtool_channels *ch)
3162 {
3163 	struct ixgbe_adapter *adapter = netdev_priv(dev);
3164 	unsigned int count = ch->combined_count;
3165 	u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
3166 
3167 	/* verify they are not requesting separate vectors */
3168 	if (!count || ch->rx_count || ch->tx_count)
3169 		return -EINVAL;
3170 
3171 	/* verify other_count has not changed */
3172 	if (ch->other_count != NON_Q_VECTORS)
3173 		return -EINVAL;
3174 
3175 	/* verify the number of channels does not exceed hardware limits */
3176 	if (count > ixgbe_max_channels(adapter))
3177 		return -EINVAL;
3178 
3179 	/* update feature limits from largest to smallest supported values */
3180 	adapter->ring_feature[RING_F_FDIR].limit = count;
3181 
3182 	/* cap RSS limit */
3183 	if (count > max_rss_indices)
3184 		count = max_rss_indices;
3185 	adapter->ring_feature[RING_F_RSS].limit = count;
3186 
3187 #ifdef IXGBE_FCOE
3188 	/* cap FCoE limit at 8 */
3189 	if (count > IXGBE_FCRETA_SIZE)
3190 		count = IXGBE_FCRETA_SIZE;
3191 	adapter->ring_feature[RING_F_FCOE].limit = count;
3192 
3193 #endif
3194 	/* use setup TC to update any traffic class queue mapping */
3195 	return ixgbe_setup_tc(dev, adapter->hw_tcs);
3196 }
3197 
3198 static int ixgbe_get_module_info(struct net_device *dev,
3199 				       struct ethtool_modinfo *modinfo)
3200 {
3201 	struct ixgbe_adapter *adapter = netdev_priv(dev);
3202 	struct ixgbe_hw *hw = &adapter->hw;
3203 	s32 status;
3204 	u8 sff8472_rev, addr_mode;
3205 	bool page_swap = false;
3206 
3207 	if (hw->phy.type == ixgbe_phy_fw)
3208 		return -ENXIO;
3209 
3210 	/* Check whether we support SFF-8472 or not */
3211 	status = hw->phy.ops.read_i2c_eeprom(hw,
3212 					     IXGBE_SFF_SFF_8472_COMP,
3213 					     &sff8472_rev);
3214 	if (status)
3215 		return -EIO;
3216 
3217 	/* addressing mode is not supported */
3218 	status = hw->phy.ops.read_i2c_eeprom(hw,
3219 					     IXGBE_SFF_SFF_8472_SWAP,
3220 					     &addr_mode);
3221 	if (status)
3222 		return -EIO;
3223 
3224 	if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3225 		e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3226 		page_swap = true;
3227 	}
3228 
3229 	if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3230 		/* We have a SFP, but it does not support SFF-8472 */
3231 		modinfo->type = ETH_MODULE_SFF_8079;
3232 		modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3233 	} else {
3234 		/* We have a SFP which supports a revision of SFF-8472. */
3235 		modinfo->type = ETH_MODULE_SFF_8472;
3236 		modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3237 	}
3238 
3239 	return 0;
3240 }
3241 
3242 static int ixgbe_get_module_eeprom(struct net_device *dev,
3243 					 struct ethtool_eeprom *ee,
3244 					 u8 *data)
3245 {
3246 	struct ixgbe_adapter *adapter = netdev_priv(dev);
3247 	struct ixgbe_hw *hw = &adapter->hw;
3248 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3249 	u8 databyte = 0xFF;
3250 	int i = 0;
3251 
3252 	if (ee->len == 0)
3253 		return -EINVAL;
3254 
3255 	if (hw->phy.type == ixgbe_phy_fw)
3256 		return -ENXIO;
3257 
3258 	for (i = ee->offset; i < ee->offset + ee->len; i++) {
3259 		/* I2C reads can take long time */
3260 		if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3261 			return -EBUSY;
3262 
3263 		if (i < ETH_MODULE_SFF_8079_LEN)
3264 			status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3265 		else
3266 			status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3267 
3268 		if (status)
3269 			return -EIO;
3270 
3271 		data[i - ee->offset] = databyte;
3272 	}
3273 
3274 	return 0;
3275 }
3276 
3277 static const struct {
3278 	ixgbe_link_speed mac_speed;
3279 	u32 supported;
3280 } ixgbe_ls_map[] = {
3281 	{ IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full },
3282 	{ IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full },
3283 	{ IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full },
3284 	{ IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full },
3285 	{ IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full },
3286 };
3287 
3288 static const struct {
3289 	u32 lp_advertised;
3290 	u32 mac_speed;
3291 } ixgbe_lp_map[] = {
3292 	{ FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full },
3293 	{ FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full },
3294 	{ FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full },
3295 	{ FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full },
3296 	{ FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full },
3297 	{ FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full},
3298 };
3299 
3300 static int
3301 ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata)
3302 {
3303 	u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
3304 	struct ixgbe_hw *hw = &adapter->hw;
3305 	s32 rc;
3306 	u16 i;
3307 
3308 	rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info);
3309 	if (rc)
3310 		return rc;
3311 
3312 	edata->lp_advertised = 0;
3313 	for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) {
3314 		if (info[0] & ixgbe_lp_map[i].lp_advertised)
3315 			edata->lp_advertised |= ixgbe_lp_map[i].mac_speed;
3316 	}
3317 
3318 	edata->supported = 0;
3319 	for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3320 		if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed)
3321 			edata->supported |= ixgbe_ls_map[i].supported;
3322 	}
3323 
3324 	edata->advertised = 0;
3325 	for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3326 		if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed)
3327 			edata->advertised |= ixgbe_ls_map[i].supported;
3328 	}
3329 
3330 	edata->eee_enabled = !!edata->advertised;
3331 	edata->tx_lpi_enabled = edata->eee_enabled;
3332 	if (edata->advertised & edata->lp_advertised)
3333 		edata->eee_active = true;
3334 
3335 	return 0;
3336 }
3337 
3338 static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3339 {
3340 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3341 	struct ixgbe_hw *hw = &adapter->hw;
3342 
3343 	if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3344 		return -EOPNOTSUPP;
3345 
3346 	if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw)
3347 		return ixgbe_get_eee_fw(adapter, edata);
3348 
3349 	return -EOPNOTSUPP;
3350 }
3351 
3352 static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
3353 {
3354 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3355 	struct ixgbe_hw *hw = &adapter->hw;
3356 	struct ethtool_eee eee_data;
3357 	s32 ret_val;
3358 
3359 	if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3360 		return -EOPNOTSUPP;
3361 
3362 	memset(&eee_data, 0, sizeof(struct ethtool_eee));
3363 
3364 	ret_val = ixgbe_get_eee(netdev, &eee_data);
3365 	if (ret_val)
3366 		return ret_val;
3367 
3368 	if (eee_data.eee_enabled && !edata->eee_enabled) {
3369 		if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) {
3370 			e_err(drv, "Setting EEE tx-lpi is not supported\n");
3371 			return -EINVAL;
3372 		}
3373 
3374 		if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) {
3375 			e_err(drv,
3376 			      "Setting EEE Tx LPI timer is not supported\n");
3377 			return -EINVAL;
3378 		}
3379 
3380 		if (eee_data.advertised != edata->advertised) {
3381 			e_err(drv,
3382 			      "Setting EEE advertised speeds is not supported\n");
3383 			return -EINVAL;
3384 		}
3385 	}
3386 
3387 	if (eee_data.eee_enabled != edata->eee_enabled) {
3388 		if (edata->eee_enabled) {
3389 			adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
3390 			hw->phy.eee_speeds_advertised =
3391 						   hw->phy.eee_speeds_supported;
3392 		} else {
3393 			adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
3394 			hw->phy.eee_speeds_advertised = 0;
3395 		}
3396 
3397 		/* reset link */
3398 		if (netif_running(netdev))
3399 			ixgbe_reinit_locked(adapter);
3400 		else
3401 			ixgbe_reset(adapter);
3402 	}
3403 
3404 	return 0;
3405 }
3406 
3407 static u32 ixgbe_get_priv_flags(struct net_device *netdev)
3408 {
3409 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3410 	u32 priv_flags = 0;
3411 
3412 	if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
3413 		priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX;
3414 
3415 	if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED)
3416 		priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN;
3417 
3418 	return priv_flags;
3419 }
3420 
3421 static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3422 {
3423 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
3424 	unsigned int flags2 = adapter->flags2;
3425 
3426 	flags2 &= ~IXGBE_FLAG2_RX_LEGACY;
3427 	if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX)
3428 		flags2 |= IXGBE_FLAG2_RX_LEGACY;
3429 
3430 	flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED;
3431 	if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN)
3432 		flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED;
3433 
3434 	if (flags2 != adapter->flags2) {
3435 		adapter->flags2 = flags2;
3436 
3437 		/* reset interface to repopulate queues */
3438 		if (netif_running(netdev))
3439 			ixgbe_reinit_locked(adapter);
3440 	}
3441 
3442 	return 0;
3443 }
3444 
3445 static const struct ethtool_ops ixgbe_ethtool_ops = {
3446 	.get_drvinfo            = ixgbe_get_drvinfo,
3447 	.get_regs_len           = ixgbe_get_regs_len,
3448 	.get_regs               = ixgbe_get_regs,
3449 	.get_wol                = ixgbe_get_wol,
3450 	.set_wol                = ixgbe_set_wol,
3451 	.nway_reset             = ixgbe_nway_reset,
3452 	.get_link               = ethtool_op_get_link,
3453 	.get_eeprom_len         = ixgbe_get_eeprom_len,
3454 	.get_eeprom             = ixgbe_get_eeprom,
3455 	.set_eeprom             = ixgbe_set_eeprom,
3456 	.get_ringparam          = ixgbe_get_ringparam,
3457 	.set_ringparam          = ixgbe_set_ringparam,
3458 	.get_pauseparam         = ixgbe_get_pauseparam,
3459 	.set_pauseparam         = ixgbe_set_pauseparam,
3460 	.get_msglevel           = ixgbe_get_msglevel,
3461 	.set_msglevel           = ixgbe_set_msglevel,
3462 	.self_test              = ixgbe_diag_test,
3463 	.get_strings            = ixgbe_get_strings,
3464 	.set_phys_id            = ixgbe_set_phys_id,
3465 	.get_sset_count         = ixgbe_get_sset_count,
3466 	.get_ethtool_stats      = ixgbe_get_ethtool_stats,
3467 	.get_coalesce           = ixgbe_get_coalesce,
3468 	.set_coalesce           = ixgbe_set_coalesce,
3469 	.get_rxnfc		= ixgbe_get_rxnfc,
3470 	.set_rxnfc		= ixgbe_set_rxnfc,
3471 	.get_rxfh_indir_size	= ixgbe_rss_indir_size,
3472 	.get_rxfh_key_size	= ixgbe_get_rxfh_key_size,
3473 	.get_rxfh		= ixgbe_get_rxfh,
3474 	.set_rxfh		= ixgbe_set_rxfh,
3475 	.get_eee		= ixgbe_get_eee,
3476 	.set_eee		= ixgbe_set_eee,
3477 	.get_channels		= ixgbe_get_channels,
3478 	.set_channels		= ixgbe_set_channels,
3479 	.get_priv_flags		= ixgbe_get_priv_flags,
3480 	.set_priv_flags		= ixgbe_set_priv_flags,
3481 	.get_ts_info		= ixgbe_get_ts_info,
3482 	.get_module_info	= ixgbe_get_module_info,
3483 	.get_module_eeprom	= ixgbe_get_module_eeprom,
3484 	.get_link_ksettings     = ixgbe_get_link_ksettings,
3485 	.set_link_ksettings     = ixgbe_set_link_ksettings,
3486 };
3487 
3488 void ixgbe_set_ethtool_ops(struct net_device *netdev)
3489 {
3490 	netdev->ethtool_ops = &ixgbe_ethtool_ops;
3491 }
3492