1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* ethtool support for ixgbe */ 30 31 #include <linux/interrupt.h> 32 #include <linux/types.h> 33 #include <linux/module.h> 34 #include <linux/slab.h> 35 #include <linux/pci.h> 36 #include <linux/netdevice.h> 37 #include <linux/ethtool.h> 38 #include <linux/vmalloc.h> 39 #include <linux/highmem.h> 40 #include <linux/uaccess.h> 41 42 #include "ixgbe.h" 43 #include "ixgbe_phy.h" 44 45 46 #define IXGBE_ALL_RAR_ENTRIES 16 47 48 enum {NETDEV_STATS, IXGBE_STATS}; 49 50 struct ixgbe_stats { 51 char stat_string[ETH_GSTRING_LEN]; 52 int type; 53 int sizeof_stat; 54 int stat_offset; 55 }; 56 57 #define IXGBE_STAT(m) IXGBE_STATS, \ 58 sizeof(((struct ixgbe_adapter *)0)->m), \ 59 offsetof(struct ixgbe_adapter, m) 60 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 61 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 62 offsetof(struct rtnl_link_stats64, m) 63 64 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 73 {"lsc_int", IXGBE_STAT(lsc_int)}, 74 {"tx_busy", IXGBE_STAT(tx_busy)}, 75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 80 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 81 {"broadcast", IXGBE_STAT(stats.bprc)}, 82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 83 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 99 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 114 #ifdef IXGBE_FCOE 115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 123 #endif /* IXGBE_FCOE */ 124 }; 125 126 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 127 * we set the num_rx_queues to evaluate to num_tx_queues. This is 128 * used because we do not have a good way to get the max number of 129 * rx queues with CONFIG_RPS disabled. 130 */ 131 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 132 133 #define IXGBE_QUEUE_STATS_LEN ( \ 134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 136 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 137 #define IXGBE_PB_STATS_LEN ( \ 138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 142 / sizeof(u64)) 143 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 144 IXGBE_PB_STATS_LEN + \ 145 IXGBE_QUEUE_STATS_LEN) 146 147 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 148 "Register test (offline)", "Eeprom test (offline)", 149 "Interrupt test (offline)", "Loopback test (offline)", 150 "Link test (on/offline)" 151 }; 152 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 153 154 static int ixgbe_get_settings(struct net_device *netdev, 155 struct ethtool_cmd *ecmd) 156 { 157 struct ixgbe_adapter *adapter = netdev_priv(netdev); 158 struct ixgbe_hw *hw = &adapter->hw; 159 ixgbe_link_speed supported_link; 160 u32 link_speed = 0; 161 bool autoneg = false; 162 bool link_up; 163 164 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 165 166 /* set the supported link speeds */ 167 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 168 ecmd->supported |= SUPPORTED_10000baseT_Full; 169 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 170 ecmd->supported |= SUPPORTED_1000baseT_Full; 171 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 172 ecmd->supported |= SUPPORTED_100baseT_Full; 173 174 /* set the advertised speeds */ 175 if (hw->phy.autoneg_advertised) { 176 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 177 ecmd->advertising |= ADVERTISED_100baseT_Full; 178 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 179 ecmd->advertising |= ADVERTISED_10000baseT_Full; 180 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 181 ecmd->advertising |= ADVERTISED_1000baseT_Full; 182 } else { 183 /* default modes in case phy.autoneg_advertised isn't set */ 184 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 185 ecmd->advertising |= ADVERTISED_10000baseT_Full; 186 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 187 ecmd->advertising |= ADVERTISED_1000baseT_Full; 188 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 189 ecmd->advertising |= ADVERTISED_100baseT_Full; 190 191 if (hw->phy.multispeed_fiber && !autoneg) { 192 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 193 ecmd->advertising = ADVERTISED_10000baseT_Full; 194 } 195 } 196 197 if (autoneg) { 198 ecmd->supported |= SUPPORTED_Autoneg; 199 ecmd->advertising |= ADVERTISED_Autoneg; 200 ecmd->autoneg = AUTONEG_ENABLE; 201 } else 202 ecmd->autoneg = AUTONEG_DISABLE; 203 204 ecmd->transceiver = XCVR_EXTERNAL; 205 206 /* Determine the remaining settings based on the PHY type. */ 207 switch (adapter->hw.phy.type) { 208 case ixgbe_phy_tn: 209 case ixgbe_phy_aq: 210 case ixgbe_phy_cu_unknown: 211 ecmd->supported |= SUPPORTED_TP; 212 ecmd->advertising |= ADVERTISED_TP; 213 ecmd->port = PORT_TP; 214 break; 215 case ixgbe_phy_qt: 216 ecmd->supported |= SUPPORTED_FIBRE; 217 ecmd->advertising |= ADVERTISED_FIBRE; 218 ecmd->port = PORT_FIBRE; 219 break; 220 case ixgbe_phy_nl: 221 case ixgbe_phy_sfp_passive_tyco: 222 case ixgbe_phy_sfp_passive_unknown: 223 case ixgbe_phy_sfp_ftl: 224 case ixgbe_phy_sfp_avago: 225 case ixgbe_phy_sfp_intel: 226 case ixgbe_phy_sfp_unknown: 227 /* SFP+ devices, further checking needed */ 228 switch (adapter->hw.phy.sfp_type) { 229 case ixgbe_sfp_type_da_cu: 230 case ixgbe_sfp_type_da_cu_core0: 231 case ixgbe_sfp_type_da_cu_core1: 232 ecmd->supported |= SUPPORTED_FIBRE; 233 ecmd->advertising |= ADVERTISED_FIBRE; 234 ecmd->port = PORT_DA; 235 break; 236 case ixgbe_sfp_type_sr: 237 case ixgbe_sfp_type_lr: 238 case ixgbe_sfp_type_srlr_core0: 239 case ixgbe_sfp_type_srlr_core1: 240 case ixgbe_sfp_type_1g_sx_core0: 241 case ixgbe_sfp_type_1g_sx_core1: 242 case ixgbe_sfp_type_1g_lx_core0: 243 case ixgbe_sfp_type_1g_lx_core1: 244 ecmd->supported |= SUPPORTED_FIBRE; 245 ecmd->advertising |= ADVERTISED_FIBRE; 246 ecmd->port = PORT_FIBRE; 247 break; 248 case ixgbe_sfp_type_not_present: 249 ecmd->supported |= SUPPORTED_FIBRE; 250 ecmd->advertising |= ADVERTISED_FIBRE; 251 ecmd->port = PORT_NONE; 252 break; 253 case ixgbe_sfp_type_1g_cu_core0: 254 case ixgbe_sfp_type_1g_cu_core1: 255 ecmd->supported |= SUPPORTED_TP; 256 ecmd->advertising |= ADVERTISED_TP; 257 ecmd->port = PORT_TP; 258 break; 259 case ixgbe_sfp_type_unknown: 260 default: 261 ecmd->supported |= SUPPORTED_FIBRE; 262 ecmd->advertising |= ADVERTISED_FIBRE; 263 ecmd->port = PORT_OTHER; 264 break; 265 } 266 break; 267 case ixgbe_phy_xaui: 268 ecmd->supported |= SUPPORTED_FIBRE; 269 ecmd->advertising |= ADVERTISED_FIBRE; 270 ecmd->port = PORT_NONE; 271 break; 272 case ixgbe_phy_unknown: 273 case ixgbe_phy_generic: 274 case ixgbe_phy_sfp_unsupported: 275 default: 276 ecmd->supported |= SUPPORTED_FIBRE; 277 ecmd->advertising |= ADVERTISED_FIBRE; 278 ecmd->port = PORT_OTHER; 279 break; 280 } 281 282 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 283 if (link_up) { 284 switch (link_speed) { 285 case IXGBE_LINK_SPEED_10GB_FULL: 286 ethtool_cmd_speed_set(ecmd, SPEED_10000); 287 break; 288 case IXGBE_LINK_SPEED_1GB_FULL: 289 ethtool_cmd_speed_set(ecmd, SPEED_1000); 290 break; 291 case IXGBE_LINK_SPEED_100_FULL: 292 ethtool_cmd_speed_set(ecmd, SPEED_100); 293 break; 294 default: 295 break; 296 } 297 ecmd->duplex = DUPLEX_FULL; 298 } else { 299 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); 300 ecmd->duplex = DUPLEX_UNKNOWN; 301 } 302 303 return 0; 304 } 305 306 static int ixgbe_set_settings(struct net_device *netdev, 307 struct ethtool_cmd *ecmd) 308 { 309 struct ixgbe_adapter *adapter = netdev_priv(netdev); 310 struct ixgbe_hw *hw = &adapter->hw; 311 u32 advertised, old; 312 s32 err = 0; 313 314 if ((hw->phy.media_type == ixgbe_media_type_copper) || 315 (hw->phy.multispeed_fiber)) { 316 /* 317 * this function does not support duplex forcing, but can 318 * limit the advertising of the adapter to the specified speed 319 */ 320 if (ecmd->advertising & ~ecmd->supported) 321 return -EINVAL; 322 323 /* only allow one speed at a time if no autoneg */ 324 if (!ecmd->autoneg && hw->phy.multispeed_fiber) { 325 if (ecmd->advertising == 326 (ADVERTISED_10000baseT_Full | 327 ADVERTISED_1000baseT_Full)) 328 return -EINVAL; 329 } 330 331 old = hw->phy.autoneg_advertised; 332 advertised = 0; 333 if (ecmd->advertising & ADVERTISED_10000baseT_Full) 334 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 335 336 if (ecmd->advertising & ADVERTISED_1000baseT_Full) 337 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 338 339 if (ecmd->advertising & ADVERTISED_100baseT_Full) 340 advertised |= IXGBE_LINK_SPEED_100_FULL; 341 342 if (old == advertised) 343 return err; 344 /* this sets the link speed and restarts auto-neg */ 345 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 346 usleep_range(1000, 2000); 347 348 hw->mac.autotry_restart = true; 349 err = hw->mac.ops.setup_link(hw, advertised, true); 350 if (err) { 351 e_info(probe, "setup link failed with code %d\n", err); 352 hw->mac.ops.setup_link(hw, old, true); 353 } 354 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 355 } else { 356 /* in this case we currently only support 10Gb/FULL */ 357 u32 speed = ethtool_cmd_speed(ecmd); 358 if ((ecmd->autoneg == AUTONEG_ENABLE) || 359 (ecmd->advertising != ADVERTISED_10000baseT_Full) || 360 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) 361 return -EINVAL; 362 } 363 364 return err; 365 } 366 367 static void ixgbe_get_pauseparam(struct net_device *netdev, 368 struct ethtool_pauseparam *pause) 369 { 370 struct ixgbe_adapter *adapter = netdev_priv(netdev); 371 struct ixgbe_hw *hw = &adapter->hw; 372 373 if (ixgbe_device_supports_autoneg_fc(hw) && 374 !hw->fc.disable_fc_autoneg) 375 pause->autoneg = 1; 376 else 377 pause->autoneg = 0; 378 379 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 380 pause->rx_pause = 1; 381 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 382 pause->tx_pause = 1; 383 } else if (hw->fc.current_mode == ixgbe_fc_full) { 384 pause->rx_pause = 1; 385 pause->tx_pause = 1; 386 } 387 } 388 389 static int ixgbe_set_pauseparam(struct net_device *netdev, 390 struct ethtool_pauseparam *pause) 391 { 392 struct ixgbe_adapter *adapter = netdev_priv(netdev); 393 struct ixgbe_hw *hw = &adapter->hw; 394 struct ixgbe_fc_info fc = hw->fc; 395 396 /* 82598 does no support link flow control with DCB enabled */ 397 if ((hw->mac.type == ixgbe_mac_82598EB) && 398 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 399 return -EINVAL; 400 401 /* some devices do not support autoneg of link flow control */ 402 if ((pause->autoneg == AUTONEG_ENABLE) && 403 !ixgbe_device_supports_autoneg_fc(hw)) 404 return -EINVAL; 405 406 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 407 408 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 409 fc.requested_mode = ixgbe_fc_full; 410 else if (pause->rx_pause && !pause->tx_pause) 411 fc.requested_mode = ixgbe_fc_rx_pause; 412 else if (!pause->rx_pause && pause->tx_pause) 413 fc.requested_mode = ixgbe_fc_tx_pause; 414 else 415 fc.requested_mode = ixgbe_fc_none; 416 417 /* if the thing changed then we'll update and use new autoneg */ 418 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 419 hw->fc = fc; 420 if (netif_running(netdev)) 421 ixgbe_reinit_locked(adapter); 422 else 423 ixgbe_reset(adapter); 424 } 425 426 return 0; 427 } 428 429 static u32 ixgbe_get_msglevel(struct net_device *netdev) 430 { 431 struct ixgbe_adapter *adapter = netdev_priv(netdev); 432 return adapter->msg_enable; 433 } 434 435 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 436 { 437 struct ixgbe_adapter *adapter = netdev_priv(netdev); 438 adapter->msg_enable = data; 439 } 440 441 static int ixgbe_get_regs_len(struct net_device *netdev) 442 { 443 #define IXGBE_REGS_LEN 1139 444 return IXGBE_REGS_LEN * sizeof(u32); 445 } 446 447 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 448 449 static void ixgbe_get_regs(struct net_device *netdev, 450 struct ethtool_regs *regs, void *p) 451 { 452 struct ixgbe_adapter *adapter = netdev_priv(netdev); 453 struct ixgbe_hw *hw = &adapter->hw; 454 u32 *regs_buff = p; 455 u8 i; 456 457 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 458 459 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 460 hw->device_id; 461 462 /* General Registers */ 463 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 464 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 465 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 466 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 467 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 468 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 469 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 470 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 471 472 /* NVM Register */ 473 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC); 474 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 475 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA); 476 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 477 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 478 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 479 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 480 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 481 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 482 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC); 483 484 /* Interrupt */ 485 /* don't read EICR because it can clear interrupt causes, instead 486 * read EICS which is a shadow but doesn't clear EICR */ 487 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 488 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 489 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 490 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 491 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 492 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 493 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 494 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 495 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 496 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 497 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 498 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 499 500 /* Flow Control */ 501 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 502 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); 503 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); 504 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); 505 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); 506 for (i = 0; i < 8; i++) { 507 switch (hw->mac.type) { 508 case ixgbe_mac_82598EB: 509 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 510 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 511 break; 512 case ixgbe_mac_82599EB: 513 case ixgbe_mac_X540: 514 case ixgbe_mac_X550: 515 case ixgbe_mac_X550EM_x: 516 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 517 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 518 break; 519 default: 520 break; 521 } 522 } 523 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 524 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 525 526 /* Receive DMA */ 527 for (i = 0; i < 64; i++) 528 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 529 for (i = 0; i < 64; i++) 530 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 531 for (i = 0; i < 64; i++) 532 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 533 for (i = 0; i < 64; i++) 534 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 535 for (i = 0; i < 64; i++) 536 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 537 for (i = 0; i < 64; i++) 538 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 539 for (i = 0; i < 16; i++) 540 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 541 for (i = 0; i < 16; i++) 542 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 543 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 544 for (i = 0; i < 8; i++) 545 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 546 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 547 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 548 549 /* Receive */ 550 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 551 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 552 for (i = 0; i < 16; i++) 553 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 554 for (i = 0; i < 16; i++) 555 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 556 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 557 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 558 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 559 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 560 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 561 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 562 for (i = 0; i < 8; i++) 563 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 564 for (i = 0; i < 8; i++) 565 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 566 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 567 568 /* Transmit */ 569 for (i = 0; i < 32; i++) 570 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 571 for (i = 0; i < 32; i++) 572 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 573 for (i = 0; i < 32; i++) 574 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 575 for (i = 0; i < 32; i++) 576 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 577 for (i = 0; i < 32; i++) 578 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 579 for (i = 0; i < 32; i++) 580 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 581 for (i = 0; i < 32; i++) 582 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 583 for (i = 0; i < 32; i++) 584 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 585 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 586 for (i = 0; i < 16; i++) 587 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 588 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 589 for (i = 0; i < 8; i++) 590 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 591 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 592 593 /* Wake Up */ 594 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 595 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 596 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 597 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 598 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 599 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 600 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 601 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 602 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 603 604 /* DCB */ 605 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 606 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 607 608 switch (hw->mac.type) { 609 case ixgbe_mac_82598EB: 610 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 611 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 612 for (i = 0; i < 8; i++) 613 regs_buff[833 + i] = 614 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 615 for (i = 0; i < 8; i++) 616 regs_buff[841 + i] = 617 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 618 for (i = 0; i < 8; i++) 619 regs_buff[849 + i] = 620 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 621 for (i = 0; i < 8; i++) 622 regs_buff[857 + i] = 623 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 624 break; 625 case ixgbe_mac_82599EB: 626 case ixgbe_mac_X540: 627 case ixgbe_mac_X550: 628 case ixgbe_mac_X550EM_x: 629 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 630 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 631 for (i = 0; i < 8; i++) 632 regs_buff[833 + i] = 633 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 634 for (i = 0; i < 8; i++) 635 regs_buff[841 + i] = 636 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 637 for (i = 0; i < 8; i++) 638 regs_buff[849 + i] = 639 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 640 for (i = 0; i < 8; i++) 641 regs_buff[857 + i] = 642 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 643 break; 644 default: 645 break; 646 } 647 648 for (i = 0; i < 8; i++) 649 regs_buff[865 + i] = 650 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 651 for (i = 0; i < 8; i++) 652 regs_buff[873 + i] = 653 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 654 655 /* Statistics */ 656 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 657 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 658 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 659 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 660 for (i = 0; i < 8; i++) 661 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 662 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 663 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 664 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 665 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 666 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 667 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 668 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 669 for (i = 0; i < 8; i++) 670 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 671 for (i = 0; i < 8; i++) 672 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 673 for (i = 0; i < 8; i++) 674 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 675 for (i = 0; i < 8; i++) 676 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 677 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 678 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 679 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 680 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 681 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 682 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 683 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 684 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 685 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 686 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 687 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc); 688 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc); 689 for (i = 0; i < 8; i++) 690 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 691 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 692 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 693 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 694 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 695 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 696 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 697 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 698 regs_buff[961] = IXGBE_GET_STAT(adapter, tor); 699 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 700 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 701 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 702 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 703 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 704 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 705 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 706 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 707 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 708 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 709 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 710 for (i = 0; i < 16; i++) 711 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 712 for (i = 0; i < 16; i++) 713 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 714 for (i = 0; i < 16; i++) 715 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 716 for (i = 0; i < 16; i++) 717 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 718 719 /* MAC */ 720 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 721 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 722 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 723 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 724 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 725 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 726 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 727 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 728 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 729 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 730 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 731 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 732 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 733 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 734 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 735 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 736 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 737 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 738 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 739 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 740 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 741 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 742 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 743 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 744 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 745 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 746 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 747 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 748 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 749 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 750 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 751 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 752 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 753 754 /* Diagnostic */ 755 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 756 for (i = 0; i < 8; i++) 757 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 758 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 759 for (i = 0; i < 4; i++) 760 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 761 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 762 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 763 for (i = 0; i < 8; i++) 764 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 765 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 766 for (i = 0; i < 4; i++) 767 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 768 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 769 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 770 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); 771 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); 772 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); 773 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); 774 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 775 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); 776 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); 777 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); 778 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); 779 for (i = 0; i < 8; i++) 780 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 781 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 782 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 783 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 784 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 785 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 786 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 787 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 788 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 789 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 790 791 /* 82599 X540 specific registers */ 792 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 793 794 /* 82599 X540 specific DCB registers */ 795 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 796 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 797 for (i = 0; i < 4; i++) 798 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 799 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 800 /* same as RTTQCNRM */ 801 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 802 /* same as RTTQCNRR */ 803 804 /* X540 specific DCB registers */ 805 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 806 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 807 } 808 809 static int ixgbe_get_eeprom_len(struct net_device *netdev) 810 { 811 struct ixgbe_adapter *adapter = netdev_priv(netdev); 812 return adapter->hw.eeprom.word_size * 2; 813 } 814 815 static int ixgbe_get_eeprom(struct net_device *netdev, 816 struct ethtool_eeprom *eeprom, u8 *bytes) 817 { 818 struct ixgbe_adapter *adapter = netdev_priv(netdev); 819 struct ixgbe_hw *hw = &adapter->hw; 820 u16 *eeprom_buff; 821 int first_word, last_word, eeprom_len; 822 int ret_val = 0; 823 u16 i; 824 825 if (eeprom->len == 0) 826 return -EINVAL; 827 828 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 829 830 first_word = eeprom->offset >> 1; 831 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 832 eeprom_len = last_word - first_word + 1; 833 834 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); 835 if (!eeprom_buff) 836 return -ENOMEM; 837 838 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 839 eeprom_buff); 840 841 /* Device's eeprom is always little-endian, word addressable */ 842 for (i = 0; i < eeprom_len; i++) 843 le16_to_cpus(&eeprom_buff[i]); 844 845 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 846 kfree(eeprom_buff); 847 848 return ret_val; 849 } 850 851 static int ixgbe_set_eeprom(struct net_device *netdev, 852 struct ethtool_eeprom *eeprom, u8 *bytes) 853 { 854 struct ixgbe_adapter *adapter = netdev_priv(netdev); 855 struct ixgbe_hw *hw = &adapter->hw; 856 u16 *eeprom_buff; 857 void *ptr; 858 int max_len, first_word, last_word, ret_val = 0; 859 u16 i; 860 861 if (eeprom->len == 0) 862 return -EINVAL; 863 864 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 865 return -EINVAL; 866 867 max_len = hw->eeprom.word_size * 2; 868 869 first_word = eeprom->offset >> 1; 870 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 871 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 872 if (!eeprom_buff) 873 return -ENOMEM; 874 875 ptr = eeprom_buff; 876 877 if (eeprom->offset & 1) { 878 /* 879 * need read/modify/write of first changed EEPROM word 880 * only the second byte of the word is being modified 881 */ 882 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 883 if (ret_val) 884 goto err; 885 886 ptr++; 887 } 888 if ((eeprom->offset + eeprom->len) & 1) { 889 /* 890 * need read/modify/write of last changed EEPROM word 891 * only the first byte of the word is being modified 892 */ 893 ret_val = hw->eeprom.ops.read(hw, last_word, 894 &eeprom_buff[last_word - first_word]); 895 if (ret_val) 896 goto err; 897 } 898 899 /* Device's eeprom is always little-endian, word addressable */ 900 for (i = 0; i < last_word - first_word + 1; i++) 901 le16_to_cpus(&eeprom_buff[i]); 902 903 memcpy(ptr, bytes, eeprom->len); 904 905 for (i = 0; i < last_word - first_word + 1; i++) 906 cpu_to_le16s(&eeprom_buff[i]); 907 908 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 909 last_word - first_word + 1, 910 eeprom_buff); 911 912 /* Update the checksum */ 913 if (ret_val == 0) 914 hw->eeprom.ops.update_checksum(hw); 915 916 err: 917 kfree(eeprom_buff); 918 return ret_val; 919 } 920 921 static void ixgbe_get_drvinfo(struct net_device *netdev, 922 struct ethtool_drvinfo *drvinfo) 923 { 924 struct ixgbe_adapter *adapter = netdev_priv(netdev); 925 u32 nvm_track_id; 926 927 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 928 strlcpy(drvinfo->version, ixgbe_driver_version, 929 sizeof(drvinfo->version)); 930 931 nvm_track_id = (adapter->eeprom_verh << 16) | 932 adapter->eeprom_verl; 933 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x", 934 nvm_track_id); 935 936 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 937 sizeof(drvinfo->bus_info)); 938 drvinfo->n_stats = IXGBE_STATS_LEN; 939 drvinfo->testinfo_len = IXGBE_TEST_LEN; 940 drvinfo->regdump_len = ixgbe_get_regs_len(netdev); 941 } 942 943 static void ixgbe_get_ringparam(struct net_device *netdev, 944 struct ethtool_ringparam *ring) 945 { 946 struct ixgbe_adapter *adapter = netdev_priv(netdev); 947 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 948 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 949 950 ring->rx_max_pending = IXGBE_MAX_RXD; 951 ring->tx_max_pending = IXGBE_MAX_TXD; 952 ring->rx_pending = rx_ring->count; 953 ring->tx_pending = tx_ring->count; 954 } 955 956 static int ixgbe_set_ringparam(struct net_device *netdev, 957 struct ethtool_ringparam *ring) 958 { 959 struct ixgbe_adapter *adapter = netdev_priv(netdev); 960 struct ixgbe_ring *temp_ring; 961 int i, err = 0; 962 u32 new_rx_count, new_tx_count; 963 964 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 965 return -EINVAL; 966 967 new_tx_count = clamp_t(u32, ring->tx_pending, 968 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 969 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 970 971 new_rx_count = clamp_t(u32, ring->rx_pending, 972 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 973 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 974 975 if ((new_tx_count == adapter->tx_ring_count) && 976 (new_rx_count == adapter->rx_ring_count)) { 977 /* nothing to do */ 978 return 0; 979 } 980 981 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 982 usleep_range(1000, 2000); 983 984 if (!netif_running(adapter->netdev)) { 985 for (i = 0; i < adapter->num_tx_queues; i++) 986 adapter->tx_ring[i]->count = new_tx_count; 987 for (i = 0; i < adapter->num_rx_queues; i++) 988 adapter->rx_ring[i]->count = new_rx_count; 989 adapter->tx_ring_count = new_tx_count; 990 adapter->rx_ring_count = new_rx_count; 991 goto clear_reset; 992 } 993 994 /* allocate temporary buffer to store rings in */ 995 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues); 996 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring)); 997 998 if (!temp_ring) { 999 err = -ENOMEM; 1000 goto clear_reset; 1001 } 1002 1003 ixgbe_down(adapter); 1004 1005 /* 1006 * Setup new Tx resources and free the old Tx resources in that order. 1007 * We can then assign the new resources to the rings via a memcpy. 1008 * The advantage to this approach is that we are guaranteed to still 1009 * have resources even in the case of an allocation failure. 1010 */ 1011 if (new_tx_count != adapter->tx_ring_count) { 1012 for (i = 0; i < adapter->num_tx_queues; i++) { 1013 memcpy(&temp_ring[i], adapter->tx_ring[i], 1014 sizeof(struct ixgbe_ring)); 1015 1016 temp_ring[i].count = new_tx_count; 1017 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1018 if (err) { 1019 while (i) { 1020 i--; 1021 ixgbe_free_tx_resources(&temp_ring[i]); 1022 } 1023 goto err_setup; 1024 } 1025 } 1026 1027 for (i = 0; i < adapter->num_tx_queues; i++) { 1028 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1029 1030 memcpy(adapter->tx_ring[i], &temp_ring[i], 1031 sizeof(struct ixgbe_ring)); 1032 } 1033 1034 adapter->tx_ring_count = new_tx_count; 1035 } 1036 1037 /* Repeat the process for the Rx rings if needed */ 1038 if (new_rx_count != adapter->rx_ring_count) { 1039 for (i = 0; i < adapter->num_rx_queues; i++) { 1040 memcpy(&temp_ring[i], adapter->rx_ring[i], 1041 sizeof(struct ixgbe_ring)); 1042 1043 temp_ring[i].count = new_rx_count; 1044 err = ixgbe_setup_rx_resources(&temp_ring[i]); 1045 if (err) { 1046 while (i) { 1047 i--; 1048 ixgbe_free_rx_resources(&temp_ring[i]); 1049 } 1050 goto err_setup; 1051 } 1052 1053 } 1054 1055 for (i = 0; i < adapter->num_rx_queues; i++) { 1056 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1057 1058 memcpy(adapter->rx_ring[i], &temp_ring[i], 1059 sizeof(struct ixgbe_ring)); 1060 } 1061 1062 adapter->rx_ring_count = new_rx_count; 1063 } 1064 1065 err_setup: 1066 ixgbe_up(adapter); 1067 vfree(temp_ring); 1068 clear_reset: 1069 clear_bit(__IXGBE_RESETTING, &adapter->state); 1070 return err; 1071 } 1072 1073 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1074 { 1075 switch (sset) { 1076 case ETH_SS_TEST: 1077 return IXGBE_TEST_LEN; 1078 case ETH_SS_STATS: 1079 return IXGBE_STATS_LEN; 1080 default: 1081 return -EOPNOTSUPP; 1082 } 1083 } 1084 1085 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1086 struct ethtool_stats *stats, u64 *data) 1087 { 1088 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1089 struct rtnl_link_stats64 temp; 1090 const struct rtnl_link_stats64 *net_stats; 1091 unsigned int start; 1092 struct ixgbe_ring *ring; 1093 int i, j; 1094 char *p = NULL; 1095 1096 ixgbe_update_stats(adapter); 1097 net_stats = dev_get_stats(netdev, &temp); 1098 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1099 switch (ixgbe_gstrings_stats[i].type) { 1100 case NETDEV_STATS: 1101 p = (char *) net_stats + 1102 ixgbe_gstrings_stats[i].stat_offset; 1103 break; 1104 case IXGBE_STATS: 1105 p = (char *) adapter + 1106 ixgbe_gstrings_stats[i].stat_offset; 1107 break; 1108 default: 1109 data[i] = 0; 1110 continue; 1111 } 1112 1113 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1114 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1115 } 1116 for (j = 0; j < netdev->num_tx_queues; j++) { 1117 ring = adapter->tx_ring[j]; 1118 if (!ring) { 1119 data[i] = 0; 1120 data[i+1] = 0; 1121 i += 2; 1122 #ifdef BP_EXTENDED_STATS 1123 data[i] = 0; 1124 data[i+1] = 0; 1125 data[i+2] = 0; 1126 i += 3; 1127 #endif 1128 continue; 1129 } 1130 1131 do { 1132 start = u64_stats_fetch_begin_irq(&ring->syncp); 1133 data[i] = ring->stats.packets; 1134 data[i+1] = ring->stats.bytes; 1135 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1136 i += 2; 1137 #ifdef BP_EXTENDED_STATS 1138 data[i] = ring->stats.yields; 1139 data[i+1] = ring->stats.misses; 1140 data[i+2] = ring->stats.cleaned; 1141 i += 3; 1142 #endif 1143 } 1144 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1145 ring = adapter->rx_ring[j]; 1146 if (!ring) { 1147 data[i] = 0; 1148 data[i+1] = 0; 1149 i += 2; 1150 #ifdef BP_EXTENDED_STATS 1151 data[i] = 0; 1152 data[i+1] = 0; 1153 data[i+2] = 0; 1154 i += 3; 1155 #endif 1156 continue; 1157 } 1158 1159 do { 1160 start = u64_stats_fetch_begin_irq(&ring->syncp); 1161 data[i] = ring->stats.packets; 1162 data[i+1] = ring->stats.bytes; 1163 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1164 i += 2; 1165 #ifdef BP_EXTENDED_STATS 1166 data[i] = ring->stats.yields; 1167 data[i+1] = ring->stats.misses; 1168 data[i+2] = ring->stats.cleaned; 1169 i += 3; 1170 #endif 1171 } 1172 1173 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1174 data[i++] = adapter->stats.pxontxc[j]; 1175 data[i++] = adapter->stats.pxofftxc[j]; 1176 } 1177 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1178 data[i++] = adapter->stats.pxonrxc[j]; 1179 data[i++] = adapter->stats.pxoffrxc[j]; 1180 } 1181 } 1182 1183 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1184 u8 *data) 1185 { 1186 char *p = (char *)data; 1187 int i; 1188 1189 switch (stringset) { 1190 case ETH_SS_TEST: 1191 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1192 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1193 data += ETH_GSTRING_LEN; 1194 } 1195 break; 1196 case ETH_SS_STATS: 1197 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1198 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1199 ETH_GSTRING_LEN); 1200 p += ETH_GSTRING_LEN; 1201 } 1202 for (i = 0; i < netdev->num_tx_queues; i++) { 1203 sprintf(p, "tx_queue_%u_packets", i); 1204 p += ETH_GSTRING_LEN; 1205 sprintf(p, "tx_queue_%u_bytes", i); 1206 p += ETH_GSTRING_LEN; 1207 #ifdef BP_EXTENDED_STATS 1208 sprintf(p, "tx_queue_%u_bp_napi_yield", i); 1209 p += ETH_GSTRING_LEN; 1210 sprintf(p, "tx_queue_%u_bp_misses", i); 1211 p += ETH_GSTRING_LEN; 1212 sprintf(p, "tx_queue_%u_bp_cleaned", i); 1213 p += ETH_GSTRING_LEN; 1214 #endif /* BP_EXTENDED_STATS */ 1215 } 1216 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1217 sprintf(p, "rx_queue_%u_packets", i); 1218 p += ETH_GSTRING_LEN; 1219 sprintf(p, "rx_queue_%u_bytes", i); 1220 p += ETH_GSTRING_LEN; 1221 #ifdef BP_EXTENDED_STATS 1222 sprintf(p, "rx_queue_%u_bp_poll_yield", i); 1223 p += ETH_GSTRING_LEN; 1224 sprintf(p, "rx_queue_%u_bp_misses", i); 1225 p += ETH_GSTRING_LEN; 1226 sprintf(p, "rx_queue_%u_bp_cleaned", i); 1227 p += ETH_GSTRING_LEN; 1228 #endif /* BP_EXTENDED_STATS */ 1229 } 1230 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1231 sprintf(p, "tx_pb_%u_pxon", i); 1232 p += ETH_GSTRING_LEN; 1233 sprintf(p, "tx_pb_%u_pxoff", i); 1234 p += ETH_GSTRING_LEN; 1235 } 1236 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1237 sprintf(p, "rx_pb_%u_pxon", i); 1238 p += ETH_GSTRING_LEN; 1239 sprintf(p, "rx_pb_%u_pxoff", i); 1240 p += ETH_GSTRING_LEN; 1241 } 1242 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1243 break; 1244 } 1245 } 1246 1247 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1248 { 1249 struct ixgbe_hw *hw = &adapter->hw; 1250 bool link_up; 1251 u32 link_speed = 0; 1252 1253 if (ixgbe_removed(hw->hw_addr)) { 1254 *data = 1; 1255 return 1; 1256 } 1257 *data = 0; 1258 1259 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1260 if (link_up) 1261 return *data; 1262 else 1263 *data = 1; 1264 return *data; 1265 } 1266 1267 /* ethtool register test data */ 1268 struct ixgbe_reg_test { 1269 u16 reg; 1270 u8 array_len; 1271 u8 test_type; 1272 u32 mask; 1273 u32 write; 1274 }; 1275 1276 /* In the hardware, registers are laid out either singly, in arrays 1277 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1278 * most tests take place on arrays or single registers (handled 1279 * as a single-element array) and special-case the tables. 1280 * Table tests are always pattern tests. 1281 * 1282 * We also make provision for some required setup steps by specifying 1283 * registers to be written without any read-back testing. 1284 */ 1285 1286 #define PATTERN_TEST 1 1287 #define SET_READ_TEST 2 1288 #define WRITE_NO_TEST 3 1289 #define TABLE32_TEST 4 1290 #define TABLE64_TEST_LO 5 1291 #define TABLE64_TEST_HI 6 1292 1293 /* default 82599 register test */ 1294 static const struct ixgbe_reg_test reg_test_82599[] = { 1295 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1296 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1297 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1298 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1299 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1300 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1301 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1302 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1303 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1304 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1305 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1306 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1307 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1308 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1309 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1310 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1311 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1312 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1313 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1314 { .reg = 0 } 1315 }; 1316 1317 /* default 82598 register test */ 1318 static const struct ixgbe_reg_test reg_test_82598[] = { 1319 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1320 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1321 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1322 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1323 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1324 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1325 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1326 /* Enable all four RX queues before testing. */ 1327 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1328 /* RDH is read-only for 82598, only test RDT. */ 1329 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1330 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1331 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1332 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1333 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1334 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1335 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1336 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1337 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1338 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1339 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1340 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1341 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1342 { .reg = 0 } 1343 }; 1344 1345 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1346 u32 mask, u32 write) 1347 { 1348 u32 pat, val, before; 1349 static const u32 test_pattern[] = { 1350 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1351 1352 if (ixgbe_removed(adapter->hw.hw_addr)) { 1353 *data = 1; 1354 return 1; 1355 } 1356 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1357 before = ixgbe_read_reg(&adapter->hw, reg); 1358 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1359 val = ixgbe_read_reg(&adapter->hw, reg); 1360 if (val != (test_pattern[pat] & write & mask)) { 1361 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1362 reg, val, (test_pattern[pat] & write & mask)); 1363 *data = reg; 1364 ixgbe_write_reg(&adapter->hw, reg, before); 1365 return true; 1366 } 1367 ixgbe_write_reg(&adapter->hw, reg, before); 1368 } 1369 return false; 1370 } 1371 1372 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1373 u32 mask, u32 write) 1374 { 1375 u32 val, before; 1376 1377 if (ixgbe_removed(adapter->hw.hw_addr)) { 1378 *data = 1; 1379 return 1; 1380 } 1381 before = ixgbe_read_reg(&adapter->hw, reg); 1382 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1383 val = ixgbe_read_reg(&adapter->hw, reg); 1384 if ((write & mask) != (val & mask)) { 1385 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1386 reg, (val & mask), (write & mask)); 1387 *data = reg; 1388 ixgbe_write_reg(&adapter->hw, reg, before); 1389 return true; 1390 } 1391 ixgbe_write_reg(&adapter->hw, reg, before); 1392 return false; 1393 } 1394 1395 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1396 { 1397 const struct ixgbe_reg_test *test; 1398 u32 value, before, after; 1399 u32 i, toggle; 1400 1401 if (ixgbe_removed(adapter->hw.hw_addr)) { 1402 e_err(drv, "Adapter removed - register test blocked\n"); 1403 *data = 1; 1404 return 1; 1405 } 1406 switch (adapter->hw.mac.type) { 1407 case ixgbe_mac_82598EB: 1408 toggle = 0x7FFFF3FF; 1409 test = reg_test_82598; 1410 break; 1411 case ixgbe_mac_82599EB: 1412 case ixgbe_mac_X540: 1413 case ixgbe_mac_X550: 1414 case ixgbe_mac_X550EM_x: 1415 toggle = 0x7FFFF30F; 1416 test = reg_test_82599; 1417 break; 1418 default: 1419 *data = 1; 1420 return 1; 1421 } 1422 1423 /* 1424 * Because the status register is such a special case, 1425 * we handle it separately from the rest of the register 1426 * tests. Some bits are read-only, some toggle, and some 1427 * are writeable on newer MACs. 1428 */ 1429 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1430 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1431 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1432 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1433 if (value != after) { 1434 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1435 after, value); 1436 *data = 1; 1437 return 1; 1438 } 1439 /* restore previous status */ 1440 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1441 1442 /* 1443 * Perform the remainder of the register test, looping through 1444 * the test table until we either fail or reach the null entry. 1445 */ 1446 while (test->reg) { 1447 for (i = 0; i < test->array_len; i++) { 1448 bool b = false; 1449 1450 switch (test->test_type) { 1451 case PATTERN_TEST: 1452 b = reg_pattern_test(adapter, data, 1453 test->reg + (i * 0x40), 1454 test->mask, 1455 test->write); 1456 break; 1457 case SET_READ_TEST: 1458 b = reg_set_and_check(adapter, data, 1459 test->reg + (i * 0x40), 1460 test->mask, 1461 test->write); 1462 break; 1463 case WRITE_NO_TEST: 1464 ixgbe_write_reg(&adapter->hw, 1465 test->reg + (i * 0x40), 1466 test->write); 1467 break; 1468 case TABLE32_TEST: 1469 b = reg_pattern_test(adapter, data, 1470 test->reg + (i * 4), 1471 test->mask, 1472 test->write); 1473 break; 1474 case TABLE64_TEST_LO: 1475 b = reg_pattern_test(adapter, data, 1476 test->reg + (i * 8), 1477 test->mask, 1478 test->write); 1479 break; 1480 case TABLE64_TEST_HI: 1481 b = reg_pattern_test(adapter, data, 1482 (test->reg + 4) + (i * 8), 1483 test->mask, 1484 test->write); 1485 break; 1486 } 1487 if (b) 1488 return 1; 1489 } 1490 test++; 1491 } 1492 1493 *data = 0; 1494 return 0; 1495 } 1496 1497 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1498 { 1499 struct ixgbe_hw *hw = &adapter->hw; 1500 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1501 *data = 1; 1502 else 1503 *data = 0; 1504 return *data; 1505 } 1506 1507 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1508 { 1509 struct net_device *netdev = (struct net_device *) data; 1510 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1511 1512 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1513 1514 return IRQ_HANDLED; 1515 } 1516 1517 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1518 { 1519 struct net_device *netdev = adapter->netdev; 1520 u32 mask, i = 0, shared_int = true; 1521 u32 irq = adapter->pdev->irq; 1522 1523 *data = 0; 1524 1525 /* Hook up test interrupt handler just for this test */ 1526 if (adapter->msix_entries) { 1527 /* NOTE: we don't test MSI-X interrupts here, yet */ 1528 return 0; 1529 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1530 shared_int = false; 1531 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1532 netdev)) { 1533 *data = 1; 1534 return -1; 1535 } 1536 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1537 netdev->name, netdev)) { 1538 shared_int = false; 1539 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1540 netdev->name, netdev)) { 1541 *data = 1; 1542 return -1; 1543 } 1544 e_info(hw, "testing %s interrupt\n", shared_int ? 1545 "shared" : "unshared"); 1546 1547 /* Disable all the interrupts */ 1548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1549 IXGBE_WRITE_FLUSH(&adapter->hw); 1550 usleep_range(10000, 20000); 1551 1552 /* Test each interrupt */ 1553 for (; i < 10; i++) { 1554 /* Interrupt to test */ 1555 mask = 1 << i; 1556 1557 if (!shared_int) { 1558 /* 1559 * Disable the interrupts to be reported in 1560 * the cause register and then force the same 1561 * interrupt and see if one gets posted. If 1562 * an interrupt was posted to the bus, the 1563 * test failed. 1564 */ 1565 adapter->test_icr = 0; 1566 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1567 ~mask & 0x00007FFF); 1568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1569 ~mask & 0x00007FFF); 1570 IXGBE_WRITE_FLUSH(&adapter->hw); 1571 usleep_range(10000, 20000); 1572 1573 if (adapter->test_icr & mask) { 1574 *data = 3; 1575 break; 1576 } 1577 } 1578 1579 /* 1580 * Enable the interrupt to be reported in the cause 1581 * register and then force the same interrupt and see 1582 * if one gets posted. If an interrupt was not posted 1583 * to the bus, the test failed. 1584 */ 1585 adapter->test_icr = 0; 1586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1588 IXGBE_WRITE_FLUSH(&adapter->hw); 1589 usleep_range(10000, 20000); 1590 1591 if (!(adapter->test_icr & mask)) { 1592 *data = 4; 1593 break; 1594 } 1595 1596 if (!shared_int) { 1597 /* 1598 * Disable the other interrupts to be reported in 1599 * the cause register and then force the other 1600 * interrupts and see if any get posted. If 1601 * an interrupt was posted to the bus, the 1602 * test failed. 1603 */ 1604 adapter->test_icr = 0; 1605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1606 ~mask & 0x00007FFF); 1607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1608 ~mask & 0x00007FFF); 1609 IXGBE_WRITE_FLUSH(&adapter->hw); 1610 usleep_range(10000, 20000); 1611 1612 if (adapter->test_icr) { 1613 *data = 5; 1614 break; 1615 } 1616 } 1617 } 1618 1619 /* Disable all the interrupts */ 1620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1621 IXGBE_WRITE_FLUSH(&adapter->hw); 1622 usleep_range(10000, 20000); 1623 1624 /* Unhook test interrupt handler */ 1625 free_irq(irq, netdev); 1626 1627 return *data; 1628 } 1629 1630 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1631 { 1632 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1633 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1634 struct ixgbe_hw *hw = &adapter->hw; 1635 u32 reg_ctl; 1636 1637 /* shut down the DMA engines now so they can be reinitialized later */ 1638 1639 /* first Rx */ 1640 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1641 reg_ctl &= ~IXGBE_RXCTRL_RXEN; 1642 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl); 1643 ixgbe_disable_rx_queue(adapter, rx_ring); 1644 1645 /* now Tx */ 1646 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); 1647 reg_ctl &= ~IXGBE_TXDCTL_ENABLE; 1648 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); 1649 1650 switch (hw->mac.type) { 1651 case ixgbe_mac_82599EB: 1652 case ixgbe_mac_X540: 1653 case ixgbe_mac_X550: 1654 case ixgbe_mac_X550EM_x: 1655 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1656 reg_ctl &= ~IXGBE_DMATXCTL_TE; 1657 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); 1658 break; 1659 default: 1660 break; 1661 } 1662 1663 ixgbe_reset(adapter); 1664 1665 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1666 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1667 } 1668 1669 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1670 { 1671 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1672 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1673 u32 rctl, reg_data; 1674 int ret_val; 1675 int err; 1676 1677 /* Setup Tx descriptor ring and Tx buffers */ 1678 tx_ring->count = IXGBE_DEFAULT_TXD; 1679 tx_ring->queue_index = 0; 1680 tx_ring->dev = &adapter->pdev->dev; 1681 tx_ring->netdev = adapter->netdev; 1682 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1683 1684 err = ixgbe_setup_tx_resources(tx_ring); 1685 if (err) 1686 return 1; 1687 1688 switch (adapter->hw.mac.type) { 1689 case ixgbe_mac_82599EB: 1690 case ixgbe_mac_X540: 1691 case ixgbe_mac_X550: 1692 case ixgbe_mac_X550EM_x: 1693 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1694 reg_data |= IXGBE_DMATXCTL_TE; 1695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1696 break; 1697 default: 1698 break; 1699 } 1700 1701 ixgbe_configure_tx_ring(adapter, tx_ring); 1702 1703 /* Setup Rx Descriptor ring and Rx buffers */ 1704 rx_ring->count = IXGBE_DEFAULT_RXD; 1705 rx_ring->queue_index = 0; 1706 rx_ring->dev = &adapter->pdev->dev; 1707 rx_ring->netdev = adapter->netdev; 1708 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1709 1710 err = ixgbe_setup_rx_resources(rx_ring); 1711 if (err) { 1712 ret_val = 4; 1713 goto err_nomem; 1714 } 1715 1716 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1717 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN); 1718 1719 ixgbe_configure_rx_ring(adapter, rx_ring); 1720 1721 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS; 1722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1723 1724 return 0; 1725 1726 err_nomem: 1727 ixgbe_free_desc_rings(adapter); 1728 return ret_val; 1729 } 1730 1731 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1732 { 1733 struct ixgbe_hw *hw = &adapter->hw; 1734 u32 reg_data; 1735 1736 1737 /* Setup MAC loopback */ 1738 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1739 reg_data |= IXGBE_HLREG0_LPBK; 1740 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1741 1742 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1743 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1744 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1745 1746 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1747 switch (adapter->hw.mac.type) { 1748 case ixgbe_mac_X540: 1749 case ixgbe_mac_X550: 1750 case ixgbe_mac_X550EM_x: 1751 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1752 reg_data |= IXGBE_MACC_FLU; 1753 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1754 break; 1755 default: 1756 if (hw->mac.orig_autoc) { 1757 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1758 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1759 } else { 1760 return 10; 1761 } 1762 } 1763 IXGBE_WRITE_FLUSH(hw); 1764 usleep_range(10000, 20000); 1765 1766 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1767 if (hw->mac.type == ixgbe_mac_82598EB) { 1768 u8 atlas; 1769 1770 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1771 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1772 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1773 1774 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1775 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1776 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1777 1778 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1779 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1780 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1781 1782 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1783 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1784 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1785 } 1786 1787 return 0; 1788 } 1789 1790 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1791 { 1792 u32 reg_data; 1793 1794 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1795 reg_data &= ~IXGBE_HLREG0_LPBK; 1796 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1797 } 1798 1799 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1800 unsigned int frame_size) 1801 { 1802 memset(skb->data, 0xFF, frame_size); 1803 frame_size >>= 1; 1804 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1805 memset(&skb->data[frame_size + 10], 0xBE, 1); 1806 memset(&skb->data[frame_size + 12], 0xAF, 1); 1807 } 1808 1809 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1810 unsigned int frame_size) 1811 { 1812 unsigned char *data; 1813 bool match = true; 1814 1815 frame_size >>= 1; 1816 1817 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1818 1819 if (data[3] != 0xFF || 1820 data[frame_size + 10] != 0xBE || 1821 data[frame_size + 12] != 0xAF) 1822 match = false; 1823 1824 kunmap(rx_buffer->page); 1825 1826 return match; 1827 } 1828 1829 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1830 struct ixgbe_ring *tx_ring, 1831 unsigned int size) 1832 { 1833 union ixgbe_adv_rx_desc *rx_desc; 1834 struct ixgbe_rx_buffer *rx_buffer; 1835 struct ixgbe_tx_buffer *tx_buffer; 1836 u16 rx_ntc, tx_ntc, count = 0; 1837 1838 /* initialize next to clean and descriptor values */ 1839 rx_ntc = rx_ring->next_to_clean; 1840 tx_ntc = tx_ring->next_to_clean; 1841 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1842 1843 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) { 1844 /* check Rx buffer */ 1845 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 1846 1847 /* sync Rx buffer for CPU read */ 1848 dma_sync_single_for_cpu(rx_ring->dev, 1849 rx_buffer->dma, 1850 ixgbe_rx_bufsz(rx_ring), 1851 DMA_FROM_DEVICE); 1852 1853 /* verify contents of skb */ 1854 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 1855 count++; 1856 1857 /* sync Rx buffer for device write */ 1858 dma_sync_single_for_device(rx_ring->dev, 1859 rx_buffer->dma, 1860 ixgbe_rx_bufsz(rx_ring), 1861 DMA_FROM_DEVICE); 1862 1863 /* unmap buffer on Tx side */ 1864 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1865 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 1866 1867 /* increment Rx/Tx next to clean counters */ 1868 rx_ntc++; 1869 if (rx_ntc == rx_ring->count) 1870 rx_ntc = 0; 1871 tx_ntc++; 1872 if (tx_ntc == tx_ring->count) 1873 tx_ntc = 0; 1874 1875 /* fetch next descriptor */ 1876 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1877 } 1878 1879 netdev_tx_reset_queue(txring_txq(tx_ring)); 1880 1881 /* re-map buffers to ring, store next to clean values */ 1882 ixgbe_alloc_rx_buffers(rx_ring, count); 1883 rx_ring->next_to_clean = rx_ntc; 1884 tx_ring->next_to_clean = tx_ntc; 1885 1886 return count; 1887 } 1888 1889 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1890 { 1891 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1892 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1893 int i, j, lc, good_cnt, ret_val = 0; 1894 unsigned int size = 1024; 1895 netdev_tx_t tx_ret_val; 1896 struct sk_buff *skb; 1897 u32 flags_orig = adapter->flags; 1898 1899 /* DCB can modify the frames on Tx */ 1900 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1901 1902 /* allocate test skb */ 1903 skb = alloc_skb(size, GFP_KERNEL); 1904 if (!skb) 1905 return 11; 1906 1907 /* place data into test skb */ 1908 ixgbe_create_lbtest_frame(skb, size); 1909 skb_put(skb, size); 1910 1911 /* 1912 * Calculate the loop count based on the largest descriptor ring 1913 * The idea is to wrap the largest ring a number of times using 64 1914 * send/receive pairs during each loop 1915 */ 1916 1917 if (rx_ring->count <= tx_ring->count) 1918 lc = ((tx_ring->count / 64) * 2) + 1; 1919 else 1920 lc = ((rx_ring->count / 64) * 2) + 1; 1921 1922 for (j = 0; j <= lc; j++) { 1923 /* reset count of good packets */ 1924 good_cnt = 0; 1925 1926 /* place 64 packets on the transmit queue*/ 1927 for (i = 0; i < 64; i++) { 1928 skb_get(skb); 1929 tx_ret_val = ixgbe_xmit_frame_ring(skb, 1930 adapter, 1931 tx_ring); 1932 if (tx_ret_val == NETDEV_TX_OK) 1933 good_cnt++; 1934 } 1935 1936 if (good_cnt != 64) { 1937 ret_val = 12; 1938 break; 1939 } 1940 1941 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1942 msleep(200); 1943 1944 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 1945 if (good_cnt != 64) { 1946 ret_val = 13; 1947 break; 1948 } 1949 } 1950 1951 /* free the original skb */ 1952 kfree_skb(skb); 1953 adapter->flags = flags_orig; 1954 1955 return ret_val; 1956 } 1957 1958 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 1959 { 1960 *data = ixgbe_setup_desc_rings(adapter); 1961 if (*data) 1962 goto out; 1963 *data = ixgbe_setup_loopback_test(adapter); 1964 if (*data) 1965 goto err_loopback; 1966 *data = ixgbe_run_loopback_test(adapter); 1967 ixgbe_loopback_cleanup(adapter); 1968 1969 err_loopback: 1970 ixgbe_free_desc_rings(adapter); 1971 out: 1972 return *data; 1973 } 1974 1975 static void ixgbe_diag_test(struct net_device *netdev, 1976 struct ethtool_test *eth_test, u64 *data) 1977 { 1978 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1979 bool if_running = netif_running(netdev); 1980 1981 if (ixgbe_removed(adapter->hw.hw_addr)) { 1982 e_err(hw, "Adapter removed - test blocked\n"); 1983 data[0] = 1; 1984 data[1] = 1; 1985 data[2] = 1; 1986 data[3] = 1; 1987 data[4] = 1; 1988 eth_test->flags |= ETH_TEST_FL_FAILED; 1989 return; 1990 } 1991 set_bit(__IXGBE_TESTING, &adapter->state); 1992 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1993 struct ixgbe_hw *hw = &adapter->hw; 1994 1995 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 1996 int i; 1997 for (i = 0; i < adapter->num_vfs; i++) { 1998 if (adapter->vfinfo[i].clear_to_send) { 1999 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2000 data[0] = 1; 2001 data[1] = 1; 2002 data[2] = 1; 2003 data[3] = 1; 2004 data[4] = 1; 2005 eth_test->flags |= ETH_TEST_FL_FAILED; 2006 clear_bit(__IXGBE_TESTING, 2007 &adapter->state); 2008 goto skip_ol_tests; 2009 } 2010 } 2011 } 2012 2013 /* Offline tests */ 2014 e_info(hw, "offline testing starting\n"); 2015 2016 /* Link test performed before hardware reset so autoneg doesn't 2017 * interfere with test result 2018 */ 2019 if (ixgbe_link_test(adapter, &data[4])) 2020 eth_test->flags |= ETH_TEST_FL_FAILED; 2021 2022 if (if_running) 2023 /* indicate we're in test mode */ 2024 dev_close(netdev); 2025 else 2026 ixgbe_reset(adapter); 2027 2028 e_info(hw, "register testing starting\n"); 2029 if (ixgbe_reg_test(adapter, &data[0])) 2030 eth_test->flags |= ETH_TEST_FL_FAILED; 2031 2032 ixgbe_reset(adapter); 2033 e_info(hw, "eeprom testing starting\n"); 2034 if (ixgbe_eeprom_test(adapter, &data[1])) 2035 eth_test->flags |= ETH_TEST_FL_FAILED; 2036 2037 ixgbe_reset(adapter); 2038 e_info(hw, "interrupt testing starting\n"); 2039 if (ixgbe_intr_test(adapter, &data[2])) 2040 eth_test->flags |= ETH_TEST_FL_FAILED; 2041 2042 /* If SRIOV or VMDq is enabled then skip MAC 2043 * loopback diagnostic. */ 2044 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2045 IXGBE_FLAG_VMDQ_ENABLED)) { 2046 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2047 data[3] = 0; 2048 goto skip_loopback; 2049 } 2050 2051 ixgbe_reset(adapter); 2052 e_info(hw, "loopback testing starting\n"); 2053 if (ixgbe_loopback_test(adapter, &data[3])) 2054 eth_test->flags |= ETH_TEST_FL_FAILED; 2055 2056 skip_loopback: 2057 ixgbe_reset(adapter); 2058 2059 /* clear testing bit and return adapter to previous state */ 2060 clear_bit(__IXGBE_TESTING, &adapter->state); 2061 if (if_running) 2062 dev_open(netdev); 2063 else if (hw->mac.ops.disable_tx_laser) 2064 hw->mac.ops.disable_tx_laser(hw); 2065 } else { 2066 e_info(hw, "online testing starting\n"); 2067 2068 /* Online tests */ 2069 if (ixgbe_link_test(adapter, &data[4])) 2070 eth_test->flags |= ETH_TEST_FL_FAILED; 2071 2072 /* Offline tests aren't run; pass by default */ 2073 data[0] = 0; 2074 data[1] = 0; 2075 data[2] = 0; 2076 data[3] = 0; 2077 2078 clear_bit(__IXGBE_TESTING, &adapter->state); 2079 } 2080 2081 skip_ol_tests: 2082 msleep_interruptible(4 * 1000); 2083 } 2084 2085 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2086 struct ethtool_wolinfo *wol) 2087 { 2088 struct ixgbe_hw *hw = &adapter->hw; 2089 int retval = 0; 2090 2091 /* WOL not supported for all devices */ 2092 if (!ixgbe_wol_supported(adapter, hw->device_id, 2093 hw->subsystem_device_id)) { 2094 retval = 1; 2095 wol->supported = 0; 2096 } 2097 2098 return retval; 2099 } 2100 2101 static void ixgbe_get_wol(struct net_device *netdev, 2102 struct ethtool_wolinfo *wol) 2103 { 2104 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2105 2106 wol->supported = WAKE_UCAST | WAKE_MCAST | 2107 WAKE_BCAST | WAKE_MAGIC; 2108 wol->wolopts = 0; 2109 2110 if (ixgbe_wol_exclusion(adapter, wol) || 2111 !device_can_wakeup(&adapter->pdev->dev)) 2112 return; 2113 2114 if (adapter->wol & IXGBE_WUFC_EX) 2115 wol->wolopts |= WAKE_UCAST; 2116 if (adapter->wol & IXGBE_WUFC_MC) 2117 wol->wolopts |= WAKE_MCAST; 2118 if (adapter->wol & IXGBE_WUFC_BC) 2119 wol->wolopts |= WAKE_BCAST; 2120 if (adapter->wol & IXGBE_WUFC_MAG) 2121 wol->wolopts |= WAKE_MAGIC; 2122 } 2123 2124 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2125 { 2126 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2127 2128 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 2129 return -EOPNOTSUPP; 2130 2131 if (ixgbe_wol_exclusion(adapter, wol)) 2132 return wol->wolopts ? -EOPNOTSUPP : 0; 2133 2134 adapter->wol = 0; 2135 2136 if (wol->wolopts & WAKE_UCAST) 2137 adapter->wol |= IXGBE_WUFC_EX; 2138 if (wol->wolopts & WAKE_MCAST) 2139 adapter->wol |= IXGBE_WUFC_MC; 2140 if (wol->wolopts & WAKE_BCAST) 2141 adapter->wol |= IXGBE_WUFC_BC; 2142 if (wol->wolopts & WAKE_MAGIC) 2143 adapter->wol |= IXGBE_WUFC_MAG; 2144 2145 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2146 2147 return 0; 2148 } 2149 2150 static int ixgbe_nway_reset(struct net_device *netdev) 2151 { 2152 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2153 2154 if (netif_running(netdev)) 2155 ixgbe_reinit_locked(adapter); 2156 2157 return 0; 2158 } 2159 2160 static int ixgbe_set_phys_id(struct net_device *netdev, 2161 enum ethtool_phys_id_state state) 2162 { 2163 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2164 struct ixgbe_hw *hw = &adapter->hw; 2165 2166 switch (state) { 2167 case ETHTOOL_ID_ACTIVE: 2168 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2169 return 2; 2170 2171 case ETHTOOL_ID_ON: 2172 hw->mac.ops.led_on(hw, IXGBE_LED_ON); 2173 break; 2174 2175 case ETHTOOL_ID_OFF: 2176 hw->mac.ops.led_off(hw, IXGBE_LED_ON); 2177 break; 2178 2179 case ETHTOOL_ID_INACTIVE: 2180 /* Restore LED settings */ 2181 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2182 break; 2183 } 2184 2185 return 0; 2186 } 2187 2188 static int ixgbe_get_coalesce(struct net_device *netdev, 2189 struct ethtool_coalesce *ec) 2190 { 2191 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2192 2193 /* only valid if in constant ITR mode */ 2194 if (adapter->rx_itr_setting <= 1) 2195 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2196 else 2197 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2198 2199 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2200 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2201 return 0; 2202 2203 /* only valid if in constant ITR mode */ 2204 if (adapter->tx_itr_setting <= 1) 2205 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2206 else 2207 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2208 2209 return 0; 2210 } 2211 2212 /* 2213 * this function must be called before setting the new value of 2214 * rx_itr_setting 2215 */ 2216 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2217 { 2218 struct net_device *netdev = adapter->netdev; 2219 2220 /* nothing to do if LRO or RSC are not enabled */ 2221 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2222 !(netdev->features & NETIF_F_LRO)) 2223 return false; 2224 2225 /* check the feature flag value and enable RSC if necessary */ 2226 if (adapter->rx_itr_setting == 1 || 2227 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2228 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2229 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2230 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2231 return true; 2232 } 2233 /* if interrupt rate is too high then disable RSC */ 2234 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2235 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2236 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2237 return true; 2238 } 2239 return false; 2240 } 2241 2242 static int ixgbe_set_coalesce(struct net_device *netdev, 2243 struct ethtool_coalesce *ec) 2244 { 2245 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2246 struct ixgbe_q_vector *q_vector; 2247 int i; 2248 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2249 bool need_reset = false; 2250 2251 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2252 /* reject Tx specific changes in case of mixed RxTx vectors */ 2253 if (ec->tx_coalesce_usecs) 2254 return -EINVAL; 2255 tx_itr_prev = adapter->rx_itr_setting; 2256 } else { 2257 tx_itr_prev = adapter->tx_itr_setting; 2258 } 2259 2260 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2261 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2262 return -EINVAL; 2263 2264 if (ec->rx_coalesce_usecs > 1) 2265 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2266 else 2267 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2268 2269 if (adapter->rx_itr_setting == 1) 2270 rx_itr_param = IXGBE_20K_ITR; 2271 else 2272 rx_itr_param = adapter->rx_itr_setting; 2273 2274 if (ec->tx_coalesce_usecs > 1) 2275 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2276 else 2277 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2278 2279 if (adapter->tx_itr_setting == 1) 2280 tx_itr_param = IXGBE_10K_ITR; 2281 else 2282 tx_itr_param = adapter->tx_itr_setting; 2283 2284 /* mixed Rx/Tx */ 2285 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2286 adapter->tx_itr_setting = adapter->rx_itr_setting; 2287 2288 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2289 if ((adapter->tx_itr_setting != 1) && 2290 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2291 if ((tx_itr_prev == 1) || 2292 (tx_itr_prev >= IXGBE_100K_ITR)) 2293 need_reset = true; 2294 } else { 2295 if ((tx_itr_prev != 1) && 2296 (tx_itr_prev < IXGBE_100K_ITR)) 2297 need_reset = true; 2298 } 2299 2300 /* check the old value and enable RSC if necessary */ 2301 need_reset |= ixgbe_update_rsc(adapter); 2302 2303 for (i = 0; i < adapter->num_q_vectors; i++) { 2304 q_vector = adapter->q_vector[i]; 2305 if (q_vector->tx.count && !q_vector->rx.count) 2306 /* tx only */ 2307 q_vector->itr = tx_itr_param; 2308 else 2309 /* rx only or mixed */ 2310 q_vector->itr = rx_itr_param; 2311 ixgbe_write_eitr(q_vector); 2312 } 2313 2314 /* 2315 * do reset here at the end to make sure EITR==0 case is handled 2316 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2317 * also locks in RSC enable/disable which requires reset 2318 */ 2319 if (need_reset) 2320 ixgbe_do_reset(netdev); 2321 2322 return 0; 2323 } 2324 2325 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2326 struct ethtool_rxnfc *cmd) 2327 { 2328 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2329 struct ethtool_rx_flow_spec *fsp = 2330 (struct ethtool_rx_flow_spec *)&cmd->fs; 2331 struct hlist_node *node2; 2332 struct ixgbe_fdir_filter *rule = NULL; 2333 2334 /* report total rule count */ 2335 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2336 2337 hlist_for_each_entry_safe(rule, node2, 2338 &adapter->fdir_filter_list, fdir_node) { 2339 if (fsp->location <= rule->sw_idx) 2340 break; 2341 } 2342 2343 if (!rule || fsp->location != rule->sw_idx) 2344 return -EINVAL; 2345 2346 /* fill out the flow spec entry */ 2347 2348 /* set flow type field */ 2349 switch (rule->filter.formatted.flow_type) { 2350 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2351 fsp->flow_type = TCP_V4_FLOW; 2352 break; 2353 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2354 fsp->flow_type = UDP_V4_FLOW; 2355 break; 2356 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2357 fsp->flow_type = SCTP_V4_FLOW; 2358 break; 2359 case IXGBE_ATR_FLOW_TYPE_IPV4: 2360 fsp->flow_type = IP_USER_FLOW; 2361 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2362 fsp->h_u.usr_ip4_spec.proto = 0; 2363 fsp->m_u.usr_ip4_spec.proto = 0; 2364 break; 2365 default: 2366 return -EINVAL; 2367 } 2368 2369 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2370 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2371 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2372 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2373 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2374 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2375 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2376 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2377 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2378 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2379 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2380 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2381 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2382 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2383 fsp->flow_type |= FLOW_EXT; 2384 2385 /* record action */ 2386 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2387 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2388 else 2389 fsp->ring_cookie = rule->action; 2390 2391 return 0; 2392 } 2393 2394 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2395 struct ethtool_rxnfc *cmd, 2396 u32 *rule_locs) 2397 { 2398 struct hlist_node *node2; 2399 struct ixgbe_fdir_filter *rule; 2400 int cnt = 0; 2401 2402 /* report total rule count */ 2403 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2404 2405 hlist_for_each_entry_safe(rule, node2, 2406 &adapter->fdir_filter_list, fdir_node) { 2407 if (cnt == cmd->rule_cnt) 2408 return -EMSGSIZE; 2409 rule_locs[cnt] = rule->sw_idx; 2410 cnt++; 2411 } 2412 2413 cmd->rule_cnt = cnt; 2414 2415 return 0; 2416 } 2417 2418 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2419 struct ethtool_rxnfc *cmd) 2420 { 2421 cmd->data = 0; 2422 2423 /* Report default options for RSS on ixgbe */ 2424 switch (cmd->flow_type) { 2425 case TCP_V4_FLOW: 2426 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2427 /* fallthrough */ 2428 case UDP_V4_FLOW: 2429 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2430 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2431 /* fallthrough */ 2432 case SCTP_V4_FLOW: 2433 case AH_ESP_V4_FLOW: 2434 case AH_V4_FLOW: 2435 case ESP_V4_FLOW: 2436 case IPV4_FLOW: 2437 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2438 break; 2439 case TCP_V6_FLOW: 2440 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2441 /* fallthrough */ 2442 case UDP_V6_FLOW: 2443 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2444 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2445 /* fallthrough */ 2446 case SCTP_V6_FLOW: 2447 case AH_ESP_V6_FLOW: 2448 case AH_V6_FLOW: 2449 case ESP_V6_FLOW: 2450 case IPV6_FLOW: 2451 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2452 break; 2453 default: 2454 return -EINVAL; 2455 } 2456 2457 return 0; 2458 } 2459 2460 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2461 u32 *rule_locs) 2462 { 2463 struct ixgbe_adapter *adapter = netdev_priv(dev); 2464 int ret = -EOPNOTSUPP; 2465 2466 switch (cmd->cmd) { 2467 case ETHTOOL_GRXRINGS: 2468 cmd->data = adapter->num_rx_queues; 2469 ret = 0; 2470 break; 2471 case ETHTOOL_GRXCLSRLCNT: 2472 cmd->rule_cnt = adapter->fdir_filter_count; 2473 ret = 0; 2474 break; 2475 case ETHTOOL_GRXCLSRULE: 2476 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2477 break; 2478 case ETHTOOL_GRXCLSRLALL: 2479 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2480 break; 2481 case ETHTOOL_GRXFH: 2482 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2483 break; 2484 default: 2485 break; 2486 } 2487 2488 return ret; 2489 } 2490 2491 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2492 struct ixgbe_fdir_filter *input, 2493 u16 sw_idx) 2494 { 2495 struct ixgbe_hw *hw = &adapter->hw; 2496 struct hlist_node *node2; 2497 struct ixgbe_fdir_filter *rule, *parent; 2498 int err = -EINVAL; 2499 2500 parent = NULL; 2501 rule = NULL; 2502 2503 hlist_for_each_entry_safe(rule, node2, 2504 &adapter->fdir_filter_list, fdir_node) { 2505 /* hash found, or no matching entry */ 2506 if (rule->sw_idx >= sw_idx) 2507 break; 2508 parent = rule; 2509 } 2510 2511 /* if there is an old rule occupying our place remove it */ 2512 if (rule && (rule->sw_idx == sw_idx)) { 2513 if (!input || (rule->filter.formatted.bkt_hash != 2514 input->filter.formatted.bkt_hash)) { 2515 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2516 &rule->filter, 2517 sw_idx); 2518 } 2519 2520 hlist_del(&rule->fdir_node); 2521 kfree(rule); 2522 adapter->fdir_filter_count--; 2523 } 2524 2525 /* 2526 * If no input this was a delete, err should be 0 if a rule was 2527 * successfully found and removed from the list else -EINVAL 2528 */ 2529 if (!input) 2530 return err; 2531 2532 /* initialize node and set software index */ 2533 INIT_HLIST_NODE(&input->fdir_node); 2534 2535 /* add filter to the list */ 2536 if (parent) 2537 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2538 else 2539 hlist_add_head(&input->fdir_node, 2540 &adapter->fdir_filter_list); 2541 2542 /* update counts */ 2543 adapter->fdir_filter_count++; 2544 2545 return 0; 2546 } 2547 2548 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2549 u8 *flow_type) 2550 { 2551 switch (fsp->flow_type & ~FLOW_EXT) { 2552 case TCP_V4_FLOW: 2553 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2554 break; 2555 case UDP_V4_FLOW: 2556 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2557 break; 2558 case SCTP_V4_FLOW: 2559 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2560 break; 2561 case IP_USER_FLOW: 2562 switch (fsp->h_u.usr_ip4_spec.proto) { 2563 case IPPROTO_TCP: 2564 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2565 break; 2566 case IPPROTO_UDP: 2567 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2568 break; 2569 case IPPROTO_SCTP: 2570 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2571 break; 2572 case 0: 2573 if (!fsp->m_u.usr_ip4_spec.proto) { 2574 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2575 break; 2576 } 2577 default: 2578 return 0; 2579 } 2580 break; 2581 default: 2582 return 0; 2583 } 2584 2585 return 1; 2586 } 2587 2588 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2589 struct ethtool_rxnfc *cmd) 2590 { 2591 struct ethtool_rx_flow_spec *fsp = 2592 (struct ethtool_rx_flow_spec *)&cmd->fs; 2593 struct ixgbe_hw *hw = &adapter->hw; 2594 struct ixgbe_fdir_filter *input; 2595 union ixgbe_atr_input mask; 2596 int err; 2597 2598 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2599 return -EOPNOTSUPP; 2600 2601 /* 2602 * Don't allow programming if the action is a queue greater than 2603 * the number of online Rx queues. 2604 */ 2605 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) && 2606 (fsp->ring_cookie >= adapter->num_rx_queues)) 2607 return -EINVAL; 2608 2609 /* Don't allow indexes to exist outside of available space */ 2610 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2611 e_err(drv, "Location out of range\n"); 2612 return -EINVAL; 2613 } 2614 2615 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2616 if (!input) 2617 return -ENOMEM; 2618 2619 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2620 2621 /* set SW index */ 2622 input->sw_idx = fsp->location; 2623 2624 /* record flow type */ 2625 if (!ixgbe_flowspec_to_flow_type(fsp, 2626 &input->filter.formatted.flow_type)) { 2627 e_err(drv, "Unrecognized flow type\n"); 2628 goto err_out; 2629 } 2630 2631 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2632 IXGBE_ATR_L4TYPE_MASK; 2633 2634 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2635 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2636 2637 /* Copy input into formatted structures */ 2638 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2639 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2640 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2641 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2642 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2643 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2644 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2645 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2646 2647 if (fsp->flow_type & FLOW_EXT) { 2648 input->filter.formatted.vm_pool = 2649 (unsigned char)ntohl(fsp->h_ext.data[1]); 2650 mask.formatted.vm_pool = 2651 (unsigned char)ntohl(fsp->m_ext.data[1]); 2652 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2653 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2654 input->filter.formatted.flex_bytes = 2655 fsp->h_ext.vlan_etype; 2656 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2657 } 2658 2659 /* determine if we need to drop or route the packet */ 2660 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2661 input->action = IXGBE_FDIR_DROP_QUEUE; 2662 else 2663 input->action = fsp->ring_cookie; 2664 2665 spin_lock(&adapter->fdir_perfect_lock); 2666 2667 if (hlist_empty(&adapter->fdir_filter_list)) { 2668 /* save mask and program input mask into HW */ 2669 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2670 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2671 if (err) { 2672 e_err(drv, "Error writing mask\n"); 2673 goto err_out_w_lock; 2674 } 2675 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2676 e_err(drv, "Only one mask supported per port\n"); 2677 goto err_out_w_lock; 2678 } 2679 2680 /* apply mask and compute/store hash */ 2681 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2682 2683 /* program filters to filter memory */ 2684 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2685 &input->filter, input->sw_idx, 2686 (input->action == IXGBE_FDIR_DROP_QUEUE) ? 2687 IXGBE_FDIR_DROP_QUEUE : 2688 adapter->rx_ring[input->action]->reg_idx); 2689 if (err) 2690 goto err_out_w_lock; 2691 2692 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2693 2694 spin_unlock(&adapter->fdir_perfect_lock); 2695 2696 return err; 2697 err_out_w_lock: 2698 spin_unlock(&adapter->fdir_perfect_lock); 2699 err_out: 2700 kfree(input); 2701 return -EINVAL; 2702 } 2703 2704 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2705 struct ethtool_rxnfc *cmd) 2706 { 2707 struct ethtool_rx_flow_spec *fsp = 2708 (struct ethtool_rx_flow_spec *)&cmd->fs; 2709 int err; 2710 2711 spin_lock(&adapter->fdir_perfect_lock); 2712 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2713 spin_unlock(&adapter->fdir_perfect_lock); 2714 2715 return err; 2716 } 2717 2718 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2719 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2720 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2721 struct ethtool_rxnfc *nfc) 2722 { 2723 u32 flags2 = adapter->flags2; 2724 2725 /* 2726 * RSS does not support anything other than hashing 2727 * to queues on src and dst IPs and ports 2728 */ 2729 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2730 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2731 return -EINVAL; 2732 2733 switch (nfc->flow_type) { 2734 case TCP_V4_FLOW: 2735 case TCP_V6_FLOW: 2736 if (!(nfc->data & RXH_IP_SRC) || 2737 !(nfc->data & RXH_IP_DST) || 2738 !(nfc->data & RXH_L4_B_0_1) || 2739 !(nfc->data & RXH_L4_B_2_3)) 2740 return -EINVAL; 2741 break; 2742 case UDP_V4_FLOW: 2743 if (!(nfc->data & RXH_IP_SRC) || 2744 !(nfc->data & RXH_IP_DST)) 2745 return -EINVAL; 2746 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2747 case 0: 2748 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2749 break; 2750 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2751 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2752 break; 2753 default: 2754 return -EINVAL; 2755 } 2756 break; 2757 case UDP_V6_FLOW: 2758 if (!(nfc->data & RXH_IP_SRC) || 2759 !(nfc->data & RXH_IP_DST)) 2760 return -EINVAL; 2761 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2762 case 0: 2763 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2764 break; 2765 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2766 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2767 break; 2768 default: 2769 return -EINVAL; 2770 } 2771 break; 2772 case AH_ESP_V4_FLOW: 2773 case AH_V4_FLOW: 2774 case ESP_V4_FLOW: 2775 case SCTP_V4_FLOW: 2776 case AH_ESP_V6_FLOW: 2777 case AH_V6_FLOW: 2778 case ESP_V6_FLOW: 2779 case SCTP_V6_FLOW: 2780 if (!(nfc->data & RXH_IP_SRC) || 2781 !(nfc->data & RXH_IP_DST) || 2782 (nfc->data & RXH_L4_B_0_1) || 2783 (nfc->data & RXH_L4_B_2_3)) 2784 return -EINVAL; 2785 break; 2786 default: 2787 return -EINVAL; 2788 } 2789 2790 /* if we changed something we need to update flags */ 2791 if (flags2 != adapter->flags2) { 2792 struct ixgbe_hw *hw = &adapter->hw; 2793 u32 mrqc; 2794 unsigned int pf_pool = adapter->num_vfs; 2795 2796 if ((hw->mac.type >= ixgbe_mac_X550) && 2797 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2798 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 2799 else 2800 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2801 2802 if ((flags2 & UDP_RSS_FLAGS) && 2803 !(adapter->flags2 & UDP_RSS_FLAGS)) 2804 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2805 2806 adapter->flags2 = flags2; 2807 2808 /* Perform hash on these packet types */ 2809 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 2810 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 2811 | IXGBE_MRQC_RSS_FIELD_IPV6 2812 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 2813 2814 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2815 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 2816 2817 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2818 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 2819 2820 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2821 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 2822 2823 if ((hw->mac.type >= ixgbe_mac_X550) && 2824 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2825 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 2826 else 2827 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2828 } 2829 2830 return 0; 2831 } 2832 2833 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2834 { 2835 struct ixgbe_adapter *adapter = netdev_priv(dev); 2836 int ret = -EOPNOTSUPP; 2837 2838 switch (cmd->cmd) { 2839 case ETHTOOL_SRXCLSRLINS: 2840 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2841 break; 2842 case ETHTOOL_SRXCLSRLDEL: 2843 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2844 break; 2845 case ETHTOOL_SRXFH: 2846 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 2847 break; 2848 default: 2849 break; 2850 } 2851 2852 return ret; 2853 } 2854 2855 static int ixgbe_get_ts_info(struct net_device *dev, 2856 struct ethtool_ts_info *info) 2857 { 2858 struct ixgbe_adapter *adapter = netdev_priv(dev); 2859 2860 switch (adapter->hw.mac.type) { 2861 case ixgbe_mac_X550: 2862 case ixgbe_mac_X550EM_x: 2863 case ixgbe_mac_X540: 2864 case ixgbe_mac_82599EB: 2865 info->so_timestamping = 2866 SOF_TIMESTAMPING_TX_SOFTWARE | 2867 SOF_TIMESTAMPING_RX_SOFTWARE | 2868 SOF_TIMESTAMPING_SOFTWARE | 2869 SOF_TIMESTAMPING_TX_HARDWARE | 2870 SOF_TIMESTAMPING_RX_HARDWARE | 2871 SOF_TIMESTAMPING_RAW_HARDWARE; 2872 2873 if (adapter->ptp_clock) 2874 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2875 else 2876 info->phc_index = -1; 2877 2878 info->tx_types = 2879 (1 << HWTSTAMP_TX_OFF) | 2880 (1 << HWTSTAMP_TX_ON); 2881 2882 info->rx_filters = 2883 (1 << HWTSTAMP_FILTER_NONE) | 2884 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2885 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2886 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 2887 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 2888 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 2889 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 2890 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 2891 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 2892 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 2893 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 2894 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2895 break; 2896 default: 2897 return ethtool_op_get_ts_info(dev, info); 2898 } 2899 return 0; 2900 } 2901 2902 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 2903 { 2904 unsigned int max_combined; 2905 u8 tcs = netdev_get_num_tc(adapter->netdev); 2906 2907 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2908 /* We only support one q_vector without MSI-X */ 2909 max_combined = 1; 2910 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2911 /* SR-IOV currently only allows one queue on the PF */ 2912 max_combined = 1; 2913 } else if (tcs > 1) { 2914 /* For DCB report channels per traffic class */ 2915 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 2916 /* 8 TC w/ 4 queues per TC */ 2917 max_combined = 4; 2918 } else if (tcs > 4) { 2919 /* 8 TC w/ 8 queues per TC */ 2920 max_combined = 8; 2921 } else { 2922 /* 4 TC w/ 16 queues per TC */ 2923 max_combined = 16; 2924 } 2925 } else if (adapter->atr_sample_rate) { 2926 /* support up to 64 queues with ATR */ 2927 max_combined = IXGBE_MAX_FDIR_INDICES; 2928 } else { 2929 /* support up to 16 queues with RSS */ 2930 max_combined = ixgbe_max_rss_indices(adapter); 2931 } 2932 2933 return max_combined; 2934 } 2935 2936 static void ixgbe_get_channels(struct net_device *dev, 2937 struct ethtool_channels *ch) 2938 { 2939 struct ixgbe_adapter *adapter = netdev_priv(dev); 2940 2941 /* report maximum channels */ 2942 ch->max_combined = ixgbe_max_channels(adapter); 2943 2944 /* report info for other vector */ 2945 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2946 ch->max_other = NON_Q_VECTORS; 2947 ch->other_count = NON_Q_VECTORS; 2948 } 2949 2950 /* record RSS queues */ 2951 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 2952 2953 /* nothing else to report if RSS is disabled */ 2954 if (ch->combined_count == 1) 2955 return; 2956 2957 /* we do not support ATR queueing if SR-IOV is enabled */ 2958 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 2959 return; 2960 2961 /* same thing goes for being DCB enabled */ 2962 if (netdev_get_num_tc(dev) > 1) 2963 return; 2964 2965 /* if ATR is disabled we can exit */ 2966 if (!adapter->atr_sample_rate) 2967 return; 2968 2969 /* report flow director queues as maximum channels */ 2970 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 2971 } 2972 2973 static int ixgbe_set_channels(struct net_device *dev, 2974 struct ethtool_channels *ch) 2975 { 2976 struct ixgbe_adapter *adapter = netdev_priv(dev); 2977 unsigned int count = ch->combined_count; 2978 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 2979 2980 /* verify they are not requesting separate vectors */ 2981 if (!count || ch->rx_count || ch->tx_count) 2982 return -EINVAL; 2983 2984 /* verify other_count has not changed */ 2985 if (ch->other_count != NON_Q_VECTORS) 2986 return -EINVAL; 2987 2988 /* verify the number of channels does not exceed hardware limits */ 2989 if (count > ixgbe_max_channels(adapter)) 2990 return -EINVAL; 2991 2992 /* update feature limits from largest to smallest supported values */ 2993 adapter->ring_feature[RING_F_FDIR].limit = count; 2994 2995 /* cap RSS limit */ 2996 if (count > max_rss_indices) 2997 count = max_rss_indices; 2998 adapter->ring_feature[RING_F_RSS].limit = count; 2999 3000 #ifdef IXGBE_FCOE 3001 /* cap FCoE limit at 8 */ 3002 if (count > IXGBE_FCRETA_SIZE) 3003 count = IXGBE_FCRETA_SIZE; 3004 adapter->ring_feature[RING_F_FCOE].limit = count; 3005 3006 #endif 3007 /* use setup TC to update any traffic class queue mapping */ 3008 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 3009 } 3010 3011 static int ixgbe_get_module_info(struct net_device *dev, 3012 struct ethtool_modinfo *modinfo) 3013 { 3014 struct ixgbe_adapter *adapter = netdev_priv(dev); 3015 struct ixgbe_hw *hw = &adapter->hw; 3016 u32 status; 3017 u8 sff8472_rev, addr_mode; 3018 bool page_swap = false; 3019 3020 /* Check whether we support SFF-8472 or not */ 3021 status = hw->phy.ops.read_i2c_eeprom(hw, 3022 IXGBE_SFF_SFF_8472_COMP, 3023 &sff8472_rev); 3024 if (status != 0) 3025 return -EIO; 3026 3027 /* addressing mode is not supported */ 3028 status = hw->phy.ops.read_i2c_eeprom(hw, 3029 IXGBE_SFF_SFF_8472_SWAP, 3030 &addr_mode); 3031 if (status != 0) 3032 return -EIO; 3033 3034 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3035 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3036 page_swap = true; 3037 } 3038 3039 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 3040 /* We have a SFP, but it does not support SFF-8472 */ 3041 modinfo->type = ETH_MODULE_SFF_8079; 3042 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3043 } else { 3044 /* We have a SFP which supports a revision of SFF-8472. */ 3045 modinfo->type = ETH_MODULE_SFF_8472; 3046 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3047 } 3048 3049 return 0; 3050 } 3051 3052 static int ixgbe_get_module_eeprom(struct net_device *dev, 3053 struct ethtool_eeprom *ee, 3054 u8 *data) 3055 { 3056 struct ixgbe_adapter *adapter = netdev_priv(dev); 3057 struct ixgbe_hw *hw = &adapter->hw; 3058 u32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3059 u8 databyte = 0xFF; 3060 int i = 0; 3061 3062 if (ee->len == 0) 3063 return -EINVAL; 3064 3065 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3066 /* I2C reads can take long time */ 3067 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3068 return -EBUSY; 3069 3070 if (i < ETH_MODULE_SFF_8079_LEN) 3071 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3072 else 3073 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3074 3075 if (status != 0) 3076 return -EIO; 3077 3078 data[i - ee->offset] = databyte; 3079 } 3080 3081 return 0; 3082 } 3083 3084 static const struct ethtool_ops ixgbe_ethtool_ops = { 3085 .get_settings = ixgbe_get_settings, 3086 .set_settings = ixgbe_set_settings, 3087 .get_drvinfo = ixgbe_get_drvinfo, 3088 .get_regs_len = ixgbe_get_regs_len, 3089 .get_regs = ixgbe_get_regs, 3090 .get_wol = ixgbe_get_wol, 3091 .set_wol = ixgbe_set_wol, 3092 .nway_reset = ixgbe_nway_reset, 3093 .get_link = ethtool_op_get_link, 3094 .get_eeprom_len = ixgbe_get_eeprom_len, 3095 .get_eeprom = ixgbe_get_eeprom, 3096 .set_eeprom = ixgbe_set_eeprom, 3097 .get_ringparam = ixgbe_get_ringparam, 3098 .set_ringparam = ixgbe_set_ringparam, 3099 .get_pauseparam = ixgbe_get_pauseparam, 3100 .set_pauseparam = ixgbe_set_pauseparam, 3101 .get_msglevel = ixgbe_get_msglevel, 3102 .set_msglevel = ixgbe_set_msglevel, 3103 .self_test = ixgbe_diag_test, 3104 .get_strings = ixgbe_get_strings, 3105 .set_phys_id = ixgbe_set_phys_id, 3106 .get_sset_count = ixgbe_get_sset_count, 3107 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3108 .get_coalesce = ixgbe_get_coalesce, 3109 .set_coalesce = ixgbe_set_coalesce, 3110 .get_rxnfc = ixgbe_get_rxnfc, 3111 .set_rxnfc = ixgbe_set_rxnfc, 3112 .get_channels = ixgbe_get_channels, 3113 .set_channels = ixgbe_set_channels, 3114 .get_ts_info = ixgbe_get_ts_info, 3115 .get_module_info = ixgbe_get_module_info, 3116 .get_module_eeprom = ixgbe_get_module_eeprom, 3117 }; 3118 3119 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3120 { 3121 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3122 } 3123