1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 /* ethtool support for ixgbe */ 29 30 #include <linux/interrupt.h> 31 #include <linux/types.h> 32 #include <linux/module.h> 33 #include <linux/slab.h> 34 #include <linux/pci.h> 35 #include <linux/netdevice.h> 36 #include <linux/ethtool.h> 37 #include <linux/vmalloc.h> 38 #include <linux/highmem.h> 39 #include <linux/uaccess.h> 40 41 #include "ixgbe.h" 42 #include "ixgbe_phy.h" 43 44 45 #define IXGBE_ALL_RAR_ENTRIES 16 46 47 enum {NETDEV_STATS, IXGBE_STATS}; 48 49 struct ixgbe_stats { 50 char stat_string[ETH_GSTRING_LEN]; 51 int type; 52 int sizeof_stat; 53 int stat_offset; 54 }; 55 56 #define IXGBE_STAT(m) IXGBE_STATS, \ 57 sizeof(((struct ixgbe_adapter *)0)->m), \ 58 offsetof(struct ixgbe_adapter, m) 59 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 60 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 61 offsetof(struct rtnl_link_stats64, m) 62 63 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 64 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 65 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 66 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 67 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 68 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 69 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 70 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 71 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 72 {"lsc_int", IXGBE_STAT(lsc_int)}, 73 {"tx_busy", IXGBE_STAT(tx_busy)}, 74 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 75 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 76 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 77 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 78 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 79 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 80 {"broadcast", IXGBE_STAT(stats.bprc)}, 81 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 82 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 83 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 84 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 85 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 86 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 87 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 88 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 89 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 90 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 91 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 92 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 93 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 94 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 95 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 96 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 97 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 98 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 99 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 100 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 101 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 102 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 103 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 104 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 105 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 106 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 107 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 108 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 109 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 110 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 111 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 112 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 113 #ifdef IXGBE_FCOE 114 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 115 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 116 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 117 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 118 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 119 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 120 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 121 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 122 #endif /* IXGBE_FCOE */ 123 }; 124 125 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 126 * we set the num_rx_queues to evaluate to num_tx_queues. This is 127 * used because we do not have a good way to get the max number of 128 * rx queues with CONFIG_RPS disabled. 129 */ 130 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 131 132 #define IXGBE_QUEUE_STATS_LEN ( \ 133 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 134 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 135 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 136 #define IXGBE_PB_STATS_LEN ( \ 137 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 138 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 139 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 140 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 141 / sizeof(u64)) 142 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 143 IXGBE_PB_STATS_LEN + \ 144 IXGBE_QUEUE_STATS_LEN) 145 146 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 147 "Register test (offline)", "Eeprom test (offline)", 148 "Interrupt test (offline)", "Loopback test (offline)", 149 "Link test (on/offline)" 150 }; 151 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 152 153 static int ixgbe_get_settings(struct net_device *netdev, 154 struct ethtool_cmd *ecmd) 155 { 156 struct ixgbe_adapter *adapter = netdev_priv(netdev); 157 struct ixgbe_hw *hw = &adapter->hw; 158 ixgbe_link_speed supported_link; 159 u32 link_speed = 0; 160 bool autoneg = false; 161 bool link_up; 162 163 /* SFP type is needed for get_link_capabilities */ 164 if (hw->phy.media_type & (ixgbe_media_type_fiber | 165 ixgbe_media_type_fiber_qsfp)) { 166 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 167 hw->phy.ops.identify_sfp(hw); 168 } 169 170 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 171 172 /* set the supported link speeds */ 173 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 174 ecmd->supported |= SUPPORTED_10000baseT_Full; 175 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 176 ecmd->supported |= SUPPORTED_1000baseT_Full; 177 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 178 ecmd->supported |= SUPPORTED_100baseT_Full; 179 180 /* set the advertised speeds */ 181 if (hw->phy.autoneg_advertised) { 182 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 183 ecmd->advertising |= ADVERTISED_100baseT_Full; 184 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 185 ecmd->advertising |= ADVERTISED_10000baseT_Full; 186 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 187 ecmd->advertising |= ADVERTISED_1000baseT_Full; 188 } else { 189 /* default modes in case phy.autoneg_advertised isn't set */ 190 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 191 ecmd->advertising |= ADVERTISED_10000baseT_Full; 192 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 193 ecmd->advertising |= ADVERTISED_1000baseT_Full; 194 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 195 ecmd->advertising |= ADVERTISED_100baseT_Full; 196 197 if (hw->phy.multispeed_fiber && !autoneg) { 198 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 199 ecmd->advertising = ADVERTISED_10000baseT_Full; 200 } 201 } 202 203 if (autoneg) { 204 ecmd->supported |= SUPPORTED_Autoneg; 205 ecmd->advertising |= ADVERTISED_Autoneg; 206 ecmd->autoneg = AUTONEG_ENABLE; 207 } else 208 ecmd->autoneg = AUTONEG_DISABLE; 209 210 ecmd->transceiver = XCVR_EXTERNAL; 211 212 /* Determine the remaining settings based on the PHY type. */ 213 switch (adapter->hw.phy.type) { 214 case ixgbe_phy_tn: 215 case ixgbe_phy_aq: 216 case ixgbe_phy_cu_unknown: 217 ecmd->supported |= SUPPORTED_TP; 218 ecmd->advertising |= ADVERTISED_TP; 219 ecmd->port = PORT_TP; 220 break; 221 case ixgbe_phy_qt: 222 ecmd->supported |= SUPPORTED_FIBRE; 223 ecmd->advertising |= ADVERTISED_FIBRE; 224 ecmd->port = PORT_FIBRE; 225 break; 226 case ixgbe_phy_nl: 227 case ixgbe_phy_sfp_passive_tyco: 228 case ixgbe_phy_sfp_passive_unknown: 229 case ixgbe_phy_sfp_ftl: 230 case ixgbe_phy_sfp_avago: 231 case ixgbe_phy_sfp_intel: 232 case ixgbe_phy_sfp_unknown: 233 /* SFP+ devices, further checking needed */ 234 switch (adapter->hw.phy.sfp_type) { 235 case ixgbe_sfp_type_da_cu: 236 case ixgbe_sfp_type_da_cu_core0: 237 case ixgbe_sfp_type_da_cu_core1: 238 ecmd->supported |= SUPPORTED_FIBRE; 239 ecmd->advertising |= ADVERTISED_FIBRE; 240 ecmd->port = PORT_DA; 241 break; 242 case ixgbe_sfp_type_sr: 243 case ixgbe_sfp_type_lr: 244 case ixgbe_sfp_type_srlr_core0: 245 case ixgbe_sfp_type_srlr_core1: 246 case ixgbe_sfp_type_1g_sx_core0: 247 case ixgbe_sfp_type_1g_sx_core1: 248 case ixgbe_sfp_type_1g_lx_core0: 249 case ixgbe_sfp_type_1g_lx_core1: 250 ecmd->supported |= SUPPORTED_FIBRE; 251 ecmd->advertising |= ADVERTISED_FIBRE; 252 ecmd->port = PORT_FIBRE; 253 break; 254 case ixgbe_sfp_type_not_present: 255 ecmd->supported |= SUPPORTED_FIBRE; 256 ecmd->advertising |= ADVERTISED_FIBRE; 257 ecmd->port = PORT_NONE; 258 break; 259 case ixgbe_sfp_type_1g_cu_core0: 260 case ixgbe_sfp_type_1g_cu_core1: 261 ecmd->supported |= SUPPORTED_TP; 262 ecmd->advertising |= ADVERTISED_TP; 263 ecmd->port = PORT_TP; 264 break; 265 case ixgbe_sfp_type_unknown: 266 default: 267 ecmd->supported |= SUPPORTED_FIBRE; 268 ecmd->advertising |= ADVERTISED_FIBRE; 269 ecmd->port = PORT_OTHER; 270 break; 271 } 272 break; 273 case ixgbe_phy_xaui: 274 ecmd->supported |= SUPPORTED_FIBRE; 275 ecmd->advertising |= ADVERTISED_FIBRE; 276 ecmd->port = PORT_NONE; 277 break; 278 case ixgbe_phy_unknown: 279 case ixgbe_phy_generic: 280 case ixgbe_phy_sfp_unsupported: 281 default: 282 ecmd->supported |= SUPPORTED_FIBRE; 283 ecmd->advertising |= ADVERTISED_FIBRE; 284 ecmd->port = PORT_OTHER; 285 break; 286 } 287 288 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 289 if (link_up) { 290 switch (link_speed) { 291 case IXGBE_LINK_SPEED_10GB_FULL: 292 ethtool_cmd_speed_set(ecmd, SPEED_10000); 293 break; 294 case IXGBE_LINK_SPEED_1GB_FULL: 295 ethtool_cmd_speed_set(ecmd, SPEED_1000); 296 break; 297 case IXGBE_LINK_SPEED_100_FULL: 298 ethtool_cmd_speed_set(ecmd, SPEED_100); 299 break; 300 default: 301 break; 302 } 303 ecmd->duplex = DUPLEX_FULL; 304 } else { 305 ethtool_cmd_speed_set(ecmd, -1); 306 ecmd->duplex = -1; 307 } 308 309 return 0; 310 } 311 312 static int ixgbe_set_settings(struct net_device *netdev, 313 struct ethtool_cmd *ecmd) 314 { 315 struct ixgbe_adapter *adapter = netdev_priv(netdev); 316 struct ixgbe_hw *hw = &adapter->hw; 317 u32 advertised, old; 318 s32 err = 0; 319 320 if ((hw->phy.media_type == ixgbe_media_type_copper) || 321 (hw->phy.multispeed_fiber)) { 322 /* 323 * this function does not support duplex forcing, but can 324 * limit the advertising of the adapter to the specified speed 325 */ 326 if (ecmd->advertising & ~ecmd->supported) 327 return -EINVAL; 328 329 /* only allow one speed at a time if no autoneg */ 330 if (!ecmd->autoneg && hw->phy.multispeed_fiber) { 331 if (ecmd->advertising == 332 (ADVERTISED_10000baseT_Full | 333 ADVERTISED_1000baseT_Full)) 334 return -EINVAL; 335 } 336 337 old = hw->phy.autoneg_advertised; 338 advertised = 0; 339 if (ecmd->advertising & ADVERTISED_10000baseT_Full) 340 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 341 342 if (ecmd->advertising & ADVERTISED_1000baseT_Full) 343 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 344 345 if (ecmd->advertising & ADVERTISED_100baseT_Full) 346 advertised |= IXGBE_LINK_SPEED_100_FULL; 347 348 if (old == advertised) 349 return err; 350 /* this sets the link speed and restarts auto-neg */ 351 hw->mac.autotry_restart = true; 352 err = hw->mac.ops.setup_link(hw, advertised, true); 353 if (err) { 354 e_info(probe, "setup link failed with code %d\n", err); 355 hw->mac.ops.setup_link(hw, old, true); 356 } 357 } else { 358 /* in this case we currently only support 10Gb/FULL */ 359 u32 speed = ethtool_cmd_speed(ecmd); 360 if ((ecmd->autoneg == AUTONEG_ENABLE) || 361 (ecmd->advertising != ADVERTISED_10000baseT_Full) || 362 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) 363 return -EINVAL; 364 } 365 366 return err; 367 } 368 369 static void ixgbe_get_pauseparam(struct net_device *netdev, 370 struct ethtool_pauseparam *pause) 371 { 372 struct ixgbe_adapter *adapter = netdev_priv(netdev); 373 struct ixgbe_hw *hw = &adapter->hw; 374 375 if (ixgbe_device_supports_autoneg_fc(hw) && 376 !hw->fc.disable_fc_autoneg) 377 pause->autoneg = 1; 378 else 379 pause->autoneg = 0; 380 381 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 382 pause->rx_pause = 1; 383 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 384 pause->tx_pause = 1; 385 } else if (hw->fc.current_mode == ixgbe_fc_full) { 386 pause->rx_pause = 1; 387 pause->tx_pause = 1; 388 } 389 } 390 391 static int ixgbe_set_pauseparam(struct net_device *netdev, 392 struct ethtool_pauseparam *pause) 393 { 394 struct ixgbe_adapter *adapter = netdev_priv(netdev); 395 struct ixgbe_hw *hw = &adapter->hw; 396 struct ixgbe_fc_info fc = hw->fc; 397 398 /* 82598 does no support link flow control with DCB enabled */ 399 if ((hw->mac.type == ixgbe_mac_82598EB) && 400 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 401 return -EINVAL; 402 403 /* some devices do not support autoneg of link flow control */ 404 if ((pause->autoneg == AUTONEG_ENABLE) && 405 !ixgbe_device_supports_autoneg_fc(hw)) 406 return -EINVAL; 407 408 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 409 410 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 411 fc.requested_mode = ixgbe_fc_full; 412 else if (pause->rx_pause && !pause->tx_pause) 413 fc.requested_mode = ixgbe_fc_rx_pause; 414 else if (!pause->rx_pause && pause->tx_pause) 415 fc.requested_mode = ixgbe_fc_tx_pause; 416 else 417 fc.requested_mode = ixgbe_fc_none; 418 419 /* if the thing changed then we'll update and use new autoneg */ 420 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 421 hw->fc = fc; 422 if (netif_running(netdev)) 423 ixgbe_reinit_locked(adapter); 424 else 425 ixgbe_reset(adapter); 426 } 427 428 return 0; 429 } 430 431 static u32 ixgbe_get_msglevel(struct net_device *netdev) 432 { 433 struct ixgbe_adapter *adapter = netdev_priv(netdev); 434 return adapter->msg_enable; 435 } 436 437 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 438 { 439 struct ixgbe_adapter *adapter = netdev_priv(netdev); 440 adapter->msg_enable = data; 441 } 442 443 static int ixgbe_get_regs_len(struct net_device *netdev) 444 { 445 #define IXGBE_REGS_LEN 1139 446 return IXGBE_REGS_LEN * sizeof(u32); 447 } 448 449 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 450 451 static void ixgbe_get_regs(struct net_device *netdev, 452 struct ethtool_regs *regs, void *p) 453 { 454 struct ixgbe_adapter *adapter = netdev_priv(netdev); 455 struct ixgbe_hw *hw = &adapter->hw; 456 u32 *regs_buff = p; 457 u8 i; 458 459 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 460 461 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 462 hw->device_id; 463 464 /* General Registers */ 465 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 466 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 467 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 468 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 469 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 470 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 471 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 472 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 473 474 /* NVM Register */ 475 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC); 476 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 477 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA); 478 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 479 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 480 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 481 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 482 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 483 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 484 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC); 485 486 /* Interrupt */ 487 /* don't read EICR because it can clear interrupt causes, instead 488 * read EICS which is a shadow but doesn't clear EICR */ 489 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 490 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 491 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 492 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 493 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 494 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 495 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 496 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 497 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 498 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 499 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 500 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 501 502 /* Flow Control */ 503 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 504 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); 505 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); 506 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); 507 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); 508 for (i = 0; i < 8; i++) { 509 switch (hw->mac.type) { 510 case ixgbe_mac_82598EB: 511 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 512 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 513 break; 514 case ixgbe_mac_82599EB: 515 case ixgbe_mac_X540: 516 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 517 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 518 break; 519 default: 520 break; 521 } 522 } 523 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 524 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 525 526 /* Receive DMA */ 527 for (i = 0; i < 64; i++) 528 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 529 for (i = 0; i < 64; i++) 530 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 531 for (i = 0; i < 64; i++) 532 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 533 for (i = 0; i < 64; i++) 534 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 535 for (i = 0; i < 64; i++) 536 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 537 for (i = 0; i < 64; i++) 538 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 539 for (i = 0; i < 16; i++) 540 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 541 for (i = 0; i < 16; i++) 542 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 543 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 544 for (i = 0; i < 8; i++) 545 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 546 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 547 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 548 549 /* Receive */ 550 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 551 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 552 for (i = 0; i < 16; i++) 553 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 554 for (i = 0; i < 16; i++) 555 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 556 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 557 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 558 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 559 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 560 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 561 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 562 for (i = 0; i < 8; i++) 563 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 564 for (i = 0; i < 8; i++) 565 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 566 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 567 568 /* Transmit */ 569 for (i = 0; i < 32; i++) 570 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 571 for (i = 0; i < 32; i++) 572 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 573 for (i = 0; i < 32; i++) 574 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 575 for (i = 0; i < 32; i++) 576 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 577 for (i = 0; i < 32; i++) 578 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 579 for (i = 0; i < 32; i++) 580 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 581 for (i = 0; i < 32; i++) 582 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 583 for (i = 0; i < 32; i++) 584 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 585 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 586 for (i = 0; i < 16; i++) 587 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 588 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 589 for (i = 0; i < 8; i++) 590 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 591 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 592 593 /* Wake Up */ 594 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 595 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 596 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 597 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 598 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 599 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 600 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 601 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 602 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 603 604 /* DCB */ 605 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 606 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 607 608 switch (hw->mac.type) { 609 case ixgbe_mac_82598EB: 610 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 611 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 612 for (i = 0; i < 8; i++) 613 regs_buff[833 + i] = 614 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 615 for (i = 0; i < 8; i++) 616 regs_buff[841 + i] = 617 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 618 for (i = 0; i < 8; i++) 619 regs_buff[849 + i] = 620 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 621 for (i = 0; i < 8; i++) 622 regs_buff[857 + i] = 623 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 624 break; 625 case ixgbe_mac_82599EB: 626 case ixgbe_mac_X540: 627 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 628 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 629 for (i = 0; i < 8; i++) 630 regs_buff[833 + i] = 631 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 632 for (i = 0; i < 8; i++) 633 regs_buff[841 + i] = 634 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 635 for (i = 0; i < 8; i++) 636 regs_buff[849 + i] = 637 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 638 for (i = 0; i < 8; i++) 639 regs_buff[857 + i] = 640 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 641 break; 642 default: 643 break; 644 } 645 646 for (i = 0; i < 8; i++) 647 regs_buff[865 + i] = 648 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 649 for (i = 0; i < 8; i++) 650 regs_buff[873 + i] = 651 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 652 653 /* Statistics */ 654 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 655 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 656 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 657 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 658 for (i = 0; i < 8; i++) 659 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 660 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 661 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 662 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 663 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 664 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 665 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 666 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 667 for (i = 0; i < 8; i++) 668 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 669 for (i = 0; i < 8; i++) 670 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 671 for (i = 0; i < 8; i++) 672 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 673 for (i = 0; i < 8; i++) 674 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 675 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 676 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 677 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 678 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 679 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 680 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 681 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 682 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 683 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 684 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 685 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc); 686 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc); 687 for (i = 0; i < 8; i++) 688 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 689 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 690 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 691 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 692 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 693 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 694 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 695 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 696 regs_buff[961] = IXGBE_GET_STAT(adapter, tor); 697 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 698 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 699 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 700 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 701 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 702 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 703 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 704 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 705 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 706 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 707 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 708 for (i = 0; i < 16; i++) 709 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 710 for (i = 0; i < 16; i++) 711 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 712 for (i = 0; i < 16; i++) 713 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 714 for (i = 0; i < 16; i++) 715 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 716 717 /* MAC */ 718 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 719 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 720 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 721 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 722 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 723 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 724 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 725 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 726 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 727 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 728 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 729 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 730 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 731 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 732 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 733 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 734 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 735 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 736 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 737 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 738 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 739 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 740 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 741 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 742 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 743 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 744 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 745 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 746 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 747 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 748 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 749 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 750 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 751 752 /* Diagnostic */ 753 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 754 for (i = 0; i < 8; i++) 755 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 756 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 757 for (i = 0; i < 4; i++) 758 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 759 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 760 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 761 for (i = 0; i < 8; i++) 762 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 763 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 764 for (i = 0; i < 4; i++) 765 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 766 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 767 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 768 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); 769 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); 770 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); 771 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); 772 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 773 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); 774 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); 775 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); 776 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); 777 for (i = 0; i < 8; i++) 778 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 779 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 780 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 781 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 782 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 783 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 784 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 785 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 786 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 787 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 788 789 /* 82599 X540 specific registers */ 790 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 791 792 /* 82599 X540 specific DCB registers */ 793 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 794 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 795 for (i = 0; i < 4; i++) 796 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 797 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 798 /* same as RTTQCNRM */ 799 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 800 /* same as RTTQCNRR */ 801 802 /* X540 specific DCB registers */ 803 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 804 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 805 } 806 807 static int ixgbe_get_eeprom_len(struct net_device *netdev) 808 { 809 struct ixgbe_adapter *adapter = netdev_priv(netdev); 810 return adapter->hw.eeprom.word_size * 2; 811 } 812 813 static int ixgbe_get_eeprom(struct net_device *netdev, 814 struct ethtool_eeprom *eeprom, u8 *bytes) 815 { 816 struct ixgbe_adapter *adapter = netdev_priv(netdev); 817 struct ixgbe_hw *hw = &adapter->hw; 818 u16 *eeprom_buff; 819 int first_word, last_word, eeprom_len; 820 int ret_val = 0; 821 u16 i; 822 823 if (eeprom->len == 0) 824 return -EINVAL; 825 826 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 827 828 first_word = eeprom->offset >> 1; 829 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 830 eeprom_len = last_word - first_word + 1; 831 832 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); 833 if (!eeprom_buff) 834 return -ENOMEM; 835 836 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 837 eeprom_buff); 838 839 /* Device's eeprom is always little-endian, word addressable */ 840 for (i = 0; i < eeprom_len; i++) 841 le16_to_cpus(&eeprom_buff[i]); 842 843 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 844 kfree(eeprom_buff); 845 846 return ret_val; 847 } 848 849 static int ixgbe_set_eeprom(struct net_device *netdev, 850 struct ethtool_eeprom *eeprom, u8 *bytes) 851 { 852 struct ixgbe_adapter *adapter = netdev_priv(netdev); 853 struct ixgbe_hw *hw = &adapter->hw; 854 u16 *eeprom_buff; 855 void *ptr; 856 int max_len, first_word, last_word, ret_val = 0; 857 u16 i; 858 859 if (eeprom->len == 0) 860 return -EINVAL; 861 862 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 863 return -EINVAL; 864 865 max_len = hw->eeprom.word_size * 2; 866 867 first_word = eeprom->offset >> 1; 868 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 869 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 870 if (!eeprom_buff) 871 return -ENOMEM; 872 873 ptr = eeprom_buff; 874 875 if (eeprom->offset & 1) { 876 /* 877 * need read/modify/write of first changed EEPROM word 878 * only the second byte of the word is being modified 879 */ 880 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 881 if (ret_val) 882 goto err; 883 884 ptr++; 885 } 886 if ((eeprom->offset + eeprom->len) & 1) { 887 /* 888 * need read/modify/write of last changed EEPROM word 889 * only the first byte of the word is being modified 890 */ 891 ret_val = hw->eeprom.ops.read(hw, last_word, 892 &eeprom_buff[last_word - first_word]); 893 if (ret_val) 894 goto err; 895 } 896 897 /* Device's eeprom is always little-endian, word addressable */ 898 for (i = 0; i < last_word - first_word + 1; i++) 899 le16_to_cpus(&eeprom_buff[i]); 900 901 memcpy(ptr, bytes, eeprom->len); 902 903 for (i = 0; i < last_word - first_word + 1; i++) 904 cpu_to_le16s(&eeprom_buff[i]); 905 906 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 907 last_word - first_word + 1, 908 eeprom_buff); 909 910 /* Update the checksum */ 911 if (ret_val == 0) 912 hw->eeprom.ops.update_checksum(hw); 913 914 err: 915 kfree(eeprom_buff); 916 return ret_val; 917 } 918 919 static void ixgbe_get_drvinfo(struct net_device *netdev, 920 struct ethtool_drvinfo *drvinfo) 921 { 922 struct ixgbe_adapter *adapter = netdev_priv(netdev); 923 u32 nvm_track_id; 924 925 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 926 strlcpy(drvinfo->version, ixgbe_driver_version, 927 sizeof(drvinfo->version)); 928 929 nvm_track_id = (adapter->eeprom_verh << 16) | 930 adapter->eeprom_verl; 931 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x", 932 nvm_track_id); 933 934 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 935 sizeof(drvinfo->bus_info)); 936 drvinfo->n_stats = IXGBE_STATS_LEN; 937 drvinfo->testinfo_len = IXGBE_TEST_LEN; 938 drvinfo->regdump_len = ixgbe_get_regs_len(netdev); 939 } 940 941 static void ixgbe_get_ringparam(struct net_device *netdev, 942 struct ethtool_ringparam *ring) 943 { 944 struct ixgbe_adapter *adapter = netdev_priv(netdev); 945 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 946 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 947 948 ring->rx_max_pending = IXGBE_MAX_RXD; 949 ring->tx_max_pending = IXGBE_MAX_TXD; 950 ring->rx_pending = rx_ring->count; 951 ring->tx_pending = tx_ring->count; 952 } 953 954 static int ixgbe_set_ringparam(struct net_device *netdev, 955 struct ethtool_ringparam *ring) 956 { 957 struct ixgbe_adapter *adapter = netdev_priv(netdev); 958 struct ixgbe_ring *temp_ring; 959 int i, err = 0; 960 u32 new_rx_count, new_tx_count; 961 962 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 963 return -EINVAL; 964 965 new_tx_count = clamp_t(u32, ring->tx_pending, 966 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 967 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 968 969 new_rx_count = clamp_t(u32, ring->rx_pending, 970 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 971 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 972 973 if ((new_tx_count == adapter->tx_ring_count) && 974 (new_rx_count == adapter->rx_ring_count)) { 975 /* nothing to do */ 976 return 0; 977 } 978 979 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 980 usleep_range(1000, 2000); 981 982 if (!netif_running(adapter->netdev)) { 983 for (i = 0; i < adapter->num_tx_queues; i++) 984 adapter->tx_ring[i]->count = new_tx_count; 985 for (i = 0; i < adapter->num_rx_queues; i++) 986 adapter->rx_ring[i]->count = new_rx_count; 987 adapter->tx_ring_count = new_tx_count; 988 adapter->rx_ring_count = new_rx_count; 989 goto clear_reset; 990 } 991 992 /* allocate temporary buffer to store rings in */ 993 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues); 994 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring)); 995 996 if (!temp_ring) { 997 err = -ENOMEM; 998 goto clear_reset; 999 } 1000 1001 ixgbe_down(adapter); 1002 1003 /* 1004 * Setup new Tx resources and free the old Tx resources in that order. 1005 * We can then assign the new resources to the rings via a memcpy. 1006 * The advantage to this approach is that we are guaranteed to still 1007 * have resources even in the case of an allocation failure. 1008 */ 1009 if (new_tx_count != adapter->tx_ring_count) { 1010 for (i = 0; i < adapter->num_tx_queues; i++) { 1011 memcpy(&temp_ring[i], adapter->tx_ring[i], 1012 sizeof(struct ixgbe_ring)); 1013 1014 temp_ring[i].count = new_tx_count; 1015 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1016 if (err) { 1017 while (i) { 1018 i--; 1019 ixgbe_free_tx_resources(&temp_ring[i]); 1020 } 1021 goto err_setup; 1022 } 1023 } 1024 1025 for (i = 0; i < adapter->num_tx_queues; i++) { 1026 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1027 1028 memcpy(adapter->tx_ring[i], &temp_ring[i], 1029 sizeof(struct ixgbe_ring)); 1030 } 1031 1032 adapter->tx_ring_count = new_tx_count; 1033 } 1034 1035 /* Repeat the process for the Rx rings if needed */ 1036 if (new_rx_count != adapter->rx_ring_count) { 1037 for (i = 0; i < adapter->num_rx_queues; i++) { 1038 memcpy(&temp_ring[i], adapter->rx_ring[i], 1039 sizeof(struct ixgbe_ring)); 1040 1041 temp_ring[i].count = new_rx_count; 1042 err = ixgbe_setup_rx_resources(&temp_ring[i]); 1043 if (err) { 1044 while (i) { 1045 i--; 1046 ixgbe_free_rx_resources(&temp_ring[i]); 1047 } 1048 goto err_setup; 1049 } 1050 1051 } 1052 1053 for (i = 0; i < adapter->num_rx_queues; i++) { 1054 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1055 1056 memcpy(adapter->rx_ring[i], &temp_ring[i], 1057 sizeof(struct ixgbe_ring)); 1058 } 1059 1060 adapter->rx_ring_count = new_rx_count; 1061 } 1062 1063 err_setup: 1064 ixgbe_up(adapter); 1065 vfree(temp_ring); 1066 clear_reset: 1067 clear_bit(__IXGBE_RESETTING, &adapter->state); 1068 return err; 1069 } 1070 1071 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1072 { 1073 switch (sset) { 1074 case ETH_SS_TEST: 1075 return IXGBE_TEST_LEN; 1076 case ETH_SS_STATS: 1077 return IXGBE_STATS_LEN; 1078 default: 1079 return -EOPNOTSUPP; 1080 } 1081 } 1082 1083 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1084 struct ethtool_stats *stats, u64 *data) 1085 { 1086 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1087 struct rtnl_link_stats64 temp; 1088 const struct rtnl_link_stats64 *net_stats; 1089 unsigned int start; 1090 struct ixgbe_ring *ring; 1091 int i, j; 1092 char *p = NULL; 1093 1094 ixgbe_update_stats(adapter); 1095 net_stats = dev_get_stats(netdev, &temp); 1096 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1097 switch (ixgbe_gstrings_stats[i].type) { 1098 case NETDEV_STATS: 1099 p = (char *) net_stats + 1100 ixgbe_gstrings_stats[i].stat_offset; 1101 break; 1102 case IXGBE_STATS: 1103 p = (char *) adapter + 1104 ixgbe_gstrings_stats[i].stat_offset; 1105 break; 1106 default: 1107 data[i] = 0; 1108 continue; 1109 } 1110 1111 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1112 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1113 } 1114 for (j = 0; j < netdev->num_tx_queues; j++) { 1115 ring = adapter->tx_ring[j]; 1116 if (!ring) { 1117 data[i] = 0; 1118 data[i+1] = 0; 1119 i += 2; 1120 #ifdef BP_EXTENDED_STATS 1121 data[i] = 0; 1122 data[i+1] = 0; 1123 data[i+2] = 0; 1124 i += 3; 1125 #endif 1126 continue; 1127 } 1128 1129 do { 1130 start = u64_stats_fetch_begin_bh(&ring->syncp); 1131 data[i] = ring->stats.packets; 1132 data[i+1] = ring->stats.bytes; 1133 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 1134 i += 2; 1135 #ifdef BP_EXTENDED_STATS 1136 data[i] = ring->stats.yields; 1137 data[i+1] = ring->stats.misses; 1138 data[i+2] = ring->stats.cleaned; 1139 i += 3; 1140 #endif 1141 } 1142 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1143 ring = adapter->rx_ring[j]; 1144 if (!ring) { 1145 data[i] = 0; 1146 data[i+1] = 0; 1147 i += 2; 1148 #ifdef BP_EXTENDED_STATS 1149 data[i] = 0; 1150 data[i+1] = 0; 1151 data[i+2] = 0; 1152 i += 3; 1153 #endif 1154 continue; 1155 } 1156 1157 do { 1158 start = u64_stats_fetch_begin_bh(&ring->syncp); 1159 data[i] = ring->stats.packets; 1160 data[i+1] = ring->stats.bytes; 1161 } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); 1162 i += 2; 1163 #ifdef BP_EXTENDED_STATS 1164 data[i] = ring->stats.yields; 1165 data[i+1] = ring->stats.misses; 1166 data[i+2] = ring->stats.cleaned; 1167 i += 3; 1168 #endif 1169 } 1170 1171 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1172 data[i++] = adapter->stats.pxontxc[j]; 1173 data[i++] = adapter->stats.pxofftxc[j]; 1174 } 1175 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1176 data[i++] = adapter->stats.pxonrxc[j]; 1177 data[i++] = adapter->stats.pxoffrxc[j]; 1178 } 1179 } 1180 1181 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1182 u8 *data) 1183 { 1184 char *p = (char *)data; 1185 int i; 1186 1187 switch (stringset) { 1188 case ETH_SS_TEST: 1189 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1190 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1191 data += ETH_GSTRING_LEN; 1192 } 1193 break; 1194 case ETH_SS_STATS: 1195 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1196 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1197 ETH_GSTRING_LEN); 1198 p += ETH_GSTRING_LEN; 1199 } 1200 for (i = 0; i < netdev->num_tx_queues; i++) { 1201 sprintf(p, "tx_queue_%u_packets", i); 1202 p += ETH_GSTRING_LEN; 1203 sprintf(p, "tx_queue_%u_bytes", i); 1204 p += ETH_GSTRING_LEN; 1205 #ifdef BP_EXTENDED_STATS 1206 sprintf(p, "tx_queue_%u_bp_napi_yield", i); 1207 p += ETH_GSTRING_LEN; 1208 sprintf(p, "tx_queue_%u_bp_misses", i); 1209 p += ETH_GSTRING_LEN; 1210 sprintf(p, "tx_queue_%u_bp_cleaned", i); 1211 p += ETH_GSTRING_LEN; 1212 #endif /* BP_EXTENDED_STATS */ 1213 } 1214 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1215 sprintf(p, "rx_queue_%u_packets", i); 1216 p += ETH_GSTRING_LEN; 1217 sprintf(p, "rx_queue_%u_bytes", i); 1218 p += ETH_GSTRING_LEN; 1219 #ifdef BP_EXTENDED_STATS 1220 sprintf(p, "rx_queue_%u_bp_poll_yield", i); 1221 p += ETH_GSTRING_LEN; 1222 sprintf(p, "rx_queue_%u_bp_misses", i); 1223 p += ETH_GSTRING_LEN; 1224 sprintf(p, "rx_queue_%u_bp_cleaned", i); 1225 p += ETH_GSTRING_LEN; 1226 #endif /* BP_EXTENDED_STATS */ 1227 } 1228 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1229 sprintf(p, "tx_pb_%u_pxon", i); 1230 p += ETH_GSTRING_LEN; 1231 sprintf(p, "tx_pb_%u_pxoff", i); 1232 p += ETH_GSTRING_LEN; 1233 } 1234 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1235 sprintf(p, "rx_pb_%u_pxon", i); 1236 p += ETH_GSTRING_LEN; 1237 sprintf(p, "rx_pb_%u_pxoff", i); 1238 p += ETH_GSTRING_LEN; 1239 } 1240 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1241 break; 1242 } 1243 } 1244 1245 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1246 { 1247 struct ixgbe_hw *hw = &adapter->hw; 1248 bool link_up; 1249 u32 link_speed = 0; 1250 *data = 0; 1251 1252 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1253 if (link_up) 1254 return *data; 1255 else 1256 *data = 1; 1257 return *data; 1258 } 1259 1260 /* ethtool register test data */ 1261 struct ixgbe_reg_test { 1262 u16 reg; 1263 u8 array_len; 1264 u8 test_type; 1265 u32 mask; 1266 u32 write; 1267 }; 1268 1269 /* In the hardware, registers are laid out either singly, in arrays 1270 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1271 * most tests take place on arrays or single registers (handled 1272 * as a single-element array) and special-case the tables. 1273 * Table tests are always pattern tests. 1274 * 1275 * We also make provision for some required setup steps by specifying 1276 * registers to be written without any read-back testing. 1277 */ 1278 1279 #define PATTERN_TEST 1 1280 #define SET_READ_TEST 2 1281 #define WRITE_NO_TEST 3 1282 #define TABLE32_TEST 4 1283 #define TABLE64_TEST_LO 5 1284 #define TABLE64_TEST_HI 6 1285 1286 /* default 82599 register test */ 1287 static const struct ixgbe_reg_test reg_test_82599[] = { 1288 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1289 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1290 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1291 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1292 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1293 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1294 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1295 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1296 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1297 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1298 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1299 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1300 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1301 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1302 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1303 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1304 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1305 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1306 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1307 { 0, 0, 0, 0 } 1308 }; 1309 1310 /* default 82598 register test */ 1311 static const struct ixgbe_reg_test reg_test_82598[] = { 1312 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1313 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1314 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1315 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1316 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1317 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1318 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1319 /* Enable all four RX queues before testing. */ 1320 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1321 /* RDH is read-only for 82598, only test RDT. */ 1322 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1323 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1324 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1325 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1326 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1327 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1328 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1329 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1330 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1331 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1332 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1333 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1334 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1335 { 0, 0, 0, 0 } 1336 }; 1337 1338 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1339 u32 mask, u32 write) 1340 { 1341 u32 pat, val, before; 1342 static const u32 test_pattern[] = { 1343 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1344 1345 if (ixgbe_removed(adapter->hw.hw_addr)) { 1346 *data = 1; 1347 return 1; 1348 } 1349 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1350 before = ixgbe_read_reg(&adapter->hw, reg); 1351 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1352 val = ixgbe_read_reg(&adapter->hw, reg); 1353 if (val != (test_pattern[pat] & write & mask)) { 1354 e_err(drv, "pattern test reg %04X failed: got " 1355 "0x%08X expected 0x%08X\n", 1356 reg, val, (test_pattern[pat] & write & mask)); 1357 *data = reg; 1358 ixgbe_write_reg(&adapter->hw, reg, before); 1359 return true; 1360 } 1361 ixgbe_write_reg(&adapter->hw, reg, before); 1362 } 1363 return false; 1364 } 1365 1366 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1367 u32 mask, u32 write) 1368 { 1369 u32 val, before; 1370 1371 if (ixgbe_removed(adapter->hw.hw_addr)) { 1372 *data = 1; 1373 return 1; 1374 } 1375 before = ixgbe_read_reg(&adapter->hw, reg); 1376 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1377 val = ixgbe_read_reg(&adapter->hw, reg); 1378 if ((write & mask) != (val & mask)) { 1379 e_err(drv, "set/check reg %04X test failed: got 0x%08X " 1380 "expected 0x%08X\n", reg, (val & mask), (write & mask)); 1381 *data = reg; 1382 ixgbe_write_reg(&adapter->hw, reg, before); 1383 return true; 1384 } 1385 ixgbe_write_reg(&adapter->hw, reg, before); 1386 return false; 1387 } 1388 1389 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1390 { 1391 const struct ixgbe_reg_test *test; 1392 u32 value, before, after; 1393 u32 i, toggle; 1394 1395 if (ixgbe_removed(adapter->hw.hw_addr)) { 1396 e_err(drv, "Adapter removed - register test blocked\n"); 1397 *data = 1; 1398 return 1; 1399 } 1400 switch (adapter->hw.mac.type) { 1401 case ixgbe_mac_82598EB: 1402 toggle = 0x7FFFF3FF; 1403 test = reg_test_82598; 1404 break; 1405 case ixgbe_mac_82599EB: 1406 case ixgbe_mac_X540: 1407 toggle = 0x7FFFF30F; 1408 test = reg_test_82599; 1409 break; 1410 default: 1411 *data = 1; 1412 return 1; 1413 break; 1414 } 1415 1416 /* 1417 * Because the status register is such a special case, 1418 * we handle it separately from the rest of the register 1419 * tests. Some bits are read-only, some toggle, and some 1420 * are writeable on newer MACs. 1421 */ 1422 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1423 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1424 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1425 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1426 if (value != after) { 1427 e_err(drv, "failed STATUS register test got: 0x%08X " 1428 "expected: 0x%08X\n", after, value); 1429 *data = 1; 1430 return 1; 1431 } 1432 /* restore previous status */ 1433 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1434 1435 /* 1436 * Perform the remainder of the register test, looping through 1437 * the test table until we either fail or reach the null entry. 1438 */ 1439 while (test->reg) { 1440 for (i = 0; i < test->array_len; i++) { 1441 bool b = false; 1442 1443 switch (test->test_type) { 1444 case PATTERN_TEST: 1445 b = reg_pattern_test(adapter, data, 1446 test->reg + (i * 0x40), 1447 test->mask, 1448 test->write); 1449 break; 1450 case SET_READ_TEST: 1451 b = reg_set_and_check(adapter, data, 1452 test->reg + (i * 0x40), 1453 test->mask, 1454 test->write); 1455 break; 1456 case WRITE_NO_TEST: 1457 ixgbe_write_reg(&adapter->hw, 1458 test->reg + (i * 0x40), 1459 test->write); 1460 break; 1461 case TABLE32_TEST: 1462 b = reg_pattern_test(adapter, data, 1463 test->reg + (i * 4), 1464 test->mask, 1465 test->write); 1466 break; 1467 case TABLE64_TEST_LO: 1468 b = reg_pattern_test(adapter, data, 1469 test->reg + (i * 8), 1470 test->mask, 1471 test->write); 1472 break; 1473 case TABLE64_TEST_HI: 1474 b = reg_pattern_test(adapter, data, 1475 (test->reg + 4) + (i * 8), 1476 test->mask, 1477 test->write); 1478 break; 1479 } 1480 if (b) 1481 return 1; 1482 } 1483 test++; 1484 } 1485 1486 *data = 0; 1487 return 0; 1488 } 1489 1490 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1491 { 1492 struct ixgbe_hw *hw = &adapter->hw; 1493 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1494 *data = 1; 1495 else 1496 *data = 0; 1497 return *data; 1498 } 1499 1500 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1501 { 1502 struct net_device *netdev = (struct net_device *) data; 1503 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1504 1505 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1506 1507 return IRQ_HANDLED; 1508 } 1509 1510 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1511 { 1512 struct net_device *netdev = adapter->netdev; 1513 u32 mask, i = 0, shared_int = true; 1514 u32 irq = adapter->pdev->irq; 1515 1516 *data = 0; 1517 1518 /* Hook up test interrupt handler just for this test */ 1519 if (adapter->msix_entries) { 1520 /* NOTE: we don't test MSI-X interrupts here, yet */ 1521 return 0; 1522 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1523 shared_int = false; 1524 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1525 netdev)) { 1526 *data = 1; 1527 return -1; 1528 } 1529 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1530 netdev->name, netdev)) { 1531 shared_int = false; 1532 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1533 netdev->name, netdev)) { 1534 *data = 1; 1535 return -1; 1536 } 1537 e_info(hw, "testing %s interrupt\n", shared_int ? 1538 "shared" : "unshared"); 1539 1540 /* Disable all the interrupts */ 1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1542 IXGBE_WRITE_FLUSH(&adapter->hw); 1543 usleep_range(10000, 20000); 1544 1545 /* Test each interrupt */ 1546 for (; i < 10; i++) { 1547 /* Interrupt to test */ 1548 mask = 1 << i; 1549 1550 if (!shared_int) { 1551 /* 1552 * Disable the interrupts to be reported in 1553 * the cause register and then force the same 1554 * interrupt and see if one gets posted. If 1555 * an interrupt was posted to the bus, the 1556 * test failed. 1557 */ 1558 adapter->test_icr = 0; 1559 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1560 ~mask & 0x00007FFF); 1561 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1562 ~mask & 0x00007FFF); 1563 IXGBE_WRITE_FLUSH(&adapter->hw); 1564 usleep_range(10000, 20000); 1565 1566 if (adapter->test_icr & mask) { 1567 *data = 3; 1568 break; 1569 } 1570 } 1571 1572 /* 1573 * Enable the interrupt to be reported in the cause 1574 * register and then force the same interrupt and see 1575 * if one gets posted. If an interrupt was not posted 1576 * to the bus, the test failed. 1577 */ 1578 adapter->test_icr = 0; 1579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1581 IXGBE_WRITE_FLUSH(&adapter->hw); 1582 usleep_range(10000, 20000); 1583 1584 if (!(adapter->test_icr &mask)) { 1585 *data = 4; 1586 break; 1587 } 1588 1589 if (!shared_int) { 1590 /* 1591 * Disable the other interrupts to be reported in 1592 * the cause register and then force the other 1593 * interrupts and see if any get posted. If 1594 * an interrupt was posted to the bus, the 1595 * test failed. 1596 */ 1597 adapter->test_icr = 0; 1598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1599 ~mask & 0x00007FFF); 1600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1601 ~mask & 0x00007FFF); 1602 IXGBE_WRITE_FLUSH(&adapter->hw); 1603 usleep_range(10000, 20000); 1604 1605 if (adapter->test_icr) { 1606 *data = 5; 1607 break; 1608 } 1609 } 1610 } 1611 1612 /* Disable all the interrupts */ 1613 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1614 IXGBE_WRITE_FLUSH(&adapter->hw); 1615 usleep_range(10000, 20000); 1616 1617 /* Unhook test interrupt handler */ 1618 free_irq(irq, netdev); 1619 1620 return *data; 1621 } 1622 1623 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1624 { 1625 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1626 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1627 struct ixgbe_hw *hw = &adapter->hw; 1628 u32 reg_ctl; 1629 1630 /* shut down the DMA engines now so they can be reinitialized later */ 1631 1632 /* first Rx */ 1633 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1634 reg_ctl &= ~IXGBE_RXCTRL_RXEN; 1635 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl); 1636 ixgbe_disable_rx_queue(adapter, rx_ring); 1637 1638 /* now Tx */ 1639 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); 1640 reg_ctl &= ~IXGBE_TXDCTL_ENABLE; 1641 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); 1642 1643 switch (hw->mac.type) { 1644 case ixgbe_mac_82599EB: 1645 case ixgbe_mac_X540: 1646 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1647 reg_ctl &= ~IXGBE_DMATXCTL_TE; 1648 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); 1649 break; 1650 default: 1651 break; 1652 } 1653 1654 ixgbe_reset(adapter); 1655 1656 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1657 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1658 } 1659 1660 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1661 { 1662 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1663 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1664 u32 rctl, reg_data; 1665 int ret_val; 1666 int err; 1667 1668 /* Setup Tx descriptor ring and Tx buffers */ 1669 tx_ring->count = IXGBE_DEFAULT_TXD; 1670 tx_ring->queue_index = 0; 1671 tx_ring->dev = &adapter->pdev->dev; 1672 tx_ring->netdev = adapter->netdev; 1673 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1674 1675 err = ixgbe_setup_tx_resources(tx_ring); 1676 if (err) 1677 return 1; 1678 1679 switch (adapter->hw.mac.type) { 1680 case ixgbe_mac_82599EB: 1681 case ixgbe_mac_X540: 1682 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1683 reg_data |= IXGBE_DMATXCTL_TE; 1684 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 ixgbe_configure_tx_ring(adapter, tx_ring); 1691 1692 /* Setup Rx Descriptor ring and Rx buffers */ 1693 rx_ring->count = IXGBE_DEFAULT_RXD; 1694 rx_ring->queue_index = 0; 1695 rx_ring->dev = &adapter->pdev->dev; 1696 rx_ring->netdev = adapter->netdev; 1697 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1698 1699 err = ixgbe_setup_rx_resources(rx_ring); 1700 if (err) { 1701 ret_val = 4; 1702 goto err_nomem; 1703 } 1704 1705 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1706 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN); 1707 1708 ixgbe_configure_rx_ring(adapter, rx_ring); 1709 1710 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS; 1711 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1712 1713 return 0; 1714 1715 err_nomem: 1716 ixgbe_free_desc_rings(adapter); 1717 return ret_val; 1718 } 1719 1720 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1721 { 1722 struct ixgbe_hw *hw = &adapter->hw; 1723 u32 reg_data; 1724 1725 1726 /* Setup MAC loopback */ 1727 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1728 reg_data |= IXGBE_HLREG0_LPBK; 1729 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1730 1731 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1732 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1733 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1734 1735 /* X540 needs to set the MACC.FLU bit to force link up */ 1736 if (adapter->hw.mac.type == ixgbe_mac_X540) { 1737 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1738 reg_data |= IXGBE_MACC_FLU; 1739 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1740 } else { 1741 if (hw->mac.orig_autoc) { 1742 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1743 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1744 } else { 1745 return 10; 1746 } 1747 } 1748 IXGBE_WRITE_FLUSH(hw); 1749 usleep_range(10000, 20000); 1750 1751 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1752 if (hw->mac.type == ixgbe_mac_82598EB) { 1753 u8 atlas; 1754 1755 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1756 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1757 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1758 1759 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1760 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1761 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1762 1763 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1764 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1765 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1766 1767 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1768 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1769 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1770 } 1771 1772 return 0; 1773 } 1774 1775 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1776 { 1777 u32 reg_data; 1778 1779 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1780 reg_data &= ~IXGBE_HLREG0_LPBK; 1781 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1782 } 1783 1784 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1785 unsigned int frame_size) 1786 { 1787 memset(skb->data, 0xFF, frame_size); 1788 frame_size >>= 1; 1789 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1790 memset(&skb->data[frame_size + 10], 0xBE, 1); 1791 memset(&skb->data[frame_size + 12], 0xAF, 1); 1792 } 1793 1794 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1795 unsigned int frame_size) 1796 { 1797 unsigned char *data; 1798 bool match = true; 1799 1800 frame_size >>= 1; 1801 1802 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1803 1804 if (data[3] != 0xFF || 1805 data[frame_size + 10] != 0xBE || 1806 data[frame_size + 12] != 0xAF) 1807 match = false; 1808 1809 kunmap(rx_buffer->page); 1810 1811 return match; 1812 } 1813 1814 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1815 struct ixgbe_ring *tx_ring, 1816 unsigned int size) 1817 { 1818 union ixgbe_adv_rx_desc *rx_desc; 1819 struct ixgbe_rx_buffer *rx_buffer; 1820 struct ixgbe_tx_buffer *tx_buffer; 1821 u16 rx_ntc, tx_ntc, count = 0; 1822 1823 /* initialize next to clean and descriptor values */ 1824 rx_ntc = rx_ring->next_to_clean; 1825 tx_ntc = tx_ring->next_to_clean; 1826 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1827 1828 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) { 1829 /* check Rx buffer */ 1830 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 1831 1832 /* sync Rx buffer for CPU read */ 1833 dma_sync_single_for_cpu(rx_ring->dev, 1834 rx_buffer->dma, 1835 ixgbe_rx_bufsz(rx_ring), 1836 DMA_FROM_DEVICE); 1837 1838 /* verify contents of skb */ 1839 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 1840 count++; 1841 1842 /* sync Rx buffer for device write */ 1843 dma_sync_single_for_device(rx_ring->dev, 1844 rx_buffer->dma, 1845 ixgbe_rx_bufsz(rx_ring), 1846 DMA_FROM_DEVICE); 1847 1848 /* unmap buffer on Tx side */ 1849 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1850 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); 1851 1852 /* increment Rx/Tx next to clean counters */ 1853 rx_ntc++; 1854 if (rx_ntc == rx_ring->count) 1855 rx_ntc = 0; 1856 tx_ntc++; 1857 if (tx_ntc == tx_ring->count) 1858 tx_ntc = 0; 1859 1860 /* fetch next descriptor */ 1861 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1862 } 1863 1864 netdev_tx_reset_queue(txring_txq(tx_ring)); 1865 1866 /* re-map buffers to ring, store next to clean values */ 1867 ixgbe_alloc_rx_buffers(rx_ring, count); 1868 rx_ring->next_to_clean = rx_ntc; 1869 tx_ring->next_to_clean = tx_ntc; 1870 1871 return count; 1872 } 1873 1874 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1875 { 1876 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1877 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1878 int i, j, lc, good_cnt, ret_val = 0; 1879 unsigned int size = 1024; 1880 netdev_tx_t tx_ret_val; 1881 struct sk_buff *skb; 1882 u32 flags_orig = adapter->flags; 1883 1884 /* DCB can modify the frames on Tx */ 1885 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1886 1887 /* allocate test skb */ 1888 skb = alloc_skb(size, GFP_KERNEL); 1889 if (!skb) 1890 return 11; 1891 1892 /* place data into test skb */ 1893 ixgbe_create_lbtest_frame(skb, size); 1894 skb_put(skb, size); 1895 1896 /* 1897 * Calculate the loop count based on the largest descriptor ring 1898 * The idea is to wrap the largest ring a number of times using 64 1899 * send/receive pairs during each loop 1900 */ 1901 1902 if (rx_ring->count <= tx_ring->count) 1903 lc = ((tx_ring->count / 64) * 2) + 1; 1904 else 1905 lc = ((rx_ring->count / 64) * 2) + 1; 1906 1907 for (j = 0; j <= lc; j++) { 1908 /* reset count of good packets */ 1909 good_cnt = 0; 1910 1911 /* place 64 packets on the transmit queue*/ 1912 for (i = 0; i < 64; i++) { 1913 skb_get(skb); 1914 tx_ret_val = ixgbe_xmit_frame_ring(skb, 1915 adapter, 1916 tx_ring); 1917 if (tx_ret_val == NETDEV_TX_OK) 1918 good_cnt++; 1919 } 1920 1921 if (good_cnt != 64) { 1922 ret_val = 12; 1923 break; 1924 } 1925 1926 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1927 msleep(200); 1928 1929 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 1930 if (good_cnt != 64) { 1931 ret_val = 13; 1932 break; 1933 } 1934 } 1935 1936 /* free the original skb */ 1937 kfree_skb(skb); 1938 adapter->flags = flags_orig; 1939 1940 return ret_val; 1941 } 1942 1943 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 1944 { 1945 *data = ixgbe_setup_desc_rings(adapter); 1946 if (*data) 1947 goto out; 1948 *data = ixgbe_setup_loopback_test(adapter); 1949 if (*data) 1950 goto err_loopback; 1951 *data = ixgbe_run_loopback_test(adapter); 1952 ixgbe_loopback_cleanup(adapter); 1953 1954 err_loopback: 1955 ixgbe_free_desc_rings(adapter); 1956 out: 1957 return *data; 1958 } 1959 1960 static void ixgbe_diag_test(struct net_device *netdev, 1961 struct ethtool_test *eth_test, u64 *data) 1962 { 1963 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1964 bool if_running = netif_running(netdev); 1965 1966 if (ixgbe_removed(adapter->hw.hw_addr)) { 1967 e_err(hw, "Adapter removed - test blocked\n"); 1968 data[0] = 1; 1969 data[1] = 1; 1970 data[2] = 1; 1971 data[3] = 1; 1972 eth_test->flags |= ETH_TEST_FL_FAILED; 1973 return; 1974 } 1975 set_bit(__IXGBE_TESTING, &adapter->state); 1976 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1977 struct ixgbe_hw *hw = &adapter->hw; 1978 1979 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 1980 int i; 1981 for (i = 0; i < adapter->num_vfs; i++) { 1982 if (adapter->vfinfo[i].clear_to_send) { 1983 netdev_warn(netdev, "%s", 1984 "offline diagnostic is not " 1985 "supported when VFs are " 1986 "present\n"); 1987 data[0] = 1; 1988 data[1] = 1; 1989 data[2] = 1; 1990 data[3] = 1; 1991 eth_test->flags |= ETH_TEST_FL_FAILED; 1992 clear_bit(__IXGBE_TESTING, 1993 &adapter->state); 1994 goto skip_ol_tests; 1995 } 1996 } 1997 } 1998 1999 /* Offline tests */ 2000 e_info(hw, "offline testing starting\n"); 2001 2002 /* Link test performed before hardware reset so autoneg doesn't 2003 * interfere with test result 2004 */ 2005 if (ixgbe_link_test(adapter, &data[4])) 2006 eth_test->flags |= ETH_TEST_FL_FAILED; 2007 2008 if (if_running) 2009 /* indicate we're in test mode */ 2010 dev_close(netdev); 2011 else 2012 ixgbe_reset(adapter); 2013 2014 e_info(hw, "register testing starting\n"); 2015 if (ixgbe_reg_test(adapter, &data[0])) 2016 eth_test->flags |= ETH_TEST_FL_FAILED; 2017 2018 ixgbe_reset(adapter); 2019 e_info(hw, "eeprom testing starting\n"); 2020 if (ixgbe_eeprom_test(adapter, &data[1])) 2021 eth_test->flags |= ETH_TEST_FL_FAILED; 2022 2023 ixgbe_reset(adapter); 2024 e_info(hw, "interrupt testing starting\n"); 2025 if (ixgbe_intr_test(adapter, &data[2])) 2026 eth_test->flags |= ETH_TEST_FL_FAILED; 2027 2028 /* If SRIOV or VMDq is enabled then skip MAC 2029 * loopback diagnostic. */ 2030 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2031 IXGBE_FLAG_VMDQ_ENABLED)) { 2032 e_info(hw, "Skip MAC loopback diagnostic in VT " 2033 "mode\n"); 2034 data[3] = 0; 2035 goto skip_loopback; 2036 } 2037 2038 ixgbe_reset(adapter); 2039 e_info(hw, "loopback testing starting\n"); 2040 if (ixgbe_loopback_test(adapter, &data[3])) 2041 eth_test->flags |= ETH_TEST_FL_FAILED; 2042 2043 skip_loopback: 2044 ixgbe_reset(adapter); 2045 2046 /* clear testing bit and return adapter to previous state */ 2047 clear_bit(__IXGBE_TESTING, &adapter->state); 2048 if (if_running) 2049 dev_open(netdev); 2050 else if (hw->mac.ops.disable_tx_laser) 2051 hw->mac.ops.disable_tx_laser(hw); 2052 } else { 2053 e_info(hw, "online testing starting\n"); 2054 2055 /* Online tests */ 2056 if (ixgbe_link_test(adapter, &data[4])) 2057 eth_test->flags |= ETH_TEST_FL_FAILED; 2058 2059 /* Offline tests aren't run; pass by default */ 2060 data[0] = 0; 2061 data[1] = 0; 2062 data[2] = 0; 2063 data[3] = 0; 2064 2065 clear_bit(__IXGBE_TESTING, &adapter->state); 2066 } 2067 2068 skip_ol_tests: 2069 msleep_interruptible(4 * 1000); 2070 } 2071 2072 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2073 struct ethtool_wolinfo *wol) 2074 { 2075 struct ixgbe_hw *hw = &adapter->hw; 2076 int retval = 0; 2077 2078 /* WOL not supported for all devices */ 2079 if (!ixgbe_wol_supported(adapter, hw->device_id, 2080 hw->subsystem_device_id)) { 2081 retval = 1; 2082 wol->supported = 0; 2083 } 2084 2085 return retval; 2086 } 2087 2088 static void ixgbe_get_wol(struct net_device *netdev, 2089 struct ethtool_wolinfo *wol) 2090 { 2091 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2092 2093 wol->supported = WAKE_UCAST | WAKE_MCAST | 2094 WAKE_BCAST | WAKE_MAGIC; 2095 wol->wolopts = 0; 2096 2097 if (ixgbe_wol_exclusion(adapter, wol) || 2098 !device_can_wakeup(&adapter->pdev->dev)) 2099 return; 2100 2101 if (adapter->wol & IXGBE_WUFC_EX) 2102 wol->wolopts |= WAKE_UCAST; 2103 if (adapter->wol & IXGBE_WUFC_MC) 2104 wol->wolopts |= WAKE_MCAST; 2105 if (adapter->wol & IXGBE_WUFC_BC) 2106 wol->wolopts |= WAKE_BCAST; 2107 if (adapter->wol & IXGBE_WUFC_MAG) 2108 wol->wolopts |= WAKE_MAGIC; 2109 } 2110 2111 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2112 { 2113 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2114 2115 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 2116 return -EOPNOTSUPP; 2117 2118 if (ixgbe_wol_exclusion(adapter, wol)) 2119 return wol->wolopts ? -EOPNOTSUPP : 0; 2120 2121 adapter->wol = 0; 2122 2123 if (wol->wolopts & WAKE_UCAST) 2124 adapter->wol |= IXGBE_WUFC_EX; 2125 if (wol->wolopts & WAKE_MCAST) 2126 adapter->wol |= IXGBE_WUFC_MC; 2127 if (wol->wolopts & WAKE_BCAST) 2128 adapter->wol |= IXGBE_WUFC_BC; 2129 if (wol->wolopts & WAKE_MAGIC) 2130 adapter->wol |= IXGBE_WUFC_MAG; 2131 2132 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2133 2134 return 0; 2135 } 2136 2137 static int ixgbe_nway_reset(struct net_device *netdev) 2138 { 2139 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2140 2141 if (netif_running(netdev)) 2142 ixgbe_reinit_locked(adapter); 2143 2144 return 0; 2145 } 2146 2147 static int ixgbe_set_phys_id(struct net_device *netdev, 2148 enum ethtool_phys_id_state state) 2149 { 2150 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2151 struct ixgbe_hw *hw = &adapter->hw; 2152 2153 switch (state) { 2154 case ETHTOOL_ID_ACTIVE: 2155 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2156 return 2; 2157 2158 case ETHTOOL_ID_ON: 2159 hw->mac.ops.led_on(hw, IXGBE_LED_ON); 2160 break; 2161 2162 case ETHTOOL_ID_OFF: 2163 hw->mac.ops.led_off(hw, IXGBE_LED_ON); 2164 break; 2165 2166 case ETHTOOL_ID_INACTIVE: 2167 /* Restore LED settings */ 2168 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2169 break; 2170 } 2171 2172 return 0; 2173 } 2174 2175 static int ixgbe_get_coalesce(struct net_device *netdev, 2176 struct ethtool_coalesce *ec) 2177 { 2178 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2179 2180 /* only valid if in constant ITR mode */ 2181 if (adapter->rx_itr_setting <= 1) 2182 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2183 else 2184 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2185 2186 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2187 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2188 return 0; 2189 2190 /* only valid if in constant ITR mode */ 2191 if (adapter->tx_itr_setting <= 1) 2192 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2193 else 2194 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2195 2196 return 0; 2197 } 2198 2199 /* 2200 * this function must be called before setting the new value of 2201 * rx_itr_setting 2202 */ 2203 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2204 { 2205 struct net_device *netdev = adapter->netdev; 2206 2207 /* nothing to do if LRO or RSC are not enabled */ 2208 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2209 !(netdev->features & NETIF_F_LRO)) 2210 return false; 2211 2212 /* check the feature flag value and enable RSC if necessary */ 2213 if (adapter->rx_itr_setting == 1 || 2214 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2215 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2216 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2217 e_info(probe, "rx-usecs value high enough " 2218 "to re-enable RSC\n"); 2219 return true; 2220 } 2221 /* if interrupt rate is too high then disable RSC */ 2222 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2223 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2224 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2225 return true; 2226 } 2227 return false; 2228 } 2229 2230 static int ixgbe_set_coalesce(struct net_device *netdev, 2231 struct ethtool_coalesce *ec) 2232 { 2233 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2234 struct ixgbe_q_vector *q_vector; 2235 int i; 2236 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2237 bool need_reset = false; 2238 2239 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2240 /* reject Tx specific changes in case of mixed RxTx vectors */ 2241 if (ec->tx_coalesce_usecs) 2242 return -EINVAL; 2243 tx_itr_prev = adapter->rx_itr_setting; 2244 } else { 2245 tx_itr_prev = adapter->tx_itr_setting; 2246 } 2247 2248 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2249 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2250 return -EINVAL; 2251 2252 if (ec->rx_coalesce_usecs > 1) 2253 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2254 else 2255 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2256 2257 if (adapter->rx_itr_setting == 1) 2258 rx_itr_param = IXGBE_20K_ITR; 2259 else 2260 rx_itr_param = adapter->rx_itr_setting; 2261 2262 if (ec->tx_coalesce_usecs > 1) 2263 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2264 else 2265 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2266 2267 if (adapter->tx_itr_setting == 1) 2268 tx_itr_param = IXGBE_10K_ITR; 2269 else 2270 tx_itr_param = adapter->tx_itr_setting; 2271 2272 /* mixed Rx/Tx */ 2273 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2274 adapter->tx_itr_setting = adapter->rx_itr_setting; 2275 2276 #if IS_ENABLED(CONFIG_BQL) 2277 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2278 if ((adapter->tx_itr_setting != 1) && 2279 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2280 if ((tx_itr_prev == 1) || 2281 (tx_itr_prev >= IXGBE_100K_ITR)) 2282 need_reset = true; 2283 } else { 2284 if ((tx_itr_prev != 1) && 2285 (tx_itr_prev < IXGBE_100K_ITR)) 2286 need_reset = true; 2287 } 2288 #endif 2289 /* check the old value and enable RSC if necessary */ 2290 need_reset |= ixgbe_update_rsc(adapter); 2291 2292 for (i = 0; i < adapter->num_q_vectors; i++) { 2293 q_vector = adapter->q_vector[i]; 2294 if (q_vector->tx.count && !q_vector->rx.count) 2295 /* tx only */ 2296 q_vector->itr = tx_itr_param; 2297 else 2298 /* rx only or mixed */ 2299 q_vector->itr = rx_itr_param; 2300 ixgbe_write_eitr(q_vector); 2301 } 2302 2303 /* 2304 * do reset here at the end to make sure EITR==0 case is handled 2305 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2306 * also locks in RSC enable/disable which requires reset 2307 */ 2308 if (need_reset) 2309 ixgbe_do_reset(netdev); 2310 2311 return 0; 2312 } 2313 2314 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2315 struct ethtool_rxnfc *cmd) 2316 { 2317 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2318 struct ethtool_rx_flow_spec *fsp = 2319 (struct ethtool_rx_flow_spec *)&cmd->fs; 2320 struct hlist_node *node2; 2321 struct ixgbe_fdir_filter *rule = NULL; 2322 2323 /* report total rule count */ 2324 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2325 2326 hlist_for_each_entry_safe(rule, node2, 2327 &adapter->fdir_filter_list, fdir_node) { 2328 if (fsp->location <= rule->sw_idx) 2329 break; 2330 } 2331 2332 if (!rule || fsp->location != rule->sw_idx) 2333 return -EINVAL; 2334 2335 /* fill out the flow spec entry */ 2336 2337 /* set flow type field */ 2338 switch (rule->filter.formatted.flow_type) { 2339 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2340 fsp->flow_type = TCP_V4_FLOW; 2341 break; 2342 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2343 fsp->flow_type = UDP_V4_FLOW; 2344 break; 2345 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2346 fsp->flow_type = SCTP_V4_FLOW; 2347 break; 2348 case IXGBE_ATR_FLOW_TYPE_IPV4: 2349 fsp->flow_type = IP_USER_FLOW; 2350 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2351 fsp->h_u.usr_ip4_spec.proto = 0; 2352 fsp->m_u.usr_ip4_spec.proto = 0; 2353 break; 2354 default: 2355 return -EINVAL; 2356 } 2357 2358 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2359 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2360 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2361 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2362 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2363 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2364 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2365 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2366 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2367 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2368 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2369 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2370 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2371 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2372 fsp->flow_type |= FLOW_EXT; 2373 2374 /* record action */ 2375 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2376 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2377 else 2378 fsp->ring_cookie = rule->action; 2379 2380 return 0; 2381 } 2382 2383 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2384 struct ethtool_rxnfc *cmd, 2385 u32 *rule_locs) 2386 { 2387 struct hlist_node *node2; 2388 struct ixgbe_fdir_filter *rule; 2389 int cnt = 0; 2390 2391 /* report total rule count */ 2392 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2393 2394 hlist_for_each_entry_safe(rule, node2, 2395 &adapter->fdir_filter_list, fdir_node) { 2396 if (cnt == cmd->rule_cnt) 2397 return -EMSGSIZE; 2398 rule_locs[cnt] = rule->sw_idx; 2399 cnt++; 2400 } 2401 2402 cmd->rule_cnt = cnt; 2403 2404 return 0; 2405 } 2406 2407 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2408 struct ethtool_rxnfc *cmd) 2409 { 2410 cmd->data = 0; 2411 2412 /* Report default options for RSS on ixgbe */ 2413 switch (cmd->flow_type) { 2414 case TCP_V4_FLOW: 2415 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2416 case UDP_V4_FLOW: 2417 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2418 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2419 case SCTP_V4_FLOW: 2420 case AH_ESP_V4_FLOW: 2421 case AH_V4_FLOW: 2422 case ESP_V4_FLOW: 2423 case IPV4_FLOW: 2424 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2425 break; 2426 case TCP_V6_FLOW: 2427 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2428 case UDP_V6_FLOW: 2429 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2430 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2431 case SCTP_V6_FLOW: 2432 case AH_ESP_V6_FLOW: 2433 case AH_V6_FLOW: 2434 case ESP_V6_FLOW: 2435 case IPV6_FLOW: 2436 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2437 break; 2438 default: 2439 return -EINVAL; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2446 u32 *rule_locs) 2447 { 2448 struct ixgbe_adapter *adapter = netdev_priv(dev); 2449 int ret = -EOPNOTSUPP; 2450 2451 switch (cmd->cmd) { 2452 case ETHTOOL_GRXRINGS: 2453 cmd->data = adapter->num_rx_queues; 2454 ret = 0; 2455 break; 2456 case ETHTOOL_GRXCLSRLCNT: 2457 cmd->rule_cnt = adapter->fdir_filter_count; 2458 ret = 0; 2459 break; 2460 case ETHTOOL_GRXCLSRULE: 2461 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2462 break; 2463 case ETHTOOL_GRXCLSRLALL: 2464 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2465 break; 2466 case ETHTOOL_GRXFH: 2467 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2468 break; 2469 default: 2470 break; 2471 } 2472 2473 return ret; 2474 } 2475 2476 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2477 struct ixgbe_fdir_filter *input, 2478 u16 sw_idx) 2479 { 2480 struct ixgbe_hw *hw = &adapter->hw; 2481 struct hlist_node *node2; 2482 struct ixgbe_fdir_filter *rule, *parent; 2483 int err = -EINVAL; 2484 2485 parent = NULL; 2486 rule = NULL; 2487 2488 hlist_for_each_entry_safe(rule, node2, 2489 &adapter->fdir_filter_list, fdir_node) { 2490 /* hash found, or no matching entry */ 2491 if (rule->sw_idx >= sw_idx) 2492 break; 2493 parent = rule; 2494 } 2495 2496 /* if there is an old rule occupying our place remove it */ 2497 if (rule && (rule->sw_idx == sw_idx)) { 2498 if (!input || (rule->filter.formatted.bkt_hash != 2499 input->filter.formatted.bkt_hash)) { 2500 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2501 &rule->filter, 2502 sw_idx); 2503 } 2504 2505 hlist_del(&rule->fdir_node); 2506 kfree(rule); 2507 adapter->fdir_filter_count--; 2508 } 2509 2510 /* 2511 * If no input this was a delete, err should be 0 if a rule was 2512 * successfully found and removed from the list else -EINVAL 2513 */ 2514 if (!input) 2515 return err; 2516 2517 /* initialize node and set software index */ 2518 INIT_HLIST_NODE(&input->fdir_node); 2519 2520 /* add filter to the list */ 2521 if (parent) 2522 hlist_add_after(&parent->fdir_node, &input->fdir_node); 2523 else 2524 hlist_add_head(&input->fdir_node, 2525 &adapter->fdir_filter_list); 2526 2527 /* update counts */ 2528 adapter->fdir_filter_count++; 2529 2530 return 0; 2531 } 2532 2533 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2534 u8 *flow_type) 2535 { 2536 switch (fsp->flow_type & ~FLOW_EXT) { 2537 case TCP_V4_FLOW: 2538 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2539 break; 2540 case UDP_V4_FLOW: 2541 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2542 break; 2543 case SCTP_V4_FLOW: 2544 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2545 break; 2546 case IP_USER_FLOW: 2547 switch (fsp->h_u.usr_ip4_spec.proto) { 2548 case IPPROTO_TCP: 2549 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2550 break; 2551 case IPPROTO_UDP: 2552 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2553 break; 2554 case IPPROTO_SCTP: 2555 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2556 break; 2557 case 0: 2558 if (!fsp->m_u.usr_ip4_spec.proto) { 2559 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2560 break; 2561 } 2562 default: 2563 return 0; 2564 } 2565 break; 2566 default: 2567 return 0; 2568 } 2569 2570 return 1; 2571 } 2572 2573 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2574 struct ethtool_rxnfc *cmd) 2575 { 2576 struct ethtool_rx_flow_spec *fsp = 2577 (struct ethtool_rx_flow_spec *)&cmd->fs; 2578 struct ixgbe_hw *hw = &adapter->hw; 2579 struct ixgbe_fdir_filter *input; 2580 union ixgbe_atr_input mask; 2581 int err; 2582 2583 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2584 return -EOPNOTSUPP; 2585 2586 /* 2587 * Don't allow programming if the action is a queue greater than 2588 * the number of online Rx queues. 2589 */ 2590 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) && 2591 (fsp->ring_cookie >= adapter->num_rx_queues)) 2592 return -EINVAL; 2593 2594 /* Don't allow indexes to exist outside of available space */ 2595 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2596 e_err(drv, "Location out of range\n"); 2597 return -EINVAL; 2598 } 2599 2600 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2601 if (!input) 2602 return -ENOMEM; 2603 2604 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2605 2606 /* set SW index */ 2607 input->sw_idx = fsp->location; 2608 2609 /* record flow type */ 2610 if (!ixgbe_flowspec_to_flow_type(fsp, 2611 &input->filter.formatted.flow_type)) { 2612 e_err(drv, "Unrecognized flow type\n"); 2613 goto err_out; 2614 } 2615 2616 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2617 IXGBE_ATR_L4TYPE_MASK; 2618 2619 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2620 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2621 2622 /* Copy input into formatted structures */ 2623 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2624 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2625 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2626 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2627 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2628 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2629 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2630 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2631 2632 if (fsp->flow_type & FLOW_EXT) { 2633 input->filter.formatted.vm_pool = 2634 (unsigned char)ntohl(fsp->h_ext.data[1]); 2635 mask.formatted.vm_pool = 2636 (unsigned char)ntohl(fsp->m_ext.data[1]); 2637 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2638 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2639 input->filter.formatted.flex_bytes = 2640 fsp->h_ext.vlan_etype; 2641 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2642 } 2643 2644 /* determine if we need to drop or route the packet */ 2645 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2646 input->action = IXGBE_FDIR_DROP_QUEUE; 2647 else 2648 input->action = fsp->ring_cookie; 2649 2650 spin_lock(&adapter->fdir_perfect_lock); 2651 2652 if (hlist_empty(&adapter->fdir_filter_list)) { 2653 /* save mask and program input mask into HW */ 2654 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2655 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2656 if (err) { 2657 e_err(drv, "Error writing mask\n"); 2658 goto err_out_w_lock; 2659 } 2660 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2661 e_err(drv, "Only one mask supported per port\n"); 2662 goto err_out_w_lock; 2663 } 2664 2665 /* apply mask and compute/store hash */ 2666 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2667 2668 /* program filters to filter memory */ 2669 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2670 &input->filter, input->sw_idx, 2671 (input->action == IXGBE_FDIR_DROP_QUEUE) ? 2672 IXGBE_FDIR_DROP_QUEUE : 2673 adapter->rx_ring[input->action]->reg_idx); 2674 if (err) 2675 goto err_out_w_lock; 2676 2677 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2678 2679 spin_unlock(&adapter->fdir_perfect_lock); 2680 2681 return err; 2682 err_out_w_lock: 2683 spin_unlock(&adapter->fdir_perfect_lock); 2684 err_out: 2685 kfree(input); 2686 return -EINVAL; 2687 } 2688 2689 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2690 struct ethtool_rxnfc *cmd) 2691 { 2692 struct ethtool_rx_flow_spec *fsp = 2693 (struct ethtool_rx_flow_spec *)&cmd->fs; 2694 int err; 2695 2696 spin_lock(&adapter->fdir_perfect_lock); 2697 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2698 spin_unlock(&adapter->fdir_perfect_lock); 2699 2700 return err; 2701 } 2702 2703 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2704 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2705 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2706 struct ethtool_rxnfc *nfc) 2707 { 2708 u32 flags2 = adapter->flags2; 2709 2710 /* 2711 * RSS does not support anything other than hashing 2712 * to queues on src and dst IPs and ports 2713 */ 2714 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2715 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2716 return -EINVAL; 2717 2718 switch (nfc->flow_type) { 2719 case TCP_V4_FLOW: 2720 case TCP_V6_FLOW: 2721 if (!(nfc->data & RXH_IP_SRC) || 2722 !(nfc->data & RXH_IP_DST) || 2723 !(nfc->data & RXH_L4_B_0_1) || 2724 !(nfc->data & RXH_L4_B_2_3)) 2725 return -EINVAL; 2726 break; 2727 case UDP_V4_FLOW: 2728 if (!(nfc->data & RXH_IP_SRC) || 2729 !(nfc->data & RXH_IP_DST)) 2730 return -EINVAL; 2731 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2732 case 0: 2733 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2734 break; 2735 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2736 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2737 break; 2738 default: 2739 return -EINVAL; 2740 } 2741 break; 2742 case UDP_V6_FLOW: 2743 if (!(nfc->data & RXH_IP_SRC) || 2744 !(nfc->data & RXH_IP_DST)) 2745 return -EINVAL; 2746 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2747 case 0: 2748 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2749 break; 2750 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2751 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2752 break; 2753 default: 2754 return -EINVAL; 2755 } 2756 break; 2757 case AH_ESP_V4_FLOW: 2758 case AH_V4_FLOW: 2759 case ESP_V4_FLOW: 2760 case SCTP_V4_FLOW: 2761 case AH_ESP_V6_FLOW: 2762 case AH_V6_FLOW: 2763 case ESP_V6_FLOW: 2764 case SCTP_V6_FLOW: 2765 if (!(nfc->data & RXH_IP_SRC) || 2766 !(nfc->data & RXH_IP_DST) || 2767 (nfc->data & RXH_L4_B_0_1) || 2768 (nfc->data & RXH_L4_B_2_3)) 2769 return -EINVAL; 2770 break; 2771 default: 2772 return -EINVAL; 2773 } 2774 2775 /* if we changed something we need to update flags */ 2776 if (flags2 != adapter->flags2) { 2777 struct ixgbe_hw *hw = &adapter->hw; 2778 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2779 2780 if ((flags2 & UDP_RSS_FLAGS) && 2781 !(adapter->flags2 & UDP_RSS_FLAGS)) 2782 e_warn(drv, "enabling UDP RSS: fragmented packets" 2783 " may arrive out of order to the stack above\n"); 2784 2785 adapter->flags2 = flags2; 2786 2787 /* Perform hash on these packet types */ 2788 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 2789 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 2790 | IXGBE_MRQC_RSS_FIELD_IPV6 2791 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 2792 2793 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2794 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 2795 2796 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2797 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 2798 2799 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2800 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 2801 2802 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2803 } 2804 2805 return 0; 2806 } 2807 2808 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2809 { 2810 struct ixgbe_adapter *adapter = netdev_priv(dev); 2811 int ret = -EOPNOTSUPP; 2812 2813 switch (cmd->cmd) { 2814 case ETHTOOL_SRXCLSRLINS: 2815 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2816 break; 2817 case ETHTOOL_SRXCLSRLDEL: 2818 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2819 break; 2820 case ETHTOOL_SRXFH: 2821 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 2822 break; 2823 default: 2824 break; 2825 } 2826 2827 return ret; 2828 } 2829 2830 static int ixgbe_get_ts_info(struct net_device *dev, 2831 struct ethtool_ts_info *info) 2832 { 2833 struct ixgbe_adapter *adapter = netdev_priv(dev); 2834 2835 switch (adapter->hw.mac.type) { 2836 case ixgbe_mac_X540: 2837 case ixgbe_mac_82599EB: 2838 info->so_timestamping = 2839 SOF_TIMESTAMPING_TX_SOFTWARE | 2840 SOF_TIMESTAMPING_RX_SOFTWARE | 2841 SOF_TIMESTAMPING_SOFTWARE | 2842 SOF_TIMESTAMPING_TX_HARDWARE | 2843 SOF_TIMESTAMPING_RX_HARDWARE | 2844 SOF_TIMESTAMPING_RAW_HARDWARE; 2845 2846 if (adapter->ptp_clock) 2847 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2848 else 2849 info->phc_index = -1; 2850 2851 info->tx_types = 2852 (1 << HWTSTAMP_TX_OFF) | 2853 (1 << HWTSTAMP_TX_ON); 2854 2855 info->rx_filters = 2856 (1 << HWTSTAMP_FILTER_NONE) | 2857 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2858 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2859 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 2860 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 2861 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 2862 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 2863 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 2864 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) | 2865 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 2866 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 2867 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2868 break; 2869 default: 2870 return ethtool_op_get_ts_info(dev, info); 2871 break; 2872 } 2873 return 0; 2874 } 2875 2876 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 2877 { 2878 unsigned int max_combined; 2879 u8 tcs = netdev_get_num_tc(adapter->netdev); 2880 2881 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 2882 /* We only support one q_vector without MSI-X */ 2883 max_combined = 1; 2884 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2885 /* SR-IOV currently only allows one queue on the PF */ 2886 max_combined = 1; 2887 } else if (tcs > 1) { 2888 /* For DCB report channels per traffic class */ 2889 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 2890 /* 8 TC w/ 4 queues per TC */ 2891 max_combined = 4; 2892 } else if (tcs > 4) { 2893 /* 8 TC w/ 8 queues per TC */ 2894 max_combined = 8; 2895 } else { 2896 /* 4 TC w/ 16 queues per TC */ 2897 max_combined = 16; 2898 } 2899 } else if (adapter->atr_sample_rate) { 2900 /* support up to 64 queues with ATR */ 2901 max_combined = IXGBE_MAX_FDIR_INDICES; 2902 } else { 2903 /* support up to 16 queues with RSS */ 2904 max_combined = IXGBE_MAX_RSS_INDICES; 2905 } 2906 2907 return max_combined; 2908 } 2909 2910 static void ixgbe_get_channels(struct net_device *dev, 2911 struct ethtool_channels *ch) 2912 { 2913 struct ixgbe_adapter *adapter = netdev_priv(dev); 2914 2915 /* report maximum channels */ 2916 ch->max_combined = ixgbe_max_channels(adapter); 2917 2918 /* report info for other vector */ 2919 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 2920 ch->max_other = NON_Q_VECTORS; 2921 ch->other_count = NON_Q_VECTORS; 2922 } 2923 2924 /* record RSS queues */ 2925 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 2926 2927 /* nothing else to report if RSS is disabled */ 2928 if (ch->combined_count == 1) 2929 return; 2930 2931 /* we do not support ATR queueing if SR-IOV is enabled */ 2932 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 2933 return; 2934 2935 /* same thing goes for being DCB enabled */ 2936 if (netdev_get_num_tc(dev) > 1) 2937 return; 2938 2939 /* if ATR is disabled we can exit */ 2940 if (!adapter->atr_sample_rate) 2941 return; 2942 2943 /* report flow director queues as maximum channels */ 2944 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 2945 } 2946 2947 static int ixgbe_set_channels(struct net_device *dev, 2948 struct ethtool_channels *ch) 2949 { 2950 struct ixgbe_adapter *adapter = netdev_priv(dev); 2951 unsigned int count = ch->combined_count; 2952 2953 /* verify they are not requesting separate vectors */ 2954 if (!count || ch->rx_count || ch->tx_count) 2955 return -EINVAL; 2956 2957 /* verify other_count has not changed */ 2958 if (ch->other_count != NON_Q_VECTORS) 2959 return -EINVAL; 2960 2961 /* verify the number of channels does not exceed hardware limits */ 2962 if (count > ixgbe_max_channels(adapter)) 2963 return -EINVAL; 2964 2965 /* update feature limits from largest to smallest supported values */ 2966 adapter->ring_feature[RING_F_FDIR].limit = count; 2967 2968 /* cap RSS limit at 16 */ 2969 if (count > IXGBE_MAX_RSS_INDICES) 2970 count = IXGBE_MAX_RSS_INDICES; 2971 adapter->ring_feature[RING_F_RSS].limit = count; 2972 2973 #ifdef IXGBE_FCOE 2974 /* cap FCoE limit at 8 */ 2975 if (count > IXGBE_FCRETA_SIZE) 2976 count = IXGBE_FCRETA_SIZE; 2977 adapter->ring_feature[RING_F_FCOE].limit = count; 2978 2979 #endif 2980 /* use setup TC to update any traffic class queue mapping */ 2981 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 2982 } 2983 2984 static int ixgbe_get_module_info(struct net_device *dev, 2985 struct ethtool_modinfo *modinfo) 2986 { 2987 struct ixgbe_adapter *adapter = netdev_priv(dev); 2988 struct ixgbe_hw *hw = &adapter->hw; 2989 u32 status; 2990 u8 sff8472_rev, addr_mode; 2991 bool page_swap = false; 2992 2993 /* Check whether we support SFF-8472 or not */ 2994 status = hw->phy.ops.read_i2c_eeprom(hw, 2995 IXGBE_SFF_SFF_8472_COMP, 2996 &sff8472_rev); 2997 if (status != 0) 2998 return -EIO; 2999 3000 /* addressing mode is not supported */ 3001 status = hw->phy.ops.read_i2c_eeprom(hw, 3002 IXGBE_SFF_SFF_8472_SWAP, 3003 &addr_mode); 3004 if (status != 0) 3005 return -EIO; 3006 3007 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3008 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3009 page_swap = true; 3010 } 3011 3012 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 3013 /* We have a SFP, but it does not support SFF-8472 */ 3014 modinfo->type = ETH_MODULE_SFF_8079; 3015 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3016 } else { 3017 /* We have a SFP which supports a revision of SFF-8472. */ 3018 modinfo->type = ETH_MODULE_SFF_8472; 3019 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3020 } 3021 3022 return 0; 3023 } 3024 3025 static int ixgbe_get_module_eeprom(struct net_device *dev, 3026 struct ethtool_eeprom *ee, 3027 u8 *data) 3028 { 3029 struct ixgbe_adapter *adapter = netdev_priv(dev); 3030 struct ixgbe_hw *hw = &adapter->hw; 3031 u32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3032 u8 databyte = 0xFF; 3033 int i = 0; 3034 3035 if (ee->len == 0) 3036 return -EINVAL; 3037 3038 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3039 /* I2C reads can take long time */ 3040 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3041 return -EBUSY; 3042 3043 if (i < ETH_MODULE_SFF_8079_LEN) 3044 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3045 else 3046 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3047 3048 if (status != 0) 3049 return -EIO; 3050 3051 data[i - ee->offset] = databyte; 3052 } 3053 3054 return 0; 3055 } 3056 3057 static const struct ethtool_ops ixgbe_ethtool_ops = { 3058 .get_settings = ixgbe_get_settings, 3059 .set_settings = ixgbe_set_settings, 3060 .get_drvinfo = ixgbe_get_drvinfo, 3061 .get_regs_len = ixgbe_get_regs_len, 3062 .get_regs = ixgbe_get_regs, 3063 .get_wol = ixgbe_get_wol, 3064 .set_wol = ixgbe_set_wol, 3065 .nway_reset = ixgbe_nway_reset, 3066 .get_link = ethtool_op_get_link, 3067 .get_eeprom_len = ixgbe_get_eeprom_len, 3068 .get_eeprom = ixgbe_get_eeprom, 3069 .set_eeprom = ixgbe_set_eeprom, 3070 .get_ringparam = ixgbe_get_ringparam, 3071 .set_ringparam = ixgbe_set_ringparam, 3072 .get_pauseparam = ixgbe_get_pauseparam, 3073 .set_pauseparam = ixgbe_set_pauseparam, 3074 .get_msglevel = ixgbe_get_msglevel, 3075 .set_msglevel = ixgbe_set_msglevel, 3076 .self_test = ixgbe_diag_test, 3077 .get_strings = ixgbe_get_strings, 3078 .set_phys_id = ixgbe_set_phys_id, 3079 .get_sset_count = ixgbe_get_sset_count, 3080 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3081 .get_coalesce = ixgbe_get_coalesce, 3082 .set_coalesce = ixgbe_set_coalesce, 3083 .get_rxnfc = ixgbe_get_rxnfc, 3084 .set_rxnfc = ixgbe_set_rxnfc, 3085 .get_channels = ixgbe_get_channels, 3086 .set_channels = ixgbe_set_channels, 3087 .get_ts_info = ixgbe_get_ts_info, 3088 .get_module_info = ixgbe_get_module_info, 3089 .get_module_eeprom = ixgbe_get_module_eeprom, 3090 }; 3091 3092 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3093 { 3094 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops); 3095 } 3096