1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* ethtool support for ixgbe */ 30 31 #include <linux/interrupt.h> 32 #include <linux/types.h> 33 #include <linux/module.h> 34 #include <linux/slab.h> 35 #include <linux/pci.h> 36 #include <linux/netdevice.h> 37 #include <linux/ethtool.h> 38 #include <linux/vmalloc.h> 39 #include <linux/highmem.h> 40 #include <linux/uaccess.h> 41 42 #include "ixgbe.h" 43 #include "ixgbe_phy.h" 44 45 46 #define IXGBE_ALL_RAR_ENTRIES 16 47 48 enum {NETDEV_STATS, IXGBE_STATS}; 49 50 struct ixgbe_stats { 51 char stat_string[ETH_GSTRING_LEN]; 52 int type; 53 int sizeof_stat; 54 int stat_offset; 55 }; 56 57 #define IXGBE_STAT(m) IXGBE_STATS, \ 58 sizeof(((struct ixgbe_adapter *)0)->m), \ 59 offsetof(struct ixgbe_adapter, m) 60 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 61 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 62 offsetof(struct rtnl_link_stats64, m) 63 64 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 73 {"lsc_int", IXGBE_STAT(lsc_int)}, 74 {"tx_busy", IXGBE_STAT(tx_busy)}, 75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 80 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 81 {"broadcast", IXGBE_STAT(stats.bprc)}, 82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 83 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 99 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 114 #ifdef IXGBE_FCOE 115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 123 #endif /* IXGBE_FCOE */ 124 }; 125 126 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 127 * we set the num_rx_queues to evaluate to num_tx_queues. This is 128 * used because we do not have a good way to get the max number of 129 * rx queues with CONFIG_RPS disabled. 130 */ 131 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 132 133 #define IXGBE_QUEUE_STATS_LEN ( \ 134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 136 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 137 #define IXGBE_PB_STATS_LEN ( \ 138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 142 / sizeof(u64)) 143 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 144 IXGBE_PB_STATS_LEN + \ 145 IXGBE_QUEUE_STATS_LEN) 146 147 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 148 "Register test (offline)", "Eeprom test (offline)", 149 "Interrupt test (offline)", "Loopback test (offline)", 150 "Link test (on/offline)" 151 }; 152 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 153 154 static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = { 155 #define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) 156 "legacy-rx", 157 }; 158 159 #define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings) 160 161 /* currently supported speeds for 10G */ 162 #define ADVRTSD_MSK_10G (SUPPORTED_10000baseT_Full | \ 163 SUPPORTED_10000baseKX4_Full | \ 164 SUPPORTED_10000baseKR_Full) 165 166 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane) 167 168 static u32 ixgbe_get_supported_10gtypes(struct ixgbe_hw *hw) 169 { 170 if (!ixgbe_isbackplane(hw->phy.media_type)) 171 return SUPPORTED_10000baseT_Full; 172 173 switch (hw->device_id) { 174 case IXGBE_DEV_ID_82598: 175 case IXGBE_DEV_ID_82599_KX4: 176 case IXGBE_DEV_ID_82599_KX4_MEZZ: 177 case IXGBE_DEV_ID_X550EM_X_KX4: 178 return SUPPORTED_10000baseKX4_Full; 179 case IXGBE_DEV_ID_82598_BX: 180 case IXGBE_DEV_ID_82599_KR: 181 case IXGBE_DEV_ID_X550EM_X_KR: 182 return SUPPORTED_10000baseKR_Full; 183 default: 184 return SUPPORTED_10000baseKX4_Full | 185 SUPPORTED_10000baseKR_Full; 186 } 187 } 188 189 static int ixgbe_get_link_ksettings(struct net_device *netdev, 190 struct ethtool_link_ksettings *cmd) 191 { 192 struct ixgbe_adapter *adapter = netdev_priv(netdev); 193 struct ixgbe_hw *hw = &adapter->hw; 194 ixgbe_link_speed supported_link; 195 bool autoneg = false; 196 u32 supported, advertising; 197 198 ethtool_convert_link_mode_to_legacy_u32(&supported, 199 cmd->link_modes.supported); 200 201 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 202 203 /* set the supported link speeds */ 204 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 205 supported |= ixgbe_get_supported_10gtypes(hw); 206 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 207 supported |= (ixgbe_isbackplane(hw->phy.media_type)) ? 208 SUPPORTED_1000baseKX_Full : 209 SUPPORTED_1000baseT_Full; 210 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 211 supported |= SUPPORTED_100baseT_Full; 212 if (supported_link & IXGBE_LINK_SPEED_10_FULL) 213 supported |= SUPPORTED_10baseT_Full; 214 215 /* default advertised speed if phy.autoneg_advertised isn't set */ 216 advertising = supported; 217 /* set the advertised speeds */ 218 if (hw->phy.autoneg_advertised) { 219 advertising = 0; 220 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) 221 advertising |= ADVERTISED_10baseT_Full; 222 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 223 advertising |= ADVERTISED_100baseT_Full; 224 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 225 advertising |= supported & ADVRTSD_MSK_10G; 226 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 227 if (supported & SUPPORTED_1000baseKX_Full) 228 advertising |= ADVERTISED_1000baseKX_Full; 229 else 230 advertising |= ADVERTISED_1000baseT_Full; 231 } 232 } else { 233 if (hw->phy.multispeed_fiber && !autoneg) { 234 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 235 advertising = ADVERTISED_10000baseT_Full; 236 } 237 } 238 239 if (autoneg) { 240 supported |= SUPPORTED_Autoneg; 241 advertising |= ADVERTISED_Autoneg; 242 cmd->base.autoneg = AUTONEG_ENABLE; 243 } else 244 cmd->base.autoneg = AUTONEG_DISABLE; 245 246 /* Determine the remaining settings based on the PHY type. */ 247 switch (adapter->hw.phy.type) { 248 case ixgbe_phy_tn: 249 case ixgbe_phy_aq: 250 case ixgbe_phy_x550em_ext_t: 251 case ixgbe_phy_fw: 252 case ixgbe_phy_cu_unknown: 253 supported |= SUPPORTED_TP; 254 advertising |= ADVERTISED_TP; 255 cmd->base.port = PORT_TP; 256 break; 257 case ixgbe_phy_qt: 258 supported |= SUPPORTED_FIBRE; 259 advertising |= ADVERTISED_FIBRE; 260 cmd->base.port = PORT_FIBRE; 261 break; 262 case ixgbe_phy_nl: 263 case ixgbe_phy_sfp_passive_tyco: 264 case ixgbe_phy_sfp_passive_unknown: 265 case ixgbe_phy_sfp_ftl: 266 case ixgbe_phy_sfp_avago: 267 case ixgbe_phy_sfp_intel: 268 case ixgbe_phy_sfp_unknown: 269 case ixgbe_phy_qsfp_passive_unknown: 270 case ixgbe_phy_qsfp_active_unknown: 271 case ixgbe_phy_qsfp_intel: 272 case ixgbe_phy_qsfp_unknown: 273 /* SFP+ devices, further checking needed */ 274 switch (adapter->hw.phy.sfp_type) { 275 case ixgbe_sfp_type_da_cu: 276 case ixgbe_sfp_type_da_cu_core0: 277 case ixgbe_sfp_type_da_cu_core1: 278 supported |= SUPPORTED_FIBRE; 279 advertising |= ADVERTISED_FIBRE; 280 cmd->base.port = PORT_DA; 281 break; 282 case ixgbe_sfp_type_sr: 283 case ixgbe_sfp_type_lr: 284 case ixgbe_sfp_type_srlr_core0: 285 case ixgbe_sfp_type_srlr_core1: 286 case ixgbe_sfp_type_1g_sx_core0: 287 case ixgbe_sfp_type_1g_sx_core1: 288 case ixgbe_sfp_type_1g_lx_core0: 289 case ixgbe_sfp_type_1g_lx_core1: 290 supported |= SUPPORTED_FIBRE; 291 advertising |= ADVERTISED_FIBRE; 292 cmd->base.port = PORT_FIBRE; 293 break; 294 case ixgbe_sfp_type_not_present: 295 supported |= SUPPORTED_FIBRE; 296 advertising |= ADVERTISED_FIBRE; 297 cmd->base.port = PORT_NONE; 298 break; 299 case ixgbe_sfp_type_1g_cu_core0: 300 case ixgbe_sfp_type_1g_cu_core1: 301 supported |= SUPPORTED_TP; 302 advertising |= ADVERTISED_TP; 303 cmd->base.port = PORT_TP; 304 break; 305 case ixgbe_sfp_type_unknown: 306 default: 307 supported |= SUPPORTED_FIBRE; 308 advertising |= ADVERTISED_FIBRE; 309 cmd->base.port = PORT_OTHER; 310 break; 311 } 312 break; 313 case ixgbe_phy_xaui: 314 supported |= SUPPORTED_FIBRE; 315 advertising |= ADVERTISED_FIBRE; 316 cmd->base.port = PORT_NONE; 317 break; 318 case ixgbe_phy_unknown: 319 case ixgbe_phy_generic: 320 case ixgbe_phy_sfp_unsupported: 321 default: 322 supported |= SUPPORTED_FIBRE; 323 advertising |= ADVERTISED_FIBRE; 324 cmd->base.port = PORT_OTHER; 325 break; 326 } 327 328 /* Indicate pause support */ 329 supported |= SUPPORTED_Pause; 330 331 switch (hw->fc.requested_mode) { 332 case ixgbe_fc_full: 333 advertising |= ADVERTISED_Pause; 334 break; 335 case ixgbe_fc_rx_pause: 336 advertising |= ADVERTISED_Pause | 337 ADVERTISED_Asym_Pause; 338 break; 339 case ixgbe_fc_tx_pause: 340 advertising |= ADVERTISED_Asym_Pause; 341 break; 342 default: 343 advertising &= ~(ADVERTISED_Pause | 344 ADVERTISED_Asym_Pause); 345 } 346 347 if (netif_carrier_ok(netdev)) { 348 switch (adapter->link_speed) { 349 case IXGBE_LINK_SPEED_10GB_FULL: 350 cmd->base.speed = SPEED_10000; 351 break; 352 case IXGBE_LINK_SPEED_5GB_FULL: 353 cmd->base.speed = SPEED_5000; 354 break; 355 case IXGBE_LINK_SPEED_2_5GB_FULL: 356 cmd->base.speed = SPEED_2500; 357 break; 358 case IXGBE_LINK_SPEED_1GB_FULL: 359 cmd->base.speed = SPEED_1000; 360 break; 361 case IXGBE_LINK_SPEED_100_FULL: 362 cmd->base.speed = SPEED_100; 363 break; 364 case IXGBE_LINK_SPEED_10_FULL: 365 cmd->base.speed = SPEED_10; 366 break; 367 default: 368 break; 369 } 370 cmd->base.duplex = DUPLEX_FULL; 371 } else { 372 cmd->base.speed = SPEED_UNKNOWN; 373 cmd->base.duplex = DUPLEX_UNKNOWN; 374 } 375 376 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 377 supported); 378 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 379 advertising); 380 381 return 0; 382 } 383 384 static int ixgbe_set_link_ksettings(struct net_device *netdev, 385 const struct ethtool_link_ksettings *cmd) 386 { 387 struct ixgbe_adapter *adapter = netdev_priv(netdev); 388 struct ixgbe_hw *hw = &adapter->hw; 389 u32 advertised, old; 390 s32 err = 0; 391 u32 supported, advertising; 392 393 ethtool_convert_link_mode_to_legacy_u32(&supported, 394 cmd->link_modes.supported); 395 ethtool_convert_link_mode_to_legacy_u32(&advertising, 396 cmd->link_modes.advertising); 397 398 if ((hw->phy.media_type == ixgbe_media_type_copper) || 399 (hw->phy.multispeed_fiber)) { 400 /* 401 * this function does not support duplex forcing, but can 402 * limit the advertising of the adapter to the specified speed 403 */ 404 if (advertising & ~supported) 405 return -EINVAL; 406 407 /* only allow one speed at a time if no autoneg */ 408 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { 409 if (advertising == 410 (ADVERTISED_10000baseT_Full | 411 ADVERTISED_1000baseT_Full)) 412 return -EINVAL; 413 } 414 415 old = hw->phy.autoneg_advertised; 416 advertised = 0; 417 if (advertising & ADVERTISED_10000baseT_Full) 418 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 419 420 if (advertising & ADVERTISED_1000baseT_Full) 421 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 422 423 if (advertising & ADVERTISED_100baseT_Full) 424 advertised |= IXGBE_LINK_SPEED_100_FULL; 425 426 if (advertising & ADVERTISED_10baseT_Full) 427 advertised |= IXGBE_LINK_SPEED_10_FULL; 428 429 if (old == advertised) 430 return err; 431 /* this sets the link speed and restarts auto-neg */ 432 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 433 usleep_range(1000, 2000); 434 435 hw->mac.autotry_restart = true; 436 err = hw->mac.ops.setup_link(hw, advertised, true); 437 if (err) { 438 e_info(probe, "setup link failed with code %d\n", err); 439 hw->mac.ops.setup_link(hw, old, true); 440 } 441 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 442 } else { 443 /* in this case we currently only support 10Gb/FULL */ 444 u32 speed = cmd->base.speed; 445 446 if ((cmd->base.autoneg == AUTONEG_ENABLE) || 447 (advertising != ADVERTISED_10000baseT_Full) || 448 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) 449 return -EINVAL; 450 } 451 452 return err; 453 } 454 455 static void ixgbe_get_pauseparam(struct net_device *netdev, 456 struct ethtool_pauseparam *pause) 457 { 458 struct ixgbe_adapter *adapter = netdev_priv(netdev); 459 struct ixgbe_hw *hw = &adapter->hw; 460 461 if (ixgbe_device_supports_autoneg_fc(hw) && 462 !hw->fc.disable_fc_autoneg) 463 pause->autoneg = 1; 464 else 465 pause->autoneg = 0; 466 467 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 468 pause->rx_pause = 1; 469 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 470 pause->tx_pause = 1; 471 } else if (hw->fc.current_mode == ixgbe_fc_full) { 472 pause->rx_pause = 1; 473 pause->tx_pause = 1; 474 } 475 } 476 477 static int ixgbe_set_pauseparam(struct net_device *netdev, 478 struct ethtool_pauseparam *pause) 479 { 480 struct ixgbe_adapter *adapter = netdev_priv(netdev); 481 struct ixgbe_hw *hw = &adapter->hw; 482 struct ixgbe_fc_info fc = hw->fc; 483 484 /* 82598 does no support link flow control with DCB enabled */ 485 if ((hw->mac.type == ixgbe_mac_82598EB) && 486 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 487 return -EINVAL; 488 489 /* some devices do not support autoneg of link flow control */ 490 if ((pause->autoneg == AUTONEG_ENABLE) && 491 !ixgbe_device_supports_autoneg_fc(hw)) 492 return -EINVAL; 493 494 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 495 496 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 497 fc.requested_mode = ixgbe_fc_full; 498 else if (pause->rx_pause && !pause->tx_pause) 499 fc.requested_mode = ixgbe_fc_rx_pause; 500 else if (!pause->rx_pause && pause->tx_pause) 501 fc.requested_mode = ixgbe_fc_tx_pause; 502 else 503 fc.requested_mode = ixgbe_fc_none; 504 505 /* if the thing changed then we'll update and use new autoneg */ 506 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 507 hw->fc = fc; 508 if (netif_running(netdev)) 509 ixgbe_reinit_locked(adapter); 510 else 511 ixgbe_reset(adapter); 512 } 513 514 return 0; 515 } 516 517 static u32 ixgbe_get_msglevel(struct net_device *netdev) 518 { 519 struct ixgbe_adapter *adapter = netdev_priv(netdev); 520 return adapter->msg_enable; 521 } 522 523 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 524 { 525 struct ixgbe_adapter *adapter = netdev_priv(netdev); 526 adapter->msg_enable = data; 527 } 528 529 static int ixgbe_get_regs_len(struct net_device *netdev) 530 { 531 #define IXGBE_REGS_LEN 1139 532 return IXGBE_REGS_LEN * sizeof(u32); 533 } 534 535 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 536 537 static void ixgbe_get_regs(struct net_device *netdev, 538 struct ethtool_regs *regs, void *p) 539 { 540 struct ixgbe_adapter *adapter = netdev_priv(netdev); 541 struct ixgbe_hw *hw = &adapter->hw; 542 u32 *regs_buff = p; 543 u8 i; 544 545 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 546 547 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 548 hw->device_id; 549 550 /* General Registers */ 551 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 552 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 553 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 554 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 555 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 556 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 557 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 558 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 559 560 /* NVM Register */ 561 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 562 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 563 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 564 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 565 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 566 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 567 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 568 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 569 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 570 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 571 572 /* Interrupt */ 573 /* don't read EICR because it can clear interrupt causes, instead 574 * read EICS which is a shadow but doesn't clear EICR */ 575 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 576 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 577 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 578 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 579 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 580 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 581 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 582 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 583 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 584 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 585 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 586 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 587 588 /* Flow Control */ 589 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 590 for (i = 0; i < 4; i++) 591 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i)); 592 for (i = 0; i < 8; i++) { 593 switch (hw->mac.type) { 594 case ixgbe_mac_82598EB: 595 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 596 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 597 break; 598 case ixgbe_mac_82599EB: 599 case ixgbe_mac_X540: 600 case ixgbe_mac_X550: 601 case ixgbe_mac_X550EM_x: 602 case ixgbe_mac_x550em_a: 603 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 604 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 605 break; 606 default: 607 break; 608 } 609 } 610 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 611 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 612 613 /* Receive DMA */ 614 for (i = 0; i < 64; i++) 615 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 616 for (i = 0; i < 64; i++) 617 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 618 for (i = 0; i < 64; i++) 619 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 620 for (i = 0; i < 64; i++) 621 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 622 for (i = 0; i < 64; i++) 623 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 624 for (i = 0; i < 64; i++) 625 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 626 for (i = 0; i < 16; i++) 627 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 628 for (i = 0; i < 16; i++) 629 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 630 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 631 for (i = 0; i < 8; i++) 632 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 633 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 634 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 635 636 /* Receive */ 637 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 638 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 639 for (i = 0; i < 16; i++) 640 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 641 for (i = 0; i < 16; i++) 642 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 643 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 644 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 645 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 646 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 647 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 648 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 649 for (i = 0; i < 8; i++) 650 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 651 for (i = 0; i < 8; i++) 652 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 653 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 654 655 /* Transmit */ 656 for (i = 0; i < 32; i++) 657 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 658 for (i = 0; i < 32; i++) 659 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 660 for (i = 0; i < 32; i++) 661 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 662 for (i = 0; i < 32; i++) 663 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 664 for (i = 0; i < 32; i++) 665 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 666 for (i = 0; i < 32; i++) 667 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 668 for (i = 0; i < 32; i++) 669 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 670 for (i = 0; i < 32; i++) 671 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 672 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 673 for (i = 0; i < 16; i++) 674 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 675 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 676 for (i = 0; i < 8; i++) 677 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 678 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 679 680 /* Wake Up */ 681 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 682 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 683 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 684 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 685 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 686 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 687 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 688 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 689 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 690 691 /* DCB */ 692 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 693 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 694 695 switch (hw->mac.type) { 696 case ixgbe_mac_82598EB: 697 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 698 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 699 for (i = 0; i < 8; i++) 700 regs_buff[833 + i] = 701 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 702 for (i = 0; i < 8; i++) 703 regs_buff[841 + i] = 704 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 705 for (i = 0; i < 8; i++) 706 regs_buff[849 + i] = 707 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 708 for (i = 0; i < 8; i++) 709 regs_buff[857 + i] = 710 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 711 break; 712 case ixgbe_mac_82599EB: 713 case ixgbe_mac_X540: 714 case ixgbe_mac_X550: 715 case ixgbe_mac_X550EM_x: 716 case ixgbe_mac_x550em_a: 717 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 718 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 719 for (i = 0; i < 8; i++) 720 regs_buff[833 + i] = 721 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 722 for (i = 0; i < 8; i++) 723 regs_buff[841 + i] = 724 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 725 for (i = 0; i < 8; i++) 726 regs_buff[849 + i] = 727 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 728 for (i = 0; i < 8; i++) 729 regs_buff[857 + i] = 730 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 731 break; 732 default: 733 break; 734 } 735 736 for (i = 0; i < 8; i++) 737 regs_buff[865 + i] = 738 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 739 for (i = 0; i < 8; i++) 740 regs_buff[873 + i] = 741 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 742 743 /* Statistics */ 744 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 745 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 746 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 747 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 748 for (i = 0; i < 8; i++) 749 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 750 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 751 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 752 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 753 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 754 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 755 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 756 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 757 for (i = 0; i < 8; i++) 758 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 759 for (i = 0; i < 8; i++) 760 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 761 for (i = 0; i < 8; i++) 762 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 763 for (i = 0; i < 8; i++) 764 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 765 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 766 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 767 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 768 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 769 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 770 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 771 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 772 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 773 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 774 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 775 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc); 776 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32); 777 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc); 778 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32); 779 for (i = 0; i < 8; i++) 780 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 781 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 782 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 783 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 784 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 785 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 786 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 787 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 788 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor); 789 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32); 790 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 791 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 792 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 793 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 794 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 795 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 796 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 797 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 798 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 799 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 800 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 801 for (i = 0; i < 16; i++) 802 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 803 for (i = 0; i < 16; i++) 804 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 805 for (i = 0; i < 16; i++) 806 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 807 for (i = 0; i < 16; i++) 808 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 809 810 /* MAC */ 811 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 812 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 813 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 814 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 815 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 816 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 817 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 818 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 819 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 820 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 821 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 822 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 823 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 824 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 825 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 826 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 827 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 828 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 829 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 830 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 831 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 832 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 833 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 834 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 835 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 836 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 837 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 838 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 839 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 840 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 841 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 842 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 843 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 844 845 /* Diagnostic */ 846 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 847 for (i = 0; i < 8; i++) 848 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 849 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 850 for (i = 0; i < 4; i++) 851 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 852 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 853 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 854 for (i = 0; i < 8; i++) 855 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 856 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 857 for (i = 0; i < 4; i++) 858 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 859 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 860 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 861 for (i = 0; i < 4; i++) 862 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i)); 863 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 864 for (i = 0; i < 4; i++) 865 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i)); 866 for (i = 0; i < 8; i++) 867 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 868 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 869 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 870 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 871 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 872 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 873 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 874 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 875 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 876 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 877 878 /* 82599 X540 specific registers */ 879 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 880 881 /* 82599 X540 specific DCB registers */ 882 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 883 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 884 for (i = 0; i < 4; i++) 885 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 886 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 887 /* same as RTTQCNRM */ 888 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 889 /* same as RTTQCNRR */ 890 891 /* X540 specific DCB registers */ 892 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 893 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 894 } 895 896 static int ixgbe_get_eeprom_len(struct net_device *netdev) 897 { 898 struct ixgbe_adapter *adapter = netdev_priv(netdev); 899 return adapter->hw.eeprom.word_size * 2; 900 } 901 902 static int ixgbe_get_eeprom(struct net_device *netdev, 903 struct ethtool_eeprom *eeprom, u8 *bytes) 904 { 905 struct ixgbe_adapter *adapter = netdev_priv(netdev); 906 struct ixgbe_hw *hw = &adapter->hw; 907 u16 *eeprom_buff; 908 int first_word, last_word, eeprom_len; 909 int ret_val = 0; 910 u16 i; 911 912 if (eeprom->len == 0) 913 return -EINVAL; 914 915 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 916 917 first_word = eeprom->offset >> 1; 918 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 919 eeprom_len = last_word - first_word + 1; 920 921 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); 922 if (!eeprom_buff) 923 return -ENOMEM; 924 925 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 926 eeprom_buff); 927 928 /* Device's eeprom is always little-endian, word addressable */ 929 for (i = 0; i < eeprom_len; i++) 930 le16_to_cpus(&eeprom_buff[i]); 931 932 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 933 kfree(eeprom_buff); 934 935 return ret_val; 936 } 937 938 static int ixgbe_set_eeprom(struct net_device *netdev, 939 struct ethtool_eeprom *eeprom, u8 *bytes) 940 { 941 struct ixgbe_adapter *adapter = netdev_priv(netdev); 942 struct ixgbe_hw *hw = &adapter->hw; 943 u16 *eeprom_buff; 944 void *ptr; 945 int max_len, first_word, last_word, ret_val = 0; 946 u16 i; 947 948 if (eeprom->len == 0) 949 return -EINVAL; 950 951 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 952 return -EINVAL; 953 954 max_len = hw->eeprom.word_size * 2; 955 956 first_word = eeprom->offset >> 1; 957 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 958 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 959 if (!eeprom_buff) 960 return -ENOMEM; 961 962 ptr = eeprom_buff; 963 964 if (eeprom->offset & 1) { 965 /* 966 * need read/modify/write of first changed EEPROM word 967 * only the second byte of the word is being modified 968 */ 969 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 970 if (ret_val) 971 goto err; 972 973 ptr++; 974 } 975 if ((eeprom->offset + eeprom->len) & 1) { 976 /* 977 * need read/modify/write of last changed EEPROM word 978 * only the first byte of the word is being modified 979 */ 980 ret_val = hw->eeprom.ops.read(hw, last_word, 981 &eeprom_buff[last_word - first_word]); 982 if (ret_val) 983 goto err; 984 } 985 986 /* Device's eeprom is always little-endian, word addressable */ 987 for (i = 0; i < last_word - first_word + 1; i++) 988 le16_to_cpus(&eeprom_buff[i]); 989 990 memcpy(ptr, bytes, eeprom->len); 991 992 for (i = 0; i < last_word - first_word + 1; i++) 993 cpu_to_le16s(&eeprom_buff[i]); 994 995 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 996 last_word - first_word + 1, 997 eeprom_buff); 998 999 /* Update the checksum */ 1000 if (ret_val == 0) 1001 hw->eeprom.ops.update_checksum(hw); 1002 1003 err: 1004 kfree(eeprom_buff); 1005 return ret_val; 1006 } 1007 1008 static void ixgbe_get_drvinfo(struct net_device *netdev, 1009 struct ethtool_drvinfo *drvinfo) 1010 { 1011 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1012 u32 nvm_track_id; 1013 1014 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 1015 strlcpy(drvinfo->version, ixgbe_driver_version, 1016 sizeof(drvinfo->version)); 1017 1018 nvm_track_id = (adapter->eeprom_verh << 16) | 1019 adapter->eeprom_verl; 1020 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x", 1021 nvm_track_id); 1022 1023 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 1024 sizeof(drvinfo->bus_info)); 1025 1026 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN; 1027 } 1028 1029 static void ixgbe_get_ringparam(struct net_device *netdev, 1030 struct ethtool_ringparam *ring) 1031 { 1032 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1033 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 1034 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 1035 1036 ring->rx_max_pending = IXGBE_MAX_RXD; 1037 ring->tx_max_pending = IXGBE_MAX_TXD; 1038 ring->rx_pending = rx_ring->count; 1039 ring->tx_pending = tx_ring->count; 1040 } 1041 1042 static int ixgbe_set_ringparam(struct net_device *netdev, 1043 struct ethtool_ringparam *ring) 1044 { 1045 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1046 struct ixgbe_ring *temp_ring; 1047 int i, err = 0; 1048 u32 new_rx_count, new_tx_count; 1049 1050 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 1051 return -EINVAL; 1052 1053 new_tx_count = clamp_t(u32, ring->tx_pending, 1054 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 1055 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 1056 1057 new_rx_count = clamp_t(u32, ring->rx_pending, 1058 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 1059 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 1060 1061 if ((new_tx_count == adapter->tx_ring_count) && 1062 (new_rx_count == adapter->rx_ring_count)) { 1063 /* nothing to do */ 1064 return 0; 1065 } 1066 1067 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 1068 usleep_range(1000, 2000); 1069 1070 if (!netif_running(adapter->netdev)) { 1071 for (i = 0; i < adapter->num_tx_queues; i++) 1072 adapter->tx_ring[i]->count = new_tx_count; 1073 for (i = 0; i < adapter->num_rx_queues; i++) 1074 adapter->rx_ring[i]->count = new_rx_count; 1075 adapter->tx_ring_count = new_tx_count; 1076 adapter->rx_ring_count = new_rx_count; 1077 goto clear_reset; 1078 } 1079 1080 /* allocate temporary buffer to store rings in */ 1081 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues); 1082 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring)); 1083 1084 if (!temp_ring) { 1085 err = -ENOMEM; 1086 goto clear_reset; 1087 } 1088 1089 ixgbe_down(adapter); 1090 1091 /* 1092 * Setup new Tx resources and free the old Tx resources in that order. 1093 * We can then assign the new resources to the rings via a memcpy. 1094 * The advantage to this approach is that we are guaranteed to still 1095 * have resources even in the case of an allocation failure. 1096 */ 1097 if (new_tx_count != adapter->tx_ring_count) { 1098 for (i = 0; i < adapter->num_tx_queues; i++) { 1099 memcpy(&temp_ring[i], adapter->tx_ring[i], 1100 sizeof(struct ixgbe_ring)); 1101 1102 temp_ring[i].count = new_tx_count; 1103 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1104 if (err) { 1105 while (i) { 1106 i--; 1107 ixgbe_free_tx_resources(&temp_ring[i]); 1108 } 1109 goto err_setup; 1110 } 1111 } 1112 1113 for (i = 0; i < adapter->num_tx_queues; i++) { 1114 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1115 1116 memcpy(adapter->tx_ring[i], &temp_ring[i], 1117 sizeof(struct ixgbe_ring)); 1118 } 1119 1120 adapter->tx_ring_count = new_tx_count; 1121 } 1122 1123 /* Repeat the process for the Rx rings if needed */ 1124 if (new_rx_count != adapter->rx_ring_count) { 1125 for (i = 0; i < adapter->num_rx_queues; i++) { 1126 memcpy(&temp_ring[i], adapter->rx_ring[i], 1127 sizeof(struct ixgbe_ring)); 1128 1129 temp_ring[i].count = new_rx_count; 1130 err = ixgbe_setup_rx_resources(&temp_ring[i]); 1131 if (err) { 1132 while (i) { 1133 i--; 1134 ixgbe_free_rx_resources(&temp_ring[i]); 1135 } 1136 goto err_setup; 1137 } 1138 1139 } 1140 1141 for (i = 0; i < adapter->num_rx_queues; i++) { 1142 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1143 1144 memcpy(adapter->rx_ring[i], &temp_ring[i], 1145 sizeof(struct ixgbe_ring)); 1146 } 1147 1148 adapter->rx_ring_count = new_rx_count; 1149 } 1150 1151 err_setup: 1152 ixgbe_up(adapter); 1153 vfree(temp_ring); 1154 clear_reset: 1155 clear_bit(__IXGBE_RESETTING, &adapter->state); 1156 return err; 1157 } 1158 1159 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1160 { 1161 switch (sset) { 1162 case ETH_SS_TEST: 1163 return IXGBE_TEST_LEN; 1164 case ETH_SS_STATS: 1165 return IXGBE_STATS_LEN; 1166 case ETH_SS_PRIV_FLAGS: 1167 return IXGBE_PRIV_FLAGS_STR_LEN; 1168 default: 1169 return -EOPNOTSUPP; 1170 } 1171 } 1172 1173 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1174 struct ethtool_stats *stats, u64 *data) 1175 { 1176 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1177 struct rtnl_link_stats64 temp; 1178 const struct rtnl_link_stats64 *net_stats; 1179 unsigned int start; 1180 struct ixgbe_ring *ring; 1181 int i, j; 1182 char *p = NULL; 1183 1184 ixgbe_update_stats(adapter); 1185 net_stats = dev_get_stats(netdev, &temp); 1186 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1187 switch (ixgbe_gstrings_stats[i].type) { 1188 case NETDEV_STATS: 1189 p = (char *) net_stats + 1190 ixgbe_gstrings_stats[i].stat_offset; 1191 break; 1192 case IXGBE_STATS: 1193 p = (char *) adapter + 1194 ixgbe_gstrings_stats[i].stat_offset; 1195 break; 1196 default: 1197 data[i] = 0; 1198 continue; 1199 } 1200 1201 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1202 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1203 } 1204 for (j = 0; j < netdev->num_tx_queues; j++) { 1205 ring = adapter->tx_ring[j]; 1206 if (!ring) { 1207 data[i] = 0; 1208 data[i+1] = 0; 1209 i += 2; 1210 continue; 1211 } 1212 1213 do { 1214 start = u64_stats_fetch_begin_irq(&ring->syncp); 1215 data[i] = ring->stats.packets; 1216 data[i+1] = ring->stats.bytes; 1217 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1218 i += 2; 1219 } 1220 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1221 ring = adapter->rx_ring[j]; 1222 if (!ring) { 1223 data[i] = 0; 1224 data[i+1] = 0; 1225 i += 2; 1226 continue; 1227 } 1228 1229 do { 1230 start = u64_stats_fetch_begin_irq(&ring->syncp); 1231 data[i] = ring->stats.packets; 1232 data[i+1] = ring->stats.bytes; 1233 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1234 i += 2; 1235 } 1236 1237 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1238 data[i++] = adapter->stats.pxontxc[j]; 1239 data[i++] = adapter->stats.pxofftxc[j]; 1240 } 1241 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1242 data[i++] = adapter->stats.pxonrxc[j]; 1243 data[i++] = adapter->stats.pxoffrxc[j]; 1244 } 1245 } 1246 1247 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1248 u8 *data) 1249 { 1250 char *p = (char *)data; 1251 int i; 1252 1253 switch (stringset) { 1254 case ETH_SS_TEST: 1255 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1256 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1257 data += ETH_GSTRING_LEN; 1258 } 1259 break; 1260 case ETH_SS_STATS: 1261 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1262 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1263 ETH_GSTRING_LEN); 1264 p += ETH_GSTRING_LEN; 1265 } 1266 for (i = 0; i < netdev->num_tx_queues; i++) { 1267 sprintf(p, "tx_queue_%u_packets", i); 1268 p += ETH_GSTRING_LEN; 1269 sprintf(p, "tx_queue_%u_bytes", i); 1270 p += ETH_GSTRING_LEN; 1271 } 1272 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1273 sprintf(p, "rx_queue_%u_packets", i); 1274 p += ETH_GSTRING_LEN; 1275 sprintf(p, "rx_queue_%u_bytes", i); 1276 p += ETH_GSTRING_LEN; 1277 } 1278 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1279 sprintf(p, "tx_pb_%u_pxon", i); 1280 p += ETH_GSTRING_LEN; 1281 sprintf(p, "tx_pb_%u_pxoff", i); 1282 p += ETH_GSTRING_LEN; 1283 } 1284 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1285 sprintf(p, "rx_pb_%u_pxon", i); 1286 p += ETH_GSTRING_LEN; 1287 sprintf(p, "rx_pb_%u_pxoff", i); 1288 p += ETH_GSTRING_LEN; 1289 } 1290 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1291 break; 1292 case ETH_SS_PRIV_FLAGS: 1293 memcpy(data, ixgbe_priv_flags_strings, 1294 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 1295 } 1296 } 1297 1298 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1299 { 1300 struct ixgbe_hw *hw = &adapter->hw; 1301 bool link_up; 1302 u32 link_speed = 0; 1303 1304 if (ixgbe_removed(hw->hw_addr)) { 1305 *data = 1; 1306 return 1; 1307 } 1308 *data = 0; 1309 1310 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1311 if (link_up) 1312 return *data; 1313 else 1314 *data = 1; 1315 return *data; 1316 } 1317 1318 /* ethtool register test data */ 1319 struct ixgbe_reg_test { 1320 u16 reg; 1321 u8 array_len; 1322 u8 test_type; 1323 u32 mask; 1324 u32 write; 1325 }; 1326 1327 /* In the hardware, registers are laid out either singly, in arrays 1328 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1329 * most tests take place on arrays or single registers (handled 1330 * as a single-element array) and special-case the tables. 1331 * Table tests are always pattern tests. 1332 * 1333 * We also make provision for some required setup steps by specifying 1334 * registers to be written without any read-back testing. 1335 */ 1336 1337 #define PATTERN_TEST 1 1338 #define SET_READ_TEST 2 1339 #define WRITE_NO_TEST 3 1340 #define TABLE32_TEST 4 1341 #define TABLE64_TEST_LO 5 1342 #define TABLE64_TEST_HI 6 1343 1344 /* default 82599 register test */ 1345 static const struct ixgbe_reg_test reg_test_82599[] = { 1346 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1347 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1348 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1349 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1350 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1351 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1352 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1353 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1354 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1355 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1356 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1357 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1358 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1359 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1360 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1361 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1362 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1363 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1364 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1365 { .reg = 0 } 1366 }; 1367 1368 /* default 82598 register test */ 1369 static const struct ixgbe_reg_test reg_test_82598[] = { 1370 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1371 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1372 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1373 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1374 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1375 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1376 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1377 /* Enable all four RX queues before testing. */ 1378 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1379 /* RDH is read-only for 82598, only test RDT. */ 1380 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1381 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1382 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1383 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1384 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1385 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1386 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1387 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1388 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1389 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1390 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1391 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1392 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1393 { .reg = 0 } 1394 }; 1395 1396 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1397 u32 mask, u32 write) 1398 { 1399 u32 pat, val, before; 1400 static const u32 test_pattern[] = { 1401 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1402 1403 if (ixgbe_removed(adapter->hw.hw_addr)) { 1404 *data = 1; 1405 return true; 1406 } 1407 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1408 before = ixgbe_read_reg(&adapter->hw, reg); 1409 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1410 val = ixgbe_read_reg(&adapter->hw, reg); 1411 if (val != (test_pattern[pat] & write & mask)) { 1412 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1413 reg, val, (test_pattern[pat] & write & mask)); 1414 *data = reg; 1415 ixgbe_write_reg(&adapter->hw, reg, before); 1416 return true; 1417 } 1418 ixgbe_write_reg(&adapter->hw, reg, before); 1419 } 1420 return false; 1421 } 1422 1423 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1424 u32 mask, u32 write) 1425 { 1426 u32 val, before; 1427 1428 if (ixgbe_removed(adapter->hw.hw_addr)) { 1429 *data = 1; 1430 return true; 1431 } 1432 before = ixgbe_read_reg(&adapter->hw, reg); 1433 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1434 val = ixgbe_read_reg(&adapter->hw, reg); 1435 if ((write & mask) != (val & mask)) { 1436 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1437 reg, (val & mask), (write & mask)); 1438 *data = reg; 1439 ixgbe_write_reg(&adapter->hw, reg, before); 1440 return true; 1441 } 1442 ixgbe_write_reg(&adapter->hw, reg, before); 1443 return false; 1444 } 1445 1446 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1447 { 1448 const struct ixgbe_reg_test *test; 1449 u32 value, before, after; 1450 u32 i, toggle; 1451 1452 if (ixgbe_removed(adapter->hw.hw_addr)) { 1453 e_err(drv, "Adapter removed - register test blocked\n"); 1454 *data = 1; 1455 return 1; 1456 } 1457 switch (adapter->hw.mac.type) { 1458 case ixgbe_mac_82598EB: 1459 toggle = 0x7FFFF3FF; 1460 test = reg_test_82598; 1461 break; 1462 case ixgbe_mac_82599EB: 1463 case ixgbe_mac_X540: 1464 case ixgbe_mac_X550: 1465 case ixgbe_mac_X550EM_x: 1466 case ixgbe_mac_x550em_a: 1467 toggle = 0x7FFFF30F; 1468 test = reg_test_82599; 1469 break; 1470 default: 1471 *data = 1; 1472 return 1; 1473 } 1474 1475 /* 1476 * Because the status register is such a special case, 1477 * we handle it separately from the rest of the register 1478 * tests. Some bits are read-only, some toggle, and some 1479 * are writeable on newer MACs. 1480 */ 1481 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1482 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1483 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1484 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1485 if (value != after) { 1486 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1487 after, value); 1488 *data = 1; 1489 return 1; 1490 } 1491 /* restore previous status */ 1492 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1493 1494 /* 1495 * Perform the remainder of the register test, looping through 1496 * the test table until we either fail or reach the null entry. 1497 */ 1498 while (test->reg) { 1499 for (i = 0; i < test->array_len; i++) { 1500 bool b = false; 1501 1502 switch (test->test_type) { 1503 case PATTERN_TEST: 1504 b = reg_pattern_test(adapter, data, 1505 test->reg + (i * 0x40), 1506 test->mask, 1507 test->write); 1508 break; 1509 case SET_READ_TEST: 1510 b = reg_set_and_check(adapter, data, 1511 test->reg + (i * 0x40), 1512 test->mask, 1513 test->write); 1514 break; 1515 case WRITE_NO_TEST: 1516 ixgbe_write_reg(&adapter->hw, 1517 test->reg + (i * 0x40), 1518 test->write); 1519 break; 1520 case TABLE32_TEST: 1521 b = reg_pattern_test(adapter, data, 1522 test->reg + (i * 4), 1523 test->mask, 1524 test->write); 1525 break; 1526 case TABLE64_TEST_LO: 1527 b = reg_pattern_test(adapter, data, 1528 test->reg + (i * 8), 1529 test->mask, 1530 test->write); 1531 break; 1532 case TABLE64_TEST_HI: 1533 b = reg_pattern_test(adapter, data, 1534 (test->reg + 4) + (i * 8), 1535 test->mask, 1536 test->write); 1537 break; 1538 } 1539 if (b) 1540 return 1; 1541 } 1542 test++; 1543 } 1544 1545 *data = 0; 1546 return 0; 1547 } 1548 1549 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1550 { 1551 struct ixgbe_hw *hw = &adapter->hw; 1552 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1553 *data = 1; 1554 else 1555 *data = 0; 1556 return *data; 1557 } 1558 1559 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1560 { 1561 struct net_device *netdev = (struct net_device *) data; 1562 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1563 1564 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1565 1566 return IRQ_HANDLED; 1567 } 1568 1569 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1570 { 1571 struct net_device *netdev = adapter->netdev; 1572 u32 mask, i = 0, shared_int = true; 1573 u32 irq = adapter->pdev->irq; 1574 1575 *data = 0; 1576 1577 /* Hook up test interrupt handler just for this test */ 1578 if (adapter->msix_entries) { 1579 /* NOTE: we don't test MSI-X interrupts here, yet */ 1580 return 0; 1581 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1582 shared_int = false; 1583 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1584 netdev)) { 1585 *data = 1; 1586 return -1; 1587 } 1588 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1589 netdev->name, netdev)) { 1590 shared_int = false; 1591 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1592 netdev->name, netdev)) { 1593 *data = 1; 1594 return -1; 1595 } 1596 e_info(hw, "testing %s interrupt\n", shared_int ? 1597 "shared" : "unshared"); 1598 1599 /* Disable all the interrupts */ 1600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1601 IXGBE_WRITE_FLUSH(&adapter->hw); 1602 usleep_range(10000, 20000); 1603 1604 /* Test each interrupt */ 1605 for (; i < 10; i++) { 1606 /* Interrupt to test */ 1607 mask = BIT(i); 1608 1609 if (!shared_int) { 1610 /* 1611 * Disable the interrupts to be reported in 1612 * the cause register and then force the same 1613 * interrupt and see if one gets posted. If 1614 * an interrupt was posted to the bus, the 1615 * test failed. 1616 */ 1617 adapter->test_icr = 0; 1618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1619 ~mask & 0x00007FFF); 1620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1621 ~mask & 0x00007FFF); 1622 IXGBE_WRITE_FLUSH(&adapter->hw); 1623 usleep_range(10000, 20000); 1624 1625 if (adapter->test_icr & mask) { 1626 *data = 3; 1627 break; 1628 } 1629 } 1630 1631 /* 1632 * Enable the interrupt to be reported in the cause 1633 * register and then force the same interrupt and see 1634 * if one gets posted. If an interrupt was not posted 1635 * to the bus, the test failed. 1636 */ 1637 adapter->test_icr = 0; 1638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1640 IXGBE_WRITE_FLUSH(&adapter->hw); 1641 usleep_range(10000, 20000); 1642 1643 if (!(adapter->test_icr & mask)) { 1644 *data = 4; 1645 break; 1646 } 1647 1648 if (!shared_int) { 1649 /* 1650 * Disable the other interrupts to be reported in 1651 * the cause register and then force the other 1652 * interrupts and see if any get posted. If 1653 * an interrupt was posted to the bus, the 1654 * test failed. 1655 */ 1656 adapter->test_icr = 0; 1657 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1658 ~mask & 0x00007FFF); 1659 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1660 ~mask & 0x00007FFF); 1661 IXGBE_WRITE_FLUSH(&adapter->hw); 1662 usleep_range(10000, 20000); 1663 1664 if (adapter->test_icr) { 1665 *data = 5; 1666 break; 1667 } 1668 } 1669 } 1670 1671 /* Disable all the interrupts */ 1672 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1673 IXGBE_WRITE_FLUSH(&adapter->hw); 1674 usleep_range(10000, 20000); 1675 1676 /* Unhook test interrupt handler */ 1677 free_irq(irq, netdev); 1678 1679 return *data; 1680 } 1681 1682 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1683 { 1684 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1685 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1686 struct ixgbe_hw *hw = &adapter->hw; 1687 u32 reg_ctl; 1688 1689 /* shut down the DMA engines now so they can be reinitialized later */ 1690 1691 /* first Rx */ 1692 hw->mac.ops.disable_rx(hw); 1693 ixgbe_disable_rx_queue(adapter, rx_ring); 1694 1695 /* now Tx */ 1696 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); 1697 reg_ctl &= ~IXGBE_TXDCTL_ENABLE; 1698 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); 1699 1700 switch (hw->mac.type) { 1701 case ixgbe_mac_82599EB: 1702 case ixgbe_mac_X540: 1703 case ixgbe_mac_X550: 1704 case ixgbe_mac_X550EM_x: 1705 case ixgbe_mac_x550em_a: 1706 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1707 reg_ctl &= ~IXGBE_DMATXCTL_TE; 1708 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); 1709 break; 1710 default: 1711 break; 1712 } 1713 1714 ixgbe_reset(adapter); 1715 1716 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1717 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1718 } 1719 1720 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1721 { 1722 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1723 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1724 struct ixgbe_hw *hw = &adapter->hw; 1725 u32 rctl, reg_data; 1726 int ret_val; 1727 int err; 1728 1729 /* Setup Tx descriptor ring and Tx buffers */ 1730 tx_ring->count = IXGBE_DEFAULT_TXD; 1731 tx_ring->queue_index = 0; 1732 tx_ring->dev = &adapter->pdev->dev; 1733 tx_ring->netdev = adapter->netdev; 1734 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1735 1736 err = ixgbe_setup_tx_resources(tx_ring); 1737 if (err) 1738 return 1; 1739 1740 switch (adapter->hw.mac.type) { 1741 case ixgbe_mac_82599EB: 1742 case ixgbe_mac_X540: 1743 case ixgbe_mac_X550: 1744 case ixgbe_mac_X550EM_x: 1745 case ixgbe_mac_x550em_a: 1746 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1747 reg_data |= IXGBE_DMATXCTL_TE; 1748 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1749 break; 1750 default: 1751 break; 1752 } 1753 1754 ixgbe_configure_tx_ring(adapter, tx_ring); 1755 1756 /* Setup Rx Descriptor ring and Rx buffers */ 1757 rx_ring->count = IXGBE_DEFAULT_RXD; 1758 rx_ring->queue_index = 0; 1759 rx_ring->dev = &adapter->pdev->dev; 1760 rx_ring->netdev = adapter->netdev; 1761 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1762 1763 err = ixgbe_setup_rx_resources(rx_ring); 1764 if (err) { 1765 ret_val = 4; 1766 goto err_nomem; 1767 } 1768 1769 hw->mac.ops.disable_rx(hw); 1770 1771 ixgbe_configure_rx_ring(adapter, rx_ring); 1772 1773 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1774 rctl |= IXGBE_RXCTRL_DMBYPS; 1775 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1776 1777 hw->mac.ops.enable_rx(hw); 1778 1779 return 0; 1780 1781 err_nomem: 1782 ixgbe_free_desc_rings(adapter); 1783 return ret_val; 1784 } 1785 1786 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1787 { 1788 struct ixgbe_hw *hw = &adapter->hw; 1789 u32 reg_data; 1790 1791 1792 /* Setup MAC loopback */ 1793 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1794 reg_data |= IXGBE_HLREG0_LPBK; 1795 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1796 1797 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1798 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1799 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1800 1801 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1802 switch (adapter->hw.mac.type) { 1803 case ixgbe_mac_X540: 1804 case ixgbe_mac_X550: 1805 case ixgbe_mac_X550EM_x: 1806 case ixgbe_mac_x550em_a: 1807 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1808 reg_data |= IXGBE_MACC_FLU; 1809 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1810 break; 1811 default: 1812 if (hw->mac.orig_autoc) { 1813 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1814 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1815 } else { 1816 return 10; 1817 } 1818 } 1819 IXGBE_WRITE_FLUSH(hw); 1820 usleep_range(10000, 20000); 1821 1822 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1823 if (hw->mac.type == ixgbe_mac_82598EB) { 1824 u8 atlas; 1825 1826 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1827 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1828 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1829 1830 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1831 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1832 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1833 1834 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1835 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1836 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1837 1838 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1839 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1840 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1841 } 1842 1843 return 0; 1844 } 1845 1846 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1847 { 1848 u32 reg_data; 1849 1850 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1851 reg_data &= ~IXGBE_HLREG0_LPBK; 1852 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1853 } 1854 1855 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1856 unsigned int frame_size) 1857 { 1858 memset(skb->data, 0xFF, frame_size); 1859 frame_size >>= 1; 1860 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1861 memset(&skb->data[frame_size + 10], 0xBE, 1); 1862 memset(&skb->data[frame_size + 12], 0xAF, 1); 1863 } 1864 1865 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1866 unsigned int frame_size) 1867 { 1868 unsigned char *data; 1869 bool match = true; 1870 1871 frame_size >>= 1; 1872 1873 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1874 1875 if (data[3] != 0xFF || 1876 data[frame_size + 10] != 0xBE || 1877 data[frame_size + 12] != 0xAF) 1878 match = false; 1879 1880 kunmap(rx_buffer->page); 1881 1882 return match; 1883 } 1884 1885 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1886 struct ixgbe_ring *tx_ring, 1887 unsigned int size) 1888 { 1889 union ixgbe_adv_rx_desc *rx_desc; 1890 struct ixgbe_rx_buffer *rx_buffer; 1891 struct ixgbe_tx_buffer *tx_buffer; 1892 u16 rx_ntc, tx_ntc, count = 0; 1893 1894 /* initialize next to clean and descriptor values */ 1895 rx_ntc = rx_ring->next_to_clean; 1896 tx_ntc = tx_ring->next_to_clean; 1897 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1898 1899 while (rx_desc->wb.upper.length) { 1900 /* check Rx buffer */ 1901 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 1902 1903 /* sync Rx buffer for CPU read */ 1904 dma_sync_single_for_cpu(rx_ring->dev, 1905 rx_buffer->dma, 1906 ixgbe_rx_bufsz(rx_ring), 1907 DMA_FROM_DEVICE); 1908 1909 /* verify contents of skb */ 1910 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 1911 count++; 1912 1913 /* sync Rx buffer for device write */ 1914 dma_sync_single_for_device(rx_ring->dev, 1915 rx_buffer->dma, 1916 ixgbe_rx_bufsz(rx_ring), 1917 DMA_FROM_DEVICE); 1918 1919 /* unmap buffer on Tx side */ 1920 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1921 1922 /* Free all the Tx ring sk_buffs */ 1923 dev_kfree_skb_any(tx_buffer->skb); 1924 1925 /* unmap skb header data */ 1926 dma_unmap_single(tx_ring->dev, 1927 dma_unmap_addr(tx_buffer, dma), 1928 dma_unmap_len(tx_buffer, len), 1929 DMA_TO_DEVICE); 1930 dma_unmap_len_set(tx_buffer, len, 0); 1931 1932 /* increment Rx/Tx next to clean counters */ 1933 rx_ntc++; 1934 if (rx_ntc == rx_ring->count) 1935 rx_ntc = 0; 1936 tx_ntc++; 1937 if (tx_ntc == tx_ring->count) 1938 tx_ntc = 0; 1939 1940 /* fetch next descriptor */ 1941 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1942 } 1943 1944 netdev_tx_reset_queue(txring_txq(tx_ring)); 1945 1946 /* re-map buffers to ring, store next to clean values */ 1947 ixgbe_alloc_rx_buffers(rx_ring, count); 1948 rx_ring->next_to_clean = rx_ntc; 1949 tx_ring->next_to_clean = tx_ntc; 1950 1951 return count; 1952 } 1953 1954 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1955 { 1956 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1957 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1958 int i, j, lc, good_cnt, ret_val = 0; 1959 unsigned int size = 1024; 1960 netdev_tx_t tx_ret_val; 1961 struct sk_buff *skb; 1962 u32 flags_orig = adapter->flags; 1963 1964 /* DCB can modify the frames on Tx */ 1965 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1966 1967 /* allocate test skb */ 1968 skb = alloc_skb(size, GFP_KERNEL); 1969 if (!skb) 1970 return 11; 1971 1972 /* place data into test skb */ 1973 ixgbe_create_lbtest_frame(skb, size); 1974 skb_put(skb, size); 1975 1976 /* 1977 * Calculate the loop count based on the largest descriptor ring 1978 * The idea is to wrap the largest ring a number of times using 64 1979 * send/receive pairs during each loop 1980 */ 1981 1982 if (rx_ring->count <= tx_ring->count) 1983 lc = ((tx_ring->count / 64) * 2) + 1; 1984 else 1985 lc = ((rx_ring->count / 64) * 2) + 1; 1986 1987 for (j = 0; j <= lc; j++) { 1988 /* reset count of good packets */ 1989 good_cnt = 0; 1990 1991 /* place 64 packets on the transmit queue*/ 1992 for (i = 0; i < 64; i++) { 1993 skb_get(skb); 1994 tx_ret_val = ixgbe_xmit_frame_ring(skb, 1995 adapter, 1996 tx_ring); 1997 if (tx_ret_val == NETDEV_TX_OK) 1998 good_cnt++; 1999 } 2000 2001 if (good_cnt != 64) { 2002 ret_val = 12; 2003 break; 2004 } 2005 2006 /* allow 200 milliseconds for packets to go from Tx to Rx */ 2007 msleep(200); 2008 2009 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 2010 if (good_cnt != 64) { 2011 ret_val = 13; 2012 break; 2013 } 2014 } 2015 2016 /* free the original skb */ 2017 kfree_skb(skb); 2018 adapter->flags = flags_orig; 2019 2020 return ret_val; 2021 } 2022 2023 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 2024 { 2025 *data = ixgbe_setup_desc_rings(adapter); 2026 if (*data) 2027 goto out; 2028 *data = ixgbe_setup_loopback_test(adapter); 2029 if (*data) 2030 goto err_loopback; 2031 *data = ixgbe_run_loopback_test(adapter); 2032 ixgbe_loopback_cleanup(adapter); 2033 2034 err_loopback: 2035 ixgbe_free_desc_rings(adapter); 2036 out: 2037 return *data; 2038 } 2039 2040 static void ixgbe_diag_test(struct net_device *netdev, 2041 struct ethtool_test *eth_test, u64 *data) 2042 { 2043 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2044 bool if_running = netif_running(netdev); 2045 2046 if (ixgbe_removed(adapter->hw.hw_addr)) { 2047 e_err(hw, "Adapter removed - test blocked\n"); 2048 data[0] = 1; 2049 data[1] = 1; 2050 data[2] = 1; 2051 data[3] = 1; 2052 data[4] = 1; 2053 eth_test->flags |= ETH_TEST_FL_FAILED; 2054 return; 2055 } 2056 set_bit(__IXGBE_TESTING, &adapter->state); 2057 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2058 struct ixgbe_hw *hw = &adapter->hw; 2059 2060 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2061 int i; 2062 for (i = 0; i < adapter->num_vfs; i++) { 2063 if (adapter->vfinfo[i].clear_to_send) { 2064 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2065 data[0] = 1; 2066 data[1] = 1; 2067 data[2] = 1; 2068 data[3] = 1; 2069 data[4] = 1; 2070 eth_test->flags |= ETH_TEST_FL_FAILED; 2071 clear_bit(__IXGBE_TESTING, 2072 &adapter->state); 2073 goto skip_ol_tests; 2074 } 2075 } 2076 } 2077 2078 /* Offline tests */ 2079 e_info(hw, "offline testing starting\n"); 2080 2081 /* Link test performed before hardware reset so autoneg doesn't 2082 * interfere with test result 2083 */ 2084 if (ixgbe_link_test(adapter, &data[4])) 2085 eth_test->flags |= ETH_TEST_FL_FAILED; 2086 2087 if (if_running) 2088 /* indicate we're in test mode */ 2089 ixgbe_close(netdev); 2090 else 2091 ixgbe_reset(adapter); 2092 2093 e_info(hw, "register testing starting\n"); 2094 if (ixgbe_reg_test(adapter, &data[0])) 2095 eth_test->flags |= ETH_TEST_FL_FAILED; 2096 2097 ixgbe_reset(adapter); 2098 e_info(hw, "eeprom testing starting\n"); 2099 if (ixgbe_eeprom_test(adapter, &data[1])) 2100 eth_test->flags |= ETH_TEST_FL_FAILED; 2101 2102 ixgbe_reset(adapter); 2103 e_info(hw, "interrupt testing starting\n"); 2104 if (ixgbe_intr_test(adapter, &data[2])) 2105 eth_test->flags |= ETH_TEST_FL_FAILED; 2106 2107 /* If SRIOV or VMDq is enabled then skip MAC 2108 * loopback diagnostic. */ 2109 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2110 IXGBE_FLAG_VMDQ_ENABLED)) { 2111 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2112 data[3] = 0; 2113 goto skip_loopback; 2114 } 2115 2116 ixgbe_reset(adapter); 2117 e_info(hw, "loopback testing starting\n"); 2118 if (ixgbe_loopback_test(adapter, &data[3])) 2119 eth_test->flags |= ETH_TEST_FL_FAILED; 2120 2121 skip_loopback: 2122 ixgbe_reset(adapter); 2123 2124 /* clear testing bit and return adapter to previous state */ 2125 clear_bit(__IXGBE_TESTING, &adapter->state); 2126 if (if_running) 2127 ixgbe_open(netdev); 2128 else if (hw->mac.ops.disable_tx_laser) 2129 hw->mac.ops.disable_tx_laser(hw); 2130 } else { 2131 e_info(hw, "online testing starting\n"); 2132 2133 /* Online tests */ 2134 if (ixgbe_link_test(adapter, &data[4])) 2135 eth_test->flags |= ETH_TEST_FL_FAILED; 2136 2137 /* Offline tests aren't run; pass by default */ 2138 data[0] = 0; 2139 data[1] = 0; 2140 data[2] = 0; 2141 data[3] = 0; 2142 2143 clear_bit(__IXGBE_TESTING, &adapter->state); 2144 } 2145 2146 skip_ol_tests: 2147 msleep_interruptible(4 * 1000); 2148 } 2149 2150 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2151 struct ethtool_wolinfo *wol) 2152 { 2153 struct ixgbe_hw *hw = &adapter->hw; 2154 int retval = 0; 2155 2156 /* WOL not supported for all devices */ 2157 if (!ixgbe_wol_supported(adapter, hw->device_id, 2158 hw->subsystem_device_id)) { 2159 retval = 1; 2160 wol->supported = 0; 2161 } 2162 2163 return retval; 2164 } 2165 2166 static void ixgbe_get_wol(struct net_device *netdev, 2167 struct ethtool_wolinfo *wol) 2168 { 2169 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2170 2171 wol->supported = WAKE_UCAST | WAKE_MCAST | 2172 WAKE_BCAST | WAKE_MAGIC; 2173 wol->wolopts = 0; 2174 2175 if (ixgbe_wol_exclusion(adapter, wol) || 2176 !device_can_wakeup(&adapter->pdev->dev)) 2177 return; 2178 2179 if (adapter->wol & IXGBE_WUFC_EX) 2180 wol->wolopts |= WAKE_UCAST; 2181 if (adapter->wol & IXGBE_WUFC_MC) 2182 wol->wolopts |= WAKE_MCAST; 2183 if (adapter->wol & IXGBE_WUFC_BC) 2184 wol->wolopts |= WAKE_BCAST; 2185 if (adapter->wol & IXGBE_WUFC_MAG) 2186 wol->wolopts |= WAKE_MAGIC; 2187 } 2188 2189 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2190 { 2191 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2192 2193 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 2194 return -EOPNOTSUPP; 2195 2196 if (ixgbe_wol_exclusion(adapter, wol)) 2197 return wol->wolopts ? -EOPNOTSUPP : 0; 2198 2199 adapter->wol = 0; 2200 2201 if (wol->wolopts & WAKE_UCAST) 2202 adapter->wol |= IXGBE_WUFC_EX; 2203 if (wol->wolopts & WAKE_MCAST) 2204 adapter->wol |= IXGBE_WUFC_MC; 2205 if (wol->wolopts & WAKE_BCAST) 2206 adapter->wol |= IXGBE_WUFC_BC; 2207 if (wol->wolopts & WAKE_MAGIC) 2208 adapter->wol |= IXGBE_WUFC_MAG; 2209 2210 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2211 2212 return 0; 2213 } 2214 2215 static int ixgbe_nway_reset(struct net_device *netdev) 2216 { 2217 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2218 2219 if (netif_running(netdev)) 2220 ixgbe_reinit_locked(adapter); 2221 2222 return 0; 2223 } 2224 2225 static int ixgbe_set_phys_id(struct net_device *netdev, 2226 enum ethtool_phys_id_state state) 2227 { 2228 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2229 struct ixgbe_hw *hw = &adapter->hw; 2230 2231 switch (state) { 2232 case ETHTOOL_ID_ACTIVE: 2233 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2234 return 2; 2235 2236 case ETHTOOL_ID_ON: 2237 hw->mac.ops.led_on(hw, hw->mac.led_link_act); 2238 break; 2239 2240 case ETHTOOL_ID_OFF: 2241 hw->mac.ops.led_off(hw, hw->mac.led_link_act); 2242 break; 2243 2244 case ETHTOOL_ID_INACTIVE: 2245 /* Restore LED settings */ 2246 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2247 break; 2248 } 2249 2250 return 0; 2251 } 2252 2253 static int ixgbe_get_coalesce(struct net_device *netdev, 2254 struct ethtool_coalesce *ec) 2255 { 2256 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2257 2258 /* only valid if in constant ITR mode */ 2259 if (adapter->rx_itr_setting <= 1) 2260 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2261 else 2262 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2263 2264 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2265 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2266 return 0; 2267 2268 /* only valid if in constant ITR mode */ 2269 if (adapter->tx_itr_setting <= 1) 2270 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2271 else 2272 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2273 2274 return 0; 2275 } 2276 2277 /* 2278 * this function must be called before setting the new value of 2279 * rx_itr_setting 2280 */ 2281 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2282 { 2283 struct net_device *netdev = adapter->netdev; 2284 2285 /* nothing to do if LRO or RSC are not enabled */ 2286 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2287 !(netdev->features & NETIF_F_LRO)) 2288 return false; 2289 2290 /* check the feature flag value and enable RSC if necessary */ 2291 if (adapter->rx_itr_setting == 1 || 2292 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2293 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2294 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2295 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2296 return true; 2297 } 2298 /* if interrupt rate is too high then disable RSC */ 2299 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2300 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2301 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2302 return true; 2303 } 2304 return false; 2305 } 2306 2307 static int ixgbe_set_coalesce(struct net_device *netdev, 2308 struct ethtool_coalesce *ec) 2309 { 2310 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2311 struct ixgbe_q_vector *q_vector; 2312 int i; 2313 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2314 bool need_reset = false; 2315 2316 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2317 /* reject Tx specific changes in case of mixed RxTx vectors */ 2318 if (ec->tx_coalesce_usecs) 2319 return -EINVAL; 2320 tx_itr_prev = adapter->rx_itr_setting; 2321 } else { 2322 tx_itr_prev = adapter->tx_itr_setting; 2323 } 2324 2325 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2326 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2327 return -EINVAL; 2328 2329 if (ec->rx_coalesce_usecs > 1) 2330 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2331 else 2332 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2333 2334 if (adapter->rx_itr_setting == 1) 2335 rx_itr_param = IXGBE_20K_ITR; 2336 else 2337 rx_itr_param = adapter->rx_itr_setting; 2338 2339 if (ec->tx_coalesce_usecs > 1) 2340 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2341 else 2342 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2343 2344 if (adapter->tx_itr_setting == 1) 2345 tx_itr_param = IXGBE_12K_ITR; 2346 else 2347 tx_itr_param = adapter->tx_itr_setting; 2348 2349 /* mixed Rx/Tx */ 2350 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2351 adapter->tx_itr_setting = adapter->rx_itr_setting; 2352 2353 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2354 if ((adapter->tx_itr_setting != 1) && 2355 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2356 if ((tx_itr_prev == 1) || 2357 (tx_itr_prev >= IXGBE_100K_ITR)) 2358 need_reset = true; 2359 } else { 2360 if ((tx_itr_prev != 1) && 2361 (tx_itr_prev < IXGBE_100K_ITR)) 2362 need_reset = true; 2363 } 2364 2365 /* check the old value and enable RSC if necessary */ 2366 need_reset |= ixgbe_update_rsc(adapter); 2367 2368 for (i = 0; i < adapter->num_q_vectors; i++) { 2369 q_vector = adapter->q_vector[i]; 2370 if (q_vector->tx.count && !q_vector->rx.count) 2371 /* tx only */ 2372 q_vector->itr = tx_itr_param; 2373 else 2374 /* rx only or mixed */ 2375 q_vector->itr = rx_itr_param; 2376 ixgbe_write_eitr(q_vector); 2377 } 2378 2379 /* 2380 * do reset here at the end to make sure EITR==0 case is handled 2381 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2382 * also locks in RSC enable/disable which requires reset 2383 */ 2384 if (need_reset) 2385 ixgbe_do_reset(netdev); 2386 2387 return 0; 2388 } 2389 2390 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2391 struct ethtool_rxnfc *cmd) 2392 { 2393 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2394 struct ethtool_rx_flow_spec *fsp = 2395 (struct ethtool_rx_flow_spec *)&cmd->fs; 2396 struct hlist_node *node2; 2397 struct ixgbe_fdir_filter *rule = NULL; 2398 2399 /* report total rule count */ 2400 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2401 2402 hlist_for_each_entry_safe(rule, node2, 2403 &adapter->fdir_filter_list, fdir_node) { 2404 if (fsp->location <= rule->sw_idx) 2405 break; 2406 } 2407 2408 if (!rule || fsp->location != rule->sw_idx) 2409 return -EINVAL; 2410 2411 /* fill out the flow spec entry */ 2412 2413 /* set flow type field */ 2414 switch (rule->filter.formatted.flow_type) { 2415 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2416 fsp->flow_type = TCP_V4_FLOW; 2417 break; 2418 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2419 fsp->flow_type = UDP_V4_FLOW; 2420 break; 2421 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2422 fsp->flow_type = SCTP_V4_FLOW; 2423 break; 2424 case IXGBE_ATR_FLOW_TYPE_IPV4: 2425 fsp->flow_type = IP_USER_FLOW; 2426 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2427 fsp->h_u.usr_ip4_spec.proto = 0; 2428 fsp->m_u.usr_ip4_spec.proto = 0; 2429 break; 2430 default: 2431 return -EINVAL; 2432 } 2433 2434 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2435 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2436 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2437 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2438 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2439 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2440 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2441 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2442 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2443 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2444 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2445 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2446 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2447 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2448 fsp->flow_type |= FLOW_EXT; 2449 2450 /* record action */ 2451 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2452 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2453 else 2454 fsp->ring_cookie = rule->action; 2455 2456 return 0; 2457 } 2458 2459 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2460 struct ethtool_rxnfc *cmd, 2461 u32 *rule_locs) 2462 { 2463 struct hlist_node *node2; 2464 struct ixgbe_fdir_filter *rule; 2465 int cnt = 0; 2466 2467 /* report total rule count */ 2468 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2469 2470 hlist_for_each_entry_safe(rule, node2, 2471 &adapter->fdir_filter_list, fdir_node) { 2472 if (cnt == cmd->rule_cnt) 2473 return -EMSGSIZE; 2474 rule_locs[cnt] = rule->sw_idx; 2475 cnt++; 2476 } 2477 2478 cmd->rule_cnt = cnt; 2479 2480 return 0; 2481 } 2482 2483 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2484 struct ethtool_rxnfc *cmd) 2485 { 2486 cmd->data = 0; 2487 2488 /* Report default options for RSS on ixgbe */ 2489 switch (cmd->flow_type) { 2490 case TCP_V4_FLOW: 2491 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2492 /* fallthrough */ 2493 case UDP_V4_FLOW: 2494 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2495 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2496 /* fallthrough */ 2497 case SCTP_V4_FLOW: 2498 case AH_ESP_V4_FLOW: 2499 case AH_V4_FLOW: 2500 case ESP_V4_FLOW: 2501 case IPV4_FLOW: 2502 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2503 break; 2504 case TCP_V6_FLOW: 2505 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2506 /* fallthrough */ 2507 case UDP_V6_FLOW: 2508 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2509 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2510 /* fallthrough */ 2511 case SCTP_V6_FLOW: 2512 case AH_ESP_V6_FLOW: 2513 case AH_V6_FLOW: 2514 case ESP_V6_FLOW: 2515 case IPV6_FLOW: 2516 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2517 break; 2518 default: 2519 return -EINVAL; 2520 } 2521 2522 return 0; 2523 } 2524 2525 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2526 u32 *rule_locs) 2527 { 2528 struct ixgbe_adapter *adapter = netdev_priv(dev); 2529 int ret = -EOPNOTSUPP; 2530 2531 switch (cmd->cmd) { 2532 case ETHTOOL_GRXRINGS: 2533 cmd->data = adapter->num_rx_queues; 2534 ret = 0; 2535 break; 2536 case ETHTOOL_GRXCLSRLCNT: 2537 cmd->rule_cnt = adapter->fdir_filter_count; 2538 ret = 0; 2539 break; 2540 case ETHTOOL_GRXCLSRULE: 2541 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2542 break; 2543 case ETHTOOL_GRXCLSRLALL: 2544 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2545 break; 2546 case ETHTOOL_GRXFH: 2547 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2548 break; 2549 default: 2550 break; 2551 } 2552 2553 return ret; 2554 } 2555 2556 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2557 struct ixgbe_fdir_filter *input, 2558 u16 sw_idx) 2559 { 2560 struct ixgbe_hw *hw = &adapter->hw; 2561 struct hlist_node *node2; 2562 struct ixgbe_fdir_filter *rule, *parent; 2563 int err = -EINVAL; 2564 2565 parent = NULL; 2566 rule = NULL; 2567 2568 hlist_for_each_entry_safe(rule, node2, 2569 &adapter->fdir_filter_list, fdir_node) { 2570 /* hash found, or no matching entry */ 2571 if (rule->sw_idx >= sw_idx) 2572 break; 2573 parent = rule; 2574 } 2575 2576 /* if there is an old rule occupying our place remove it */ 2577 if (rule && (rule->sw_idx == sw_idx)) { 2578 if (!input || (rule->filter.formatted.bkt_hash != 2579 input->filter.formatted.bkt_hash)) { 2580 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2581 &rule->filter, 2582 sw_idx); 2583 } 2584 2585 hlist_del(&rule->fdir_node); 2586 kfree(rule); 2587 adapter->fdir_filter_count--; 2588 } 2589 2590 /* 2591 * If no input this was a delete, err should be 0 if a rule was 2592 * successfully found and removed from the list else -EINVAL 2593 */ 2594 if (!input) 2595 return err; 2596 2597 /* initialize node and set software index */ 2598 INIT_HLIST_NODE(&input->fdir_node); 2599 2600 /* add filter to the list */ 2601 if (parent) 2602 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2603 else 2604 hlist_add_head(&input->fdir_node, 2605 &adapter->fdir_filter_list); 2606 2607 /* update counts */ 2608 adapter->fdir_filter_count++; 2609 2610 return 0; 2611 } 2612 2613 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2614 u8 *flow_type) 2615 { 2616 switch (fsp->flow_type & ~FLOW_EXT) { 2617 case TCP_V4_FLOW: 2618 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2619 break; 2620 case UDP_V4_FLOW: 2621 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2622 break; 2623 case SCTP_V4_FLOW: 2624 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2625 break; 2626 case IP_USER_FLOW: 2627 switch (fsp->h_u.usr_ip4_spec.proto) { 2628 case IPPROTO_TCP: 2629 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2630 break; 2631 case IPPROTO_UDP: 2632 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2633 break; 2634 case IPPROTO_SCTP: 2635 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2636 break; 2637 case 0: 2638 if (!fsp->m_u.usr_ip4_spec.proto) { 2639 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2640 break; 2641 } 2642 default: 2643 return 0; 2644 } 2645 break; 2646 default: 2647 return 0; 2648 } 2649 2650 return 1; 2651 } 2652 2653 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2654 struct ethtool_rxnfc *cmd) 2655 { 2656 struct ethtool_rx_flow_spec *fsp = 2657 (struct ethtool_rx_flow_spec *)&cmd->fs; 2658 struct ixgbe_hw *hw = &adapter->hw; 2659 struct ixgbe_fdir_filter *input; 2660 union ixgbe_atr_input mask; 2661 u8 queue; 2662 int err; 2663 2664 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2665 return -EOPNOTSUPP; 2666 2667 /* ring_cookie is a masked into a set of queues and ixgbe pools or 2668 * we use the drop index. 2669 */ 2670 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 2671 queue = IXGBE_FDIR_DROP_QUEUE; 2672 } else { 2673 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); 2674 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie); 2675 2676 if (!vf && (ring >= adapter->num_rx_queues)) 2677 return -EINVAL; 2678 else if (vf && 2679 ((vf > adapter->num_vfs) || 2680 ring >= adapter->num_rx_queues_per_pool)) 2681 return -EINVAL; 2682 2683 /* Map the ring onto the absolute queue index */ 2684 if (!vf) 2685 queue = adapter->rx_ring[ring]->reg_idx; 2686 else 2687 queue = ((vf - 1) * 2688 adapter->num_rx_queues_per_pool) + ring; 2689 } 2690 2691 /* Don't allow indexes to exist outside of available space */ 2692 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2693 e_err(drv, "Location out of range\n"); 2694 return -EINVAL; 2695 } 2696 2697 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2698 if (!input) 2699 return -ENOMEM; 2700 2701 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2702 2703 /* set SW index */ 2704 input->sw_idx = fsp->location; 2705 2706 /* record flow type */ 2707 if (!ixgbe_flowspec_to_flow_type(fsp, 2708 &input->filter.formatted.flow_type)) { 2709 e_err(drv, "Unrecognized flow type\n"); 2710 goto err_out; 2711 } 2712 2713 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2714 IXGBE_ATR_L4TYPE_MASK; 2715 2716 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2717 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2718 2719 /* Copy input into formatted structures */ 2720 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2721 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2722 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2723 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2724 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2725 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2726 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2727 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2728 2729 if (fsp->flow_type & FLOW_EXT) { 2730 input->filter.formatted.vm_pool = 2731 (unsigned char)ntohl(fsp->h_ext.data[1]); 2732 mask.formatted.vm_pool = 2733 (unsigned char)ntohl(fsp->m_ext.data[1]); 2734 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2735 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2736 input->filter.formatted.flex_bytes = 2737 fsp->h_ext.vlan_etype; 2738 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2739 } 2740 2741 /* determine if we need to drop or route the packet */ 2742 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2743 input->action = IXGBE_FDIR_DROP_QUEUE; 2744 else 2745 input->action = fsp->ring_cookie; 2746 2747 spin_lock(&adapter->fdir_perfect_lock); 2748 2749 if (hlist_empty(&adapter->fdir_filter_list)) { 2750 /* save mask and program input mask into HW */ 2751 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2752 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2753 if (err) { 2754 e_err(drv, "Error writing mask\n"); 2755 goto err_out_w_lock; 2756 } 2757 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2758 e_err(drv, "Only one mask supported per port\n"); 2759 goto err_out_w_lock; 2760 } 2761 2762 /* apply mask and compute/store hash */ 2763 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2764 2765 /* program filters to filter memory */ 2766 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2767 &input->filter, input->sw_idx, queue); 2768 if (err) 2769 goto err_out_w_lock; 2770 2771 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2772 2773 spin_unlock(&adapter->fdir_perfect_lock); 2774 2775 return err; 2776 err_out_w_lock: 2777 spin_unlock(&adapter->fdir_perfect_lock); 2778 err_out: 2779 kfree(input); 2780 return -EINVAL; 2781 } 2782 2783 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2784 struct ethtool_rxnfc *cmd) 2785 { 2786 struct ethtool_rx_flow_spec *fsp = 2787 (struct ethtool_rx_flow_spec *)&cmd->fs; 2788 int err; 2789 2790 spin_lock(&adapter->fdir_perfect_lock); 2791 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2792 spin_unlock(&adapter->fdir_perfect_lock); 2793 2794 return err; 2795 } 2796 2797 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2798 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2799 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2800 struct ethtool_rxnfc *nfc) 2801 { 2802 u32 flags2 = adapter->flags2; 2803 2804 /* 2805 * RSS does not support anything other than hashing 2806 * to queues on src and dst IPs and ports 2807 */ 2808 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2809 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2810 return -EINVAL; 2811 2812 switch (nfc->flow_type) { 2813 case TCP_V4_FLOW: 2814 case TCP_V6_FLOW: 2815 if (!(nfc->data & RXH_IP_SRC) || 2816 !(nfc->data & RXH_IP_DST) || 2817 !(nfc->data & RXH_L4_B_0_1) || 2818 !(nfc->data & RXH_L4_B_2_3)) 2819 return -EINVAL; 2820 break; 2821 case UDP_V4_FLOW: 2822 if (!(nfc->data & RXH_IP_SRC) || 2823 !(nfc->data & RXH_IP_DST)) 2824 return -EINVAL; 2825 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2826 case 0: 2827 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2828 break; 2829 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2830 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2831 break; 2832 default: 2833 return -EINVAL; 2834 } 2835 break; 2836 case UDP_V6_FLOW: 2837 if (!(nfc->data & RXH_IP_SRC) || 2838 !(nfc->data & RXH_IP_DST)) 2839 return -EINVAL; 2840 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2841 case 0: 2842 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2843 break; 2844 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2845 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2846 break; 2847 default: 2848 return -EINVAL; 2849 } 2850 break; 2851 case AH_ESP_V4_FLOW: 2852 case AH_V4_FLOW: 2853 case ESP_V4_FLOW: 2854 case SCTP_V4_FLOW: 2855 case AH_ESP_V6_FLOW: 2856 case AH_V6_FLOW: 2857 case ESP_V6_FLOW: 2858 case SCTP_V6_FLOW: 2859 if (!(nfc->data & RXH_IP_SRC) || 2860 !(nfc->data & RXH_IP_DST) || 2861 (nfc->data & RXH_L4_B_0_1) || 2862 (nfc->data & RXH_L4_B_2_3)) 2863 return -EINVAL; 2864 break; 2865 default: 2866 return -EINVAL; 2867 } 2868 2869 /* if we changed something we need to update flags */ 2870 if (flags2 != adapter->flags2) { 2871 struct ixgbe_hw *hw = &adapter->hw; 2872 u32 mrqc; 2873 unsigned int pf_pool = adapter->num_vfs; 2874 2875 if ((hw->mac.type >= ixgbe_mac_X550) && 2876 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2877 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 2878 else 2879 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2880 2881 if ((flags2 & UDP_RSS_FLAGS) && 2882 !(adapter->flags2 & UDP_RSS_FLAGS)) 2883 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2884 2885 adapter->flags2 = flags2; 2886 2887 /* Perform hash on these packet types */ 2888 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 2889 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 2890 | IXGBE_MRQC_RSS_FIELD_IPV6 2891 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 2892 2893 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2894 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 2895 2896 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2897 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 2898 2899 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2900 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 2901 2902 if ((hw->mac.type >= ixgbe_mac_X550) && 2903 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2904 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 2905 else 2906 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2907 } 2908 2909 return 0; 2910 } 2911 2912 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2913 { 2914 struct ixgbe_adapter *adapter = netdev_priv(dev); 2915 int ret = -EOPNOTSUPP; 2916 2917 switch (cmd->cmd) { 2918 case ETHTOOL_SRXCLSRLINS: 2919 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2920 break; 2921 case ETHTOOL_SRXCLSRLDEL: 2922 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2923 break; 2924 case ETHTOOL_SRXFH: 2925 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 2926 break; 2927 default: 2928 break; 2929 } 2930 2931 return ret; 2932 } 2933 2934 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) 2935 { 2936 if (adapter->hw.mac.type < ixgbe_mac_X550) 2937 return 16; 2938 else 2939 return 64; 2940 } 2941 2942 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) 2943 { 2944 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2945 2946 return sizeof(adapter->rss_key); 2947 } 2948 2949 static u32 ixgbe_rss_indir_size(struct net_device *netdev) 2950 { 2951 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2952 2953 return ixgbe_rss_indir_tbl_entries(adapter); 2954 } 2955 2956 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir) 2957 { 2958 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter); 2959 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask; 2960 2961 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 2962 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1; 2963 2964 for (i = 0; i < reta_size; i++) 2965 indir[i] = adapter->rss_indir_tbl[i] & rss_m; 2966 } 2967 2968 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 2969 u8 *hfunc) 2970 { 2971 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2972 2973 if (hfunc) 2974 *hfunc = ETH_RSS_HASH_TOP; 2975 2976 if (indir) 2977 ixgbe_get_reta(adapter, indir); 2978 2979 if (key) 2980 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev)); 2981 2982 return 0; 2983 } 2984 2985 static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir, 2986 const u8 *key, const u8 hfunc) 2987 { 2988 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2989 int i; 2990 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 2991 2992 if (hfunc) 2993 return -EINVAL; 2994 2995 /* Fill out the redirection table */ 2996 if (indir) { 2997 int max_queues = min_t(int, adapter->num_rx_queues, 2998 ixgbe_rss_indir_tbl_max(adapter)); 2999 3000 /*Allow at least 2 queues w/ SR-IOV.*/ 3001 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 3002 (max_queues < 2)) 3003 max_queues = 2; 3004 3005 /* Verify user input. */ 3006 for (i = 0; i < reta_entries; i++) 3007 if (indir[i] >= max_queues) 3008 return -EINVAL; 3009 3010 for (i = 0; i < reta_entries; i++) 3011 adapter->rss_indir_tbl[i] = indir[i]; 3012 } 3013 3014 /* Fill out the rss hash key */ 3015 if (key) { 3016 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev)); 3017 ixgbe_store_key(adapter); 3018 } 3019 3020 ixgbe_store_reta(adapter); 3021 3022 return 0; 3023 } 3024 3025 static int ixgbe_get_ts_info(struct net_device *dev, 3026 struct ethtool_ts_info *info) 3027 { 3028 struct ixgbe_adapter *adapter = netdev_priv(dev); 3029 3030 /* we always support timestamping disabled */ 3031 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 3032 3033 switch (adapter->hw.mac.type) { 3034 case ixgbe_mac_X550: 3035 case ixgbe_mac_X550EM_x: 3036 case ixgbe_mac_x550em_a: 3037 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 3038 /* fallthrough */ 3039 case ixgbe_mac_X540: 3040 case ixgbe_mac_82599EB: 3041 info->so_timestamping = 3042 SOF_TIMESTAMPING_TX_SOFTWARE | 3043 SOF_TIMESTAMPING_RX_SOFTWARE | 3044 SOF_TIMESTAMPING_SOFTWARE | 3045 SOF_TIMESTAMPING_TX_HARDWARE | 3046 SOF_TIMESTAMPING_RX_HARDWARE | 3047 SOF_TIMESTAMPING_RAW_HARDWARE; 3048 3049 if (adapter->ptp_clock) 3050 info->phc_index = ptp_clock_index(adapter->ptp_clock); 3051 else 3052 info->phc_index = -1; 3053 3054 info->tx_types = 3055 BIT(HWTSTAMP_TX_OFF) | 3056 BIT(HWTSTAMP_TX_ON); 3057 3058 info->rx_filters |= 3059 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3060 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3061 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 3062 break; 3063 default: 3064 return ethtool_op_get_ts_info(dev, info); 3065 } 3066 return 0; 3067 } 3068 3069 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 3070 { 3071 unsigned int max_combined; 3072 u8 tcs = netdev_get_num_tc(adapter->netdev); 3073 3074 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3075 /* We only support one q_vector without MSI-X */ 3076 max_combined = 1; 3077 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3078 /* Limit value based on the queue mask */ 3079 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1; 3080 } else if (tcs > 1) { 3081 /* For DCB report channels per traffic class */ 3082 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3083 /* 8 TC w/ 4 queues per TC */ 3084 max_combined = 4; 3085 } else if (tcs > 4) { 3086 /* 8 TC w/ 8 queues per TC */ 3087 max_combined = 8; 3088 } else { 3089 /* 4 TC w/ 16 queues per TC */ 3090 max_combined = 16; 3091 } 3092 } else if (adapter->atr_sample_rate) { 3093 /* support up to 64 queues with ATR */ 3094 max_combined = IXGBE_MAX_FDIR_INDICES; 3095 } else { 3096 /* support up to 16 queues with RSS */ 3097 max_combined = ixgbe_max_rss_indices(adapter); 3098 } 3099 3100 return max_combined; 3101 } 3102 3103 static void ixgbe_get_channels(struct net_device *dev, 3104 struct ethtool_channels *ch) 3105 { 3106 struct ixgbe_adapter *adapter = netdev_priv(dev); 3107 3108 /* report maximum channels */ 3109 ch->max_combined = ixgbe_max_channels(adapter); 3110 3111 /* report info for other vector */ 3112 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3113 ch->max_other = NON_Q_VECTORS; 3114 ch->other_count = NON_Q_VECTORS; 3115 } 3116 3117 /* record RSS queues */ 3118 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 3119 3120 /* nothing else to report if RSS is disabled */ 3121 if (ch->combined_count == 1) 3122 return; 3123 3124 /* we do not support ATR queueing if SR-IOV is enabled */ 3125 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3126 return; 3127 3128 /* same thing goes for being DCB enabled */ 3129 if (netdev_get_num_tc(dev) > 1) 3130 return; 3131 3132 /* if ATR is disabled we can exit */ 3133 if (!adapter->atr_sample_rate) 3134 return; 3135 3136 /* report flow director queues as maximum channels */ 3137 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 3138 } 3139 3140 static int ixgbe_set_channels(struct net_device *dev, 3141 struct ethtool_channels *ch) 3142 { 3143 struct ixgbe_adapter *adapter = netdev_priv(dev); 3144 unsigned int count = ch->combined_count; 3145 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 3146 3147 /* verify they are not requesting separate vectors */ 3148 if (!count || ch->rx_count || ch->tx_count) 3149 return -EINVAL; 3150 3151 /* verify other_count has not changed */ 3152 if (ch->other_count != NON_Q_VECTORS) 3153 return -EINVAL; 3154 3155 /* verify the number of channels does not exceed hardware limits */ 3156 if (count > ixgbe_max_channels(adapter)) 3157 return -EINVAL; 3158 3159 /* update feature limits from largest to smallest supported values */ 3160 adapter->ring_feature[RING_F_FDIR].limit = count; 3161 3162 /* cap RSS limit */ 3163 if (count > max_rss_indices) 3164 count = max_rss_indices; 3165 adapter->ring_feature[RING_F_RSS].limit = count; 3166 3167 #ifdef IXGBE_FCOE 3168 /* cap FCoE limit at 8 */ 3169 if (count > IXGBE_FCRETA_SIZE) 3170 count = IXGBE_FCRETA_SIZE; 3171 adapter->ring_feature[RING_F_FCOE].limit = count; 3172 3173 #endif 3174 /* use setup TC to update any traffic class queue mapping */ 3175 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 3176 } 3177 3178 static int ixgbe_get_module_info(struct net_device *dev, 3179 struct ethtool_modinfo *modinfo) 3180 { 3181 struct ixgbe_adapter *adapter = netdev_priv(dev); 3182 struct ixgbe_hw *hw = &adapter->hw; 3183 s32 status; 3184 u8 sff8472_rev, addr_mode; 3185 bool page_swap = false; 3186 3187 if (hw->phy.type == ixgbe_phy_fw) 3188 return -ENXIO; 3189 3190 /* Check whether we support SFF-8472 or not */ 3191 status = hw->phy.ops.read_i2c_eeprom(hw, 3192 IXGBE_SFF_SFF_8472_COMP, 3193 &sff8472_rev); 3194 if (status) 3195 return -EIO; 3196 3197 /* addressing mode is not supported */ 3198 status = hw->phy.ops.read_i2c_eeprom(hw, 3199 IXGBE_SFF_SFF_8472_SWAP, 3200 &addr_mode); 3201 if (status) 3202 return -EIO; 3203 3204 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3205 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3206 page_swap = true; 3207 } 3208 3209 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 3210 /* We have a SFP, but it does not support SFF-8472 */ 3211 modinfo->type = ETH_MODULE_SFF_8079; 3212 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3213 } else { 3214 /* We have a SFP which supports a revision of SFF-8472. */ 3215 modinfo->type = ETH_MODULE_SFF_8472; 3216 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3217 } 3218 3219 return 0; 3220 } 3221 3222 static int ixgbe_get_module_eeprom(struct net_device *dev, 3223 struct ethtool_eeprom *ee, 3224 u8 *data) 3225 { 3226 struct ixgbe_adapter *adapter = netdev_priv(dev); 3227 struct ixgbe_hw *hw = &adapter->hw; 3228 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3229 u8 databyte = 0xFF; 3230 int i = 0; 3231 3232 if (ee->len == 0) 3233 return -EINVAL; 3234 3235 if (hw->phy.type == ixgbe_phy_fw) 3236 return -ENXIO; 3237 3238 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3239 /* I2C reads can take long time */ 3240 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3241 return -EBUSY; 3242 3243 if (i < ETH_MODULE_SFF_8079_LEN) 3244 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3245 else 3246 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3247 3248 if (status) 3249 return -EIO; 3250 3251 data[i - ee->offset] = databyte; 3252 } 3253 3254 return 0; 3255 } 3256 3257 static const struct { 3258 ixgbe_link_speed mac_speed; 3259 u32 supported; 3260 } ixgbe_ls_map[] = { 3261 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full }, 3262 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full }, 3263 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full }, 3264 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full }, 3265 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full }, 3266 }; 3267 3268 static const struct { 3269 u32 lp_advertised; 3270 u32 mac_speed; 3271 } ixgbe_lp_map[] = { 3272 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full }, 3273 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full }, 3274 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full }, 3275 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full }, 3276 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full }, 3277 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full}, 3278 }; 3279 3280 static int 3281 ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata) 3282 { 3283 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3284 struct ixgbe_hw *hw = &adapter->hw; 3285 s32 rc; 3286 u16 i; 3287 3288 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info); 3289 if (rc) 3290 return rc; 3291 3292 edata->lp_advertised = 0; 3293 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) { 3294 if (info[0] & ixgbe_lp_map[i].lp_advertised) 3295 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed; 3296 } 3297 3298 edata->supported = 0; 3299 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3300 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed) 3301 edata->supported |= ixgbe_ls_map[i].supported; 3302 } 3303 3304 edata->advertised = 0; 3305 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3306 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed) 3307 edata->advertised |= ixgbe_ls_map[i].supported; 3308 } 3309 3310 edata->eee_enabled = !!edata->advertised; 3311 edata->tx_lpi_enabled = edata->eee_enabled; 3312 if (edata->advertised & edata->lp_advertised) 3313 edata->eee_active = true; 3314 3315 return 0; 3316 } 3317 3318 static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3319 { 3320 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3321 struct ixgbe_hw *hw = &adapter->hw; 3322 3323 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3324 return -EOPNOTSUPP; 3325 3326 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw) 3327 return ixgbe_get_eee_fw(adapter, edata); 3328 3329 return -EOPNOTSUPP; 3330 } 3331 3332 static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata) 3333 { 3334 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3335 struct ixgbe_hw *hw = &adapter->hw; 3336 struct ethtool_eee eee_data; 3337 s32 ret_val; 3338 3339 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3340 return -EOPNOTSUPP; 3341 3342 memset(&eee_data, 0, sizeof(struct ethtool_eee)); 3343 3344 ret_val = ixgbe_get_eee(netdev, &eee_data); 3345 if (ret_val) 3346 return ret_val; 3347 3348 if (eee_data.eee_enabled && !edata->eee_enabled) { 3349 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) { 3350 e_err(drv, "Setting EEE tx-lpi is not supported\n"); 3351 return -EINVAL; 3352 } 3353 3354 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) { 3355 e_err(drv, 3356 "Setting EEE Tx LPI timer is not supported\n"); 3357 return -EINVAL; 3358 } 3359 3360 if (eee_data.advertised != edata->advertised) { 3361 e_err(drv, 3362 "Setting EEE advertised speeds is not supported\n"); 3363 return -EINVAL; 3364 } 3365 } 3366 3367 if (eee_data.eee_enabled != edata->eee_enabled) { 3368 if (edata->eee_enabled) { 3369 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 3370 hw->phy.eee_speeds_advertised = 3371 hw->phy.eee_speeds_supported; 3372 } else { 3373 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 3374 hw->phy.eee_speeds_advertised = 0; 3375 } 3376 3377 /* reset link */ 3378 if (netif_running(netdev)) 3379 ixgbe_reinit_locked(adapter); 3380 else 3381 ixgbe_reset(adapter); 3382 } 3383 3384 return 0; 3385 } 3386 3387 static u32 ixgbe_get_priv_flags(struct net_device *netdev) 3388 { 3389 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3390 u32 priv_flags = 0; 3391 3392 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 3393 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX; 3394 3395 return priv_flags; 3396 } 3397 3398 static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3399 { 3400 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3401 unsigned int flags2 = adapter->flags2; 3402 3403 flags2 &= ~IXGBE_FLAG2_RX_LEGACY; 3404 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX) 3405 flags2 |= IXGBE_FLAG2_RX_LEGACY; 3406 3407 if (flags2 != adapter->flags2) { 3408 adapter->flags2 = flags2; 3409 3410 /* reset interface to repopulate queues */ 3411 if (netif_running(netdev)) 3412 ixgbe_reinit_locked(adapter); 3413 } 3414 3415 return 0; 3416 } 3417 3418 static const struct ethtool_ops ixgbe_ethtool_ops = { 3419 .get_drvinfo = ixgbe_get_drvinfo, 3420 .get_regs_len = ixgbe_get_regs_len, 3421 .get_regs = ixgbe_get_regs, 3422 .get_wol = ixgbe_get_wol, 3423 .set_wol = ixgbe_set_wol, 3424 .nway_reset = ixgbe_nway_reset, 3425 .get_link = ethtool_op_get_link, 3426 .get_eeprom_len = ixgbe_get_eeprom_len, 3427 .get_eeprom = ixgbe_get_eeprom, 3428 .set_eeprom = ixgbe_set_eeprom, 3429 .get_ringparam = ixgbe_get_ringparam, 3430 .set_ringparam = ixgbe_set_ringparam, 3431 .get_pauseparam = ixgbe_get_pauseparam, 3432 .set_pauseparam = ixgbe_set_pauseparam, 3433 .get_msglevel = ixgbe_get_msglevel, 3434 .set_msglevel = ixgbe_set_msglevel, 3435 .self_test = ixgbe_diag_test, 3436 .get_strings = ixgbe_get_strings, 3437 .set_phys_id = ixgbe_set_phys_id, 3438 .get_sset_count = ixgbe_get_sset_count, 3439 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3440 .get_coalesce = ixgbe_get_coalesce, 3441 .set_coalesce = ixgbe_set_coalesce, 3442 .get_rxnfc = ixgbe_get_rxnfc, 3443 .set_rxnfc = ixgbe_set_rxnfc, 3444 .get_rxfh_indir_size = ixgbe_rss_indir_size, 3445 .get_rxfh_key_size = ixgbe_get_rxfh_key_size, 3446 .get_rxfh = ixgbe_get_rxfh, 3447 .set_rxfh = ixgbe_set_rxfh, 3448 .get_eee = ixgbe_get_eee, 3449 .set_eee = ixgbe_set_eee, 3450 .get_channels = ixgbe_get_channels, 3451 .set_channels = ixgbe_set_channels, 3452 .get_priv_flags = ixgbe_get_priv_flags, 3453 .set_priv_flags = ixgbe_set_priv_flags, 3454 .get_ts_info = ixgbe_get_ts_info, 3455 .get_module_info = ixgbe_get_module_info, 3456 .get_module_eeprom = ixgbe_get_module_eeprom, 3457 .get_link_ksettings = ixgbe_get_link_ksettings, 3458 .set_link_ksettings = ixgbe_set_link_ksettings, 3459 }; 3460 3461 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3462 { 3463 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3464 } 3465