1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 /* ethtool support for ixgbe */ 30 31 #include <linux/interrupt.h> 32 #include <linux/types.h> 33 #include <linux/module.h> 34 #include <linux/slab.h> 35 #include <linux/pci.h> 36 #include <linux/netdevice.h> 37 #include <linux/ethtool.h> 38 #include <linux/vmalloc.h> 39 #include <linux/highmem.h> 40 #include <linux/uaccess.h> 41 42 #include "ixgbe.h" 43 #include "ixgbe_phy.h" 44 45 46 #define IXGBE_ALL_RAR_ENTRIES 16 47 48 enum {NETDEV_STATS, IXGBE_STATS}; 49 50 struct ixgbe_stats { 51 char stat_string[ETH_GSTRING_LEN]; 52 int type; 53 int sizeof_stat; 54 int stat_offset; 55 }; 56 57 #define IXGBE_STAT(m) IXGBE_STATS, \ 58 sizeof(((struct ixgbe_adapter *)0)->m), \ 59 offsetof(struct ixgbe_adapter, m) 60 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ 61 sizeof(((struct rtnl_link_stats64 *)0)->m), \ 62 offsetof(struct rtnl_link_stats64, m) 63 64 static const struct ixgbe_stats ixgbe_gstrings_stats[] = { 65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)}, 66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)}, 67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)}, 68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)}, 69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, 70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, 71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, 72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, 73 {"lsc_int", IXGBE_STAT(lsc_int)}, 74 {"tx_busy", IXGBE_STAT(tx_busy)}, 75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, 76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)}, 77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)}, 78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)}, 79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)}, 80 {"multicast", IXGBE_NETDEV_STAT(multicast)}, 81 {"broadcast", IXGBE_STAT(stats.bprc)}, 82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, 83 {"collisions", IXGBE_NETDEV_STAT(collisions)}, 84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)}, 85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)}, 86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)}, 87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, 88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, 89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, 90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, 91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)}, 92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)}, 93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)}, 94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)}, 95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)}, 96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)}, 97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)}, 98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, 99 {"tx_restart_queue", IXGBE_STAT(restart_queue)}, 100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, 101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, 102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, 103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, 104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, 105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, 106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, 107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, 108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, 109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, 110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)}, 111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)}, 112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)}, 113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)}, 114 #ifdef IXGBE_FCOE 115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, 116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, 117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, 118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, 119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)}, 120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)}, 121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, 122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, 123 #endif /* IXGBE_FCOE */ 124 }; 125 126 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so 127 * we set the num_rx_queues to evaluate to num_tx_queues. This is 128 * used because we do not have a good way to get the max number of 129 * rx queues with CONFIG_RPS disabled. 130 */ 131 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues 132 133 #define IXGBE_QUEUE_STATS_LEN ( \ 134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \ 135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) 136 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) 137 #define IXGBE_PB_STATS_LEN ( \ 138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ 139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ 140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ 141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ 142 / sizeof(u64)) 143 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ 144 IXGBE_PB_STATS_LEN + \ 145 IXGBE_QUEUE_STATS_LEN) 146 147 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { 148 "Register test (offline)", "Eeprom test (offline)", 149 "Interrupt test (offline)", "Loopback test (offline)", 150 "Link test (on/offline)" 151 }; 152 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN 153 154 static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = { 155 #define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0) 156 "legacy-rx", 157 }; 158 159 #define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings) 160 161 /* currently supported speeds for 10G */ 162 #define ADVRTSD_MSK_10G (SUPPORTED_10000baseT_Full | \ 163 SUPPORTED_10000baseKX4_Full | \ 164 SUPPORTED_10000baseKR_Full) 165 166 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane) 167 168 static u32 ixgbe_get_supported_10gtypes(struct ixgbe_hw *hw) 169 { 170 if (!ixgbe_isbackplane(hw->phy.media_type)) 171 return SUPPORTED_10000baseT_Full; 172 173 switch (hw->device_id) { 174 case IXGBE_DEV_ID_82598: 175 case IXGBE_DEV_ID_82599_KX4: 176 case IXGBE_DEV_ID_82599_KX4_MEZZ: 177 case IXGBE_DEV_ID_X550EM_X_KX4: 178 return SUPPORTED_10000baseKX4_Full; 179 case IXGBE_DEV_ID_82598_BX: 180 case IXGBE_DEV_ID_82599_KR: 181 case IXGBE_DEV_ID_X550EM_X_KR: 182 case IXGBE_DEV_ID_X550EM_X_XFI: 183 return SUPPORTED_10000baseKR_Full; 184 default: 185 return SUPPORTED_10000baseKX4_Full | 186 SUPPORTED_10000baseKR_Full; 187 } 188 } 189 190 static int ixgbe_get_link_ksettings(struct net_device *netdev, 191 struct ethtool_link_ksettings *cmd) 192 { 193 struct ixgbe_adapter *adapter = netdev_priv(netdev); 194 struct ixgbe_hw *hw = &adapter->hw; 195 ixgbe_link_speed supported_link; 196 bool autoneg = false; 197 u32 supported, advertising; 198 199 ethtool_convert_link_mode_to_legacy_u32(&supported, 200 cmd->link_modes.supported); 201 202 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg); 203 204 /* set the supported link speeds */ 205 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 206 supported |= ixgbe_get_supported_10gtypes(hw); 207 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) 208 supported |= (ixgbe_isbackplane(hw->phy.media_type)) ? 209 SUPPORTED_1000baseKX_Full : 210 SUPPORTED_1000baseT_Full; 211 if (supported_link & IXGBE_LINK_SPEED_100_FULL) 212 supported |= SUPPORTED_100baseT_Full; 213 if (supported_link & IXGBE_LINK_SPEED_10_FULL) 214 supported |= SUPPORTED_10baseT_Full; 215 216 /* default advertised speed if phy.autoneg_advertised isn't set */ 217 advertising = supported; 218 /* set the advertised speeds */ 219 if (hw->phy.autoneg_advertised) { 220 advertising = 0; 221 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) 222 advertising |= ADVERTISED_10baseT_Full; 223 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 224 advertising |= ADVERTISED_100baseT_Full; 225 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 226 advertising |= supported & ADVRTSD_MSK_10G; 227 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) { 228 if (supported & SUPPORTED_1000baseKX_Full) 229 advertising |= ADVERTISED_1000baseKX_Full; 230 else 231 advertising |= ADVERTISED_1000baseT_Full; 232 } 233 } else { 234 if (hw->phy.multispeed_fiber && !autoneg) { 235 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) 236 advertising = ADVERTISED_10000baseT_Full; 237 } 238 } 239 240 if (autoneg) { 241 supported |= SUPPORTED_Autoneg; 242 advertising |= ADVERTISED_Autoneg; 243 cmd->base.autoneg = AUTONEG_ENABLE; 244 } else 245 cmd->base.autoneg = AUTONEG_DISABLE; 246 247 /* Determine the remaining settings based on the PHY type. */ 248 switch (adapter->hw.phy.type) { 249 case ixgbe_phy_tn: 250 case ixgbe_phy_aq: 251 case ixgbe_phy_x550em_ext_t: 252 case ixgbe_phy_fw: 253 case ixgbe_phy_cu_unknown: 254 supported |= SUPPORTED_TP; 255 advertising |= ADVERTISED_TP; 256 cmd->base.port = PORT_TP; 257 break; 258 case ixgbe_phy_qt: 259 supported |= SUPPORTED_FIBRE; 260 advertising |= ADVERTISED_FIBRE; 261 cmd->base.port = PORT_FIBRE; 262 break; 263 case ixgbe_phy_nl: 264 case ixgbe_phy_sfp_passive_tyco: 265 case ixgbe_phy_sfp_passive_unknown: 266 case ixgbe_phy_sfp_ftl: 267 case ixgbe_phy_sfp_avago: 268 case ixgbe_phy_sfp_intel: 269 case ixgbe_phy_sfp_unknown: 270 case ixgbe_phy_qsfp_passive_unknown: 271 case ixgbe_phy_qsfp_active_unknown: 272 case ixgbe_phy_qsfp_intel: 273 case ixgbe_phy_qsfp_unknown: 274 /* SFP+ devices, further checking needed */ 275 switch (adapter->hw.phy.sfp_type) { 276 case ixgbe_sfp_type_da_cu: 277 case ixgbe_sfp_type_da_cu_core0: 278 case ixgbe_sfp_type_da_cu_core1: 279 supported |= SUPPORTED_FIBRE; 280 advertising |= ADVERTISED_FIBRE; 281 cmd->base.port = PORT_DA; 282 break; 283 case ixgbe_sfp_type_sr: 284 case ixgbe_sfp_type_lr: 285 case ixgbe_sfp_type_srlr_core0: 286 case ixgbe_sfp_type_srlr_core1: 287 case ixgbe_sfp_type_1g_sx_core0: 288 case ixgbe_sfp_type_1g_sx_core1: 289 case ixgbe_sfp_type_1g_lx_core0: 290 case ixgbe_sfp_type_1g_lx_core1: 291 supported |= SUPPORTED_FIBRE; 292 advertising |= ADVERTISED_FIBRE; 293 cmd->base.port = PORT_FIBRE; 294 break; 295 case ixgbe_sfp_type_not_present: 296 supported |= SUPPORTED_FIBRE; 297 advertising |= ADVERTISED_FIBRE; 298 cmd->base.port = PORT_NONE; 299 break; 300 case ixgbe_sfp_type_1g_cu_core0: 301 case ixgbe_sfp_type_1g_cu_core1: 302 supported |= SUPPORTED_TP; 303 advertising |= ADVERTISED_TP; 304 cmd->base.port = PORT_TP; 305 break; 306 case ixgbe_sfp_type_unknown: 307 default: 308 supported |= SUPPORTED_FIBRE; 309 advertising |= ADVERTISED_FIBRE; 310 cmd->base.port = PORT_OTHER; 311 break; 312 } 313 break; 314 case ixgbe_phy_xaui: 315 supported |= SUPPORTED_FIBRE; 316 advertising |= ADVERTISED_FIBRE; 317 cmd->base.port = PORT_NONE; 318 break; 319 case ixgbe_phy_unknown: 320 case ixgbe_phy_generic: 321 case ixgbe_phy_sfp_unsupported: 322 default: 323 supported |= SUPPORTED_FIBRE; 324 advertising |= ADVERTISED_FIBRE; 325 cmd->base.port = PORT_OTHER; 326 break; 327 } 328 329 /* Indicate pause support */ 330 supported |= SUPPORTED_Pause; 331 332 switch (hw->fc.requested_mode) { 333 case ixgbe_fc_full: 334 advertising |= ADVERTISED_Pause; 335 break; 336 case ixgbe_fc_rx_pause: 337 advertising |= ADVERTISED_Pause | 338 ADVERTISED_Asym_Pause; 339 break; 340 case ixgbe_fc_tx_pause: 341 advertising |= ADVERTISED_Asym_Pause; 342 break; 343 default: 344 advertising &= ~(ADVERTISED_Pause | 345 ADVERTISED_Asym_Pause); 346 } 347 348 if (netif_carrier_ok(netdev)) { 349 switch (adapter->link_speed) { 350 case IXGBE_LINK_SPEED_10GB_FULL: 351 cmd->base.speed = SPEED_10000; 352 break; 353 case IXGBE_LINK_SPEED_5GB_FULL: 354 cmd->base.speed = SPEED_5000; 355 break; 356 case IXGBE_LINK_SPEED_2_5GB_FULL: 357 cmd->base.speed = SPEED_2500; 358 break; 359 case IXGBE_LINK_SPEED_1GB_FULL: 360 cmd->base.speed = SPEED_1000; 361 break; 362 case IXGBE_LINK_SPEED_100_FULL: 363 cmd->base.speed = SPEED_100; 364 break; 365 case IXGBE_LINK_SPEED_10_FULL: 366 cmd->base.speed = SPEED_10; 367 break; 368 default: 369 break; 370 } 371 cmd->base.duplex = DUPLEX_FULL; 372 } else { 373 cmd->base.speed = SPEED_UNKNOWN; 374 cmd->base.duplex = DUPLEX_UNKNOWN; 375 } 376 377 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 378 supported); 379 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 380 advertising); 381 382 return 0; 383 } 384 385 static int ixgbe_set_link_ksettings(struct net_device *netdev, 386 const struct ethtool_link_ksettings *cmd) 387 { 388 struct ixgbe_adapter *adapter = netdev_priv(netdev); 389 struct ixgbe_hw *hw = &adapter->hw; 390 u32 advertised, old; 391 s32 err = 0; 392 u32 supported, advertising; 393 394 ethtool_convert_link_mode_to_legacy_u32(&supported, 395 cmd->link_modes.supported); 396 ethtool_convert_link_mode_to_legacy_u32(&advertising, 397 cmd->link_modes.advertising); 398 399 if ((hw->phy.media_type == ixgbe_media_type_copper) || 400 (hw->phy.multispeed_fiber)) { 401 /* 402 * this function does not support duplex forcing, but can 403 * limit the advertising of the adapter to the specified speed 404 */ 405 if (advertising & ~supported) 406 return -EINVAL; 407 408 /* only allow one speed at a time if no autoneg */ 409 if (!cmd->base.autoneg && hw->phy.multispeed_fiber) { 410 if (advertising == 411 (ADVERTISED_10000baseT_Full | 412 ADVERTISED_1000baseT_Full)) 413 return -EINVAL; 414 } 415 416 old = hw->phy.autoneg_advertised; 417 advertised = 0; 418 if (advertising & ADVERTISED_10000baseT_Full) 419 advertised |= IXGBE_LINK_SPEED_10GB_FULL; 420 421 if (advertising & ADVERTISED_1000baseT_Full) 422 advertised |= IXGBE_LINK_SPEED_1GB_FULL; 423 424 if (advertising & ADVERTISED_100baseT_Full) 425 advertised |= IXGBE_LINK_SPEED_100_FULL; 426 427 if (advertising & ADVERTISED_10baseT_Full) 428 advertised |= IXGBE_LINK_SPEED_10_FULL; 429 430 if (old == advertised) 431 return err; 432 /* this sets the link speed and restarts auto-neg */ 433 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 434 usleep_range(1000, 2000); 435 436 hw->mac.autotry_restart = true; 437 err = hw->mac.ops.setup_link(hw, advertised, true); 438 if (err) { 439 e_info(probe, "setup link failed with code %d\n", err); 440 hw->mac.ops.setup_link(hw, old, true); 441 } 442 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 443 } else { 444 /* in this case we currently only support 10Gb/FULL */ 445 u32 speed = cmd->base.speed; 446 447 if ((cmd->base.autoneg == AUTONEG_ENABLE) || 448 (advertising != ADVERTISED_10000baseT_Full) || 449 (speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL)) 450 return -EINVAL; 451 } 452 453 return err; 454 } 455 456 static void ixgbe_get_pauseparam(struct net_device *netdev, 457 struct ethtool_pauseparam *pause) 458 { 459 struct ixgbe_adapter *adapter = netdev_priv(netdev); 460 struct ixgbe_hw *hw = &adapter->hw; 461 462 if (ixgbe_device_supports_autoneg_fc(hw) && 463 !hw->fc.disable_fc_autoneg) 464 pause->autoneg = 1; 465 else 466 pause->autoneg = 0; 467 468 if (hw->fc.current_mode == ixgbe_fc_rx_pause) { 469 pause->rx_pause = 1; 470 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { 471 pause->tx_pause = 1; 472 } else if (hw->fc.current_mode == ixgbe_fc_full) { 473 pause->rx_pause = 1; 474 pause->tx_pause = 1; 475 } 476 } 477 478 static int ixgbe_set_pauseparam(struct net_device *netdev, 479 struct ethtool_pauseparam *pause) 480 { 481 struct ixgbe_adapter *adapter = netdev_priv(netdev); 482 struct ixgbe_hw *hw = &adapter->hw; 483 struct ixgbe_fc_info fc = hw->fc; 484 485 /* 82598 does no support link flow control with DCB enabled */ 486 if ((hw->mac.type == ixgbe_mac_82598EB) && 487 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)) 488 return -EINVAL; 489 490 /* some devices do not support autoneg of link flow control */ 491 if ((pause->autoneg == AUTONEG_ENABLE) && 492 !ixgbe_device_supports_autoneg_fc(hw)) 493 return -EINVAL; 494 495 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE); 496 497 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg) 498 fc.requested_mode = ixgbe_fc_full; 499 else if (pause->rx_pause && !pause->tx_pause) 500 fc.requested_mode = ixgbe_fc_rx_pause; 501 else if (!pause->rx_pause && pause->tx_pause) 502 fc.requested_mode = ixgbe_fc_tx_pause; 503 else 504 fc.requested_mode = ixgbe_fc_none; 505 506 /* if the thing changed then we'll update and use new autoneg */ 507 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { 508 hw->fc = fc; 509 if (netif_running(netdev)) 510 ixgbe_reinit_locked(adapter); 511 else 512 ixgbe_reset(adapter); 513 } 514 515 return 0; 516 } 517 518 static u32 ixgbe_get_msglevel(struct net_device *netdev) 519 { 520 struct ixgbe_adapter *adapter = netdev_priv(netdev); 521 return adapter->msg_enable; 522 } 523 524 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) 525 { 526 struct ixgbe_adapter *adapter = netdev_priv(netdev); 527 adapter->msg_enable = data; 528 } 529 530 static int ixgbe_get_regs_len(struct net_device *netdev) 531 { 532 #define IXGBE_REGS_LEN 1139 533 return IXGBE_REGS_LEN * sizeof(u32); 534 } 535 536 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ 537 538 static void ixgbe_get_regs(struct net_device *netdev, 539 struct ethtool_regs *regs, void *p) 540 { 541 struct ixgbe_adapter *adapter = netdev_priv(netdev); 542 struct ixgbe_hw *hw = &adapter->hw; 543 u32 *regs_buff = p; 544 u8 i; 545 546 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); 547 548 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 549 hw->device_id; 550 551 /* General Registers */ 552 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); 553 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); 554 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 555 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); 556 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); 557 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 558 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); 559 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); 560 561 /* NVM Register */ 562 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 563 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); 564 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw)); 565 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); 566 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); 567 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); 568 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); 569 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); 570 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); 571 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw)); 572 573 /* Interrupt */ 574 /* don't read EICR because it can clear interrupt causes, instead 575 * read EICS which is a shadow but doesn't clear EICR */ 576 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); 577 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); 578 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); 579 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); 580 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); 581 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); 582 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); 583 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); 584 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); 585 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); 586 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); 587 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); 588 589 /* Flow Control */ 590 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); 591 for (i = 0; i < 4; i++) 592 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i)); 593 for (i = 0; i < 8; i++) { 594 switch (hw->mac.type) { 595 case ixgbe_mac_82598EB: 596 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); 597 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); 598 break; 599 case ixgbe_mac_82599EB: 600 case ixgbe_mac_X540: 601 case ixgbe_mac_X550: 602 case ixgbe_mac_X550EM_x: 603 case ixgbe_mac_x550em_a: 604 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i)); 605 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 606 break; 607 default: 608 break; 609 } 610 } 611 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); 612 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); 613 614 /* Receive DMA */ 615 for (i = 0; i < 64; i++) 616 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 617 for (i = 0; i < 64; i++) 618 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 619 for (i = 0; i < 64; i++) 620 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 621 for (i = 0; i < 64; i++) 622 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 623 for (i = 0; i < 64; i++) 624 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 625 for (i = 0; i < 64; i++) 626 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 627 for (i = 0; i < 16; i++) 628 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 629 for (i = 0; i < 16; i++) 630 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 631 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 632 for (i = 0; i < 8; i++) 633 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); 634 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 635 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); 636 637 /* Receive */ 638 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 639 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); 640 for (i = 0; i < 16; i++) 641 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 642 for (i = 0; i < 16; i++) 643 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 644 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); 645 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); 646 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 647 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); 648 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); 649 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 650 for (i = 0; i < 8; i++) 651 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); 652 for (i = 0; i < 8; i++) 653 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); 654 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); 655 656 /* Transmit */ 657 for (i = 0; i < 32; i++) 658 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 659 for (i = 0; i < 32; i++) 660 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 661 for (i = 0; i < 32; i++) 662 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 663 for (i = 0; i < 32; i++) 664 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 665 for (i = 0; i < 32; i++) 666 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 667 for (i = 0; i < 32; i++) 668 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 669 for (i = 0; i < 32; i++) 670 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); 671 for (i = 0; i < 32; i++) 672 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); 673 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 674 for (i = 0; i < 16; i++) 675 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 676 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); 677 for (i = 0; i < 8; i++) 678 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); 679 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); 680 681 /* Wake Up */ 682 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); 683 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); 684 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); 685 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); 686 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); 687 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 688 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 689 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 690 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); 691 692 /* DCB */ 693 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */ 694 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */ 695 696 switch (hw->mac.type) { 697 case ixgbe_mac_82598EB: 698 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 699 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); 700 for (i = 0; i < 8; i++) 701 regs_buff[833 + i] = 702 IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); 703 for (i = 0; i < 8; i++) 704 regs_buff[841 + i] = 705 IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); 706 for (i = 0; i < 8; i++) 707 regs_buff[849 + i] = 708 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); 709 for (i = 0; i < 8; i++) 710 regs_buff[857 + i] = 711 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); 712 break; 713 case ixgbe_mac_82599EB: 714 case ixgbe_mac_X540: 715 case ixgbe_mac_X550: 716 case ixgbe_mac_X550EM_x: 717 case ixgbe_mac_x550em_a: 718 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 719 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS); 720 for (i = 0; i < 8; i++) 721 regs_buff[833 + i] = 722 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i)); 723 for (i = 0; i < 8; i++) 724 regs_buff[841 + i] = 725 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i)); 726 for (i = 0; i < 8; i++) 727 regs_buff[849 + i] = 728 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i)); 729 for (i = 0; i < 8; i++) 730 regs_buff[857 + i] = 731 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i)); 732 break; 733 default: 734 break; 735 } 736 737 for (i = 0; i < 8; i++) 738 regs_buff[865 + i] = 739 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */ 740 for (i = 0; i < 8; i++) 741 regs_buff[873 + i] = 742 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */ 743 744 /* Statistics */ 745 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); 746 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); 747 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); 748 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); 749 for (i = 0; i < 8; i++) 750 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); 751 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); 752 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); 753 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); 754 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); 755 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); 756 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); 757 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); 758 for (i = 0; i < 8; i++) 759 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); 760 for (i = 0; i < 8; i++) 761 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); 762 for (i = 0; i < 8; i++) 763 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); 764 for (i = 0; i < 8; i++) 765 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); 766 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); 767 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); 768 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); 769 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); 770 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); 771 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); 772 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); 773 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); 774 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); 775 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); 776 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc); 777 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32); 778 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc); 779 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32); 780 for (i = 0; i < 8; i++) 781 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); 782 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); 783 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); 784 regs_buff[956] = IXGBE_GET_STAT(adapter, roc); 785 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); 786 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); 787 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); 788 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); 789 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor); 790 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32); 791 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); 792 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); 793 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); 794 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); 795 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); 796 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); 797 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); 798 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); 799 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); 800 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); 801 regs_buff[973] = IXGBE_GET_STAT(adapter, xec); 802 for (i = 0; i < 16; i++) 803 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); 804 for (i = 0; i < 16; i++) 805 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); 806 for (i = 0; i < 16; i++) 807 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); 808 for (i = 0; i < 16; i++) 809 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); 810 811 /* MAC */ 812 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); 813 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 814 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 815 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); 816 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); 817 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 818 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 819 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); 820 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); 821 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); 822 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); 823 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); 824 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); 825 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); 826 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); 827 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); 828 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); 829 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); 830 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); 831 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); 832 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); 833 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); 834 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); 835 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); 836 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); 837 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); 838 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); 839 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); 840 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 841 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); 842 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); 843 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); 844 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 845 846 /* Diagnostic */ 847 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); 848 for (i = 0; i < 8; i++) 849 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); 850 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); 851 for (i = 0; i < 4; i++) 852 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); 853 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); 854 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); 855 for (i = 0; i < 8; i++) 856 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); 857 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); 858 for (i = 0; i < 4; i++) 859 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); 860 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); 861 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); 862 for (i = 0; i < 4; i++) 863 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i)); 864 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); 865 for (i = 0; i < 4; i++) 866 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i)); 867 for (i = 0; i < 8; i++) 868 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); 869 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); 870 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); 871 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); 872 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); 873 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); 874 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); 875 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); 876 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); 877 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); 878 879 /* 82599 X540 specific registers */ 880 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN); 881 882 /* 82599 X540 specific DCB registers */ 883 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 884 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC); 885 for (i = 0; i < 4; i++) 886 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i)); 887 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM); 888 /* same as RTTQCNRM */ 889 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD); 890 /* same as RTTQCNRR */ 891 892 /* X540 specific DCB registers */ 893 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR); 894 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG); 895 } 896 897 static int ixgbe_get_eeprom_len(struct net_device *netdev) 898 { 899 struct ixgbe_adapter *adapter = netdev_priv(netdev); 900 return adapter->hw.eeprom.word_size * 2; 901 } 902 903 static int ixgbe_get_eeprom(struct net_device *netdev, 904 struct ethtool_eeprom *eeprom, u8 *bytes) 905 { 906 struct ixgbe_adapter *adapter = netdev_priv(netdev); 907 struct ixgbe_hw *hw = &adapter->hw; 908 u16 *eeprom_buff; 909 int first_word, last_word, eeprom_len; 910 int ret_val = 0; 911 u16 i; 912 913 if (eeprom->len == 0) 914 return -EINVAL; 915 916 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 917 918 first_word = eeprom->offset >> 1; 919 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 920 eeprom_len = last_word - first_word + 1; 921 922 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); 923 if (!eeprom_buff) 924 return -ENOMEM; 925 926 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len, 927 eeprom_buff); 928 929 /* Device's eeprom is always little-endian, word addressable */ 930 for (i = 0; i < eeprom_len; i++) 931 le16_to_cpus(&eeprom_buff[i]); 932 933 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 934 kfree(eeprom_buff); 935 936 return ret_val; 937 } 938 939 static int ixgbe_set_eeprom(struct net_device *netdev, 940 struct ethtool_eeprom *eeprom, u8 *bytes) 941 { 942 struct ixgbe_adapter *adapter = netdev_priv(netdev); 943 struct ixgbe_hw *hw = &adapter->hw; 944 u16 *eeprom_buff; 945 void *ptr; 946 int max_len, first_word, last_word, ret_val = 0; 947 u16 i; 948 949 if (eeprom->len == 0) 950 return -EINVAL; 951 952 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 953 return -EINVAL; 954 955 max_len = hw->eeprom.word_size * 2; 956 957 first_word = eeprom->offset >> 1; 958 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 959 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 960 if (!eeprom_buff) 961 return -ENOMEM; 962 963 ptr = eeprom_buff; 964 965 if (eeprom->offset & 1) { 966 /* 967 * need read/modify/write of first changed EEPROM word 968 * only the second byte of the word is being modified 969 */ 970 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]); 971 if (ret_val) 972 goto err; 973 974 ptr++; 975 } 976 if ((eeprom->offset + eeprom->len) & 1) { 977 /* 978 * need read/modify/write of last changed EEPROM word 979 * only the first byte of the word is being modified 980 */ 981 ret_val = hw->eeprom.ops.read(hw, last_word, 982 &eeprom_buff[last_word - first_word]); 983 if (ret_val) 984 goto err; 985 } 986 987 /* Device's eeprom is always little-endian, word addressable */ 988 for (i = 0; i < last_word - first_word + 1; i++) 989 le16_to_cpus(&eeprom_buff[i]); 990 991 memcpy(ptr, bytes, eeprom->len); 992 993 for (i = 0; i < last_word - first_word + 1; i++) 994 cpu_to_le16s(&eeprom_buff[i]); 995 996 ret_val = hw->eeprom.ops.write_buffer(hw, first_word, 997 last_word - first_word + 1, 998 eeprom_buff); 999 1000 /* Update the checksum */ 1001 if (ret_val == 0) 1002 hw->eeprom.ops.update_checksum(hw); 1003 1004 err: 1005 kfree(eeprom_buff); 1006 return ret_val; 1007 } 1008 1009 static void ixgbe_get_drvinfo(struct net_device *netdev, 1010 struct ethtool_drvinfo *drvinfo) 1011 { 1012 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1013 u32 nvm_track_id; 1014 1015 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver)); 1016 strlcpy(drvinfo->version, ixgbe_driver_version, 1017 sizeof(drvinfo->version)); 1018 1019 nvm_track_id = (adapter->eeprom_verh << 16) | 1020 adapter->eeprom_verl; 1021 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x", 1022 nvm_track_id); 1023 1024 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 1025 sizeof(drvinfo->bus_info)); 1026 1027 drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN; 1028 } 1029 1030 static void ixgbe_get_ringparam(struct net_device *netdev, 1031 struct ethtool_ringparam *ring) 1032 { 1033 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1034 struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; 1035 struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; 1036 1037 ring->rx_max_pending = IXGBE_MAX_RXD; 1038 ring->tx_max_pending = IXGBE_MAX_TXD; 1039 ring->rx_pending = rx_ring->count; 1040 ring->tx_pending = tx_ring->count; 1041 } 1042 1043 static int ixgbe_set_ringparam(struct net_device *netdev, 1044 struct ethtool_ringparam *ring) 1045 { 1046 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1047 struct ixgbe_ring *temp_ring; 1048 int i, err = 0; 1049 u32 new_rx_count, new_tx_count; 1050 1051 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 1052 return -EINVAL; 1053 1054 new_tx_count = clamp_t(u32, ring->tx_pending, 1055 IXGBE_MIN_TXD, IXGBE_MAX_TXD); 1056 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); 1057 1058 new_rx_count = clamp_t(u32, ring->rx_pending, 1059 IXGBE_MIN_RXD, IXGBE_MAX_RXD); 1060 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); 1061 1062 if ((new_tx_count == adapter->tx_ring_count) && 1063 (new_rx_count == adapter->rx_ring_count)) { 1064 /* nothing to do */ 1065 return 0; 1066 } 1067 1068 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 1069 usleep_range(1000, 2000); 1070 1071 if (!netif_running(adapter->netdev)) { 1072 for (i = 0; i < adapter->num_tx_queues; i++) 1073 adapter->tx_ring[i]->count = new_tx_count; 1074 for (i = 0; i < adapter->num_xdp_queues; i++) 1075 adapter->xdp_ring[i]->count = new_tx_count; 1076 for (i = 0; i < adapter->num_rx_queues; i++) 1077 adapter->rx_ring[i]->count = new_rx_count; 1078 adapter->tx_ring_count = new_tx_count; 1079 adapter->xdp_ring_count = new_tx_count; 1080 adapter->rx_ring_count = new_rx_count; 1081 goto clear_reset; 1082 } 1083 1084 /* allocate temporary buffer to store rings in */ 1085 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues); 1086 i = max_t(int, i, adapter->num_xdp_queues); 1087 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring)); 1088 1089 if (!temp_ring) { 1090 err = -ENOMEM; 1091 goto clear_reset; 1092 } 1093 1094 ixgbe_down(adapter); 1095 1096 /* 1097 * Setup new Tx resources and free the old Tx resources in that order. 1098 * We can then assign the new resources to the rings via a memcpy. 1099 * The advantage to this approach is that we are guaranteed to still 1100 * have resources even in the case of an allocation failure. 1101 */ 1102 if (new_tx_count != adapter->tx_ring_count) { 1103 for (i = 0; i < adapter->num_tx_queues; i++) { 1104 memcpy(&temp_ring[i], adapter->tx_ring[i], 1105 sizeof(struct ixgbe_ring)); 1106 1107 temp_ring[i].count = new_tx_count; 1108 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1109 if (err) { 1110 while (i) { 1111 i--; 1112 ixgbe_free_tx_resources(&temp_ring[i]); 1113 } 1114 goto err_setup; 1115 } 1116 } 1117 1118 for (i = 0; i < adapter->num_xdp_queues; i++) { 1119 memcpy(&temp_ring[i], adapter->xdp_ring[i], 1120 sizeof(struct ixgbe_ring)); 1121 1122 temp_ring[i].count = new_tx_count; 1123 err = ixgbe_setup_tx_resources(&temp_ring[i]); 1124 if (err) { 1125 while (i) { 1126 i--; 1127 ixgbe_free_tx_resources(&temp_ring[i]); 1128 } 1129 goto err_setup; 1130 } 1131 } 1132 1133 for (i = 0; i < adapter->num_tx_queues; i++) { 1134 ixgbe_free_tx_resources(adapter->tx_ring[i]); 1135 1136 memcpy(adapter->tx_ring[i], &temp_ring[i], 1137 sizeof(struct ixgbe_ring)); 1138 } 1139 for (i = 0; i < adapter->num_xdp_queues; i++) { 1140 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 1141 1142 memcpy(adapter->xdp_ring[i], &temp_ring[i], 1143 sizeof(struct ixgbe_ring)); 1144 } 1145 1146 adapter->tx_ring_count = new_tx_count; 1147 } 1148 1149 /* Repeat the process for the Rx rings if needed */ 1150 if (new_rx_count != adapter->rx_ring_count) { 1151 for (i = 0; i < adapter->num_rx_queues; i++) { 1152 memcpy(&temp_ring[i], adapter->rx_ring[i], 1153 sizeof(struct ixgbe_ring)); 1154 1155 temp_ring[i].count = new_rx_count; 1156 err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]); 1157 if (err) { 1158 while (i) { 1159 i--; 1160 ixgbe_free_rx_resources(&temp_ring[i]); 1161 } 1162 goto err_setup; 1163 } 1164 1165 } 1166 1167 for (i = 0; i < adapter->num_rx_queues; i++) { 1168 ixgbe_free_rx_resources(adapter->rx_ring[i]); 1169 1170 memcpy(adapter->rx_ring[i], &temp_ring[i], 1171 sizeof(struct ixgbe_ring)); 1172 } 1173 1174 adapter->rx_ring_count = new_rx_count; 1175 } 1176 1177 err_setup: 1178 ixgbe_up(adapter); 1179 vfree(temp_ring); 1180 clear_reset: 1181 clear_bit(__IXGBE_RESETTING, &adapter->state); 1182 return err; 1183 } 1184 1185 static int ixgbe_get_sset_count(struct net_device *netdev, int sset) 1186 { 1187 switch (sset) { 1188 case ETH_SS_TEST: 1189 return IXGBE_TEST_LEN; 1190 case ETH_SS_STATS: 1191 return IXGBE_STATS_LEN; 1192 case ETH_SS_PRIV_FLAGS: 1193 return IXGBE_PRIV_FLAGS_STR_LEN; 1194 default: 1195 return -EOPNOTSUPP; 1196 } 1197 } 1198 1199 static void ixgbe_get_ethtool_stats(struct net_device *netdev, 1200 struct ethtool_stats *stats, u64 *data) 1201 { 1202 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1203 struct rtnl_link_stats64 temp; 1204 const struct rtnl_link_stats64 *net_stats; 1205 unsigned int start; 1206 struct ixgbe_ring *ring; 1207 int i, j; 1208 char *p = NULL; 1209 1210 ixgbe_update_stats(adapter); 1211 net_stats = dev_get_stats(netdev, &temp); 1212 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1213 switch (ixgbe_gstrings_stats[i].type) { 1214 case NETDEV_STATS: 1215 p = (char *) net_stats + 1216 ixgbe_gstrings_stats[i].stat_offset; 1217 break; 1218 case IXGBE_STATS: 1219 p = (char *) adapter + 1220 ixgbe_gstrings_stats[i].stat_offset; 1221 break; 1222 default: 1223 data[i] = 0; 1224 continue; 1225 } 1226 1227 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == 1228 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 1229 } 1230 for (j = 0; j < netdev->num_tx_queues; j++) { 1231 ring = adapter->tx_ring[j]; 1232 if (!ring) { 1233 data[i] = 0; 1234 data[i+1] = 0; 1235 i += 2; 1236 continue; 1237 } 1238 1239 do { 1240 start = u64_stats_fetch_begin_irq(&ring->syncp); 1241 data[i] = ring->stats.packets; 1242 data[i+1] = ring->stats.bytes; 1243 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1244 i += 2; 1245 } 1246 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) { 1247 ring = adapter->rx_ring[j]; 1248 if (!ring) { 1249 data[i] = 0; 1250 data[i+1] = 0; 1251 i += 2; 1252 continue; 1253 } 1254 1255 do { 1256 start = u64_stats_fetch_begin_irq(&ring->syncp); 1257 data[i] = ring->stats.packets; 1258 data[i+1] = ring->stats.bytes; 1259 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1260 i += 2; 1261 } 1262 1263 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1264 data[i++] = adapter->stats.pxontxc[j]; 1265 data[i++] = adapter->stats.pxofftxc[j]; 1266 } 1267 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) { 1268 data[i++] = adapter->stats.pxonrxc[j]; 1269 data[i++] = adapter->stats.pxoffrxc[j]; 1270 } 1271 } 1272 1273 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, 1274 u8 *data) 1275 { 1276 char *p = (char *)data; 1277 int i; 1278 1279 switch (stringset) { 1280 case ETH_SS_TEST: 1281 for (i = 0; i < IXGBE_TEST_LEN; i++) { 1282 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN); 1283 data += ETH_GSTRING_LEN; 1284 } 1285 break; 1286 case ETH_SS_STATS: 1287 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { 1288 memcpy(p, ixgbe_gstrings_stats[i].stat_string, 1289 ETH_GSTRING_LEN); 1290 p += ETH_GSTRING_LEN; 1291 } 1292 for (i = 0; i < netdev->num_tx_queues; i++) { 1293 sprintf(p, "tx_queue_%u_packets", i); 1294 p += ETH_GSTRING_LEN; 1295 sprintf(p, "tx_queue_%u_bytes", i); 1296 p += ETH_GSTRING_LEN; 1297 } 1298 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) { 1299 sprintf(p, "rx_queue_%u_packets", i); 1300 p += ETH_GSTRING_LEN; 1301 sprintf(p, "rx_queue_%u_bytes", i); 1302 p += ETH_GSTRING_LEN; 1303 } 1304 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1305 sprintf(p, "tx_pb_%u_pxon", i); 1306 p += ETH_GSTRING_LEN; 1307 sprintf(p, "tx_pb_%u_pxoff", i); 1308 p += ETH_GSTRING_LEN; 1309 } 1310 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 1311 sprintf(p, "rx_pb_%u_pxon", i); 1312 p += ETH_GSTRING_LEN; 1313 sprintf(p, "rx_pb_%u_pxoff", i); 1314 p += ETH_GSTRING_LEN; 1315 } 1316 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ 1317 break; 1318 case ETH_SS_PRIV_FLAGS: 1319 memcpy(data, ixgbe_priv_flags_strings, 1320 IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN); 1321 } 1322 } 1323 1324 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) 1325 { 1326 struct ixgbe_hw *hw = &adapter->hw; 1327 bool link_up; 1328 u32 link_speed = 0; 1329 1330 if (ixgbe_removed(hw->hw_addr)) { 1331 *data = 1; 1332 return 1; 1333 } 1334 *data = 0; 1335 1336 hw->mac.ops.check_link(hw, &link_speed, &link_up, true); 1337 if (link_up) 1338 return *data; 1339 else 1340 *data = 1; 1341 return *data; 1342 } 1343 1344 /* ethtool register test data */ 1345 struct ixgbe_reg_test { 1346 u16 reg; 1347 u8 array_len; 1348 u8 test_type; 1349 u32 mask; 1350 u32 write; 1351 }; 1352 1353 /* In the hardware, registers are laid out either singly, in arrays 1354 * spaced 0x40 bytes apart, or in contiguous tables. We assume 1355 * most tests take place on arrays or single registers (handled 1356 * as a single-element array) and special-case the tables. 1357 * Table tests are always pattern tests. 1358 * 1359 * We also make provision for some required setup steps by specifying 1360 * registers to be written without any read-back testing. 1361 */ 1362 1363 #define PATTERN_TEST 1 1364 #define SET_READ_TEST 2 1365 #define WRITE_NO_TEST 3 1366 #define TABLE32_TEST 4 1367 #define TABLE64_TEST_LO 5 1368 #define TABLE64_TEST_HI 6 1369 1370 /* default 82599 register test */ 1371 static const struct ixgbe_reg_test reg_test_82599[] = { 1372 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1373 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1374 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1375 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1376 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 1377 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1378 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1379 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1380 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1381 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1382 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1383 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1384 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1385 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1386 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, 1387 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, 1388 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1389 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, 1390 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1391 { .reg = 0 } 1392 }; 1393 1394 /* default 82598 register test */ 1395 static const struct ixgbe_reg_test reg_test_82598[] = { 1396 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1397 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1398 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1399 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, 1400 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1401 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1402 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1403 /* Enable all four RX queues before testing. */ 1404 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, 1405 /* RDH is read-only for 82598, only test RDT. */ 1406 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1407 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, 1408 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, 1409 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1410 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, 1411 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1412 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1413 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1414 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, 1415 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, 1416 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1417 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, 1418 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1419 { .reg = 0 } 1420 }; 1421 1422 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, 1423 u32 mask, u32 write) 1424 { 1425 u32 pat, val, before; 1426 static const u32 test_pattern[] = { 1427 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1428 1429 if (ixgbe_removed(adapter->hw.hw_addr)) { 1430 *data = 1; 1431 return true; 1432 } 1433 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) { 1434 before = ixgbe_read_reg(&adapter->hw, reg); 1435 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); 1436 val = ixgbe_read_reg(&adapter->hw, reg); 1437 if (val != (test_pattern[pat] & write & mask)) { 1438 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1439 reg, val, (test_pattern[pat] & write & mask)); 1440 *data = reg; 1441 ixgbe_write_reg(&adapter->hw, reg, before); 1442 return true; 1443 } 1444 ixgbe_write_reg(&adapter->hw, reg, before); 1445 } 1446 return false; 1447 } 1448 1449 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, 1450 u32 mask, u32 write) 1451 { 1452 u32 val, before; 1453 1454 if (ixgbe_removed(adapter->hw.hw_addr)) { 1455 *data = 1; 1456 return true; 1457 } 1458 before = ixgbe_read_reg(&adapter->hw, reg); 1459 ixgbe_write_reg(&adapter->hw, reg, write & mask); 1460 val = ixgbe_read_reg(&adapter->hw, reg); 1461 if ((write & mask) != (val & mask)) { 1462 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", 1463 reg, (val & mask), (write & mask)); 1464 *data = reg; 1465 ixgbe_write_reg(&adapter->hw, reg, before); 1466 return true; 1467 } 1468 ixgbe_write_reg(&adapter->hw, reg, before); 1469 return false; 1470 } 1471 1472 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) 1473 { 1474 const struct ixgbe_reg_test *test; 1475 u32 value, before, after; 1476 u32 i, toggle; 1477 1478 if (ixgbe_removed(adapter->hw.hw_addr)) { 1479 e_err(drv, "Adapter removed - register test blocked\n"); 1480 *data = 1; 1481 return 1; 1482 } 1483 switch (adapter->hw.mac.type) { 1484 case ixgbe_mac_82598EB: 1485 toggle = 0x7FFFF3FF; 1486 test = reg_test_82598; 1487 break; 1488 case ixgbe_mac_82599EB: 1489 case ixgbe_mac_X540: 1490 case ixgbe_mac_X550: 1491 case ixgbe_mac_X550EM_x: 1492 case ixgbe_mac_x550em_a: 1493 toggle = 0x7FFFF30F; 1494 test = reg_test_82599; 1495 break; 1496 default: 1497 *data = 1; 1498 return 1; 1499 } 1500 1501 /* 1502 * Because the status register is such a special case, 1503 * we handle it separately from the rest of the register 1504 * tests. Some bits are read-only, some toggle, and some 1505 * are writeable on newer MACs. 1506 */ 1507 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS); 1508 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle); 1509 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle); 1510 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle; 1511 if (value != after) { 1512 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1513 after, value); 1514 *data = 1; 1515 return 1; 1516 } 1517 /* restore previous status */ 1518 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before); 1519 1520 /* 1521 * Perform the remainder of the register test, looping through 1522 * the test table until we either fail or reach the null entry. 1523 */ 1524 while (test->reg) { 1525 for (i = 0; i < test->array_len; i++) { 1526 bool b = false; 1527 1528 switch (test->test_type) { 1529 case PATTERN_TEST: 1530 b = reg_pattern_test(adapter, data, 1531 test->reg + (i * 0x40), 1532 test->mask, 1533 test->write); 1534 break; 1535 case SET_READ_TEST: 1536 b = reg_set_and_check(adapter, data, 1537 test->reg + (i * 0x40), 1538 test->mask, 1539 test->write); 1540 break; 1541 case WRITE_NO_TEST: 1542 ixgbe_write_reg(&adapter->hw, 1543 test->reg + (i * 0x40), 1544 test->write); 1545 break; 1546 case TABLE32_TEST: 1547 b = reg_pattern_test(adapter, data, 1548 test->reg + (i * 4), 1549 test->mask, 1550 test->write); 1551 break; 1552 case TABLE64_TEST_LO: 1553 b = reg_pattern_test(adapter, data, 1554 test->reg + (i * 8), 1555 test->mask, 1556 test->write); 1557 break; 1558 case TABLE64_TEST_HI: 1559 b = reg_pattern_test(adapter, data, 1560 (test->reg + 4) + (i * 8), 1561 test->mask, 1562 test->write); 1563 break; 1564 } 1565 if (b) 1566 return 1; 1567 } 1568 test++; 1569 } 1570 1571 *data = 0; 1572 return 0; 1573 } 1574 1575 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) 1576 { 1577 struct ixgbe_hw *hw = &adapter->hw; 1578 if (hw->eeprom.ops.validate_checksum(hw, NULL)) 1579 *data = 1; 1580 else 1581 *data = 0; 1582 return *data; 1583 } 1584 1585 static irqreturn_t ixgbe_test_intr(int irq, void *data) 1586 { 1587 struct net_device *netdev = (struct net_device *) data; 1588 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1589 1590 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); 1591 1592 return IRQ_HANDLED; 1593 } 1594 1595 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) 1596 { 1597 struct net_device *netdev = adapter->netdev; 1598 u32 mask, i = 0, shared_int = true; 1599 u32 irq = adapter->pdev->irq; 1600 1601 *data = 0; 1602 1603 /* Hook up test interrupt handler just for this test */ 1604 if (adapter->msix_entries) { 1605 /* NOTE: we don't test MSI-X interrupts here, yet */ 1606 return 0; 1607 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { 1608 shared_int = false; 1609 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, 1610 netdev)) { 1611 *data = 1; 1612 return -1; 1613 } 1614 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, 1615 netdev->name, netdev)) { 1616 shared_int = false; 1617 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, 1618 netdev->name, netdev)) { 1619 *data = 1; 1620 return -1; 1621 } 1622 e_info(hw, "testing %s interrupt\n", shared_int ? 1623 "shared" : "unshared"); 1624 1625 /* Disable all the interrupts */ 1626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1627 IXGBE_WRITE_FLUSH(&adapter->hw); 1628 usleep_range(10000, 20000); 1629 1630 /* Test each interrupt */ 1631 for (; i < 10; i++) { 1632 /* Interrupt to test */ 1633 mask = BIT(i); 1634 1635 if (!shared_int) { 1636 /* 1637 * Disable the interrupts to be reported in 1638 * the cause register and then force the same 1639 * interrupt and see if one gets posted. If 1640 * an interrupt was posted to the bus, the 1641 * test failed. 1642 */ 1643 adapter->test_icr = 0; 1644 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1645 ~mask & 0x00007FFF); 1646 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1647 ~mask & 0x00007FFF); 1648 IXGBE_WRITE_FLUSH(&adapter->hw); 1649 usleep_range(10000, 20000); 1650 1651 if (adapter->test_icr & mask) { 1652 *data = 3; 1653 break; 1654 } 1655 } 1656 1657 /* 1658 * Enable the interrupt to be reported in the cause 1659 * register and then force the same interrupt and see 1660 * if one gets posted. If an interrupt was not posted 1661 * to the bus, the test failed. 1662 */ 1663 adapter->test_icr = 0; 1664 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 1665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 1666 IXGBE_WRITE_FLUSH(&adapter->hw); 1667 usleep_range(10000, 20000); 1668 1669 if (!(adapter->test_icr & mask)) { 1670 *data = 4; 1671 break; 1672 } 1673 1674 if (!shared_int) { 1675 /* 1676 * Disable the other interrupts to be reported in 1677 * the cause register and then force the other 1678 * interrupts and see if any get posted. If 1679 * an interrupt was posted to the bus, the 1680 * test failed. 1681 */ 1682 adapter->test_icr = 0; 1683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 1684 ~mask & 0x00007FFF); 1685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, 1686 ~mask & 0x00007FFF); 1687 IXGBE_WRITE_FLUSH(&adapter->hw); 1688 usleep_range(10000, 20000); 1689 1690 if (adapter->test_icr) { 1691 *data = 5; 1692 break; 1693 } 1694 } 1695 } 1696 1697 /* Disable all the interrupts */ 1698 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); 1699 IXGBE_WRITE_FLUSH(&adapter->hw); 1700 usleep_range(10000, 20000); 1701 1702 /* Unhook test interrupt handler */ 1703 free_irq(irq, netdev); 1704 1705 return *data; 1706 } 1707 1708 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) 1709 { 1710 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1711 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1712 struct ixgbe_hw *hw = &adapter->hw; 1713 u32 reg_ctl; 1714 1715 /* shut down the DMA engines now so they can be reinitialized later */ 1716 1717 /* first Rx */ 1718 hw->mac.ops.disable_rx(hw); 1719 ixgbe_disable_rx_queue(adapter, rx_ring); 1720 1721 /* now Tx */ 1722 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx)); 1723 reg_ctl &= ~IXGBE_TXDCTL_ENABLE; 1724 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl); 1725 1726 switch (hw->mac.type) { 1727 case ixgbe_mac_82599EB: 1728 case ixgbe_mac_X540: 1729 case ixgbe_mac_X550: 1730 case ixgbe_mac_X550EM_x: 1731 case ixgbe_mac_x550em_a: 1732 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1733 reg_ctl &= ~IXGBE_DMATXCTL_TE; 1734 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); 1735 break; 1736 default: 1737 break; 1738 } 1739 1740 ixgbe_reset(adapter); 1741 1742 ixgbe_free_tx_resources(&adapter->test_tx_ring); 1743 ixgbe_free_rx_resources(&adapter->test_rx_ring); 1744 } 1745 1746 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) 1747 { 1748 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1749 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1750 struct ixgbe_hw *hw = &adapter->hw; 1751 u32 rctl, reg_data; 1752 int ret_val; 1753 int err; 1754 1755 /* Setup Tx descriptor ring and Tx buffers */ 1756 tx_ring->count = IXGBE_DEFAULT_TXD; 1757 tx_ring->queue_index = 0; 1758 tx_ring->dev = &adapter->pdev->dev; 1759 tx_ring->netdev = adapter->netdev; 1760 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx; 1761 1762 err = ixgbe_setup_tx_resources(tx_ring); 1763 if (err) 1764 return 1; 1765 1766 switch (adapter->hw.mac.type) { 1767 case ixgbe_mac_82599EB: 1768 case ixgbe_mac_X540: 1769 case ixgbe_mac_X550: 1770 case ixgbe_mac_X550EM_x: 1771 case ixgbe_mac_x550em_a: 1772 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); 1773 reg_data |= IXGBE_DMATXCTL_TE; 1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); 1775 break; 1776 default: 1777 break; 1778 } 1779 1780 ixgbe_configure_tx_ring(adapter, tx_ring); 1781 1782 /* Setup Rx Descriptor ring and Rx buffers */ 1783 rx_ring->count = IXGBE_DEFAULT_RXD; 1784 rx_ring->queue_index = 0; 1785 rx_ring->dev = &adapter->pdev->dev; 1786 rx_ring->netdev = adapter->netdev; 1787 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx; 1788 1789 err = ixgbe_setup_rx_resources(adapter, rx_ring); 1790 if (err) { 1791 ret_val = 4; 1792 goto err_nomem; 1793 } 1794 1795 hw->mac.ops.disable_rx(hw); 1796 1797 ixgbe_configure_rx_ring(adapter, rx_ring); 1798 1799 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); 1800 rctl |= IXGBE_RXCTRL_DMBYPS; 1801 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); 1802 1803 hw->mac.ops.enable_rx(hw); 1804 1805 return 0; 1806 1807 err_nomem: 1808 ixgbe_free_desc_rings(adapter); 1809 return ret_val; 1810 } 1811 1812 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) 1813 { 1814 struct ixgbe_hw *hw = &adapter->hw; 1815 u32 reg_data; 1816 1817 1818 /* Setup MAC loopback */ 1819 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1820 reg_data |= IXGBE_HLREG0_LPBK; 1821 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data); 1822 1823 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1824 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; 1825 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data); 1826 1827 /* X540 and X550 needs to set the MACC.FLU bit to force link up */ 1828 switch (adapter->hw.mac.type) { 1829 case ixgbe_mac_X540: 1830 case ixgbe_mac_X550: 1831 case ixgbe_mac_X550EM_x: 1832 case ixgbe_mac_x550em_a: 1833 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC); 1834 reg_data |= IXGBE_MACC_FLU; 1835 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data); 1836 break; 1837 default: 1838 if (hw->mac.orig_autoc) { 1839 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU; 1840 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data); 1841 } else { 1842 return 10; 1843 } 1844 } 1845 IXGBE_WRITE_FLUSH(hw); 1846 usleep_range(10000, 20000); 1847 1848 /* Disable Atlas Tx lanes; re-enabled in reset path */ 1849 if (hw->mac.type == ixgbe_mac_82598EB) { 1850 u8 atlas; 1851 1852 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); 1853 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; 1854 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); 1855 1856 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); 1857 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 1858 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); 1859 1860 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); 1861 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 1862 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); 1863 1864 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); 1865 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 1866 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); 1867 } 1868 1869 return 0; 1870 } 1871 1872 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) 1873 { 1874 u32 reg_data; 1875 1876 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); 1877 reg_data &= ~IXGBE_HLREG0_LPBK; 1878 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); 1879 } 1880 1881 static void ixgbe_create_lbtest_frame(struct sk_buff *skb, 1882 unsigned int frame_size) 1883 { 1884 memset(skb->data, 0xFF, frame_size); 1885 frame_size >>= 1; 1886 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1); 1887 memset(&skb->data[frame_size + 10], 0xBE, 1); 1888 memset(&skb->data[frame_size + 12], 0xAF, 1); 1889 } 1890 1891 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer, 1892 unsigned int frame_size) 1893 { 1894 unsigned char *data; 1895 bool match = true; 1896 1897 frame_size >>= 1; 1898 1899 data = kmap(rx_buffer->page) + rx_buffer->page_offset; 1900 1901 if (data[3] != 0xFF || 1902 data[frame_size + 10] != 0xBE || 1903 data[frame_size + 12] != 0xAF) 1904 match = false; 1905 1906 kunmap(rx_buffer->page); 1907 1908 return match; 1909 } 1910 1911 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring, 1912 struct ixgbe_ring *tx_ring, 1913 unsigned int size) 1914 { 1915 union ixgbe_adv_rx_desc *rx_desc; 1916 struct ixgbe_rx_buffer *rx_buffer; 1917 struct ixgbe_tx_buffer *tx_buffer; 1918 u16 rx_ntc, tx_ntc, count = 0; 1919 1920 /* initialize next to clean and descriptor values */ 1921 rx_ntc = rx_ring->next_to_clean; 1922 tx_ntc = tx_ring->next_to_clean; 1923 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1924 1925 while (rx_desc->wb.upper.length) { 1926 /* check Rx buffer */ 1927 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc]; 1928 1929 /* sync Rx buffer for CPU read */ 1930 dma_sync_single_for_cpu(rx_ring->dev, 1931 rx_buffer->dma, 1932 ixgbe_rx_bufsz(rx_ring), 1933 DMA_FROM_DEVICE); 1934 1935 /* verify contents of skb */ 1936 if (ixgbe_check_lbtest_frame(rx_buffer, size)) 1937 count++; 1938 1939 /* sync Rx buffer for device write */ 1940 dma_sync_single_for_device(rx_ring->dev, 1941 rx_buffer->dma, 1942 ixgbe_rx_bufsz(rx_ring), 1943 DMA_FROM_DEVICE); 1944 1945 /* unmap buffer on Tx side */ 1946 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc]; 1947 1948 /* Free all the Tx ring sk_buffs */ 1949 dev_kfree_skb_any(tx_buffer->skb); 1950 1951 /* unmap skb header data */ 1952 dma_unmap_single(tx_ring->dev, 1953 dma_unmap_addr(tx_buffer, dma), 1954 dma_unmap_len(tx_buffer, len), 1955 DMA_TO_DEVICE); 1956 dma_unmap_len_set(tx_buffer, len, 0); 1957 1958 /* increment Rx/Tx next to clean counters */ 1959 rx_ntc++; 1960 if (rx_ntc == rx_ring->count) 1961 rx_ntc = 0; 1962 tx_ntc++; 1963 if (tx_ntc == tx_ring->count) 1964 tx_ntc = 0; 1965 1966 /* fetch next descriptor */ 1967 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc); 1968 } 1969 1970 netdev_tx_reset_queue(txring_txq(tx_ring)); 1971 1972 /* re-map buffers to ring, store next to clean values */ 1973 ixgbe_alloc_rx_buffers(rx_ring, count); 1974 rx_ring->next_to_clean = rx_ntc; 1975 tx_ring->next_to_clean = tx_ntc; 1976 1977 return count; 1978 } 1979 1980 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) 1981 { 1982 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; 1983 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; 1984 int i, j, lc, good_cnt, ret_val = 0; 1985 unsigned int size = 1024; 1986 netdev_tx_t tx_ret_val; 1987 struct sk_buff *skb; 1988 u32 flags_orig = adapter->flags; 1989 1990 /* DCB can modify the frames on Tx */ 1991 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 1992 1993 /* allocate test skb */ 1994 skb = alloc_skb(size, GFP_KERNEL); 1995 if (!skb) 1996 return 11; 1997 1998 /* place data into test skb */ 1999 ixgbe_create_lbtest_frame(skb, size); 2000 skb_put(skb, size); 2001 2002 /* 2003 * Calculate the loop count based on the largest descriptor ring 2004 * The idea is to wrap the largest ring a number of times using 64 2005 * send/receive pairs during each loop 2006 */ 2007 2008 if (rx_ring->count <= tx_ring->count) 2009 lc = ((tx_ring->count / 64) * 2) + 1; 2010 else 2011 lc = ((rx_ring->count / 64) * 2) + 1; 2012 2013 for (j = 0; j <= lc; j++) { 2014 /* reset count of good packets */ 2015 good_cnt = 0; 2016 2017 /* place 64 packets on the transmit queue*/ 2018 for (i = 0; i < 64; i++) { 2019 skb_get(skb); 2020 tx_ret_val = ixgbe_xmit_frame_ring(skb, 2021 adapter, 2022 tx_ring); 2023 if (tx_ret_val == NETDEV_TX_OK) 2024 good_cnt++; 2025 } 2026 2027 if (good_cnt != 64) { 2028 ret_val = 12; 2029 break; 2030 } 2031 2032 /* allow 200 milliseconds for packets to go from Tx to Rx */ 2033 msleep(200); 2034 2035 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size); 2036 if (good_cnt != 64) { 2037 ret_val = 13; 2038 break; 2039 } 2040 } 2041 2042 /* free the original skb */ 2043 kfree_skb(skb); 2044 adapter->flags = flags_orig; 2045 2046 return ret_val; 2047 } 2048 2049 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) 2050 { 2051 *data = ixgbe_setup_desc_rings(adapter); 2052 if (*data) 2053 goto out; 2054 *data = ixgbe_setup_loopback_test(adapter); 2055 if (*data) 2056 goto err_loopback; 2057 *data = ixgbe_run_loopback_test(adapter); 2058 ixgbe_loopback_cleanup(adapter); 2059 2060 err_loopback: 2061 ixgbe_free_desc_rings(adapter); 2062 out: 2063 return *data; 2064 } 2065 2066 static void ixgbe_diag_test(struct net_device *netdev, 2067 struct ethtool_test *eth_test, u64 *data) 2068 { 2069 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2070 bool if_running = netif_running(netdev); 2071 2072 if (ixgbe_removed(adapter->hw.hw_addr)) { 2073 e_err(hw, "Adapter removed - test blocked\n"); 2074 data[0] = 1; 2075 data[1] = 1; 2076 data[2] = 1; 2077 data[3] = 1; 2078 data[4] = 1; 2079 eth_test->flags |= ETH_TEST_FL_FAILED; 2080 return; 2081 } 2082 set_bit(__IXGBE_TESTING, &adapter->state); 2083 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 2084 struct ixgbe_hw *hw = &adapter->hw; 2085 2086 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 2087 int i; 2088 for (i = 0; i < adapter->num_vfs; i++) { 2089 if (adapter->vfinfo[i].clear_to_send) { 2090 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n"); 2091 data[0] = 1; 2092 data[1] = 1; 2093 data[2] = 1; 2094 data[3] = 1; 2095 data[4] = 1; 2096 eth_test->flags |= ETH_TEST_FL_FAILED; 2097 clear_bit(__IXGBE_TESTING, 2098 &adapter->state); 2099 goto skip_ol_tests; 2100 } 2101 } 2102 } 2103 2104 /* Offline tests */ 2105 e_info(hw, "offline testing starting\n"); 2106 2107 /* Link test performed before hardware reset so autoneg doesn't 2108 * interfere with test result 2109 */ 2110 if (ixgbe_link_test(adapter, &data[4])) 2111 eth_test->flags |= ETH_TEST_FL_FAILED; 2112 2113 if (if_running) 2114 /* indicate we're in test mode */ 2115 ixgbe_close(netdev); 2116 else 2117 ixgbe_reset(adapter); 2118 2119 e_info(hw, "register testing starting\n"); 2120 if (ixgbe_reg_test(adapter, &data[0])) 2121 eth_test->flags |= ETH_TEST_FL_FAILED; 2122 2123 ixgbe_reset(adapter); 2124 e_info(hw, "eeprom testing starting\n"); 2125 if (ixgbe_eeprom_test(adapter, &data[1])) 2126 eth_test->flags |= ETH_TEST_FL_FAILED; 2127 2128 ixgbe_reset(adapter); 2129 e_info(hw, "interrupt testing starting\n"); 2130 if (ixgbe_intr_test(adapter, &data[2])) 2131 eth_test->flags |= ETH_TEST_FL_FAILED; 2132 2133 /* If SRIOV or VMDq is enabled then skip MAC 2134 * loopback diagnostic. */ 2135 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | 2136 IXGBE_FLAG_VMDQ_ENABLED)) { 2137 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n"); 2138 data[3] = 0; 2139 goto skip_loopback; 2140 } 2141 2142 ixgbe_reset(adapter); 2143 e_info(hw, "loopback testing starting\n"); 2144 if (ixgbe_loopback_test(adapter, &data[3])) 2145 eth_test->flags |= ETH_TEST_FL_FAILED; 2146 2147 skip_loopback: 2148 ixgbe_reset(adapter); 2149 2150 /* clear testing bit and return adapter to previous state */ 2151 clear_bit(__IXGBE_TESTING, &adapter->state); 2152 if (if_running) 2153 ixgbe_open(netdev); 2154 else if (hw->mac.ops.disable_tx_laser) 2155 hw->mac.ops.disable_tx_laser(hw); 2156 } else { 2157 e_info(hw, "online testing starting\n"); 2158 2159 /* Online tests */ 2160 if (ixgbe_link_test(adapter, &data[4])) 2161 eth_test->flags |= ETH_TEST_FL_FAILED; 2162 2163 /* Offline tests aren't run; pass by default */ 2164 data[0] = 0; 2165 data[1] = 0; 2166 data[2] = 0; 2167 data[3] = 0; 2168 2169 clear_bit(__IXGBE_TESTING, &adapter->state); 2170 } 2171 2172 skip_ol_tests: 2173 msleep_interruptible(4 * 1000); 2174 } 2175 2176 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, 2177 struct ethtool_wolinfo *wol) 2178 { 2179 struct ixgbe_hw *hw = &adapter->hw; 2180 int retval = 0; 2181 2182 /* WOL not supported for all devices */ 2183 if (!ixgbe_wol_supported(adapter, hw->device_id, 2184 hw->subsystem_device_id)) { 2185 retval = 1; 2186 wol->supported = 0; 2187 } 2188 2189 return retval; 2190 } 2191 2192 static void ixgbe_get_wol(struct net_device *netdev, 2193 struct ethtool_wolinfo *wol) 2194 { 2195 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2196 2197 wol->supported = WAKE_UCAST | WAKE_MCAST | 2198 WAKE_BCAST | WAKE_MAGIC; 2199 wol->wolopts = 0; 2200 2201 if (ixgbe_wol_exclusion(adapter, wol) || 2202 !device_can_wakeup(&adapter->pdev->dev)) 2203 return; 2204 2205 if (adapter->wol & IXGBE_WUFC_EX) 2206 wol->wolopts |= WAKE_UCAST; 2207 if (adapter->wol & IXGBE_WUFC_MC) 2208 wol->wolopts |= WAKE_MCAST; 2209 if (adapter->wol & IXGBE_WUFC_BC) 2210 wol->wolopts |= WAKE_BCAST; 2211 if (adapter->wol & IXGBE_WUFC_MAG) 2212 wol->wolopts |= WAKE_MAGIC; 2213 } 2214 2215 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2216 { 2217 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2218 2219 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 2220 return -EOPNOTSUPP; 2221 2222 if (ixgbe_wol_exclusion(adapter, wol)) 2223 return wol->wolopts ? -EOPNOTSUPP : 0; 2224 2225 adapter->wol = 0; 2226 2227 if (wol->wolopts & WAKE_UCAST) 2228 adapter->wol |= IXGBE_WUFC_EX; 2229 if (wol->wolopts & WAKE_MCAST) 2230 adapter->wol |= IXGBE_WUFC_MC; 2231 if (wol->wolopts & WAKE_BCAST) 2232 adapter->wol |= IXGBE_WUFC_BC; 2233 if (wol->wolopts & WAKE_MAGIC) 2234 adapter->wol |= IXGBE_WUFC_MAG; 2235 2236 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2237 2238 return 0; 2239 } 2240 2241 static int ixgbe_nway_reset(struct net_device *netdev) 2242 { 2243 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2244 2245 if (netif_running(netdev)) 2246 ixgbe_reinit_locked(adapter); 2247 2248 return 0; 2249 } 2250 2251 static int ixgbe_set_phys_id(struct net_device *netdev, 2252 enum ethtool_phys_id_state state) 2253 { 2254 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2255 struct ixgbe_hw *hw = &adapter->hw; 2256 2257 switch (state) { 2258 case ETHTOOL_ID_ACTIVE: 2259 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2260 return 2; 2261 2262 case ETHTOOL_ID_ON: 2263 hw->mac.ops.led_on(hw, hw->mac.led_link_act); 2264 break; 2265 2266 case ETHTOOL_ID_OFF: 2267 hw->mac.ops.led_off(hw, hw->mac.led_link_act); 2268 break; 2269 2270 case ETHTOOL_ID_INACTIVE: 2271 /* Restore LED settings */ 2272 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg); 2273 break; 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int ixgbe_get_coalesce(struct net_device *netdev, 2280 struct ethtool_coalesce *ec) 2281 { 2282 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2283 2284 /* only valid if in constant ITR mode */ 2285 if (adapter->rx_itr_setting <= 1) 2286 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2287 else 2288 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2289 2290 /* if in mixed tx/rx queues per vector mode, report only rx settings */ 2291 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2292 return 0; 2293 2294 /* only valid if in constant ITR mode */ 2295 if (adapter->tx_itr_setting <= 1) 2296 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2297 else 2298 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2299 2300 return 0; 2301 } 2302 2303 /* 2304 * this function must be called before setting the new value of 2305 * rx_itr_setting 2306 */ 2307 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter) 2308 { 2309 struct net_device *netdev = adapter->netdev; 2310 2311 /* nothing to do if LRO or RSC are not enabled */ 2312 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) || 2313 !(netdev->features & NETIF_F_LRO)) 2314 return false; 2315 2316 /* check the feature flag value and enable RSC if necessary */ 2317 if (adapter->rx_itr_setting == 1 || 2318 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 2319 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 2320 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 2321 e_info(probe, "rx-usecs value high enough to re-enable RSC\n"); 2322 return true; 2323 } 2324 /* if interrupt rate is too high then disable RSC */ 2325 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 2326 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 2327 e_info(probe, "rx-usecs set too low, disabling RSC\n"); 2328 return true; 2329 } 2330 return false; 2331 } 2332 2333 static int ixgbe_set_coalesce(struct net_device *netdev, 2334 struct ethtool_coalesce *ec) 2335 { 2336 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2337 struct ixgbe_q_vector *q_vector; 2338 int i; 2339 u16 tx_itr_param, rx_itr_param, tx_itr_prev; 2340 bool need_reset = false; 2341 2342 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) { 2343 /* reject Tx specific changes in case of mixed RxTx vectors */ 2344 if (ec->tx_coalesce_usecs) 2345 return -EINVAL; 2346 tx_itr_prev = adapter->rx_itr_setting; 2347 } else { 2348 tx_itr_prev = adapter->tx_itr_setting; 2349 } 2350 2351 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) || 2352 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2))) 2353 return -EINVAL; 2354 2355 if (ec->rx_coalesce_usecs > 1) 2356 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2357 else 2358 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2359 2360 if (adapter->rx_itr_setting == 1) 2361 rx_itr_param = IXGBE_20K_ITR; 2362 else 2363 rx_itr_param = adapter->rx_itr_setting; 2364 2365 if (ec->tx_coalesce_usecs > 1) 2366 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2367 else 2368 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2369 2370 if (adapter->tx_itr_setting == 1) 2371 tx_itr_param = IXGBE_12K_ITR; 2372 else 2373 tx_itr_param = adapter->tx_itr_setting; 2374 2375 /* mixed Rx/Tx */ 2376 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) 2377 adapter->tx_itr_setting = adapter->rx_itr_setting; 2378 2379 /* detect ITR changes that require update of TXDCTL.WTHRESH */ 2380 if ((adapter->tx_itr_setting != 1) && 2381 (adapter->tx_itr_setting < IXGBE_100K_ITR)) { 2382 if ((tx_itr_prev == 1) || 2383 (tx_itr_prev >= IXGBE_100K_ITR)) 2384 need_reset = true; 2385 } else { 2386 if ((tx_itr_prev != 1) && 2387 (tx_itr_prev < IXGBE_100K_ITR)) 2388 need_reset = true; 2389 } 2390 2391 /* check the old value and enable RSC if necessary */ 2392 need_reset |= ixgbe_update_rsc(adapter); 2393 2394 for (i = 0; i < adapter->num_q_vectors; i++) { 2395 q_vector = adapter->q_vector[i]; 2396 if (q_vector->tx.count && !q_vector->rx.count) 2397 /* tx only */ 2398 q_vector->itr = tx_itr_param; 2399 else 2400 /* rx only or mixed */ 2401 q_vector->itr = rx_itr_param; 2402 ixgbe_write_eitr(q_vector); 2403 } 2404 2405 /* 2406 * do reset here at the end to make sure EITR==0 case is handled 2407 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings 2408 * also locks in RSC enable/disable which requires reset 2409 */ 2410 if (need_reset) 2411 ixgbe_do_reset(netdev); 2412 2413 return 0; 2414 } 2415 2416 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2417 struct ethtool_rxnfc *cmd) 2418 { 2419 union ixgbe_atr_input *mask = &adapter->fdir_mask; 2420 struct ethtool_rx_flow_spec *fsp = 2421 (struct ethtool_rx_flow_spec *)&cmd->fs; 2422 struct hlist_node *node2; 2423 struct ixgbe_fdir_filter *rule = NULL; 2424 2425 /* report total rule count */ 2426 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2427 2428 hlist_for_each_entry_safe(rule, node2, 2429 &adapter->fdir_filter_list, fdir_node) { 2430 if (fsp->location <= rule->sw_idx) 2431 break; 2432 } 2433 2434 if (!rule || fsp->location != rule->sw_idx) 2435 return -EINVAL; 2436 2437 /* fill out the flow spec entry */ 2438 2439 /* set flow type field */ 2440 switch (rule->filter.formatted.flow_type) { 2441 case IXGBE_ATR_FLOW_TYPE_TCPV4: 2442 fsp->flow_type = TCP_V4_FLOW; 2443 break; 2444 case IXGBE_ATR_FLOW_TYPE_UDPV4: 2445 fsp->flow_type = UDP_V4_FLOW; 2446 break; 2447 case IXGBE_ATR_FLOW_TYPE_SCTPV4: 2448 fsp->flow_type = SCTP_V4_FLOW; 2449 break; 2450 case IXGBE_ATR_FLOW_TYPE_IPV4: 2451 fsp->flow_type = IP_USER_FLOW; 2452 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 2453 fsp->h_u.usr_ip4_spec.proto = 0; 2454 fsp->m_u.usr_ip4_spec.proto = 0; 2455 break; 2456 default: 2457 return -EINVAL; 2458 } 2459 2460 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port; 2461 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; 2462 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port; 2463 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; 2464 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0]; 2465 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; 2466 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0]; 2467 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; 2468 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id; 2469 fsp->m_ext.vlan_tci = mask->formatted.vlan_id; 2470 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes; 2471 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; 2472 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool); 2473 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); 2474 fsp->flow_type |= FLOW_EXT; 2475 2476 /* record action */ 2477 if (rule->action == IXGBE_FDIR_DROP_QUEUE) 2478 fsp->ring_cookie = RX_CLS_FLOW_DISC; 2479 else 2480 fsp->ring_cookie = rule->action; 2481 2482 return 0; 2483 } 2484 2485 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter, 2486 struct ethtool_rxnfc *cmd, 2487 u32 *rule_locs) 2488 { 2489 struct hlist_node *node2; 2490 struct ixgbe_fdir_filter *rule; 2491 int cnt = 0; 2492 2493 /* report total rule count */ 2494 cmd->data = (1024 << adapter->fdir_pballoc) - 2; 2495 2496 hlist_for_each_entry_safe(rule, node2, 2497 &adapter->fdir_filter_list, fdir_node) { 2498 if (cnt == cmd->rule_cnt) 2499 return -EMSGSIZE; 2500 rule_locs[cnt] = rule->sw_idx; 2501 cnt++; 2502 } 2503 2504 cmd->rule_cnt = cnt; 2505 2506 return 0; 2507 } 2508 2509 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, 2510 struct ethtool_rxnfc *cmd) 2511 { 2512 cmd->data = 0; 2513 2514 /* Report default options for RSS on ixgbe */ 2515 switch (cmd->flow_type) { 2516 case TCP_V4_FLOW: 2517 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2518 /* fallthrough */ 2519 case UDP_V4_FLOW: 2520 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2521 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2522 /* fallthrough */ 2523 case SCTP_V4_FLOW: 2524 case AH_ESP_V4_FLOW: 2525 case AH_V4_FLOW: 2526 case ESP_V4_FLOW: 2527 case IPV4_FLOW: 2528 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2529 break; 2530 case TCP_V6_FLOW: 2531 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2532 /* fallthrough */ 2533 case UDP_V6_FLOW: 2534 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2535 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2536 /* fallthrough */ 2537 case SCTP_V6_FLOW: 2538 case AH_ESP_V6_FLOW: 2539 case AH_V6_FLOW: 2540 case ESP_V6_FLOW: 2541 case IPV6_FLOW: 2542 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2543 break; 2544 default: 2545 return -EINVAL; 2546 } 2547 2548 return 0; 2549 } 2550 2551 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2552 u32 *rule_locs) 2553 { 2554 struct ixgbe_adapter *adapter = netdev_priv(dev); 2555 int ret = -EOPNOTSUPP; 2556 2557 switch (cmd->cmd) { 2558 case ETHTOOL_GRXRINGS: 2559 cmd->data = adapter->num_rx_queues; 2560 ret = 0; 2561 break; 2562 case ETHTOOL_GRXCLSRLCNT: 2563 cmd->rule_cnt = adapter->fdir_filter_count; 2564 ret = 0; 2565 break; 2566 case ETHTOOL_GRXCLSRULE: 2567 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd); 2568 break; 2569 case ETHTOOL_GRXCLSRLALL: 2570 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs); 2571 break; 2572 case ETHTOOL_GRXFH: 2573 ret = ixgbe_get_rss_hash_opts(adapter, cmd); 2574 break; 2575 default: 2576 break; 2577 } 2578 2579 return ret; 2580 } 2581 2582 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2583 struct ixgbe_fdir_filter *input, 2584 u16 sw_idx) 2585 { 2586 struct ixgbe_hw *hw = &adapter->hw; 2587 struct hlist_node *node2; 2588 struct ixgbe_fdir_filter *rule, *parent; 2589 int err = -EINVAL; 2590 2591 parent = NULL; 2592 rule = NULL; 2593 2594 hlist_for_each_entry_safe(rule, node2, 2595 &adapter->fdir_filter_list, fdir_node) { 2596 /* hash found, or no matching entry */ 2597 if (rule->sw_idx >= sw_idx) 2598 break; 2599 parent = rule; 2600 } 2601 2602 /* if there is an old rule occupying our place remove it */ 2603 if (rule && (rule->sw_idx == sw_idx)) { 2604 if (!input || (rule->filter.formatted.bkt_hash != 2605 input->filter.formatted.bkt_hash)) { 2606 err = ixgbe_fdir_erase_perfect_filter_82599(hw, 2607 &rule->filter, 2608 sw_idx); 2609 } 2610 2611 hlist_del(&rule->fdir_node); 2612 kfree(rule); 2613 adapter->fdir_filter_count--; 2614 } 2615 2616 /* 2617 * If no input this was a delete, err should be 0 if a rule was 2618 * successfully found and removed from the list else -EINVAL 2619 */ 2620 if (!input) 2621 return err; 2622 2623 /* initialize node and set software index */ 2624 INIT_HLIST_NODE(&input->fdir_node); 2625 2626 /* add filter to the list */ 2627 if (parent) 2628 hlist_add_behind(&input->fdir_node, &parent->fdir_node); 2629 else 2630 hlist_add_head(&input->fdir_node, 2631 &adapter->fdir_filter_list); 2632 2633 /* update counts */ 2634 adapter->fdir_filter_count++; 2635 2636 return 0; 2637 } 2638 2639 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp, 2640 u8 *flow_type) 2641 { 2642 switch (fsp->flow_type & ~FLOW_EXT) { 2643 case TCP_V4_FLOW: 2644 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2645 break; 2646 case UDP_V4_FLOW: 2647 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2648 break; 2649 case SCTP_V4_FLOW: 2650 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2651 break; 2652 case IP_USER_FLOW: 2653 switch (fsp->h_u.usr_ip4_spec.proto) { 2654 case IPPROTO_TCP: 2655 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 2656 break; 2657 case IPPROTO_UDP: 2658 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4; 2659 break; 2660 case IPPROTO_SCTP: 2661 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4; 2662 break; 2663 case 0: 2664 if (!fsp->m_u.usr_ip4_spec.proto) { 2665 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4; 2666 break; 2667 } 2668 default: 2669 return 0; 2670 } 2671 break; 2672 default: 2673 return 0; 2674 } 2675 2676 return 1; 2677 } 2678 2679 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2680 struct ethtool_rxnfc *cmd) 2681 { 2682 struct ethtool_rx_flow_spec *fsp = 2683 (struct ethtool_rx_flow_spec *)&cmd->fs; 2684 struct ixgbe_hw *hw = &adapter->hw; 2685 struct ixgbe_fdir_filter *input; 2686 union ixgbe_atr_input mask; 2687 u8 queue; 2688 int err; 2689 2690 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 2691 return -EOPNOTSUPP; 2692 2693 /* ring_cookie is a masked into a set of queues and ixgbe pools or 2694 * we use the drop index. 2695 */ 2696 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 2697 queue = IXGBE_FDIR_DROP_QUEUE; 2698 } else { 2699 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); 2700 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie); 2701 2702 if (!vf && (ring >= adapter->num_rx_queues)) 2703 return -EINVAL; 2704 else if (vf && 2705 ((vf > adapter->num_vfs) || 2706 ring >= adapter->num_rx_queues_per_pool)) 2707 return -EINVAL; 2708 2709 /* Map the ring onto the absolute queue index */ 2710 if (!vf) 2711 queue = adapter->rx_ring[ring]->reg_idx; 2712 else 2713 queue = ((vf - 1) * 2714 adapter->num_rx_queues_per_pool) + ring; 2715 } 2716 2717 /* Don't allow indexes to exist outside of available space */ 2718 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) { 2719 e_err(drv, "Location out of range\n"); 2720 return -EINVAL; 2721 } 2722 2723 input = kzalloc(sizeof(*input), GFP_ATOMIC); 2724 if (!input) 2725 return -ENOMEM; 2726 2727 memset(&mask, 0, sizeof(union ixgbe_atr_input)); 2728 2729 /* set SW index */ 2730 input->sw_idx = fsp->location; 2731 2732 /* record flow type */ 2733 if (!ixgbe_flowspec_to_flow_type(fsp, 2734 &input->filter.formatted.flow_type)) { 2735 e_err(drv, "Unrecognized flow type\n"); 2736 goto err_out; 2737 } 2738 2739 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 2740 IXGBE_ATR_L4TYPE_MASK; 2741 2742 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 2743 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 2744 2745 /* Copy input into formatted structures */ 2746 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src; 2747 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; 2748 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst; 2749 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; 2750 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc; 2751 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; 2752 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst; 2753 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; 2754 2755 if (fsp->flow_type & FLOW_EXT) { 2756 input->filter.formatted.vm_pool = 2757 (unsigned char)ntohl(fsp->h_ext.data[1]); 2758 mask.formatted.vm_pool = 2759 (unsigned char)ntohl(fsp->m_ext.data[1]); 2760 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci; 2761 mask.formatted.vlan_id = fsp->m_ext.vlan_tci; 2762 input->filter.formatted.flex_bytes = 2763 fsp->h_ext.vlan_etype; 2764 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; 2765 } 2766 2767 /* determine if we need to drop or route the packet */ 2768 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) 2769 input->action = IXGBE_FDIR_DROP_QUEUE; 2770 else 2771 input->action = fsp->ring_cookie; 2772 2773 spin_lock(&adapter->fdir_perfect_lock); 2774 2775 if (hlist_empty(&adapter->fdir_filter_list)) { 2776 /* save mask and program input mask into HW */ 2777 memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); 2778 err = ixgbe_fdir_set_input_mask_82599(hw, &mask); 2779 if (err) { 2780 e_err(drv, "Error writing mask\n"); 2781 goto err_out_w_lock; 2782 } 2783 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { 2784 e_err(drv, "Only one mask supported per port\n"); 2785 goto err_out_w_lock; 2786 } 2787 2788 /* apply mask and compute/store hash */ 2789 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); 2790 2791 /* program filters to filter memory */ 2792 err = ixgbe_fdir_write_perfect_filter_82599(hw, 2793 &input->filter, input->sw_idx, queue); 2794 if (err) 2795 goto err_out_w_lock; 2796 2797 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 2798 2799 spin_unlock(&adapter->fdir_perfect_lock); 2800 2801 return err; 2802 err_out_w_lock: 2803 spin_unlock(&adapter->fdir_perfect_lock); 2804 err_out: 2805 kfree(input); 2806 return -EINVAL; 2807 } 2808 2809 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 2810 struct ethtool_rxnfc *cmd) 2811 { 2812 struct ethtool_rx_flow_spec *fsp = 2813 (struct ethtool_rx_flow_spec *)&cmd->fs; 2814 int err; 2815 2816 spin_lock(&adapter->fdir_perfect_lock); 2817 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location); 2818 spin_unlock(&adapter->fdir_perfect_lock); 2819 2820 return err; 2821 } 2822 2823 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \ 2824 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2825 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter, 2826 struct ethtool_rxnfc *nfc) 2827 { 2828 u32 flags2 = adapter->flags2; 2829 2830 /* 2831 * RSS does not support anything other than hashing 2832 * to queues on src and dst IPs and ports 2833 */ 2834 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2835 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2836 return -EINVAL; 2837 2838 switch (nfc->flow_type) { 2839 case TCP_V4_FLOW: 2840 case TCP_V6_FLOW: 2841 if (!(nfc->data & RXH_IP_SRC) || 2842 !(nfc->data & RXH_IP_DST) || 2843 !(nfc->data & RXH_L4_B_0_1) || 2844 !(nfc->data & RXH_L4_B_2_3)) 2845 return -EINVAL; 2846 break; 2847 case UDP_V4_FLOW: 2848 if (!(nfc->data & RXH_IP_SRC) || 2849 !(nfc->data & RXH_IP_DST)) 2850 return -EINVAL; 2851 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2852 case 0: 2853 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2854 break; 2855 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2856 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP; 2857 break; 2858 default: 2859 return -EINVAL; 2860 } 2861 break; 2862 case UDP_V6_FLOW: 2863 if (!(nfc->data & RXH_IP_SRC) || 2864 !(nfc->data & RXH_IP_DST)) 2865 return -EINVAL; 2866 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2867 case 0: 2868 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2869 break; 2870 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2871 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP; 2872 break; 2873 default: 2874 return -EINVAL; 2875 } 2876 break; 2877 case AH_ESP_V4_FLOW: 2878 case AH_V4_FLOW: 2879 case ESP_V4_FLOW: 2880 case SCTP_V4_FLOW: 2881 case AH_ESP_V6_FLOW: 2882 case AH_V6_FLOW: 2883 case ESP_V6_FLOW: 2884 case SCTP_V6_FLOW: 2885 if (!(nfc->data & RXH_IP_SRC) || 2886 !(nfc->data & RXH_IP_DST) || 2887 (nfc->data & RXH_L4_B_0_1) || 2888 (nfc->data & RXH_L4_B_2_3)) 2889 return -EINVAL; 2890 break; 2891 default: 2892 return -EINVAL; 2893 } 2894 2895 /* if we changed something we need to update flags */ 2896 if (flags2 != adapter->flags2) { 2897 struct ixgbe_hw *hw = &adapter->hw; 2898 u32 mrqc; 2899 unsigned int pf_pool = adapter->num_vfs; 2900 2901 if ((hw->mac.type >= ixgbe_mac_X550) && 2902 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2903 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool)); 2904 else 2905 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); 2906 2907 if ((flags2 & UDP_RSS_FLAGS) && 2908 !(adapter->flags2 & UDP_RSS_FLAGS)) 2909 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2910 2911 adapter->flags2 = flags2; 2912 2913 /* Perform hash on these packet types */ 2914 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 2915 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP 2916 | IXGBE_MRQC_RSS_FIELD_IPV6 2917 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 2918 2919 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP | 2920 IXGBE_MRQC_RSS_FIELD_IPV6_UDP); 2921 2922 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 2923 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 2924 2925 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 2926 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 2927 2928 if ((hw->mac.type >= ixgbe_mac_X550) && 2929 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 2930 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc); 2931 else 2932 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 2933 } 2934 2935 return 0; 2936 } 2937 2938 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2939 { 2940 struct ixgbe_adapter *adapter = netdev_priv(dev); 2941 int ret = -EOPNOTSUPP; 2942 2943 switch (cmd->cmd) { 2944 case ETHTOOL_SRXCLSRLINS: 2945 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd); 2946 break; 2947 case ETHTOOL_SRXCLSRLDEL: 2948 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd); 2949 break; 2950 case ETHTOOL_SRXFH: 2951 ret = ixgbe_set_rss_hash_opt(adapter, cmd); 2952 break; 2953 default: 2954 break; 2955 } 2956 2957 return ret; 2958 } 2959 2960 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) 2961 { 2962 if (adapter->hw.mac.type < ixgbe_mac_X550) 2963 return 16; 2964 else 2965 return 64; 2966 } 2967 2968 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) 2969 { 2970 return IXGBE_RSS_KEY_SIZE; 2971 } 2972 2973 static u32 ixgbe_rss_indir_size(struct net_device *netdev) 2974 { 2975 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2976 2977 return ixgbe_rss_indir_tbl_entries(adapter); 2978 } 2979 2980 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir) 2981 { 2982 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter); 2983 u16 rss_m = adapter->ring_feature[RING_F_RSS].mask; 2984 2985 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 2986 rss_m = adapter->ring_feature[RING_F_RSS].indices - 1; 2987 2988 for (i = 0; i < reta_size; i++) 2989 indir[i] = adapter->rss_indir_tbl[i] & rss_m; 2990 } 2991 2992 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 2993 u8 *hfunc) 2994 { 2995 struct ixgbe_adapter *adapter = netdev_priv(netdev); 2996 2997 if (hfunc) 2998 *hfunc = ETH_RSS_HASH_TOP; 2999 3000 if (indir) 3001 ixgbe_get_reta(adapter, indir); 3002 3003 if (key) 3004 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev)); 3005 3006 return 0; 3007 } 3008 3009 static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir, 3010 const u8 *key, const u8 hfunc) 3011 { 3012 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3013 int i; 3014 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3015 3016 if (hfunc) 3017 return -EINVAL; 3018 3019 /* Fill out the redirection table */ 3020 if (indir) { 3021 int max_queues = min_t(int, adapter->num_rx_queues, 3022 ixgbe_rss_indir_tbl_max(adapter)); 3023 3024 /*Allow at least 2 queues w/ SR-IOV.*/ 3025 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 3026 (max_queues < 2)) 3027 max_queues = 2; 3028 3029 /* Verify user input. */ 3030 for (i = 0; i < reta_entries; i++) 3031 if (indir[i] >= max_queues) 3032 return -EINVAL; 3033 3034 for (i = 0; i < reta_entries; i++) 3035 adapter->rss_indir_tbl[i] = indir[i]; 3036 } 3037 3038 /* Fill out the rss hash key */ 3039 if (key) { 3040 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev)); 3041 ixgbe_store_key(adapter); 3042 } 3043 3044 ixgbe_store_reta(adapter); 3045 3046 return 0; 3047 } 3048 3049 static int ixgbe_get_ts_info(struct net_device *dev, 3050 struct ethtool_ts_info *info) 3051 { 3052 struct ixgbe_adapter *adapter = netdev_priv(dev); 3053 3054 /* we always support timestamping disabled */ 3055 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE); 3056 3057 switch (adapter->hw.mac.type) { 3058 case ixgbe_mac_X550: 3059 case ixgbe_mac_X550EM_x: 3060 case ixgbe_mac_x550em_a: 3061 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL); 3062 /* fallthrough */ 3063 case ixgbe_mac_X540: 3064 case ixgbe_mac_82599EB: 3065 info->so_timestamping = 3066 SOF_TIMESTAMPING_TX_SOFTWARE | 3067 SOF_TIMESTAMPING_RX_SOFTWARE | 3068 SOF_TIMESTAMPING_SOFTWARE | 3069 SOF_TIMESTAMPING_TX_HARDWARE | 3070 SOF_TIMESTAMPING_RX_HARDWARE | 3071 SOF_TIMESTAMPING_RAW_HARDWARE; 3072 3073 if (adapter->ptp_clock) 3074 info->phc_index = ptp_clock_index(adapter->ptp_clock); 3075 else 3076 info->phc_index = -1; 3077 3078 info->tx_types = 3079 BIT(HWTSTAMP_TX_OFF) | 3080 BIT(HWTSTAMP_TX_ON); 3081 3082 info->rx_filters |= 3083 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 3084 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 3085 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); 3086 break; 3087 default: 3088 return ethtool_op_get_ts_info(dev, info); 3089 } 3090 return 0; 3091 } 3092 3093 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter) 3094 { 3095 unsigned int max_combined; 3096 u8 tcs = netdev_get_num_tc(adapter->netdev); 3097 3098 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3099 /* We only support one q_vector without MSI-X */ 3100 max_combined = 1; 3101 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3102 /* Limit value based on the queue mask */ 3103 max_combined = adapter->ring_feature[RING_F_RSS].mask + 1; 3104 } else if (tcs > 1) { 3105 /* For DCB report channels per traffic class */ 3106 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3107 /* 8 TC w/ 4 queues per TC */ 3108 max_combined = 4; 3109 } else if (tcs > 4) { 3110 /* 8 TC w/ 8 queues per TC */ 3111 max_combined = 8; 3112 } else { 3113 /* 4 TC w/ 16 queues per TC */ 3114 max_combined = 16; 3115 } 3116 } else if (adapter->atr_sample_rate) { 3117 /* support up to 64 queues with ATR */ 3118 max_combined = IXGBE_MAX_FDIR_INDICES; 3119 } else { 3120 /* support up to 16 queues with RSS */ 3121 max_combined = ixgbe_max_rss_indices(adapter); 3122 } 3123 3124 return max_combined; 3125 } 3126 3127 static void ixgbe_get_channels(struct net_device *dev, 3128 struct ethtool_channels *ch) 3129 { 3130 struct ixgbe_adapter *adapter = netdev_priv(dev); 3131 3132 /* report maximum channels */ 3133 ch->max_combined = ixgbe_max_channels(adapter); 3134 3135 /* report info for other vector */ 3136 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3137 ch->max_other = NON_Q_VECTORS; 3138 ch->other_count = NON_Q_VECTORS; 3139 } 3140 3141 /* record RSS queues */ 3142 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices; 3143 3144 /* nothing else to report if RSS is disabled */ 3145 if (ch->combined_count == 1) 3146 return; 3147 3148 /* we do not support ATR queueing if SR-IOV is enabled */ 3149 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3150 return; 3151 3152 /* same thing goes for being DCB enabled */ 3153 if (netdev_get_num_tc(dev) > 1) 3154 return; 3155 3156 /* if ATR is disabled we can exit */ 3157 if (!adapter->atr_sample_rate) 3158 return; 3159 3160 /* report flow director queues as maximum channels */ 3161 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices; 3162 } 3163 3164 static int ixgbe_set_channels(struct net_device *dev, 3165 struct ethtool_channels *ch) 3166 { 3167 struct ixgbe_adapter *adapter = netdev_priv(dev); 3168 unsigned int count = ch->combined_count; 3169 u8 max_rss_indices = ixgbe_max_rss_indices(adapter); 3170 3171 /* verify they are not requesting separate vectors */ 3172 if (!count || ch->rx_count || ch->tx_count) 3173 return -EINVAL; 3174 3175 /* verify other_count has not changed */ 3176 if (ch->other_count != NON_Q_VECTORS) 3177 return -EINVAL; 3178 3179 /* verify the number of channels does not exceed hardware limits */ 3180 if (count > ixgbe_max_channels(adapter)) 3181 return -EINVAL; 3182 3183 /* update feature limits from largest to smallest supported values */ 3184 adapter->ring_feature[RING_F_FDIR].limit = count; 3185 3186 /* cap RSS limit */ 3187 if (count > max_rss_indices) 3188 count = max_rss_indices; 3189 adapter->ring_feature[RING_F_RSS].limit = count; 3190 3191 #ifdef IXGBE_FCOE 3192 /* cap FCoE limit at 8 */ 3193 if (count > IXGBE_FCRETA_SIZE) 3194 count = IXGBE_FCRETA_SIZE; 3195 adapter->ring_feature[RING_F_FCOE].limit = count; 3196 3197 #endif 3198 /* use setup TC to update any traffic class queue mapping */ 3199 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev)); 3200 } 3201 3202 static int ixgbe_get_module_info(struct net_device *dev, 3203 struct ethtool_modinfo *modinfo) 3204 { 3205 struct ixgbe_adapter *adapter = netdev_priv(dev); 3206 struct ixgbe_hw *hw = &adapter->hw; 3207 s32 status; 3208 u8 sff8472_rev, addr_mode; 3209 bool page_swap = false; 3210 3211 if (hw->phy.type == ixgbe_phy_fw) 3212 return -ENXIO; 3213 3214 /* Check whether we support SFF-8472 or not */ 3215 status = hw->phy.ops.read_i2c_eeprom(hw, 3216 IXGBE_SFF_SFF_8472_COMP, 3217 &sff8472_rev); 3218 if (status) 3219 return -EIO; 3220 3221 /* addressing mode is not supported */ 3222 status = hw->phy.ops.read_i2c_eeprom(hw, 3223 IXGBE_SFF_SFF_8472_SWAP, 3224 &addr_mode); 3225 if (status) 3226 return -EIO; 3227 3228 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 3229 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 3230 page_swap = true; 3231 } 3232 3233 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 3234 /* We have a SFP, but it does not support SFF-8472 */ 3235 modinfo->type = ETH_MODULE_SFF_8079; 3236 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 3237 } else { 3238 /* We have a SFP which supports a revision of SFF-8472. */ 3239 modinfo->type = ETH_MODULE_SFF_8472; 3240 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 3241 } 3242 3243 return 0; 3244 } 3245 3246 static int ixgbe_get_module_eeprom(struct net_device *dev, 3247 struct ethtool_eeprom *ee, 3248 u8 *data) 3249 { 3250 struct ixgbe_adapter *adapter = netdev_priv(dev); 3251 struct ixgbe_hw *hw = &adapter->hw; 3252 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 3253 u8 databyte = 0xFF; 3254 int i = 0; 3255 3256 if (ee->len == 0) 3257 return -EINVAL; 3258 3259 if (hw->phy.type == ixgbe_phy_fw) 3260 return -ENXIO; 3261 3262 for (i = ee->offset; i < ee->offset + ee->len; i++) { 3263 /* I2C reads can take long time */ 3264 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 3265 return -EBUSY; 3266 3267 if (i < ETH_MODULE_SFF_8079_LEN) 3268 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 3269 else 3270 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 3271 3272 if (status) 3273 return -EIO; 3274 3275 data[i - ee->offset] = databyte; 3276 } 3277 3278 return 0; 3279 } 3280 3281 static const struct { 3282 ixgbe_link_speed mac_speed; 3283 u32 supported; 3284 } ixgbe_ls_map[] = { 3285 { IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full }, 3286 { IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full }, 3287 { IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full }, 3288 { IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full }, 3289 { IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full }, 3290 }; 3291 3292 static const struct { 3293 u32 lp_advertised; 3294 u32 mac_speed; 3295 } ixgbe_lp_map[] = { 3296 { FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full }, 3297 { FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full }, 3298 { FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full }, 3299 { FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full }, 3300 { FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full }, 3301 { FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full}, 3302 }; 3303 3304 static int 3305 ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata) 3306 { 3307 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3308 struct ixgbe_hw *hw = &adapter->hw; 3309 s32 rc; 3310 u16 i; 3311 3312 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, &info); 3313 if (rc) 3314 return rc; 3315 3316 edata->lp_advertised = 0; 3317 for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) { 3318 if (info[0] & ixgbe_lp_map[i].lp_advertised) 3319 edata->lp_advertised |= ixgbe_lp_map[i].mac_speed; 3320 } 3321 3322 edata->supported = 0; 3323 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3324 if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed) 3325 edata->supported |= ixgbe_ls_map[i].supported; 3326 } 3327 3328 edata->advertised = 0; 3329 for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) { 3330 if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed) 3331 edata->advertised |= ixgbe_ls_map[i].supported; 3332 } 3333 3334 edata->eee_enabled = !!edata->advertised; 3335 edata->tx_lpi_enabled = edata->eee_enabled; 3336 if (edata->advertised & edata->lp_advertised) 3337 edata->eee_active = true; 3338 3339 return 0; 3340 } 3341 3342 static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 3343 { 3344 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3345 struct ixgbe_hw *hw = &adapter->hw; 3346 3347 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3348 return -EOPNOTSUPP; 3349 3350 if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw) 3351 return ixgbe_get_eee_fw(adapter, edata); 3352 3353 return -EOPNOTSUPP; 3354 } 3355 3356 static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata) 3357 { 3358 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3359 struct ixgbe_hw *hw = &adapter->hw; 3360 struct ethtool_eee eee_data; 3361 s32 ret_val; 3362 3363 if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) 3364 return -EOPNOTSUPP; 3365 3366 memset(&eee_data, 0, sizeof(struct ethtool_eee)); 3367 3368 ret_val = ixgbe_get_eee(netdev, &eee_data); 3369 if (ret_val) 3370 return ret_val; 3371 3372 if (eee_data.eee_enabled && !edata->eee_enabled) { 3373 if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) { 3374 e_err(drv, "Setting EEE tx-lpi is not supported\n"); 3375 return -EINVAL; 3376 } 3377 3378 if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) { 3379 e_err(drv, 3380 "Setting EEE Tx LPI timer is not supported\n"); 3381 return -EINVAL; 3382 } 3383 3384 if (eee_data.advertised != edata->advertised) { 3385 e_err(drv, 3386 "Setting EEE advertised speeds is not supported\n"); 3387 return -EINVAL; 3388 } 3389 } 3390 3391 if (eee_data.eee_enabled != edata->eee_enabled) { 3392 if (edata->eee_enabled) { 3393 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 3394 hw->phy.eee_speeds_advertised = 3395 hw->phy.eee_speeds_supported; 3396 } else { 3397 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 3398 hw->phy.eee_speeds_advertised = 0; 3399 } 3400 3401 /* reset link */ 3402 if (netif_running(netdev)) 3403 ixgbe_reinit_locked(adapter); 3404 else 3405 ixgbe_reset(adapter); 3406 } 3407 3408 return 0; 3409 } 3410 3411 static u32 ixgbe_get_priv_flags(struct net_device *netdev) 3412 { 3413 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3414 u32 priv_flags = 0; 3415 3416 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 3417 priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX; 3418 3419 return priv_flags; 3420 } 3421 3422 static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags) 3423 { 3424 struct ixgbe_adapter *adapter = netdev_priv(netdev); 3425 unsigned int flags2 = adapter->flags2; 3426 3427 flags2 &= ~IXGBE_FLAG2_RX_LEGACY; 3428 if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX) 3429 flags2 |= IXGBE_FLAG2_RX_LEGACY; 3430 3431 if (flags2 != adapter->flags2) { 3432 adapter->flags2 = flags2; 3433 3434 /* reset interface to repopulate queues */ 3435 if (netif_running(netdev)) 3436 ixgbe_reinit_locked(adapter); 3437 } 3438 3439 return 0; 3440 } 3441 3442 static const struct ethtool_ops ixgbe_ethtool_ops = { 3443 .get_drvinfo = ixgbe_get_drvinfo, 3444 .get_regs_len = ixgbe_get_regs_len, 3445 .get_regs = ixgbe_get_regs, 3446 .get_wol = ixgbe_get_wol, 3447 .set_wol = ixgbe_set_wol, 3448 .nway_reset = ixgbe_nway_reset, 3449 .get_link = ethtool_op_get_link, 3450 .get_eeprom_len = ixgbe_get_eeprom_len, 3451 .get_eeprom = ixgbe_get_eeprom, 3452 .set_eeprom = ixgbe_set_eeprom, 3453 .get_ringparam = ixgbe_get_ringparam, 3454 .set_ringparam = ixgbe_set_ringparam, 3455 .get_pauseparam = ixgbe_get_pauseparam, 3456 .set_pauseparam = ixgbe_set_pauseparam, 3457 .get_msglevel = ixgbe_get_msglevel, 3458 .set_msglevel = ixgbe_set_msglevel, 3459 .self_test = ixgbe_diag_test, 3460 .get_strings = ixgbe_get_strings, 3461 .set_phys_id = ixgbe_set_phys_id, 3462 .get_sset_count = ixgbe_get_sset_count, 3463 .get_ethtool_stats = ixgbe_get_ethtool_stats, 3464 .get_coalesce = ixgbe_get_coalesce, 3465 .set_coalesce = ixgbe_set_coalesce, 3466 .get_rxnfc = ixgbe_get_rxnfc, 3467 .set_rxnfc = ixgbe_set_rxnfc, 3468 .get_rxfh_indir_size = ixgbe_rss_indir_size, 3469 .get_rxfh_key_size = ixgbe_get_rxfh_key_size, 3470 .get_rxfh = ixgbe_get_rxfh, 3471 .set_rxfh = ixgbe_set_rxfh, 3472 .get_eee = ixgbe_get_eee, 3473 .set_eee = ixgbe_set_eee, 3474 .get_channels = ixgbe_get_channels, 3475 .set_channels = ixgbe_set_channels, 3476 .get_priv_flags = ixgbe_get_priv_flags, 3477 .set_priv_flags = ixgbe_set_priv_flags, 3478 .get_ts_info = ixgbe_get_ts_info, 3479 .get_module_info = ixgbe_get_module_info, 3480 .get_module_eeprom = ixgbe_get_module_eeprom, 3481 .get_link_ksettings = ixgbe_get_link_ksettings, 3482 .set_link_ksettings = ixgbe_set_link_ksettings, 3483 }; 3484 3485 void ixgbe_set_ethtool_ops(struct net_device *netdev) 3486 { 3487 netdev->ethtool_ops = &ixgbe_ethtool_ops; 3488 } 3489