1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /******************************************************************************* 3 4 Intel 10 Gigabit PCI Express Linux driver 5 Copyright(c) 1999 - 2013 Intel Corporation. 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 28 *******************************************************************************/ 29 30 #ifndef _DCB_82598_CONFIG_H_ 31 #define _DCB_82598_CONFIG_H_ 32 33 /* DCB register definitions */ 34 35 #define IXGBE_DPMCS_MTSOS_SHIFT 16 36 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */ 37 #define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */ 38 #define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 39 #define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */ 40 41 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */ 42 43 #define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 44 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */ 45 46 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */ 47 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */ 48 49 #define IXGBE_TDTQ2TCCR_MCL_SHIFT 12 50 #define IXGBE_TDTQ2TCCR_BWG_SHIFT 9 51 #define IXGBE_TDTQ2TCCR_GSP 0x40000000 52 #define IXGBE_TDTQ2TCCR_LSP 0x80000000 53 54 #define IXGBE_TDPT2TCCR_MCL_SHIFT 12 55 #define IXGBE_TDPT2TCCR_BWG_SHIFT 9 56 #define IXGBE_TDPT2TCCR_GSP 0x40000000 57 #define IXGBE_TDPT2TCCR_LSP 0x80000000 58 59 #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */ 60 #define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */ 61 #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */ 62 63 #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */ 64 65 #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 66 #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 67 #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 68 #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 69 70 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 71 72 /* DCB hardware-specific driver APIs */ 73 74 /* DCB PFC functions */ 75 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en); 76 77 /* DCB hw initialization */ 78 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 79 u16 *refill, 80 u16 *max, 81 u8 *prio_type); 82 83 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 84 u16 *refill, 85 u16 *max, 86 u8 *bwg_id, 87 u8 *prio_type); 88 89 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 90 u16 *refill, 91 u16 *max, 92 u8 *bwg_id, 93 u8 *prio_type); 94 95 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 96 u16 *max, u8 *bwg_id, u8 *prio_type); 97 98 #endif /* _DCB_82598_CONFIG_H */ 99