1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #include "ixgbe.h" 30 #include "ixgbe_type.h" 31 #include "ixgbe_dcb.h" 32 #include "ixgbe_dcb_82598.h" 33 34 /** 35 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter 36 * @hw: pointer to hardware structure 37 * @dcb_config: pointer to ixgbe_dcb_config structure 38 * 39 * Configure Rx Data Arbiter and credits for each traffic class. 40 */ 41 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 42 u16 *refill, 43 u16 *max, 44 u8 *prio_type) 45 { 46 u32 reg = 0; 47 u32 credit_refill = 0; 48 u32 credit_max = 0; 49 u8 i = 0; 50 51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 53 54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 55 /* Enable Arbiter */ 56 reg &= ~IXGBE_RMCS_ARBDIS; 57 /* Enable Receive Recycle within the BWG */ 58 reg |= IXGBE_RMCS_RRM; 59 /* Enable Deficit Fixed Priority arbitration*/ 60 reg |= IXGBE_RMCS_DFP; 61 62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 63 64 /* Configure traffic class credits and priority */ 65 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 66 credit_refill = refill[i]; 67 credit_max = max[i]; 68 69 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 70 71 if (prio_type[i] == prio_link) 72 reg |= IXGBE_RT2CR_LSP; 73 74 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); 75 } 76 77 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 78 reg |= IXGBE_RDRXCTL_RDMTS_1_2; 79 reg |= IXGBE_RDRXCTL_MPBEN; 80 reg |= IXGBE_RDRXCTL_MCEN; 81 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 82 83 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 84 /* Make sure there is enough descriptors before arbitration */ 85 reg &= ~IXGBE_RXCTRL_DMBYPS; 86 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); 87 88 return 0; 89 } 90 91 /** 92 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter 93 * @hw: pointer to hardware structure 94 * @dcb_config: pointer to ixgbe_dcb_config structure 95 * 96 * Configure Tx Descriptor Arbiter and credits for each traffic class. 97 */ 98 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 99 u16 *refill, 100 u16 *max, 101 u8 *bwg_id, 102 u8 *prio_type) 103 { 104 u32 reg, max_credits; 105 u8 i; 106 107 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); 108 109 /* Enable arbiter */ 110 reg &= ~IXGBE_DPMCS_ARBDIS; 111 /* Enable DFP and Recycle mode */ 112 reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM); 113 reg |= IXGBE_DPMCS_TSOEF; 114 /* Configure Max TSO packet size 34KB including payload and headers */ 115 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); 116 117 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); 118 119 /* Configure traffic class credits and priority */ 120 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 121 max_credits = max[i]; 122 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; 123 reg |= refill[i]; 124 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; 125 126 if (prio_type[i] == prio_group) 127 reg |= IXGBE_TDTQ2TCCR_GSP; 128 129 if (prio_type[i] == prio_link) 130 reg |= IXGBE_TDTQ2TCCR_LSP; 131 132 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); 133 } 134 135 return 0; 136 } 137 138 /** 139 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter 140 * @hw: pointer to hardware structure 141 * @dcb_config: pointer to ixgbe_dcb_config structure 142 * 143 * Configure Tx Data Arbiter and credits for each traffic class. 144 */ 145 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 146 u16 *refill, 147 u16 *max, 148 u8 *bwg_id, 149 u8 *prio_type) 150 { 151 u32 reg; 152 u8 i; 153 154 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); 155 /* Enable Data Plane Arbiter */ 156 reg &= ~IXGBE_PDPMCS_ARBDIS; 157 /* Enable DFP and Transmit Recycle Mode */ 158 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); 159 160 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); 161 162 /* Configure traffic class credits and priority */ 163 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 164 reg = refill[i]; 165 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; 166 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; 167 168 if (prio_type[i] == prio_group) 169 reg |= IXGBE_TDPT2TCCR_GSP; 170 171 if (prio_type[i] == prio_link) 172 reg |= IXGBE_TDPT2TCCR_LSP; 173 174 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); 175 } 176 177 /* Enable Tx packet buffer division */ 178 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); 179 reg |= IXGBE_DTXCTL_ENDBUBD; 180 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); 181 182 return 0; 183 } 184 185 /** 186 * ixgbe_dcb_config_pfc_82598 - Config priority flow control 187 * @hw: pointer to hardware structure 188 * @dcb_config: pointer to ixgbe_dcb_config structure 189 * 190 * Configure Priority Flow Control for each traffic class. 191 */ 192 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) 193 { 194 u32 reg; 195 u8 i; 196 197 if (pfc_en) { 198 /* Enable Transmit Priority Flow Control */ 199 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 200 reg &= ~IXGBE_RMCS_TFCE_802_3X; 201 /* correct the reporting of our flow control status */ 202 reg |= IXGBE_RMCS_TFCE_PRIORITY; 203 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 204 205 /* Enable Receive Priority Flow Control */ 206 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 207 reg &= ~IXGBE_FCTRL_RFCE; 208 reg |= IXGBE_FCTRL_RPFCE; 209 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); 210 211 /* Configure pause time */ 212 for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++) 213 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800); 214 215 /* Configure flow control refresh threshold value */ 216 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400); 217 } 218 219 /* 220 * Configure flow control thresholds and enable priority flow control 221 * for each traffic class. 222 */ 223 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 224 int enabled = pfc_en & (1 << i); 225 226 reg = hw->fc.low_water << 10; 227 228 if (enabled == pfc_enabled_tx || 229 enabled == pfc_enabled_full) 230 reg |= IXGBE_FCRTL_XONE; 231 232 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg); 233 234 reg = hw->fc.high_water[i] << 10; 235 if (enabled == pfc_enabled_tx || 236 enabled == pfc_enabled_full) 237 reg |= IXGBE_FCRTH_FCEN; 238 239 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); 240 } 241 242 return 0; 243 } 244 245 /** 246 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics 247 * @hw: pointer to hardware structure 248 * 249 * Configure queue statistics registers, all queues belonging to same traffic 250 * class uses a single set of queue statistics counters. 251 */ 252 static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) 253 { 254 u32 reg = 0; 255 u8 i = 0; 256 u8 j = 0; 257 258 /* Receive Queues stats setting - 8 queues per statistics reg */ 259 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { 260 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); 261 reg |= ((0x1010101) * j); 262 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); 263 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); 264 reg |= ((0x1010101) * j); 265 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); 266 } 267 /* Transmit Queues stats setting - 4 queues per statistics reg */ 268 for (i = 0; i < 8; i++) { 269 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); 270 reg |= ((0x1010101) * i); 271 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); 272 } 273 274 return 0; 275 } 276 277 /** 278 * ixgbe_dcb_hw_config_82598 - Config and enable DCB 279 * @hw: pointer to hardware structure 280 * @dcb_config: pointer to ixgbe_dcb_config structure 281 * 282 * Configure dcb settings and enable dcb mode. 283 */ 284 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 285 u16 *max, u8 *bwg_id, u8 *prio_type) 286 { 287 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type); 288 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 289 bwg_id, prio_type); 290 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 291 bwg_id, prio_type); 292 ixgbe_dcb_config_pfc_82598(hw, pfc_en); 293 ixgbe_dcb_config_tc_stats_82598(hw); 294 295 return 0; 296 } 297